diff --git a/.github/workflows/gk7102_images.yml b/.github/workflows/gk7102_images.yml new file mode 100644 index 00000000..b9339ee0 --- /dev/null +++ b/.github/workflows/gk7102_images.yml @@ -0,0 +1,130 @@ +name: "GK7102" + +on: + workflow_dispatch: + +jobs: + build_core: + name: OpenIPC firmware for GK7102 + runs-on: ubuntu-latest + + steps: + + - name: Checkout + id: checkout + uses: actions/checkout@v2 + + - name: Install build dependencies + id: install + run: | + make install-deps + mkdir -p tmp + + - name: Free disk space + id: freshing + run: | + sudo swapoff -a + sudo rm -f /swapfile + sudo apt clean + docker rmi $(docker image ls -aq) + df -h + + - name: Prepare buildroot + id: prepare + run: | + HEAD_TAG=$(git tag --points-at HEAD) + GIT_HASH=$(git rev-parse --short $GITHUB_SHA) + BRANCH_NAME=$(echo $GITHUB_REF | cut -d'/' -f 3) + if [ -z "$HEAD_TAG" ]; then + TAG_NAME="latest" + RELEASE_NAME="Development Build" + PRERELEASE=true + else + TAG_NAME=${{ github.ref }} + RELEASE_NAME="Release ${{ github.ref }}" + PRERELEASE=false + fi + echo "GIT_HASH=$GIT_HASH" >> $GITHUB_ENV + echo "TAG_NAME=$TAG_NAME" >> $GITHUB_ENV + echo "RELEASE_NAME=$RELEASE_NAME" >> $GITHUB_ENV + echo "PRERELEASE=$PRERELEASE" >> $GITHUB_ENV + echo "BRANCH_NAME=$BRANCH_NAME" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE + make prepare + + - name: Build GK7102 firmware + id: build-gk7102-firmware + continue-on-error: true + run: | + ARCHIVE_FW="${GITHUB_WORKSPACE}/output/images/openipc.gk7102-br.tgz" + echo "ARCHIVE_FW=$ARCHIVE_FW" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE + make PLATFORM=goke BOARD=unknown_unknown_gk7102_openipc all + [[ $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) -gt 2097152 ]] && echo "TG_NOTIFY=Warning, kernel size exceeded : $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) vs 2097152... GK7102" >> $GITHUB_ENV && exit 1 + [[ $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/rootfs.squashfs) -gt 5242880 ]] && echo "TG_NOTIFY=Warning, rootfs size exceeded - $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/rootfs.squashfs) vs 5242880... GK7102" >> $GITHUB_ENV && exit 1 + cd ${GITHUB_WORKSPACE}/output/images + mv uImage uImage.gk7102 + mv rootfs.squashfs rootfs.squashfs.gk7102 + tar -C ${GITHUB_WORKSPACE}/output/images -cvzf $ARCHIVE_FW rootfs.squashfs.fh8856 uImage.gk7102 + + - name: Build GK7102 SDK + id: build-gk7102-sdk + continue-on-error: true + run: | + ARCHIVE_SDK="${GITHUB_WORKSPACE}/output/images/arm-openipc-linux-musleabi_sdk-buildroot.tar.gz" + echo "ARCHIVE_SDK=$ARCHIVE_SDK" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE/output + make sdk + + - name: Send warning message to telegram channel + env: + TG_TOKEN: ${{ secrets.TELEGRAM_TOKEN_BOT_OPENIPC }} + TG_CHANNEL: ${{ secrets.TELEGRAM_CHANNEL_OPENIPC_DEV }} + if: steps.build-gk7102-firmware.outcome != 'success' || steps.build-gk7102-sdk.outcome != 'success' + run: | + TG_OPTIONS="-s --connect-timeout 30 --max-time 30" + TG_NOTIFY="${TG_NOTIFY:=Warning, Buildroot compiling error... GK7102}" + TG_HEADER=$(echo -e "\r\n$TG_NOTIFY \r\n\r\nCommit: $GIT_HASH \r\nBranch: $BRANCH_NAME \r\nTag: $TAG_NAME \r\n\r\n\xE2\x9A\xA0 GitHub Actions") + curl $TG_OPTIONS -H "Content-Type: multipart/form-data" -X POST https://api.telegram.org/bot$TG_TOKEN/sendMessage \ + -F chat_id=$TG_CHANNEL -F text="$TG_HEADER" + + - name: Create release + uses: actions/create-release@v1 + continue-on-error: true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ env.TAG_NAME }} + release_name: ${{ env.RELEASE_NAME }} + draft: false + prerelease: ${{ env.PRERELEASE }} + + - name: Upload FW to release + uses: svenstaro/upload-release-action@v2 + continue-on-error: true + with: + repo_token: ${{ secrets.GITHUB_TOKEN }} + file: ${{ env.ARCHIVE_FW }} + asset_name: "openipc.gk7102-br.tgz" + tag: ${{ env.TAG_NAME }} + overwrite: true + + - name: Upload SDK to release + uses: svenstaro/upload-release-action@v2 + continue-on-error: true + with: + repo_token: ${{ secrets.GITHUB_TOKEN }} + file: ${{ env.ARCHIVE_SDK }} + asset_name: "arm-openipc-gk7102-linux-musleabi_sdk-buildroot.tar.gz" + tag: ${{ env.TAG_NAME }} + overwrite: true + + - name: Send binary file to telegram channel + env: + TG_TOKEN: ${{ secrets.TELEGRAM_TOKEN_BOT_OPENIPC }} + TG_CHANNEL: ${{ secrets.TELEGRAM_CHANNEL_OPENIPC_DEV }} + run: | + TG_OPTIONS="-s --connect-timeout 30 --max-time 30" + TG_HEADER=$(echo -e "\r\nCommit: $GIT_HASH \r\nBranch: $BRANCH_NAME \r\nTag: $TAG_NAME \r\n\r\n\xE2\x9C\x85 GitHub Actions") + curl $TG_OPTIONS -H "Content-Type: multipart/form-data" -X POST https://api.telegram.org/bot$TG_TOKEN/sendDocument \ + -F chat_id=$TG_CHANNEL -F document="@$ARCHIVE_FW" -F caption="$TG_HEADER" diff --git a/br-ext-chip-goke/Config.in b/br-ext-chip-goke/Config.in index dc0fb48f..32a92f2e 100644 --- a/br-ext-chip-goke/Config.in +++ b/br-ext-chip-goke/Config.in @@ -4,6 +4,7 @@ source "$BR2_EXTERNAL_GOKE_PATH/package/aura-httpd/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/dropbear-openipc/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/fdk-aac-openipc/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/fwprintenv-openipc/Config.in" +source "$BR2_EXTERNAL_GOKE_PATH/package/goke-osdrv-gk710x/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/goke-osdrv-gk7205v200/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/ipctool/Config.in" source "$BR2_EXTERNAL_GOKE_PATH/package/json-c-openipc/Config.in" diff --git a/br-ext-chip-goke/board/gk710x/kernel/gk710x.generic.config b/br-ext-chip-goke/board/gk710x/kernel/gk710x.generic.config new file mode 100644 index 00000000..6e852168 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/gk710x.generic.config @@ -0,0 +1,1732 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.43 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0xC0200000 +CONFIG_TEXT_OFFSET=0x00000000 +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" +CONFIG_LOCALVERSION="-Goke" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="openipc" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y + +# +# RCU Subsystem +# +CONFIG_TINY_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +CONFIG_ARCH_GK710X=y +# CONFIG_ARCH_GK710X_FPGA is not set +# CONFIG_ARCH_GK710XS is not set +# CONFIG_ARCH_GK710XS_FPGA is not set +# CONFIG_ARCH_GK720X is not set +# CONFIG_ARCH_GK720X_FPGA is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set + +# +# System MMU +# +# CONFIG_ONLY_USE_NOR_8M is not set +CONFIG_ONLY_USE_NOR_16M=y +# CONFIG_ONLY_USE_NOR_32M is not set +# CONFIG_ONLY_USE_NAND is not set +# CONFIG_USE_NOR_AND_NAND is not set + +# +# Gk710X select peripheral +# +CONFIG_PHY_USE_AO_MCLK=y +# CONFIG_PHY_USE_SD_CLK is not set +# CONFIG_PHY_USE_EXTERN_CLK is not set +CONFIG_PMU_POWER_OFF_CPU=y +# CONFIG_PMU_ALWAYS_RUNNING is not set +# CONFIG_PMU_AUTOMOTIVE is not set +# CONFIG_SYSTEM_USE_EXTERN_I2S is not set +CONFIG_GK_CHIP_INCLUDE_FILE="mach/gk710x.h" + +# +# soc/fpga modules list +# +CONFIG_PLAT_GOKE=y +CONFIG_GK_CPU_ARM_1176_V1_00=y +CONFIG_GK_PLL_CHIP_V1_00=y +CONFIG_GK_EFUSE=y +CONFIG_GK_EFUSE_V1_00=y +CONFIG_GK_CRYPT=y +CONFIG_GK_CRYPT_V1_00=y +CONFIG_GK_TIMER=y +CONFIG_GK_TIMER_V1_00=y +CONFIG_GK_WDT=y +CONFIG_GK_WDT_V1_00=y +CONFIG_GK_DDR2_CON=y +CONFIG_GK_DDR2_CON_V1_00=y +CONFIG_GK_DDR2_PHY=y +CONFIG_GK_DDR2_PHY_V1_00=y +CONFIG_GK_GPIO=y +CONFIG_GK_GPIO_V1_00=y +CONFIG_GK_GPIO_MAX_INPUT_TYPE=64 +CONFIG_GK_GPIO_INSTANCES=1 +CONFIG_GK_UART=y +CONFIG_GK_UART_V1_00=y +CONFIG_GK_MUSB=y +CONFIG_GK_MUSB_CON_V1_00=y +CONFIG_GK_USB_DMA=y +CONFIG_GK_USB_DMA_V1_00=y +CONFIG_GK_USB_PHY=y +CONFIG_GK_USB_PHY_V1_00=y +CONFIG_GK_I2S=y +CONFIG_GK_I2S_V1_00=y +CONFIG_GK_AUD_CON=y +CONFIG_GK_AUD_CON_V1_00=y +CONFIG_GK_AUD_AD=y +CONFIG_GK_AUD_AD_V1_00=y +CONFIG_GK_AUD_DMA=y +CONFIG_GK_AUD_DMA_V1_00=y +CONFIG_GK_ETH=y +CONFIG_GK_ETH_EMAC=y +CONFIG_GK_ETH_EMAC_V1_00=y +CONFIG_GK_ETH_EDMA=y +CONFIG_GK_ETH_EDMA_V1_00=y +CONFIG_GK_ETH_EPHY=y +CONFIG_GK_ETH_EPHY_V1_00=y +CONFIG_GK_PWM=y +CONFIG_GK_PWM_V1_00=y +CONFIG_GK_SDIO=y +CONFIG_GK_SDIO2=y +CONFIG_GK_SDIO2_V1_00=y +CONFIG_GK_ADC=y +CONFIG_GK_ADC_V1_00=y +CONFIG_GK_I2C=y +CONFIG_GK_I2C_V1_00=y +CONFIG_GK_SFLASH=y +CONFIG_GK_SFLASH_V1_00=y +CONFIG_GK_SPI=y +CONFIG_GK_SPI_V1_00=y +CONFIG_GK_PMU=y +CONFIG_GK_PMU_V1_00=y +CONFIG_GK_MCU=y +CONFIG_GK_MCU_V1_00=y +CONFIG_GK_RTC=y +CONFIG_GK_RTC_V1_00=y +CONFIG_GK_IR=y +CONFIG_GK_IR_V1_00=y +CONFIG_GK_VOUT=y +CONFIG_GK_VOUT_V1_00=y +CONFIG_GK_HDMI=y +CONFIG_GK_HDMI_V1_00=y +CONFIG_GK_MIPI=y +CONFIG_GK_MIPI_V1_00=y +CONFIG_GK_VIN=y +CONFIG_GK_VIN_V1_00=y +CONFIG_GK_MDMA=y +CONFIG_GK_MDMA_V1_00=y +CONFIG_GK_SMEM=y +CONFIG_GK_SMEM_V1_00=y +CONFIG_GK_DSP1=y +CONFIG_GK_DSP1_V1_00=y +CONFIG_GK_DSP2=y +CONFIG_GK_DSP2_V1_00=y +CONFIG_GK_ISP=y +CONFIG_GK_ISP_V1_00=y +CONFIG_GK_FW=y +CONFIG_GK_FW_V1_00=y +CONFIG_GK_FB=y +CONFIG_GK_FB_V1_00=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_USE_DOMAINS=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=4 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_ARCH_NR_GPIO=64 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_DEPRECATED_PARAM_STRUCT=y + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_UDP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_NETPRIO_CGROUP is not set +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_AFS_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_SFLASH_GOKE=y +CONFIG_SFLASH_1X_R_1X_W_MODE=y +# CONFIG_SFLASH_4X_R_1X_W_MODE is not set +# CONFIG_SFLASH_4X_R_4X_W_MODE is not set +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=y +CONFIG_MTD_PHRAM=y +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_SPINAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +CONFIG_ADC_GOKE=y +# CONFIG_PWM_GOKE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +CONFIG_ETH_GOKE=y +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=y + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_GOKE_IR=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_GOKE=y +CONFIG_SERIAL_GOKE_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_GOKE=y +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_GOKE=y +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_WATCHDOG_GOKE=y +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_ARCH_HAS_XHCI is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_DEBUG=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_GOKE=y +# CONFIG_CLOCK_32K is not set +CONFIG_CLOCK_24M=y +CONFIG_DMADEVICES=y +CONFIG_DMADEVICES_DEBUG=y +# CONFIG_DMADEVICES_VDEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_DISABLE_UNUSED is not set +# CONFIG_COMMON_CLK_DEBUG is not set + +# +# Hardware Spinlock drivers +# +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_OVERLAYFS_FS=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf-8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=0 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/br-ext-chip-goke/board/gk710x/kernel/gk710xs.generic.config b/br-ext-chip-goke/board/gk710x/kernel/gk710xs.generic.config new file mode 100644 index 00000000..98b956f7 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/gk710xs.generic.config @@ -0,0 +1,1733 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.43 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0xC0200000 +CONFIG_TEXT_OFFSET=0x00000000 +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" +CONFIG_LOCALVERSION="-Goke" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="openipc" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y + +# +# RCU Subsystem +# +CONFIG_TINY_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_GK710X is not set +# CONFIG_ARCH_GK710X_FPGA is not set +CONFIG_ARCH_GK710XS=y +# CONFIG_ARCH_GK710XS_FPGA is not set +# CONFIG_ARCH_GK720X is not set +# CONFIG_ARCH_GK720X_FPGA is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set + +# +# System MMU +# +# CONFIG_GK710XS_SDIO2 is not set +# CONFIG_ONLY_USE_NOR_8M is not set +CONFIG_ONLY_USE_NOR_16M=y +# CONFIG_ONLY_USE_NOR_32M is not set +# CONFIG_ONLY_USE_NAND is not set +# CONFIG_USE_NOR_AND_NAND is not set + +# +# Gk710X select peripheral +# +CONFIG_PHY_USE_AO_MCLK=y +# CONFIG_PHY_USE_SD_CLK is not set +# CONFIG_PHY_USE_EXTERN_CLK is not set +CONFIG_PMU_POWER_OFF_CPU=y +# CONFIG_PMU_ALWAYS_RUNNING is not set +# CONFIG_PMU_AUTOMOTIVE is not set +# CONFIG_SYSTEM_USE_EXTERN_I2S is not set +CONFIG_GK_CHIP_INCLUDE_FILE="mach/gk710xs.h" + +# +# soc/fpga modules list +# +CONFIG_PLAT_GOKE=y +CONFIG_GK_CPU_ARM_1176_V1_00=y +CONFIG_GK_PLL_CHIP_V1_00=y +CONFIG_GK_EFUSE=y +CONFIG_GK_EFUSE_V1_00=y +CONFIG_GK_CRYPT=y +CONFIG_GK_CRYPT_V1_00=y +CONFIG_GK_TIMER=y +CONFIG_GK_TIMER_V1_00=y +CONFIG_GK_WDT=y +CONFIG_GK_WDT_V1_00=y +CONFIG_GK_DDR2_CON=y +CONFIG_GK_DDR2_CON_V1_00=y +CONFIG_GK_DDR2_PHY=y +CONFIG_GK_DDR2_PHY_V1_00=y +CONFIG_GK_GPIO=y +CONFIG_GK_GPIO_V1_20=y +CONFIG_GK_GPIO_MAX_INPUT_TYPE=128 +CONFIG_GK_GPIO_INSTANCES=1 +CONFIG_GK_UART=y +CONFIG_GK_UART_V1_00=y +CONFIG_GK_MUSB=y +CONFIG_GK_MUSB_CON_V1_10=y +CONFIG_GK_USB_DMA=y +CONFIG_GK_USB_DMA_V1_00=y +CONFIG_GK_USB_PHY=y +CONFIG_GK_USB_PHY_V1_00=y +CONFIG_GK_I2S=y +CONFIG_GK_I2S_V1_00=y +CONFIG_GK_AUD_CON=y +CONFIG_GK_AUD_CON_V1_00=y +CONFIG_GK_AUD_AD=y +CONFIG_GK_AUD_AD_V1_00=y +CONFIG_GK_AUD_DMA=y +CONFIG_GK_AUD_DMA_V1_00=y +CONFIG_GK_ETH=y +CONFIG_GK_ETH_EMAC=y +CONFIG_GK_ETH_EMAC_V1_00=y +CONFIG_GK_ETH_EDMA=y +CONFIG_GK_ETH_EDMA_V1_00=y +CONFIG_GK_ETH_EPHY=y +CONFIG_GK_ETH_EPHY_V1_00=y +CONFIG_GK_PWM=y +CONFIG_GK_PWM_V1_00=y +CONFIG_GK_SDIO=y +CONFIG_GK_SDIO2=y +CONFIG_GK_SDIO2_V1_00=y +CONFIG_GK_ADC=y +CONFIG_GK_ADC_V1_00=y +CONFIG_GK_I2C=y +CONFIG_GK_I2C_V1_00=y +CONFIG_GK_SFLASH=y +CONFIG_GK_SFLASH_V1_00=y +CONFIG_GK_SPI=y +CONFIG_GK_SPI_V1_00=y +CONFIG_GK_PMU=y +CONFIG_GK_PMU_V1_00=y +CONFIG_GK_MCU=y +CONFIG_GK_MCU_V1_00=y +CONFIG_GK_RTC=y +CONFIG_GK_RTC_V1_00=y +CONFIG_GK_IR=y +CONFIG_GK_IR_V1_00=y +CONFIG_GK_VOUT=y +CONFIG_GK_VOUT_V1_00=y +CONFIG_GK_HDMI=y +CONFIG_GK_HDMI_V1_00=y +CONFIG_GK_MIPI=y +CONFIG_GK_MIPI_V1_00=y +CONFIG_GK_VIN=y +CONFIG_GK_VIN_V1_00=y +CONFIG_GK_MDMA=y +CONFIG_GK_MDMA_V1_00=y +CONFIG_GK_SMEM=y +CONFIG_GK_SMEM_V1_00=y +CONFIG_GK_DSP1=y +CONFIG_GK_DSP1_V1_00=y +CONFIG_GK_DSP2=y +CONFIG_GK_DSP2_V1_00=y +CONFIG_GK_ISP=y +CONFIG_GK_ISP_V1_00=y +CONFIG_GK_FW=y +CONFIG_GK_FW_V1_00=y +CONFIG_GK_FB=y +CONFIG_GK_FB_V1_00=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_USE_DOMAINS=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=4 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_ARCH_NR_GPIO=64 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_DEPRECATED_PARAM_STRUCT=y + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_UDP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_NETPRIO_CGROUP is not set +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_AFS_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_SFLASH_GOKE=y +CONFIG_SFLASH_1X_R_1X_W_MODE=y +# CONFIG_SFLASH_4X_R_1X_W_MODE is not set +# CONFIG_SFLASH_4X_R_4X_W_MODE is not set +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=y +CONFIG_MTD_PHRAM=y +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_SPINAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# Misc devices +# +CONFIG_ADC_GOKE=y +# CONFIG_PWM_GOKE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +CONFIG_ETH_GOKE=y +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=y + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_GOKE_IR=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_GOKE=y +CONFIG_SERIAL_GOKE_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_GOKE=y +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_GOKE=y +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_WATCHDOG_GOKE=y +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_ARCH_HAS_XHCI is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_DEBUG=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_GOKE=y +# CONFIG_CLOCK_32K is not set +CONFIG_CLOCK_24M=y +CONFIG_DMADEVICES=y +CONFIG_DMADEVICES_DEBUG=y +# CONFIG_DMADEVICES_VDEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_DISABLE_UNUSED is not set +# CONFIG_COMMON_CLK_DEBUG is not set + +# +# Hardware Spinlock drivers +# +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_OVERLAYFS_FS=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf-8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=0 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/br-ext-chip-goke/board/gk710x/kernel/overlay/include/linux/compiler-gcc7.h b/br-ext-chip-goke/board/gk710x/kernel/overlay/include/linux/compiler-gcc7.h new file mode 100644 index 00000000..613f9936 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/overlay/include/linux/compiler-gcc7.h @@ -0,0 +1,65 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +#define __used __attribute__((__used__)) +#define __must_check __attribute__((warn_unused_result)) +#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) + +/* Mark functions as cold. gcc will assume any path leading to a call + to them will be unlikely. This means a lot of manual unlikely()s + are unnecessary now for any paths leading to the usual suspects + like BUG(), printk(), panic() etc. [but let's keep them for now for + older compilers] + + Early snapshots of gcc 4.3 don't support this and we can't detect this + in the preprocessor, but we can live with this because they're unreleased. + Maketime probing would be overkill here. + + gcc also has a __attribute__((__hot__)) to move hot functions into + a special section, but I don't see any sense in this right now in + the kernel context */ +#define __cold __attribute__((__cold__)) + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ + +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() + +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +/* + * Tell the optimizer that something else uses this function or variable. + */ +#define __visible __attribute__((externally_visible)) + +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#define __HAVE_BUILTIN_BSWAP16__ +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/br-ext-chip-goke/board/gk710x/kernel/patches/0000-gk710x-kernel-3.4.43.patch b/br-ext-chip-goke/board/gk710x/kernel/patches/0000-gk710x-kernel-3.4.43.patch new file mode 100644 index 00000000..03c38e78 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/patches/0000-gk710x-kernel-3.4.43.patch @@ -0,0 +1,298910 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 7fe19a38..42b6b332 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -59,7 +59,7 @@ config GENERIC_GPIO + + config ARCH_USES_GETTIMEOFFSET + bool +- default n ++ default y + + config GENERIC_CLOCKEVENTS + bool +@@ -241,6 +241,13 @@ config PHYS_OFFSET + Please provide the physical address corresponding to the + location of main memory in your system. + ++config TEXT_OFFSET ++ hex "kernel start offset address base on physical address" ++ default 0x00000000 ++ help ++ Please provide the physical address corresponding to the ++ kernel start of main memory in your system. ++ + config GENERIC_BUG + def_bool y + depends on BUG +@@ -472,6 +479,832 @@ config ARCH_MXS + help + Support for Freescale MXS-based family of processors + ++config ARCH_GK710X ++ bool "Goke ipc GK710X family" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++ select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++ select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++ select GK_MUSB_CON_V1_00 ++# select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_00 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK710X(GK7101/GK7102/GK7103...) Soc ++ ++config ARCH_GK710X_FPGA ++ bool "Goke ipc GK710X FPGA" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++ select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++ select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++ select GK_MUSB_CON_V1_00 ++# select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_00 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK710X(GK7101/GK7102/GK7103...) FPGA ++ ++config ARCH_GK710XS ++ bool "Goke ipc GK710XS family" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++ select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++# select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_GPIO_V1_20 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++# select GK_MUSB_CON_V1_00 ++ select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_00 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK710XS(GK7101S/GK7102S/GK7103S...) Soc ++ ++config ARCH_GK710XS_FPGA ++ bool "Goke ipc GK710XS FPGA" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++ select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++# select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_GPIO_V1_20 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++# select GK_MUSB_CON_V1_00 ++ select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_00 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK710XS(GK7101S/GK7102S/GK7103S...) FPGA ++ ++config ARCH_GK720X ++ bool "Goke ipc GK720X_chip family" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++# select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++# select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_GPIO_V1_20 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++# select GK_MUSB_CON_V1_00 ++ select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_00 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK720X(GK7201/GK7202/GK7203...) chip ++ ++config ARCH_GK720X_FPGA ++ bool "Goke ipc GK720X_FPGA family" ++ select CPU_V6 ++ select HAVE_PWM ++ select MULTI_IRQ_HANDLER ++ select IRQ_DOMAIN ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_CLOCKEVENTS ++ select CLKDEV_LOOKUP ++ select COMMON_CLK ++ select NO_IOPORT ++# select PLAT_GOKE ++ select GK_CPU_ARM_1176_V1_00 ++# select GK_CPU_ARM_1176_V1_10 ++# select GK_CPU_ARM_1176_V1_20 ++# select GK_CPU_CORTEX_A7_V1_00 ++ select GK_BUS_NIC_400_V1_00 ++# select GK_BUS_CCN_V1_00 ++# select GK_BUS_NOC_V1_00 ++# select GK_PLL_FPGA_V1_00 ++# select GK_PLL_FPGA_V1_10 ++# select GK_PLL_FPGA_V1_20 ++# select GK_PLL_FPGA_V1_30 ++ select GK_PLL_CHIP_V1_00 ++# select GK_PLL_CHIP_V1_10 ++# select GK_PLL_CHIP_V1_20 ++# select GK_PLL_CHIP_V1_30 ++ select GK_EFUSE ++ select GK_EFUSE_V1_00 ++# select GK_EFUSE_V1_10 ++# select GK_EFUSE_V1_20 ++# select GK_EFUSE_V1_30 ++ select GK_CRYPT ++ select GK_CRYPT_V1_00 ++# select GK_CRYPT_V1_10 ++ select GK_TIMER ++ select GK_TIMER_V1_00 ++# select GK_TIMER_V1_10 ++ select GK_WDT ++ select GK_WDT_V1_00 ++# select GK_WDT_V1_10 ++ select GK_DDR2_CON ++ select GK_DDR2_CON_V1_00 ++# select GK_DDR2_CON_V1_10 ++ select GK_DDR2_PHY ++ select GK_DDR2_PHY_V1_00 ++# select GK_DDR2_PHY_V1_10 ++ select GK_GPIO ++# select GK_GPIO_V1_00 ++# select GK_GPIO_V1_10 ++ select GK_GPIO_V1_20 ++ select GK_UART ++ select GK_UART_V1_00 ++# select GK_UART_V1_10 ++# select GK_UART_V1_20 ++ select GK_MUSB ++# select GK_MUSB_CON_V1_00 ++ select GK_MUSB_CON_V1_10 ++ select GK_USB_DMA ++ select GK_USB_DMA_V1_00 ++# select GK_USB_DMA_V1_10 ++ select GK_USB_PHY ++ select GK_USB_PHY_V1_00 ++ select GK_I2S ++ select GK_I2S_V1_00 ++ select GK_AUD_CON ++ select GK_AUD_CON_V1_00 ++ select GK_AUD_AD ++ select GK_AUD_AD_V1_00 ++ select GK_AUD_DMA ++ select GK_AUD_DMA_V1_00 ++# select GK_AUD_DMA_V1_10 ++ select GK_ETH ++ select GK_ETH_EMAC ++ select GK_ETH_EMAC_V1_01 ++ select GK_ETH_EDMA ++ select GK_ETH_EDMA_V1_00 ++ select GK_ETH_EPHY ++ select GK_ETH_EPHY_V1_00 ++ select GK_PWM ++ select GK_PWM_V1_00 ++ select GK_SDIO ++ select GK_SDIO2 ++ select GK_SDIO2_V1_00 ++# select GK_SDIO3 ++# select GK_SDIO3_V1_00 ++ select GK_ADC ++ select GK_ADC_V1_00 ++# select GK_ADC_V1_10 ++ select GK_I2C ++ select GK_I2C_V1_00 ++ select GK_SFLASH ++ select GK_SFLASH_V1_00 ++ select GK_SPI ++ select GK_SPI_V1_00 ++ select GK_PMU ++ select GK_PMU_V1_00 ++# select GK_PMU_V1_10 ++ select GK_MCU ++ select GK_MCU_V1_00 ++ select GK_RTC ++ select GK_RTC_V1_00 ++ select GK_IR ++ select GK_IR_V1_00 ++ select GK_VOUT ++ select GK_VOUT_V1_00 ++# select GK_VOUT_V1_10 ++# select GK_VOUT_V1_20 ++ select GK_HDMI ++ select GK_HDMI_V1_00 ++ select GK_MIPI ++ select GK_MIPI_V1_00 ++ select GK_VIN ++ select GK_VIN_V1_00 ++# select GK_VIN_V1_10 ++# select GK_VIN_V1_20 ++ select GK_MDMA ++ select GK_MDMA_V1_00 ++ select GK_SMEM ++ select GK_SMEM_V1_00 ++# select GK_SMEM_V1_10 ++ select GK_DSP1 ++ select GK_DSP1_V1_00 ++ select GK_DSP2 ++ select GK_DSP2_V1_00 ++ select GK_ISP ++ select GK_ISP_V1_00 ++# select GK_ISP_V1_10 ++ select GK_FW ++ select GK_FW_V1_00 ++# select GK_FW_V1_10 ++# select GK_FW_V1_20 ++ select GK_FB ++ select GK_FB_V1_00 ++ help ++ Support for Goke GK720X(GK7201/GK7202/GK7203...) FPGA ++ + config ARCH_NETX + bool "Hilscher NetX based" + select CLKSRC_MMIO +@@ -1128,6 +1961,14 @@ source "arch/arm/mach-vt8500/Kconfig" + + source "arch/arm/mach-w90x900/Kconfig" + ++source "arch/arm/mach-gk710x/Kconfig" ++ ++source "arch/arm/mach-gk710xs/Kconfig" ++ ++ ++ ++source "arch/arm/plat-goke/Kconfig" ++ + # Definitions to make life easier + config ARCH_ACORN + bool +@@ -1618,10 +2459,16 @@ config LOCAL_TIMERS + "thundering herd" at every timer tick. + + config ARCH_NR_GPIO +- int ++ int "gpio numbers" + default 1024 if ARCH_SHMOBILE || ARCH_TEGRA + default 355 if ARCH_U8500 + default 264 if MACH_H4700 ++ default 55 if ARCH_GK710X ++ default 55 if ARCH_GK710X_FPGA ++ default 64 if ARCH_GK710XS ++ default 64 if ARCH_GK710XS_FPGA ++ default 64 if ARCH_GK720X_FPGA ++ default 64 if ARCH_GK720X + default 0 + help + Maximum number of GPIOs in the system. +@@ -1631,7 +2478,7 @@ config ARCH_NR_GPIO + source kernel/Kconfig.preempt + + config HZ +- int ++ int "TIME HZ" + default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ + ARCH_S5PV210 || ARCH_EXYNOS4 + default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index 1d6402cb..66aee95c 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -131,6 +131,12 @@ endif + textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 ++textofs-$(CONFIG_ARCH_GK710X) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) ++textofs-$(CONFIG_ARCH_GK710X_FPGA) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) ++textofs-$(CONFIG_ARCH_GK710XS) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) ++textofs-$(CONFIG_ARCH_GK710XS_FPGA) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) ++textofs-$(CONFIG_ARCH_GK720X) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) ++textofs-$(CONFIG_ARCH_GK720X_FPGA) := $(shell printf "0x%08x" $$(($(CONFIG_TEXT_OFFSET) + 0x8000))) + + # Machine directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. +@@ -143,6 +149,12 @@ machine-$(CONFIG_ARCH_DOVE) := dove + machine-$(CONFIG_ARCH_EBSA110) := ebsa110 + machine-$(CONFIG_ARCH_EP93XX) := ep93xx + machine-$(CONFIG_ARCH_GEMINI) := gemini ++machine-$(CONFIG_ARCH_GK710X) := gk710x ++machine-$(CONFIG_ARCH_GK710X_FPGA) := gk710x_fpga ++machine-$(CONFIG_ARCH_GK710XS) := gk710xs ++machine-$(CONFIG_ARCH_GK710XS_FPGA) := gk710xs_fpga ++machine-$(CONFIG_ARCH_GK720X) := gk720x ++machine-$(CONFIG_ARCH_GK720X_FPGA) := gk720x_fpga + machine-$(CONFIG_ARCH_H720X) := h720x + machine-$(CONFIG_ARCH_HIGHBANK) := highbank + machine-$(CONFIG_ARCH_INTEGRATOR) := integrator +@@ -212,6 +224,7 @@ plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung + plat-$(CONFIG_PLAT_S5P) := s5p samsung + plat-$(CONFIG_PLAT_SPEAR) := spear + plat-$(CONFIG_PLAT_VERSATILE) := versatile ++plat-$(CONFIG_PLAT_GOKE) := goke + + ifeq ($(CONFIG_ARCH_EBSA110),y) + # This is what happens if you forget the IOCS16 line. +diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile +index c877087d..8fd609b1 100644 +--- a/arch/arm/boot/Makefile ++++ b/arch/arm/boot/Makefile +@@ -54,6 +54,9 @@ $(obj)/compressed/vmlinux: $(obj)/Image FORCE + $(obj)/zImage: $(obj)/compressed/vmlinux FORCE + $(call if_changed,objcopy) + @echo ' Kernel: $@ is ready' ++ @echo ' ZRELADDR = $(ZRELADDR)' ++ @echo ' PARAMS_PHYS = $(PARAMS_PHYS)' ++ @echo ' INITRD_PHYS = $(INITRD_PHYS)' + + endif + +diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c +index 8e2a8fca..85003fde 100644 +--- a/arch/arm/boot/compressed/misc.c ++++ b/arch/arm/boot/compressed/misc.c +@@ -1,7 +1,7 @@ + /* + * misc.c +- * +- * This is a collection of several routines from gzip-1.0.3 ++ * ++ * This is a collection of several routines from gzip-1.0.3 + * adapted for Linux. + * + * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 +@@ -10,7 +10,7 @@ + * + * Nicolas Pitre 1999/04/14 : + * For this code to run directly from Flash, all constant variables must +- * be marked with 'const' and all other variables initialized at run-time ++ * be marked with 'const' and all other variables initialized at run-time + * only. This way all non constant variables will end up in the bss segment, + * which should point to addresses in RAM and cleared to 0 on start. + * This allows for a much quicker boot time. +@@ -27,6 +27,24 @@ extern void error(char *x); + + #include + ++/* avoid EXPORT_SYMBOL warning. */ ++#define EXPORT_SYMBOL(x) ++ ++#if GPIO_HAL_MODE ++HAL_IO(gpio) ++#else ++DIR_IO(gpio) ++#endif ++#if RCT_HAL_MODE ++HAL_IO(rct) ++#else ++DIR_IO(rct) ++#endif ++#if UART_HAL_MODE ++HAL_IO(uart) ++#else ++DIR_IO(uart) ++#endif + #ifdef CONFIG_DEBUG_ICEDCC + + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) +@@ -129,6 +147,72 @@ asmlinkage void __div0(void) + + extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); + ++static inline void clk_setting(void) ++{ ++ u32 type; ++ u32 ARMFreq; ++ ++ type = *(volatile u32 *)CONFIG_U2K_PHY_TYPE; ++ ++ if(type != 0){ ++#ifdef CONFIG_PHY_USE_SD_CLK ++ gk_gpio_setbitsl(GK_PA_GPIO0 + 0x3c, 0x00000001); ++ gk_rct_clrbitsl(GK_PA_RCT + 0x108, 0x00000018); ++ gk_rct_writel(GK_PA_RCT + 0x014, 0x0011202D); ++ gk_rct_writel(GK_PA_RCT + 0x01c, 0x00D55555); ++ gk_rct_writel(GK_PA_RCT + 0x018, 0x00000016); ++#endif ++#ifdef CONFIG_PHY_USE_AO_MCLK ++ gk_rct_writel(GK_PA_RCT + 0x024, 0x00124021); ++ gk_rct_writel(GK_PA_RCT + 0x078, 0x00555555); ++ if(type == 2)//50MHz ++ gk_rct_writel(GK_PA_RCT + 0x084, 0x00000002); ++ else//25MHz ++ gk_rct_writel(GK_PA_RCT + 0x084, 0x00000004); ++ gk_rct_writel(GK_PA_RCT + 0x080, 0x00000001); ++#endif ++ } ++ else ++ { ++ gk_gpio_clrbitsl(GK_PA_GPIO0 + 0x3c, 0x00000001); ++#ifdef CONFIG_PHY_USE_SD_CLK ++ gk_rct_setbitsl(GK_PA_RCT + 0x108, 0x00000018); ++ gk_rct_writel(GK_PA_RCT + 0x014, 0x0011202E); ++ gk_rct_writel(GK_PA_RCT + 0x01c, 0x00000000); ++ gk_rct_writel(GK_PA_RCT + 0x018, 0x00000017); ++#endif ++ ++#ifdef CONFIG_PHY_USE_AO_MCLK ++ gk_rct_writel(GK_PA_RCT + 0x024, 0x00124020); ++ gk_rct_writel(GK_PA_RCT + 0x078, 0x00000000); ++ gk_rct_writel(GK_PA_RCT + 0x084, 0x00000004); ++ gk_rct_writel(GK_PA_RCT + 0x080, 0x00000001); ++#endif ++ } ++ ++//misc clock configure ++ // SFLASH ioctrl ++ gk_rct_writel(GK_PA_RCT + 0x0198, 0x00000011); ++ ++ // Sensor ioctrl ++ gk_rct_writel(GK_PA_RCT + 0x019C, 0x00000012); ++ // modify idsp arm freq ++ //[25:20]REFDIV ++ //[18:16]PSTDIV2 ++ //[14:12]PSTDIV1 ++ //[11:0]FBDIV ++ // Fout=(Fin / REFDIV)*FBDIV/ POSTDIV1/ POSTDIV2 ++ // 0x53 = 1G ++ // 0x4B = 900M ++ // 0x43 = 800M ++ // 0x32 = 600M ++ // 0x21 = 400M ++ // 0x29 = 500M ++ //putstr("modify idsp arm freq\n"); ++ ARMFreq = *(volatile u32 *)CONFIG_U2K_ARM_FREQ; ++ gk_rct_writel(GK_PA_RCT + 0x8c, ARMFreq); ++} ++ + + void + decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, +@@ -144,6 +228,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, + + arch_decomp_setup(); + ++ clk_setting(); ++ + putstr("Uncompressing Linux..."); + ret = do_decompress(input_data, input_data_end - input_data, + output_data, error); +diff --git a/arch/arm/configs/gk710x_evb_mini_defconfig b/arch/arm/configs/gk710x_evb_mini_defconfig +new file mode 100644 +index 00000000..7b18b6b8 +--- /dev/null ++++ b/arch/arm/configs/gk710x_evb_mini_defconfig +@@ -0,0 +1,160 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0xC0200000 ++CONFIG_EXPERIMENTAL=y ++CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" ++CONFIG_LOCALVERSION="-gk" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_KERNEL_XZ=y ++CONFIG_DEFAULT_HOSTNAME="GK710X" ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_IKCONFIG=y ++CONFIG_CGROUPS=y ++CONFIG_NAMESPACES=y ++CONFIG_RELAY=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_ARCH_GK710X=y ++CONFIG_ONLY_USE_NOR_16M=y ++# CONFIG_ARM_THUMB is not set ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_KSM=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_DEPRECATED_PARAM_STRUCT=y ++CONFIG_KEXEC=y ++CONFIG_VFP=y ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_FIB_TRIE_STATS=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=y ++CONFIG_NET_IPGRE_DEMUX=y ++CONFIG_NET_IPGRE=y ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_ARPD=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++CONFIG_INET_IPCOMP=y ++CONFIG_INET_UDP_DIAG=y ++CONFIG_IPV6=y ++# CONFIG_WIRELESS is not set ++# CONFIG_FIRMWARE_IN_KERNEL is not set ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_AFS_PARTS=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_SFLASH_GOKE=y ++CONFIG_MTD_SLRAM=y ++CONFIG_MTD_PHRAM=y ++CONFIG_MTD_BLOCK2MTD=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_ADC_GOKE=y ++CONFIG_NETDEVICES=y ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CIRRUS is not set ++CONFIG_ETH_GOKE=y ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++CONFIG_INPUT_POLLDEV=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_GOKE_IR=y ++# CONFIG_SERIO is not set ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_GOKE=y ++CONFIG_SERIAL_GOKE_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_GOKE=y ++CONFIG_SPI=y ++CONFIG_SPI_SPIDEV=y ++CONFIG_SPI_GOKE=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_GOKE=y ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DEBUG=y ++CONFIG_RTC_DRV_GOKE=y ++CONFIG_DMADEVICES=y ++CONFIG_DMADEVICES_DEBUG=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_AUTOFS4_FS=y ++CONFIG_FSCACHE=y ++CONFIG_CACHEFILES=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_JFFS2_FS=y ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="cp437" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_PRINTK_TIME=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=0 ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_LZO=y ++CONFIG_CRYPTO_ANSI_CPRNG=y ++CONFIG_CRC16=y ++CONFIG_CRC_T10DIF=y ++CONFIG_CRC_ITU_T=y ++CONFIG_AVERAGE=y +diff --git a/arch/arm/configs/gk710xs_evb_mini_defconfig b/arch/arm/configs/gk710xs_evb_mini_defconfig +new file mode 100644 +index 00000000..358862f8 +--- /dev/null ++++ b/arch/arm/configs/gk710xs_evb_mini_defconfig +@@ -0,0 +1,160 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0xC0200000 ++CONFIG_EXPERIMENTAL=y ++CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" ++CONFIG_LOCALVERSION="-gk" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_KERNEL_XZ=y ++CONFIG_DEFAULT_HOSTNAME="GK710XS" ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_IKCONFIG=y ++CONFIG_CGROUPS=y ++CONFIG_NAMESPACES=y ++CONFIG_RELAY=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_ARCH_GK710XS=y ++CONFIG_ONLY_USE_NOR_16M=y ++# CONFIG_ARM_THUMB is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_KSM=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_DEPRECATED_PARAM_STRUCT=y ++CONFIG_KEXEC=y ++CONFIG_VFP=y ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_FIB_TRIE_STATS=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=y ++CONFIG_NET_IPGRE_DEMUX=y ++CONFIG_NET_IPGRE=y ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_ARPD=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++CONFIG_INET_IPCOMP=y ++CONFIG_INET_UDP_DIAG=y ++CONFIG_IPV6=y ++# CONFIG_WIRELESS is not set ++# CONFIG_FIRMWARE_IN_KERNEL is not set ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_AFS_PARTS=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_SFLASH_GOKE=y ++CONFIG_MTD_SLRAM=y ++CONFIG_MTD_PHRAM=y ++CONFIG_MTD_BLOCK2MTD=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_ADC_GOKE=y ++CONFIG_NETDEVICES=y ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CIRRUS is not set ++CONFIG_ETH_GOKE=y ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++CONFIG_INPUT_POLLDEV=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_GOKE_IR=y ++# CONFIG_SERIO is not set ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_GOKE=y ++CONFIG_SERIAL_GOKE_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_GOKE=y ++CONFIG_SPI=y ++CONFIG_SPI_SPIDEV=y ++CONFIG_SPI_GOKE=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_GOKE=y ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DEBUG=y ++CONFIG_RTC_DRV_GOKE=y ++CONFIG_DMADEVICES=y ++CONFIG_DMADEVICES_DEBUG=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_AUTOFS4_FS=y ++CONFIG_FSCACHE=y ++CONFIG_CACHEFILES=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_JFFS2_FS=y ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="cp437" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_PRINTK_TIME=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=0 ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_LZO=y ++CONFIG_CRYPTO_ANSI_CPRNG=y ++CONFIG_CRC16=y ++CONFIG_CRC_T10DIF=y ++CONFIG_CRC_ITU_T=y ++CONFIG_AVERAGE=y +diff --git a/arch/arm/configs/gk720x_evb_mini_defconfig b/arch/arm/configs/gk720x_evb_mini_defconfig +new file mode 100644 +index 00000000..a4662527 +--- /dev/null ++++ b/arch/arm/configs/gk720x_evb_mini_defconfig +@@ -0,0 +1,169 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0xC0300000 ++CONFIG_EXPERIMENTAL=y ++CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" ++CONFIG_LOCALVERSION="-gk" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_KERNEL_XZ=y ++CONFIG_DEFAULT_HOSTNAME="GK720X" ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_IKCONFIG=y ++CONFIG_CGROUPS=y ++CONFIG_NAMESPACES=y ++CONFIG_RELAY=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_ARCH_GK720X=y ++CONFIG_ONLY_USE_NOR_16M=y ++# CONFIG_ARM_THUMB is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_KSM=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_DEPRECATED_PARAM_STRUCT=y ++CONFIG_KEXEC=y ++CONFIG_VFP=y ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_FIB_TRIE_STATS=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=y ++CONFIG_NET_IPGRE_DEMUX=y ++CONFIG_NET_IPGRE=y ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_ARPD=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++CONFIG_INET_IPCOMP=y ++CONFIG_INET_UDP_DIAG=y ++CONFIG_IPV6=y ++CONFIG_INITRAMFS_SOURCE="/opt/goke/rootfs_uClibc" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++CONFIG_INITRAMFS_COMPRESSION_NONE=y ++# CONFIG_WIRELESS is not set ++# CONFIG_FIRMWARE_IN_KERNEL is not set ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_AFS_PARTS=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_SFLASH_GOKE=y ++CONFIG_MTD_SLRAM=y ++CONFIG_MTD_PHRAM=y ++CONFIG_MTD_BLOCK2MTD=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_ADC_GOKE=y ++CONFIG_NETDEVICES=y ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CIRRUS is not set ++CONFIG_ETH_GOKE=y ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++CONFIG_INPUT_POLLDEV=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_GOKE_IR=y ++# CONFIG_SERIO is not set ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_GOKE=y ++CONFIG_SERIAL_GOKE_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_GOKE=y ++CONFIG_SPI=y ++CONFIG_SPI_SPIDEV=y ++CONFIG_SPI_GOKE=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_GOKE=y ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DEBUG=y ++CONFIG_RTC_DRV_GOKE=y ++CONFIG_DMADEVICES=y ++CONFIG_DMADEVICES_DEBUG=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_AUTOFS4_FS=y ++CONFIG_FSCACHE=y ++CONFIG_CACHEFILES=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_JFFS2_FS=y ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="cp437" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_PRINTK_TIME=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=0 ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_LZO=y ++CONFIG_CRYPTO_ANSI_CPRNG=y ++CONFIG_CRC16=y ++CONFIG_CRC_T10DIF=y ++CONFIG_CRC_ITU_T=y ++CONFIG_AVERAGE=y +diff --git a/arch/arm/configs/gk720x_fpga_mini_defconfig b/arch/arm/configs/gk720x_fpga_mini_defconfig +new file mode 100644 +index 00000000..e224feba +--- /dev/null ++++ b/arch/arm/configs/gk720x_fpga_mini_defconfig +@@ -0,0 +1,169 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0xC0300000 ++CONFIG_EXPERIMENTAL=y ++CONFIG_CROSS_COMPILE="arm-goke-linux-uclibcgnueabi-" ++CONFIG_LOCALVERSION="-gk" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_KERNEL_XZ=y ++CONFIG_DEFAULT_HOSTNAME="GK720X_FPGA" ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_IKCONFIG=y ++CONFIG_CGROUPS=y ++CONFIG_NAMESPACES=y ++CONFIG_RELAY=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_ARCH_GK720X_FPGA=y ++CONFIG_ONLY_USE_NOR_16M=y ++# CONFIG_ARM_THUMB is not set ++CONFIG_MULTI_IRQ_HANDLER=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_KSM=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_DEPRECATED_PARAM_STRUCT=y ++CONFIG_KEXEC=y ++CONFIG_VFP=y ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=y ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_FIB_TRIE_STATS=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=y ++CONFIG_NET_IPGRE_DEMUX=y ++CONFIG_NET_IPGRE=y ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_ARPD=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++CONFIG_INET_IPCOMP=y ++CONFIG_INET_UDP_DIAG=y ++CONFIG_IPV6=y ++CONFIG_INITRAMFS_SOURCE="/opt/goke/rootfs_uClibc" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++CONFIG_INITRAMFS_COMPRESSION_NONE=y ++# CONFIG_WIRELESS is not set ++# CONFIG_FIRMWARE_IN_KERNEL is not set ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_AFS_PARTS=y ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_SFLASH_GOKE=y ++CONFIG_MTD_SLRAM=y ++CONFIG_MTD_PHRAM=y ++CONFIG_MTD_BLOCK2MTD=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_ADC_GOKE=y ++CONFIG_NETDEVICES=y ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CIRRUS is not set ++CONFIG_ETH_GOKE=y ++# CONFIG_NET_VENDOR_FARADAY is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++CONFIG_INPUT_POLLDEV=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_GOKE_IR=y ++# CONFIG_SERIO is not set ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_GOKE=y ++CONFIG_SERIAL_GOKE_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_GOKE=y ++CONFIG_SPI=y ++CONFIG_SPI_SPIDEV=y ++CONFIG_SPI_GOKE=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_GOKE=y ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DEBUG=y ++CONFIG_RTC_DRV_GOKE=y ++CONFIG_DMADEVICES=y ++CONFIG_DMADEVICES_DEBUG=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_AUTOFS4_FS=y ++CONFIG_FSCACHE=y ++CONFIG_CACHEFILES=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_JFFS2_FS=y ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="cp437" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_PRINTK_TIME=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=0 ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_LZO=y ++CONFIG_CRYPTO_ANSI_CPRNG=y ++CONFIG_CRC16=y ++CONFIG_CRC_T10DIF=y ++CONFIG_CRC_ITU_T=y ++CONFIG_AVERAGE=y +diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h +index 9af5563d..619c4132 100644 +--- a/arch/arm/include/asm/io.h ++++ b/arch/arm/include/asm/io.h +@@ -28,6 +28,10 @@ + #include + #include + ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++#include ++ + /* + * ISA I/O bus memory addresses are 1:1 with the physical address. + */ +@@ -47,13 +51,15 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); + extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); + extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); + +-#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) +-#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) +-#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v)) + +-#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) +-#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) +-#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) ++#define __raw_writeb(v,a) (__chk_io_ptr(a), gk_hw_writeb((u32)a,v)) ++#define __raw_writew(v,a) (__chk_io_ptr(a), gk_hw_writew((u32)a,v)) ++#define __raw_writel(v,a) (__chk_io_ptr(a), gk_hw_writel((u32)a,v)) ++ ++#define __raw_readb(a) (__chk_io_ptr(a), gk_hw_readb((u32)a)) ++#define __raw_readw(a) (__chk_io_ptr(a), gk_hw_readw((u32)a)) ++#define __raw_readl(a) (__chk_io_ptr(a), gk_hw_readl((u32)a)) ++ + + /* + * Architecture ioremap implementation. +diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h +index fcb57574..32d1f18a 100644 +--- a/arch/arm/include/asm/memory.h ++++ b/arch/arm/include/asm/memory.h +@@ -81,6 +81,7 @@ + #define IOREMAP_MAX_ORDER 24 + + #define CONSISTENT_END (0xffe00000UL) ++#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) + + #else /* CONFIG_MMU */ + +diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h +index 41dc31f8..83a83ea0 100644 +--- a/arch/arm/include/asm/pgtable.h ++++ b/arch/arm/include/asm/pgtable.h +@@ -105,7 +105,8 @@ extern pgprot_t pgprot_kernel; + + #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE + #define pgprot_dmacoherent(prot) \ +- __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN) ++ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) ++// __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN) + #define __HAVE_PHYS_MEM_ACCESS_PROT + struct file; + extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, +diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S +index a9b9e228..25d403ef 100644 +--- a/arch/arm/lib/memcpy.S ++++ b/arch/arm/lib/memcpy.S +@@ -47,6 +47,10 @@ + .macro enter reg1 reg2 + stmdb sp!, {r0, \reg1, \reg2} + .endm ++ ++ .macro usave reg1 reg2 ++ UNWIND( .save {r0, \reg1, \reg2} ) ++ .endm + + .macro exit reg1 reg2 + ldmfd sp!, {r0, \reg1, \reg2} +diff --git a/arch/arm/mach-gk710x/Kconfig b/arch/arm/mach-gk710x/Kconfig +new file mode 100644 +index 00000000..9db429ca +--- /dev/null ++++ b/arch/arm/mach-gk710x/Kconfig +@@ -0,0 +1,27 @@ ++# ++# arch/arm/mach-gk710x/Kconfig ++# ++# History: ++# 2014/06/18 - [Kewell Liu] created file ++# ++# Copyright (C) 2002-2016, Goke Microelectronics China. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++# ++ ++if ARCH_GK710X ++ ++endif ++ +diff --git a/arch/arm/mach-gk710x/Makefile b/arch/arm/mach-gk710x/Makefile +new file mode 100644 +index 00000000..e5835428 +--- /dev/null ++++ b/arch/arm/mach-gk710x/Makefile +@@ -0,0 +1,13 @@ ++ ++obj-$(CONFIG_ARCH_GK710X) += gk710x.o ++obj-$(CONFIG_ARCH_GK710X) += irq.o ++obj-$(CONFIG_ARCH_GK710X) += rct.o ++obj-$(CONFIG_ARCH_GK710X) += mdma.o dma.o ++obj-$(CONFIG_ARCH_GK710X) += vi.o ++ ++obj-$(CONFIG_ARCH_GK710X) += mach-gk710x.o ++ ++ccflags-$(CONFIG_ARCH_GK710X) += -D__LINUX__ ++ ++ccflags-$(CONFIG_ARCH_GK710X) += -Iarch/arm/mach-gk710x/include ++ +diff --git a/arch/arm/mach-gk710x/Makefile.boot b/arch/arm/mach-gk710x/Makefile.boot +new file mode 100644 +index 00000000..f835b343 +--- /dev/null ++++ b/arch/arm/mach-gk710x/Makefile.boot +@@ -0,0 +1,6 @@ ++ ++zreladdr-y := $(shell printf "0x%08x" $$(($(CONFIG_PHYS_OFFSET) + $(TEXT_OFFSET)))) ++params_phys-y := $(shell printf "0x%08x" $$(($(CONFIG_PHYS_OFFSET) + 0x100))) ++ ++dtb-y += gk7101-evb.dtb ++ +diff --git a/arch/arm/mach-gk710x/dma.c b/arch/arm/mach-gk710x/dma.c +new file mode 100644 +index 00000000..9304ee04 +--- /dev/null ++++ b/arch/arm/mach-gk710x/dma.c +@@ -0,0 +1,507 @@ ++/* ++ * arch/arm/mach-gk/dma.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct dma_s G_dma; ++static spinlock_t dma_lock; ++static gk_dma_req_t *dummy_descriptor = NULL; ++static dma_addr_t dummy_descriptor_phys; ++ ++#ifdef CONFIG_GK_DMA_PROC ++static const char dma_proc_name[] = "dma"; ++static struct proc_dir_entry *dma_file; ++ ++static int gk_dma_proc_read(char *buf, char **start, off_t off, ++ int len, int *eof, void *data) ++{ ++ char *p = buf; ++ ++ p += sprintf(p, "You can add something here to debug DMA \n"); ++ ++ return p - buf; ++} ++#endif ++ ++extern void gk_usb_dma_irq(void); ++static irqreturn_t gk_dma_int_handler(int irq, void *dev_id) ++{ ++ struct dma_s *dma; ++ int i; ++ int j; ++ u32 ireg; ++ ++ dma = (struct dma_s *)dev_id; ++ ++ ireg = gk_dma_readl(DMA_INT_REG); ++ for (i = 0; i < NUM_DMA_CHANNELS; i++) { ++ if (ireg & (0x1 << i)) { ++ dma->chan[i].status = gk_dma_readl(DMA_CHAN_STA_REG(i)); ++ gk_dma_writel(DMA_CHAN_STA_REG(i), 0); ++ ++ for (j = 0; j < dma->chan[i].irq_count; j++) { ++ if (dma->chan[i].irq[j].enabled == 1) { ++ dma->chan[i].irq[j].handler( ++ dma->chan[i].irq[j].harg, ++ dma->chan[i].status); ++ } ++ } ++ } ++ } ++#if 0 ++ if (ireg & 0x8) { ++ //printk("@:%x\n", ireg); ++ //printk("$\n"); ++ gk_usb_dma_irq(); ++ } ++#endif ++ return IRQ_HANDLED; ++} ++ ++#if (DMA_SUPPORT_DMA_FIOS == 1) ++static irqreturn_t gk_dma_fios_int_handler(int irq, void *dev_id) ++{ ++ struct dma_s *dma; ++ int i; ++ u32 ireg; ++ ++ dma = (struct dma_s *)dev_id; ++ ++ ireg = gk_dma_readl(DMA_FIOS_INT_REG); ++ if (ireg & DMA_INT_CHAN0) { ++ dma->chan[FIO_DMA_CHAN].status = ++ gk_dma_readl(DMA_FIOS_CHAN_STA_REG(FIO_DMA_CHAN)); ++ gk_dma_writel(DMA_FIOS_CHAN_STA_REG(FIO_DMA_CHAN), 0); ++ ++ for (i = 0; i < dma->chan[FIO_DMA_CHAN].irq_count; i++) { ++ if (dma->chan[FIO_DMA_CHAN].irq[i].enabled == 1) { ++ dma->chan[FIO_DMA_CHAN].irq[i].handler( ++ dma->chan[FIO_DMA_CHAN].irq[i].harg, ++ dma->chan[FIO_DMA_CHAN].status); ++ } ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++int gk_dma_request_irq(int chan, ++ gk_dma_handler handler, void *harg) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ if (unlikely(G_dma.chan[chan].irq_count > ++ MAX_DMA_CHANNEL_IRQ_HANDLERS)) { ++ pr_err("%s: chan[%d]'s irq_count[%d] > " ++ "MAX_DMA_CHANNEL_IRQ_HANDLERS[%d]!\n", ++ __func__, chan, G_dma.chan[chan].irq_count, ++ MAX_DMA_CHANNEL_IRQ_HANDLERS); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit; ++ } ++ ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ G_dma.chan[chan].irq[i].handler = handler; ++ G_dma.chan[chan].irq[i].harg = harg; ++ G_dma.chan[chan].irq_count++; ++ break; ++ } ++ } ++ ++gk_dma_request_irq_exit: ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_request_irq_exit_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_request_irq); ++ ++void gk_dma_free_irq(int chan, gk_dma_handler handler) ++{ ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ return; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ if (unlikely(G_dma.chan[chan].irq_count > ++ MAX_DMA_CHANNEL_IRQ_HANDLERS)) { ++ pr_err("%s: chan[%d]'s irq_count[%d] > " ++ "MAX_DMA_CHANNEL_IRQ_HANDLERS[%d]!\n", ++ __func__, chan, G_dma.chan[chan].irq_count, ++ MAX_DMA_CHANNEL_IRQ_HANDLERS); ++ goto gk_dma_free_irq_exit; ++ } ++ ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ G_dma.chan[chan].irq[i].handler = NULL; ++ G_dma.chan[chan].irq[i].harg = NULL; ++ G_dma.chan[chan].irq_count--; ++ break; ++ } ++ } ++ ++ for (i = i + 1; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler != NULL) { ++ G_dma.chan[chan].irq[i - 1].enabled = ++ G_dma.chan[chan].irq[i].enabled; ++ G_dma.chan[chan].irq[i - 1].handler = ++ G_dma.chan[chan].irq[i].handler; ++ G_dma.chan[chan].irq[i - 1].harg = ++ G_dma.chan[chan].irq[i].harg; ++ G_dma.chan[chan].irq[i].handler = NULL; ++ G_dma.chan[chan].irq[i].harg = NULL; ++ G_dma.chan[chan].irq[i].enabled = 0; ++ } ++ } ++ ++gk_dma_free_irq_exit: ++ spin_unlock_irqrestore(&dma_lock, flags); ++} ++EXPORT_SYMBOL(gk_dma_free_irq); ++ ++int gk_dma_enable_irq(int chan, gk_dma_handler handler) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_enable_irq_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_enable_irq_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ retval = -EINVAL; ++ pr_err("%s: can't find 0x%x!\n", ++ __func__, (u32)handler); ++ break; ++ } ++ ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 1; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_enable_irq_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_enable_irq); ++ ++int gk_dma_disable_irq(int chan, gk_dma_handler handler) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_disable_irq_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_disable_irq_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ retval = -EINVAL; ++ pr_err("%s: can't find 0x%x!\n", ++ __func__, (u32)handler); ++ break; ++ } ++ ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_disable_irq_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_disable_irq); ++ ++static inline int gk_req_dma(gk_dma_req_t * req, int chan) ++{ ++ int retval = 0; ++ u32 ctr = 0; ++ ++ if (unlikely(req->xfr_count > 0x003fffff)) { ++ pr_err("%s: xfr_count[0x%x] out of range!\n", ++ __func__, req->xfr_count); ++ retval = -EINVAL; ++ goto gk_req_dma_exit; ++ } ++ ++ gk_dma_writel(DMA_CHAN_STA_REG(chan), 0); ++ ++ if (req->next == NULL) { ++ gk_dma_writel(DMA_CHAN_SRC_REG(chan), req->src); ++ ++ gk_dma_writel(DMA_CHAN_DST_REG(chan), req->dst); ++ ++ ctr |= (req->attr | req->xfr_count); ++ ctr &= ~DMA_CHANX_CTR_D; ++ ctr |= DMA_CHANX_CTR_EN; ++ ++ } else {/* Descriptor mode */ ++ gk_dma_writel((u32) req, DMA_CHAN_DA_REG(chan)); ++ ++ ctr |= DMA_CHANX_CTR_D; ++ ctr |= DMA_CHANX_CTR_EN; ++ } ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), ctr); ++ ++gk_req_dma_exit: ++ return retval; ++} ++ ++int gk_dma_xfr(gk_dma_req_t *req, int chan) ++{ ++ int retval = 0; ++ ++ ++#ifdef CHECK_DMA_CHAN_USE_FLAG ++ unsigned long flags; ++#endif ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_xfr_exit; ++ } ++ ++ if (unlikely(req == NULL)) { ++ pr_err("%s: req is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_xfr_exit; ++ } ++ ++#ifdef CHECK_DMA_CHAN_USE_FLAG ++ spin_lock_irqsave(&dma_lock, flags); ++ G_dma.chan[chan].use_flag = 1; ++ spin_unlock_irqrestore(&dma_lock, flags); ++#endif ++ ++ retval = gk_req_dma(req, chan); ++ ++gk_dma_xfr_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_xfr); ++ ++int gk_dma_desc_xfr(dma_addr_t desc_addr, int chan) ++{ ++ ++ ++ if (unlikely(desc_addr == 0)) { ++ pr_err("%s: desc_addr is NULL!\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely((desc_addr & 0x7) != 0)) { ++ pr_err("%s: desc_addr isn't aligned!\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return -EINVAL; ++ } ++ ++ if (gk_dma_readl(DMA_CHAN_CTR_REG(chan)) & DMA_CHANX_CTR_EN) ++ pr_err("%s: dma (channel = %d) is still enabled!\n", __func__, chan); ++ ++ gk_dma_writel(DMA_CHAN_DA_REG(chan), desc_addr); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), DMA_CHANX_CTR_EN | DMA_CHANX_CTR_D); ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_dma_desc_xfr); ++ ++int gk_dma_desc_stop(int chan) ++{ ++ ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return -EINVAL; ++ } ++ ++ /* Disable DMA: following sequence is not mentioned at APM.*/ ++ if (gk_dma_readl(DMA_CHAN_CTR_REG(chan)) & DMA_CHANX_CTR_EN) { ++ gk_dma_writel(DMA_CHAN_STA_REG(chan), DMA_CHANX_STA_DD); ++ ++ ++ gk_dma_writel(DMA_CHAN_DA_REG(chan), dummy_descriptor_phys); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), 0x28000000); ++ ++ ++ udelay(1); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_dma_desc_stop); ++ ++int gk_dma_read_ctrl_reg(int chan) ++{ ++ return gk_dma_readl(DMA_CHAN_CTR_REG(chan));//add by DONALD, for audio drv use, mask different register addr macro value. ++} ++EXPORT_SYMBOL(gk_dma_read_ctrl_reg); ++ ++ ++int __init gk_init_dma(void) ++{ ++ int retval = 0; ++ int i; ++ struct dma_s *dma = &G_dma; ++ gk_dma_req_t *dma_desc_array; ++ ++ spin_lock_init(&dma_lock); ++ memset(&G_dma, 0x0, sizeof(G_dma)); ++ ++ dummy_descriptor = dma_alloc_coherent(NULL, ++ sizeof(gk_dma_req_t) * 4, ++ &dummy_descriptor_phys, GFP_KERNEL); ++ if (!dummy_descriptor) { ++ retval = -ENOMEM; ++ goto gk_init_dma_exit; ++ } ++ ++ dma_desc_array = (gk_dma_req_t *)dummy_descriptor; ++ dma_desc_array->attr = DMA_DESC_EOC | DMA_DESC_WM | DMA_DESC_NI | ++ DMA_DESC_IE | DMA_DESC_ST | DMA_DESC_ID; ++ dma_desc_array->src = 0; ++ dma_desc_array->next = (gk_dma_req_t *)dummy_descriptor_phys; ++ dma_desc_array->rpt = dummy_descriptor_phys + sizeof(gk_dma_req_t); ++ dma_desc_array->dst = dummy_descriptor_phys + sizeof(gk_dma_req_t) * 2; ++ dma_desc_array->xfr_count = 0; ++ ++ retval = request_irq(DMA_IRQ, gk_dma_int_handler, ++ IRQ_TYPE_LEVEL_HIGH, "gk-dma", dma); ++ if (retval) { ++ pr_err("%s: request_irq %d fail %d!\n", ++ __func__, DMA_IRQ, retval); ++ goto gk_init_dma_exit; ++ } ++ ++ for (i = 0; i < NUM_DMA_CHANNELS; i++) { ++ gk_dma_writel(DMA_CHAN_STA_REG(i), 0); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(i), 0x38000000); ++ ++ } ++ ++#if (DMA_SUPPORT_DMA_FIOS == 1) ++ retval = request_irq(DMA_FIOS_IRQ, gk_dma_fios_int_handler, ++ IRQ_TYPE_LEVEL_HIGH, "gk-fios-dma", dma); ++ if (retval){ ++ pr_err("%s: request_irq %d fail %d!\n", ++ __func__, DMA_FIOS_IRQ, retval); ++ goto gk_init_dma_exit; ++ } ++ gk_dma_writel(DMA_FIOS_CHAN_STA_REG(0), 0); ++ ++ ++ gk_dma_writel(DMA_FIOS_CHAN_CTR_REG(0), 0x38000000); ++ ++#endif ++ ++#ifdef CONFIG_GK_DMA_PROC ++ dma_file = create_proc_entry(dma_proc_name, S_IRUGO | S_IWUSR, ++ get_gk_proc_dir()); ++ if (dma_file == NULL) { ++ retval = -ENOMEM; ++ pr_err("%s: for %s fail!\n", __func__, dma_proc_name); ++ } else { ++ dma_file->read_proc = gk_dma_proc_read; ++ dma_file->write_proc = NULL; ++ } ++#endif ++ ++gk_init_dma_exit: ++ return retval; ++} ++ +diff --git a/arch/arm/mach-gk710x/gk710x.c b/arch/arm/mach-gk710x/gk710x.c +new file mode 100644 +index 00000000..41de4f51 +--- /dev/null ++++ b/arch/arm/mach-gk710x/gk710x.c +@@ -0,0 +1,774 @@ ++/* ++ * linux/arch/arm/mach-gk/gk.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++//#define KE_DEBUG ++ ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++extern u8* load_data_init(void); ++ ++ ++struct gk_mem_map_desc ++{ ++ char name[32]; ++ struct map_desc io_desc; ++}; ++ ++/* the module name MUST match hardware.h */ ++#define IOMAP_DESC_ENTRY(module, len) { \ ++ .virtual = GK_VA_##module, \ ++ .pfn = __phys_to_pfn(GK_PA_##module), \ ++ .length = (len), \ ++ .type = MT_DEVICE \ ++} ++ ++#define GK_IOMAP(module_name, module, len) { \ ++ .name = module_name, \ ++ IOMAP_DESC_ENTRY(module, len), \ ++} ++ ++ ++#define GK_IO_DESC_AHB_ID 0 ++#define GK_IO_DESC_APB_ID 1 ++#define GK_IO_DESC_PPM_ID 2 ++#define GK_IO_DESC_BSB_ID 3 ++#define GK_IO_DESC_DSP_ID 4 ++#define GK_IO_DESC_USR_ID 5 ++ ++static struct gk_mem_map_desc gk_mem_desc[] = ++{ ++ // reserved 0xF0000000 to hal1, and 0xF1000000 to hal2 ++ // used in get_hal1_virt & get_hal2_virt; ++ [GK_IO_DESC_AHB_ID] = ++ {/*0*/ ++ .name = "AHB", ++ .io_desc = ++ { ++ .virtual= GK_VA_AHB_BASE, ++ .pfn = __phys_to_pfn(GK_PA_AHB_BASE), ++ .length = 0x01000000, ++ .type = MT_DEVICE, ++ }, ++ }, ++ [GK_IO_DESC_APB_ID] = ++ {/*1*/ ++ .name = "APB", ++ .io_desc = ++ { ++ .virtual= GK_VA_APB_BASE, ++ .pfn = __phys_to_pfn(GK_PA_APB_BASE), ++ .length = 0x01000000, ++ .type = MT_DEVICE, ++ }, ++ }, ++ [GK_IO_DESC_PPM_ID] = ++ {/*2*/ ++ .name = "PPM", /*Private Physical Memory*/ ++ .io_desc = ++ { ++ .virtual= 0xc0000000, ++ .pfn = __phys_to_pfn(0xc0000000/*DEFAULT_MEM_START*/), ++ .length = CONFIG_PHYS_OFFSET-0xc0000000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_BSB_ID] = ++ {/*3*/ ++ .name = "BSB", ++ .io_desc = ++ { ++ .virtual= 0xf5000000, ++ .pfn = __phys_to_pfn(0xc2800000), ++ .length = 0x00200000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_DSP_ID] = ++ {/*4*/ ++ .name = "DSP", ++ .io_desc = ++ { ++ .virtual= 0xf6000000, ++ .pfn = __phys_to_pfn(0xC2a00000), ++ .length = 0x01500000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_USR_ID] = ++ {/*5*/ ++ .name = "USR", ++ .io_desc = ++ { ++ .virtual= 0xfe000000, // dsp_size <= 0xfe000000-0xf6000000 ++ .pfn = __phys_to_pfn(0xC3FF0000), ++ .length = 0x00010000, ++ .type = MT_MEMORY, ++ }, ++ }, ++}; ++ ++ ++ ++#if 1 ++//-----------HAL1------------- ++u32 get_hal1_virt(void) ++{ ++ return 0xF0000000; ++} ++EXPORT_SYMBOL(get_hal1_virt); ++ ++//-----------HAL2------------- ++u32 get_hal2_virt(void) ++{ ++ return 0xF1000000; ++} ++EXPORT_SYMBOL(get_hal2_virt); ++ ++//-----------AHB------------- ++u32 get_ahb_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_ahb_phys); ++ ++u32 get_ahb_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_ahb_virt); ++ ++u32 get_ahb_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_ahb_size); ++ ++//-----------APB------------- ++u32 get_apb_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_apb_phys); ++ ++u32 get_apb_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_apb_virt); ++ ++u32 get_apb_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_apb_size); ++ ++//-----------PPM------------- ++u32 get_ppm_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_ppm_phys); ++ ++u32 get_ppm_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_ppm_virt); ++ ++u32 get_ppm_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_ppm_size); ++ ++//-----------DSP------------- ++u32 get_dspmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_dspmem_virt); ++ ++u32 get_dspmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_dspmem_size); ++ ++u32 get_dspmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_dspmem_phys); ++ ++//-----------BSB------------- ++u32 get_bsbmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_bsbmem_phys); ++ ++u32 get_bsbmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_bsbmem_virt); ++ ++u32 get_bsbmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_bsbmem_size); ++u32 get_usrmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_usrmem_phys); ++u32 get_usrmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_usrmem_virt); ++u32 get_usrmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_usrmem_size); ++ ++ ++ ++u32 gk_phys_to_virt(u32 paddr) ++{ ++ int i; ++ u32 phystart; ++ u32 phylength; ++ u32 phyoffset; ++ u32 vstart; ++ ++ for (i = 0; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ phystart = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ phylength = gk_mem_desc[i].io_desc.length; ++ vstart = gk_mem_desc[i].io_desc.virtual; ++ if ((paddr >= phystart) && (paddr < (phystart + phylength))) ++ { ++ phyoffset = paddr - phystart; ++ return (vstart + phyoffset); ++ } ++ } ++ ++ return __phys_to_virt(paddr); ++} ++EXPORT_SYMBOL(gk_phys_to_virt); ++ ++u32 gk_virt_to_phys(u32 vaddr) ++{ ++ int i; ++ u32 phystart; ++ u32 vlength; ++ u32 voffset; ++ u32 vstart; ++ ++ for (i = 0; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ phystart = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ vlength = gk_mem_desc[i].io_desc.length; ++ vstart = gk_mem_desc[i].io_desc.virtual; ++ if ((vaddr >= vstart) && (vaddr < (vstart + vlength))) ++ { ++ voffset = vaddr - vstart; ++ return (phystart + voffset); ++ } ++ } ++ ++ return __virt_to_phys(vaddr); ++} ++EXPORT_SYMBOL(gk_virt_to_phys); ++#endif ++ ++void get_stepping_info(int *chip, int *major, int *minor) ++{ ++ *chip = 0x5; ++ *major = 0x1; ++ *minor = 0x0; ++} ++EXPORT_SYMBOL(get_stepping_info); ++ ++/* ==========================================================================*/ ++u64 gk_dmamask = DMA_BIT_MASK(32); ++EXPORT_SYMBOL(gk_dmamask); ++ ++ ++/* ==========================================================================*/ ++static struct proc_dir_entry *gk_proc_dir = NULL; ++ ++int __init gk_create_proc_dir(void) ++{ ++ int retval = 0; ++ ++ printk("create proc dir\n"); ++ ++ gk_proc_dir = proc_mkdir("goke", NULL); ++ if (!gk_proc_dir) ++ retval = -ENOMEM; ++ ++ return retval; ++} ++ ++struct proc_dir_entry *get_gk_proc_dir(void) ++{ ++ return gk_proc_dir; ++} ++EXPORT_SYMBOL(get_gk_proc_dir); ++ ++/* ==========================================================================*/ ++typedef void* (*hal_function_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) ; ++ ++struct hw_ops *g_hw; ++EXPORT_SYMBOL(g_hw); ++ ++ ++#if HW_HAL_MODE ++HAL_IO(hw) ++#else ++DIR_IO(hw) ++#endif ++ ++#if ADC_HAL_MODE ++HAL_IO(adc) ++#else ++DIR_IO(adc) ++#endif ++#if AUD_HAL_MODE ++HAL_IO(aud) ++#else ++DIR_IO(aud) ++#endif ++#if CRY_HAL_MODE ++HAL_IO(cry) ++#else ++DIR_IO(cry) ++#endif ++#if DDR_HAL_MODE ++HAL_IO(ddr) ++#else ++DIR_IO(ddr) ++#endif ++#if DSP_HAL_MODE ++HAL_IO(dsp) ++#else ++DIR_IO(dsp) ++#endif ++#if ETH_HAL_MODE ++HAL_IO(eth) ++#else ++DIR_IO(eth) ++#endif ++#if GREG_HAL_MODE ++HAL_IO(greg) ++#else ++DIR_IO(greg) ++#endif ++#if GPIO_HAL_MODE ++HAL_IO(gpio) ++#else ++DIR_IO(gpio) ++#endif ++#if I2C_HAL_MODE ++HAL_IO(i2c) ++#else ++DIR_IO(i2c) ++#endif ++#if I2S_HAL_MODE ++HAL_IO(i2s) ++#else ++DIR_IO(i2s) ++#endif ++#if IR_HAL_MODE ++HAL_IO(ir) ++#else ++DIR_IO(ir) ++#endif ++#if IRQ_HAL_MODE ++HAL_IO(irq) ++#else ++DIR_IO(irq) ++#endif ++#if MCU_HAL_MODE ++HAL_IO(mcu) ++#else ++DIR_IO(mcu) ++#endif ++#if PWM_HAL_MODE ++HAL_IO(pwm) ++#else ++DIR_IO(pwm) ++#endif ++#if RCT_HAL_MODE ++HAL_IO(rct) ++#else ++DIR_IO(rct) ++#endif ++#if SD_HAL_MODE ++HAL_IO(sd) ++#else ++DIR_IO(sd) ++#endif ++#if SF_HAL_MODE ++HAL_IO(sf) ++#else ++DIR_IO(sf) ++#endif ++#if SSI_HAL_MODE ++HAL_IO(ssi) ++#else ++DIR_IO(ssi) ++#endif ++#if TIMER_HAL_MODE ++HAL_IO(timer) ++#else ++DIR_IO(timer) ++#endif ++#if UART_HAL_MODE ++HAL_IO(uart) ++#else ++DIR_IO(uart) ++#endif ++#if USB_HAL_MODE ++HAL_IO(usb) ++#else ++DIR_IO(usb) ++#endif ++#if VOUT_HAL_MODE ++HAL_IO(vout) ++#else ++DIR_IO(vout) ++#endif ++#if WDT_HAL_MODE ++HAL_IO(wdt) ++#else ++DIR_IO(wdt) ++#endif ++#if EFUSE_HAL_MODE ++HAL_IO(efuse) ++#else ++DIR_IO(efuse) ++#endif ++#if USB_DMA_ADD_MODE ++unsigned int gk_dma_readl(unsigned int ptr) ++{ ++ return g_hw->dma_readl(ptr); ++} ++EXPORT_SYMBOL(gk_dma_readl); ++void gk_dma_writel(unsigned int ptr, unsigned int value) ++{ ++ g_hw->dma_writel(ptr,value); ++} ++EXPORT_SYMBOL(gk_dma_writel); ++#else ++DIR_IO(dma) ++#endif ++#if USB_DMA_ADD_MODE ++unsigned char (*gk_usb_readb)(unsigned int ptr, unsigned int offset); ++unsigned short (*gk_usb_readw)(unsigned int ptr, unsigned int offset); ++unsigned int (*gk_usb_readl)(unsigned int ptr, unsigned int offset); ++void (*gk_usb_writeb)(unsigned int ptr, unsigned int offset, unsigned char value); ++void (*gk_usb_writew)(unsigned int ptr, unsigned int offset, unsigned short value); ++void (*gk_usb_writel)(unsigned int ptr, unsigned int offset, unsigned int value); ++ ++#endif ++#if SPI_API_MODE ++unsigned char (*gk_spi_readb)(unsigned int ptr); ++unsigned short (*gk_spi_readw)(unsigned int ptr); ++unsigned int (*gk_spi_readl)(unsigned int ptr); ++void (*gk_spi_writeb)(unsigned int ptr, unsigned char value); ++void (*gk_spi_writew)(unsigned int ptr, unsigned short value); ++void (*gk_spi_writel)(unsigned int ptr, unsigned int value); ++#endif ++ ++static inline unsigned int gk_hal_init (void *hal_base_address, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) ++{ ++ unsigned int rval=0; ++ hal_function_t hal_init = (hal_function_t) (hal_base_address) ; ++ ++ g_hw = (struct hw_ops *)hal_init (arg0, arg1, arg2, arg3, arg4) ; ++ printk("hal version = %x \n", (u32)g_hw->get_version()); ++ ++#if USB_DMA_ADD_MODE ++ if((u32)g_hw->get_version() < 0x20151223) ++ { ++ printk("Error: hal version must up to 0x20151223!!!\n"); ++ } ++ gk_usb_readb = g_hw->usb_readb; ++ gk_usb_readw = g_hw->usb_readw; ++ gk_usb_readl = g_hw->usb_readl; ++ gk_usb_writeb = g_hw->usb_writeb; ++ gk_usb_writew = g_hw->usb_writew; ++ gk_usb_writel = g_hw->usb_writel; ++ ++#endif ++#if SPI_API_MODE ++ if((u32)g_hw->get_version() < 0x20160324) ++ { ++ printk("Error: hal version must up to 0x20160324!!!\n"); ++ } ++ gk_spi_readb = g_hw->spi_readb; ++ gk_spi_readw = g_hw->spi_readw; ++ gk_spi_readl = g_hw->spi_readl; ++ gk_spi_writeb = g_hw->spi_writeb; ++ gk_spi_writew = g_hw->spi_writew; ++ gk_spi_writel = g_hw->spi_writel; ++#endif ++ return rval ; ++} ++ ++ ++static int __init early_boot_splash_logo(char *p) ++{ ++ printk("set boot splash logo = 1 \n"); ++ gk_boot_splash_logo = 1; ++ return 0; ++} ++early_param("boot_splash_logo_on", early_boot_splash_logo); ++ ++void __init gk_map_io(void) ++{ ++ int i; ++ u32 iop, ios, iov, hal_add; ++ u32 usr_phy_addr; ++ u32 bsb_phy_addr; ++ u32 bsb_size; ++ u32 dsp_phy_addr; ++ u32 dsp_size; ++ u32 soc_type; //0:, 1:7102 ++ u32 mem_size; ++ u32 mem_total; ++ u32 usr_size; //user used, cmem module ++ struct memblock_region *reg; ++ unsigned long kernelMemoryGet=0; ++ ++ /*************************/ ++ /* AHB */ ++ /*-----------------------*/ ++ /* APB */ ++ /*-----------------------*/ ++ /* PPM <3M> */ ++ /*-----------------------*/ ++ /* KER */ ++ /*-----------------------*/ ++ /* BSB <2M/4M> */ ++ /*-----------------------*/ ++ /* DSP */ ++ /*-----------------------*/ ++ /* USR <64K> */ ++ /*************************/ ++ ++ for (i = 0; i < GK_IO_DESC_BSB_ID; i++) ++ { ++ iop = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ ios = gk_mem_desc[i].io_desc.length; ++ iov = gk_mem_desc[i].io_desc.virtual; ++ printk("%s: 0x%x 0x%x -- 0x%x\n", gk_mem_desc[i].name, iop, iov, ios); ++ if (ios > 0) ++ { ++ iotable_init(&(gk_mem_desc[i].io_desc), 1); ++ } ++ } ++ ++ /* calc mem_size by uboot params parsing*/ ++ for_each_memblock(memory, reg) ++ { ++ unsigned long pages = memblock_region_memory_end_pfn(reg) - ++ memblock_region_memory_base_pfn(reg); ++ kernelMemoryGet = pages >> (20 - PAGE_SHIFT); ++ } ++ mem_size = kernelMemoryGet*1024*1024; ++ ++#if 0 ++ soc_type = *(volatile u32 *)CONFIG_U2K_SOC_ADDR; ++ ++ /* if can't get correct value from uboot env, use GK7102 for default*/ ++ if(soc_type>1) ++ soc_type = 1; ++ ++ ++ ++ mem_total = *(volatile u32 *)CONFIG_U2K_TOTAL_MEM; ++ if(mem_total != 64 && mem_total != 128) ++ { ++ /* set mem_total and bsb size by chip ID*/ ++ switch(soc_type) ++ { ++ case CONFIG_SOC_GK7102: /*GK7102*/ ++ mem_total = 64*1024*1024; ++ //bsb_size = 0x200000; /*use 2M for GK7102*/ ++ break; ++ case CONFIG_SOC_GK7101: /*GK*/ ++ default: ++ mem_total = 128*1024*1024; ++ //bsb_size = 0x400000; /*use 4M for GK*/ ++ break; ++ } ++ } ++ else mem_total = mem_total*1024*1024; ++#else ++ mem_total = (*(volatile u32 *)CONFIG_U2K_TOTAL_MEM)*1024*1024; ++#endif ++ ++ bsb_size = *(volatile u32 *)CONFIG_U2K_BSB_ADDR; ++ usr_size = 0x10000; ++ usr_phy_addr = 0xC0000000 + mem_total - usr_size; ++ bsb_phy_addr = 0xC0000000 + get_ppm_size() + mem_size; ++ dsp_phy_addr = bsb_phy_addr + bsb_size; ++ dsp_size = mem_total - get_ppm_size() - mem_size - bsb_size - usr_size; ++ ++ gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.pfn = __phys_to_pfn(bsb_phy_addr); ++ gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.length = bsb_size; ++ ++ gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.pfn = __phys_to_pfn(dsp_phy_addr); ++ gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.length = dsp_size; ++ ++ gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.pfn = __phys_to_pfn(usr_phy_addr); ++ gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.length = usr_size; ++ ++ for (i = GK_IO_DESC_BSB_ID; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ iop = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ ios = gk_mem_desc[i].io_desc.length; ++ iov = gk_mem_desc[i].io_desc.virtual; ++ printk("%s: 0x%x 0x%x -- 0x%x\n", gk_mem_desc[i].name, iop, iov, ios); ++ if (ios > 0) ++ { ++ iotable_init(&(gk_mem_desc[i].io_desc), 1); ++ } ++ } ++ ++ hal_add = *(volatile u32 *)CONFIG_U2K_HAL_ADDR; ++ gk_hal_init((void*)(gk_phys_to_virt(hal_add)), get_hal1_virt(), get_hal2_virt(), get_ahb_virt(), get_apb_virt(), (u32)iotable_init); ++} ++ ++void gk_load_51mcu_code(u32 code) ++{ ++ int i; ++ u8 *pData = NULL; ++ ++ pData = load_data_init(); ++ ++ /* Software Reset */ ++ gk_mcu_setbitsl( MCU_SYS_BASE + 0x0000, 1 << 5); ++ ++ /* Enable the download command */ ++ gk_mcu_setbitsl( MCU_SYS_BASE + 0x002C, 1 << 4); ++ ++ /* Disable the MCU51 core clock */ ++ gk_mcu_clrbitsl( MCU_SYS_BASE + 0x002C, 1 << 1); ++ ++ /* Download MCU code to boot ram */ ++ for(i=0;i<4096;i++) ++ { ++ gk_mcu_writel((GK_VA_PMU_C51_CODE + (i*4)), pData[i]); ++ } ++ gk_mcu_writel(MCU_SYS_BASE + 0x005C, code); ++ gk_mcu_writel(MCU_SYS_BASE + 0x002C, 0xB2);// 1011 0010 ++ gk_mcu_writel(MCU_SYS_BASE + 0x002C, 0x63);// 0110 0011 ++} ++ ++void gk_power_off(void) ++{ ++ ++ u32 code = PMU_POWER_OFF_CPU; ++ /* Disable interrupts first */ ++ local_irq_disable(); ++ local_fiq_disable(); ++ printk("gk power off...\n"); ++ ++#ifdef CONFIG_PMU_AUTOMOTIVE ++ code = PMU_AUTOMOTIVE_KEY; ++#endif ++#ifdef CONFIG_PMU_POWER_OFF_CPU ++ code = PMU_POWER_OFF_CPU; ++#endif ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++ code = PMU_ALWAYS_RUNNING_POWEROFF; ++#endif ++ gk_load_51mcu_code(code); ++ ++ //printk("c51 start ... ...\n"); ++ while(1){;} ++} ++ ++ ++//reboot, user watch dog ++void gk_restart(char mode, const char *cmd) ++{ ++ printk("gk reboot...\n"); ++ ++ gk_wdt_writel( WDOG_RELOAD_REG, 0xff); ++ gk_wdt_writel( WDOG_RESTART_REG, 0x4755); ++ gk_wdt_writel( WDOG_CONTROL_REG, WDOG_CTR_RST_EN | WDOG_CTR_EN); ++ mdelay(1000); ++ printk("watchdog reset failed...\n"); ++} ++ ++ ++/* ==========================================================================*/ ++DEFINE_SPINLOCK(gk_reg_lock); ++unsigned long gk_reg_flags; ++u32 gk_reglock_count = 0; ++ ++/* ==========================================================================*/ ++EXPORT_SYMBOL(gk_reg_lock); ++EXPORT_SYMBOL(gk_reg_flags); ++EXPORT_SYMBOL(gk_reglock_count); ++module_param (gk_reglock_count, uint, S_IRUGO); ++ ++ +diff --git a/arch/arm/mach-gk710x/include/hal/hal.h b/arch/arm/mach-gk710x/include/hal/hal.h +new file mode 100644 +index 00000000..054e318c +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/hal/hal.h +@@ -0,0 +1,22 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/hal/hal.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_HAL_H ++#define __HAL_HAL_H ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710x/include/hal/header.h b/arch/arm/mach-gk710x/include/hal/header.h +new file mode 100644 +index 00000000..259c551b +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/hal/header.h +@@ -0,0 +1,20 @@ ++#ifndef _HEADER_H_INCLUDED_ ++#define _HEADER_H_INCLUDED_ ++ ++typedef struct gk_hal_header_s { ++ char magic[16] ; ++ unsigned int major_version ; ++ unsigned int minor_version ; ++ unsigned char chip_name[8] ; ++ unsigned char chip_stepping[8] ; ++ unsigned char build_id[32] ; ++ unsigned char build_date[32] ; ++} gk_hal_header_t; ++ ++typedef struct gk_hal_function_info_s { ++ unsigned int (*function)(unsigned int, unsigned int, ++ unsigned int, unsigned int) ; ++ const char* name ; ++} gk_hal_function_info_t ; ++ ++#endif // ifndef _HEADER_H_INCLUDED_ +diff --git a/arch/arm/mach-gk710x/include/mach/audio_codec.h b/arch/arm/mach-gk710x/include/mach/audio_codec.h +new file mode 100644 +index 00000000..53e527ba +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/audio_codec.h +@@ -0,0 +1,115 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/hal/audio_codec.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __HAL_AUDIO_CODEC_H__ ++#define __HAL_AUDIO_CODEC_H__ ++ ++#include ++ ++#define AUDIO_DMA_REG_OFFSET (0x30000000) ++ ++/*AHB genneral */ ++#define AHB_GREG_BASE (GK_VA_AHB_GREG) ++#define AHB_GREG_BASE_PHYS (GK_PA_AHB_GREG) ++#define AHB_GREG_REG(x) (AHB_GREG_BASE + (x)) ++#define AHB_GREG_REG_PHYS(x) (AHB_GREG_BASE_PHYS + (x)) ++ ++#define AHB_GREG_BASE_extern AHB_GREG_BASE ++ ++/*digital model*/ ++#define AUDIO_CODEC_DIGITAL_BASE (GK_VA_AUDIO_CODEC_DIGITAL) ++#define AUDIO_CODEC_DIGITAL_BASE_PHYS (GK_PA_AUDIO_CODEC_DIGITAL) ++#define AUDIO_CODEC_DIGITAL_REG(x) (AUDIO_CODEC_DIGITAL_BASE + (x)) ++#define AUDIO_CODEC_DIGITAL_REG_PHYS(x) (AUDIO_CODEC_DIGITAL_BASE_PHYS + (x)) ++ ++#define AUDIO_CODEC_DIGITAL_BASE_extern AUDIO_CODEC_DIGITAL_BASE ++ ++/*analog model*/ ++#define AUDIO_CODEC_ANALOG_BASE (GK_VA_AUDIO_CODEC_ANALOG) ++#define AUDIO_CODEC_ANALOG_BASE_PHYS (GK_PA_AUDIO_CODEC_ANALOG) ++#define AUDIO_CODEC_ANALOG_REG(x) (AUDIO_CODEC_ANALOG_BASE + (x)) ++#define AUDIO_CODEC_ANALOG_REG_PHYS(x) (AUDIO_CODEC_ANALOG_BASE_PHYS + (x)) ++ ++#define AUDIO_CODEC_ANALOG_BASE_extern AUDIO_CODEC_ANALOG_BASE ++ ++/*AHB genneral reg*/ ++#define AHB_GENNERNAL0_REG AHB_GREG_REG(0x00) ++#define AHB_GENNERNAL1_REG AHB_GREG_REG(0x04) ++ ++/*digital model reg */ ++#define AUDC_DIGITAL_SYS_RST_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x00) ++#define AUDC_DIGITAL_CKG_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x04) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL2_REG AUDIO_CODEC_DIGITAL_REG(0x18) ++#define AUDC_DIGITAL_TIMING_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x08) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x10) ++#define AUDC_DIGITAL_AUDIOBAND_STS_REG AUDIO_CODEC_DIGITAL_REG(0x1c) ++#define AUDC_DIGITAL_SDM_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x34) ++#define AUDC_DIGITAL_SDM_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x38) ++#define AUDC_DIGITAL_NF_SYNTH_1_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x3c) ++#define AUDC_DIGITAL_NF_SYNTH_1_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x40) ++#define AUDC_DIGITAL_NF_SYNTH_2_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x44) ++#define AUDC_DIGITAL_NF_SYNTH_2_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x48) ++#define AUDC_DIGITAL_DIG_MIC_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x4c) ++#define AUDC_DIGITAL_AUDIOBAND_STS2_REG AUDIO_CODEC_DIGITAL_REG(0x20) ++#define AUDC_DIGITAL_SDM_DWA_DATAIN_L_REG AUDIO_CODEC_DIGITAL_REG(0x54) ++#define AUDC_DIGITAL_SDM_DWA_DATAIN_R_REG AUDIO_CODEC_DIGITAL_REG(0x58) ++#define AUDC_DIGITAL_VALID_SIGNALS_REG AUDIO_CODEC_DIGITAL_REG(0x5c) ++#define AUDC_DIGITAL_PGA1_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x68) ++#define AUDC_DIGITAL_MMP1_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x60) ++#define AUDC_DIGITAL_MMP1_DPGA_CFG2_REG AUDIO_CODEC_DIGITAL_REG(0x64) ++#define AUDC_DIGITAL_MIX_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x50) ++ ++#define AUDC_DIGITAL_MMP2_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x6c) ++#define AUDC_DIGITAL_MMP2_DPGA_CFG2_REG AUDIO_CODEC_DIGITAL_REG(0x70) ++#define AUDC_DIGITAL_INT1_DOUT_REG AUDIO_CODEC_DIGITAL_REG(0x74) ++#define AUDC_DIGITAL_FIFO_TH_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x7c) ++#define AUDC_DIGITAL_INT2_DOUT_REG AUDIO_CODEC_DIGITAL_REG(0x78) ++ ++#define AUDC_DIGITAL_TIMING_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x0c) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x14) ++#define AUDC_DIGITAL_FIFO_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x80) ++#define AUDC_DIGITAL_FIFO_STS_REG AUDIO_CODEC_DIGITAL_REG(0x84) ++#define AUDC_DIGITAL_NF_SYNTH_5_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x88) ++#define AUDC_DIGITAL_NF_SYNTH_5_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x8c) ++#define AUDC_DIGITAL_INT_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x90) ++ ++#define AUDC_DIGITAL_SINE_GEN_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x24) ++#define AUDC_DIGITAL_SINE_GEN_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x28) ++#define AUDC_DIGITAL_TEST_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x30) ++ ++/*analog model reg */ ++#define AUDC_ANALOG_CTRL00_REG AUDIO_CODEC_ANALOG_REG(0x00) ++#define AUDC_ANALOG_CTRL01_REG AUDIO_CODEC_ANALOG_REG(0x04) ++#define AUDC_ANALOG_CTRL02_REG AUDIO_CODEC_ANALOG_REG(0x08) ++#define AUDC_ANALOG_CTRL03_REG AUDIO_CODEC_ANALOG_REG(0x0c) ++#define AUDC_ANALOG_CTRL04_REG AUDIO_CODEC_ANALOG_REG(0x10) ++#define AUDC_ANALOG_CTRL05_REG AUDIO_CODEC_ANALOG_REG(0x14) ++#define AUDC_ANALOG_CTRL06_REG AUDIO_CODEC_ANALOG_REG(0x18) ++#define AUDC_ANALOG_CTRL07_REG AUDIO_CODEC_ANALOG_REG(0x1c) ++#define AUDC_ANALOG_CTRL08_REG AUDIO_CODEC_ANALOG_REG(0x20) ++#define AUDC_ANALOG_CTRL09_REG AUDIO_CODEC_ANALOG_REG(0x24) ++#define AUDC_ANALOG_CTRL10_REG AUDIO_CODEC_ANALOG_REG(0x28) ++#define AUDC_ANALOG_CTRL11_REG AUDIO_CODEC_ANALOG_REG(0x2c) ++#define AUDC_ANALOG_CTRL12_REG AUDIO_CODEC_ANALOG_REG(0x30) ++#define AUDC_ANALOG_CTRL13_REG AUDIO_CODEC_ANALOG_REG(0x34) ++#define AUDC_ANALOG_CTRL14_REG AUDIO_CODEC_ANALOG_REG(0x38) ++#define AUDC_ANALOG_CTRL15_REG AUDIO_CODEC_ANALOG_REG(0x3c) ++#define AUDC_ANALOG_CTRL16_REG AUDIO_CODEC_ANALOG_REG(0x40) ++#define AUDC_ANALOG_CTRL17_REG AUDIO_CODEC_ANALOG_REG(0x44) ++#define AUDC_ANALOG_CTRL18_REG AUDIO_CODEC_ANALOG_REG(0x48) ++ ++extern unsigned int gk_aud_get_dma_offset(void); ++#endif /* __HAL_AUDIO_CODEC_H__ */ +diff --git a/arch/arm/mach-gk710x/include/mach/crypto.h b/arch/arm/mach-gk710x/include/mach/crypto.h +new file mode 100644 +index 00000000..1b58d898 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/crypto.h +@@ -0,0 +1,48 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/hal/i2s.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_CRYPTO_H__ ++#define __HAL_CRYPTO_H__ ++ ++#include ++ ++#define CRYPTO_VA_BASE GK_VA_CRYPT_UNIT ++#define CRYPTO_VA_REG(x) (CRYPTO_VA_BASE + (x)) ++#define REG_CRYPTO_DES_KEY CRYPTO_VA_REG(0x00c) /* read/write */ ++#define REG_CRYPTO_DES_INPUT CRYPTO_VA_REG(0x014) /* read/write */ ++#define REG_CRYPTO_DES_OPCODE CRYPTO_VA_REG(0x004) /* read/write */ ++#define REG_CRYPTO_DES_OUTPUT_RDY CRYPTO_VA_REG(0x018) /* read */ ++#define REG_CRYPTO_DES_OUTPUT CRYPTO_VA_REG(0x020) /* read */ ++#define REG_CRYPTO_DES_INTERRUPT CRYPTO_VA_REG(0x000) /* read/write */ ++ ++#define REG_CRYPTO_AES_128_KEY CRYPTO_VA_REG(0x074) /* read/write */ ++ ++#define REG_CRYPTO_AES_192_KEY CRYPTO_VA_REG(0x064) /* read/write */ ++ ++#define REG_CRYPTO_AES_256_KEY CRYPTO_VA_REG(0x04c) /* read/write */ ++ ++#define REG_CRYPTO_AES_INPUT CRYPTO_VA_REG(0x084) /* read/write */ ++#define REG_CRYPTO_AES_OPCODE CRYPTO_VA_REG(0x02C) /* read/write */ ++#define REG_CRYPTO_AES_OUTPUT_RDY CRYPTO_VA_REG(0x088) /* read */ ++ ++#define REG_CRYPTO_AES_OUTPUT CRYPTO_VA_REG(0x098) /* read */ ++#define REG_CRYPTO_AES_INTERRUPT CRYPTO_VA_REG(0x028) /* read/write */ ++#define REG_CRYPTO_EFUSE_BOOT_SW_DIS CRYPTO_VA_REG(0x024) /* read/write */ ++ ++ ++ ++#endif /* __HAL_CRYPTO_H__ */ +\ No newline at end of file +diff --git a/arch/arm/mach-gk710x/include/mach/debug-macro.S b/arch/arm/mach-gk710x/include/mach/debug-macro.S +new file mode 100644 +index 00000000..4f799674 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/debug-macro.S +@@ -0,0 +1,65 @@ ++/* ++ * arch/arm/mach-gk710x/include/mach/debug-macro.S ++ * ++ * History: ++ * 2014/06/18 - [Kewell Liu] created file ++ * ++ * Copyright (C) 2002-2014, Goke Microelectronics China. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++ ++#ifdef CONFIG_MMU ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =GK_PA_APB_BASE @ Physical Base ++ ldr \rv, =GK_VA_APB_BASE @ Virtual Base ++ .endm ++ ++#else /* !CONFIG_MMU */ ++ ++ .macro addruart, rx, tmp ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 @ MMU enabled ++ moveq \rx, #GK_PA_APB_BASE @ physical base address ++ movne \rx, #GK_VA_APB_BASE @ virtual address ++ orr \rx, \rx, #UART_OFFSET ++ .endm ++ ++#endif /* CONFIG_MMU */ ++ ++.macro senduart, rd, rx ++ str \rd, [\rx, #UART_TH_OFFSET] ++.endm ++ ++.macro waituart, rd, rx ++1001: ++ ldr \rd, [\rx, #UART_LS_OFFSET] ++ tst \rd, #UART_LS_TEMT ++ beq 1001b ++ ++.endm ++ ++.macro busyuart, rd, rx ++1002: ++ ldr \rd, [\rx, #UART_LS_OFFSET] ++ tst \rd, #UART_LS_TEMT ++ beq 1002b ++.endm ++ +diff --git a/arch/arm/mach-gk710x/include/mach/dma.h b/arch/arm/mach-gk710x/include/mach/dma.h +new file mode 100644 +index 00000000..6f9b4440 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/dma.h +@@ -0,0 +1,170 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/hal/dma.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_DMA_H__ ++#define __HAL_DMA_H__ ++#include ++ ++ ++#define DMA_BASE (GK_VA_DMAC) ++#define DMA_REG(x) (DMA_BASE + (x)) ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define DMA_SUPPORT_DMA_FIOS 0 /* DMA_FIOS */ ++ ++/****************************/ ++/* DMA Channel Assignments */ ++/****************************/ ++ ++#if (DMA_SUPPORT_DMA_FIOS == 0) ++/* DMA instance channel */ ++#define FIO_DMA_CHAN 0 ++#define I2S_RX_DMA_CHAN 1 ++#define I2S_TX_DMA_CHAN 2 ++#define HOST_RX_DMA_CHAN 3 ++#define HOST_TX_DMA_CHAN 4 ++#endif ++ ++#define MS_DMA_CHAN 3 ++/* No AHB MS controller */ ++ ++/* Max number of channel */ ++#define NUM_DMA_FIOS_CHANNELS DMA_SUPPORT_DMA_FIOS ++ ++#define NUM_DMA_CHANNELS 4 ++ ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++#define DMA_CHAN_TX 3 ++#define DMA_CHAN_RX 3 ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++#define DMA_CHAN_TX 0 ++#define DMA_CHAN_RX 3 ++#endif ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define DMA_CHAN_CTR_REG(x) DMA_REG((0x300 + ((x) << 4))) ++#define DMA_CHAN_SRC_REG(x) DMA_REG((0x304 + ((x) << 4))) ++#define DMA_CHAN_DST_REG(x) DMA_REG((0x308 + ((x) << 4))) ++#define DMA_CHAN_STA_REG(x) DMA_REG((0x30C + ((x) << 4))) ++#define DMA_CHAN_DA_REG(x) DMA_REG((0x380 + ((x) << 2))) ++#define DMA_INT_REG DMA_REG(0x3F0) ++ ++/* DMA_CHANX_CTR_REG */ ++#define DMA_CHANX_CTR_EN 0x80000000 ++#define DMA_CHANX_CTR_D 0x40000000 ++#define DMA_CHANX_CTR_WM 0x20000000 ++#define DMA_CHANX_CTR_RM 0x10000000 ++#define DMA_CHANX_CTR_NI 0x08000000 ++#define DMA_CHANX_CTR_BLK_1024B 0x07000000 ++#define DMA_CHANX_CTR_BLK_512B 0x06000000 ++#define DMA_CHANX_CTR_BLK_256B 0x05000000 ++#define DMA_CHANX_CTR_BLK_128B 0x04000000 ++#define DMA_CHANX_CTR_BLK_64B 0x03000000 ++#define DMA_CHANX_CTR_BLK_32B 0x02000000 ++#define DMA_CHANX_CTR_BLK_16B 0x01000000 ++#define DMA_CHANX_CTR_BLK_8B 0x00000000 ++#define DMA_CHANX_CTR_TS_8B 0x00C00000 ++#define DMA_CHANX_CTR_TS_4B 0x00800000 ++#define DMA_CHANX_CTR_TS_2B 0x00400000 ++#define DMA_CHANX_CTR_TS_1B 0x00000000 ++ ++/* DMA descriptor bit fields */ ++#define DMA_DESC_EOC 0x01000000 ++#define DMA_DESC_WM 0x00800000 ++#define DMA_DESC_RM 0x00400000 ++#define DMA_DESC_NI 0x00200000 ++#define DMA_DESC_TS_8B 0x00180000 ++#define DMA_DESC_TS_4B 0x00100000 ++#define DMA_DESC_TS_2B 0x00080000 ++#define DMA_DESC_TS_1B 0x00000000 ++#define DMA_DESC_BLK_1024B 0x00070000 ++#define DMA_DESC_BLK_512B 0x00060000 ++#define DMA_DESC_BLK_256B 0x00050000 ++#define DMA_DESC_BLK_128B 0x00040000 ++#define DMA_DESC_BLK_64B 0x00030000 ++#define DMA_DESC_BLK_32B 0x00020000 ++#define DMA_DESC_BLK_16B 0x00010000 ++#define DMA_DESC_BLK_8B 0x00000000 ++#define DMA_DESC_ID 0x00000004 ++#define DMA_DESC_IE 0x00000002 ++#define DMA_DESC_ST 0x00000001 ++ ++/* DMA_CHANX_STA_REG */ ++#define DMA_CHANX_STA_DM 0x80000000 ++#define DMA_CHANX_STA_OE 0x40000000 ++#define DMA_CHANX_STA_DA 0x20000000 ++#define DMA_CHANX_STA_DD 0x10000000 ++#define DMA_CHANX_STA_OD 0x08000000 ++#define DMA_CHANX_STA_ME 0x04000000 ++#define DMA_CHANX_STA_BE 0x02000000 ++#define DMA_CHANX_STA_RWE 0x01000000 ++#define DMA_CHANX_STA_AE 0x00800000 ++#define DMA_CHANX_STA_DN 0x00400000 ++ ++/* DMA_INT_REG */ ++#define DMA_INT_CHAN(x) (0x1 << (x)) ++ ++#if defined(__FPGA__) ++#define DMA_INT_CHAN7 0x00000080 ++#define DMA_INT_CHAN6 0x00000040 ++#define DMA_INT_CHAN5 0x00000020 ++#endif ++ ++#define DMA_INT_CHAN4 0x00000010 ++#define DMA_INT_CHAN3 0x00000008 ++#define DMA_INT_CHAN2 0x00000004 ++#define DMA_INT_CHAN1 0x00000002 ++#define DMA_INT_CHAN0 0x00000001 ++ ++ ++/*********************************/ ++/* FIO/DMA Burst Setup */ ++/* - descriptor, non-descriptor */ ++/* - main, spare */ ++/*********************************/ ++ ++#if defined(__FPGA__) ++ ++#define DMA_NODC_MN_BURST_SIZE (DMA_CHANX_CTR_BLK_32B | DMA_CHANX_CTR_TS_4B) ++#define DMA_NODC_SP_BURST_SIZE (DMA_CHANX_CTR_BLK_32B | DMA_CHANX_CTR_TS_4B) ++#define DMA_DESC_MN_BURST_SIZE (DMA_DESC_BLK_32B | DMA_DESC_TS_4B) ++#define DMA_DESC_SP_BURST_SIZE (DMA_DESC_BLK_32B | DMA_DESC_TS_4B) ++#define FIO_MN_BURST_SIZE (FIO_DMACTR_BLK_32B | FIO_DMACTR_TS4B) ++#define FIO_SP_BURST_SIZE (FIO_DMACTR_BLK_32B | FIO_DMACTR_TS4B) ++ ++#else ++ ++#if (DMA_SUPPORT_DMA_FIOS == 0) ++#define DMA_NODC_MN_BURST_SIZE (DMA_CHANX_CTR_BLK_512B | DMA_CHANX_CTR_TS_4B) ++#define DMA_NODC_SP_BURST_SIZE (DMA_CHANX_CTR_BLK_512B | DMA_CHANX_CTR_TS_4B) ++#define DMA_DESC_MN_BURST_SIZE (DMA_DESC_BLK_512B | DMA_DESC_TS_4B) ++#define DMA_DESC_SP_BURST_SIZE (DMA_DESC_BLK_512B | DMA_DESC_TS_4B) ++#define FIO_MN_BURST_SIZE (FIO_DMACTR_BLK_512B | FIO_DMACTR_TS4B) ++#define FIO_SP_BURST_SIZE (FIO_DMACTR_BLK_512B | FIO_DMACTR_TS4B) ++#else ++ ++#endif ++ ++#endif ++ ++#endif /* __HAL_DMA_H__ */ +diff --git a/arch/arm/mach-gk710x/include/mach/entry-macro.S b/arch/arm/mach-gk710x/include/mach/entry-macro.S +new file mode 100644 +index 00000000..009fdae1 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/entry-macro.S +@@ -0,0 +1,59 @@ ++/* ++ * arch/arm/mach-gk710x/include/mach/entry-macro.S ++ * ++ * History: ++ * 2014/06/18 - [Kewell Liu] created file ++ * ++ * Copyright (C) 2002-2014, Goke Microelectronics China. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .macro stat2nr, stat, nr, tmp ++ rsbs \tmp, \stat, #0 ++ and \nr, \tmp, \stat ++ clzcc \nr, \nr ++ rsc \nr, \nr, #32 ++ teq \nr, #32 ++ .endm ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ldr \base, =(VIC1_BASE) ++ ldr \irqstat, [\base, #VIC_IRQ_STA_OFFSET] ++ stat2nr \irqstat, \irqnr, \tmp ++#if (VIC_INSTANCES >= 2) ++ bne 1000f ++ ldr \base, =(VIC2_BASE) ++ ldr \irqstat, [\base, #VIC_IRQ_STA_OFFSET] ++ stat2nr \irqstat, \irqnr, \tmp ++ addne \irqnr, \irqnr, #VIC2_INT_VEC(0) ++#endif ++1000: ++ .endm ++ +diff --git a/arch/arm/mach-gk710x/include/mach/eth.h b/arch/arm/mach-gk710x/include/mach/eth.h +new file mode 100644 +index 00000000..b9115887 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/eth.h +@@ -0,0 +1,466 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/eth.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __MACH_ETH_H__ ++#define __MACH_ETH_H__ ++ ++#include ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define ETH_INSTANCES 1 ++ ++#define SUPPORT_GMII 0 // 10/100 bits phy ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define ETH_REG(x) (GK_VA_ETH_GMAC + (x)) ++ ++#define ETH_MAC_CFG_REG ETH_REG(0x0000) ++ ++#define ETH_MAC_GMII_ADDR_REG ETH_REG(0x0004) ++#define ETH_MAC_GMII_DATA_REG ETH_REG(0x0008) ++ ++#define ETH_MAC_FRAME_FILTER_REG ETH_REG(0x000c) ++#define ETH_MAC_HASH_HI_REG ETH_REG(0x0010) ++#define ETH_MAC_HASH_LO_REG ETH_REG(0x0014) ++#define ETH_MAC_FLOW_CTR_REG ETH_REG(0x0018) ++#define ETH_MAC_VLAN_TAG_REG ETH_REG(0x001c) ++#define ETH_MAC_VERSION_REG ETH_REG(0x0058) ++ ++#define ETH_MAC_MAC0_HI_REG ETH_REG(0x0040) ++#define ETH_MAC_MAC0_LO_REG ETH_REG(0x0044) ++#define ETH_MAC_MAC1_HI_REG ETH_REG(0x0048) ++#define ETH_MAC_MAC1_LO_REG ETH_REG(0x004c) ++#define ETH_MAC_MAC2_HI_REG ETH_REG(0x0050) ++#define ETH_MAC_MAC2_LO_REG ETH_REG(0x0054) ++ ++ ++#define ETH_DMA_TX_POLL_DMD_REG ETH_REG(0x1000) ++#define ETH_DMA_RX_POLL_DMD_REG ETH_REG(0x1004) ++#define ETH_DMA_BUS_MODE_REG ETH_REG(0x1008) ++#define ETH_DMA_RX_DESC_LIST_REG ETH_REG(0x100c) ++#define ETH_DMA_TX_DESC_LIST_REG ETH_REG(0x1010) ++#define ETH_DMA_STATUS_REG ETH_REG(0x1014) ++#define ETH_DMA_MISS_FRAME_BOCNT_REG ETH_REG(0x1018) ++ ++#define ETH_DMA_INTEN_REG ETH_REG(0x101c) ++#define ETH_DMA_OPMODE_REG ETH_REG(0x1020) ++ ++#define ETH_DMA_HOST_TX_DESC_REG ETH_REG(0x1048) ++#define ETH_DMA_HOST_RX_DESC_REG ETH_REG(0x104c) ++#define ETH_DMA_HOST_TX_BUF_REG ETH_REG(0x1040) ++#define ETH_DMA_HOST_RX_BUF_REG ETH_REG(0x1044) ++ ++ ++//------------------------------------------- ++#define ETH_MAC_CFG_OFFSET (0x0000) ++#define ETH_MAC_FRAME_FILTER_OFFSET (0x000c) ++#define ETH_MAC_HASH_HI_OFFSET (0x0010) ++#define ETH_MAC_HASH_LO_OFFSET (0x0014) ++#define ETH_MAC_GMII_ADDR_OFFSET (0x0004) ++#define ETH_MAC_GMII_DATA_OFFSET (0x0008) ++#define ETH_MAC_FLOW_CTR_OFFSET (0x0018) ++#define ETH_MAC_VLAN_TAG_OFFSET (0x001c) ++#define ETH_MAC_VERSION_OFFSET (0x0058) ++#define ETH_MAC_MAC0_HI_OFFSET (0x0040) ++#define ETH_MAC_MAC0_LO_OFFSET (0x0044) ++#define ETH_MAC_MAC1_HI_OFFSET (0x0048) ++#define ETH_MAC_MAC1_LO_OFFSET (0x004c) ++#define ETH_MAC_MAC2_HI_OFFSET (0x0050) ++#define ETH_MAC_MAC2_LO_OFFSET (0x0054) ++ ++#define ETH_DMA_BUS_MODE_OFFSET (0x1008) ++#define ETH_DMA_TX_POLL_DMD_OFFSET (0x1000) ++#define ETH_DMA_RX_POLL_DMD_OFFSET (0x1004) ++#define ETH_DMA_RX_DESC_LIST_OFFSET (0x100c) ++#define ETH_DMA_TX_DESC_LIST_OFFSET (0x1010) ++#define ETH_DMA_STATUS_OFFSET (0x1014) ++#define ETH_DMA_OPMODE_OFFSET (0x1020) ++#define ETH_DMA_INTEN_OFFSET (0x101c) ++#define ETH_DMA_MISS_FRAME_BOCNT_OFFSET (0x1018) ++#define ETH_DMA_HOST_TX_DESC_OFFSET (0x1048) ++#define ETH_DMA_HOST_RX_DESC_OFFSET (0x104c) ++#define ETH_DMA_HOST_TX_BUF_OFFSET (0x1040) ++#define ETH_DMA_HOST_RX_BUF_OFFSET (0x1044) ++ ++/* ETH_MAC_CFG_REG */ ++#define ETH_MAC_CFG_WD 0x00800000 ++#define ETH_MAC_CFG_JD 0x00400000 ++#define ETH_MAC_CFG_BE 0x00200000 ++#define ETH_MAC_CFG_JE 0x00100000 ++#define ETH_MAC_CFG_IFG_96 0x000e0000 ++#define ETH_MAC_CFG_IFG_88 0x000c0000 ++#define ETH_MAC_CFG_IFG_80 0x000a0000 ++#define ETH_MAC_CFG_IFG_72 0x00080000 ++#define ETH_MAC_CFG_IFG_64 0x00060000 ++#define ETH_MAC_CFG_IFG_56 0x00040000 ++#define ETH_MAC_CFG_IFG_48 0x00020000 ++#define ETH_MAC_CFG_IFG_40 0x00000000 ++#define ETH_MAC_CFG_DCRS 0x00010000 ++#define ETH_MAC_CFG_PS 0x00008000 ++#define ETH_MAC_CFG_FES 0x00004000 ++#define ETH_MAC_CFG_DO 0x00002000 ++#define ETH_MAC_CFG_LM 0x00001000 ++#define ETH_MAC_CFG_DM 0x00000800 ++#define ETH_MAC_CFG_IPC 0x00000400 ++#define ETH_MAC_CFG_DR 0x00000200 ++#define ETH_MAC_CFG_LUD 0x00000100 ++#define ETH_MAC_CFG_ACS 0x00000080 ++#define ETH_MAC_CFG_BL_1 0x00000060 ++#define ETH_MAC_CFG_BL_4 0x00000040 ++#define ETH_MAC_CFG_BL_8 0x00000020 ++#define ETH_MAC_CFG_BL_10 0x00000000 ++#define ETH_MAC_CFG_DC 0x00000010 ++#define ETH_MAC_CFG_TE 0x00000008 /* Transmitter Enable */ ++#define ETH_MAC_CFG_RE 0x00000004 /* Receiver Enable */ ++ ++/* ETH_MAC_FRAME_FILTER_REG */ ++#define ETH_MAC_FRAME_FILTER_RA 0x80000000 ++#define ETH_MAC_FRAME_FILTER_SAF 0x00000200 ++#define ETH_MAC_FRAME_FILTER_SAIF 0x00000100 ++#define ETH_MAC_FRAME_FILTER_PCF_PASS 0x000000c0 ++#define ETH_MAC_FRAME_FILTER_PCF_FAIL 0x00000040 ++#define ETH_MAC_FRAME_FILTER_PCF_ALL 0x00000000 ++#define ETH_MAC_FRAME_FILTER_DBF 0x00000020 ++#define ETH_MAC_FRAME_FILTER_PM 0x00000010 ++#define ETH_MAC_FRAME_FILTER_DAIF 0x00000008 ++#define ETH_MAC_FRAME_FILTER_HMC 0x00000004 ++#define ETH_MAC_FRAME_FILTER_HUC 0x00000002 ++#define ETH_MAC_FRAME_FILTER_PR 0x00000001 ++ ++/* ETH_MAC_GMII_ADDR_REG */ ++#define ETH_MAC_GMII_ADDR_PA(x) (((x) & 0x1f) << 11) ++#define ETH_MAC_GMII_ADDR_GR(x) (((x) & 0x1f) << 6) ++#define ETH_MAC_GMII_ADDR_CR_250_300MHZ 0x00000014 ++#define ETH_MAC_GMII_ADDR_CR_150_250MHZ 0x00000010 ++#define ETH_MAC_GMII_ADDR_CR_35_60MHZ 0x0000000c ++#define ETH_MAC_GMII_ADDR_CR_20_35MHZ 0x00000008 ++#define ETH_MAC_GMII_ADDR_CR_100_150MHZ 0x00000004 ++#define ETH_MAC_GMII_ADDR_CR_60_100MHZ 0x00000000 ++#define ETH_MAC_GMII_ADDR_GW 0x00000002 ++#define ETH_MAC_GMII_ADDR_GB 0x00000001 ++ ++/* ETH_MAC_FLOW_CTR_REG */ ++#define ETH_MAC_FLOW_CTR_PT(x) (((x) & 0xffff) << 16) ++#define ETH_MAC_FLOW_CTR_PLT_256 0x00000030 ++#define ETH_MAC_FLOW_CTR_PLT_144 0x00000020 ++#define ETH_MAC_FLOW_CTR_PLT_28 0x00000010 ++#define ETH_MAC_FLOW_CTR_PLT_4 0x00000000 ++#define ETH_MAC_FLOW_CTR_UP 0x00000008 ++#define ETH_MAC_FLOW_CTR_RFE 0x00000004 ++#define ETH_MAC_FLOW_CTR_TFE 0x00000002 ++#define ETH_MAC_FLOW_CTR_FCBBPA 0x00000001 ++ ++/* ETH_MAC_VERSION_REG */ ++#define ETH_MAC_VERSION_USER(v) (((x) & 0x0000ff00) >> 8) ++#define ETH_MAC_VERSION_SYN(v) ((x) & 0x000000ff) ++ ++/* ETH_DMA_BUS_MODE_REG */ ++#define ETH_DMA_BUS_MODE_FB 0x00010000 ++#define ETH_DMA_BUS_MODE_PR4 0x0000c000 ++#define ETH_DMA_BUS_MODE_PR3 0x00008000 ++#define ETH_DMA_BUS_MODE_PR2 0x00004000 ++#define ETH_DMA_BUS_MODE_PR1 0x00000000 ++#define ETH_DMA_BUS_MODE_PBL_32 0x00002000 ++#define ETH_DMA_BUS_MODE_PBL_16 0x00001000 ++#define ETH_DMA_BUS_MODE_PBL_8 0x00000800 ++#define ETH_DMA_BUS_MODE_PBL_4 0x00000400 ++#define ETH_DMA_BUS_MODE_PBL_2 0x00000200 ++#define ETH_DMA_BUS_MODE_PBL_1 0x00000100 ++#define ETH_DMA_BUS_MODE_DSL(len) ((len & 0x1f) << 2) ++#define ETH_DMA_BUS_MODE_DA_RX 0x00000002 ++#define ETH_DMA_BUS_MODE_DA_TX 0x00000000 ++#define ETH_DMA_BUS_MODE_SWR 0x00000001 ++ ++/* ETH_DMA_STATUS_REG */ ++#define ETH_DMA_STATUS_GPI 0x10000000 ++#define ETH_DMA_STATUS_GMI 0x08000000 ++#define ETH_DMA_STATUS_GLI 0x04000000 ++#define ETH_DMA_STATUS_EB_MASK 0x03800000 ++#define ETH_DMA_STATUS_EB_TXDMA 0x02000000 ++#define ETH_DMA_STATUS_EB_RXDMA 0x00000000 ++#define ETH_DMA_STATUS_EB_RXFER 0x01000000 ++#define ETH_DMA_STATUS_EB_TXFER 0x00000000 ++#define ETH_DMA_STATUS_EB_DESC 0x00800000 ++#define ETH_DMA_STATUS_EB_DBUF 0x00000000 ++#define ETH_DMA_STATUS_TS_MASK 0x00700000 ++#define ETH_DMA_STATUS_TS_CTD 0x00700000 ++#define ETH_DMA_STATUS_TS_SUSP 0x00600000 ++#define ETH_DMA_STATUS_TS_READ 0x00300000 ++#define ETH_DMA_STATUS_TS_WAIT 0x00200000 ++#define ETH_DMA_STATUS_TS_FETCH 0x00100000 ++#define ETH_DMA_STATUS_TS_STOP 0x00000000 ++#define ETH_DMA_STATUS_RS_MASK 0x000e0000 ++#define ETH_DMA_STATUS_RS_RCV 0x000e0000 ++#define ETH_DMA_STATUS_RS_CRD 0x000a0000 ++#define ETH_DMA_STATUS_RS_SUSP 0x00080000 ++#define ETH_DMA_STATUS_RS_WAIT 0x00060000 ++#define ETH_DMA_STATUS_RS_FETCH 0x00020000 ++#define ETH_DMA_STATUS_RS_STOP 0x00000000 ++#define ETH_DMA_STATUS_NIS 0x00010000 ++#define ETH_DMA_STATUS_AIS 0x00008000 ++#define ETH_DMA_STATUS_ERI 0x00004000 ++#define ETH_DMA_STATUS_FBI 0x00002000 ++#define ETH_DMA_STATUS_ETI 0x00000400 ++#define ETH_DMA_STATUS_RWT 0x00000200 ++#define ETH_DMA_STATUS_RPS 0x00000100 ++#define ETH_DMA_STATUS_RU 0x00000080 ++#define ETH_DMA_STATUS_RI 0x00000040 ++#define ETH_DMA_STATUS_UNF 0x00000020 ++#define ETH_DMA_STATUS_OVF 0x00000010 ++#define ETH_DMA_STATUS_TJT 0x00000008 ++#define ETH_DMA_STATUS_TU 0x00000004 ++#define ETH_DMA_STATUS_TPS 0x00000002 ++#define ETH_DMA_STATUS_TI 0x00000001 ++ ++/* ETH_DMA_OPMODE_REG */ ++#define ETH_DMA_OPMODE_DT 0x04000000 ++#define ETH_DMA_OPMODE_RSF 0x02000000 ++#define ETH_DMA_OPMODE_DFF 0x01000000 ++#define ETH_DMA_OPMODE_TSF 0x00200000 ++#define ETH_DMA_OPMODE_FTF 0x00100000 ++#define ETH_DMA_OPMODE_TTC_16 0x0001c000 ++#define ETH_DMA_OPMODE_TTC_24 0x00018000 ++#define ETH_DMA_OPMODE_TTC_32 0x00014000 ++#define ETH_DMA_OPMODE_TTC_40 0x00010000 ++#define ETH_DMA_OPMODE_TTC_256 0x0000c000 ++#define ETH_DMA_OPMODE_TTC_192 0x00008000 ++#define ETH_DMA_OPMODE_TTC_128 0x00004000 ++#define ETH_DMA_OPMODE_TTC_64 0x00000000 ++#define ETH_DMA_OPMODE_ST 0x00002000 ++#define ETH_DMA_OPMODE_RFD_4K 0x00001800 ++#define ETH_DMA_OPMODE_RFD_3K 0x00001000 ++#define ETH_DMA_OPMODE_RFD_2K 0x00000800 ++#define ETH_DMA_OPMODE_RFD_1K 0x00000000 ++#define ETH_DMA_OPMODE_RFA_4K 0x00000600 ++#define ETH_DMA_OPMODE_RFA_3K 0x00000400 ++#define ETH_DMA_OPMODE_RFA_2K 0x00000200 ++#define ETH_DMA_OPMODE_RFA_1K 0x00000000 ++#define ETH_DMA_OPMODE_EFC 0x00000100 ++#define ETH_DMA_OPMODE_FEF 0x00000080 ++#define ETH_DMA_OPMODE_FUF 0x00000040 ++#define ETH_DMA_OPMODE_RTC_128 0x00000018 ++#define ETH_DMA_OPMODE_RTC_96 0x00000010 ++#define ETH_DMA_OPMODE_RTC_32 0x00000008 ++#define ETH_DMA_OPMODE_RTC_64 0x00000000 ++#define ETH_DMA_OPMODE_OSF 0x00000004 ++#define ETH_DMA_OPMODE_SR 0x00000002 ++ ++/* ETH_DMA_INTEN_REG */ ++#define ETH_DMA_INTEN_NIE 0x00010000 ++#define ETH_DMA_INTEN_AIE 0x00008000 ++#define ETH_DMA_INTEN_ERE 0x00004000 ++#define ETH_DMA_INTEN_FBE 0x00002000 ++#define ETH_DMA_INTEN_ETE 0x00000400 ++#define ETH_DMA_INTEN_RWE 0x00000200 ++#define ETH_DMA_INTEN_RSE 0x00000100 ++#define ETH_DMA_INTEN_RUE 0x00000080 ++#define ETH_DMA_INTEN_RIE 0x00000040 ++#define ETH_DMA_INTEN_UNE 0x00000020 ++#define ETH_DMA_INTEN_OVE 0x00000010 ++#define ETH_DMA_INTEN_TJE 0x00000008 ++#define ETH_DMA_INTEN_TUE 0x00000004 ++#define ETH_DMA_INTEN_TSE 0x00000002 ++#define ETH_DMA_INTEN_TIE 0x00000001 ++ ++/* ETH_DMA_MISS_FRAME_BOCNT_REG */ ++#define ETH_DMA_MISS_FRAME_BOCNT_FIFO 0x10000000 ++#define ETH_DMA_MISS_FRAME_BOCNT_APP(v) (((v) & 0x0ffe0000) >> 17) ++#define ETH_DMA_MISS_FRAME_BOCNT_FRAME 0x00001000 ++#define ETH_DMA_MISS_FRAME_BOCNT_HOST(v) ((v) & 0x0000ffff) ++ ++/* Receive Descriptor 0 (RDES0) */ ++#define ETH_RDES0_OWN 0x80000000 ++#define ETH_RDES0_AFM 0x40000000 ++#define ETH_RDES0_FL(v) (((v) & 0x3fff0000) >> 16) ++#define ETH_RDES0_ES 0x00008000 ++#define ETH_RDES0_DE 0x00004000 ++#define ETH_RDES0_SAF 0x00002000 ++#define ETH_RDES0_LE 0x00001000 ++#define ETH_RDES0_OE 0x00000800 ++#define ETH_RDES0_VLAN 0x00000400 ++#define ETH_RDES0_FS 0x00000200 ++#define ETH_RDES0_LS 0x00000100 ++#define ETH_RDES0_IPC 0x00000080 ++#define ETH_RDES0_LC 0x00000040 ++#define ETH_RDES0_FT 0x00000020 ++#define ETH_RDES0_RWT 0x00000010 ++#define ETH_RDES0_RE 0x00000008 ++#define ETH_RDES0_DBE 0x00000004 ++#define ETH_RDES0_CE 0x00000002 ++#define ETH_RDES0_RX 0x00000001 ++ ++#define ETH_RDES0_COE_MASK 0x000000a1 ++#define ETH_RDES0_COE_LENLT600 0x00000000 /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ ++#define ETH_RDES0_COE_UNSUPPORTED 0x00000001 /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ ++#define ETH_RDES0_COE_RESERVED 0x00000080 /* Bit(5:7:0)=>2 Reserved */ ++#define ETH_RDES0_COE_CHKBYPASS 0x00000081 /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ ++#define ETH_RDES0_COE_NOCHKERROR 0x00000020 /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ ++#define ETH_RDES0_COE_PLCHKERROR 0x00000021 /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ ++#define ETH_RDES0_COE_HDRCHKERROR 0x000000a0 /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ ++#define ETH_RDES0_COE_HDRPLCHKERROR 0x000000a1 /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ ++ ++/* Receive Descriptor 1 (RDES1) */ ++#define ETH_RDES1_DIC 0x80000000 ++#define ETH_RDES1_RER 0x02000000 ++#define ETH_RDES1_RCH 0x01000000 ++#define ETH_RDES1_RBS2(v) (((v) & 0x003ff800) >> 11) /* Receive Buffer 2 Size */ ++#define ETH_RDES1_RBS1(v) ((v) & 0x000007ff) /* Receive Buffer 1 Size */ ++#define ETH_RDES1_RBS2x(x) (((x) << 11) & 0x003ff800) /* Receive Buffer 2 Size */ ++#define ETH_RDES1_RBS1x(x) ((x) & 0x000007ff) /* Receive Buffer 1 Size */ ++ ++/* Transmit Descriptor 0 (TDES0) */ ++#define ETH_TDES0_OWN 0x80000000 ++#define ETH_TDES0_TTSS 0x00020000 ++#define ETH_TDES0_IHE 0x00010000 ++#define ETH_TDES0_ES 0x00008000 ++#define ETH_TDES0_JT 0x00004000 ++#define ETH_TDES0_FF 0x00002000 ++#define ETH_TDES0_PCE 0x00001000 ++#define ETH_TDES0_LCA 0x00000800 ++#define ETH_TDES0_NC 0x00000400 ++#define ETH_TDES0_LCO 0x00000200 ++#define ETH_TDES0_EC 0x00000100 ++#define ETH_TDES0_VF 0x00000080 ++#define ETH_TDES0_CC(v) (((v) & 0x00000078) >> 3) ++#define ETH_TDES0_ED 0x00000004 ++#define ETH_TDES0_UF 0x00000002 ++#define ETH_TDES0_DB 0x00000001 ++#define ETH_TDES0_ES_MASK (ETH_TDES0_UF | ETH_TDES0_ED | \ ++ ETH_TDES0_EC | ETH_TDES0_LCO | \ ++ ETH_TDES0_NC | ETH_TDES0_LCA | \ ++ ETH_TDES0_FF | ETH_TDES0_JT | \ ++ ETH_TDES0_ES) ++ ++/* Transmit Descriptor 1 (TDES1) */ ++#define ETH_TDES1_IC 0x80000000 ++#define ETH_TDES1_LS 0x40000000 ++#define ETH_TDES1_FS 0x20000000 ++#define ETH_TDES1_CIC_TUI 0x10000000 ++#define ETH_TDES1_CIC_HDR 0x08000000 ++#define ETH_TDES1_DC 0x04000000 ++#define ETH_TDES1_TER 0x02000000 ++#define ETH_TDES1_TCH 0x01000000 ++#define ETH_TDES1_DP 0x00800000 ++#define ETH_TDES1_TBS2(v) (((v) & 0x003ff800) >> 11) ++#define ETH_TDES1_TBS1(v) ((v) & 0x000007ff) ++#define ETH_TDES1_TBS2x(x) (((x) << 11) & 0x003ff800) ++#define ETH_TDES1_TBS1x(x) ((x) & 0x000007ff) ++ ++/* ==========================================================================*/ ++#define GKETH_MAC_SIZE (6) ++ ++ ++#define EPHY_BASE (GK_VA_ETH_PHY) ++#define EPHY_REG(x) (EPHY_BASE + (x)) ++ ++#define REG_EPHY_CONTROL EPHY_REG(0x000) /* read/write */ ++#define REG_EPHY_STATUS EPHY_REG(0x004) /* read */ ++#define REG_EPHY_ID1 EPHY_REG(0x008) /* read */ ++#define REG_EPHY_ID2 EPHY_REG(0x00C) /* read */ ++#define REG_EPHY_ANAR EPHY_REG(0x010) /* read/write */ ++#define REG_EPHY_ANLPAR EPHY_REG(0x014) /* read */ ++#define REG_EPHY_ANER EPHY_REG(0x018) /* read/write */ ++#define REG_EPHY_ANNPAR EPHY_REG(0x01C) /* read/write */ ++#define REG_EPHY_ANLPNP EPHY_REG(0x020) /* read */ ++#define REG_EPHY_MS_CONTROL EPHY_REG(0x024) /* read/write */ ++#define REG_EPHY_MS_STATUS EPHY_REG(0x028) /* read */ ++#define REG_EPHY_PSE_CONTROL EPHY_REG(0x02C) /* read/write */ ++#define REG_EPHY_PSE_STATUS EPHY_REG(0x030) /* read */ ++#define REG_EPHY_MMD_CONTROL EPHY_REG(0x034) /* read/write */ ++#define REG_EPHY_MMD_CONTROL_ADDR EPHY_REG(0x038) /* read/write */ ++#define REG_EPHY_AN_R_15 EPHY_REG(0x03C) /* read */ ++#define REG_EPHY_WAVE_SHAPING_34 EPHY_REG(0x040) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_56 EPHY_REG(0x044) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_78 EPHY_REG(0x048) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_9A EPHY_REG(0x04C) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_BC EPHY_REG(0x050) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_DE EPHY_REG(0x054) /* read/write */ ++#define REG_EPHY_SPEED EPHY_REG(0x058) /* read/write */ ++#define REG_EPHY_LTP EPHY_REG(0x05C) /* read/write */ ++#define REG_EPHY_MCU EPHY_REG(0x060) /* read/write */ ++#define REG_EPHY_CODE_RAM EPHY_REG(0x064) /* read/write */ ++#define REG_EPHY_CODE_RAM_W EPHY_REG(0x068) /* read/write */ ++#define REG_EPHY_100M_LINK EPHY_REG(0x088) /* read/write */ ++#define REG_EPHY_DEBUG EPHY_REG(0x0C8) /* read/write */ ++#define REG_EPHY_DEBUG_MODE EPHY_REG(0x0E0) /* read/write */ ++#define REG_EPHY_ADC_GAIN_PGA EPHY_REG(0x36C) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL3 EPHY_REG(0x370) /* read/write */ ++#define REG_EPHY_RX_LPF EPHY_REG(0x374) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL0 EPHY_REG(0x394) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL1 EPHY_REG(0x398) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL2 EPHY_REG(0x3A8) /* read/write */ ++#define REG_EPHY_ADC_DC EPHY_REG(0x3D4) /* read/write */ ++#define REG_EPHY_LDO EPHY_REG(0x3F8) /* read/write */ ++#define REG_EPHY_CLK_GATE EPHY_REG(0x450) /* read */ ++#define REG_EPHY_CLK1 EPHY_REG(0x460) /* read/write */ ++#define REG_EPHY_POWER EPHY_REG(0x474) /* read/write */ ++#define REG_EPHY_MDIIO EPHY_REG(0x540) /* read/write */ ++#define REG_EPHY_CLK0 EPHY_REG(0x588) /* read/write */ ++ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_eth_platform_info { ++ u8 mac_addr[GKETH_MAC_SIZE]; ++ u32 napi_weight; ++ u32 watchdog_timeo; ++ ++ u32 phy_id; ++ u32 phy_supported; ++ u32 mii_id; ++ struct gk_gpio_io_info phy_reset; ++ u32 mii_retry_limit; ++ u32 mii_retry_tmo; ++ ++ u32 default_tx_ring_size; ++ u32 default_rx_ring_size; ++ u32 default_dma_bus_mode; ++ u32 default_dma_opmode; ++ u32 default_supported; ++ ++ int (*is_enabled)(void); ++}; ++ ++#define GK_ETH_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(eth##id##_napi_weight, ¶m_ops_uint, &(arg.napi_weight), perm); \ ++ module_param_cb(eth##id##_watchdog_timeo, ¶m_ops_uint, &(arg.watchdog_timeo), perm); \ ++ module_param_cb(eth##id##_phy_id, ¶m_ops_uint, &(arg.phy_id), perm); \ ++ module_param_cb(eth##id##_mii_id, ¶m_ops_uint, &(arg.mii_id), perm); \ ++ module_param_cb(eth##id##_mii_retry_limit, ¶m_ops_uint, &(arg.mii_retry_limit), perm); \ ++ module_param_cb(eth##id##_mii_retry_tmo, ¶m_ops_uint, &(arg.mii_retry_tmo), perm); ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_eth0; ++ ++/* ==========================================================================*/ ++extern int gk_init_eth0(const u8 *mac_addr); ++extern void gk_set_phy_reset_pin(u32 gpio_pin); ++extern void gk_set_phy_speed_led(u32 gpio_type); ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++ ++#endif /* __MACH_ETH_H__ */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/event.h b/arch/arm/mach-gk710x/include/mach/event.h +new file mode 100644 +index 00000000..f9fb34f3 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/event.h +@@ -0,0 +1,121 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/plat/event.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __PLAT_EVENT_H ++#define __PLAT_EVENT_H ++ ++/* ==========================================================================*/ ++#define GK_EVENT_PRE (0x80000000) ++#define GK_EVENT_POST (0x40000000) ++#define GK_EVENT_CHECK (0x20000000) ++ ++#define GK_EVENT_ID_CPUFREQ (1) ++#define GK_EVENT_ID_PM (2) ++#define GK_EVENT_ID_TOSS (3) ++#define GK_EVENT_ID_GIVEUP_DSP (4) ++#define GK_EVENT_ID_TAKEOVER_DSP (5) ++#define GK_EVENT_ID_USBVBUS (6) ++#define GK_EVENT_ID_VI_LOSS (7) ++ ++#define GK_EVENT_PRE_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_PRE) ++#define GK_EVENT_POST_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_POST) ++#define GK_EVENT_CHECK_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_PM (GK_EVENT_ID_PM | GK_EVENT_PRE) ++#define GK_EVENT_POST_PM (GK_EVENT_ID_PM | GK_EVENT_POST) ++#define GK_EVENT_CHECK_PM (GK_EVENT_ID_PM | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_PRE) ++#define GK_EVENT_POST_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_POST) ++#define GK_EVENT_CHECK_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_CHECK) ++ ++#define GK_EVENT_PRE_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_PRE) ++#define GK_EVENT_POST_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_POST) ++#define GK_EVENT_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_PRE) ++#define GK_EVENT_POST_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_POST) ++#define GK_EVENT_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_CHECK) ++ ++#define GK_EVENT_CHECK_USBVBUS (GK_EVENT_ID_USBVBUS | GK_EVENT_CHECK) ++ ++#define GK_EVENT_POST_VI_LOSS (GK_EVENT_ID_VI_LOSS | GK_EVENT_POST) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++#include ++ ++/* ==========================================================================*/ ++enum gk_event_type { ++ /* No Event */ ++ GK_EV_NONE = 0x00000000, ++ ++ /* VI Event */ ++ GK_EV_VI_DECODER_SOURCE_PLUG = 0x00010000, ++ GK_EV_VI_DECODER_SOURCE_REMOVE, ++ ++ /* VO Event */ ++ GK_EV_VO_CVBS_PLUG = 0x00020000, ++ GK_EV_VO_CVBS_REMOVE, ++ GK_EV_VO_YPBPR_PLUG, ++ GK_EV_VO_YPBPR_REMOVE, ++ GK_EV_VO_HDMI_PLUG, ++ GK_EV_VO_HDMI_REMOVE, ++ ++ /* SENSOR Event*/ ++ GK_EV_ACCELEROMETER_REPORT = 0x00030000, ++ GK_EV_MAGNETIC_FIELD_REPORT, ++ GK_EV_LIGHT_REPORT, ++ GK_EV_PROXIMITY_REPORT, ++ GK_EV_GYROSCOPE_REPORT, ++ GK_EV_TEMPERATURE_REPORT, ++ ++ /* FB2 Event */ ++ GK_EV_FB2_PAN_DISPLAY = 0x00040000, ++}; ++ ++struct gk_event { ++ u32 sno; //sequential number ++ u64 time_code; ++ enum gk_event_type type; ++ u8 data[32]; ++}; ++ ++struct gk_event_pool { ++ struct mutex op_mutex; ++ struct gk_event events[256]; ++ unsigned int ev_sno; ++ unsigned char ev_index; ++}; ++ ++extern int gk_event_pool_init(struct gk_event_pool *pool); ++extern int gk_event_pool_affuse(struct gk_event_pool *pool, ++ struct gk_event event); ++extern int gk_event_pool_query_index(struct gk_event_pool *pool); ++extern int gk_event_pool_query_event(struct gk_event_pool *pool, ++ struct gk_event *event, unsigned char index); ++extern int gk_event_report_uevent(struct kobject *kobj, ++ enum kobject_action action, char *envp_ext[]); ++ ++/* ==========================================================================*/ ++extern int gk_unregister_event_notifier(void *nb); ++extern int gk_set_event(unsigned long val, void *v); ++extern int gk_register_raw_event_notifier(void *nb); ++extern int gk_unregister_raw_event_notifier(void *nb); ++extern int gk_set_raw_event(unsigned long val, void *v); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710x/include/mach/flash.h b/arch/arm/mach-gk710x/include/mach/flash.h +new file mode 100644 +index 00000000..d0b4b3fd +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/flash.h +@@ -0,0 +1,59 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/flash.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_FLASH_H ++#define __MACH_FLASH_H ++ ++#include ++ ++#define SFLASH_REG(x) (GK_VA_SFLASH + (x)) ++ ++#define REG_SFLASH_DATA SFLASH_REG(0x00) /* read/write */ ++#define REG_SFLASH_COMMAND SFLASH_REG(0x04) /* read/write */ ++#define REG_SFLASH_CE SFLASH_REG(0x08) /* read/write */ ++#define REG_SFLASH_SPEED SFLASH_REG(0x0C) /* read/write */ ++#define REG_SFLASH_PARA_XIP SFLASH_REG(0x10) /* read/write */ ++ ++// FPGA: SCLK = 40MHz ++// EVB: SCLK = 138MHz ++// 000: SCLK/2 ++// 001: SCLK/4 ++// 010: SCLK/6 ++// 011: SCLK/8 ++// 100: SCLK/10 ++typedef enum ++{ ++ GOKE_SFLASH_FREQ_DIV2 = 0, ++ GOKE_SFLASH_FREQ_DIV4, ++ GOKE_SFLASH_FREQ_DIV6, ++ GOKE_SFLASH_FREQ_DIV8, ++ GOKE_SFLASH_FREQ_DIV10 ++}GD_SFLASH_SPEED_MODE; ++ ++#define SYSTEM_SFLASH_FREQ GOKE_SFLASH_FREQ_DIV2 ++ ++struct sflash_platform_data /* flash device platform_data */ ++{ ++ uint32_t speed_mode; ++ uint32_t channel; ++ uint32_t nr_parts; ++ struct mtd_partition *parts; ++}; ++ ++#endif /* __MACH_FLASH_H */ ++ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/gk710x.h b/arch/arm/mach-gk710x/include/mach/gk710x.h +new file mode 100644 +index 00000000..c308c13d +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/gk710x.h +@@ -0,0 +1,200 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/mach/gk.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK710X_H ++#define __MACH_GK710X_H ++ ++ ++#include ++#include ++ ++#define CHIP_ID(x) ((x / 1000)) ++#define CHIP_MAJOR(x) ((x / 100) % 10) ++#define CHIP_MINOR(x) ((x / 10) % 10) ++ ++/* ==========================================================================*/ ++#define GK_DEBUG_NULL (0) ++#define GK_DEBUG_MEDIA (1 << 0) ++#define GK_DEBUG_VI (1 << 1) ++#define GK_DEBUG_VO (1 << 2) ++#define GK_DEBUG_AAA (1 << 3) ++#define GK_DEBUG_DSP (1 << 4) ++ ++/* definition SOC types */ ++#define CONFIG_SOC_GK7101 0 ++#define CONFIG_SOC_GK7102 1 ++ ++#define CONFIG_U2K_PHY_TYPE 0xC0000000 ++#define CONFIG_U2K_ARM_FREQ 0xC0000004 ++#define CONFIG_U2K_HAL_ADDR 0xC0000008 ++ ++#define CONFIG_U2K_SOC_ADDR 0xC0000010 //0:, 1:7102 ++#define CONFIG_U2K_MEM_ADDR 0xC0000014 ++#define CONFIG_U2K_BSB_ADDR 0xC0000018 ++#define CONFIG_U2K_DSP_ADDR 0xC000001C ++ ++#define CONFIG_U2K_ENABLE 0xC0000020 ++#define CONFIG_U2K_USR_ADDR 0xC0000024 //for user's cmem module ++ ++#define CONFIG_U2K_TOTAL_MEM 0xC0000028 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++/* ==========================================================================*/ ++extern u32 gk_debug_level; ++extern u32 gk_debug_info; ++ ++#define HW_HAL_MODE 1 ++#define USB_DMA_ADD_MODE 0 // 1: need update hal to 20151223 ++#define SPI_API_MODE 1 // 1: need update hal to 20160324 ++#define ADC_HAL_MODE 1 ++#define AUD_HAL_MODE 1 ++#define CRY_HAL_MODE 1 ++#define DDR_HAL_MODE 1 ++#define DSP_HAL_MODE 1 ++#define ETH_HAL_MODE 1 ++#define GREG_HAL_MODE 1 ++#define GPIO_HAL_MODE 1 ++#define I2C_HAL_MODE 1 ++#define I2S_HAL_MODE 1 ++#define IR_HAL_MODE 1 ++#define IRQ_HAL_MODE 1 ++#define MCU_HAL_MODE 1 ++#define PWM_HAL_MODE 1 ++#define RCT_HAL_MODE 1 ++#define SD_HAL_MODE 1 ++#define SF_HAL_MODE 1 ++#define SSI_HAL_MODE 1 ++#define TIMER_HAL_MODE 1 ++#define UART_HAL_MODE 1 ++#define USB_HAL_MODE 1 ++#define VOUT_HAL_MODE 1 ++#define WDT_HAL_MODE 1 ++#define EFUSE_HAL_MODE 0 ++struct hw_ops ++{ ++ int (*get_version)(void); ++ unsigned int (*reserved)(unsigned int ); ++ ++ unsigned char (*hw_readb)(unsigned int ); ++ unsigned short (*hw_readw)(unsigned int ); ++ unsigned int (*hw_readl)(unsigned int ); ++ ++ void (*hw_writeb)(unsigned char , unsigned int ); ++ void (*hw_writew)(unsigned short , unsigned int ); ++ void (*hw_writel)(unsigned int , unsigned int ); ++ ++ unsigned int (*flash_read)(void); ++ void (*flash_write)(unsigned int); ++ ++ unsigned char (*usb_readb)(unsigned int ptr, unsigned int offset); ++ unsigned short (*usb_readw)(unsigned int ptr, unsigned int offset); ++ unsigned int (*usb_readl)(unsigned int ptr, unsigned int offset); ++ void (*usb_writeb)(unsigned int ptr, unsigned int offset, unsigned char value); ++ void (*usb_writew)(unsigned int ptr, unsigned int offset, unsigned short value); ++ void (*usb_writel)(unsigned int ptr, unsigned int offset, unsigned int value); ++ ++ unsigned int (*dma_readl)(unsigned int ptr); ++ void (*dma_writel)(unsigned int ptr, unsigned int value); ++ ++#if SPI_API_MODE ++ unsigned char (*spi_readb)(unsigned int ptr); ++ unsigned short (*spi_readw)(unsigned int ptr); ++ unsigned int (*spi_readl)(unsigned int ptr); ++ void (*spi_writeb)(unsigned int ptr, unsigned char value); ++ void (*spi_writew)(unsigned int ptr, unsigned short value); ++ void (*spi_writel)(unsigned int ptr, unsigned int value); ++#endif ++}; ++ ++extern struct hw_ops *g_hw; ++ ++extern unsigned long gk_debug_lookup_name(const char *name); ++void sensor_init(u8 active_level); ++void sensor_power(u8 power); ++u32 get_audio_clk_freq(void); ++ ++ ++#endif /* __ASSEMBLER__ */ ++ ++extern u32 get_ppm_phys(void); ++extern u32 get_ppm_virt(void); ++extern u32 get_ppm_size(void); ++ ++extern u32 get_bsbmem_phys(void); ++extern u32 get_bsbmem_virt(void); ++extern u32 get_bsbmem_size(void); ++ ++extern u32 get_dspmem_phys(void); ++extern u32 get_dspmem_virt(void); ++extern u32 get_dspmem_size(void); ++ ++extern u32 gk_phys_to_virt(u32 paddr); ++extern u32 gk_virt_to_phys(u32 vaddr); ++ ++extern u32 get_hal1_virt(void); ++extern u32 get_hal2_virt(void); ++ ++extern u32 get_ahb_phys(void); ++extern u32 get_ahb_virt(void); ++extern u32 get_ahb_size(void); ++ ++extern u32 get_apb_phys(void); ++extern u32 get_apb_virt(void); ++extern u32 get_apb_size(void); ++ ++extern u32 get_osd_phys(void); ++extern u32 get_osd_virt(void); ++extern u32 get_osd_size(void); ++ ++extern u32 get_pri_phys(void); ++extern u32 get_pri_virt(void); ++extern u32 get_pri_size(void); ++ ++extern u32 get_qpm_phys(void); ++extern u32 get_qpm_virt(void); ++extern u32 get_qpm_size(void); ++ ++extern u32 get_bsbmem_virt(void); ++extern u32 get_bsbmem_size(void); ++ ++extern u32 get_usrmem_phys(void); ++extern u32 get_usrmem_virt(void); ++extern u32 get_usrmem_size(void); ++ ++extern void get_stepping_info(int *chip, int *major, int *minor); ++extern int gk_register_event_notifier(void *nb); ++ ++extern u32 gk_boot_splash_logo; ++ ++extern u64 gk_dmamask; ++ ++extern int gk_create_proc_dir(void); ++extern struct proc_dir_entry *get_gk_proc_dir(void); ++ ++extern void get_stepping_info(int *chip, int *major, int *minor); ++ ++extern void gk_restart(char mode, const char *cmd); ++extern void gk_power_off(void); ++ ++extern void gk_map_io(void) __init; ++ ++extern void gk_load_51mcu_code(u32 code); ++ ++#endif /* __MACH_GK_H */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/gpio.h b/arch/arm/mach-gk710x/include/mach/gpio.h +new file mode 100644 +index 00000000..51741c05 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/gpio.h +@@ -0,0 +1,114 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/gpio.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GPIO_H_ ++#define __MACH_GPIO_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++#define GPIO0_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK0_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK1_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK0_PLL_IOCTRL_BASE (GK_VA_RCT + 0x0264) /* read/write */ ++#define GPIO0_BANK1_PLL_IOCTRL_BASE (GK_VA_RCT + 0x0264 - 0x100) /* read/write */ ++ ++// for bank ++#define REG_GPIO_IS_LOW_OFFSET (0x0000) /* read/write */ ++#define REG_GPIO_IS_HIGH_OFFSET (0x0004) /* read/write */ ++#define REG_GPIO_IBE_LOW_OFFSET (0x0008) /* read/write */ ++#define REG_GPIO_IBE_HIGH_OFFSET (0x000C) /* read/write */ ++#define REG_GPIO_IEV_LOW_OFFSET (0x0010) /* read/write */ ++#define REG_GPIO_IEV_HIGH_OFFSET (0x0014) /* read/write */ ++#define REG_GPIO_IE_LOW_OFFSET (0x0018) /* read/write */ ++#define REG_GPIO_IE_HIGH_OFFSET (0x001C) /* read/write */ ++#define REG_GPIO_IC_LOW_OFFSET (0x0020) /* write */ ++#define REG_GPIO_IC_HIGH_OFFSET (0x0024) /* write */ ++#define REG_GPIO_RIS_LOW_OFFSET (0x0028) /* read */ ++#define REG_GPIO_RIS_HIGH_OFFSET (0x002C) /* read */ ++#define REG_GPIO_MIS_LOW_OFFSET (0x0030) /* read */ ++#define REG_GPIO_MIS_HIGH_OFFSET (0x0034) /* read */ ++#define REG_GPIO_DIN_LOW_OFFSET (0x0040) /* read */ ++#define REG_GPIO_DIN_HIGH_OFFSET (0x0044) /* read */ ++#define REG_GPIO_OUTPUT_CFG_OFFSET (0x0100) /* write */ ++#define REG_GPIO_INPUT_CFG_OFFSET (0x0200) /* write */ ++ ++// for all bank ++#define REG_GPIO_INT_EN_OFFSET (0x0038) /* write */ ++#define REG_GPIO_PER_SEL_OFFSET (0x003C) /* read/write */ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++/*! ++******************************************************************************* ++** ++** \brief All available GPIO pins named by number. ++** ++** \sa GPIO_Open() ++** \sa GPIO_OpenFunctionMode() ++** \sa GPIO_SetType() ++** ++******************************************************************************* ++*/ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern int __init gk_init_gpio(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif /* __MACH_GPIO_H_ */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/gtypes.h b/arch/arm/mach-gk710x/include/mach/gtypes.h +new file mode 100644 +index 00000000..26932665 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/gtypes.h +@@ -0,0 +1,132 @@ ++#ifndef _GTYPES_H_ ++#define _GTYPES_H_ ++ ++#ifdef __LINUX__ ++#include /* kmalloc */ ++#include /* printk */ ++#include /* wait queue */ ++#include /* copy user<->kernel */ ++#include /* paddr<->vaddr */ ++#include /* semaphore */ ++#include /* poll */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* necessary undefines */ ++#ifdef GFALSE ++ #undef GFALSE ++#endif ++#ifdef GTRUE ++ #undef GTRUE ++#endif ++ ++ ++/*! ++******************************************************************************* ++** ++** \name GOKESDK Error Codes ++** ++******************************************************************************* ++*/ ++/*@{*/ ++enum ++{ ++ GD_OK = 0, //!< No error. ++ GD_ERR_BAD_PARAMETER, //!< Bad parameter passed. ++ GD_ERR_OUT_OF_MEMORY, //!< Memory allocation failed. ++ GD_ERR_ALREADY_INITIALIZED, //!< Device already initialised. ++ GD_ERR_NOT_INITIALIZED, //!< Device not initialised. ++ GD_ERR_ALREADY_OPEN, //!< Device could not be opened again. ++ GD_ERR_FEATURE_NOT_SUPPORTED, //!< Feature or function is not available. ++ GD_ERR_TIMEOUT, //!< Timeout occured. ++ GD_ERR_DEVICE_BUSY, //!< The device is busy. ++ GD_ERR_INVALID_HANDLE, //!< The handle is invalid. ++}; ++/*@}*/ ++ ++ ++/*! ++******************************************************************************* ++** ++** \name GOKESDK Data Types ++** ++******************************************************************************* ++*/ ++/*@{*/ ++typedef unsigned char U8; //!< 8 bit unsigned integer. ++typedef unsigned short U16; //!< 16 bit unsigned integer. ++#ifdef __LINUX__ ++typedef unsigned int U32; //!< 32 bit unsigned integer. ++typedef signed int S32; //!< 32 bit signed integer. ++#else ++typedef unsigned long U32; //!< 32 bit unsigned integer. ++typedef signed long S32; //!< 32 bit signed integer. ++#endif ++typedef signed char S8; //!< 8 bit signed integer. ++typedef signed short S16; //!< 16 bit signed integer. ++typedef unsigned long long U64; //!< 64 bit unsigned integer. ++ ++#ifdef __LINUX__ ++typedef int GERR; ++#else ++typedef unsigned long GERR; //!< GOKESDK error/return code. ++#endif ++typedef unsigned long GD_HANDLE; //!< GOKESDK handle. ++ ++/*! \brief Defines a GOKESDK boolean. */ ++#ifndef GTYPES_NO_BOOL ++typedef enum ++{ ++ GFALSE = 0, //!< Logical false. ++ GTRUE = 1 //!< Logical true. ++} GBOOL; ++#endif ++/*@}*/ ++ ++ ++ ++ ++/*! ++******************************************************************************* ++** ++** \brief Defines a GOKESDK null. ++** ++******************************************************************************* ++*/ ++#ifndef NULL ++ #define NULL 0 ++#endif ++ ++ ++/* ++******************************************************************************* ++** ++** Defines the keyword for inlining a function. ++** ++******************************************************************************* ++*/ ++ ++#define GH_INLINE_LEVEL 2 ++ ++#if defined(__HIGHC__) ++#define GH_INLINE _Inline ++#endif ++#if defined(__GNUC__) ++#define GH_INLINE static __inline__ ++#endif ++ ++#ifdef GISR_IS_VOID ++ #define GISR1 void /* customize C-Interrupt handler */ ++ #define GISR2 void ++#else ++ #define GISR1 irqreturn_t ++ #define GISR2 irqreturn_t ++#endif ++ ++#endif +\ No newline at end of file +diff --git a/arch/arm/mach-gk710x/include/mach/hardware.h b/arch/arm/mach-gk710x/include/mach/hardware.h +new file mode 100644 +index 00000000..03f9e71c +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/hardware.h +@@ -0,0 +1,226 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/mach/hardware.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/*-------------------------------------------------------------*/ ++ ++#define CONFIG_GK_PPM_SIZE 0x200000 ++ ++#define DEFAULT_MEM_START (0xc0000000) ++ ++ ++#define AHB_SIZE (0x01000000) ++#define APB_SIZE (0x01000000) ++ ++#define NOLINUX_MEM_V_START (0xe0000000) ++#define NOLINUX_MEM_V_SIZE (0x00100000) ++ ++ ++//-------------------dummy-----ahb----------- ++#define GK_PA_AHB_BASE (0x90000000) ++#define GK_VA_AHB_BASE (0xf2000000) ++ ++#define GK_ADDR_SDC_OFFSET 0x00000 //0x02000 //for dummy ++#define GK_ADDR_EFUSE_OFFSET 0x01000 ++#define GK_ADDR_DDRC_OFFSET 0x02000 ++#define GK_ADDR_DMAC_OFFSET 0x03000 ++#define GK_ADDR_VO_OFFSET 0x04000 ++#define GK_ADDR_CRYPT_OFFSET 0x05000 ++#define GK_ADDR_USB_OFFSET 0x06000 ++#define GK_ADDR_VIC1_OFFSET 0x08000 ++#define GK_ADDR_VIC2_OFFSET 0x09000 ++#define GK_ADDR_ETH_GMAC_OFFSET 0x0E000 ++#define GK_ADDR_ETH_DMA_OFFSET 0x0F000 ++#define GK_ADDR_I2S_OFFSET 0x0A000 ++#define GK_ADDR_SFLASH_OFFSET 0x16000 ++ ++#define GK_ADDR_ADC_OFFSET 0x20A00 ++#define GK_ADDR_AHB_GREG_OFFSET 0x20E00 ++#define GK_ADDR_USB_PHY_OFFSET 0x21000 ++#define GK_ADDR_ENET_PHY_OFFSET 0x22000 ++#define GK_ADDR_VEDIO_DAC_OFFSET 0x22600 ++ ++ ++#define GK_ADDR_PMU_OFFSET 0x80000 ++#define GK_ADDR_PMU_RTC_OFFSET 0x80000 ++#define GK_ADDR_PMU_C51_CODE_OFFSET 0xC0000 ++ ++ ++#define GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET 0x21C00 ++#define GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET 0x20C00 ++ ++ ++#define GK_PA_SDC (GK_PA_AHB_BASE + GK_ADDR_SDC_OFFSET) ++#define GK_PA_I2S (GK_PA_AHB_BASE + GK_ADDR_I2S_OFFSET) ++#define GK_PA_AHB_GREG (GK_PA_AHB_BASE + GK_ADDR_AHB_GREG_OFFSET) ++#define GK_PA_EFUSE (GK_PA_AHB_BASE + GK_ADDR_EFUSE_OFFSET) ++#define GK_PA_SFLASH (GK_PA_AHB_BASE + GK_ADDR_SFLASH_OFFSET) ++#define GK_PA_ADC (GK_PA_AHB_BASE + GK_ADDR_ADC_OFFSET) ++#define GK_PA_VO (GK_PA_AHB_BASE + GK_ADDR_VO_OFFSET) ++#define GK_PA_AUDIO_CODEC_DIGITAL (GK_PA_AHB_BASE + GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET) ++#define GK_PA_AUDIO_CODEC_ANALOG (GK_PA_AHB_BASE + GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET) ++#define GK_PA_DDRC (GK_PA_AHB_BASE + GK_ADDR_DDRC_OFFSET) ++#define GK_PA_VIC1 (GK_PA_AHB_BASE + GK_ADDR_VIC1_OFFSET) ++#define GK_PA_VIC2 (GK_PA_AHB_BASE + GK_ADDR_VIC2_OFFSET) ++#define GK_PA_ETH_GMAC (GK_PA_AHB_BASE + GK_ADDR_ETH_GMAC_OFFSET) ++#define GK_PA_ETH_DMA (GK_PA_AHB_BASE + GK_ADDR_ETH_DMA_OFFSET) ++#define GK_PA_USB_PHY (GK_PA_AHB_BASE + GK_ADDR_USB_PHY_OFFSET) ++#define GK_PA_ETH_PHY (GK_PA_AHB_BASE + GK_ADDR_ENET_PHY_OFFSET) ++#define GK_PA_PMU (GK_PA_AHB_BASE + GK_ADDR_PMU_OFFSET) ++#define GK_PA_PMU_RTC (GK_PA_AHB_BASE + GK_ADDR_PMU_RTC_OFFSET) ++#define GK_PA_PMU_C51_CODE (GK_PA_AHB_BASE + GK_ADDR_PMU_C51_CODE_OFFSET) ++#define GK_PA_VEDIO_DAC (GK_PA_AHB_BASE + GK_ADDR_VEDIO_DAC_OFFSET) ++#define GK_PA_CRYPT_UNIT (GK_PA_AHB_BASE + GK_ADDR_CRYPT_OFFSET) ++ ++#define GK_VA_SDC (GK_VA_AHB_BASE + GK_ADDR_SDC_OFFSET) ++#define GK_VA_I2S (GK_VA_AHB_BASE + GK_ADDR_I2S_OFFSET) ++#define GK_VA_AHB_GREG (GK_VA_AHB_BASE + GK_ADDR_AHB_GREG_OFFSET) ++#define GK_VA_EFUSE (GK_VA_AHB_BASE + GK_ADDR_EFUSE_OFFSET) ++#define GK_VA_ADC (GK_VA_AHB_BASE + GK_ADDR_ADC_OFFSET) ++#define GK_VA_DDRC (GK_VA_AHB_BASE + GK_ADDR_DDRC_OFFSET) ++#define GK_VA_VIC1 (GK_VA_AHB_BASE + GK_ADDR_VIC1_OFFSET) ++#define GK_VA_VIC2 (GK_VA_AHB_BASE + GK_ADDR_VIC2_OFFSET) ++#define GK_VA_ETH_GMAC (GK_VA_AHB_BASE + GK_ADDR_ETH_GMAC_OFFSET) ++#define GK_VA_ETH_DMA (GK_VA_AHB_BASE + GK_ADDR_ETH_DMA_OFFSET) ++#define GK_VA_USB_PHY (GK_VA_AHB_BASE + GK_ADDR_USB_PHY_OFFSET) ++#define GK_VA_ETH_PHY (GK_VA_AHB_BASE + GK_ADDR_ENET_PHY_OFFSET) ++#define GK_VA_PMU (GK_VA_AHB_BASE + GK_ADDR_PMU_OFFSET) ++#define GK_VA_PMU_RTC (GK_VA_AHB_BASE + GK_ADDR_PMU_RTC_OFFSET) ++#define GK_VA_SFLASH (GK_VA_AHB_BASE + GK_ADDR_SFLASH_OFFSET) ++#define GK_VA_VO (GK_VA_AHB_BASE + GK_ADDR_VO_OFFSET) ++#define GK_VA_AUDIO_CODEC_DIGITAL (GK_VA_AHB_BASE + GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET) ++#define GK_VA_AUDIO_CODEC_ANALOG (GK_VA_AHB_BASE + GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET) ++#define GK_VA_PMU_C51_CODE (GK_VA_AHB_BASE + GK_ADDR_PMU_C51_CODE_OFFSET) ++#define GK_VA_VEDIO_DAC (GK_VA_AHB_BASE + GK_ADDR_VEDIO_DAC_OFFSET) /*cvbs*/ ++#define GK_VA_CRYPT_UNIT (GK_VA_AHB_BASE + GK_ADDR_CRYPT_OFFSET) ++#if USB_DMA_ADD_MODE ++#define GK_PA_DMAC (GK_PA_AHB_BASE + GK_ADDR_DMAC_OFFSET) ++#define GK_PA_USB (GK_PA_AHB_BASE + GK_ADDR_USB_OFFSET) ++#define GK_VA_DMAC (GK_VA_AHB_BASE + GK_ADDR_DMAC_OFFSET) ++#define GK_VA_USB (GK_VA_AHB_BASE + GK_ADDR_USB_OFFSET) ++#else ++#define GK_PA_DMAC (0x60005000) ++#define GK_PA_USB (0x60006000) ++#define GK_VA_DMAC (0xf0005000) ++#define GK_VA_USB (0xf0006000) ++#endif ++ ++ ++//-------------------dummy-----apb----------- ++#define GK_PA_APB_BASE (0xA0000000) ++#define GK_VA_APB_BASE (0xf3000000) ++ ++#define GK_ADDR_TIMER_OFFSET 0x00000 ++#define GK_ADDR_IDC_OFFSET 0x03000 ++#define GK_ADDR_IDC2_OFFSET 0x04000 ++#define GK_ADDR_UART0_OFFSET 0x05000 ++#define GK_ADDR_WDT_OFFSET 0x06000 ++#define GK_ADDR_GPIO0_OFFSET 0x09000 ++#define GK_ADDR_ADC2_OFFSET 0x07000 ++ ++#define GK_ADDR_PWM0_OFFSET 0x0a000 ++#define GK_ADDR_PWM1_OFFSET 0x0b000 ++#define GK_ADDR_PWM2_OFFSET 0x0c000 ++#define GK_ADDR_PWM3_OFFSET 0x0d000 ++ ++#define GK_ADDR_UART2_OFFSET 0x1E000 ++#define GK_ADDR_UART1_OFFSET 0x1F000 ++ ++#define GK_ADDR_SSI1_OFFSET 0x02000 ++#define GK_ADDR_SSI2_OFFSET 0x08000 ++#define GK_ADDR_TSSI_OFFSET 0x01000 ++ ++#define GK_ADDR_MEM_OFFSET 0x150000 ++#define GK_ADDR_RCT_OFFSET 0x170000 ++ ++ ++ ++#define GK_PA_TIMER (GK_PA_APB_BASE + GK_ADDR_TIMER_OFFSET) ++#define GK_PA_IDC (GK_PA_APB_BASE + GK_ADDR_IDC_OFFSET) ++#define GK_PA_IDC2 (GK_PA_APB_BASE + GK_ADDR_IDC2_OFFSET) ++#define GK_PA_UART0 (GK_PA_APB_BASE + GK_ADDR_UART0_OFFSET) ++#define GK_PA_WDT (GK_PA_APB_BASE + GK_ADDR_WDT_OFFSET) ++#define GK_PA_GPIO0 (GK_PA_APB_BASE + GK_ADDR_GPIO0_OFFSET) ++#define GK_PA_PWM0 (GK_PA_APB_BASE + GK_ADDR_PWM0_OFFSET) ++#define GK_PA_PWM1 (GK_PA_APB_BASE + GK_ADDR_PWM1_OFFSET) ++#define GK_PA_PWM2 (GK_PA_APB_BASE + GK_ADDR_PWM2_OFFSET) ++#define GK_PA_PWM3 (GK_PA_APB_BASE + GK_ADDR_PWM3_OFFSET) ++#define GK_PA_UART2 (GK_PA_APB_BASE + GK_ADDR_UART2_OFFSET) ++#define GK_PA_UART1 (GK_PA_APB_BASE + GK_ADDR_UART1_OFFSET) ++#define GK_PA_ADC2 (GK_PA_APB_BASE + GK_ADDR_ADC2_OFFSET) ++ ++#define GK_PA_SSI1 (GK_PA_APB_BASE + GK_ADDR_SSI1_OFFSET) ++#define GK_PA_SSI2 (GK_PA_APB_BASE + GK_ADDR_SSI2_OFFSET) ++#define GK_PA_TSSI (GK_PA_APB_BASE + GK_ADDR_TSSI_OFFSET) ++#define GK_PA_RCT (GK_PA_APB_BASE + GK_ADDR_RCT_OFFSET) ++#define GK_PA_MEM (GK_PA_APB_BASE + GK_ADDR_MEM_OFFSET) ++ ++ ++ ++#define GK_VA_TIMER (GK_VA_APB_BASE + GK_ADDR_TIMER_OFFSET) ++#define GK_VA_IDC (GK_VA_APB_BASE + GK_ADDR_IDC_OFFSET) ++#define GK_VA_IDC2 (GK_VA_APB_BASE + GK_ADDR_IDC2_OFFSET) ++#define GK_VA_UART0 (GK_VA_APB_BASE + GK_ADDR_UART0_OFFSET) ++#define GK_VA_WDT (GK_VA_APB_BASE + GK_ADDR_WDT_OFFSET) ++#define GK_VA_GPIO0 (GK_VA_APB_BASE + GK_ADDR_GPIO0_OFFSET) ++#define GK_VA_PWM0 (GK_VA_APB_BASE + GK_ADDR_PWM0_OFFSET) ++#define GK_VA_PWM1 (GK_VA_APB_BASE + GK_ADDR_PWM1_OFFSET) ++#define GK_VA_PWM2 (GK_VA_APB_BASE + GK_ADDR_PWM2_OFFSET) ++#define GK_VA_PWM3 (GK_VA_APB_BASE + GK_ADDR_PWM3_OFFSET) ++#define GK_VA_ADC2 (GK_VA_APB_BASE + GK_ADDR_ADC2_OFFSET) ++ ++#define GK_VA_UART2 (GK_VA_APB_BASE + GK_ADDR_UART2_OFFSET) ++#define GK_VA_UART1 (GK_VA_APB_BASE + GK_ADDR_UART1_OFFSET) ++ ++#define GK_VA_SSI1 (GK_VA_APB_BASE + GK_ADDR_SSI1_OFFSET) ++#define GK_VA_SSI2 (GK_VA_APB_BASE + GK_ADDR_SSI2_OFFSET) ++#define GK_VA_TSSI (GK_VA_APB_BASE + GK_ADDR_TSSI_OFFSET) ++#define GK_VA_RCT (GK_VA_APB_BASE + GK_ADDR_RCT_OFFSET) ++#define GK_VA_MEM (GK_VA_APB_BASE + GK_ADDR_MEM_OFFSET) ++ ++ ++#define GRAPHICS_DMA_OFFSET 0x15000 ++#define GRAPHICS_DMA_BASE (GK_VA_AHB_BASE + GRAPHICS_DMA_OFFSET) ++#define GRAPHICS_DMA_REG(x) (GRAPHICS_DMA_BASE + (x)) ++ ++ ++ ++#define VO_CLK_ONCHIP_PLL_27MHZ 0x0 /* Default setting */ ++#define VO_CLK_ONCHIP_PLL_SP_CLK 0x1 ++#define VO_CLK_ONCHIP_PLL_CLK_SI 0x2 ++#define VO_CLK_EXTERNAL 0x3 ++#define VO_CLK_ONCHIP_PLL_DSP_SCLK 0x4 ++ ++#define TIMER_OFFSET 0xb000 ++ ++ ++#define CONSISTENT_DMA_SIZE SZ_8M ++ ++/* ==========================================================================*/ ++ ++//end ++ ++#endif /* __ASM_ARCH_HARDWARE_H */ ++ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/i2s.h b/arch/arm/mach-gk710x/include/mach/i2s.h +new file mode 100644 +index 00000000..5bdd528f +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/i2s.h +@@ -0,0 +1,158 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/i2s.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_I2S_H__ ++#define __HAL_I2S_H__ ++ ++#include ++ ++#define I2S_BASE (GK_VA_I2S) ++#define I2S_BASE_PHYS (GK_PA_I2S) ++#define I2S_REG(x) (I2S_BASE + (x)) ++#define I2S_REG_PHYS(x) (I2S_BASE_PHYS + (x)) ++ ++#define I2S_BASE_extern I2S_BASE ++ ++#define I2S_DMA_REG_OFFSET (0x30000000) ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define I2S_SUPPORT_GATE_SHIFT 1 ++#define I2S_MAX_CHANNELS 6 ++#define I2S_GK_IP 1 ++#define I2S_24BITMUX_MODE_REG_BITS 4 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define I2S_MODE_OFFSET 0x08 ++#define I2S_RX_CTRL_OFFSET 0x2c ++#define I2S_TX_CTRL_OFFSET 0x0c ++#define I2S_WLEN_OFFSET 0x58 ++#define I2S_WPOS_OFFSET 0x44 ++#define I2S_SLOT_OFFSET 0x50 ++#define I2S_TX_FIFO_LTH_OFFSET 0x10 ++#define I2S_RX_FIFO_GTH_OFFSET 0x3c ++#define I2S_CLOCK_OFFSET 0x00 ++#define I2S_INIT_OFFSET 0x4c ++#define I2S_TX_STATUS_OFFSET 0x14 ++#define I2S_TX_LEFT_DATA_OFFSET 0x1c ++#define I2S_TX_RIGHT_DATA_OFFSET 0x20 ++#define I2S_RX_STATUS_OFFSET 0x54 ++#define I2S_RX_DATA_OFFSET 0x30 ++#define I2S_TX_FIFO_CNTR_OFFSET 0x18 ++#define I2S_RX_FIFO_CNTR_OFFSET 0x34 ++#define I2S_TX_INT_ENABLE_OFFSET 0x24 ++#define I2S_RX_INT_ENABLE_OFFSET 0x38 ++#define I2S_RX_ECHO_OFFSET 0x40 ++#define I2S_24BITMUX_MODE_OFFSET 0x28 ++#define I2S_RX_DATA_DMA_OFFSET 0x80 ++#define I2S_TX_LEFT_DATA_DMA_OFFSET 0xc0 ++ ++#define I2S_MODE_REG I2S_REG(0x08) ++#define I2S_RX_CTRL_REG I2S_REG(0x2c) ++#define I2S_TX_CTRL_REG I2S_REG(0x0c) ++#define I2S_WLEN_REG I2S_REG(0x58) ++#define I2S_WPOS_REG I2S_REG(0x44) ++#define I2S_SLOT_REG I2S_REG(0x50) ++#define I2S_TX_FIFO_LTH_REG I2S_REG(0x10) ++#define I2S_RX_FIFO_GTH_REG I2S_REG(0x3c) ++#define I2S_CLOCK_REG I2S_REG(0x00) ++#define I2S_INIT_REG I2S_REG(0x4c) ++#define I2S_TX_STATUS_REG I2S_REG(0x14) ++#define I2S_TX_LEFT_DATA_REG I2S_REG(0x1c) ++#define I2S_TX_RIGHT_DATA_REG I2S_REG(0x20) ++#define I2S_RX_STATUS_REG I2S_REG(0x54) ++#define I2S_RX_DATA_REG I2S_REG(0x30) ++#define I2S_TX_FIFO_CNTR_REG I2S_REG(0x18) ++#define I2S_RX_FIFO_CNTR_REG I2S_REG(0x34) ++#define I2S_TX_INT_ENABLE_REG I2S_REG(0x24) ++#define I2S_RX_INT_ENABLE_REG I2S_REG(0x38) ++#define I2S_RX_ECHO_REG I2S_REG(0x40) ++#define I2S_24BITMUX_MODE_REG I2S_REG(0x28) ++#define I2S_GATEOFF_REG I2S_REG(0x48) ++#define I2S_CHANNEL_SELECT_REG I2S_REG(0x04) ++#define I2S_RX_DATA_DMA_REG I2S_REG(0x80) ++#define I2S_TX_LEFT_DATA_DMA_REG I2S_REG(0xc0) ++ ++ ++#if (I2S_GK_IP == 1) ++#define I2S_TX_FIFO_RESET_BIT (1 << 0) ++#define I2S_RX_FIFO_RESET_BIT (1 << 3) ++#endif ++#define I2S_TX_ENABLE_BIT (1 << 2) ++#define I2S_RX_ENABLE_BIT (1 << 1) ++#define I2S_FIFO_RESET_BIT (1 << 4) ++ ++#define I2S_RX_LOOPBACK_BIT (1 << 2) ++#define I2S_RX_ORDER_BIT (1 << 0) ++#define I2S_RX_WS_MST_BIT (1 << 3) ++#define I2S_RX_WS_INV_BIT (1 << 1) ++ ++#define I2S_TX_LOOPBACK_BIT (1 << 5) ++#define I2S_TX_ORDER_BIT (1 << 3) ++#define I2S_TX_WS_MST_BIT (1 << 6) ++#define I2S_TX_WS_INV_BIT (1 << 2) ++#define I2S_TX_UNISON_BIT (1 << 4) ++#define I2S_TX_MUTE_BIT (1 << 7) ++#define I2S_TX_MONO_MASK 0xfffffffc ++#define I2S_TX_MONO_STEREO (0) ++#define I2S_TX_MONO_RIGHT (2) ++#define I2S_TX_MONO_LEFT (3) ++ ++#define I2S_CLK_WS_OUT_EN (1 << 7) ++#define I2S_CLK_BCLK_OUT_EN (1 << 5) ++#define I2S_CLK_BCLK_OUTPUT (1 << 8) ++#define I2S_CLK_TX_PO_FALL (1 << 9) ++#define I2S_CLK_RX_PO_FALL (1 << 6) ++#define I2S_CLK_DIV_MASK 0xffffffe0 ++#define I2S_CLK_MASTER_MODE (I2S_CLK_WS_OUT_EN | \ ++ I2S_CLK_BCLK_OUT_EN | \ ++ I2S_CLK_TX_PO_FALL | \ ++ I2S_CLK_RX_PO_FALL | \ ++ I2S_CLK_BCLK_OUTPUT) ++ ++ ++#if (I2S_GK_IP == 0) ++#define I2S_RX_SHIFT_ENB (1 << 2) ++#define I2S_TX_SHIFT_ENB (1 << 1) ++#else ++#define I2S_RX_SHIFT_ENB (1 << 1) ++#define I2S_TX_SHIFT_ENB (1 << 0) ++#endif ++ ++#define I2S_2CHANNELS_ENB 0x00 ++#define I2S_4CHANNELS_ENB 0x01 ++#define I2S_6CHANNELS_ENB 0x02 ++ ++#define I2S_FIFO_THRESHOLD_INTRPT 0x08 ++#define I2S_FIFO_FULL_INTRPT 0x02 ++#define I2S_FIFO_EMPTY_INTRPT 0x01 ++ ++/* I2S_24BITMUX_MODE_REG */ ++#define I2S_24BITMUX_MODE_BIT (1 << 3) ++#if (I2S_24BITMUX_MODE_REG_BITS == 4) ++#define I2S_24BITMUX_MODE_FDMA_BURST_DIS 0x2 ++#define I2S_24BITMUX_MODE_RST_CHAN0 0x4 ++#define I2S_24BITMUX_MODE_DMA_BOOTSEL 0x8 ++#endif ++ ++#endif /* __HAL_I2S_H__ */ +diff --git a/arch/arm/mach-gk710x/include/mach/idc.h b/arch/arm/mach-gk710x/include/mach/idc.h +new file mode 100644 +index 00000000..4d460e70 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/idc.h +@@ -0,0 +1,165 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/mach/idc.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __MACH_IDC_H__ ++#define __MACH_IDC_H__ ++ ++#include ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define IDC_INSTANCES 2 ++#define IDCS_INSTANCES 0 ++ ++#define IDC_INTERNAL_DELAY_CLK 2 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define IDC_PSLL_OFFSET 0x00 ++#define IDC_PSLH_OFFSET 0x04 ++#define IDC_FMCTRL_OFFSET 0x08 ++#define IDC_CTRL_OFFSET 0x0c ++#define IDC_STS_OFFSET 0x10 ++#define IDC_ENR_OFFSET 0x14 ++#define IDC_DATA_OFFSET 0x18 ++#define IDC_FMDATA_OFFSET 0x1c ++ ++#if (IDCS_INSTANCES >= 1) ++#define IDCS_ENR_OFFSET 0x00 ++#define IDCS_CTRL_OFFSET 0x04 ++#define IDCS_DATA_OFFSET 0x08 ++#define IDCS_STS_OFFSET 0x0c ++#define IDCS_FIFO_CNT_OFFSET 0x10 ++#define IDCS_RX_CNT_OFFSET 0x14 ++#define IDCS_TX_CNT_OFFSET 0x18 ++#define IDCS_HOLD_TIME_OFFSET 0x1c ++#define IDCS_SLAVE_ADDR_OFFSET 0x20 ++#define IDCS_SCL_TIMER_OFFSET 0x24 ++#define IDCS_TIMEOUT_STS_OFFSET 0x28 ++#endif ++ ++#define IDC_REG(x) (GK_PA_IDC + (x)) ++ ++#define IDC_ENR_REG IDC_REG(IDC_ENR_OFFSET) ++#define IDC_CTRL_REG IDC_REG(IDC_CTRL_OFFSET) ++#define IDC_DATA_REG IDC_REG(IDC_DATA_OFFSET) ++#define IDC_STS_REG IDC_REG(IDC_STS_OFFSET) ++#define IDC_PSLL_REG IDC_REG(IDC_PSLL_OFFSET) ++#define IDC_PSLH_REG IDC_REG(IDC_PSLH_OFFSET) ++#define IDC_FMCTRL_REG IDC_REG(IDC_FMCTRL_OFFSET) ++#define IDC_FMDATA_REG IDC_REG(IDC_FMDATA_OFFSET) ++ ++#if (IDC_INSTANCES >= 2) ++ ++#define IDC2_REG(x) (GK_PA_IDC2 + (x)) ++ ++#define IDC2_ENR_REG IDC2_REG(IDC_ENR_OFFSET) ++#define IDC2_CTRL_REG IDC2_REG(IDC_CTRL_OFFSET) ++#define IDC2_DATA_REG IDC2_REG(IDC_DATA_OFFSET) ++#define IDC2_STS_REG IDC2_REG(IDC_STS_OFFSET) ++#define IDC2_PSLL_REG IDC2_REG(IDC_PSLL_OFFSET) ++#define IDC2_PSLH_REG IDC2_REG(IDC_PSLH_OFFSET) ++#define IDC2_FMCTRL_REG IDC2_REG(IDC_FMCTRL_OFFSET) ++#define IDC2_FMDATA_REG IDC2_REG(IDC_FMDATA_OFFSET) ++#endif ++ ++#if (IDCS_INSTANCES >= 1) ++#define IDCS_ENR_REG IDCS_REG(IDCS_ENR_OFFSET) ++#define IDCS_CTRL_REG IDCS_REG(IDCS_CTRL_OFFSET) ++#define IDCS_DATA_REG IDCS_REG(IDCS_DATA_OFFSET) ++#define IDCS_STS_REG IDCS_REG(IDCS_STS_OFFSET) ++#define IDCS_FIFO_CNT_REG IDCS_REG(IDCS_FIFO_CNT_OFFSET) ++#define IDCS_RX_CNT_REG IDCS_REG(IDCS_RX_CNT_OFFSET) ++#define IDCS_TX_CNT_REG IDCS_REG(IDCS_TX_CNT_OFFSET) ++#define IDCS_HOLD_TIME_REG IDCS_REG(IDCS_HOLD_TIME_OFFSET) ++#define IDCS_SLAVE_ADDR_REG IDCS_REG(IDCS_SLAVE_ADDR_OFFSET) ++#define IDCS_SCL_TIMER_REG IDCS_REG(IDCS_SCL_TIMER_OFFSET) ++#define IDCS_TIMEOUT_STS_REG IDCS_REG(IDCS_TIMEOUT_STS_OFFSET) ++ ++ ++/* Bit/format definition */ ++ ++/* IDCS_CTRL_REG */ ++#define IDCS_IRQ_EN 0x02 ++#define IDCS_IRQ_P_SR_EN 0x04 ++#define IDCS_IRQ_FIFO_TH_EN 0x08 ++#define IDCS_IRQ_TIME_OUT_EN 0x10 ++ ++/* IDCS_STS_REG */ ++#define IDCS_TIMEOUT 0x100 ++#define IDCS_STOP 0x080 ++#define IDCS_REPEATED_START 0x040 ++#define IDCS_FIFO_TH_VLD 0x020 ++#define IDCS_SEL 0x010 ++#define IDCS_GENERAL_CALL 0x008 ++#define IDCS_FIFO_FULL 0x004 ++#define IDCS_FIFO_EMPTY 0x002 ++#define IDCS_RX_TX_STATE 0x001 ++ ++#define IDCS_TX_MODE 0x0 ++#define IDCS_RX_MODE 0x1 ++ ++#endif ++ ++/* ==========================================================================*/ ++/* IDC_ENABLE_REG */ ++#define IDC_ENR_ENABLE (0x01)//bit0 ++#define IDC_ENR_DISABLE (0x00) ++ ++/* IDC_CTRL_REG */ ++#define IDC_CTRL_IF (0x08)//bit3 ++#define IDC_CTRL_ACK (0x04)//bit2 ++#define IDC_CTRL_START (0x02)//bit1 ++#define IDC_CTRL_STOP (0x01)//bit0 ++#define IDC_CTRL_CLS (0x00) ++ ++#define IDC_FIFO_BUF_SIZE (63) ++ ++/* IDC_STS_REG */ ++#define IDC_STS_MODE (0x01)//1:master receiver; 0:master transmitter ++ ++/* IDC_FM_CTRL_REG */ ++ ++#define IDC_FMCTRL_IF (0x10)//bit4 ++#define IDC_FMCTRL_START (0x02)//bit1 ++#define IDC_FMCTRL_STOP (0x01)//bit0 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_platform_i2c { ++ int clk_limit; //Hz ++ int bulk_write_num; ++ unsigned int i2c_class; ++ u32 (*get_clock)(void); ++}; ++#define IDC_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(idc##id##_clk_limit, ¶m_ops_int, &(arg.clk_limit), perm); \ ++ module_param_cb(idc##id##_bulk_write_num, ¶m_ops_int, &(arg.bulk_write_num), perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_idc; ++extern struct platform_device gk_idc_hdmi; ++//extern struct platform_device gk_i2cmux; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IDC_H__ */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/io.h b/arch/arm/mach-gk710x/include/mach/io.h +new file mode 100644 +index 00000000..74fb7c4c +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/io.h +@@ -0,0 +1,506 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/io.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IO_H ++#define __MACH_IO_H ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#ifndef __ASSEMBLER__ ++ ++#include ++ ++extern spinlock_t gk_reg_lock; ++extern unsigned long gk_reg_flags; ++extern u32 gk_reglock_count; ++ ++extern struct hw_ops *g_hw; ++#define gk_hal_readb(a) g_hw->hw_readb((u32)(a)) ++#define gk_hal_readw(a) g_hw->hw_readw((u32)(a)) ++#define gk_hal_writeb(a,v) g_hw->hw_writeb((v),(u32)(a)) ++#define gk_hal_writew(a,v) g_hw->hw_writew((v),(u32)(a)) ++#define gk_hal_readl(a) g_hw->hw_readl((u32)(a)) ++#define gk_hal_writel(a,v) g_hw->hw_writel((v),(u32)(a)) ++#define gk_flash_read() g_hw->flash_read() ++#define gk_flash_write(v) g_hw->flash_write((v)) ++#if 0 ++#define GK_REG_LOCK() spin_lock_irqsave(&gk_reg_lock, gk_reg_flags) ++#define GK_REG_UNLOCK() spin_unlock_irqrestore(&gk_reg_lock, gk_reg_flags) ++#define GK_INC_REGLOCK_COUNT() gk_reglock_count++ ++#else ++#define GK_REG_LOCK() ++#define GK_REG_UNLOCK() ++#define GK_INC_REGLOCK_COUNT() ++#endif ++ ++#define HAL_IO(mod) \ ++unsigned char gk_##mod##_readb(unsigned int addr) \ ++{\ ++ return g_hw->hw_readb((u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readb);\ ++unsigned short gk_##mod##_readw(unsigned int addr) \ ++{\ ++ return g_hw->hw_readw((u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readw);\ ++unsigned int gk_##mod##_readl(unsigned int addr) \ ++{\ ++ return g_hw->hw_readl((u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readl);\ ++void gk_##mod##_writeb(unsigned int addr,unsigned char val) \ ++{\ ++ g_hw->hw_writeb((val),(u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writeb); \ ++void gk_##mod##_writew(unsigned int addr,unsigned short val) \ ++{\ ++ g_hw->hw_writew((val),(u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writew); \ ++void gk_##mod##_writel(unsigned int addr,unsigned int val) \ ++{\ ++ g_hw->hw_writel((val),(u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writel); ++#define DIR_IO(mod) \ ++unsigned char gk_##mod##_readb(unsigned int addr) \ ++{\ ++ return *((volatile unsigned char*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readb);\ ++unsigned short gk_##mod##_readw(unsigned int addr)\ ++{\ ++ return *((volatile unsigned short*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readw);\ ++unsigned int gk_##mod##_readl(unsigned int addr)\ ++{\ ++ return *((volatile unsigned int*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readl);\ ++void gk_##mod##_writeb(unsigned int addr,unsigned char val)\ ++{\ ++ *((volatile unsigned char*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writeb);\ ++void gk_##mod##_writew(unsigned int addr,unsigned short val)\ ++{\ ++ *((volatile unsigned short*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writew);\ ++void gk_##mod##_writel(unsigned int addr,unsigned int val)\ ++{\ ++ *((volatile unsigned int*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writel); ++ ++ ++#define IO_DEC(mod) \ ++extern unsigned char gk_##mod##_readb(unsigned int addr); \ ++extern unsigned short gk_##mod##_readw(unsigned int addr); \ ++extern unsigned int gk_##mod##_readl(unsigned int addr); \ ++extern void gk_##mod##_writeb(unsigned int addr,unsigned char val); \ ++extern void gk_##mod##_writew(unsigned int addr,unsigned short val); \ ++extern void gk_##mod##_writel(unsigned int addr,unsigned int val); ++ ++IO_DEC(hw) ++IO_DEC(adc) ++IO_DEC(aud) ++IO_DEC(cry) ++IO_DEC(ddr) ++IO_DEC(dma) ++IO_DEC(dsp) ++IO_DEC(eth) ++IO_DEC(greg) ++IO_DEC(gpio) ++IO_DEC(i2c) ++IO_DEC(i2s) ++IO_DEC(ir) ++IO_DEC(irq) ++IO_DEC(mcu) ++IO_DEC(pmu) ++IO_DEC(rct) ++IO_DEC(sd) ++IO_DEC(sf) ++IO_DEC(ssi) ++IO_DEC(timer) ++IO_DEC(uart) ++IO_DEC(usb) ++IO_DEC(vout) ++IO_DEC(wdt) ++IO_DEC(pwm) ++IO_DEC(efuse) ++ ++#define GK_HAL_OS_LOCK() \ ++ do { \ ++ GK_REG_LOCK(); \ ++ GK_INC_REGLOCK_COUNT(); \ ++ } while(0) ++ ++ ++#define GK_HAL_OS_UNLOCK() \ ++ do { \ ++ GK_REG_UNLOCK(); \ ++ } while(0) ++ ++//-------------------------------------- ++static inline u8 __gk_readb(const volatile void __iomem *address) ++{ ++ u8 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readb((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writeb(const volatile void __iomem *address, u8 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writeb((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++static inline u16 __gk_readw(const volatile void __iomem *address) ++{ ++ u16 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readw((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writew(const volatile void __iomem *address, u16 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writew((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++static inline u32 __gk_readl(const volatile void __iomem *address) ++{ ++ u32 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readl((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writel(const volatile void __iomem *address, u32 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writel((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++ ++ ++#if USB_DMA_ADD_MODE ++extern unsigned char (*gk_musb_readb)(unsigned int ptr, unsigned int offset); ++extern unsigned short (*gk_musb_readw)(unsigned int ptr, unsigned int offset); ++extern unsigned int (*gk_musb_readl)(unsigned int ptr, unsigned int offset); ++extern void (*gk_musb_writeb)(unsigned int ptr, unsigned int offset, unsigned char value); ++extern void (*gk_musb_writew)(unsigned int ptr, unsigned int offset, unsigned short value); ++extern void (*gk_musb_writel)(unsigned int ptr, unsigned int offset, unsigned int value); ++ ++#else ++#define gk_musb_readb(a, o) (*((volatile unsigned char*)(a+o))) ++#define gk_musb_readw(a, o) (*((volatile unsigned short*)(a+o))) ++#define gk_musb_readl(a, o) (*((volatile unsigned int*)(a+o))) ++#define gk_musb_writeb(a, o, v) ((*((volatile unsigned char*)(a+o))) = v) ++#define gk_musb_writew(a, o, v) ((*((volatile unsigned short*)(a+o))) = v) ++#define gk_musb_writel(a, o, v) ((*((volatile unsigned int*)(a+o))) = v) ++ ++#endif ++ ++#if SPI_API_MODE ++extern unsigned char (*gk_spi_readb)(unsigned int ptr); ++extern unsigned short (*gk_spi_readw)(unsigned int ptr); ++extern unsigned int (*gk_spi_readl)(unsigned int ptr); ++extern void (*gk_spi_writeb)(unsigned int ptr, unsigned char value); ++extern void (*gk_spi_writew)(unsigned int ptr, unsigned short value); ++extern void (*gk_spi_writel)(unsigned int ptr, unsigned int value); ++#else ++#define gk_spi_readb(a) gk_hal_readb(a) ++#define gk_spi_readw(a) gk_hal_readw(a) ++#define gk_spi_readl(a) gk_hal_readl(a) ++#define gk_spi_writeb(a, v) gk_hal_writeb((a), v) ++#define gk_spi_writew(a, v) gk_hal_writew((a), v) ++#define gk_spi_writel(a, v) gk_hal_writel((a), v) ++#endif ++ ++ ++#define gk_adc_setbitsb(v, mask) gk_adc_writeb((v),(gk_adc_readb((v)) | (mask))) ++#define gk_adc_setbitsw(v, mask) gk_adc_writew((v),(gk_adc_readw((v)) | (mask))) ++#define gk_adc_setbitsl(v, mask) gk_adc_writel((v),(gk_adc_readl((v)) | (mask))) ++#define gk_adc_clrbitsb(v, mask) gk_adc_writeb((v),(gk_adc_readb((v)) & ~(mask))) ++#define gk_adc_clrbitsw(v, mask) gk_adc_writew((v),(gk_adc_readw((v)) & ~(mask))) ++#define gk_adc_clrbitsl(v, mask) gk_adc_writel((v),(gk_adc_readl((v)) & ~(mask))) ++#define gk_adc_tstbitsb(v, mask) (gk_adc_readb((v)) & (mask)) ++#define gk_adc_tstbitsw(v, mask) (gk_adc_readw((v)) & (mask)) ++#define gk_adc_tstbitsl(v, mask) (gk_adc_readl((v)) & (mask)) ++ ++ ++ ++#define gk_aud_setbitsb(v, mask) gk_aud_writeb((v),(gk_aud_readb((v)) | (mask))) ++#define gk_aud_setbitsw(v, mask) gk_aud_writew((v),(gk_aud_readw((v)) | (mask))) ++#define gk_aud_setbitsl(v, mask) gk_aud_writel((v),(gk_aud_readl((v)) | (mask))) ++#define gk_aud_clrbitsb(v, mask) gk_aud_writeb((v),(gk_aud_readb((v)) & ~(mask))) ++#define gk_aud_clrbitsw(v, mask) gk_aud_writew((v),(gk_aud_readw((v)) & ~(mask))) ++#define gk_aud_clrbitsl(v, mask) gk_aud_writel((v),(gk_aud_readl((v)) & ~(mask))) ++#define gk_aud_tstbitsb(v, mask) (gk_aud_readb((v)) & (mask)) ++#define gk_aud_tstbitsw(v, mask) (gk_aud_readw((v)) & (mask)) ++#define gk_aud_tstbitsl(v, mask) (gk_aud_readl((v)) & (mask)) ++ ++ ++ ++ ++#define gk_cry_setbitsb(v, mask) gk_cry_writeb((v),(gk_cry_readb((v)) | (mask))) ++#define gk_cry_setbitsw(v, mask) gk_cry_writew((v),(gk_cry_readw((v)) | (mask))) ++#define gk_cry_setbitsl(v, mask) gk_cry_writel((v),(gk_cry_readl((v)) | (mask))) ++#define gk_cry_clrbitsb(v, mask) gk_cry_writeb((v),(gk_cry_readb((v)) & ~(mask))) ++#define gk_cry_clrbitsw(v, mask) gk_cry_writew((v),(gk_cry_readw((v)) & ~(mask))) ++#define gk_cry_clrbitsl(v, mask) gk_cry_writel((v),(gk_cry_readl((v)) & ~(mask))) ++#define gk_cry_tstbitsb(v, mask) (gk_cry_readb((v)) & (mask)) ++#define gk_cry_tstbitsw(v, mask) (gk_cry_readw((v)) & (mask)) ++#define gk_cry_tstbitsl(v, mask) (gk_cry_readl((v)) & (mask)) ++ ++ ++#define gk_ddr_setbitsb(v, mask) gk_ddr_writeb((v),(gk_ddr_readb((v)) | (mask))) ++#define gk_ddr_setbitsw(v, mask) gk_ddr_writew((v),(gk_ddr_readw((v)) | (mask))) ++#define gk_ddr_setbitsl(v, mask) gk_ddr_writel((v),(gk_ddr_readl((v)) | (mask))) ++#define gk_ddr_clrbitsb(v, mask) gk_ddr_writeb((v),(gk_ddr_readb((v)) & ~(mask))) ++#define gk_ddr_clrbitsw(v, mask) gk_ddr_writew((v),(gk_ddr_readw((v)) & ~(mask))) ++#define gk_ddr_clrbitsl(v, mask) gk_ddr_writel((v),(gk_ddr_readl((v)) & ~(mask))) ++#define gk_ddr_tstbitsb(v, mask) (gk_ddr_readb((v)) & (mask)) ++#define gk_ddr_tstbitsw(v, mask) (gk_ddr_readw((v)) & (mask)) ++#define gk_ddr_tstbitsl(v, mask) (gk_ddr_readl((v)) & (mask)) ++ ++ ++ ++#define gk_dsp_setbitsb(v, mask) gk_dsp_writeb((v),(gk_dsp_readb((v)) | (mask))) ++#define gk_dsp_setbitsw(v, mask) gk_dsp_writew((v),(gk_dsp_readw((v)) | (mask))) ++#define gk_dsp_setbitsl(v, mask) gk_dsp_writel((v),(gk_dsp_readl((v)) | (mask))) ++#define gk_dsp_clrbitsb(v, mask) gk_dsp_writeb((v),(gk_dsp_readb((v)) & ~(mask))) ++#define gk_dsp_clrbitsw(v, mask) gk_dsp_writew((v),(gk_dsp_readw((v)) & ~(mask))) ++#define gk_dsp_clrbitsl(v, mask) gk_dsp_writel((v),(gk_dsp_readl((v)) & ~(mask))) ++#define gk_dsp_tstbitsb(v, mask) (gk_dsp_readb((v)) & (mask)) ++#define gk_dsp_tstbitsw(v, mask) (gk_dsp_readw((v)) & (mask)) ++#define gk_dsp_tstbitsl(v, mask) (gk_dsp_readl((v)) & (mask)) ++ ++ ++#define gk_eth_setbitsb(v, mask) gk_eth_writeb((v),(gk_eth_readb((v)) | (mask))) ++#define gk_eth_setbitsw(v, mask) gk_eth_writew((v),(gk_eth_readw((v)) | (mask))) ++#define gk_eth_setbitsl(v, mask) gk_eth_writel((v),(gk_eth_readl((v)) | (mask))) ++#define gk_eth_clrbitsb(v, mask) gk_eth_writeb((v),(gk_eth_readb((v)) & ~(mask))) ++#define gk_eth_clrbitsw(v, mask) gk_eth_writew((v),(gk_eth_readw((v)) & ~(mask))) ++#define gk_eth_clrbitsl(v, mask) gk_eth_writel((v),(gk_eth_readl((v)) & ~(mask))) ++#define gk_eth_tstbitsb(v, mask) (gk_eth_readb((v)) & (mask)) ++#define gk_eth_tstbitsw(v, mask) (gk_eth_readw((v)) & (mask)) ++#define gk_eth_tstbitsl(v, mask) (gk_eth_readl((v)) & (mask)) ++ ++ ++#define gk_greg_setbitsb(v, mask) gk_greg_writeb((v),(gk_greg_readb((v)) | (mask))) ++#define gk_greg_setbitsw(v, mask) gk_greg_writew((v),(gk_greg_readw((v)) | (mask))) ++#define gk_greg_setbitsl(v, mask) gk_greg_writel((v),(gk_greg_readl((v)) | (mask))) ++#define gk_greg_clrbitsb(v, mask) gk_greg_writeb((v),(gk_greg_readb((v)) & ~(mask))) ++#define gk_greg_clrbitsw(v, mask) gk_greg_writew((v),(gk_greg_readw((v)) & ~(mask))) ++#define gk_greg_clrbitsl(v, mask) gk_greg_writel((v),(gk_greg_readl((v)) & ~(mask))) ++#define gk_greg_tstbitsb(v, mask) (gk_greg_readb((v)) & (mask)) ++#define gk_greg_tstbitsw(v, mask) (gk_greg_readw((v)) & (mask)) ++#define gk_greg_tstbitsl(v, mask) (gk_greg_readl((v)) & (mask)) ++ ++#define gk_gpio_setbitsb(v, mask) gk_gpio_writeb((v),(gk_gpio_readb((v)) | (mask))) ++#define gk_gpio_setbitsw(v, mask) gk_gpio_writew((v),(gk_gpio_readw((v)) | (mask))) ++#define gk_gpio_setbitsl(v, mask) gk_gpio_writel((v),(gk_gpio_readl((v)) | (mask))) ++#define gk_gpio_clrbitsb(v, mask) gk_gpio_writeb((v),(gk_gpio_readb((v)) & ~(mask))) ++#define gk_gpio_clrbitsw(v, mask) gk_gpio_writew((v),(gk_gpio_readw((v)) & ~(mask))) ++#define gk_gpio_clrbitsl(v, mask) gk_gpio_writel((v),(gk_gpio_readl((v)) & ~(mask))) ++#define gk_gpio_tstbitsb(v, mask) (gk_gpio_readb((v)) & (mask)) ++#define gk_gpio_tstbitsw(v, mask) (gk_gpio_readw((v)) & (mask)) ++#define gk_gpio_tstbitsl(v, mask) (gk_gpio_readl((v)) & (mask)) ++ ++#define gk_i2c_setbitsb(v, mask) gk_i2c_writeb((v),(gk_i2c_readb((v)) | (mask))) ++#define gk_i2c_setbitsw(v, mask) gk_i2c_writew((v),(gk_i2c_readw((v)) | (mask))) ++#define gk_i2c_setbitsl(v, mask) gk_i2c_writel((v),(gk_i2c_readl((v)) | (mask))) ++#define gk_i2c_clrbitsb(v, mask) gk_i2c_writeb((v),(gk_i2c_readb((v)) & ~(mask))) ++#define gk_i2c_clrbitsw(v, mask) gk_i2c_writew((v),(gk_i2c_readw((v)) & ~(mask))) ++#define gk_i2c_clrbitsl(v, mask) gk_i2c_writel((v),(gk_i2c_readl((v)) & ~(mask))) ++#define gk_i2c_tstbitsb(v, mask) (gk_i2c_readb((v)) & (mask)) ++#define gk_i2c_tstbitsw(v, mask) (gk_i2c_readw((v)) & (mask)) ++#define gk_i2c_tstbitsl(v, mask) (gk_i2c_readl((v)) & (mask)) ++ ++ ++#define gk_i2s_setbitsb(v, mask) gk_i2s_writeb((v),(gk_i2s_readb((v)) | (mask))) ++#define gk_i2s_setbitsw(v, mask) gk_i2s_writew((v),(gk_i2s_readw((v)) | (mask))) ++#define gk_i2s_setbitsl(v, mask) gk_i2s_writel((v),(gk_i2s_readl((v)) | (mask))) ++#define gk_i2s_clrbitsb(v, mask) gk_i2s_writeb((v),(gk_i2s_readb((v)) & ~(mask))) ++#define gk_i2s_clrbitsw(v, mask) gk_i2s_writew((v),(gk_i2s_readw((v)) & ~(mask))) ++#define gk_i2s_clrbitsl(v, mask) gk_i2s_writel((v),(gk_i2s_readl((v)) & ~(mask))) ++#define gk_i2s_tstbitsb(v, mask) (gk_i2s_readb((v)) & (mask)) ++#define gk_i2s_tstbitsw(v, mask) (gk_i2s_readw((v)) & (mask)) ++#define gk_i2s_tstbitsl(v, mask) (gk_i2s_readl((v)) & (mask)) ++ ++#define gk_ir_setbitsb(v, mask) gk_ir_writeb((v),(gk_ir_readb((v)) | (mask))) ++#define gk_ir_setbitsw(v, mask) gk_ir_writew((v),(gk_ir_readw((v)) | (mask))) ++#define gk_ir_setbitsl(v, mask) gk_ir_writel((v),(gk_ir_readl((v)) | (mask))) ++#define gk_ir_clrbitsb(v, mask) gk_ir_writeb((v),(gk_ir_readb((v)) & ~(mask))) ++#define gk_ir_clrbitsw(v, mask) gk_ir_writew((v),(gk_ir_readw((v)) & ~(mask))) ++#define gk_ir_clrbitsl(v, mask) gk_ir_writel((v),(gk_ir_readl((v)) & ~(mask))) ++#define gk_ir_tstbitsb(v, mask) (gk_ir_readb((v)) & (mask)) ++#define gk_ir_tstbitsw(v, mask) (gk_ir_readw((v)) & (mask)) ++#define gk_ir_tstbitsl(v, mask) (gk_ir_readl((v)) & (mask)) ++ ++#define gk_irq_setbitsb(v, mask) gk_irq_writeb((v),(gk_irq_readb((v)) | (mask))) ++#define gk_irq_setbitsw(v, mask) gk_irq_writew((v),(gk_irq_readw((v)) | (mask))) ++#define gk_irq_setbitsl(v, mask) gk_irq_writel((v),(gk_irq_readl((v)) | (mask))) ++#define gk_irq_clrbitsb(v, mask) gk_irq_writeb((v),(gk_irq_readb((v)) & ~(mask))) ++#define gk_irq_clrbitsw(v, mask) gk_irq_writew((v),(gk_irq_readw((v)) & ~(mask))) ++#define gk_irq_clrbitsl(v, mask) gk_irq_writel((v),(gk_irq_readl((v)) & ~(mask))) ++#define gk_irq_tstbitsb(v, mask) (gk_irq_readb((v)) & (mask)) ++#define gk_irq_tstbitsw(v, mask) (gk_irq_readw((v)) & (mask)) ++#define gk_irq_tstbitsl(v, mask) (gk_irq_readl((v)) & (mask)) ++ ++#define gk_mcu_setbitsb(v, mask) gk_mcu_writeb((v),(gk_mcu_readb((v)) | (mask))) ++#define gk_mcu_setbitsw(v, mask) gk_mcu_writew((v),(gk_mcu_readw((v)) | (mask))) ++#define gk_mcu_setbitsl(v, mask) gk_mcu_writel((v),(gk_mcu_readl((v)) | (mask))) ++#define gk_mcu_clrbitsb(v, mask) gk_mcu_writeb((v),(gk_mcu_readb((v)) & ~(mask))) ++#define gk_mcu_clrbitsw(v, mask) gk_mcu_writew((v),(gk_mcu_readw((v)) & ~(mask))) ++#define gk_mcu_clrbitsl(v, mask) gk_mcu_writel((v),(gk_mcu_readl((v)) & ~(mask))) ++#define gk_mcu_tstbitsb(v, mask) (gk_mcu_readb((v)) & (mask)) ++#define gk_mcu_tstbitsw(v, mask) (gk_mcu_readw((v)) & (mask)) ++#define gk_mcu_tstbitsl(v, mask) (gk_mcu_readl((v)) & (mask)) ++ ++#define gk_pwm_setbitsb(v, mask) gk_pwm_writeb((v),(gk_pwm_readb((v)) | (mask))) ++#define gk_pwm_setbitsw(v, mask) gk_pwm_writew((v),(gk_pwm_readw((v)) | (mask))) ++#define gk_pwm_setbitsl(v, mask) gk_pwm_writel((v),(gk_pwm_readl((v)) | (mask))) ++#define gk_pwm_clrbitsb(v, mask) gk_pwm_writeb((v),(gk_pwm_readb((v)) & ~(mask))) ++#define gk_pwm_clrbitsw(v, mask) gk_pwm_writew((v),(gk_pwm_readw((v)) & ~(mask))) ++#define gk_pwm_clrbitsl(v, mask) gk_pwm_writel((v),(gk_pwm_readl((v)) & ~(mask))) ++#define gk_pwm_tstbitsb(v, mask) (gk_pwm_readb((v)) & (mask)) ++#define gk_pwm_tstbitsw(v, mask) (gk_pwm_readw((v)) & (mask)) ++#define gk_pwm_tstbitsl(v, mask) (gk_pwm_readl((v)) & (mask)) ++ ++#define gk_rct_setbitsb(v, mask) gk_rct_writeb((v),(gk_rct_readb((v)) | (mask))) ++#define gk_rct_setbitsw(v, mask) gk_rct_writew((v),(gk_rct_readw((v)) | (mask))) ++#define gk_rct_setbitsl(v, mask) gk_rct_writel((v),(gk_rct_readl((v)) | (mask))) ++#define gk_rct_clrbitsb(v, mask) gk_rct_writeb((v),(gk_rct_readb((v)) & ~(mask))) ++#define gk_rct_clrbitsw(v, mask) gk_rct_writew((v),(gk_rct_readw((v)) & ~(mask))) ++#define gk_rct_clrbitsl(v, mask) gk_rct_writel((v),(gk_rct_readl((v)) & ~(mask))) ++#define gk_rct_tstbitsb(v, mask) (gk_rct_readb((v)) & (mask)) ++#define gk_rct_tstbitsw(v, mask) (gk_rct_readw((v)) & (mask)) ++#define gk_rct_tstbitsl(v, mask) (gk_rct_readl((v)) & (mask)) ++ ++#define gk_sd_setbitsb(v, mask) gk_sd_writeb((v),(gk_sd_readb((v)) | (mask))) ++#define gk_sd_setbitsw(v, mask) gk_sd_writew((v),(gk_sd_readw((v)) | (mask))) ++#define gk_sd_setbitsl(v, mask) gk_sd_writel((v),(gk_sd_readl((v)) | (mask))) ++#define gk_sd_clrbitsb(v, mask) gk_sd_writeb((v),(gk_sd_readb((v)) & ~(mask))) ++#define gk_sd_clrbitsw(v, mask) gk_sd_writew((v),(gk_sd_readw((v)) & ~(mask))) ++#define gk_sd_clrbitsl(v, mask) gk_sd_writel((v),(gk_sd_readl((v)) & ~(mask))) ++#define gk_sd_tstbitsb(v, mask) (gk_sd_readb((v)) & (mask)) ++#define gk_sd_tstbitsw(v, mask) (gk_sd_readw((v)) & (mask)) ++#define gk_sd_tstbitsl(v, mask) (gk_sd_readl((v)) & (mask)) ++ ++#define gk_sf_setbitsb(v, mask) gk_sf_writeb((v),(gk_sf_readb((v)) | (mask))) ++#define gk_sf_setbitsw(v, mask) gk_sf_writew((v),(gk_sf_readw((v)) | (mask))) ++#define gk_sf_setbitsl(v, mask) gk_sf_writel((v),(gk_sf_readl((v)) | (mask))) ++#define gk_sf_clrbitsb(v, mask) gk_sf_writeb((v),(gk_sf_readb((v)) & ~(mask))) ++#define gk_sf_clrbitsw(v, mask) gk_sf_writew((v),(gk_sf_readw((v)) & ~(mask))) ++#define gk_sf_clrbitsl(v, mask) gk_sf_writel((v),(gk_sf_readl((v)) & ~(mask))) ++#define gk_sf_tstbitsb(v, mask) (gk_sf_readb((v)) & (mask)) ++#define gk_sf_tstbitsw(v, mask) (gk_sf_readw((v)) & (mask)) ++#define gk_sf_tstbitsl(v, mask) (gk_sf_readl((v)) & (mask)) ++ ++#define gk_ssi_setbitsb(v, mask) gk_ssi_writeb((v),(gk_ssi_readb((v)) | (mask))) ++#define gk_ssi_setbitsw(v, mask) gk_ssi_writew((v),(gk_ssi_readw((v)) | (mask))) ++#define gk_ssi_setbitsl(v, mask) gk_ssi_writel((v),(gk_ssi_readl((v)) | (mask))) ++#define gk_ssi_clrbitsb(v, mask) gk_ssi_writeb((v),(gk_ssi_readb((v)) & ~(mask))) ++#define gk_ssi_clrbitsw(v, mask) gk_ssi_writew((v),(gk_ssi_readw((v)) & ~(mask))) ++#define gk_ssi_clrbitsl(v, mask) gk_ssi_writel((v),(gk_ssi_readl((v)) & ~(mask))) ++#define gk_ssi_tstbitsb(v, mask) (gk_ssi_readb((v)) & (mask)) ++#define gk_ssi_tstbitsw(v, mask) (gk_ssi_readw((v)) & (mask)) ++#define gk_ssi_tstbitsl(v, mask) (gk_ssi_readl((v)) & (mask)) ++ ++#define gk_timer_setbitsb(v, mask) gk_timer_writeb((v),(gk_timer_readb((v)) | (mask))) ++#define gk_timer_setbitsw(v, mask) gk_timer_writew((v),(gk_timer_readw((v)) | (mask))) ++#define gk_timer_setbitsl(v, mask) gk_timer_writel((v),(gk_timer_readl((v)) | (mask))) ++#define gk_timer_clrbitsb(v, mask) gk_timer_writeb((v),(gk_timer_readb((v)) & ~(mask))) ++#define gk_timer_clrbitsw(v, mask) gk_timer_writew((v),(gk_timer_readw((v)) & ~(mask))) ++#define gk_timer_clrbitsl(v, mask) gk_timer_writel((v),(gk_timer_readl((v)) & ~(mask))) ++#define gk_timer_tstbitsb(v, mask) (gk_timer_readb((v)) & (mask)) ++#define gk_timer_tstbitsw(v, mask) (gk_timer_readw((v)) & (mask)) ++#define gk_timer_tstbitsl(v, mask) (gk_timer_readl((v)) & (mask)) ++ ++#define gk_uart_setbitsb(v, mask) gk_uart_writeb((v),(gk_uart_readb((v)) | (mask))) ++#define gk_uart_setbitsw(v, mask) gk_uart_writew((v),(gk_uart_readw((v)) | (mask))) ++#define gk_uart_setbitsl(v, mask) gk_uart_writel((v),(gk_uart_readl((v)) | (mask))) ++#define gk_uart_clrbitsb(v, mask) gk_uart_writeb((v),(gk_uart_readb((v)) & ~(mask))) ++#define gk_uart_clrbitsw(v, mask) gk_uart_writew((v),(gk_uart_readw((v)) & ~(mask))) ++#define gk_uart_clrbitsl(v, mask) gk_uart_writel((v),(gk_uart_readl((v)) & ~(mask))) ++#define gk_uart_tstbitsb(v, mask) (gk_uart_readb((v)) & (mask)) ++#define gk_uart_tstbitsw(v, mask) (gk_uart_readw((v)) & (mask)) ++#define gk_uart_tstbitsl(v, mask) (gk_uart_readl((v)) & (mask)) ++ ++#define gk_usb_setbitsb(v, mask) gk_usb_writeb((v),(gk_usb_readb((v)) | (mask))) ++#define gk_usb_setbitsw(v, mask) gk_usb_writew((v),(gk_usb_readw((v)) | (mask))) ++#define gk_usb_setbitsl(v, mask) gk_usb_writel((v),(gk_usb_readl((v)) | (mask))) ++#define gk_usb_clrbitsb(v, mask) gk_usb_writeb((v),(gk_usb_readb((v)) & ~(mask))) ++#define gk_usb_clrbitsw(v, mask) gk_usb_writew((v),(gk_usb_readw((v)) & ~(mask))) ++#define gk_usb_clrbitsl(v, mask) gk_usb_writel((v),(gk_usb_readl((v)) & ~(mask))) ++#define gk_usb_tstbitsb(v, mask) (gk_usb_readb((v)) & (mask)) ++#define gk_usb_tstbitsw(v, mask) (gk_usb_readw((v)) & (mask)) ++#define gk_usb_tstbitsl(v, mask) (gk_usb_readl((v)) & (mask)) ++ ++#define gk_vout_setbitsb(v, mask) gk_vout_writeb((v),(gk_vout_readb((v)) | (mask))) ++#define gk_vout_setbitsw(v, mask) gk_vout_writew((v),(gk_vout_readw((v)) | (mask))) ++#define gk_vout_setbitsl(v, mask) gk_vout_writel((v),(gk_vout_readl((v)) | (mask))) ++#define gk_vout_clrbitsb(v, mask) gk_vout_writeb((v),(gk_vout_readb((v)) & ~(mask))) ++#define gk_vout_clrbitsw(v, mask) gk_vout_writew((v),(gk_vout_readw((v)) & ~(mask))) ++#define gk_vout_clrbitsl(v, mask) gk_vout_writel((v),(gk_vout_readl((v)) & ~(mask))) ++#define gk_vout_tstbitsb(v, mask) (gk_vout_readb((v)) & (mask)) ++#define gk_vout_tstbitsw(v, mask) (gk_vout_readw((v)) & (mask)) ++#define gk_vout_tstbitsl(v, mask) (gk_vout_readl((v)) & (mask)) ++ ++#define gk_wdt_setbitsb(v, mask) gk_wdt_writeb((v),(gk_wdt_readb((v)) | (mask))) ++#define gk_wdt_setbitsw(v, mask) gk_wdt_writew((v),(gk_wdt_readw((v)) | (mask))) ++#define gk_wdt_setbitsl(v, mask) gk_wdt_writel((v),(gk_wdt_readl((v)) | (mask))) ++#define gk_wdt_clrbitsb(v, mask) gk_wdt_writeb((v),(gk_wdt_readb((v)) & ~(mask))) ++#define gk_wdt_clrbitsw(v, mask) gk_wdt_writew((v),(gk_wdt_readw((v)) & ~(mask))) ++#define gk_wdt_clrbitsl(v, mask) gk_wdt_writel((v),(gk_wdt_readl((v)) & ~(mask))) ++#define gk_wdt_tstbitsb(v, mask) (gk_wdt_readb((v)) & (mask)) ++#define gk_wdt_tstbitsw(v, mask) (gk_wdt_readw((v)) & (mask)) ++#define gk_wdt_tstbitsl(v, mask) (gk_wdt_readl((v)) & (mask)) ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IO_H */ +diff --git a/arch/arm/mach-gk710x/include/mach/ir.h b/arch/arm/mach-gk710x/include/mach/ir.h +new file mode 100644 +index 00000000..2bf5ca2e +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/ir.h +@@ -0,0 +1,50 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/mach/ir.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IR_H ++#define __MACH_IR_H ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++enum gk_ir_protocol { ++ GK_IR_PROTOCOL_NEC = 0, ++ GK_IR_PROTOCOL_PANASONIC = 1, ++ GK_IR_PROTOCOL_SONY = 2, ++ GK_IR_PROTOCOL_PHILIPS = 3, ++ GK_IR_PROTOCOL_END ++}; ++ ++struct gk_ir_controller { ++ ++ int protocol; ++ int debug; ++}; ++#define GK_IR_PARAM_CALL(arg, perm) \ ++ module_param_cb(ir_protocol, ¶m_ops_int, &arg.protocol, perm); \ ++ module_param_cb(ir_debug, ¶m_ops_int, &arg.debug, perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_ir; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IR_H */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/irqs.h b/arch/arm/mach-gk710x/include/mach/irqs.h +new file mode 100644 +index 00000000..6a01df2f +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/irqs.h +@@ -0,0 +1,198 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/irqs.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IRQS_H ++#define __MACH_IRQS_H ++ ++#include ++#define NR_IRQS 128 ++ ++#define NR_VIC_IRQ_SIZE (32) ++ ++#define VIC1_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 0)) ++#define VIC2_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 1)) ++//#define VIC3_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 2)) ++//#define VIC4_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 3)) ++ ++/* The following are ARCH specific IRQ numbers */ ++ ++#define VIC_INSTANCES 2 ++ ++#define NR_VIC_IRQS (VIC_INSTANCES * NR_VIC_IRQ_SIZE) ++#define GPIO_INT_VEC(x) (NR_VIC_IRQS + x) ++ ++// VIC Instance 1 ++#define SSI_SLAVE_IRQ 0 ++#define ETH_IRQ 1 ++#define ICORE_ERROR_IRQ 2 ++#define GPIO2_IRQ 4 ++#define CD2ND_BIT_CD_IRQ 5 ++#define USBVBUS_IRQ 6 ++#define VO_IRQ 7 ++#define DSP_VO1_IRQ 7 ++#define SD_IRQ 8 ++#define IDC_IRQ 9 ++#define SSI_IRQ 10 ++#define WDT_IRQ 11 ++#define IRIF_IRQ 12 ++#define CFCD1_IRQ 13 ++#define SDCD_IRQ 14 /* SD0 SD card card detection. */ ++#define UART1_IRQ 15 ++#define GPIO0_IRQ 16 ++#define GPIO1_IRQ 17 ++#define TIMER1_IRQ 18 ++#define TIMER2_IRQ 19 ++#define TIMER3_IRQ 20 ++#define DMA_IRQ 21 ++#define FIOCMD_IRQ 22 ++#define FIODMA_IRQ 23 ++#define VI_IRQ 24 ++#define DSP_VI_IRQ 24 ++#define VCORE_IRQ 25 ++#define DSP_VCORE_IRQ 25 ++#define USBC_IRQ 26 ++#define UART2_IRQ 27 ++#define HIF2_IRQ 28 ++#define I2STX_IRQ 29 ++#define I2SRX_IRQ 30 ++#define UART0_IRQ 31 ++ ++// VIC Instance 2 ++#define DMA_FIOS_IRQ (32 + 7) ++#define VO0_TV_SYNC_IRQ (32 + 16) ++#define VO1_LCD_SYNC_IRQ (32 + 17) ++#define DSP_VO0_IRQ (32 + 18) ++#define AES_IRQ (32 + 19) ++#define DES_IRQ (32 + 20) ++#define MDMA_IRQ (32 + 22) ++#define MOTOR_IRQ (32 + 23) ++#define ADC_LEVEL_IRQ (32 + 24) ++#define IDC_HDMI_IRQ (32 + 26) ++#define ICORE_LAST_PIXEL_IRQ (32 + 27) ++#define ICORE_VSYNC_IRQ (32 + 28) ++#define ICORE_SENSOR_VSYNC_IRQ (32 + 29) ++#define HDMI_IRQ (32 + 30) ++#define SSI2_IRQ (32 + 31) ++ ++#define MAX_IRQ_NUM (SSI2_IRQ + 1) ++#define IR_IRQ HDMI_IRQ ++ ++ ++//#define MAX_IRQ_NUM (MOTOR_IRQ + 1) ++ ++#define GPIO_IRQ(x) ((x) + NR_VIC_IRQS) ++ ++ ++#define VIC_IRQ(x) (x) ++ ++ ++/* ++ * VIC trigger types (SW definition). ++ */ ++#define VIRQ_RISING_EDGE 0 ++#define VIRQ_FALLING_EDGE 1 ++#define VIRQ_BOTH_EDGES 2 ++#define VIRQ_LEVEL_LOW 3 ++#define VIRQ_LEVEL_HIGH 4 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define VIC_IRQ_STA_OFFSET 0x30 ++#define VIC_FIQ_STA_OFFSET 0x34 ++#define VIC_RAW_STA_OFFSET 0x18 ++#define VIC_INT_SEL_OFFSET 0x0c ++#define VIC_INTEN_OFFSET 0x10 ++#define VIC_INTEN_CLR_OFFSET 0x14 ++#define VIC_SOFTEN_OFFSET 0x1c ++#define VIC_SOFTEN_CLR_OFFSET 0x20 ++#define VIC_PROTEN_OFFSET 0x24 ++#define VIC_SENSE_OFFSET 0x00 ++#define VIC_BOTHEDGE_OFFSET 0x08 ++#define VIC_EVENT_OFFSET 0x04 ++#define VIC_EDGE_CLR_OFFSET 0x38 ++ ++#define VIC1_BASE (GK_VA_VIC1) ++#define VIC2_BASE (GK_VA_VIC2) ++ ++#define VIC1_REG(x) (VIC1_BASE + (x)) ++#define VIC2_REG(x) (VIC2_BASE + (x)) ++ ++#define VIC_IRQ_STA_REG VIC1_REG(VIC_IRQ_STA_OFFSET) ++#define VIC_FIQ_STA_REG VIC1_REG(VIC_FIQ_STA_OFFSET) ++#define VIC_RAW_STA_REG VIC1_REG(VIC_RAW_STA_OFFSET) ++#define VIC_INT_SEL_REG VIC1_REG(VIC_INT_SEL_OFFSET) ++#define VIC_INTEN_REG VIC1_REG(VIC_INTEN_OFFSET) ++#define VIC_INTEN_CLR_REG VIC1_REG(VIC_INTEN_CLR_OFFSET) ++#define VIC_SOFTEN_REG VIC1_REG(VIC_SOFTEN_OFFSET) ++#define VIC_SOFTEN_CLR_REG VIC1_REG(VIC_SOFTEN_CLR_OFFSET) ++#define VIC_PROTEN_REG VIC1_REG(VIC_PROTEN_OFFSET) ++#define VIC_SENSE_REG VIC1_REG(VIC_SENSE_OFFSET) ++#define VIC_BOTHEDGE_REG VIC1_REG(VIC_BOTHEDGE_OFFSET) ++#define VIC_EVENT_REG VIC1_REG(VIC_EVENT_OFFSET) ++#define VIC_EDGE_CLR_REG VIC1_REG(VIC_EDGE_CLR_OFFSET) ++ ++#if (VIC_INSTANCES >= 2) ++ ++#define VIC2_IRQ_STA_REG VIC2_REG(VIC_IRQ_STA_OFFSET) ++#define VIC2_FIQ_STA_REG VIC2_REG(VIC_FIQ_STA_OFFSET) ++#define VIC2_RAW_STA_REG VIC2_REG(VIC_RAW_STA_OFFSET) ++#define VIC2_INT_SEL_REG VIC2_REG(VIC_INT_SEL_OFFSET) ++#define VIC2_INTEN_REG VIC2_REG(VIC_INTEN_OFFSET) ++#define VIC2_INTEN_CLR_REG VIC2_REG(VIC_INTEN_CLR_OFFSET) ++#define VIC2_SOFTEN_REG VIC2_REG(VIC_SOFTEN_OFFSET) ++#define VIC2_SOFTEN_CLR_REG VIC2_REG(VIC_SOFTEN_CLR_OFFSET) ++#define VIC2_PROTEN_REG VIC2_REG(VIC_PROTEN_OFFSET) ++#define VIC2_SENSE_REG VIC2_REG(VIC_SENSE_OFFSET) ++#define VIC2_BOTHEDGE_REG VIC2_REG(VIC_BOTHEDGE_OFFSET) ++#define VIC2_EVENT_REG VIC2_REG(VIC_EVENT_OFFSET) ++#define VIC2_EDGE_CLR_REG VIC2_REG(VIC_EDGE_CLR_OFFSET) ++ ++#endif ++ ++struct gk_irq_info ++{ ++ int irq_gpio; ++ int irq_line; ++ int irq_type; ++ int irq_gpio_val; ++ int irq_gpio_mode; ++}; ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++#ifndef __ASSEMBLY__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++struct pt_regs; ++ ++extern void gk_init_irq(void) __init; ++extern void gk_vic_handle_irq(struct pt_regs *regs); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++#endif /* __MACH_IRQS_H */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/rct.h b/arch/arm/mach-gk710x/include/mach/rct.h +new file mode 100644 +index 00000000..bff86cad +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/rct.h +@@ -0,0 +1,36 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/rct.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_RCT_H ++#define __MACH_RCT_H ++ ++/* ==============================================*/ ++#define GK_APB_FREQ 69000000 //20MHz ++#define GK_UART_FREQ 24000000 ++#define GK_SD_FREQ 48000000 ++ ++u32 get_apb_bus_freq_hz(void); ++u32 get_uart_freq_hz(void); ++u32 get_sd_freq_hz(void); ++u32 get_ssi0_freq_hz(void); ++u32 get_ssi1_freq_hz(void); ++ ++void set_sd_rct(u32 freq); ++ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710x/include/mach/sd.h b/arch/arm/mach-gk710x/include/mach/sd.h +new file mode 100644 +index 00000000..392a1ffa +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/sd.h +@@ -0,0 +1,423 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/mach/sd.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK_SD_H ++#define __MACH_GK_SD_H ++ ++#include ++ ++/* ==========================================================================*/ ++#define GK_SD_MAX_SLOT_NUM (2) ++ ++#define GK_SD_PRIVATE_CAPS_VDD_18 (0x1 << 0) ++#define GK_SD_PRIVATE_CAPS_ADMA (0x1 << 1) ++#define GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK (0x1 << 2) ++#define GK_SD_PRIVATE_CAPS_DDR (0x1 << 3) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_sd_slot { ++ struct mmc_host *pmmc_host; ++ ++ u32 default_caps; ++ u32 active_caps; ++ u32 default_caps2; ++ u32 active_caps2; ++ u32 private_caps; ++ ++ struct gk_gpio_io_info ext_power; ++ struct gk_gpio_io_info ext_reset; ++ int fixed_cd; ++ struct gk_irq_info gpio_cd; ++ u32 cd_delay; //jiffies ++ int fixed_wp; ++ struct gk_gpio_io_info gpio_wp; ++ ++ int (*check_owner)(void); ++ void (*request)(void); ++ void (*release)(void); ++ void (*set_int)(u32 mask, u32 on); ++ void (*set_vdd)(u32 vdd); ++ void (*set_bus_timing)(u32 timing); ++}; ++ ++struct gk_sd_controller { ++ u32 num_slots; ++ struct gk_sd_slot slot[GK_SD_MAX_SLOT_NUM]; ++ void (*set_pll)(u32); ++ u32 (*get_pll)(void); ++ ++ u32 max_blk_mask; ++ u32 max_clock; ++ u32 active_clock; ++ u32 wait_tmo; ++ u32 pwr_delay; //ms ++ ++ u32 dma_fix; ++ u32 support_pll_scaler; ++}; ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_sd0; ++ ++extern int gk_init_sd(void); ++extern void gk_detect_sd_slot(int bus, int slot, int fixed_cd); ++extern void gk_set_sd_detect_pin(u32 gpio_pin); ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#define SD_INSTANCES 1 ++#define SD_SUPPORT_PLL_SCALER 0 ++#define SD_HAS_INTERNAL_MUXER 1 ++#define SD_HAS_INTERNAL_2ND_CDWP 0 ++#define SD_HAS_DELAY_CTRL 0 ++#define SD_BUS_SWITCH_DLY 0 ++#define SD_HAS_IO_DRIVE_CTRL 1 ++ ++#define SD_HOST1_SUPPORT_XC 0 ++#define SD_HOST2_SUPPORT_XC 0 ++ ++#define SD_SUPPORT_ACMD23 1 ++ ++#define SD_HAS_SDXC_CLOCK 0 ++ ++#define SD_HOST1_HOST2_HAS_MUX 0 ++#define SD_SUPPORT_ADMA 0 ++ ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define SD_REG(x) (GK_VA_SDC + (x)) //(0xf0002000 + (x)) ++ ++#define SD_DMA_ADDR_OFFSET 0x000 ++#define SD_BLK_SZ_OFFSET 0x00c /* Half word */ ++#define SD_BLK_CNT_OFFSET 0x00a /* Half word */ ++#define SD_ARG_OFFSET 0x034 ++#define SD_XFR_OFFSET 0x004 /* Half word */ ++#define SD_CMD_OFFSET 0x016 /* Half word */ ++#define SD_RSP0_OFFSET 0x01c ++#define SD_RSP1_OFFSET 0x020 ++#define SD_RSP2_OFFSET 0x024 ++#define SD_RSP3_OFFSET 0x028 ++#define SD_DATA_OFFSET 0x040 ++#define SD_STA_OFFSET 0x030 ++#define SD_HOST_OFFSET 0x02c /* Byte */ ++#define SD_PWR_OFFSET 0x02d /* Byte */ ++#define SD_GAP_OFFSET 0x02e /* Byte */ ++#define SD_WAK_OFFSET 0x02f /* Byte */ ++#define SD_CLK_OFFSET 0x01a /* Half word */ ++#define SD_TMO_OFFSET 0x018 /* Byte */ ++#define SD_RESET_OFFSET 0x019 /* Byte */ ++#define SD_NIS_OFFSET 0x012 /* Half word */ ++#define SD_EIS_OFFSET 0x014 /* Half word */ ++#define SD_NISEN_OFFSET 0x00e /* Half word */ ++#define SD_EISEN_OFFSET 0x010 /* Half word */ ++#define SD_NIXEN_OFFSET 0x006 /* Half word */ ++#define SD_EIXEN_OFFSET 0x008 /* Half word */ ++#define SD_AC12ES_OFFSET 0x03c /* Half word */ ++#define SD_CAP_OFFSET 0x038 ++#define SD_CUR_OFFSET 0x048 ++#define SD_ADMA_STA_OFFSET 0x054 ++#define SD_ADMA_ADDR_OFFSET 0x058 ++#define SD_XC_CTR_OFFSET 0x060 ++#define SD_BOOT_CTR_OFFSET 0x070 ++#define SD_BOOT_STA_OFFSET 0x074 ++#define SD_VOL_SW_OFFSET 0x07c ++#define SD_SIST_OFFSET 0x0fc /* Half word */ ++#define SD_VER_OFFSET 0x0fe /* Half word */ ++ ++#define SD_DMA_ADDR_REG SD_REG(SD_DMA_ADDR_OFFSET) ++#define SD_BLK_SZ_REG SD_REG(SD_BLK_SZ_OFFSET) /* Half word */ ++#define SD_BLK_CNT_REG SD_REG(SD_BLK_CNT_OFFSET) /* Half word */ ++#define SD_ARG_REG SD_REG(SD_ARG_OFFSET) ++#define SD_XFR_REG SD_REG(SD_XFR_OFFSET) /* Half word */ ++#define SD_CMD_REG SD_REG(SD_CMD_OFFSET) /* Half word */ ++#define SD_RSP0_REG SD_REG(SD_RSP0_OFFSET) ++#define SD_RSP1_REG SD_REG(SD_RSP1_OFFSET) ++#define SD_RSP2_REG SD_REG(SD_RSP2_OFFSET) ++#define SD_RSP3_REG SD_REG(SD_RSP3_OFFSET) ++#define SD_DATA_REG SD_REG(SD_DATA_OFFSET) ++#define SD_STA_REG SD_REG(SD_STA_OFFSET) ++#define SD_HOST_REG SD_REG(SD_HOST_OFFSET) /* Byte */ ++#define SD_PWR_REG SD_REG(SD_PWR_OFFSET) /* Byte */ ++#define SD_GAP_REG SD_REG(SD_GAP_OFFSET) /* Byte */ ++#define SD_WAK_REG SD_REG(SD_WAK_OFFSET) /* Byte */ ++#define SD_CLK_REG SD_REG(SD_CLK_OFFSET) /* Half word */ ++#define SD_TMO_REG SD_REG(SD_TMO_OFFSET) /* Byte */ ++#define SD_RESET_REG SD_REG(SD_RESET_OFFSET) /* Byte */ ++#define SD_NIS_REG SD_REG(SD_NIS_OFFSET) /* Half word */ ++#define SD_EIS_REG SD_REG(SD_EIS_OFFSET) /* Half word */ ++#define SD_NISEN_REG SD_REG(SD_NISEN_OFFSET) /* Half word */ ++#define SD_EISEN_REG SD_REG(SD_EISEN_OFFSET) /* Half word */ ++#define SD_NIXEN_REG SD_REG(SD_NIXEN_OFFSET) /* Half word */ ++#define SD_EIXEN_REG SD_REG(SD_EIXEN_OFFSET) /* Half word */ ++#define SD_AC12ES_REG SD_REG(SD_AC12ES_OFFSET) /* Half word */ ++#define SD_CAP_REG SD_REG(SD_CAP_OFFSET) ++#define SD_CUR_REG SD_REG(SD_CUR_OFFSET) ++#define SD_ADMA_STA_REG SD_REG(SD_ADMA_STA_OFFSET) ++#define SD_ADMA_ADDR_REG SD_REG(SD_ADMA_ADDR_OFFSET) ++#define SD_XC_CTR_REG SD_REG(SD_XC_CTR_OFFSET) ++#define SD_BOOT_CTR_REG SD_REG(SD_BOOT_CTR_OFFSET) ++#define SD_BOOT_STA_REG SD_REG(SD_BOOT_STA_OFFSET) ++#define SD_VOL_SW_REG SD_REG(SD_VOL_SW_OFFSET) ++#define SD_SIST_REG SD_REG(SD_SIST_OFFSET) /* Half word */ ++#define SD_VER_REG SD_REG(SD_VER_OFFSET) /* Half word */ ++ ++/* SD_BLK_SZ_REG */ ++#define SD_BLK_SZ_4KB 0x0000 ++#define SD_BLK_SZ_8KB 0x1000 ++#define SD_BLK_SZ_16KB 0x2000 ++#define SD_BLK_SZ_32KB 0x3000 ++#define SD_BLK_SZ_64KB 0x4000 ++#define SD_BLK_SZ_128KB 0x5000 ++#define SD_BLK_SZ_256KB 0x6000 ++#define SD_BLK_SZ_512KB 0x7000 ++ ++/* SD_XFR_REG */ ++#define SD_XFR_MUL_SEL 0x0020 ++#define SD_XFR_SGL_SEL 0x0000 ++#define SD_XFR_CTH_SEL 0x0010 ++#define SD_XFR_HTC_SEL 0x0000 ++#define SD_XFR_DMA_EN 0x0004 ++#define SD_XFR_AC12_EN 0x0002 ++#define SD_XFR_BLKCNT_EN 0x0001 ++ ++/* SD_CMD_REG */ ++#define SD_CMD_IDX(x) ((x) << 8) ++#define SD_CMD_NORMAL 0x00000000 ++#define SD_CMD_SUSPEND 0x00000040 ++#define SD_CMD_RESUME 0x00000080 ++#define SD_CMD_ABORT 0x000000C0 ++#define SD_CMD_CHKIDX 0x00000020 ++#define SD_CMD_DATA 0x00000010 ++#define SD_CMD_CHKCRC 0x00000008 ++ ++#define SD_CMD_RSP_NONE 0x00000000 ++#define SD_CMD_RSP_136 0x00000001 ++#define SD_CMD_RSP_48 0x00000002 ++#define SD_CMD_RSP_48BUSY 0x00000003 ++ ++/* SD_STA_REG */ ++#define SD_STA_DAT_LSL(x) ((((x) & 0x1e000000) >> 25) |(((x) & 0x00f00000) >> 20)) ++#define SD_STA_CMD_LSL(x) (((x) & 0x01000000) >> 24) ++#define SD_STA_WPS_PL 0x00080000 ++#define SD_STA_CSS 0x00040000 ++#define SD_STA_CDP_L 0x00020000 ++#define SD_STA_CARD_INSERTED 0x00010000 ++#define SD_STA_BUFFER_READ_EN 0x00000800 ++#define SD_STA_WRITE_XFR_ACTIVE 0x00000400 ++#define SD_STA_BUFFER_WRITE_EN 0x00000200 ++#define SD_STA_READ_XFR_ACTIVE 0x00000100 ++#define SD_STA_CMD_INHIBIT_DAT 0x00000004 ++#define SD_STA_DAT_ACTIVE 0x00000002 ++#define SD_STA_CMD_INHIBIT_CMD 0x00000001 ++ ++#define SD_STA_WRITABLE 0 ++#define SD_STA_READ_ONLY 1 ++ ++/* SD_HOST_REG */ ++#define SD_HOST_HIGH_SPEED 0x08 ++#define SD_HOST_8BIT 0x04 ++#define SD_HOST_4BIT 0x02 ++#define SD_HOST_LED_ON 0x01 ++ ++/* SD_PWR_REG */ ++#define SD_PWR_3_3V 0x0e ++#define SD_PWR_3_0V 0x0c ++#define SD_PWR_1_8V 0x0a ++#define SD_PWR_ON 0x01 ++#define SD_PWR_OFF 0x00 ++ ++/* SD_GAP_REG */ ++#define SD_GAP_INT_AT_GAP 0x08 ++#define SD_GAP_CONT_REQ 0x04 ++#define SD_GAP_READ_WAIT 0x02 ++#define SD_GAP_STOP_AT_GAP 0x01 ++ ++/* SD_WAK_REG */ ++#define SD_WAK_ON_CARD_RMV 0x04 ++#define SD_WAK_ON_CARD_INT 0x02 ++#define SD_WAK_ON_CARD_IST 0x01 ++ ++/* SD_CLK_REG */ ++#define SD_CLK_DIV_256 0x8000 ++#define SD_CLK_DIV_128 0x4000 ++#define SD_CLK_DIV_64 0x2000 ++#define SD_CLK_DIV_32 0x1000 ++#define SD_CLK_DIV_16 0x0800 ++#define SD_CLK_DIV_8 0x0400 ++#define SD_CLK_DIV_4 0x0200 ++#define SD_CLK_DIV_2 0x0100 ++#define SD_CLK_DIV_1 0x0000 ++#define SD_CLK_EN 0x0004 ++#define SD_CLK_ICLK_STABLE 0x0002 ++#define SD_CLK_ICLK_EN 0x0001 ++ ++/* SD_TMO_REG */ ++/* SD_RESET_REG */ ++#define SD_RESET_DAT 0x04 ++#define SD_RESET_ALL 0x02 ++#define SD_RESET_CMD 0x01 ++ ++/* SD_NIS_REG */ ++#define SD_NIS_ERROR 0x8000 ++#define SD_NIS_CARD 0x0100 ++#define SD_NIS_REMOVAL 0x0080 ++#define SD_NIS_READ_READY 0x0040 ++#define SD_NIS_INSERT 0x0020 ++#define SD_NIS_WRITE_READY 0x0010 ++#define SD_NIS_XFR_DONE 0x0008 ++#define SD_NIS_DMA 0x0004 ++#define SD_NIS_BLOCK_GAP 0x0002 ++#define SD_NIS_CMD_DONE 0x0001 ++ ++/* SD_EIS_REG */ ++#define SD_EIS_ACMD12_ERR 0x0100 ++#define SD_EIS_CURRENT_ERR 0x0080 ++#define SD_EIS_DATA_BIT_ERR 0x0040 ++#define SD_EIS_DATA_CRC_ERR 0x0020 ++#define SD_EIS_DATA_TMOUT_ERR 0x0010 ++#define SD_EIS_CMD_IDX_ERR 0x0008 ++#define SD_EIS_CMD_BIT_ERR 0x0004 ++#define SD_EIS_CMD_CRC_ERR 0x0002 ++#define SD_EIS_CMD_TMOUT_ERR 0x0001 ++ ++ ++/* SD_NISEN_REG */ ++#define SD_NISEN_CARD 0x0100 ++#define SD_NISEN_REMOVAL 0x0080 ++#define SD_NISEN_INSERT 0x0040 ++#define SD_NISEN_READ_READY 0x0020 ++#define SD_NISEN_WRITE_READY 0x0010 ++#define SD_NISEN_DMA 0x0008 ++#define SD_NISEN_BLOCK_GAP 0x0004 ++#define SD_NISEN_XFR_DONE 0x0002 ++#define SD_NISEN_CMD_DONE 0x0001 ++ ++/* SD_EISEN_REG */ ++#define SD_EISEN_ADMA_ERR 0x0200 ++#define SD_EISEN_ACMD12_ERR 0x0100 ++#define SD_EISEN_CURRENT_ERR 0x0080 ++#define SD_EISEN_DATA_BIT_ERR 0x0040 ++#define SD_EISEN_DATA_TMOUT_ERR 0x0020 ++#define SD_EISEN_DATA_CRC_ERR 0x0010 ++#define SD_EISEN_CMD_IDX_ERR 0x0008 ++#define SD_EISEN_CMD_CRC_ERR 0x0004 ++#define SD_EISEN_CMD_BIT_ERR 0x0002 ++#define SD_EISEN_CMD_TMOUT_ERR 0x0001 ++ ++/* SD_NIXEN_REG */ ++#define SD_NIXEN_CARD 0x0100 ++#define SD_NIXEN_REMOVAL 0x0080 ++#define SD_NIXEN_INSERT 0x0040 ++#define SD_NIXEN_READ_READY 0x0020 ++#define SD_NIXEN_WRITE_READY 0x0010 ++#define SD_NIXEN_DMA 0x0008 ++#define SD_NIXEN_BLOCK_GAP 0x0004 ++#define SD_NIXEN_XFR_DONE 0x0002 ++#define SD_NIXEN_CMD_DONE 0x0001 ++ ++/* SD_EIXEN_REG */ ++#define SD_EISEN_ADMA_ERR 0x0200 ++#define SD_EIXEN_ACMD12_ERR 0x0100 ++#define SD_EIXEN_CURRENT_ERR 0x0080 ++#define SD_EIXEN_DATA_BIT_ERR 0x0040 ++#define SD_EIXEN_DATA_CRC_ERR 0x0020 ++#define SD_EIXEN_CMD_CRC_ERR 0x0010 ++#define SD_EIXEN_DATA_TMOUT_ERR 0x0008 ++#define SD_EIXEN_CMD_IDX_ERR 0x0004 ++#define SD_EIXEN_CMD_BIT_ERR 0x0002 ++#define SD_EIXEN_CMD_TMOUT_ERR 0x0001 ++ ++/* SD_AC12ES_REG */ ++#define SD_AC12ES_NOT_ISSUED 0x0040 ++#define SD_AC12ES_INDEX 0x0020 ++#define SD_AC12ES_NOT_EXECED 0x0010 ++#define SD_AC12ES_END_BIT 0x0004 ++#define SD_AC12ES_CRC_ERROR 0x0002 ++#define SD_AC12ES_TMOUT_ERROR 0x0001 ++ ++/* SD_ADMA_STA_REG */ ++#define SD_ADMA_STA_ST_STOP 0x00000000 ++#define SD_ADMA_STA_ST_FDS 0x00000001 ++#define SD_ADMA_STA_ST_TFR 0x00000003 ++#define SD_ADMA_STA_LEN_ERR 0x00000004 ++ ++/* SD_CAP_REG */ ++#define SD_CAP_INTMODE 0x08000000 ++#define SD_CAP_VOL_1_8V 0x04000000 ++#define SD_CAP_VOL_3_0V 0x02000000 ++#define SD_CAP_VOL_3_3V 0x01000000 ++#define SD_CAP_DMA 0x00800000 ++#define SD_CAP_SUS_RES 0x00400000 ++#define SD_CAP_HIGH_SPEED 0x00200000 ++//#define SD_CAP_ADMA_SUPPORT 0x00080000 ++#define SD_CAP_MAX_512B_BLK 0x00000000 ++#define SD_CAP_MAX_1KB_BLK 0x00010000 ++#define SD_CAP_MAX_2KB_BLK 0x00020000 ++#define SD_CAP_BASE_FREQ(x) (((x) & 0x3f00) >> 8) ++#define SD_CAP_TOCLK_KHZ 0x00000000 ++#define SD_CAP_TOCLK_MHZ 0x00000080 ++#define SD_CAP_TOCLK_FREQ(x) (((x) & 0x3f)) ++ ++/* SD_XC_CTR_REG */ ++#define SD_XC_CTR_DDR_EN 0x00008000 ++#define SD_XC_CTR_VOL_1_8V 0x00000001 ++#define SD_XC_CTR_VOL_3_3V 0x00000000 ++ ++/* SD_BOOT_CTR_REG */ ++#define SD_BOOT_CTR_RST_EN 0x00010000 ++ ++/* SD_BOOT_STA_REG */ ++#define SD_BOOT_STA_END_ALT 0x01010000 ++#define SD_BOOT_STA_BOOT_RDY 0x00000001 ++ ++/* SD_VOL_SW_REG */ ++#define SD_VOL_SW_CMD_STAT_H 0x00010000 ++#define SD_VOL_SW_DAT_STAT_H 0x00000007 ++ ++/* SD_VER_REG */ ++#define SD_VER_VENDOR(x) ((x) >> 8) ++#define SD_VER_SPEC(x) ((x) & 0xf) ++ ++#define REG_SDIO_SYSADDRREG SD_REG(SD_DMA_ADDR_OFFSET) /* read/write */ ++#define REG_SDIO_BLKREG SD_REG(SD_BLK_SZ_OFFSET) /* read/write */ ++#define REG_SDIO_ARGREG SD_REG(SD_ARG_OFFSET) /* read/write */ ++#define REG_SDIO_TRANMODEREG SD_REG(SD_XFR_OFFSET) /* read/write */ ++#define REG_SDIO_RESP0REG SD_REG(SD_RSP0_OFFSET) /* read */ ++#define REG_SDIO_RESP1REG SD_REG(SD_RSP1_OFFSET) /* read */ ++#define REG_SDIO_RESP2REG SD_REG(SD_RSP2_OFFSET) /* read */ ++#define REG_SDIO_RESP3REG SD_REG(SD_RSP3_OFFSET) /* read */ ++#define REG_SDIO_BUFFERDATAPORTREG SD_REG(SD_DATA_OFFSET) /* read/write */ ++#define REG_SDIO_PRESENTSTATEREG SD_REG(SD_STA_OFFSET) /* read */ ++#define REG_SDIO_CONTROL00REG SD_REG(SD_HOST_OFFSET) /* read/write */ ++#define REG_SDIO_CONTROL01REG SD_REG(SD_CLK_OFFSET) /* read/write */ ++#define REG_SDIO_INTSTATUSREG SD_REG(SD_NIS_OFFSET) /* read/write */ ++#define REG_SDIO_INTSTATUSENREG SD_REG(SD_NISEN_OFFSET) /* read/write */ ++#define REG_SDIO_INTSIGENREG SD_REG(SD_NIXEN_OFFSET) /* read/write */ ++#define REG_SDIO_AUTOCMD12ERRSTATUSREG SD_REG(SD_AC12ES_OFFSET) /* read/write */ ++#define REG_SDIO_CAPREG SD_REG(SD_CAP_OFFSET) /* read */ ++#define REG_SDIO_MAXCURCAPREG SD_REG(SD_CUR_OFFSET) /* read/write */ ++#define REG_SDIO_SLOTINTSTATUSREG SD_REG(SD_SIST_OFFSET) /* read */ ++ ++#endif /* __MACH_GK_SD_H */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/spi.h b/arch/arm/mach-gk710x/include/mach/spi.h +new file mode 100644 +index 00000000..6e5eac05 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/spi.h +@@ -0,0 +1,326 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/spi.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK_SPI_H ++#define __MACH_GK_SPI_H ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++#define SPI_MAX_SLAVE_ID 7 ++ ++#define SPI_SUPPORT_TISSP_NSM 1 ++ ++#define SPI_INSTANCES 2 ++#define SPI_AHB_INSTANCES 0 ++#define SPI_SUPPORT_TSSI_MODE 1 ++ ++ ++#define SPI_EN2_EN3_ENABLED_BY_HOST_ENA_REG 0 ++ ++#define SPI_EN2_ENABLED_BY_GPIO2_AFSEL_REG 0 ++ ++#define SPI_EN4_7_ENABLED_BY_GPIO1_AFSEL_REG 1 ++ ++#define SPI_SLAVE_INSTANCES 0 ++ ++#define SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY 0 ++#define SPI_SUPPORT_MASTER_DELAY_START_TIME 0 ++#define SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE 0 ++ ++#define SPI_EN2_EN3_ENABLED_BY_GPIO2_AFSEL_REG 0 ++ ++/* SPI_FIFO_SIZE */ ++#define SPI_DATA_FIFO_SIZE_16 0x10 ++#define SPI_DATA_FIFO_SIZE_32 0x20 ++#define SPI_DATA_FIFO_SIZE_64 0x40 ++#define SPI_DATA_FIFO_SIZE_128 0x80 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#if SPI_API_MODE ++#define SPI_CTRLR0_OFFSET 0x00 ++#define SPI_CTRLR1_OFFSET 0x04 ++#define SPI_SSIENR_OFFSET 0x08 ++#define SPI_MWCR_OFFSET 0x0C ++#define SPI_SER_OFFSET 0x10 ++#define SPI_BAUDR_OFFSET 0x14 ++#define SPI_TXFTLR_OFFSET 0x18 ++#define SPI_RXFTLR_OFFSET 0x1C ++#define SPI_TXFLR_OFFSET 0x20 ++#define SPI_RXFLR_OFFSET 0x24 ++#define SPI_SR_OFFSET 0x28 ++#define SPI_IMR_OFFSET 0x2C ++#define SPI_ISR_OFFSET 0x30 ++#define SPI_RISR_OFFSET 0x34 ++#define SPI_TXOICR_OFFSET 0x38 ++#define SPI_RXOICR_OFFSET 0x3C ++#define SPI_RXUICR_OFFSET 0x40 ++#define SPI_MSTICR_OFFSET 0x44 ++#define SPI_ICR_OFFSET 0x48 ++#if (SPI_AHB_INSTANCES >= 1) ++#define SPI_DMAC_OFFSET 0x4C ++#endif ++#define SPI_IDR_OFFSET 0x58 ++#define SPI_VERSION_ID_OFFSET 0x5C ++#define SPI_DR_OFFSET 0x60 ++ ++#if (SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY == 1) ++#define SPI_SSIENPOLR_OFFSET 0x260 ++#endif ++#if (SPI_SUPPORT_MASTER_DELAY_START_TIME == 1) ++#define SPI_SCLK_OUT_DLY_OFFSET 0x264 ++#endif ++#if (SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE == 1) ++#define SPI_START_BIT_OFFSET 0x268 ++#endif ++ ++#define TSSI_CTRL_OFFSET 0x00 ++#define TSSI_SSR_OFFSET 0x04 ++#define TSSI_INDEX_OFFSET 0x08 ++#define TSSI_DATA_OFFSET 0x0C ++#define TSSI_POLARITY_INVERT 0x10 ++#else ++#define SPI_CTRLR0_OFFSET 0x0c ++#define SPI_CTRLR1_OFFSET 0x10 ++#define SPI_SSIENR_OFFSET 0x08 ++#define SPI_MWCR_OFFSET 0x14 ++#define SPI_SER_OFFSET 0x60 ++#define SPI_BAUDR_OFFSET 0x18 ++#define SPI_TXFTLR_OFFSET 0x3c ++#define SPI_RXFTLR_OFFSET 0x48 ++#define SPI_TXFLR_OFFSET 0x40 ++#define SPI_RXFLR_OFFSET 0x4c ++#define SPI_SR_OFFSET 0x04 ++#define SPI_IMR_OFFSET 0x1c ++#define SPI_ISR_OFFSET 0x30 ++#define SPI_RISR_OFFSET 0x2c ++#define SPI_TXOICR_OFFSET 0x44 ++#define SPI_RXOICR_OFFSET 0x50 ++#define SPI_RXUICR_OFFSET 0x54 ++#define SPI_MSTICR_OFFSET 0x24 ++#define SPI_ICR_OFFSET 0x20 ++#if (SPI_AHB_INSTANCES >= 1) ++#define SPI_DMAC_OFFSET 0x28 ++#endif ++#define SPI_IDR_OFFSET 0x00 ++#define SPI_VERSION_ID_OFFSET 0x5c ++#define SPI_DR_OFFSET 0x38 ++ ++#if (SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY == 1) ++#define SPI_SSIENPOLR_OFFSET 0x260 ++#endif ++#if (SPI_SUPPORT_MASTER_DELAY_START_TIME == 1) ++#define SPI_SCLK_OUT_DLY_OFFSET 0x264 ++#endif ++#if (SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE == 1) ++#define SPI_START_BIT_OFFSET 0x268 ++#endif ++ ++#define TSSI_CTRL_OFFSET 0x04 ++#define TSSI_SSR_OFFSET 0x00 ++#define TSSI_INDEX_OFFSET 0x0c ++#define TSSI_DATA_OFFSET 0x08 ++#define TSSI_POLARITY_INVERT 0x10 ++#endif ++ ++#define SPI_REG(x) (GK_VA_SSI1 + (x)) ++#define SPI2_REG(x) (GK_VA_SSI2 + (x)) ++#define TSSI_REG(x) (GK_VA_TSSI + (x)) ++ ++#define SPI_CTRLR0_REG SPI_REG(SPI_CTRLR0_OFFSET) ++#define SPI_CTRLR1_REG SPI_REG(SPI_CTRLR1_OFFSET) ++#define SPI_SSIENR_REG SPI_REG(SPI_SSIENR_OFFSET) ++#define SPI_MWCR_REG SPI_REG(SPI_MWCR_OFFSET) ++#define SPI_SER_REG SPI_REG(SPI_SER_OFFSET) ++#define SPI_BAUDR_REG SPI_REG(SPI_BAUDR_OFFSET) ++#define SPI_TXFTLR_REG SPI_REG(SPI_TXFTLR_OFFSET) ++#define SPI_RXFTLR_REG SPI_REG(SPI_RXFTLR_OFFSET) ++#define SPI_TXFLR_REG SPI_REG(SPI_TXFLR_OFFSET) ++#define SPI_RXFLR_REG SPI_REG(SPI_RXFLR_OFFSET) ++#define SPI_SR_REG SPI_REG(SPI_SR_OFFSET) ++#define SPI_IMR_REG SPI_REG(SPI_IMR_OFFSET) ++#define SPI_ISR_REG SPI_REG(SPI_ISR_OFFSET) ++#define SPI_RISR_REG SPI_REG(SPI_RISR_OFFSET) ++#define SPI_TXOICR_REG SPI_REG(SPI_TXOICR_OFFSET) ++#define SPI_RXOICR_REG SPI_REG(SPI_RXOICR_OFFSET) ++#define SPI_RXUICR_REG SPI_REG(SPI_RXUICR_OFFSET) ++#define SPI_MSTICR_REG SPI_REG(SPI_MSTICR_OFFSET) ++#define SPI_ICR_REG SPI_REG(SPI_ICR_OFFSET) ++#define SPI_IDR_REG SPI_REG(SPI_IDR_OFFSET) ++#define SPI_VERSION_ID_REG SPI_REG(SPI_VERSION_ID_OFFSET) ++#define SPI_DR_REG SPI_REG(SPI_DR_OFFSET) ++ ++#if (SPI_INSTANCES >= 2) ++#define SPI2_CTRLR0_REG SPI2_REG(SPI_CTRLR0_OFFSET) ++#define SPI2_CTRLR1_REG SPI2_REG(SPI_CTRLR1_OFFSET) ++#define SPI2_SSIENR_REG SPI2_REG(SPI_SSIENR_OFFSET) ++#define SPI2_MWCR_REG SPI2_REG(SPI_MWCR_OFFSET) ++#define SPI2_SER_REG SPI2_REG(SPI_SER_OFFSET) ++#define SPI2_BAUDR_REG SPI2_REG(SPI_BAUDR_OFFSET) ++#define SPI2_TXFTLR_REG SPI2_REG(SPI_TXFTLR_OFFSET) ++#define SPI2_RXFTLR_REG SPI2_REG(SPI_RXFTLR_OFFSET) ++#define SPI2_TXFLR_REG SPI2_REG(SPI_TXFLR_OFFSET) ++#define SPI2_RXFLR_REG SPI2_REG(SPI_RXFLR_OFFSET) ++#define SPI2_SR_REG SPI2_REG(SPI_SR_OFFSET) ++#define SPI2_IMR_REG SPI2_REG(SPI_IMR_OFFSET) ++#define SPI2_ISR_REG SPI2_REG(SPI_ISR_OFFSET) ++#define SPI2_RISR_REG SPI2_REG(SPI_RISR_OFFSET) ++#define SPI2_TXOICR_REG SPI2_REG(SPI_TXOICR_OFFSET) ++#define SPI2_RXOICR_REG SPI2_REG(SPI_RXOICR_OFFSET) ++#define SPI2_RXUICR_REG SPI2_REG(SPI_RXUICR_OFFSET) ++#define SPI2_MSTICR_REG SPI2_REG(SPI_MSTICR_OFFSET) ++#define SPI2_ICR_REG SPI2_REG(SPI_ICR_OFFSET) ++#define SPI2_IDR_REG SPI2_REG(SPI_IDR_OFFSET) ++#define SPI2_VERSION_ID_REG SPI2_REG(SPI_VERSION_ID_OFFSET) ++#define SPI2_DR_REG SPI2_REG(SPI_DR_OFFSET) ++#endif ++ ++#define TSSI_CTRL_REG TSSI_REG(TSSI_CTRL_OFFSET) ++#define TSSI_SSR_REG TSSI_REG(TSSI_SSR_OFFSET) ++#define TSSI_INDEX_REG TSSI_REG(TSSI_INDEX_OFFSET) ++#define TSSI_DATA_REG TSSI_REG(TSSI_DATA_OFFSET) ++#define TSSI_POLARITY_INVERT_REG TSSI_REG(TSSI_POLARITY_INVERT) ++ ++ ++#define SPI_MASTER_INSTANCES (SPI_INSTANCES + SPI_AHB_INSTANCES) ++ ++/* ==========================================================================*/ ++/* SPI rw mode */ ++#define SPI_WRITE_READ 0 ++#define SPI_WRITE_ONLY 1 ++#define SPI_READ_ONLY 2 ++ ++/* Tx FIFO empty interrupt mask */ ++#define SPI_TXEIS_MASK 0x00000001 ++#define SPI_TXOIS_MASK 0x00000002 ++ ++/* SPI Parameters */ ++#define SPI_DUMMY_DATA 0xffff ++#define MAX_QUERY_TIMES 10 ++ ++/* Default SPI settings */ ++#define SPI_MODE SPI_MODE_0 ++#define SPI_SCPOL 0 ++#define SPI_SCPH 0 ++#define SPI_FRF 0 ++#define SPI_CFS 0x0 ++#define SPI_DFS 0xf ++#define SPI_BAUD_RATE 200000 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_spi_hw_info { ++ int bus_id; ++ int cs_id; ++}; ++typedef struct gk_spi_hw_info gk_spi_hw_t; ++ ++struct gk_spi_cfg_info { ++ u8 spi_mode; ++ u8 cfs_dfs; ++ u8 cs_change; ++ u32 baud_rate; ++}; ++typedef struct gk_spi_cfg_info gk_spi_cfg_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *buffer; ++ u16 n_size; ++} gk_spi_write_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *buffer; ++ u16 n_size; ++} gk_spi_read_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *w_buffer; ++ u8 *r_buffer; ++ u16 w_size; ++ u16 r_size; ++} gk_spi_write_then_read_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *w_buffer; ++ u8 *r_buffer; ++ u16 n_size; ++} gk_spi_write_and_read_t; ++ ++struct gk_spi_cs_config { ++ u8 bus_id; ++ u8 cs_id; ++ u8 cs_num; ++ int *cs_pins; ++}; ++ ++struct gk_spi_platform_info { ++ int support_dma; ++ int fifo_entries; ++ int cs_num; ++ int *cs_pins; ++ void (*cs_activate) (struct gk_spi_cs_config *); ++ void (*cs_deactivate)(struct gk_spi_cs_config *); ++ void (*rct_set_ssi_pll)(void); ++ u32 (*get_ssi_freq_hz)(void); ++}; ++#define GK_SPI_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(spi##id##_cs0, ¶m_ops_int, &(arg[0]), perm); \ ++ module_param_cb(spi##id##_cs1, ¶m_ops_int, &(arg[1]), perm); \ ++ module_param_cb(spi##id##_cs2, ¶m_ops_int, &(arg[2]), perm); \ ++ module_param_cb(spi##id##_cs3, ¶m_ops_int, &(arg[3]), perm); \ ++ module_param_cb(spi##id##_cs4, ¶m_ops_int, &(arg[4]), perm); \ ++ module_param_cb(spi##id##_cs5, ¶m_ops_int, &(arg[5]), perm); \ ++ module_param_cb(spi##id##_cs6, ¶m_ops_int, &(arg[6]), perm); \ ++ module_param_cb(spi##id##_cs7, ¶m_ops_int, &(arg[7]), perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_spi0; ++extern struct platform_device gk_spi1; ++extern struct platform_device gk_spi2; ++extern struct platform_device gk_spi3; ++extern struct platform_device gk_spi4; ++extern struct platform_device gk_spi_slave; ++ ++/* ==========================================================================*/ ++extern int gk_spi_write(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_t *spi_write); ++extern int gk_spi_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_read_t *spi_read); ++extern int gk_spi_write_then_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_then_read_t *spi_write_then_read); ++extern int gk_spi_write_and_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_and_read_t *spi_write_and_read); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710x/include/mach/timer.h b/arch/arm/mach-gk710x/include/mach/timer.h +new file mode 100644 +index 00000000..e7edc4de +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/timer.h +@@ -0,0 +1,100 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/timer.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_TIMER_H__ ++#define __MACH_TIMER_H__ ++ ++#include ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define INTERVAL_TIMER_INSTANCES 3 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define TIMER_BASE GK_VA_TIMER ++#define TIMER_REG(x) (GK_VA_TIMER + (x)) ++ ++#define TIMER_CTR_OFFSET 0x0c ++ ++#define TIMER1_STATUS_OFFSET 0x00 ++#define TIMER1_MATCH1_OFFSET 0x04 ++#define TIMER1_MATCH2_OFFSET 0x08 ++ ++#define TIMER2_STATUS_OFFSET 0x14 ++#define TIMER2_MATCH1_OFFSET 0x18 ++#define TIMER2_MATCH2_OFFSET 0x1c ++ ++#define TIMER3_STATUS_OFFSET 0x20 ++#define TIMER3_MATCH1_OFFSET 0x24 ++#define TIMER3_MATCH2_OFFSET 0x28 ++ ++#define TIMER1_RELOAD_OFFSET 0x30 ++#define TIMER2_RELOAD_OFFSET 0x34 ++#define TIMER3_RELOAD_OFFSET 0x38 ++ ++#define TIMER1_STATUS_REG TIMER_REG(TIMER1_STATUS_OFFSET) ++#define TIMER1_RELOAD_REG TIMER_REG(TIMER1_RELOAD_OFFSET) ++#define TIMER1_MATCH1_REG TIMER_REG(TIMER1_MATCH1_OFFSET) ++#define TIMER1_MATCH2_REG TIMER_REG(TIMER1_MATCH2_OFFSET) ++#define TIMER2_STATUS_REG TIMER_REG(TIMER2_STATUS_OFFSET) ++#define TIMER2_RELOAD_REG TIMER_REG(TIMER2_RELOAD_OFFSET) ++#define TIMER2_MATCH1_REG TIMER_REG(TIMER2_MATCH1_OFFSET) ++#define TIMER2_MATCH2_REG TIMER_REG(TIMER2_MATCH2_OFFSET) ++#define TIMER3_STATUS_REG TIMER_REG(TIMER3_STATUS_OFFSET) ++#define TIMER3_RELOAD_REG TIMER_REG(TIMER3_RELOAD_OFFSET) ++#define TIMER3_MATCH1_REG TIMER_REG(TIMER3_MATCH1_OFFSET) ++#define TIMER3_MATCH2_REG TIMER_REG(TIMER3_MATCH2_OFFSET) ++ ++#define TIMER_CTR_REG TIMER_REG(TIMER_CTR_OFFSET) ++ ++ ++/* Bit field definition of timer control register */ ++#define TIMER_CTR_EN1 0x00000400 ++#define TIMER_CTR_EN2 0x00000200 ++#define TIMER_CTR_EN3 0x00000100 ++ ++#define TIMER_CTR_CSL1 0x00000040 ++#define TIMER_CTR_CSL2 0x00000020 ++#define TIMER_CTR_CSL3 0x00000010 ++ ++#define TIMER_CTR_OF1 0x00000004 ++#define TIMER_CTR_OF2 0x00000002 ++#define TIMER_CTR_OF3 0x00000001 ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern struct sys_timer gk_sys_timer; ++extern int gk_init_timer(void) __init; ++ ++extern int get_hwtimer_output_ticks(u64 *out_tick); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +\ No newline at end of file +diff --git a/arch/arm/mach-gk710x/include/mach/timex.h b/arch/arm/mach-gk710x/include/mach/timex.h +new file mode 100644 +index 00000000..6ba355a1 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/timex.h +@@ -0,0 +1,26 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/timex.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_TIMEX_H ++#define __MACH_TIMEX_H ++ ++ ++#define CLOCK_TICK_RATE 15000000 //unit:100Hz 18MHz ++ ++ ++#endif /* __MACH_TIMEX_H */ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/uart.h b/arch/arm/mach-gk710x/include/mach/uart.h +new file mode 100644 +index 00000000..d286b801 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/uart.h +@@ -0,0 +1,316 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/uart.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_UART_H_ ++#define __MACH_UART_H_ ++ ++#include ++#include ++ ++//#define KE_DEBUG ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++ ++#define UART_BASE_FREQ (get_uart_freq_hz()) ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++#define UART_INSTANCES 3 ++ ++#define UART0_VA_ADDR (GK_VA_UART0) ++#define UART0_PA_ADDR (GK_PA_UART0) ++ ++#if (UART_INSTANCES >= 2) ++#define UART1_VA_ADDR (GK_VA_UART1) ++#define UART1_PA_ADDR (GK_PA_UART1) ++#endif ++ ++#if (UART_INSTANCES >= 3) ++#define UART2_VA_ADDR (GK_VA_UART2) ++#define UART2_PA_ADDR (GK_PA_UART2) ++#endif ++ ++#if (UART_INSTANCES >= 4) ++#define UART3_VA_ADDR (GK_VA_UART3) ++#define UART3_PA_ADDR (GK_PA_UART3) ++#endif ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define UART0_REG(x) (GK_VA_UART0 + (x)) ++ ++#if (UART_INSTANCES >= 2) ++#define UART1_REG(x) (GK_VA_UART1 + (x)) ++#endif ++ ++#if (UART_INSTANCES >= 3) ++#define UART2_REG(x) (GK_VA_UART2 + (x)) ++#endif ++ ++#if (UART_INSTANCES >= 4) ++#define UART3_REG(x) (GK_VA_UART3 + (x)) ++#endif ++ ++#define UART_RB_OFFSET 0x04 ++#define UART_TH_OFFSET 0x04 ++#define UART_DLL_OFFSET 0x04 ++#define UART_IE_OFFSET 0x00 ++#define UART_DLH_OFFSET 0x00 ++#define UART_II_OFFSET 0x08 ++#define UART_FC_OFFSET 0x08 ++#define UART_LC_OFFSET 0x18 ++#define UART_MC_OFFSET 0x0c ++#define UART_LS_OFFSET 0x14 ++#define UART_MS_OFFSET 0x10 ++#define UART_SC_OFFSET 0x1c /* Byte */ ++#define UART_SRR_OFFSET 0x88 ++ ++#define UART0_RB_REG UART0_REG(UART_RB_OFFSET) ++#define UART0_TH_REG UART0_REG(UART_TH_OFFSET) ++#define UART0_DLL_REG UART0_REG(UART_DLL_OFFSET) ++#define UART0_IE_REG UART0_REG(UART_IE_OFFSET) ++#define UART0_DLH_REG UART0_REG(UART_DLH_OFFSET) ++#define UART0_II_REG UART0_REG(UART_II_OFFSET) ++#define UART0_FC_REG UART0_REG(UART_FC_OFFSET) ++#define UART0_LC_REG UART0_REG(UART_LC_OFFSET) ++#define UART0_MC_REG UART0_REG(UART_MC_OFFSET) ++#define UART0_LS_REG UART0_REG(UART_LS_OFFSET) ++#define UART0_MS_REG UART0_REG(UART_MS_OFFSET) ++#define UART0_SC_REG UART0_REG(UART_SC_OFFSET) /* Byte */ ++ ++#if (UART_INSTANCES >= 2) ++ ++#define UART1_RB_REG UART1_REG(UART_RB_OFFSET) ++#define UART1_TH_REG UART1_REG(UART_TH_OFFSET) ++#define UART1_DLL_REG UART1_REG(UART_DLL_OFFSET) ++#define UART1_IE_REG UART1_REG(UART_IE_OFFSET) ++#define UART1_DLH_REG UART1_REG(UART_DLH_OFFSET) ++#define UART1_II_REG UART1_REG(UART_II_OFFSET) ++#define UART1_FC_REG UART1_REG(UART_FC_OFFSET) ++#define UART1_LC_REG UART1_REG(UART_LC_OFFSET) ++#define UART1_MC_REG UART1_REG(UART_MC_OFFSET) ++#define UART1_LS_REG UART1_REG(UART_LS_OFFSET) ++#define UART1_MS_REG UART1_REG(UART_MS_OFFSET) ++#define UART1_SC_REG UART1_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 2 */ ++ ++#if (UART_INSTANCES >= 3) ++ ++#define UART2_RB_REG UART2_REG(UART_RB_OFFSET) ++#define UART2_TH_REG UART2_REG(UART_TH_OFFSET) ++#define UART2_DLL_REG UART2_REG(UART_DLL_OFFSET) ++#define UART2_IE_REG UART2_REG(UART_IE_OFFSET) ++#define UART2_DLH_REG UART2_REG(UART_DLH_OFFSET) ++#define UART2_II_REG UART2_REG(UART_II_OFFSET) ++#define UART2_FC_REG UART2_REG(UART_FC_OFFSET) ++#define UART2_LC_REG UART2_REG(UART_LC_OFFSET) ++#define UART2_MC_REG UART2_REG(UART_MC_OFFSET) ++#define UART2_LS_REG UART2_REG(UART_LS_OFFSET) ++#define UART2_MS_REG UART2_REG(UART_MS_OFFSET) ++#define UART2_SC_REG UART2_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 3 */ ++ ++#if (UART_INSTANCES >= 4) ++ ++#define UART3_RB_REG UART3_REG(UART_RB_OFFSET) ++#define UART3_TH_REG UART3_REG(UART_TH_OFFSET) ++#define UART3_DLL_REG UART3_REG(UART_DLL_OFFSET) ++#define UART3_IE_REG UART3_REG(UART_IE_OFFSET) ++#define UART3_DLH_REG UART3_REG(UART_DLH_OFFSET) ++#define UART3_II_REG UART3_REG(UART_II_OFFSET) ++#define UART3_FC_REG UART3_REG(UART_FC_OFFSET) ++#define UART3_LC_REG UART3_REG(UART_LC_OFFSET) ++#define UART3_MC_REG UART3_REG(UART_MC_OFFSET) ++#define UART3_LS_REG UART3_REG(UART_LS_OFFSET) ++#define UART3_MS_REG UART3_REG(UART_MS_OFFSET) ++#define UART3_SC_REG UART3_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 4 */ ++ ++/* UART[x]_IE_REG */ ++#define UART_IE_PTIME 0x80 ++#define UART_IE_ETOI 0x20 ++#define UART_IE_EBDI 0x10 ++#define UART_IE_EDSSI 0x08 ++#define UART_IE_ELSI 0x04 ++#define UART_IE_ETBEI 0x02 ++#define UART_IE_ERBFI 0x01 ++ ++/* UART[x]_II_REG */ ++#define UART_II_MODEM_STATUS_CHANGED 0x00 ++#define UART_II_NO_INT_PENDING 0x01 ++#define UART_II_THR_EMPTY 0x02 ++#define UART_II_RCV_DATA_AVAIL 0x04 ++#define UART_II_RCV_STATUS 0x06 ++#define UART_II_CHAR_TIMEOUT 0x0c ++ ++/* UART[x]_FC_REG */ ++#define UART_FC_RX_ONECHAR 0x00 ++#define UART_FC_RX_QUARTER_FULL 0x40 ++#define UART_FC_RX_HALF_FULL 0x80 ++#define UART_FC_RX_2_TO_FULL 0xc0 ++#define UART_FC_TX_EMPTY 0x00 ++#define UART_FC_TX_2_IN_FIFO 0x10 ++#define UART_FC_TX_QUATER_IN_FIFO 0x20 ++#define UART_FC_TX_HALF_IN_FIFO 0x30 ++#define UART_FC_XMITR 0x04 ++#define UART_FC_RCVRR 0x02 ++#define UART_FC_FIFOE 0x01 ++ ++/* UART[x]_LC_REG */ ++#define UART_LC_BRK 0x80 ++ ++#define UART_LC_EVEN_PARITY 0x40 ++#define UART_LC_ODD_PARITY 0x00 ++ ++#define UART_LC_STICKY_PARITY 0x20 ++#define UART_LC_DLAB 0x10 ++ ++#define UART_LC_STOP_2BIT 0x08 ++#define UART_LC_STOP_1BIT 0x00 ++ ++#define UART_LC_PEN 0x04 ++#define UART_LC_CLS_8_BITS 0x03 ++#define UART_LC_CLS_7_BITS 0x02 ++#define UART_LC_CLS_6_BITS 0x01 ++#define UART_LC_CLS_5_BITS 0x00 ++ ++/* quick defs */ ++#define UART_LC_8N1 0x03 ++#define UART_LC_7E1 0x0a ++ ++/* UART[x]_MC_REG */ ++#define UART_MC_LB 0x40 ++#define UART_MC_AFCE 0x20 ++#define UART_MC_SIRE 0x10 ++#define UART_MC_RTS 0x08 ++#define UART_MC_DTR 0x04 ++#define UART_MC_OUT2 0x02 ++#define UART_MC_OUT1 0x01 ++ ++/* UART[x]_LS_REG */ ++#define UART_LS_FERR 0x80 ++ ++#define UART_LS_TEMT 0x40 ++#define UART_LS_BI 0x20 ++#define UART_LS_FE 0x10 ++#define UART_LS_THRE 0x08 ++ ++#define UART_LS_DR 0x04 ++#define UART_LS_PE 0x02 ++#define UART_LS_OE 0x01 ++ ++/* UART[x]_MS_REG */ ++#define UART_MS_DCD 0x80 ++#define UART_MS_DCTS 0x40 ++#define UART_MS_CTS 0x20 ++#define UART_MS_DDCD 0x10 ++#define UART_MS_DSR 0x08 ++#define UART_MS_DDSR 0x04 ++#define UART_MS_TERI 0x02 ++#define UART_MS_RI 0x01 ++ ++/* Other defs for UART */ ++#define RECV_BUF_SIZ 1500 ++#define SEND_BUF_SIZ 1500 ++ ++/* ==========================================================================*/ ++#define UART_FIFO_SIZE (16) ++ ++#define DEFAULT_UART_MCR (0) ++#define DEFAULT_UART_IER (UART_IE_ELSI | UART_IE_ERBFI) ++#define DEFAULT_UART_FCR (UART_FC_FIFOE | UART_FC_RX_2_TO_FULL | UART_FC_TX_EMPTY) ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifndef __ASSEMBLER__ ++ ++struct gk_uart_port_info ++{ ++ void *port; //struct uart_port * ++ u32 mcr; ++ u32 fcr; ++ u32 ier; ++ u32 tx_fifo_fix; ++ ++ void (*stop_tx)(unsigned char __iomem *membase); ++ void (*set_pll)(void); ++ u32 (*get_pll)(void); ++ u32 (*get_ms)(unsigned char __iomem *membase); ++}; ++ ++struct gk_uart_platform_info ++{ ++ int total_port_num; ++ int registed_port_num; ++ ++ struct gk_uart_port_info port[UART_INSTANCES]; ++}; ++ ++extern struct gk_uart_platform_info gk_uart_ports; ++ ++#ifdef KE_DEBUG ++extern void after_print(const char *str, ...); ++#endif ++ ++/* ==========================================================================*/ ++#endif /* __ASSEMBLER__ */ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __MACH_UART_H_ */ +diff --git a/arch/arm/mach-gk710x/include/mach/uncompress.h b/arch/arm/mach-gk710x/include/mach/uncompress.h +new file mode 100644 +index 00000000..87d274d1 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/uncompress.h +@@ -0,0 +1,96 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/uncompress.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_UNCOMPRESS_H ++#define __MACH_UNCOMPRESS_H ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++#include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++typedef void* (*hal_function_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) ; ++ ++struct hw_ops *g_hw; ++ ++#define PA_UART0 GK_PA_UART0 ++#define UART_RB_OFFSET 0x04 ++#define UART_TH_OFFSET 0x04 ++#define UART_DLL_OFFSET 0x04 ++#define UART_IE_OFFSET 0x00 ++#define UART_DLH_OFFSET 0x00 ++#define UART_II_OFFSET 0x08 ++#define UART_FC_OFFSET 0x08 ++#define UART_LC_OFFSET 0x18 ++#define UART_MC_OFFSET 0x0c ++#define UART_LS_OFFSET 0x14 ++#define UART_MS_OFFSET 0x10 ++#define UART_SC_OFFSET 0x1c /* Byte */ ++#define UART_SRR_OFFSET 0x88 ++ ++ ++#define UART_LS_REG ((PA_UART0 + UART_LS_OFFSET)) ++#define UART_TH_REG ((PA_UART0 + UART_TH_OFFSET)) ++#define UART_RB_REG ((PA_UART0 + UART_RB_OFFSET)) ++#define UART_SRR_REG ((PA_UART0 + UART_SRR_OFFSET)) ++ ++#define UART_LC_REG ((PA_UART0 + UART_LC_OFFSET)) ++#define UART_DLL_REG ((PA_UART0 + UART_DLL_OFFSET)) ++#define UART_DLH_REG ((PA_UART0 + UART_DLH_OFFSET)) ++ ++/* ==========================================================================*/ ++ ++static inline void putc(int c) ++{ ++ while (!(gk_uart_readl(UART_LS_REG) & UART_LS_TEMT)); ++ gk_uart_writel(UART_TH_REG, c); ++} ++ ++static inline void flush(void) ++{ ++ unsigned int dump; ++ ++ while (gk_uart_readl(UART_LS_REG) & UART_LS_DR) ++ { ++ dump = gk_uart_readl(UART_RB_REG); ++ } ++} ++ ++ ++ ++ ++ ++static inline void arch_decomp_setup(void) ++{ ++ ++ hal_function_t hal_init = (hal_function_t) (*(volatile u32 *)CONFIG_U2K_HAL_ADDR); ++ ++ g_hw = (struct hw_ops *)hal_init (0, 0, 0x90000000, 0xa0000000, 0); ++ ++} ++ ++#define arch_decomp_wdog() ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_UNCOMPRESS_H */ +diff --git a/arch/arm/mach-gk710x/include/mach/vmalloc.h b/arch/arm/mach-gk710x/include/mach/vmalloc.h +new file mode 100644 +index 00000000..ff65ed24 +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/vmalloc.h +@@ -0,0 +1,37 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/vmalloc.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_VMALLOC_H ++#define __MACH_VMALLOC_H ++ ++/* ==========================================================================*/ ++#if defined(CONFIG_VMSPLIT_3G) ++#define VMALLOC_END UL(0xe0000000) ++#else ++#define VMALLOC_END UL(0xb0000000) ++#endif ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++/* ==========================================================================*/ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710x/include/mach/vo_i80.h b/arch/arm/mach-gk710x/include/mach/vo_i80.h +new file mode 100644 +index 00000000..8c0acfef +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/vo_i80.h +@@ -0,0 +1,79 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/vo_i80.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_VO_I80_H ++#define __MACH_V0_I80_H ++ ++#include ++ ++#define VO_I80_BASE (GK_VA_VO) ++#define VO_I80_REG(x) (VO_I80_BASE + (x)) ++ ++#define REG_VO_I80_DATA_FORMAT VO_I80_REG(0xC00) /* read/write */ ++#define REG_VO_I80_PIC_RESOLUTION VO_I80_REG(0xC04) /* read/write */ ++#define REG_VO_I80_PIXEL_RDWRCMD VO_I80_REG(0xC08) /* read/write */ ++#define REG_VO_I80_CMD_FORMAT VO_I80_REG(0xC0C) /* read/write */ ++#define REG_VO_I80_LCD_RST_PARA1 VO_I80_REG(0xC10) /* read/write */ ++#define REG_VO_I80_LCD_RST_PARA2 VO_I80_REG(0xC14) /* read/write */ ++#define REG_VO_I80_DELAY_PARA VO_I80_REG(0xC18) /* read/write */ ++#define REG_VO_I80_TWR_TIMING VO_I80_REG(0xC1C) /* read/write */ ++#define REG_VO_I80_TRD_TIMING VO_I80_REG(0xC20) /* read/write */ ++#define REG_VO_I80_TCS_TIMING VO_I80_REG(0xC24) /* read/write */ ++#define REG_VO_I80_POLAR_CTRL VO_I80_REG(0xC28) /* read/write */ ++#define REG_VO_I80_CTRL VO_I80_REG(0xC2C) /* read/write */ ++#define REG_VO_I80_FRAME_COUNTER VO_I80_REG(0xC30) /* read */ ++#define REG_VO_I80_I80_STATE VO_I80_REG(0xC34) /* read */ ++#define REG_VO_I80_CMD_SRAM_STATE VO_I80_REG(0xC38) /* read/write */ ++#define REG_VO_I80_TCSREF_WT_TIMING VO_I80_REG(0xC3C) /* read/write */ ++#define REG_VO_I80_TCSREF_RD_TIMING VO_I80_REG(0xC40) /* read/write */ ++#define REG_VO_I80_TODH_TIMING VO_I80_REG(0xC44) /* read/write */ ++#define REG_VO_I80_LCD_STATE VO_I80_REG(0xC48) /* read */ ++#define REG_VO_I80_LCD_STATE0 VO_I80_REG(0xC4C) /* read */ ++#define REG_VO_I80_LCD_STATE1 VO_I80_REG(0xC50) /* read */ ++#define REG_VO_I80_LCD_STATE2 VO_I80_REG(0xC54) /* read */ ++#define REG_VO_I80_LCD_STATE3 VO_I80_REG(0xC58) /* read */ ++#define REG_VO_I80_LCD_STATE4 VO_I80_REG(0xC5C) /* read */ ++#define REG_VO_I80_SRAM_CMDPARA VO_I80_REG(0xC80) /* read/write */ ++ ++ ++ ++#define I80_DESIGN_REF_CLK_FREQ 200//MHz GK7101S-->200MHz GK8601-->300MHz ++ ++#define I80_CLK_FREQ 100//MHz GK7101S: FPGA-->100MHz IC-->200MHz ++#define I80_CLK_PERIOD (1000/I80_CLK_FREQ)//FPGA-->10ns/Cycle IC-->5ns/cycle ++ ++#define MAX_RESET_1ST_H_L_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(100*I80_CLK_FREQ) )//FPGA-->40ms IC-->20ms ++#define MAX_RESET_2ND_H_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(10*I80_CLK_FREQ) ) //FPGA-->409ms IC-->204ms ++#define MAX_DELAY_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(10*I80_CLK_FREQ) ) //FPGA-->409ms IC-->204ms ++//#define MAX_TRANS_NS ((1<<9)-1)*I80_CLK_PERIOD //FPGA-->5110ns IC-->2555ns ++//#define MAX_TAS_NS ((1<<6)-1)*I80_CLK_PERIOD //FPGA-->630ns IC-->315ns ++ ++#define TIMING_PARA_CEIL_NS(x) (((x)*I80_CLK_FREQ+999)/1000) ++ ++#define I80_1ST_H_L_COUNTER (10*I80_DESIGN_REF_CLK_FREQ) ++#define I80_2ND_H_COUNTER (100*I80_DESIGN_REF_CLK_FREQ) ++#define I80_HW_DELAY_COUNTER (100*I80_DESIGN_REF_CLK_FREQ) ++ ++#define TIMING_PARA_FIRST_H_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_1ST_H_L_COUNTER-1)/I80_1ST_H_L_COUNTER) ++#define TIMING_PARA_FIRST_L_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_1ST_H_L_COUNTER-1)/I80_1ST_H_L_COUNTER) ++#define TIMING_PARA_SECOND_H_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_2ND_H_COUNTER-1)/I80_2ND_H_COUNTER) ++#define TIMING_PARA_HW_DELAY_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_HW_DELAY_COUNTER-1)/I80_HW_DELAY_COUNTER) ++ ++ ++#endif /* __MACH_VO_I80_H */ ++ ++ +diff --git a/arch/arm/mach-gk710x/include/mach/wdt.h b/arch/arm/mach-gk710x/include/mach/wdt.h +new file mode 100644 +index 00000000..8956e6fc +--- /dev/null ++++ b/arch/arm/mach-gk710x/include/mach/wdt.h +@@ -0,0 +1,77 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/wdt.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_WDT_H ++#define __MACH_WDT_H ++ ++/* ==============================================*/ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++/* On A5S WDT_RST_L_REG can not be cleared. */ ++/* When is more then 0xff. To work around we set */ ++/* WDT_RST_L_REG to 0x0 before WDT start because */ ++/* it is preserved during soft reset, if it's */ ++/* still 0x0 we could know the reset is from WDT */ ++ ++#define RCT_WDT_RESET_VAL 0 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define WDOG_REG(x) (GK_VA_WDT + (x)) ++ ++#define WDOG_STATUS_OFFSET 0x0c ++#define WDOG_RELOAD_OFFSET 0x10 ++#define WDOG_RESTART_OFFSET 0x14 ++#define WDOG_CONTROL_OFFSET 0x00 ++#define WDOG_TIMEOUT_OFFSET 0x04 ++#define WDOG_CLR_TMO_OFFSET 0x08 ++#define WDOG_RST_WD_OFFSET 0x18 ++ ++#define WDOG_STATUS_REG WDOG_REG(WDOG_STATUS_OFFSET) ++#define WDOG_RELOAD_REG WDOG_REG(WDOG_RELOAD_OFFSET) ++#define WDOG_RESTART_REG WDOG_REG(WDOG_RESTART_OFFSET) ++#define WDOG_CONTROL_REG WDOG_REG(WDOG_CONTROL_OFFSET) ++#define WDOG_TIMEOUT_REG WDOG_REG(WDOG_TIMEOUT_OFFSET) ++#define WDOG_CLR_TMO_REG WDOG_REG(WDOG_CLR_TMO_OFFSET) ++#define WDOG_RST_WD_REG WDOG_REG(WDOG_RST_WD_OFFSET) ++ ++/* Bit field definition of watch dog timer control register */ ++#define WDOG_CTR_RST_EN 0x00000004 ++#define WDOG_CTR_INT_EN 0x00000002 ++#define WDOG_CTR_EN 0x00000001 ++ ++/* WDOG_RESTART_REG only works with magic 0x4755. */ ++/* Set this value would transferred the value in */ ++/* WDOG_RELOAD_REG into WDOG_STATUS_REG and would */ ++/* not trigger the underflow event. */ ++#define WDT_RESTART_VAL 0X4755 ++ ++/* ==============================================*/ ++#ifndef __ASSEMBLER__ ++ ++extern struct platform_device gk_wdt; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==============================================*/ ++ ++#endif /* __REGS_WDT_H */ ++ +diff --git a/arch/arm/mach-gk710x/irq.c b/arch/arm/mach-gk710x/irq.c +new file mode 100644 +index 00000000..d70f61dc +--- /dev/null ++++ b/arch/arm/mach-gk710x/irq.c +@@ -0,0 +1,410 @@ ++/* ++ * arch/arm/mach-gk/irq.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_ARM_VIC ++#include ++#endif ++ ++/** ++ * struct vic_device - VIC PM device ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ * @domain: The IRQ domain for the VIC. ++ */ ++struct gk_vic_device { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++ struct irq_domain *domain; ++}; ++ ++/* ==========================================================================*/ ++ ++/* we cannot allocate memory when VICs are initially registered */ ++static struct gk_vic_device gk_vic_decs[VIC_INSTANCES]; ++ ++static int gk_vic_id; ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#define GK_GPIO_IRQ2GIRQ() do { \ ++ girq -= GPIO_IRQ(0); \ ++ } while (0) ++ ++ ++/* ==========================================================================*/ ++#if (VIC_INSTANCES == 1) ++#define GK_VIC_IRQ2BASE() do { \ ++ irq -= VIC1_INT_VEC(0); \ ++ } while (0) ++#elif (VIC_INSTANCES == 2) ++#define GK_VIC_IRQ2BASE() do { \ ++ irq -= VIC1_INT_VEC(0); \ ++ if (irq >= NR_VIC_IRQ_SIZE) { \ ++ irq -= NR_VIC_IRQ_SIZE; \ ++ vic_base = VIC2_BASE; \ ++ } \ ++ } while (0) ++#endif ++ ++static void gk_ack_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_EDGE_CLR_OFFSET, 0x1 << irq); ++} ++ ++static void gk_disable_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_CLR_OFFSET, 0x1 << irq); ++} ++ ++static void gk_enable_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_OFFSET, 0x1 << irq); ++} ++ ++static void gk_mask_ack_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_CLR_OFFSET, 0x1 << irq); ++ gk_irq_writel(vic_base + VIC_EDGE_CLR_OFFSET, 0x1 << irq); ++} ++ ++static int gk_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 mask; ++ u32 bit; ++ u32 sense; ++ u32 bothedges; ++ u32 event; ++ struct irq_desc *desc = irq_to_desc(d->irq); ++ u32 irq = d->irq; ++ ++ //printk("%s: irq[%d] type[%d] desc[%p]\n", __func__, irq, type, desc); ++ ++ GK_VIC_IRQ2BASE(); ++ ++ mask = ~(0x1 << irq); ++ bit = (0x1 << irq); ++ sense = gk_irq_readl(vic_base + VIC_SENSE_OFFSET); ++ bothedges = gk_irq_readl(vic_base + VIC_BOTHEDGE_OFFSET); ++ event = gk_irq_readl(vic_base + VIC_EVENT_OFFSET); ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_RISING: ++ sense &= mask; ++ bothedges &= mask; ++ event |= bit; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ sense &= mask; ++ bothedges &= mask; ++ event &= mask; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ sense &= mask; ++ bothedges |= bit; ++ event &= mask; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ sense |= bit; ++ bothedges &= mask; ++ event |= bit; ++ desc->handle_irq = handle_level_irq; ++ break; ++ case IRQ_TYPE_LEVEL_LOW: ++ sense |= bit; ++ bothedges &= mask; ++ event &= mask; ++ desc->handle_irq = handle_level_irq; ++ break; ++ default: ++ pr_err("%s: can't set irq type %d for irq 0x%08x@%d\n", ++ __func__, type, vic_base, irq); ++ return -EINVAL; ++ } ++ ++ gk_irq_writel(vic_base + VIC_SENSE_OFFSET, sense); ++ gk_irq_writel(vic_base + VIC_BOTHEDGE_OFFSET, bothedges); ++ gk_irq_writel(vic_base + VIC_EVENT_OFFSET, event); ++ ++ gk_ack_irq(d); ++ ++ return 0; ++} ++ ++static struct irq_chip gk_irq_chip = { ++ .name = "gk irq", ++ .irq_ack = gk_ack_irq, ++ .irq_mask = gk_disable_irq, ++ .irq_unmask = gk_enable_irq, ++ .irq_mask_ack = gk_mask_ack_irq, ++ .irq_set_type = gk_irq_set_type, ++}; ++ ++void gk_swvic_set(u32 irq) ++{ ++ u32 vic_base = VIC1_BASE; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_SOFTEN_OFFSET, 0x1 << irq); ++} ++EXPORT_SYMBOL(gk_swvic_set); ++ ++void gk_swvic_clr(u32 irq) ++{ ++ u32 vic_base = VIC1_BASE; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_SOFTEN_CLR_OFFSET, 0x1 << irq); ++} ++EXPORT_SYMBOL(gk_swvic_clr); ++ ++/* ==========================================================================*/ ++static inline u32 gk_irq_stat2nr(u32 stat) ++{ ++ u32 tmp; ++ u32 nr; ++ ++ __asm__ __volatile__ ++ ("rsbs %[tmp], %[stat], #0" : ++ [tmp] "=r" (tmp) : [stat] "r" (stat)); ++ __asm__ __volatile__ ++ ("and %[nr], %[tmp], %[stat]" : ++ [nr] "=r" (nr) : [tmp] "r" (tmp), [stat] "r" (stat)); ++ __asm__ __volatile__ ++ ("clzcc %[nr], %[nr]" : ++ [nr] "+r" (nr)); ++ __asm__ __volatile__ ++ ("rsc %[nr], %[nr], #32" : ++ [nr] "+r" (nr)); ++ ++ return nr; ++} ++ ++/* ==========================================================================*/ ++ ++u32 vic_base_addr[VIC_INSTANCES] = { ++ VIC1_BASE, ++#if (VIC_INSTANCES >= 2) ++ VIC2_BASE, ++#endif ++#if (VIC_INSTANCES >= 3) ++ VIC3_BASE, ++#endif ++#if (VIC_INSTANCES >= 4) ++ VIC4_BASE, ++#endif ++}; ++ ++#ifndef CONFIG_ARM_VIC ++ ++/** ++ * gk_vic_register() - Register a VIC. ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * @node: The device tree node associated with the VIC. ++ * ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ * ++ * This also configures the IRQ domain for the VIC. ++ */ ++static void __init gk_vic_register(void __iomem *base, unsigned int irq, ++ u32 resume_sources, struct device_node *node) ++{ ++ struct gk_vic_device *pVic; ++ ++ if (gk_vic_id >= ARRAY_SIZE(gk_vic_decs)) ++ { ++ printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); ++ return; ++ } ++ ++ pVic = &gk_vic_decs[gk_vic_id]; ++ pVic->base = base; ++ pVic->resume_sources = resume_sources; ++ pVic->irq = irq; ++ gk_vic_id++; ++ pVic->domain = irq_domain_add_legacy(node, NR_VIC_IRQ_SIZE, irq, 0, ++ &irq_domain_simple_ops, pVic); ++} ++ ++void __init gk_init_vic(u32 num_vic) ++{ ++ int irq, i; ++ ++ printk("gk init vic...\n"); ++ for (i = 0; i < NR_IRQS; i++) ++ { ++ //pr_err("registering irq %d \n", i); ++ irq_set_chip_and_handler(i, &gk_irq_chip, handle_level_irq); ++ set_irq_flags(i, IRQF_VALID); ++ } ++ ++ /* initialize the VICs */ ++ for (irq = 0; irq < num_vic; irq++) ++ { ++ gk_vic_register((void __iomem *)vic_base_addr[irq], (NR_VIC_IRQ_SIZE * irq), 0, NULL); ++ } ++} ++ ++/* ++ * Handle each interrupt in a single VIC. Returns non-zero if we've ++ * handled at least one interrupt. This reads the status register ++ * before handling each interrupt, which is necessary given that ++ * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. ++ */ ++static int gk_handle_one_vic(struct gk_vic_device *vic, struct pt_regs *regs) ++{ ++ u32 stat, irq; ++ int handled = 0; ++ ++ while ((stat = readl_relaxed(vic->base + VIC_IRQ_STA_OFFSET))) { ++ irq = ffs(stat) - 1; ++ handle_IRQ(irq_find_mapping(vic->domain, irq), regs); ++ handled = 1; ++ } ++ ++ return handled; ++} ++ ++/* ++ * Keep iterating over all registered VIC's until there are no pending ++ * interrupts. ++ */ ++asmlinkage void __exception_irq_entry gk_vic_handle_irq(struct pt_regs *regs) ++{ ++ int i, handled; ++ do { ++ for (i = 0, handled = 0; i < gk_vic_id; ++i) ++ handled |= gk_handle_one_vic(&gk_vic_decs[i], regs); ++ } while (handled); ++} ++ ++#else ++ ++void __init gk_init_vic(u32 num_vic) ++{ ++ u32 vic[] = {~0, ~0, ~0}; ++ int irq; ++ ++printk("gk init vic...\n"); ++ /* initialize the VICs */ ++ for (irq = 0; irq < num_vic; irq++) ++ { ++ vic_init(vic_base_addr[irq], (NR_VIC_IRQ_SIZE * irq), vic[irq], 0); ++ } ++} ++ ++#endif ++ ++void __init gk_init_irq(void) ++{ ++ ++#ifndef CONFIG_ARM_VIC ++ printk(">> gk init irq vic1...\n"); ++ /* Set VIC sense and event type for each entry ++ * note: we initialize udc vbus irq type here */ ++ gk_irq_writel(VIC_SENSE_REG, 0x00000000); ++ gk_irq_writel(VIC_BOTHEDGE_REG, 0x00000000); ++ gk_irq_writel(VIC_EVENT_REG, 0x00000000); ++ ++#if (VIC_INSTANCES >= 2) ++ printk(">> gk init irq vic2...\n"); ++ gk_irq_writel(VIC2_SENSE_REG, 0x00000000); ++ gk_irq_writel(VIC2_BOTHEDGE_REG, 0x00000000); ++ gk_irq_writel(VIC2_EVENT_REG, 0x00000000); ++#endif ++ ++ /* Disable all IRQ */ ++ gk_irq_writel(VIC_INT_SEL_REG, 0x00000000); ++ gk_irq_writel(VIC_INTEN_REG, 0x00000000); ++ gk_irq_writel(VIC_INTEN_CLR_REG, 0xffffffff); ++ gk_irq_writel(VIC_EDGE_CLR_REG, 0xffffffff); ++ ++#if (VIC_INSTANCES >= 2) ++ gk_irq_writel(VIC2_INT_SEL_REG, 0x00000000); ++ gk_irq_writel(VIC2_INTEN_REG, 0x00000000); ++ gk_irq_writel(VIC2_INTEN_CLR_REG, 0xffffffff); ++ gk_irq_writel(VIC2_EDGE_CLR_REG, 0xffffffff); ++#endif ++#endif ++ ++ gk_init_vic(VIC_INSTANCES); ++ ++} ++ +diff --git a/arch/arm/mach-gk710x/mach-gk710x.c b/arch/arm/mach-gk710x/mach-gk710x.c +new file mode 100644 +index 00000000..1c3a4319 +--- /dev/null ++++ b/arch/arm/mach-gk710x/mach-gk710x.c +@@ -0,0 +1,1012 @@ ++/* ++ * linux/arch/arm/mach-gk/mach-gk.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++ ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern struct platform_device gk_fb0; ++extern struct platform_device gk_fb1; ++extern int gk_init_fb(void); ++ ++extern struct platform_device gk_sd0; ++ ++extern struct i2c_board_info gk_board_vi_infos[2]; ++extern struct i2c_board_info gk_board_hdmi_infos[2]; ++ ++//u64 gk_dmamask = DMA_BIT_MASK(32); ++//EXPORT_SYMBOL(gk_dmamask); ++ ++/* ==========================================================================*/ ++ ++#if defined(CONFIG_MTD_SFLASH_GOKE) || defined(CONFIG_MTD_SFLASH_GOKE_MODULE) ++ ++ ++#if defined(CONFIG_ONLY_USE_NOR_8M) ++#define GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET \ ++ (0) ++#define GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE \ ++ (256 * 1024) ++ ++#define GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET \ ++ (GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET \ ++ + GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE) ++#define GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE \ ++ (64 * 1024) ++ ++#define GKAPP_MTDBLOCK2_USER_OFFSET \ ++ (GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET \ ++ + GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE) ++#define GKAPP_MTDBLOCK2_USER_SIZE \ ++ (128 * 1024) ++ ++#define GKAPP_MTDBLOCK3_CUSTOM_OFFSET \ ++ (GKAPP_MTDBLOCK2_USER_OFFSET \ ++ + GKAPP_MTDBLOCK2_USER_SIZE) ++#define GKAPP_MTDBLOCK3_CUSTOM_SIZE \ ++ (512 * 1024) ++ ++#define GKAPP_MTDBLOCK4_KERNEL_OFFSET \ ++ (GKAPP_MTDBLOCK3_CUSTOM_OFFSET \ ++ + GKAPP_MTDBLOCK3_CUSTOM_SIZE) ++#define GKAPP_MTDBLOCK4_KERNEL_SIZE \ ++ ((1024 + 320) * 1024) ++ ++#define GKAPP_MTDBLOCK5_ROOTFS_OFFSET \ ++ (GKAPP_MTDBLOCK4_KERNEL_OFFSET \ ++ + GKAPP_MTDBLOCK4_KERNEL_SIZE) ++#define GKAPP_MTDBLOCK5_ROOTFS_SIZE \ ++ ((4096 + 0) * 1024) ++ ++#define GKAPP_MTDBLOCK6_RESOURCE_OFFSET \ ++ (GKAPP_MTDBLOCK5_ROOTFS_OFFSET \ ++ + GKAPP_MTDBLOCK5_ROOTFS_SIZE) ++#define GKAPP_MTDBLOCK6_RESOURCE_SIZE \ ++ ((1024 + 704 + 64) * 1024) ++ ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++#if 0 ++ [0] = { ++ .name = "uboot", ++ .offset = GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET, ++ .size = GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE, ++ }, ++ [1] = { ++ .name = "uboot_env", ++ .offset = GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET, ++ .size = GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE, ++ }, ++ [2] = {/* for usrm of Juan */ ++ .name = "user", ++ .offset = GKAPP_MTDBLOCK2_USER_OFFSET, ++ .size = GKAPP_MTDBLOCK2_USER_SIZE, ++ }, ++ [3] = {/* mount custom.jffs2 /media/conf */ ++ .name = "conf", ++ .offset = GKAPP_MTDBLOCK3_CUSTOM_OFFSET, ++ .size = GKAPP_MTDBLOCK3_CUSTOM_SIZE, ++ }, ++ [4] = { ++ .name = "kernel", ++ .offset = GKAPP_MTDBLOCK4_KERNEL_OFFSET, ++ .size = GKAPP_MTDBLOCK4_KERNEL_SIZE, ++ }, ++ [5] = {/* ro squashfs rootfs */ ++ .name = "rootfs", ++ .offset = GKAPP_MTDBLOCK5_ROOTFS_OFFSET, ++ .size = GKAPP_MTDBLOCK5_ROOTFS_SIZE, ++ }, ++ [6] = {/* mount font&web squashfs to /media/custom */ ++ .name = "resource", ++ .offset = GKAPP_MTDBLOCK6_RESOURCE_OFFSET, ++ .size = GKAPP_MTDBLOCK6_RESOURCE_SIZE, ++ }, ++#else ++#if 1//defined(CONFIG_MACH_GK7102_HZD_OJTV_v10_JXH42) || defined(CONFIG_MACH_GK_HZD_OJTV_v10_OV2710) ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //128k ++ [2] = { ++ .name = "user", ++ .offset = 0x00050000, ++ .size = 0x00020000, ++ }, ++ //448k ++ [3] = { ++ .name = "config", ++ .offset = 0x00070000, ++ .size = 0x00070000, ++ }, ++ //1344k ++ [4] = { ++ .name = "kernel", ++ .offset = 0x000e0000, ++ .size = 0x001A0000, ++ }, ++ //4M ++ [5] = { ++ .name = "rootfs", ++ .offset = 0x00280000, ++ .size = 0x003b0000, ++ }, ++ //1856k ++ [6] = { ++ .name = "resource", ++ .offset = 0x00630000, ++ .size = 0x001d0000, ++ }, ++ //ALL 0--8M ++ [7] = { ++ .name = "all", ++ .offset = 0x00000000, ++ .size = 0x00800000, ++ }, ++#else ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //128k ++ [2] = { ++ .name = "user", ++ .offset = 0x00050000, ++ .size = 0x00020000, ++ }, ++ //448k ++ [3] = { ++ .name = "config", ++ .offset = 0x00070000, ++ .size = 0x00070000, ++ }, ++ //1344k ++ [4] = { ++ .name = "kernel", ++ .offset = 0x000e0000, ++ .size = 0x00150000, ++ }, ++ //4M ++ [5] = { ++ .name = "rootfs", ++ .offset = 0x00230000, ++ .size = 0x00400000, ++ }, ++ //1856k ++ [6] = { ++ .name = "resource", ++ .offset = 0x00630000, ++ .size = 0x001d0000, ++ }, ++ //ALL 0--8M ++ [7] = { ++ .name = "all", ++ .offset = 0x00000000, ++ .size = 0x00800000, ++ }, ++ #endif ++#endif ++}; ++#elif defined(CONFIG_ONLY_USE_NOR_16M) ++// for 16M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ // 2M ++ [2] = { ++ .name = "kernel", ++ .offset = 0x00050000, ++ .size = 0x00200000, ++ }, ++ //13M + 512K ++ [3] = { ++ .name = "rootfs", ++ .offset = 0x00250000, ++ .size = 0x00DB0000, ++ }, ++ ++}; ++#elif defined(CONFIG_ONLY_USE_NOR_32M) ++// for 32M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //768K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x000c0000, ++ }, ++ // 2.5M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x00110000, ++ .size = 0x00280000, ++ }, ++ //27M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00390000, ++ .size = 0x01b00000, ++ }, ++ // 1.5M ++ [5] = { ++ .name = "resource", ++ .offset = 0x01e90000, ++ .size = 0x00170000, ++ }, ++}; ++#elif defined(CONFIG_USE_NOR_AND_NAND) ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //192K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //512K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x00080000, ++ }, ++ // 1.25M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x000D0000, ++ .size = 0x00140000, ++ }, ++ //5M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00210000, ++ .size = 0x00500000, ++ }, ++ // 1M ++ [5] = { ++ .name = "resource", ++ .offset = 0x00710000, ++ .size = 0x000E0000, ++ }, ++}; ++#elif defined(CONFIG_ONLY_USE_NAND) ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //192K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //512K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x00080000, ++ }, ++ // 1.25M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x000D0000, ++ .size = 0x00140000, ++ }, ++ //5M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00210000, ++ .size = 0x00500000, ++ }, ++ // 1M ++ [5] = { ++ .name = "resource", ++ .offset = 0x00710000, ++ .size = 0x000E0000, ++ }, ++}; ++#else ++ ++#endif ++ ++static struct sflash_platform_data flash_platform_data = ++{ ++ .speed_mode = (uint32_t)SYSTEM_SFLASH_FREQ, ++ .channel = 0, ++ .nr_parts = ARRAY_SIZE(gk_flash_parts), ++ .parts = gk_flash_parts, ++}; ++ ++static struct platform_device gk_flash_device0 = ++{ ++ .name = "gk_flash", ++ .id = 0, ++ .dev = ++ { ++ .platform_data = &flash_platform_data, ++ }, ++}; ++#endif/*defined(CONFIG_MTD_GK_SFLASH) || defined(CONFIG_MTD_GK_SFLASH_MODULE)*/ ++ ++/* ================ Watch Dog Timer ======================*/ ++#ifdef CONFIG_WATCHDOG_GOKE ++static struct resource gk_wdt_resource[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_WDT, SZ_4K), ++ [1] = DEFINE_RES_IRQ(WDT_IRQ), ++}; ++ ++struct platform_device gk_wdt = { ++ .name = "gk-wdt", ++ .id = -1, ++ .resource = gk_wdt_resource, ++ .num_resources = ARRAY_SIZE(gk_wdt_resource), ++ .dev = { ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif /* CONFIG_WATCHDOG_GOKE */ ++/* ================= End ======================*/ ++ ++/* ================ Inter Integrated Circuit ===================*/ ++ ++#ifdef CONFIG_I2C_GOKE ++static struct resource gk_idc_resources[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_IDC, SZ_4K), ++ [1] = DEFINE_RES_IRQ(IDC_IRQ), ++}; ++ ++struct gk_platform_i2c gk_idc_platform_info = { ++ .clk_limit = 400000, ++ .bulk_write_num = 60, ++ .get_clock = get_apb_bus_freq_hz, ++}; ++IDC_PARAM_CALL(0, gk_idc_platform_info, 0644); ++ ++struct platform_device gk_idc = { ++ .name = "i2c", ++ .id = 0, ++ .resource = gk_idc_resources, ++ .num_resources = ARRAY_SIZE(gk_idc_resources), ++ .dev = { ++ .platform_data = &gk_idc_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++#if (IDC_INSTANCES >= 2) ++static struct resource gk_idc_hdmi_resources[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_IDC2, SZ_4K), ++ [1] = DEFINE_RES_IRQ(IDC_HDMI_IRQ), ++}; ++ ++struct gk_platform_i2c gk_idc_hdmi_platform_info = { ++ .clk_limit = 400000, ++ .bulk_write_num = 60, ++ .i2c_class = I2C_CLASS_DDC, ++ .get_clock = get_apb_bus_freq_hz, ++}; ++IDC_PARAM_CALL(1, gk_idc_hdmi_platform_info, 0644); ++ ++struct platform_device gk_idc_hdmi = { ++ .name = "i2c", ++ .id = 1, ++ .resource = gk_idc_hdmi_resources, ++ .num_resources = ARRAY_SIZE(gk_idc_hdmi_resources), ++ .dev = { ++ .platform_data = &gk_idc_hdmi_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++#endif ++ ++#ifdef CONFIG_SPI_GOKE ++/* ==========================================================================*/ ++void gk_spi_cs_activate(struct gk_spi_cs_config *cs_config) ++{ ++ u8 cs_pin; ++ ++ if (cs_config->bus_id >= SPI_MASTER_INSTANCES || ++ cs_config->cs_id >= cs_config->cs_num) ++ return; ++ cs_pin = cs_config->cs_pins[cs_config->cs_id]; ++ gk_gpio_set_out(cs_pin, 0); ++} ++ ++void gk_spi_cs_deactivate(struct gk_spi_cs_config *cs_config) ++{ ++ u8 cs_pin; ++ ++ if (cs_config->bus_id >= SPI_MASTER_INSTANCES || ++ cs_config->cs_id >= cs_config->cs_num) ++ return; ++ ++ cs_pin = cs_config->cs_pins[cs_config->cs_id]; ++ gk_gpio_set_out(cs_pin, 1); ++} ++ ++struct resource gk_spi0_resources[] = { ++ [0] = { ++ .start = GK_VA_SSI1, ++ .end = GK_VA_SSI1 + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SSI_IRQ, ++ .end = SSI_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++int gk_spi0_cs_pins[] = {-1, -1, -1, -1, -1, -1, -1, -1}; ++GK_SPI_PARAM_CALL(0, gk_spi0_cs_pins, 0644); ++struct gk_spi_platform_info gk_spi0_platform_info = { ++ .support_dma = 0, ++#if (SPI_MASTER_INSTANCES == 5 ) ++ .fifo_entries = 64, ++#else ++ .fifo_entries = 16, ++#endif ++ .cs_num = ARRAY_SIZE(gk_spi0_cs_pins), ++ .cs_pins = gk_spi0_cs_pins, ++ .cs_activate = gk_spi_cs_activate, ++ .cs_deactivate = gk_spi_cs_deactivate, ++// .rct_set_ssi_pll = rct_set_ssi_pll, ++ .get_ssi_freq_hz = get_ssi0_freq_hz, ++}; ++ ++struct platform_device gk_spi0 = { ++ .name = "spi", ++ .id = 0, ++ .resource = gk_spi0_resources, ++ .num_resources = ARRAY_SIZE(gk_spi0_resources), ++ .dev = { ++ .platform_data = &gk_spi0_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++#if (SPI_MASTER_INSTANCES >= 2 ) ++struct resource gk_spi1_resources[] = { ++ [0] = { ++ .start = GK_VA_SSI2, ++ .end = GK_VA_SSI2 + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SSI2_IRQ, ++ .end = SSI2_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++int gk_spi1_cs_pins[] = {-1, -1, -1, -1, -1, -1, -1, -1}; ++GK_SPI_PARAM_CALL(1, gk_spi1_cs_pins, 0644); ++struct gk_spi_platform_info gk_spi1_platform_info = { ++ .support_dma = 0, ++ .fifo_entries = 16, ++ .cs_num = ARRAY_SIZE(gk_spi1_cs_pins), ++ .cs_pins = gk_spi1_cs_pins, ++ .cs_activate = gk_spi_cs_activate, ++ .cs_deactivate = gk_spi_cs_deactivate, ++ .get_ssi_freq_hz = get_ssi1_freq_hz, ++}; ++ ++struct platform_device gk_spi1 = { ++ .name = "spi", ++ .id = 1, ++ .resource = gk_spi1_resources, ++ .num_resources = ARRAY_SIZE(gk_spi1_resources), ++ .dev = { ++ .platform_data = &gk_spi1_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++#endif ++static struct spi_board_info gk_spi_devices[] = { ++ { ++#ifdef CONFIG_MMC_SPI ++ .modalias = "mmc_spi", ++ .max_speed_hz = 69000000/4, /* max spi clock (SCK) speed in HZ */ ++ .bus_num = 0, ++ .mode = SPI_MODE_3, ++ //.platform_data = &bfin_mmc_spi_pdata, ++ //.controller_data = &mmc_spi_chip_info, ++#else ++ .modalias = "spidev", ++#endif ++ .bus_num = 0, ++ .chip_select = 0, ++ }, ++#if (SPI_INSTANCES >= 2) ++ { ++ .modalias = "spidev", ++ .bus_num = 1, ++ .chip_select = 0, ++ } ++#endif ++}; ++ ++/* ================= rtc ======================*/ ++struct platform_device gk_rtc = { ++ .name = "gk-rtc", ++ .id = -1, ++}; ++/* ================= End ======================*/ ++ ++/* ================= ir ======================*/ ++ ++struct gk_ir_controller gk_platform_ir_controller0 = { ++ ++ .protocol = GK_IR_PROTOCOL_NEC, ++ .debug = 0, ++}; ++GK_IR_PARAM_CALL(gk_platform_ir_controller0, 0644); ++ ++struct platform_device gk_ir = { ++ .name = "ir", ++ .id = 1, ++ .dev = { ++ .platform_data = &gk_platform_ir_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ ++/* ================= pcm/i2s ======================*/ ++ ++struct platform_device gk_pcm0 = { ++ .name = "gk-pcm-audio", ++ .id = -1, ++}; ++ ++static struct resource gk_i2s0_resources[] = { ++ [0] = { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = I2STX_IRQ, ++ .end = I2SRX_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct gk_i2s_controller gk_i2s_controller0 = { ++ .aucodec_digitalio_0 = NULL, ++ .aucodec_digitalio_1 = NULL, ++ .aucodec_digitalio_2 = NULL, ++ .channel_select = NULL, ++ .set_audio_pll = NULL, ++}; ++ ++ ++struct platform_device gk_i2s0 = { ++ .name = "gk-i2s", ++ .id = 0, ++ .resource = gk_i2s0_resources, ++ .num_resources = ARRAY_SIZE(gk_i2s0_resources), ++ .dev = { ++ .platform_data = &gk_i2s_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++/* ================= musb ====================*/ ++static struct musb_hdrc_config gk_musb_config = { ++ .multipoint = 1, ++ .dyn_fifo = 0, ++ .big_endian = 0, ++ .dma = 0, ++ .num_eps = 8, ++ .ram_bits = 12, ++}; ++ ++static struct musb_hdrc_platform_data gk_musb_data = { ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ .mode = MUSB_HOST, ++#elif defined(CONFIG_GK_USB_SLAVE_MODE) ++ .mode = MUSB_PERIPHERAL, ++#elif defined(CONFIG_GK_USB_OTG_MODE) ++ .mode = MUSB_HOST, ++#endif ++ .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */ ++ .config = &gk_musb_config, ++}; ++ ++static struct resource gk_musb_resources[] = { ++ /* Order is significant! The start/end fields ++ * are updated during setup.. ++ */ ++ [0] = { ++ .start = GK_VA_USB, ++ .end = GK_VA_USB + 0x2000, ++ .flags = IORESOURCE_MEM, ++ }, ++/* ++ [1] = { ++ .start = GK_VA_USB_PHY, ++ .end = GK_VA_USB_PHY + 0xa00, ++ .flags = IORESOURCE_MEM, ++ }, ++*/ ++ [1] = { ++ .start = USBC_IRQ, ++ .end = USBC_IRQ, ++ .flags = IORESOURCE_IRQ, ++ .name = "mc", ++ }, ++}; ++ ++ ++static struct platform_device gk_musb = { ++ .name = "musb-gk", ++ .id = -1, ++ .dev = { ++ .platform_data = &gk_musb_data, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .num_resources = ARRAY_SIZE(gk_musb_resources), ++ .resource = gk_musb_resources, ++}; ++ ++ ++/* ================= End ======================*/ ++unsigned int gk_aud_get_dma_offset(void) ++{ ++ return AUDIO_DMA_REG_OFFSET; ++} ++EXPORT_SYMBOL(gk_aud_get_dma_offset); ++ ++ ++static struct platform_device *gk_devices[] __initdata = { ++ ++#ifdef CONFIG_MMC_GOKE ++#ifndef CONFIG_PHY_USE_SD_CLK ++ &gk_sd0, ++#endif ++#endif ++#ifdef CONFIG_WATCHDOG_GOKE ++ &gk_wdt, ++#endif ++#ifdef CONFIG_I2C_GOKE ++ &gk_idc, ++#if (IDC_INSTANCES >= 2) ++ &gk_idc_hdmi, ++#endif ++#endif ++ ++#ifdef CONFIG_FB_GOKE ++ &gk_fb0, ++ &gk_fb1, ++#endif ++#ifdef CONFIG_SPI_GOKE ++ &gk_spi0, ++#if (SPI_MASTER_INSTANCES >= 2 ) ++ &gk_spi1, ++#endif ++#endif ++#ifdef CONFIG_RTC_DRV_GOKE ++ &gk_rtc, ++#endif ++#ifdef CONFIG_INPUT_GOKE_IR ++ &gk_ir, ++#endif ++ ++#ifdef CONFIG_ETH_GOKE ++ &gk_eth0, ++#endif ++ //&gk_pcm0, ++ //&gk_i2s0, ++ &gk_musb, ++}; ++ ++//louis add ++/* ==========================================================================*/ ++ ++unsigned int gk_debug_level = GK_DEBUG_MEDIA | GK_DEBUG_DSP | GK_DEBUG_VI | GK_DEBUG_VO | GK_DEBUG_AAA; ++EXPORT_SYMBOL(gk_debug_level); ++ ++unsigned int gk_debug_info = 0; ++EXPORT_SYMBOL(gk_debug_info); ++ ++unsigned int gk_boot_splash_logo = 0; ++EXPORT_SYMBOL(gk_boot_splash_logo); ++ ++unsigned long gk_debug_lookup_name(const char *name) ++{ ++ return module_kallsyms_lookup_name(name); ++} ++EXPORT_SYMBOL(gk_debug_lookup_name); ++//end ++ ++void sensor_init(u8 active_level) ++{ ++ struct gk_gpio_io_info sensor_reset; ++ sensor_reset.gpio_id = gk_all_gpio_cfg.sensor_reset; ++ sensor_reset.active_level = active_level; ++ sensor_reset.active_delay = 1; ++ ++ printk("sensor board reset...\n"); ++ gk_set_gpio_output(&sensor_reset, 1); ++ mdelay(50);//100ms ++ gk_set_gpio_output(&sensor_reset, 0); ++ mdelay(200);//100ms ++} ++EXPORT_SYMBOL(sensor_init); ++ ++void sensor_power(u8 power) ++{ ++} ++EXPORT_SYMBOL(sensor_power); ++ ++/* ==========================================================================*/ ++static u8 cmdline_mac[6]; ++static int __init init_setup_mac(char *str) ++{ ++ int count, i, val; ++ ++ for (count = 0; count < 6 && *str; count++, str += 3) { ++ if (!isxdigit(str[0]) || !isxdigit(str[1])) ++ return 0; ++ if (str[2] != ((count < 5) ? ':' : '\0')) ++ return 0; ++ ++ for (i = 0, val = 0; i < 2; i++) { ++ val = val << 4; ++ val |= isdigit(str[i]) ? ++ str[i] - '0' : toupper(str[i]) - 'A' + 10; ++ } ++ cmdline_mac[count] = val; ++ } ++ return 1; ++ ++} ++__setup("mac=", init_setup_mac); ++ ++u8 cmdline_phytype; ++static int __init init_setup_phytype(char *str) ++{ ++ if (!isxdigit(str[0])) ++ return 0; ++ ++ cmdline_phytype = str[0] - '0'; ++ return 1; ++} ++__setup("phytype=", init_setup_phytype); ++EXPORT_SYMBOL(cmdline_phytype); ++ ++int __init gk_init_board(char *board_name) ++{ ++#ifdef CONFIG_ETH_GOKE ++ unsigned char mac_addr[6] = {00,0x11,0x22,0xa3,0xa0,00}; ++#endif ++ int retval = 0; ++ ++ //pr_info("Goke %s:\n", board_name); ++ //pr_info("\tboard revision:\t\t%d\n", 1); ++ ++ //retval = gk_init_pll(); ++ //BUG_ON(retval != 0); ++ // ++ printk("init timer...\n"); ++ retval = gk_init_timer(); ++ BUG_ON(retval != 0); ++ ++ printk("init gpio...\n"); ++ retval = gk_init_gpio(); ++ BUG_ON(retval != 0); ++ ++ gk_set_sd_detect_pin(gk_all_gpio_cfg.sd_detect); ++#ifdef CONFIG_SPI_GOKE ++ gk_spi0_cs_pins[0] = gk_all_gpio_cfg.spi0_en0; ++#if (SPI_MASTER_INSTANCES >= 2 ) ++ gk_spi1_cs_pins[0] = gk_all_gpio_cfg.spi1_en0; ++#endif ++#endif ++ ++ ++#ifdef CONFIG_ETH_GOKE ++ gk_set_phy_reset_pin(gk_all_gpio_cfg.phy_reset); ++ #if (ETH_INSTANCES >= 1) ++ if (cmdline_mac[0]) ++ memcpy(mac_addr, cmdline_mac, 6); ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ retval = gk_init_eth0(mac_addr); ++ BUG_ON(retval != 0); ++ #endif ++#endif ++ ++ retval = gk_init_dma(); ++ BUG_ON(retval != 0); ++ ++ //config video DAC for CVBS ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x00, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x04, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x08, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x10, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x14, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x18, 0x3F); ++ ++ gk_init_sd(); ++ ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_func_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_func_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++ gk_load_51mcu_code(PMU_ALWAYS_RUNNING); ++#endif ++ return retval; ++ ++} ++ ++static void __init gk_init_machine(void) ++{ ++ int i; ++ ++ //clkdev_init(); ++ gk_init_board("GK_chip"); ++ ++#if defined(CONFIG_MTD_SFLASH_GOKE) || defined(CONFIG_MTD_SFLASH_GOKE_MODULE) ++ platform_device_register(&gk_flash_device0); ++#endif ++ ++ gk_create_proc_dir(); ++ ++#ifdef CONFIG_FB_GOKE ++ gk_init_fb(); ++#endif ++ ++ printk("gk register devices %d\n", ARRAY_SIZE(gk_devices)); ++ ++ /* Register devices */ ++ platform_add_devices(gk_devices, ARRAY_SIZE(gk_devices)); ++ for (i = 0; i < ARRAY_SIZE(gk_devices); i++) { ++ device_set_wakeup_capable(&gk_devices[i]->dev, 1); ++ device_set_wakeup_enable(&gk_devices[i]->dev, 0); ++ } ++ ++ printk("gk register I2C\n"); ++ //i2c_register_board_info(0, &gk_ak4642_board_info, 1); ++ i2c_register_board_info(0, gk_board_vi_infos, ARRAY_SIZE(gk_board_vi_infos)); ++ i2c_register_board_info(1, gk_board_hdmi_infos, ARRAY_SIZE(gk_board_hdmi_infos)); ++ ++ spi_register_board_info(gk_spi_devices, ++ ARRAY_SIZE(gk_spi_devices)); ++ ++ pm_power_off = gk_power_off; ++ ++} ++ ++MACHINE_START(GOKE_IPC, "Goke IPC Board") ++ .map_io = gk_map_io, ++ .init_irq = gk_init_irq, ++ .handle_irq = gk_vic_handle_irq, ++ .timer = &gk_sys_timer, ++ .init_machine = gk_init_machine, ++ .restart = gk_restart, ++MACHINE_END ++ ++ +diff --git a/arch/arm/mach-gk710x/mdma.c b/arch/arm/mach-gk710x/mdma.c +new file mode 100644 +index 00000000..877f9b54 +--- /dev/null ++++ b/arch/arm/mach-gk710x/mdma.c +@@ -0,0 +1,238 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/mdma.c ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define TRANSFER_2D_WIDTH (1<<12) /* 4096*/ ++#define MAX_TRANSFER_2D_HEIGHT (1<<11) /* 2048*/ ++#define MAX_TRANSFER_SIZE_2D_UNIT (TRANSFER_2D_WIDTH * MAX_TRANSFER_2D_HEIGHT) /* 8MB*/ ++ ++#define TRANSFER_1D_WIDTH TRANSFER_2D_WIDTH ++#define MAX_TRANSFER_SIZE_1D_UNIT TRANSFER_1D_WIDTH ++ ++/* transfer 6 big blocks (although maximum is 8), because we may do another 1 small block and 1 line. total 8 Ops */ ++#define MAX_TRANSFER_SIZE_ONCE (MAX_TRANSFER_SIZE_2D_UNIT * 6) /* 48 MB*/ ++ ++#define MAX_OPS 8 ++ ++ ++static struct completion transfer_completion; ++ ++ ++/* handle 8MB at one time */ ++static inline int transfer_big_unit(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ int row_count; ++ if (size > MAX_TRANSFER_SIZE_2D_UNIT) { ++ printk("transfer_unit size %d bigger than %d \n", ++ size, MAX_TRANSFER_SIZE_2D_UNIT); ++ return -1; ++ } ++ ++ row_count = size / TRANSFER_2D_WIDTH; ++ ++ /* copy rows by 2D copy */ ++ if (row_count > 0) { ++ gk_dsp_writel(MDMA_SRC_1_BASE_REG, (long)src_addr); ++ gk_dsp_writel(MDMA_SRC_1_PITCH_REG, TRANSFER_2D_WIDTH); ++ gk_dsp_writel(MDMA_DST_BASE_REG, (long)dest_addr); ++ gk_dsp_writel(MDMA_DST_PITCH_REG, TRANSFER_2D_WIDTH); ++ gk_dsp_writel(MDMA_WIDTH_REG, TRANSFER_2D_WIDTH - 1); ++ gk_dsp_writel(MDMA_HEIGHT_REG, row_count - 1); ++ ++ /* start 2D copy */ ++ gk_dsp_writel(MDMA_OPCODE_REG, 1); ++ } ++ return 0; ++ ++} ++ ++ ++/* use 1D copy to copy max 4KB each time */ ++static inline int transfer_small_unit(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ ++ if (size > TRANSFER_1D_WIDTH) { ++ printk("transfer_unit size %d bigger than %d \n", ++ size, TRANSFER_1D_WIDTH); ++ return -1; ++ } ++ ++ /* linear copy */ ++ gk_dsp_writel(MDMA_SRC_1_BASE_REG, (long)src_addr); ++ gk_dsp_writel(MDMA_DST_BASE_REG, (long)dest_addr); ++ gk_dsp_writel(MDMA_WIDTH_REG, TRANSFER_1D_WIDTH - 1); ++ ++ /* start linear copy */ ++ gk_dsp_writel(MDMA_OPCODE_REG, 0); ++ ++ return 0; ++} ++ ++ ++ ++/* this is async function, just fill dma registers and let it run*/ ++static inline int transfer_once(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ //total pending count must be no bigger than 8 ++ int big_count; ++ int rows_count; ++ int i; ++ u32 transferred_bytes = 0; ++ int remain_bytes ; ++ ++ if (size > MAX_TRANSFER_SIZE_ONCE) { ++ printk(" size too big %d for transfer once \n", size); ++ return -1; ++ } ++ ++ big_count = size/MAX_TRANSFER_SIZE_2D_UNIT; ++ //big pages (each is 8MB) ++ for (i = big_count ; i > 0; i--) { ++ transfer_big_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, ++ MAX_TRANSFER_SIZE_2D_UNIT); ++ transferred_bytes += MAX_TRANSFER_SIZE_2D_UNIT; ++ } ++ remain_bytes = size - transferred_bytes; ++ ++ ++ //transfer rows (align to TRANSFER_2D_WIDTH) ++ rows_count = remain_bytes / TRANSFER_2D_WIDTH; ++ if (rows_count > 0) { ++ transfer_big_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, ++ TRANSFER_2D_WIDTH * rows_count); ++ transferred_bytes += TRANSFER_2D_WIDTH * rows_count; ++ remain_bytes = size - transferred_bytes; ++ } ++ ++ if (remain_bytes > 0) { ++ transfer_small_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, remain_bytes); ++ } ++ ++ return 0; ++} ++ ++/* this is synchronous function, will wait till transfer finishes */ ++int dma_memcpy(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ int remain_size = size; ++ int transferred_size = 0; ++ int current_transfer_size; ++ ++ while (remain_size > 0) { ++ if (remain_size > MAX_TRANSFER_SIZE_ONCE) { ++ remain_size -= MAX_TRANSFER_SIZE_ONCE; ++ current_transfer_size = MAX_TRANSFER_SIZE_ONCE; ++ } else { ++ current_transfer_size = remain_size; ++ remain_size = 0; ++ } ++ ++ transfer_once(dest_addr + transferred_size, ++ src_addr + transferred_size, current_transfer_size); ++ wait_for_completion(&transfer_completion); ++ transferred_size += current_transfer_size; ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(dma_memcpy); ++ ++ ++static irqreturn_t mdma_interrupt(int irq, void *dev_id) ++{ ++ int pending_ops; ++ pending_ops = gk_dsp_readl(MDMA_PENDING_OPS_REG); ++ ++ if (pending_ops == 0) { ++ /* if no following transfer */ ++ complete(&transfer_completion); ++ } else { ++ ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int hw_init(void) ++{ ++ int errorCode; ++ /* request irq, no device id, no irq sharing */ ++ errorCode = request_irq(MDMA_IRQ, mdma_interrupt, IRQF_TRIGGER_RISING, "mdma", 0); ++ ++ if (errorCode) { ++ printk("mdma irq request failed \n"); ++ return -1; ++ } ++ printk("mdma request irq: %d \n", MDMA_IRQ); ++ ++ return 0; ++} ++ ++ ++/* wait till transmit completes */ ++static void wait_transmit_complete(void) ++{ ++ int pending_ops; ++ pending_ops = gk_dsp_readl(MDMA_PENDING_OPS_REG); ++ ++ while(pending_ops!= 0) { ++ mdelay(10); ++ } ++} ++ ++static int __init mdma_init(void) ++{ ++ printk("mdma init...\n"); ++ ++ /* hardware and irq init */ ++ if (hw_init() != 0) ++ return -1; ++ /* init completion */ ++ init_completion(&transfer_completion); ++ ++ return 0; ++} ++ ++ ++static void __exit mdma_exit(void) ++{ ++ wait_transmit_complete(); ++} ++ ++MODULE_AUTHOR("Louis "); ++MODULE_DESCRIPTION("MDMA driver on gk"); ++MODULE_LICENSE("GPL v2"); ++MODULE_VERSION("1.0"); ++ ++module_init(mdma_init); ++module_exit(mdma_exit); ++ +diff --git a/arch/arm/mach-gk710x/rct.c b/arch/arm/mach-gk710x/rct.c +new file mode 100644 +index 00000000..457669ba +--- /dev/null ++++ b/arch/arm/mach-gk710x/rct.c +@@ -0,0 +1,194 @@ ++/* ++ * arch/arm/mach-gk/rct.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++u32 get_apb_bus_freq_hz(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0118; ++ u32 apb_freq; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0118 = gk_rct_readl(GK_VA_RCT + 0x0118); ++ if(div0118 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ apb_freq = (24 * arm_pll.bitc.fbdiv * 1000000)/(div0118 * 4 * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ } ++ else ++ { ++ apb_freq = GK_APB_FREQ; ++ } ++ ++ return apb_freq; ++} ++EXPORT_SYMBOL(get_apb_bus_freq_hz); ++ ++u32 get_uart_freq_hz(void) ++{ ++ return (u32)GK_UART_FREQ; ++} ++EXPORT_SYMBOL(get_uart_freq_hz); ++ ++u32 get_ssi0_freq_hz(void) ++{ ++ u32 div = gk_rct_readl(GK_VA_RCT + 0x0030) & 0xFF; ++ if(div == 0) ++ { ++ div = 8; ++ } ++ return (get_apb_bus_freq_hz()/div); ++} ++EXPORT_SYMBOL(get_ssi0_freq_hz); ++ ++u32 get_ssi1_freq_hz(void) ++{ ++ u32 div = gk_rct_readl(GK_VA_RCT + 0x00A0) & 0xFF; ++ if(div == 0) ++ { ++ div = 8; ++ } ++ return (get_apb_bus_freq_hz()/div); ++} ++EXPORT_SYMBOL(get_ssi1_freq_hz); ++ ++u32 get_sd_freq_hz(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0018; ++ u32 sd_freq; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0018 = gk_rct_readl(GK_VA_RCT + 0x0018); ++ if(div0018 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ sd_freq = (24 * arm_pll.bitc.fbdiv * 1000000)/(div0018 * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ } ++ else ++ { ++ sd_freq = GK_SD_FREQ; ++ } ++ return sd_freq; ++} ++EXPORT_SYMBOL(get_sd_freq_hz); ++ ++void set_sd_rct(u32 freq) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0018; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0018 = gk_rct_readl(GK_VA_RCT + 0x0018); ++ if(div0018 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ div0018 = (24 * arm_pll.bitc.fbdiv * 1000000)/(arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ div0018 /= freq; ++ gk_rct_writel(GK_VA_RCT + 0x0018, div0018); ++ } ++} ++EXPORT_SYMBOL(set_sd_rct); ++ ++u32 get_audio_clk_freq(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 PST_div; ++ u32 PRE_div; ++ u32 audio_freq; ++ u32 FRAC; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x024); ++ FRAC = gk_rct_readl(GK_VA_RCT + 0x078); ++ PST_div = gk_rct_readl(GK_VA_RCT + 0x084); ++ PRE_div = gk_rct_readl(GK_VA_RCT + 0x080); ++ if(PST_div * PRE_div * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ u64 FRAC_c; ++ u64 div_all; ++ FRAC_c = FRAC; ++ FRAC_c *= 15625; ++ FRAC_c *= 24; ++ div_all = 262144 * PST_div * PRE_div * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2; ++ FRAC_c += (div_all>>1); ++ do_div((FRAC_c), (div_all)); \ ++ audio_freq = (24 * (arm_pll.bitc.fbdiv * 1000000))/(PST_div * PRE_div * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ audio_freq += (u32)FRAC_c; ++ } ++ else ++ { ++ audio_freq = 12288000; ++ } ++ return audio_freq; ++} ++EXPORT_SYMBOL(get_audio_clk_freq); ++ +diff --git a/arch/arm/mach-gk710x/vi.c b/arch/arm/mach-gk710x/vi.c +new file mode 100644 +index 00000000..7e1b626a +--- /dev/null ++++ b/arch/arm/mach-gk710x/vi.c +@@ -0,0 +1,51 @@ ++/* ++ * arch/arm/mach-gk/vi.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++/* ==========================================================================*/ ++struct i2c_board_info gk_board_vi_infos[2] = { ++ [0] = { ++ .type = "gk_vi0", ++ .addr = 0x02, ++ }, ++ [1] = { ++ .type = "gk_vi1", ++ .addr = 0x03, ++ }, ++}; ++ ++struct i2c_board_info gk_board_hdmi_infos[2] = { ++ [0] = { ++ .type = "rtc8563", ++ .addr = 0x51, ++ }, ++ [1] = { ++ .type = "bma250", ++ .addr = 0x18, ++ }, ++}; ++ +diff --git a/arch/arm/mach-gk710xs/Kconfig b/arch/arm/mach-gk710xs/Kconfig +new file mode 100644 +index 00000000..a5a5247d +--- /dev/null ++++ b/arch/arm/mach-gk710xs/Kconfig +@@ -0,0 +1,38 @@ ++# ++# arch/arm/mach-gk710x/Kconfig ++# ++# History: ++# 2014/06/18 - [Kewell Liu] created file ++# ++# Copyright (C) 2002-2016, Goke Microelectronics China. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++# ++ ++if ARCH_GK710XS ++ ++config GK710XS_SDIO2 ++ bool "Gk710xs select SDIO2 enable" ++ default n ++ help ++ select SDIO2 enable. ++ ++#config MACH_GK7102S_ELEC_SC1135_V1_00 ++# depends on MACH_GK7102S ++# bool "GK7102S Elec Board" ++# help ++# select ELEC GK7102S + SC1135 Board ++endif ++ +diff --git a/arch/arm/mach-gk710xs/Makefile b/arch/arm/mach-gk710xs/Makefile +new file mode 100644 +index 00000000..1b837c23 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/Makefile +@@ -0,0 +1,12 @@ ++ ++obj-$(CONFIG_ARCH_GK710XS) += gk710xs.o ++obj-$(CONFIG_ARCH_GK710XS) += irq.o ++obj-$(CONFIG_ARCH_GK710XS) += rct.o ++obj-$(CONFIG_ARCH_GK710XS) += mdma.o dma.o ++obj-$(CONFIG_ARCH_GK710XS) += vi.o ++obj-$(CONFIG_ARCH_GK710XS) += mach-gk710xs.o ++ ++ccflags-$(CONFIG_ARCH_GK710XS) += -D__LINUX__ ++ ++ccflags-$(CONFIG_ARCH_GK710XS) += -Iarch/arm/mach-gk710xs/include ++ +diff --git a/arch/arm/mach-gk710xs/Makefile.boot b/arch/arm/mach-gk710xs/Makefile.boot +new file mode 100644 +index 00000000..2fa061fd +--- /dev/null ++++ b/arch/arm/mach-gk710xs/Makefile.boot +@@ -0,0 +1,6 @@ ++ ++zreladdr-y := $(shell printf "0x%08x" $$(($(CONFIG_PHYS_OFFSET) + $(TEXT_OFFSET)))) ++params_phys-y := $(shell printf "0x%08x" $$(($(CONFIG_PHYS_OFFSET) + 0x100))) ++ ++dtb-y += gk710xs-evb.dtb ++ +diff --git a/arch/arm/mach-gk710xs/dma.c b/arch/arm/mach-gk710xs/dma.c +new file mode 100644 +index 00000000..68e8eab7 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/dma.c +@@ -0,0 +1,508 @@ ++/* ++ * arch/arm/mach-gk/dma.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct dma_s G_dma; ++static spinlock_t dma_lock; ++static gk_dma_req_t *dummy_descriptor = NULL; ++static dma_addr_t dummy_descriptor_phys; ++ ++#ifdef CONFIG_GK_DMA_PROC ++static const char dma_proc_name[] = "dma"; ++static struct proc_dir_entry *dma_file; ++ ++static int gk_dma_proc_read(char *buf, char **start, off_t off, ++ int len, int *eof, void *data) ++{ ++ char *p = buf; ++ ++ p += sprintf(p, "You can add something here to debug DMA \n"); ++ ++ return p - buf; ++} ++#endif ++ ++extern void gk_usb_dma_irq(void); ++static irqreturn_t gk_dma_int_handler(int irq, void *dev_id) ++{ ++ struct dma_s *dma; ++ int i; ++ int j; ++ u32 ireg; ++ ++ dma = (struct dma_s *)dev_id; ++ ++ ireg = gk_dma_readl(DMA_INT_REG); ++ for (i = 0; i < NUM_DMA_CHANNELS; i++) { ++ if (ireg & (0x1 << i)) { ++ dma->chan[i].status = gk_dma_readl(DMA_CHAN_STA_REG(i)); ++ gk_dma_writel(DMA_CHAN_STA_REG(i), 0); ++ ++ for (j = 0; j < dma->chan[i].irq_count; j++) { ++ if (dma->chan[i].irq[j].enabled == 1) { ++ dma->chan[i].irq[j].handler( ++ dma->chan[i].irq[j].harg, ++ dma->chan[i].status); ++ } ++ } ++ } ++ } ++#if 0 ++ if ((ireg & 0x8) || (ireg & 0x1)) { ++ //if (ireg & 0x8) { ++ //printk("@:%x\n", ireg); ++ //printk("$\n"); ++ gk_usb_dma_irq(); ++ } ++#endif ++ return IRQ_HANDLED; ++} ++ ++#if (DMA_SUPPORT_DMA_FIOS == 1) ++static irqreturn_t gk_dma_fios_int_handler(int irq, void *dev_id) ++{ ++ struct dma_s *dma; ++ int i; ++ u32 ireg; ++ ++ dma = (struct dma_s *)dev_id; ++ ++ ireg = gk_dma_readl(DMA_FIOS_INT_REG); ++ if (ireg & DMA_INT_CHAN0) { ++ dma->chan[FIO_DMA_CHAN].status = ++ gk_dma_readl(DMA_FIOS_CHAN_STA_REG(FIO_DMA_CHAN)); ++ gk_dma_writel(DMA_FIOS_CHAN_STA_REG(FIO_DMA_CHAN), 0); ++ ++ for (i = 0; i < dma->chan[FIO_DMA_CHAN].irq_count; i++) { ++ if (dma->chan[FIO_DMA_CHAN].irq[i].enabled == 1) { ++ dma->chan[FIO_DMA_CHAN].irq[i].handler( ++ dma->chan[FIO_DMA_CHAN].irq[i].harg, ++ dma->chan[FIO_DMA_CHAN].status); ++ } ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++int gk_dma_request_irq(int chan, ++ gk_dma_handler handler, void *harg) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ if (unlikely(G_dma.chan[chan].irq_count > ++ MAX_DMA_CHANNEL_IRQ_HANDLERS)) { ++ pr_err("%s: chan[%d]'s irq_count[%d] > " ++ "MAX_DMA_CHANNEL_IRQ_HANDLERS[%d]!\n", ++ __func__, chan, G_dma.chan[chan].irq_count, ++ MAX_DMA_CHANNEL_IRQ_HANDLERS); ++ retval = -EINVAL; ++ goto gk_dma_request_irq_exit; ++ } ++ ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ G_dma.chan[chan].irq[i].handler = handler; ++ G_dma.chan[chan].irq[i].harg = harg; ++ G_dma.chan[chan].irq_count++; ++ break; ++ } ++ } ++ ++gk_dma_request_irq_exit: ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_request_irq_exit_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_request_irq); ++ ++void gk_dma_free_irq(int chan, gk_dma_handler handler) ++{ ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ return; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ if (unlikely(G_dma.chan[chan].irq_count > ++ MAX_DMA_CHANNEL_IRQ_HANDLERS)) { ++ pr_err("%s: chan[%d]'s irq_count[%d] > " ++ "MAX_DMA_CHANNEL_IRQ_HANDLERS[%d]!\n", ++ __func__, chan, G_dma.chan[chan].irq_count, ++ MAX_DMA_CHANNEL_IRQ_HANDLERS); ++ goto gk_dma_free_irq_exit; ++ } ++ ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ G_dma.chan[chan].irq[i].handler = NULL; ++ G_dma.chan[chan].irq[i].harg = NULL; ++ G_dma.chan[chan].irq_count--; ++ break; ++ } ++ } ++ ++ for (i = i + 1; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler != NULL) { ++ G_dma.chan[chan].irq[i - 1].enabled = ++ G_dma.chan[chan].irq[i].enabled; ++ G_dma.chan[chan].irq[i - 1].handler = ++ G_dma.chan[chan].irq[i].handler; ++ G_dma.chan[chan].irq[i - 1].harg = ++ G_dma.chan[chan].irq[i].harg; ++ G_dma.chan[chan].irq[i].handler = NULL; ++ G_dma.chan[chan].irq[i].harg = NULL; ++ G_dma.chan[chan].irq[i].enabled = 0; ++ } ++ } ++ ++gk_dma_free_irq_exit: ++ spin_unlock_irqrestore(&dma_lock, flags); ++} ++EXPORT_SYMBOL(gk_dma_free_irq); ++ ++int gk_dma_enable_irq(int chan, gk_dma_handler handler) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_enable_irq_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_enable_irq_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ retval = -EINVAL; ++ pr_err("%s: can't find 0x%x!\n", ++ __func__, (u32)handler); ++ break; ++ } ++ ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 1; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_enable_irq_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_enable_irq); ++ ++int gk_dma_disable_irq(int chan, gk_dma_handler handler) ++{ ++ int retval = 0; ++ int i; ++ unsigned long flags; ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_disable_irq_na; ++ } ++ ++ if (unlikely(handler == NULL)) { ++ pr_err("%s: handler is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_disable_irq_na; ++ } ++ ++ spin_lock_irqsave(&dma_lock, flags); ++ for (i = 0; i < MAX_DMA_CHANNEL_IRQ_HANDLERS; i++) { ++ if (G_dma.chan[chan].irq[i].handler == NULL) { ++ retval = -EINVAL; ++ pr_err("%s: can't find 0x%x!\n", ++ __func__, (u32)handler); ++ break; ++ } ++ ++ if (G_dma.chan[chan].irq[i].handler == handler) { ++ G_dma.chan[chan].irq[i].enabled = 0; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&dma_lock, flags); ++ ++gk_dma_disable_irq_na: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_disable_irq); ++ ++static inline int gk_req_dma(gk_dma_req_t * req, int chan) ++{ ++ int retval = 0; ++ u32 ctr = 0; ++ ++ if (unlikely(req->xfr_count > 0x003fffff)) { ++ pr_err("%s: xfr_count[0x%x] out of range!\n", ++ __func__, req->xfr_count); ++ retval = -EINVAL; ++ goto gk_req_dma_exit; ++ } ++ ++ gk_dma_writel(DMA_CHAN_STA_REG(chan), 0); ++ ++ if (req->next == NULL) { ++ gk_dma_writel(DMA_CHAN_SRC_REG(chan), req->src); ++ ++ gk_dma_writel(DMA_CHAN_DST_REG(chan), req->dst); ++ ++ ctr |= (req->attr | req->xfr_count); ++ ctr &= ~DMA_CHANX_CTR_D; ++ ctr |= DMA_CHANX_CTR_EN; ++ ++ } else {/* Descriptor mode */ ++ gk_dma_writel((u32) req, DMA_CHAN_DA_REG(chan)); ++ ++ ctr |= DMA_CHANX_CTR_D; ++ ctr |= DMA_CHANX_CTR_EN; ++ } ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), ctr); ++ ++gk_req_dma_exit: ++ return retval; ++} ++ ++int gk_dma_xfr(gk_dma_req_t *req, int chan) ++{ ++ int retval = 0; ++ ++ ++#ifdef CHECK_DMA_CHAN_USE_FLAG ++ unsigned long flags; ++#endif ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ retval = -EINVAL; ++ goto gk_dma_xfr_exit; ++ } ++ ++ if (unlikely(req == NULL)) { ++ pr_err("%s: req is NULL!\n", __func__); ++ retval = -EINVAL; ++ goto gk_dma_xfr_exit; ++ } ++ ++#ifdef CHECK_DMA_CHAN_USE_FLAG ++ spin_lock_irqsave(&dma_lock, flags); ++ G_dma.chan[chan].use_flag = 1; ++ spin_unlock_irqrestore(&dma_lock, flags); ++#endif ++ ++ retval = gk_req_dma(req, chan); ++ ++gk_dma_xfr_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_dma_xfr); ++ ++int gk_dma_desc_xfr(dma_addr_t desc_addr, int chan) ++{ ++ ++ ++ if (unlikely(desc_addr == 0)) { ++ pr_err("%s: desc_addr is NULL!\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely((desc_addr & 0x7) != 0)) { ++ pr_err("%s: desc_addr isn't aligned!\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return -EINVAL; ++ } ++ ++ if (gk_dma_readl(DMA_CHAN_CTR_REG(chan)) & DMA_CHANX_CTR_EN) ++ pr_err("%s: dma (channel = %d) is still enabled!\n", __func__, chan); ++ ++ gk_dma_writel(DMA_CHAN_DA_REG(chan), desc_addr); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), DMA_CHANX_CTR_EN | DMA_CHANX_CTR_D); ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_dma_desc_xfr); ++ ++int gk_dma_desc_stop(int chan) ++{ ++ ++ ++ if (unlikely(chan < 0 || chan >= NUM_DMA_CHANNELS)) { ++ pr_err("%s: chan[%d] < NUM_DMA_CHANNELS[%d]!\n", ++ __func__, chan, NUM_DMA_CHANNELS); ++ return -EINVAL; ++ } ++ ++ /* Disable DMA: following sequence is not mentioned at APM.*/ ++ if (gk_dma_readl(DMA_CHAN_CTR_REG(chan)) & DMA_CHANX_CTR_EN) { ++ gk_dma_writel(DMA_CHAN_STA_REG(chan), DMA_CHANX_STA_DD); ++ ++ ++ gk_dma_writel(DMA_CHAN_DA_REG(chan), dummy_descriptor_phys); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(chan), 0x28000000); ++ ++ ++ udelay(1); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_dma_desc_stop); ++ ++int gk_dma_read_ctrl_reg(int chan) ++{ ++ return gk_dma_readl(DMA_CHAN_CTR_REG(chan));//add by DONALD, for audio drv use, mask different register addr macro value. ++} ++EXPORT_SYMBOL(gk_dma_read_ctrl_reg); ++ ++ ++int __init gk_init_dma(void) ++{ ++ int retval = 0; ++ int i; ++ struct dma_s *dma = &G_dma; ++ gk_dma_req_t *dma_desc_array; ++ ++ spin_lock_init(&dma_lock); ++ memset(&G_dma, 0x0, sizeof(G_dma)); ++ ++ dummy_descriptor = dma_alloc_coherent(NULL, ++ sizeof(gk_dma_req_t) * 4, ++ &dummy_descriptor_phys, GFP_KERNEL); ++ if (!dummy_descriptor) { ++ retval = -ENOMEM; ++ goto gk_init_dma_exit; ++ } ++ ++ dma_desc_array = (gk_dma_req_t *)dummy_descriptor; ++ dma_desc_array->attr = DMA_DESC_EOC | DMA_DESC_WM | DMA_DESC_NI | ++ DMA_DESC_IE | DMA_DESC_ST | DMA_DESC_ID; ++ dma_desc_array->src = 0; ++ dma_desc_array->next = (gk_dma_req_t *)dummy_descriptor_phys; ++ dma_desc_array->rpt = dummy_descriptor_phys + sizeof(gk_dma_req_t); ++ dma_desc_array->dst = dummy_descriptor_phys + sizeof(gk_dma_req_t) * 2; ++ dma_desc_array->xfr_count = 0; ++ ++ retval = request_irq(DMA_IRQ, gk_dma_int_handler, ++ IRQ_TYPE_LEVEL_HIGH, "gk-dma", dma); ++ if (retval) { ++ pr_err("%s: request_irq %d fail %d!\n", ++ __func__, DMA_IRQ, retval); ++ goto gk_init_dma_exit; ++ } ++ ++ for (i = 0; i < NUM_DMA_CHANNELS; i++) { ++ gk_dma_writel(DMA_CHAN_STA_REG(i), 0); ++ ++ gk_dma_writel(DMA_CHAN_CTR_REG(i), 0x38000000); ++ ++ } ++ ++#if (DMA_SUPPORT_DMA_FIOS == 1) ++ retval = request_irq(DMA_FIOS_IRQ, gk_dma_fios_int_handler, ++ IRQ_TYPE_LEVEL_HIGH, "gk-fios-dma", dma); ++ if (retval){ ++ pr_err("%s: request_irq %d fail %d!\n", ++ __func__, DMA_FIOS_IRQ, retval); ++ goto gk_init_dma_exit; ++ } ++ gk_dma_writel(DMA_FIOS_CHAN_STA_REG(0), 0); ++ ++ ++ gk_dma_writel(DMA_FIOS_CHAN_CTR_REG(0), 0x38000000); ++ ++#endif ++ ++#ifdef CONFIG_GK_DMA_PROC ++ dma_file = create_proc_entry(dma_proc_name, S_IRUGO | S_IWUSR, ++ get_gk_proc_dir()); ++ if (dma_file == NULL) { ++ retval = -ENOMEM; ++ pr_err("%s: for %s fail!\n", __func__, dma_proc_name); ++ } else { ++ dma_file->read_proc = gk_dma_proc_read; ++ dma_file->write_proc = NULL; ++ } ++#endif ++ ++gk_init_dma_exit: ++ return retval; ++} ++ +diff --git a/arch/arm/mach-gk710xs/gk710xs.c b/arch/arm/mach-gk710xs/gk710xs.c +new file mode 100644 +index 00000000..a9d92dba +--- /dev/null ++++ b/arch/arm/mach-gk710xs/gk710xs.c +@@ -0,0 +1,736 @@ ++/* ++ * linux/arch/arm/mach-gk/gk.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++//#define KE_DEBUG ++ ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern u8* load_data_init(void); ++ ++ ++struct gk_mem_map_desc ++{ ++ char name[32]; ++ struct map_desc io_desc; ++}; ++ ++/* the module name MUST match hardware.h */ ++#define IOMAP_DESC_ENTRY(module, len) { \ ++ .virtual = GK_VA_##module, \ ++ .pfn = __phys_to_pfn(GK_PA_##module), \ ++ .length = (len), \ ++ .type = MT_DEVICE \ ++} ++ ++#define GK_IOMAP(module_name, module, len) { \ ++ .name = module_name, \ ++ IOMAP_DESC_ENTRY(module, len), \ ++} ++ ++ ++#define GK_IO_DESC_AHB_ID 0 ++#define GK_IO_DESC_APB_ID 1 ++#define GK_IO_DESC_PPM_ID 2 ++#define GK_IO_DESC_BSB_ID 3 ++#define GK_IO_DESC_DSP_ID 4 ++#define GK_IO_DESC_USR_ID 5 ++ ++static struct gk_mem_map_desc gk_mem_desc[] = ++{ ++ // reserved 0xF0000000 to hal1, and 0xF1000000 to hal2 ++ // used in get_hal1_virt & get_hal2_virt; ++ [GK_IO_DESC_AHB_ID] = ++ {/*0*/ ++ .name = "AHB", ++ .io_desc = ++ { ++ .virtual= GK_VA_AHB_BASE, ++ .pfn = __phys_to_pfn(GK_PA_AHB_BASE), ++ .length = 0x01000000, ++ .type = MT_DEVICE, ++ }, ++ }, ++ [GK_IO_DESC_APB_ID] = ++ {/*1*/ ++ .name = "APB", ++ .io_desc = ++ { ++ .virtual= GK_VA_APB_BASE, ++ .pfn = __phys_to_pfn(GK_PA_APB_BASE), ++ .length = 0x01000000, ++ .type = MT_DEVICE, ++ }, ++ }, ++ [GK_IO_DESC_PPM_ID] = ++ {/*2*/ ++ .name = "PPM", /*Private Physical Memory*/ ++ .io_desc = ++ { ++ .virtual= 0xc0000000, ++ .pfn = __phys_to_pfn(0xc0000000/*DEFAULT_MEM_START*/), ++ .length = CONFIG_PHYS_OFFSET-0xc0000000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_BSB_ID] = ++ {/*3*/ ++ .name = "BSB", ++ .io_desc = ++ { ++ .virtual= 0xf5000000, ++ .pfn = __phys_to_pfn(0xc2800000), ++ .length = 0x00200000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_DSP_ID] = ++ {/*4*/ ++ .name = "DSP", ++ .io_desc = ++ { ++ .virtual= 0xf6000000, ++ .pfn = __phys_to_pfn(0xC2a00000), ++ .length = 0x01500000, ++ .type = MT_MEMORY, ++ }, ++ }, ++ [GK_IO_DESC_USR_ID] = ++ {/*5*/ ++ .name = "USR", ++ .io_desc = ++ { ++ .virtual= 0xfe000000, // dsp_size <= 0xfe000000-0xf6000000 ++ .pfn = __phys_to_pfn(0xC3FF0000), ++ .length = 0x00010000, ++ .type = MT_MEMORY, ++ }, ++ }, ++}; ++ ++ ++ ++#if 1 ++//-----------HAL1------------- ++u32 get_hal1_virt(void) ++{ ++ return 0xF2000000; ++} ++EXPORT_SYMBOL(get_hal1_virt); ++ ++//-----------HAL2------------- ++u32 get_hal2_virt(void) ++{ ++ return 0xF3000000; ++} ++EXPORT_SYMBOL(get_hal2_virt); ++ ++//-----------AHB------------- ++u32 get_ahb_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_ahb_phys); ++ ++u32 get_ahb_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_ahb_virt); ++ ++u32 get_ahb_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_AHB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_ahb_size); ++ ++//-----------APB------------- ++u32 get_apb_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_apb_phys); ++ ++u32 get_apb_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_apb_virt); ++ ++u32 get_apb_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_APB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_apb_size); ++ ++//-----------PPM------------- ++u32 get_ppm_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_ppm_phys); ++ ++u32 get_ppm_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_ppm_virt); ++ ++u32 get_ppm_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_PPM_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_ppm_size); ++ ++//-----------DSP------------- ++u32 get_dspmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_dspmem_virt); ++ ++u32 get_dspmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_dspmem_size); ++ ++u32 get_dspmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_dspmem_phys); ++ ++//-----------BSB------------- ++u32 get_bsbmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_bsbmem_phys); ++ ++u32 get_bsbmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_bsbmem_virt); ++ ++u32 get_bsbmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_bsbmem_size); ++u32 get_usrmem_phys(void) ++{ ++ return __pfn_to_phys(gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.pfn); ++} ++EXPORT_SYMBOL(get_usrmem_phys); ++u32 get_usrmem_virt(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.virtual; ++} ++EXPORT_SYMBOL(get_usrmem_virt); ++u32 get_usrmem_size(void) ++{ ++ return gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.length; ++} ++EXPORT_SYMBOL(get_usrmem_size); ++ ++ ++ ++u32 gk_phys_to_virt(u32 paddr) ++{ ++ int i; ++ u32 phystart; ++ u32 phylength; ++ u32 phyoffset; ++ u32 vstart; ++ ++ for (i = 0; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ phystart = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ phylength = gk_mem_desc[i].io_desc.length; ++ vstart = gk_mem_desc[i].io_desc.virtual; ++ if ((paddr >= phystart) && (paddr < (phystart + phylength))) ++ { ++ phyoffset = paddr - phystart; ++ return (vstart + phyoffset); ++ } ++ } ++ ++ return __phys_to_virt(paddr); ++} ++EXPORT_SYMBOL(gk_phys_to_virt); ++ ++u32 gk_virt_to_phys(u32 vaddr) ++{ ++ int i; ++ u32 phystart; ++ u32 vlength; ++ u32 voffset; ++ u32 vstart; ++ ++ for (i = 0; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ phystart = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ vlength = gk_mem_desc[i].io_desc.length; ++ vstart = gk_mem_desc[i].io_desc.virtual; ++ if ((vaddr >= vstart) && (vaddr < (vstart + vlength))) ++ { ++ voffset = vaddr - vstart; ++ return (phystart + voffset); ++ } ++ } ++ ++ return __virt_to_phys(vaddr); ++} ++EXPORT_SYMBOL(gk_virt_to_phys); ++#endif ++ ++void get_stepping_info(int *chip, int *major, int *minor) ++{ ++ *chip = 0x5; ++ *major = 0x1; ++ *minor = 0x0; ++} ++EXPORT_SYMBOL(get_stepping_info); ++ ++/* ==========================================================================*/ ++u64 gk_dmamask = DMA_BIT_MASK(32); ++EXPORT_SYMBOL(gk_dmamask); ++ ++ ++/* ==========================================================================*/ ++static struct proc_dir_entry *gk_proc_dir = NULL; ++ ++int __init gk_create_proc_dir(void) ++{ ++ int retval = 0; ++ ++ printk("create proc dir\n"); ++ ++ gk_proc_dir = proc_mkdir("goke", NULL); ++ if (!gk_proc_dir) ++ retval = -ENOMEM; ++ ++ return retval; ++} ++ ++struct proc_dir_entry *get_gk_proc_dir(void) ++{ ++ return gk_proc_dir; ++} ++EXPORT_SYMBOL(get_gk_proc_dir); ++ ++/* ==========================================================================*/ ++typedef void* (*hal_function_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) ; ++ ++struct hw_ops *g_hw; ++EXPORT_SYMBOL(g_hw); ++ ++#if HW_HAL_MODE ++HAL_IO(hw) ++#else ++DIR_IO(hw) ++#endif ++ ++#if ADC_HAL_MODE ++HAL_IO(adc) ++#else ++DIR_IO(adc) ++#endif ++#if AUD_HAL_MODE ++HAL_IO(aud) ++#else ++DIR_IO(aud) ++#endif ++#if CRY_HAL_MODE ++HAL_IO(cry) ++#else ++DIR_IO(cry) ++#endif ++#if DDR_HAL_MODE ++HAL_IO(ddr) ++#else ++DIR_IO(ddr) ++#endif ++#if DMA_HAL_MODE ++HAL_IO(dma) ++#else ++DIR_IO(dma) ++#endif ++#if DSP_HAL_MODE ++HAL_IO(dsp) ++#else ++DIR_IO(dsp) ++#endif ++#if ETH_HAL_MODE ++HAL_IO(eth) ++#else ++DIR_IO(eth) ++#endif ++#if GREG_HAL_MODE ++HAL_IO(greg) ++#else ++DIR_IO(greg) ++#endif ++#if GPIO_HAL_MODE ++HAL_IO(gpio) ++#else ++DIR_IO(gpio) ++#endif ++#if I2C_HAL_MODE ++HAL_IO(i2c) ++#else ++DIR_IO(i2c) ++#endif ++#if I2S_HAL_MODE ++HAL_IO(i2s) ++#else ++DIR_IO(i2s) ++#endif ++#if IR_HAL_MODE ++HAL_IO(ir) ++#else ++DIR_IO(ir) ++#endif ++#if IRQ_HAL_MODE ++HAL_IO(irq) ++#else ++DIR_IO(irq) ++#endif ++#if MCU_HAL_MODE ++HAL_IO(mcu) ++#else ++DIR_IO(mcu) ++#endif ++#if PWM_HAL_MODE ++HAL_IO(pwm) ++#else ++DIR_IO(pwm) ++#endif ++#if RCT_HAL_MODE ++HAL_IO(rct) ++#else ++DIR_IO(rct) ++#endif ++#if SD_HAL_MODE ++HAL_IO(sd) ++#else ++DIR_IO(sd) ++#endif ++#if SF_HAL_MODE ++HAL_IO(sf) ++#else ++DIR_IO(sf) ++#endif ++#if SSI_HAL_MODE ++HAL_IO(ssi) ++#else ++DIR_IO(ssi) ++#endif ++#if TIMER_HAL_MODE ++HAL_IO(timer) ++#else ++DIR_IO(timer) ++#endif ++#if UART_HAL_MODE ++HAL_IO(uart) ++#else ++DIR_IO(uart) ++#endif ++#if USB_HAL_MODE ++HAL_IO(usb) ++#else ++DIR_IO(usb) ++#endif ++#if VOUT_HAL_MODE ++HAL_IO(vout) ++#else ++DIR_IO(vout) ++#endif ++#if WDT_HAL_MODE ++HAL_IO(wdt) ++#else ++DIR_IO(wdt) ++#endif ++#if EFUSE_HAL_MODE ++HAL_IO(efuse) ++#else ++DIR_IO(efuse) ++#endif ++#if USB_DMA_ADD_MODE ++unsigned char (*gk_usb_readb)(unsigned int ptr, unsigned int offset); ++unsigned short (*gk_usb_readw)(unsigned int ptr, unsigned int offset); ++unsigned int (*gk_usb_readl)(unsigned int ptr, unsigned int offset); ++void (*gk_usb_writeb)(unsigned int ptr, unsigned int offset, unsigned char value); ++void (*gk_usb_writew)(unsigned int ptr, unsigned int offset, unsigned short value); ++void (*gk_usb_writel)(unsigned int ptr, unsigned int offset, unsigned int value); ++ ++unsigned int (*gk_dma_readl)(unsigned int ptr); ++void (*gk_dma_writel)(unsigned int ptr, unsigned int value); ++#endif ++static inline unsigned int gk_hal_init (void *hal_base_address, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) ++{ ++ unsigned int rval=0; ++#if 1 ++ hal_function_t hal_init = (hal_function_t) (hal_base_address) ; ++ ++ g_hw = (struct hw_ops *)hal_init (arg0, arg1, arg2, arg3, arg4) ; ++ printk("hal version = %x \n", (u32)g_hw->get_version()); ++#endif ++ ++ return rval ; ++} ++ ++ ++static int __init early_boot_splash_logo(char *p) ++{ ++ printk("set boot splash logo = 1 \n"); ++ gk_boot_splash_logo = 1; ++ return 0; ++} ++early_param("boot_splash_logo_on", early_boot_splash_logo); ++ ++void __init gk_map_io(void) ++{ ++ int i; ++ u32 iop, ios, iov, hal_add; ++ u32 usr_phy_addr; ++ u32 bsb_phy_addr; ++ u32 bsb_size; ++ u32 dsp_phy_addr; ++ u32 dsp_size; ++#if 0 ++ u32 soc_type; //0:, 1:7102 ++#endif ++ u32 mem_size; ++ u32 mem_total; ++ u32 usr_size; //user used, cmem module ++ struct memblock_region *reg; ++ unsigned long kernelMemoryGet=0; ++ ++ /*************************/ ++ /* AHB */ ++ /*-----------------------*/ ++ /* APB */ ++ /*-----------------------*/ ++ /* PPM <3M> */ ++ /*-----------------------*/ ++ /* KER */ ++ /*-----------------------*/ ++ /* BSB <2M/4M> */ ++ /*-----------------------*/ ++ /* DSP */ ++ /*-----------------------*/ ++ /* USR <64K> */ ++ /*************************/ ++ ++ for (i = 0; i < GK_IO_DESC_BSB_ID; i++) ++ { ++ iop = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ ios = gk_mem_desc[i].io_desc.length; ++ iov = gk_mem_desc[i].io_desc.virtual; ++ printk("%s: 0x%x 0x%x -- 0x%x\n", gk_mem_desc[i].name, iop, iov, ios); ++ if (ios > 0) ++ { ++ iotable_init(&(gk_mem_desc[i].io_desc), 1); ++ } ++ } ++ ++ /* calc mem_size by uboot params parsing*/ ++ for_each_memblock(memory, reg) ++ { ++ unsigned long pages = memblock_region_memory_end_pfn(reg) - ++ memblock_region_memory_base_pfn(reg); ++ kernelMemoryGet = pages >> (20 - PAGE_SHIFT); ++ } ++ mem_size = kernelMemoryGet*1024*1024; ++ ++#if 0 ++ soc_type = *(volatile u32 *)CONFIG_U2K_SOC_ADDR; ++ ++ /* if can't get correct value from uboot env, use GK7102 for default*/ ++ if(soc_type>1) ++ soc_type = 1; ++ ++ ++ ++ mem_total = *(volatile u32 *)CONFIG_U2K_TOTAL_MEM; ++ if(mem_total != 64 && mem_total != 128) ++ { ++ /* set mem_total and bsb size by chip ID*/ ++ switch(soc_type) ++ { ++ case CONFIG_SOC_GK7102: /*GK7102*/ ++ mem_total = 64*1024*1024; ++ //bsb_size = 0x200000; /*use 2M for GK7102*/ ++ break; ++ case CONFIG_SOC_GK7101: /*GK*/ ++ default: ++ mem_total = 128*1024*1024; ++ //bsb_size = 0x400000; /*use 4M for GK*/ ++ break; ++ } ++ } ++ else mem_total = mem_total*1024*1024; ++#else ++ mem_total = (*(volatile u32 *)CONFIG_U2K_TOTAL_MEM)*1024*1024; ++#endif ++ ++ bsb_size = *(volatile u32 *)CONFIG_U2K_BSB_ADDR; ++ usr_size = 0x10000; ++ usr_phy_addr = 0xC0000000 + mem_total - usr_size; ++ bsb_phy_addr = 0xC0000000 + get_ppm_size() + mem_size; ++ dsp_phy_addr = bsb_phy_addr + bsb_size; ++ dsp_size = mem_total - get_ppm_size() - mem_size - bsb_size - usr_size; ++ ++ gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.pfn = __phys_to_pfn(bsb_phy_addr); ++ gk_mem_desc[GK_IO_DESC_BSB_ID].io_desc.length = bsb_size; ++ ++ gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.pfn = __phys_to_pfn(dsp_phy_addr); ++ gk_mem_desc[GK_IO_DESC_DSP_ID].io_desc.length = dsp_size; ++ ++ gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.pfn = __phys_to_pfn(usr_phy_addr); ++ gk_mem_desc[GK_IO_DESC_USR_ID].io_desc.length = usr_size; ++ ++ for (i = GK_IO_DESC_BSB_ID; i < ARRAY_SIZE(gk_mem_desc); i++) ++ { ++ iop = __pfn_to_phys(gk_mem_desc[i].io_desc.pfn); ++ ios = gk_mem_desc[i].io_desc.length; ++ iov = gk_mem_desc[i].io_desc.virtual; ++ printk("%s: 0x%x 0x%x -- 0x%x\n", gk_mem_desc[i].name, iop, iov, ios); ++ if (ios > 0) ++ { ++ iotable_init(&(gk_mem_desc[i].io_desc), 1); ++ } ++ } ++ ++ hal_add = *(volatile u32 *)CONFIG_U2K_HAL_ADDR; ++ gk_hal_init((void*)(gk_phys_to_virt(hal_add)), get_hal1_virt(), get_hal2_virt(), get_ahb_virt(), get_apb_virt(), (u32)iotable_init); ++} ++ ++void gk_load_51mcu_code(u32 code) ++{ ++ int i; ++ u8 *pData = NULL; ++ ++ pData = load_data_init(); ++ ++ /* Software Reset */ ++ gk_mcu_setbitsl( MCU_SYS_BASE + 0x0000, 1 << 5); ++ ++ /* Enable the download command */ ++ gk_mcu_setbitsl( MCU_SYS_BASE + 0x002C, 1 << 4); ++ ++ /* Disable the MCU51 core clock */ ++ gk_mcu_clrbitsl( MCU_SYS_BASE + 0x002C, 1 << 1); ++ ++ /* Download MCU code to boot ram */ ++ for(i=0;i<4096;i++) ++ { ++ gk_mcu_writel((GK_VA_PMU_C51_CODE + (i*4)), pData[i]); ++ } ++ gk_mcu_writel(MCU_SYS_BASE + 0x005C, code); ++ gk_mcu_writel(MCU_SYS_BASE + 0x002C, 0xB2);// 1011 0010 ++ gk_mcu_writel(MCU_SYS_BASE + 0x002C, 0x63);// 0110 0011 ++} ++ ++void gk_power_off(void) ++{ ++ ++ u32 code = PMU_POWER_OFF_CPU; ++ /* Disable interrupts first */ ++ local_irq_disable(); ++ local_fiq_disable(); ++ printk("gk power off...\n"); ++ ++#ifdef CONFIG_PMU_AUTOMOTIVE ++ code = PMU_AUTOMOTIVE_KEY; ++#endif ++#ifdef CONFIG_PMU_POWER_OFF_CPU ++ code = PMU_POWER_OFF_CPU; ++#endif ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++ code = PMU_ALWAYS_RUNNING_POWEROFF; ++#endif ++ gk_load_51mcu_code(code); ++ ++ //printk("c51 start ... ...\n"); ++ while(1){;} ++} ++ ++ ++//reboot, user watch dog ++void gk_restart(char mode, const char *cmd) ++{ ++ printk("gk reboot...\n"); ++ ++ gk_wdt_writel( WDOG_RELOAD_REG, 0xff); ++ gk_wdt_writel( WDOG_RESTART_REG, 0x4755); ++ gk_wdt_writel( WDOG_CONTROL_REG, WDOG_CTR_RST_EN | WDOG_CTR_EN); ++ mdelay(1000); ++ printk("watchdog reset failed...\n"); ++} ++ ++ ++/* ==========================================================================*/ ++DEFINE_SPINLOCK(gk_reg_lock); ++unsigned long gk_reg_flags; ++u32 gk_reglock_count = 0; ++ ++/* ==========================================================================*/ ++EXPORT_SYMBOL(gk_reg_lock); ++EXPORT_SYMBOL(gk_reg_flags); ++EXPORT_SYMBOL(gk_reglock_count); ++module_param (gk_reglock_count, uint, S_IRUGO); ++ ++ +diff --git a/arch/arm/mach-gk710xs/include/hal/hal.h b/arch/arm/mach-gk710xs/include/hal/hal.h +new file mode 100644 +index 00000000..2ea55b76 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/hal/hal.h +@@ -0,0 +1,22 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/hal.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_HAL_H ++#define __HAL_HAL_H ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710xs/include/hal/header.h b/arch/arm/mach-gk710xs/include/hal/header.h +new file mode 100644 +index 00000000..259c551b +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/hal/header.h +@@ -0,0 +1,20 @@ ++#ifndef _HEADER_H_INCLUDED_ ++#define _HEADER_H_INCLUDED_ ++ ++typedef struct gk_hal_header_s { ++ char magic[16] ; ++ unsigned int major_version ; ++ unsigned int minor_version ; ++ unsigned char chip_name[8] ; ++ unsigned char chip_stepping[8] ; ++ unsigned char build_id[32] ; ++ unsigned char build_date[32] ; ++} gk_hal_header_t; ++ ++typedef struct gk_hal_function_info_s { ++ unsigned int (*function)(unsigned int, unsigned int, ++ unsigned int, unsigned int) ; ++ const char* name ; ++} gk_hal_function_info_t ; ++ ++#endif // ifndef _HEADER_H_INCLUDED_ +diff --git a/arch/arm/mach-gk710xs/include/mach/audio_codec.h b/arch/arm/mach-gk710xs/include/mach/audio_codec.h +new file mode 100644 +index 00000000..e9ae79fb +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/audio_codec.h +@@ -0,0 +1,116 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/audio_codec.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __HAL_AUDIO_CODEC_H__ ++#define __HAL_AUDIO_CODEC_H__ ++ ++#include ++ ++#define AUDIO_DMA_REG_OFFSET (0x00000000) ++ ++ ++/*AHB genneral */ ++#define AHB_GREG_BASE (GK_VA_AHB_GREG) ++#define AHB_GREG_BASE_PHYS (GK_PA_AHB_GREG) ++#define AHB_GREG_REG(x) (AHB_GREG_BASE + (x)) ++#define AHB_GREG_REG_PHYS(x) (AHB_GREG_BASE_PHYS + (x)) ++ ++#define AHB_GREG_BASE_extern AHB_GREG_BASE ++ ++/*digital model*/ ++#define AUDIO_CODEC_DIGITAL_BASE (GK_VA_AUDIO_CODEC_DIGITAL) ++#define AUDIO_CODEC_DIGITAL_BASE_PHYS (GK_PA_AUDIO_CODEC_DIGITAL) ++#define AUDIO_CODEC_DIGITAL_REG(x) (AUDIO_CODEC_DIGITAL_BASE + (x)) ++#define AUDIO_CODEC_DIGITAL_REG_PHYS(x) (AUDIO_CODEC_DIGITAL_BASE_PHYS + (x)) ++ ++#define AUDIO_CODEC_DIGITAL_BASE_extern AUDIO_CODEC_DIGITAL_BASE ++ ++/*analog model*/ ++#define AUDIO_CODEC_ANALOG_BASE (GK_VA_AUDIO_CODEC_ANALOG) ++#define AUDIO_CODEC_ANALOG_BASE_PHYS (GK_PA_AUDIO_CODEC_ANALOG) ++#define AUDIO_CODEC_ANALOG_REG(x) (AUDIO_CODEC_ANALOG_BASE + (x)) ++#define AUDIO_CODEC_ANALOG_REG_PHYS(x) (AUDIO_CODEC_ANALOG_BASE_PHYS + (x)) ++ ++#define AUDIO_CODEC_ANALOG_BASE_extern AUDIO_CODEC_ANALOG_BASE ++ ++/*AHB genneral reg*/ ++#define AHB_GENNERNAL0_REG AHB_GREG_REG(0x00) ++#define AHB_GENNERNAL1_REG AHB_GREG_REG(0x04) ++ ++/*digital model reg */ ++#define AUDC_DIGITAL_SYS_RST_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x00) ++#define AUDC_DIGITAL_CKG_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x04) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL2_REG AUDIO_CODEC_DIGITAL_REG(0x18) ++#define AUDC_DIGITAL_TIMING_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x08) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x10) ++#define AUDC_DIGITAL_AUDIOBAND_STS_REG AUDIO_CODEC_DIGITAL_REG(0x1c) ++#define AUDC_DIGITAL_SDM_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x34) ++#define AUDC_DIGITAL_SDM_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x38) ++#define AUDC_DIGITAL_NF_SYNTH_1_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x3c) ++#define AUDC_DIGITAL_NF_SYNTH_1_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x40) ++#define AUDC_DIGITAL_NF_SYNTH_2_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x44) ++#define AUDC_DIGITAL_NF_SYNTH_2_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x48) ++#define AUDC_DIGITAL_DIG_MIC_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x4c) ++#define AUDC_DIGITAL_AUDIOBAND_STS2_REG AUDIO_CODEC_DIGITAL_REG(0x20) ++#define AUDC_DIGITAL_SDM_DWA_DATAIN_L_REG AUDIO_CODEC_DIGITAL_REG(0x54) ++#define AUDC_DIGITAL_SDM_DWA_DATAIN_R_REG AUDIO_CODEC_DIGITAL_REG(0x58) ++#define AUDC_DIGITAL_VALID_SIGNALS_REG AUDIO_CODEC_DIGITAL_REG(0x5c) ++#define AUDC_DIGITAL_PGA1_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x68) ++#define AUDC_DIGITAL_MMP1_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x60) ++#define AUDC_DIGITAL_MMP1_DPGA_CFG2_REG AUDIO_CODEC_DIGITAL_REG(0x64) ++#define AUDC_DIGITAL_MIX_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x50) ++ ++#define AUDC_DIGITAL_MMP2_DPGA_CFG1_REG AUDIO_CODEC_DIGITAL_REG(0x6c) ++#define AUDC_DIGITAL_MMP2_DPGA_CFG2_REG AUDIO_CODEC_DIGITAL_REG(0x70) ++#define AUDC_DIGITAL_INT1_DOUT_REG AUDIO_CODEC_DIGITAL_REG(0x74) ++#define AUDC_DIGITAL_FIFO_TH_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x7c) ++#define AUDC_DIGITAL_INT2_DOUT_REG AUDIO_CODEC_DIGITAL_REG(0x78) ++ ++#define AUDC_DIGITAL_TIMING_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x0c) ++#define AUDC_DIGITAL_AUDIOBAND_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x14) ++#define AUDC_DIGITAL_FIFO_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x80) ++#define AUDC_DIGITAL_FIFO_STS_REG AUDIO_CODEC_DIGITAL_REG(0x84) ++#define AUDC_DIGITAL_NF_SYNTH_5_NF_H_REG AUDIO_CODEC_DIGITAL_REG(0x88) ++#define AUDC_DIGITAL_NF_SYNTH_5_NF_L_REG AUDIO_CODEC_DIGITAL_REG(0x8c) ++#define AUDC_DIGITAL_INT_CTRL_REG AUDIO_CODEC_DIGITAL_REG(0x90) ++ ++#define AUDC_DIGITAL_SINE_GEN_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x24) ++#define AUDC_DIGITAL_SINE_GEN_CTRL1_REG AUDIO_CODEC_DIGITAL_REG(0x28) ++#define AUDC_DIGITAL_TEST_CTRL0_REG AUDIO_CODEC_DIGITAL_REG(0x30) ++ ++/*analog model reg */ ++#define AUDC_ANALOG_CTRL00_REG AUDIO_CODEC_ANALOG_REG(0x00) ++#define AUDC_ANALOG_CTRL01_REG AUDIO_CODEC_ANALOG_REG(0x04) ++#define AUDC_ANALOG_CTRL02_REG AUDIO_CODEC_ANALOG_REG(0x08) ++#define AUDC_ANALOG_CTRL03_REG AUDIO_CODEC_ANALOG_REG(0x0c) ++#define AUDC_ANALOG_CTRL04_REG AUDIO_CODEC_ANALOG_REG(0x10) ++#define AUDC_ANALOG_CTRL05_REG AUDIO_CODEC_ANALOG_REG(0x14) ++#define AUDC_ANALOG_CTRL06_REG AUDIO_CODEC_ANALOG_REG(0x18) ++#define AUDC_ANALOG_CTRL07_REG AUDIO_CODEC_ANALOG_REG(0x1c) ++#define AUDC_ANALOG_CTRL08_REG AUDIO_CODEC_ANALOG_REG(0x20) ++#define AUDC_ANALOG_CTRL09_REG AUDIO_CODEC_ANALOG_REG(0x24) ++#define AUDC_ANALOG_CTRL10_REG AUDIO_CODEC_ANALOG_REG(0x28) ++#define AUDC_ANALOG_CTRL11_REG AUDIO_CODEC_ANALOG_REG(0x2c) ++#define AUDC_ANALOG_CTRL12_REG AUDIO_CODEC_ANALOG_REG(0x30) ++#define AUDC_ANALOG_CTRL13_REG AUDIO_CODEC_ANALOG_REG(0x34) ++#define AUDC_ANALOG_CTRL14_REG AUDIO_CODEC_ANALOG_REG(0x38) ++#define AUDC_ANALOG_CTRL15_REG AUDIO_CODEC_ANALOG_REG(0x3c) ++#define AUDC_ANALOG_CTRL16_REG AUDIO_CODEC_ANALOG_REG(0x40) ++#define AUDC_ANALOG_CTRL17_REG AUDIO_CODEC_ANALOG_REG(0x44) ++#define AUDC_ANALOG_CTRL18_REG AUDIO_CODEC_ANALOG_REG(0x48) ++ ++extern unsigned int gk_aud_get_dma_offset(void); ++#endif /* __HAL_AUDIO_CODEC_H__ */ +diff --git a/arch/arm/mach-gk710xs/include/mach/crypto.h b/arch/arm/mach-gk710xs/include/mach/crypto.h +new file mode 100644 +index 00000000..ef01bbe9 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/crypto.h +@@ -0,0 +1,48 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/i2s.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_CRYPTO_H__ ++#define __HAL_CRYPTO_H__ ++ ++#include ++ ++#define CRYPTO_VA_BASE GK_VA_CRYPT_UNIT ++#define CRYPTO_VA_REG(x) (CRYPTO_VA_BASE + (x)) ++#define REG_CRYPTO_DES_KEY CRYPTO_VA_REG(0x00c) /* read/write */ ++#define REG_CRYPTO_DES_INPUT CRYPTO_VA_REG(0x014) /* read/write */ ++#define REG_CRYPTO_DES_OPCODE CRYPTO_VA_REG(0x004) /* read/write */ ++#define REG_CRYPTO_DES_OUTPUT_RDY CRYPTO_VA_REG(0x018) /* read */ ++#define REG_CRYPTO_DES_OUTPUT CRYPTO_VA_REG(0x020) /* read */ ++#define REG_CRYPTO_DES_INTERRUPT CRYPTO_VA_REG(0x000) /* read/write */ ++ ++#define REG_CRYPTO_AES_128_KEY CRYPTO_VA_REG(0x074) /* read/write */ ++ ++#define REG_CRYPTO_AES_192_KEY CRYPTO_VA_REG(0x064) /* read/write */ ++ ++#define REG_CRYPTO_AES_256_KEY CRYPTO_VA_REG(0x04c) /* read/write */ ++ ++#define REG_CRYPTO_AES_INPUT CRYPTO_VA_REG(0x084) /* read/write */ ++#define REG_CRYPTO_AES_OPCODE CRYPTO_VA_REG(0x02C) /* read/write */ ++#define REG_CRYPTO_AES_OUTPUT_RDY CRYPTO_VA_REG(0x088) /* read */ ++ ++#define REG_CRYPTO_AES_OUTPUT CRYPTO_VA_REG(0x098) /* read */ ++#define REG_CRYPTO_AES_INTERRUPT CRYPTO_VA_REG(0x028) /* read/write */ ++#define REG_CRYPTO_EFUSE_BOOT_SW_DIS CRYPTO_VA_REG(0x024) /* read/write */ ++ ++ ++ ++#endif /* __HAL_CRYPTO_H__ */ +diff --git a/arch/arm/mach-gk710xs/include/mach/debug-macro.S b/arch/arm/mach-gk710xs/include/mach/debug-macro.S +new file mode 100644 +index 00000000..f9b1a09d +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/debug-macro.S +@@ -0,0 +1,65 @@ ++/* ++ * arch/arm/mach-gk710xs/include/mach/debug-macro.S ++ * ++ * History: ++ * 2014/06/18 - [Kewell Liu] created file ++ * ++ * Copyright (C) 2002-2014, Goke Microelectronics China. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++ ++#ifdef CONFIG_MMU ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =GK_PA_APB_BASE @ Physical Base ++ ldr \rv, =GK_VA_APB_BASE @ Virtual Base ++ .endm ++ ++#else /* !CONFIG_MMU */ ++ ++ .macro addruart, rx, tmp ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 @ MMU enabled ++ moveq \rx, #GK_PA_APB_BASE @ physical base address ++ movne \rx, #GK_VA_APB_BASE @ virtual address ++ orr \rx, \rx, #UART_OFFSET ++ .endm ++ ++#endif /* CONFIG_MMU */ ++ ++.macro senduart, rd, rx ++ str \rd, [\rx, #UART_TH_OFFSET] ++.endm ++ ++.macro waituart, rd, rx ++1001: ++ ldr \rd, [\rx, #UART_LS_OFFSET] ++ tst \rd, #UART_LS_TEMT ++ beq 1001b ++ ++.endm ++ ++.macro busyuart, rd, rx ++1002: ++ ldr \rd, [\rx, #UART_LS_OFFSET] ++ tst \rd, #UART_LS_TEMT ++ beq 1002b ++.endm ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/dma.h b/arch/arm/mach-gk710xs/include/mach/dma.h +new file mode 100644 +index 00000000..9a61e2f2 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/dma.h +@@ -0,0 +1,171 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/dma.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_DMA_H__ ++#define __HAL_DMA_H__ ++#include ++ ++ ++#define DMA_BASE (GK_VA_DMAC) ++#define DMA_REG(x) (DMA_BASE + (x)) ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define DMA_SUPPORT_DMA_FIOS 0 /* DMA_FIOS */ ++ ++/****************************/ ++/* DMA Channel Assignments */ ++/****************************/ ++ ++#if (DMA_SUPPORT_DMA_FIOS == 0) ++/* DMA instance channel */ ++#define FIO_DMA_CHAN 0 ++#define I2S_RX_DMA_CHAN 1 ++#define I2S_TX_DMA_CHAN 2 ++#define HOST_RX_DMA_CHAN 3 ++#define HOST_TX_DMA_CHAN 4 ++#endif ++ ++#define MS_DMA_CHAN 3 ++/* No AHB MS controller */ ++ ++/* Max number of channel */ ++#define NUM_DMA_FIOS_CHANNELS DMA_SUPPORT_DMA_FIOS ++ ++ ++#define NUM_DMA_CHANNELS 4 ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++#define DMA_CHAN_TX 3 ++#define DMA_CHAN_RX 3 ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++#define DMA_CHAN_TX 0 ++#define DMA_CHAN_RX 3 ++#endif ++ ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define DMA_CHAN_CTR_REG(x) DMA_REG((0x31C + ((x) << 4))) ++#define DMA_CHAN_SRC_REG(x) DMA_REG((0x320 + ((x) << 4))) ++#define DMA_CHAN_DST_REG(x) DMA_REG((0x324 + ((x) << 4))) ++#define DMA_CHAN_STA_REG(x) DMA_REG((0x328 + ((x) << 4))) ++#define DMA_CHAN_DA_REG(x) DMA_REG((0x308 + ((x) << 2))) ++#define DMA_INT_REG DMA_REG(0x304) ++ ++/* DMA_CHANX_CTR_REG */ ++#define DMA_CHANX_CTR_EN 0x80000000 ++#define DMA_CHANX_CTR_D 0x40000000 ++#define DMA_CHANX_CTR_WM 0x20000000 ++#define DMA_CHANX_CTR_RM 0x10000000 ++#define DMA_CHANX_CTR_NI 0x08000000 ++#define DMA_CHANX_CTR_BLK_1024B 0x07000000 ++#define DMA_CHANX_CTR_BLK_512B 0x06000000 ++#define DMA_CHANX_CTR_BLK_256B 0x05000000 ++#define DMA_CHANX_CTR_BLK_128B 0x04000000 ++#define DMA_CHANX_CTR_BLK_64B 0x03000000 ++#define DMA_CHANX_CTR_BLK_32B 0x02000000 ++#define DMA_CHANX_CTR_BLK_16B 0x01000000 ++#define DMA_CHANX_CTR_BLK_8B 0x00000000 ++#define DMA_CHANX_CTR_TS_8B 0x00C00000 ++#define DMA_CHANX_CTR_TS_4B 0x00800000 ++#define DMA_CHANX_CTR_TS_2B 0x00400000 ++#define DMA_CHANX_CTR_TS_1B 0x00000000 ++ ++/* DMA descriptor bit fields */ ++#define DMA_DESC_EOC 0x01000000 ++#define DMA_DESC_WM 0x00800000 ++#define DMA_DESC_RM 0x00400000 ++#define DMA_DESC_NI 0x00200000 ++#define DMA_DESC_TS_8B 0x00180000 ++#define DMA_DESC_TS_4B 0x00100000 ++#define DMA_DESC_TS_2B 0x00080000 ++#define DMA_DESC_TS_1B 0x00000000 ++#define DMA_DESC_BLK_1024B 0x00070000 ++#define DMA_DESC_BLK_512B 0x00060000 ++#define DMA_DESC_BLK_256B 0x00050000 ++#define DMA_DESC_BLK_128B 0x00040000 ++#define DMA_DESC_BLK_64B 0x00030000 ++#define DMA_DESC_BLK_32B 0x00020000 ++#define DMA_DESC_BLK_16B 0x00010000 ++#define DMA_DESC_BLK_8B 0x00000000 ++#define DMA_DESC_ID 0x00000004 ++#define DMA_DESC_IE 0x00000002 ++#define DMA_DESC_ST 0x00000001 ++ ++/* DMA_CHANX_STA_REG */ ++#define DMA_CHANX_STA_DM 0x80000000 ++#define DMA_CHANX_STA_OE 0x40000000 ++#define DMA_CHANX_STA_DA 0x20000000 ++#define DMA_CHANX_STA_DD 0x10000000 ++#define DMA_CHANX_STA_OD 0x08000000 ++#define DMA_CHANX_STA_ME 0x04000000 ++#define DMA_CHANX_STA_BE 0x02000000 ++#define DMA_CHANX_STA_RWE 0x01000000 ++#define DMA_CHANX_STA_AE 0x00800000 ++#define DMA_CHANX_STA_DN 0x00400000 ++ ++/* DMA_INT_REG */ ++#define DMA_INT_CHAN(x) (0x1 << (x)) ++ ++#if defined(__FPGA__) ++#define DMA_INT_CHAN7 0x00000080 ++#define DMA_INT_CHAN6 0x00000040 ++#define DMA_INT_CHAN5 0x00000020 ++#endif ++ ++#define DMA_INT_CHAN4 0x00000010 ++#define DMA_INT_CHAN3 0x00000008 ++#define DMA_INT_CHAN2 0x00000004 ++#define DMA_INT_CHAN1 0x00000002 ++#define DMA_INT_CHAN0 0x00000001 ++ ++ ++/*********************************/ ++/* FIO/DMA Burst Setup */ ++/* - descriptor, non-descriptor */ ++/* - main, spare */ ++/*********************************/ ++ ++#if defined(__FPGA__) ++ ++#define DMA_NODC_MN_BURST_SIZE (DMA_CHANX_CTR_BLK_32B | DMA_CHANX_CTR_TS_4B) ++#define DMA_NODC_SP_BURST_SIZE (DMA_CHANX_CTR_BLK_32B | DMA_CHANX_CTR_TS_4B) ++#define DMA_DESC_MN_BURST_SIZE (DMA_DESC_BLK_32B | DMA_DESC_TS_4B) ++#define DMA_DESC_SP_BURST_SIZE (DMA_DESC_BLK_32B | DMA_DESC_TS_4B) ++#define FIO_MN_BURST_SIZE (FIO_DMACTR_BLK_32B | FIO_DMACTR_TS4B) ++#define FIO_SP_BURST_SIZE (FIO_DMACTR_BLK_32B | FIO_DMACTR_TS4B) ++ ++#else ++ ++#if (DMA_SUPPORT_DMA_FIOS == 0) ++#define DMA_NODC_MN_BURST_SIZE (DMA_CHANX_CTR_BLK_512B | DMA_CHANX_CTR_TS_4B) ++#define DMA_NODC_SP_BURST_SIZE (DMA_CHANX_CTR_BLK_512B | DMA_CHANX_CTR_TS_4B) ++#define DMA_DESC_MN_BURST_SIZE (DMA_DESC_BLK_512B | DMA_DESC_TS_4B) ++#define DMA_DESC_SP_BURST_SIZE (DMA_DESC_BLK_512B | DMA_DESC_TS_4B) ++#define FIO_MN_BURST_SIZE (FIO_DMACTR_BLK_512B | FIO_DMACTR_TS4B) ++#define FIO_SP_BURST_SIZE (FIO_DMACTR_BLK_512B | FIO_DMACTR_TS4B) ++#else ++ ++#endif ++ ++#endif ++ ++#endif /* __HAL_DMA_H__ */ +diff --git a/arch/arm/mach-gk710xs/include/mach/entry-macro.S b/arch/arm/mach-gk710xs/include/mach/entry-macro.S +new file mode 100644 +index 00000000..46dd9c23 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/entry-macro.S +@@ -0,0 +1,59 @@ ++/* ++ * arch/arm/mach-gk710xs/include/mach/entry-macro.S ++ * ++ * History: ++ * 2014/06/18 - [Kewell Liu] created file ++ * ++ * Copyright (C) 2002-2014, Goke Microelectronics China. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .macro stat2nr, stat, nr, tmp ++ rsbs \tmp, \stat, #0 ++ and \nr, \tmp, \stat ++ clzcc \nr, \nr ++ rsc \nr, \nr, #32 ++ teq \nr, #32 ++ .endm ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ldr \base, =(VIC1_BASE) ++ ldr \irqstat, [\base, #VIC_IRQ_STA_OFFSET] ++ stat2nr \irqstat, \irqnr, \tmp ++#if (VIC_INSTANCES >= 2) ++ bne 1000f ++ ldr \base, =(VIC2_BASE) ++ ldr \irqstat, [\base, #VIC_IRQ_STA_OFFSET] ++ stat2nr \irqstat, \irqnr, \tmp ++ addne \irqnr, \irqnr, #VIC2_INT_VEC(0) ++#endif ++1000: ++ .endm ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/eth.h b/arch/arm/mach-gk710xs/include/mach/eth.h +new file mode 100644 +index 00000000..346af333 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/eth.h +@@ -0,0 +1,466 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/eth.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __MACH_ETH_H__ ++#define __MACH_ETH_H__ ++ ++#include ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define ETH_INSTANCES 1 ++ ++#define SUPPORT_GMII 0 // 10/100 bits phy ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define ETH_REG(x) (GK_VA_ETH_GMAC + (x)) ++ ++#define ETH_MAC_CFG_REG ETH_REG(0x0000) ++ ++#define ETH_MAC_GMII_ADDR_REG ETH_REG(0x0004) ++#define ETH_MAC_GMII_DATA_REG ETH_REG(0x0008) ++ ++#define ETH_MAC_FRAME_FILTER_REG ETH_REG(0x000c) ++#define ETH_MAC_HASH_HI_REG ETH_REG(0x0010) ++#define ETH_MAC_HASH_LO_REG ETH_REG(0x0014) ++#define ETH_MAC_FLOW_CTR_REG ETH_REG(0x0018) ++#define ETH_MAC_VLAN_TAG_REG ETH_REG(0x001c) ++#define ETH_MAC_VERSION_REG ETH_REG(0x0058) ++ ++#define ETH_MAC_MAC0_HI_REG ETH_REG(0x0040) ++#define ETH_MAC_MAC0_LO_REG ETH_REG(0x0044) ++#define ETH_MAC_MAC1_HI_REG ETH_REG(0x0048) ++#define ETH_MAC_MAC1_LO_REG ETH_REG(0x004c) ++#define ETH_MAC_MAC2_HI_REG ETH_REG(0x0050) ++#define ETH_MAC_MAC2_LO_REG ETH_REG(0x0054) ++ ++ ++#define ETH_DMA_TX_POLL_DMD_REG ETH_REG(0x1000) ++#define ETH_DMA_RX_POLL_DMD_REG ETH_REG(0x1004) ++#define ETH_DMA_BUS_MODE_REG ETH_REG(0x1008) ++#define ETH_DMA_RX_DESC_LIST_REG ETH_REG(0x100c) ++#define ETH_DMA_TX_DESC_LIST_REG ETH_REG(0x1010) ++#define ETH_DMA_STATUS_REG ETH_REG(0x1014) ++#define ETH_DMA_MISS_FRAME_BOCNT_REG ETH_REG(0x1018) ++ ++#define ETH_DMA_INTEN_REG ETH_REG(0x101c) ++#define ETH_DMA_OPMODE_REG ETH_REG(0x1020) ++ ++#define ETH_DMA_HOST_TX_DESC_REG ETH_REG(0x1048) ++#define ETH_DMA_HOST_RX_DESC_REG ETH_REG(0x104c) ++#define ETH_DMA_HOST_TX_BUF_REG ETH_REG(0x1040) ++#define ETH_DMA_HOST_RX_BUF_REG ETH_REG(0x1044) ++ ++ ++//------------------------------------------- ++#define ETH_MAC_CFG_OFFSET (0x0000) ++#define ETH_MAC_FRAME_FILTER_OFFSET (0x000c) ++#define ETH_MAC_HASH_HI_OFFSET (0x0010) ++#define ETH_MAC_HASH_LO_OFFSET (0x0014) ++#define ETH_MAC_GMII_ADDR_OFFSET (0x0004) ++#define ETH_MAC_GMII_DATA_OFFSET (0x0008) ++#define ETH_MAC_FLOW_CTR_OFFSET (0x0018) ++#define ETH_MAC_VLAN_TAG_OFFSET (0x001c) ++#define ETH_MAC_VERSION_OFFSET (0x0058) ++#define ETH_MAC_MAC0_HI_OFFSET (0x0040) ++#define ETH_MAC_MAC0_LO_OFFSET (0x0044) ++#define ETH_MAC_MAC1_HI_OFFSET (0x0048) ++#define ETH_MAC_MAC1_LO_OFFSET (0x004c) ++#define ETH_MAC_MAC2_HI_OFFSET (0x0050) ++#define ETH_MAC_MAC2_LO_OFFSET (0x0054) ++ ++#define ETH_DMA_BUS_MODE_OFFSET (0x1008) ++#define ETH_DMA_TX_POLL_DMD_OFFSET (0x1000) ++#define ETH_DMA_RX_POLL_DMD_OFFSET (0x1004) ++#define ETH_DMA_RX_DESC_LIST_OFFSET (0x100c) ++#define ETH_DMA_TX_DESC_LIST_OFFSET (0x1010) ++#define ETH_DMA_STATUS_OFFSET (0x1014) ++#define ETH_DMA_OPMODE_OFFSET (0x1020) ++#define ETH_DMA_INTEN_OFFSET (0x101c) ++#define ETH_DMA_MISS_FRAME_BOCNT_OFFSET (0x1018) ++#define ETH_DMA_HOST_TX_DESC_OFFSET (0x1048) ++#define ETH_DMA_HOST_RX_DESC_OFFSET (0x104c) ++#define ETH_DMA_HOST_TX_BUF_OFFSET (0x1040) ++#define ETH_DMA_HOST_RX_BUF_OFFSET (0x1044) ++ ++/* ETH_MAC_CFG_REG */ ++#define ETH_MAC_CFG_WD 0x00800000 ++#define ETH_MAC_CFG_JD 0x00400000 ++#define ETH_MAC_CFG_BE 0x00200000 ++#define ETH_MAC_CFG_JE 0x00100000 ++#define ETH_MAC_CFG_IFG_96 0x000e0000 ++#define ETH_MAC_CFG_IFG_88 0x000c0000 ++#define ETH_MAC_CFG_IFG_80 0x000a0000 ++#define ETH_MAC_CFG_IFG_72 0x00080000 ++#define ETH_MAC_CFG_IFG_64 0x00060000 ++#define ETH_MAC_CFG_IFG_56 0x00040000 ++#define ETH_MAC_CFG_IFG_48 0x00020000 ++#define ETH_MAC_CFG_IFG_40 0x00000000 ++#define ETH_MAC_CFG_DCRS 0x00010000 ++#define ETH_MAC_CFG_PS 0x00008000 ++#define ETH_MAC_CFG_FES 0x00004000 ++#define ETH_MAC_CFG_DO 0x00002000 ++#define ETH_MAC_CFG_LM 0x00001000 ++#define ETH_MAC_CFG_DM 0x00000800 ++#define ETH_MAC_CFG_IPC 0x00000400 ++#define ETH_MAC_CFG_DR 0x00000200 ++#define ETH_MAC_CFG_LUD 0x00000100 ++#define ETH_MAC_CFG_ACS 0x00000080 ++#define ETH_MAC_CFG_BL_1 0x00000060 ++#define ETH_MAC_CFG_BL_4 0x00000040 ++#define ETH_MAC_CFG_BL_8 0x00000020 ++#define ETH_MAC_CFG_BL_10 0x00000000 ++#define ETH_MAC_CFG_DC 0x00000010 ++#define ETH_MAC_CFG_TE 0x00000008 /* Transmitter Enable */ ++#define ETH_MAC_CFG_RE 0x00000004 /* Receiver Enable */ ++ ++/* ETH_MAC_FRAME_FILTER_REG */ ++#define ETH_MAC_FRAME_FILTER_RA 0x80000000 ++#define ETH_MAC_FRAME_FILTER_SAF 0x00000200 ++#define ETH_MAC_FRAME_FILTER_SAIF 0x00000100 ++#define ETH_MAC_FRAME_FILTER_PCF_PASS 0x000000c0 ++#define ETH_MAC_FRAME_FILTER_PCF_FAIL 0x00000040 ++#define ETH_MAC_FRAME_FILTER_PCF_ALL 0x00000000 ++#define ETH_MAC_FRAME_FILTER_DBF 0x00000020 ++#define ETH_MAC_FRAME_FILTER_PM 0x00000010 ++#define ETH_MAC_FRAME_FILTER_DAIF 0x00000008 ++#define ETH_MAC_FRAME_FILTER_HMC 0x00000004 ++#define ETH_MAC_FRAME_FILTER_HUC 0x00000002 ++#define ETH_MAC_FRAME_FILTER_PR 0x00000001 ++ ++/* ETH_MAC_GMII_ADDR_REG */ ++#define ETH_MAC_GMII_ADDR_PA(x) (((x) & 0x1f) << 11) ++#define ETH_MAC_GMII_ADDR_GR(x) (((x) & 0x1f) << 6) ++#define ETH_MAC_GMII_ADDR_CR_250_300MHZ 0x00000014 ++#define ETH_MAC_GMII_ADDR_CR_150_250MHZ 0x00000010 ++#define ETH_MAC_GMII_ADDR_CR_35_60MHZ 0x0000000c ++#define ETH_MAC_GMII_ADDR_CR_20_35MHZ 0x00000008 ++#define ETH_MAC_GMII_ADDR_CR_100_150MHZ 0x00000004 ++#define ETH_MAC_GMII_ADDR_CR_60_100MHZ 0x00000000 ++#define ETH_MAC_GMII_ADDR_GW 0x00000002 ++#define ETH_MAC_GMII_ADDR_GB 0x00000001 ++ ++/* ETH_MAC_FLOW_CTR_REG */ ++#define ETH_MAC_FLOW_CTR_PT(x) (((x) & 0xffff) << 16) ++#define ETH_MAC_FLOW_CTR_PLT_256 0x00000030 ++#define ETH_MAC_FLOW_CTR_PLT_144 0x00000020 ++#define ETH_MAC_FLOW_CTR_PLT_28 0x00000010 ++#define ETH_MAC_FLOW_CTR_PLT_4 0x00000000 ++#define ETH_MAC_FLOW_CTR_UP 0x00000008 ++#define ETH_MAC_FLOW_CTR_RFE 0x00000004 ++#define ETH_MAC_FLOW_CTR_TFE 0x00000002 ++#define ETH_MAC_FLOW_CTR_FCBBPA 0x00000001 ++ ++/* ETH_MAC_VERSION_REG */ ++#define ETH_MAC_VERSION_USER(v) (((x) & 0x0000ff00) >> 8) ++#define ETH_MAC_VERSION_SYN(v) ((x) & 0x000000ff) ++ ++/* ETH_DMA_BUS_MODE_REG */ ++#define ETH_DMA_BUS_MODE_FB 0x00010000 ++#define ETH_DMA_BUS_MODE_PR4 0x0000c000 ++#define ETH_DMA_BUS_MODE_PR3 0x00008000 ++#define ETH_DMA_BUS_MODE_PR2 0x00004000 ++#define ETH_DMA_BUS_MODE_PR1 0x00000000 ++#define ETH_DMA_BUS_MODE_PBL_32 0x00002000 ++#define ETH_DMA_BUS_MODE_PBL_16 0x00001000 ++#define ETH_DMA_BUS_MODE_PBL_8 0x00000800 ++#define ETH_DMA_BUS_MODE_PBL_4 0x00000400 ++#define ETH_DMA_BUS_MODE_PBL_2 0x00000200 ++#define ETH_DMA_BUS_MODE_PBL_1 0x00000100 ++#define ETH_DMA_BUS_MODE_DSL(len) ((len & 0x1f) << 2) ++#define ETH_DMA_BUS_MODE_DA_RX 0x00000002 ++#define ETH_DMA_BUS_MODE_DA_TX 0x00000000 ++#define ETH_DMA_BUS_MODE_SWR 0x00000001 ++ ++/* ETH_DMA_STATUS_REG */ ++#define ETH_DMA_STATUS_GPI 0x10000000 ++#define ETH_DMA_STATUS_GMI 0x08000000 ++#define ETH_DMA_STATUS_GLI 0x04000000 ++#define ETH_DMA_STATUS_EB_MASK 0x03800000 ++#define ETH_DMA_STATUS_EB_TXDMA 0x02000000 ++#define ETH_DMA_STATUS_EB_RXDMA 0x00000000 ++#define ETH_DMA_STATUS_EB_RXFER 0x01000000 ++#define ETH_DMA_STATUS_EB_TXFER 0x00000000 ++#define ETH_DMA_STATUS_EB_DESC 0x00800000 ++#define ETH_DMA_STATUS_EB_DBUF 0x00000000 ++#define ETH_DMA_STATUS_TS_MASK 0x00700000 ++#define ETH_DMA_STATUS_TS_CTD 0x00700000 ++#define ETH_DMA_STATUS_TS_SUSP 0x00600000 ++#define ETH_DMA_STATUS_TS_READ 0x00300000 ++#define ETH_DMA_STATUS_TS_WAIT 0x00200000 ++#define ETH_DMA_STATUS_TS_FETCH 0x00100000 ++#define ETH_DMA_STATUS_TS_STOP 0x00000000 ++#define ETH_DMA_STATUS_RS_MASK 0x000e0000 ++#define ETH_DMA_STATUS_RS_RCV 0x000e0000 ++#define ETH_DMA_STATUS_RS_CRD 0x000a0000 ++#define ETH_DMA_STATUS_RS_SUSP 0x00080000 ++#define ETH_DMA_STATUS_RS_WAIT 0x00060000 ++#define ETH_DMA_STATUS_RS_FETCH 0x00020000 ++#define ETH_DMA_STATUS_RS_STOP 0x00000000 ++#define ETH_DMA_STATUS_NIS 0x00010000 ++#define ETH_DMA_STATUS_AIS 0x00008000 ++#define ETH_DMA_STATUS_ERI 0x00004000 ++#define ETH_DMA_STATUS_FBI 0x00002000 ++#define ETH_DMA_STATUS_ETI 0x00000400 ++#define ETH_DMA_STATUS_RWT 0x00000200 ++#define ETH_DMA_STATUS_RPS 0x00000100 ++#define ETH_DMA_STATUS_RU 0x00000080 ++#define ETH_DMA_STATUS_RI 0x00000040 ++#define ETH_DMA_STATUS_UNF 0x00000020 ++#define ETH_DMA_STATUS_OVF 0x00000010 ++#define ETH_DMA_STATUS_TJT 0x00000008 ++#define ETH_DMA_STATUS_TU 0x00000004 ++#define ETH_DMA_STATUS_TPS 0x00000002 ++#define ETH_DMA_STATUS_TI 0x00000001 ++ ++/* ETH_DMA_OPMODE_REG */ ++#define ETH_DMA_OPMODE_DT 0x04000000 ++#define ETH_DMA_OPMODE_RSF 0x02000000 ++#define ETH_DMA_OPMODE_DFF 0x01000000 ++#define ETH_DMA_OPMODE_TSF 0x00200000 ++#define ETH_DMA_OPMODE_FTF 0x00100000 ++#define ETH_DMA_OPMODE_TTC_16 0x0001c000 ++#define ETH_DMA_OPMODE_TTC_24 0x00018000 ++#define ETH_DMA_OPMODE_TTC_32 0x00014000 ++#define ETH_DMA_OPMODE_TTC_40 0x00010000 ++#define ETH_DMA_OPMODE_TTC_256 0x0000c000 ++#define ETH_DMA_OPMODE_TTC_192 0x00008000 ++#define ETH_DMA_OPMODE_TTC_128 0x00004000 ++#define ETH_DMA_OPMODE_TTC_64 0x00000000 ++#define ETH_DMA_OPMODE_ST 0x00002000 ++#define ETH_DMA_OPMODE_RFD_4K 0x00001800 ++#define ETH_DMA_OPMODE_RFD_3K 0x00001000 ++#define ETH_DMA_OPMODE_RFD_2K 0x00000800 ++#define ETH_DMA_OPMODE_RFD_1K 0x00000000 ++#define ETH_DMA_OPMODE_RFA_4K 0x00000600 ++#define ETH_DMA_OPMODE_RFA_3K 0x00000400 ++#define ETH_DMA_OPMODE_RFA_2K 0x00000200 ++#define ETH_DMA_OPMODE_RFA_1K 0x00000000 ++#define ETH_DMA_OPMODE_EFC 0x00000100 ++#define ETH_DMA_OPMODE_FEF 0x00000080 ++#define ETH_DMA_OPMODE_FUF 0x00000040 ++#define ETH_DMA_OPMODE_RTC_128 0x00000018 ++#define ETH_DMA_OPMODE_RTC_96 0x00000010 ++#define ETH_DMA_OPMODE_RTC_32 0x00000008 ++#define ETH_DMA_OPMODE_RTC_64 0x00000000 ++#define ETH_DMA_OPMODE_OSF 0x00000004 ++#define ETH_DMA_OPMODE_SR 0x00000002 ++ ++/* ETH_DMA_INTEN_REG */ ++#define ETH_DMA_INTEN_NIE 0x00010000 ++#define ETH_DMA_INTEN_AIE 0x00008000 ++#define ETH_DMA_INTEN_ERE 0x00004000 ++#define ETH_DMA_INTEN_FBE 0x00002000 ++#define ETH_DMA_INTEN_ETE 0x00000400 ++#define ETH_DMA_INTEN_RWE 0x00000200 ++#define ETH_DMA_INTEN_RSE 0x00000100 ++#define ETH_DMA_INTEN_RUE 0x00000080 ++#define ETH_DMA_INTEN_RIE 0x00000040 ++#define ETH_DMA_INTEN_UNE 0x00000020 ++#define ETH_DMA_INTEN_OVE 0x00000010 ++#define ETH_DMA_INTEN_TJE 0x00000008 ++#define ETH_DMA_INTEN_TUE 0x00000004 ++#define ETH_DMA_INTEN_TSE 0x00000002 ++#define ETH_DMA_INTEN_TIE 0x00000001 ++ ++/* ETH_DMA_MISS_FRAME_BOCNT_REG */ ++#define ETH_DMA_MISS_FRAME_BOCNT_FIFO 0x10000000 ++#define ETH_DMA_MISS_FRAME_BOCNT_APP(v) (((v) & 0x0ffe0000) >> 17) ++#define ETH_DMA_MISS_FRAME_BOCNT_FRAME 0x00001000 ++#define ETH_DMA_MISS_FRAME_BOCNT_HOST(v) ((v) & 0x0000ffff) ++ ++/* Receive Descriptor 0 (RDES0) */ ++#define ETH_RDES0_OWN 0x80000000 ++#define ETH_RDES0_AFM 0x40000000 ++#define ETH_RDES0_FL(v) (((v) & 0x3fff0000) >> 16) ++#define ETH_RDES0_ES 0x00008000 ++#define ETH_RDES0_DE 0x00004000 ++#define ETH_RDES0_SAF 0x00002000 ++#define ETH_RDES0_LE 0x00001000 ++#define ETH_RDES0_OE 0x00000800 ++#define ETH_RDES0_VLAN 0x00000400 ++#define ETH_RDES0_FS 0x00000200 ++#define ETH_RDES0_LS 0x00000100 ++#define ETH_RDES0_IPC 0x00000080 ++#define ETH_RDES0_LC 0x00000040 ++#define ETH_RDES0_FT 0x00000020 ++#define ETH_RDES0_RWT 0x00000010 ++#define ETH_RDES0_RE 0x00000008 ++#define ETH_RDES0_DBE 0x00000004 ++#define ETH_RDES0_CE 0x00000002 ++#define ETH_RDES0_RX 0x00000001 ++ ++#define ETH_RDES0_COE_MASK 0x000000a1 ++#define ETH_RDES0_COE_LENLT600 0x00000000 /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ ++#define ETH_RDES0_COE_UNSUPPORTED 0x00000001 /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ ++#define ETH_RDES0_COE_RESERVED 0x00000080 /* Bit(5:7:0)=>2 Reserved */ ++#define ETH_RDES0_COE_CHKBYPASS 0x00000081 /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ ++#define ETH_RDES0_COE_NOCHKERROR 0x00000020 /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ ++#define ETH_RDES0_COE_PLCHKERROR 0x00000021 /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ ++#define ETH_RDES0_COE_HDRCHKERROR 0x000000a0 /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ ++#define ETH_RDES0_COE_HDRPLCHKERROR 0x000000a1 /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ ++ ++/* Receive Descriptor 1 (RDES1) */ ++#define ETH_RDES1_DIC 0x80000000 ++#define ETH_RDES1_RER 0x02000000 ++#define ETH_RDES1_RCH 0x01000000 ++#define ETH_RDES1_RBS2(v) (((v) & 0x003ff800) >> 11) /* Receive Buffer 2 Size */ ++#define ETH_RDES1_RBS1(v) ((v) & 0x000007ff) /* Receive Buffer 1 Size */ ++#define ETH_RDES1_RBS2x(x) (((x) << 11) & 0x003ff800) /* Receive Buffer 2 Size */ ++#define ETH_RDES1_RBS1x(x) ((x) & 0x000007ff) /* Receive Buffer 1 Size */ ++ ++/* Transmit Descriptor 0 (TDES0) */ ++#define ETH_TDES0_OWN 0x80000000 ++#define ETH_TDES0_TTSS 0x00020000 ++#define ETH_TDES0_IHE 0x00010000 ++#define ETH_TDES0_ES 0x00008000 ++#define ETH_TDES0_JT 0x00004000 ++#define ETH_TDES0_FF 0x00002000 ++#define ETH_TDES0_PCE 0x00001000 ++#define ETH_TDES0_LCA 0x00000800 ++#define ETH_TDES0_NC 0x00000400 ++#define ETH_TDES0_LCO 0x00000200 ++#define ETH_TDES0_EC 0x00000100 ++#define ETH_TDES0_VF 0x00000080 ++#define ETH_TDES0_CC(v) (((v) & 0x00000078) >> 3) ++#define ETH_TDES0_ED 0x00000004 ++#define ETH_TDES0_UF 0x00000002 ++#define ETH_TDES0_DB 0x00000001 ++#define ETH_TDES0_ES_MASK (ETH_TDES0_UF | ETH_TDES0_ED | \ ++ ETH_TDES0_EC | ETH_TDES0_LCO | \ ++ ETH_TDES0_NC | ETH_TDES0_LCA | \ ++ ETH_TDES0_FF | ETH_TDES0_JT | \ ++ ETH_TDES0_ES) ++ ++/* Transmit Descriptor 1 (TDES1) */ ++#define ETH_TDES1_IC 0x80000000 ++#define ETH_TDES1_LS 0x40000000 ++#define ETH_TDES1_FS 0x20000000 ++#define ETH_TDES1_CIC_TUI 0x10000000 ++#define ETH_TDES1_CIC_HDR 0x08000000 ++#define ETH_TDES1_DC 0x04000000 ++#define ETH_TDES1_TER 0x02000000 ++#define ETH_TDES1_TCH 0x01000000 ++#define ETH_TDES1_DP 0x00800000 ++#define ETH_TDES1_TBS2(v) (((v) & 0x003ff800) >> 11) ++#define ETH_TDES1_TBS1(v) ((v) & 0x000007ff) ++#define ETH_TDES1_TBS2x(x) (((x) << 11) & 0x003ff800) ++#define ETH_TDES1_TBS1x(x) ((x) & 0x000007ff) ++ ++/* ==========================================================================*/ ++#define GKETH_MAC_SIZE (6) ++ ++ ++#define EPHY_BASE (GK_VA_ETH_PHY) ++#define EPHY_REG(x) (EPHY_BASE + (x)) ++ ++#define REG_EPHY_CONTROL EPHY_REG(0x000) /* read/write */ ++#define REG_EPHY_STATUS EPHY_REG(0x004) /* read */ ++#define REG_EPHY_ID1 EPHY_REG(0x008) /* read */ ++#define REG_EPHY_ID2 EPHY_REG(0x00C) /* read */ ++#define REG_EPHY_ANAR EPHY_REG(0x010) /* read/write */ ++#define REG_EPHY_ANLPAR EPHY_REG(0x014) /* read */ ++#define REG_EPHY_ANER EPHY_REG(0x018) /* read/write */ ++#define REG_EPHY_ANNPAR EPHY_REG(0x01C) /* read/write */ ++#define REG_EPHY_ANLPNP EPHY_REG(0x020) /* read */ ++#define REG_EPHY_MS_CONTROL EPHY_REG(0x024) /* read/write */ ++#define REG_EPHY_MS_STATUS EPHY_REG(0x028) /* read */ ++#define REG_EPHY_PSE_CONTROL EPHY_REG(0x02C) /* read/write */ ++#define REG_EPHY_PSE_STATUS EPHY_REG(0x030) /* read */ ++#define REG_EPHY_MMD_CONTROL EPHY_REG(0x034) /* read/write */ ++#define REG_EPHY_MMD_CONTROL_ADDR EPHY_REG(0x038) /* read/write */ ++#define REG_EPHY_AN_R_15 EPHY_REG(0x03C) /* read */ ++#define REG_EPHY_WAVE_SHAPING_34 EPHY_REG(0x040) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_56 EPHY_REG(0x044) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_78 EPHY_REG(0x048) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_9A EPHY_REG(0x04C) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_BC EPHY_REG(0x050) /* read/write */ ++#define REG_EPHY_WAVE_SHAPING_DE EPHY_REG(0x054) /* read/write */ ++#define REG_EPHY_SPEED EPHY_REG(0x058) /* read/write */ ++#define REG_EPHY_LTP EPHY_REG(0x05C) /* read/write */ ++#define REG_EPHY_MCU EPHY_REG(0x060) /* read/write */ ++#define REG_EPHY_CODE_RAM EPHY_REG(0x064) /* read/write */ ++#define REG_EPHY_CODE_RAM_W EPHY_REG(0x068) /* read/write */ ++#define REG_EPHY_100M_LINK EPHY_REG(0x088) /* read/write */ ++#define REG_EPHY_DEBUG EPHY_REG(0x0C8) /* read/write */ ++#define REG_EPHY_DEBUG_MODE EPHY_REG(0x0E0) /* read/write */ ++#define REG_EPHY_ADC_GAIN_PGA EPHY_REG(0x36C) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL3 EPHY_REG(0x370) /* read/write */ ++#define REG_EPHY_RX_LPF EPHY_REG(0x374) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL0 EPHY_REG(0x394) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL1 EPHY_REG(0x398) /* read/write */ ++#define REG_EPHY_PLL_ADC_CTRL2 EPHY_REG(0x3A8) /* read/write */ ++#define REG_EPHY_ADC_DC EPHY_REG(0x3D4) /* read/write */ ++#define REG_EPHY_LDO EPHY_REG(0x3F8) /* read/write */ ++#define REG_EPHY_CLK_GATE EPHY_REG(0x450) /* read */ ++#define REG_EPHY_CLK1 EPHY_REG(0x460) /* read/write */ ++#define REG_EPHY_POWER EPHY_REG(0x474) /* read/write */ ++#define REG_EPHY_MDIIO EPHY_REG(0x540) /* read/write */ ++#define REG_EPHY_CLK0 EPHY_REG(0x588) /* read/write */ ++ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_eth_platform_info { ++ u8 mac_addr[GKETH_MAC_SIZE]; ++ u32 napi_weight; ++ u32 watchdog_timeo; ++ ++ u32 phy_id; ++ u32 phy_supported; ++ u32 mii_id; ++ struct gk_gpio_io_info phy_reset; ++ u32 mii_retry_limit; ++ u32 mii_retry_tmo; ++ ++ u32 default_tx_ring_size; ++ u32 default_rx_ring_size; ++ u32 default_dma_bus_mode; ++ u32 default_dma_opmode; ++ u32 default_supported; ++ ++ int (*is_enabled)(void); ++}; ++ ++#define GK_ETH_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(eth##id##_napi_weight, ¶m_ops_uint, &(arg.napi_weight), perm); \ ++ module_param_cb(eth##id##_watchdog_timeo, ¶m_ops_uint, &(arg.watchdog_timeo), perm); \ ++ module_param_cb(eth##id##_phy_id, ¶m_ops_uint, &(arg.phy_id), perm); \ ++ module_param_cb(eth##id##_mii_id, ¶m_ops_uint, &(arg.mii_id), perm); \ ++ module_param_cb(eth##id##_mii_retry_limit, ¶m_ops_uint, &(arg.mii_retry_limit), perm); \ ++ module_param_cb(eth##id##_mii_retry_tmo, ¶m_ops_uint, &(arg.mii_retry_tmo), perm); ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_eth0; ++ ++/* ==========================================================================*/ ++extern int gk_init_eth0(const u8 *mac_addr); ++extern void gk_set_phy_reset_pin(u32 gpio_pin); ++extern void gk_set_phy_speed_led(u32 gpio_type); ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++ ++#endif /* __MACH_ETH_H__ */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/event.h b/arch/arm/mach-gk710xs/include/mach/event.h +new file mode 100644 +index 00000000..55670825 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/event.h +@@ -0,0 +1,121 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/plat/event.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __PLAT_EVENT_H ++#define __PLAT_EVENT_H ++ ++/* ==========================================================================*/ ++#define GK_EVENT_PRE (0x80000000) ++#define GK_EVENT_POST (0x40000000) ++#define GK_EVENT_CHECK (0x20000000) ++ ++#define GK_EVENT_ID_CPUFREQ (1) ++#define GK_EVENT_ID_PM (2) ++#define GK_EVENT_ID_TOSS (3) ++#define GK_EVENT_ID_GIVEUP_DSP (4) ++#define GK_EVENT_ID_TAKEOVER_DSP (5) ++#define GK_EVENT_ID_USBVBUS (6) ++#define GK_EVENT_ID_VI_LOSS (7) ++ ++#define GK_EVENT_PRE_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_PRE) ++#define GK_EVENT_POST_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_POST) ++#define GK_EVENT_CHECK_CPUFREQ (GK_EVENT_ID_CPUFREQ | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_PM (GK_EVENT_ID_PM | GK_EVENT_PRE) ++#define GK_EVENT_POST_PM (GK_EVENT_ID_PM | GK_EVENT_POST) ++#define GK_EVENT_CHECK_PM (GK_EVENT_ID_PM | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_PRE) ++#define GK_EVENT_POST_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_POST) ++#define GK_EVENT_CHECK_TOSS (GK_EVENT_ID_TOSS | GK_EVENT_CHECK) ++ ++#define GK_EVENT_PRE_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_PRE) ++#define GK_EVENT_POST_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_POST) ++#define GK_EVENT_GIVEUP_DSP (GK_EVENT_ID_GIVEUP_DSP | GK_EVENT_CHECK) ++#define GK_EVENT_PRE_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_PRE) ++#define GK_EVENT_POST_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_POST) ++#define GK_EVENT_TAKEOVER_DSP (GK_EVENT_ID_TAKEOVER_DSP | GK_EVENT_CHECK) ++ ++#define GK_EVENT_CHECK_USBVBUS (GK_EVENT_ID_USBVBUS | GK_EVENT_CHECK) ++ ++#define GK_EVENT_POST_VI_LOSS (GK_EVENT_ID_VI_LOSS | GK_EVENT_POST) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++#include ++ ++/* ==========================================================================*/ ++enum gk_event_type { ++ /* No Event */ ++ GK_EV_NONE = 0x00000000, ++ ++ /* VI Event */ ++ GK_EV_VI_DECODER_SOURCE_PLUG = 0x00010000, ++ GK_EV_VI_DECODER_SOURCE_REMOVE, ++ ++ /* VO Event */ ++ GK_EV_VO_CVBS_PLUG = 0x00020000, ++ GK_EV_VO_CVBS_REMOVE, ++ GK_EV_VO_YPBPR_PLUG, ++ GK_EV_VO_YPBPR_REMOVE, ++ GK_EV_VO_HDMI_PLUG, ++ GK_EV_VO_HDMI_REMOVE, ++ ++ /* SENSOR Event*/ ++ GK_EV_ACCELEROMETER_REPORT = 0x00030000, ++ GK_EV_MAGNETIC_FIELD_REPORT, ++ GK_EV_LIGHT_REPORT, ++ GK_EV_PROXIMITY_REPORT, ++ GK_EV_GYROSCOPE_REPORT, ++ GK_EV_TEMPERATURE_REPORT, ++ ++ /* FB2 Event */ ++ GK_EV_FB2_PAN_DISPLAY = 0x00040000, ++}; ++ ++struct gk_event { ++ u32 sno; //sequential number ++ u64 time_code; ++ enum gk_event_type type; ++ u8 data[32]; ++}; ++ ++struct gk_event_pool { ++ struct mutex op_mutex; ++ struct gk_event events[256]; ++ unsigned int ev_sno; ++ unsigned char ev_index; ++}; ++ ++extern int gk_event_pool_init(struct gk_event_pool *pool); ++extern int gk_event_pool_affuse(struct gk_event_pool *pool, ++ struct gk_event event); ++extern int gk_event_pool_query_index(struct gk_event_pool *pool); ++extern int gk_event_pool_query_event(struct gk_event_pool *pool, ++ struct gk_event *event, unsigned char index); ++extern int gk_event_report_uevent(struct kobject *kobj, ++ enum kobject_action action, char *envp_ext[]); ++ ++/* ==========================================================================*/ ++extern int gk_unregister_event_notifier(void *nb); ++extern int gk_set_event(unsigned long val, void *v); ++extern int gk_register_raw_event_notifier(void *nb); ++extern int gk_unregister_raw_event_notifier(void *nb); ++extern int gk_set_raw_event(unsigned long val, void *v); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/flash.h b/arch/arm/mach-gk710xs/include/mach/flash.h +new file mode 100644 +index 00000000..c0a15479 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/flash.h +@@ -0,0 +1,59 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/flash.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_FLASH_H ++#define __MACH_FLASH_H ++ ++#include ++ ++#define SFLASH_REG(x) (GK_VA_SFLASH + (x)) ++ ++#define REG_SFLASH_DATA SFLASH_REG(0x00) /* read/write */ ++#define REG_SFLASH_COMMAND SFLASH_REG(0x04) /* read/write */ ++#define REG_SFLASH_CE SFLASH_REG(0x08) /* read/write */ ++#define REG_SFLASH_SPEED SFLASH_REG(0x0C) /* read/write */ ++#define REG_SFLASH_PARA_XIP SFLASH_REG(0x10) /* read/write */ ++ ++// FPGA: SCLK = 40MHz ++// EVB: SCLK = 138MHz ++// 000: SCLK/2 ++// 001: SCLK/4 ++// 010: SCLK/6 ++// 011: SCLK/8 ++// 100: SCLK/10 ++typedef enum ++{ ++ GOKE_SFLASH_FREQ_DIV2 = 0, ++ GOKE_SFLASH_FREQ_DIV4, ++ GOKE_SFLASH_FREQ_DIV6, ++ GOKE_SFLASH_FREQ_DIV8, ++ GOKE_SFLASH_FREQ_DIV10 ++}GD_SFLASH_SPEED_MODE; ++ ++#define SYSTEM_SFLASH_FREQ GOKE_SFLASH_FREQ_DIV2 ++ ++struct sflash_platform_data /* flash device platform_data */ ++{ ++ uint32_t speed_mode; ++ uint32_t channel; ++ uint32_t nr_parts; ++ struct mtd_partition *parts; ++}; ++ ++#endif /* __MACH_FLASH_H */ ++ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/gk710xs.h b/arch/arm/mach-gk710xs/include/mach/gk710xs.h +new file mode 100644 +index 00000000..6ecbdd0d +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/gk710xs.h +@@ -0,0 +1,183 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/gk.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK710X_H ++#define __MACH_GK710X_H ++ ++ ++#include ++#include ++ ++#define CHIP_ID(x) ((x / 1000)) ++#define CHIP_MAJOR(x) ((x / 100) % 10) ++#define CHIP_MINOR(x) ((x / 10) % 10) ++ ++/* ==========================================================================*/ ++#define GK_DEBUG_NULL (0) ++#define GK_DEBUG_MEDIA (1 << 0) ++#define GK_DEBUG_VI (1 << 1) ++#define GK_DEBUG_VO (1 << 2) ++#define GK_DEBUG_AAA (1 << 3) ++#define GK_DEBUG_DSP (1 << 4) ++ ++/* definition SOC types */ ++#define CONFIG_SOC_GK7101 0 ++#define CONFIG_SOC_GK7102 1 ++ ++#define CONFIG_U2K_PHY_TYPE 0xC0000000 ++#define CONFIG_U2K_ARM_FREQ 0xC0000004 ++#define CONFIG_U2K_HAL_ADDR 0xC0000008 ++ ++#define CONFIG_U2K_SOC_ADDR 0xC0000010 //0:, 1:7102 ++#define CONFIG_U2K_MEM_ADDR 0xC0000014 ++#define CONFIG_U2K_BSB_ADDR 0xC0000018 ++#define CONFIG_U2K_DSP_ADDR 0xC000001C ++ ++#define CONFIG_U2K_ENABLE 0xC0000020 ++#define CONFIG_U2K_USR_ADDR 0xC0000024 //for user's cmem module ++ ++#define CONFIG_U2K_TOTAL_MEM 0xC0000028 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++/* ==========================================================================*/ ++extern u32 gk_debug_level; ++extern u32 gk_debug_info; ++ ++#define HW_HAL_MODE 0 ++#define USB_DMA_ADD_MODE 0 ++#define FLASH_HAL_MODE 0 ++ ++#define ADC_HAL_MODE 0 ++#define AUD_HAL_MODE 0 ++#define CRY_HAL_MODE 0 ++#define DDR_HAL_MODE 0 ++#define DMA_HAL_MODE 0 ++#define DSP_HAL_MODE 0 ++#define ETH_HAL_MODE 0 ++#define GREG_HAL_MODE 0 ++#define GPIO_HAL_MODE 0 ++#define I2C_HAL_MODE 0 ++#define I2S_HAL_MODE 0 ++#define IR_HAL_MODE 0 ++#define IRQ_HAL_MODE 0 ++#define MCU_HAL_MODE 0 ++#define PWM_HAL_MODE 0 ++#define RCT_HAL_MODE 0 ++#define SD_HAL_MODE 0 ++#define SF_HAL_MODE 0 ++#define SSI_HAL_MODE 1 ++#define TIMER_HAL_MODE 0 ++#define UART_HAL_MODE 1 ++#define USB_HAL_MODE 0 ++#define VOUT_HAL_MODE 0 ++#define WDT_HAL_MODE 0 ++#define EFUSE_HAL_MODE 0 ++struct hw_ops ++{ ++ int (*get_version)(void); ++ unsigned int (*reserved)(unsigned int ); ++ ++ unsigned char (*hw_readb)(unsigned int ); ++ unsigned short (*hw_readw)(unsigned int ); ++ unsigned int (*hw_readl)(unsigned int ); ++ ++ void (*hw_writeb)(unsigned char , unsigned int ); ++ void (*hw_writew)(unsigned short , unsigned int ); ++ void (*hw_writel)(unsigned int , unsigned int ); ++ ++ unsigned int (*flash_read)(void); ++ void (*flash_write)(unsigned int); ++}; ++ ++extern struct hw_ops *g_hw; ++ ++extern unsigned long gk_debug_lookup_name(const char *name); ++void sensor_init(u8 active_level); ++void sensor_power(u8 power); ++u32 get_audio_clk_freq(void); ++ ++ ++#endif /* __ASSEMBLER__ */ ++ ++extern u32 get_ppm_phys(void); ++extern u32 get_ppm_virt(void); ++extern u32 get_ppm_size(void); ++ ++extern u32 get_bsbmem_phys(void); ++extern u32 get_bsbmem_virt(void); ++extern u32 get_bsbmem_size(void); ++ ++extern u32 get_dspmem_phys(void); ++extern u32 get_dspmem_virt(void); ++extern u32 get_dspmem_size(void); ++ ++extern u32 gk_phys_to_virt(u32 paddr); ++extern u32 gk_virt_to_phys(u32 vaddr); ++ ++extern u32 get_hal1_virt(void); ++extern u32 get_hal2_virt(void); ++ ++extern u32 get_ahb_phys(void); ++extern u32 get_ahb_virt(void); ++extern u32 get_ahb_size(void); ++ ++extern u32 get_apb_phys(void); ++extern u32 get_apb_virt(void); ++extern u32 get_apb_size(void); ++ ++extern u32 get_osd_phys(void); ++extern u32 get_osd_virt(void); ++extern u32 get_osd_size(void); ++ ++extern u32 get_pri_phys(void); ++extern u32 get_pri_virt(void); ++extern u32 get_pri_size(void); ++ ++extern u32 get_qpm_phys(void); ++extern u32 get_qpm_virt(void); ++extern u32 get_qpm_size(void); ++ ++extern u32 get_bsbmem_virt(void); ++extern u32 get_bsbmem_size(void); ++ ++extern u32 get_usrmem_phys(void); ++extern u32 get_usrmem_virt(void); ++extern u32 get_usrmem_size(void); ++ ++extern void get_stepping_info(int *chip, int *major, int *minor); ++extern int gk_register_event_notifier(void *nb); ++ ++extern u32 gk_boot_splash_logo; ++ ++extern u64 gk_dmamask; ++ ++extern int gk_create_proc_dir(void); ++extern struct proc_dir_entry *get_gk_proc_dir(void); ++ ++extern void get_stepping_info(int *chip, int *major, int *minor); ++ ++extern void gk_restart(char mode, const char *cmd); ++extern void gk_power_off(void); ++ ++extern void gk_map_io(void) __init; ++ ++extern void gk_load_51mcu_code(u32 code); ++ ++#endif /* __MACH_GK_H */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/gpio.h b/arch/arm/mach-gk710xs/include/mach/gpio.h +new file mode 100644 +index 00000000..4129060a +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/gpio.h +@@ -0,0 +1,116 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/gpio.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GPIO_H_ ++#define __MACH_GPIO_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++#define GPIO0_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK0_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK1_BASE (GK_VA_GPIO0) ++#define GPIO0_BANK0_PLL_IOCTRL_BASE (GK_VA_RCT + 0x0230) /* read/write */ ++#define GPIO0_BANK1_PLL_IOCTRL_BASE (GK_VA_RCT + 0x0230 - 0x100) /* read/write */ ++ ++// for bank ++#define REG_GPIO_IS_LOW_OFFSET (0x0000) /* read/write */ ++#define REG_GPIO_IS_HIGH_OFFSET (0x0004) /* read/write */ ++#define REG_GPIO_IBE_LOW_OFFSET (0x0008) /* read/write */ ++#define REG_GPIO_IBE_HIGH_OFFSET (0x000C) /* read/write */ ++#define REG_GPIO_IEV_LOW_OFFSET (0x0010) /* read/write */ ++#define REG_GPIO_IEV_HIGH_OFFSET (0x0014) /* read/write */ ++#define REG_GPIO_IE_LOW_OFFSET (0x0018) /* read/write */ ++#define REG_GPIO_IE_HIGH_OFFSET (0x001C) /* read/write */ ++#define REG_GPIO_IC_LOW_OFFSET (0x0020) /* write */ ++#define REG_GPIO_IC_HIGH_OFFSET (0x0024) /* write */ ++#define REG_GPIO_RIS_LOW_OFFSET (0x0028) /* read */ ++#define REG_GPIO_RIS_HIGH_OFFSET (0x002C) /* read */ ++#define REG_GPIO_MIS_LOW_OFFSET (0x0030) /* read */ ++#define REG_GPIO_MIS_HIGH_OFFSET (0x0034) /* read */ ++#define REG_GPIO_DIN_LOW_OFFSET (0x0040) /* read */ ++#define REG_GPIO_DIN_HIGH_OFFSET (0x0044) /* read */ ++#define REG_GPIO_OUTPUT_CFG_OFFSET (0x0100) /* write */ ++#define REG_GPIO_INPUT_CFG_OFFSET (0x0200) /* write */ ++ ++// for all bank ++#define REG_GPIO_INT_EN_OFFSET (0x0038) /* write */ ++#define REG_GPIO_PER_SEL_OFFSET (0x003C) /* read/write */ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++ ++/////add: ++//#if defined(CONFIG_MACH_GK7102S_ELEC_SC1135_V1_00) ++//#include "gpio_elec_sc1135_v1.h" ++//#endif ++/*! ++******************************************************************************* ++** ++** \brief All available GPIO pins named by number. ++** ++** \sa GPIO_Open() ++** \sa GPIO_OpenFunctionMode() ++** \sa GPIO_SetType() ++** ++******************************************************************************* ++*/ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern int __init gk_init_gpio(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif /* __MACH_GPIO_H_ */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/gpio_elec_sc1135_v1.h b/arch/arm/mach-gk710xs/include/mach/gpio_elec_sc1135_v1.h +new file mode 100644 +index 00000000..9c8d2ef0 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/gpio_elec_sc1135_v1.h +@@ -0,0 +1,118 @@ ++#ifndef _GPIO_ELEC_SC1135_V1_H_ ++#define _GPIO_ELEC_SC1135_V1_H_ ++ ++#ifdef CONFIG_PHY_USE_AO_MCLK ++ #define SYSTEM_GPIO_PHY_CLK GPIO_TYPE_OUTPUT_AOMCLK ++#endif ++#ifdef CONFIG_PHY_USE_SD_CLK ++ #define SYSTEM_GPIO_PHY_CLK GPIO_TYPE_OUTPUT_SDIO_CLK ++#endif ++#ifdef CONFIG_PHY_USE_EXTERN_CLK ++ #define SYSTEM_GPIO_PHY_CLK GPIO_TYPE_INPUT ++#endif ++ ++ ++#if defined(CONFIG_MACH_GK7101S_ELEC_SC1135_V1_00) || defined(CONFIG_MACH_GK7102S_ELEC_SC1135_V1_00) ++#define SYSTEM_GPIO_EXTPHY_TABLE \ ++ { GPIO_3 , GPIO_TYPE_INPUT_ENET_PHY_RXDV }, \ ++ { GPIO_30, GPIO_TYPE_OUTPUT_ENET_PHY_TXEN }, \ ++ { GPIO_31, GPIO_TYPE_OUTPUT_ENET_PHY_TXD_1 }, \ ++ { GPIO_32, GPIO_TYPE_OUTPUT_ENET_PHY_TXD_0 }, \ ++ { GPIO_33, GPIO_TYPE_INPUT_ENET_PHY_RXER }, \ ++ { GPIO_35, GPIO_TYPE_OUTPUT_ENET_GMII_MDC_O }, \ ++ { GPIO_36, GPIO_TYPE_INOUT_ETH_MDIO }, \ ++ { GPIO_48, GPIO_TYPE_INPUT }, \ ++ { GPIO_49, GPIO_TYPE_OUTPUT_1 /*ETH reset*/}, \ ++ { GPIO_50, SYSTEM_GPIO_PHY_CLK }, \ ++ { GPIO_51, GPIO_TYPE_INPUT_ENET_PHY_RXD_1 }, \ ++ { GPIO_52, GPIO_TYPE_INPUT_ENET_PHY_RXD_2 /*CLK*/}, \ ++ { GPIO_53, GPIO_TYPE_INPUT_ENET_PHY_RXD_0 }, \ ++ { GPIO_54, GPIO_TYPE_INPUT }, ++ ++#define SYSTEM_GPIO_INTPHY_TABLE \ ++ { GPIO_3 , GPIO_TYPE_INPUT }, \ ++ { GPIO_30, GPIO_TYPE_INPUT }, \ ++ { GPIO_31, GPIO_TYPE_INPUT }, \ ++ { GPIO_32, GPIO_TYPE_INPUT }, \ ++ { GPIO_33, GPIO_TYPE_INPUT }, \ ++ { GPIO_35, GPIO_TYPE_INPUT }, \ ++ { GPIO_36, GPIO_TYPE_INPUT }, \ ++ { GPIO_48, SYSTEM_GPIO_PHY_CLK }, \ ++ { GPIO_49, GPIO_TYPE_INPUT }, \ ++ { GPIO_50, GPIO_TYPE_INPUT }, \ ++ { GPIO_51, GPIO_TYPE_INPUT }, \ ++ { GPIO_52, GPIO_TYPE_INPUT }, \ ++ { GPIO_53, GPIO_TYPE_INPUT }, \ ++ { GPIO_54, GPIO_TYPE_OUTPUT_EPHY_LED_3 }, ++ ++#define SYSTEM_GPIO_XREF_TABLE \ ++ { GPIO_0 , GPIO_TYPE_OUTPUT_SF_CS0 }, \ ++ { GPIO_1 , GPIO_TYPE_OUTPUT_SF_CS1 }, \ ++ { GPIO_2 , GPIO_TYPE_INPUT }, \ ++ { GPIO_4 , GPIO_TYPE_INPUT }, \ ++ { GPIO_5 , GPIO_TYPE_INPUT }, \ ++ { GPIO_6 , GPIO_TYPE_INPUT }, \ ++ { GPIO_7 , GPIO_TYPE_INPUT }, \ ++ { GPIO_8 , GPIO_TYPE_INPUT }, \ ++ { GPIO_9 , GPIO_TYPE_INPUT }, \ ++ { GPIO_10, GPIO_TYPE_INPUT }, \ ++ { GPIO_11, GPIO_TYPE_INPUT }, \ ++ { GPIO_12, GPIO_TYPE_OUTPUT_0 /*IR_LED_CTRL*/}, \ ++ { GPIO_13, GPIO_TYPE_INPUT }, \ ++ { GPIO_14, GPIO_TYPE_INPUT }, \ ++ { GPIO_15, GPIO_TYPE_INPUT /*IR_DET_ADC*/}, \ ++ { GPIO_16, GPIO_TYPE_INPUT }, \ ++ { GPIO_17, GPIO_TYPE_INPUT }, \ ++ { GPIO_18, GPIO_TYPE_INPUT }, \ ++ { GPIO_19, GPIO_TYPE_INPUT }, \ ++ { GPIO_20, GPIO_TYPE_OUTPUT_0 /*IR_CUT+*/}, \ ++ { GPIO_21, GPIO_TYPE_INPUT }, \ ++ { GPIO_22, GPIO_TYPE_INPUT }, \ ++ { GPIO_23, GPIO_TYPE_OUTPUT_0 /*IR_CUT-*/}, \ ++ { GPIO_24, GPIO_TYPE_INPUT }, \ ++ { GPIO_25, GPIO_TYPE_INPUT_UART0_RX }, \ ++ { GPIO_26, GPIO_TYPE_OUTPUT_UART0_TX }, \ ++ { GPIO_27, GPIO_TYPE_OUTPUT_1 /*Sensor reset*/}, \ ++ { GPIO_28, GPIO_TYPE_INOUT_I2C_DATA /*S D*/}, \ ++ { GPIO_29, GPIO_TYPE_INOUT_I2C_CLK /*S C*/}, \ ++ { GPIO_34, GPIO_TYPE_INPUT }, \ ++ { GPIO_37, GPIO_TYPE_INPUT }, \ ++ { GPIO_38, GPIO_TYPE_INPUT }, \ ++ { GPIO_39, GPIO_TYPE_INPUT_SD_CD_N }, \ ++ { GPIO_40, GPIO_TYPE_INPUT }, \ ++ { GPIO_41, GPIO_TYPE_INOUT_SD_DATA_3 }, \ ++ { GPIO_42, GPIO_TYPE_INOUT_SD_DATA_2 }, \ ++ { GPIO_43, GPIO_TYPE_INOUT_SD_CMD }, \ ++ { GPIO_44, GPIO_TYPE_OUTPUT_SDIO_CLK }, \ ++ { GPIO_45, GPIO_TYPE_INOUT_SD_DATA_1 }, \ ++ { GPIO_46, GPIO_TYPE_OUTPUT_1/*SDIO_CARD_POWER_EN*/}, \ ++ { GPIO_47, GPIO_TYPE_INOUT_SD_DATA_0 }, \ ++ { GPIO_55, GPIO_TYPE_INPUT }, \ ++ { GPIO_56, GPIO_TYPE_INPUT }, \ ++ { GPIO_57, GPIO_TYPE_INPUT }, \ ++ { GPIO_58, GPIO_TYPE_INPUT }, \ ++ { GPIO_59, GPIO_TYPE_INPUT }, \ ++ { GPIO_60, GPIO_TYPE_INPUT }, \ ++ { GPIO_61, GPIO_TYPE_INPUT }, \ ++ { GPIO_62, GPIO_TYPE_INPUT } ++ ++#define SYSTEM_GPIO_IR_LED_CTRL GPIO_4 // not real pin ++#define SYSTEM_GPIO_IR_CUT1 GPIO_20 ++#define SYSTEM_GPIO_IR_CUT2 GPIO_23 ++#define SYSTEM_GPIO_SENSOR_RESET GPIO_27 ++#define SYSTEM_GPIO_PHY_RESET GPIO_49 ++#define SYSTEM_GPIO_PHY_SPEED_LED GPIO_54 ++ ++#define SYSTEM_GPIO_SPI0_EN0 GPIO_5 // not real pin ++#define SYSTEM_GPIO_SPI1_EN0 GPIO_6 // not real pin ++#define SYSTEM_GPIO_PWM0 GPIO_7 // not real pin ++#define SYSTEM_GPIO_PWM1 GPIO_8 // not real pin ++#define SYSTEM_GPIO_PWM2 GPIO_9 // not real pin ++#define SYSTEM_GPIO_PWM3 GPIO_10 // not real pin ++#define SYSTEM_GPIO_USB_HOST GPIO_11 // not real pin ++#define SYSTEM_GPIO_SD_DETECT GPIO_39 ++#define SYSTEM_GPIO_SD_POWER GPIO_46 ++#endif /* CONFIG_MACH_GK7102S_ELEC_SC1135_V1_00 */ ++ ++#endif /* _GPIO_RB_SC1035_H_ */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/gtypes.h b/arch/arm/mach-gk710xs/include/mach/gtypes.h +new file mode 100644 +index 00000000..26932665 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/gtypes.h +@@ -0,0 +1,132 @@ ++#ifndef _GTYPES_H_ ++#define _GTYPES_H_ ++ ++#ifdef __LINUX__ ++#include /* kmalloc */ ++#include /* printk */ ++#include /* wait queue */ ++#include /* copy user<->kernel */ ++#include /* paddr<->vaddr */ ++#include /* semaphore */ ++#include /* poll */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* necessary undefines */ ++#ifdef GFALSE ++ #undef GFALSE ++#endif ++#ifdef GTRUE ++ #undef GTRUE ++#endif ++ ++ ++/*! ++******************************************************************************* ++** ++** \name GOKESDK Error Codes ++** ++******************************************************************************* ++*/ ++/*@{*/ ++enum ++{ ++ GD_OK = 0, //!< No error. ++ GD_ERR_BAD_PARAMETER, //!< Bad parameter passed. ++ GD_ERR_OUT_OF_MEMORY, //!< Memory allocation failed. ++ GD_ERR_ALREADY_INITIALIZED, //!< Device already initialised. ++ GD_ERR_NOT_INITIALIZED, //!< Device not initialised. ++ GD_ERR_ALREADY_OPEN, //!< Device could not be opened again. ++ GD_ERR_FEATURE_NOT_SUPPORTED, //!< Feature or function is not available. ++ GD_ERR_TIMEOUT, //!< Timeout occured. ++ GD_ERR_DEVICE_BUSY, //!< The device is busy. ++ GD_ERR_INVALID_HANDLE, //!< The handle is invalid. ++}; ++/*@}*/ ++ ++ ++/*! ++******************************************************************************* ++** ++** \name GOKESDK Data Types ++** ++******************************************************************************* ++*/ ++/*@{*/ ++typedef unsigned char U8; //!< 8 bit unsigned integer. ++typedef unsigned short U16; //!< 16 bit unsigned integer. ++#ifdef __LINUX__ ++typedef unsigned int U32; //!< 32 bit unsigned integer. ++typedef signed int S32; //!< 32 bit signed integer. ++#else ++typedef unsigned long U32; //!< 32 bit unsigned integer. ++typedef signed long S32; //!< 32 bit signed integer. ++#endif ++typedef signed char S8; //!< 8 bit signed integer. ++typedef signed short S16; //!< 16 bit signed integer. ++typedef unsigned long long U64; //!< 64 bit unsigned integer. ++ ++#ifdef __LINUX__ ++typedef int GERR; ++#else ++typedef unsigned long GERR; //!< GOKESDK error/return code. ++#endif ++typedef unsigned long GD_HANDLE; //!< GOKESDK handle. ++ ++/*! \brief Defines a GOKESDK boolean. */ ++#ifndef GTYPES_NO_BOOL ++typedef enum ++{ ++ GFALSE = 0, //!< Logical false. ++ GTRUE = 1 //!< Logical true. ++} GBOOL; ++#endif ++/*@}*/ ++ ++ ++ ++ ++/*! ++******************************************************************************* ++** ++** \brief Defines a GOKESDK null. ++** ++******************************************************************************* ++*/ ++#ifndef NULL ++ #define NULL 0 ++#endif ++ ++ ++/* ++******************************************************************************* ++** ++** Defines the keyword for inlining a function. ++** ++******************************************************************************* ++*/ ++ ++#define GH_INLINE_LEVEL 2 ++ ++#if defined(__HIGHC__) ++#define GH_INLINE _Inline ++#endif ++#if defined(__GNUC__) ++#define GH_INLINE static __inline__ ++#endif ++ ++#ifdef GISR_IS_VOID ++ #define GISR1 void /* customize C-Interrupt handler */ ++ #define GISR2 void ++#else ++ #define GISR1 irqreturn_t ++ #define GISR2 irqreturn_t ++#endif ++ ++#endif +\ No newline at end of file +diff --git a/arch/arm/mach-gk710xs/include/mach/hardware.h b/arch/arm/mach-gk710xs/include/mach/hardware.h +new file mode 100644 +index 00000000..56dabda4 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/hardware.h +@@ -0,0 +1,223 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/hardware.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/*-------------------------------------------------------------*/ ++ ++#define CONFIG_GK_PPM_SIZE 0x200000 ++ ++#define DEFAULT_MEM_START (0xc0000000) ++ ++ ++#define AHB_SIZE (0x01000000) ++#define APB_SIZE (0x01000000) ++ ++#define NOLINUX_MEM_V_START (0xe0000000) ++#define NOLINUX_MEM_V_SIZE (0x00100000) ++ ++ ++//-------------------dummy-----ahb----------- ++#define GK_PA_AHB_BASE (0x90000000) ++#define GK_VA_AHB_BASE (0xf2000000) ++ ++#define GK_ADDR_SDC_OFFSET 0x00000 //0x02000 //for dummy ++#define GK_ADDR_SDC1_OFFSET 0x10000 //0x02000 //for dummy ++#define GK_ADDR_EFUSE_OFFSET 0x01000 ++#define GK_ADDR_DDRC_OFFSET 0x02000 ++#define GK_ADDR_DMAC_OFFSET 0x03000 ++#define GK_ADDR_VO_OFFSET 0x04000 ++#define GK_ADDR_CRYPT_OFFSET 0x05000 ++#define GK_ADDR_USB_OFFSET 0x06000 ++#define GK_ADDR_VIC1_OFFSET 0x08000 ++#define GK_ADDR_VIC2_OFFSET 0x09000 ++#define GK_ADDR_ETH_GMAC_OFFSET 0x0E000 ++#define GK_ADDR_ETH_DMA_OFFSET 0x0F000 ++#define GK_ADDR_I2S_OFFSET 0x0A000 ++#define GK_ADDR_SFLASH_OFFSET 0x16000 ++ ++#define GK_ADDR_ADC_OFFSET 0x20A00 ++#define GK_ADDR_AHB_GREG_OFFSET 0x20E00 ++#define GK_ADDR_USB_PHY_OFFSET 0x21000 ++#define GK_ADDR_ENET_PHY_OFFSET 0x22000 ++#define GK_ADDR_VEDIO_DAC_OFFSET 0x22600 ++ ++ ++#define GK_ADDR_PMU_OFFSET 0x80000 ++#define GK_ADDR_PMU_RTC_OFFSET 0x80000 ++#define GK_ADDR_PMU_C51_CODE_OFFSET 0xC0000 ++ ++ ++#define GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET 0x21C00 ++#define GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET 0x20C00 ++ ++ ++#define GK_PA_SDC (GK_PA_AHB_BASE + GK_ADDR_SDC_OFFSET) ++#define GK_PA_SDC1 (GK_PA_AHB_BASE + GK_ADDR_SDC1_OFFSET) ++#define GK_PA_I2S (GK_PA_AHB_BASE + GK_ADDR_I2S_OFFSET) ++#define GK_PA_AHB_GREG (GK_PA_AHB_BASE + GK_ADDR_AHB_GREG_OFFSET) ++#define GK_PA_EFUSE (GK_PA_AHB_BASE + GK_ADDR_EFUSE_OFFSET) ++#define GK_PA_SFLASH (GK_PA_AHB_BASE + GK_ADDR_SFLASH_OFFSET) ++#define GK_PA_ADC (GK_PA_AHB_BASE + GK_ADDR_ADC_OFFSET) ++#define GK_PA_VO (GK_PA_AHB_BASE + GK_ADDR_VO_OFFSET) ++#define GK_PA_AUDIO_CODEC_DIGITAL (GK_PA_AHB_BASE + GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET) ++#define GK_PA_AUDIO_CODEC_ANALOG (GK_PA_AHB_BASE + GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET) ++#define GK_PA_DDRC (GK_PA_AHB_BASE + GK_ADDR_DDRC_OFFSET) ++#define GK_PA_VIC1 (GK_PA_AHB_BASE + GK_ADDR_VIC1_OFFSET) ++#define GK_PA_VIC2 (GK_PA_AHB_BASE + GK_ADDR_VIC2_OFFSET) ++#define GK_PA_ETH_GMAC (GK_PA_AHB_BASE + GK_ADDR_ETH_GMAC_OFFSET) ++#define GK_PA_ETH_DMA (GK_PA_AHB_BASE + GK_ADDR_ETH_DMA_OFFSET) ++#define GK_PA_USB_PHY (GK_PA_AHB_BASE + GK_ADDR_USB_PHY_OFFSET) ++#define GK_PA_ETH_PHY (GK_PA_AHB_BASE + GK_ADDR_ENET_PHY_OFFSET) ++#define GK_PA_PMU (GK_PA_AHB_BASE + GK_ADDR_PMU_OFFSET) ++#define GK_PA_PMU_RTC (GK_PA_AHB_BASE + GK_ADDR_PMU_RTC_OFFSET) ++#define GK_PA_PMU_C51_CODE (GK_PA_AHB_BASE + GK_ADDR_PMU_C51_CODE_OFFSET) ++#define GK_PA_VEDIO_DAC (GK_PA_AHB_BASE + GK_ADDR_VEDIO_DAC_OFFSET) ++#define GK_PA_CRYPT_UNIT (GK_PA_AHB_BASE + GK_ADDR_CRYPT_OFFSET) ++ ++#define GK_VA_SDC (GK_VA_AHB_BASE + GK_ADDR_SDC_OFFSET) ++#define GK_VA_SDC1 (GK_VA_AHB_BASE + GK_ADDR_SDC1_OFFSET) ++#define GK_VA_I2S (GK_VA_AHB_BASE + GK_ADDR_I2S_OFFSET) ++#define GK_VA_AHB_GREG (GK_VA_AHB_BASE + GK_ADDR_AHB_GREG_OFFSET) ++#define GK_VA_EFUSE (GK_VA_AHB_BASE + GK_ADDR_EFUSE_OFFSET) ++#define GK_VA_ADC (GK_VA_AHB_BASE + GK_ADDR_ADC_OFFSET) ++#define GK_VA_DDRC (GK_VA_AHB_BASE + GK_ADDR_DDRC_OFFSET) ++#define GK_VA_VIC1 (GK_VA_AHB_BASE + GK_ADDR_VIC1_OFFSET) ++#define GK_VA_VIC2 (GK_VA_AHB_BASE + GK_ADDR_VIC2_OFFSET) ++#define GK_VA_ETH_GMAC (GK_VA_AHB_BASE + GK_ADDR_ETH_GMAC_OFFSET) ++#define GK_VA_ETH_DMA (GK_VA_AHB_BASE + GK_ADDR_ETH_DMA_OFFSET) ++#define GK_VA_USB_PHY (GK_VA_AHB_BASE + GK_ADDR_USB_PHY_OFFSET) ++#define GK_VA_ETH_PHY (GK_VA_AHB_BASE + GK_ADDR_ENET_PHY_OFFSET) ++#define GK_VA_PMU (GK_VA_AHB_BASE + GK_ADDR_PMU_OFFSET) ++#define GK_VA_PMU_RTC (GK_VA_AHB_BASE + GK_ADDR_PMU_RTC_OFFSET) ++#define GK_VA_SFLASH (GK_VA_AHB_BASE + GK_ADDR_SFLASH_OFFSET) ++#define GK_VA_VO (GK_VA_AHB_BASE + GK_ADDR_VO_OFFSET) ++#define GK_VA_AUDIO_CODEC_DIGITAL (GK_VA_AHB_BASE + GK_ADDR_AUDIO_CODEC_DIGITAL_OFFSET) ++#define GK_VA_AUDIO_CODEC_ANALOG (GK_VA_AHB_BASE + GK_ADDR_AUDIO_CODEC_ANALOG_OFFSET) ++#define GK_VA_PMU_C51_CODE (GK_VA_AHB_BASE + GK_ADDR_PMU_C51_CODE_OFFSET) ++#define GK_VA_VEDIO_DAC (GK_VA_AHB_BASE + GK_ADDR_VEDIO_DAC_OFFSET) /*cvbs*/ ++#define GK_VA_CRYPT_UNIT (GK_VA_AHB_BASE + GK_ADDR_CRYPT_OFFSET) ++ ++#define GK_PA_DMAC (GK_PA_AHB_BASE + GK_ADDR_DMAC_OFFSET) ++#define GK_PA_USB (GK_PA_AHB_BASE + GK_ADDR_USB_OFFSET) ++#define GK_VA_DMAC (GK_VA_AHB_BASE + GK_ADDR_DMAC_OFFSET) ++#define GK_VA_USB (GK_VA_AHB_BASE + GK_ADDR_USB_OFFSET) ++ ++ ++//-------------------dummy-----apb----------- ++#define GK_PA_APB_BASE (0xA0000000) ++#define GK_VA_APB_BASE (0xf3000000) ++ ++#define GK_ADDR_TIMER_OFFSET 0x00000 ++#define GK_ADDR_IDC_OFFSET 0x03000 ++#define GK_ADDR_IDC2_OFFSET 0x04000 ++#define GK_ADDR_UART0_OFFSET 0x05000 ++#define GK_ADDR_WDT_OFFSET 0x06000 ++#define GK_ADDR_GPIO0_OFFSET 0x09000 ++#define GK_ADDR_ADC2_OFFSET 0x07000 ++ ++#define GK_ADDR_PWM0_OFFSET 0x0a000 ++#define GK_ADDR_PWM1_OFFSET 0x0b000 ++#define GK_ADDR_PWM2_OFFSET 0x0c000 ++#define GK_ADDR_PWM3_OFFSET 0x0d000 ++ ++#define GK_ADDR_UART2_OFFSET 0x1E000 ++#define GK_ADDR_UART1_OFFSET 0x1F000 ++ ++#define GK_ADDR_SSI1_OFFSET 0x08000 ++#define GK_ADDR_SSI2_OFFSET 0x02000 ++#define GK_ADDR_TSSI_OFFSET 0x01000 ++ ++#define GK_ADDR_MEM_OFFSET 0x150000 ++#define GK_ADDR_RCT_OFFSET 0x170000 ++ ++ ++ ++#define GK_PA_TIMER (GK_PA_APB_BASE + GK_ADDR_TIMER_OFFSET) ++#define GK_PA_IDC (GK_PA_APB_BASE + GK_ADDR_IDC_OFFSET) ++#define GK_PA_IDC2 (GK_PA_APB_BASE + GK_ADDR_IDC2_OFFSET) ++#define GK_PA_UART0 (GK_PA_APB_BASE + GK_ADDR_UART0_OFFSET) ++#define GK_PA_WDT (GK_PA_APB_BASE + GK_ADDR_WDT_OFFSET) ++#define GK_PA_GPIO0 (GK_PA_APB_BASE + GK_ADDR_GPIO0_OFFSET) ++#define GK_PA_PWM0 (GK_PA_APB_BASE + GK_ADDR_PWM0_OFFSET) ++#define GK_PA_PWM1 (GK_PA_APB_BASE + GK_ADDR_PWM1_OFFSET) ++#define GK_PA_PWM2 (GK_PA_APB_BASE + GK_ADDR_PWM2_OFFSET) ++#define GK_PA_PWM3 (GK_PA_APB_BASE + GK_ADDR_PWM3_OFFSET) ++#define GK_PA_UART2 (GK_PA_APB_BASE + GK_ADDR_UART2_OFFSET) ++#define GK_PA_UART1 (GK_PA_APB_BASE + GK_ADDR_UART1_OFFSET) ++#define GK_PA_ADC2 (GK_PA_APB_BASE + GK_ADDR_ADC2_OFFSET) ++ ++#define GK_PA_SSI1 (GK_PA_APB_BASE + GK_ADDR_SSI1_OFFSET) ++#define GK_PA_SSI2 (GK_PA_APB_BASE + GK_ADDR_SSI2_OFFSET) ++#define GK_PA_TSSI (GK_PA_APB_BASE + GK_ADDR_TSSI_OFFSET) ++#define GK_PA_RCT (GK_PA_APB_BASE + GK_ADDR_RCT_OFFSET) ++#define GK_PA_MEM (GK_PA_APB_BASE + GK_ADDR_MEM_OFFSET) ++ ++ ++ ++#define GK_VA_TIMER (GK_VA_APB_BASE + GK_ADDR_TIMER_OFFSET) ++#define GK_VA_IDC (GK_VA_APB_BASE + GK_ADDR_IDC_OFFSET) ++#define GK_VA_IDC2 (GK_VA_APB_BASE + GK_ADDR_IDC2_OFFSET) ++#define GK_VA_UART0 (GK_VA_APB_BASE + GK_ADDR_UART0_OFFSET) ++#define GK_VA_WDT (GK_VA_APB_BASE + GK_ADDR_WDT_OFFSET) ++#define GK_VA_GPIO0 (GK_VA_APB_BASE + GK_ADDR_GPIO0_OFFSET) ++#define GK_VA_PWM0 (GK_VA_APB_BASE + GK_ADDR_PWM0_OFFSET) ++#define GK_VA_PWM1 (GK_VA_APB_BASE + GK_ADDR_PWM1_OFFSET) ++#define GK_VA_PWM2 (GK_VA_APB_BASE + GK_ADDR_PWM2_OFFSET) ++#define GK_VA_PWM3 (GK_VA_APB_BASE + GK_ADDR_PWM3_OFFSET) ++#define GK_VA_ADC2 (GK_VA_APB_BASE + GK_ADDR_ADC2_OFFSET) ++ ++#define GK_VA_UART2 (GK_VA_APB_BASE + GK_ADDR_UART2_OFFSET) ++#define GK_VA_UART1 (GK_VA_APB_BASE + GK_ADDR_UART1_OFFSET) ++ ++#define GK_VA_SSI1 (GK_VA_APB_BASE + GK_ADDR_SSI1_OFFSET) ++#define GK_VA_SSI2 (GK_VA_APB_BASE + GK_ADDR_SSI2_OFFSET) ++#define GK_VA_TSSI (GK_VA_APB_BASE + GK_ADDR_TSSI_OFFSET) ++#define GK_VA_RCT (GK_VA_APB_BASE + GK_ADDR_RCT_OFFSET) ++#define GK_VA_MEM (GK_VA_APB_BASE + GK_ADDR_MEM_OFFSET) ++ ++ ++#define GRAPHICS_DMA_OFFSET 0x15000 ++#define GRAPHICS_DMA_BASE (GK_VA_AHB_BASE + GRAPHICS_DMA_OFFSET) ++#define GRAPHICS_DMA_REG(x) (GRAPHICS_DMA_BASE + (x)) ++ ++ ++ ++#define VO_CLK_ONCHIP_PLL_27MHZ 0x0 /* Default setting */ ++#define VO_CLK_ONCHIP_PLL_SP_CLK 0x1 ++#define VO_CLK_ONCHIP_PLL_CLK_SI 0x2 ++#define VO_CLK_EXTERNAL 0x3 ++#define VO_CLK_ONCHIP_PLL_DSP_SCLK 0x4 ++ ++#define TIMER_OFFSET 0xb000 ++ ++ ++#define CONSISTENT_DMA_SIZE SZ_8M ++ ++/* ==========================================================================*/ ++ ++//end ++ ++#endif /* __ASM_ARCH_HARDWARE_H */ ++ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/i2s.h b/arch/arm/mach-gk710xs/include/mach/i2s.h +new file mode 100644 +index 00000000..b3a531a1 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/i2s.h +@@ -0,0 +1,158 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/hal/i2s.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __HAL_I2S_H__ ++#define __HAL_I2S_H__ ++ ++#include ++ ++#define I2S_BASE (GK_VA_I2S) ++#define I2S_BASE_PHYS (GK_PA_I2S) ++#define I2S_REG(x) (I2S_BASE + (x)) ++#define I2S_REG_PHYS(x) (I2S_BASE_PHYS + (x)) ++ ++#define I2S_BASE_extern I2S_BASE ++ ++#define I2S_DMA_REG_OFFSET (0x00000000) ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define I2S_SUPPORT_GATE_SHIFT 1 ++#define I2S_MAX_CHANNELS 6 ++#define I2S_GK_IP 1 ++#define I2S_24BITMUX_MODE_REG_BITS 4 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define I2S_MODE_OFFSET 0x08 ++#define I2S_RX_CTRL_OFFSET 0x2c ++#define I2S_TX_CTRL_OFFSET 0x0c ++#define I2S_WLEN_OFFSET 0x58 ++#define I2S_WPOS_OFFSET 0x44 ++#define I2S_SLOT_OFFSET 0x50 ++#define I2S_TX_FIFO_LTH_OFFSET 0x10 ++#define I2S_RX_FIFO_GTH_OFFSET 0x3c ++#define I2S_CLOCK_OFFSET 0x00 ++#define I2S_INIT_OFFSET 0x4c ++#define I2S_TX_STATUS_OFFSET 0x14 ++#define I2S_TX_LEFT_DATA_OFFSET 0x1c ++#define I2S_TX_RIGHT_DATA_OFFSET 0x20 ++#define I2S_RX_STATUS_OFFSET 0x54 ++#define I2S_RX_DATA_OFFSET 0x30 ++#define I2S_TX_FIFO_CNTR_OFFSET 0x18 ++#define I2S_RX_FIFO_CNTR_OFFSET 0x34 ++#define I2S_TX_INT_ENABLE_OFFSET 0x24 ++#define I2S_RX_INT_ENABLE_OFFSET 0x38 ++#define I2S_RX_ECHO_OFFSET 0x40 ++#define I2S_24BITMUX_MODE_OFFSET 0x28 ++#define I2S_RX_DATA_DMA_OFFSET 0x80 ++#define I2S_TX_LEFT_DATA_DMA_OFFSET 0xc0 ++ ++#define I2S_MODE_REG I2S_REG(0x08) ++#define I2S_RX_CTRL_REG I2S_REG(0x2c) ++#define I2S_TX_CTRL_REG I2S_REG(0x0c) ++#define I2S_WLEN_REG I2S_REG(0x58) ++#define I2S_WPOS_REG I2S_REG(0x44) ++#define I2S_SLOT_REG I2S_REG(0x50) ++#define I2S_TX_FIFO_LTH_REG I2S_REG(0x10) ++#define I2S_RX_FIFO_GTH_REG I2S_REG(0x3c) ++#define I2S_CLOCK_REG I2S_REG(0x00) ++#define I2S_INIT_REG I2S_REG(0x4c) ++#define I2S_TX_STATUS_REG I2S_REG(0x14) ++#define I2S_TX_LEFT_DATA_REG I2S_REG(0x1c) ++#define I2S_TX_RIGHT_DATA_REG I2S_REG(0x20) ++#define I2S_RX_STATUS_REG I2S_REG(0x54) ++#define I2S_RX_DATA_REG I2S_REG(0x30) ++#define I2S_TX_FIFO_CNTR_REG I2S_REG(0x18) ++#define I2S_RX_FIFO_CNTR_REG I2S_REG(0x34) ++#define I2S_TX_INT_ENABLE_REG I2S_REG(0x24) ++#define I2S_RX_INT_ENABLE_REG I2S_REG(0x38) ++#define I2S_RX_ECHO_REG I2S_REG(0x40) ++#define I2S_24BITMUX_MODE_REG I2S_REG(0x28) ++#define I2S_GATEOFF_REG I2S_REG(0x48) ++#define I2S_CHANNEL_SELECT_REG I2S_REG(0x04) ++#define I2S_RX_DATA_DMA_REG I2S_REG(0x80) ++#define I2S_TX_LEFT_DATA_DMA_REG I2S_REG(0xc0) ++ ++ ++#if (I2S_GK_IP == 1) ++#define I2S_TX_FIFO_RESET_BIT (1 << 0) ++#define I2S_RX_FIFO_RESET_BIT (1 << 3) ++#endif ++#define I2S_TX_ENABLE_BIT (1 << 2) ++#define I2S_RX_ENABLE_BIT (1 << 1) ++#define I2S_FIFO_RESET_BIT (1 << 4) ++ ++#define I2S_RX_LOOPBACK_BIT (1 << 2) ++#define I2S_RX_ORDER_BIT (1 << 0) ++#define I2S_RX_WS_MST_BIT (1 << 3) ++#define I2S_RX_WS_INV_BIT (1 << 1) ++ ++#define I2S_TX_LOOPBACK_BIT (1 << 5) ++#define I2S_TX_ORDER_BIT (1 << 3) ++#define I2S_TX_WS_MST_BIT (1 << 6) ++#define I2S_TX_WS_INV_BIT (1 << 2) ++#define I2S_TX_UNISON_BIT (1 << 4) ++#define I2S_TX_MUTE_BIT (1 << 7) ++#define I2S_TX_MONO_MASK 0xfffffffc ++#define I2S_TX_MONO_STEREO (0) ++#define I2S_TX_MONO_RIGHT (2) ++#define I2S_TX_MONO_LEFT (3) ++ ++#define I2S_CLK_WS_OUT_EN (1 << 7) ++#define I2S_CLK_BCLK_OUT_EN (1 << 5) ++#define I2S_CLK_BCLK_OUTPUT (1 << 8) ++#define I2S_CLK_TX_PO_FALL (1 << 9) ++#define I2S_CLK_RX_PO_FALL (1 << 6) ++#define I2S_CLK_DIV_MASK 0xffffffe0 ++#define I2S_CLK_MASTER_MODE (I2S_CLK_WS_OUT_EN | \ ++ I2S_CLK_BCLK_OUT_EN | \ ++ I2S_CLK_TX_PO_FALL | \ ++ I2S_CLK_RX_PO_FALL | \ ++ I2S_CLK_BCLK_OUTPUT) ++ ++ ++#if (I2S_GK_IP == 0) ++#define I2S_RX_SHIFT_ENB (1 << 2) ++#define I2S_TX_SHIFT_ENB (1 << 1) ++#else ++#define I2S_RX_SHIFT_ENB (1 << 1) ++#define I2S_TX_SHIFT_ENB (1 << 0) ++#endif ++ ++#define I2S_2CHANNELS_ENB 0x00 ++#define I2S_4CHANNELS_ENB 0x01 ++#define I2S_6CHANNELS_ENB 0x02 ++ ++#define I2S_FIFO_THRESHOLD_INTRPT 0x08 ++#define I2S_FIFO_FULL_INTRPT 0x02 ++#define I2S_FIFO_EMPTY_INTRPT 0x01 ++ ++/* I2S_24BITMUX_MODE_REG */ ++#define I2S_24BITMUX_MODE_BIT (1 << 3) ++#if (I2S_24BITMUX_MODE_REG_BITS == 4) ++#define I2S_24BITMUX_MODE_FDMA_BURST_DIS 0x2 ++#define I2S_24BITMUX_MODE_RST_CHAN0 0x4 ++#define I2S_24BITMUX_MODE_DMA_BOOTSEL 0x8 ++#endif ++ ++#endif /* __HAL_I2S_H__ */ +diff --git a/arch/arm/mach-gk710xs/include/mach/idc.h b/arch/arm/mach-gk710xs/include/mach/idc.h +new file mode 100644 +index 00000000..0b462563 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/idc.h +@@ -0,0 +1,165 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/idc.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __MACH_IDC_H__ ++#define __MACH_IDC_H__ ++ ++#include ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define IDC_INSTANCES 2 ++#define IDCS_INSTANCES 0 ++ ++#define IDC_INTERNAL_DELAY_CLK 2 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define IDC_PSLL_OFFSET 0x00 ++#define IDC_PSLH_OFFSET 0x04 ++#define IDC_FMCTRL_OFFSET 0x08 ++#define IDC_CTRL_OFFSET 0x0c ++#define IDC_STS_OFFSET 0x10 ++#define IDC_ENR_OFFSET 0x14 ++#define IDC_DATA_OFFSET 0x18 ++#define IDC_FMDATA_OFFSET 0x1c ++ ++#if (IDCS_INSTANCES >= 1) ++#define IDCS_ENR_OFFSET 0x00 ++#define IDCS_CTRL_OFFSET 0x04 ++#define IDCS_DATA_OFFSET 0x08 ++#define IDCS_STS_OFFSET 0x0c ++#define IDCS_FIFO_CNT_OFFSET 0x10 ++#define IDCS_RX_CNT_OFFSET 0x14 ++#define IDCS_TX_CNT_OFFSET 0x18 ++#define IDCS_HOLD_TIME_OFFSET 0x1c ++#define IDCS_SLAVE_ADDR_OFFSET 0x20 ++#define IDCS_SCL_TIMER_OFFSET 0x24 ++#define IDCS_TIMEOUT_STS_OFFSET 0x28 ++#endif ++ ++#define IDC_REG(x) (GK_PA_IDC + (x)) ++ ++#define IDC_ENR_REG IDC_REG(IDC_ENR_OFFSET) ++#define IDC_CTRL_REG IDC_REG(IDC_CTRL_OFFSET) ++#define IDC_DATA_REG IDC_REG(IDC_DATA_OFFSET) ++#define IDC_STS_REG IDC_REG(IDC_STS_OFFSET) ++#define IDC_PSLL_REG IDC_REG(IDC_PSLL_OFFSET) ++#define IDC_PSLH_REG IDC_REG(IDC_PSLH_OFFSET) ++#define IDC_FMCTRL_REG IDC_REG(IDC_FMCTRL_OFFSET) ++#define IDC_FMDATA_REG IDC_REG(IDC_FMDATA_OFFSET) ++ ++#if (IDC_INSTANCES >= 2) ++ ++#define IDC2_REG(x) (GK_PA_IDC2 + (x)) ++ ++#define IDC2_ENR_REG IDC2_REG(IDC_ENR_OFFSET) ++#define IDC2_CTRL_REG IDC2_REG(IDC_CTRL_OFFSET) ++#define IDC2_DATA_REG IDC2_REG(IDC_DATA_OFFSET) ++#define IDC2_STS_REG IDC2_REG(IDC_STS_OFFSET) ++#define IDC2_PSLL_REG IDC2_REG(IDC_PSLL_OFFSET) ++#define IDC2_PSLH_REG IDC2_REG(IDC_PSLH_OFFSET) ++#define IDC2_FMCTRL_REG IDC2_REG(IDC_FMCTRL_OFFSET) ++#define IDC2_FMDATA_REG IDC2_REG(IDC_FMDATA_OFFSET) ++#endif ++ ++#if (IDCS_INSTANCES >= 1) ++#define IDCS_ENR_REG IDCS_REG(IDCS_ENR_OFFSET) ++#define IDCS_CTRL_REG IDCS_REG(IDCS_CTRL_OFFSET) ++#define IDCS_DATA_REG IDCS_REG(IDCS_DATA_OFFSET) ++#define IDCS_STS_REG IDCS_REG(IDCS_STS_OFFSET) ++#define IDCS_FIFO_CNT_REG IDCS_REG(IDCS_FIFO_CNT_OFFSET) ++#define IDCS_RX_CNT_REG IDCS_REG(IDCS_RX_CNT_OFFSET) ++#define IDCS_TX_CNT_REG IDCS_REG(IDCS_TX_CNT_OFFSET) ++#define IDCS_HOLD_TIME_REG IDCS_REG(IDCS_HOLD_TIME_OFFSET) ++#define IDCS_SLAVE_ADDR_REG IDCS_REG(IDCS_SLAVE_ADDR_OFFSET) ++#define IDCS_SCL_TIMER_REG IDCS_REG(IDCS_SCL_TIMER_OFFSET) ++#define IDCS_TIMEOUT_STS_REG IDCS_REG(IDCS_TIMEOUT_STS_OFFSET) ++ ++ ++/* Bit/format definition */ ++ ++/* IDCS_CTRL_REG */ ++#define IDCS_IRQ_EN 0x02 ++#define IDCS_IRQ_P_SR_EN 0x04 ++#define IDCS_IRQ_FIFO_TH_EN 0x08 ++#define IDCS_IRQ_TIME_OUT_EN 0x10 ++ ++/* IDCS_STS_REG */ ++#define IDCS_TIMEOUT 0x100 ++#define IDCS_STOP 0x080 ++#define IDCS_REPEATED_START 0x040 ++#define IDCS_FIFO_TH_VLD 0x020 ++#define IDCS_SEL 0x010 ++#define IDCS_GENERAL_CALL 0x008 ++#define IDCS_FIFO_FULL 0x004 ++#define IDCS_FIFO_EMPTY 0x002 ++#define IDCS_RX_TX_STATE 0x001 ++ ++#define IDCS_TX_MODE 0x0 ++#define IDCS_RX_MODE 0x1 ++ ++#endif ++ ++/* ==========================================================================*/ ++/* IDC_ENABLE_REG */ ++#define IDC_ENR_ENABLE (0x01)//bit0 ++#define IDC_ENR_DISABLE (0x00) ++ ++/* IDC_CTRL_REG */ ++#define IDC_CTRL_IF (0x08)//bit3 ++#define IDC_CTRL_ACK (0x04)//bit2 ++#define IDC_CTRL_START (0x02)//bit1 ++#define IDC_CTRL_STOP (0x01)//bit0 ++#define IDC_CTRL_CLS (0x00) ++ ++#define IDC_FIFO_BUF_SIZE (63) ++ ++/* IDC_STS_REG */ ++#define IDC_STS_MODE (0x01)//1:master receiver; 0:master transmitter ++ ++/* IDC_FM_CTRL_REG */ ++ ++#define IDC_FMCTRL_IF (0x10)//bit4 ++#define IDC_FMCTRL_START (0x02)//bit1 ++#define IDC_FMCTRL_STOP (0x01)//bit0 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_platform_i2c { ++ int clk_limit; //Hz ++ int bulk_write_num; ++ unsigned int i2c_class; ++ u32 (*get_clock)(void); ++}; ++#define IDC_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(idc##id##_clk_limit, ¶m_ops_int, &(arg.clk_limit), perm); \ ++ module_param_cb(idc##id##_bulk_write_num, ¶m_ops_int, &(arg.bulk_write_num), perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_idc; ++extern struct platform_device gk_idc_hdmi; ++//extern struct platform_device gk_i2cmux; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IDC_H__ */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/io.h b/arch/arm/mach-gk710xs/include/mach/io.h +new file mode 100644 +index 00000000..866e4fca +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/io.h +@@ -0,0 +1,491 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/io.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IO_H ++#define __MACH_IO_H ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#ifndef __ASSEMBLER__ ++ ++#include ++ ++extern spinlock_t gk_reg_lock; ++extern unsigned long gk_reg_flags; ++extern u32 gk_reglock_count; ++ ++#define gk_hal_readb(a) g_hw->hw_readb((u32)(a)) ++#define gk_hal_readw(a) g_hw->hw_readw((u32)(a)) ++#define gk_hal_writeb(a,v) g_hw->hw_writeb((v),(u32)(a)) ++#define gk_hal_writew(a,v) g_hw->hw_writew((v),(u32)(a)) ++#define gk_hal_readl(a) g_hw->hw_readl((u32)(a)) ++#define gk_hal_writel(a,v) g_hw->hw_writel((v),(u32)(a)) ++#if FLASH_HAL_MODE ++#define gk_flash_read() g_hw->flash_read() ++#define gk_flash_write(v) g_hw->flash_write((v)) ++#else ++#define gk_flash_read() (*((volatile unsigned int *)(REG_SFLASH_DATA))) ++#define gk_flash_write(v) (*((volatile unsigned int *)(REG_SFLASH_DATA)) = (v)); ++#endif ++ ++#if 0 ++#define GK_REG_LOCK() spin_lock_irqsave(&gk_reg_lock, gk_reg_flags) ++#define GK_REG_UNLOCK() spin_unlock_irqrestore(&gk_reg_lock, gk_reg_flags) ++#define GK_INC_REGLOCK_COUNT() gk_reglock_count++ ++#else ++#define GK_REG_LOCK() ++#define GK_REG_UNLOCK() ++#define GK_INC_REGLOCK_COUNT() ++#endif ++ ++#define HAL_IO(mod) \ ++unsigned char gk_##mod##_readb(unsigned int addr) \ ++{\ ++ return g_hw->hw_readb((u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readb);\ ++unsigned short gk_##mod##_readw(unsigned int addr) \ ++{\ ++ return g_hw->hw_readw((u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readw);\ ++unsigned int gk_##mod##_readl(unsigned int addr) \ ++{\ ++ return g_hw->hw_readl((u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readl);\ ++void gk_##mod##_writeb(unsigned int addr,unsigned char val) \ ++{\ ++ g_hw->hw_writeb((val),(u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writeb); \ ++void gk_##mod##_writew(unsigned int addr,unsigned short val) \ ++{\ ++ g_hw->hw_writew((val),(u32)(addr)); \ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writew); \ ++void gk_##mod##_writel(unsigned int addr,unsigned int val) \ ++{\ ++ g_hw->hw_writel((val),(u32)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writel); ++#define DIR_IO(mod) \ ++unsigned char gk_##mod##_readb(unsigned int addr) \ ++{\ ++ return *((volatile unsigned char*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readb);\ ++unsigned short gk_##mod##_readw(unsigned int addr)\ ++{\ ++ return *((volatile unsigned short*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readw);\ ++unsigned int gk_##mod##_readl(unsigned int addr)\ ++{\ ++ return *((volatile unsigned int*)(addr));\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_readl);\ ++void gk_##mod##_writeb(unsigned int addr,unsigned char val)\ ++{\ ++ *((volatile unsigned char*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writeb);\ ++void gk_##mod##_writew(unsigned int addr,unsigned short val)\ ++{\ ++ *((volatile unsigned short*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writew);\ ++void gk_##mod##_writel(unsigned int addr,unsigned int val)\ ++{\ ++ *((volatile unsigned int*)(addr))= val;\ ++}\ ++EXPORT_SYMBOL(gk_##mod##_writel); ++ ++ ++#define IO_DEC(mod) \ ++extern unsigned char gk_##mod##_readb(unsigned int addr); \ ++extern unsigned short gk_##mod##_readw(unsigned int addr); \ ++extern unsigned int gk_##mod##_readl(unsigned int addr); \ ++extern void gk_##mod##_writeb(unsigned int addr,unsigned char val); \ ++extern void gk_##mod##_writew(unsigned int addr,unsigned short val); \ ++extern void gk_##mod##_writel(unsigned int addr,unsigned int val); ++ ++IO_DEC(hw) ++IO_DEC(adc) ++IO_DEC(aud) ++IO_DEC(cry) ++IO_DEC(ddr) ++IO_DEC(dma) ++IO_DEC(dsp) ++IO_DEC(eth) ++IO_DEC(greg) ++IO_DEC(gpio) ++IO_DEC(i2c) ++IO_DEC(i2s) ++IO_DEC(ir) ++IO_DEC(irq) ++IO_DEC(mcu) ++IO_DEC(pmu) ++IO_DEC(rct) ++IO_DEC(sd) ++IO_DEC(sf) ++IO_DEC(ssi) ++IO_DEC(timer) ++IO_DEC(uart) ++IO_DEC(usb) ++IO_DEC(vout) ++IO_DEC(wdt) ++IO_DEC(pwm) ++IO_DEC(efuse) ++ ++#define GK_HAL_OS_LOCK() \ ++ do { \ ++ GK_REG_LOCK(); \ ++ GK_INC_REGLOCK_COUNT(); \ ++ } while(0) ++ ++ ++#define GK_HAL_OS_UNLOCK() \ ++ do { \ ++ GK_REG_UNLOCK(); \ ++ } while(0) ++ ++//-------------------------------------- ++static inline u8 __gk_readb(const volatile void __iomem *address) ++{ ++ u8 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readb((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writeb(const volatile void __iomem *address, u8 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writeb((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++static inline u16 __gk_readw(const volatile void __iomem *address) ++{ ++ u16 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readw((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writew(const volatile void __iomem *address, u16 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writew((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++static inline u32 __gk_readl(const volatile void __iomem *address) ++{ ++ u32 tmpval; ++ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ tmpval = gk_hw_readl((u32)address); ++ GK_REG_UNLOCK(); ++ ++ return tmpval; ++} ++ ++static inline void __gk_writel(const volatile void __iomem *address, u32 value) ++{ ++ GK_REG_LOCK(); ++ GK_INC_REGLOCK_COUNT(); ++ gk_hw_writel((u32)address,value); ++ GK_REG_UNLOCK(); ++} ++ ++#define gk_adc_setbitsb(v, mask) gk_adc_writeb((v),(gk_adc_readb((v)) | (mask))) ++#define gk_adc_setbitsw(v, mask) gk_adc_writew((v),(gk_adc_readw((v)) | (mask))) ++#define gk_adc_setbitsl(v, mask) gk_adc_writel((v),(gk_adc_readl((v)) | (mask))) ++#define gk_adc_clrbitsb(v, mask) gk_adc_writeb((v),(gk_adc_readb((v)) & ~(mask))) ++#define gk_adc_clrbitsw(v, mask) gk_adc_writew((v),(gk_adc_readw((v)) & ~(mask))) ++#define gk_adc_clrbitsl(v, mask) gk_adc_writel((v),(gk_adc_readl((v)) & ~(mask))) ++#define gk_adc_tstbitsb(v, mask) (gk_adc_readb((v)) & (mask)) ++#define gk_adc_tstbitsw(v, mask) (gk_adc_readw((v)) & (mask)) ++#define gk_adc_tstbitsl(v, mask) (gk_adc_readl((v)) & (mask)) ++ ++#define gk_aud_setbitsb(v, mask) gk_aud_writeb((v),(gk_aud_readb((v)) | (mask))) ++#define gk_aud_setbitsw(v, mask) gk_aud_writew((v),(gk_aud_readw((v)) | (mask))) ++#define gk_aud_setbitsl(v, mask) gk_aud_writel((v),(gk_aud_readl((v)) | (mask))) ++#define gk_aud_clrbitsb(v, mask) gk_aud_writeb((v),(gk_aud_readb((v)) & ~(mask))) ++#define gk_aud_clrbitsw(v, mask) gk_aud_writew((v),(gk_aud_readw((v)) & ~(mask))) ++#define gk_aud_clrbitsl(v, mask) gk_aud_writel((v),(gk_aud_readl((v)) & ~(mask))) ++#define gk_aud_tstbitsb(v, mask) (gk_aud_readb((v)) & (mask)) ++#define gk_aud_tstbitsw(v, mask) (gk_aud_readw((v)) & (mask)) ++#define gk_aud_tstbitsl(v, mask) (gk_aud_readl((v)) & (mask)) ++ ++#define gk_cry_setbitsb(v, mask) gk_cry_writeb((v),(gk_cry_readb((v)) | (mask))) ++#define gk_cry_setbitsw(v, mask) gk_cry_writew((v),(gk_cry_readw((v)) | (mask))) ++#define gk_cry_setbitsl(v, mask) gk_cry_writel((v),(gk_cry_readl((v)) | (mask))) ++#define gk_cry_clrbitsb(v, mask) gk_cry_writeb((v),(gk_cry_readb((v)) & ~(mask))) ++#define gk_cry_clrbitsw(v, mask) gk_cry_writew((v),(gk_cry_readw((v)) & ~(mask))) ++#define gk_cry_clrbitsl(v, mask) gk_cry_writel((v),(gk_cry_readl((v)) & ~(mask))) ++#define gk_cry_tstbitsb(v, mask) (gk_cry_readb((v)) & (mask)) ++#define gk_cry_tstbitsw(v, mask) (gk_cry_readw((v)) & (mask)) ++#define gk_cry_tstbitsl(v, mask) (gk_cry_readl((v)) & (mask)) ++ ++#define gk_ddr_setbitsb(v, mask) gk_ddr_writeb((v),(gk_ddr_readb((v)) | (mask))) ++#define gk_ddr_setbitsw(v, mask) gk_ddr_writew((v),(gk_ddr_readw((v)) | (mask))) ++#define gk_ddr_setbitsl(v, mask) gk_ddr_writel((v),(gk_ddr_readl((v)) | (mask))) ++#define gk_ddr_clrbitsb(v, mask) gk_ddr_writeb((v),(gk_ddr_readb((v)) & ~(mask))) ++#define gk_ddr_clrbitsw(v, mask) gk_ddr_writew((v),(gk_ddr_readw((v)) & ~(mask))) ++#define gk_ddr_clrbitsl(v, mask) gk_ddr_writel((v),(gk_ddr_readl((v)) & ~(mask))) ++#define gk_ddr_tstbitsb(v, mask) (gk_ddr_readb((v)) & (mask)) ++#define gk_ddr_tstbitsw(v, mask) (gk_ddr_readw((v)) & (mask)) ++#define gk_ddr_tstbitsl(v, mask) (gk_ddr_readl((v)) & (mask)) ++ ++#define gk_dma_setbitsb(v, mask) gk_dma_writeb((v),(gk_dma_readb((v)) | (mask))) ++#define gk_dma_setbitsw(v, mask) gk_dma_writew((v),(gk_dma_readw((v)) | (mask))) ++#define gk_dma_setbitsl(v, mask) gk_dma_writel((v),(gk_dma_readl((v)) | (mask))) ++#define gk_dma_clrbitsb(v, mask) gk_dma_writeb((v),(gk_dma_readb((v)) & ~(mask))) ++#define gk_dma_clrbitsw(v, mask) gk_dma_writew((v),(gk_dma_readw((v)) & ~(mask))) ++#define gk_dma_clrbitsl(v, mask) gk_dma_writel((v),(gk_dma_readl((v)) & ~(mask))) ++#define gk_dma_tstbitsb(v, mask) (gk_dma_readb((v)) & (mask)) ++#define gk_dma_tstbitsw(v, mask) (gk_dma_readw((v)) & (mask)) ++#define gk_dma_tstbitsl(v, mask) (gk_dma_readl((v)) & (mask)) ++ ++#define gk_dsp_setbitsb(v, mask) gk_dsp_writeb((v),(gk_dsp_readb((v)) | (mask))) ++#define gk_dsp_setbitsw(v, mask) gk_dsp_writew((v),(gk_dsp_readw((v)) | (mask))) ++#define gk_dsp_setbitsl(v, mask) gk_dsp_writel((v),(gk_dsp_readl((v)) | (mask))) ++#define gk_dsp_clrbitsb(v, mask) gk_dsp_writeb((v),(gk_dsp_readb((v)) & ~(mask))) ++#define gk_dsp_clrbitsw(v, mask) gk_dsp_writew((v),(gk_dsp_readw((v)) & ~(mask))) ++#define gk_dsp_clrbitsl(v, mask) gk_dsp_writel((v),(gk_dsp_readl((v)) & ~(mask))) ++#define gk_dsp_tstbitsb(v, mask) (gk_dsp_readb((v)) & (mask)) ++#define gk_dsp_tstbitsw(v, mask) (gk_dsp_readw((v)) & (mask)) ++#define gk_dsp_tstbitsl(v, mask) (gk_dsp_readl((v)) & (mask)) ++ ++#define gk_eth_setbitsb(v, mask) gk_eth_writeb((v),(gk_eth_readb((v)) | (mask))) ++#define gk_eth_setbitsw(v, mask) gk_eth_writew((v),(gk_eth_readw((v)) | (mask))) ++#define gk_eth_setbitsl(v, mask) gk_eth_writel((v),(gk_eth_readl((v)) | (mask))) ++#define gk_eth_clrbitsb(v, mask) gk_eth_writeb((v),(gk_eth_readb((v)) & ~(mask))) ++#define gk_eth_clrbitsw(v, mask) gk_eth_writew((v),(gk_eth_readw((v)) & ~(mask))) ++#define gk_eth_clrbitsl(v, mask) gk_eth_writel((v),(gk_eth_readl((v)) & ~(mask))) ++#define gk_eth_tstbitsb(v, mask) (gk_eth_readb((v)) & (mask)) ++#define gk_eth_tstbitsw(v, mask) (gk_eth_readw((v)) & (mask)) ++#define gk_eth_tstbitsl(v, mask) (gk_eth_readl((v)) & (mask)) ++ ++#define gk_greg_setbitsb(v, mask) gk_greg_writeb((v),(gk_greg_readb((v)) | (mask))) ++#define gk_greg_setbitsw(v, mask) gk_greg_writew((v),(gk_greg_readw((v)) | (mask))) ++#define gk_greg_setbitsl(v, mask) gk_greg_writel((v),(gk_greg_readl((v)) | (mask))) ++#define gk_greg_clrbitsb(v, mask) gk_greg_writeb((v),(gk_greg_readb((v)) & ~(mask))) ++#define gk_greg_clrbitsw(v, mask) gk_greg_writew((v),(gk_greg_readw((v)) & ~(mask))) ++#define gk_greg_clrbitsl(v, mask) gk_greg_writel((v),(gk_greg_readl((v)) & ~(mask))) ++#define gk_greg_tstbitsb(v, mask) (gk_greg_readb((v)) & (mask)) ++#define gk_greg_tstbitsw(v, mask) (gk_greg_readw((v)) & (mask)) ++#define gk_greg_tstbitsl(v, mask) (gk_greg_readl((v)) & (mask)) ++ ++#define gk_gpio_setbitsb(v, mask) gk_gpio_writeb((v),(gk_gpio_readb((v)) | (mask))) ++#define gk_gpio_setbitsw(v, mask) gk_gpio_writew((v),(gk_gpio_readw((v)) | (mask))) ++#define gk_gpio_setbitsl(v, mask) gk_gpio_writel((v),(gk_gpio_readl((v)) | (mask))) ++#define gk_gpio_clrbitsb(v, mask) gk_gpio_writeb((v),(gk_gpio_readb((v)) & ~(mask))) ++#define gk_gpio_clrbitsw(v, mask) gk_gpio_writew((v),(gk_gpio_readw((v)) & ~(mask))) ++#define gk_gpio_clrbitsl(v, mask) gk_gpio_writel((v),(gk_gpio_readl((v)) & ~(mask))) ++#define gk_gpio_tstbitsb(v, mask) (gk_gpio_readb((v)) & (mask)) ++#define gk_gpio_tstbitsw(v, mask) (gk_gpio_readw((v)) & (mask)) ++#define gk_gpio_tstbitsl(v, mask) (gk_gpio_readl((v)) & (mask)) ++ ++#define gk_i2c_setbitsb(v, mask) gk_i2c_writeb((v),(gk_i2c_readb((v)) | (mask))) ++#define gk_i2c_setbitsw(v, mask) gk_i2c_writew((v),(gk_i2c_readw((v)) | (mask))) ++#define gk_i2c_setbitsl(v, mask) gk_i2c_writel((v),(gk_i2c_readl((v)) | (mask))) ++#define gk_i2c_clrbitsb(v, mask) gk_i2c_writeb((v),(gk_i2c_readb((v)) & ~(mask))) ++#define gk_i2c_clrbitsw(v, mask) gk_i2c_writew((v),(gk_i2c_readw((v)) & ~(mask))) ++#define gk_i2c_clrbitsl(v, mask) gk_i2c_writel((v),(gk_i2c_readl((v)) & ~(mask))) ++#define gk_i2c_tstbitsb(v, mask) (gk_i2c_readb((v)) & (mask)) ++#define gk_i2c_tstbitsw(v, mask) (gk_i2c_readw((v)) & (mask)) ++#define gk_i2c_tstbitsl(v, mask) (gk_i2c_readl((v)) & (mask)) ++ ++#define gk_i2s_setbitsb(v, mask) gk_i2s_writeb((v),(gk_i2s_readb((v)) | (mask))) ++#define gk_i2s_setbitsw(v, mask) gk_i2s_writew((v),(gk_i2s_readw((v)) | (mask))) ++#define gk_i2s_setbitsl(v, mask) gk_i2s_writel((v),(gk_i2s_readl((v)) | (mask))) ++#define gk_i2s_clrbitsb(v, mask) gk_i2s_writeb((v),(gk_i2s_readb((v)) & ~(mask))) ++#define gk_i2s_clrbitsw(v, mask) gk_i2s_writew((v),(gk_i2s_readw((v)) & ~(mask))) ++#define gk_i2s_clrbitsl(v, mask) gk_i2s_writel((v),(gk_i2s_readl((v)) & ~(mask))) ++#define gk_i2s_tstbitsb(v, mask) (gk_i2s_readb((v)) & (mask)) ++#define gk_i2s_tstbitsw(v, mask) (gk_i2s_readw((v)) & (mask)) ++#define gk_i2s_tstbitsl(v, mask) (gk_i2s_readl((v)) & (mask)) ++ ++ ++#define gk_ir_setbitsb(v, mask) gk_ir_writeb((v),(gk_ir_readb((v)) | (mask))) ++#define gk_ir_setbitsw(v, mask) gk_ir_writew((v),(gk_ir_readw((v)) | (mask))) ++#define gk_ir_setbitsl(v, mask) gk_ir_writel((v),(gk_ir_readl((v)) | (mask))) ++#define gk_ir_clrbitsb(v, mask) gk_ir_writeb((v),(gk_ir_readb((v)) & ~(mask))) ++#define gk_ir_clrbitsw(v, mask) gk_ir_writew((v),(gk_ir_readw((v)) & ~(mask))) ++#define gk_ir_clrbitsl(v, mask) gk_ir_writel((v),(gk_ir_readl((v)) & ~(mask))) ++#define gk_ir_tstbitsb(v, mask) (gk_ir_readb((v)) & (mask)) ++#define gk_ir_tstbitsw(v, mask) (gk_ir_readw((v)) & (mask)) ++#define gk_ir_tstbitsl(v, mask) (gk_ir_readl((v)) & (mask)) ++ ++#define gk_irq_setbitsb(v, mask) gk_irq_writeb((v),(gk_irq_readb((v)) | (mask))) ++#define gk_irq_setbitsw(v, mask) gk_irq_writew((v),(gk_irq_readw((v)) | (mask))) ++#define gk_irq_setbitsl(v, mask) gk_irq_writel((v),(gk_irq_readl((v)) | (mask))) ++#define gk_irq_clrbitsb(v, mask) gk_irq_writeb((v),(gk_irq_readb((v)) & ~(mask))) ++#define gk_irq_clrbitsw(v, mask) gk_irq_writew((v),(gk_irq_readw((v)) & ~(mask))) ++#define gk_irq_clrbitsl(v, mask) gk_irq_writel((v),(gk_irq_readl((v)) & ~(mask))) ++#define gk_irq_tstbitsb(v, mask) (gk_irq_readb((v)) & (mask)) ++#define gk_irq_tstbitsw(v, mask) (gk_irq_readw((v)) & (mask)) ++#define gk_irq_tstbitsl(v, mask) (gk_irq_readl((v)) & (mask)) ++ ++#define gk_mcu_setbitsb(v, mask) gk_mcu_writeb((v),(gk_mcu_readb((v)) | (mask))) ++#define gk_mcu_setbitsw(v, mask) gk_mcu_writew((v),(gk_mcu_readw((v)) | (mask))) ++#define gk_mcu_setbitsl(v, mask) gk_mcu_writel((v),(gk_mcu_readl((v)) | (mask))) ++#define gk_mcu_clrbitsb(v, mask) gk_mcu_writeb((v),(gk_mcu_readb((v)) & ~(mask))) ++#define gk_mcu_clrbitsw(v, mask) gk_mcu_writew((v),(gk_mcu_readw((v)) & ~(mask))) ++#define gk_mcu_clrbitsl(v, mask) gk_mcu_writel((v),(gk_mcu_readl((v)) & ~(mask))) ++#define gk_mcu_tstbitsb(v, mask) (gk_mcu_readb((v)) & (mask)) ++#define gk_mcu_tstbitsw(v, mask) (gk_mcu_readw((v)) & (mask)) ++#define gk_mcu_tstbitsl(v, mask) (gk_mcu_readl((v)) & (mask)) ++ ++#define gk_pwm_setbitsb(v, mask) gk_pwm_writeb((v),(gk_pwm_readb((v)) | (mask))) ++#define gk_pwm_setbitsw(v, mask) gk_pwm_writew((v),(gk_pwm_readw((v)) | (mask))) ++#define gk_pwm_setbitsl(v, mask) gk_pwm_writel((v),(gk_pwm_readl((v)) | (mask))) ++#define gk_pwm_clrbitsb(v, mask) gk_pwm_writeb((v),(gk_pwm_readb((v)) & ~(mask))) ++#define gk_pwm_clrbitsw(v, mask) gk_pwm_writew((v),(gk_pwm_readw((v)) & ~(mask))) ++#define gk_pwm_clrbitsl(v, mask) gk_pwm_writel((v),(gk_pwm_readl((v)) & ~(mask))) ++#define gk_pwm_tstbitsb(v, mask) (gk_pwm_readb((v)) & (mask)) ++#define gk_pwm_tstbitsw(v, mask) (gk_pwm_readw((v)) & (mask)) ++#define gk_pwm_tstbitsl(v, mask) (gk_pwm_readl((v)) & (mask)) ++ ++#define gk_rct_setbitsb(v, mask) gk_rct_writeb((v),(gk_rct_readb((v)) | (mask))) ++#define gk_rct_setbitsw(v, mask) gk_rct_writew((v),(gk_rct_readw((v)) | (mask))) ++#define gk_rct_setbitsl(v, mask) gk_rct_writel((v),(gk_rct_readl((v)) | (mask))) ++#define gk_rct_clrbitsb(v, mask) gk_rct_writeb((v),(gk_rct_readb((v)) & ~(mask))) ++#define gk_rct_clrbitsw(v, mask) gk_rct_writew((v),(gk_rct_readw((v)) & ~(mask))) ++#define gk_rct_clrbitsl(v, mask) gk_rct_writel((v),(gk_rct_readl((v)) & ~(mask))) ++#define gk_rct_tstbitsb(v, mask) (gk_rct_readb((v)) & (mask)) ++#define gk_rct_tstbitsw(v, mask) (gk_rct_readw((v)) & (mask)) ++#define gk_rct_tstbitsl(v, mask) (gk_rct_readl((v)) & (mask)) ++ ++#define gk_sd_setbitsb(v, mask) gk_sd_writeb((v),(gk_sd_readb((v)) | (mask))) ++#define gk_sd_setbitsw(v, mask) gk_sd_writew((v),(gk_sd_readw((v)) | (mask))) ++#define gk_sd_setbitsl(v, mask) gk_sd_writel((v),(gk_sd_readl((v)) | (mask))) ++#define gk_sd_clrbitsb(v, mask) gk_sd_writeb((v),(gk_sd_readb((v)) & ~(mask))) ++#define gk_sd_clrbitsw(v, mask) gk_sd_writew((v),(gk_sd_readw((v)) & ~(mask))) ++#define gk_sd_clrbitsl(v, mask) gk_sd_writel((v),(gk_sd_readl((v)) & ~(mask))) ++#define gk_sd_tstbitsb(v, mask) (gk_sd_readb((v)) & (mask)) ++#define gk_sd_tstbitsw(v, mask) (gk_sd_readw((v)) & (mask)) ++#define gk_sd_tstbitsl(v, mask) (gk_sd_readl((v)) & (mask)) ++ ++#define gk_sf_setbitsb(v, mask) gk_sf_writeb((v),(gk_sf_readb((v)) | (mask))) ++#define gk_sf_setbitsw(v, mask) gk_sf_writew((v),(gk_sf_readw((v)) | (mask))) ++#define gk_sf_setbitsl(v, mask) gk_sf_writel((v),(gk_sf_readl((v)) | (mask))) ++#define gk_sf_clrbitsb(v, mask) gk_sf_writeb((v),(gk_sf_readb((v)) & ~(mask))) ++#define gk_sf_clrbitsw(v, mask) gk_sf_writew((v),(gk_sf_readw((v)) & ~(mask))) ++#define gk_sf_clrbitsl(v, mask) gk_sf_writel((v),(gk_sf_readl((v)) & ~(mask))) ++#define gk_sf_tstbitsb(v, mask) (gk_sf_readb((v)) & (mask)) ++#define gk_sf_tstbitsw(v, mask) (gk_sf_readw((v)) & (mask)) ++#define gk_sf_tstbitsl(v, mask) (gk_sf_readl((v)) & (mask)) ++ ++#define gk_ssi_setbitsb(v, mask) gk_ssi_writeb((v),(gk_ssi_readb((v)) | (mask))) ++#define gk_ssi_setbitsw(v, mask) gk_ssi_writew((v),(gk_ssi_readw((v)) | (mask))) ++#define gk_ssi_setbitsl(v, mask) gk_ssi_writel((v),(gk_ssi_readl((v)) | (mask))) ++#define gk_ssi_clrbitsb(v, mask) gk_ssi_writeb((v),(gk_ssi_readb((v)) & ~(mask))) ++#define gk_ssi_clrbitsw(v, mask) gk_ssi_writew((v),(gk_ssi_readw((v)) & ~(mask))) ++#define gk_ssi_clrbitsl(v, mask) gk_ssi_writel((v),(gk_ssi_readl((v)) & ~(mask))) ++#define gk_ssi_tstbitsb(v, mask) (gk_ssi_readb((v)) & (mask)) ++#define gk_ssi_tstbitsw(v, mask) (gk_ssi_readw((v)) & (mask)) ++#define gk_ssi_tstbitsl(v, mask) (gk_ssi_readl((v)) & (mask)) ++ ++#define gk_timer_setbitsb(v, mask) gk_timer_writeb((v),(gk_timer_readb((v)) | (mask))) ++#define gk_timer_setbitsw(v, mask) gk_timer_writew((v),(gk_timer_readw((v)) | (mask))) ++#define gk_timer_setbitsl(v, mask) gk_timer_writel((v),(gk_timer_readl((v)) | (mask))) ++#define gk_timer_clrbitsb(v, mask) gk_timer_writeb((v),(gk_timer_readb((v)) & ~(mask))) ++#define gk_timer_clrbitsw(v, mask) gk_timer_writew((v),(gk_timer_readw((v)) & ~(mask))) ++#define gk_timer_clrbitsl(v, mask) gk_timer_writel((v),(gk_timer_readl((v)) & ~(mask))) ++#define gk_timer_tstbitsb(v, mask) (gk_timer_readb((v)) & (mask)) ++#define gk_timer_tstbitsw(v, mask) (gk_timer_readw((v)) & (mask)) ++#define gk_timer_tstbitsl(v, mask) (gk_timer_readl((v)) & (mask)) ++ ++#define gk_uart_setbitsb(v, mask) gk_uart_writeb((v),(gk_uart_readb((v)) | (mask))) ++#define gk_uart_setbitsw(v, mask) gk_uart_writew((v),(gk_uart_readw((v)) | (mask))) ++#define gk_uart_setbitsl(v, mask) gk_uart_writel((v),(gk_uart_readl((v)) | (mask))) ++#define gk_uart_clrbitsb(v, mask) gk_uart_writeb((v),(gk_uart_readb((v)) & ~(mask))) ++#define gk_uart_clrbitsw(v, mask) gk_uart_writew((v),(gk_uart_readw((v)) & ~(mask))) ++#define gk_uart_clrbitsl(v, mask) gk_uart_writel((v),(gk_uart_readl((v)) & ~(mask))) ++#define gk_uart_tstbitsb(v, mask) (gk_uart_readb((v)) & (mask)) ++#define gk_uart_tstbitsw(v, mask) (gk_uart_readw((v)) & (mask)) ++#define gk_uart_tstbitsl(v, mask) (gk_uart_readl((v)) & (mask)) ++ ++#define gk_usb_setbitsb(v, mask) gk_usb_writeb((v),(gk_usb_readb((v)) | (mask))) ++#define gk_usb_setbitsw(v, mask) gk_usb_writew((v),(gk_usb_readw((v)) | (mask))) ++#define gk_usb_setbitsl(v, mask) gk_usb_writel((v),(gk_usb_readl((v)) | (mask))) ++#define gk_usb_clrbitsb(v, mask) gk_usb_writeb((v),(gk_usb_readb((v)) & ~(mask))) ++#define gk_usb_clrbitsw(v, mask) gk_usb_writew((v),(gk_usb_readw((v)) & ~(mask))) ++#define gk_usb_clrbitsl(v, mask) gk_usb_writel((v),(gk_usb_readl((v)) & ~(mask))) ++#define gk_usb_tstbitsb(v, mask) (gk_usb_readb((v)) & (mask)) ++#define gk_usb_tstbitsw(v, mask) (gk_usb_readw((v)) & (mask)) ++#define gk_usb_tstbitsl(v, mask) (gk_usb_readl((v)) & (mask)) ++ ++#define gk_vout_setbitsb(v, mask) gk_vout_writeb((v),(gk_vout_readb((v)) | (mask))) ++#define gk_vout_setbitsw(v, mask) gk_vout_writew((v),(gk_vout_readw((v)) | (mask))) ++#define gk_vout_setbitsl(v, mask) gk_vout_writel((v),(gk_vout_readl((v)) | (mask))) ++#define gk_vout_clrbitsb(v, mask) gk_vout_writeb((v),(gk_vout_readb((v)) & ~(mask))) ++#define gk_vout_clrbitsw(v, mask) gk_vout_writew((v),(gk_vout_readw((v)) & ~(mask))) ++#define gk_vout_clrbitsl(v, mask) gk_vout_writel((v),(gk_vout_readl((v)) & ~(mask))) ++#define gk_vout_tstbitsb(v, mask) (gk_vout_readb((v)) & (mask)) ++#define gk_vout_tstbitsw(v, mask) (gk_vout_readw((v)) & (mask)) ++#define gk_vout_tstbitsl(v, mask) (gk_vout_readl((v)) & (mask)) ++ ++#define gk_wdt_setbitsb(v, mask) gk_wdt_writeb((v),(gk_wdt_readb((v)) | (mask))) ++#define gk_wdt_setbitsw(v, mask) gk_wdt_writew((v),(gk_wdt_readw((v)) | (mask))) ++#define gk_wdt_setbitsl(v, mask) gk_wdt_writel((v),(gk_wdt_readl((v)) | (mask))) ++#define gk_wdt_clrbitsb(v, mask) gk_wdt_writeb((v),(gk_wdt_readb((v)) & ~(mask))) ++#define gk_wdt_clrbitsw(v, mask) gk_wdt_writew((v),(gk_wdt_readw((v)) & ~(mask))) ++#define gk_wdt_clrbitsl(v, mask) gk_wdt_writel((v),(gk_wdt_readl((v)) & ~(mask))) ++#define gk_wdt_tstbitsb(v, mask) (gk_wdt_readb((v)) & (mask)) ++#define gk_wdt_tstbitsw(v, mask) (gk_wdt_readw((v)) & (mask)) ++#define gk_wdt_tstbitsl(v, mask) (gk_wdt_readl((v)) & (mask)) ++ ++ ++#define gk_musb_readb(a, o) gk_usb_readb((a+o)) ++#define gk_musb_readw(a, o) gk_usb_readw((a+o)) ++#define gk_musb_readl(a, o) gk_usb_readl((a+o)) ++#define gk_musb_writeb(a, o, v) gk_usb_writeb((a+o),(v)) ++#define gk_musb_writew(a, o, v) gk_usb_writew((a+o),(v)) ++#define gk_musb_writel(a, o, v) gk_usb_writel((a+o),(v)) ++ ++#define gk_spi_readb(a) gk_ssi_readb((a)) ++#define gk_spi_readw(a) gk_ssi_readw((a)) ++#define gk_spi_readl(a) gk_ssi_readl((a)) ++#define gk_spi_writeb(a, v) gk_ssi_writeb((a),(v)) ++#define gk_spi_writew(a, v) gk_ssi_writew((a),(v)) ++#define gk_spi_writel(a, v) gk_ssi_writel((a),(v)) ++ ++ ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IO_H */ +diff --git a/arch/arm/mach-gk710xs/include/mach/ir.h b/arch/arm/mach-gk710xs/include/mach/ir.h +new file mode 100644 +index 00000000..8c4cc40a +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/ir.h +@@ -0,0 +1,50 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/ir.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IR_H ++#define __MACH_IR_H ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++enum gk_ir_protocol { ++ GK_IR_PROTOCOL_NEC = 0, ++ GK_IR_PROTOCOL_PANASONIC = 1, ++ GK_IR_PROTOCOL_SONY = 2, ++ GK_IR_PROTOCOL_PHILIPS = 3, ++ GK_IR_PROTOCOL_END ++}; ++ ++struct gk_ir_controller { ++ ++ int protocol; ++ int debug; ++}; ++#define GK_IR_PARAM_CALL(arg, perm) \ ++ module_param_cb(ir_protocol, ¶m_ops_int, &arg.protocol, perm); \ ++ module_param_cb(ir_debug, ¶m_ops_int, &arg.debug, perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_ir; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_IR_H */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/irqs.h b/arch/arm/mach-gk710xs/include/mach/irqs.h +new file mode 100644 +index 00000000..62bfc193 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/irqs.h +@@ -0,0 +1,198 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/irqs.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_IRQS_H ++#define __MACH_IRQS_H ++ ++#include ++#define NR_IRQS 128 ++ ++#define NR_VIC_IRQ_SIZE (32) ++ ++#define VIC1_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 0)) ++#define VIC2_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 1)) ++//#define VIC3_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 2)) ++//#define VIC4_INT_VEC(x) ((x) + (NR_VIC_IRQ_SIZE * 3)) ++ ++/* The following are ARCH specific IRQ numbers */ ++ ++#define VIC_INSTANCES 2 ++ ++#define NR_VIC_IRQS (VIC_INSTANCES * NR_VIC_IRQ_SIZE) ++#define GPIO_INT_VEC(x) (NR_VIC_IRQS + x) ++ ++// VIC Instance 1 ++#define SSI_SLAVE_IRQ 0 ++#define ETH_IRQ 1 ++#define ICORE_ERROR_IRQ 2 ++#define GPIO2_IRQ 4 ++#define CD2ND_BIT_CD_IRQ 5 ++#define USBVBUS_IRQ 6 ++#define VO_IRQ 7 ++#define DSP_VO1_IRQ 7 ++#define SD_IRQ 8 ++#define IDC_IRQ 9 ++#define SSI_IRQ 10 ++#define WDT_IRQ 11 ++#define IRIF_IRQ 12 ++#define SD1CD_IRQ 13 ++#define SDCD_IRQ 14 /* SD0 SD card card detection. */ ++#define UART1_IRQ 15 ++#define GPIO0_IRQ 16 ++#define GPIO1_IRQ 17 ++#define TIMER1_IRQ 18 ++#define TIMER2_IRQ 19 ++#define TIMER3_IRQ 20 ++#define DMA_IRQ 21 ++#define SD1_IRQ 22 ++#define FIODMA_IRQ 23 ++#define VI_IRQ 24 ++#define DSP_VI_IRQ 24 ++#define VCORE_IRQ 25 ++#define DSP_VCORE_IRQ 25 ++#define USBC_IRQ 26 ++#define UART2_IRQ 27 ++#define HIF2_IRQ 28 ++#define I2STX_IRQ 29 ++#define I2SRX_IRQ 30 ++#define UART0_IRQ 31 ++ ++// VIC Instance 2 ++#define DMA_FIOS_IRQ (32 + 7) ++#define VO0_TV_SYNC_IRQ (32 + 16) ++#define VO1_LCD_SYNC_IRQ (32 + 17) ++#define DSP_VO0_IRQ (32 + 18) ++#define AES_IRQ (32 + 19) ++#define DES_IRQ (32 + 20) ++#define MDMA_IRQ (32 + 22) ++#define MOTOR_IRQ (32 + 23) ++#define ADC_LEVEL_IRQ (32 + 24) ++#define IDC_HDMI_IRQ (32 + 26) ++#define ICORE_LAST_PIXEL_IRQ (32 + 27) ++#define ICORE_VSYNC_IRQ (32 + 28) ++#define ICORE_SENSOR_VSYNC_IRQ (32 + 29) ++#define HDMI_IRQ (32 + 30) ++#define SSI2_IRQ (32 + 31) ++ ++#define MAX_IRQ_NUM (SSI2_IRQ + 1) ++#define IR_IRQ HDMI_IRQ ++ ++ ++//#define MAX_IRQ_NUM (MOTOR_IRQ + 1) ++ ++#define GPIO_IRQ(x) ((x) + NR_VIC_IRQS) ++ ++ ++#define VIC_IRQ(x) (x) ++ ++ ++/* ++ * VIC trigger types (SW definition). ++ */ ++#define VIRQ_RISING_EDGE 0 ++#define VIRQ_FALLING_EDGE 1 ++#define VIRQ_BOTH_EDGES 2 ++#define VIRQ_LEVEL_LOW 3 ++#define VIRQ_LEVEL_HIGH 4 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define VIC_IRQ_STA_OFFSET 0x30 ++#define VIC_FIQ_STA_OFFSET 0x34 ++#define VIC_RAW_STA_OFFSET 0x18 ++#define VIC_INT_SEL_OFFSET 0x0c ++#define VIC_INTEN_OFFSET 0x10 ++#define VIC_INTEN_CLR_OFFSET 0x14 ++#define VIC_SOFTEN_OFFSET 0x1c ++#define VIC_SOFTEN_CLR_OFFSET 0x20 ++#define VIC_PROTEN_OFFSET 0x24 ++#define VIC_SENSE_OFFSET 0x00 ++#define VIC_BOTHEDGE_OFFSET 0x08 ++#define VIC_EVENT_OFFSET 0x04 ++#define VIC_EDGE_CLR_OFFSET 0x38 ++ ++#define VIC1_BASE (GK_VA_VIC1) ++#define VIC2_BASE (GK_VA_VIC2) ++ ++#define VIC1_REG(x) (VIC1_BASE + (x)) ++#define VIC2_REG(x) (VIC2_BASE + (x)) ++ ++#define VIC_IRQ_STA_REG VIC1_REG(VIC_IRQ_STA_OFFSET) ++#define VIC_FIQ_STA_REG VIC1_REG(VIC_FIQ_STA_OFFSET) ++#define VIC_RAW_STA_REG VIC1_REG(VIC_RAW_STA_OFFSET) ++#define VIC_INT_SEL_REG VIC1_REG(VIC_INT_SEL_OFFSET) ++#define VIC_INTEN_REG VIC1_REG(VIC_INTEN_OFFSET) ++#define VIC_INTEN_CLR_REG VIC1_REG(VIC_INTEN_CLR_OFFSET) ++#define VIC_SOFTEN_REG VIC1_REG(VIC_SOFTEN_OFFSET) ++#define VIC_SOFTEN_CLR_REG VIC1_REG(VIC_SOFTEN_CLR_OFFSET) ++#define VIC_PROTEN_REG VIC1_REG(VIC_PROTEN_OFFSET) ++#define VIC_SENSE_REG VIC1_REG(VIC_SENSE_OFFSET) ++#define VIC_BOTHEDGE_REG VIC1_REG(VIC_BOTHEDGE_OFFSET) ++#define VIC_EVENT_REG VIC1_REG(VIC_EVENT_OFFSET) ++#define VIC_EDGE_CLR_REG VIC1_REG(VIC_EDGE_CLR_OFFSET) ++ ++#if (VIC_INSTANCES >= 2) ++ ++#define VIC2_IRQ_STA_REG VIC2_REG(VIC_IRQ_STA_OFFSET) ++#define VIC2_FIQ_STA_REG VIC2_REG(VIC_FIQ_STA_OFFSET) ++#define VIC2_RAW_STA_REG VIC2_REG(VIC_RAW_STA_OFFSET) ++#define VIC2_INT_SEL_REG VIC2_REG(VIC_INT_SEL_OFFSET) ++#define VIC2_INTEN_REG VIC2_REG(VIC_INTEN_OFFSET) ++#define VIC2_INTEN_CLR_REG VIC2_REG(VIC_INTEN_CLR_OFFSET) ++#define VIC2_SOFTEN_REG VIC2_REG(VIC_SOFTEN_OFFSET) ++#define VIC2_SOFTEN_CLR_REG VIC2_REG(VIC_SOFTEN_CLR_OFFSET) ++#define VIC2_PROTEN_REG VIC2_REG(VIC_PROTEN_OFFSET) ++#define VIC2_SENSE_REG VIC2_REG(VIC_SENSE_OFFSET) ++#define VIC2_BOTHEDGE_REG VIC2_REG(VIC_BOTHEDGE_OFFSET) ++#define VIC2_EVENT_REG VIC2_REG(VIC_EVENT_OFFSET) ++#define VIC2_EDGE_CLR_REG VIC2_REG(VIC_EDGE_CLR_OFFSET) ++ ++#endif ++ ++struct gk_irq_info ++{ ++ int irq_gpio; ++ int irq_line; ++ int irq_type; ++ int irq_gpio_val; ++ int irq_gpio_mode; ++}; ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++#ifndef __ASSEMBLY__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++struct pt_regs; ++ ++extern void gk_init_irq(void) __init; ++extern void gk_vic_handle_irq(struct pt_regs *regs); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++#endif /* __MACH_IRQS_H */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/rct.h b/arch/arm/mach-gk710xs/include/mach/rct.h +new file mode 100644 +index 00000000..d7d38cf3 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/rct.h +@@ -0,0 +1,36 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/rct.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_RCT_H ++#define __MACH_RCT_H ++ ++/* ==============================================*/ ++#define GK_APB_FREQ 69000000 //20MHz ++#define GK_UART_FREQ 24000000 ++#define GK_SD_FREQ 48000000 ++ ++u32 get_apb_bus_freq_hz(void); ++u32 get_uart_freq_hz(void); ++u32 get_sd_freq_hz(void); ++u32 get_ssi0_freq_hz(void); ++u32 get_ssi1_freq_hz(void); ++ ++void set_sd_rct(u32 freq); ++ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/sd.h b/arch/arm/mach-gk710xs/include/mach/sd.h +new file mode 100644 +index 00000000..03b08c44 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/sd.h +@@ -0,0 +1,512 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/sd.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK_SD_H ++#define __MACH_GK_SD_H ++ ++#include ++ ++/* ==========================================================================*/ ++#define GK_SD_MAX_SLOT_NUM (2) ++ ++#define GK_SD_PRIVATE_CAPS_VDD_18 (0x1 << 0) ++#define GK_SD_PRIVATE_CAPS_ADMA (0x1 << 1) ++#define GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK (0x1 << 2) ++#define GK_SD_PRIVATE_CAPS_DDR (0x1 << 3) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_sd_slot { ++ struct mmc_host *pmmc_host; ++ ++ u32 default_caps; ++ u32 active_caps; ++ u32 default_caps2; ++ u32 active_caps2; ++ u32 private_caps; ++ ++ struct gk_gpio_io_info ext_power; ++ struct gk_gpio_io_info ext_reset; ++ int fixed_cd; ++ struct gk_irq_info gpio_cd; ++ u32 cd_delay; //jiffies ++ int fixed_wp; ++ struct gk_gpio_io_info gpio_wp; ++ ++ int (*check_owner)(void); ++ void (*request)(void); ++ void (*release)(void); ++ void (*set_int)(u32 mask, u32 on); ++ void (*set_vdd)(u32 vdd); ++ void (*set_bus_timing)(u32 timing); ++}; ++ ++struct gk_sd_controller { ++ u32 num_slots; ++ struct gk_sd_slot slot[GK_SD_MAX_SLOT_NUM]; ++ void (*set_pll)(u32); ++ u32 (*get_pll)(void); ++ ++ u32 max_blk_mask; ++ u32 max_clock; ++ u32 active_clock; ++ u32 wait_tmo; ++ u32 pwr_delay; //ms ++ ++ u32 dma_fix; ++ u32 support_pll_scaler; ++}; ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_sd0; ++ ++extern int gk_init_sd(void); ++extern void gk_detect_sd_slot(int bus, int slot, int fixed_cd); ++extern void gk_set_sd_detect_pin(u32 gpio_pin); ++#ifdef CONFIG_GK710XS_SDIO2 ++extern struct platform_device gk_sd1; ++extern void gk_detect_sd1_slot(int bus, int slot, int fixed_cd); ++extern void gk_set_sd1_detect_pin(u32 gpio_pin); ++#endif ++ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#define SD_INSTANCES 1 ++#define SD_SUPPORT_PLL_SCALER 0 ++#define SD_HAS_INTERNAL_MUXER 1 ++#define SD_HAS_INTERNAL_2ND_CDWP 0 ++#define SD_HAS_DELAY_CTRL 0 ++#define SD_BUS_SWITCH_DLY 0 ++#define SD_HAS_IO_DRIVE_CTRL 1 ++ ++#define SD_HOST1_SUPPORT_XC 0 ++#define SD_HOST2_SUPPORT_XC 0 ++ ++#define SD_SUPPORT_ACMD23 1 ++ ++#define SD_HAS_SDXC_CLOCK 0 ++ ++#define SD_HOST1_HOST2_HAS_MUX 0 ++#define SD_SUPPORT_ADMA 0 ++ ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define SD_REG(x) (GK_VA_SDC + (x)) //(0xf0002000 + (x)) ++#ifdef CONFIG_GK710XS_SDIO2 ++#define SD1_REG(x) (GK_VA_SDC1 + (x)) //(0xf0002000 + (x)) ++#endif ++ ++#define SD_DMA_ADDR_OFFSET 0x000 ++#define SD_BLK_SZ_OFFSET 0x00c /* Half word */ ++#define SD_BLK_CNT_OFFSET 0x00a /* Half word */ ++#define SD_ARG_OFFSET 0x034 ++#define SD_XFR_OFFSET 0x004 /* Half word */ ++#define SD_CMD_OFFSET 0x016 /* Half word */ ++#define SD_RSP0_OFFSET 0x01c ++#define SD_RSP1_OFFSET 0x020 ++#define SD_RSP2_OFFSET 0x024 ++#define SD_RSP3_OFFSET 0x028 ++#define SD_DATA_OFFSET 0x040 ++#define SD_STA_OFFSET 0x030 ++#define SD_HOST_OFFSET 0x02c /* Byte */ ++#define SD_PWR_OFFSET 0x02d /* Byte */ ++#define SD_GAP_OFFSET 0x02e /* Byte */ ++#define SD_WAK_OFFSET 0x02f /* Byte */ ++#define SD_CLK_OFFSET 0x01a /* Half word */ ++#define SD_TMO_OFFSET 0x018 /* Byte */ ++#define SD_RESET_OFFSET 0x019 /* Byte */ ++#define SD_NIS_OFFSET 0x012 /* Half word */ ++#define SD_EIS_OFFSET 0x014 /* Half word */ ++#define SD_NISEN_OFFSET 0x00e /* Half word */ ++#define SD_EISEN_OFFSET 0x010 /* Half word */ ++#define SD_NIXEN_OFFSET 0x006 /* Half word */ ++#define SD_EIXEN_OFFSET 0x008 /* Half word */ ++#define SD_AC12ES_OFFSET 0x03c /* Half word */ ++#define SD_CAP_OFFSET 0x038 ++#define SD_CUR_OFFSET 0x048 ++#define SD_ADMA_STA_OFFSET 0x054 ++#define SD_ADMA_ADDR_OFFSET 0x058 ++#define SD_XC_CTR_OFFSET 0x060 ++#define SD_BOOT_CTR_OFFSET 0x070 ++#define SD_BOOT_STA_OFFSET 0x074 ++#define SD_VOL_SW_OFFSET 0x07c ++#define SD_SIST_OFFSET 0x0fc /* Half word */ ++#define SD_VER_OFFSET 0x0fe /* Half word */ ++ ++#define SD_DMA_ADDR_REG SD_REG(SD_DMA_ADDR_OFFSET) ++#define SD_BLK_SZ_REG SD_REG(SD_BLK_SZ_OFFSET) /* Half word */ ++#define SD_BLK_CNT_REG SD_REG(SD_BLK_CNT_OFFSET) /* Half word */ ++#define SD_ARG_REG SD_REG(SD_ARG_OFFSET) ++#define SD_XFR_REG SD_REG(SD_XFR_OFFSET) /* Half word */ ++#define SD_CMD_REG SD_REG(SD_CMD_OFFSET) /* Half word */ ++#define SD_RSP0_REG SD_REG(SD_RSP0_OFFSET) ++#define SD_RSP1_REG SD_REG(SD_RSP1_OFFSET) ++#define SD_RSP2_REG SD_REG(SD_RSP2_OFFSET) ++#define SD_RSP3_REG SD_REG(SD_RSP3_OFFSET) ++#define SD_DATA_REG SD_REG(SD_DATA_OFFSET) ++#define SD_STA_REG SD_REG(SD_STA_OFFSET) ++#define SD_HOST_REG SD_REG(SD_HOST_OFFSET) /* Byte */ ++#define SD_PWR_REG SD_REG(SD_PWR_OFFSET) /* Byte */ ++#define SD_GAP_REG SD_REG(SD_GAP_OFFSET) /* Byte */ ++#define SD_WAK_REG SD_REG(SD_WAK_OFFSET) /* Byte */ ++#define SD_CLK_REG SD_REG(SD_CLK_OFFSET) /* Half word */ ++#define SD_TMO_REG SD_REG(SD_TMO_OFFSET) /* Byte */ ++#define SD_RESET_REG SD_REG(SD_RESET_OFFSET) /* Byte */ ++#define SD_NIS_REG SD_REG(SD_NIS_OFFSET) /* Half word */ ++#define SD_EIS_REG SD_REG(SD_EIS_OFFSET) /* Half word */ ++#define SD_NISEN_REG SD_REG(SD_NISEN_OFFSET) /* Half word */ ++#define SD_EISEN_REG SD_REG(SD_EISEN_OFFSET) /* Half word */ ++#define SD_NIXEN_REG SD_REG(SD_NIXEN_OFFSET) /* Half word */ ++#define SD_EIXEN_REG SD_REG(SD_EIXEN_OFFSET) /* Half word */ ++#define SD_AC12ES_REG SD_REG(SD_AC12ES_OFFSET) /* Half word */ ++#define SD_CAP_REG SD_REG(SD_CAP_OFFSET) ++#define SD_CUR_REG SD_REG(SD_CUR_OFFSET) ++#define SD_ADMA_STA_REG SD_REG(SD_ADMA_STA_OFFSET) ++#define SD_ADMA_ADDR_REG SD_REG(SD_ADMA_ADDR_OFFSET) ++#define SD_XC_CTR_REG SD_REG(SD_XC_CTR_OFFSET) ++#define SD_BOOT_CTR_REG SD_REG(SD_BOOT_CTR_OFFSET) ++#define SD_BOOT_STA_REG SD_REG(SD_BOOT_STA_OFFSET) ++#define SD_VOL_SW_REG SD_REG(SD_VOL_SW_OFFSET) ++#define SD_SIST_REG SD_REG(SD_SIST_OFFSET) /* Half word */ ++#define SD_VER_REG SD_REG(SD_VER_OFFSET) /* Half word */ ++ ++#ifdef CONFIG_GK710XS_SDIO2 ++#define SD1_DMA_ADDR_REG SD1_REG(SD_DMA_ADDR_OFFSET) ++#define SD1_BLK_SZ_REG SD1_REG(SD_BLK_SZ_OFFSET) /* Half word */ ++#define SD1_BLK_CNT_REG SD1_REG(SD_BLK_CNT_OFFSET) /* Half word */ ++#define SD1_ARG_REG SD1_REG(SD_ARG_OFFSET) ++#define SD1_XFR_REG SD1_REG(SD_XFR_OFFSET) /* Half word */ ++#define SD1_CMD_REG SD1_REG(SD_CMD_OFFSET) /* Half word */ ++#define SD1_RSP0_REG SD1_REG(SD_RSP0_OFFSET) ++#define SD1_RSP1_REG SD1_REG(SD_RSP1_OFFSET) ++#define SD1_RSP2_REG SD1_REG(SD_RSP2_OFFSET) ++#define SD1_RSP3_REG SD1_REG(SD_RSP3_OFFSET) ++#define SD1_DATA_REG SD1_REG(SD_DATA_OFFSET) ++#define SD1_STA_REG SD1_REG(SD_STA_OFFSET) ++#define SD1_HOST_REG SD1_REG(SD_HOST_OFFSET) /* Byte */ ++#define SD1_PWR_REG SD1_REG(SD_PWR_OFFSET) /* Byte */ ++#define SD1_GAP_REG SD1_REG(SD_GAP_OFFSET) /* Byte */ ++#define SD1_WAK_REG SD1_REG(SD_WAK_OFFSET) /* Byte */ ++#define SD1_CLK_REG SD1_REG(SD_CLK_OFFSET) /* Half word */ ++#define SD1_TMO_REG SD1_REG(SD_TMO_OFFSET) /* Byte */ ++#define SD1_RESET_REG SD1_REG(SD_RESET_OFFSET) /* Byte */ ++#define SD1_NIS_REG SD1_REG(SD_NIS_OFFSET) /* Half word */ ++#define SD1_EIS_REG SD1_REG(SD_EIS_OFFSET) /* Half word */ ++#define SD1_NISEN_REG SD1_REG(SD_NISEN_OFFSET) /* Half word */ ++#define SD1_EISEN_REG SD1_REG(SD_EISEN_OFFSET) /* Half word */ ++#define SD1_NIXEN_REG SD1_REG(SD_NIXEN_OFFSET) /* Half word */ ++#define SD1_EIXEN_REG SD1_REG(SD_EIXEN_OFFSET) /* Half word */ ++#define SD1_AC12ES_REG SD1_REG(SD_AC12ES_OFFSET) /* Half word */ ++#define SD1_CAP_REG SD1_REG(SD_CAP_OFFSET) ++#define SD1_CUR_REG SD1_REG(SD_CUR_OFFSET) ++#define SD1_ADMA_STA_REG SD1_REG(SD_ADMA_STA_OFFSET) ++#define SD1_ADMA_ADDR_REG SD1_REG(SD_ADMA_ADDR_OFFSET) ++#define SD1_XC_CTR_REG SD1_REG(SD_XC_CTR_OFFSET) ++#define SD1_BOOT_CTR_REG SD1_REG(SD_BOOT_CTR_OFFSET) ++#define SD1_BOOT_STA_REG SD1_REG(SD_BOOT_STA_OFFSET) ++#define SD1_VOL_SW_REG SD1_REG(SD_VOL_SW_OFFSET) ++#define SD1_SIST_REG SD1_REG(SD_SIST_OFFSET) /* Half word */ ++#define SD1_VER_REG SD1_REG(SD_VER_OFFSET) /* Half word */ ++#endif ++ ++/* SD_BLK_SZ_REG */ ++#define SD_BLK_SZ_4KB 0x0000 ++#define SD_BLK_SZ_8KB 0x1000 ++#define SD_BLK_SZ_16KB 0x2000 ++#define SD_BLK_SZ_32KB 0x3000 ++#define SD_BLK_SZ_64KB 0x4000 ++#define SD_BLK_SZ_128KB 0x5000 ++#define SD_BLK_SZ_256KB 0x6000 ++#define SD_BLK_SZ_512KB 0x7000 ++ ++/* SD_XFR_REG */ ++#if defined(CONFIG_ARCH_GK710XS) ++#define SD_XFR_MUL_SEL 0x0010 ++#define SD_XFR_SGL_SEL 0x0000 ++#define SD_XFR_CTH_SEL 0x0020 ++#else ++#define SD_XFR_MUL_SEL 0x0020 ++#define SD_XFR_SGL_SEL 0x0000 ++#define SD_XFR_CTH_SEL 0x0010 ++#endif ++#define SD_XFR_HTC_SEL 0x0000 ++#define SD_XFR_DMA_EN 0x0004 ++#define SD_XFR_AC12_EN 0x0002 ++#define SD_XFR_BLKCNT_EN 0x0001 ++ ++/* SD_CMD_REG */ ++#define SD_CMD_IDX(x) ((x) << 8) ++#define SD_CMD_NORMAL 0x00000000 ++#define SD_CMD_SUSPEND 0x00000040 ++#define SD_CMD_RESUME 0x00000080 ++#define SD_CMD_ABORT 0x000000C0 ++#define SD_CMD_CHKIDX 0x00000020 ++#define SD_CMD_DATA 0x00000010 ++#define SD_CMD_CHKCRC 0x00000008 ++ ++#define SD_CMD_RSP_NONE 0x00000000 ++#define SD_CMD_RSP_136 0x00000001 ++#define SD_CMD_RSP_48 0x00000002 ++#define SD_CMD_RSP_48BUSY 0x00000003 ++ ++/* SD_STA_REG */ ++#define SD_STA_DAT_LSL(x) ((((x) & 0x1e000000) >> 25) |(((x) & 0x00f00000) >> 20)) ++#define SD_STA_CMD_LSL(x) (((x) & 0x01000000) >> 24) ++#define SD_STA_WPS_PL 0x00080000 ++#define SD_STA_CSS 0x00040000 ++#define SD_STA_CDP_L 0x00020000 ++#define SD_STA_CARD_INSERTED 0x00010000 ++#define SD_STA_BUFFER_READ_EN 0x00000800 ++#define SD_STA_WRITE_XFR_ACTIVE 0x00000400 ++#define SD_STA_BUFFER_WRITE_EN 0x00000200 ++#define SD_STA_READ_XFR_ACTIVE 0x00000100 ++#define SD_STA_CMD_INHIBIT_DAT 0x00000004 ++#define SD_STA_DAT_ACTIVE 0x00000002 ++#define SD_STA_CMD_INHIBIT_CMD 0x00000001 ++ ++#define SD_STA_WRITABLE 0 ++#define SD_STA_READ_ONLY 1 ++ ++/* SD_HOST_REG */ ++#define SD_HOST_HIGH_SPEED 0x08 ++#define SD_HOST_8BIT 0x04 ++#define SD_HOST_4BIT 0x02 ++#define SD_HOST_LED_ON 0x01 ++ ++/* SD_PWR_REG */ ++#define SD_PWR_3_3V 0x0e ++#define SD_PWR_3_0V 0x0c ++#define SD_PWR_1_8V 0x0a ++#define SD_PWR_ON 0x01 ++#define SD_PWR_OFF 0x00 ++ ++/* SD_GAP_REG */ ++#define SD_GAP_INT_AT_GAP 0x08 ++#define SD_GAP_CONT_REQ 0x04 ++#define SD_GAP_READ_WAIT 0x02 ++#define SD_GAP_STOP_AT_GAP 0x01 ++ ++/* SD_WAK_REG */ ++#define SD_WAK_ON_CARD_RMV 0x04 ++#define SD_WAK_ON_CARD_INT 0x02 ++#define SD_WAK_ON_CARD_IST 0x01 ++ ++/* SD_CLK_REG */ ++#define SD_CLK_DIV_256 0x8000 ++#define SD_CLK_DIV_128 0x4000 ++#define SD_CLK_DIV_64 0x2000 ++#define SD_CLK_DIV_32 0x1000 ++#define SD_CLK_DIV_16 0x0800 ++#define SD_CLK_DIV_8 0x0400 ++#define SD_CLK_DIV_4 0x0200 ++#define SD_CLK_DIV_2 0x0100 ++#define SD_CLK_DIV_1 0x0000 ++#define SD_CLK_EN 0x0004 ++#define SD_CLK_ICLK_STABLE 0x0002 ++#define SD_CLK_ICLK_EN 0x0001 ++ ++/* SD_TMO_REG */ ++/* SD_RESET_REG */ ++#define SD_RESET_DAT 0x04 ++#define SD_RESET_ALL 0x02 ++#define SD_RESET_CMD 0x01 ++ ++/* SD_NIS_REG */ ++#define SD_NIS_ERROR 0x8000 ++#define SD_NIS_CARD 0x0100 ++#define SD_NIS_REMOVAL 0x0080 ++#define SD_NIS_READ_READY 0x0040 ++#define SD_NIS_INSERT 0x0020 ++#define SD_NIS_WRITE_READY 0x0010 ++#define SD_NIS_XFR_DONE 0x0008 ++#define SD_NIS_DMA 0x0004 ++#define SD_NIS_BLOCK_GAP 0x0002 ++#define SD_NIS_CMD_DONE 0x0001 ++ ++/* SD_EIS_REG */ ++#define SD_EIS_ACMD12_ERR 0x0100 ++#define SD_EIS_CURRENT_ERR 0x0080 ++#define SD_EIS_DATA_BIT_ERR 0x0040 ++#define SD_EIS_DATA_CRC_ERR 0x0020 ++#define SD_EIS_DATA_TMOUT_ERR 0x0010 ++#define SD_EIS_CMD_IDX_ERR 0x0008 ++#define SD_EIS_CMD_BIT_ERR 0x0004 ++#define SD_EIS_CMD_CRC_ERR 0x0002 ++#define SD_EIS_CMD_TMOUT_ERR 0x0001 ++ ++ ++/* SD_NISEN_REG */ ++#define SD_NISEN_CARD 0x0100 ++#define SD_NISEN_REMOVAL 0x0080 ++#define SD_NISEN_INSERT 0x0040 ++#define SD_NISEN_READ_READY 0x0020 ++#define SD_NISEN_WRITE_READY 0x0010 ++#define SD_NISEN_DMA 0x0008 ++#define SD_NISEN_BLOCK_GAP 0x0004 ++#define SD_NISEN_XFR_DONE 0x0002 ++#define SD_NISEN_CMD_DONE 0x0001 ++ ++/* SD_EISEN_REG */ ++#define SD_EISEN_ADMA_ERR 0x0200 ++#define SD_EISEN_ACMD12_ERR 0x0100 ++#define SD_EISEN_CURRENT_ERR 0x0080 ++#define SD_EISEN_DATA_BIT_ERR 0x0040 ++#define SD_EISEN_DATA_TMOUT_ERR 0x0020 ++#define SD_EISEN_DATA_CRC_ERR 0x0010 ++#define SD_EISEN_CMD_IDX_ERR 0x0008 ++#define SD_EISEN_CMD_CRC_ERR 0x0004 ++#define SD_EISEN_CMD_BIT_ERR 0x0002 ++#define SD_EISEN_CMD_TMOUT_ERR 0x0001 ++ ++/* SD_NIXEN_REG */ ++#define SD_NIXEN_CARD 0x0100 ++#define SD_NIXEN_REMOVAL 0x0080 ++#define SD_NIXEN_INSERT 0x0040 ++#define SD_NIXEN_READ_READY 0x0020 ++#define SD_NIXEN_WRITE_READY 0x0010 ++#define SD_NIXEN_DMA 0x0008 ++#define SD_NIXEN_BLOCK_GAP 0x0004 ++#define SD_NIXEN_XFR_DONE 0x0002 ++#define SD_NIXEN_CMD_DONE 0x0001 ++ ++/* SD_EIXEN_REG */ ++#define SD_EISEN_ADMA_ERR 0x0200 ++#define SD_EIXEN_ACMD12_ERR 0x0100 ++#define SD_EIXEN_CURRENT_ERR 0x0080 ++#define SD_EIXEN_DATA_BIT_ERR 0x0040 ++#define SD_EIXEN_DATA_CRC_ERR 0x0020 ++#define SD_EIXEN_CMD_CRC_ERR 0x0010 ++#define SD_EIXEN_DATA_TMOUT_ERR 0x0008 ++#define SD_EIXEN_CMD_IDX_ERR 0x0004 ++#define SD_EIXEN_CMD_BIT_ERR 0x0002 ++#define SD_EIXEN_CMD_TMOUT_ERR 0x0001 ++ ++/* SD_AC12ES_REG */ ++#define SD_AC12ES_NOT_ISSUED 0x0040 ++#define SD_AC12ES_INDEX 0x0020 ++#define SD_AC12ES_NOT_EXECED 0x0010 ++#define SD_AC12ES_END_BIT 0x0004 ++#define SD_AC12ES_CRC_ERROR 0x0002 ++#define SD_AC12ES_TMOUT_ERROR 0x0001 ++ ++/* SD_ADMA_STA_REG */ ++#define SD_ADMA_STA_ST_STOP 0x00000000 ++#define SD_ADMA_STA_ST_FDS 0x00000001 ++#define SD_ADMA_STA_ST_TFR 0x00000003 ++#define SD_ADMA_STA_LEN_ERR 0x00000004 ++ ++/* SD_CAP_REG */ ++#define SD_CAP_INTMODE 0x08000000 ++#define SD_CAP_VOL_1_8V 0x04000000 ++#define SD_CAP_VOL_3_0V 0x02000000 ++#define SD_CAP_VOL_3_3V 0x01000000 ++#define SD_CAP_DMA 0x00800000 ++#define SD_CAP_SUS_RES 0x00400000 ++#define SD_CAP_HIGH_SPEED 0x00200000 ++//#define SD_CAP_ADMA_SUPPORT 0x00080000 ++#define SD_CAP_MAX_512B_BLK 0x00000000 ++#define SD_CAP_MAX_1KB_BLK 0x00010000 ++#define SD_CAP_MAX_2KB_BLK 0x00020000 ++#define SD_CAP_BASE_FREQ(x) (((x) & 0x3f00) >> 8) ++#define SD_CAP_TOCLK_KHZ 0x00000000 ++#define SD_CAP_TOCLK_MHZ 0x00000080 ++#define SD_CAP_TOCLK_FREQ(x) (((x) & 0x3f)) ++ ++/* SD_XC_CTR_REG */ ++#define SD_XC_CTR_DDR_EN 0x00008000 ++#define SD_XC_CTR_VOL_1_8V 0x00000001 ++#define SD_XC_CTR_VOL_3_3V 0x00000000 ++ ++/* SD_BOOT_CTR_REG */ ++#define SD_BOOT_CTR_RST_EN 0x00010000 ++ ++/* SD_BOOT_STA_REG */ ++#define SD_BOOT_STA_END_ALT 0x01010000 ++#define SD_BOOT_STA_BOOT_RDY 0x00000001 ++ ++/* SD_VOL_SW_REG */ ++#define SD_VOL_SW_CMD_STAT_H 0x00010000 ++#define SD_VOL_SW_DAT_STAT_H 0x00000007 ++ ++/* SD_VER_REG */ ++#define SD_VER_VENDOR(x) ((x) >> 8) ++#define SD_VER_SPEC(x) ((x) & 0xf) ++ ++#if 0 ++#define REG_SDIO_SYSADDRREG SD_REG(SD_DMA_ADDR_OFFSET) /* read/write */ ++#define REG_SDIO_BLKCNTREG SD_REG(SD_BLK_CNT_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_BLKSZREG SD_REG(SD_BLK_SZ_OFFSET) /* read/write */ ++#define REG_SDIO_ARGREG SD_REG(SD_ARG_OFFSET) /* read/write */ ++#define REG_SDIO_TRANMODEREG SD_REG(SD_XFR_OFFSET) /* read/write */ ++#define REG_SDIO_CMDREG SD_REG(SD_CMD_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_RESP0REG SD_REG(SD_RSP0_OFFSET) /* read */ ++#define REG_SDIO_RESP1REG SD_REG(SD_RSP1_OFFSET) /* read */ ++#define REG_SDIO_RESP2REG SD_REG(SD_RSP2_OFFSET) /* read */ ++#define REG_SDIO_RESP3REG SD_REG(SD_RSP3_OFFSET) /* read */ ++#define REG_SDIO_BUFFERDATAPORTREG SD_REG(SD_DATA_OFFSET) /* read/write */ ++#define REG_SDIO_PRESENTSTATEREG SD_REG(SD_STA_OFFSET) /* read */ ++#define REG_SDIO_CONTROL00REG SD_REG(SD_HOST_OFFSET) /* read/write */ ++#define REG_SDIO_CONTROL010REG SD_REG(SD_TMO_OFFSET) /* read/write */ ++#define REG_SDIO_CONTROL011REG SD_REG(SD_CLK_OFFSET) /* read/write */ ++#define REG_SDIO_NORINTSTATUSREG SD_REG(SD_NIS_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_ERRINTSTATUSREG SD_REG(SD_EIS_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_NORINTSTATUSENREG SD_REG(SD_NISEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_ERRINTSTATUSENREG SD_REG(SD_EISEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_NORINTSIGENREG SD_REG(SD_NIXEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_ERRINTSIGENREG SD_REG(SD_EIXEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO_AUTOCMD12ERRSTATUSREG SD_REG(SD_AC12ES_OFFSET) /* read/write */ ++#define REG_SDIO_CAPREG SD_REG(SD_CAP_OFFSET) /* read */ ++#define REG_SDIO_MAXCURCAPREG SD_REG(SD_CUR_OFFSET) /* read/write */ ++#define REG_SDIO_SLOTINTSTATUSREG SD_REG(SD_SIST_OFFSET) /* read */ ++ ++#ifdef CONFIG_GK710XS_SDIO2 ++#define REG_SDIO1_SYSADDRREG SD1_REG(SD_DMA_ADDR_OFFSET) /* read/write */ ++#define REG_SDIO1_BLKCNTREG SD1_REG(SD_BLK_CNT_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_BLKSZREG SD1_REG(SD_BLK_SZ_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_ARGREG SD1_REG(SD_ARG_OFFSET) /* read/write */ ++#define REG_SDIO1_TRANMODEREG SD1_REG(SD_XFR_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_CMDREG SD1_REG(SD_CMD_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_RESP0REG SD1_REG(SD_RSP0_OFFSET) /* read */ ++#define REG_SDIO1_RESP1REG SD1_REG(SD_RSP1_OFFSET) /* read */ ++#define REG_SDIO1_RESP2REG SD1_REG(SD_RSP2_OFFSET) /* read */ ++#define REG_SDIO1_RESP3REG SD1_REG(SD_RSP3_OFFSET) /* read */ ++#define REG_SDIO1_BUFFERDATAPORTREG SD1_REG(SD_DATA_OFFSET) /* read/write */ ++#define REG_SDIO1_PRESENTSTATEREG SD1_REG(SD_STA_OFFSET) /* read */ ++#define REG_SDIO1_CONTROL00REG SD1_REG(SD_HOST_OFFSET) /* read/write */ ++#define REG_SDIO1_CONTROL010REG SD1_REG(SD_TMO_OFFSET) /* read/write */ ++#define REG_SDIO1_CONTROL011REG SD1_REG(SD_CLK_OFFSET) /* read/write */ ++#define REG_SDIO1_NORINTSTATUSREG SD1_REG(SD_NIS_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_ERRINTSTATUSREG SD1_REG(SD_EIS_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_NORINTSTATUSENREG SD1_REG(SD_NISEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_ERRINTSTATUSENREG SD1_REG(SD_EISEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_NORINTSIGENREG SD1_REG(SD_NIXEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_ERRINTSIGENREG SD1_REG(SD_EIXEN_OFFSET) /* read/write 16bit */ ++#define REG_SDIO1_AUTOCMD12ERRSTATUSREG SD1_REG(SD_AC12ES_OFFSET) /* read/write */ ++#define REG_SDIO1_CAPREG SD1_REG(SD_CAP_OFFSET) /* read */ ++#define REG_SDIO1_MAXCURCAPREG SD1_REG(SD_CUR_OFFSET) /* read/write */ ++#define REG_SDIO1_SLOTINTSTATUSREG SD1_REG(SD_SIST_OFFSET) /* read */ ++#endif ++#endif ++ ++#endif /* __MACH_GK_SD_H */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/spi.h b/arch/arm/mach-gk710xs/include/mach/spi.h +new file mode 100644 +index 00000000..66706e39 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/spi.h +@@ -0,0 +1,327 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/spi.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_GK_SPI_H ++#define __MACH_GK_SPI_H ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++#define SPI_MAX_SLAVE_ID 7 ++ ++#define SPI_SUPPORT_TISSP_NSM 1 ++ ++#define SPI_INSTANCES 2 ++#define SPI_AHB_INSTANCES 0 ++#define SPI_SUPPORT_TSSI_MODE 1 ++ ++ ++#define SPI_EN2_EN3_ENABLED_BY_HOST_ENA_REG 0 ++ ++#define SPI_EN2_ENABLED_BY_GPIO2_AFSEL_REG 0 ++ ++#define SPI_EN4_7_ENABLED_BY_GPIO1_AFSEL_REG 1 ++ ++#define SPI_SLAVE_INSTANCES 0 ++ ++#define SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY 0 ++#define SPI_SUPPORT_MASTER_DELAY_START_TIME 0 ++#define SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE 0 ++ ++#define SPI_EN2_EN3_ENABLED_BY_GPIO2_AFSEL_REG 0 ++ ++/* SPI_FIFO_SIZE */ ++#define SPI_DATA_FIFO_SIZE_16 0x10 ++#define SPI_DATA_FIFO_SIZE_32 0x20 ++#define SPI_DATA_FIFO_SIZE_64 0x40 ++#define SPI_DATA_FIFO_SIZE_128 0x80 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#if SSI_HAL_MODE ++#define SPI_CTRLR0_OFFSET 0x0c ++#define SPI_CTRLR1_OFFSET 0x10 ++#define SPI_SSIENR_OFFSET 0x08 ++#define SPI_MWCR_OFFSET 0x14 ++#define SPI_SER_OFFSET 0x60 ++#define SPI_BAUDR_OFFSET 0x18 ++#define SPI_TXFTLR_OFFSET 0x3c ++#define SPI_RXFTLR_OFFSET 0x48 ++#define SPI_TXFLR_OFFSET 0x40 ++#define SPI_RXFLR_OFFSET 0x4c ++#define SPI_SR_OFFSET 0x04 ++#define SPI_IMR_OFFSET 0x1c ++#define SPI_ISR_OFFSET 0x30 ++#define SPI_RISR_OFFSET 0x2c ++#define SPI_TXOICR_OFFSET 0x44 ++#define SPI_RXOICR_OFFSET 0x50 ++#define SPI_RXUICR_OFFSET 0x54 ++#define SPI_MSTICR_OFFSET 0x24 ++#define SPI_ICR_OFFSET 0x20 ++#if (SPI_AHB_INSTANCES >= 1) ++#define SPI_DMAC_OFFSET 0x28 ++#endif ++#define SPI_IDR_OFFSET 0x00 ++#define SPI_VERSION_ID_OFFSET 0x5c ++#define SPI_DR_OFFSET 0x38 ++ ++#if (SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY == 1) ++#define SPI_SSIENPOLR_OFFSET 0x260 ++#endif ++#if (SPI_SUPPORT_MASTER_DELAY_START_TIME == 1) ++#define SPI_SCLK_OUT_DLY_OFFSET 0x264 ++#endif ++#if (SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE == 1) ++#define SPI_START_BIT_OFFSET 0x268 ++#endif ++ ++#define TSSI_CTRL_OFFSET 0x04 ++#define TSSI_SSR_OFFSET 0x00 ++#define TSSI_INDEX_OFFSET 0x0c ++#define TSSI_DATA_OFFSET 0x08 ++#define TSSI_POLARITY_INVERT 0x10 ++ ++#else ++#define SPI_CTRLR0_OFFSET 0x00 ++#define SPI_CTRLR1_OFFSET 0x04 ++#define SPI_SSIENR_OFFSET 0x08 ++#define SPI_MWCR_OFFSET 0x0C ++#define SPI_SER_OFFSET 0x10 ++#define SPI_BAUDR_OFFSET 0x14 ++#define SPI_TXFTLR_OFFSET 0x18 ++#define SPI_RXFTLR_OFFSET 0x1C ++#define SPI_TXFLR_OFFSET 0x20 ++#define SPI_RXFLR_OFFSET 0x24 ++#define SPI_SR_OFFSET 0x28 ++#define SPI_IMR_OFFSET 0x2C ++#define SPI_ISR_OFFSET 0x30 ++#define SPI_RISR_OFFSET 0x34 ++#define SPI_TXOICR_OFFSET 0x38 ++#define SPI_RXOICR_OFFSET 0x3C ++#define SPI_RXUICR_OFFSET 0x40 ++#define SPI_MSTICR_OFFSET 0x44 ++#define SPI_ICR_OFFSET 0x48 ++#if (SPI_AHB_INSTANCES >= 1) ++#define SPI_DMAC_OFFSET 0x4C ++#endif ++#define SPI_IDR_OFFSET 0x58 ++#define SPI_VERSION_ID_OFFSET 0x5C ++#define SPI_DR_OFFSET 0x60 ++ ++#if (SPI_SUPPORT_MASTER_CHANGE_ENA_POLARITY == 1) ++#define SPI_SSIENPOLR_OFFSET 0x260 ++#endif ++#if (SPI_SUPPORT_MASTER_DELAY_START_TIME == 1) ++#define SPI_SCLK_OUT_DLY_OFFSET 0x264 ++#endif ++#if (SPI_SUPPORT_NSM_SHAKE_START_BIT_CHSANGE == 1) ++#define SPI_START_BIT_OFFSET 0x268 ++#endif ++ ++#define TSSI_CTRL_OFFSET 0x00 ++#define TSSI_SSR_OFFSET 0x04 ++#define TSSI_INDEX_OFFSET 0x08 ++#define TSSI_DATA_OFFSET 0x0C ++#define TSSI_POLARITY_INVERT 0x10 ++#endif ++ ++#define SPI_REG(x) (GK_VA_SSI1 + (x)) ++#define SPI2_REG(x) (GK_VA_SSI2 + (x)) ++#define TSSI_REG(x) (GK_VA_TSSI + (x)) ++ ++#define SPI_CTRLR0_REG SPI_REG(SPI_CTRLR0_OFFSET) ++#define SPI_CTRLR1_REG SPI_REG(SPI_CTRLR1_OFFSET) ++#define SPI_SSIENR_REG SPI_REG(SPI_SSIENR_OFFSET) ++#define SPI_MWCR_REG SPI_REG(SPI_MWCR_OFFSET) ++#define SPI_SER_REG SPI_REG(SPI_SER_OFFSET) ++#define SPI_BAUDR_REG SPI_REG(SPI_BAUDR_OFFSET) ++#define SPI_TXFTLR_REG SPI_REG(SPI_TXFTLR_OFFSET) ++#define SPI_RXFTLR_REG SPI_REG(SPI_RXFTLR_OFFSET) ++#define SPI_TXFLR_REG SPI_REG(SPI_TXFLR_OFFSET) ++#define SPI_RXFLR_REG SPI_REG(SPI_RXFLR_OFFSET) ++#define SPI_SR_REG SPI_REG(SPI_SR_OFFSET) ++#define SPI_IMR_REG SPI_REG(SPI_IMR_OFFSET) ++#define SPI_ISR_REG SPI_REG(SPI_ISR_OFFSET) ++#define SPI_RISR_REG SPI_REG(SPI_RISR_OFFSET) ++#define SPI_TXOICR_REG SPI_REG(SPI_TXOICR_OFFSET) ++#define SPI_RXOICR_REG SPI_REG(SPI_RXOICR_OFFSET) ++#define SPI_RXUICR_REG SPI_REG(SPI_RXUICR_OFFSET) ++#define SPI_MSTICR_REG SPI_REG(SPI_MSTICR_OFFSET) ++#define SPI_ICR_REG SPI_REG(SPI_ICR_OFFSET) ++#define SPI_IDR_REG SPI_REG(SPI_IDR_OFFSET) ++#define SPI_VERSION_ID_REG SPI_REG(SPI_VERSION_ID_OFFSET) ++#define SPI_DR_REG SPI_REG(SPI_DR_OFFSET) ++ ++#if (SPI_INSTANCES >= 2) ++#define SPI2_CTRLR0_REG SPI2_REG(SPI_CTRLR0_OFFSET) ++#define SPI2_CTRLR1_REG SPI2_REG(SPI_CTRLR1_OFFSET) ++#define SPI2_SSIENR_REG SPI2_REG(SPI_SSIENR_OFFSET) ++#define SPI2_MWCR_REG SPI2_REG(SPI_MWCR_OFFSET) ++#define SPI2_SER_REG SPI2_REG(SPI_SER_OFFSET) ++#define SPI2_BAUDR_REG SPI2_REG(SPI_BAUDR_OFFSET) ++#define SPI2_TXFTLR_REG SPI2_REG(SPI_TXFTLR_OFFSET) ++#define SPI2_RXFTLR_REG SPI2_REG(SPI_RXFTLR_OFFSET) ++#define SPI2_TXFLR_REG SPI2_REG(SPI_TXFLR_OFFSET) ++#define SPI2_RXFLR_REG SPI2_REG(SPI_RXFLR_OFFSET) ++#define SPI2_SR_REG SPI2_REG(SPI_SR_OFFSET) ++#define SPI2_IMR_REG SPI2_REG(SPI_IMR_OFFSET) ++#define SPI2_ISR_REG SPI2_REG(SPI_ISR_OFFSET) ++#define SPI2_RISR_REG SPI2_REG(SPI_RISR_OFFSET) ++#define SPI2_TXOICR_REG SPI2_REG(SPI_TXOICR_OFFSET) ++#define SPI2_RXOICR_REG SPI2_REG(SPI_RXOICR_OFFSET) ++#define SPI2_RXUICR_REG SPI2_REG(SPI_RXUICR_OFFSET) ++#define SPI2_MSTICR_REG SPI2_REG(SPI_MSTICR_OFFSET) ++#define SPI2_ICR_REG SPI2_REG(SPI_ICR_OFFSET) ++#define SPI2_IDR_REG SPI2_REG(SPI_IDR_OFFSET) ++#define SPI2_VERSION_ID_REG SPI2_REG(SPI_VERSION_ID_OFFSET) ++#define SPI2_DR_REG SPI2_REG(SPI_DR_OFFSET) ++#endif ++ ++#define TSSI_CTRL_REG TSSI_REG(TSSI_CTRL_OFFSET) ++#define TSSI_SSR_REG TSSI_REG(TSSI_SSR_OFFSET) ++#define TSSI_INDEX_REG TSSI_REG(TSSI_INDEX_OFFSET) ++#define TSSI_DATA_REG TSSI_REG(TSSI_DATA_OFFSET) ++#define TSSI_POLARITY_INVERT_REG TSSI_REG(TSSI_POLARITY_INVERT) ++ ++ ++#define SPI_MASTER_INSTANCES (SPI_INSTANCES + SPI_AHB_INSTANCES) ++ ++/* ==========================================================================*/ ++/* SPI rw mode */ ++#define SPI_WRITE_READ 0 ++#define SPI_WRITE_ONLY 1 ++#define SPI_READ_ONLY 2 ++ ++/* Tx FIFO empty interrupt mask */ ++#define SPI_TXEIS_MASK 0x00000001 ++#define SPI_TXOIS_MASK 0x00000002 ++ ++/* SPI Parameters */ ++#define SPI_DUMMY_DATA 0xffff ++#define MAX_QUERY_TIMES 10 ++ ++/* Default SPI settings */ ++#define SPI_MODE SPI_MODE_0 ++#define SPI_SCPOL 0 ++#define SPI_SCPH 0 ++#define SPI_FRF 0 ++#define SPI_CFS 0x0 ++#define SPI_DFS 0xf ++#define SPI_BAUD_RATE 200000 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_spi_hw_info { ++ int bus_id; ++ int cs_id; ++}; ++typedef struct gk_spi_hw_info gk_spi_hw_t; ++ ++struct gk_spi_cfg_info { ++ u8 spi_mode; ++ u8 cfs_dfs; ++ u8 cs_change; ++ u32 baud_rate; ++}; ++typedef struct gk_spi_cfg_info gk_spi_cfg_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *buffer; ++ u16 n_size; ++} gk_spi_write_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *buffer; ++ u16 n_size; ++} gk_spi_read_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *w_buffer; ++ u8 *r_buffer; ++ u16 w_size; ++ u16 r_size; ++} gk_spi_write_then_read_t; ++ ++typedef struct { ++ u8 bus_id; ++ u8 cs_id; ++ u8 *w_buffer; ++ u8 *r_buffer; ++ u16 n_size; ++} gk_spi_write_and_read_t; ++ ++struct gk_spi_cs_config { ++ u8 bus_id; ++ u8 cs_id; ++ u8 cs_num; ++ int *cs_pins; ++}; ++ ++struct gk_spi_platform_info { ++ int support_dma; ++ int fifo_entries; ++ int cs_num; ++ int *cs_pins; ++ void (*cs_activate) (struct gk_spi_cs_config *); ++ void (*cs_deactivate)(struct gk_spi_cs_config *); ++ void (*rct_set_ssi_pll)(void); ++ u32 (*get_ssi_freq_hz)(void); ++}; ++#define GK_SPI_PARAM_CALL(id, arg, perm) \ ++ module_param_cb(spi##id##_cs0, ¶m_ops_int, &(arg[0]), perm); \ ++ module_param_cb(spi##id##_cs1, ¶m_ops_int, &(arg[1]), perm); \ ++ module_param_cb(spi##id##_cs2, ¶m_ops_int, &(arg[2]), perm); \ ++ module_param_cb(spi##id##_cs3, ¶m_ops_int, &(arg[3]), perm); \ ++ module_param_cb(spi##id##_cs4, ¶m_ops_int, &(arg[4]), perm); \ ++ module_param_cb(spi##id##_cs5, ¶m_ops_int, &(arg[5]), perm); \ ++ module_param_cb(spi##id##_cs6, ¶m_ops_int, &(arg[6]), perm); \ ++ module_param_cb(spi##id##_cs7, ¶m_ops_int, &(arg[7]), perm) ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_spi0; ++extern struct platform_device gk_spi1; ++extern struct platform_device gk_spi2; ++extern struct platform_device gk_spi3; ++extern struct platform_device gk_spi4; ++extern struct platform_device gk_spi_slave; ++ ++/* ==========================================================================*/ ++extern int gk_spi_write(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_t *spi_write); ++extern int gk_spi_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_read_t *spi_read); ++extern int gk_spi_write_then_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_then_read_t *spi_write_then_read); ++extern int gk_spi_write_and_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_and_read_t *spi_write_and_read); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/timer.h b/arch/arm/mach-gk710xs/include/mach/timer.h +new file mode 100644 +index 00000000..fa099e1b +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/timer.h +@@ -0,0 +1,100 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/timer.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_TIMER_H__ ++#define __MACH_TIMER_H__ ++ ++#include ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++#define INTERVAL_TIMER_INSTANCES 3 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++#define TIMER_BASE GK_VA_TIMER ++#define TIMER_REG(x) (GK_VA_TIMER + (x)) ++ ++#define TIMER_CTR_OFFSET 0x0c ++ ++#define TIMER1_STATUS_OFFSET 0x00 ++#define TIMER1_MATCH1_OFFSET 0x04 ++#define TIMER1_MATCH2_OFFSET 0x08 ++ ++#define TIMER2_STATUS_OFFSET 0x14 ++#define TIMER2_MATCH1_OFFSET 0x18 ++#define TIMER2_MATCH2_OFFSET 0x1c ++ ++#define TIMER3_STATUS_OFFSET 0x20 ++#define TIMER3_MATCH1_OFFSET 0x24 ++#define TIMER3_MATCH2_OFFSET 0x28 ++ ++#define TIMER1_RELOAD_OFFSET 0x30 ++#define TIMER2_RELOAD_OFFSET 0x34 ++#define TIMER3_RELOAD_OFFSET 0x38 ++ ++#define TIMER1_STATUS_REG TIMER_REG(TIMER1_STATUS_OFFSET) ++#define TIMER1_RELOAD_REG TIMER_REG(TIMER1_RELOAD_OFFSET) ++#define TIMER1_MATCH1_REG TIMER_REG(TIMER1_MATCH1_OFFSET) ++#define TIMER1_MATCH2_REG TIMER_REG(TIMER1_MATCH2_OFFSET) ++#define TIMER2_STATUS_REG TIMER_REG(TIMER2_STATUS_OFFSET) ++#define TIMER2_RELOAD_REG TIMER_REG(TIMER2_RELOAD_OFFSET) ++#define TIMER2_MATCH1_REG TIMER_REG(TIMER2_MATCH1_OFFSET) ++#define TIMER2_MATCH2_REG TIMER_REG(TIMER2_MATCH2_OFFSET) ++#define TIMER3_STATUS_REG TIMER_REG(TIMER3_STATUS_OFFSET) ++#define TIMER3_RELOAD_REG TIMER_REG(TIMER3_RELOAD_OFFSET) ++#define TIMER3_MATCH1_REG TIMER_REG(TIMER3_MATCH1_OFFSET) ++#define TIMER3_MATCH2_REG TIMER_REG(TIMER3_MATCH2_OFFSET) ++ ++#define TIMER_CTR_REG TIMER_REG(TIMER_CTR_OFFSET) ++ ++ ++/* Bit field definition of timer control register */ ++#define TIMER_CTR_EN1 0x00000400 ++#define TIMER_CTR_EN2 0x00000200 ++#define TIMER_CTR_EN3 0x00000100 ++ ++#define TIMER_CTR_CSL1 0x00000004 ++#define TIMER_CTR_CSL2 0x00000002 ++#define TIMER_CTR_CSL3 0x00000001 ++ ++#define TIMER_CTR_OF1 0x00000040 ++#define TIMER_CTR_OF2 0x00000020 ++#define TIMER_CTR_OF3 0x00000010 ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern struct sys_timer gk_sys_timer; ++extern int gk_init_timer(void) __init; ++ ++extern int get_hwtimer_output_ticks(u64 *out_tick); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +diff --git a/arch/arm/mach-gk710xs/include/mach/timex.h b/arch/arm/mach-gk710xs/include/mach/timex.h +new file mode 100644 +index 00000000..326a719c +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/timex.h +@@ -0,0 +1,26 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/timex.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_TIMEX_H ++#define __MACH_TIMEX_H ++ ++ ++#define CLOCK_TICK_RATE 15000000 //unit:100Hz 18MHz ++ ++ ++#endif /* __MACH_TIMEX_H */ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/uart.h b/arch/arm/mach-gk710xs/include/mach/uart.h +new file mode 100644 +index 00000000..d286b801 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/uart.h +@@ -0,0 +1,316 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/mach/uart.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_UART_H_ ++#define __MACH_UART_H_ ++ ++#include ++#include ++ ++//#define KE_DEBUG ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++ ++#define UART_BASE_FREQ (get_uart_freq_hz()) ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++#define UART_INSTANCES 3 ++ ++#define UART0_VA_ADDR (GK_VA_UART0) ++#define UART0_PA_ADDR (GK_PA_UART0) ++ ++#if (UART_INSTANCES >= 2) ++#define UART1_VA_ADDR (GK_VA_UART1) ++#define UART1_PA_ADDR (GK_PA_UART1) ++#endif ++ ++#if (UART_INSTANCES >= 3) ++#define UART2_VA_ADDR (GK_VA_UART2) ++#define UART2_PA_ADDR (GK_PA_UART2) ++#endif ++ ++#if (UART_INSTANCES >= 4) ++#define UART3_VA_ADDR (GK_VA_UART3) ++#define UART3_PA_ADDR (GK_PA_UART3) ++#endif ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define UART0_REG(x) (GK_VA_UART0 + (x)) ++ ++#if (UART_INSTANCES >= 2) ++#define UART1_REG(x) (GK_VA_UART1 + (x)) ++#endif ++ ++#if (UART_INSTANCES >= 3) ++#define UART2_REG(x) (GK_VA_UART2 + (x)) ++#endif ++ ++#if (UART_INSTANCES >= 4) ++#define UART3_REG(x) (GK_VA_UART3 + (x)) ++#endif ++ ++#define UART_RB_OFFSET 0x04 ++#define UART_TH_OFFSET 0x04 ++#define UART_DLL_OFFSET 0x04 ++#define UART_IE_OFFSET 0x00 ++#define UART_DLH_OFFSET 0x00 ++#define UART_II_OFFSET 0x08 ++#define UART_FC_OFFSET 0x08 ++#define UART_LC_OFFSET 0x18 ++#define UART_MC_OFFSET 0x0c ++#define UART_LS_OFFSET 0x14 ++#define UART_MS_OFFSET 0x10 ++#define UART_SC_OFFSET 0x1c /* Byte */ ++#define UART_SRR_OFFSET 0x88 ++ ++#define UART0_RB_REG UART0_REG(UART_RB_OFFSET) ++#define UART0_TH_REG UART0_REG(UART_TH_OFFSET) ++#define UART0_DLL_REG UART0_REG(UART_DLL_OFFSET) ++#define UART0_IE_REG UART0_REG(UART_IE_OFFSET) ++#define UART0_DLH_REG UART0_REG(UART_DLH_OFFSET) ++#define UART0_II_REG UART0_REG(UART_II_OFFSET) ++#define UART0_FC_REG UART0_REG(UART_FC_OFFSET) ++#define UART0_LC_REG UART0_REG(UART_LC_OFFSET) ++#define UART0_MC_REG UART0_REG(UART_MC_OFFSET) ++#define UART0_LS_REG UART0_REG(UART_LS_OFFSET) ++#define UART0_MS_REG UART0_REG(UART_MS_OFFSET) ++#define UART0_SC_REG UART0_REG(UART_SC_OFFSET) /* Byte */ ++ ++#if (UART_INSTANCES >= 2) ++ ++#define UART1_RB_REG UART1_REG(UART_RB_OFFSET) ++#define UART1_TH_REG UART1_REG(UART_TH_OFFSET) ++#define UART1_DLL_REG UART1_REG(UART_DLL_OFFSET) ++#define UART1_IE_REG UART1_REG(UART_IE_OFFSET) ++#define UART1_DLH_REG UART1_REG(UART_DLH_OFFSET) ++#define UART1_II_REG UART1_REG(UART_II_OFFSET) ++#define UART1_FC_REG UART1_REG(UART_FC_OFFSET) ++#define UART1_LC_REG UART1_REG(UART_LC_OFFSET) ++#define UART1_MC_REG UART1_REG(UART_MC_OFFSET) ++#define UART1_LS_REG UART1_REG(UART_LS_OFFSET) ++#define UART1_MS_REG UART1_REG(UART_MS_OFFSET) ++#define UART1_SC_REG UART1_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 2 */ ++ ++#if (UART_INSTANCES >= 3) ++ ++#define UART2_RB_REG UART2_REG(UART_RB_OFFSET) ++#define UART2_TH_REG UART2_REG(UART_TH_OFFSET) ++#define UART2_DLL_REG UART2_REG(UART_DLL_OFFSET) ++#define UART2_IE_REG UART2_REG(UART_IE_OFFSET) ++#define UART2_DLH_REG UART2_REG(UART_DLH_OFFSET) ++#define UART2_II_REG UART2_REG(UART_II_OFFSET) ++#define UART2_FC_REG UART2_REG(UART_FC_OFFSET) ++#define UART2_LC_REG UART2_REG(UART_LC_OFFSET) ++#define UART2_MC_REG UART2_REG(UART_MC_OFFSET) ++#define UART2_LS_REG UART2_REG(UART_LS_OFFSET) ++#define UART2_MS_REG UART2_REG(UART_MS_OFFSET) ++#define UART2_SC_REG UART2_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 3 */ ++ ++#if (UART_INSTANCES >= 4) ++ ++#define UART3_RB_REG UART3_REG(UART_RB_OFFSET) ++#define UART3_TH_REG UART3_REG(UART_TH_OFFSET) ++#define UART3_DLL_REG UART3_REG(UART_DLL_OFFSET) ++#define UART3_IE_REG UART3_REG(UART_IE_OFFSET) ++#define UART3_DLH_REG UART3_REG(UART_DLH_OFFSET) ++#define UART3_II_REG UART3_REG(UART_II_OFFSET) ++#define UART3_FC_REG UART3_REG(UART_FC_OFFSET) ++#define UART3_LC_REG UART3_REG(UART_LC_OFFSET) ++#define UART3_MC_REG UART3_REG(UART_MC_OFFSET) ++#define UART3_LS_REG UART3_REG(UART_LS_OFFSET) ++#define UART3_MS_REG UART3_REG(UART_MS_OFFSET) ++#define UART3_SC_REG UART3_REG(UART_SC_OFFSET) /* Byte */ ++ ++#endif /* UART_INSTANCES >= 4 */ ++ ++/* UART[x]_IE_REG */ ++#define UART_IE_PTIME 0x80 ++#define UART_IE_ETOI 0x20 ++#define UART_IE_EBDI 0x10 ++#define UART_IE_EDSSI 0x08 ++#define UART_IE_ELSI 0x04 ++#define UART_IE_ETBEI 0x02 ++#define UART_IE_ERBFI 0x01 ++ ++/* UART[x]_II_REG */ ++#define UART_II_MODEM_STATUS_CHANGED 0x00 ++#define UART_II_NO_INT_PENDING 0x01 ++#define UART_II_THR_EMPTY 0x02 ++#define UART_II_RCV_DATA_AVAIL 0x04 ++#define UART_II_RCV_STATUS 0x06 ++#define UART_II_CHAR_TIMEOUT 0x0c ++ ++/* UART[x]_FC_REG */ ++#define UART_FC_RX_ONECHAR 0x00 ++#define UART_FC_RX_QUARTER_FULL 0x40 ++#define UART_FC_RX_HALF_FULL 0x80 ++#define UART_FC_RX_2_TO_FULL 0xc0 ++#define UART_FC_TX_EMPTY 0x00 ++#define UART_FC_TX_2_IN_FIFO 0x10 ++#define UART_FC_TX_QUATER_IN_FIFO 0x20 ++#define UART_FC_TX_HALF_IN_FIFO 0x30 ++#define UART_FC_XMITR 0x04 ++#define UART_FC_RCVRR 0x02 ++#define UART_FC_FIFOE 0x01 ++ ++/* UART[x]_LC_REG */ ++#define UART_LC_BRK 0x80 ++ ++#define UART_LC_EVEN_PARITY 0x40 ++#define UART_LC_ODD_PARITY 0x00 ++ ++#define UART_LC_STICKY_PARITY 0x20 ++#define UART_LC_DLAB 0x10 ++ ++#define UART_LC_STOP_2BIT 0x08 ++#define UART_LC_STOP_1BIT 0x00 ++ ++#define UART_LC_PEN 0x04 ++#define UART_LC_CLS_8_BITS 0x03 ++#define UART_LC_CLS_7_BITS 0x02 ++#define UART_LC_CLS_6_BITS 0x01 ++#define UART_LC_CLS_5_BITS 0x00 ++ ++/* quick defs */ ++#define UART_LC_8N1 0x03 ++#define UART_LC_7E1 0x0a ++ ++/* UART[x]_MC_REG */ ++#define UART_MC_LB 0x40 ++#define UART_MC_AFCE 0x20 ++#define UART_MC_SIRE 0x10 ++#define UART_MC_RTS 0x08 ++#define UART_MC_DTR 0x04 ++#define UART_MC_OUT2 0x02 ++#define UART_MC_OUT1 0x01 ++ ++/* UART[x]_LS_REG */ ++#define UART_LS_FERR 0x80 ++ ++#define UART_LS_TEMT 0x40 ++#define UART_LS_BI 0x20 ++#define UART_LS_FE 0x10 ++#define UART_LS_THRE 0x08 ++ ++#define UART_LS_DR 0x04 ++#define UART_LS_PE 0x02 ++#define UART_LS_OE 0x01 ++ ++/* UART[x]_MS_REG */ ++#define UART_MS_DCD 0x80 ++#define UART_MS_DCTS 0x40 ++#define UART_MS_CTS 0x20 ++#define UART_MS_DDCD 0x10 ++#define UART_MS_DSR 0x08 ++#define UART_MS_DDSR 0x04 ++#define UART_MS_TERI 0x02 ++#define UART_MS_RI 0x01 ++ ++/* Other defs for UART */ ++#define RECV_BUF_SIZ 1500 ++#define SEND_BUF_SIZ 1500 ++ ++/* ==========================================================================*/ ++#define UART_FIFO_SIZE (16) ++ ++#define DEFAULT_UART_MCR (0) ++#define DEFAULT_UART_IER (UART_IE_ELSI | UART_IE_ERBFI) ++#define DEFAULT_UART_FCR (UART_FC_FIFOE | UART_FC_RX_2_TO_FULL | UART_FC_TX_EMPTY) ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifndef __ASSEMBLER__ ++ ++struct gk_uart_port_info ++{ ++ void *port; //struct uart_port * ++ u32 mcr; ++ u32 fcr; ++ u32 ier; ++ u32 tx_fifo_fix; ++ ++ void (*stop_tx)(unsigned char __iomem *membase); ++ void (*set_pll)(void); ++ u32 (*get_pll)(void); ++ u32 (*get_ms)(unsigned char __iomem *membase); ++}; ++ ++struct gk_uart_platform_info ++{ ++ int total_port_num; ++ int registed_port_num; ++ ++ struct gk_uart_port_info port[UART_INSTANCES]; ++}; ++ ++extern struct gk_uart_platform_info gk_uart_ports; ++ ++#ifdef KE_DEBUG ++extern void after_print(const char *str, ...); ++#endif ++ ++/* ==========================================================================*/ ++#endif /* __ASSEMBLER__ */ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __MACH_UART_H_ */ +diff --git a/arch/arm/mach-gk710xs/include/mach/uncompress.h b/arch/arm/mach-gk710xs/include/mach/uncompress.h +new file mode 100644 +index 00000000..cfa8cc09 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/uncompress.h +@@ -0,0 +1,76 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/uncompress.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_UNCOMPRESS_H ++#define __MACH_UNCOMPRESS_H ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++#include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++typedef void* (*hal_function_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) ; ++ ++struct hw_ops *g_hw; ++ ++#define PA_UART0 GK_PA_UART0 ++ ++#define UART_LS_REG ((PA_UART0 + UART_LS_OFFSET)) ++#define UART_TH_REG ((PA_UART0 + UART_TH_OFFSET)) ++#define UART_RB_REG ((PA_UART0 + UART_RB_OFFSET)) ++#define UART_SRR_REG ((PA_UART0 + UART_SRR_OFFSET)) ++ ++#define UART_LC_REG ((PA_UART0 + UART_LC_OFFSET)) ++#define UART_DLL_REG ((PA_UART0 + UART_DLL_OFFSET)) ++#define UART_DLH_REG ((PA_UART0 + UART_DLH_OFFSET)) ++ ++/* ==========================================================================*/ ++ ++static inline void putc(int c) ++{ ++ while (!(gk_uart_readl(UART_LS_REG) & UART_LS_TEMT)); ++ gk_uart_writel(UART_TH_REG, c); ++} ++ ++static inline void flush(void) ++{ ++ unsigned int dump; ++ ++ while (gk_uart_readl(UART_LS_REG) & UART_LS_DR) ++ { ++ dump = gk_uart_readl(UART_RB_REG); ++ } ++} ++ ++static inline void arch_decomp_setup(void) ++{ ++ hal_function_t hal_init = (hal_function_t) (*(volatile u32 *)CONFIG_U2K_HAL_ADDR); ++ g_hw = (struct hw_ops *)hal_init (0, 0, 0x90000000, 0xa0000000, 0); ++} ++ ++ ++#define arch_decomp_wdog() ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif /* __MACH_UNCOMPRESS_H */ +diff --git a/arch/arm/mach-gk710xs/include/mach/vmalloc.h b/arch/arm/mach-gk710xs/include/mach/vmalloc.h +new file mode 100644 +index 00000000..5a0f541f +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/vmalloc.h +@@ -0,0 +1,37 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/vmalloc.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_VMALLOC_H ++#define __MACH_VMALLOC_H ++ ++/* ==========================================================================*/ ++#if defined(CONFIG_VMSPLIT_3G) ++#define VMALLOC_END UL(0xe0000000) ++#else ++#define VMALLOC_END UL(0xb0000000) ++#endif ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++/* ==========================================================================*/ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/vo_i80.h b/arch/arm/mach-gk710xs/include/mach/vo_i80.h +new file mode 100644 +index 00000000..e4d07221 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/vo_i80.h +@@ -0,0 +1,79 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/vo_i80.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_VO_I80_H ++#define __MACH_V0_I80_H ++ ++#include ++ ++#define VO_I80_BASE (GK_VA_VO) ++#define VO_I80_REG(x) (VO_I80_BASE + (x)) ++ ++#define REG_VO_I80_DATA_FORMAT VO_I80_REG(0xC00) /* read/write */ ++#define REG_VO_I80_PIC_RESOLUTION VO_I80_REG(0xC04) /* read/write */ ++#define REG_VO_I80_PIXEL_RDWRCMD VO_I80_REG(0xC08) /* read/write */ ++#define REG_VO_I80_CMD_FORMAT VO_I80_REG(0xC0C) /* read/write */ ++#define REG_VO_I80_LCD_RST_PARA1 VO_I80_REG(0xC10) /* read/write */ ++#define REG_VO_I80_LCD_RST_PARA2 VO_I80_REG(0xC14) /* read/write */ ++#define REG_VO_I80_DELAY_PARA VO_I80_REG(0xC18) /* read/write */ ++#define REG_VO_I80_TWR_TIMING VO_I80_REG(0xC1C) /* read/write */ ++#define REG_VO_I80_TRD_TIMING VO_I80_REG(0xC20) /* read/write */ ++#define REG_VO_I80_TCS_TIMING VO_I80_REG(0xC24) /* read/write */ ++#define REG_VO_I80_POLAR_CTRL VO_I80_REG(0xC28) /* read/write */ ++#define REG_VO_I80_CTRL VO_I80_REG(0xC2C) /* read/write */ ++#define REG_VO_I80_FRAME_COUNTER VO_I80_REG(0xC30) /* read */ ++#define REG_VO_I80_I80_STATE VO_I80_REG(0xC34) /* read */ ++#define REG_VO_I80_CMD_SRAM_STATE VO_I80_REG(0xC38) /* read/write */ ++#define REG_VO_I80_TCSREF_WT_TIMING VO_I80_REG(0xC3C) /* read/write */ ++#define REG_VO_I80_TCSREF_RD_TIMING VO_I80_REG(0xC40) /* read/write */ ++#define REG_VO_I80_TODH_TIMING VO_I80_REG(0xC44) /* read/write */ ++#define REG_VO_I80_LCD_STATE VO_I80_REG(0xC48) /* read */ ++#define REG_VO_I80_LCD_STATE0 VO_I80_REG(0xC4C) /* read */ ++#define REG_VO_I80_LCD_STATE1 VO_I80_REG(0xC50) /* read */ ++#define REG_VO_I80_LCD_STATE2 VO_I80_REG(0xC54) /* read */ ++#define REG_VO_I80_LCD_STATE3 VO_I80_REG(0xC58) /* read */ ++#define REG_VO_I80_LCD_STATE4 VO_I80_REG(0xC5C) /* read */ ++#define REG_VO_I80_SRAM_CMDPARA VO_I80_REG(0xC80) /* read/write */ ++ ++ ++ ++#define I80_DESIGN_REF_CLK_FREQ 200//MHz GK7101S-->200MHz GK8601-->300MHz ++ ++#define I80_CLK_FREQ 200//MHz GK7101S: FPGA-->100MHz IC-->200MHz ++#define I80_CLK_PERIOD (1000/I80_CLK_FREQ)//FPGA-->10ns/Cycle IC-->5ns/cycle ++ ++#define MAX_RESET_1ST_H_L_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(100*I80_CLK_FREQ) )//FPGA-->40ms IC-->20ms ++#define MAX_RESET_2ND_H_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(10*I80_CLK_FREQ) ) //FPGA-->409ms IC-->204ms ++#define MAX_DELAY_MS ( ((1<<11)-1)*I80_DESIGN_REF_CLK_FREQ/(10*I80_CLK_FREQ) ) //FPGA-->409ms IC-->204ms ++//#define MAX_TRANS_NS ((1<<9)-1)*I80_CLK_PERIOD //FPGA-->5110ns IC-->2555ns ++//#define MAX_TAS_NS ((1<<6)-1)*I80_CLK_PERIOD //FPGA-->630ns IC-->315ns ++ ++#define TIMING_PARA_CEIL_NS(x) (((x)*I80_CLK_FREQ+999)/1000) ++ ++#define I80_1ST_H_L_COUNTER (10*I80_DESIGN_REF_CLK_FREQ) ++#define I80_2ND_H_COUNTER (100*I80_DESIGN_REF_CLK_FREQ) ++#define I80_HW_DELAY_COUNTER (100*I80_DESIGN_REF_CLK_FREQ) ++ ++#define TIMING_PARA_FIRST_H_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_1ST_H_L_COUNTER-1)/I80_1ST_H_L_COUNTER) ++#define TIMING_PARA_FIRST_L_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_1ST_H_L_COUNTER-1)/I80_1ST_H_L_COUNTER) ++#define TIMING_PARA_SECOND_H_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_2ND_H_COUNTER-1)/I80_2ND_H_COUNTER) ++#define TIMING_PARA_HW_DELAY_CEIL_MS(x) ((1000*I80_CLK_FREQ*(x)+I80_HW_DELAY_COUNTER-1)/I80_HW_DELAY_COUNTER) ++ ++ ++#endif /* __MACH_VO_I80_H */ ++ ++ +diff --git a/arch/arm/mach-gk710xs/include/mach/wdt.h b/arch/arm/mach-gk710xs/include/mach/wdt.h +new file mode 100644 +index 00000000..96be7d71 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/include/mach/wdt.h +@@ -0,0 +1,77 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/include/mach/wdt.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __MACH_WDT_H ++#define __MACH_WDT_H ++ ++/* ==============================================*/ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++/* On A5S WDT_RST_L_REG can not be cleared. */ ++/* When is more then 0xff. To work around we set */ ++/* WDT_RST_L_REG to 0x0 before WDT start because */ ++/* it is preserved during soft reset, if it's */ ++/* still 0x0 we could know the reset is from WDT */ ++ ++#define RCT_WDT_RESET_VAL 0 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#define WDOG_REG(x) (GK_VA_WDT + (x)) ++ ++#define WDOG_STATUS_OFFSET 0x0c ++#define WDOG_RELOAD_OFFSET 0x10 ++#define WDOG_RESTART_OFFSET 0x14 ++#define WDOG_CONTROL_OFFSET 0x00 ++#define WDOG_TIMEOUT_OFFSET 0x04 ++#define WDOG_CLR_TMO_OFFSET 0x08 ++#define WDOG_RST_WD_OFFSET 0x18 ++ ++#define WDOG_STATUS_REG WDOG_REG(WDOG_STATUS_OFFSET) ++#define WDOG_RELOAD_REG WDOG_REG(WDOG_RELOAD_OFFSET) ++#define WDOG_RESTART_REG WDOG_REG(WDOG_RESTART_OFFSET) ++#define WDOG_CONTROL_REG WDOG_REG(WDOG_CONTROL_OFFSET) ++#define WDOG_TIMEOUT_REG WDOG_REG(WDOG_TIMEOUT_OFFSET) ++#define WDOG_CLR_TMO_REG WDOG_REG(WDOG_CLR_TMO_OFFSET) ++#define WDOG_RST_WD_REG WDOG_REG(WDOG_RST_WD_OFFSET) ++ ++/* Bit field definition of watch dog timer control register */ ++#define WDOG_CTR_RST_EN 0x00000004 ++#define WDOG_CTR_INT_EN 0x00000002 ++#define WDOG_CTR_EN 0x00000001 ++ ++/* WDOG_RESTART_REG only works with magic 0x4755. */ ++/* Set this value would transferred the value in */ ++/* WDOG_RELOAD_REG into WDOG_STATUS_REG and would */ ++/* not trigger the underflow event. */ ++#define WDT_RESTART_VAL 0X4755 ++ ++/* ==============================================*/ ++#ifndef __ASSEMBLER__ ++ ++extern struct platform_device gk_wdt; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==============================================*/ ++ ++#endif /* __REGS_WDT_H */ ++ +diff --git a/arch/arm/mach-gk710xs/irq.c b/arch/arm/mach-gk710xs/irq.c +new file mode 100644 +index 00000000..d70f61dc +--- /dev/null ++++ b/arch/arm/mach-gk710xs/irq.c +@@ -0,0 +1,410 @@ ++/* ++ * arch/arm/mach-gk/irq.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_ARM_VIC ++#include ++#endif ++ ++/** ++ * struct vic_device - VIC PM device ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ * @domain: The IRQ domain for the VIC. ++ */ ++struct gk_vic_device { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++ struct irq_domain *domain; ++}; ++ ++/* ==========================================================================*/ ++ ++/* we cannot allocate memory when VICs are initially registered */ ++static struct gk_vic_device gk_vic_decs[VIC_INSTANCES]; ++ ++static int gk_vic_id; ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++#define GK_GPIO_IRQ2GIRQ() do { \ ++ girq -= GPIO_IRQ(0); \ ++ } while (0) ++ ++ ++/* ==========================================================================*/ ++#if (VIC_INSTANCES == 1) ++#define GK_VIC_IRQ2BASE() do { \ ++ irq -= VIC1_INT_VEC(0); \ ++ } while (0) ++#elif (VIC_INSTANCES == 2) ++#define GK_VIC_IRQ2BASE() do { \ ++ irq -= VIC1_INT_VEC(0); \ ++ if (irq >= NR_VIC_IRQ_SIZE) { \ ++ irq -= NR_VIC_IRQ_SIZE; \ ++ vic_base = VIC2_BASE; \ ++ } \ ++ } while (0) ++#endif ++ ++static void gk_ack_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_EDGE_CLR_OFFSET, 0x1 << irq); ++} ++ ++static void gk_disable_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_CLR_OFFSET, 0x1 << irq); ++} ++ ++static void gk_enable_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_OFFSET, 0x1 << irq); ++} ++ ++static void gk_mask_ack_irq(struct irq_data *d) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 irq = d->irq; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_INTEN_CLR_OFFSET, 0x1 << irq); ++ gk_irq_writel(vic_base + VIC_EDGE_CLR_OFFSET, 0x1 << irq); ++} ++ ++static int gk_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ u32 vic_base = VIC1_BASE; ++ u32 mask; ++ u32 bit; ++ u32 sense; ++ u32 bothedges; ++ u32 event; ++ struct irq_desc *desc = irq_to_desc(d->irq); ++ u32 irq = d->irq; ++ ++ //printk("%s: irq[%d] type[%d] desc[%p]\n", __func__, irq, type, desc); ++ ++ GK_VIC_IRQ2BASE(); ++ ++ mask = ~(0x1 << irq); ++ bit = (0x1 << irq); ++ sense = gk_irq_readl(vic_base + VIC_SENSE_OFFSET); ++ bothedges = gk_irq_readl(vic_base + VIC_BOTHEDGE_OFFSET); ++ event = gk_irq_readl(vic_base + VIC_EVENT_OFFSET); ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_RISING: ++ sense &= mask; ++ bothedges &= mask; ++ event |= bit; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ sense &= mask; ++ bothedges &= mask; ++ event &= mask; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ sense &= mask; ++ bothedges |= bit; ++ event &= mask; ++ desc->handle_irq = handle_edge_irq; ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ sense |= bit; ++ bothedges &= mask; ++ event |= bit; ++ desc->handle_irq = handle_level_irq; ++ break; ++ case IRQ_TYPE_LEVEL_LOW: ++ sense |= bit; ++ bothedges &= mask; ++ event &= mask; ++ desc->handle_irq = handle_level_irq; ++ break; ++ default: ++ pr_err("%s: can't set irq type %d for irq 0x%08x@%d\n", ++ __func__, type, vic_base, irq); ++ return -EINVAL; ++ } ++ ++ gk_irq_writel(vic_base + VIC_SENSE_OFFSET, sense); ++ gk_irq_writel(vic_base + VIC_BOTHEDGE_OFFSET, bothedges); ++ gk_irq_writel(vic_base + VIC_EVENT_OFFSET, event); ++ ++ gk_ack_irq(d); ++ ++ return 0; ++} ++ ++static struct irq_chip gk_irq_chip = { ++ .name = "gk irq", ++ .irq_ack = gk_ack_irq, ++ .irq_mask = gk_disable_irq, ++ .irq_unmask = gk_enable_irq, ++ .irq_mask_ack = gk_mask_ack_irq, ++ .irq_set_type = gk_irq_set_type, ++}; ++ ++void gk_swvic_set(u32 irq) ++{ ++ u32 vic_base = VIC1_BASE; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_SOFTEN_OFFSET, 0x1 << irq); ++} ++EXPORT_SYMBOL(gk_swvic_set); ++ ++void gk_swvic_clr(u32 irq) ++{ ++ u32 vic_base = VIC1_BASE; ++ ++ GK_VIC_IRQ2BASE(); ++ ++ gk_irq_writel(vic_base + VIC_SOFTEN_CLR_OFFSET, 0x1 << irq); ++} ++EXPORT_SYMBOL(gk_swvic_clr); ++ ++/* ==========================================================================*/ ++static inline u32 gk_irq_stat2nr(u32 stat) ++{ ++ u32 tmp; ++ u32 nr; ++ ++ __asm__ __volatile__ ++ ("rsbs %[tmp], %[stat], #0" : ++ [tmp] "=r" (tmp) : [stat] "r" (stat)); ++ __asm__ __volatile__ ++ ("and %[nr], %[tmp], %[stat]" : ++ [nr] "=r" (nr) : [tmp] "r" (tmp), [stat] "r" (stat)); ++ __asm__ __volatile__ ++ ("clzcc %[nr], %[nr]" : ++ [nr] "+r" (nr)); ++ __asm__ __volatile__ ++ ("rsc %[nr], %[nr], #32" : ++ [nr] "+r" (nr)); ++ ++ return nr; ++} ++ ++/* ==========================================================================*/ ++ ++u32 vic_base_addr[VIC_INSTANCES] = { ++ VIC1_BASE, ++#if (VIC_INSTANCES >= 2) ++ VIC2_BASE, ++#endif ++#if (VIC_INSTANCES >= 3) ++ VIC3_BASE, ++#endif ++#if (VIC_INSTANCES >= 4) ++ VIC4_BASE, ++#endif ++}; ++ ++#ifndef CONFIG_ARM_VIC ++ ++/** ++ * gk_vic_register() - Register a VIC. ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * @node: The device tree node associated with the VIC. ++ * ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ * ++ * This also configures the IRQ domain for the VIC. ++ */ ++static void __init gk_vic_register(void __iomem *base, unsigned int irq, ++ u32 resume_sources, struct device_node *node) ++{ ++ struct gk_vic_device *pVic; ++ ++ if (gk_vic_id >= ARRAY_SIZE(gk_vic_decs)) ++ { ++ printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); ++ return; ++ } ++ ++ pVic = &gk_vic_decs[gk_vic_id]; ++ pVic->base = base; ++ pVic->resume_sources = resume_sources; ++ pVic->irq = irq; ++ gk_vic_id++; ++ pVic->domain = irq_domain_add_legacy(node, NR_VIC_IRQ_SIZE, irq, 0, ++ &irq_domain_simple_ops, pVic); ++} ++ ++void __init gk_init_vic(u32 num_vic) ++{ ++ int irq, i; ++ ++ printk("gk init vic...\n"); ++ for (i = 0; i < NR_IRQS; i++) ++ { ++ //pr_err("registering irq %d \n", i); ++ irq_set_chip_and_handler(i, &gk_irq_chip, handle_level_irq); ++ set_irq_flags(i, IRQF_VALID); ++ } ++ ++ /* initialize the VICs */ ++ for (irq = 0; irq < num_vic; irq++) ++ { ++ gk_vic_register((void __iomem *)vic_base_addr[irq], (NR_VIC_IRQ_SIZE * irq), 0, NULL); ++ } ++} ++ ++/* ++ * Handle each interrupt in a single VIC. Returns non-zero if we've ++ * handled at least one interrupt. This reads the status register ++ * before handling each interrupt, which is necessary given that ++ * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. ++ */ ++static int gk_handle_one_vic(struct gk_vic_device *vic, struct pt_regs *regs) ++{ ++ u32 stat, irq; ++ int handled = 0; ++ ++ while ((stat = readl_relaxed(vic->base + VIC_IRQ_STA_OFFSET))) { ++ irq = ffs(stat) - 1; ++ handle_IRQ(irq_find_mapping(vic->domain, irq), regs); ++ handled = 1; ++ } ++ ++ return handled; ++} ++ ++/* ++ * Keep iterating over all registered VIC's until there are no pending ++ * interrupts. ++ */ ++asmlinkage void __exception_irq_entry gk_vic_handle_irq(struct pt_regs *regs) ++{ ++ int i, handled; ++ do { ++ for (i = 0, handled = 0; i < gk_vic_id; ++i) ++ handled |= gk_handle_one_vic(&gk_vic_decs[i], regs); ++ } while (handled); ++} ++ ++#else ++ ++void __init gk_init_vic(u32 num_vic) ++{ ++ u32 vic[] = {~0, ~0, ~0}; ++ int irq; ++ ++printk("gk init vic...\n"); ++ /* initialize the VICs */ ++ for (irq = 0; irq < num_vic; irq++) ++ { ++ vic_init(vic_base_addr[irq], (NR_VIC_IRQ_SIZE * irq), vic[irq], 0); ++ } ++} ++ ++#endif ++ ++void __init gk_init_irq(void) ++{ ++ ++#ifndef CONFIG_ARM_VIC ++ printk(">> gk init irq vic1...\n"); ++ /* Set VIC sense and event type for each entry ++ * note: we initialize udc vbus irq type here */ ++ gk_irq_writel(VIC_SENSE_REG, 0x00000000); ++ gk_irq_writel(VIC_BOTHEDGE_REG, 0x00000000); ++ gk_irq_writel(VIC_EVENT_REG, 0x00000000); ++ ++#if (VIC_INSTANCES >= 2) ++ printk(">> gk init irq vic2...\n"); ++ gk_irq_writel(VIC2_SENSE_REG, 0x00000000); ++ gk_irq_writel(VIC2_BOTHEDGE_REG, 0x00000000); ++ gk_irq_writel(VIC2_EVENT_REG, 0x00000000); ++#endif ++ ++ /* Disable all IRQ */ ++ gk_irq_writel(VIC_INT_SEL_REG, 0x00000000); ++ gk_irq_writel(VIC_INTEN_REG, 0x00000000); ++ gk_irq_writel(VIC_INTEN_CLR_REG, 0xffffffff); ++ gk_irq_writel(VIC_EDGE_CLR_REG, 0xffffffff); ++ ++#if (VIC_INSTANCES >= 2) ++ gk_irq_writel(VIC2_INT_SEL_REG, 0x00000000); ++ gk_irq_writel(VIC2_INTEN_REG, 0x00000000); ++ gk_irq_writel(VIC2_INTEN_CLR_REG, 0xffffffff); ++ gk_irq_writel(VIC2_EDGE_CLR_REG, 0xffffffff); ++#endif ++#endif ++ ++ gk_init_vic(VIC_INSTANCES); ++ ++} ++ +diff --git a/arch/arm/mach-gk710xs/mach-gk710xs.c b/arch/arm/mach-gk710xs/mach-gk710xs.c +new file mode 100644 +index 00000000..4e6e9779 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/mach-gk710xs.c +@@ -0,0 +1,1026 @@ ++/* ++ * linux/arch/arm/mach-gk/mach-gk.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++ ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern struct platform_device gk_fb0; ++extern struct platform_device gk_fb1; ++extern int gk_init_fb(void); ++ ++extern struct platform_device gk_sd0; ++ ++extern struct i2c_board_info gk_board_vi_infos[2]; ++extern struct i2c_board_info gk_board_hdmi_infos[2]; ++ ++//u64 gk_dmamask = DMA_BIT_MASK(32); ++//EXPORT_SYMBOL(gk_dmamask); ++ ++/* ==========================================================================*/ ++ ++#if defined(CONFIG_MTD_SFLASH_GOKE) || defined(CONFIG_MTD_SFLASH_GOKE_MODULE) ++//add: ++//#if defined(CONFIG_MACH_GK7102S_ELEC_SC1135_V1_00) ++//MACHINE_START(GK7102S_ELEC_SC1135_V1_00,"ELEC GK7102S V1 Board") ++//#endif ++ ++ ++#if defined(CONFIG_ONLY_USE_NOR_8M) ++#define GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET \ ++ (0) ++#define GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE \ ++ (256 * 1024) ++ ++#define GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET \ ++ (GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET \ ++ + GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE) ++#define GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE \ ++ (64 * 1024) ++ ++#define GKAPP_MTDBLOCK2_USER_OFFSET \ ++ (GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET \ ++ + GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE) ++#define GKAPP_MTDBLOCK2_USER_SIZE \ ++ (128 * 1024) ++ ++#define GKAPP_MTDBLOCK3_CUSTOM_OFFSET \ ++ (GKAPP_MTDBLOCK2_USER_OFFSET \ ++ + GKAPP_MTDBLOCK2_USER_SIZE) ++#define GKAPP_MTDBLOCK3_CUSTOM_SIZE \ ++ (512 * 1024) ++ ++#define GKAPP_MTDBLOCK4_KERNEL_OFFSET \ ++ (GKAPP_MTDBLOCK3_CUSTOM_OFFSET \ ++ + GKAPP_MTDBLOCK3_CUSTOM_SIZE) ++#define GKAPP_MTDBLOCK4_KERNEL_SIZE \ ++ ((1024 + 320) * 1024) ++ ++#define GKAPP_MTDBLOCK5_ROOTFS_OFFSET \ ++ (GKAPP_MTDBLOCK4_KERNEL_OFFSET \ ++ + GKAPP_MTDBLOCK4_KERNEL_SIZE) ++#define GKAPP_MTDBLOCK5_ROOTFS_SIZE \ ++ ((4096 + 0) * 1024) ++ ++#define GKAPP_MTDBLOCK6_RESOURCE_OFFSET \ ++ (GKAPP_MTDBLOCK5_ROOTFS_OFFSET \ ++ + GKAPP_MTDBLOCK5_ROOTFS_SIZE) ++#define GKAPP_MTDBLOCK6_RESOURCE_SIZE \ ++ ((1024 + 704 + 64) * 1024) ++ ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++#if 0 ++ [0] = { ++ .name = "uboot", ++ .offset = GKAPP_MTDBLOCK0_UBOOT_BIN_OFFSET, ++ .size = GKAPP_MTDBLOCK0_UBOOT_BIN_SIZE, ++ }, ++ [1] = { ++ .name = "uboot_env", ++ .offset = GKAPP_MTDBLOCK1_UBOOT_ENV_OFFSET, ++ .size = GKAPP_MTDBLOCK1_UBOOT_ENV_SIZE, ++ }, ++ [2] = {/* for usrm of Juan */ ++ .name = "user", ++ .offset = GKAPP_MTDBLOCK2_USER_OFFSET, ++ .size = GKAPP_MTDBLOCK2_USER_SIZE, ++ }, ++ [3] = {/* mount custom.jffs2 /media/conf */ ++ .name = "conf", ++ .offset = GKAPP_MTDBLOCK3_CUSTOM_OFFSET, ++ .size = GKAPP_MTDBLOCK3_CUSTOM_SIZE, ++ }, ++ [4] = { ++ .name = "kernel", ++ .offset = GKAPP_MTDBLOCK4_KERNEL_OFFSET, ++ .size = GKAPP_MTDBLOCK4_KERNEL_SIZE, ++ }, ++ [5] = {/* ro squashfs rootfs */ ++ .name = "rootfs", ++ .offset = GKAPP_MTDBLOCK5_ROOTFS_OFFSET, ++ .size = GKAPP_MTDBLOCK5_ROOTFS_SIZE, ++ }, ++ [6] = {/* mount font&web squashfs to /media/custom */ ++ .name = "resource", ++ .offset = GKAPP_MTDBLOCK6_RESOURCE_OFFSET, ++ .size = GKAPP_MTDBLOCK6_RESOURCE_SIZE, ++ }, ++#else ++#if 1//defined(CONFIG_MACH_GK7102_HZD_OJTV_v10_JXH42) || defined(CONFIG_MACH_GK_HZD_OJTV_v10_OV2710) ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //128k ++ [2] = { ++ .name = "user", ++ .offset = 0x00050000, ++ .size = 0x00020000, ++ }, ++ //448k ++ [3] = { ++ .name = "config", ++ .offset = 0x00070000, ++ .size = 0x00070000, ++ }, ++ //1344k ++ [4] = { ++ .name = "kernel", ++ .offset = 0x000e0000, ++ .size = 0x001A0000, ++ }, ++ //4M ++ [5] = { ++ .name = "rootfs", ++ .offset = 0x00280000, ++ .size = 0x003b0000, ++ }, ++ //1856k ++ [6] = { ++ .name = "resource", ++ .offset = 0x00630000, ++ .size = 0x001d0000, ++ }, ++ //ALL 0--8M ++ [7] = { ++ .name = "all", ++ .offset = 0x00000000, ++ .size = 0x00800000, ++ }, ++#else ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //128k ++ [2] = { ++ .name = "user", ++ .offset = 0x00050000, ++ .size = 0x00020000, ++ }, ++ //448k ++ [3] = { ++ .name = "config", ++ .offset = 0x00070000, ++ .size = 0x00070000, ++ }, ++ //1344k ++ [4] = { ++ .name = "kernel", ++ .offset = 0x000e0000, ++ .size = 0x00150000, ++ }, ++ //4M ++ [5] = { ++ .name = "rootfs", ++ .offset = 0x00230000, ++ .size = 0x00400000, ++ }, ++ //1856k ++ [6] = { ++ .name = "resource", ++ .offset = 0x00630000, ++ .size = 0x001d0000, ++ }, ++ //ALL 0--8M ++ [7] = { ++ .name = "all", ++ .offset = 0x00000000, ++ .size = 0x00800000, ++ }, ++ #endif ++#endif ++}; ++#elif defined(CONFIG_ONLY_USE_NOR_16M) ++// for 16M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ // 2M ++ [2] = { ++ .name = "kernel", ++ .offset = 0x00050000, ++ .size = 0x00200000, ++ }, ++ //13M + 512K ++ [3] = { ++ .name = "rootfs", ++ .offset = 0x00250000, ++ .size = 0x00DB0000, ++ }, ++ ++}; ++#elif defined(CONFIG_ONLY_USE_NOR_32M) ++// for 32M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //256K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //768K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x000c0000, ++ }, ++ // 2.5M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x00110000, ++ .size = 0x00280000, ++ }, ++ //27M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00390000, ++ .size = 0x01b00000, ++ }, ++ // 1.5M ++ [5] = { ++ .name = "resource", ++ .offset = 0x01e90000, ++ .size = 0x00170000, ++ }, ++}; ++#elif defined(CONFIG_USE_NOR_AND_NAND) ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //192K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //512K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x00080000, ++ }, ++ // 1.25M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x000D0000, ++ .size = 0x00140000, ++ }, ++ //5M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00210000, ++ .size = 0x00500000, ++ }, ++ // 1M ++ [5] = { ++ .name = "resource", ++ .offset = 0x00710000, ++ .size = 0x000E0000, ++ }, ++}; ++#elif defined(CONFIG_ONLY_USE_NAND) ++// for 8M nor flash ++static struct mtd_partition gk_flash_parts[]= ++{ ++ //192K ++ [0] = { ++ .name = "uboot", ++ .offset = 0x00000000, ++ .size = 0x00040000, ++ }, ++ //64K ++ [1] = { ++ .name = "ubootenv", ++ .offset = 0x00040000, ++ .size = 0x00010000, ++ }, ++ //512K ++ [2] = { ++ .name = "config", ++ .offset = 0x00050000, ++ .size = 0x00080000, ++ }, ++ // 1.25M ++ [3] = { ++ .name = "kernel", ++ .offset = 0x000D0000, ++ .size = 0x00140000, ++ }, ++ //5M ++ [4] = { ++ .name = "rootfs", ++ .offset = 0x00210000, ++ .size = 0x00500000, ++ }, ++ // 1M ++ [5] = { ++ .name = "resource", ++ .offset = 0x00710000, ++ .size = 0x000E0000, ++ }, ++}; ++#else ++ ++#endif ++ ++static struct sflash_platform_data flash_platform_data = ++{ ++ .speed_mode = (uint32_t)SYSTEM_SFLASH_FREQ, ++ .channel = 0, ++ .nr_parts = ARRAY_SIZE(gk_flash_parts), ++ .parts = gk_flash_parts, ++}; ++ ++static struct platform_device gk_flash_device0 = ++{ ++ .name = "gk_flash", ++ .id = 0, ++ .dev = ++ { ++ .platform_data = &flash_platform_data, ++ }, ++}; ++#endif/*defined(CONFIG_MTD_GK_SFLASH) || defined(CONFIG_MTD_GK_SFLASH_MODULE)*/ ++ ++/* ================ Watch Dog Timer ======================*/ ++#ifdef CONFIG_WATCHDOG_GOKE ++static struct resource gk_wdt_resource[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_WDT, SZ_4K), ++ [1] = DEFINE_RES_IRQ(WDT_IRQ), ++}; ++ ++struct platform_device gk_wdt = { ++ .name = "gk-wdt", ++ .id = -1, ++ .resource = gk_wdt_resource, ++ .num_resources = ARRAY_SIZE(gk_wdt_resource), ++ .dev = { ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif /* CONFIG_WATCHDOG_GOKE */ ++/* ================= End ======================*/ ++ ++/* ================ Inter Integrated Circuit ===================*/ ++ ++#ifdef CONFIG_I2C_GOKE ++static struct resource gk_idc_resources[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_IDC, SZ_4K), ++ [1] = DEFINE_RES_IRQ(IDC_IRQ), ++}; ++ ++struct gk_platform_i2c gk_idc_platform_info = { ++ .clk_limit = 400000, ++ .bulk_write_num = 60, ++ .get_clock = get_apb_bus_freq_hz, ++}; ++IDC_PARAM_CALL(0, gk_idc_platform_info, 0644); ++ ++struct platform_device gk_idc = { ++ .name = "i2c", ++ .id = 0, ++ .resource = gk_idc_resources, ++ .num_resources = ARRAY_SIZE(gk_idc_resources), ++ .dev = { ++ .platform_data = &gk_idc_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++#if (IDC_INSTANCES >= 2) ++static struct resource gk_idc_hdmi_resources[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_IDC2, SZ_4K), ++ [1] = DEFINE_RES_IRQ(IDC_HDMI_IRQ), ++}; ++ ++struct gk_platform_i2c gk_idc_hdmi_platform_info = { ++ .clk_limit = 400000, ++ .bulk_write_num = 60, ++ .i2c_class = I2C_CLASS_DDC, ++ .get_clock = get_apb_bus_freq_hz, ++}; ++IDC_PARAM_CALL(1, gk_idc_hdmi_platform_info, 0644); ++ ++struct platform_device gk_idc_hdmi = { ++ .name = "i2c", ++ .id = 1, ++ .resource = gk_idc_hdmi_resources, ++ .num_resources = ARRAY_SIZE(gk_idc_hdmi_resources), ++ .dev = { ++ .platform_data = &gk_idc_hdmi_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++#endif ++ ++#ifdef CONFIG_SPI_GOKE ++/* ==========================================================================*/ ++void gk_spi_cs_activate(struct gk_spi_cs_config *cs_config) ++{ ++ u8 cs_pin; ++ ++ if (cs_config->bus_id >= SPI_MASTER_INSTANCES || ++ cs_config->cs_id >= cs_config->cs_num) ++ return; ++ cs_pin = cs_config->cs_pins[cs_config->cs_id]; ++ gk_gpio_set_out(cs_pin, 0); ++} ++ ++void gk_spi_cs_deactivate(struct gk_spi_cs_config *cs_config) ++{ ++ u8 cs_pin; ++ ++ if (cs_config->bus_id >= SPI_MASTER_INSTANCES || ++ cs_config->cs_id >= cs_config->cs_num) ++ return; ++ ++ cs_pin = cs_config->cs_pins[cs_config->cs_id]; ++ gk_gpio_set_out(cs_pin, 1); ++} ++ ++struct resource gk_spi0_resources[] = { ++ [0] = { ++ .start = GK_VA_SSI1, ++ .end = GK_VA_SSI1 + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SSI_IRQ, ++ .end = SSI_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++int gk_spi0_cs_pins[] = {-1, -1, -1, -1, -1, -1, -1, -1}; ++GK_SPI_PARAM_CALL(0, gk_spi0_cs_pins, 0644); ++struct gk_spi_platform_info gk_spi0_platform_info = { ++ .support_dma = 0, ++#if (SPI_MASTER_INSTANCES == 5 ) ++ .fifo_entries = 64, ++#else ++ .fifo_entries = 16, ++#endif ++ .cs_num = ARRAY_SIZE(gk_spi0_cs_pins), ++ .cs_pins = gk_spi0_cs_pins, ++ .cs_activate = gk_spi_cs_activate, ++ .cs_deactivate = gk_spi_cs_deactivate, ++// .rct_set_ssi_pll = rct_set_ssi_pll, ++ .get_ssi_freq_hz = get_ssi0_freq_hz, ++}; ++ ++struct platform_device gk_spi0 = { ++ .name = "spi", ++ .id = 0, ++ .resource = gk_spi0_resources, ++ .num_resources = ARRAY_SIZE(gk_spi0_resources), ++ .dev = { ++ .platform_data = &gk_spi0_platform_info, ++ //.dma_mask = &gk_dmamask, ++ //.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++#if (SPI_MASTER_INSTANCES >= 2 ) ++struct resource gk_spi1_resources[] = { ++ [0] = { ++ .start = GK_VA_SSI2, ++ .end = GK_VA_SSI2 + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SSI2_IRQ, ++ .end = SSI2_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++int gk_spi1_cs_pins[] = {-1, -1, -1, -1, -1, -1, -1, -1}; ++GK_SPI_PARAM_CALL(1, gk_spi1_cs_pins, 0644); ++struct gk_spi_platform_info gk_spi1_platform_info = { ++ .support_dma = 0, ++ .fifo_entries = 16, ++ .cs_num = ARRAY_SIZE(gk_spi1_cs_pins), ++ .cs_pins = gk_spi1_cs_pins, ++ .cs_activate = gk_spi_cs_activate, ++ .cs_deactivate = gk_spi_cs_deactivate, ++ .get_ssi_freq_hz = get_ssi1_freq_hz, ++}; ++ ++struct platform_device gk_spi1 = { ++ .name = "spi", ++ .id = 1, ++ .resource = gk_spi1_resources, ++ .num_resources = ARRAY_SIZE(gk_spi1_resources), ++ .dev = { ++ .platform_data = &gk_spi1_platform_info, ++ //.dma_mask = &gk_dmamask, ++ //.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++#endif ++static struct spi_board_info gk_spi_devices[] = { ++ { ++#ifdef CONFIG_MMC_SPI ++ .modalias = "mmc_spi", ++ .max_speed_hz = 69000000/4, /* max spi clock (SCK) speed in HZ */ ++ .bus_num = 0, ++ .mode = SPI_MODE_3, ++ //.platform_data = &bfin_mmc_spi_pdata, ++ //.controller_data = &mmc_spi_chip_info, ++#else ++ .modalias = "spidev", ++#endif ++ .bus_num = 0, ++ .chip_select = 0, ++ }, ++#if (SPI_INSTANCES >= 2) ++ { ++ .modalias = "spidev", ++ .bus_num = 1, ++ .chip_select = 0, ++ } ++#endif ++}; ++ ++/* ================= rtc ======================*/ ++struct platform_device gk_rtc = { ++ .name = "gk-rtc", ++ .id = -1, ++}; ++/* ================= End ======================*/ ++ ++/* ================= ir ======================*/ ++ ++struct gk_ir_controller gk_platform_ir_controller0 = { ++ ++ .protocol = GK_IR_PROTOCOL_NEC, ++ .debug = 0, ++}; ++GK_IR_PARAM_CALL(gk_platform_ir_controller0, 0644); ++ ++struct platform_device gk_ir = { ++ .name = "ir", ++ .id = 1, ++ .dev = { ++ .platform_data = &gk_platform_ir_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ ++/* ================= pcm/i2s ======================*/ ++ ++struct platform_device gk_pcm0 = { ++ .name = "gk-pcm-audio", ++ .id = -1, ++}; ++ ++static struct resource gk_i2s0_resources[] = { ++ [0] = { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = I2STX_IRQ, ++ .end = I2SRX_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct gk_i2s_controller gk_i2s_controller0 = { ++ .aucodec_digitalio_0 = NULL, ++ .aucodec_digitalio_1 = NULL, ++ .aucodec_digitalio_2 = NULL, ++ .channel_select = NULL, ++ .set_audio_pll = NULL, ++}; ++ ++ ++struct platform_device gk_i2s0 = { ++ .name = "gk-i2s", ++ .id = 0, ++ .resource = gk_i2s0_resources, ++ .num_resources = ARRAY_SIZE(gk_i2s0_resources), ++ .dev = { ++ .platform_data = &gk_i2s_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++/* ================= musb ====================*/ ++static struct musb_hdrc_config gk_musb_config = { ++ .multipoint = 1, ++ .dyn_fifo = 0, ++ .big_endian = 0, ++ .dma = 0, ++ .num_eps = 8, ++ .ram_bits = 12, ++}; ++ ++static struct musb_hdrc_platform_data gk_musb_data = { ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ .mode = MUSB_HOST, ++#elif defined(CONFIG_GK_USB_SLAVE_MODE) ++ .mode = MUSB_PERIPHERAL, ++#elif defined(CONFIG_GK_USB_OTG_MODE) ++ .mode = MUSB_HOST, ++#endif ++ .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */ ++ .config = &gk_musb_config, ++}; ++ ++static struct resource gk_musb_resources[] = { ++ /* Order is significant! The start/end fields ++ * are updated during setup.. ++ */ ++ [0] = { ++ .start = GK_VA_USB, ++ .end = GK_VA_USB + 0x2000, ++ .flags = IORESOURCE_MEM, ++ }, ++/* ++ [1] = { ++ .start = GK_VA_USB_PHY, ++ .end = GK_VA_USB_PHY + 0xa00, ++ .flags = IORESOURCE_MEM, ++ }, ++*/ ++ [1] = { ++ .start = USBC_IRQ, ++ .end = USBC_IRQ, ++ .flags = IORESOURCE_IRQ, ++ .name = "mc", ++ }, ++}; ++ ++ ++static struct platform_device gk_musb = { ++ .name = "musb-gk", ++ .id = -1, ++ .dev = { ++ .platform_data = &gk_musb_data, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .num_resources = ARRAY_SIZE(gk_musb_resources), ++ .resource = gk_musb_resources, ++}; ++ ++ ++/* ================= End ======================*/ ++unsigned int gk_aud_get_dma_offset(void) ++{ ++ return AUDIO_DMA_REG_OFFSET; ++} ++EXPORT_SYMBOL(gk_aud_get_dma_offset); ++ ++ ++static struct platform_device *gk_devices[] __initdata = { ++ ++#ifdef CONFIG_MMC_GOKE ++#ifndef CONFIG_PHY_USE_SD_CLK ++ &gk_sd0, ++#ifdef CONFIG_GK710XS_SDIO2 ++ &gk_sd1, ++#endif ++#endif ++#endif ++#ifdef CONFIG_WATCHDOG_GOKE ++ &gk_wdt, ++#endif ++#ifdef CONFIG_I2C_GOKE ++ &gk_idc, ++#if (IDC_INSTANCES >= 2) ++ &gk_idc_hdmi, ++#endif ++#endif ++ ++#ifdef CONFIG_FB_GOKE ++ &gk_fb0, ++ &gk_fb1, ++#endif ++#ifdef CONFIG_SPI_GOKE ++ &gk_spi0, ++#if (SPI_MASTER_INSTANCES >= 2 ) ++ &gk_spi1, ++#endif ++#endif ++#ifdef CONFIG_RTC_DRV_GOKE ++ &gk_rtc, ++#endif ++#ifdef CONFIG_INPUT_GOKE_IR ++ &gk_ir, ++#endif ++ ++#ifdef CONFIG_ETH_GOKE ++ &gk_eth0, ++#endif ++ //&gk_pcm0, ++ //&gk_i2s0, ++ &gk_musb, ++}; ++ ++//louis add ++/* ==========================================================================*/ ++ ++unsigned int gk_debug_level = GK_DEBUG_MEDIA | GK_DEBUG_DSP | GK_DEBUG_VI | GK_DEBUG_VO | GK_DEBUG_AAA; ++EXPORT_SYMBOL(gk_debug_level); ++ ++unsigned int gk_debug_info = 0; ++EXPORT_SYMBOL(gk_debug_info); ++ ++unsigned int gk_boot_splash_logo = 0; ++EXPORT_SYMBOL(gk_boot_splash_logo); ++ ++unsigned long gk_debug_lookup_name(const char *name) ++{ ++ return module_kallsyms_lookup_name(name); ++} ++EXPORT_SYMBOL(gk_debug_lookup_name); ++//end ++ ++void sensor_init(u8 active_level) ++{ ++ struct gk_gpio_io_info sensor_reset; ++ sensor_reset.gpio_id = gk_all_gpio_cfg.sensor_reset; ++ sensor_reset.active_level = active_level; ++ sensor_reset.active_delay = 1; ++ ++ printk("sensor board reset...\n"); ++ gk_set_gpio_output(&sensor_reset, 1); ++ mdelay(50);//100ms ++ gk_set_gpio_output(&sensor_reset, 0); ++ mdelay(200);//100ms ++} ++EXPORT_SYMBOL(sensor_init); ++ ++void sensor_power(u8 power) ++{ ++} ++EXPORT_SYMBOL(sensor_power); ++ ++/* ==========================================================================*/ ++static u8 cmdline_mac[6]; ++static int __init init_setup_mac(char *str) ++{ ++ int count, i, val; ++ ++ for (count = 0; count < 6 && *str; count++, str += 3) { ++ if (!isxdigit(str[0]) || !isxdigit(str[1])) ++ return 0; ++ if (str[2] != ((count < 5) ? ':' : '\0')) ++ return 0; ++ ++ for (i = 0, val = 0; i < 2; i++) { ++ val = val << 4; ++ val |= isdigit(str[i]) ? ++ str[i] - '0' : toupper(str[i]) - 'A' + 10; ++ } ++ cmdline_mac[count] = val; ++ } ++ return 1; ++ ++} ++__setup("mac=", init_setup_mac); ++ ++u8 cmdline_phytype; ++static int __init init_setup_phytype(char *str) ++{ ++ if (!isxdigit(str[0])) ++ return 0; ++ ++ cmdline_phytype = str[0] - '0'; ++ return 1; ++} ++__setup("phytype=", init_setup_phytype); ++EXPORT_SYMBOL(cmdline_phytype); ++ ++int __init gk_init_board(char *board_name) ++{ ++#ifdef CONFIG_ETH_GOKE ++ unsigned char mac_addr[6] = {00,0x11,0x22,0xa3,0xa0,00}; ++#endif ++ int retval = 0; ++ ++ //pr_info("Goke %s:\n", board_name); ++ //pr_info("\tboard revision:\t\t%d\n", 1); ++ ++ //retval = gk_init_pll(); ++ //BUG_ON(retval != 0); ++ // ++#if 1 //wangbin add for gk7101s ++// gk_writel(0xf3170208,0x24);//RGB i80 CVBS ++// gk_writel(0xf3170208,0x20);//BT1120 ++#endif ++ printk("init timer...\n"); ++ retval = gk_init_timer(); ++ BUG_ON(retval != 0); ++ ++ printk("init gpio...\n"); ++ retval = gk_init_gpio(); ++ BUG_ON(retval != 0); ++ ++ gk_set_sd_detect_pin(gk_all_gpio_cfg.sd_detect); ++#ifdef CONFIG_GK710XS_SDIO2 ++ gk_set_sd1_detect_pin(gk_all_gpio_cfg.sd1_detect); ++#endif ++#ifdef CONFIG_SPI_GOKE ++ gk_spi0_cs_pins[0] = gk_all_gpio_cfg.spi0_en0; ++#if (SPI_MASTER_INSTANCES >= 2 ) ++ gk_spi1_cs_pins[0] = gk_all_gpio_cfg.spi1_en0; ++#endif ++#endif ++ ++ ++#ifdef CONFIG_ETH_GOKE ++ gk_set_phy_reset_pin(gk_all_gpio_cfg.phy_reset); ++ #if (ETH_INSTANCES >= 1) ++ if (cmdline_mac[0]) ++ memcpy(mac_addr, cmdline_mac, 6); ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ retval = gk_init_eth0(mac_addr); ++ BUG_ON(retval != 0); ++ #endif ++#endif ++ ++ retval = gk_init_dma(); ++ BUG_ON(retval != 0); ++ ++ //config video DAC for CVBS ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x00, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x04, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x08, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x10, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x14, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x18, 0x3F); ++ ++ gk_init_sd(); ++ ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_func_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_func_config(gk_all_gpio_cfg.pmu_ctl, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++ gk_load_51mcu_code(PMU_ALWAYS_RUNNING); ++#endif ++ return retval; ++ ++} ++ ++static void __init gk_init_machine(void) ++{ ++ int i; ++ ++ //clkdev_init(); ++ gk_init_board("GK_chip"); ++ ++#if defined(CONFIG_MTD_SFLASH_GOKE) || defined(CONFIG_MTD_SFLASH_GOKE_MODULE) ++ platform_device_register(&gk_flash_device0); ++#endif ++ ++ gk_create_proc_dir(); ++ ++#ifdef CONFIG_FB_GOKE ++ gk_init_fb(); ++#endif ++ ++ printk("gk register devices %d\n", ARRAY_SIZE(gk_devices)); ++ ++ /* Register devices */ ++ platform_add_devices(gk_devices, ARRAY_SIZE(gk_devices)); ++ for (i = 0; i < ARRAY_SIZE(gk_devices); i++) { ++ device_set_wakeup_capable(&gk_devices[i]->dev, 1); ++ device_set_wakeup_enable(&gk_devices[i]->dev, 0); ++ } ++ ++ printk("gk register I2C\n"); ++ //i2c_register_board_info(0, &gk_ak4642_board_info, 1); ++ i2c_register_board_info(0, gk_board_vi_infos, ARRAY_SIZE(gk_board_vi_infos)); ++ i2c_register_board_info(1, gk_board_hdmi_infos, ARRAY_SIZE(gk_board_hdmi_infos)); ++ ++ spi_register_board_info(gk_spi_devices, ++ ARRAY_SIZE(gk_spi_devices)); ++ ++ pm_power_off = gk_power_off; ++ ++} ++ ++MACHINE_START(GOKE_IPC, "Goke IPC Board") ++ .map_io = gk_map_io, ++ .init_irq = gk_init_irq, ++ .handle_irq = gk_vic_handle_irq, ++ .timer = &gk_sys_timer, ++ .init_machine = gk_init_machine, ++ .restart = gk_restart, ++MACHINE_END ++ ++ +diff --git a/arch/arm/mach-gk710xs/mdma.c b/arch/arm/mach-gk710xs/mdma.c +new file mode 100644 +index 00000000..62964dd4 +--- /dev/null ++++ b/arch/arm/mach-gk710xs/mdma.c +@@ -0,0 +1,238 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk710xs/mdma.c ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define TRANSFER_2D_WIDTH (1<<12) /* 4096*/ ++#define MAX_TRANSFER_2D_HEIGHT (1<<11) /* 2048*/ ++#define MAX_TRANSFER_SIZE_2D_UNIT (TRANSFER_2D_WIDTH * MAX_TRANSFER_2D_HEIGHT) /* 8MB*/ ++ ++#define TRANSFER_1D_WIDTH TRANSFER_2D_WIDTH ++#define MAX_TRANSFER_SIZE_1D_UNIT TRANSFER_1D_WIDTH ++ ++/* transfer 6 big blocks (although maximum is 8), because we may do another 1 small block and 1 line. total 8 Ops */ ++#define MAX_TRANSFER_SIZE_ONCE (MAX_TRANSFER_SIZE_2D_UNIT * 6) /* 48 MB*/ ++ ++#define MAX_OPS 8 ++ ++ ++static struct completion transfer_completion; ++ ++ ++/* handle 8MB at one time */ ++static inline int transfer_big_unit(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ int row_count; ++ if (size > MAX_TRANSFER_SIZE_2D_UNIT) { ++ printk("transfer_unit size %d bigger than %d \n", ++ size, MAX_TRANSFER_SIZE_2D_UNIT); ++ return -1; ++ } ++ ++ row_count = size / TRANSFER_2D_WIDTH; ++ ++ /* copy rows by 2D copy */ ++ if (row_count > 0) { ++ gk_dsp_writel(MDMA_SRC_1_BASE_REG, (long)src_addr); ++ gk_dsp_writel(MDMA_SRC_1_PITCH_REG, TRANSFER_2D_WIDTH); ++ gk_dsp_writel(MDMA_DST_BASE_REG, (long)dest_addr); ++ gk_dsp_writel(MDMA_DST_PITCH_REG, TRANSFER_2D_WIDTH); ++ gk_dsp_writel(MDMA_WIDTH_REG, TRANSFER_2D_WIDTH - 1); ++ gk_dsp_writel(MDMA_HEIGHT_REG, row_count - 1); ++ ++ /* start 2D copy */ ++ gk_dsp_writel(MDMA_OPCODE_REG, 1); ++ } ++ return 0; ++ ++} ++ ++ ++/* use 1D copy to copy max 4KB each time */ ++static inline int transfer_small_unit(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ ++ if (size > TRANSFER_1D_WIDTH) { ++ printk("transfer_unit size %d bigger than %d \n", ++ size, TRANSFER_1D_WIDTH); ++ return -1; ++ } ++ ++ /* linear copy */ ++ gk_dsp_writel(MDMA_SRC_1_BASE_REG, (long)src_addr); ++ gk_dsp_writel(MDMA_DST_BASE_REG, (long)dest_addr); ++ gk_dsp_writel(MDMA_WIDTH_REG, TRANSFER_1D_WIDTH - 1); ++ ++ /* start linear copy */ ++ gk_dsp_writel(MDMA_OPCODE_REG, 0); ++ ++ return 0; ++} ++ ++ ++ ++/* this is async function, just fill dma registers and let it run*/ ++static inline int transfer_once(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ //total pending count must be no bigger than 8 ++ int big_count; ++ int rows_count; ++ int i; ++ u32 transferred_bytes = 0; ++ int remain_bytes ; ++ ++ if (size > MAX_TRANSFER_SIZE_ONCE) { ++ printk(" size too big %d for transfer once \n", size); ++ return -1; ++ } ++ ++ big_count = size/MAX_TRANSFER_SIZE_2D_UNIT; ++ //big pages (each is 8MB) ++ for (i = big_count ; i > 0; i--) { ++ transfer_big_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, ++ MAX_TRANSFER_SIZE_2D_UNIT); ++ transferred_bytes += MAX_TRANSFER_SIZE_2D_UNIT; ++ } ++ remain_bytes = size - transferred_bytes; ++ ++ ++ //transfer rows (align to TRANSFER_2D_WIDTH) ++ rows_count = remain_bytes / TRANSFER_2D_WIDTH; ++ if (rows_count > 0) { ++ transfer_big_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, ++ TRANSFER_2D_WIDTH * rows_count); ++ transferred_bytes += TRANSFER_2D_WIDTH * rows_count; ++ remain_bytes = size - transferred_bytes; ++ } ++ ++ if (remain_bytes > 0) { ++ transfer_small_unit(dest_addr + transferred_bytes, ++ src_addr + transferred_bytes, remain_bytes); ++ } ++ ++ return 0; ++} ++ ++/* this is synchronous function, will wait till transfer finishes */ ++int dma_memcpy(u8 *dest_addr, u8 *src_addr, u32 size) ++{ ++ int remain_size = size; ++ int transferred_size = 0; ++ int current_transfer_size; ++ ++ while (remain_size > 0) { ++ if (remain_size > MAX_TRANSFER_SIZE_ONCE) { ++ remain_size -= MAX_TRANSFER_SIZE_ONCE; ++ current_transfer_size = MAX_TRANSFER_SIZE_ONCE; ++ } else { ++ current_transfer_size = remain_size; ++ remain_size = 0; ++ } ++ ++ transfer_once(dest_addr + transferred_size, ++ src_addr + transferred_size, current_transfer_size); ++ wait_for_completion(&transfer_completion); ++ transferred_size += current_transfer_size; ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(dma_memcpy); ++ ++ ++static irqreturn_t mdma_interrupt(int irq, void *dev_id) ++{ ++ int pending_ops; ++ pending_ops = gk_dsp_readl(MDMA_PENDING_OPS_REG); ++ ++ if (pending_ops == 0) { ++ /* if no following transfer */ ++ complete(&transfer_completion); ++ } else { ++ ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int hw_init(void) ++{ ++ int errorCode; ++ /* request irq, no device id, no irq sharing */ ++ errorCode = request_irq(MDMA_IRQ, mdma_interrupt, IRQF_TRIGGER_RISING, "mdma", 0); ++ ++ if (errorCode) { ++ printk("mdma irq request failed \n"); ++ return -1; ++ } ++ printk("mdma request irq: %d \n", MDMA_IRQ); ++ ++ return 0; ++} ++ ++ ++/* wait till transmit completes */ ++static void wait_transmit_complete(void) ++{ ++ int pending_ops; ++ pending_ops = gk_dsp_readl(MDMA_PENDING_OPS_REG); ++ ++ while(pending_ops!= 0) { ++ mdelay(10); ++ } ++} ++ ++static int __init mdma_init(void) ++{ ++ printk("mdma init...\n"); ++ ++ /* hardware and irq init */ ++ if (hw_init() != 0) ++ return -1; ++ /* init completion */ ++ init_completion(&transfer_completion); ++ ++ return 0; ++} ++ ++ ++static void __exit mdma_exit(void) ++{ ++ wait_transmit_complete(); ++} ++ ++MODULE_AUTHOR("Louis "); ++MODULE_DESCRIPTION("MDMA driver on gk"); ++MODULE_LICENSE("GPL v2"); ++MODULE_VERSION("1.0"); ++ ++module_init(mdma_init); ++module_exit(mdma_exit); ++ +diff --git a/arch/arm/mach-gk710xs/rct.c b/arch/arm/mach-gk710xs/rct.c +new file mode 100644 +index 00000000..457669ba +--- /dev/null ++++ b/arch/arm/mach-gk710xs/rct.c +@@ -0,0 +1,194 @@ ++/* ++ * arch/arm/mach-gk/rct.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++u32 get_apb_bus_freq_hz(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0118; ++ u32 apb_freq; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0118 = gk_rct_readl(GK_VA_RCT + 0x0118); ++ if(div0118 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ apb_freq = (24 * arm_pll.bitc.fbdiv * 1000000)/(div0118 * 4 * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ } ++ else ++ { ++ apb_freq = GK_APB_FREQ; ++ } ++ ++ return apb_freq; ++} ++EXPORT_SYMBOL(get_apb_bus_freq_hz); ++ ++u32 get_uart_freq_hz(void) ++{ ++ return (u32)GK_UART_FREQ; ++} ++EXPORT_SYMBOL(get_uart_freq_hz); ++ ++u32 get_ssi0_freq_hz(void) ++{ ++ u32 div = gk_rct_readl(GK_VA_RCT + 0x0030) & 0xFF; ++ if(div == 0) ++ { ++ div = 8; ++ } ++ return (get_apb_bus_freq_hz()/div); ++} ++EXPORT_SYMBOL(get_ssi0_freq_hz); ++ ++u32 get_ssi1_freq_hz(void) ++{ ++ u32 div = gk_rct_readl(GK_VA_RCT + 0x00A0) & 0xFF; ++ if(div == 0) ++ { ++ div = 8; ++ } ++ return (get_apb_bus_freq_hz()/div); ++} ++EXPORT_SYMBOL(get_ssi1_freq_hz); ++ ++u32 get_sd_freq_hz(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0018; ++ u32 sd_freq; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0018 = gk_rct_readl(GK_VA_RCT + 0x0018); ++ if(div0018 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ sd_freq = (24 * arm_pll.bitc.fbdiv * 1000000)/(div0018 * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ } ++ else ++ { ++ sd_freq = GK_SD_FREQ; ++ } ++ return sd_freq; ++} ++EXPORT_SYMBOL(get_sd_freq_hz); ++ ++void set_sd_rct(u32 freq) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 div0018; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x014); ++ div0018 = gk_rct_readl(GK_VA_RCT + 0x0018); ++ if(div0018 * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ div0018 = (24 * arm_pll.bitc.fbdiv * 1000000)/(arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ div0018 /= freq; ++ gk_rct_writel(GK_VA_RCT + 0x0018, div0018); ++ } ++} ++EXPORT_SYMBOL(set_sd_rct); ++ ++u32 get_audio_clk_freq(void) ++{ ++ typedef union { ++ u32 all; ++ struct { ++ u32 fbdiv : 12; ++ u32 pstdiv1 : 3; ++ u32 : 1; ++ u32 pstdiv2 : 3; ++ u32 : 1; ++ u32 refdiv : 6; ++ u32 : 6; ++ } bitc; ++ } GH_PLL_CORE_CTRL_S; ++ GH_PLL_CORE_CTRL_S arm_pll; ++ u32 PST_div; ++ u32 PRE_div; ++ u32 audio_freq; ++ u32 FRAC; ++ arm_pll.all = gk_rct_readl(GK_VA_RCT + 0x024); ++ FRAC = gk_rct_readl(GK_VA_RCT + 0x078); ++ PST_div = gk_rct_readl(GK_VA_RCT + 0x084); ++ PRE_div = gk_rct_readl(GK_VA_RCT + 0x080); ++ if(PST_div * PRE_div * arm_pll.bitc.fbdiv * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2) ++ { ++ u64 FRAC_c; ++ u64 div_all; ++ FRAC_c = FRAC; ++ FRAC_c *= 15625; ++ FRAC_c *= 24; ++ div_all = 262144 * PST_div * PRE_div * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2; ++ FRAC_c += (div_all>>1); ++ do_div((FRAC_c), (div_all)); \ ++ audio_freq = (24 * (arm_pll.bitc.fbdiv * 1000000))/(PST_div * PRE_div * arm_pll.bitc.refdiv * arm_pll.bitc.pstdiv1 * arm_pll.bitc.pstdiv2); ++ audio_freq += (u32)FRAC_c; ++ } ++ else ++ { ++ audio_freq = 12288000; ++ } ++ return audio_freq; ++} ++EXPORT_SYMBOL(get_audio_clk_freq); ++ +diff --git a/arch/arm/mach-gk710xs/vi.c b/arch/arm/mach-gk710xs/vi.c +new file mode 100644 +index 00000000..42a3081c +--- /dev/null ++++ b/arch/arm/mach-gk710xs/vi.c +@@ -0,0 +1,55 @@ ++/* ++ * arch/arm/mach-gk/vi.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++/* ==========================================================================*/ ++struct i2c_board_info gk_board_vi_infos[2] = { ++ [0] = { ++ .type = "gk_vi0", ++ .addr = 0x02, ++ }, ++ [1] = { ++ .type = "gk_vi1", ++ .addr = 0x03, ++ }, ++}; ++ ++struct i2c_board_info gk_board_hdmi_infos[3] = { ++ [0] = { ++ .type = "ep952", ++ .addr = (0x52>>1), ++ }, ++ [1] = { ++ .type = "rtc8563", ++ .addr = 0x51, ++ }, ++ [2] = { ++ .type = "bma250", ++ .addr = 0x18, ++ }, ++}; ++ +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 7c8a7d84..f6f381f2 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -747,7 +747,11 @@ config CPU_DCACHE_SIZE + hex + depends on CPU_ARM740T || CPU_ARM946E + default 0x00001000 if CPU_ARM740T +- default 0x00002000 # default size for ARM946E-S ++ default 0x00002000 if !(PLAT_GOKE) # default size for ARM946E-S ++ default 0x00004000 if ARCH_GK710X ++ default 0x00004000 if ARCH_GK710X_FPGA ++ default 0x00004000 if ARCH_GK710XS ++ default 0x00004000 if ARCH_GK710XS_FPGA + help + Some cores are synthesizable to have various sized cache. For + ARM946E-S case, it can vary from 0KB to 1MB. +@@ -890,7 +894,11 @@ config ARM_L1_CACHE_SHIFT_6 + config ARM_L1_CACHE_SHIFT + int + default 6 if ARM_L1_CACHE_SHIFT_6 +- default 5 ++ default 5 if !(PLAT_GOKE) ++ default 4 if ARCH_GK710X ++ default 4 if ARCH_GK710X_FPGA ++ default 4 if ARCH_GK710XS ++ default 4 if ARCH_GK710XS_FPGA + + config ARM_DMA_MEM_BUFFERABLE + bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 +diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c +index a3e4adf2..ad77d659 100644 +--- a/arch/arm/mm/dma-mapping.c ++++ b/arch/arm/mm/dma-mapping.c +@@ -128,7 +128,7 @@ static void __dma_free_buffer(struct page *page, size_t size) + */ + static pte_t **consistent_pte; + +-#define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M ++#define DEFAULT_CONSISTENT_DMA_SIZE SZ_8M + + unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE; + +diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c +index 8f5813bb..1742ae3d 100644 +--- a/arch/arm/mm/init.c ++++ b/arch/arm/mm/init.c +@@ -653,6 +653,9 @@ void __init mem_init(void) + " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n" + #endif + " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" ++#ifdef CONFIG_MMU ++ " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n" ++#endif + " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" + " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" + #ifdef CONFIG_HIGHMEM +@@ -673,6 +676,9 @@ void __init mem_init(void) + MLK(ITCM_OFFSET, (unsigned long) itcm_end), + #endif + MLK(FIXADDR_START, FIXADDR_TOP), ++#ifdef CONFIG_MMU ++ MLM(CONSISTENT_BASE, CONSISTENT_END), ++#endif + MLM(VMALLOC_START, VMALLOC_END), + MLM(PAGE_OFFSET, (unsigned long)high_memory), + #ifdef CONFIG_HIGHMEM +diff --git a/arch/arm/plat-goke/Kconfig b/arch/arm/plat-goke/Kconfig +new file mode 100644 +index 00000000..c14cdce3 +--- /dev/null ++++ b/arch/arm/plat-goke/Kconfig +@@ -0,0 +1,734 @@ ++# ++# arch/arm/plat-goke/Kconfig ++# ++# History: ++# 2016/04/18 - [Steven Yu] created file ++# ++# Copyright (C) 2002-2016, Goke Microelectronics China. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++# ++ ++if ARCH_GK710X || ARCH_GK710XS || ARCH_GK710X_FPGA || ARCH_GK710XS_FPGA || ARCH_GK720X || ARCH_GK720X_FPGA ++ ++choice ++ prompt "Gk710X system flash select" ++ default ONLY_USE_NOR_8M ++ ++config ONLY_USE_NOR_8M ++ bool "system only 8Mbytes nor flash" ++ help ++ select Goke GK710X only use 8M nor flash ++ ++config ONLY_USE_NOR_16M ++ bool "system only 16Mbytes nor flash" ++ help ++ select Goke GK710X only use 16M nor flash ++ ++config ONLY_USE_NOR_32M ++ bool "system only 32Mbytes nor flash" ++ help ++ select Goke GK710X only use 32M nor flash ++ ++config ONLY_USE_NAND ++ bool "system only use nand flash" ++ help ++ select Goke GK710X only use nand flash ++ ++config USE_NOR_AND_NAND ++ bool "system use nor and nand flash" ++ help ++ select Goke GK710X only use nor and nand flash ++ ++endchoice ++ ++ ++menu "Gk710X select peripheral" ++ ++choice ++ prompt "phy clk mode select" ++ default PHY_USE_AO_MCLK ++ ++config PHY_USE_AO_MCLK ++ bool "the phy use the audio mclk" ++ help ++ select Goke GK710X phy the phy use audio mclk ++ ++config PHY_USE_SD_CLK ++ bool "the phy use the SDIO clk" ++ help ++ select Goke GK710X phy the phy use SDIO mclk ++ ++config PHY_USE_EXTERN_CLK ++ bool "the phy use the extern clk" ++ help ++ select Goke GK710X phy the phy use the extern mclk ++ ++endchoice ++ ++choice ++ prompt "pmu work mode" ++ default PMU_POWER_OFF_CPU ++ ++config PMU_POWER_OFF_CPU ++ bool "load mcu code then power off the arm cpu" ++ help ++ select the 51cpu work mode ++ ++config PMU_ALWAYS_RUNNING ++ bool "load mcu code do not power off the arm cpu" ++ help ++ select the 51cpu work mode, must use a gpio connect to pmu gpio 3 to get the pmu controller ++ ++config PMU_AUTOMOTIVE ++ bool "work mode for automotive" ++ help ++ select the 51cpu work mode ++ ++endchoice ++ ++ ++config SYSTEM_USE_EXTERN_I2S ++ bool "The soc select extern I2S" ++ help ++ select extern I2S or not. ++ ++endmenu ++ ++config GK_CHIP_INCLUDE_FILE ++ string ++ default "mach/gk710x.h" if ARCH_GK710X ++ default "mach/gk710xs.h" if ARCH_GK710XS ++ default "mach/gk720x.h" if ARCH_GK720X ++ default "mach/gk720x.h" if ARCH_GK720X_FPGA ++endif ++ ++comment "soc/fpga modules list" ++ ++config PLAT_GOKE ++ bool ++ help ++ Support for . ++ ++config GK_CPU_ARM_1176_V1_00 ++ bool ++ help ++ Support for ARM 1176 v1.00. ++ ++config GK_CPU_ARM_1176_V1_10 ++ bool ++ help ++ Support for ARM 1176 v1.10. ++ ++config GK_CPU_ARM_1176_V1_20 ++ bool ++ help ++ Support for ARM 1176 v1.20. ++ ++config GK_CPU_CORTEX_A7_V1_00 ++ bool ++ help ++ Support for CORTEX A7 v1.00. ++ ++config GK_PLL_CHIP_V1_00 ++ bool ++ help ++ Support for pll v1.00 soc. ++ ++config GK_PLL_CHIP_V1_10 ++ bool ++ help ++ Support for pll v1.10 soc. ++ ++config GK_PLL_CHIP_V1_20 ++ bool ++ help ++ Support for pll v1.20 soc. ++ ++config GK_PLL_FPGA_V1_00 ++ bool ++ help ++ Support for pll v1.00 fpga. ++ ++config GK_PLL_FPGA_V1_10 ++ bool ++ help ++ Support for pll v1.10 fpga. ++ ++config GK_PLL_FPGA_V1_20 ++ bool ++ help ++ Support for pll v1.20 fpga. ++ ++config GK_EFUSE ++ bool ++ help ++ Support for efuse v1.00. ++ ++config GK_EFUSE_V1_00 ++ bool ++ help ++ Support for efuse v1.00. ++ ++config GK_EFUSE_V1_10 ++ bool ++ help ++ Support for efuse v1.10. ++ ++config GK_EFUSE_V1_20 ++ bool ++ help ++ Support for efuse v1.20. ++ ++config GK_EFUSE_V1_30 ++ bool ++ help ++ Support for efuse v1.30. ++ ++config GK_CRYPT ++ bool ++ help ++ Support for . ++ ++config GK_CRYPT_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_CRYPT_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_TIMER ++ bool ++ help ++ Support for . ++ ++config GK_TIMER_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_TIMER_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_WDT ++ bool ++ help ++ Support for . ++ ++config GK_WDT_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_WDT_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_CON ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_CON_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_CON_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_PHY ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_PHY_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_DDR2_PHY_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_GPIO ++ bool ++ help ++ Support for . ++ ++config GK_GPIO_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_GPIO_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_GPIO_V1_20 ++ bool ++ help ++ Support for . ++ ++config GK_GPIO_MAX_INPUT_TYPE ++ int ++ default 64 if ARCH_GK710X ++ default 64 if ARCH_GK710X_FPGA ++ default 128 if ARCH_GK710XS ++ default 128 if ARCH_GK710XS_FPGA ++ default 128 if ARCH_GK720X ++ default 128 if ARCH_GK720X_FPGA ++ help ++ Support for . ++ ++config GK_GPIO_INSTANCES ++ int ++ default 1 if ARCH_GK710X ++ default 1 if ARCH_GK710X_FPGA ++ default 1 if ARCH_GK710XS ++ default 1 if ARCH_GK710XS_FPGA ++ default 1 if ARCH_GK720X ++ default 1 if ARCH_GK720X_FPGA ++ help ++ Support for . ++ ++config GK_UART ++ bool ++ help ++ Support for . ++ ++config GK_UART_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_UART_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_UART_V1_20 ++ bool ++ help ++ Support for . ++ ++config GK_MUSB ++ bool ++ help ++ Support for . ++ ++config GK_MUSB_CON_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_MUSB_CON_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_USB_DMA ++ bool ++ help ++ Support for . ++ ++config GK_USB_DMA_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_USB_DMA_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_USB_PHY ++ bool ++ help ++ Support for . ++ ++config GK_USB_PHY_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_I2S ++ bool ++ help ++ Support for . ++ ++config GK_I2S_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_AUD_CON ++ bool ++ help ++ Support for . ++ ++config GK_AUD_CON_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_AUD_AD ++ bool ++ help ++ Support for . ++ ++config GK_AUD_AD_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_AUD_DMA ++ bool ++ help ++ Support for . ++ ++config GK_AUD_DMA_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_AUD_DMA_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_ETH ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EMAC ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EMAC_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EMAC_V1_01 ++ bool ++ help ++ Support for . ++config GK_ETH_EDMA ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EDMA_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EPHY ++ bool ++ help ++ Support for . ++ ++config GK_ETH_EPHY_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_PWM ++ bool ++ help ++ Support for . ++ ++config GK_PWM_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SDIO ++ bool ++ help ++ Support for . ++ ++config GK_SDIO2 ++ bool ++ help ++ Support for . ++ ++config GK_SDIO2_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SDIO3 ++ bool ++ help ++ Support for . ++ ++config GK_SDIO3_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ADC ++ bool ++ help ++ Support for . ++ ++config GK_ADC_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ADC_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_I2C ++ bool ++ help ++ Support for . ++ ++config GK_I2C_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SFLASH ++ bool ++ help ++ Support for . ++ ++config GK_SFLASH_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SPI ++ bool ++ help ++ Support for . ++ ++config GK_SPI_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_PMU ++ bool ++ help ++ Support for . ++ ++config GK_PMU_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_PMU_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_MCU ++ bool ++ help ++ Support for . ++ ++config GK_MCU_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_RTC ++ bool ++ help ++ Support for . ++ ++config GK_RTC_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_IR ++ bool ++ help ++ Support for . ++ ++config GK_IR_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_VOUT ++ bool ++ help ++ Support for . ++ ++config GK_VOUT_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_VOUT_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_VOUT_V1_20 ++ bool ++ help ++ Support for . ++ ++config GK_HDMI ++ bool ++ help ++ Support for . ++ ++config GK_HDMI_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_MIPI ++ bool ++ help ++ Support for . ++ ++config GK_MIPI_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_VIN ++ bool ++ help ++ Support for . ++ ++config GK_VIN_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_VIN_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_VIN_V1_20 ++ bool ++ help ++ Support for . ++ ++config GK_MDMA ++ bool ++ help ++ Support for . ++ ++config GK_MDMA_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SMEM ++ bool ++ help ++ Support for . ++ ++config GK_SMEM_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_SMEM_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_DSP1 ++ bool ++ help ++ Support for . ++ ++config GK_DSP1_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_DSP2 ++ bool ++ help ++ Support for . ++ ++config GK_DSP2_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ISP ++ bool ++ help ++ Support for . ++ ++config GK_ISP_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_ISP_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_FW ++ bool ++ help ++ Support for . ++ ++config GK_FW_V1_00 ++ bool ++ help ++ Support for . ++ ++config GK_FW_V1_10 ++ bool ++ help ++ Support for . ++ ++config GK_FW_V1_20 ++ bool ++ help ++ Support for . ++ ++config GK_FB ++ bool ++ help ++ Support for . ++ ++config GK_FB_V1_00 ++ bool ++ help ++ Support for . +diff --git a/arch/arm/plat-goke/Makefile b/arch/arm/plat-goke/Makefile +new file mode 100644 +index 00000000..cf261b01 +--- /dev/null ++++ b/arch/arm/plat-goke/Makefile +@@ -0,0 +1,16 @@ ++obj-y += gk_gpio.o ++obj-y += timer.o ++obj-$(CONFIG_SERIAL_GOKE) += uart.o ++obj-$(CONFIG_ETH_GOKE) += eth.o ++obj-y += cache.o event.o highres_timer.o sync_proc.o ++obj-y += fb.o ++obj-y += pmu.o ++obj-y += sd.o ++obj-y += hw_timer.o ++obj-y += switch.o ++ ++obj-$(CONFIG_GK_GPIO_V1_00) += gk_gpio_v1_00.o ++obj-$(CONFIG_GK_GPIO_V1_10) += gk_gpio_v1_10.o ++obj-$(CONFIG_GK_GPIO_V1_20) += gk_gpio_v1_20.o ++ ++ccflags-y += -Iarch/arm/plat-goke/include/ +diff --git a/arch/arm/plat-goke/cache.c b/arch/arm/plat-goke/cache.c +new file mode 100644 +index 00000000..285625d8 +--- /dev/null ++++ b/arch/arm/plat-goke/cache.c +@@ -0,0 +1,354 @@ ++/* ++ * arch/arm/mach-gk7101/cache.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#ifdef CONFIG_CACHE_PL310 ++#include ++#endif ++#include ++ ++#include ++#include ++ ++/* ==========================================================================*/ ++#ifdef MODULE_PARAM_PREFIX ++#undef MODULE_PARAM_PREFIX ++#endif ++#define MODULE_PARAM_PREFIX "gk_config." ++ ++ ++/* ==========================================================================*/ ++#ifdef CONFIG_OUTER_CACHE ++static u32 cache_l2_status = 0; ++#ifdef CONFIG_CACHE_PL310 ++static void __iomem *gk_cache_l2_base = __io(GK_VA_L2CC_BASE); ++#endif ++#endif ++ ++static int cache_check_start = 1; ++module_param(cache_check_start, int, 0644); ++static int cache_check_end = 0; ++module_param(cache_check_end, int, 0644); ++static int cache_check_fail_halt = 0; ++module_param(cache_check_fail_halt, int, 0644); ++ ++/* ==========================================================================*/ ++void gk_cache_clean_range(void *addr, unsigned int size) ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ u32 vstart; ++ u32 vend; ++#ifdef CONFIG_OUTER_CACHE ++ u32 pstart; ++#endif ++ u32 addr_tmp; ++ ++ vstart = (u32)addr & CACHE_LINE_MASK; ++ vend = ((u32)addr + size + CACHE_LINE_SIZE - 1) & CACHE_LINE_MASK; ++ if (cache_check_start && (vstart != (u32)addr)) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vstart, (u32)addr); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++ if (cache_check_end && (vend != ((u32)addr + size))) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vend, ((u32)addr + size)); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++#ifdef CONFIG_OUTER_CACHE ++ pstart = gk_virt_to_phys(vstart); ++#endif ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c10, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++ ++#ifdef CONFIG_OUTER_CACHE ++ outer_clean_range(pstart, (pstart + size)); ++#endif ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_clean_range); ++ ++void gk_cache_inv_range(void *addr, unsigned int size) ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ u32 vstart; ++ u32 vend; ++#ifdef CONFIG_OUTER_CACHE ++ u32 pstart; ++#endif ++ u32 addr_tmp; ++ ++ vstart = (u32)addr & CACHE_LINE_MASK; ++ vend = ((u32)addr + size + CACHE_LINE_SIZE - 1) & CACHE_LINE_MASK; ++ if (cache_check_start && (vstart != (u32)addr)) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vstart, (u32)addr); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++ if (cache_check_end && (vend != ((u32)addr + size))) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vend, ((u32)addr + size)); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++#ifdef CONFIG_OUTER_CACHE ++ pstart = gk_virt_to_phys(vstart); ++ outer_inv_range(pstart, (pstart + size)); ++#endif ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c6, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++ ++#ifdef CONFIG_OUTER_CACHE ++ outer_inv_range(pstart, (pstart + size)); ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c6, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++#endif ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_inv_range); ++ ++void gk_cache_flush_range(void *addr, unsigned int size) ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ u32 vstart; ++ u32 vend; ++#ifdef CONFIG_OUTER_CACHE ++ u32 pstart; ++#endif ++ u32 addr_tmp; ++ ++ vstart = (u32)addr & CACHE_LINE_MASK; ++ vend = ((u32)addr + size + CACHE_LINE_SIZE - 1) & CACHE_LINE_MASK; ++ if (cache_check_start && (vstart != (u32)addr)) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vstart, (u32)addr); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++ if (cache_check_end && (vend != ((u32)addr + size))) { ++ pr_warn("%s start:0x%08x vs 0x%08x\n", ++ __func__, vend, ((u32)addr + size)); ++ if (cache_check_fail_halt) ++ BUG(); ++ } ++#ifdef CONFIG_OUTER_CACHE ++ pstart = gk_virt_to_phys(vstart); ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c10, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++ ++ outer_flush_range(pstart, (pstart + size)); ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c6, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++#else ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c14, 1" : : "r" (addr_tmp)); ++ } ++ dsb(); ++#endif ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_flush_range); ++ ++void gk_cache_pli_range(void *addr, unsigned int size) ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ u32 vstart; ++ u32 vend; ++ u32 addr_tmp; ++ ++ vstart = (u32)addr & CACHE_LINE_MASK; ++ vend = ((u32)addr + size + CACHE_LINE_SIZE - 1) & CACHE_LINE_MASK; ++ ++ for (addr_tmp = vstart; addr_tmp < vend; addr_tmp += CACHE_LINE_SIZE) { ++#if __LINUX_ARM_ARCH__ >= 7 ++ __asm__ __volatile__ ( ++ "pli [%0]" : : "r" (addr_tmp)); ++#elif __LINUX_ARM_ARCH__ >= 5 ++ __asm__ __volatile__ ( ++ "mcr p15, 0, %0, c7, c13, 1" : : "r" (addr_tmp)); ++#else ++#error "PLI not supported" ++#endif ++ } ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_pli_range); ++ ++#ifdef CONFIG_OUTER_CACHE ++/* ==========================================================================*/ ++void gk_cache_l2_enable_raw() ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ if (!outer_is_enabled()) { ++ ++#ifdef CONFIG_CACHE_PL310 ++ if (readl(gk_cache_l2_base + L2X0_DATA_LATENCY_CTRL) != ++ 0x00000120) { ++ writel(0x00000120, (gk_cache_l2_base + ++ L2X0_DATA_LATENCY_CTRL)); ++ l2x0_init(gk_cache_l2_base, ++ ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | ++ (0x1 << L2X0_AUX_CTRL_CR_POLICY_SHIFT) | ++ (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | ++ (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | ++ (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)), ++ L2X0_AUX_CTRL_MASK); ++ } else ++#endif ++ outer_enable(); ++ } ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_l2_enable_raw); ++ ++void gk_cache_l2_disable_raw() ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return ; ++#else ++ ++ flush_cache_all(); ++ outer_flush_all(); ++ outer_disable(); ++ outer_inv_all(); ++ flush_cache_all(); ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_l2_disable_raw); ++ ++int gk_cache_l2_enable() ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return 0; ++#else ++ ++ gk_cache_l2_enable_raw(); ++ return outer_is_enabled() ? 0 : -1; ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_l2_enable); ++ ++int gk_cache_l2_disable() ++{ ++#ifdef CONFIG_CPU_DCACHE_DISABLE ++ return 0; ++#else ++ ++ unsigned long flags; ++ ++ if (outer_is_enabled()) { ++ disable_nonboot_cpus(); ++ local_irq_save(flags); ++ gk_cache_l2_disable_raw(); ++ local_irq_restore(flags); ++ enable_nonboot_cpus(); ++ } ++ ++ ++ return outer_is_enabled() ? -1 : 0; ++ ++#endif //CONFIG_CPU_DCACHE_DISABLE ++} ++EXPORT_SYMBOL(gk_cache_l2_disable); ++ ++/* =========================Debug Only========================================*/ ++int cache_l2_set_status(const char *val, const struct kernel_param *kp) ++{ ++ int ret; ++ ++ ret = param_set_uint(val, kp); ++ if (!ret) { ++ if (cache_l2_status) { ++ ret = gk_cache_l2_enable(); ++ } else { ++ ret = gk_cache_l2_disable(); ++ } ++ } ++ ++ return ret; ++} ++ ++static int cache_l2_get_status(char *buffer, const struct kernel_param *kp) ++{ ++ cache_l2_status = outer_is_enabled(); ++ ++ return param_get_uint(buffer, kp); ++} ++ ++static struct kernel_param_ops param_ops_cache_l2 = { ++ .set = cache_l2_set_status, ++ .get = cache_l2_get_status, ++}; ++module_param_cb(cache_l2, ¶m_ops_cache_l2, &cache_l2_status, 0644); ++#endif ++ +diff --git a/arch/arm/plat-goke/eth.c b/arch/arm/plat-goke/eth.c +new file mode 100644 +index 00000000..0f80af70 +--- /dev/null ++++ b/arch/arm/plat-goke/eth.c +@@ -0,0 +1,127 @@ ++/* ++ * arch/arm/mach-gk7101/eth.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++extern u64 gk_dmamask; ++ ++int rct_is_eth_enabled(void) ++{ ++ return 1; ++} ++ ++/* ==========================================================================*/ ++#ifdef MODULE_PARAM_PREFIX ++#undef MODULE_PARAM_PREFIX ++#endif ++#define MODULE_PARAM_PREFIX "gk_config." ++ ++/* ==========================================================================*/ ++static struct resource gk_eth0_resources[] = { ++ [0] = DEFINE_RES_MEM(GK_VA_ETH_GMAC, SZ_8K), ++ [1] = DEFINE_RES_IRQ(ETH_IRQ), ++}; ++ ++struct gk_eth_platform_info gk_eth0_platform_info = { ++ .mac_addr = {0, 0, 0, 0, 0, 0}, ++ .napi_weight = 32, ++ .watchdog_timeo = (2 * HZ), ++ .mii_id = -1, ++ .phy_supported = SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++#if (SUPPORT_GMII == 1) ++ SUPPORTED_1000baseT_Half | ++ SUPPORTED_1000baseT_Full | ++#endif ++ SUPPORTED_Autoneg | ++ SUPPORTED_MII, ++ .phy_reset = { ++ .gpio_id = -1, ++ .active_level = GPIO_HIGH, ++ .active_delay = 1, ++ }, ++ .mii_retry_limit = 200, ++ .mii_retry_tmo = 10, ++ .default_tx_ring_size = 32, ++ .default_rx_ring_size = 64, ++ .default_dma_bus_mode = (ETH_DMA_BUS_MODE_FB | ++ ETH_DMA_BUS_MODE_PBL_32 | ++ ETH_DMA_BUS_MODE_DA_RX), ++ .default_dma_opmode = (ETH_DMA_OPMODE_TTC_256 | ++ ETH_DMA_OPMODE_RTC_64 | ++ ETH_DMA_OPMODE_FUF), ++ .default_supported = 0, ++ .is_enabled = rct_is_eth_enabled, ++}; ++GK_ETH_PARAM_CALL(0, gk_eth0_platform_info, 0644); ++ ++int __init gk_init_eth0(const u8 *mac_addr) ++{ ++ int errCode = 0; ++ ++ gk_eth0_platform_info.mac_addr[0] = mac_addr[0]; ++ gk_eth0_platform_info.mac_addr[1] = mac_addr[1]; ++ gk_eth0_platform_info.mac_addr[2] = mac_addr[2]; ++ gk_eth0_platform_info.mac_addr[3] = mac_addr[3]; ++ gk_eth0_platform_info.mac_addr[4] = mac_addr[4]; ++ gk_eth0_platform_info.mac_addr[5] = mac_addr[5]; ++ ++ ++ return errCode; ++} ++ ++void gk_set_phy_reset_pin(u32 gpio_pin) ++{ ++ /*set phy reset pin*/ ++ gk_eth0_platform_info.phy_reset.gpio_id = gpio_pin; ++} ++ ++ ++void gk_set_phy_speed_led(u32 gpio_type) ++{ ++ gk_gpio_func_config(gk_all_gpio_cfg.phy_speed_led, gpio_type); ++} ++ ++struct platform_device gk_eth0 = { ++ .name = "gk-eth", ++ .id = 0, ++ .resource = gk_eth0_resources, ++ .num_resources = ARRAY_SIZE(gk_eth0_resources), ++ .dev = { ++ .platform_data = &gk_eth0_platform_info, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ +diff --git a/arch/arm/plat-goke/event.c b/arch/arm/plat-goke/event.c +new file mode 100644 +index 00000000..13d0d705 +--- /dev/null ++++ b/arch/arm/plat-goke/event.c +@@ -0,0 +1,160 @@ ++/* ++ * arch/arm/mach-gk/event.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++ ++/* ==========================================================================*/ ++static BLOCKING_NOTIFIER_HEAD(blocking_event_list); ++static RAW_NOTIFIER_HEAD(raw_event_list); ++ ++/* ==========================================================================*/ ++int gk_register_event_notifier(void *nb) ++{ ++ return blocking_notifier_chain_register(&blocking_event_list, nb); ++} ++EXPORT_SYMBOL(gk_register_event_notifier); ++ ++int gk_unregister_event_notifier(void *nb) ++{ ++ return blocking_notifier_chain_unregister(&blocking_event_list, nb); ++} ++EXPORT_SYMBOL(gk_unregister_event_notifier); ++ ++int gk_set_event(unsigned long val, void *v) ++{ ++ return blocking_notifier_call_chain(&blocking_event_list, val, v); ++} ++EXPORT_SYMBOL(gk_set_event); ++ ++int gk_register_raw_event_notifier(void *nb) ++{ ++ return raw_notifier_chain_register(&raw_event_list, nb); ++} ++EXPORT_SYMBOL(gk_register_raw_event_notifier); ++ ++int gk_unregister_raw_event_notifier(void *nb) ++{ ++ return raw_notifier_chain_unregister(&raw_event_list, nb); ++} ++EXPORT_SYMBOL(gk_unregister_raw_event_notifier); ++ ++int gk_set_raw_event(unsigned long val, void *v) ++{ ++ return raw_notifier_call_chain(&raw_event_list, val, v); ++} ++EXPORT_SYMBOL(gk_set_raw_event); ++ ++int gk_event_pool_init(struct gk_event_pool *pool) ++{ ++ if (!pool) ++ return -EINVAL; ++ ++ memset(pool, 0, sizeof(struct gk_event_pool)); ++ mutex_init(&pool->op_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(gk_event_pool_init); ++ ++int gk_event_pool_affuse(struct gk_event_pool *pool, ++ struct gk_event event) ++{ ++ if (!pool) ++ return -EINVAL; ++ ++ if (event.type == GK_EV_NONE) ++ return 0; ++ ++ mutex_lock(&pool->op_mutex); ++ pool->ev_sno++; ++ pool->events[pool->ev_index].sno = pool->ev_sno; ++ pool->events[pool->ev_index].time_code = 0; //FIX ME ++ pool->events[pool->ev_index].type = event.type; ++ memcpy(pool->events[pool->ev_index].data, event.data, sizeof(event.data)); ++ pool->ev_index++; ++ mutex_unlock(&pool->op_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_event_pool_affuse); ++ ++int gk_event_pool_query_index(struct gk_event_pool *pool) ++{ ++ unsigned char index; ++ ++ if (!pool) ++ return -EINVAL; ++ ++ mutex_lock(&pool->op_mutex); ++ index = pool->ev_index - 1; ++ mutex_unlock(&pool->op_mutex); ++ ++ return (int)index; ++} ++EXPORT_SYMBOL(gk_event_pool_query_index); ++ ++int gk_event_pool_query_event(struct gk_event_pool *pool, ++ struct gk_event *event, unsigned char index) ++{ ++ int retval = 0; ++ ++ if (!pool || !event) ++ return -EINVAL; ++ ++ mutex_lock(&pool->op_mutex); ++ ++ if (pool->events[index].type == GK_EV_NONE) { ++ retval = -EAGAIN; ++ goto gk_event_pool_query_event_exit; ++ } ++ ++ if (index == pool->ev_index) { ++ retval = -EAGAIN; ++ goto gk_event_pool_query_event_exit; ++ } ++ ++ *event = pool->events[index]; ++ ++gk_event_pool_query_event_exit: ++ mutex_unlock(&pool->op_mutex); ++ return retval; ++} ++EXPORT_SYMBOL(gk_event_pool_query_event); ++ ++int gk_event_report_uevent(struct kobject *kobj, enum kobject_action action, ++ char *envp_ext[]) ++{ ++ return kobject_uevent_env(kobj, action, envp_ext); ++} ++EXPORT_SYMBOL(gk_event_report_uevent); ++ ++ +diff --git a/arch/arm/plat-goke/fb.c b/arch/arm/plat-goke/fb.c +new file mode 100644 +index 00000000..1100605a +--- /dev/null ++++ b/arch/arm/plat-goke/fb.c +@@ -0,0 +1,893 @@ ++/* ++ * arch/arm/mach-gk/fb.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/* ==========================================================================*/ ++static struct gk_platform_fb gk_platform_fb0 = { ++ .screen_var = { ++ .xres = 720, ++ .yres = 480, ++ .xres_virtual = 720, ++ .yres_virtual = 480, ++ .xoffset = 0, ++ .yoffset = 0, ++ .bits_per_pixel = 8, ++ .red = {.offset = 0, .length = 8, .msb_right = 0}, ++ .green = {.offset = 0, .length = 8, .msb_right = 0}, ++ .blue = {.offset = 0, .length = 8, .msb_right = 0}, ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, ++ .width = -1, ++ .pixclock = 36101, ++ .left_margin = 24, ++ .right_margin = 96, ++ .upper_margin = 10, ++ .lower_margin = 32, ++ .hsync_len = 40, ++ .vsync_len = 3, ++ .vmode = FB_VMODE_NONINTERLACED, ++ }, ++ .screen_fix = { ++ .id = "GK FB", ++ .type = FB_TYPE_PACKED_PIXELS, ++ .visual = FB_VISUAL_PSEUDOCOLOR, ++ .xpanstep = 1, ++ .ypanstep = 1, ++ .ywrapstep = 1, ++ .accel = FB_ACCEL_NONE, ++ .line_length = 0, ++ .smem_start = 0, ++ .smem_len = 0, ++ }, ++ .dsp_status = GK_DSP_UNKNOWN_MODE, ++ .fb_status = GK_FB_UNKNOWN_MODE, ++ .clut_table = { ++ 0, 128, 128, ++ 1, 128, 128, ++ 2, 128, 128, ++ 3, 128, 128, ++ 4, 128, 128, ++ 5, 128, 128, ++ 6, 128, 128, ++ 7, 128, 128, ++ 8, 128, 128, ++ 9, 128, 128, ++ 10, 128, 128, ++ 11, 128, 128, ++ 12, 128, 128, ++ 13, 128, 128, ++ 14, 128, 128, ++ 15, 128, 128, ++ 16, 128, 128, ++ 17, 128, 128, ++ 18, 128, 128, ++ 19, 128, 128, ++ 20, 128, 128, ++ 21, 128, 128, ++ 22, 128, 128, ++ 23, 128, 128, ++ 24, 128, 128, ++ 25, 128, 128, ++ 26, 128, 128, ++ 27, 128, 128, ++ 28, 128, 128, ++ 29, 128, 128, ++ 30, 128, 128, ++ 31, 128, 128, ++ 32, 128, 128, ++ 33, 128, 128, ++ 34, 128, 128, ++ 35, 128, 128, ++ 36, 128, 128, ++ 37, 128, 128, ++ 38, 128, 128, ++ 39, 128, 128, ++ 40, 128, 128, ++ 41, 128, 128, ++ 42, 128, 128, ++ 43, 128, 128, ++ 44, 128, 128, ++ 45, 128, 128, ++ 46, 128, 128, ++ 47, 128, 128, ++ 48, 128, 128, ++ 49, 128, 128, ++ 50, 128, 128, ++ 51, 128, 128, ++ 52, 128, 128, ++ 53, 128, 128, ++ 54, 128, 128, ++ 55, 128, 128, ++ 56, 128, 128, ++ 57, 128, 128, ++ 58, 128, 128, ++ 59, 128, 128, ++ 60, 128, 128, ++ 61, 128, 128, ++ 62, 128, 128, ++ 63, 128, 128, ++ 64, 128, 128, ++ 65, 128, 128, ++ 66, 128, 128, ++ 67, 128, 128, ++ 68, 128, 128, ++ 69, 128, 128, ++ 70, 128, 128, ++ 71, 128, 128, ++ 72, 128, 128, ++ 73, 128, 128, ++ 74, 128, 128, ++ 75, 128, 128, ++ 76, 128, 128, ++ 77, 128, 128, ++ 78, 128, 128, ++ 79, 128, 128, ++ 80, 128, 128, ++ 81, 128, 128, ++ 82, 128, 128, ++ 83, 128, 128, ++ 84, 128, 128, ++ 85, 128, 128, ++ 86, 128, 128, ++ 87, 128, 128, ++ 88, 128, 128, ++ 89, 128, 128, ++ 90, 128, 128, ++ 91, 128, 128, ++ 92, 128, 128, ++ 93, 128, 128, ++ 94, 128, 128, ++ 95, 128, 128, ++ 96, 128, 128, ++ 97, 128, 128, ++ 98, 128, 128, ++ 99, 128, 128, ++ 100, 128, 128, ++ 101, 128, 128, ++ 102, 128, 128, ++ 103, 128, 128, ++ 104, 128, 128, ++ 105, 128, 128, ++ 106, 128, 128, ++ 107, 128, 128, ++ 108, 128, 128, ++ 109, 128, 128, ++ 110, 128, 128, ++ 111, 128, 128, ++ 112, 128, 128, ++ 113, 128, 128, ++ 114, 128, 128, ++ 115, 128, 128, ++ 116, 128, 128, ++ 117, 128, 128, ++ 118, 128, 128, ++ 119, 128, 128, ++ 120, 128, 128, ++ 121, 128, 128, ++ 122, 128, 128, ++ 123, 128, 128, ++ 124, 128, 128, ++ 125, 128, 128, ++ 126, 128, 128, ++ 127, 128, 128, ++ 128, 128, 128, ++ 129, 128, 128, ++ 130, 128, 128, ++ 131, 128, 128, ++ 132, 128, 128, ++ 133, 128, 128, ++ 134, 128, 128, ++ 135, 128, 128, ++ 136, 128, 128, ++ 137, 128, 128, ++ 138, 128, 128, ++ 139, 128, 128, ++ 140, 128, 128, ++ 141, 128, 128, ++ 142, 128, 128, ++ 143, 128, 128, ++ 144, 128, 128, ++ 145, 128, 128, ++ 146, 128, 128, ++ 147, 128, 128, ++ 148, 128, 128, ++ 149, 128, 128, ++ 150, 128, 128, ++ 151, 128, 128, ++ 152, 128, 128, ++ 153, 128, 128, ++ 154, 128, 128, ++ 155, 128, 128, ++ 156, 128, 128, ++ 157, 128, 128, ++ 158, 128, 128, ++ 159, 128, 128, ++ 160, 128, 128, ++ 161, 128, 128, ++ 162, 128, 128, ++ 163, 128, 128, ++ 164, 128, 128, ++ 165, 128, 128, ++ 166, 128, 128, ++ 167, 128, 128, ++ 168, 128, 128, ++ 169, 128, 128, ++ 170, 128, 128, ++ 171, 128, 128, ++ 172, 128, 128, ++ 173, 128, 128, ++ 174, 128, 128, ++ 175, 128, 128, ++ 176, 128, 128, ++ 177, 128, 128, ++ 178, 128, 128, ++ 179, 128, 128, ++ 180, 128, 128, ++ 181, 128, 128, ++ 182, 128, 128, ++ 183, 128, 128, ++ 184, 128, 128, ++ 185, 128, 128, ++ 186, 128, 128, ++ 187, 128, 128, ++ 188, 128, 128, ++ 189, 128, 128, ++ 190, 128, 128, ++ 191, 128, 128, ++ 192, 128, 128, ++ 193, 128, 128, ++ 194, 128, 128, ++ 195, 128, 128, ++ 196, 128, 128, ++ 197, 128, 128, ++ 198, 128, 128, ++ 199, 128, 128, ++ 200, 128, 128, ++ 201, 128, 128, ++ 202, 128, 128, ++ 203, 128, 128, ++ 204, 128, 128, ++ 205, 128, 128, ++ 206, 128, 128, ++ 207, 128, 128, ++ 208, 128, 128, ++ 209, 128, 128, ++ 210, 128, 128, ++ 211, 128, 128, ++ 212, 128, 128, ++ 213, 128, 128, ++ 214, 128, 128, ++ 215, 128, 128, ++ 216, 128, 128, ++ 217, 128, 128, ++ 218, 128, 128, ++ 219, 128, 128, ++ 220, 128, 128, ++ 221, 128, 128, ++ 222, 128, 128, ++ 223, 128, 128, ++ 224, 128, 128, ++ 225, 128, 128, ++ 226, 128, 128, ++ 227, 128, 128, ++ 228, 128, 128, ++ 229, 128, 128, ++ 230, 128, 128, ++ 231, 128, 128, ++ 232, 128, 128, ++ 233, 128, 128, ++ 234, 128, 128, ++ 235, 128, 128, ++ 236, 128, 128, ++ 237, 128, 128, ++ 238, 128, 128, ++ 239, 128, 128, ++ 240, 128, 128, ++ 241, 128, 128, ++ 242, 128, 128, ++ 243, 128, 128, ++ 244, 128, 128, ++ 245, 128, 128, ++ 246, 128, 128, ++ 247, 128, 128, ++ 248, 128, 128, ++ 249, 128, 128, ++ 250, 128, 128, ++ 251, 128, 128, ++ 252, 128, 128, ++ 253, 128, 128, ++ 254, 128, 128, ++ 255, 128, 128, ++ }, ++ .blend_table = { ++ 0, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ }, ++ .color_format = GK_FB_COLOR_CLUT_8BPP, ++ .conversion_buf = { ++ .available = 0, ++ .ping_buf = NULL, ++ .ping_buf_size = 0, ++ .pong_buf = NULL, ++ .pong_buf_size = 0, ++ }, ++ .use_prealloc = 0, ++ .prealloc_line_length = 0, ++ ++ .pan_display = NULL, ++ .setcmap = NULL, ++ .check_var = NULL, ++ .set_par = NULL, ++ .set_blank = NULL, ++ ++ .proc_fb_info = NULL, ++ .proc_file = NULL, ++}; ++ ++struct platform_device gk_fb0 = { ++ .name = "gk-fb", ++ .id = 0, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &gk_platform_fb0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct gk_platform_fb gk_platform_fb1 = { ++ .screen_var = { ++ .xres = 720, ++ .yres = 480, ++ .xres_virtual = 720, ++ .yres_virtual = 480, ++ .xoffset = 0, ++ .yoffset = 0, ++ .bits_per_pixel = 8, ++ .red = {.offset = 0, .length = 8, .msb_right = 0}, ++ .green = {.offset = 0, .length = 8, .msb_right = 0}, ++ .blue = {.offset = 0, .length = 8, .msb_right = 0}, ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, ++ .width = -1, ++ .pixclock = 36101, ++ .left_margin = 24, ++ .right_margin = 96, ++ .upper_margin = 10, ++ .lower_margin = 32, ++ .hsync_len = 40, ++ .vsync_len = 3, ++ .vmode = FB_VMODE_NONINTERLACED, ++ }, ++ .screen_fix = { ++ .id = "GK FB", ++ .type = FB_TYPE_PACKED_PIXELS, ++ .visual = FB_VISUAL_PSEUDOCOLOR, ++ .xpanstep = 1, ++ .ypanstep = 1, ++ .ywrapstep = 1, ++ .accel = FB_ACCEL_NONE, ++ .line_length = 0, ++ .smem_start = 0, ++ .smem_len = 0, ++ }, ++ .dsp_status = GK_DSP_UNKNOWN_MODE, ++ .fb_status = GK_FB_UNKNOWN_MODE, ++ .clut_table = { ++ 0, 128, 128, ++ 1, 128, 128, ++ 2, 128, 128, ++ 3, 128, 128, ++ 4, 128, 128, ++ 5, 128, 128, ++ 6, 128, 128, ++ 7, 128, 128, ++ 8, 128, 128, ++ 9, 128, 128, ++ 10, 128, 128, ++ 11, 128, 128, ++ 12, 128, 128, ++ 13, 128, 128, ++ 14, 128, 128, ++ 15, 128, 128, ++ 16, 128, 128, ++ 17, 128, 128, ++ 18, 128, 128, ++ 19, 128, 128, ++ 20, 128, 128, ++ 21, 128, 128, ++ 22, 128, 128, ++ 23, 128, 128, ++ 24, 128, 128, ++ 25, 128, 128, ++ 26, 128, 128, ++ 27, 128, 128, ++ 28, 128, 128, ++ 29, 128, 128, ++ 30, 128, 128, ++ 31, 128, 128, ++ 32, 128, 128, ++ 33, 128, 128, ++ 34, 128, 128, ++ 35, 128, 128, ++ 36, 128, 128, ++ 37, 128, 128, ++ 38, 128, 128, ++ 39, 128, 128, ++ 40, 128, 128, ++ 41, 128, 128, ++ 42, 128, 128, ++ 43, 128, 128, ++ 44, 128, 128, ++ 45, 128, 128, ++ 46, 128, 128, ++ 47, 128, 128, ++ 48, 128, 128, ++ 49, 128, 128, ++ 50, 128, 128, ++ 51, 128, 128, ++ 52, 128, 128, ++ 53, 128, 128, ++ 54, 128, 128, ++ 55, 128, 128, ++ 56, 128, 128, ++ 57, 128, 128, ++ 58, 128, 128, ++ 59, 128, 128, ++ 60, 128, 128, ++ 61, 128, 128, ++ 62, 128, 128, ++ 63, 128, 128, ++ 64, 128, 128, ++ 65, 128, 128, ++ 66, 128, 128, ++ 67, 128, 128, ++ 68, 128, 128, ++ 69, 128, 128, ++ 70, 128, 128, ++ 71, 128, 128, ++ 72, 128, 128, ++ 73, 128, 128, ++ 74, 128, 128, ++ 75, 128, 128, ++ 76, 128, 128, ++ 77, 128, 128, ++ 78, 128, 128, ++ 79, 128, 128, ++ 80, 128, 128, ++ 81, 128, 128, ++ 82, 128, 128, ++ 83, 128, 128, ++ 84, 128, 128, ++ 85, 128, 128, ++ 86, 128, 128, ++ 87, 128, 128, ++ 88, 128, 128, ++ 89, 128, 128, ++ 90, 128, 128, ++ 91, 128, 128, ++ 92, 128, 128, ++ 93, 128, 128, ++ 94, 128, 128, ++ 95, 128, 128, ++ 96, 128, 128, ++ 97, 128, 128, ++ 98, 128, 128, ++ 99, 128, 128, ++ 100, 128, 128, ++ 101, 128, 128, ++ 102, 128, 128, ++ 103, 128, 128, ++ 104, 128, 128, ++ 105, 128, 128, ++ 106, 128, 128, ++ 107, 128, 128, ++ 108, 128, 128, ++ 109, 128, 128, ++ 110, 128, 128, ++ 111, 128, 128, ++ 112, 128, 128, ++ 113, 128, 128, ++ 114, 128, 128, ++ 115, 128, 128, ++ 116, 128, 128, ++ 117, 128, 128, ++ 118, 128, 128, ++ 119, 128, 128, ++ 120, 128, 128, ++ 121, 128, 128, ++ 122, 128, 128, ++ 123, 128, 128, ++ 124, 128, 128, ++ 125, 128, 128, ++ 126, 128, 128, ++ 127, 128, 128, ++ 128, 128, 128, ++ 129, 128, 128, ++ 130, 128, 128, ++ 131, 128, 128, ++ 132, 128, 128, ++ 133, 128, 128, ++ 134, 128, 128, ++ 135, 128, 128, ++ 136, 128, 128, ++ 137, 128, 128, ++ 138, 128, 128, ++ 139, 128, 128, ++ 140, 128, 128, ++ 141, 128, 128, ++ 142, 128, 128, ++ 143, 128, 128, ++ 144, 128, 128, ++ 145, 128, 128, ++ 146, 128, 128, ++ 147, 128, 128, ++ 148, 128, 128, ++ 149, 128, 128, ++ 150, 128, 128, ++ 151, 128, 128, ++ 152, 128, 128, ++ 153, 128, 128, ++ 154, 128, 128, ++ 155, 128, 128, ++ 156, 128, 128, ++ 157, 128, 128, ++ 158, 128, 128, ++ 159, 128, 128, ++ 160, 128, 128, ++ 161, 128, 128, ++ 162, 128, 128, ++ 163, 128, 128, ++ 164, 128, 128, ++ 165, 128, 128, ++ 166, 128, 128, ++ 167, 128, 128, ++ 168, 128, 128, ++ 169, 128, 128, ++ 170, 128, 128, ++ 171, 128, 128, ++ 172, 128, 128, ++ 173, 128, 128, ++ 174, 128, 128, ++ 175, 128, 128, ++ 176, 128, 128, ++ 177, 128, 128, ++ 178, 128, 128, ++ 179, 128, 128, ++ 180, 128, 128, ++ 181, 128, 128, ++ 182, 128, 128, ++ 183, 128, 128, ++ 184, 128, 128, ++ 185, 128, 128, ++ 186, 128, 128, ++ 187, 128, 128, ++ 188, 128, 128, ++ 189, 128, 128, ++ 190, 128, 128, ++ 191, 128, 128, ++ 192, 128, 128, ++ 193, 128, 128, ++ 194, 128, 128, ++ 195, 128, 128, ++ 196, 128, 128, ++ 197, 128, 128, ++ 198, 128, 128, ++ 199, 128, 128, ++ 200, 128, 128, ++ 201, 128, 128, ++ 202, 128, 128, ++ 203, 128, 128, ++ 204, 128, 128, ++ 205, 128, 128, ++ 206, 128, 128, ++ 207, 128, 128, ++ 208, 128, 128, ++ 209, 128, 128, ++ 210, 128, 128, ++ 211, 128, 128, ++ 212, 128, 128, ++ 213, 128, 128, ++ 214, 128, 128, ++ 215, 128, 128, ++ 216, 128, 128, ++ 217, 128, 128, ++ 218, 128, 128, ++ 219, 128, 128, ++ 220, 128, 128, ++ 221, 128, 128, ++ 222, 128, 128, ++ 223, 128, 128, ++ 224, 128, 128, ++ 225, 128, 128, ++ 226, 128, 128, ++ 227, 128, 128, ++ 228, 128, 128, ++ 229, 128, 128, ++ 230, 128, 128, ++ 231, 128, 128, ++ 232, 128, 128, ++ 233, 128, 128, ++ 234, 128, 128, ++ 235, 128, 128, ++ 236, 128, 128, ++ 237, 128, 128, ++ 238, 128, 128, ++ 239, 128, 128, ++ 240, 128, 128, ++ 241, 128, 128, ++ 242, 128, 128, ++ 243, 128, 128, ++ 244, 128, 128, ++ 245, 128, 128, ++ 246, 128, 128, ++ 247, 128, 128, ++ 248, 128, 128, ++ 249, 128, 128, ++ 250, 128, 128, ++ 251, 128, 128, ++ 252, 128, 128, ++ 253, 128, 128, ++ 254, 128, 128, ++ 255, 128, 128, ++ }, ++ .blend_table = { ++ 0, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ 12, 12, 12, 12, 12, 12, 12, 12, ++ }, ++ .color_format = GK_FB_COLOR_CLUT_8BPP, ++ .conversion_buf = { ++ .available = 0, ++ .ping_buf = NULL, ++ .ping_buf_size = 0, ++ .pong_buf = NULL, ++ .pong_buf_size = 0, ++ }, ++ .use_prealloc = 0, ++ .prealloc_line_length = 0, ++ ++ .pan_display = NULL, ++ .setcmap = NULL, ++ .check_var = NULL, ++ .set_par = NULL, ++ .set_blank = NULL, ++ ++ .proc_fb_info = NULL, ++ .proc_file = NULL, ++}; ++ ++struct platform_device gk_fb1 = { ++ .name = "gk-fb", ++ .id = 1, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &gk_platform_fb1, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++int gk_fb_get_platform_info(u32 fb_id, ++ struct gk_platform_fb *platform_info) ++{ ++ u32 status = -EPERM; ++ ++ if (fb_id == 0) { ++ mutex_lock(&gk_platform_fb0.lock); ++ memcpy(platform_info, &gk_platform_fb0, ++ sizeof(struct gk_platform_fb)); ++ mutex_unlock(&gk_platform_fb0.lock); ++ ++ status = 0; ++ } else ++ if (fb_id == 1) { ++ mutex_lock(&gk_platform_fb1.lock); ++ memcpy(platform_info, &gk_platform_fb1, ++ sizeof(struct gk_platform_fb)); ++ mutex_unlock(&gk_platform_fb1.lock); ++ ++ status = 0; ++ } ++ ++ ++ return status; ++} ++EXPORT_SYMBOL(gk_fb_get_platform_info); ++ ++int gk_fb_set_media_info(u32 fb_id, struct gk_fb_media_info *media) ++{ ++ u32 status = -EPERM; ++ ++ if (fb_id == 0) { ++ mutex_lock(&gk_platform_fb0.lock); ++ gk_platform_fb0.screen_var = media->screen_var; ++ gk_platform_fb0.screen_fix = media->screen_fix; ++ gk_platform_fb0.pan_display = media->pan_display; ++ gk_platform_fb0.setcmap = media->setcmap; ++ gk_platform_fb0.check_var = media->check_var; ++ gk_platform_fb0.set_par = media->set_par; ++ gk_platform_fb0.set_blank = media->set_blank; ++ gk_platform_fb0.dsp_status = media->dsp_status; ++ mutex_unlock(&gk_platform_fb0.lock); ++ ++ status = 0; ++ } else ++ if (fb_id == 1) { ++ mutex_lock(&gk_platform_fb1.lock); ++ gk_platform_fb1.screen_var = media->screen_var; ++ gk_platform_fb1.screen_fix = media->screen_fix; ++ gk_platform_fb1.pan_display = media->pan_display; ++ gk_platform_fb1.setcmap = media->setcmap; ++ gk_platform_fb1.check_var = media->check_var; ++ gk_platform_fb1.set_par = media->set_par; ++ gk_platform_fb1.set_blank = media->set_blank; ++ gk_platform_fb1.dsp_status = media->dsp_status; ++ mutex_unlock(&gk_platform_fb1.lock); ++ ++ status = 0; ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(gk_fb_set_media_info); ++ ++int gk_fb_update_info(u32 fb_id, int xres, int yres, ++ int xvirtual, int yvirtual, int format, u32 bits_per_pixel, ++ u32 smem_start, u32 smem_len) ++{ ++ u32 status = -EPERM; ++ ++ if (fb_id == 0) { ++ mutex_lock(&gk_platform_fb0.lock); ++ gk_platform_fb0.screen_var.xres = xres; ++ gk_platform_fb0.screen_var.yres = yres; ++ gk_platform_fb0.screen_var.xres_virtual = xvirtual; ++ gk_platform_fb0.screen_var.yres_virtual = yvirtual; ++ gk_platform_fb0.screen_var.bits_per_pixel = ++ bits_per_pixel; ++ gk_platform_fb0.color_format = format; ++ gk_platform_fb0.use_prealloc = 1; ++ gk_platform_fb0.screen_fix.smem_start = smem_start; ++ gk_platform_fb0.screen_fix.smem_len = smem_len; ++ mutex_unlock(&gk_platform_fb0.lock); ++ ++ status = 0; ++ } else ++ if (fb_id == 1) { ++ mutex_lock(&gk_platform_fb1.lock); ++ gk_platform_fb1.screen_var.xres = xres; ++ gk_platform_fb1.screen_var.yres = yres; ++ gk_platform_fb1.screen_var.xres_virtual = xvirtual; ++ gk_platform_fb1.screen_var.yres_virtual = yvirtual; ++ gk_platform_fb1.screen_var.bits_per_pixel = ++ bits_per_pixel; ++ gk_platform_fb1.color_format = format; ++ gk_platform_fb1.use_prealloc = 1; ++ gk_platform_fb1.screen_fix.smem_start = smem_start; ++ gk_platform_fb1.screen_fix.smem_len = smem_len; ++ mutex_unlock(&gk_platform_fb1.lock); ++ ++ status = 0; ++ } ++ ++ pr_debug("%s %d: %dx%d %dx%d %d %d 0x%08x:0x%08x\n", __func__, fb_id, ++ xres, yres, xvirtual, yvirtual, ++ format, bits_per_pixel, smem_start, smem_len); ++ ++ return status; ++} ++#if 1 ++int __init gk_init_fb(void) ++{ ++ printk("init fb...\n"); ++ ++ mutex_init(&gk_platform_fb0.lock); ++ init_waitqueue_head(&gk_platform_fb0.proc_wait); ++ ++ mutex_init(&gk_platform_fb1.lock); ++ init_waitqueue_head(&gk_platform_fb1.proc_wait); ++ ++ return 0; ++} ++#endif ++ +diff --git a/arch/arm/plat-goke/gk_gpio.c b/arch/arm/plat-goke/gk_gpio.c +new file mode 100644 +index 00000000..68e7a446 +--- /dev/null ++++ b/arch/arm/plat-goke/gk_gpio.c +@@ -0,0 +1,1123 @@ ++/* ++ * arch/arm/mach-gk7101/gpio.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* ++ m instances per chip ++ n banks per instance ++ max 64 pins per bank ++ pin: used as pin number at chip ++ offset: used as offset at it's instance ++ pin = it's instance base number + offset ++*/ ++ ++static DEFINE_MUTEX(gk_gpio_mtx); ++extern struct gk_gpio_inst gk_gpio_insts[CONFIG_GK_GPIO_INSTANCES]; ++ ++void GH_GPIO_set_INPUT_CFG_in_sel(u8 index, u8 data) ++{ ++ GH_GPIO_INPUT_CFG_S in_data; ++ in_data.all = gk_gpio_insts[0].input_cfg[index]; ++ in_data.bitc.in_sel = data; ++ gk_gpio_insts[0].input_cfg[index] = in_data.all; ++ gk_gpio_writel(gk_gpio_insts[0].gpio_bank[0].base_reg + REG_GPIO_INPUT_CFG_OFFSET + (index * 0x4), in_data.all); ++} ++ ++/* ==========================================================================*/ ++#define to_gk_gpio_chip(c) \ ++ container_of(c, struct gk_gpio_bank, chip) ++ ++static struct gk_gpio_inst* gk_gpio_id_to_inst(u32 pin) ++{ ++ u32 i; ++ u32 j; ++ if (pin < 0) ++ { ++ return NULL; ++ } ++ else ++ { ++ for(i=0; i= gk_gpio_insts[i].gpio_bank[j].chip.base) && ++ (pin < (gk_gpio_insts[i].gpio_bank[j].chip.base + ++ gk_gpio_insts[i].gpio_bank[j].chip.ngpio))) ++ { ++ return &gk_gpio_insts[i]; ++ } ++ } ++ } ++ } ++ return NULL; ++} ++ ++static struct gk_gpio_bank* gk_gpio_id_to_bank(u32 pin) ++{ ++ u32 i; ++ u32 j; ++ if (pin< 0) ++ { ++ return NULL; ++ } ++ else ++ { ++ for(i=0; i= gk_gpio_insts[i].gpio_bank[j].chip.base) && ++ (pin < (gk_gpio_insts[i].gpio_bank[j].chip.base + ++ gk_gpio_insts[i].gpio_bank[j].chip.ngpio))) ++ { ++ return &gk_gpio_insts[i].gpio_bank[j]; ++ } ++ } ++ } ++ } ++ return NULL; ++} ++ ++ ++ ++int gk_gpio_request(struct gpio_chip *chip, u32 offset) ++{ ++ int ret = 0; ++ struct gk_gpio_bank *bank; ++ u32 pin; ++ ++ bank = to_gk_gpio_chip(chip); ++ mutex_lock(&gk_gpio_mtx); ++ ++ pin = offset + chip->base; ++ if (test_bit(pin, (const volatile unsigned long *) ++ gk_gpio_insts[bank->index].gpio_valid)) ++ { ++ if (test_bit(pin, (const volatile unsigned long *) ++ gk_gpio_insts[bank->index].gpio_freeflag)) ++ { ++ __clear_bit(pin, (volatile unsigned long *) ++ gk_gpio_insts[bank->index].gpio_freeflag); ++ } ++ else ++ { ++ ret = -EACCES; ++ } ++ } ++ else ++ { ++ ret = -EPERM; ++ } ++ ++ mutex_unlock(&gk_gpio_mtx); ++ ++ return ret; ++} ++ ++void gk_gpio_free(struct gpio_chip *chip, u32 offset) ++{ ++ u32 pin; ++ struct gk_gpio_bank *bank; ++ ++ mutex_lock(&gk_gpio_mtx); ++ ++ pin = offset + chip->base; ++ bank = to_gk_gpio_chip(chip); ++ ++ __set_bit(pin, (volatile unsigned long *) ++ gk_gpio_insts[bank->index].gpio_freeflag); ++ ++ mutex_unlock(&gk_gpio_mtx); ++} ++ ++int gk_gpio_func_config(u32 pin, u32 func) ++{ ++ int ret = 0; ++ unsigned long flags; ++ struct gk_gpio_bank *bank; ++ ++ bank = gk_gpio_id_to_bank(pin); ++ if (bank == NULL) ++ { ++ pr_err("%s: invalid GPIO %d for func %d.\n", __func__, pin, func); ++ return -EINVAL; ++ } ++ spin_lock_irqsave(&bank->lock, flags); ++ ++ if(GPIO_GET_FUNC(func) > GPIO_FUNC_INOUT) ++ { ++ pr_err("%s: invalid GPIO func %d for GPIO:%d.\n", __func__, func, pin); ++ spin_unlock_irqrestore(&bank->lock, flags); ++ return -EINVAL; ++ } ++ ++ //printk("gpio==============[%s %d]\n", __func__, __LINE__); ++ ret = gk_gpio_set_type(bank, pin, func); ++ spin_unlock_irqrestore(&bank->lock, flags); ++ ++ return ret; ++ ++} ++ ++int gk_gpio_direction_input(struct gpio_chip *chip, u32 offset, int val) ++{ ++ int ret = 0; ++ u32 pin; ++ ++ pin = offset + chip->base; ++ if (val == 0) ++ ret = gk_gpio_func_config(pin, GPIO_TYPE_INPUT_0); ++ else ++ ret = gk_gpio_func_config(pin, GPIO_TYPE_INPUT_1); ++ return ret; ++} ++ ++static inline int gk_gpio_inline_get(struct gk_gpio_bank *bank, u32 pin) ++{ ++ unsigned long flags; ++ u32 val = 0; ++ ++ spin_lock_irqsave(&bank->lock, flags); ++ ++ if((pin - bank->chip.base) < 32) ++ { ++ val = gk_gpio_readl(bank->base_reg + REG_GPIO_DIN_LOW_OFFSET); ++ } ++ else ++ { ++ val = gk_gpio_readl(bank->base_reg + REG_GPIO_DIN_HIGH_OFFSET); ++ } ++ ++ spin_unlock_irqrestore(&bank->lock, flags); ++ ++ val = (val >> (pin % 32)) & 0x1; ++ return (val ? GPIO_HIGH : GPIO_LOW); ++ ++} ++ ++int gk_gpio_get(u32 pin) ++{ ++ struct gk_gpio_bank *bank; ++ ++ bank = gk_gpio_id_to_bank(pin); ++ if (bank == NULL) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pin); ++ return 0; ++ } ++ ++ return gk_gpio_inline_get(bank, (u32)pin); ++} ++EXPORT_SYMBOL(gk_gpio_get); ++ ++int gk_gpio_get_ex(struct gpio_chip *chip, unsigned offset) ++{ ++ u32 pin; ++ ++ pin = offset + chip->base; ++ return gk_gpio_get(pin); ++} ++EXPORT_SYMBOL(gk_gpio_get_ex); ++ ++void gk_gpio_set_out(u32 pin, u32 value) ++{ ++ struct gk_gpio_bank* bank; ++ GH_GPIO_OUTPUT_CFG_S data; ++ bank = gk_gpio_id_to_bank(pin); ++ data.all = gk_gpio_insts[bank->index].output_cfg[pin]; ++ data.bitc.out_sel = 1; ++ if (value == GPIO_LOW) ++ { ++ data.bitc.out_sel &= ~0x01; ++ } ++ else ++ { ++ data.bitc.out_sel |= 0x01; ++ } ++ gk_gpio_writel(bank->base_reg + REG_GPIO_OUTPUT_CFG_OFFSET + ((pin - bank->chip.base) * 0x4), ++ data.all); ++ gk_gpio_insts[bank->index].output_cfg[pin] = data.all; ++} ++EXPORT_SYMBOL(gk_gpio_set_out); ++ ++static inline void gk_gpio_inline_set(struct gk_gpio_bank *bank, u32 pin, int value) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&bank->lock, flags); ++ gk_gpio_set_out(pin, value); ++ spin_unlock_irqrestore(&bank->lock, flags); ++} ++ ++int gk_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) ++{ ++ int ret = 0; ++ u32 pin; ++ struct gk_gpio_bank *bank; ++ ++ pin = offset + chip->base; ++ ++ bank = gk_gpio_id_to_bank(pin); ++ ret = gk_gpio_func_config(pin, val ? GPIO_TYPE_OUTPUT_1 : GPIO_TYPE_OUTPUT_0); ++ gk_gpio_inline_set(bank, pin, val); ++ ++ return ret; ++} ++ ++void gk_gpio_set(struct gpio_chip *chip, unsigned offset, int val) ++{ ++ struct gk_gpio_bank *bank; ++ u32 pin; ++ ++ pin = offset + chip->base; ++ ++ bank = gk_gpio_id_to_bank(pin); ++ if (bank == NULL) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pin); ++ return; ++ } ++ gk_gpio_inline_set(bank, pin, val); ++} ++EXPORT_SYMBOL(gk_gpio_set); ++ ++int gk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ struct gk_gpio_bank *bank; ++ u32 pin; ++ pin = offset + chip->base; ++ ++ bank = to_gk_gpio_chip(chip); ++ return gk_gpio_insts[bank->index].irq_no; ++} ++ ++void gk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ++{ ++ int i; ++ struct gk_gpio_bank *bank; ++ u32 afsel; ++ u32 lmask; ++ u32 data; ++ u32 hmask; ++ unsigned long flags; ++ ++ bank = to_gk_gpio_chip(chip); ++ ++ spin_lock_irqsave(&bank->lock, flags); ++ afsel = gk_gpio_readl(gk_gpio_insts[bank->index].base_bus + REG_GPIO_PER_SEL_OFFSET); ++ lmask = gk_gpio_readl(bank->base_reg + REG_GPIO_IE_LOW_OFFSET); ++ hmask = gk_gpio_readl(bank->base_reg + REG_GPIO_IE_HIGH_OFFSET); ++ data = gk_gpio_readl(gk_gpio_insts[bank->index].base_bus + REG_GPIO_INT_EN_OFFSET); ++ spin_unlock_irqrestore(&bank->lock, flags); ++ ++ seq_printf(s, "GPIO_BASE:\t0x%08X\n", bank->base_reg); ++ seq_printf(s, "GPIO_PSEL:\t0x%08X\n", afsel); ++ seq_printf(s, "GPIO_MASK:\t0x%08X:0x%08X\n", hmask, lmask); ++ seq_printf(s, "GPIO_GPEN:\t0x%08X\n", data); ++ ++ for (i = 0; i < chip->ngpio; i++) ++ { ++ seq_printf(s, "GPIO %d: HW\n", (chip->base + i)); ++ } ++} ++ ++int gk_gpio_set_type(struct gk_gpio_bank* bank, u32 pin, u32 type) ++{ ++ GH_GPIO_OUTPUT_CFG_S out_data; ++ GH_GPIO_INPUT_CFG_S in_data; ++ GH_PLL_IOCTRL_GPIO_S io_data; ++ out_data.all = gk_gpio_insts[bank->index].output_cfg[pin]; ++ switch(GPIO_GET_FUNC(type)) ++ { ++ case GPIO_FUNC_OUT: // out ++ out_data.bitc.out_sel = GPIO_GET_OUT_SEL(type); ++ out_data.bitc.oen_sel = GPIO_GET_OEN_SEL(type); ++ break; ++ case GPIO_FUNC_IN: // in ++ if(GPIO_GET_IN_SEL(type) >= 2) ++ { ++ out_data.bitc.out_sel = GPIO_GET_OUT_SEL(type); ++ out_data.bitc.oen_sel = GPIO_GET_OEN_SEL(type); ++ in_data.all = gk_gpio_insts[bank->index].input_cfg[GPIO_GET_IN_SEL(type) - 2]; ++ in_data.bitc.in_sel = pin; ++ gk_gpio_writel(bank->base_reg + REG_GPIO_INPUT_CFG_OFFSET + ((GPIO_GET_IN_SEL(type) - 2) * 0x4), ++ in_data.all); ++ gk_gpio_insts[bank->index].input_cfg[GPIO_GET_IN_SEL(type) - 2] = in_data.all; ++ } ++ else ++ { ++ out_data.bitc.out_sel = GPIO_GET_OUT_SEL(type); ++ out_data.bitc.oen_sel = GPIO_GET_OEN_SEL(type); ++ } ++ break; ++ case GPIO_FUNC_INOUT: // in+out ++ // don't change, otherwise if out_sel at first might output a 0, then change to 1 ++ in_data.all = gk_gpio_insts[bank->index].input_cfg[GPIO_GET_IN_SEL(type) - 2]; ++ in_data.bitc.in_sel = pin; ++ gk_gpio_writel(bank->base_reg + REG_GPIO_INPUT_CFG_OFFSET + ((GPIO_GET_IN_SEL(type) - 2) * 0x4), ++ in_data.all); ++ gk_gpio_insts[bank->index].input_cfg[GPIO_GET_IN_SEL(type) - 2] = in_data.all; ++ out_data.bitc.oen_sel = GPIO_GET_OEN_SEL(type); ++ out_data.bitc.out_sel = GPIO_GET_OUT_SEL(type); ++ break; ++ default: ++ return -EINVAL; ++ } ++ out_data.bitc.oen_invert = GPIO_GET_OEN_INVERT(type); ++ out_data.bitc.out_invert = GPIO_GET_OUT_INVERT(type); ++ gk_gpio_writel(bank->base_reg + REG_GPIO_OUTPUT_CFG_OFFSET + ((pin - bank->chip.base) * 0x4), ++ out_data.all); ++ gk_gpio_insts[bank->index].output_cfg[pin] = out_data.all; ++ // Pull up/down & 2mA...... ++#if defined(CONFIG_ARCH_GK710XS) ++ if(pin<4)//gpio0-3 ++ { ++ io_data.all = gk_gpio_readl((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04))); ++ switch(pin%4) ++ { ++ case 0: ++ io_data.bitc.io2 = GPIO_GET_IOCTRL(type); ++ break; ++ case 1: ++ io_data.bitc.io0 = GPIO_GET_IOCTRL(type); ++ break; ++ case 2: ++ io_data.bitc.io1 = GPIO_GET_IOCTRL(type); ++ break; ++ case 3: ++ io_data.bitc.io3 = GPIO_GET_IOCTRL(type); ++ break; ++ } ++ gk_gpio_writel((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04)), io_data.all); ++ } ++ else if(pin<52)//gpio4-51 ++ { ++ io_data.all = gk_gpio_readl((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04))); ++ switch(pin%4) ++ { ++ case 0: ++ io_data.bitc.io1 = GPIO_GET_IOCTRL(type); ++ break; ++ case 1: ++ io_data.bitc.io2 = GPIO_GET_IOCTRL(type); ++ break; ++ case 2: ++ io_data.bitc.io0 = GPIO_GET_IOCTRL(type); ++ break; ++ case 3: ++ io_data.bitc.io3 = GPIO_GET_IOCTRL(type); ++ break; ++ } ++ gk_gpio_writel((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04)), io_data.all); ++ ++ } ++ else if(pin<56)//gpio52-55 ++ { ++ io_data.all = gk_gpio_readl((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04))); ++ switch(pin%4) ++ { ++ case 0: ++ io_data.bitc.io1 = GPIO_GET_IOCTRL(type); ++ break; ++ case 1: ++ io_data.bitc.io0 = GPIO_GET_IOCTRL(type); ++ break; ++ case 2: ++ io_data.bitc.io2 = GPIO_GET_IOCTRL(type); ++ break; ++ case 3: ++ io_data.bitc.io3 = GPIO_GET_IOCTRL(type); ++ break; ++ } ++ gk_gpio_writel((bank->io_reg + ((((55-pin)-bank->chip.base)/0x04) * 0x04)), io_data.all); ++ } ++ else//gpio56-62 ++ { ++ io_data.all = gk_gpio_readl((bank->io_reg + (((pin-bank->chip.base)/0x04) * 0x04))); ++ switch(pin%4) ++ { ++ case 0: ++ io_data.bitc.io0 = GPIO_GET_IOCTRL(type); ++ break; ++ case 1: ++ io_data.bitc.io1 = GPIO_GET_IOCTRL(type); ++ break; ++ case 2: ++ io_data.bitc.io2 = GPIO_GET_IOCTRL(type); ++ break; ++ case 3: ++ io_data.bitc.io3 = GPIO_GET_IOCTRL(type); ++ break; ++ } ++ gk_gpio_writel((bank->io_reg + (((pin-bank->chip.base)/0x04) * 0x04)), io_data.all); ++ } ++#else ++ io_data.all = gk_gpio_readl((bank->io_reg - (((pin-bank->chip.base)/0x04) * 0x04))); ++ switch(pin%4) ++ { ++ case 0: ++ io_data.bitc.io0 = GPIO_GET_IOCTRL(type); ++ break; ++ case 1: ++ io_data.bitc.io1 = GPIO_GET_IOCTRL(type); ++ break; ++ case 2: ++ io_data.bitc.io2 = GPIO_GET_IOCTRL(type); ++ break; ++ case 3: ++ io_data.bitc.io3 = GPIO_GET_IOCTRL(type); ++ break; ++ } ++ gk_gpio_writel((bank->io_reg - (((pin-bank->chip.base)/0x04) * 0x04)), io_data.all); ++#endif ++ ++ return(0); ++} ++ ++void gk_gpio_config(u32 pin, u32 func) ++{ ++ if(gk_gpio_func_config((u32)pin, func)) ++ { ++ pr_err("%s: failed to configure GPIO %d for func %d.\n", __func__, pin, func); ++ } ++} ++EXPORT_SYMBOL(gk_gpio_config); ++ ++void gk_gpio_raw_lock(u32 pin, unsigned long *pflags) ++{ ++ struct gk_gpio_bank *bank; ++ bank = gk_gpio_id_to_bank(pin); ++ if (bank == NULL) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pin); ++ return; ++ } ++ spin_lock_irqsave(&bank->lock, *pflags); ++} ++ ++void gk_gpio_raw_unlock(u32 pin, unsigned long *pflags) ++{ ++ struct gk_gpio_bank *bank; ++ bank = gk_gpio_id_to_bank(pin); ++ if (bank == NULL) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pin); ++ return; ++ } ++ spin_unlock_irqrestore(&bank->lock, *pflags); ++} ++ ++u32 gk_gpio_suspend(u32 level) ++{ ++ u32 i; ++ u32 j; ++ unsigned long flags; ++ ++ for (i = 0; i < CONFIG_GK_GPIO_INSTANCES; i++) ++ { ++ for (j = 0; j < gk_gpio_insts[i].bank_num; j++) ++ { ++ spin_lock_irqsave(&gk_gpio_insts[i].gpio_bank[j].lock, flags); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.isl_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IS_LOW_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ish_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IS_HIGH_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ibel_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IBE_LOW_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ibeh_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IBE_HIGH_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ievl_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IEV_LOW_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ievh_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IEV_HIGH_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.iel_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IE_LOW_OFFSET); ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ieh_reg = ++ gk_gpio_readl(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IE_HIGH_OFFSET); ++ spin_unlock_irqrestore(&gk_gpio_insts[i].gpio_bank[j].lock, flags); ++ } ++ gk_gpio_insts[i].per_sel_reg = ++ gk_gpio_readl(gk_gpio_insts[i].base_bus + REG_GPIO_PER_SEL_OFFSET); ++ gk_gpio_writel(gk_gpio_insts[i].base_bus + REG_GPIO_INT_EN_OFFSET, 0x00000000); ++ } ++ ++ return 0; ++} ++ ++u32 gk_gpio_resume(u32 level) ++{ ++ u32 i; ++ u32 j; ++ unsigned long flags; ++ ++ for (i = 0; i < CONFIG_GK_GPIO_INSTANCES; i++) ++ { ++ for (j = 0; j < gk_gpio_insts[i].bank_num; j++) ++ { ++ spin_lock_irqsave(&gk_gpio_insts[i].gpio_bank[j].lock, flags); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IS_LOW_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.isl_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IS_HIGH_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ish_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IBE_LOW_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ibel_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IBE_HIGH_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ibeh_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IEV_LOW_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ievl_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IEV_HIGH_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ievh_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IE_LOW_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.iel_reg); ++ gk_gpio_writel(gk_gpio_insts[i].gpio_bank[j].base_reg + REG_GPIO_IE_HIGH_OFFSET, ++ gk_gpio_insts[i].gpio_bank[j].pm_info.ieh_reg); ++ spin_unlock_irqrestore(&gk_gpio_insts[i].gpio_bank[j].lock, flags); ++ } ++ gk_gpio_writel(gk_gpio_insts[i].base_bus + REG_GPIO_PER_SEL_OFFSET, ++ gk_gpio_insts[i].per_sel_reg); ++ gk_gpio_writel(gk_gpio_insts[i].base_bus + REG_GPIO_INT_EN_OFFSET, 0x00000001); ++ } ++ return 0; ++} ++ ++int gk_set_gpio_output_can_sleep(struct gk_gpio_io_info *pinfo, u32 on, int can_sleep) ++{ ++ if (pinfo == NULL) ++ { ++ pr_err("%s: pinfo is NULL.\n", __func__); ++ return -1; ++ } ++ if (pinfo->gpio_id < 0 ) ++ { ++ pr_debug("%s: wrong gpio id %d.\n", __func__, pinfo->gpio_id); ++ return -1; ++ } ++ ++ pr_debug("%s: Gpio[%d] %s, level[%s], delay[%dms].\n", __func__, ++ pinfo->gpio_id, on ? "ON" : "OFF", ++ pinfo->active_level ? "HIGH" : "LOW", ++ pinfo->active_delay); ++ if (pinfo->gpio_id >= CONFIG_ARCH_NR_GPIO) ++ { ++ pr_debug("%s: try expander gpio id %d.\n", ++ __func__, pinfo->gpio_id); ++ return -1; ++ } ++ else ++ { ++ if (on) ++ { ++ gk_gpio_config(pinfo->gpio_id, pinfo->active_level ? GPIO_TYPE_OUTPUT_1 : GPIO_TYPE_OUTPUT_0); ++ gk_gpio_set_out(pinfo->gpio_id, pinfo->active_level); ++ } ++ else ++ { ++ gk_gpio_config(pinfo->gpio_id, pinfo->active_level ? GPIO_TYPE_OUTPUT_0 : GPIO_TYPE_OUTPUT_1); ++ gk_gpio_set_out(pinfo->gpio_id, !pinfo->active_level); ++ } ++ } ++ if (can_sleep) ++ { ++ msleep(pinfo->active_delay); ++ } ++ else ++ { ++ mdelay(pinfo->active_delay); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_set_gpio_output_can_sleep); ++ ++u32 gk_get_gpio_input_can_sleep(struct gk_gpio_io_info *pinfo, int can_sleep) ++{ ++ u32 gpio_value = 0; ++ ++ if (pinfo == NULL) ++ { ++ pr_err("%s: pinfo is NULL.\n", __func__); ++ goto gk_get_gpio_input_can_sleep_exit; ++ } ++ if (pinfo->gpio_id < 0 ) ++ { ++ pr_debug("%s: wrong gpio id %d.\n", __func__, pinfo->gpio_id); ++ goto gk_get_gpio_input_can_sleep_exit; ++ } ++ ++ if (pinfo->gpio_id >= CONFIG_ARCH_NR_GPIO) ++ { ++ pr_debug("%s: try expander gpio id %d.\n", ++ __func__, pinfo->gpio_id); ++ goto gk_get_gpio_input_can_sleep_exit; ++ } ++ else ++ { ++ gk_gpio_config(pinfo->gpio_id, pinfo->active_level ? GPIO_TYPE_OUTPUT_1 : GPIO_TYPE_OUTPUT_0); ++ if (can_sleep) ++ { ++ msleep(pinfo->active_delay); ++ } ++ else ++ { ++ mdelay(pinfo->active_delay); ++ } ++ gpio_value = gk_gpio_get(pinfo->gpio_id); ++ } ++ ++ pr_debug("%s: {gpio[%d], level[%s], delay[%dms]} get[%d].\n", ++ __func__, pinfo->gpio_id, ++ pinfo->active_level ? "HIGH" : "LOW", ++ pinfo->active_delay, gpio_value); ++ ++gk_get_gpio_input_can_sleep_exit: ++ return (gpio_value == pinfo->active_level) ? 1 : 0; ++} ++EXPORT_SYMBOL(gk_get_gpio_input_can_sleep); ++ ++int gk_set_gpio_reset_can_sleep(struct gk_gpio_io_info *pinfo, int can_sleep) ++{ ++ int ret = 0; ++ ++ if (pinfo == NULL) ++ { ++ pr_err("%s: pinfo is NULL.\n", __func__); ++ ret = -1; ++ goto gk_set_gpio_reset_can_sleep_exit; ++ } ++ if (pinfo->gpio_id < 0 ) ++ { ++ pr_debug("%s: wrong gpio id %d.\n", __func__, pinfo->gpio_id); ++ ret = -1; ++ goto gk_set_gpio_reset_can_sleep_exit; ++ } ++ ++ pr_debug("%s: Reset gpio[%d], level[%s], delay[%dms].\n", ++ __func__, pinfo->gpio_id, ++ pinfo->active_level ? "HIGH" : "LOW", ++ pinfo->active_delay); ++ if (pinfo->gpio_id >= CONFIG_ARCH_NR_GPIO) ++ { ++ pr_debug("%s: try expander gpio id %d.\n", ++ __func__, pinfo->gpio_id); ++ ret = -1; ++ goto gk_set_gpio_reset_can_sleep_exit; ++ } ++ else ++ { ++ gk_gpio_config(pinfo->gpio_id, GPIO_TYPE_OUTPUT_0); ++ gk_gpio_set_out(pinfo->gpio_id, pinfo->active_level); ++ if (can_sleep) ++ { ++ msleep(pinfo->active_delay); ++ } ++ else ++ { ++ mdelay(pinfo->active_delay); ++ } ++ gk_gpio_set_out(pinfo->gpio_id, !pinfo->active_level); ++ if (can_sleep) ++ { ++ msleep(pinfo->active_delay); ++ } ++ else ++ { ++ mdelay(pinfo->active_delay); ++ } ++ } ++ ++gk_set_gpio_reset_can_sleep_exit: ++ return ret; ++} ++EXPORT_SYMBOL(gk_set_gpio_reset_can_sleep); ++ ++int gk_set_gpio_output(struct gk_gpio_io_info *pinfo, u32 on) ++{ ++ return gk_set_gpio_output_can_sleep(pinfo, on, 0); ++} ++EXPORT_SYMBOL(gk_set_gpio_output); ++ ++u32 gk_get_gpio_input(struct gk_gpio_io_info *pinfo) ++{ ++ return gk_get_gpio_input_can_sleep(pinfo, 0); ++} ++EXPORT_SYMBOL(gk_get_gpio_input); ++ ++int gk_set_gpio_reset(struct gk_gpio_io_info *pinfo) ++{ ++ return gk_set_gpio_reset_can_sleep(pinfo, 0); ++} ++EXPORT_SYMBOL(gk_set_gpio_reset); ++ ++int gk_is_valid_gpio_irq(struct gk_gpio_irq_info *pinfo) ++{ ++ struct gk_gpio_inst *gpio_inst; ++ struct gk_gpio_bank *gpio_bank; ++ if (pinfo == NULL) ++ { ++ printk("%s: pinfo is NULL.\n", __func__); ++ return 0; ++ } ++ ++ gpio_inst = gk_gpio_id_to_inst(pinfo->pin); ++ gpio_bank = gk_gpio_id_to_bank(pinfo->pin); ++ if ((gpio_bank == NULL) || (gpio_inst == NULL)) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pinfo->pin); ++ return 0; ++ } ++ ++ if ((pinfo->type != IRQ_TYPE_EDGE_RISING) && ++ (pinfo->type != IRQ_TYPE_EDGE_FALLING) && ++ (pinfo->type != IRQ_TYPE_EDGE_BOTH) && ++ (pinfo->type != IRQ_TYPE_LEVEL_HIGH) && ++ (pinfo->type != IRQ_TYPE_LEVEL_LOW)) ++ return 0; ++ ++ return 1; ++} ++EXPORT_SYMBOL(gk_is_valid_gpio_irq); ++ ++static irqreturn_t gk_gpio_irq(int irq, void *dev) ++{ ++ struct gk_gpio_inst *gpio_inst; ++ struct gk_gpio_bank *gpio_bank; ++ struct gk_gpio_irq_info *pinfo = (struct gk_gpio_irq_info*)dev; ++ unsigned long flags; ++ u32 misl_reg; ++ u32 mish_reg; ++ u32 index; ++ u32 mask = 1; ++ u32 i = 1; ++ mdelay(20); ++ ++ if (pinfo == NULL) ++ { ++ pr_err("%s: pinfo is NULL.\n", __func__); ++ return IRQ_NONE; ++ } ++ gpio_inst = gk_gpio_id_to_inst(pinfo->pin); ++ if (gpio_inst == NULL) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pinfo->pin); ++ return IRQ_NONE; ++ } ++ for(i=0;ibank_num;i++) ++ { ++ gpio_bank = &gpio_inst->gpio_bank[i]; ++ spin_lock_irqsave(&gpio_bank->lock, flags); ++ misl_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_MIS_LOW_OFFSET); ++ mish_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_MIS_HIGH_OFFSET); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IC_LOW_OFFSET, misl_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IC_HIGH_OFFSET, mish_reg); ++ spin_unlock_irqrestore(&gpio_bank->lock, flags); ++ ++ for(index=0; index < 32; index++) ++ { ++ if(misl_reg & mask) ++ { ++ pinfo[index+gpio_bank->chip.base].val = gk_gpio_inline_get(gpio_bank, index+gpio_bank->chip.base); ++ if (pinfo[index+gpio_bank->chip.base].handler) ++ { ++ pinfo[index+gpio_bank->chip.base].handler(irq, &pinfo[index+gpio_bank->chip.base]); ++ } ++ } ++ if(mish_reg & mask) ++ { ++ pinfo[index + gpio_bank->chip.base + 32].val = gk_gpio_inline_get(gpio_bank, index+gpio_bank->chip.base + 32); ++ if (pinfo[index + gpio_bank->chip.base + 32].handler) ++ { ++ pinfo[index + gpio_bank->chip.base + 32].handler(irq, &pinfo[index + gpio_bank->chip.base + 32]); ++ } ++ } ++ mask <<= 1; ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++int gk_gpio_request_irq(struct gk_gpio_irq_info *pinfo) ++{ ++ struct gk_gpio_inst *gpio_inst; ++ struct gk_gpio_bank *gpio_bank; ++ u32 mask; ++ u32 offset; ++ unsigned long flags; ++ if (pinfo == NULL) ++ { ++ pr_err("%s: pinfo is NULL.\n", __func__); ++ return -1; ++ } ++ ++ gpio_inst = gk_gpio_id_to_inst(pinfo->pin); ++ gpio_bank = gk_gpio_id_to_bank(pinfo->pin); ++ if ((gpio_bank == NULL) || (gpio_inst == NULL)) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pinfo->pin); ++ return -1; ++ } ++ spin_lock_irqsave(&gpio_bank->lock, flags); ++ memcpy(&gpio_inst->irq_info[pinfo->pin], pinfo, sizeof(struct gk_gpio_irq_info)); ++ gk_gpio_writel(gpio_inst->base_bus + REG_GPIO_INT_EN_OFFSET, 0x00); ++ mask = 0x01<<(pinfo->pin % 0x20); ++ offset = pinfo->pin - gpio_bank->chip.base; ++ if(offset / 0x20) ++ { ++ gpio_bank->pm_info.ish_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IS_HIGH_OFFSET); ++ gpio_bank->pm_info.ibeh_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IBE_HIGH_OFFSET); ++ gpio_bank->pm_info.ievh_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IEV_HIGH_OFFSET); ++ gpio_bank->pm_info.ieh_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IE_HIGH_OFFSET); ++ ++ gpio_bank->pm_info.ieh_reg |= mask; ++ switch(pinfo->type) ++ { ++ case IRQ_TYPE_LEVEL_LOW: ++ gpio_bank->pm_info.ish_reg |= mask; ++ gpio_bank->pm_info.ibeh_reg &= ~mask; ++ gpio_bank->pm_info.ievh_reg &= ~mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ gpio_bank->pm_info.ish_reg |= mask; ++ gpio_bank->pm_info.ibeh_reg &= ~mask; ++ gpio_bank->pm_info.ievh_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_0); ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ gpio_bank->pm_info.ish_reg &= ~mask; ++ gpio_bank->pm_info.ibeh_reg &= ~mask; ++ gpio_bank->pm_info.ievh_reg &= ~mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ gpio_bank->pm_info.ish_reg &= ~mask; ++ gpio_bank->pm_info.ibeh_reg &= ~mask; ++ gpio_bank->pm_info.ievh_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_0); ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ gpio_bank->pm_info.ish_reg &= ~mask; ++ gpio_bank->pm_info.ibeh_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ } ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IS_HIGH_OFFSET, gpio_bank->pm_info.ish_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IBE_HIGH_OFFSET, gpio_bank->pm_info.ibeh_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IEV_HIGH_OFFSET, gpio_bank->pm_info.ievh_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IE_HIGH_OFFSET, gpio_bank->pm_info.ieh_reg); ++ } ++ else ++ { ++ gpio_bank->pm_info.isl_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IS_LOW_OFFSET); ++ gpio_bank->pm_info.ibel_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IBE_LOW_OFFSET); ++ gpio_bank->pm_info.ievl_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IEV_LOW_OFFSET); ++ gpio_bank->pm_info.iel_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IE_LOW_OFFSET); ++ ++ gpio_bank->pm_info.iel_reg |= mask; ++ switch(pinfo->type) ++ { ++ case IRQ_TYPE_LEVEL_LOW: ++ gpio_bank->pm_info.isl_reg |= mask; ++ gpio_bank->pm_info.ibel_reg &= ~mask; ++ gpio_bank->pm_info.ievl_reg &= ~mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ gpio_bank->pm_info.isl_reg |= mask; ++ gpio_bank->pm_info.ibel_reg &= ~mask; ++ gpio_bank->pm_info.ievl_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_0); ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ gpio_bank->pm_info.isl_reg &= ~mask; ++ gpio_bank->pm_info.ibel_reg &= ~mask; ++ gpio_bank->pm_info.ievl_reg &= ~mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ gpio_bank->pm_info.isl_reg &= ~mask; ++ gpio_bank->pm_info.ibel_reg &= ~mask; ++ gpio_bank->pm_info.ievl_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_0); ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ gpio_bank->pm_info.isl_reg &= ~mask; ++ gpio_bank->pm_info.ibel_reg |= mask; ++ gk_gpio_set_type(gpio_bank, pinfo->pin, GPIO_TYPE_INPUT_1); ++ break; ++ } ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IS_LOW_OFFSET, gpio_bank->pm_info.isl_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IBE_LOW_OFFSET, gpio_bank->pm_info.ibel_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IEV_LOW_OFFSET, gpio_bank->pm_info.ievl_reg); ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IE_LOW_OFFSET, gpio_bank->pm_info.iel_reg); ++ } ++ __set_bit(offset, (volatile unsigned long *)gpio_inst->irq_flag); ++ if(gpio_inst->irq_now == 0x00) ++ { ++ request_irq(gpio_inst->irq_no, gk_gpio_irq, IRQF_TRIGGER_HIGH, "gpio_irq", (void*)(&gpio_inst->irq_info[0])); ++ gpio_inst->irq_now = 0x01; ++ gk_gpio_writel(gpio_inst->base_bus + REG_GPIO_INT_EN_OFFSET, 0x01); ++ } ++ spin_unlock_irqrestore(&gpio_bank->lock, flags); ++ return 0; ++} ++EXPORT_SYMBOL(gk_gpio_request_irq); ++ ++int gk_gpio_release_irq(u32 pin) ++{ ++ struct gk_gpio_inst *gpio_inst; ++ struct gk_gpio_bank *gpio_bank; ++ u32 mask, i; ++ u32 offset; ++ unsigned long flags; ++ ++ gpio_inst = gk_gpio_id_to_inst(pin); ++ gpio_bank = gk_gpio_id_to_bank(pin); ++ if ((gpio_bank == NULL) || (gpio_inst == NULL)) ++ { ++ pr_err("%s: invalid GPIO %d.\n", __func__, pin); ++ return -1; ++ } ++ spin_lock_irqsave(&gpio_bank->lock, flags); ++ memset(&gpio_inst->irq_info[pin], 0x00, sizeof(struct gk_gpio_irq_info)); ++ ++ offset = pin - gpio_bank->chip.base; ++ mask = 0x01<<(offset % 0x20); ++ if(offset / 0x20) ++ { ++ gpio_bank->pm_info.ieh_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IE_HIGH_OFFSET); ++ gpio_bank->pm_info.ieh_reg &= ~mask; ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IE_HIGH_OFFSET, gpio_bank->pm_info.ieh_reg); ++ } ++ else ++ { ++ gpio_bank->pm_info.iel_reg = gk_gpio_readl(gpio_bank->base_reg + REG_GPIO_IE_LOW_OFFSET); ++ gpio_bank->pm_info.iel_reg &= ~mask; ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_IE_LOW_OFFSET, gpio_bank->pm_info.iel_reg); ++ } ++ __clear_bit(offset, (volatile unsigned long *)gpio_inst->irq_flag); ++ offset = 0; ++ for (i = 0; i < (sizeof(gpio_inst->irq_flag) /sizeof(gpio_inst->irq_flag[0])); i++) ++ { ++ if(gpio_inst->irq_flag[i] != 0) ++ { ++ offset = 1; ++ break; ++ } ++ } ++ if(!offset) ++ { ++ gk_gpio_writel(gpio_bank->base_reg + REG_GPIO_INT_EN_OFFSET, 0x00); ++ } ++ spin_unlock_irqrestore(&gpio_bank->lock, flags); ++ return 0; ++} ++EXPORT_SYMBOL(gk_gpio_release_irq); ++ ++int __init goke_init_gpio(void) ++{ ++ u32 i,j,ret=0; ++ for(i=0;i ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++gpio_cfg_t gk_all_gpio_cfg; ++ ++struct gk_gpio_bank gk_gpio0_banks[] = ++{ ++ GK_GPIO_BANK("gk-gpio0", GPIO0_BANK0_BASE, GPIO0_BANK0_PLL_IOCTRL_BASE, ++ GK_GPIO(0 * GPIO_BANK_SIZE), CONFIG_ARCH_NR_GPIO, 0), ++}; ++// last one max = CONFIG_ARCH_NR_GPIO - base ++ ++struct gk_gpio_inst gk_gpio_insts[CONFIG_GK_GPIO_INSTANCES] = ++{ ++ [0] = ++ { ++ .bank_num = ARRAY_SIZE(gk_gpio0_banks), ++ .gpio_bank = gk_gpio0_banks, ++ .output_cfg = {0}, ++ .input_cfg = {0}, ++ .irq_no = GPIO0_IRQ, ++ .irq_info = {{0}}, ++ .irq_now = 0, ++ .gpio_valid = {0}, ++ .gpio_freeflag = {0}, ++ .irq_flag = {0}, ++ .base_bus = GPIO0_BASE, ++ .per_sel_reg = 0, ++ }, ++}; ++ ++int __init gk_init_gpio(void) ++{ ++ int retval = 0; ++ int i, index; ++ int gpio_count; ++ ++ const char chip_type[][8] = ++ { ++ {"GK7101"}, ++ {"GK7102"}, ++ {"GK7101S"}, ++ {"GK7102S"} ++ }; ++ ++ /* use usr memory's GPIO setting by uboot pass*/ ++ u32 usrmemphyaddr=0; ++ int intphy_gpio_count; ++ int extphy_gpio_count; ++ ++ usrmemphyaddr=get_usrmem_virt(); ++ memcpy((u8*)&gk_all_gpio_cfg,(u8*)usrmemphyaddr,sizeof(gk_all_gpio_cfg)); ++ gk_all_gpio_cfg.board_type[31] = '\0'; ++ /*get gpio configure infor*/ ++ gpio_count = gk_all_gpio_cfg.gpio_count; ++ intphy_gpio_count = gk_all_gpio_cfg.intphy_gpio_count; ++ extphy_gpio_count = gk_all_gpio_cfg.extphy_gpio_count; ++ ++#if 1 ++ printk("###################################\n"); ++ if(gk_all_gpio_cfg.soc_type >= sizeof(chip_type)/ sizeof(chip_type[0])) ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", "Unknown",gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version>> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ else ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", chip_type[gk_all_gpio_cfg.soc_type],gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version >> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ if (gk_all_gpio_cfg.ext_phy_clk == 0) ++ printk("[NET INT_CLK] Internal PHY clock \n"); ++ else ++ printk("[NET EXT_CLK] External PHY clock %dMHz \n", gk_all_gpio_cfg.ext_phy_clk); ++ printk("[GPIO]#############################\n"); ++ printk("[GPIO] gpio map get from uboot\n"); ++ printk("[GPIO CFG] gpio count = %d\n",gk_all_gpio_cfg.gpio_count); ++ printk("[GPIO CFG] intphy count = %d\n",gk_all_gpio_cfg.intphy_gpio_count); ++ printk("[GPIO CFG] extphy count = %d\n",gk_all_gpio_cfg.extphy_gpio_count); ++ printk("[GPIO CFG] IR LED CTL (%d)\n",gk_all_gpio_cfg.ir_led_ctl); ++ printk("[GPIO CFG] IR CUT1 (%d)\n",gk_all_gpio_cfg.ir_cut1); ++ printk("[GPIO CFG] IR CUT2 (%d)\n",gk_all_gpio_cfg.ir_cut2); ++ printk("[GPIO CFG] SENSOR Reset (%d)\n",gk_all_gpio_cfg.sensor_reset); ++ printk("[GPIO CFG] PHY Reset (%d)\n",gk_all_gpio_cfg.phy_reset); ++ printk("[GPIO CFG] PHY Speed Led (%d)\n",gk_all_gpio_cfg.phy_speed_led); ++ printk("[GPIO CFG] SPI0 EN (%d)\n",gk_all_gpio_cfg.spi0_en0); ++ printk("[GPIO CFG] SPI1 EN (%d)\n",gk_all_gpio_cfg.spi1_en0); ++ printk("[GPIO CFG] USB HOST (%d)\n",gk_all_gpio_cfg.usb_host); ++ printk("[GPIO CFG] SD Detect (%d)\n",gk_all_gpio_cfg.sd_detect); ++ printk("[GPIO CFG] SD Power (%d)\n",gk_all_gpio_cfg.sd_power); ++ printk("[GPIO]#############################\n"); ++#endif ++ ++ goke_init_gpio(); ++ ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.gpio_chip[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.gpio_chip[index].pin, gk_all_gpio_cfg.gpio_chip[index].type); ++ } ++ } ++ ++ if(cmdline_phytype == 0) ++ { ++ gpio_count = intphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.int_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.int_phy_gpio[index].pin, gk_all_gpio_cfg.int_phy_gpio[index].type); ++ } ++ } ++ } ++ else ++ { ++ gpio_count = extphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.ext_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.ext_phy_gpio[index].pin, gk_all_gpio_cfg.ext_phy_gpio[index].type); ++ } ++ } ++ } ++ ++ for(i=0;i ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++gpio_cfg_t gk_all_gpio_cfg; ++ ++struct gk_gpio_bank gk_gpio0_banks[] = ++{ ++ GK_GPIO_BANK("gk-gpio0", GPIO0_BANK0_BASE, GPIO0_BANK0_PLL_IOCTRL_BASE, ++ GK_GPIO(0 * GPIO_BANK_SIZE), GPIO_BANK_SIZE, 0), ++ GK_GPIO_BANK("gk-gpio1", GPIO0_BANK1_BASE, GPIO0_BANK1_PLL_IOCTRL_BASE, ++ GK_GPIO(1 * GPIO_BANK_SIZE), CONFIG_ARCH_NR_GPIO - GK_GPIO(1 * GPIO_BANK_SIZE), 0), ++}; ++// last one max = CONFIG_ARCH_NR_GPIO - base ++ ++struct gk_gpio_inst gk_gpio_insts[CONFIG_GK_GPIO_INSTANCES] = ++{ ++ [0] = ++ { ++ .bank_num = ARRAY_SIZE(gk_gpio0_banks), ++ .gpio_bank = gk_gpio0_banks, ++ .output_cfg = {0}, ++ .input_cfg = {0}, ++ .irq_no = GPIO0_IRQ, ++ .irq_info = {0}, ++ .irq_now = 0, ++ .gpio_valid = {0}, ++ .gpio_freeflag = {0}, ++ .irq_flag = {0}, ++ .base_bus = GPIO0_BASE, ++ .per_sel_reg = 0, ++ }, ++}; ++ ++int __init gk_init_gpio(void) ++{ ++ int retval = 0; ++ int i, index; ++ int gpio_count; ++ ++ const char chip_type[][8] = ++ { ++ {"GK7101"}, ++ {"GK7102"}, ++ {"GK7101S"}, ++ {"GK7102S"} ++ }; ++ ++ /* use usr memory's GPIO setting by uboot pass*/ ++ u32 usrmemphyaddr=0; ++ int intphy_gpio_count; ++ int extphy_gpio_count; ++ ++ usrmemphyaddr=get_usrmem_virt(); ++ memcpy((u8*)&gk_all_gpio_cfg,(u8*)usrmemphyaddr,sizeof(gk_all_gpio_cfg)); ++ gk_all_gpio_cfg.board_type[31] = '\0'; ++ /*get gpio configure infor*/ ++ gpio_count = gk_all_gpio_cfg.gpio_count; ++ intphy_gpio_count = gk_all_gpio_cfg.intphy_gpio_count; ++ extphy_gpio_count = gk_all_gpio_cfg.extphy_gpio_count; ++ ++#if 1 ++ printk("###################################\n"); ++ if(gk_all_gpio_cfg.soc_type >= sizeof(chip_type)/ sizeof(chip_type[0])) ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", "Unknown",gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version>> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ else ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", chip_type[gk_all_gpio_cfg.soc_type],gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version >> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ if (gk_all_gpio_cfg.ext_phy_clk == 0) ++ printk("[NET INT_CLK] Internal PHY clock \n"); ++ else ++ printk("[NET EXT_CLK] External PHY clock %dMHz \n", gk_all_gpio_cfg.ext_phy_clk); ++ printk("[GPIO]#############################\n"); ++ printk("[GPIO] gpio map get from uboot\n"); ++ printk("[GPIO CFG] gpio count = %d\n",gk_all_gpio_cfg.gpio_count); ++ printk("[GPIO CFG] intphy count = %d\n",gk_all_gpio_cfg.intphy_gpio_count); ++ printk("[GPIO CFG] extphy count = %d\n",gk_all_gpio_cfg.extphy_gpio_count); ++ printk("[GPIO CFG] IR LED CTL (%d)\n",gk_all_gpio_cfg.ir_led_ctl); ++ printk("[GPIO CFG] IR CUT1 (%d)\n",gk_all_gpio_cfg.ir_cut1); ++ printk("[GPIO CFG] IR CUT2 (%d)\n",gk_all_gpio_cfg.ir_cut2); ++ printk("[GPIO CFG] SENSOR Reset (%d)\n",gk_all_gpio_cfg.sensor_reset); ++ printk("[GPIO CFG] PHY Reset (%d)\n",gk_all_gpio_cfg.phy_reset); ++ printk("[GPIO CFG] PHY Speed Led (%d)\n",gk_all_gpio_cfg.phy_speed_led); ++ printk("[GPIO CFG] SPI0 EN (%d)\n",gk_all_gpio_cfg.spi0_en0); ++ printk("[GPIO CFG] SPI1 EN (%d)\n",gk_all_gpio_cfg.spi1_en0); ++ printk("[GPIO CFG] USB HOST (%d)\n",gk_all_gpio_cfg.usb_host); ++ printk("[GPIO CFG] SD Detect (%d)\n",gk_all_gpio_cfg.sd_detect); ++ printk("[GPIO CFG] SD Power (%d)\n",gk_all_gpio_cfg.sd_power); ++ printk("[GPIO]#############################\n"); ++#endif ++ ++ goke_init_gpio(); ++ ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.gpio_chip[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.gpio_chip[index].pin, gk_all_gpio_cfg.gpio_chip[index].type); ++ } ++ } ++ if(cmdline_phytype == 0) ++ { ++ gpio_count = intphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.int_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.int_phy_gpio[index].pin, gk_all_gpio_cfg.int_phy_gpio[index].type); ++ } ++ } ++ } ++ else ++ { ++ gpio_count = extphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.ext_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.ext_phy_gpio[index].pin, gk_all_gpio_cfg.ext_phy_gpio[index].type); ++ } ++ } ++ } ++ for(i=0;i ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++gpio_cfg_t gk_all_gpio_cfg; ++ ++struct gk_gpio_bank gk_gpio0_banks[] = ++{ ++ GK_GPIO_BANK("gk-gpio0", GPIO0_BANK0_BASE, GPIO0_BANK0_PLL_IOCTRL_BASE, ++ GK_GPIO(0 * GPIO_BANK_SIZE), CONFIG_ARCH_NR_GPIO, 0), ++}; ++// last one max = CONFIG_ARCH_NR_GPIO - base ++ ++struct gk_gpio_inst gk_gpio_insts[CONFIG_GK_GPIO_INSTANCES] = ++{ ++ [0] = ++ { ++ .bank_num = ARRAY_SIZE(gk_gpio0_banks), ++ .gpio_bank = gk_gpio0_banks, ++ .output_cfg = {0}, ++ .input_cfg = {0}, ++ .irq_no = GPIO0_IRQ, ++ .irq_info = {{0},}, ++ .irq_now = 0, ++ .gpio_valid = {0}, ++ .gpio_freeflag = {0}, ++ .irq_flag = {0}, ++ .base_bus = GPIO0_BASE, ++ .per_sel_reg = 0, ++ }, ++}; ++ ++int __init gk_init_gpio(void) ++{ ++ int retval = 0; ++ int i, index; ++ int gpio_count; ++ ++ const char chip_type[][8] = ++ { ++ {"GK7101"}, ++ {"GK7102"}, ++ {"GK7101S"}, ++ {"GK7102S"} ++ }; ++ ++ /* use usr memory's GPIO setting by uboot pass*/ ++ u32 usrmemphyaddr=0; ++ int intphy_gpio_count; ++ int extphy_gpio_count; ++ ++ usrmemphyaddr=get_usrmem_virt(); ++ memcpy((u8*)&gk_all_gpio_cfg,(u8*)usrmemphyaddr,sizeof(gk_all_gpio_cfg)); ++ gk_all_gpio_cfg.board_type[31] = '\0'; ++ /*get gpio configure infor*/ ++ gpio_count = gk_all_gpio_cfg.gpio_count; ++ intphy_gpio_count = gk_all_gpio_cfg.intphy_gpio_count; ++ extphy_gpio_count = gk_all_gpio_cfg.extphy_gpio_count; ++ ++#if 1 ++ printk("###################################\n"); ++ if(gk_all_gpio_cfg.soc_type >= sizeof(chip_type)/ sizeof(chip_type[0])) ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", "Unknown",gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version>> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ else ++ { ++ printk("[BOOT VERSION] %s %s v%d.%d \n", chip_type[gk_all_gpio_cfg.soc_type],gk_all_gpio_cfg.board_type, ++ gk_all_gpio_cfg.board_version >> 16, gk_all_gpio_cfg.board_version & 0xffff); ++ } ++ if (gk_all_gpio_cfg.ext_phy_clk == 0) ++ printk("[NET INT_CLK] Internal PHY clock \n"); ++ else ++ printk("[NET EXT_CLK] External PHY clock %dMHz \n", gk_all_gpio_cfg.ext_phy_clk); ++ printk("[GPIO]#############################\n"); ++ printk("[GPIO] gpio map get from uboot\n"); ++ printk("[GPIO CFG] gpio count = %d\n",gk_all_gpio_cfg.gpio_count); ++ printk("[GPIO CFG] intphy count = %d\n",gk_all_gpio_cfg.intphy_gpio_count); ++ printk("[GPIO CFG] extphy count = %d\n",gk_all_gpio_cfg.extphy_gpio_count); ++ printk("[GPIO CFG] IR LED CTL (%d)\n",gk_all_gpio_cfg.ir_led_ctl); ++ printk("[GPIO CFG] IR CUT1 (%d)\n",gk_all_gpio_cfg.ir_cut1); ++ printk("[GPIO CFG] IR CUT2 (%d)\n",gk_all_gpio_cfg.ir_cut2); ++ printk("[GPIO CFG] SENSOR Reset (%d)\n",gk_all_gpio_cfg.sensor_reset); ++ printk("[GPIO CFG] PHY Reset (%d)\n",gk_all_gpio_cfg.phy_reset); ++ printk("[GPIO CFG] PHY Speed Led (%d)\n",gk_all_gpio_cfg.phy_speed_led); ++ printk("[GPIO CFG] SPI0 EN (%d)\n",gk_all_gpio_cfg.spi0_en0); ++ printk("[GPIO CFG] SPI1 EN (%d)\n",gk_all_gpio_cfg.spi1_en0); ++ printk("[GPIO CFG] USB HOST (%d)\n",gk_all_gpio_cfg.usb_host); ++ printk("[GPIO CFG] SD Detect (%d)\n",gk_all_gpio_cfg.sd_detect); ++ printk("[GPIO CFG] SD Power (%d)\n",gk_all_gpio_cfg.sd_power); ++ printk("[GPIO CFG] SD1 Detect (%d)\n",gk_all_gpio_cfg.sd1_detect); ++ printk("[GPIO CFG] SD1 Power (%d)\n",gk_all_gpio_cfg.sd1_power); ++ printk("[GPIO]#############################\n"); ++#endif ++ ++ goke_init_gpio(); ++ ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.gpio_chip[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.gpio_chip[index].pin, gk_all_gpio_cfg.gpio_chip[index].type); ++ } ++ } ++ if(cmdline_phytype == 0) ++ { ++ gpio_count = intphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.int_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.int_phy_gpio[index].pin, gk_all_gpio_cfg.int_phy_gpio[index].type); ++ } ++ } ++ } ++ else ++ { ++ gpio_count = extphy_gpio_count; ++ for(index=0; index < gpio_count; index++) ++ { ++ if(gk_all_gpio_cfg.ext_phy_gpio[index].type != GPIO_TYPE_UNDEFINED) ++ { ++ gk_gpio_func_config(gk_all_gpio_cfg.ext_phy_gpio[index].pin, gk_all_gpio_cfg.ext_phy_gpio[index].type); ++ } ++ } ++ } ++ for(i=0;i ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int highres_timer_start(struct hrtimer *timer, ktime_t tim, const enum hrtimer_mode mode) ++{ ++ return hrtimer_start(timer, tim, mode); ++} ++EXPORT_SYMBOL(highres_timer_start); ++ ++void highres_timer_init(struct hrtimer *timer, clockid_t clock_id, enum hrtimer_mode mode) ++{ ++ hrtimer_init(timer, clock_id, mode); ++} ++EXPORT_SYMBOL(highres_timer_init); ++ ++int highres_timer_cancel(struct hrtimer *timer) ++{ ++ return hrtimer_cancel(timer); ++} ++EXPORT_SYMBOL(highres_timer_cancel); ++ ++MODULE_AUTHOR("Louis"); ++MODULE_DESCRIPTION("high resolution timer wrapper"); ++MODULE_LICENSE("GPL v2"); ++MODULE_VERSION("1.0"); ++ +diff --git a/arch/arm/plat-goke/hw_timer.c b/arch/arm/plat-goke/hw_timer.c +new file mode 100644 +index 00000000..34737b28 +--- /dev/null ++++ b/arch/arm/plat-goke/hw_timer.c +@@ -0,0 +1,594 @@ ++/* ++ * arch/arm/mach-gk/hw_timer.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++ ++#define GK_HWTIMER_NAME "hwtimer" ++ ++#define GK_HWTIMER_STATUS_REG TIMER1_STATUS_REG ++#define GK_HWTIMER_RELOAD_REG TIMER1_RELOAD_REG ++#define GK_HWTIMER_MATCH1_REG TIMER1_MATCH1_REG ++#define GK_HWTIMER_MATCH2_REG TIMER1_MATCH2_REG ++#define GK_HWTIMER_CTR_EN TIMER_CTR_EN1 ++#define GK_HWTIMER_CTR_OF TIMER_CTR_OF1 ++#define GK_HWTIMER_CTR_CSL TIMER_CTR_CSL1 ++#define GK_HWTIMER_CTR_MASK 0x0000000F ++ ++#define GK_HWTIMER_IRQ TIMER1_IRQ ++ ++#define HWTIMER_INPUT_FREQ (get_apb_bus_freq_hz()) ++#define HWTIMER_OUTPUT_FREQ 90000 ++ ++typedef struct hw_timer_state_s ++{ ++ u32 enable_flag; ++ u32 reg_value; ++ u64 overflow_count; ++ u64 overflow_value; ++ u64 output_ticks; ++}hw_timer_state_t; ++ ++static u64 hwtimer_overflow_count = 0; ++static u64 hwtimer_init_output_value = 0; ++static u32 hwtimer_init_overflow_value = 0; ++static u32 hwtimer_input_freq_unchanged = 1; ++ ++static hw_timer_state_t timer_state; ++ ++static spinlock_t timer_isr_lock; ++ ++static int hwtimer_reset(void); ++ ++static inline void gk_hwtimer_disable(void) ++{ ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_HWTIMER_CTR_EN); ++} ++ ++static inline void gk_hwtimer_enable(void) ++{ ++ gk_timer_setbitsl(TIMER_CTR_REG, GK_HWTIMER_CTR_EN); ++} ++ ++static inline void gk_hwtimer_misc(void) ++{ ++ gk_timer_setbitsl(TIMER_CTR_REG, GK_HWTIMER_CTR_OF); ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_HWTIMER_CTR_CSL); ++} ++ ++static inline void gk_hwtimer_config(void) ++{ ++ if (hwtimer_init_overflow_value) { ++ gk_timer_writel(GK_HWTIMER_STATUS_REG, hwtimer_init_overflow_value); ++ gk_timer_writel(GK_HWTIMER_RELOAD_REG, hwtimer_init_overflow_value); ++ } else { ++ hwtimer_init_overflow_value = HWTIMER_INPUT_FREQ; ++ gk_timer_writel(GK_HWTIMER_STATUS_REG, hwtimer_init_overflow_value); ++ gk_timer_writel(GK_HWTIMER_RELOAD_REG, hwtimer_init_overflow_value); ++ } ++ ++ gk_timer_writel(GK_HWTIMER_MATCH1_REG, 0x0); ++ gk_timer_writel(GK_HWTIMER_MATCH2_REG, 0x0); ++ gk_hwtimer_misc(); ++} ++ ++static inline void gk_hwtimer_init(void) ++{ ++ gk_hwtimer_disable(); ++ gk_hwtimer_config(); ++ gk_hwtimer_enable(); ++ timer_state.enable_flag = 1; ++} ++ ++static u32 gk_hwtimer_read(void) ++{ ++ return (u32)gk_timer_readl(GK_HWTIMER_STATUS_REG); ++} ++ ++static inline int get_gcd(int a, int b) ++{ ++ if ((a == 0) || (b == 0)) { ++ printk("wrong input for gcd \n"); ++ return 1; ++ } ++ while ((a != 0) && (b != 0)) { ++ if (a > b) { ++ a = a % b; ++ } else { ++ b = b % a; ++ } ++ } ++ return (a == 0) ? b : a; ++} ++ ++static int calc_output_ticks(void) ++{ ++ u64 total_ticks; ++ u64 overflow_ticks; ++ u64 hwtimer_ticks; ++ u32 curr_reg_value; ++ int output_freq = HWTIMER_OUTPUT_FREQ; ++ ++ int gcd; ++ ++ if (hwtimer_input_freq_unchanged) { ++ curr_reg_value = gk_hwtimer_read(); ++ ++ overflow_ticks = hwtimer_overflow_count * hwtimer_init_overflow_value; ++ hwtimer_ticks = hwtimer_init_overflow_value - curr_reg_value; ++ total_ticks = overflow_ticks + hwtimer_ticks; ++ ++ // change frequency from apb clock to 90K ++ gcd = get_gcd(output_freq, (int)hwtimer_init_overflow_value); ++ total_ticks = total_ticks * (output_freq / gcd) + ++ hwtimer_init_overflow_value / (gcd * 2); ++ if (hwtimer_init_overflow_value) ++ do_div(total_ticks, hwtimer_init_overflow_value / gcd); ++ else { ++ printk("HWTimer: calculate output ticks failed! Can not divide zero!\n"); ++ return -EINVAL; ++ } ++ ++ //update timer state ++ timer_state.output_ticks = total_ticks; ++ timer_state.overflow_count = hwtimer_overflow_count; ++ timer_state.reg_value = curr_reg_value; ++ } else { ++ curr_reg_value = gk_hwtimer_read(); ++ if (curr_reg_value > timer_state.reg_value) { ++ overflow_ticks = (hwtimer_overflow_count - timer_state.overflow_count) ++ * hwtimer_init_overflow_value; ++ hwtimer_ticks = curr_reg_value - timer_state.reg_value; ++ total_ticks = overflow_ticks + hwtimer_ticks; ++ } else { ++ overflow_ticks = (hwtimer_overflow_count - timer_state.overflow_count) ++ * hwtimer_init_overflow_value; ++ hwtimer_ticks = timer_state.reg_value - curr_reg_value; ++ total_ticks = overflow_ticks - hwtimer_ticks; ++ } ++ ++ // change frequency from apb clock to 90K ++ total_ticks = total_ticks * HWTIMER_OUTPUT_FREQ; ++ if (timer_state.overflow_value) ++ do_div(total_ticks, timer_state.overflow_value); ++ else { ++ printk("HWTimer: calculate output ticks failed! Can not divide zero!\n"); ++ return -EINVAL; ++ } ++ total_ticks += timer_state.output_ticks; ++ ++ //update timer state structure ++ timer_state.output_ticks = total_ticks; ++ timer_state.overflow_count = hwtimer_overflow_count; ++ timer_state.reg_value = curr_reg_value; ++ } ++ ++ return 0; ++} ++ ++/*static void hw_timer_check_input_freq(int isr_flag) ++{ ++ u32 curr_input_freq = HWTIMER_INPUT_FREQ; ++ ++ if (timer_state.overflow_value != curr_input_freq) { ++ //printk("HWTimer: input frequency is changed from %lld to %u!\n", ++ // timer_state.overflow_value, curr_input_freq); ++ if (hwtimer_input_freq_unchanged) { ++ hwtimer_input_freq_unchanged = 0; ++ } ++ if (isr_flag) ++ calc_output_ticks(); ++ timer_state.overflow_value = curr_input_freq; ++ } ++}*/ ++ ++static int hwtimer_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[50]; ++ ++ if (count > 50) { ++ printk("HWTimer: %s: count %d out of size!\n", __func__, (u32)count); ++ retval = -ENOSPC; ++ goto hwtimer_write_proc_exit; ++ } ++ if (count > 1) { ++ if (copy_from_user(buf, buffer, count - 1)) { ++ printk("HWTimer: %s: copy_from_user fail!\n", __func__); ++ retval = -EFAULT; ++ goto hwtimer_write_proc_exit; ++ } ++ buf[count] = '\0'; ++ hwtimer_init_output_value = simple_strtoull(buf, NULL, 10); ++ } ++ ++ hwtimer_reset(); ++ ++ retval = count; ++ ++hwtimer_write_proc_exit: ++ return retval; ++} ++ ++int get_hwtimer_output_ticks(u64 *out_tick) ++{ ++ int ret = 0; ++ if (timer_state.enable_flag) { ++ ret = calc_output_ticks(); ++ if (!ret) { ++ //hw_timer_check_input_freq(0); ++ *out_tick = timer_state.output_ticks + hwtimer_init_output_value; ++ } else { ++ *out_tick = 0; ++ } ++ } else { ++ *out_tick = 0; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL(get_hwtimer_output_ticks); ++ ++static int hwtimer_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ u64 final_ticks = 0; ++ ++ if (off) ++ return ret; ++ ++ *start = page + off; ++ *eof = 1; ++ ++ if (timer_state.enable_flag) { ++ ret = calc_output_ticks(); ++ if (!ret) { ++ //hw_timer_check_input_freq(0); ++ final_ticks = timer_state.output_ticks + hwtimer_init_output_value; ++ ret = sprintf(*start, "%lld\n", final_ticks); ++ } else { ++ ret = sprintf(*start, "%d\n", 0); ++ } ++ } else { ++ ret = sprintf(*start, "%d\n", 0); ++ } ++ ++ return ret; ++} ++ ++/* buffer size is one page but our output routines use some slack for overruns */ ++#define PROC_BLOCK_SIZE (PAGE_SIZE - 1024) ++static ssize_t hwtimer_proc_file_read_func(struct file *file, ++ char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ struct inode * inode = file->f_path.dentry->d_inode; ++ char *page; ++ ssize_t retval=0; ++ int eof=0; ++ ssize_t n, count; ++ char *start; ++ struct proc_dir_entry * dp; ++ unsigned long long pos; ++ ++ pos = *ppos; ++ if (pos > MAX_NON_LFS) ++ return 0; ++ if (nbytes > MAX_NON_LFS - pos) ++ nbytes = MAX_NON_LFS - pos; ++ ++ dp = PDE(inode); ++ if (!(page = (char*) __get_free_page(GFP_TEMPORARY))) ++ return -ENOMEM; ++ ++ while ((nbytes > 0) && !eof) { ++ count = min_t(size_t, PROC_BLOCK_SIZE, nbytes); ++ ++ start = NULL; ++ if (dp->read_proc) { ++ n = dp->read_proc(page, &start, *ppos, ++ count, &eof, dp->data); ++ } else ++ break; ++ ++ if (n == 0) /* end of file */ ++ break; ++ if (n < 0) { /* error */ ++ if (retval == 0) ++ retval = n; ++ break; ++ } ++ ++ if (start == NULL) { ++ if (n > PAGE_SIZE) { ++ printk(KERN_ERR ++ "proc_file_read: Apparent buffer overflow!\n"); ++ n = PAGE_SIZE; ++ } ++ n -= *ppos; ++ if (n <= 0) ++ break; ++ if (n > count) ++ n = count; ++ start = page + *ppos; ++ } else if (start < page) { ++ if (n > PAGE_SIZE) { ++ printk(KERN_ERR ++ "proc_file_read: Apparent buffer overflow!\n"); ++ n = PAGE_SIZE; ++ } ++ if (n > count) { ++ /* ++ * Don't reduce n because doing so might ++ * cut off part of a data block. ++ */ ++ printk(KERN_WARNING ++ "proc_file_read: Read count exceeded\n"); ++ } ++ } else /* start >= page */ { ++ unsigned long startoff = (unsigned long)(start - page); ++ if (n > (PAGE_SIZE - startoff)) { ++ printk(KERN_ERR ++ "proc_file_read: Apparent buffer overflow!\n"); ++ n = PAGE_SIZE - startoff; ++ } ++ if (n > count) ++ n = count; ++ } ++ ++ n -= copy_to_user(buf, start < page ? page : start, n); ++ if (n == 0) { ++ if (retval == 0) ++ retval = -EFAULT; ++ break; ++ } ++ ++ // disable proc file offset update to support read without sync ++ //*ppos += start < page ? (unsigned long)start : n; ++ nbytes -= n; ++ buf += n; ++ retval += n; ++ } ++ free_page((unsigned long) page); ++ return retval; ++} ++ ++static void __hwtimer_pde_users_dec(struct proc_dir_entry *pde) ++{ ++ pde->pde_users--; ++ if (pde->pde_unload_completion && pde->pde_users == 0) ++ complete(pde->pde_unload_completion); ++} ++ ++static void hw_timer_pde_users_dec(struct proc_dir_entry *pde) ++{ ++ spin_lock(&pde->pde_unload_lock); ++ __hwtimer_pde_users_dec(pde); ++ spin_unlock(&pde->pde_unload_lock); ++} ++ ++static ssize_t hwtimer_proc_file_read(struct file *file, ++ char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ struct proc_dir_entry *pde = PDE(file->f_path.dentry->d_inode); ++ ssize_t rv = -EIO; ++ ++ spin_lock(&pde->pde_unload_lock); ++ if (!pde->proc_fops) { ++ spin_unlock(&pde->pde_unload_lock); ++ return rv; ++ } ++ pde->pde_users++; ++ spin_unlock(&pde->pde_unload_lock); ++ ++ rv = hwtimer_proc_file_read_func(file, buf, nbytes, ppos); ++ ++ hw_timer_pde_users_dec(pde); ++ return rv; ++} ++ ++static ssize_t hwtimer_proc_file_write(struct file *file, ++ const char __user *buffer, size_t count, loff_t *ppos) ++{ ++ struct proc_dir_entry *pde = PDE(file->f_path.dentry->d_inode); ++ ssize_t rv = -EIO; ++ ++ if (pde->write_proc) { ++ spin_lock(&pde->pde_unload_lock); ++ if (!pde->proc_fops) { ++ spin_unlock(&pde->pde_unload_lock); ++ return rv; ++ } ++ pde->pde_users++; ++ spin_unlock(&pde->pde_unload_lock); ++ ++ /* FIXME: does this routine need ppos? probably... */ ++ rv = pde->write_proc(file, buffer, count, pde->data); ++ hw_timer_pde_users_dec(pde); ++ } ++ return rv; ++} ++ ++static const struct file_operations hwtimer_fops = { ++ .owner = THIS_MODULE, ++ .read = hwtimer_proc_file_read, ++ .write = hwtimer_proc_file_write, ++}; ++ ++static int hwtimer_create_proc(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *hwtimer_entry; ++ ++ hwtimer_entry = proc_create_data(GK_HWTIMER_NAME, ++ S_IRUGO | S_IWUGO, get_gk_proc_dir(), &hwtimer_fops, NULL); ++ //hwtimer_entry = create_proc_entry(GK_HWTIMER_NAME, ++ // S_IRUGO, get_gk_proc_dir()); ++ ++ if (!hwtimer_entry) { ++ err_code = -EINVAL; ++ } else { ++ hwtimer_entry->read_proc = hwtimer_read_proc; ++ hwtimer_entry->write_proc = hwtimer_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static irqreturn_t hwtimer_isr(int irq, void *dev_id) ++{ ++ spin_lock(&timer_isr_lock); ++ hwtimer_overflow_count++; ++ spin_unlock(&timer_isr_lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static void init_timer_state(void) ++{ ++ timer_state.enable_flag = 0; ++ timer_state.output_ticks = 0; ++ timer_state.overflow_count = 0; ++ timer_state.reg_value = hwtimer_init_overflow_value; ++ timer_state.overflow_value = hwtimer_init_overflow_value; ++} ++ ++static void hwtimer_remove_proc(void) ++{ ++ remove_proc_entry(GK_HWTIMER_NAME, get_gk_proc_dir()); ++} ++ ++int hwtimer_reset() ++{ ++ hwtimer_overflow_count = 0; ++ hwtimer_init_overflow_value = HWTIMER_INPUT_FREQ; ++ init_timer_state(); ++ gk_hwtimer_init(); ++ ++ return 0; ++} ++ ++static int __init hwtimer_init(void) ++{ ++ int err_code = 0; ++ err_code = hwtimer_create_proc(); ++ if (err_code) { ++ printk("HWTimer: create proc file for hw timer failed!\n"); ++ goto hwtimer_init_err_create_proc; ++ } ++ ++ hwtimer_overflow_count = 0; ++ err_code = request_irq(GK_HWTIMER_IRQ, hwtimer_isr, ++ IRQF_TRIGGER_RISING, GK_HWTIMER_NAME, NULL); ++ if (err_code) { ++ printk("HWTimer: request irq for hw timer failed!\n"); ++ goto hwtimer_init_err_request_irq; ++ } ++ ++ hwtimer_init_overflow_value = HWTIMER_INPUT_FREQ; ++ init_timer_state(); ++ gk_hwtimer_init(); ++ ++ goto hwtimer_init_err_na; ++ ++hwtimer_init_err_request_irq: ++ free_irq(GK_HWTIMER_IRQ, NULL); ++ ++hwtimer_init_err_create_proc: ++ hwtimer_remove_proc(); ++ ++hwtimer_init_err_na: ++ return err_code; ++} ++ ++static void __exit hwtimer_exit(void) ++{ ++ if (timer_state.enable_flag) { ++ gk_hwtimer_disable(); ++ timer_state.enable_flag = 0; ++ } ++ free_irq(GK_HWTIMER_IRQ, NULL); ++ hwtimer_remove_proc(); ++} ++ ++module_init(hwtimer_init); ++module_exit(hwtimer_exit); ++ ++MODULE_DESCRIPTION("gk hardware timer driver"); ++MODULE_LICENSE("Proprietary"); ++ +diff --git a/arch/arm/plat-goke/include/plat/audio.h b/arch/arm/plat-goke/include/plat/audio.h +new file mode 100644 +index 00000000..68d66997 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/audio.h +@@ -0,0 +1,181 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/audio.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __PLAT_AUDIO_H ++#define __PLAT_AUDIO_H ++ ++#include ++ ++/* ==========================================================================*/ ++#define DAI_CLOCK_MASK 0x0000001f ++ ++#define MAX_MCLK_IDX_NUM 15 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct notifier_block; ++ ++struct gk_i2s_interface { ++ u8 state; ++ u8 mode; ++ u8 sfreq; ++ u8 clksrc; ++ u8 ms_mode; ++ u8 mclk; ++ u8 ch; ++ u8 oversample; ++ u8 word_order; ++ u8 word_len; ++ u8 word_pos; ++ u8 slots; ++}; ++ ++#define MAX_OVERSAMPLE_IDX_NUM 9 ++enum AudioCodec_OverSample { ++ AudioCodec_128xfs = 0, ++ AudioCodec_256xfs = 1, ++ AudioCodec_384xfs = 2, ++ AudioCodec_512xfs = 3, ++ AudioCodec_768xfs = 4, ++ AudioCodec_1024xfs = 5, ++ AudioCodec_1152xfs = 6, ++ AudioCodec_1536xfs = 7, ++ AudioCodec_2304xfs = 8 ++}; ++ ++enum AudioCodec_MCLK { ++ AudioCodec_18_432M = 0, ++ AudioCodec_16_9344M = 1, ++ AudioCodec_12_288M = 2, ++ AudioCodec_11_2896M = 3, ++ AudioCodec_9_216M = 4, ++ AudioCodec_8_4672M = 5, ++ AudioCodec_8_192M = 6, ++ AudioCodec_6_144 = 7, ++ AudioCodec_5_6448M = 8, ++ AudioCodec_4_608M = 9, ++ AudioCodec_4_2336M = 10, ++ AudioCodec_4_096M = 11, ++ AudioCodec_3_072M = 12, ++ AudioCodec_2_8224M = 13, ++ AudioCodec_2_048M = 14 ++}; ++ ++enum audio_in_freq_e ++{ ++ AUDIO_SF_reserved = 0, ++ AUDIO_SF_96000, ++ AUDIO_SF_48000, ++ AUDIO_SF_44100, ++ AUDIO_SF_32000, ++ AUDIO_SF_24000, ++ AUDIO_SF_22050, ++ AUDIO_SF_16000, ++ AUDIO_SF_12000, ++ AUDIO_SF_11025, ++ AUDIO_SF_8000, ++}; ++ ++enum Audio_Notify_Type ++{ ++ AUDIO_NOTIFY_UNKNOWN, ++ AUDIO_NOTIFY_INIT, ++ AUDIO_NOTIFY_SETHWPARAMS, ++ AUDIO_NOTIFY_REMOVE ++}; ++ ++enum DAI_Mode ++{ ++ DAI_leftJustified_Mode = 0, ++ DAI_rightJustified_Mode = 1, ++ DAI_MSBExtend_Mode = 2, ++ DAI_I2S_Mode = 4, ++ DAI_DSP_Mode = 6 ++}; ++ ++enum DAI_MS_MODE ++{ ++ DAI_SLAVE = 0, ++ DAI_MASTER = 1 ++}; ++ ++enum DAI_resolution ++{ ++ DAI_16bits = 0, ++ DAI_18bits = 1, ++ DAI_20bits = 2, ++ DAI_24bits = 3, ++ DAI_32bits = 4 ++ ++}; ++ ++enum DAI_ifunion ++{ ++ DAI_union = 0, ++ DAI_nonunion = 1 ++}; ++ ++enum DAI_WordOrder ++{ ++ DAI_MSB_FIRST = 0, ++ DAI_LSB_FIRST = 1 ++}; ++ ++enum DAI_INIT_CTL ++{ ++ DAI_FIFO_RST = 1, ++ DAI_RX_EN = 2, ++ DAI_TX_EN = 4 ++}; ++ ++#define DAI_32slots 32 ++#define DAI_64slots 64 ++#define DAI_48slots 48 ++ ++#define GK_CLKSRC_ONCHIP AUC_CLK_ONCHIP_PLL_27MHZ ++#define GK_CLKSRC_EXTERNAL AUC_CLK_EXTERNAL ++#define GK_CLKDIV_LRCLK 0 ++ ++struct gk_i2s_controller { ++ void (*aucodec_digitalio_0)(void); ++ void (*aucodec_digitalio_1)(void); ++ void (*aucodec_digitalio_2)(void); ++ void (*channel_select)(u32); ++ void (*set_audio_pll)(u8, u8); ++}; ++ ++/* ==========================================================================*/ ++extern struct platform_device gk_i2s0; ++extern struct platform_device gk_pcm0; ++extern struct platform_device gk_dummy_codec0; ++ ++extern u32 alsa_tx_enable_flag; ++ ++/* ==========================================================================*/ ++extern int gk_init_audio(void); ++ ++extern void gk_audio_notify_transition(struct gk_i2s_interface *data, unsigned int type); ++extern int gk_audio_register_notifier(struct notifier_block *nb); ++extern int gk_audio_unregister_notifier(struct notifier_block *nb); ++ ++extern struct gk_i2s_interface get_audio_i2s_interface(void); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/cache.h b/arch/arm/plat-goke/include/plat/cache.h +new file mode 100644 +index 00000000..dc650b35 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/cache.h +@@ -0,0 +1,41 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/plat/cache.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_CACHE_H ++#define __PLAT_CACHE_H ++ ++/* ==========================================================================*/ ++#define CACHE_LINE_SIZE 32 ++#define CACHE_LINE_MASK ~(CACHE_LINE_SIZE - 1) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++extern void gk_cache_clean_range(void *addr, unsigned int size); ++extern void gk_cache_inv_range(void *addr, unsigned int size); ++extern void gk_cache_flush_range(void *addr, unsigned int size); ++extern void gk_cache_pli_range(void *addr, unsigned int size); ++extern int gk_cache_l2_enable(void); ++extern int gk_cache_l2_disable(void); ++extern void gk_cache_l2_enable_raw(void); ++extern void gk_cache_l2_disable_raw(void); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/dma.h b/arch/arm/plat-goke/include/plat/dma.h +new file mode 100644 +index 00000000..81687552 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/dma.h +@@ -0,0 +1,86 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/dma.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_DMA_H ++#define __PLAT_DMA_H ++ ++#include ++ ++/* ==========================================================================*/ ++#define MAX_DMA_CHANNEL_IRQ_HANDLERS 4 ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++typedef struct gk_dma_req_s { ++ u32 src; /* Source address */ ++ u32 dst; /* Destination address */ ++ struct gk_dma_req_s *next; /* Pointing to next descriptor */ ++ u32 rpt; /* The physical address to store DMA hardware ++ reporting status */ ++ u32 xfr_count; /* Transfer byte count , max value = 2^22 */ ++ u32 attr; /* Descriptor 's attribute */ ++} gk_dma_req_t; ++ ++typedef struct gk_dmadesc_s { ++ u32 src_addr; /**< Source address */ ++ u32 dst_addr; /**< Destination address */ ++ u32 next; /**< Next descriptor */ ++ u32 rpt_addr; /**< Report address */ ++ u32 xfrcnt; /**< Transfer count */ ++ u32 ctrl; /**< Control */ ++ u32 rsv0; /**< Reserved */ ++ u32 rsv1; /**< Reserved */ ++ u32 rpt; /**< Report */ ++ u32 rsv2; /**< Reserved */ ++ u32 rsv3; /**< Reserved */ ++ u32 rsv4; /**< Reserved */ ++} gk_dmadesc_t; ++ ++typedef void (*gk_dma_handler)(void *dev_id, u32 status); ++ ++struct dma_s { ++ struct dma_chan_s { ++ u32 status; /**< The status of the current transaction */ ++ int use_flag; ++ int irq_count; ++ struct { ++ int enabled; ++ gk_dma_handler handler; ++ void *harg; ++ } irq[MAX_DMA_CHANNEL_IRQ_HANDLERS]; ++ } chan[NUM_DMA_CHANNELS]; ++}; ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++extern int gk_dma_request_irq(int chan, gk_dma_handler handler, void *harg); ++extern void gk_dma_free_irq(int chan, gk_dma_handler handler); ++extern int gk_dma_enable_irq(int chan, gk_dma_handler handler); ++extern int gk_dma_disable_irq(int chan, gk_dma_handler handler); ++extern int gk_dma_xfr(gk_dma_req_t *req, int chan); ++extern int gk_dma_desc_xfr(dma_addr_t desc_addr, int chan); ++extern int gk_dma_desc_stop(int chan); ++extern int gk_dma_read_ctrl_reg(int chan); ++extern int gk_init_dma(void); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/fb.h b/arch/arm/plat-goke/include/plat/fb.h +new file mode 100644 +index 00000000..a40df190 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/fb.h +@@ -0,0 +1,143 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/fb.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_FB_H ++#define __PLAT_FB_H ++ ++/* ==========================================================================*/ ++#define GK_CLUT_BYTES (3) ++#define GK_CLUT_TABLE_SIZE (256 * GK_CLUT_BYTES) ++#define GK_BLEND_TABLE_SIZE (256) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++#include "linux/fb.h" ++enum gk_fb_color_format { ++ GK_FB_COLOR_AUTO = 0, ++ ++ GK_FB_COLOR_CLUT_8BPP, ++ GK_FB_COLOR_RGB565, ++ ++ GK_FB_COLOR_BGR565, ++ GK_FB_COLOR_AGBR4444, //AYUV 4:4:4:4 ++ GK_FB_COLOR_RGBA4444, ++ GK_FB_COLOR_BGRA4444, ++ GK_FB_COLOR_ABGR4444, ++ GK_FB_COLOR_ARGB4444, ++ GK_FB_COLOR_AGBR1555, //AYUV 1:5:5:5 ++ GK_FB_COLOR_GBR1555, //YUV 1(ignored):5:5:5 ++ GK_FB_COLOR_RGBA5551, ++ GK_FB_COLOR_BGRA5551, ++ GK_FB_COLOR_ABGR1555, ++ GK_FB_COLOR_ARGB1555, ++ GK_FB_COLOR_AGBR8888, //AYUV 8:8:8:8 ++ GK_FB_COLOR_RGBA8888, ++ GK_FB_COLOR_BGRA8888, ++ GK_FB_COLOR_ABGR8888, ++ GK_FB_COLOR_ARGB8888, ++ ++ GK_FB_COLOR_YUV565, ++ GK_FB_COLOR_AYUV4444, ++ GK_FB_COLOR_AYUV1555, ++ GK_FB_COLOR_YUV555, ++ ++ GK_FB_COLOR_UNSUPPORTED, //Reserved only, not supported ++}; ++ ++typedef enum ++{ ++ GK_DSP_ENCODE_MODE = 0x00, ++ GK_DSP_DECODE_MODE = 0x01, ++ GK_DSP_RESET_MODE = 0x02, ++ GK_DSP_UNKNOWN_MODE = 0x03, ++ GK_DSP_QUICKLOGO_MODE = 0x04, ++}gk_dsp_op_mode_e; ++ ++enum gk_fb_status { ++ GK_FB_UNKNOWN_MODE = 0x00, ++ GK_FB_ACTIVE_MODE, ++ GK_FB_STOP_MODE, ++}; ++ ++typedef int (*gk_fb_pan_display_fn)(struct fb_var_screeninfo *var, ++ struct fb_info *info); ++typedef int (*gk_fb_setcmap_fn)(struct fb_cmap *cmap, ++ struct fb_info *info); ++typedef int (*gk_fb_check_var_fn)(struct fb_var_screeninfo *var, ++ struct fb_info *info); ++typedef int (*gk_fb_set_par_fn)(struct fb_info *info); ++typedef int (*gk_fb_blank_fn)(int blank_mode, struct fb_info *info); ++ ++struct gk_fb_cvs_buf { //Conversion Buffer ++ int available; ++ u8 *ping_buf; ++ u32 ping_buf_size; ++ u8 *pong_buf; ++ u32 pong_buf_size; ++}; ++ ++struct gk_fb_media_info { ++ struct fb_var_screeninfo screen_var; ++ struct fb_fix_screeninfo screen_fix; ++ gk_dsp_op_mode_e dsp_status; ++ ++ gk_fb_pan_display_fn pan_display; ++ gk_fb_setcmap_fn setcmap; ++ gk_fb_check_var_fn check_var; ++ gk_fb_set_par_fn set_par; ++ gk_fb_blank_fn set_blank; ++}; ++ ++struct gk_platform_fb { ++ struct mutex lock; ++ struct fb_var_screeninfo screen_var; ++ struct fb_fix_screeninfo screen_fix; ++ gk_dsp_op_mode_e dsp_status; ++ enum gk_fb_status fb_status; ++ u8 clut_table[GK_CLUT_TABLE_SIZE]; ++ u8 blend_table[GK_BLEND_TABLE_SIZE]; ++ enum gk_fb_color_format color_format; ++ struct gk_fb_cvs_buf conversion_buf; ++ u32 use_prealloc; ++ u32 prealloc_line_length; ++ ++ gk_fb_pan_display_fn pan_display; ++ gk_fb_setcmap_fn setcmap; ++ gk_fb_check_var_fn check_var; ++ gk_fb_set_par_fn set_par; ++ gk_fb_blank_fn set_blank; ++ ++ struct fb_info *proc_fb_info; ++ struct proc_dir_entry *proc_file; ++ wait_queue_head_t proc_wait; ++ u32 proc_wait_flag; ++}; ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++extern int gk_fb_get_platform_info(u32, struct gk_platform_fb *); ++extern int gk_fb_set_media_info(u32, struct gk_fb_media_info *); ++extern int gk_fb_update_info(u32 fb_id, int xres, int yres, ++ int xvirtual, int yvirtual, int format, u32 bits_per_pixel, ++ u32 smem_start, u32 smem_len); ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/gk_gpio.h b/arch/arm/plat-goke/include/plat/gk_gpio.h +new file mode 100644 +index 00000000..6ccbf5dc +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/gk_gpio.h +@@ -0,0 +1,228 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/plat-goke/include/plat/gk_gpio.h ++** ++** \version $Id: gk_gpio.h 9588 2016-08-16 01:55:35Z dengbiao $ ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2016 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef _GK_GPIO_H_ ++#define _GK_GPIO_H_ ++#include ++#include ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++#define GK_GPIO(n) (n) ++#define GPIO_BANK_SIZE 64 ++ ++/* SW definitions */ ++#define GPIO_HIGH 1 ++#define GPIO_LOW 0 ++ ++#define GK_GPIO_IO_MODULE_PARAM_CALL(name_prefix, arg, perm) \ ++ module_param_cb(name_prefix##gpio_id, ¶m_ops_int, &(arg.gpio_id), perm); \ ++ module_param_cb(name_prefix##active_level, ¶m_ops_int, &(arg.active_level), perm); \ ++ module_param_cb(name_prefix##active_delay, ¶m_ops_int, &(arg.active_delay), perm) ++#define GK_GPIO_RESET_MODULE_PARAM_CALL(name_prefix, arg, perm) \ ++ module_param_cb(name_prefix##gpio_id, ¶m_ops_int, &(arg.gpio_id), perm); \ ++ module_param_cb(name_prefix##active_level, ¶m_ops_int, &(arg.active_level), perm); \ ++ module_param_cb(name_prefix##active_delay, ¶m_ops_int, &(arg.active_delay), perm) ++ ++/* GPIO function selection */ ++/* Select SW or HW control and input/output direction of S/W function */ ++#define GPIO_FUNC_SW_INPUT 0 ++#define GPIO_FUNC_SW_OUTPUT 1 ++#define GPIO_FUNC_HW 2 ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++/* GPIO function selection */ ++typedef enum ++{ ++ GPIO_FUNC_IN = 1, ++ GPIO_FUNC_OUT = 2, ++ GPIO_FUNC_INOUT = 3, ++}GPIO_FUNC_TYPE_E; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++struct gk_gpio_irq_info ++{ ++ int pin; ++ int type; ++ int val; // when is input, the value will be transfered to handler ++ irq_handler_t handler; ++}; ++struct gk_gpio_io_info ++{ ++ int gpio_id; ++ int active_level; ++ int active_delay; //ms ++}; ++ ++typedef struct ++{ ++ u32 pin; ++ u32 type; ++}GPIO_XREF_S; ++ ++struct gk_gpio_bank ++{ ++ struct gpio_chip chip; ++ spinlock_t lock; ++ u32 base_reg; // for is/ibe/iev/ie/ic/ris/mis/din/ ++ u32 io_reg; // PLL_IOCTRL ++ u32 index; // instance no ++ struct ++ { ++ u32 isl_reg; ++ u32 ish_reg; ++ u32 ibel_reg; ++ u32 ibeh_reg; ++ u32 ievl_reg; ++ u32 ievh_reg; ++ u32 iel_reg; ++ u32 ieh_reg; ++ }pm_info; ++}; ++ ++struct gk_gpio_inst ++{ ++ u32 bank_num; ++ struct gk_gpio_bank* gpio_bank; ++ u32 output_cfg[CONFIG_ARCH_NR_GPIO]; // CONFIG_GK_GPIO_MAX_OUTPUT_TYPE != CONFIG_ARCH_NR_GPIO ++ u32 input_cfg[CONFIG_GK_GPIO_MAX_INPUT_TYPE]; // CONFIG_GK_GPIO_MAX_INPUT_TYPE != CONFIG_ARCH_NR_GPIO ++ u32 irq_no; ++ struct gk_gpio_irq_info irq_info[CONFIG_ARCH_NR_GPIO]; ++ u32 irq_now; ++ u32 gpio_valid[BITS_TO_LONGS(CONFIG_ARCH_NR_GPIO)]; ++ u32 gpio_freeflag[BITS_TO_LONGS(CONFIG_ARCH_NR_GPIO)]; ++ u32 irq_flag[BITS_TO_LONGS(CONFIG_ARCH_NR_GPIO)]; ++ u32 base_bus; // for sel/in ++ u32 per_sel_reg; ++}; ++ ++#define GK_GPIO_BANK(name, reg_base, io_base, base_gpio, gpio_num, bank) \ ++{ \ ++ .chip = \ ++ { \ ++ .label = name, \ ++ .owner = THIS_MODULE, \ ++ .request = gk_gpio_request, \ ++ .free = gk_gpio_free, \ ++ .direction_input = gk_gpio_direction_input, \ ++ .get = gk_gpio_get_ex, \ ++ .direction_output = gk_gpio_direction_output, \ ++ .set = gk_gpio_set, \ ++ .to_irq = gk_gpio_to_irq, \ ++ .dbg_show = gk_gpio_dbg_show, \ ++ .base = base_gpio, \ ++ .ngpio = gpio_num, \ ++ .can_sleep = 0, \ ++ .exported = 0, \ ++ }, \ ++ .base_reg = reg_base, \ ++ .io_reg = io_base, \ ++ .index = bank, \ ++ .pm_info = {0}, \ ++} ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++#ifdef CONFIG_GK_GPIO_V1_00 ++#include ++#endif ++#ifdef CONFIG_GK_GPIO_V1_10 ++#include ++#endif ++#ifdef CONFIG_GK_GPIO_V1_20 ++#include ++#endif ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++extern int __init gk_init_gpio(void); ++extern int gk_gpio_set_type(struct gk_gpio_bank* bank, u32 pin, u32 type); // GPIO_TYPE_E ++int gk_gpio_request(struct gpio_chip *chip, u32 pin); ++void gk_gpio_free(struct gpio_chip *chip, u32 pin); ++int gk_gpio_direction_input(struct gpio_chip *chip, u32 pin, int val); ++int gk_gpio_get(unsigned offset); ++int gk_gpio_get_ex(struct gpio_chip *chip, unsigned offset); ++int gk_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val); ++void gk_gpio_set(struct gpio_chip *chip, unsigned offset, int val); ++int gk_gpio_to_irq(struct gpio_chip *chip, unsigned offset); ++void gk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip); ++int gk_is_valid_gpio_irq(struct gk_gpio_irq_info *pinfo); ++extern void gk_gpio_set_out(u32 id, u32 value); ++ ++int gk_gpio_func_config(u32 pin, u32 func); ++ ++extern int gk_set_gpio_output(struct gk_gpio_io_info *pinfo, u32 on); ++extern u32 gk_get_gpio_input(struct gk_gpio_io_info *pinfo); ++extern int gk_set_gpio_reset(struct gk_gpio_io_info *pinfo); ++extern int gk_set_gpio_output_can_sleep(struct gk_gpio_io_info *pinfo, u32 on, int can_sleep); ++extern u32 gk_get_gpio_input_can_sleep(struct gk_gpio_io_info *pinfo, int can_sleep); ++extern int gk_set_gpio_reset_can_sleep(struct gk_gpio_io_info *pinfo, int can_sleep); ++extern void gk_gpio_config(u32 pin, u32 func); ++ ++ ++#define GK_GPIO_IRQ_MODULE_PARAM_CALL(name_prefix, arg, perm) \ ++ module_param_cb(name_prefix##pin, ¶m_ops_int, &(arg.pin), perm); \ ++ module_param_cb(name_prefix##type, ¶m_ops_int, &(arg.type), perm); \ ++ module_param_cb(name_prefix##val, ¶m_ops_int, &(arg.val), perm); ++ ++#define GK_IRQ_MODULE_PARAM_CALL(name_prefix, arg, perm) \ ++ module_param_cb(name_prefix##irq_gpio, ¶m_ops_int, &(arg.irq_gpio), perm); \ ++ module_param_cb(name_prefix##irq_line, ¶m_ops_int, &(arg.irq_line), perm); \ ++ module_param_cb(name_prefix##irq_type, ¶m_ops_int, &(arg.irq_type), perm); \ ++ module_param_cb(name_prefix##irq_gpio_val, ¶m_ops_int, &(arg.irq_gpio_val), perm); \ ++ module_param_cb(name_prefix##irq_gpio_mode, ¶m_ops_int, &(arg.irq_gpio_mode), perm) ++extern int gk_is_valid_gpio_irq(struct gk_gpio_irq_info *pgpio_irq); ++extern int gk_gpio_request_irq(struct gk_gpio_irq_info *pinfo); ++extern int gk_gpio_release_irq(u32 pin); ++int __init goke_init_gpio(void); ++void GH_GPIO_set_INPUT_CFG_in_sel(u8 index, u8 data); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++#endif /* _GK_GPIO_H_ */ ++ +diff --git a/arch/arm/plat-goke/include/plat/gk_gpio_v1_00.h b/arch/arm/plat-goke/include/plat/gk_gpio_v1_00.h +new file mode 100644 +index 00000000..f1ac8d9b +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/gk_gpio_v1_00.h +@@ -0,0 +1,320 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/plat-goke/include/plat/gk_gpio_v1_00.h ++** ++** \version $Id: gk_gpio_v1_00.h 10728 2016-10-21 02:05:33Z yulindeng $ ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2016 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef _GK_GPIO_V1_00_H_ ++#define _GK_GPIO_V1_00_H_ ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++/************************/ ++/* GPIO pins definition */ ++/************************/ ++#define GPIO_SET_OUT_SEL(n) ((n)&0x3F) ++#define GPIO_SET_IN_SEL(n) (((n)&0x3F)<<8) ++#define GPIO_SET_OEN_SEL(n) (((n)&0x3F)<<16) ++#define GPIO_SET_OUT_INVERT(n) (((n)&0x1)<<22) ++#define GPIO_SET_OEN_INVERT(n) (((n)&0x1)<<23) ++#define GPIO_SET_IOCTRL(n) (((n)&0x3F)<<24) ++#define GPIO_SET_FUNC(n) (((n)&0x3)<<30) ++ ++#define GPIO_GET_OUT_SEL(n) (((n)&0x0000003F)) ++#define GPIO_GET_IN_SEL(n) (((n)&0x00003F00)>>8) ++#define GPIO_GET_OEN_SEL(n) (((n)&0x003F0000)>>16) ++#define GPIO_GET_OUT_INVERT(n) (((n)&0x00400000)>>22) ++#define GPIO_GET_OEN_INVERT(n) (((n)&0x00800000)>>23) ++#define GPIO_GET_IOCTRL(n) (((n)&0x3F000000)>>24) ++#define GPIO_GET_FUNC(n) (((n)&0xC0000000)>>30) ++ ++#define IOCTRL_NORMAL 0x00 //!< Hi-z ++#define IOCTRL_PULL_UP 0x10 //!< PULL_UP ++#define IOCTRL_PULL_DOWN 0x20 //!< PULL_DOWN ++#define IOCTRL_REPEAT 0x30 //!< REPEAT ++ ++#define IOCTRL_2MA 0x00 //!< 2mA ++#define IOCTRL_4MA 0x01 //!< 4mA ++#define IOCTRL_8MA 0x02 //!< 8mA ++#define IOCTRL_12MA 0x03 //!< 12mA ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++typedef enum ++{ ++ /* ----------------------------------- GPIO output function define ----------------------------------- */ ++ GPIO_TYPE_OUTPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Output type: value = 0 ++ GPIO_TYPE_OUTPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 1), //!< Output type: value = 1 ++ GPIO_TYPE_OUTPUT_SPI1_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 2) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 2), //!< Output type: tssi_txd ++ GPIO_TYPE_OUTPUT_SPI1_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 3), //!< Output type: tssi_cs0_n ++ GPIO_TYPE_OUTPUT_SPI1_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 4), //!< Output type: tssi_sclk_out ++ GPIO_TYPE_OUTPUT_UART2_RTS_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 5), //!< Output type: uart2_rts_n ++ GPIO_TYPE_OUTPUT_UART2_DTR_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 6), //!< Output type: uart2_dtr_n ++ GPIO_TYPE_OUTPUT_UART2_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 7), //!< Output type: uart2_tx ++ GPIO_TYPE_OUTPUT_UART1_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 8), //!< Output type: uart1_tx ++ GPIO_TYPE_OUTPUT_UART0_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 9), //!< Output type: uart0_tx ++ GPIO_TYPE_OUTPUT_PWM3_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(10), //!< Output type: pwm3_out ++ GPIO_TYPE_OUTPUT_PWM2_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(11), //!< Output type: pwm2_out ++ GPIO_TYPE_OUTPUT_PWM1_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(12), //!< Output type: pwm1_out ++ GPIO_TYPE_OUTPUT_PWM0_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(13), //!< Output type: pwm0_out ++ GPIO_TYPE_OUTPUT_SPI0_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 7) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(14), //!< Output type: ssi_txd ++ GPIO_TYPE_OUTPUT_SPI0_CS7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(15), //!< Output type: ssi_cs7_n ++ GPIO_TYPE_OUTPUT_SPI0_CS6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(16), //!< Output type: ssi_cs6_n ++ GPIO_TYPE_OUTPUT_SPI0_CS5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(17), //!< Output type: ssi_cs5_n ++ GPIO_TYPE_OUTPUT_SPI0_CS4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(18), //!< Output type: ssi_cs4_n ++ GPIO_TYPE_OUTPUT_SPI0_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(19), //!< Output type: ssi_cs1_n ++ GPIO_TYPE_OUTPUT_SPI0_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(20), //!< Output type: ssi_cs0_n ++ GPIO_TYPE_OUTPUT_SPI0_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(21), //!< Output type: ssi_sclk_out ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL( 8) GPIO_SET_OUT_SEL(22) ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_OEN_SEL( 9) GPIO_SET_OUT_SEL(23) ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_OEN_SEL(10) GPIO_SET_OUT_SEL(24) ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_OEN_SEL(11) GPIO_SET_OUT_SEL(25) ++ //GPIO_TYPE_INOUT_SD_DATA_4 GPIO_SET_OEN_SEL(12) GPIO_SET_OUT_SEL(26) ++ //GPIO_TYPE_INOUT_SD_DATA_5 GPIO_SET_OEN_SEL(13) GPIO_SET_OUT_SEL(27) ++ //GPIO_TYPE_INOUT_SD_DATA_6 GPIO_SET_OEN_SEL(14) GPIO_SET_OUT_SEL(28) ++ //GPIO_TYPE_INOUT_SD_DATA_7 GPIO_SET_OEN_SEL(15) GPIO_SET_OUT_SEL(29) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_OEN_SEL(16) GPIO_SET_OUT_SEL(30) ++ GPIO_TYPE_OUTPUT_SDIO_CLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(31), //!< Output type: sd_clk_sdcard ++ GPIO_TYPE_OUTPUT_AOMCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(32), //!< Output type: i2s_au_clk ++ GPIO_TYPE_OUTPUT_AOBCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(17) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(33), //!< Output type: i2s_clk_o ++ GPIO_TYPE_OUTPUT_AOLRCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(18) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(34), //!< Output type: i2s_ws_o ++ GPIO_TYPE_OUTPUT_AO_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(35), //!< Output type: i2s_so ++ GPIO_TYPE_OUTPUT_SF_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(36), //!< Output type: sf_cs0_n ++ GPIO_TYPE_OUTPUT_SF_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(37), //!< Output type: sf_cs1_n ++ GPIO_TYPE_OUTPUT_EPHY_LED_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(38), //!< Output type: ephy_led[0] hcd ok ++ GPIO_TYPE_OUTPUT_EPHY_LED_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(39), //!< Output type: ephy_led[1] duplex ++ GPIO_TYPE_OUTPUT_EPHY_LED_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(40), //!< Output type: ephy_led[2] 10M CRS out ++ GPIO_TYPE_OUTPUT_EPHY_LED_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(41), //!< Output type: ephy_led[3] 100M CRS out ++ GPIO_TYPE_OUTPUT_EPHY_LED_4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(42), //!< Output type: ephy_led[4] clo gs ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(43), //!< Output type: enet_phy_txd[0] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(44), //!< Output type: enet_phy_txd[1] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(45), //!< Output type: enet_phy_txd[2] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(46), //!< Output type: enet_phy_txd[3] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXER = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(47), //!< Output type: enet_phy_txer ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXEN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(48), //!< Output type: enet_phy_txen ++ // GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_OUT_SEL(49) ++ GPIO_TYPE_OUTPUT_ENET_GMII_MDC_O = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(50), //!< Output type: enet_gmii_mdc_o ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(51), //!< Output type: ahb_dac_dr[0] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(52), //!< Output type: ahb_dac_dr[1] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(53), //!< Output type: ahb_dac_dr[2] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(54), //!< Output type: ahb_dac_dr[3] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(55), //!< Output type: ahb_dac_dr[4] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(56), //!< Output type: ahb_dac_dr[5] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(57), //!< Output type: ahb_dac_dr[6] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(58), //!< Output type: ahb_dac_dr[7] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_8 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(59), //!< Output type: ahb_dac_dr[8] ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_9 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(60), //!< Output type: ahb_dac_dr[9] ++ ++ /* ----------------------------------- GPIO input function define ----------------------------------- */ ++ GPIO_TYPE_INPUT = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_NORMAL|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 1) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_SPI1_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: tssi_rxd ++ //GPIO_TYPE_INOUT_I2C_DATA GPIO_SET_IN_SEL(2+ 1) ++ //GPIO_TYPE_INOUT_I2C_CLK GPIO_SET_IN_SEL(2+ 2) ++ //GPIO_TYPE_INOUT_I2C_DATA2 GPIO_SET_IN_SEL(2+ 3) ++ //GPIO_TYPE_INOUT_I2C_CLK2 GPIO_SET_IN_SEL(2+ 4) ++ GPIO_TYPE_INPUT_UART2_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 5) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart2_rx ++ GPIO_TYPE_INPUT_UART1_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 6) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart1_rx ++ GPIO_TYPE_INPUT_UART0_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 7) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart0_rx ++ GPIO_TYPE_INPUT_TIMER1_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 8) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer1_clk ++ GPIO_TYPE_INPUT_TIMER2_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 9) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer2_clk ++ GPIO_TYPE_INPUT_TIMER3_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+10) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer3_clk ++ GPIO_TYPE_INPUT_SPI0_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+11) | GPIO_SET_OUT_SEL( 0), //!< Input type: ssi_rxd ++ GPIO_TYPE_INPUT_SD_WP_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+12) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd_wp_n ++ GPIO_TYPE_INPUT_SD_CD_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+13) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd_cd_n ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_IN_SEL(2+14) ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_IN_SEL(2+15) ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_IN_SEL(2+16) ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_IN_SEL(2+17) ++ //GPIO_TYPE_INOUT_SD_DATA_4 GPIO_SET_IN_SEL(2+18) ++ //GPIO_TYPE_INOUT_SD_DATA_5 GPIO_SET_IN_SEL(2+19) ++ //GPIO_TYPE_INOUT_SD_DATA_6 GPIO_SET_IN_SEL(2+20) ++ //GPIO_TYPE_INOUT_SD_DATA_7 GPIO_SET_IN_SEL(2+21) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_IN_SEL(2+22) ++ GPIO_TYPE_INPUT_I2S_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+23) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_clk ++ GPIO_TYPE_INPUT_I2S_WS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+24) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_ws ++ GPIO_TYPE_INPUT_I2S_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+25) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_si ++ GPIO_TYPE_INPUT_CLK_AU = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+26) | GPIO_SET_OUT_SEL( 0), //!< Input type: clk_au ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+27) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[0] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+28) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[1] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_2 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+29) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[2] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_3 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+30) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[3] ++ GPIO_TYPE_INPUT_ENET_PHY_COL = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+31) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_col ++ GPIO_TYPE_INPUT_ENET_PHY_CRS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+32) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_crs ++ GPIO_TYPE_INPUT_ENET_PHY_RXER = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+33) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxer ++ GPIO_TYPE_INPUT_ENET_PHY_RXDV = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+34) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxdv ++ // GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_IN_SEL(2+35) ++ GPIO_TYPE_INPUT_ENET_CLK_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+36) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_clk_rx ++ GPIO_TYPE_INPUT_ENET_CLK_TX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+37) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_clk_tx ++ ++ /* ----------------------------------- GPIO input&&output function define ----------------------------------- */ ++ GPIO_TYPE_INOUT_I2C_DATA = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 3) | GPIO_SET_IN_SEL(2+ 1) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_sda ++ GPIO_TYPE_INOUT_I2C_CLK = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 4) | GPIO_SET_IN_SEL(2+ 2) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_scl ++ GPIO_TYPE_INOUT_I2C_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 5) | GPIO_SET_IN_SEL(2+ 3) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_sda2 ++ GPIO_TYPE_INOUT_I2C_CLK2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 6) | GPIO_SET_IN_SEL(2+ 4) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_scl2 ++ ++ GPIO_TYPE_INOUT_ETH_MDIO = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(19) | GPIO_SET_IN_SEL(2+35) | GPIO_SET_OUT_SEL(49), //!< Input/Output type: enet_gmii_mdi/enet_gmii_mod_o ++ ++ GPIO_TYPE_INOUT_SD_DATA_0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 8) | GPIO_SET_IN_SEL(2+14) | GPIO_SET_OUT_SEL(22), //!< Input/Output type: sd_data_out[0] ++ GPIO_TYPE_INOUT_SD_DATA_1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 9) | GPIO_SET_IN_SEL(2+15) | GPIO_SET_OUT_SEL(23), //!< Input/Output type: sd_data_out[1] ++ GPIO_TYPE_INOUT_SD_DATA_2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(10) | GPIO_SET_IN_SEL(2+16) | GPIO_SET_OUT_SEL(24), //!< Input/Output type: sd_data_out[2] ++ GPIO_TYPE_INOUT_SD_DATA_3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(11) | GPIO_SET_IN_SEL(2+17) | GPIO_SET_OUT_SEL(25), //!< Input/Output type: sd_data_out[3] ++ GPIO_TYPE_INOUT_SD_DATA_4 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(12) | GPIO_SET_IN_SEL(2+18) | GPIO_SET_OUT_SEL(26), //!< Input/Output type: sd_data_out[4] ++ GPIO_TYPE_INOUT_SD_DATA_5 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(13) | GPIO_SET_IN_SEL(2+19) | GPIO_SET_OUT_SEL(27), //!< Input/Output type: sd_data_out[5] ++ GPIO_TYPE_INOUT_SD_DATA_6 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(14) | GPIO_SET_IN_SEL(2+20) | GPIO_SET_OUT_SEL(28), //!< Input/Output type: sd_data_out[6] ++ GPIO_TYPE_INOUT_SD_DATA_7 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(15) | GPIO_SET_IN_SEL(2+21) | GPIO_SET_OUT_SEL(29), //!< Input/Output type: sd_data_out[7] ++ GPIO_TYPE_INOUT_SD_CMD = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(16) | GPIO_SET_IN_SEL(2+22) | GPIO_SET_OUT_SEL(30), //!< Input/Output : sd_cmd ++ ++ GPIO_TYPE_UNDEFINED = 0, ++} GPIO_TYPE_E; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++typedef union { /* PLL_IOCTRL_GPIO */ ++ u32 all; ++ struct { ++ u32 io1 : 6; ++ u32 : 2; ++ u32 io2 : 6; ++ u32 : 2; ++ u32 io0 : 6; ++ u32 : 2; ++ u32 io3 : 6; ++ u32 : 2; ++ } bitc; ++} GH_PLL_IOCTRL_GPIO_S; ++ ++typedef union { /* GPIO_OUTPUT_CFG */ ++ u32 all; ++ struct { ++ u32 out_sel : 6; ++ u32 : 2; ++ u32 oen_sel : 6; ++ u32 out_invert : 1; ++ u32 oen_invert : 1; ++ u32 : 16; ++ } bitc; ++} GH_GPIO_OUTPUT_CFG_S; ++ ++typedef union { /* GPIO_INPUT_CFG */ ++ u32 all; ++ struct { ++ u32 in_sel : 6; ++ u32 : 26; ++ } bitc; ++} GH_GPIO_INPUT_CFG_S; ++ ++typedef union { /* GPIO_INT_EN */ ++ u32 all; ++ struct { ++ u32 int_en : 1; ++ u32 : 31; ++ } bitc; ++} GH_GPIO_INT_EN_S; ++ ++typedef struct gpio_cfg ++{ ++ u32 gpio_count; ++ GPIO_XREF_S gpio_chip[64]; ++ u32 extphy_gpio_count; ++ GPIO_XREF_S ext_phy_gpio[16]; ++ u32 intphy_gpio_count; ++ GPIO_XREF_S int_phy_gpio[16]; ++ ++ u32 ir_led_ctl; ++ u32 ir_cut1; ++ u32 ir_cut2; ++ ++ u32 sensor_reset; ++ ++ u32 phy_reset; ++ u32 phy_speed_led; ++ ++ u32 spi0_en0; ++ u32 spi1_en0; ++ ++ u32 pwm0; ++ u32 pwm1; ++ u32 pwm2; ++ u32 pwm3; ++ ++ u32 usb_host; ++ ++ u32 sd_detect; ++ u32 sd_power; ++ ++ //board info ++ u32 soc_type; ++ s8 board_type[32]; ++ u32 board_version; ++ u32 reserve1; ++ ++ //extra device info ++ u32 ext_phy_clk; ++ u32 reserve2; ++ ++ // Add by Steven Yu:for pmu ++ u32 pmu_ctl; ++ ++}gpio_cfg_t; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++extern gpio_cfg_t gk_all_gpio_cfg; ++extern u8 cmdline_phytype; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++#endif /* _GK_GPIO_V1_00_H_ */ ++ +diff --git a/arch/arm/plat-goke/include/plat/gk_gpio_v1_10.h b/arch/arm/plat-goke/include/plat/gk_gpio_v1_10.h +new file mode 100644 +index 00000000..e83395c5 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/gk_gpio_v1_10.h +@@ -0,0 +1,506 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/plat-goke/include/plat/gk_gpio_v1_10.h ++** ++** \version $Id: gk_gpio_v1_10.h 10728 2016-10-21 02:05:33Z yulindeng $ ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2016 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef _GK_GPIO_V1_10_H_ ++#define _GK_GPIO_V1_10_H_ ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++/************************/ ++/* GPIO pins definition */ ++/************************/ ++#define GPIO_SET_OUT_SEL(n) ((n)&0x7F) ++#define GPIO_SET_IN_SEL(n) (((n)&0x7F)<<7) ++#define GPIO_SET_OEN_SEL(n) (((n)&0x7F)<<14) ++#define GPIO_SET_OUT_INVERT(n) (((n)&0x1)<<22) ++#define GPIO_SET_OEN_INVERT(n) (((n)&0x1)<<23) ++#define GPIO_SET_IOCTRL(n) (((n)&0x3F)<<24) ++#define GPIO_SET_FUNC(n) (((n)&0x3)<<30) ++ ++#define GPIO_GET_OUT_SEL(n) (((n)&0x0000007F)) ++#define GPIO_GET_IN_SEL(n) (((n)&0x00003F80)>>7) ++#define GPIO_GET_OEN_SEL(n) (((n)&0x001FC000)>>14) ++#define GPIO_GET_OUT_INVERT(n) (((n)&0x00400000)>>22) ++#define GPIO_GET_OEN_INVERT(n) (((n)&0x00800000)>>23) ++#define GPIO_GET_IOCTRL(n) (((n)&0x3F000000)>>24) ++#define GPIO_GET_FUNC(n) (((n)&0xC0000000)>>30) ++ ++#define IOCTRL_NORMAL 0x00 //!< Hi-z ++#define IOCTRL_PULL_UP 0x10 //!< PULL_UP ++#define IOCTRL_PULL_DOWN 0x20 //!< PULL_DOWN ++#define IOCTRL_REPEAT 0x30 //!< REPEAT ++ ++#define IOCTRL_2MA 0x00 //!< 2mA ++#define IOCTRL_4MA 0x01 //!< 4mA ++#define IOCTRL_8MA 0x02 //!< 8mA ++#define IOCTRL_12MA 0x03 //!< 12mA ++#define IOCTRL_10MA 0x03 //!< 10mA ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++typedef enum ++{ ++ /* ----------------------------------- GPIO output function define ----------------------------------- */ ++ //GPIO_SET_OUT_SEL( 0) ++ //GPIO_SET_OUT_SEL( 1) ++ //GPIO_SET_OUT_SEL( 2) ++ GPIO_TYPE_OUTPUT_JTAG_TDO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 3) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 3), //!< 3.Output type: pad_jtag_tdo ++ //GPIO_TYPE_INOUT_I2C_CLK GPIO_SET_OEN_SEL( 4) | GPIO_SET_IN_SEL( 4) | GPIO_SET_OUT_SEL( 4), //!< 4.Input/Output type : pad_sensor_scl ++ //GPIO_TYPE_INOUT_I2C_DATA GPIO_SET_OEN_SEL( 5) | GPIO_SET_IN_SEL( 5) | GPIO_SET_OUT_SEL( 5), //!< 5.Input/Output type : pad_sensor_sda ++ GPIO_TYPE_OUTPUT_SENSOR_RESET = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 6), //!< 6.Output type: pad_sensor_reset ++ GPIO_TYPE_OUTPUT_SENSOR_POWEREN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 7), //!< 7.Output type: pad_sensor_poweren ++ GPIO_TYPE_OUTPUT_LCD_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 8), //!< 8.Output type: pad_lcd_data0 ++ GPIO_TYPE_OUTPUT_LCD_DATA1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 9), //!< 9.Output type: pad_lcd_data1 ++ GPIO_TYPE_OUTPUT_LCD_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 10), //!< 10.Output type: pad_lcd_data2 ++ GPIO_TYPE_OUTPUT_LCD_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 11), //!< 11.Output type: pad_lcd_data3 ++ GPIO_TYPE_OUTPUT_LCD_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 12), //!< 12.Output type: pad_lcd_data4 ++ GPIO_TYPE_OUTPUT_LCD_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 13), //!< 13.Output type: pad_lcd_data5 ++ GPIO_TYPE_OUTPUT_LCD_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 14), //!< 14.Output type: pad_lcd_data6 ++ GPIO_TYPE_OUTPUT_LCD_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 15), //!< 15.Output type: pad_lcd_data7 ++ GPIO_TYPE_OUTPUT_LCD_DATA8 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 16), //!< 16.Output type: pad_lcd_data8 ++ GPIO_TYPE_OUTPUT_LCD_DATA9 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 17), //!< 17.Output type: pad_lcd_data9 ++ GPIO_TYPE_OUTPUT_LCD_DATA10 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 18), //!< 18.Output type: pad_lcd_data10 ++ GPIO_TYPE_OUTPUT_LCD_DATA11 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 19), //!< 19.Output type: pad_lcd_data11 ++ GPIO_TYPE_OUTPUT_LCD_DATA12 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 20), //!< 20.Output type: pad_lcd_data12 ++ GPIO_TYPE_OUTPUT_LCD_DATA13 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 21), //!< 21.Output type: pad_lcd_data13 ++ GPIO_TYPE_OUTPUT_LCD_DATA14 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 22), //!< 22.Output type: pad_lcd_data14 ++ GPIO_TYPE_OUTPUT_LCD_DATA15 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 23), //!< 23.Output type: pad_lcd_data15 ++ GPIO_TYPE_OUTPUT_LCD_DATA16 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 24), //!< 24.Output type: pad_lcd_data16 ++ GPIO_TYPE_OUTPUT_LCD_DATA17 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 25), //!< 25.Output type: pad_lcd_data17 ++ GPIO_TYPE_OUTPUT_LCD_DATA18 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 26), //!< 26.Output type: pad_lcd_data18 ++ GPIO_TYPE_OUTPUT_LCD_DATA19 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 27), //!< 27.Output type: pad_lcd_data19 ++ GPIO_TYPE_OUTPUT_LCD_DATA20 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 28), //!< 28.Output type: pad_lcd_data20 ++ GPIO_TYPE_OUTPUT_LCD_DATA21 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 29), //!< 29.Output type: pad_lcd_data21 ++ GPIO_TYPE_OUTPUT_LCD_DATA22 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 30), //!< 30.Output type: pad_lcd_data22 ++ GPIO_TYPE_OUTPUT_LCD_DATA23 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 31), //!< 31.Output type: pad_lcd_data23 ++ GPIO_TYPE_OUTPUT_LCD_DEN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 32), //!< 32.Output type: pad_lcd_den ++ GPIO_TYPE_OUTPUT_LCD_VSYNC = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 33), //!< 33.Output type: pad_lcd_vsync ++ GPIO_TYPE_OUTPUT_LCD_HSYNC = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 34), //!< 34.Output type: pad_lcd_hsync ++ GPIO_TYPE_OUTPUT_LCD_CLOCK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_10MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 35), //!< 35.Output type: pad_lcd_clock ++ //GPIO_TYPE_INOUT_I2C_CLK2 GPIO_SET_OEN_SEL( 36) | GPIO_SET_IN_SEL( 36) | GPIO_SET_OUT_SEL( 36), //!< 36.Input/Output type : pad_lcd_scl ++ //GPIO_TYPE_INOUT_I2C_DATA2 GPIO_SET_OEN_SEL( 37) | GPIO_SET_IN_SEL( 37) | GPIO_SET_OUT_SEL( 37), //!< 37.Input/Output type : pad_lcd_sda ++ GPIO_TYPE_OUTPUT_LCD_CS = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 38), //!< 38.Output type: pad_lcd_cs ++ GPIO_TYPE_OUTPUT_LCD_RESET = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 39), //!< 39.Output type: pad_lcd_reset ++ GPIO_TYPE_OUTPUT_LCD_BL_EN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 40), //!< 40.Output type: pad_lcd_bl_en ++ //GPIO_TYPE_INPUT_USB_OTG_ID GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 41) | GPIO_SET_OUT_SEL( 41), //!< 41.Input type: pad_usb_otg_id ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL( 42) | GPIO_SET_IN_SEL( 42) | GPIO_SET_OUT_SEL( 42), //!< 42.Input/Output type : pad_sd0_d0 ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_OEN_SEL( 43) | GPIO_SET_IN_SEL( 43) | GPIO_SET_OUT_SEL( 43), //!< 43.Input/Output type : pad_sd0_d1 ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_OEN_SEL( 44) | GPIO_SET_IN_SEL( 44) | GPIO_SET_OUT_SEL( 44), //!< 44.Input/Output type : pad_sd0_d2 ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_OEN_SEL( 45) | GPIO_SET_IN_SEL( 45) | GPIO_SET_OUT_SEL( 45), //!< 45.Input/Output type : pad_sd0_d3 ++ GPIO_TYPE_OUTPUT_SDIO_CLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_REPEAT |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 46) | GPIO_SET_IN_SEL( 46) | GPIO_SET_OUT_SEL( 46), //!< 46.Output type: pad_sd0_clk ++ //GPIO_TYPE_INOUT_SD_CMD GPIO_SET_OEN_SEL( 47) | GPIO_SET_IN_SEL( 47) | GPIO_SET_OUT_SEL( 47), //!< 47.Input/Output type : pad_sd0_cmd ++ GPIO_TYPE_INPUT_SD_CD_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 48) | GPIO_SET_IN_SEL( 48) | GPIO_SET_OUT_SEL( 48), //!< 48.Output type: pad_sd0_cd ++ //GPIO_TYPE_INPUT_SPI0_SI GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 49) | GPIO_SET_OUT_SEL( 49), //!< 49.Input type: pad_spi_si ++ GPIO_TYPE_OUTPUT_SPI0_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 50) | GPIO_SET_IN_SEL( 50) | GPIO_SET_OUT_SEL( 50), //!< 50.Output type: pad_spi_so ++ GPIO_TYPE_OUTPUT_SPI0_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 51) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 51), //!< 51.Output type: pad_spi_cs ++ GPIO_TYPE_OUTPUT_SPI0_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 52) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 52), //!< 52.Output type: pad_spi_sclk ++ //GPIO_TYPE_INPUT_UART0_RX GPIO_SET_OEN_SEL( 53) | GPIO_SET_IN_SEL( 53) | GPIO_SET_OUT_SEL( 53), //!< 53.Input type: pad_uart_rx ++ GPIO_TYPE_OUTPUT_UART0_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 54) | GPIO_SET_IN_SEL( 54) | GPIO_SET_OUT_SEL( 54), //!< 54.Output type: pad_uart_tx ++ GPIO_TYPE_OUTPUT_GPS_POWER_EN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 55), //!< 55.Output type: pad_gps_power_en ++ GPIO_TYPE_OUTPUT_GPS_TXD = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 56) | GPIO_SET_IN_SEL( 56) | GPIO_SET_OUT_SEL( 56), //!< 56.Output type: pad_gps_tx ++ //GPIO_TYPE_INPUT_GPS_RXD GPIO_SET_OEN_SEL( 57) | GPIO_SET_IN_SEL( 57) | GPIO_SET_OUT_SEL( 57), //!< 57.Input type: pad_gps_rx ++ GPIO_TYPE_OUTPUT_RD_POWER_EN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL( 58) | GPIO_SET_OUT_SEL( 58), //!< 58.Output type: pad_rd_power_en ++ //GPIO_TYPE_INPUT_RD_RXD GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 59) | GPIO_SET_OUT_SEL( 59), //!< 59.Input type: pad_rd_rx ++ //GPIO_TYPE_INOUT_I2C_CLK3 GPIO_SET_OEN_SEL( 60) | GPIO_SET_IN_SEL( 60) | GPIO_SET_OUT_SEL( 60), //!< 60.Input/Output type : pad_g_sen_sck ++ //GPIO_TYPE_INOUT_I2C_DATA3 GPIO_SET_OEN_SEL( 61) | GPIO_SET_IN_SEL( 61) | GPIO_SET_OUT_SEL( 61), //!< 61.Input/Output type : pad_g_sen_sda ++ GPIO_TYPE_OUTPUT_SF_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 62) | GPIO_SET_IN_SEL( 62) | GPIO_SET_OUT_SEL( 62), //!< 62.Output type: pad_sf_cs ++ GPIO_TYPE_OUTPUT_PWM = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL( 63) | GPIO_SET_OUT_SEL( 63), //!< 63.Output type: pad_pwm ++ GPIO_TYPE_OUTPUT_I2S_MCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 64) | GPIO_SET_IN_SEL( 64) | GPIO_SET_OUT_SEL( 64), //!< 64.Output type: pad_i2s_mclk ++ //GPIO_TYPE_INOUT_I2S_SCLK GPIO_SET_OEN_SEL( 65) | GPIO_SET_IN_SEL( 65) | GPIO_SET_OUT_SEL( 65), //!< 65.Input/Output type : pad_i2s_sclk ++ //GPIO_TYPE_INOUT_I2S_WS GPIO_SET_OEN_SEL( 66) | GPIO_SET_IN_SEL( 66) | GPIO_SET_OUT_SEL( 66), //!< 66.Input/Output type : pad_i2s_ws ++ //GPIO_TYPE_INPUT_I2S_SDATA0 GPIO_SET_OEN_SEL( 67) | GPIO_SET_IN_SEL( 67) | GPIO_SET_OUT_SEL( 67), //!< 67.Input type: pad_i2s_sdata0 ++ GPIO_TYPE_OUTPUT_I2S_SDATA1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 68) | GPIO_SET_IN_SEL( 68) | GPIO_SET_OUT_SEL( 68), //!< 68.Output type: pad_i2s_data1 ++ GPIO_TYPE_OUTPUT_SPI0_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 74) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 69), //!< 69.Output type: ss_1_n ++ GPIO_TYPE_OUTPUT_SPI0_CS4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 74) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 70), //!< 70.Output type: ss_4_n ++ GPIO_TYPE_OUTPUT_SPI0_CS5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 74) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 71), //!< 71.Output type: ss_5_n ++ GPIO_TYPE_OUTPUT_SPI0_CS6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 74) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 72), //!< 72.Output type: ss_6_n ++ GPIO_TYPE_OUTPUT_SPI0_CS7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 74) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 73), //!< 73.Output type: ss_7_n ++ GPIO_TYPE_OUTPUT_SS_TXD2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 74), //!< 74.Output type: txd2 ++ GPIO_TYPE_OUTPUT_SCLK2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 75), //!< 75.Output type: sclk2_out ++ GPIO_TYPE_OUTPUT_RTS2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 76), //!< 76.Output type: rts_2_n ++ GPIO_TYPE_OUTPUT_DTR2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 77), //!< 77.Output type: dtr_2_n ++ GPIO_TYPE_OUTPUT_UART1_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 78), //!< 78.Output type: UART_TX_2 ++ GPIO_TYPE_OUTPUT_UART2_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 79), //!< 79.Output type: UART_TX_3 ++ //GPIO_SET_OUT_SEL( 80) ++ //GPIO_SET_OUT_SEL( 81) ++ GPIO_TYPE_OUTPUT_EPHY_LED_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 82), //!< 82.Output type: enet_phy_led0 ++ GPIO_TYPE_OUTPUT_EPHY_LED_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 83), //!< 83.Output type: enet_phy_led1 ++ GPIO_TYPE_OUTPUT_EPHY_LED_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 84), //!< 84.Output type: enet_phy_led2 ++ GPIO_TYPE_OUTPUT_EPHY_LED_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 85), //!< 85.Output type: enet_phy_led3 ++ GPIO_TYPE_OUTPUT_EPHY_LED_4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 86), //!< 86.Output type: enet_phy_led4 ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 87), //!< 87.Output type: enet_phy_txd0 ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 88), //!< 88.Output type: enet_phy_txd1 ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 89), //!< 89.Output type: enet_phy_txd2 ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 90), //!< 90.Output type: enet_phy_txd3 ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXER = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 91), //!< 91.Output type: enet_phy_txer ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXEN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 92), //!< 92.Output type: enet_phy_txen ++ //GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_OEN_SEL( 69) | GPIO_SET_IN_SEL( 87) | GPIO_SET_OUT_SEL( 93), //!< 93.Output type: enet_gmii_mdo_o ++ GPIO_TYPE_OUTPUT_ENET_GMII_MDC_O = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 94), //!< 94.Output type: enet_gmii_mdc_o ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 95), //!< 95.Output type: ahd_dac_dr0 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 96), //!< 96.Output type: ahd_dac_dr1 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 97), //!< 97.Output type: ahd_dac_dr2 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 98), //!< 98.Output type: ahd_dac_dr3 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL( 99), //!< 99.Output type: ahd_dac_dr4 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(100), //!<100.Output type: ahd_dac_dr5 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(101), //!<101.Output type: ahd_dac_dr6 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(102), //!<102.Output type: ahd_dac_dr7 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_8 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(103), //!<103.Output type: ahd_dac_dr8 ++ GPIO_TYPE_OUTPUT_AHB_DAC_DR_9 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(104), //!<104.Output type: ahd_dac_dr9 ++ GPIO_TYPE_OUTPUT_I80_RESET = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(105), //!<105.Output type: i80_reset ++ GPIO_TYPE_OUTPUT_I80_CS = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(106), //!<106.Output type: i80_cs ++ GPIO_TYPE_OUTPUT_I80_RD = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(107), //!<107.Output type: i80_rd ++ GPIO_TYPE_OUTPUT_I80_WR = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(108), //!<108.Output type: i80_wr ++ GPIO_TYPE_OUTPUT_I80_RS = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(109), //!<109.Output type: i80_rs ++ //GPIO_TYPE_INOUT_I80_D8 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 16) | GPIO_SET_OUT_SEL(110), //!<110.Output type: i80_d8 ++ //GPIO_TYPE_INOUT_I80_D7 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 15) | GPIO_SET_OUT_SEL(111), //!<111.Output type: i80_d7 ++ //GPIO_TYPE_INOUT_I80_D6 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 14) | GPIO_SET_OUT_SEL(112), //!<112.Output type: i80_d6 ++ //GPIO_TYPE_INOUT_I80_D5 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 13) | GPIO_SET_OUT_SEL(113), //!<113.Output type: i80_d5 ++ //GPIO_TYPE_INOUT_I80_D4 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 12) | GPIO_SET_OUT_SEL(114), //!<114.Output type: i80_d4 ++ //GPIO_TYPE_INOUT_I80_D3 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 11) | GPIO_SET_OUT_SEL(115), //!<115.Output type: i80_d3 ++ //GPIO_TYPE_INOUT_I80_D2 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 10) | GPIO_SET_OUT_SEL(116), //!<116.Output type: i80_d2 ++ //GPIO_TYPE_INOUT_I80_D1 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 9) | GPIO_SET_OUT_SEL(117), //!<117.Output type: i80_d1 ++ //GPIO_TYPE_INOUT_I80_D0 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 8) | GPIO_SET_OUT_SEL(118), //!<118.Output type: i80_d0 ++ GPIO_TYPE_INPUT_UART3_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(119), //!<119.Output type: UART_ORC_TX ++ //GPIO_SET_OUT_SEL(120) ++ //GPIO_SET_OUT_SEL(121) ++ //GPIO_SET_OUT_SEL(122) ++ //GPIO_SET_OUT_SEL(123) ++ //GPIO_SET_OUT_SEL(124) ++ //GPIO_SET_OUT_SEL(125) ++ GPIO_TYPE_OUTPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(126), //!< Output type: value = 0 ++ GPIO_TYPE_OUTPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(127), //!< Output type: value = 1 ++ ++ /* ----------------------------------- GPIO input function define ----------------------------------- */ ++ GPIO_TYPE_INPUT_JTAG_TRSTN = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< 0. Input type: pad_jtag_trstn ++ GPIO_TYPE_INPUT_JTAG_TMS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 1) | GPIO_SET_OUT_SEL( 0), //!< 1. Input type: pad_jtag_tms ++ GPIO_TYPE_INPUT_JTAG_TDI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 2) | GPIO_SET_IN_SEL( 2) | GPIO_SET_OUT_SEL( 0), //!< 2. Input type: pad_jtag_tdi ++ //GPIO_SET_IN_SEL( 3) ++ //GPIO_TYPE_INOUT_I2C_CLK GPIO_SET_OEN_SEL( 4) | GPIO_SET_IN_SEL( 4) | GPIO_SET_OUT_SEL( 4), //!< 4. Input/Output type : pad_sensor_scl ++ //GPIO_TYPE_INOUT_I2C_DATA GPIO_SET_OEN_SEL( 5) | GPIO_SET_IN_SEL( 5) | GPIO_SET_OUT_SEL( 5), //!< 5. Input/Output type : pad_sensor_sda ++ //GPIO_SET_IN_SEL( 6) ++ //GPIO_SET_IN_SEL( 7) ++ //GPIO_TYPE_INOUT_I80_D0 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 8) | GPIO_SET_OUT_SEL(118), //!<118.Output type: i80_d0 ++ //GPIO_TYPE_INOUT_I80_D1 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 9) | GPIO_SET_OUT_SEL(117), //!<117.Output type: i80_d1 ++ //GPIO_TYPE_INOUT_I80_D2 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 10) | GPIO_SET_OUT_SEL(116), //!<116.Output type: i80_d2 ++ //GPIO_TYPE_INOUT_I80_D3 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 11) | GPIO_SET_OUT_SEL(115), //!<115.Output type: i80_d3 ++ //GPIO_TYPE_INOUT_I80_D4 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 12) | GPIO_SET_OUT_SEL(114), //!<114.Output type: i80_d4 ++ //GPIO_TYPE_INOUT_I80_D5 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 13) | GPIO_SET_OUT_SEL(113), //!<113.Output type: i80_d5 ++ //GPIO_TYPE_INOUT_I80_D6 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 14) | GPIO_SET_OUT_SEL(112), //!<112.Output type: i80_d6 ++ //GPIO_TYPE_INOUT_I80_D7 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 15) | GPIO_SET_OUT_SEL(111), //!<111.Output type: i80_d7 ++ //GPIO_TYPE_INOUT_I80_D8 GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 16) | GPIO_SET_OUT_SEL(110), //!<110.Output type: i80_d8 ++ //GPIO_SET_IN_SEL( 17) ++ //GPIO_SET_IN_SEL( 18) ++ //GPIO_SET_IN_SEL( 19) ++ //GPIO_SET_IN_SEL( 20) ++ //GPIO_SET_IN_SEL( 21) ++ //GPIO_SET_IN_SEL( 22) ++ //GPIO_SET_IN_SEL( 23) ++ //GPIO_SET_IN_SEL( 24) ++ //GPIO_SET_IN_SEL( 25) ++ //GPIO_SET_IN_SEL( 26) ++ //GPIO_SET_IN_SEL( 27) ++ //GPIO_SET_IN_SEL( 28) ++ //GPIO_SET_IN_SEL( 29) ++ //GPIO_SET_IN_SEL( 30) ++ //GPIO_SET_IN_SEL( 31) ++ //GPIO_SET_IN_SEL( 32) ++ //GPIO_SET_IN_SEL( 33) ++ //GPIO_SET_IN_SEL( 34) ++ //GPIO_SET_IN_SEL( 35) ++ //GPIO_TYPE_INOUT_I2C_CLK2 GPIO_SET_OEN_SEL( 36) | GPIO_SET_IN_SEL( 36) | GPIO_SET_OUT_SEL( 36), //!< 36.Input/Output type : pad_lcd_scl ++ //GPIO_TYPE_INOUT_I2C_DATA2 GPIO_SET_OEN_SEL( 37) | GPIO_SET_IN_SEL( 37) | GPIO_SET_OUT_SEL( 37), //!< 37.Input/Output type : pad_lcd_sda ++ //GPIO_SET_IN_SEL( 38) ++ //GPIO_SET_IN_SEL( 39) ++ //GPIO_SET_IN_SEL( 40) ++ GPIO_TYPE_INPUT_USB_OTG_ID = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_REPEAT |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 41) | GPIO_SET_OUT_SEL( 41), //!< 41.Input type: pad_usb_otg_id ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL( 42) | GPIO_SET_IN_SEL( 42) | GPIO_SET_OUT_SEL( 42), //!< 42.Input/Output type : pad_sd0_d0 ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_OEN_SEL( 43) | GPIO_SET_IN_SEL( 43) | GPIO_SET_OUT_SEL( 43), //!< 43.Input/Output type : pad_sd0_d1 ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_OEN_SEL( 44) | GPIO_SET_IN_SEL( 44) | GPIO_SET_OUT_SEL( 44), //!< 44.Input/Output type : pad_sd0_d2 ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_OEN_SEL( 45) | GPIO_SET_IN_SEL( 45) | GPIO_SET_OUT_SEL( 45), //!< 45.Input/Output type : pad_sd0_d3 ++ //GPIO_TYPE_OUTPUT_SDIO_CLK GPIO_SET_OEN_SEL( 46) | GPIO_SET_IN_SEL( 46) | GPIO_SET_OUT_SEL( 46), //!< 46.Output type: pad_sd0_clk ++ //GPIO_TYPE_INOUT_SD_CMD GPIO_SET_OEN_SEL( 47) | GPIO_SET_IN_SEL( 47) | GPIO_SET_OUT_SEL( 47), //!< 47.Input/Output type : pad_sd0_cmd ++ //GPIO_TYPE_INPUT_SD_CD_N GPIO_SET_OEN_SEL( 48) | GPIO_SET_IN_SEL( 48) | GPIO_SET_OUT_SEL( 48), //!< 48.Output type: pad_sd0_cd ++ GPIO_TYPE_INPUT_SPI0_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 49) | GPIO_SET_OUT_SEL( 49), //!< 49.Input type: pad_spi_si ++ //PIO_TYPE_OUTPUT_SPI_SO GPIO_SET_OEN_SEL( 50) | GPIO_SET_IN_SEL( 50) | GPIO_SET_OUT_SEL( 50), //!< 50.Output type: pad_spi_so ++ //GPIO_SET_IN_SEL( 51) ++ //GPIO_SET_IN_SEL( 52) ++ GPIO_TYPE_INPUT_UART0_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 53) | GPIO_SET_IN_SEL( 53) | GPIO_SET_OUT_SEL( 53), //!< 53.Input type: pad_uart_rx ++ //GPIO_TYPE_OUTPUT_UART0_TX GPIO_SET_OEN_SEL( 54) | GPIO_SET_IN_SEL( 54) | GPIO_SET_OUT_SEL( 54), //!< 54.Output type: pad_uart_tx ++ //GPIO_SET_IN_SEL( 55) ++ //GPIO_TYPE_OUTPUT_GPS_TXD GPIO_SET_OEN_SEL( 56) | GPIO_SET_IN_SEL( 56) | GPIO_SET_OUT_SEL( 56), //!< 56.Output type: pad_gps_tx ++ GPIO_TYPE_INPUT_GPS_RXD = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 57) | GPIO_SET_IN_SEL( 57) | GPIO_SET_OUT_SEL( 57), //!< 57.Input type: pad_gps_rx ++ //GPIO_TYPE_OUTPUT_RD_POWER_EN GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL( 58) | GPIO_SET_OUT_SEL( 58), //!< 58.Output type: pad_rd_power_en ++ GPIO_TYPE_INPUT_RD_RXD = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 59) | GPIO_SET_OUT_SEL( 59), //!< 59.Input type: pad_rd_rx ++ //GPIO_TYPE_INOUT_I2C_CLK3 GPIO_SET_OEN_SEL( 60) | GPIO_SET_IN_SEL( 60) | GPIO_SET_OUT_SEL( 60), //!< 60.Input/Output type : pad_g_sen_sck ++ //GPIO_TYPE_INOUT_I2C_DATA3 GPIO_SET_OEN_SEL( 61) | GPIO_SET_IN_SEL( 61) | GPIO_SET_OUT_SEL( 61), //!< 61.Input/Output type : pad_g_sen_sda ++ //GPIO_TYPE_OUTPUT_SF_CS0 GPIO_SET_OEN_SEL( 62) | GPIO_SET_IN_SEL( 62) | GPIO_SET_OUT_SEL( 62), //!< 62.Output type: pad_sf_cs ++ //GPIO_TYPE_OUTPUT_PWM GPIO_SET_OEN_SEL(126) | GPIO_SET_IN_SEL( 63) | GPIO_SET_OUT_SEL( 63), //!< 63.Output type: pad_pwm ++ //GPIO_TYPE_OUTPUT_I2S_MCLK GPIO_SET_OEN_SEL( 64) | GPIO_SET_IN_SEL( 64) | GPIO_SET_OUT_SEL( 64), //!< 64.Output type: pad_i2s_mclk ++ //GPIO_TYPE_INOUT_I2S_SCLK GPIO_SET_OEN_SEL( 65) | GPIO_SET_IN_SEL( 65) | GPIO_SET_OUT_SEL( 65), //!< 65.Input/Output type : pad_i2s_sclk ++ //GPIO_TYPE_INOUT_I2S_WS GPIO_SET_OEN_SEL( 66) | GPIO_SET_IN_SEL( 66) | GPIO_SET_OUT_SEL( 66), //!< 66.Input/Output type : pad_i2s_ws ++ //GPIO_TYPE_INPUT_I2S_SDATA0 GPIO_SET_OEN_SEL( 67) | GPIO_SET_IN_SEL( 67) | GPIO_SET_OUT_SEL( 67), //!< 67.Input type: pad_i2s_sdata0 ++ //GPIO_TYPE_OUTPUT_I2S_SDATA1 GPIO_SET_OEN_SEL( 68) | GPIO_SET_IN_SEL( 68) | GPIO_SET_OUT_SEL( 68), //!< 68.Output type: pad_i2s_data1 ++ GPIO_TYPE_INPUT_TIMER1_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 69) | GPIO_SET_OUT_SEL(126), //!< 69.Input type: tm11_clk ++ GPIO_TYPE_INPUT_TIMER2_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 70) | GPIO_SET_OUT_SEL(126), //!< 70.Input type: tm12_clk ++ GPIO_TYPE_INPUT_TIMER3_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 71) | GPIO_SET_OUT_SEL(126), //!< 71.Input type: tm13_clk ++ GPIO_TYPE_INPUT_SD_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 70) | GPIO_SET_IN_SEL( 72) | GPIO_SET_OUT_SEL(126), //!< Input type: sd_data4_in ++ GPIO_TYPE_INPUT_SD_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 71) | GPIO_SET_IN_SEL( 73) | GPIO_SET_OUT_SEL(126), //!< Input type: sd_data5_in ++ GPIO_TYPE_INPUT_SD_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 72) | GPIO_SET_IN_SEL( 74) | GPIO_SET_OUT_SEL(126), //!< Input type: sd_data6_in ++ GPIO_TYPE_INPUT_SD_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 73) | GPIO_SET_IN_SEL( 75) | GPIO_SET_OUT_SEL(126), //!< Input type: sd_data7_in ++ GPIO_TYPE_INPUT_ENET_CLK_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 76) | GPIO_SET_OUT_SEL(126), //!< 76.Input type: gpio_clk_rx_i ++ GPIO_TYPE_INPUT_ENET_CLK_TX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 77) | GPIO_SET_OUT_SEL(126), //!< 77.Input type: gpio_clk_tx_i ++ GPIO_TYPE_INPUT_GPIO_RCT_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 78) | GPIO_SET_OUT_SEL(126), //!< 78.Input type: gpio_rct_clk_au ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 79) | GPIO_SET_OUT_SEL(126), //!< 79.Input type: gpio_phy_rxd0 ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 80) | GPIO_SET_OUT_SEL(126), //!< 80.Input type: gpio_phy_rxd1 ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_2 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_REPEAT |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 81) | GPIO_SET_OUT_SEL(126), //!< 81.Input type: gpio_phy_rxd2 ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_3 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 82) | GPIO_SET_OUT_SEL(126), //!< 82.Input type: gpio_phy_rxd3 ++ GPIO_TYPE_INPUT_ENET_PHY_COL = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 83) | GPIO_SET_OUT_SEL(126), //!< 83.Input type: gpio_phy_cil_i ++ GPIO_TYPE_INPUT_ENET_PHY_CRS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 84) | GPIO_SET_OUT_SEL(126), //!< 84.Input type: gpio_phy_crs_i ++ GPIO_TYPE_INPUT_ENET_PHY_RXER = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 85) | GPIO_SET_OUT_SEL(126), //!< 85.Input type: gpio_phy_rxer ++ GPIO_TYPE_INPUT_ENET_PHY_RXDV = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 86) | GPIO_SET_OUT_SEL(126), //!< 86.Input type: gpio_phy_rxdv ++ //GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_OEN_SEL( 69) | GPIO_SET_IN_SEL( 87) | GPIO_SET_OUT_SEL( 93), //!< 93.Output type: enet_gmii_mdo_o ++ GPIO_TYPE_INPUT_UART1_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 88) | GPIO_SET_OUT_SEL(126), //!< 88.Input type: UART_RX_2 ++ GPIO_TYPE_INPUT_UART2_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 89) | GPIO_SET_OUT_SEL(126), //!< 89.Input type: UART_RX_3 ++ GPIO_TYPE_INPUT_SS_RXD2 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 90) | GPIO_SET_OUT_SEL(126), //!< 90.Input type: usrt3rx ++ GPIO_TYPE_INPUT_SD_WP_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 91) | GPIO_SET_OUT_SEL(126), //!< 91.Input type: sdwp_n ++ GPIO_TYPE_INPUT_SD_WP3 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 92) | GPIO_SET_OUT_SEL(126), //!< 92.Input type: sdwp_n3 ++ GPIO_TYPE_INPUT_UART3_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL( 93) | GPIO_SET_OUT_SEL(126), //!< 93.Input type: UART_ORC_RX ++ //GPIO_SET_IN_SEL( 94) ++ //GPIO_SET_IN_SEL( 95) ++ //GPIO_SET_IN_SEL( 96) ++ //GPIO_SET_IN_SEL( 97) ++ //GPIO_SET_IN_SEL( 98) ++ //GPIO_SET_IN_SEL( 99) ++ //GPIO_SET_IN_SEL(100) ++ //GPIO_SET_IN_SEL(101) ++ //GPIO_SET_IN_SEL(102) ++ //GPIO_SET_IN_SEL(103) ++ //GPIO_SET_IN_SEL(104) ++ //GPIO_SET_IN_SEL(105) ++ //GPIO_SET_IN_SEL(106) ++ //GPIO_SET_IN_SEL(107) ++ //GPIO_SET_IN_SEL(108) ++ //GPIO_SET_IN_SEL(109) ++ //GPIO_SET_IN_SEL(110) ++ //GPIO_SET_IN_SEL(111) ++ //GPIO_SET_IN_SEL(112) ++ //GPIO_SET_IN_SEL(113) ++ //GPIO_SET_IN_SEL(114) ++ //GPIO_SET_IN_SEL(115) ++ //GPIO_SET_IN_SEL(116) ++ //GPIO_SET_IN_SEL(117) ++ //GPIO_SET_IN_SEL(118) ++ //GPIO_SET_IN_SEL(119) ++ //GPIO_SET_IN_SEL(120) ++ //GPIO_SET_IN_SEL(121) ++ //GPIO_SET_IN_SEL(122) ++ //GPIO_SET_IN_SEL(123) ++ //GPIO_SET_IN_SEL(124) ++ //GPIO_SET_IN_SEL(125) ++ GPIO_TYPE_INPUT = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(127), //!< Input type: normal input ++ GPIO_TYPE_INPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL(126) | GPIO_SET_OUT_SEL(127), //!< Input type: normal input ++ GPIO_TYPE_INPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(127) | GPIO_SET_IN_SEL(127) | GPIO_SET_OUT_SEL(127), //!< Input type: normal input ++ ++ /* ----------------------------------- GPIO input&&output function define ----------------------------------- */ ++ GPIO_TYPE_INOUT_I2C_CLK = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 4) | GPIO_SET_IN_SEL( 4) | GPIO_SET_OUT_SEL( 4), //!< 4.Input/Output type : pad_sensor_scl ++ GPIO_TYPE_INOUT_I2C_DATA = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 5) | GPIO_SET_IN_SEL( 5) | GPIO_SET_OUT_SEL( 5), //!< 5.Input/Output type : pad_sensor_sda ++ GPIO_TYPE_INOUT_I80_D0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 8) | GPIO_SET_OUT_SEL(118), //!<118.Output type: i80_d0 ++ GPIO_TYPE_INOUT_I80_D1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 9) | GPIO_SET_OUT_SEL(117), //!<117.Output type: i80_d1 ++ GPIO_TYPE_INOUT_I80_D2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 10) | GPIO_SET_OUT_SEL(116), //!<116.Output type: i80_d2 ++ GPIO_TYPE_INOUT_I80_D3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 11) | GPIO_SET_OUT_SEL(115), //!<115.Output type: i80_d3 ++ GPIO_TYPE_INOUT_I80_D4 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 12) | GPIO_SET_OUT_SEL(114), //!<114.Output type: i80_d4 ++ GPIO_TYPE_INOUT_I80_D5 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 13) | GPIO_SET_OUT_SEL(113), //!<113.Output type: i80_d5 ++ GPIO_TYPE_INOUT_I80_D6 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 14) | GPIO_SET_OUT_SEL(112), //!<112.Output type: i80_d6 ++ GPIO_TYPE_INOUT_I80_D7 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 15) | GPIO_SET_OUT_SEL(111), //!<111.Output type: i80_d7 ++ GPIO_TYPE_INOUT_I80_D8 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 75) | GPIO_SET_IN_SEL( 16) | GPIO_SET_OUT_SEL(110), //!<110.Output type: i80_d8 ++ GPIO_TYPE_INOUT_I2C_CLK2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 36) | GPIO_SET_IN_SEL( 36) | GPIO_SET_OUT_SEL( 36), //!< 36.Input/Output type : pad_lcd_scl ++ GPIO_TYPE_INOUT_I2C_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 37) | GPIO_SET_IN_SEL( 37) | GPIO_SET_OUT_SEL( 37), //!< 37.Input/Output type : pad_lcd_sda ++ GPIO_TYPE_INOUT_SD_DATA_0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 42) | GPIO_SET_IN_SEL( 42) | GPIO_SET_OUT_SEL( 42), //!< 42.Input/Output type : pad_sd0_d0 ++ GPIO_TYPE_INOUT_SD_DATA_1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 43) | GPIO_SET_IN_SEL( 43) | GPIO_SET_OUT_SEL( 43), //!< 43.Input/Output type : pad_sd0_d1 ++ GPIO_TYPE_INOUT_SD_DATA_2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 44) | GPIO_SET_IN_SEL( 44) | GPIO_SET_OUT_SEL( 44), //!< 44.Input/Output type : pad_sd0_d2 ++ GPIO_TYPE_INOUT_SD_DATA_3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_8MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 45) | GPIO_SET_IN_SEL( 45) | GPIO_SET_OUT_SEL( 45), //!< 45.Input/Output type : pad_sd0_d3 ++ GPIO_TYPE_INOUT_SD_CMD = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 47) | GPIO_SET_IN_SEL( 47) | GPIO_SET_OUT_SEL( 47), //!< 47.Input/Output type : pad_sd0_cmd ++ GPIO_TYPE_INOUT_I2C_CLK3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 60) | GPIO_SET_IN_SEL( 60) | GPIO_SET_OUT_SEL( 60), //!< 60.Input/Output type : pad_g_sen_sck ++ GPIO_TYPE_INOUT_I2C_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 61) | GPIO_SET_IN_SEL( 61) | GPIO_SET_OUT_SEL( 61), //!< 61.Input/Output type : pad_g_sen_sda ++ GPIO_TYPE_INOUT_I2S_SCLK = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 65) | GPIO_SET_IN_SEL( 65) | GPIO_SET_OUT_SEL( 65), //!< 65.Input/Output type : pad_i2s_sclk ++ GPIO_TYPE_INOUT_I2S_WS = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 66) | GPIO_SET_IN_SEL( 66) | GPIO_SET_OUT_SEL( 66), //!< 66.Input/Output type : pad_i2s_ws ++ GPIO_TYPE_INPUT_I2S_SDATA0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA ) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 67) | GPIO_SET_IN_SEL( 67) | GPIO_SET_OUT_SEL( 67), //!< 67.Input type: pad_i2s_sdata0 ++ GPIO_TYPE_INOUT_ETH_MDIO = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_NORMAL |IOCTRL_4MA ) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 69) | GPIO_SET_IN_SEL( 87) | GPIO_SET_OUT_SEL( 93), //!< 93.Output type: enet_gmii_mdo_o ++ ++ GPIO_TYPE_UNDEFINED = 0, ++} GPIO_TYPE_E; ++/* ++GPIO_TYPE_OUTPUT_SPI1_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 2) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 2), //!< Output type: tssi_txd ++GPIO_TYPE_OUTPUT_SPI1_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 3), //!< Output type: tssi_cs0_n ++GPIO_TYPE_OUTPUT_SPI1_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 4), //!< Output type: tssi_sclk_out ++GPIO_TYPE_OUTPUT_UART2_RTS_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 5), //!< Output type: uart2_rts_n ++GPIO_TYPE_OUTPUT_UART2_DTR_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 6), //!< Output type: uart2_dtr_n ++GPIO_TYPE_OUTPUT_PWM3_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(10), //!< Output type: pwm3_out ++GPIO_TYPE_OUTPUT_PWM2_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(11), //!< Output type: pwm2_out ++GPIO_TYPE_OUTPUT_PWM1_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(12), //!< Output type: pwm1_out ++GPIO_TYPE_OUTPUT_PWM0_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(13), //!< Output type: pwm0_out ++GPIO_TYPE_OUTPUT_AOMCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(32), //!< Output type: i2s_au_clk ++GPIO_TYPE_OUTPUT_AOBCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(17) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(33), //!< Output type: i2s_clk_o ++GPIO_TYPE_OUTPUT_AOLRCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(18) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(34), //!< Output type: i2s_ws_o ++GPIO_TYPE_OUTPUT_AO_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(35), //!< Output type: i2s_so ++GPIO_TYPE_OUTPUT_SF_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(37), //!< Output type: sf_cs1_n ++GPIO_TYPE_INPUT_SPI1_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: tssi_rxd ++GPIO_TYPE_INPUT_I2S_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+23) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_clk ++GPIO_TYPE_INPUT_I2S_WS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+24) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_ws ++GPIO_TYPE_INPUT_I2S_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+25) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_si ++GPIO_TYPE_INPUT_CLK_AU = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+26) | GPIO_SET_OUT_SEL( 0), //!< Input type: clk_au ++GPIO_TYPE_INOUT_SD_DATA_4 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(12) | GPIO_SET_IN_SEL(2+18) | GPIO_SET_OUT_SEL(26), //!< Input/Output type: sd_data_out[4] ++GPIO_TYPE_INOUT_SD_DATA_5 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(13) | GPIO_SET_IN_SEL(2+19) | GPIO_SET_OUT_SEL(27), //!< Input/Output type: sd_data_out[5] ++GPIO_TYPE_INOUT_SD_DATA_6 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(14) | GPIO_SET_IN_SEL(2+20) | GPIO_SET_OUT_SEL(28), //!< Input/Output type: sd_data_out[6] ++GPIO_TYPE_INOUT_SD_DATA_7 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(15) | GPIO_SET_IN_SEL(2+21) | GPIO_SET_OUT_SEL(29), //!< Input/Output type: sd_data_out[7] ++*/ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++typedef union { /* PLL_IOCTRL_GPIO */ ++ u32 all; ++ struct { ++ u32 io1 : 6; ++ u32 : 2; ++ u32 io2 : 6; ++ u32 : 2; ++ u32 io0 : 6; ++ u32 : 2; ++ u32 io3 : 6; ++ u32 : 2; ++ } bitc; ++} GH_PLL_IOCTRL_GPIO_S; ++ ++typedef union { /* GPIO_OUTPUT_CFG */ ++ u32 all; ++ struct { ++ u32 out_sel : 7; ++ u32 oen_sel : 7; ++ u32 out_invert : 1; ++ u32 oen_invert : 1; ++ u32 : 16; ++ } bitc; ++} GH_GPIO_OUTPUT_CFG_S; ++ ++typedef union { /* GPIO_INPUT_CFG */ ++ u32 all; ++ struct { ++ u32 in_sel : 7; ++ u32 : 25; ++ } bitc; ++} GH_GPIO_INPUT_CFG_S; ++ ++typedef union { /* GPIO_INT_EN */ ++ u32 all; ++ struct { ++ u32 int_en : 1; ++ u32 : 31; ++ } bitc; ++} GH_GPIO_INT_EN_S; ++ ++typedef struct gpio_cfg ++{ ++ u32 gpio_count; ++ GPIO_XREF_S gpio_chip[128]; ++ u32 extphy_gpio_count; ++ GPIO_XREF_S ext_phy_gpio[16]; ++ u32 intphy_gpio_count; ++ GPIO_XREF_S int_phy_gpio[16]; ++ ++ u32 ir_led_ctl; ++ u32 ir_cut1; ++ u32 ir_cut2; ++ ++ u32 sensor_reset; ++ ++ u32 phy_reset; ++ u32 phy_speed_led; ++ ++ u32 spi0_en0; ++ u32 spi1_en0; ++ ++ u32 pwm0; ++ u32 pwm1; ++ u32 pwm2; ++ u32 pwm3; ++ ++ u32 usb_host; ++ ++ u32 sd_detect; ++ u32 sd_power; ++ ++ //board info ++ u32 soc_type; ++ s8 board_type[32]; ++ u32 board_version; ++ u32 reserve1; ++ ++ //extra device info ++ u32 ext_phy_clk; ++ u32 reserve2; ++ ++ // Add by Steven Yu:for pmu ++ u32 pmu_ctl; ++ ++}gpio_cfg_t; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++extern gpio_cfg_t gk_all_gpio_cfg; ++extern u8 cmdline_phytype; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++#endif /* _GK_GPIO_V1_10_H_ */ ++ +diff --git a/arch/arm/plat-goke/include/plat/gk_gpio_v1_20.h b/arch/arm/plat-goke/include/plat/gk_gpio_v1_20.h +new file mode 100644 +index 00000000..ed8ab340 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/gk_gpio_v1_20.h +@@ -0,0 +1,404 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/plat-goke/include/plat/gk_gpio_v1_00.h ++** ++** \version $Id: gk_gpio_v1_00.h 9208 2016-07-21 12:51:42Z yulindeng $ ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2016 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef _GK_GPIO_V1_20_H_ ++#define _GK_GPIO_V1_20_H_ ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Defines and Macros ++//***************************************************************************** ++//***************************************************************************** ++/************************/ ++/* GPIO pins definition */ ++/************************/ ++#define GPIO_SET_OUT_SEL(n) ((n)&0x7F) ++#define GPIO_SET_IN_SEL(n) (((n)&0x3F)<<8) ++#define GPIO_SET_OEN_SEL(n) (((n)&0x3F)<<16) ++#define GPIO_SET_OUT_INVERT(n) (((n)&0x1)<<22) ++#define GPIO_SET_OEN_INVERT(n) (((n)&0x1)<<23) ++#define GPIO_SET_IOCTRL(n) (((n)&0x3F)<<24) ++#define GPIO_SET_FUNC(n) (((n)&0x3)<<30) ++ ++#define GPIO_GET_OUT_SEL(n) (((n)&0x0000007F)) ++#define GPIO_GET_IN_SEL(n) (((n)&0x00003F00)>>8) ++#define GPIO_GET_OEN_SEL(n) (((n)&0x003F0000)>>16) ++#define GPIO_GET_OUT_INVERT(n) (((n)&0x00400000)>>22) ++#define GPIO_GET_OEN_INVERT(n) (((n)&0x00800000)>>23) ++#define GPIO_GET_IOCTRL(n) (((n)&0x3F000000)>>24) ++#define GPIO_GET_FUNC(n) (((n)&0xC0000000)>>30) ++ ++#define IOCTRL_NORMAL 0x00 //!< Hi-z ++#define IOCTRL_PULL_UP 0x10 //!< PULL_UP ++#define IOCTRL_PULL_DOWN 0x20 //!< PULL_DOWN ++#define IOCTRL_REPEAT 0x30 //!< REPEAT ++ ++#define IOCTRL_2MA 0x00 //!< 2mA ++#define IOCTRL_4MA 0x01 //!< 4mA ++#define IOCTRL_8MA 0x02 //!< 8mA ++#define IOCTRL_12MA 0x03 //!< 12mA ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Enumerated types ++//***************************************************************************** ++//***************************************************************************** ++typedef enum ++{ ++ /* ----------------------------------- GPIO output function define ----------------------------------- */ ++ GPIO_TYPE_OUTPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Output type: value = 0 ++ GPIO_TYPE_OUTPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 1), //!< Output type: value = 1 ++ GPIO_TYPE_OUTPUT_SPI1_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 2) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 2), //!< Output type: tssi_txd ++ GPIO_TYPE_OUTPUT_SPI1_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 3), //!< Output type: tssi_cs0_n ++ GPIO_TYPE_OUTPUT_SPI1_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 4), //!< Output type: tssi_sclk_out ++ GPIO_TYPE_OUTPUT_UART2_RTS_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 5), //!< Output type: uart2_rts_n ++ GPIO_TYPE_OUTPUT_UART2_DTR_N = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 6), //!< Output type: uart2_dtr_n ++ GPIO_TYPE_OUTPUT_UART2_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 7), //!< Output type: uart2_tx ++ GPIO_TYPE_OUTPUT_UART1_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 8), //!< Output type: uart1_tx ++ GPIO_TYPE_OUTPUT_UART0_TX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 9), //!< Output type: uart0_tx ++ GPIO_TYPE_OUTPUT_PWM3_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(10), //!< Output type: pwm3_out ++ GPIO_TYPE_OUTPUT_PWM2_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(11), //!< Output type: pwm2_out ++ GPIO_TYPE_OUTPUT_PWM1_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(12), //!< Output type: pwm1_out ++ GPIO_TYPE_OUTPUT_PWM0_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(13), //!< Output type: pwm0_out ++ GPIO_TYPE_OUTPUT_SPI0_SO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 7) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(14), //!< Output type: ssi_txd ++ GPIO_TYPE_OUTPUT_SPI0_CS7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(15), //!< Output type: ssi_cs7_n ++ GPIO_TYPE_OUTPUT_SPI0_CS6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(16), //!< Output type: ssi_cs6_n ++ GPIO_TYPE_OUTPUT_SPI0_CS5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(17), //!< Output type: ssi_cs5_n ++ GPIO_TYPE_OUTPUT_SPI0_CS4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(18), //!< Output type: ssi_cs4_n ++ GPIO_TYPE_OUTPUT_SPI0_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(19), //!< Output type: ssi_cs1_n ++ GPIO_TYPE_OUTPUT_SPI0_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(20), //!< Output type: ssi_cs0_n ++ GPIO_TYPE_OUTPUT_SPI0_SCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(21), //!< Output type: ssi_sclk_out ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL( 8) GPIO_SET_OUT_SEL(22) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL( 9) GPIO_SET_OUT_SEL(23) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(10) GPIO_SET_OUT_SEL(24) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(11) GPIO_SET_OUT_SEL(25) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(12) GPIO_SET_OUT_SEL(26) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(13) GPIO_SET_OUT_SEL(27) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(14) GPIO_SET_OUT_SEL(28) ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_OEN_SEL(15) GPIO_SET_OUT_SEL(29) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_OEN_SEL(16) GPIO_SET_OUT_SEL(30) ++ GPIO_TYPE_OUTPUT_SDIO_CLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(31), //!< Output type: sd_clk_sdcard ++ GPIO_TYPE_OUTPUT_AOMCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(32), //!< Output type: i2s_au_clk ++ GPIO_TYPE_OUTPUT_AOBCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(17) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(33), //!< Output type: i2s_clk_o ++ GPIO_TYPE_OUTPUT_AOLRCLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(18) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(34), //!< Output type: i2s_ws_o ++ GPIO_TYPE_OUTPUT_AO_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(35), //!< Output type: i2s_so ++ GPIO_TYPE_OUTPUT_SF_CS0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(36), //!< Output type: sf_cs0_n ++ GPIO_TYPE_OUTPUT_SF_CS1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(37), //!< Output type: sf_cs1_n ++ GPIO_TYPE_OUTPUT_EPHY_LED_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(38), //!< Output type: ephy_led[0] hcd ok ++ GPIO_TYPE_OUTPUT_EPHY_LED_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(39), //!< Output type: ephy_led[1] duplex ++ GPIO_TYPE_OUTPUT_EPHY_LED_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(40), //!< Output type: ephy_led[2] 10M CRS out ++ GPIO_TYPE_OUTPUT_EPHY_LED_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(41), //!< Output type: ephy_led[3] 100M CRS out ++ GPIO_TYPE_OUTPUT_EPHY_LED_4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(42), //!< Output type: ephy_led[4] clo gs ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(43), //!< Output type: enet_phy_txd[0] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(44), //!< Output type: enet_phy_txd[1] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(45), //!< Output type: enet_phy_txd[2] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(46), //!< Output type: enet_phy_txd[3] ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXER = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(47), //!< Output type: enet_phy_txer ++ GPIO_TYPE_OUTPUT_ENET_PHY_TXEN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(48), //!< Output type: enet_phy_txen ++ // GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_OUT_SEL(49) ++ GPIO_TYPE_OUTPUT_ENET_GMII_MDC_O = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(50), //!< Output type: enet_gmii_mdc_o ++ //GPIO_TYPE_INOUT_SD2_DATA_0 GPIO_SET_OEN_SEL(20) GPIO_SET_OUT_SEL(51) ++ //GPIO_TYPE_INOUT_SD2_DATA_1 GPIO_SET_OEN_SEL(21) GPIO_SET_OUT_SEL(52) ++ //GPIO_TYPE_INOUT_SD2_DATA_2 GPIO_SET_OEN_SEL(22) GPIO_SET_OUT_SEL(53) ++ //GPIO_TYPE_INOUT_SD2_DATA_3 GPIO_SET_OEN_SEL(23) GPIO_SET_OUT_SEL(54) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_OEN_SEL(24) GPIO_SET_OUT_SEL(55) ++ GPIO_TYPE_OUTPUT_SDIO2_CLK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(56), //!< Output type: sd2_clk_sdcard ++ GPIO_TYPE_OUTPUT_JTAGE_TDO = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(57), //!< Output type: jtag_tdout ++ GPIO_TYPE_OUTPUT_VD_VSYNC = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(58), //!< Output type: lcd_vsync ++ GPIO_TYPE_OUTPUT_VD_HSYNC = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(59), //!< Output type: lcd_hsync ++ GPIO_TYPE_OUTPUT_VD_CLOCK = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(60), //!< Output type: lcd_dclk ++ GPIO_TYPE_OUTPUT_VD_HVLD = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(61), //!< Output type: lcd_hvld ++ GPIO_TYPE_OUTPUT_VD_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(62), //!< Output type: lcd_data0 ++ GPIO_TYPE_OUTPUT_VD_DATA1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(63), //!< Output type: lcd_data1 ++ GPIO_TYPE_OUTPUT_VD_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(64), //!< Output type: lcd_data2 ++ GPIO_TYPE_OUTPUT_VD_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(65), //!< Output type: lcd_data3 ++ GPIO_TYPE_OUTPUT_VD_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(66), //!< Output type: lcd_data4 ++ GPIO_TYPE_OUTPUT_VD_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(67), //!< Output type: lcd_data5 ++ GPIO_TYPE_OUTPUT_VD_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(68), //!< Output type: lcd_data6 ++ GPIO_TYPE_OUTPUT_VD_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(69), //!< Output type: lcd_data7 ++ GPIO_TYPE_OUTPUT_VD_DATA8 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(70), //!< Output type: lcd_data8 ++ GPIO_TYPE_OUTPUT_VD_DATA9 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(71), //!< Output type: lcd_data9 ++ GPIO_TYPE_OUTPUT_VD_DATA10 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(72), //!< Output type: lcd_data10 ++ GPIO_TYPE_OUTPUT_VD_DATA11 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(73), //!< Output type: lcd_data11 ++ GPIO_TYPE_OUTPUT_VD_DATA12 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(74), //!< Output type: lcd_data12 ++ GPIO_TYPE_OUTPUT_VD_DATA13 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(75), //!< Output type: lcd_data13 ++ GPIO_TYPE_OUTPUT_VD_DATA14 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(76), //!< Output type: lcd_data14 ++ GPIO_TYPE_OUTPUT_VD_DATA15 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(77), //!< Output type: lcd_data15 ++ GPIO_TYPE_OUTPUT_VD_DATA16 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(78), //!< Output type: lcd_data16 ++ GPIO_TYPE_OUTPUT_VD_DATA17 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(79), //!< Output type: lcd_data17 ++ GPIO_TYPE_OUTPUT_VD_DATA18 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(80), //!< Output type: lcd_data18 ++ GPIO_TYPE_OUTPUT_VD_DATA19 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(81), //!< Output type: lcd_data19 ++ GPIO_TYPE_OUTPUT_VD_DATA20 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(82), //!< Output type: lcd_data20 ++ GPIO_TYPE_OUTPUT_VD_DATA21 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(83), //!< Output type: lcd_data21 ++ GPIO_TYPE_OUTPUT_VD_DATA22 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(84), //!< Output type: lcd_data22 ++ GPIO_TYPE_OUTPUT_VD_DATA23 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(85), //!< Output type: lcd_data23 ++ GPIO_TYPE_OUTPUT_RCT_CLK_OUT2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(86), //!< Output type: rct_clk_out2 ++ GPIO_TYPE_OUTPUT_RCT_CLK_OUT1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(87), //!< Output type: rct_clk_out1 ++ GPIO_TYPE_OUTPUT_I80_LCD_RST = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(88), //!< Output type: i80_lcd_rst ++ GPIO_TYPE_OUTPUT_I80_RDN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(89), //!< Output type: i80_rdn ++ GPIO_TYPE_OUTPUT_I80_WRN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(90), //!< Output type: i80_wrn ++ GPIO_TYPE_OUTPUT_I80_DCX = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(91), //!< Output type: i80_dcx ++ GPIO_TYPE_OUTPUT_I80_CSN = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(92), //!< Output type: i80_csn ++ GPIO_TYPE_OUTPUT_I80_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(93), //!< Output type: i80_data_tx0 ++ GPIO_TYPE_OUTPUT_I80_DATA1 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(94), //!< Output type: i80_data_tx1 ++ GPIO_TYPE_OUTPUT_I80_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(95), //!< Output type: i80_data_tx2 ++ GPIO_TYPE_OUTPUT_I80_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(96), //!< Output type: i80_data_tx3 ++ GPIO_TYPE_OUTPUT_I80_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(97), //!< Output type: i80_data_tx4 ++ GPIO_TYPE_OUTPUT_I80_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(98), //!< Output type: i80_data_tx5 ++ GPIO_TYPE_OUTPUT_I80_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(99), //!< Output type: i80_data_tx6 ++ GPIO_TYPE_OUTPUT_I80_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(100), //!< Output type: i80_data_tx7 ++ GPIO_TYPE_OUTPUT_I80_DATA8 = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(101), //!< Output type: i80_data_tx8 ++ GPIO_TYPE_OUTPUT_PWM7_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(102), //!< Output type: pwm7_out ++ GPIO_TYPE_OUTPUT_PWM6_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(103), //!< Output type: pwm6_out ++ GPIO_TYPE_OUTPUT_PWM5_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(104), //!< Output type: pwm5_out ++ GPIO_TYPE_OUTPUT_PWM4_OUT = GPIO_SET_FUNC(GPIO_FUNC_OUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 0) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL(105), //!< Output type: pwm4_out ++ ++ /* ----------------------------------- GPIO input function define ----------------------------------- */ ++ ++ GPIO_TYPE_INPUT = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_NORMAL|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL( 1) | GPIO_SET_OUT_SEL( 0), //!< Input type: normal input ++ GPIO_TYPE_INPUT_SPI1_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 0) | GPIO_SET_OUT_SEL( 0), //!< Input type: tssi_rxd ++ //GPIO_TYPE_INOUT_I2C_DATA GPIO_SET_IN_SEL(2+ 1) ++ //GPIO_TYPE_INOUT_I2C_CLK GPIO_SET_IN_SEL(2+ 2) ++ //GPIO_TYPE_INOUT_I2C_DATA2 GPIO_SET_IN_SEL(2+ 3) ++ //GPIO_TYPE_INOUT_I2C_CLK2 GPIO_SET_IN_SEL(2+ 4) ++ GPIO_TYPE_INPUT_UART2_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 5) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart2_rx ++ GPIO_TYPE_INPUT_UART1_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 6) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart1_rx ++ GPIO_TYPE_INPUT_UART0_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 7) | GPIO_SET_OUT_SEL( 0), //!< Input type: uart0_rx ++ GPIO_TYPE_INPUT_TIMER1_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 8) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer1_clk ++ GPIO_TYPE_INPUT_TIMER2_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+ 9) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer2_clk ++ GPIO_TYPE_INPUT_TIMER3_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+10) | GPIO_SET_OUT_SEL( 0), //!< Input type: timer3_clk ++ GPIO_TYPE_INPUT_SPI0_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+11) | GPIO_SET_OUT_SEL( 0), //!< Input type: ssi_rxd ++ GPIO_TYPE_INPUT_SD_WP_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+12) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd_wp_n ++ GPIO_TYPE_INPUT_SD_CD_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+13) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd_cd_n ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_IN_SEL(2+14) ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_IN_SEL(2+15) ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_IN_SEL(2+16) ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_IN_SEL(2+17) ++ //GPIO_TYPE_INOUT_SD_DATA_4 GPIO_SET_IN_SEL(2+18) ++ //GPIO_TYPE_INOUT_SD_DATA_5 GPIO_SET_IN_SEL(2+19) ++ //GPIO_TYPE_INOUT_SD_DATA_6 GPIO_SET_IN_SEL(2+20) ++ //GPIO_TYPE_INOUT_SD_DATA_7 GPIO_SET_IN_SEL(2+21) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_IN_SEL(2+22) ++ GPIO_TYPE_INPUT_I2S_CLK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+23) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_clk ++ GPIO_TYPE_INPUT_I2S_WS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+24) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_ws ++ GPIO_TYPE_INPUT_I2S_SI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+25) | GPIO_SET_OUT_SEL( 0), //!< Input type: i2s_si ++ GPIO_TYPE_INPUT_CLK_AU = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+26) | GPIO_SET_OUT_SEL( 0), //!< Input type: clk_au ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+27) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[0] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+28) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[1] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_2 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+29) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[2] ++ GPIO_TYPE_INPUT_ENET_PHY_RXD_3 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+30) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxd[3] ++ GPIO_TYPE_INPUT_ENET_PHY_COL = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+31) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_col ++ GPIO_TYPE_INPUT_ENET_PHY_CRS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+32) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_crs ++ GPIO_TYPE_INPUT_ENET_PHY_RXER = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+33) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxer ++ GPIO_TYPE_INPUT_ENET_PHY_RXDV = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+34) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_phy_rxdv ++ // GPIO_TYPE_INOUT_ETH_MDIO GPIO_SET_IN_SEL(2+35) ++ GPIO_TYPE_INPUT_ENET_CLK_RX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+36) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_clk_rx ++ GPIO_TYPE_INPUT_ENET_CLK_TX = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+37) | GPIO_SET_OUT_SEL( 0), //!< Input type: enet_clk_tx ++ GPIO_TYPE_INPUT_SD2_WP_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+38) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd2_wp_n ++ GPIO_TYPE_INPUT_SD2_CD_N = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+39) | GPIO_SET_OUT_SEL( 0), //!< Input type: sd2_cd_n ++ //GPIO_TYPE_INOUT_SD_DATA_0 GPIO_SET_IN_SEL(2+40) ++ //GPIO_TYPE_INOUT_SD_DATA_1 GPIO_SET_IN_SEL(2+41) ++ //GPIO_TYPE_INOUT_SD_DATA_2 GPIO_SET_IN_SEL(2+42) ++ //GPIO_TYPE_INOUT_SD_DATA_3 GPIO_SET_IN_SEL(2+43) ++ //GPIO_TYPE_INOUT_SDIO_CMD GPIO_SET_IN_SEL(2+44) ++ GPIO_TYPE_INPUT_I80_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+45) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx0 ++ GPIO_TYPE_INPUT_I80_DATA1 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+46) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx1 ++ GPIO_TYPE_INPUT_I80_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+47) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx2 ++ GPIO_TYPE_INPUT_I80_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+48) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx3 ++ GPIO_TYPE_INPUT_I80_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+49) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx4 ++ GPIO_TYPE_INPUT_I80_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+50) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx5 ++ GPIO_TYPE_INPUT_I80_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+51) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx6 ++ GPIO_TYPE_INPUT_I80_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+52) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx7 ++ GPIO_TYPE_INPUT_I80_DATA8 = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+53) | GPIO_SET_OUT_SEL( 0), //!< Input type: i80_data_rx8 ++ GPIO_TYPE_INPUT_JTAG_TRSTN = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+56) | GPIO_SET_OUT_SEL( 0), //!< Input type: jtag_trstn ++ GPIO_TYPE_INPUT_JTAG_TCK = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+57) | GPIO_SET_OUT_SEL( 0), //!< Input type: jtag_tck ++ GPIO_TYPE_INPUT_JTAG_TMS = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+58) | GPIO_SET_OUT_SEL( 0), //!< Input type: jtag_tms ++ GPIO_TYPE_INPUT_JTAG_TDI = GPIO_SET_FUNC(GPIO_FUNC_IN) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 1) | GPIO_SET_IN_SEL(2+59) | GPIO_SET_OUT_SEL( 0), //!< Input type: jtag_tdi ++ ++ /* ----------------------------------- GPIO input&&output function define ----------------------------------- */ ++ GPIO_TYPE_INOUT_I2C_DATA = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 3) | GPIO_SET_IN_SEL(2+ 1) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_sda ++ GPIO_TYPE_INOUT_I2C_CLK = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 4) | GPIO_SET_IN_SEL(2+ 2) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_scl ++ GPIO_TYPE_INOUT_I2C_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 5) | GPIO_SET_IN_SEL(2+ 3) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_sda2 ++ GPIO_TYPE_INOUT_I2C_CLK2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(0) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 6) | GPIO_SET_IN_SEL(2+ 4) | GPIO_SET_OUT_SEL( 0), //!< Input/Output type: i2c_scl2 ++ ++ GPIO_TYPE_INOUT_ETH_MDIO = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(19) | GPIO_SET_IN_SEL(2+35) | GPIO_SET_OUT_SEL(49), //!< Input/Output type: enet_gmii_mdi/enet_gmii_mod_o ++ ++ GPIO_TYPE_INOUT_SD_DATA_0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 8) | GPIO_SET_IN_SEL(2+14) | GPIO_SET_OUT_SEL(22), //!< Input/Output type: sd_data_out[0] ++ GPIO_TYPE_INOUT_SD_DATA_1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL( 9) | GPIO_SET_IN_SEL(2+15) | GPIO_SET_OUT_SEL(23), //!< Input/Output type: sd_data_out[1] ++ GPIO_TYPE_INOUT_SD_DATA_2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(10) | GPIO_SET_IN_SEL(2+16) | GPIO_SET_OUT_SEL(24), //!< Input/Output type: sd_data_out[2] ++ GPIO_TYPE_INOUT_SD_DATA_3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(11) | GPIO_SET_IN_SEL(2+17) | GPIO_SET_OUT_SEL(25), //!< Input/Output type: sd_data_out[3] ++ GPIO_TYPE_INOUT_SD_DATA_4 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(12) | GPIO_SET_IN_SEL(2+18) | GPIO_SET_OUT_SEL(26), //!< Input/Output type: sd_data_out[4] ++ GPIO_TYPE_INOUT_SD_DATA_5 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(13) | GPIO_SET_IN_SEL(2+19) | GPIO_SET_OUT_SEL(27), //!< Input/Output type: sd_data_out[5] ++ GPIO_TYPE_INOUT_SD_DATA_6 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(14) | GPIO_SET_IN_SEL(2+20) | GPIO_SET_OUT_SEL(28), //!< Input/Output type: sd_data_out[6] ++ GPIO_TYPE_INOUT_SD_DATA_7 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(15) | GPIO_SET_IN_SEL(2+21) | GPIO_SET_OUT_SEL(29), //!< Input/Output type: sd_data_out[7] ++ GPIO_TYPE_INOUT_SD_CMD = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(16) | GPIO_SET_IN_SEL(2+22) | GPIO_SET_OUT_SEL(30), //!< Input/Output : sd_cmd ++ ++ GPIO_TYPE_INOUT_SD2_DATA_0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(20) | GPIO_SET_IN_SEL(2+40) | GPIO_SET_OUT_SEL(51), //!< Input/Output type: sd2_data_out[0] ++ GPIO_TYPE_INOUT_SD2_DATA_1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(21) | GPIO_SET_IN_SEL(2+41) | GPIO_SET_OUT_SEL(52), //!< Input/Output type: sd2_data_out[1] ++ GPIO_TYPE_INOUT_SD2_DATA_2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(22) | GPIO_SET_IN_SEL(2+42) | GPIO_SET_OUT_SEL(53), //!< Input/Output type: sd2_data_out[2] ++ GPIO_TYPE_INOUT_SD2_DATA_3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(23) | GPIO_SET_IN_SEL(2+43) | GPIO_SET_OUT_SEL(54), //!< Input/Output type: sd2_data_out[3] ++ GPIO_TYPE_INOUT_SD2_CMD = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_UP|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(24) | GPIO_SET_IN_SEL(2+44) | GPIO_SET_OUT_SEL(55), //!< Input/Output : sd2_cmd ++ ++ GPIO_TYPE_INOUT_I80_DATA0 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+45) | GPIO_SET_OUT_SEL(93), //!< Input/Output type: i80_data_rx0 ++ GPIO_TYPE_INOUT_I80_DATA1 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+46) | GPIO_SET_OUT_SEL(94), //!< Input/Output type: i80_data_rx1 ++ GPIO_TYPE_INOUT_I80_DATA2 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+47) | GPIO_SET_OUT_SEL(95), //!< Input/Output type: i80_data_rx2 ++ GPIO_TYPE_INOUT_I80_DATA3 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+48) | GPIO_SET_OUT_SEL(96), //!< Input/Output type: i80_data_rx3 ++ GPIO_TYPE_INOUT_I80_DATA4 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+49) | GPIO_SET_OUT_SEL(97), //!< Input/Output type: i80_data_rx4 ++ GPIO_TYPE_INOUT_I80_DATA5 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+50) | GPIO_SET_OUT_SEL(98), //!< Input/Output type: i80_data_rx5 ++ GPIO_TYPE_INOUT_I80_DATA6 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+51) | GPIO_SET_OUT_SEL(99), //!< Input/Output type: i80_data_rx6 ++ GPIO_TYPE_INOUT_I80_DATA7 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+52) | GPIO_SET_OUT_SEL(100), //!< Input/Output type: i80_data_rx7 ++ GPIO_TYPE_INOUT_I80_DATA8 = GPIO_SET_FUNC(GPIO_FUNC_INOUT) | GPIO_SET_IOCTRL(IOCTRL_PULL_DOWN|IOCTRL_2MA) | GPIO_SET_OEN_INVERT(1) | GPIO_SET_OUT_INVERT(0) | GPIO_SET_OEN_SEL(25) | GPIO_SET_IN_SEL(2+53) | GPIO_SET_OUT_SEL(101), //!< Input/Output type: i80_data_rx8 ++ ++ GPIO_TYPE_UNDEFINED = 0, ++} GPIO_TYPE_E; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Data Structures ++//***************************************************************************** ++//***************************************************************************** ++typedef union { /* PLL_IOCTRL_GPIO */ ++ u32 all; ++ struct { ++ u32 io0 : 6; ++ u32 : 2; ++ u32 io1 : 6; ++ u32 : 2; ++ u32 io2 : 6; ++ u32 : 2; ++ u32 io3 : 6; ++ u32 : 2; ++ } bitc; ++} GH_PLL_IOCTRL_GPIO_S; ++ ++typedef union { /* GPIO_OUTPUT_CFG */ ++ u32 all; ++ struct { ++ u32 out_sel : 7; ++ u32 : 1; ++ u32 oen_sel : 6; ++ u32 out_invert : 1; ++ u32 oen_invert : 1; ++ u32 : 16; ++ } bitc; ++} GH_GPIO_OUTPUT_CFG_S; ++ ++typedef union { /* GPIO_INPUT_CFG */ ++ u32 all; ++ struct { ++ u32 in_sel : 6; ++ u32 : 26; ++ } bitc; ++} GH_GPIO_INPUT_CFG_S; ++ ++typedef union { /* GPIO_INT_EN */ ++ u32 all; ++ struct { ++ u32 int_en : 1; ++ u32 : 31; ++ } bitc; ++} GH_GPIO_INT_EN_S; ++ ++typedef struct gpio_cfg ++{ ++ u32 gpio_count; ++ GPIO_XREF_S gpio_chip[64]; ++ u32 extphy_gpio_count; ++ GPIO_XREF_S ext_phy_gpio[16]; ++ u32 intphy_gpio_count; ++ GPIO_XREF_S int_phy_gpio[16]; ++ ++ u32 ir_led_ctl; ++ u32 ir_cut1; ++ u32 ir_cut2; ++ ++ u32 sensor_reset; ++ ++ u32 phy_reset; ++ u32 phy_speed_led; ++ ++ u32 spi0_en0; ++ u32 spi1_en0; ++ ++ u32 pwm0; ++ u32 pwm1; ++ u32 pwm2; ++ u32 pwm3; ++ ++ u32 usb_host; ++ ++ u32 sd_detect; ++ u32 sd_power; ++ u32 sd1_detect; ++ u32 sd1_power; ++ ++ //board info ++ u32 soc_type; ++ s8 board_type[32]; ++ u32 board_version; ++ u32 reserve1; ++ ++ //extra device info ++ u32 ext_phy_clk; ++ u32 reserve2; ++ ++ // Add by Steven Yu:for pmu ++ u32 pmu_ctl; ++ ++}gpio_cfg_t; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** Global Data ++//***************************************************************************** ++//***************************************************************************** ++extern gpio_cfg_t gk_all_gpio_cfg; ++extern u8 cmdline_phytype; ++ ++ ++ ++//***************************************************************************** ++//***************************************************************************** ++//** API Functions ++//***************************************************************************** ++//***************************************************************************** ++ ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++#endif /* _GK_GPIO_V1_20_H_ */ ++ +diff --git a/arch/arm/plat-goke/include/plat/highres_timer.h b/arch/arm/plat-goke/include/plat/highres_timer.h +new file mode 100644 +index 00000000..aecf5e7d +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/highres_timer.h +@@ -0,0 +1,25 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/plat/highres_timer.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++#ifndef __PLAT_HIGHRES_TIMER_H ++#define __PLAT_HIGHRES_TIMER_H ++ ++extern void highres_timer_init(struct hrtimer *timer, clockid_t clock_id, enum hrtimer_mode mode); ++extern int highres_timer_start(struct hrtimer *timer, ktime_t tim, const enum hrtimer_mode mode); ++extern int highres_timer_cancel(struct hrtimer *timer); ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/input.h b/arch/arm/plat-goke/include/plat/input.h +new file mode 100644 +index 00000000..02b8be2e +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/input.h +@@ -0,0 +1,265 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/input.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_INPUT_H__ ++#define __PLAT_INPUT_H__ ++ ++#define MCU_RTC_BASE (GK_VA_PMU_RTC + 0x0000) //0xf2080000 ++#define MCU_IRR_BASE (GK_VA_PMU_RTC + 0x2000) ++#define MCU_FPC_BASE (GK_VA_PMU_RTC + 0x4000) ++#define MCU_GPIO_BASE (GK_VA_PMU_RTC + 0x6000) ++#define MCU_SYS_BASE (GK_VA_PMU_RTC + 0xA000) ++#define MCU_IRQ_BASE (GK_VA_PMU_RTC + 0xDC00) ++ ++/********************************/ ++/* PGPIO Register List */ ++/********************************/ ++#define PMU_GPIO_0_PWRUP 5 ++#define PMU_GPIO_1_IR 7 ++#define PMU_GPIO_2 2 ++#define PMU_GPIO_3 3 ++#define PMU_GPIO_4 4 ++ ++#define PMU_GPIO_0_DATA (MCU_GPIO_BASE + (0x0004 << PMU_GPIO_0_PWRUP)) ++#define PMU_GPIO_1_DATA (MCU_GPIO_BASE + (0x0004 << PMU_GPIO_1_IR)) ++#define PMU_GPIO_2_DATA (MCU_GPIO_BASE + (0x0004 << PMU_GPIO_2)) ++#define PMU_GPIO_3_DATA (MCU_GPIO_BASE + (0x0004 << PMU_GPIO_3)) ++#define PMU_GPIO_4_DATA (MCU_GPIO_BASE + (0x0004 << PMU_GPIO_4)) ++#define PMU_GPIO_DIR (MCU_GPIO_BASE + 0x0400) ++#define PMU_GPIO_IS (MCU_GPIO_BASE + 0x0404) ++#define PMU_GPIO_IBE (MCU_GPIO_BASE + 0x0408) ++#define PMU_GPIO_IEV (MCU_GPIO_BASE + 0x040C) ++#define PMU_GPIO_IE (MCU_GPIO_BASE + 0x0410) ++#define PMU_GPIO_RIS (MCU_GPIO_BASE + 0x0414) ++#define PMU_GPIO_MIS (MCU_GPIO_BASE + 0x0418) ++#define PMU_GPIO_IC (MCU_GPIO_BASE + 0x041C) ++#define PMU_GPIO_AFSEL (MCU_GPIO_BASE + 0x0420) ++ ++#define PMU_AUTOMOTIVE_KEY 0x10 // power on/off by key ++#define PMU_AUTOMOTIVE_ACC 0x11 // power on/off by acc ++#define PMU_AUTOMOTIVE_KEY_ACC 0x12 // power on/off by key & check the acc status ++#define PMU_POWER_OFF_CPU 0x20 // load 51 code then power off, power on by IR ++#define PMU_ALWAYS_RUNNING_POWEROFF 0x30 // load 51 code then power off, power on by IR ++#define PMU_ALWAYS_RUNNING 0x31 // load 51 code but do not power off, rtc always work ++typedef enum ++{ ++ NEG_EDGE = 0, ++ POS_EDGE, ++ ALL_EDGE, ++}GPIO_INT_EDGE_MODE_E; ++ ++typedef enum ++{ ++ EDGE_TRIGGER = 0, ++ LEVEL_TRIGGER, ++}GPIO_INT_TRIGGER_MODE_E; ++ ++typedef enum ++{ ++ LOW_LEVEL = 0, ++ HIGH_LEVEL, ++}GPIO_INT_LEVEL_MODE_E; ++ ++/********************************/ ++/* IR Register List */ ++/********************************/ ++#define REG_IRR_PROG (MCU_IRR_BASE + 0x00) /* write */ //0xf0082000 ++#define IRR_RESTART_IRR (1<<3) ++#define IRR_FALLING_DETECT (1<<2) ++#define IRR_RISING_DETECT (1<<1) ++#define IRR_TRANS_0XFF (1<<0) ++#define REG_IRR_PRESCALER_L (MCU_IRR_BASE + 0x04) /* write */ ++#define REG_IRR_PRESCALER_H (MCU_IRR_BASE + 0x08) /* write */ ++#define REG_IRR_IRR_READ (MCU_IRR_BASE + 0x0C) /* read/clear */ ++#define IRR_READ_VALID (1<<7) ++#define REG_IRR_IRT_READ (MCU_IRR_BASE + 0x10) /* read/clear */ ++#define REG_IRR_IRQMASK_L (MCU_IRR_BASE + 0x14) /* write */ ++#define IRR_RX_DATA_L_MSK (0x3<<0) ++#define REG_IRR_IRQMASK_H (MCU_IRR_BASE + 0x18) /* write */ ++#define IRR_RX_DATA_H_MSK (0x3f<<0) ++#define IRR_RX_DATA_H_SHIFT (2) ++ ++/********************************/ ++/* SYS/IRQ Register List */ ++/********************************/ ++#define REG_PMU_SYS_REG_CFG1 (MCU_SYS_BASE + 0x0004) /* read/write */ ++#define REG_PMU_IRQ_EN (MCU_IRQ_BASE + 0x0000) ++#define IRQ_EN_RTC (1<<0) ++#define IRQ_EN_IRR (1<<1) ++#define IRQ_EN_FPC (1<<2) ++#define IRQ_EN_GPIO (1<<3) ++#define IRQ_EN_CEC (1<<4) ++#define IRQ_EN_ADC (1<<5) ++#define IRQ_EN_IRT (1<<6) ++#define REG_PMU_IRQ_CLR_RTC (MCU_IRQ_BASE + 0x0020) /* read/write */ ++#define REG_PMU_IRQ_CLR_IRR (MCU_IRQ_BASE + 0x0024) /* read/write */ ++#define REG_PMU_IRQ_CLR_FPC (MCU_IRQ_BASE + 0x0028) /* read/write */ ++#define REG_PMU_IRQ_CLR_GPIO (MCU_IRQ_BASE + 0x002C) /* read/write */ ++#define REG_PMU_IRQ_CLR_CEC (MCU_IRQ_BASE + 0x0030) /* read/write */ ++#define REG_PMU_IRQ_CLR_ADC (MCU_IRQ_BASE + 0x0034) /* read/write */ ++#define REG_PMU_IRQ_CLR_IRT (MCU_IRQ_BASE + 0x0038) /* read/write */ ++#define REG_PMU_IRQ_STATUS (MCU_IRQ_BASE + 0x0040) /* read/write */ ++ ++/* ==========================================================================*/ ++#define GKINPUT_TABLE_SIZE (256) ++ ++#define GKINPUT_SOURCE_MASK (0x0F) ++#define GKINPUT_SOURCE_IR (0x01) ++#define GKINPUT_SOURCE_ADC (0x02) ++#define GKINPUT_SOURCE_GPIO (0x04) ++#define GKINPUT_SOURCE_VI (0x08) ++ ++#define GKINPUT_TYPE_MASK (0xF0) ++#define GKINPUT_TYPE_KEY (0x10) ++#define GKINPUT_TYPE_REL (0x20) ++#define GKINPUT_TYPE_ABS (0x40) ++#define GKINPUT_TYPE_SW (0x80) ++ ++#define GKINPUT_IR_KEY (GKINPUT_SOURCE_IR | GKINPUT_TYPE_KEY) ++#define GKINPUT_IR_REL (GKINPUT_SOURCE_IR | GKINPUT_TYPE_REL) ++#define GKINPUT_IR_ABS (GKINPUT_SOURCE_IR | GKINPUT_TYPE_ABS) ++#define GKINPUT_IR_SW (GKINPUT_SOURCE_IR | GKINPUT_TYPE_SW) ++#define GKINPUT_ADC_KEY (GKINPUT_SOURCE_ADC | GKINPUT_TYPE_KEY) ++#define GKINPUT_ADC_REL (GKINPUT_SOURCE_ADC | GKINPUT_TYPE_REL) ++#define GKINPUT_ADC_ABS (GKINPUT_SOURCE_ADC | GKINPUT_TYPE_ABS) ++#define GKINPUT_GPIO_KEY (GKINPUT_SOURCE_GPIO | GKINPUT_TYPE_KEY) ++#define GKINPUT_GPIO_REL (GKINPUT_SOURCE_GPIO | GKINPUT_TYPE_REL) ++#define GKINPUT_GPIO_ABS (GKINPUT_SOURCE_GPIO | GKINPUT_TYPE_ABS) ++#define GKINPUT_GPIO_SW (GKINPUT_SOURCE_GPIO | GKINPUT_TYPE_SW) ++#define GKINPUT_VI_KEY (GKINPUT_SOURCE_VI | GKINPUT_TYPE_KEY) ++#define GKINPUT_VI_REL (GKINPUT_SOURCE_VI | GKINPUT_TYPE_REL) ++#define GKINPUT_VI_ABS (GKINPUT_SOURCE_VI | GKINPUT_TYPE_ABS) ++#define GKINPUT_VI_SW (GKINPUT_SOURCE_VI | GKINPUT_TYPE_SW) ++ ++#define GKINPUT_END (0xFFFFFFFF) ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++struct gk_key_table { ++ u32 type; ++ union { ++ struct { ++ u32 key_code; ++ u32 key_flag; ++ u32 raw_id; ++ } ir_key; ++ struct { ++ u32 key_code; ++ s32 rel_step; ++ u32 raw_id; ++ } ir_rel; ++ struct { ++ s32 abs_x; ++ s32 abs_y; ++ u32 raw_id; ++ } ir_abs; ++ struct { ++ u32 key_code; ++ u32 key_value; ++ u32 raw_id; ++ } ir_sw; ++ struct { ++ u32 key_code; ++ u16 irq_trig;// 0 low trigger, 1 high trigger ++ u16 chan; ++ u16 low_level; ++ u16 high_level; ++ } adc_key; ++ struct { ++ u16 key_code; ++ s16 rel_step; ++ u16 irq_trig;// 0 low trigger, 1 high trigger ++ u16 chan; ++ u16 low_level; ++ u16 high_level; ++ } adc_rel; ++ struct { ++ s16 abs_x; ++ s16 abs_y; ++ u16 irq_trig;// 0 low trigger, 1 high trigger ++ u16 chan; ++ u16 low_level; ++ u16 high_level; ++ } adc_abs; ++ struct { ++ u32 key_code; ++ u32 active_val; ++ u16 can_wakeup; ++ u8 id; ++ u8 irq_mode; ++ } gpio_key; ++ struct { ++ u32 key_code; ++ s32 rel_step; ++ u16 can_wakeup; ++ u8 id; ++ u8 irq_mode; ++ } gpio_rel; ++ struct { ++ s32 abs_x; ++ s32 abs_y; ++ u16 can_wakeup; ++ u8 id; ++ u8 irq_mode; ++ } gpio_abs; ++ struct { ++ u32 key_code; ++ u32 active_val; ++ u16 can_wakeup; ++ u8 id; ++ u8 irq_mode; ++ } gpio_sw; ++ struct { ++ u32 reserve; ++ u32 reserve0; ++ u32 reserve1; ++ } vi_key; ++ struct { ++ u32 reserve; ++ u32 reserve0; ++ u32 reserve1; ++ } vi_rel; ++ struct { ++ u32 reserve; ++ u32 reserve0; ++ u32 reserve1; ++ } vi_abs; ++ struct { ++ u32 reserve; ++ u32 reserve0; ++ u32 reserve1; ++ } vi_sw; ++ }; ++}; ++ ++/* ==========================================================================*/ ++struct gk_input_board_info { ++ struct gk_key_table *pkeymap; ++ struct input_dev *pinput_dev; ++ struct platform_device *pdev; ++ ++ int abx_max_x; ++ int abx_max_y; ++ int abx_max_pressure; ++ int abx_max_width; ++}; ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/mdma.h b/arch/arm/plat-goke/include/plat/mdma.h +new file mode 100644 +index 00000000..62b720d1 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/mdma.h +@@ -0,0 +1,82 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk7101/include/plat/mdma.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_MDMA_H__ ++#define __PLAT_MDMA_H__ ++ ++ ++/****************************************************/ ++/* Capabilities based on chip revision */ ++/****************************************************/ ++ ++ ++#define NUMBERS_MDMA_INSTANCES 4 ++ ++ ++#define MDMA_ON_AHB 1 ++ ++ ++#define MDMA_SUPPORT_ALPHA_BLEND 0 ++ ++/****************************************************/ ++/* Controller registers definitions */ ++/****************************************************/ ++ ++#if (MDMA_ON_AHB == 1) ++#define MDMA_SRC_1_BASE_OFFSET 0x00 ++#define MDMA_SRC_1_PITCH_OFFSET 0x04 ++#define MDMA_SRC_2_BASE_OFFSET 0x08 ++#define MDMA_SRC_2_PITCH_OFFSET 0x0c ++#define MDMA_DST_BASE_OFFSET 0x10 ++#define MDMA_DST_PITCH_OFFSET 0x14 ++#define MDMA_WIDTH_OFFSET 0x18 ++#define MDMA_HIGHT_OFFSET 0x1c ++#define MDMA_TRANSPARENT_OFFSET 0x20 ++#define MDMA_OPCODE_OFFSET 0x24 ++#define MDMA_PENDING_OPS_OFFSET 0x28 ++ ++#if (MDMA_SUPPORT_ALPHA_BLEND == 1) ++#define MDMA_PIXELFORMAT_OFFSET 0x2c ++#define MDMA_ALPHA_OFFSET 0x30 ++#define MDMA_CLUT_BASE_OFFSET 0x400 ++#endif ++ ++#define MDMA_SRC_1_BASE_REG GRAPHICS_DMA_REG(MDMA_SRC_1_BASE_OFFSET) ++#define MDMA_SRC_1_PITCH_REG GRAPHICS_DMA_REG(MDMA_SRC_1_PITCH_OFFSET) ++#define MDMA_SRC_2_BASE_REG GRAPHICS_DMA_REG(MDMA_SRC_2_BASE_OFFSET) ++#define MDMA_SRC_2_PITCH_REG GRAPHICS_DMA_REG(MDMA_SRC_2_PITCH_OFFSET) ++#define MDMA_DST_BASE_REG GRAPHICS_DMA_REG(MDMA_DST_BASE_OFFSET) ++#define MDMA_DST_PITCH_REG GRAPHICS_DMA_REG(MDMA_DST_PITCH_OFFSET) ++#define MDMA_WIDTH_REG GRAPHICS_DMA_REG(MDMA_WIDTH_OFFSET) ++#define MDMA_HEIGHT_REG GRAPHICS_DMA_REG(MDMA_HIGHT_OFFSET) ++#define MDMA_TRANSPARENT_REG GRAPHICS_DMA_REG(MDMA_TRANSPARENT_OFFSET) ++#define MDMA_OPCODE_REG GRAPHICS_DMA_REG(MDMA_OPCODE_OFFSET) ++#define MDMA_PENDING_OPS_REG GRAPHICS_DMA_REG(MDMA_PENDING_OPS_OFFSET) ++ ++#if (MDMA_SUPPORT_ALPHA_BLEND == 1) ++#define MDMA_PIXELFORMAT_REG GRAPHICS_DMA_REG(MDMA_PIXELFORMAT_OFFSET) ++#define MDMA_ALPHA_REG GRAPHICS_DMA_REG(MDMA_ALPHA_OFFSET) ++#define MDMA_CLUT_BASE_REG GRAPHICS_DMA_REG(MDMA_CLUT_BASE_OFFSET) ++ ++/* MDMA_PIXELFORMAT_REG */ ++#define MDMA_PIXELFORMAT_THROTTLE_DRAM (1L << 11) ++ ++#endif /* (MDMA_SUPPORT_ALPHA_BLEND == 1)*/ ++#endif /* MDMA_ON_AHB == 1 */ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/reglock.h b/arch/arm/plat-goke/include/plat/reglock.h +new file mode 100644 +index 00000000..7b657ab8 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/reglock.h +@@ -0,0 +1,44 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/reglock.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_REGISTER_LOCK_H ++#define __PLAT_REGISTER_LOCK_H ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++ ++#ifdef CONFIG_GK_ADD_REGISTER_LOCK ++#include ++extern spinlock_t gk_register_lock; ++extern unsigned long gk_register_flags; ++extern u32 gk_reglock_count; ++ ++#define GK_REG_LOCK() spin_lock_irqsave(&gk_register_lock, gk_register_flags) ++#define GK_REG_UNLOCK() spin_unlock_irqrestore(&gk_register_lock, gk_register_flags) ++#define GK_INC_REGLOCK_COUNT() gk_reglock_count++ ++#else ++#define GK_REG_LOCK() ++#define GK_REG_UNLOCK() ++#define GK_INC_REGLOCK_COUNT() ++ ++#endif /* CONFIG_GK_ADD_REGISTER_LOCK */ ++ ++#endif /* __ASSEMBLER__ */ ++/* ==========================================================================*/ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/include/plat/syncproc.h b/arch/arm/plat-goke/include/plat/syncproc.h +new file mode 100644 +index 00000000..c15eb2d8 +--- /dev/null ++++ b/arch/arm/plat-goke/include/plat/syncproc.h +@@ -0,0 +1,73 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/include/plat/syncproc.h ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#ifndef __PLAT_SYNC_PROC_H ++#define __PLAT_SYNC_PROC_H ++ ++/* ==========================================================================*/ ++#define GK_SYNC_PROC_MAX_ID (31) ++#define GK_SYNC_PROC_PAGE_SIZE (PAGE_SIZE - 16) ++ ++/* ==========================================================================*/ ++#ifndef __ASSEMBLER__ ++#include ++#include ++#include ++typedef int(sync_read_proc_t)(char *start, void *data); ++ ++struct gk_sync_proc_pinfo { ++ u32 id; ++ u32 mask; ++ char *page; ++}; ++ ++struct gk_sync_proc_hinfo { ++ u32 maxid; ++ wait_queue_head_t sync_proc_head; ++ atomic_t sync_proc_flag; ++ struct idr sync_proc_idr; ++ struct mutex sync_proc_lock; ++ sync_read_proc_t *sync_read_proc; ++ void *sync_read_data; ++}; ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++extern int gk_sync_proc_hinit(struct gk_sync_proc_hinfo *hinfo); ++extern int gk_sync_proc_open(struct inode *inode, struct file *file); ++extern int gk_sync_proc_release(struct inode *inode, struct file *file); ++extern ssize_t gk_sync_proc_read(struct file *file, char __user *buf, size_t size, loff_t *ppos); ++extern ssize_t gk_sync_proc_write(struct file *file, const char __user *buf, size_t size, loff_t *ppos); ++ ++struct gk_async_proc_info { ++ char proc_name[256]; ++ struct file_operations fops; ++ void *private_data; ++ struct fasync_struct *fasync_queue; ++ struct mutex op_mutex; ++ int use_count; ++}; ++ ++extern int gk_async_proc_create(struct gk_async_proc_info *pinfo); ++extern int gk_async_proc_remove(struct gk_async_proc_info *pinfo); ++ ++ ++#endif /* __ASSEMBLER__ */ ++ ++#endif ++ +diff --git a/arch/arm/plat-goke/pmu.c b/arch/arm/plat-goke/pmu.c +new file mode 100644 +index 00000000..771737f9 +--- /dev/null ++++ b/arch/arm/plat-goke/pmu.c +@@ -0,0 +1,3869 @@ ++/* ++ * arch/arm/mach-gk7101/pmu.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++u8 BOOTRAM[SZ_4K] = {0}; // 4K MCU boot ram ++ ++u8* load_data_init(void) ++{ ++ BOOTRAM[0] = 0x02; ++ BOOTRAM[1] = 0x08; ++ BOOTRAM[2] = 0x40; ++ BOOTRAM[3] = 0x02; ++ BOOTRAM[4] = 0x09; ++ BOOTRAM[5] = 0xCE; ++ BOOTRAM[6] = 0x90; ++ BOOTRAM[7] = 0x81; ++ BOOTRAM[8] = 0x80; ++ BOOTRAM[9] = 0xEB; ++ BOOTRAM[10] = 0xF0; ++ BOOTRAM[11] = 0xA3; ++ BOOTRAM[12] = 0xEA; ++ BOOTRAM[13] = 0xF0; ++ BOOTRAM[14] = 0xA3; ++ BOOTRAM[15] = 0xE9; ++ BOOTRAM[16] = 0xF0; ++ BOOTRAM[17] = 0xE4; ++ BOOTRAM[18] = 0x90; ++ BOOTRAM[19] = 0x81; ++ BOOTRAM[20] = 0x89; ++ BOOTRAM[21] = 0xF0; ++ BOOTRAM[22] = 0xFD; ++ BOOTRAM[23] = 0xFC; ++ BOOTRAM[24] = 0xD3; ++ BOOTRAM[25] = 0x90; ++ BOOTRAM[26] = 0x81; ++ BOOTRAM[27] = 0x4F; ++ BOOTRAM[28] = 0xE0; ++ BOOTRAM[29] = 0x9D; ++ BOOTRAM[30] = 0x90; ++ BOOTRAM[31] = 0x81; ++ BOOTRAM[32] = 0x4E; ++ BOOTRAM[33] = 0xE0; ++ BOOTRAM[34] = 0x9C; ++ BOOTRAM[35] = 0x50; ++ BOOTRAM[36] = 0x03; ++ BOOTRAM[37] = 0x02; ++ BOOTRAM[38] = 0x03; ++ BOOTRAM[39] = 0x0E; ++ BOOTRAM[40] = 0xED; ++ BOOTRAM[41] = 0x25; ++ BOOTRAM[42] = 0xE0; ++ BOOTRAM[43] = 0xFF; ++ BOOTRAM[44] = 0xEC; ++ BOOTRAM[45] = 0x33; ++ BOOTRAM[46] = 0xFE; ++ BOOTRAM[47] = 0x74; ++ BOOTRAM[48] = 0x00; ++ BOOTRAM[49] = 0x2F; ++ BOOTRAM[50] = 0xF5; ++ BOOTRAM[51] = 0x82; ++ BOOTRAM[52] = 0x74; ++ BOOTRAM[53] = 0x81; ++ BOOTRAM[54] = 0x3E; ++ BOOTRAM[55] = 0xF5; ++ BOOTRAM[56] = 0x83; ++ BOOTRAM[57] = 0xE0; ++ BOOTRAM[58] = 0xFE; ++ BOOTRAM[59] = 0xA3; ++ BOOTRAM[60] = 0xE0; ++ BOOTRAM[61] = 0xFF; ++ BOOTRAM[62] = 0x90; ++ BOOTRAM[63] = 0x81; ++ BOOTRAM[64] = 0x89; ++ BOOTRAM[65] = 0xE0; ++ BOOTRAM[66] = 0xF9; ++ BOOTRAM[67] = 0x70; ++ BOOTRAM[68] = 0x3E; ++ BOOTRAM[69] = 0xC3; ++ BOOTRAM[70] = 0xEF; ++ BOOTRAM[71] = 0x94; ++ BOOTRAM[72] = 0x7C; ++ BOOTRAM[73] = 0xEE; ++ BOOTRAM[74] = 0x94; ++ BOOTRAM[75] = 0x15; ++ BOOTRAM[76] = 0x50; ++ BOOTRAM[77] = 0x0C; ++ BOOTRAM[78] = 0xEF; ++ BOOTRAM[79] = 0x94; ++ BOOTRAM[80] = 0x94; ++ BOOTRAM[81] = 0xEE; ++ BOOTRAM[82] = 0x94; ++ BOOTRAM[83] = 0x11; ++ BOOTRAM[84] = 0x40; ++ BOOTRAM[85] = 0x04; ++ BOOTRAM[86] = 0x74; ++ BOOTRAM[87] = 0x01; ++ BOOTRAM[88] = 0x80; ++ BOOTRAM[89] = 0x16; ++ BOOTRAM[90] = 0xC3; ++ BOOTRAM[91] = 0xEF; ++ BOOTRAM[92] = 0x94; ++ BOOTRAM[93] = 0xB8; ++ BOOTRAM[94] = 0xEE; ++ BOOTRAM[95] = 0x94; ++ BOOTRAM[96] = 0x0B; ++ BOOTRAM[97] = 0x50; ++ BOOTRAM[98] = 0x1D; ++ BOOTRAM[99] = 0xEF; ++ BOOTRAM[100] = 0x94; ++ BOOTRAM[101] = 0xC4; ++ BOOTRAM[102] = 0xEE; ++ BOOTRAM[103] = 0x94; ++ BOOTRAM[104] = 0x09; ++ BOOTRAM[105] = 0x40; ++ BOOTRAM[106] = 0x15; ++ BOOTRAM[107] = 0x90; ++ BOOTRAM[108] = 0x81; ++ BOOTRAM[109] = 0x89; ++ BOOTRAM[110] = 0x74; ++ BOOTRAM[111] = 0x14; ++ BOOTRAM[112] = 0xF0; ++ BOOTRAM[113] = 0xE4; ++ BOOTRAM[114] = 0x90; ++ BOOTRAM[115] = 0x81; ++ BOOTRAM[116] = 0x83; ++ BOOTRAM[117] = 0xF0; ++ BOOTRAM[118] = 0xA3; ++ BOOTRAM[119] = 0xF0; ++ BOOTRAM[120] = 0xA3; ++ BOOTRAM[121] = 0xF0; ++ BOOTRAM[122] = 0xA3; ++ BOOTRAM[123] = 0xF0; ++ BOOTRAM[124] = 0xA3; ++ BOOTRAM[125] = 0x02; ++ BOOTRAM[126] = 0x02; ++ BOOTRAM[127] = 0xF9; ++ BOOTRAM[128] = 0x02; ++ BOOTRAM[129] = 0x03; ++ BOOTRAM[130] = 0x00; ++ BOOTRAM[131] = 0xE9; ++ BOOTRAM[132] = 0x64; ++ BOOTRAM[133] = 0x01; ++ BOOTRAM[134] = 0x60; ++ BOOTRAM[135] = 0x03; ++ BOOTRAM[136] = 0x02; ++ BOOTRAM[137] = 0x01; ++ BOOTRAM[138] = 0x21; ++ BOOTRAM[139] = 0xC3; ++ BOOTRAM[140] = 0xEF; ++ BOOTRAM[141] = 0x94; ++ BOOTRAM[142] = 0xB0; ++ BOOTRAM[143] = 0xEE; ++ BOOTRAM[144] = 0x94; ++ BOOTRAM[145] = 0x04; ++ BOOTRAM[146] = 0x50; ++ BOOTRAM[147] = 0x37; ++ BOOTRAM[148] = 0xEF; ++ BOOTRAM[149] = 0x94; ++ BOOTRAM[150] = 0xE8; ++ BOOTRAM[151] = 0xEE; ++ BOOTRAM[152] = 0x94; ++ BOOTRAM[153] = 0x03; ++ BOOTRAM[154] = 0x40; ++ BOOTRAM[155] = 0x2F; ++ BOOTRAM[156] = 0x90; ++ BOOTRAM[157] = 0x81; ++ BOOTRAM[158] = 0x83; ++ BOOTRAM[159] = 0xE0; ++ BOOTRAM[160] = 0xF0; ++ BOOTRAM[161] = 0x90; ++ BOOTRAM[162] = 0x81; ++ BOOTRAM[163] = 0x88; ++ BOOTRAM[164] = 0xE0; ++ BOOTRAM[165] = 0x04; ++ BOOTRAM[166] = 0xF0; ++ BOOTRAM[167] = 0x70; ++ BOOTRAM[168] = 0x06; ++ BOOTRAM[169] = 0x90; ++ BOOTRAM[170] = 0x81; ++ BOOTRAM[171] = 0x87; ++ BOOTRAM[172] = 0xE0; ++ BOOTRAM[173] = 0x04; ++ BOOTRAM[174] = 0xF0; ++ BOOTRAM[175] = 0x90; ++ BOOTRAM[176] = 0x81; ++ BOOTRAM[177] = 0x87; ++ BOOTRAM[178] = 0xE0; ++ BOOTRAM[179] = 0x70; ++ BOOTRAM[180] = 0x04; ++ BOOTRAM[181] = 0xA3; ++ BOOTRAM[182] = 0xE0; ++ BOOTRAM[183] = 0x64; ++ BOOTRAM[184] = 0x08; ++ BOOTRAM[185] = 0x60; ++ BOOTRAM[186] = 0x03; ++ BOOTRAM[187] = 0x02; ++ BOOTRAM[188] = 0x03; ++ BOOTRAM[189] = 0x06; ++ BOOTRAM[190] = 0x90; ++ BOOTRAM[191] = 0x81; ++ BOOTRAM[192] = 0x89; ++ BOOTRAM[193] = 0x74; ++ BOOTRAM[194] = 0x02; ++ BOOTRAM[195] = 0xF0; ++ BOOTRAM[196] = 0xE4; ++ BOOTRAM[197] = 0x90; ++ BOOTRAM[198] = 0x81; ++ BOOTRAM[199] = 0x87; ++ BOOTRAM[200] = 0x02; ++ BOOTRAM[201] = 0x02; ++ BOOTRAM[202] = 0xF9; ++ BOOTRAM[203] = 0xC3; ++ BOOTRAM[204] = 0xEF; ++ BOOTRAM[205] = 0x94; ++ BOOTRAM[206] = 0xFC; ++ BOOTRAM[207] = 0xEE; ++ BOOTRAM[208] = 0x94; ++ BOOTRAM[209] = 0x08; ++ BOOTRAM[210] = 0x50; ++ BOOTRAM[211] = 0x4A; ++ BOOTRAM[212] = 0xEF; ++ BOOTRAM[213] = 0x94; ++ BOOTRAM[214] = 0xD0; ++ BOOTRAM[215] = 0xEE; ++ BOOTRAM[216] = 0x94; ++ BOOTRAM[217] = 0x07; ++ BOOTRAM[218] = 0x40; ++ BOOTRAM[219] = 0x42; ++ BOOTRAM[220] = 0x90; ++ BOOTRAM[221] = 0x81; ++ BOOTRAM[222] = 0x87; ++ BOOTRAM[223] = 0xA3; ++ BOOTRAM[224] = 0xE0; ++ BOOTRAM[225] = 0xFB; ++ BOOTRAM[226] = 0x74; ++ BOOTRAM[227] = 0x01; ++ BOOTRAM[228] = 0xA8; ++ BOOTRAM[229] = 0x03; ++ BOOTRAM[230] = 0x08; ++ BOOTRAM[231] = 0x80; ++ BOOTRAM[232] = 0x02; ++ BOOTRAM[233] = 0xC3; ++ BOOTRAM[234] = 0x33; ++ BOOTRAM[235] = 0xD8; ++ BOOTRAM[236] = 0xFC; ++ BOOTRAM[237] = 0xFB; ++ BOOTRAM[238] = 0x90; ++ BOOTRAM[239] = 0x81; ++ BOOTRAM[240] = 0x83; ++ BOOTRAM[241] = 0xE0; ++ BOOTRAM[242] = 0x2B; ++ BOOTRAM[243] = 0xF0; ++ BOOTRAM[244] = 0x90; ++ BOOTRAM[245] = 0x81; ++ BOOTRAM[246] = 0x88; ++ BOOTRAM[247] = 0xE0; ++ BOOTRAM[248] = 0x04; ++ BOOTRAM[249] = 0xF0; ++ BOOTRAM[250] = 0x70; ++ BOOTRAM[251] = 0x06; ++ BOOTRAM[252] = 0x90; ++ BOOTRAM[253] = 0x81; ++ BOOTRAM[254] = 0x87; ++ BOOTRAM[255] = 0xE0; ++ BOOTRAM[256] = 0x04; ++ BOOTRAM[257] = 0xF0; ++ BOOTRAM[258] = 0x90; ++ BOOTRAM[259] = 0x81; ++ BOOTRAM[260] = 0x87; ++ BOOTRAM[261] = 0xE0; ++ BOOTRAM[262] = 0x70; ++ BOOTRAM[263] = 0x04; ++ BOOTRAM[264] = 0xA3; ++ BOOTRAM[265] = 0xE0; ++ BOOTRAM[266] = 0x64; ++ BOOTRAM[267] = 0x08; ++ BOOTRAM[268] = 0x60; ++ BOOTRAM[269] = 0x03; ++ BOOTRAM[270] = 0x02; ++ BOOTRAM[271] = 0x03; ++ BOOTRAM[272] = 0x06; ++ BOOTRAM[273] = 0x90; ++ BOOTRAM[274] = 0x81; ++ BOOTRAM[275] = 0x89; ++ BOOTRAM[276] = 0x74; ++ BOOTRAM[277] = 0x02; ++ BOOTRAM[278] = 0xF0; ++ BOOTRAM[279] = 0xE4; ++ BOOTRAM[280] = 0x90; ++ BOOTRAM[281] = 0x81; ++ BOOTRAM[282] = 0x87; ++ BOOTRAM[283] = 0x02; ++ BOOTRAM[284] = 0x02; ++ BOOTRAM[285] = 0xF9; ++ BOOTRAM[286] = 0x02; ++ BOOTRAM[287] = 0x03; ++ BOOTRAM[288] = 0x00; ++ BOOTRAM[289] = 0xE9; ++ BOOTRAM[290] = 0x64; ++ BOOTRAM[291] = 0x02; ++ BOOTRAM[292] = 0x60; ++ BOOTRAM[293] = 0x03; ++ BOOTRAM[294] = 0x02; ++ BOOTRAM[295] = 0x01; ++ BOOTRAM[296] = 0xBF; ++ BOOTRAM[297] = 0xC3; ++ BOOTRAM[298] = 0xEF; ++ BOOTRAM[299] = 0x94; ++ BOOTRAM[300] = 0xB0; ++ BOOTRAM[301] = 0xEE; ++ BOOTRAM[302] = 0x94; ++ BOOTRAM[303] = 0x04; ++ BOOTRAM[304] = 0x50; ++ BOOTRAM[305] = 0x37; ++ BOOTRAM[306] = 0xEF; ++ BOOTRAM[307] = 0x94; ++ BOOTRAM[308] = 0xE8; ++ BOOTRAM[309] = 0xEE; ++ BOOTRAM[310] = 0x94; ++ BOOTRAM[311] = 0x03; ++ BOOTRAM[312] = 0x40; ++ BOOTRAM[313] = 0x2F; ++ BOOTRAM[314] = 0x90; ++ BOOTRAM[315] = 0x81; ++ BOOTRAM[316] = 0x84; ++ BOOTRAM[317] = 0xE0; ++ BOOTRAM[318] = 0xF0; ++ BOOTRAM[319] = 0x90; ++ BOOTRAM[320] = 0x81; ++ BOOTRAM[321] = 0x88; ++ BOOTRAM[322] = 0xE0; ++ BOOTRAM[323] = 0x04; ++ BOOTRAM[324] = 0xF0; ++ BOOTRAM[325] = 0x70; ++ BOOTRAM[326] = 0x06; ++ BOOTRAM[327] = 0x90; ++ BOOTRAM[328] = 0x81; ++ BOOTRAM[329] = 0x87; ++ BOOTRAM[330] = 0xE0; ++ BOOTRAM[331] = 0x04; ++ BOOTRAM[332] = 0xF0; ++ BOOTRAM[333] = 0x90; ++ BOOTRAM[334] = 0x81; ++ BOOTRAM[335] = 0x87; ++ BOOTRAM[336] = 0xE0; ++ BOOTRAM[337] = 0x70; ++ BOOTRAM[338] = 0x04; ++ BOOTRAM[339] = 0xA3; ++ BOOTRAM[340] = 0xE0; ++ BOOTRAM[341] = 0x64; ++ BOOTRAM[342] = 0x08; ++ BOOTRAM[343] = 0x60; ++ BOOTRAM[344] = 0x03; ++ BOOTRAM[345] = 0x02; ++ BOOTRAM[346] = 0x03; ++ BOOTRAM[347] = 0x06; ++ BOOTRAM[348] = 0x90; ++ BOOTRAM[349] = 0x81; ++ BOOTRAM[350] = 0x89; ++ BOOTRAM[351] = 0x74; ++ BOOTRAM[352] = 0x03; ++ BOOTRAM[353] = 0xF0; ++ BOOTRAM[354] = 0xE4; ++ BOOTRAM[355] = 0x90; ++ BOOTRAM[356] = 0x81; ++ BOOTRAM[357] = 0x87; ++ BOOTRAM[358] = 0x02; ++ BOOTRAM[359] = 0x02; ++ BOOTRAM[360] = 0xF9; ++ BOOTRAM[361] = 0xC3; ++ BOOTRAM[362] = 0xEF; ++ BOOTRAM[363] = 0x94; ++ BOOTRAM[364] = 0xFC; ++ BOOTRAM[365] = 0xEE; ++ BOOTRAM[366] = 0x94; ++ BOOTRAM[367] = 0x08; ++ BOOTRAM[368] = 0x50; ++ BOOTRAM[369] = 0x4A; ++ BOOTRAM[370] = 0xEF; ++ BOOTRAM[371] = 0x94; ++ BOOTRAM[372] = 0xD0; ++ BOOTRAM[373] = 0xEE; ++ BOOTRAM[374] = 0x94; ++ BOOTRAM[375] = 0x07; ++ BOOTRAM[376] = 0x40; ++ BOOTRAM[377] = 0x42; ++ BOOTRAM[378] = 0x90; ++ BOOTRAM[379] = 0x81; ++ BOOTRAM[380] = 0x87; ++ BOOTRAM[381] = 0xA3; ++ BOOTRAM[382] = 0xE0; ++ BOOTRAM[383] = 0xFB; ++ BOOTRAM[384] = 0x74; ++ BOOTRAM[385] = 0x01; ++ BOOTRAM[386] = 0xA8; ++ BOOTRAM[387] = 0x03; ++ BOOTRAM[388] = 0x08; ++ BOOTRAM[389] = 0x80; ++ BOOTRAM[390] = 0x02; ++ BOOTRAM[391] = 0xC3; ++ BOOTRAM[392] = 0x33; ++ BOOTRAM[393] = 0xD8; ++ BOOTRAM[394] = 0xFC; ++ BOOTRAM[395] = 0xFB; ++ BOOTRAM[396] = 0x90; ++ BOOTRAM[397] = 0x81; ++ BOOTRAM[398] = 0x84; ++ BOOTRAM[399] = 0xE0; ++ BOOTRAM[400] = 0x2B; ++ BOOTRAM[401] = 0xF0; ++ BOOTRAM[402] = 0x90; ++ BOOTRAM[403] = 0x81; ++ BOOTRAM[404] = 0x88; ++ BOOTRAM[405] = 0xE0; ++ BOOTRAM[406] = 0x04; ++ BOOTRAM[407] = 0xF0; ++ BOOTRAM[408] = 0x70; ++ BOOTRAM[409] = 0x06; ++ BOOTRAM[410] = 0x90; ++ BOOTRAM[411] = 0x81; ++ BOOTRAM[412] = 0x87; ++ BOOTRAM[413] = 0xE0; ++ BOOTRAM[414] = 0x04; ++ BOOTRAM[415] = 0xF0; ++ BOOTRAM[416] = 0x90; ++ BOOTRAM[417] = 0x81; ++ BOOTRAM[418] = 0x87; ++ BOOTRAM[419] = 0xE0; ++ BOOTRAM[420] = 0x70; ++ BOOTRAM[421] = 0x04; ++ BOOTRAM[422] = 0xA3; ++ BOOTRAM[423] = 0xE0; ++ BOOTRAM[424] = 0x64; ++ BOOTRAM[425] = 0x08; ++ BOOTRAM[426] = 0x60; ++ BOOTRAM[427] = 0x03; ++ BOOTRAM[428] = 0x02; ++ BOOTRAM[429] = 0x03; ++ BOOTRAM[430] = 0x06; ++ BOOTRAM[431] = 0x90; ++ BOOTRAM[432] = 0x81; ++ BOOTRAM[433] = 0x89; ++ BOOTRAM[434] = 0x74; ++ BOOTRAM[435] = 0x03; ++ BOOTRAM[436] = 0xF0; ++ BOOTRAM[437] = 0xE4; ++ BOOTRAM[438] = 0x90; ++ BOOTRAM[439] = 0x81; ++ BOOTRAM[440] = 0x87; ++ BOOTRAM[441] = 0x02; ++ BOOTRAM[442] = 0x02; ++ BOOTRAM[443] = 0xF9; ++ BOOTRAM[444] = 0x02; ++ BOOTRAM[445] = 0x03; ++ BOOTRAM[446] = 0x00; ++ BOOTRAM[447] = 0xE9; ++ BOOTRAM[448] = 0x64; ++ BOOTRAM[449] = 0x03; ++ BOOTRAM[450] = 0x60; ++ BOOTRAM[451] = 0x03; ++ BOOTRAM[452] = 0x02; ++ BOOTRAM[453] = 0x02; ++ BOOTRAM[454] = 0x5D; ++ BOOTRAM[455] = 0xC3; ++ BOOTRAM[456] = 0xEF; ++ BOOTRAM[457] = 0x94; ++ BOOTRAM[458] = 0xB0; ++ BOOTRAM[459] = 0xEE; ++ BOOTRAM[460] = 0x94; ++ BOOTRAM[461] = 0x04; ++ BOOTRAM[462] = 0x50; ++ BOOTRAM[463] = 0x37; ++ BOOTRAM[464] = 0xEF; ++ BOOTRAM[465] = 0x94; ++ BOOTRAM[466] = 0xE8; ++ BOOTRAM[467] = 0xEE; ++ BOOTRAM[468] = 0x94; ++ BOOTRAM[469] = 0x03; ++ BOOTRAM[470] = 0x40; ++ BOOTRAM[471] = 0x2F; ++ BOOTRAM[472] = 0x90; ++ BOOTRAM[473] = 0x81; ++ BOOTRAM[474] = 0x85; ++ BOOTRAM[475] = 0xE0; ++ BOOTRAM[476] = 0xF0; ++ BOOTRAM[477] = 0x90; ++ BOOTRAM[478] = 0x81; ++ BOOTRAM[479] = 0x88; ++ BOOTRAM[480] = 0xE0; ++ BOOTRAM[481] = 0x04; ++ BOOTRAM[482] = 0xF0; ++ BOOTRAM[483] = 0x70; ++ BOOTRAM[484] = 0x06; ++ BOOTRAM[485] = 0x90; ++ BOOTRAM[486] = 0x81; ++ BOOTRAM[487] = 0x87; ++ BOOTRAM[488] = 0xE0; ++ BOOTRAM[489] = 0x04; ++ BOOTRAM[490] = 0xF0; ++ BOOTRAM[491] = 0x90; ++ BOOTRAM[492] = 0x81; ++ BOOTRAM[493] = 0x87; ++ BOOTRAM[494] = 0xE0; ++ BOOTRAM[495] = 0x70; ++ BOOTRAM[496] = 0x04; ++ BOOTRAM[497] = 0xA3; ++ BOOTRAM[498] = 0xE0; ++ BOOTRAM[499] = 0x64; ++ BOOTRAM[500] = 0x08; ++ BOOTRAM[501] = 0x60; ++ BOOTRAM[502] = 0x03; ++ BOOTRAM[503] = 0x02; ++ BOOTRAM[504] = 0x03; ++ BOOTRAM[505] = 0x06; ++ BOOTRAM[506] = 0x90; ++ BOOTRAM[507] = 0x81; ++ BOOTRAM[508] = 0x89; ++ BOOTRAM[509] = 0x74; ++ BOOTRAM[510] = 0x04; ++ BOOTRAM[511] = 0xF0; ++ BOOTRAM[512] = 0xE4; ++ BOOTRAM[513] = 0x90; ++ BOOTRAM[514] = 0x81; ++ BOOTRAM[515] = 0x87; ++ BOOTRAM[516] = 0x02; ++ BOOTRAM[517] = 0x02; ++ BOOTRAM[518] = 0xF9; ++ BOOTRAM[519] = 0xC3; ++ BOOTRAM[520] = 0xEF; ++ BOOTRAM[521] = 0x94; ++ BOOTRAM[522] = 0xFC; ++ BOOTRAM[523] = 0xEE; ++ BOOTRAM[524] = 0x94; ++ BOOTRAM[525] = 0x08; ++ BOOTRAM[526] = 0x50; ++ BOOTRAM[527] = 0x4A; ++ BOOTRAM[528] = 0xEF; ++ BOOTRAM[529] = 0x94; ++ BOOTRAM[530] = 0xD0; ++ BOOTRAM[531] = 0xEE; ++ BOOTRAM[532] = 0x94; ++ BOOTRAM[533] = 0x07; ++ BOOTRAM[534] = 0x40; ++ BOOTRAM[535] = 0x42; ++ BOOTRAM[536] = 0x90; ++ BOOTRAM[537] = 0x81; ++ BOOTRAM[538] = 0x87; ++ BOOTRAM[539] = 0xA3; ++ BOOTRAM[540] = 0xE0; ++ BOOTRAM[541] = 0xFB; ++ BOOTRAM[542] = 0x74; ++ BOOTRAM[543] = 0x01; ++ BOOTRAM[544] = 0xA8; ++ BOOTRAM[545] = 0x03; ++ BOOTRAM[546] = 0x08; ++ BOOTRAM[547] = 0x80; ++ BOOTRAM[548] = 0x02; ++ BOOTRAM[549] = 0xC3; ++ BOOTRAM[550] = 0x33; ++ BOOTRAM[551] = 0xD8; ++ BOOTRAM[552] = 0xFC; ++ BOOTRAM[553] = 0xFB; ++ BOOTRAM[554] = 0x90; ++ BOOTRAM[555] = 0x81; ++ BOOTRAM[556] = 0x85; ++ BOOTRAM[557] = 0xE0; ++ BOOTRAM[558] = 0x2B; ++ BOOTRAM[559] = 0xF0; ++ BOOTRAM[560] = 0x90; ++ BOOTRAM[561] = 0x81; ++ BOOTRAM[562] = 0x88; ++ BOOTRAM[563] = 0xE0; ++ BOOTRAM[564] = 0x04; ++ BOOTRAM[565] = 0xF0; ++ BOOTRAM[566] = 0x70; ++ BOOTRAM[567] = 0x06; ++ BOOTRAM[568] = 0x90; ++ BOOTRAM[569] = 0x81; ++ BOOTRAM[570] = 0x87; ++ BOOTRAM[571] = 0xE0; ++ BOOTRAM[572] = 0x04; ++ BOOTRAM[573] = 0xF0; ++ BOOTRAM[574] = 0x90; ++ BOOTRAM[575] = 0x81; ++ BOOTRAM[576] = 0x87; ++ BOOTRAM[577] = 0xE0; ++ BOOTRAM[578] = 0x70; ++ BOOTRAM[579] = 0x04; ++ BOOTRAM[580] = 0xA3; ++ BOOTRAM[581] = 0xE0; ++ BOOTRAM[582] = 0x64; ++ BOOTRAM[583] = 0x08; ++ BOOTRAM[584] = 0x60; ++ BOOTRAM[585] = 0x03; ++ BOOTRAM[586] = 0x02; ++ BOOTRAM[587] = 0x03; ++ BOOTRAM[588] = 0x06; ++ BOOTRAM[589] = 0x90; ++ BOOTRAM[590] = 0x81; ++ BOOTRAM[591] = 0x89; ++ BOOTRAM[592] = 0x74; ++ BOOTRAM[593] = 0x04; ++ BOOTRAM[594] = 0xF0; ++ BOOTRAM[595] = 0xE4; ++ BOOTRAM[596] = 0x90; ++ BOOTRAM[597] = 0x81; ++ BOOTRAM[598] = 0x87; ++ BOOTRAM[599] = 0x02; ++ BOOTRAM[600] = 0x02; ++ BOOTRAM[601] = 0xF9; ++ BOOTRAM[602] = 0x02; ++ BOOTRAM[603] = 0x03; ++ BOOTRAM[604] = 0x00; ++ BOOTRAM[605] = 0xE9; ++ BOOTRAM[606] = 0x64; ++ BOOTRAM[607] = 0x04; ++ BOOTRAM[608] = 0x60; ++ BOOTRAM[609] = 0x03; ++ BOOTRAM[610] = 0x02; ++ BOOTRAM[611] = 0x03; ++ BOOTRAM[612] = 0x06; ++ BOOTRAM[613] = 0xC3; ++ BOOTRAM[614] = 0xEF; ++ BOOTRAM[615] = 0x94; ++ BOOTRAM[616] = 0xB0; ++ BOOTRAM[617] = 0xEE; ++ BOOTRAM[618] = 0x94; ++ BOOTRAM[619] = 0x04; ++ BOOTRAM[620] = 0x50; ++ BOOTRAM[621] = 0x33; ++ BOOTRAM[622] = 0xEF; ++ BOOTRAM[623] = 0x94; ++ BOOTRAM[624] = 0xE8; ++ BOOTRAM[625] = 0xEE; ++ BOOTRAM[626] = 0x94; ++ BOOTRAM[627] = 0x03; ++ BOOTRAM[628] = 0x40; ++ BOOTRAM[629] = 0x2B; ++ BOOTRAM[630] = 0x90; ++ BOOTRAM[631] = 0x81; ++ BOOTRAM[632] = 0x86; ++ BOOTRAM[633] = 0xE0; ++ BOOTRAM[634] = 0xF0; ++ BOOTRAM[635] = 0x90; ++ BOOTRAM[636] = 0x81; ++ BOOTRAM[637] = 0x88; ++ BOOTRAM[638] = 0xE0; ++ BOOTRAM[639] = 0x04; ++ BOOTRAM[640] = 0xF0; ++ BOOTRAM[641] = 0x70; ++ BOOTRAM[642] = 0x06; ++ BOOTRAM[643] = 0x90; ++ BOOTRAM[644] = 0x81; ++ BOOTRAM[645] = 0x87; ++ BOOTRAM[646] = 0xE0; ++ BOOTRAM[647] = 0x04; ++ BOOTRAM[648] = 0xF0; ++ BOOTRAM[649] = 0x90; ++ BOOTRAM[650] = 0x81; ++ BOOTRAM[651] = 0x87; ++ BOOTRAM[652] = 0xE0; ++ BOOTRAM[653] = 0x70; ++ BOOTRAM[654] = 0x04; ++ BOOTRAM[655] = 0xA3; ++ BOOTRAM[656] = 0xE0; ++ BOOTRAM[657] = 0x64; ++ BOOTRAM[658] = 0x08; ++ BOOTRAM[659] = 0x70; ++ BOOTRAM[660] = 0x71; ++ BOOTRAM[661] = 0x90; ++ BOOTRAM[662] = 0x81; ++ BOOTRAM[663] = 0x89; ++ BOOTRAM[664] = 0x74; ++ BOOTRAM[665] = 0x05; ++ BOOTRAM[666] = 0xF0; ++ BOOTRAM[667] = 0xE4; ++ BOOTRAM[668] = 0x90; ++ BOOTRAM[669] = 0x81; ++ BOOTRAM[670] = 0x87; ++ BOOTRAM[671] = 0x80; ++ BOOTRAM[672] = 0x58; ++ BOOTRAM[673] = 0xC3; ++ BOOTRAM[674] = 0xEF; ++ BOOTRAM[675] = 0x94; ++ BOOTRAM[676] = 0xFC; ++ BOOTRAM[677] = 0xEE; ++ BOOTRAM[678] = 0x94; ++ BOOTRAM[679] = 0x08; ++ BOOTRAM[680] = 0x50; ++ BOOTRAM[681] = 0x56; ++ BOOTRAM[682] = 0xEF; ++ BOOTRAM[683] = 0x94; ++ BOOTRAM[684] = 0xD0; ++ BOOTRAM[685] = 0xEE; ++ BOOTRAM[686] = 0x94; ++ BOOTRAM[687] = 0x07; ++ BOOTRAM[688] = 0x40; ++ BOOTRAM[689] = 0x4E; ++ BOOTRAM[690] = 0x90; ++ BOOTRAM[691] = 0x81; ++ BOOTRAM[692] = 0x87; ++ BOOTRAM[693] = 0xA3; ++ BOOTRAM[694] = 0xE0; ++ BOOTRAM[695] = 0xFF; ++ BOOTRAM[696] = 0x74; ++ BOOTRAM[697] = 0x01; ++ BOOTRAM[698] = 0xA8; ++ BOOTRAM[699] = 0x07; ++ BOOTRAM[700] = 0x08; ++ BOOTRAM[701] = 0x80; ++ BOOTRAM[702] = 0x02; ++ BOOTRAM[703] = 0xC3; ++ BOOTRAM[704] = 0x33; ++ BOOTRAM[705] = 0xD8; ++ BOOTRAM[706] = 0xFC; ++ BOOTRAM[707] = 0xFF; ++ BOOTRAM[708] = 0x90; ++ BOOTRAM[709] = 0x81; ++ BOOTRAM[710] = 0x86; ++ BOOTRAM[711] = 0xE0; ++ BOOTRAM[712] = 0x2F; ++ BOOTRAM[713] = 0xF0; ++ BOOTRAM[714] = 0x90; ++ BOOTRAM[715] = 0x81; ++ BOOTRAM[716] = 0x88; ++ BOOTRAM[717] = 0xE0; ++ BOOTRAM[718] = 0x04; ++ BOOTRAM[719] = 0xF0; ++ BOOTRAM[720] = 0x70; ++ BOOTRAM[721] = 0x06; ++ BOOTRAM[722] = 0x90; ++ BOOTRAM[723] = 0x81; ++ BOOTRAM[724] = 0x87; ++ BOOTRAM[725] = 0xE0; ++ BOOTRAM[726] = 0x04; ++ BOOTRAM[727] = 0xF0; ++ BOOTRAM[728] = 0x90; ++ BOOTRAM[729] = 0x81; ++ BOOTRAM[730] = 0x87; ++ BOOTRAM[731] = 0xE0; ++ BOOTRAM[732] = 0x70; ++ BOOTRAM[733] = 0x04; ++ BOOTRAM[734] = 0xA3; ++ BOOTRAM[735] = 0xE0; ++ BOOTRAM[736] = 0x64; ++ BOOTRAM[737] = 0x08; ++ BOOTRAM[738] = 0x70; ++ BOOTRAM[739] = 0x22; ++ BOOTRAM[740] = 0x90; ++ BOOTRAM[741] = 0x81; ++ BOOTRAM[742] = 0x85; ++ BOOTRAM[743] = 0xE0; ++ BOOTRAM[744] = 0xF4; ++ BOOTRAM[745] = 0xFF; ++ BOOTRAM[746] = 0xA3; ++ BOOTRAM[747] = 0xE0; ++ BOOTRAM[748] = 0x90; ++ BOOTRAM[749] = 0x81; ++ BOOTRAM[750] = 0x89; ++ BOOTRAM[751] = 0xB5; ++ BOOTRAM[752] = 0x07; ++ BOOTRAM[753] = 0x0C; ++ BOOTRAM[754] = 0x74; ++ BOOTRAM[755] = 0x05; ++ BOOTRAM[756] = 0xF0; ++ BOOTRAM[757] = 0xE4; ++ BOOTRAM[758] = 0x90; ++ BOOTRAM[759] = 0x81; ++ BOOTRAM[760] = 0x87; ++ BOOTRAM[761] = 0xF0; ++ BOOTRAM[762] = 0xA3; ++ BOOTRAM[763] = 0xF0; ++ BOOTRAM[764] = 0x80; ++ BOOTRAM[765] = 0x08; ++ BOOTRAM[766] = 0x80; ++ BOOTRAM[767] = 0x03; ++ BOOTRAM[768] = 0x90; ++ BOOTRAM[769] = 0x81; ++ BOOTRAM[770] = 0x89; ++ BOOTRAM[771] = 0x74; ++ BOOTRAM[772] = 0x14; ++ BOOTRAM[773] = 0xF0; ++ BOOTRAM[774] = 0x0D; ++ BOOTRAM[775] = 0xBD; ++ BOOTRAM[776] = 0x00; ++ BOOTRAM[777] = 0x01; ++ BOOTRAM[778] = 0x0C; ++ BOOTRAM[779] = 0x02; ++ BOOTRAM[780] = 0x00; ++ BOOTRAM[781] = 0x18; ++ BOOTRAM[782] = 0x90; ++ BOOTRAM[783] = 0x81; ++ BOOTRAM[784] = 0x83; ++ BOOTRAM[785] = 0xE0; ++ BOOTRAM[786] = 0xFE; ++ BOOTRAM[787] = 0xA3; ++ BOOTRAM[788] = 0xE0; ++ BOOTRAM[789] = 0x7C; ++ BOOTRAM[790] = 0x00; ++ BOOTRAM[791] = 0x24; ++ BOOTRAM[792] = 0x00; ++ BOOTRAM[793] = 0xFF; ++ BOOTRAM[794] = 0xEC; ++ BOOTRAM[795] = 0x3E; ++ BOOTRAM[796] = 0xF9; ++ BOOTRAM[797] = 0x90; ++ BOOTRAM[798] = 0x81; ++ BOOTRAM[799] = 0x80; ++ BOOTRAM[800] = 0xE0; ++ BOOTRAM[801] = 0xFB; ++ BOOTRAM[802] = 0xA3; ++ BOOTRAM[803] = 0xE0; ++ BOOTRAM[804] = 0xFA; ++ BOOTRAM[805] = 0xA3; ++ BOOTRAM[806] = 0xE0; ++ BOOTRAM[807] = 0xC9; ++ BOOTRAM[808] = 0x8F; ++ BOOTRAM[809] = 0xF0; ++ BOOTRAM[810] = 0x12; ++ BOOTRAM[811] = 0x04; ++ BOOTRAM[812] = 0x57; ++ BOOTRAM[813] = 0x90; ++ BOOTRAM[814] = 0x81; ++ BOOTRAM[815] = 0x89; ++ BOOTRAM[816] = 0xE0; ++ BOOTRAM[817] = 0xB4; ++ BOOTRAM[818] = 0x05; ++ BOOTRAM[819] = 0x06; ++ BOOTRAM[820] = 0x90; ++ BOOTRAM[821] = 0x81; ++ BOOTRAM[822] = 0x85; ++ BOOTRAM[823] = 0xE0; ++ BOOTRAM[824] = 0xFF; ++ BOOTRAM[825] = 0x22; ++ BOOTRAM[826] = 0x7F; ++ BOOTRAM[827] = 0x00; ++ BOOTRAM[828] = 0x22; ++ BOOTRAM[829] = 0xE7; ++ BOOTRAM[830] = 0x09; ++ BOOTRAM[831] = 0xF6; ++ BOOTRAM[832] = 0x08; ++ BOOTRAM[833] = 0xDF; ++ BOOTRAM[834] = 0xFA; ++ BOOTRAM[835] = 0x80; ++ BOOTRAM[836] = 0x46; ++ BOOTRAM[837] = 0xE7; ++ BOOTRAM[838] = 0x09; ++ BOOTRAM[839] = 0xF2; ++ BOOTRAM[840] = 0x08; ++ BOOTRAM[841] = 0xDF; ++ BOOTRAM[842] = 0xFA; ++ BOOTRAM[843] = 0x80; ++ BOOTRAM[844] = 0x3E; ++ BOOTRAM[845] = 0x88; ++ BOOTRAM[846] = 0x82; ++ BOOTRAM[847] = 0x8C; ++ BOOTRAM[848] = 0x83; ++ BOOTRAM[849] = 0xE7; ++ BOOTRAM[850] = 0x09; ++ BOOTRAM[851] = 0xF0; ++ BOOTRAM[852] = 0xA3; ++ BOOTRAM[853] = 0xDF; ++ BOOTRAM[854] = 0xFA; ++ BOOTRAM[855] = 0x80; ++ BOOTRAM[856] = 0x32; ++ BOOTRAM[857] = 0xE3; ++ BOOTRAM[858] = 0x09; ++ BOOTRAM[859] = 0xF6; ++ BOOTRAM[860] = 0x08; ++ BOOTRAM[861] = 0xDF; ++ BOOTRAM[862] = 0xFA; ++ BOOTRAM[863] = 0x80; ++ BOOTRAM[864] = 0x78; ++ BOOTRAM[865] = 0xE3; ++ BOOTRAM[866] = 0x09; ++ BOOTRAM[867] = 0xF2; ++ BOOTRAM[868] = 0x08; ++ BOOTRAM[869] = 0xDF; ++ BOOTRAM[870] = 0xFA; ++ BOOTRAM[871] = 0x80; ++ BOOTRAM[872] = 0x70; ++ BOOTRAM[873] = 0x88; ++ BOOTRAM[874] = 0x82; ++ BOOTRAM[875] = 0x8C; ++ BOOTRAM[876] = 0x83; ++ BOOTRAM[877] = 0xE3; ++ BOOTRAM[878] = 0x09; ++ BOOTRAM[879] = 0xF0; ++ BOOTRAM[880] = 0xA3; ++ BOOTRAM[881] = 0xDF; ++ BOOTRAM[882] = 0xFA; ++ BOOTRAM[883] = 0x80; ++ BOOTRAM[884] = 0x64; ++ BOOTRAM[885] = 0x89; ++ BOOTRAM[886] = 0x82; ++ BOOTRAM[887] = 0x8A; ++ BOOTRAM[888] = 0x83; ++ BOOTRAM[889] = 0xE0; ++ BOOTRAM[890] = 0xA3; ++ BOOTRAM[891] = 0xF6; ++ BOOTRAM[892] = 0x08; ++ BOOTRAM[893] = 0xDF; ++ BOOTRAM[894] = 0xFA; ++ BOOTRAM[895] = 0x80; ++ BOOTRAM[896] = 0x58; ++ BOOTRAM[897] = 0x89; ++ BOOTRAM[898] = 0x82; ++ BOOTRAM[899] = 0x8A; ++ BOOTRAM[900] = 0x83; ++ BOOTRAM[901] = 0xE0; ++ BOOTRAM[902] = 0xA3; ++ BOOTRAM[903] = 0xF2; ++ BOOTRAM[904] = 0x08; ++ BOOTRAM[905] = 0xDF; ++ BOOTRAM[906] = 0xFA; ++ BOOTRAM[907] = 0x80; ++ BOOTRAM[908] = 0x4C; ++ BOOTRAM[909] = 0x80; ++ BOOTRAM[910] = 0xD2; ++ BOOTRAM[911] = 0x80; ++ BOOTRAM[912] = 0xFA; ++ BOOTRAM[913] = 0x80; ++ BOOTRAM[914] = 0xC6; ++ BOOTRAM[915] = 0x80; ++ BOOTRAM[916] = 0xD4; ++ BOOTRAM[917] = 0x80; ++ BOOTRAM[918] = 0x69; ++ BOOTRAM[919] = 0x80; ++ BOOTRAM[920] = 0xF2; ++ BOOTRAM[921] = 0x80; ++ BOOTRAM[922] = 0x33; ++ BOOTRAM[923] = 0x80; ++ BOOTRAM[924] = 0x10; ++ BOOTRAM[925] = 0x80; ++ BOOTRAM[926] = 0xA6; ++ BOOTRAM[927] = 0x80; ++ BOOTRAM[928] = 0xEA; ++ BOOTRAM[929] = 0x80; ++ BOOTRAM[930] = 0x9A; ++ BOOTRAM[931] = 0x80; ++ BOOTRAM[932] = 0xA8; ++ BOOTRAM[933] = 0x80; ++ BOOTRAM[934] = 0xDA; ++ BOOTRAM[935] = 0x80; ++ BOOTRAM[936] = 0xE2; ++ BOOTRAM[937] = 0x80; ++ BOOTRAM[938] = 0xCA; ++ BOOTRAM[939] = 0x80; ++ BOOTRAM[940] = 0x33; ++ BOOTRAM[941] = 0x89; ++ BOOTRAM[942] = 0x82; ++ BOOTRAM[943] = 0x8A; ++ BOOTRAM[944] = 0x83; ++ BOOTRAM[945] = 0xEC; ++ BOOTRAM[946] = 0xFA; ++ BOOTRAM[947] = 0xE4; ++ BOOTRAM[948] = 0x93; ++ BOOTRAM[949] = 0xA3; ++ BOOTRAM[950] = 0xC8; ++ BOOTRAM[951] = 0xC5; ++ BOOTRAM[952] = 0x82; ++ BOOTRAM[953] = 0xC8; ++ BOOTRAM[954] = 0xCC; ++ BOOTRAM[955] = 0xC5; ++ BOOTRAM[956] = 0x83; ++ BOOTRAM[957] = 0xCC; ++ BOOTRAM[958] = 0xF0; ++ BOOTRAM[959] = 0xA3; ++ BOOTRAM[960] = 0xC8; ++ BOOTRAM[961] = 0xC5; ++ BOOTRAM[962] = 0x82; ++ BOOTRAM[963] = 0xC8; ++ BOOTRAM[964] = 0xCC; ++ BOOTRAM[965] = 0xC5; ++ BOOTRAM[966] = 0x83; ++ BOOTRAM[967] = 0xCC; ++ BOOTRAM[968] = 0xDF; ++ BOOTRAM[969] = 0xE9; ++ BOOTRAM[970] = 0xDE; ++ BOOTRAM[971] = 0xE7; ++ BOOTRAM[972] = 0x80; ++ BOOTRAM[973] = 0x0D; ++ BOOTRAM[974] = 0x89; ++ BOOTRAM[975] = 0x82; ++ BOOTRAM[976] = 0x8A; ++ BOOTRAM[977] = 0x83; ++ BOOTRAM[978] = 0xE4; ++ BOOTRAM[979] = 0x93; ++ BOOTRAM[980] = 0xA3; ++ BOOTRAM[981] = 0xF6; ++ BOOTRAM[982] = 0x08; ++ BOOTRAM[983] = 0xDF; ++ BOOTRAM[984] = 0xF9; ++ BOOTRAM[985] = 0xEC; ++ BOOTRAM[986] = 0xFA; ++ BOOTRAM[987] = 0xA9; ++ BOOTRAM[988] = 0xF0; ++ BOOTRAM[989] = 0xED; ++ BOOTRAM[990] = 0xFB; ++ BOOTRAM[991] = 0x22; ++ BOOTRAM[992] = 0x89; ++ BOOTRAM[993] = 0x82; ++ BOOTRAM[994] = 0x8A; ++ BOOTRAM[995] = 0x83; ++ BOOTRAM[996] = 0xEC; ++ BOOTRAM[997] = 0xFA; ++ BOOTRAM[998] = 0xE0; ++ BOOTRAM[999] = 0xA3; ++ BOOTRAM[1000] = 0xC8; ++ BOOTRAM[1001] = 0xC5; ++ BOOTRAM[1002] = 0x82; ++ BOOTRAM[1003] = 0xC8; ++ BOOTRAM[1004] = 0xCC; ++ BOOTRAM[1005] = 0xC5; ++ BOOTRAM[1006] = 0x83; ++ BOOTRAM[1007] = 0xCC; ++ BOOTRAM[1008] = 0xF0; ++ BOOTRAM[1009] = 0xA3; ++ BOOTRAM[1010] = 0xC8; ++ BOOTRAM[1011] = 0xC5; ++ BOOTRAM[1012] = 0x82; ++ BOOTRAM[1013] = 0xC8; ++ BOOTRAM[1014] = 0xCC; ++ BOOTRAM[1015] = 0xC5; ++ BOOTRAM[1016] = 0x83; ++ BOOTRAM[1017] = 0xCC; ++ BOOTRAM[1018] = 0xDF; ++ BOOTRAM[1019] = 0xEA; ++ BOOTRAM[1020] = 0xDE; ++ BOOTRAM[1021] = 0xE8; ++ BOOTRAM[1022] = 0x80; ++ BOOTRAM[1023] = 0xDB; ++ BOOTRAM[1024] = 0x89; ++ BOOTRAM[1025] = 0x82; ++ BOOTRAM[1026] = 0x8A; ++ BOOTRAM[1027] = 0x83; ++ BOOTRAM[1028] = 0xE4; ++ BOOTRAM[1029] = 0x93; ++ BOOTRAM[1030] = 0xA3; ++ BOOTRAM[1031] = 0xF2; ++ BOOTRAM[1032] = 0x08; ++ BOOTRAM[1033] = 0xDF; ++ BOOTRAM[1034] = 0xF9; ++ BOOTRAM[1035] = 0x80; ++ BOOTRAM[1036] = 0xCC; ++ BOOTRAM[1037] = 0x88; ++ BOOTRAM[1038] = 0xF0; ++ BOOTRAM[1039] = 0xEF; ++ BOOTRAM[1040] = 0x60; ++ BOOTRAM[1041] = 0x01; ++ BOOTRAM[1042] = 0x0E; ++ BOOTRAM[1043] = 0x4E; ++ BOOTRAM[1044] = 0x60; ++ BOOTRAM[1045] = 0xC3; ++ BOOTRAM[1046] = 0x88; ++ BOOTRAM[1047] = 0xF0; ++ BOOTRAM[1048] = 0xED; ++ BOOTRAM[1049] = 0x24; ++ BOOTRAM[1050] = 0x02; ++ BOOTRAM[1051] = 0xB4; ++ BOOTRAM[1052] = 0x04; ++ BOOTRAM[1053] = 0x00; ++ BOOTRAM[1054] = 0x50; ++ BOOTRAM[1055] = 0xB9; ++ BOOTRAM[1056] = 0xF5; ++ BOOTRAM[1057] = 0x82; ++ BOOTRAM[1058] = 0xEB; ++ BOOTRAM[1059] = 0x24; ++ BOOTRAM[1060] = 0x02; ++ BOOTRAM[1061] = 0xB4; ++ BOOTRAM[1062] = 0x04; ++ BOOTRAM[1063] = 0x00; ++ BOOTRAM[1064] = 0x50; ++ BOOTRAM[1065] = 0xAF; ++ BOOTRAM[1066] = 0x23; ++ BOOTRAM[1067] = 0x23; ++ BOOTRAM[1068] = 0x45; ++ BOOTRAM[1069] = 0x82; ++ BOOTRAM[1070] = 0x23; ++ BOOTRAM[1071] = 0x90; ++ BOOTRAM[1072] = 0x03; ++ BOOTRAM[1073] = 0x8D; ++ BOOTRAM[1074] = 0x73; ++ BOOTRAM[1075] = 0xBB; ++ BOOTRAM[1076] = 0x01; ++ BOOTRAM[1077] = 0x06; ++ BOOTRAM[1078] = 0x89; ++ BOOTRAM[1079] = 0x82; ++ BOOTRAM[1080] = 0x8A; ++ BOOTRAM[1081] = 0x83; ++ BOOTRAM[1082] = 0xF0; ++ BOOTRAM[1083] = 0x22; ++ BOOTRAM[1084] = 0x50; ++ BOOTRAM[1085] = 0x02; ++ BOOTRAM[1086] = 0xF7; ++ BOOTRAM[1087] = 0x22; ++ BOOTRAM[1088] = 0xBB; ++ BOOTRAM[1089] = 0xFE; ++ BOOTRAM[1090] = 0x01; ++ BOOTRAM[1091] = 0xF3; ++ BOOTRAM[1092] = 0x22; ++ BOOTRAM[1093] = 0xEF; ++ BOOTRAM[1094] = 0x8D; ++ BOOTRAM[1095] = 0xF0; ++ BOOTRAM[1096] = 0xA4; ++ BOOTRAM[1097] = 0xA8; ++ BOOTRAM[1098] = 0xF0; ++ BOOTRAM[1099] = 0xCF; ++ BOOTRAM[1100] = 0x8C; ++ BOOTRAM[1101] = 0xF0; ++ BOOTRAM[1102] = 0xA4; ++ BOOTRAM[1103] = 0x28; ++ BOOTRAM[1104] = 0xCE; ++ BOOTRAM[1105] = 0x8D; ++ BOOTRAM[1106] = 0xF0; ++ BOOTRAM[1107] = 0xA4; ++ BOOTRAM[1108] = 0x2E; ++ BOOTRAM[1109] = 0xFE; ++ BOOTRAM[1110] = 0x22; ++ BOOTRAM[1111] = 0xBB; ++ BOOTRAM[1112] = 0x01; ++ BOOTRAM[1113] = 0x0A; ++ BOOTRAM[1114] = 0x89; ++ BOOTRAM[1115] = 0x82; ++ BOOTRAM[1116] = 0x8A; ++ BOOTRAM[1117] = 0x83; ++ BOOTRAM[1118] = 0xF0; ++ BOOTRAM[1119] = 0xE5; ++ BOOTRAM[1120] = 0xF0; ++ BOOTRAM[1121] = 0xA3; ++ BOOTRAM[1122] = 0xF0; ++ BOOTRAM[1123] = 0x22; ++ BOOTRAM[1124] = 0x50; ++ BOOTRAM[1125] = 0x06; ++ BOOTRAM[1126] = 0xF7; ++ BOOTRAM[1127] = 0x09; ++ BOOTRAM[1128] = 0xA7; ++ BOOTRAM[1129] = 0xF0; ++ BOOTRAM[1130] = 0x19; ++ BOOTRAM[1131] = 0x22; ++ BOOTRAM[1132] = 0xBB; ++ BOOTRAM[1133] = 0xFE; ++ BOOTRAM[1134] = 0x06; ++ BOOTRAM[1135] = 0xF3; ++ BOOTRAM[1136] = 0xE5; ++ BOOTRAM[1137] = 0xF0; ++ BOOTRAM[1138] = 0x09; ++ BOOTRAM[1139] = 0xF3; ++ BOOTRAM[1140] = 0x19; ++ BOOTRAM[1141] = 0x22; ++ BOOTRAM[1142] = 0x90; ++ BOOTRAM[1143] = 0x19; ++ BOOTRAM[1144] = 0x06; ++ BOOTRAM[1145] = 0xE0; ++ BOOTRAM[1146] = 0xA3; ++ BOOTRAM[1147] = 0xF0; ++ BOOTRAM[1148] = 0x7D; ++ BOOTRAM[1149] = 0x01; ++ BOOTRAM[1150] = 0x7F; ++ BOOTRAM[1151] = 0x02; ++ BOOTRAM[1152] = 0x12; ++ BOOTRAM[1153] = 0x0C; ++ BOOTRAM[1154] = 0x76; ++ BOOTRAM[1155] = 0x7F; ++ BOOTRAM[1156] = 0x03; ++ BOOTRAM[1157] = 0x12; ++ BOOTRAM[1158] = 0x0C; ++ BOOTRAM[1159] = 0x76; ++ BOOTRAM[1160] = 0x7F; ++ BOOTRAM[1161] = 0x04; ++ BOOTRAM[1162] = 0x12; ++ BOOTRAM[1163] = 0x0C; ++ BOOTRAM[1164] = 0x76; ++ BOOTRAM[1165] = 0x7F; ++ BOOTRAM[1166] = 0x05; ++ BOOTRAM[1167] = 0x12; ++ BOOTRAM[1168] = 0x0C; ++ BOOTRAM[1169] = 0x76; ++ BOOTRAM[1170] = 0x1D; ++ BOOTRAM[1171] = 0x7F; ++ BOOTRAM[1172] = 0x07; ++ BOOTRAM[1173] = 0x12; ++ BOOTRAM[1174] = 0x0C; ++ BOOTRAM[1175] = 0x76; ++ BOOTRAM[1176] = 0x0D; ++ BOOTRAM[1177] = 0x7F; ++ BOOTRAM[1178] = 0x02; ++ BOOTRAM[1179] = 0x12; ++ BOOTRAM[1180] = 0x0C; ++ BOOTRAM[1181] = 0xA2; ++ BOOTRAM[1182] = 0x90; ++ BOOTRAM[1183] = 0x81; ++ BOOTRAM[1184] = 0x97; ++ BOOTRAM[1185] = 0xE0; ++ BOOTRAM[1186] = 0xFF; ++ BOOTRAM[1187] = 0x64; ++ BOOTRAM[1188] = 0x10; ++ BOOTRAM[1189] = 0x60; ++ BOOTRAM[1190] = 0x05; ++ BOOTRAM[1191] = 0xEF; ++ BOOTRAM[1192] = 0x64; ++ BOOTRAM[1193] = 0x12; ++ BOOTRAM[1194] = 0x70; ++ BOOTRAM[1195] = 0x29; ++ BOOTRAM[1196] = 0xE4; ++ BOOTRAM[1197] = 0x12; ++ BOOTRAM[1198] = 0x0A; ++ BOOTRAM[1199] = 0x99; ++ BOOTRAM[1200] = 0x90; ++ BOOTRAM[1201] = 0x81; ++ BOOTRAM[1202] = 0x96; ++ BOOTRAM[1203] = 0xE0; ++ BOOTRAM[1204] = 0xFD; ++ BOOTRAM[1205] = 0x7F; ++ BOOTRAM[1206] = 0x02; ++ BOOTRAM[1207] = 0x12; ++ BOOTRAM[1208] = 0x0A; ++ BOOTRAM[1209] = 0x44; ++ BOOTRAM[1210] = 0x7D; ++ BOOTRAM[1211] = 0x01; ++ BOOTRAM[1212] = 0x12; ++ BOOTRAM[1213] = 0x0A; ++ BOOTRAM[1214] = 0x3B; ++ BOOTRAM[1215] = 0x90; ++ BOOTRAM[1216] = 0x19; ++ BOOTRAM[1217] = 0x07; ++ BOOTRAM[1218] = 0x74; ++ BOOTRAM[1219] = 0xFF; ++ BOOTRAM[1220] = 0xF0; ++ BOOTRAM[1221] = 0x7D; ++ BOOTRAM[1222] = 0x01; ++ BOOTRAM[1223] = 0x7F; ++ BOOTRAM[1224] = 0x02; ++ BOOTRAM[1225] = 0x12; ++ BOOTRAM[1226] = 0x0C; ++ BOOTRAM[1227] = 0xFA; ++ BOOTRAM[1228] = 0x1D; ++ BOOTRAM[1229] = 0x7F; ++ BOOTRAM[1230] = 0x04; ++ BOOTRAM[1231] = 0x12; ++ BOOTRAM[1232] = 0x0C; ++ BOOTRAM[1233] = 0xFA; ++ BOOTRAM[1234] = 0x0D; ++ BOOTRAM[1235] = 0x80; ++ BOOTRAM[1236] = 0x2C; ++ BOOTRAM[1237] = 0x90; ++ BOOTRAM[1238] = 0x81; ++ BOOTRAM[1239] = 0x97; ++ BOOTRAM[1240] = 0xE0; ++ BOOTRAM[1241] = 0x64; ++ BOOTRAM[1242] = 0x11; ++ BOOTRAM[1243] = 0x70; ++ BOOTRAM[1244] = 0x2B; ++ BOOTRAM[1245] = 0x12; ++ BOOTRAM[1246] = 0x0A; ++ BOOTRAM[1247] = 0x99; ++ BOOTRAM[1248] = 0x0D; ++ BOOTRAM[1249] = 0x7F; ++ BOOTRAM[1250] = 0x02; ++ BOOTRAM[1251] = 0x12; ++ BOOTRAM[1252] = 0x0A; ++ BOOTRAM[1253] = 0x44; ++ BOOTRAM[1254] = 0x90; ++ BOOTRAM[1255] = 0x81; ++ BOOTRAM[1256] = 0x96; ++ BOOTRAM[1257] = 0xE0; ++ BOOTRAM[1258] = 0xFD; ++ BOOTRAM[1259] = 0x12; ++ BOOTRAM[1260] = 0x0A; ++ BOOTRAM[1261] = 0x3B; ++ BOOTRAM[1262] = 0x90; ++ BOOTRAM[1263] = 0x19; ++ BOOTRAM[1264] = 0x07; ++ BOOTRAM[1265] = 0x74; ++ BOOTRAM[1266] = 0xFF; ++ BOOTRAM[1267] = 0xF0; ++ BOOTRAM[1268] = 0xE4; ++ BOOTRAM[1269] = 0xFD; ++ BOOTRAM[1270] = 0x7F; ++ BOOTRAM[1271] = 0x02; ++ BOOTRAM[1272] = 0x12; ++ BOOTRAM[1273] = 0x0C; ++ BOOTRAM[1274] = 0xFA; ++ BOOTRAM[1275] = 0x0D; ++ BOOTRAM[1276] = 0x7F; ++ BOOTRAM[1277] = 0x04; ++ BOOTRAM[1278] = 0x12; ++ BOOTRAM[1279] = 0x0C; ++ BOOTRAM[1280] = 0xFA; ++ BOOTRAM[1281] = 0x7F; ++ BOOTRAM[1282] = 0x05; ++ BOOTRAM[1283] = 0x12; ++ BOOTRAM[1284] = 0x0C; ++ BOOTRAM[1285] = 0xFA; ++ BOOTRAM[1286] = 0x80; ++ BOOTRAM[1287] = 0x19; ++ BOOTRAM[1288] = 0x7D; ++ BOOTRAM[1289] = 0x01; ++ BOOTRAM[1290] = 0x7F; ++ BOOTRAM[1291] = 0x03; ++ BOOTRAM[1292] = 0x12; ++ BOOTRAM[1293] = 0x0C; ++ BOOTRAM[1294] = 0xA2; ++ BOOTRAM[1295] = 0x1D; ++ BOOTRAM[1296] = 0x7F; ++ BOOTRAM[1297] = 0x04; ++ BOOTRAM[1298] = 0x12; ++ BOOTRAM[1299] = 0x0C; ++ BOOTRAM[1300] = 0xA2; ++ BOOTRAM[1301] = 0x0D; ++ BOOTRAM[1302] = 0x7F; ++ BOOTRAM[1303] = 0x05; ++ BOOTRAM[1304] = 0x12; ++ BOOTRAM[1305] = 0x0C; ++ BOOTRAM[1306] = 0xA2; ++ BOOTRAM[1307] = 0x1D; ++ BOOTRAM[1308] = 0x7F; ++ BOOTRAM[1309] = 0x04; ++ BOOTRAM[1310] = 0x12; ++ BOOTRAM[1311] = 0x0D; ++ BOOTRAM[1312] = 0x52; ++ BOOTRAM[1313] = 0x90; ++ BOOTRAM[1314] = 0x81; ++ BOOTRAM[1315] = 0x97; ++ BOOTRAM[1316] = 0xE0; ++ BOOTRAM[1317] = 0xFF; ++ BOOTRAM[1318] = 0x64; ++ BOOTRAM[1319] = 0x31; ++ BOOTRAM[1320] = 0x60; ++ BOOTRAM[1321] = 0x05; ++ BOOTRAM[1322] = 0xEF; ++ BOOTRAM[1323] = 0x64; ++ BOOTRAM[1324] = 0x30; ++ BOOTRAM[1325] = 0x70; ++ BOOTRAM[1326] = 0x39; ++ BOOTRAM[1327] = 0xE4; ++ BOOTRAM[1328] = 0xFD; ++ BOOTRAM[1329] = 0x7F; ++ BOOTRAM[1330] = 0x02; ++ BOOTRAM[1331] = 0x12; ++ BOOTRAM[1332] = 0x0A; ++ BOOTRAM[1333] = 0xC0; ++ BOOTRAM[1334] = 0x7D; ++ BOOTRAM[1335] = 0x02; ++ BOOTRAM[1336] = 0x7F; ++ BOOTRAM[1337] = 0x02; ++ BOOTRAM[1338] = 0x12; ++ BOOTRAM[1339] = 0x0A; ++ BOOTRAM[1340] = 0x44; ++ BOOTRAM[1341] = 0x7D; ++ BOOTRAM[1342] = 0x20; ++ BOOTRAM[1343] = 0x7F; ++ BOOTRAM[1344] = 0x02; ++ BOOTRAM[1345] = 0x12; ++ BOOTRAM[1346] = 0x0D; ++ BOOTRAM[1347] = 0xA6; ++ BOOTRAM[1348] = 0xE4; ++ BOOTRAM[1349] = 0xFD; ++ BOOTRAM[1350] = 0x0F; ++ BOOTRAM[1351] = 0x12; ++ BOOTRAM[1352] = 0x0A; ++ BOOTRAM[1353] = 0xC0; ++ BOOTRAM[1354] = 0x0D; ++ BOOTRAM[1355] = 0x7F; ++ BOOTRAM[1356] = 0x03; ++ BOOTRAM[1357] = 0x12; ++ BOOTRAM[1358] = 0x0A; ++ BOOTRAM[1359] = 0x44; ++ BOOTRAM[1360] = 0x7D; ++ BOOTRAM[1361] = 0x20; ++ BOOTRAM[1362] = 0x7F; ++ BOOTRAM[1363] = 0x03; ++ BOOTRAM[1364] = 0x12; ++ BOOTRAM[1365] = 0x0D; ++ BOOTRAM[1366] = 0xA6; ++ BOOTRAM[1367] = 0x90; ++ BOOTRAM[1368] = 0x19; ++ BOOTRAM[1369] = 0x07; ++ BOOTRAM[1370] = 0x74; ++ BOOTRAM[1371] = 0xFF; ++ BOOTRAM[1372] = 0xF0; ++ BOOTRAM[1373] = 0x7D; ++ BOOTRAM[1374] = 0x01; ++ BOOTRAM[1375] = 0x1F; ++ BOOTRAM[1376] = 0x12; ++ BOOTRAM[1377] = 0x0C; ++ BOOTRAM[1378] = 0xFA; ++ BOOTRAM[1379] = 0x7F; ++ BOOTRAM[1380] = 0x03; ++ BOOTRAM[1381] = 0x12; ++ BOOTRAM[1382] = 0x0C; ++ BOOTRAM[1383] = 0xFA; ++ BOOTRAM[1384] = 0x22; ++ BOOTRAM[1385] = 0xE4; ++ BOOTRAM[1386] = 0xFF; ++ BOOTRAM[1387] = 0xFE; ++ BOOTRAM[1388] = 0xF9; ++ BOOTRAM[1389] = 0x90; ++ BOOTRAM[1390] = 0x08; ++ BOOTRAM[1391] = 0x04; ++ BOOTRAM[1392] = 0xE0; ++ BOOTRAM[1393] = 0xFD; ++ BOOTRAM[1394] = 0x7C; ++ BOOTRAM[1395] = 0x00; ++ BOOTRAM[1396] = 0x90; ++ BOOTRAM[1397] = 0x08; ++ BOOTRAM[1398] = 0x03; ++ BOOTRAM[1399] = 0xE0; ++ BOOTRAM[1400] = 0xFB; ++ BOOTRAM[1401] = 0x7A; ++ BOOTRAM[1402] = 0x00; ++ BOOTRAM[1403] = 0x20; ++ BOOTRAM[1404] = 0xE7; ++ BOOTRAM[1405] = 0x03; ++ BOOTRAM[1406] = 0x02; ++ BOOTRAM[1407] = 0x06; ++ BOOTRAM[1408] = 0x2D; ++ BOOTRAM[1409] = 0x54; ++ BOOTRAM[1410] = 0x3F; ++ BOOTRAM[1411] = 0x78; ++ BOOTRAM[1412] = 0x02; ++ BOOTRAM[1413] = 0xC3; ++ BOOTRAM[1414] = 0x33; ++ BOOTRAM[1415] = 0xCE; ++ BOOTRAM[1416] = 0x33; ++ BOOTRAM[1417] = 0xCE; ++ BOOTRAM[1418] = 0xD8; ++ BOOTRAM[1419] = 0xF9; ++ BOOTRAM[1420] = 0xFF; ++ BOOTRAM[1421] = 0xED; ++ BOOTRAM[1422] = 0x54; ++ BOOTRAM[1423] = 0x03; ++ BOOTRAM[1424] = 0xFD; ++ BOOTRAM[1425] = 0xEF; ++ BOOTRAM[1426] = 0x4D; ++ BOOTRAM[1427] = 0xFF; ++ BOOTRAM[1428] = 0xC3; ++ BOOTRAM[1429] = 0x94; ++ BOOTRAM[1430] = 0xFC; ++ BOOTRAM[1431] = 0xEE; ++ BOOTRAM[1432] = 0x94; ++ BOOTRAM[1433] = 0x00; ++ BOOTRAM[1434] = 0x50; ++ BOOTRAM[1435] = 0x39; ++ BOOTRAM[1436] = 0x90; ++ BOOTRAM[1437] = 0x08; ++ BOOTRAM[1438] = 0x00; ++ BOOTRAM[1439] = 0x74; ++ BOOTRAM[1440] = 0x03; ++ BOOTRAM[1441] = 0xF0; ++ BOOTRAM[1442] = 0x12; ++ BOOTRAM[1443] = 0x0E; ++ BOOTRAM[1444] = 0xDA; ++ BOOTRAM[1445] = 0xAC; ++ BOOTRAM[1446] = 0x06; ++ BOOTRAM[1447] = 0xAD; ++ BOOTRAM[1448] = 0x07; ++ BOOTRAM[1449] = 0x90; ++ BOOTRAM[1450] = 0x81; ++ BOOTRAM[1451] = 0x4F; ++ BOOTRAM[1452] = 0xE0; ++ BOOTRAM[1453] = 0x25; ++ BOOTRAM[1454] = 0xE0; ++ BOOTRAM[1455] = 0xFF; ++ BOOTRAM[1456] = 0x90; ++ BOOTRAM[1457] = 0x81; ++ BOOTRAM[1458] = 0x4E; ++ BOOTRAM[1459] = 0xE0; ++ BOOTRAM[1460] = 0x33; ++ BOOTRAM[1461] = 0xFE; ++ BOOTRAM[1462] = 0x74; ++ BOOTRAM[1463] = 0x00; ++ BOOTRAM[1464] = 0x2F; ++ BOOTRAM[1465] = 0xF5; ++ BOOTRAM[1466] = 0x82; ++ BOOTRAM[1467] = 0x74; ++ BOOTRAM[1468] = 0x81; ++ BOOTRAM[1469] = 0x3E; ++ BOOTRAM[1470] = 0xF5; ++ BOOTRAM[1471] = 0x83; ++ BOOTRAM[1472] = 0xEC; ++ BOOTRAM[1473] = 0xF0; ++ BOOTRAM[1474] = 0xA3; ++ BOOTRAM[1475] = 0xED; ++ BOOTRAM[1476] = 0xF0; ++ BOOTRAM[1477] = 0x90; ++ BOOTRAM[1478] = 0x81; ++ BOOTRAM[1479] = 0x4F; ++ BOOTRAM[1480] = 0xE0; ++ BOOTRAM[1481] = 0x04; ++ BOOTRAM[1482] = 0xF0; ++ BOOTRAM[1483] = 0x70; ++ BOOTRAM[1484] = 0x06; ++ BOOTRAM[1485] = 0x90; ++ BOOTRAM[1486] = 0x81; ++ BOOTRAM[1487] = 0x4E; ++ BOOTRAM[1488] = 0xE0; ++ BOOTRAM[1489] = 0x04; ++ BOOTRAM[1490] = 0xF0; ++ BOOTRAM[1491] = 0x80; ++ BOOTRAM[1492] = 0x45; ++ BOOTRAM[1493] = 0xC3; ++ BOOTRAM[1494] = 0xEF; ++ BOOTRAM[1495] = 0x94; ++ BOOTRAM[1496] = 0xFC; ++ BOOTRAM[1497] = 0xEE; ++ BOOTRAM[1498] = 0x94; ++ BOOTRAM[1499] = 0x00; ++ BOOTRAM[1500] = 0x40; ++ BOOTRAM[1501] = 0x3C; ++ BOOTRAM[1502] = 0xD3; ++ BOOTRAM[1503] = 0x90; ++ BOOTRAM[1504] = 0x81; ++ BOOTRAM[1505] = 0x4F; ++ BOOTRAM[1506] = 0xE0; ++ BOOTRAM[1507] = 0x94; ++ BOOTRAM[1508] = 0x00; ++ BOOTRAM[1509] = 0x90; ++ BOOTRAM[1510] = 0x81; ++ BOOTRAM[1511] = 0x4E; ++ BOOTRAM[1512] = 0xE0; ++ BOOTRAM[1513] = 0x94; ++ BOOTRAM[1514] = 0x00; ++ BOOTRAM[1515] = 0x40; ++ BOOTRAM[1516] = 0x2D; ++ BOOTRAM[1517] = 0x90; ++ BOOTRAM[1518] = 0x08; ++ BOOTRAM[1519] = 0x00; ++ BOOTRAM[1520] = 0x74; ++ BOOTRAM[1521] = 0x02; ++ BOOTRAM[1522] = 0xF0; ++ BOOTRAM[1523] = 0x7B; ++ BOOTRAM[1524] = 0x01; ++ BOOTRAM[1525] = 0x7A; ++ BOOTRAM[1526] = 0x81; ++ BOOTRAM[1527] = 0x79; ++ BOOTRAM[1528] = 0x7E; ++ BOOTRAM[1529] = 0x12; ++ BOOTRAM[1530] = 0x00; ++ BOOTRAM[1531] = 0x06; ++ BOOTRAM[1532] = 0xA9; ++ BOOTRAM[1533] = 0x07; ++ BOOTRAM[1534] = 0xE9; ++ BOOTRAM[1535] = 0x60; ++ BOOTRAM[1536] = 0x12; ++ BOOTRAM[1537] = 0x90; ++ BOOTRAM[1538] = 0x81; ++ BOOTRAM[1539] = 0x7E; ++ BOOTRAM[1540] = 0xE0; ++ BOOTRAM[1541] = 0xFE; ++ BOOTRAM[1542] = 0xA3; ++ BOOTRAM[1543] = 0xE0; ++ BOOTRAM[1544] = 0xFF; ++ BOOTRAM[1545] = 0xAD; ++ BOOTRAM[1546] = 0x01; ++ BOOTRAM[1547] = 0x12; ++ BOOTRAM[1548] = 0x0C; ++ BOOTRAM[1549] = 0x16; ++ BOOTRAM[1550] = 0x7E; ++ BOOTRAM[1551] = 0x00; ++ BOOTRAM[1552] = 0x12; ++ BOOTRAM[1553] = 0x0A; ++ BOOTRAM[1554] = 0xEC; ++ BOOTRAM[1555] = 0xE4; ++ BOOTRAM[1556] = 0x90; ++ BOOTRAM[1557] = 0x81; ++ BOOTRAM[1558] = 0x4E; ++ BOOTRAM[1559] = 0xF0; ++ BOOTRAM[1560] = 0xA3; ++ BOOTRAM[1561] = 0xF0; ++ BOOTRAM[1562] = 0xC3; ++ BOOTRAM[1563] = 0x90; ++ BOOTRAM[1564] = 0x81; ++ BOOTRAM[1565] = 0x4F; ++ BOOTRAM[1566] = 0xE0; ++ BOOTRAM[1567] = 0x94; ++ BOOTRAM[1568] = 0x27; ++ BOOTRAM[1569] = 0x90; ++ BOOTRAM[1570] = 0x81; ++ BOOTRAM[1571] = 0x4E; ++ BOOTRAM[1572] = 0xE0; ++ BOOTRAM[1573] = 0x94; ++ BOOTRAM[1574] = 0x00; ++ BOOTRAM[1575] = 0x40; ++ BOOTRAM[1576] = 0x04; ++ BOOTRAM[1577] = 0xE4; ++ BOOTRAM[1578] = 0xF0; ++ BOOTRAM[1579] = 0xA3; ++ BOOTRAM[1580] = 0xF0; ++ BOOTRAM[1581] = 0x22; ++ BOOTRAM[1582] = 0x90; ++ BOOTRAM[1583] = 0x81; ++ BOOTRAM[1584] = 0x82; ++ BOOTRAM[1585] = 0xEE; ++ BOOTRAM[1586] = 0xF0; ++ BOOTRAM[1587] = 0xA3; ++ BOOTRAM[1588] = 0xEF; ++ BOOTRAM[1589] = 0xF0; ++ BOOTRAM[1590] = 0xA3; ++ BOOTRAM[1591] = 0xEC; ++ BOOTRAM[1592] = 0xF0; ++ BOOTRAM[1593] = 0xA3; ++ BOOTRAM[1594] = 0xED; ++ BOOTRAM[1595] = 0xF0; ++ BOOTRAM[1596] = 0x90; ++ BOOTRAM[1597] = 0x81; ++ BOOTRAM[1598] = 0x91; ++ BOOTRAM[1599] = 0x74; ++ BOOTRAM[1600] = 0x01; ++ BOOTRAM[1601] = 0xF0; ++ BOOTRAM[1602] = 0xA3; ++ BOOTRAM[1603] = 0x74; ++ BOOTRAM[1604] = 0x81; ++ BOOTRAM[1605] = 0xF0; ++ BOOTRAM[1606] = 0xA3; ++ BOOTRAM[1607] = 0x74; ++ BOOTRAM[1608] = 0x88; ++ BOOTRAM[1609] = 0xF0; ++ BOOTRAM[1610] = 0x7B; ++ BOOTRAM[1611] = 0x01; ++ BOOTRAM[1612] = 0x7A; ++ BOOTRAM[1613] = 0x81; ++ BOOTRAM[1614] = 0x79; ++ BOOTRAM[1615] = 0x86; ++ BOOTRAM[1616] = 0x12; ++ BOOTRAM[1617] = 0x0D; ++ BOOTRAM[1618] = 0x7D; ++ BOOTRAM[1619] = 0x90; ++ BOOTRAM[1620] = 0x81; ++ BOOTRAM[1621] = 0x91; ++ BOOTRAM[1622] = 0x74; ++ BOOTRAM[1623] = 0x01; ++ BOOTRAM[1624] = 0xF0; ++ BOOTRAM[1625] = 0xA3; ++ BOOTRAM[1626] = 0x74; ++ BOOTRAM[1627] = 0x81; ++ BOOTRAM[1628] = 0xF0; ++ BOOTRAM[1629] = 0xA3; ++ BOOTRAM[1630] = 0x74; ++ BOOTRAM[1631] = 0x8C; ++ BOOTRAM[1632] = 0xF0; ++ BOOTRAM[1633] = 0x7B; ++ BOOTRAM[1634] = 0x01; ++ BOOTRAM[1635] = 0x7A; ++ BOOTRAM[1636] = 0x81; ++ BOOTRAM[1637] = 0x79; ++ BOOTRAM[1638] = 0x8A; ++ BOOTRAM[1639] = 0x12; ++ BOOTRAM[1640] = 0x0D; ++ BOOTRAM[1641] = 0x7D; ++ BOOTRAM[1642] = 0x90; ++ BOOTRAM[1643] = 0x81; ++ BOOTRAM[1644] = 0x88; ++ BOOTRAM[1645] = 0xE0; ++ BOOTRAM[1646] = 0xFE; ++ BOOTRAM[1647] = 0xA3; ++ BOOTRAM[1648] = 0xE0; ++ BOOTRAM[1649] = 0xFF; ++ BOOTRAM[1650] = 0xC3; ++ BOOTRAM[1651] = 0x90; ++ BOOTRAM[1652] = 0x81; ++ BOOTRAM[1653] = 0x8D; ++ BOOTRAM[1654] = 0xE0; ++ BOOTRAM[1655] = 0x9F; ++ BOOTRAM[1656] = 0xFF; ++ BOOTRAM[1657] = 0x90; ++ BOOTRAM[1658] = 0x81; ++ BOOTRAM[1659] = 0x8C; ++ BOOTRAM[1660] = 0xE0; ++ BOOTRAM[1661] = 0x9E; ++ BOOTRAM[1662] = 0xFE; ++ BOOTRAM[1663] = 0xD3; ++ BOOTRAM[1664] = 0x90; ++ BOOTRAM[1665] = 0x81; ++ BOOTRAM[1666] = 0x85; ++ BOOTRAM[1667] = 0xE0; ++ BOOTRAM[1668] = 0x9F; ++ BOOTRAM[1669] = 0x90; ++ BOOTRAM[1670] = 0x81; ++ BOOTRAM[1671] = 0x84; ++ BOOTRAM[1672] = 0xE0; ++ BOOTRAM[1673] = 0x9E; ++ BOOTRAM[1674] = 0x50; ++ BOOTRAM[1675] = 0xC7; ++ BOOTRAM[1676] = 0x90; ++ BOOTRAM[1677] = 0x81; ++ BOOTRAM[1678] = 0x86; ++ BOOTRAM[1679] = 0xE0; ++ BOOTRAM[1680] = 0xFE; ++ BOOTRAM[1681] = 0xA3; ++ BOOTRAM[1682] = 0xE0; ++ BOOTRAM[1683] = 0xFF; ++ BOOTRAM[1684] = 0x90; ++ BOOTRAM[1685] = 0x81; ++ BOOTRAM[1686] = 0x8A; ++ BOOTRAM[1687] = 0xE0; ++ BOOTRAM[1688] = 0xFC; ++ BOOTRAM[1689] = 0xA3; ++ BOOTRAM[1690] = 0xE0; ++ BOOTRAM[1691] = 0xFD; ++ BOOTRAM[1692] = 0xC3; ++ BOOTRAM[1693] = 0x9F; ++ BOOTRAM[1694] = 0xFF; ++ BOOTRAM[1695] = 0xEC; ++ BOOTRAM[1696] = 0x9E; ++ BOOTRAM[1697] = 0xFE; ++ BOOTRAM[1698] = 0xD3; ++ BOOTRAM[1699] = 0x90; ++ BOOTRAM[1700] = 0x81; ++ BOOTRAM[1701] = 0x83; ++ BOOTRAM[1702] = 0xE0; ++ BOOTRAM[1703] = 0x9F; ++ BOOTRAM[1704] = 0x90; ++ BOOTRAM[1705] = 0x81; ++ BOOTRAM[1706] = 0x82; ++ BOOTRAM[1707] = 0xE0; ++ BOOTRAM[1708] = 0x9E; ++ BOOTRAM[1709] = 0x40; ++ BOOTRAM[1710] = 0x3F; ++ BOOTRAM[1711] = 0x90; ++ BOOTRAM[1712] = 0x81; ++ BOOTRAM[1713] = 0x86; ++ BOOTRAM[1714] = 0xE0; ++ BOOTRAM[1715] = 0xFE; ++ BOOTRAM[1716] = 0xA3; ++ BOOTRAM[1717] = 0xE0; ++ BOOTRAM[1718] = 0xFF; ++ BOOTRAM[1719] = 0xC3; ++ BOOTRAM[1720] = 0xED; ++ BOOTRAM[1721] = 0x9F; ++ BOOTRAM[1722] = 0xEC; ++ BOOTRAM[1723] = 0x9E; ++ BOOTRAM[1724] = 0x50; ++ BOOTRAM[1725] = 0x95; ++ BOOTRAM[1726] = 0x90; ++ BOOTRAM[1727] = 0x81; ++ BOOTRAM[1728] = 0x8A; ++ BOOTRAM[1729] = 0xE0; ++ BOOTRAM[1730] = 0xFE; ++ BOOTRAM[1731] = 0xA3; ++ BOOTRAM[1732] = 0xE0; ++ BOOTRAM[1733] = 0xFF; ++ BOOTRAM[1734] = 0xC3; ++ BOOTRAM[1735] = 0x90; ++ BOOTRAM[1736] = 0x81; ++ BOOTRAM[1737] = 0x87; ++ BOOTRAM[1738] = 0xE0; ++ BOOTRAM[1739] = 0x9F; ++ BOOTRAM[1740] = 0xFF; ++ BOOTRAM[1741] = 0x90; ++ BOOTRAM[1742] = 0x81; ++ BOOTRAM[1743] = 0x86; ++ BOOTRAM[1744] = 0xE0; ++ BOOTRAM[1745] = 0x9E; ++ BOOTRAM[1746] = 0xFE; ++ BOOTRAM[1747] = 0x90; ++ BOOTRAM[1748] = 0x81; ++ BOOTRAM[1749] = 0x82; ++ BOOTRAM[1750] = 0xE0; ++ BOOTRAM[1751] = 0xFC; ++ BOOTRAM[1752] = 0xA3; ++ BOOTRAM[1753] = 0xE0; ++ BOOTRAM[1754] = 0xFD; ++ BOOTRAM[1755] = 0xC3; ++ BOOTRAM[1756] = 0x74; ++ BOOTRAM[1757] = 0xFF; ++ BOOTRAM[1758] = 0x9D; ++ BOOTRAM[1759] = 0xFD; ++ BOOTRAM[1760] = 0x74; ++ BOOTRAM[1761] = 0xFF; ++ BOOTRAM[1762] = 0x9C; ++ BOOTRAM[1763] = 0xFC; ++ BOOTRAM[1764] = 0xC3; ++ BOOTRAM[1765] = 0xED; ++ BOOTRAM[1766] = 0x9F; ++ BOOTRAM[1767] = 0xEC; ++ BOOTRAM[1768] = 0x9E; ++ BOOTRAM[1769] = 0x50; ++ BOOTRAM[1770] = 0x03; ++ BOOTRAM[1771] = 0x02; ++ BOOTRAM[1772] = 0x06; ++ BOOTRAM[1773] = 0x53; ++ BOOTRAM[1774] = 0x22; ++ BOOTRAM[1775] = 0x90; ++ BOOTRAM[1776] = 0x19; ++ BOOTRAM[1777] = 0x06; ++ BOOTRAM[1778] = 0xE0; ++ BOOTRAM[1779] = 0x90; ++ BOOTRAM[1780] = 0x81; ++ BOOTRAM[1781] = 0x7E; ++ BOOTRAM[1782] = 0xF0; ++ BOOTRAM[1783] = 0xE0; ++ BOOTRAM[1784] = 0xFF; ++ BOOTRAM[1785] = 0x90; ++ BOOTRAM[1786] = 0x19; ++ BOOTRAM[1787] = 0x07; ++ BOOTRAM[1788] = 0xF0; ++ BOOTRAM[1789] = 0xEF; ++ BOOTRAM[1790] = 0x30; ++ BOOTRAM[1791] = 0xE2; ++ BOOTRAM[1792] = 0x41; ++ BOOTRAM[1793] = 0x90; ++ BOOTRAM[1794] = 0x81; ++ BOOTRAM[1795] = 0x97; ++ BOOTRAM[1796] = 0xE0; ++ BOOTRAM[1797] = 0xFF; ++ BOOTRAM[1798] = 0x64; ++ BOOTRAM[1799] = 0x10; ++ BOOTRAM[1800] = 0x60; ++ BOOTRAM[1801] = 0x0A; ++ BOOTRAM[1802] = 0xEF; ++ BOOTRAM[1803] = 0x64; ++ BOOTRAM[1804] = 0x11; ++ BOOTRAM[1805] = 0x60; ++ BOOTRAM[1806] = 0x05; ++ BOOTRAM[1807] = 0xEF; ++ BOOTRAM[1808] = 0x64; ++ BOOTRAM[1809] = 0x12; ++ BOOTRAM[1810] = 0x70; ++ BOOTRAM[1811] = 0x19; ++ BOOTRAM[1812] = 0xEF; ++ BOOTRAM[1813] = 0xB4; ++ BOOTRAM[1814] = 0x12; ++ BOOTRAM[1815] = 0x11; ++ BOOTRAM[1816] = 0x7F; ++ BOOTRAM[1817] = 0x04; ++ BOOTRAM[1818] = 0x12; ++ BOOTRAM[1819] = 0x0D; ++ BOOTRAM[1820] = 0x26; ++ BOOTRAM[1821] = 0x90; ++ BOOTRAM[1822] = 0x81; ++ BOOTRAM[1823] = 0x94; ++ BOOTRAM[1824] = 0xE0; ++ BOOTRAM[1825] = 0x6F; ++ BOOTRAM[1826] = 0x70; ++ BOOTRAM[1827] = 0x01; ++ BOOTRAM[1828] = 0xEE; ++ BOOTRAM[1829] = 0x70; ++ BOOTRAM[1830] = 0x1B; ++ BOOTRAM[1831] = 0x80; ++ BOOTRAM[1832] = 0x00; ++ BOOTRAM[1833] = 0x7F; ++ BOOTRAM[1834] = 0x02; ++ BOOTRAM[1835] = 0x80; ++ BOOTRAM[1836] = 0x12; ++ BOOTRAM[1837] = 0x90; ++ BOOTRAM[1838] = 0x81; ++ BOOTRAM[1839] = 0x97; ++ BOOTRAM[1840] = 0xE0; ++ BOOTRAM[1841] = 0xFF; ++ BOOTRAM[1842] = 0x64; ++ BOOTRAM[1843] = 0x31; ++ BOOTRAM[1844] = 0x60; ++ BOOTRAM[1845] = 0x04; ++ BOOTRAM[1846] = 0xEF; ++ BOOTRAM[1847] = 0xB4; ++ BOOTRAM[1848] = 0x30; ++ BOOTRAM[1849] = 0x08; ++ BOOTRAM[1850] = 0x7F; ++ BOOTRAM[1851] = 0x02; ++ BOOTRAM[1852] = 0x12; ++ BOOTRAM[1853] = 0x0D; ++ BOOTRAM[1854] = 0x26; ++ BOOTRAM[1855] = 0x12; ++ BOOTRAM[1856] = 0x0E; ++ BOOTRAM[1857] = 0x8B; ++ BOOTRAM[1858] = 0x90; ++ BOOTRAM[1859] = 0x81; ++ BOOTRAM[1860] = 0x7E; ++ BOOTRAM[1861] = 0xE0; ++ BOOTRAM[1862] = 0x30; ++ BOOTRAM[1863] = 0xE3; ++ BOOTRAM[1864] = 0x13; ++ BOOTRAM[1865] = 0x90; ++ BOOTRAM[1866] = 0x81; ++ BOOTRAM[1867] = 0x97; ++ BOOTRAM[1868] = 0xE0; ++ BOOTRAM[1869] = 0xFF; ++ BOOTRAM[1870] = 0x64; ++ BOOTRAM[1871] = 0x31; ++ BOOTRAM[1872] = 0x60; ++ BOOTRAM[1873] = 0x04; ++ BOOTRAM[1874] = 0xEF; ++ BOOTRAM[1875] = 0xB4; ++ BOOTRAM[1876] = 0x30; ++ BOOTRAM[1877] = 0x06; ++ BOOTRAM[1878] = 0x12; ++ BOOTRAM[1879] = 0x0E; ++ BOOTRAM[1880] = 0xCA; ++ BOOTRAM[1881] = 0x12; ++ BOOTRAM[1882] = 0x0E; ++ BOOTRAM[1883] = 0xD2; ++ BOOTRAM[1884] = 0x90; ++ BOOTRAM[1885] = 0x81; ++ BOOTRAM[1886] = 0x7E; ++ BOOTRAM[1887] = 0xE0; ++ BOOTRAM[1888] = 0x30; ++ BOOTRAM[1889] = 0xE4; ++ BOOTRAM[1890] = 0x17; ++ BOOTRAM[1891] = 0x90; ++ BOOTRAM[1892] = 0x81; ++ BOOTRAM[1893] = 0x97; ++ BOOTRAM[1894] = 0xE0; ++ BOOTRAM[1895] = 0xFF; ++ BOOTRAM[1896] = 0x64; ++ BOOTRAM[1897] = 0x10; ++ BOOTRAM[1898] = 0x60; ++ BOOTRAM[1899] = 0x09; ++ BOOTRAM[1900] = 0xEF; ++ BOOTRAM[1901] = 0x64; ++ BOOTRAM[1902] = 0x11; ++ BOOTRAM[1903] = 0x60; ++ BOOTRAM[1904] = 0x04; ++ BOOTRAM[1905] = 0xEF; ++ BOOTRAM[1906] = 0xB4; ++ BOOTRAM[1907] = 0x12; ++ BOOTRAM[1908] = 0x05; ++ BOOTRAM[1909] = 0x7F; ++ BOOTRAM[1910] = 0x04; ++ BOOTRAM[1911] = 0x12; ++ BOOTRAM[1912] = 0x0E; ++ BOOTRAM[1913] = 0x8B; ++ BOOTRAM[1914] = 0x90; ++ BOOTRAM[1915] = 0x81; ++ BOOTRAM[1916] = 0x7E; ++ BOOTRAM[1917] = 0xE0; ++ BOOTRAM[1918] = 0x30; ++ BOOTRAM[1919] = 0xE5; ++ BOOTRAM[1920] = 0x17; ++ BOOTRAM[1921] = 0x90; ++ BOOTRAM[1922] = 0x81; ++ BOOTRAM[1923] = 0x97; ++ BOOTRAM[1924] = 0xE0; ++ BOOTRAM[1925] = 0xFF; ++ BOOTRAM[1926] = 0x64; ++ BOOTRAM[1927] = 0x10; ++ BOOTRAM[1928] = 0x60; ++ BOOTRAM[1929] = 0x09; ++ BOOTRAM[1930] = 0xEF; ++ BOOTRAM[1931] = 0x64; ++ BOOTRAM[1932] = 0x11; ++ BOOTRAM[1933] = 0x60; ++ BOOTRAM[1934] = 0x04; ++ BOOTRAM[1935] = 0xEF; ++ BOOTRAM[1936] = 0xB4; ++ BOOTRAM[1937] = 0x12; ++ BOOTRAM[1938] = 0x05; ++ BOOTRAM[1939] = 0x7F; ++ BOOTRAM[1940] = 0x05; ++ BOOTRAM[1941] = 0x12; ++ BOOTRAM[1942] = 0x0E; ++ BOOTRAM[1943] = 0x8B; ++ BOOTRAM[1944] = 0x22; ++ BOOTRAM[1945] = 0x90; ++ BOOTRAM[1946] = 0x81; ++ BOOTRAM[1947] = 0x68; ++ BOOTRAM[1948] = 0x74; ++ BOOTRAM[1949] = 0x01; ++ BOOTRAM[1950] = 0xF0; ++ BOOTRAM[1951] = 0xE4; ++ BOOTRAM[1952] = 0xA3; ++ BOOTRAM[1953] = 0xF0; ++ BOOTRAM[1954] = 0xA3; ++ BOOTRAM[1955] = 0xF0; ++ BOOTRAM[1956] = 0x90; ++ BOOTRAM[1957] = 0x37; ++ BOOTRAM[1958] = 0x00; ++ BOOTRAM[1959] = 0xF0; ++ BOOTRAM[1960] = 0x12; ++ BOOTRAM[1961] = 0x0E; ++ BOOTRAM[1962] = 0xC2; ++ BOOTRAM[1963] = 0x90; ++ BOOTRAM[1964] = 0x28; ++ BOOTRAM[1965] = 0x17; ++ BOOTRAM[1966] = 0xE0; ++ BOOTRAM[1967] = 0x90; ++ BOOTRAM[1968] = 0x81; ++ BOOTRAM[1969] = 0x97; ++ BOOTRAM[1970] = 0xF0; ++ BOOTRAM[1971] = 0xE0; ++ BOOTRAM[1972] = 0xFF; ++ BOOTRAM[1973] = 0x64; ++ BOOTRAM[1974] = 0x10; ++ BOOTRAM[1975] = 0x60; ++ BOOTRAM[1976] = 0x1C; ++ BOOTRAM[1977] = 0xEF; ++ BOOTRAM[1978] = 0x64; ++ BOOTRAM[1979] = 0x11; ++ BOOTRAM[1980] = 0x60; ++ BOOTRAM[1981] = 0x17; ++ BOOTRAM[1982] = 0xEF; ++ BOOTRAM[1983] = 0x64; ++ BOOTRAM[1984] = 0x12; ++ BOOTRAM[1985] = 0x60; ++ BOOTRAM[1986] = 0x12; ++ BOOTRAM[1987] = 0xEF; ++ BOOTRAM[1988] = 0x64; ++ BOOTRAM[1989] = 0x20; ++ BOOTRAM[1990] = 0x60; ++ BOOTRAM[1991] = 0x0D; ++ BOOTRAM[1992] = 0xEF; ++ BOOTRAM[1993] = 0x64; ++ BOOTRAM[1994] = 0x31; ++ BOOTRAM[1995] = 0x60; ++ BOOTRAM[1996] = 0x08; ++ BOOTRAM[1997] = 0xEF; ++ BOOTRAM[1998] = 0x64; ++ BOOTRAM[1999] = 0x30; ++ BOOTRAM[2000] = 0x60; ++ BOOTRAM[2001] = 0x03; ++ BOOTRAM[2002] = 0x74; ++ BOOTRAM[2003] = 0x20; ++ BOOTRAM[2004] = 0xF0; ++ BOOTRAM[2005] = 0x90; ++ BOOTRAM[2006] = 0x81; ++ BOOTRAM[2007] = 0x97; ++ BOOTRAM[2008] = 0xE0; ++ BOOTRAM[2009] = 0xFF; ++ BOOTRAM[2010] = 0x64; ++ BOOTRAM[2011] = 0x10; ++ BOOTRAM[2012] = 0x60; ++ BOOTRAM[2013] = 0x0A; ++ BOOTRAM[2014] = 0xEF; ++ BOOTRAM[2015] = 0x64; ++ BOOTRAM[2016] = 0x11; ++ BOOTRAM[2017] = 0x60; ++ BOOTRAM[2018] = 0x05; ++ BOOTRAM[2019] = 0xEF; ++ BOOTRAM[2020] = 0x64; ++ BOOTRAM[2021] = 0x12; ++ BOOTRAM[2022] = 0x70; ++ BOOTRAM[2023] = 0x2B; ++ BOOTRAM[2024] = 0x90; ++ BOOTRAM[2025] = 0x28; ++ BOOTRAM[2026] = 0x18; ++ BOOTRAM[2027] = 0xE0; ++ BOOTRAM[2028] = 0x90; ++ BOOTRAM[2029] = 0x81; ++ BOOTRAM[2030] = 0x96; ++ BOOTRAM[2031] = 0xF0; ++ BOOTRAM[2032] = 0xE0; ++ BOOTRAM[2033] = 0xFF; ++ BOOTRAM[2034] = 0x64; ++ BOOTRAM[2035] = 0x01; ++ BOOTRAM[2036] = 0x60; ++ BOOTRAM[2037] = 0x0A; ++ BOOTRAM[2038] = 0xEF; ++ BOOTRAM[2039] = 0x60; ++ BOOTRAM[2040] = 0x07; ++ BOOTRAM[2041] = 0x64; ++ BOOTRAM[2042] = 0x02; ++ BOOTRAM[2043] = 0x60; ++ BOOTRAM[2044] = 0x03; ++ BOOTRAM[2045] = 0x74; ++ BOOTRAM[2046] = 0x01; ++ BOOTRAM[2047] = 0xF0; ++ BOOTRAM[2048] = 0x90; ++ BOOTRAM[2049] = 0x28; ++ BOOTRAM[2050] = 0x19; ++ BOOTRAM[2051] = 0xE0; ++ BOOTRAM[2052] = 0x90; ++ BOOTRAM[2053] = 0x81; ++ BOOTRAM[2054] = 0x94; ++ BOOTRAM[2055] = 0xF0; ++ BOOTRAM[2056] = 0xE0; ++ BOOTRAM[2057] = 0xFF; ++ BOOTRAM[2058] = 0x60; ++ BOOTRAM[2059] = 0x07; ++ BOOTRAM[2060] = 0x64; ++ BOOTRAM[2061] = 0x01; ++ BOOTRAM[2062] = 0x60; ++ BOOTRAM[2063] = 0x03; ++ BOOTRAM[2064] = 0x74; ++ BOOTRAM[2065] = 0x01; ++ BOOTRAM[2066] = 0xF0; ++ BOOTRAM[2067] = 0xD2; ++ BOOTRAM[2068] = 0xAF; ++ BOOTRAM[2069] = 0xD2; ++ BOOTRAM[2070] = 0xA8; ++ BOOTRAM[2071] = 0xC2; ++ BOOTRAM[2072] = 0x88; ++ BOOTRAM[2073] = 0x12; ++ BOOTRAM[2074] = 0x0E; ++ BOOTRAM[2075] = 0x29; ++ BOOTRAM[2076] = 0x12; ++ BOOTRAM[2077] = 0x0E; ++ BOOTRAM[2078] = 0x5A; ++ BOOTRAM[2079] = 0x12; ++ BOOTRAM[2080] = 0x0E; ++ BOOTRAM[2081] = 0x3A; ++ BOOTRAM[2082] = 0x90; ++ BOOTRAM[2083] = 0x81; ++ BOOTRAM[2084] = 0x97; ++ BOOTRAM[2085] = 0xE0; ++ BOOTRAM[2086] = 0x64; ++ BOOTRAM[2087] = 0x31; ++ BOOTRAM[2088] = 0x60; ++ BOOTRAM[2089] = 0x03; ++ BOOTRAM[2090] = 0x12; ++ BOOTRAM[2091] = 0x0B; ++ BOOTRAM[2092] = 0x8C; ++ BOOTRAM[2093] = 0x90; ++ BOOTRAM[2094] = 0x37; ++ BOOTRAM[2095] = 0x00; ++ BOOTRAM[2096] = 0x74; ++ BOOTRAM[2097] = 0x0B; ++ BOOTRAM[2098] = 0xF0; ++ BOOTRAM[2099] = 0x7D; ++ BOOTRAM[2100] = 0x07; ++ BOOTRAM[2101] = 0x7C; ++ BOOTRAM[2102] = 0x00; ++ BOOTRAM[2103] = 0x7F; ++ BOOTRAM[2104] = 0x20; ++ BOOTRAM[2105] = 0x7E; ++ BOOTRAM[2106] = 0xA1; ++ BOOTRAM[2107] = 0x12; ++ BOOTRAM[2108] = 0x06; ++ BOOTRAM[2109] = 0x2E; ++ BOOTRAM[2110] = 0x80; ++ BOOTRAM[2111] = 0xF3; ++ BOOTRAM[2112] = 0x78; ++ BOOTRAM[2113] = 0x7F; ++ BOOTRAM[2114] = 0xE4; ++ BOOTRAM[2115] = 0xF6; ++ BOOTRAM[2116] = 0xD8; ++ BOOTRAM[2117] = 0xFD; ++ BOOTRAM[2118] = 0x75; ++ BOOTRAM[2119] = 0x81; ++ BOOTRAM[2120] = 0x07; ++ BOOTRAM[2121] = 0x02; ++ BOOTRAM[2122] = 0x08; ++ BOOTRAM[2123] = 0x87; ++ BOOTRAM[2124] = 0x02; ++ BOOTRAM[2125] = 0x07; ++ BOOTRAM[2126] = 0x99; ++ BOOTRAM[2127] = 0xE4; ++ BOOTRAM[2128] = 0x93; ++ BOOTRAM[2129] = 0xA3; ++ BOOTRAM[2130] = 0xF8; ++ BOOTRAM[2131] = 0xE4; ++ BOOTRAM[2132] = 0x93; ++ BOOTRAM[2133] = 0xA3; ++ BOOTRAM[2134] = 0x40; ++ BOOTRAM[2135] = 0x03; ++ BOOTRAM[2136] = 0xF6; ++ BOOTRAM[2137] = 0x80; ++ BOOTRAM[2138] = 0x01; ++ BOOTRAM[2139] = 0xF2; ++ BOOTRAM[2140] = 0x08; ++ BOOTRAM[2141] = 0xDF; ++ BOOTRAM[2142] = 0xF4; ++ BOOTRAM[2143] = 0x80; ++ BOOTRAM[2144] = 0x29; ++ BOOTRAM[2145] = 0xE4; ++ BOOTRAM[2146] = 0x93; ++ BOOTRAM[2147] = 0xA3; ++ BOOTRAM[2148] = 0xF8; ++ BOOTRAM[2149] = 0x54; ++ BOOTRAM[2150] = 0x07; ++ BOOTRAM[2151] = 0x24; ++ BOOTRAM[2152] = 0x0C; ++ BOOTRAM[2153] = 0xC8; ++ BOOTRAM[2154] = 0xC3; ++ BOOTRAM[2155] = 0x33; ++ BOOTRAM[2156] = 0xC4; ++ BOOTRAM[2157] = 0x54; ++ BOOTRAM[2158] = 0x0F; ++ BOOTRAM[2159] = 0x44; ++ BOOTRAM[2160] = 0x20; ++ BOOTRAM[2161] = 0xC8; ++ BOOTRAM[2162] = 0x83; ++ BOOTRAM[2163] = 0x40; ++ BOOTRAM[2164] = 0x04; ++ BOOTRAM[2165] = 0xF4; ++ BOOTRAM[2166] = 0x56; ++ BOOTRAM[2167] = 0x80; ++ BOOTRAM[2168] = 0x01; ++ BOOTRAM[2169] = 0x46; ++ BOOTRAM[2170] = 0xF6; ++ BOOTRAM[2171] = 0xDF; ++ BOOTRAM[2172] = 0xE4; ++ BOOTRAM[2173] = 0x80; ++ BOOTRAM[2174] = 0x0B; ++ BOOTRAM[2175] = 0x01; ++ BOOTRAM[2176] = 0x02; ++ BOOTRAM[2177] = 0x04; ++ BOOTRAM[2178] = 0x08; ++ BOOTRAM[2179] = 0x10; ++ BOOTRAM[2180] = 0x20; ++ BOOTRAM[2181] = 0x40; ++ BOOTRAM[2182] = 0x80; ++ BOOTRAM[2183] = 0x90; ++ BOOTRAM[2184] = 0x08; ++ BOOTRAM[2185] = 0xCC; ++ BOOTRAM[2186] = 0xE4; ++ BOOTRAM[2187] = 0x7E; ++ BOOTRAM[2188] = 0x01; ++ BOOTRAM[2189] = 0x93; ++ BOOTRAM[2190] = 0x60; ++ BOOTRAM[2191] = 0xBC; ++ BOOTRAM[2192] = 0xA3; ++ BOOTRAM[2193] = 0xFF; ++ BOOTRAM[2194] = 0x54; ++ BOOTRAM[2195] = 0x3F; ++ BOOTRAM[2196] = 0x30; ++ BOOTRAM[2197] = 0xE5; ++ BOOTRAM[2198] = 0x09; ++ BOOTRAM[2199] = 0x54; ++ BOOTRAM[2200] = 0x1F; ++ BOOTRAM[2201] = 0xFE; ++ BOOTRAM[2202] = 0xE4; ++ BOOTRAM[2203] = 0x93; ++ BOOTRAM[2204] = 0xA3; ++ BOOTRAM[2205] = 0x60; ++ BOOTRAM[2206] = 0x01; ++ BOOTRAM[2207] = 0x0E; ++ BOOTRAM[2208] = 0xCF; ++ BOOTRAM[2209] = 0x54; ++ BOOTRAM[2210] = 0xC0; ++ BOOTRAM[2211] = 0x25; ++ BOOTRAM[2212] = 0xE0; ++ BOOTRAM[2213] = 0x60; ++ BOOTRAM[2214] = 0xA8; ++ BOOTRAM[2215] = 0x40; ++ BOOTRAM[2216] = 0xB8; ++ BOOTRAM[2217] = 0xE4; ++ BOOTRAM[2218] = 0x93; ++ BOOTRAM[2219] = 0xA3; ++ BOOTRAM[2220] = 0xFA; ++ BOOTRAM[2221] = 0xE4; ++ BOOTRAM[2222] = 0x93; ++ BOOTRAM[2223] = 0xA3; ++ BOOTRAM[2224] = 0xF8; ++ BOOTRAM[2225] = 0xE4; ++ BOOTRAM[2226] = 0x93; ++ BOOTRAM[2227] = 0xA3; ++ BOOTRAM[2228] = 0xC8; ++ BOOTRAM[2229] = 0xC5; ++ BOOTRAM[2230] = 0x82; ++ BOOTRAM[2231] = 0xC8; ++ BOOTRAM[2232] = 0xCA; ++ BOOTRAM[2233] = 0xC5; ++ BOOTRAM[2234] = 0x83; ++ BOOTRAM[2235] = 0xCA; ++ BOOTRAM[2236] = 0xF0; ++ BOOTRAM[2237] = 0xA3; ++ BOOTRAM[2238] = 0xC8; ++ BOOTRAM[2239] = 0xC5; ++ BOOTRAM[2240] = 0x82; ++ BOOTRAM[2241] = 0xC8; ++ BOOTRAM[2242] = 0xCA; ++ BOOTRAM[2243] = 0xC5; ++ BOOTRAM[2244] = 0x83; ++ BOOTRAM[2245] = 0xCA; ++ BOOTRAM[2246] = 0xDF; ++ BOOTRAM[2247] = 0xE9; ++ BOOTRAM[2248] = 0xDE; ++ BOOTRAM[2249] = 0xE7; ++ BOOTRAM[2250] = 0x80; ++ BOOTRAM[2251] = 0xBE; ++ BOOTRAM[2252] = 0x41; ++ BOOTRAM[2253] = 0x81; ++ BOOTRAM[2254] = 0x97; ++ BOOTRAM[2255] = 0x00; ++ BOOTRAM[2256] = 0x41; ++ BOOTRAM[2257] = 0x81; ++ BOOTRAM[2258] = 0x96; ++ BOOTRAM[2259] = 0x00; ++ BOOTRAM[2260] = 0x41; ++ BOOTRAM[2261] = 0x81; ++ BOOTRAM[2262] = 0x94; ++ BOOTRAM[2263] = 0x00; ++ BOOTRAM[2264] = 0x41; ++ BOOTRAM[2265] = 0x81; ++ BOOTRAM[2266] = 0x95; ++ BOOTRAM[2267] = 0x01; ++ BOOTRAM[2268] = 0x42; ++ BOOTRAM[2269] = 0x81; ++ BOOTRAM[2270] = 0x98; ++ BOOTRAM[2271] = 0x00; ++ BOOTRAM[2272] = 0x00; ++ BOOTRAM[2273] = 0x60; ++ BOOTRAM[2274] = 0x4E; ++ BOOTRAM[2275] = 0x81; ++ BOOTRAM[2276] = 0x00; ++ BOOTRAM[2277] = 0x00; ++ BOOTRAM[2278] = 0x00; ++ BOOTRAM[2279] = 0x00; ++ BOOTRAM[2280] = 0x00; ++ BOOTRAM[2281] = 0x00; ++ BOOTRAM[2282] = 0x00; ++ BOOTRAM[2283] = 0x00; ++ BOOTRAM[2284] = 0x00; ++ BOOTRAM[2285] = 0x00; ++ BOOTRAM[2286] = 0x00; ++ BOOTRAM[2287] = 0x00; ++ BOOTRAM[2288] = 0x00; ++ BOOTRAM[2289] = 0x00; ++ BOOTRAM[2290] = 0x00; ++ BOOTRAM[2291] = 0x00; ++ BOOTRAM[2292] = 0x00; ++ BOOTRAM[2293] = 0x00; ++ BOOTRAM[2294] = 0x00; ++ BOOTRAM[2295] = 0x00; ++ BOOTRAM[2296] = 0x00; ++ BOOTRAM[2297] = 0x00; ++ BOOTRAM[2298] = 0x00; ++ BOOTRAM[2299] = 0x00; ++ BOOTRAM[2300] = 0x00; ++ BOOTRAM[2301] = 0x00; ++ BOOTRAM[2302] = 0x00; ++ BOOTRAM[2303] = 0x00; ++ BOOTRAM[2304] = 0x00; ++ BOOTRAM[2305] = 0x00; ++ BOOTRAM[2306] = 0x00; ++ BOOTRAM[2307] = 0x00; ++ BOOTRAM[2308] = 0x00; ++ BOOTRAM[2309] = 0x00; ++ BOOTRAM[2310] = 0x00; ++ BOOTRAM[2311] = 0x00; ++ BOOTRAM[2312] = 0x00; ++ BOOTRAM[2313] = 0x00; ++ BOOTRAM[2314] = 0x00; ++ BOOTRAM[2315] = 0x00; ++ BOOTRAM[2316] = 0x00; ++ BOOTRAM[2317] = 0x00; ++ BOOTRAM[2318] = 0x00; ++ BOOTRAM[2319] = 0x00; ++ BOOTRAM[2320] = 0x00; ++ BOOTRAM[2321] = 0x00; ++ BOOTRAM[2322] = 0x00; ++ BOOTRAM[2323] = 0x00; ++ BOOTRAM[2324] = 0x00; ++ BOOTRAM[2325] = 0x00; ++ BOOTRAM[2326] = 0x00; ++ BOOTRAM[2327] = 0x00; ++ BOOTRAM[2328] = 0x00; ++ BOOTRAM[2329] = 0x00; ++ BOOTRAM[2330] = 0x00; ++ BOOTRAM[2331] = 0x00; ++ BOOTRAM[2332] = 0x00; ++ BOOTRAM[2333] = 0x00; ++ BOOTRAM[2334] = 0x00; ++ BOOTRAM[2335] = 0x00; ++ BOOTRAM[2336] = 0x00; ++ BOOTRAM[2337] = 0x00; ++ BOOTRAM[2338] = 0x00; ++ BOOTRAM[2339] = 0x00; ++ BOOTRAM[2340] = 0x00; ++ BOOTRAM[2341] = 0x00; ++ BOOTRAM[2342] = 0x00; ++ BOOTRAM[2343] = 0x00; ++ BOOTRAM[2344] = 0x00; ++ BOOTRAM[2345] = 0x00; ++ BOOTRAM[2346] = 0x00; ++ BOOTRAM[2347] = 0x00; ++ BOOTRAM[2348] = 0x00; ++ BOOTRAM[2349] = 0x00; ++ BOOTRAM[2350] = 0x00; ++ BOOTRAM[2351] = 0x00; ++ BOOTRAM[2352] = 0x00; ++ BOOTRAM[2353] = 0x00; ++ BOOTRAM[2354] = 0x00; ++ BOOTRAM[2355] = 0x42; ++ BOOTRAM[2356] = 0x81; ++ BOOTRAM[2357] = 0x4E; ++ BOOTRAM[2358] = 0x00; ++ BOOTRAM[2359] = 0x00; ++ BOOTRAM[2360] = 0x58; ++ BOOTRAM[2361] = 0x81; ++ BOOTRAM[2362] = 0x50; ++ BOOTRAM[2363] = 0x0B; ++ BOOTRAM[2364] = 0x0B; ++ BOOTRAM[2365] = 0x0C; ++ BOOTRAM[2366] = 0x00; ++ BOOTRAM[2367] = 0x1B; ++ BOOTRAM[2368] = 0x01; ++ BOOTRAM[2369] = 0x0F; ++ BOOTRAM[2370] = 0x02; ++ BOOTRAM[2371] = 0x03; ++ BOOTRAM[2372] = 0x03; ++ BOOTRAM[2373] = 0x19; ++ BOOTRAM[2374] = 0x04; ++ BOOTRAM[2375] = 0x11; ++ BOOTRAM[2376] = 0x05; ++ BOOTRAM[2377] = 0x01; ++ BOOTRAM[2378] = 0x06; ++ BOOTRAM[2379] = 0x09; ++ BOOTRAM[2380] = 0x07; ++ BOOTRAM[2381] = 0x1D; ++ BOOTRAM[2382] = 0x08; ++ BOOTRAM[2383] = 0x0D; ++ BOOTRAM[2384] = 0x09; ++ BOOTRAM[2385] = 0x1C; ++ BOOTRAM[2386] = 0x0A; ++ BOOTRAM[2387] = 0x41; ++ BOOTRAM[2388] = 0x81; ++ BOOTRAM[2389] = 0x9E; ++ BOOTRAM[2390] = 0x00; ++ BOOTRAM[2391] = 0x00; ++ BOOTRAM[2392] = 0x90; ++ BOOTRAM[2393] = 0x81; ++ BOOTRAM[2394] = 0x95; ++ BOOTRAM[2395] = 0x74; ++ BOOTRAM[2396] = 0x01; ++ BOOTRAM[2397] = 0xF0; ++ BOOTRAM[2398] = 0x90; ++ BOOTRAM[2399] = 0x81; ++ BOOTRAM[2400] = 0x97; ++ BOOTRAM[2401] = 0xE0; ++ BOOTRAM[2402] = 0xFF; ++ BOOTRAM[2403] = 0x64; ++ BOOTRAM[2404] = 0x10; ++ BOOTRAM[2405] = 0x60; ++ BOOTRAM[2406] = 0x09; ++ BOOTRAM[2407] = 0xEF; ++ BOOTRAM[2408] = 0x64; ++ BOOTRAM[2409] = 0x11; ++ BOOTRAM[2410] = 0x60; ++ BOOTRAM[2411] = 0x04; ++ BOOTRAM[2412] = 0xEF; ++ BOOTRAM[2413] = 0xB4; ++ BOOTRAM[2414] = 0x12; ++ BOOTRAM[2415] = 0x11; ++ BOOTRAM[2416] = 0x7D; ++ BOOTRAM[2417] = 0x07; ++ BOOTRAM[2418] = 0x7C; ++ BOOTRAM[2419] = 0x00; ++ BOOTRAM[2420] = 0x7F; ++ BOOTRAM[2421] = 0x20; ++ BOOTRAM[2422] = 0x7E; ++ BOOTRAM[2423] = 0xA1; ++ BOOTRAM[2424] = 0x12; ++ BOOTRAM[2425] = 0x06; ++ BOOTRAM[2426] = 0x2E; ++ BOOTRAM[2427] = 0xE4; ++ BOOTRAM[2428] = 0xFD; ++ BOOTRAM[2429] = 0x7F; ++ BOOTRAM[2430] = 0x03; ++ BOOTRAM[2431] = 0x80; ++ BOOTRAM[2432] = 0x04; ++ BOOTRAM[2433] = 0xE4; ++ BOOTRAM[2434] = 0xFD; ++ BOOTRAM[2435] = 0x7F; ++ BOOTRAM[2436] = 0x04; ++ BOOTRAM[2437] = 0x12; ++ BOOTRAM[2438] = 0x0D; ++ BOOTRAM[2439] = 0x52; ++ BOOTRAM[2440] = 0xE4; ++ BOOTRAM[2441] = 0xFD; ++ BOOTRAM[2442] = 0xFC; ++ BOOTRAM[2443] = 0x7F; ++ BOOTRAM[2444] = 0xE8; ++ BOOTRAM[2445] = 0x7E; ++ BOOTRAM[2446] = 0x03; ++ BOOTRAM[2447] = 0x12; ++ BOOTRAM[2448] = 0x06; ++ BOOTRAM[2449] = 0x2E; ++ BOOTRAM[2450] = 0x12; ++ BOOTRAM[2451] = 0x0E; ++ BOOTRAM[2452] = 0xCA; ++ BOOTRAM[2453] = 0x90; ++ BOOTRAM[2454] = 0x28; ++ BOOTRAM[2455] = 0x00; ++ BOOTRAM[2456] = 0xE0; ++ BOOTRAM[2457] = 0x44; ++ BOOTRAM[2458] = 0x10; ++ BOOTRAM[2459] = 0xF0; ++ BOOTRAM[2460] = 0xE4; ++ BOOTRAM[2461] = 0xFD; ++ BOOTRAM[2462] = 0xFC; ++ BOOTRAM[2463] = 0x7F; ++ BOOTRAM[2464] = 0xE8; ++ BOOTRAM[2465] = 0x7E; ++ BOOTRAM[2466] = 0x03; ++ BOOTRAM[2467] = 0x12; ++ BOOTRAM[2468] = 0x06; ++ BOOTRAM[2469] = 0x2E; ++ BOOTRAM[2470] = 0x90; ++ BOOTRAM[2471] = 0x81; ++ BOOTRAM[2472] = 0x97; ++ BOOTRAM[2473] = 0xE0; ++ BOOTRAM[2474] = 0xFF; ++ BOOTRAM[2475] = 0x64; ++ BOOTRAM[2476] = 0x31; ++ BOOTRAM[2477] = 0x60; ++ BOOTRAM[2478] = 0x1E; ++ BOOTRAM[2479] = 0xEF; ++ BOOTRAM[2480] = 0x64; ++ BOOTRAM[2481] = 0x30; ++ BOOTRAM[2482] = 0x60; ++ BOOTRAM[2483] = 0x19; ++ BOOTRAM[2484] = 0x12; ++ BOOTRAM[2485] = 0x0E; ++ BOOTRAM[2486] = 0xD2; ++ BOOTRAM[2487] = 0xE4; ++ BOOTRAM[2488] = 0xFD; ++ BOOTRAM[2489] = 0xFC; ++ BOOTRAM[2490] = 0x7F; ++ BOOTRAM[2491] = 0xE8; ++ BOOTRAM[2492] = 0x7E; ++ BOOTRAM[2493] = 0x03; ++ BOOTRAM[2494] = 0x12; ++ BOOTRAM[2495] = 0x06; ++ BOOTRAM[2496] = 0x2E; ++ BOOTRAM[2497] = 0xE4; ++ BOOTRAM[2498] = 0xFD; ++ BOOTRAM[2499] = 0xFC; ++ BOOTRAM[2500] = 0x7F; ++ BOOTRAM[2501] = 0xE8; ++ BOOTRAM[2502] = 0x7E; ++ BOOTRAM[2503] = 0x03; ++ BOOTRAM[2504] = 0x12; ++ BOOTRAM[2505] = 0x06; ++ BOOTRAM[2506] = 0x2E; ++ BOOTRAM[2507] = 0x80; ++ BOOTRAM[2508] = 0xEA; ++ BOOTRAM[2509] = 0x22; ++ BOOTRAM[2510] = 0xC0; ++ BOOTRAM[2511] = 0xE0; ++ BOOTRAM[2512] = 0xC0; ++ BOOTRAM[2513] = 0xF0; ++ BOOTRAM[2514] = 0xC0; ++ BOOTRAM[2515] = 0x83; ++ BOOTRAM[2516] = 0xC0; ++ BOOTRAM[2517] = 0x82; ++ BOOTRAM[2518] = 0xC0; ++ BOOTRAM[2519] = 0xD0; ++ BOOTRAM[2520] = 0x75; ++ BOOTRAM[2521] = 0xD0; ++ BOOTRAM[2522] = 0x00; ++ BOOTRAM[2523] = 0xC0; ++ BOOTRAM[2524] = 0x00; ++ BOOTRAM[2525] = 0xC0; ++ BOOTRAM[2526] = 0x01; ++ BOOTRAM[2527] = 0xC0; ++ BOOTRAM[2528] = 0x02; ++ BOOTRAM[2529] = 0xC0; ++ BOOTRAM[2530] = 0x03; ++ BOOTRAM[2531] = 0xC0; ++ BOOTRAM[2532] = 0x04; ++ BOOTRAM[2533] = 0xC0; ++ BOOTRAM[2534] = 0x05; ++ BOOTRAM[2535] = 0xC0; ++ BOOTRAM[2536] = 0x06; ++ BOOTRAM[2537] = 0xC0; ++ BOOTRAM[2538] = 0x07; ++ BOOTRAM[2539] = 0x90; ++ BOOTRAM[2540] = 0x37; ++ BOOTRAM[2541] = 0x10; ++ BOOTRAM[2542] = 0xE0; ++ BOOTRAM[2543] = 0x90; ++ BOOTRAM[2544] = 0x81; ++ BOOTRAM[2545] = 0x7D; ++ BOOTRAM[2546] = 0xF0; ++ BOOTRAM[2547] = 0xE0; ++ BOOTRAM[2548] = 0x30; ++ BOOTRAM[2549] = 0xE0; ++ BOOTRAM[2550] = 0x09; ++ BOOTRAM[2551] = 0x12; ++ BOOTRAM[2552] = 0x0B; ++ BOOTRAM[2553] = 0xD9; ++ BOOTRAM[2554] = 0x90; ++ BOOTRAM[2555] = 0x37; ++ BOOTRAM[2556] = 0x08; ++ BOOTRAM[2557] = 0x74; ++ BOOTRAM[2558] = 0x01; ++ BOOTRAM[2559] = 0xF0; ++ BOOTRAM[2560] = 0x90; ++ BOOTRAM[2561] = 0x81; ++ BOOTRAM[2562] = 0x7D; ++ BOOTRAM[2563] = 0xE0; ++ BOOTRAM[2564] = 0x30; ++ BOOTRAM[2565] = 0xE1; ++ BOOTRAM[2566] = 0x09; ++ BOOTRAM[2567] = 0x12; ++ BOOTRAM[2568] = 0x05; ++ BOOTRAM[2569] = 0x69; ++ BOOTRAM[2570] = 0x90; ++ BOOTRAM[2571] = 0x37; ++ BOOTRAM[2572] = 0x09; ++ BOOTRAM[2573] = 0x74; ++ BOOTRAM[2574] = 0x02; ++ BOOTRAM[2575] = 0xF0; ++ BOOTRAM[2576] = 0x90; ++ BOOTRAM[2577] = 0x81; ++ BOOTRAM[2578] = 0x7D; ++ BOOTRAM[2579] = 0xE0; ++ BOOTRAM[2580] = 0x30; ++ BOOTRAM[2581] = 0xE3; ++ BOOTRAM[2582] = 0x09; ++ BOOTRAM[2583] = 0x90; ++ BOOTRAM[2584] = 0x37; ++ BOOTRAM[2585] = 0x0B; ++ BOOTRAM[2586] = 0x74; ++ BOOTRAM[2587] = 0x08; ++ BOOTRAM[2588] = 0xF0; ++ BOOTRAM[2589] = 0x12; ++ BOOTRAM[2590] = 0x06; ++ BOOTRAM[2591] = 0xEF; ++ BOOTRAM[2592] = 0xD0; ++ BOOTRAM[2593] = 0x07; ++ BOOTRAM[2594] = 0xD0; ++ BOOTRAM[2595] = 0x06; ++ BOOTRAM[2596] = 0xD0; ++ BOOTRAM[2597] = 0x05; ++ BOOTRAM[2598] = 0xD0; ++ BOOTRAM[2599] = 0x04; ++ BOOTRAM[2600] = 0xD0; ++ BOOTRAM[2601] = 0x03; ++ BOOTRAM[2602] = 0xD0; ++ BOOTRAM[2603] = 0x02; ++ BOOTRAM[2604] = 0xD0; ++ BOOTRAM[2605] = 0x01; ++ BOOTRAM[2606] = 0xD0; ++ BOOTRAM[2607] = 0x00; ++ BOOTRAM[2608] = 0xD0; ++ BOOTRAM[2609] = 0xD0; ++ BOOTRAM[2610] = 0xD0; ++ BOOTRAM[2611] = 0x82; ++ BOOTRAM[2612] = 0xD0; ++ BOOTRAM[2613] = 0x83; ++ BOOTRAM[2614] = 0xD0; ++ BOOTRAM[2615] = 0xF0; ++ BOOTRAM[2616] = 0xD0; ++ BOOTRAM[2617] = 0xE0; ++ BOOTRAM[2618] = 0x32; ++ BOOTRAM[2619] = 0x7F; ++ BOOTRAM[2620] = 0x04; ++ BOOTRAM[2621] = 0x12; ++ BOOTRAM[2622] = 0x0A; ++ BOOTRAM[2623] = 0x44; ++ BOOTRAM[2624] = 0x7D; ++ BOOTRAM[2625] = 0x01; ++ BOOTRAM[2626] = 0x7F; ++ BOOTRAM[2627] = 0x05; ++ BOOTRAM[2628] = 0x90; ++ BOOTRAM[2629] = 0x19; ++ BOOTRAM[2630] = 0x03; ++ BOOTRAM[2631] = 0xE0; ++ BOOTRAM[2632] = 0xFE; ++ BOOTRAM[2633] = 0x90; ++ BOOTRAM[2634] = 0x19; ++ BOOTRAM[2635] = 0x02; ++ BOOTRAM[2636] = 0xE0; ++ BOOTRAM[2637] = 0xFC; ++ BOOTRAM[2638] = 0xED; ++ BOOTRAM[2639] = 0x14; ++ BOOTRAM[2640] = 0x60; ++ BOOTRAM[2641] = 0x17; ++ BOOTRAM[2642] = 0x04; ++ BOOTRAM[2643] = 0x70; ++ BOOTRAM[2644] = 0x28; ++ BOOTRAM[2645] = 0x74; ++ BOOTRAM[2646] = 0x01; ++ BOOTRAM[2647] = 0xA8; ++ BOOTRAM[2648] = 0x07; ++ BOOTRAM[2649] = 0x08; ++ BOOTRAM[2650] = 0x80; ++ BOOTRAM[2651] = 0x02; ++ BOOTRAM[2652] = 0xC3; ++ BOOTRAM[2653] = 0x33; ++ BOOTRAM[2654] = 0xD8; ++ BOOTRAM[2655] = 0xFC; ++ BOOTRAM[2656] = 0xF4; ++ BOOTRAM[2657] = 0xFD; ++ BOOTRAM[2658] = 0x5E; ++ BOOTRAM[2659] = 0xFE; ++ BOOTRAM[2660] = 0xEC; ++ BOOTRAM[2661] = 0x5D; ++ BOOTRAM[2662] = 0xFC; ++ BOOTRAM[2663] = 0x80; ++ BOOTRAM[2664] = 0x21; ++ BOOTRAM[2665] = 0x74; ++ BOOTRAM[2666] = 0x01; ++ BOOTRAM[2667] = 0xA8; ++ BOOTRAM[2668] = 0x07; ++ BOOTRAM[2669] = 0x08; ++ BOOTRAM[2670] = 0x80; ++ BOOTRAM[2671] = 0x02; ++ BOOTRAM[2672] = 0xC3; ++ BOOTRAM[2673] = 0x33; ++ BOOTRAM[2674] = 0xD8; ++ BOOTRAM[2675] = 0xFC; ++ BOOTRAM[2676] = 0xFD; ++ BOOTRAM[2677] = 0x4E; ++ BOOTRAM[2678] = 0xFE; ++ BOOTRAM[2679] = 0xED; ++ BOOTRAM[2680] = 0xF4; ++ BOOTRAM[2681] = 0x5C; ++ BOOTRAM[2682] = 0xFC; ++ BOOTRAM[2683] = 0x80; ++ BOOTRAM[2684] = 0x0D; ++ BOOTRAM[2685] = 0x74; ++ BOOTRAM[2686] = 0x01; ++ BOOTRAM[2687] = 0xA8; ++ BOOTRAM[2688] = 0x07; ++ BOOTRAM[2689] = 0x08; ++ BOOTRAM[2690] = 0x80; ++ BOOTRAM[2691] = 0x02; ++ BOOTRAM[2692] = 0xC3; ++ BOOTRAM[2693] = 0x33; ++ BOOTRAM[2694] = 0xD8; ++ BOOTRAM[2695] = 0xFC; ++ BOOTRAM[2696] = 0x4C; ++ BOOTRAM[2697] = 0xFC; ++ BOOTRAM[2698] = 0xAF; ++ BOOTRAM[2699] = 0x06; ++ BOOTRAM[2700] = 0x90; ++ BOOTRAM[2701] = 0x19; ++ BOOTRAM[2702] = 0x03; ++ BOOTRAM[2703] = 0xEE; ++ BOOTRAM[2704] = 0xF0; ++ BOOTRAM[2705] = 0xAF; ++ BOOTRAM[2706] = 0x04; ++ BOOTRAM[2707] = 0x90; ++ BOOTRAM[2708] = 0x19; ++ BOOTRAM[2709] = 0x02; ++ BOOTRAM[2710] = 0xEC; ++ BOOTRAM[2711] = 0xF0; ++ BOOTRAM[2712] = 0x22; ++ BOOTRAM[2713] = 0xFD; ++ BOOTRAM[2714] = 0x7F; ++ BOOTRAM[2715] = 0x03; ++ BOOTRAM[2716] = 0x12; ++ BOOTRAM[2717] = 0x0C; ++ BOOTRAM[2718] = 0xA2; ++ BOOTRAM[2719] = 0x0D; ++ BOOTRAM[2720] = 0x7F; ++ BOOTRAM[2721] = 0x04; ++ BOOTRAM[2722] = 0x12; ++ BOOTRAM[2723] = 0x0C; ++ BOOTRAM[2724] = 0xA2; ++ BOOTRAM[2725] = 0x7F; ++ BOOTRAM[2726] = 0x05; ++ BOOTRAM[2727] = 0x12; ++ BOOTRAM[2728] = 0x0C; ++ BOOTRAM[2729] = 0xA2; ++ BOOTRAM[2730] = 0x1D; ++ BOOTRAM[2731] = 0x7F; ++ BOOTRAM[2732] = 0x03; ++ BOOTRAM[2733] = 0x12; ++ BOOTRAM[2734] = 0x0D; ++ BOOTRAM[2735] = 0x52; ++ BOOTRAM[2736] = 0xE4; ++ BOOTRAM[2737] = 0xFD; ++ BOOTRAM[2738] = 0x7F; ++ BOOTRAM[2739] = 0x02; ++ BOOTRAM[2740] = 0x12; ++ BOOTRAM[2741] = 0x0A; ++ BOOTRAM[2742] = 0xC0; ++ BOOTRAM[2743] = 0x0D; ++ BOOTRAM[2744] = 0x7F; ++ BOOTRAM[2745] = 0x04; ++ BOOTRAM[2746] = 0x12; ++ BOOTRAM[2747] = 0x0A; ++ BOOTRAM[2748] = 0xC0; ++ BOOTRAM[2749] = 0x1D; ++ BOOTRAM[2750] = 0x7F; ++ BOOTRAM[2751] = 0x05; ++ BOOTRAM[2752] = 0x90; ++ BOOTRAM[2753] = 0x19; ++ BOOTRAM[2754] = 0x01; ++ BOOTRAM[2755] = 0xE0; ++ BOOTRAM[2756] = 0xFE; ++ BOOTRAM[2757] = 0xED; ++ BOOTRAM[2758] = 0x70; ++ BOOTRAM[2759] = 0x0F; ++ BOOTRAM[2760] = 0x04; ++ BOOTRAM[2761] = 0xA8; ++ BOOTRAM[2762] = 0x07; ++ BOOTRAM[2763] = 0x08; ++ BOOTRAM[2764] = 0x80; ++ BOOTRAM[2765] = 0x02; ++ BOOTRAM[2766] = 0xC3; ++ BOOTRAM[2767] = 0x33; ++ BOOTRAM[2768] = 0xD8; ++ BOOTRAM[2769] = 0xFC; ++ BOOTRAM[2770] = 0xF4; ++ BOOTRAM[2771] = 0x5E; ++ BOOTRAM[2772] = 0xFE; ++ BOOTRAM[2773] = 0x80; ++ BOOTRAM[2774] = 0x0D; ++ BOOTRAM[2775] = 0x74; ++ BOOTRAM[2776] = 0x01; ++ BOOTRAM[2777] = 0xA8; ++ BOOTRAM[2778] = 0x07; ++ BOOTRAM[2779] = 0x08; ++ BOOTRAM[2780] = 0x80; ++ BOOTRAM[2781] = 0x02; ++ BOOTRAM[2782] = 0xC3; ++ BOOTRAM[2783] = 0x33; ++ BOOTRAM[2784] = 0xD8; ++ BOOTRAM[2785] = 0xFC; ++ BOOTRAM[2786] = 0x4E; ++ BOOTRAM[2787] = 0xFE; ++ BOOTRAM[2788] = 0xAF; ++ BOOTRAM[2789] = 0x06; ++ BOOTRAM[2790] = 0x90; ++ BOOTRAM[2791] = 0x19; ++ BOOTRAM[2792] = 0x01; ++ BOOTRAM[2793] = 0xEE; ++ BOOTRAM[2794] = 0xF0; ++ BOOTRAM[2795] = 0x22; ++ BOOTRAM[2796] = 0x90; ++ BOOTRAM[2797] = 0x81; ++ BOOTRAM[2798] = 0x80; ++ BOOTRAM[2799] = 0xEE; ++ BOOTRAM[2800] = 0xF0; ++ BOOTRAM[2801] = 0xA3; ++ BOOTRAM[2802] = 0xEF; ++ BOOTRAM[2803] = 0xF0; ++ BOOTRAM[2804] = 0x64; ++ BOOTRAM[2805] = 0x0B; ++ BOOTRAM[2806] = 0x4E; ++ BOOTRAM[2807] = 0x70; ++ BOOTRAM[2808] = 0x0C; ++ BOOTRAM[2809] = 0x90; ++ BOOTRAM[2810] = 0x81; ++ BOOTRAM[2811] = 0x95; ++ BOOTRAM[2812] = 0xE0; ++ BOOTRAM[2813] = 0x60; ++ BOOTRAM[2814] = 0x03; ++ BOOTRAM[2815] = 0x02; ++ BOOTRAM[2816] = 0x0B; ++ BOOTRAM[2817] = 0x8C; ++ BOOTRAM[2818] = 0x02; ++ BOOTRAM[2819] = 0x09; ++ BOOTRAM[2820] = 0x58; ++ BOOTRAM[2821] = 0x90; ++ BOOTRAM[2822] = 0x81; ++ BOOTRAM[2823] = 0x80; ++ BOOTRAM[2824] = 0xE0; ++ BOOTRAM[2825] = 0xFE; ++ BOOTRAM[2826] = 0xA3; ++ BOOTRAM[2827] = 0xE0; ++ BOOTRAM[2828] = 0xFF; ++ BOOTRAM[2829] = 0x64; ++ BOOTRAM[2830] = 0x01; ++ BOOTRAM[2831] = 0x4E; ++ BOOTRAM[2832] = 0x70; ++ BOOTRAM[2833] = 0x09; ++ BOOTRAM[2834] = 0x12; ++ BOOTRAM[2835] = 0x0E; ++ BOOTRAM[2836] = 0x80; ++ BOOTRAM[2837] = 0x90; ++ BOOTRAM[2838] = 0x81; ++ BOOTRAM[2839] = 0x98; ++ BOOTRAM[2840] = 0xE4; ++ BOOTRAM[2841] = 0x80; ++ BOOTRAM[2842] = 0x09; ++ BOOTRAM[2843] = 0xEF; ++ BOOTRAM[2844] = 0x64; ++ BOOTRAM[2845] = 0x04; ++ BOOTRAM[2846] = 0x4E; ++ BOOTRAM[2847] = 0x70; ++ BOOTRAM[2848] = 0x08; ++ BOOTRAM[2849] = 0x90; ++ BOOTRAM[2850] = 0x81; ++ BOOTRAM[2851] = 0x98; ++ BOOTRAM[2852] = 0xF0; ++ BOOTRAM[2853] = 0xA3; ++ BOOTRAM[2854] = 0x04; ++ BOOTRAM[2855] = 0xF0; ++ BOOTRAM[2856] = 0x22; ++ BOOTRAM[2857] = 0xEF; ++ BOOTRAM[2858] = 0x64; ++ BOOTRAM[2859] = 0x03; ++ BOOTRAM[2860] = 0x4E; ++ BOOTRAM[2861] = 0x70; ++ BOOTRAM[2862] = 0x0D; ++ BOOTRAM[2863] = 0x7F; ++ BOOTRAM[2864] = 0x02; ++ BOOTRAM[2865] = 0xFE; ++ BOOTRAM[2866] = 0x12; ++ BOOTRAM[2867] = 0x0E; ++ BOOTRAM[2868] = 0x95; ++ BOOTRAM[2869] = 0xE4; ++ BOOTRAM[2870] = 0x90; ++ BOOTRAM[2871] = 0x81; ++ BOOTRAM[2872] = 0x98; ++ BOOTRAM[2873] = 0xF0; ++ BOOTRAM[2874] = 0xA3; ++ BOOTRAM[2875] = 0xF0; ++ BOOTRAM[2876] = 0x22; ++ BOOTRAM[2877] = 0x78; ++ BOOTRAM[2878] = 0x9A; ++ BOOTRAM[2879] = 0x7C; ++ BOOTRAM[2880] = 0x81; ++ BOOTRAM[2881] = 0x7D; ++ BOOTRAM[2882] = 0x01; ++ BOOTRAM[2883] = 0x7B; ++ BOOTRAM[2884] = 0xFF; ++ BOOTRAM[2885] = 0x7A; ++ BOOTRAM[2886] = 0x0E; ++ BOOTRAM[2887] = 0x79; ++ BOOTRAM[2888] = 0xF0; ++ BOOTRAM[2889] = 0x7E; ++ BOOTRAM[2890] = 0x00; ++ BOOTRAM[2891] = 0x7F; ++ BOOTRAM[2892] = 0x04; ++ BOOTRAM[2893] = 0x12; ++ BOOTRAM[2894] = 0x04; ++ BOOTRAM[2895] = 0x0D; ++ BOOTRAM[2896] = 0x90; ++ BOOTRAM[2897] = 0x28; ++ BOOTRAM[2898] = 0x11; ++ BOOTRAM[2899] = 0xE4; ++ BOOTRAM[2900] = 0xF0; ++ BOOTRAM[2901] = 0x90; ++ BOOTRAM[2902] = 0x81; ++ BOOTRAM[2903] = 0x9D; ++ BOOTRAM[2904] = 0xE0; ++ BOOTRAM[2905] = 0x90; ++ BOOTRAM[2906] = 0x00; ++ BOOTRAM[2907] = 0x04; ++ BOOTRAM[2908] = 0xF0; ++ BOOTRAM[2909] = 0x90; ++ BOOTRAM[2910] = 0x81; ++ BOOTRAM[2911] = 0x9C; ++ BOOTRAM[2912] = 0xE0; ++ BOOTRAM[2913] = 0x90; ++ BOOTRAM[2914] = 0x00; ++ BOOTRAM[2915] = 0x03; ++ BOOTRAM[2916] = 0xF0; ++ BOOTRAM[2917] = 0x90; ++ BOOTRAM[2918] = 0x81; ++ BOOTRAM[2919] = 0x9B; ++ BOOTRAM[2920] = 0xE0; ++ BOOTRAM[2921] = 0x90; ++ BOOTRAM[2922] = 0x00; ++ BOOTRAM[2923] = 0x02; ++ BOOTRAM[2924] = 0xF0; ++ BOOTRAM[2925] = 0x90; ++ BOOTRAM[2926] = 0x81; ++ BOOTRAM[2927] = 0x9A; ++ BOOTRAM[2928] = 0xE0; ++ BOOTRAM[2929] = 0x90; ++ BOOTRAM[2930] = 0x00; ++ BOOTRAM[2931] = 0x01; ++ BOOTRAM[2932] = 0xF0; ++ BOOTRAM[2933] = 0xE4; ++ BOOTRAM[2934] = 0xFB; ++ BOOTRAM[2935] = 0xFD; ++ BOOTRAM[2936] = 0xFF; ++ BOOTRAM[2937] = 0x12; ++ BOOTRAM[2938] = 0x0E; ++ BOOTRAM[2939] = 0x74; ++ BOOTRAM[2940] = 0xE4; ++ BOOTRAM[2941] = 0xFE; ++ BOOTRAM[2942] = 0x12; ++ BOOTRAM[2943] = 0x0D; ++ BOOTRAM[2944] = 0xE0; ++ BOOTRAM[2945] = 0x12; ++ BOOTRAM[2946] = 0x0E; ++ BOOTRAM[2947] = 0xB9; ++ BOOTRAM[2948] = 0x90; ++ BOOTRAM[2949] = 0x28; ++ BOOTRAM[2950] = 0x11; ++ BOOTRAM[2951] = 0xE0; ++ BOOTRAM[2952] = 0x44; ++ BOOTRAM[2953] = 0x02; ++ BOOTRAM[2954] = 0xF0; ++ BOOTRAM[2955] = 0x22; ++ BOOTRAM[2956] = 0x7D; ++ BOOTRAM[2957] = 0x07; ++ BOOTRAM[2958] = 0x7C; ++ BOOTRAM[2959] = 0x00; ++ BOOTRAM[2960] = 0x7F; ++ BOOTRAM[2961] = 0x20; ++ BOOTRAM[2962] = 0x7E; ++ BOOTRAM[2963] = 0xA1; ++ BOOTRAM[2964] = 0x12; ++ BOOTRAM[2965] = 0x06; ++ BOOTRAM[2966] = 0x2E; ++ BOOTRAM[2967] = 0xE4; ++ BOOTRAM[2968] = 0x90; ++ BOOTRAM[2969] = 0x81; ++ BOOTRAM[2970] = 0x95; ++ BOOTRAM[2971] = 0xF0; ++ BOOTRAM[2972] = 0x12; ++ BOOTRAM[2973] = 0x0E; ++ BOOTRAM[2974] = 0xC2; ++ BOOTRAM[2975] = 0x90; ++ BOOTRAM[2976] = 0x28; ++ BOOTRAM[2977] = 0x00; ++ BOOTRAM[2978] = 0xE0; ++ BOOTRAM[2979] = 0x54; ++ BOOTRAM[2980] = 0xEF; ++ BOOTRAM[2981] = 0xF0; ++ BOOTRAM[2982] = 0xE4; ++ BOOTRAM[2983] = 0xFD; ++ BOOTRAM[2984] = 0xFC; ++ BOOTRAM[2985] = 0x7F; ++ BOOTRAM[2986] = 0xE8; ++ BOOTRAM[2987] = 0x7E; ++ BOOTRAM[2988] = 0x03; ++ BOOTRAM[2989] = 0x12; ++ BOOTRAM[2990] = 0x06; ++ BOOTRAM[2991] = 0x2E; ++ BOOTRAM[2992] = 0x90; ++ BOOTRAM[2993] = 0x81; ++ BOOTRAM[2994] = 0x97; ++ BOOTRAM[2995] = 0xE0; ++ BOOTRAM[2996] = 0xFF; ++ BOOTRAM[2997] = 0x64; ++ BOOTRAM[2998] = 0x10; ++ BOOTRAM[2999] = 0x60; ++ BOOTRAM[3000] = 0x09; ++ BOOTRAM[3001] = 0xEF; ++ BOOTRAM[3002] = 0x64; ++ BOOTRAM[3003] = 0x11; ++ BOOTRAM[3004] = 0x60; ++ BOOTRAM[3005] = 0x04; ++ BOOTRAM[3006] = 0xEF; ++ BOOTRAM[3007] = 0xB4; ++ BOOTRAM[3008] = 0x12; ++ BOOTRAM[3009] = 0x06; ++ BOOTRAM[3010] = 0x7D; ++ BOOTRAM[3011] = 0x01; ++ BOOTRAM[3012] = 0x7F; ++ BOOTRAM[3013] = 0x03; ++ BOOTRAM[3014] = 0x80; ++ BOOTRAM[3015] = 0x04; ++ BOOTRAM[3016] = 0x7D; ++ BOOTRAM[3017] = 0x01; ++ BOOTRAM[3018] = 0x7F; ++ BOOTRAM[3019] = 0x04; ++ BOOTRAM[3020] = 0x12; ++ BOOTRAM[3021] = 0x0D; ++ BOOTRAM[3022] = 0x52; ++ BOOTRAM[3023] = 0xE4; ++ BOOTRAM[3024] = 0xFD; ++ BOOTRAM[3025] = 0xFC; ++ BOOTRAM[3026] = 0x7F; ++ BOOTRAM[3027] = 0xE8; ++ BOOTRAM[3028] = 0x7E; ++ BOOTRAM[3029] = 0x03; ++ BOOTRAM[3030] = 0x02; ++ BOOTRAM[3031] = 0x06; ++ BOOTRAM[3032] = 0x2E; ++ BOOTRAM[3033] = 0x90; ++ BOOTRAM[3034] = 0x00; ++ BOOTRAM[3035] = 0x08; ++ BOOTRAM[3036] = 0x74; ++ BOOTRAM[3037] = 0x01; ++ BOOTRAM[3038] = 0xF0; ++ BOOTRAM[3039] = 0xE4; ++ BOOTRAM[3040] = 0xF0; ++ BOOTRAM[3041] = 0x7B; ++ BOOTRAM[3042] = 0x01; ++ BOOTRAM[3043] = 0x90; ++ BOOTRAM[3044] = 0x81; ++ BOOTRAM[3045] = 0x86; ++ BOOTRAM[3046] = 0x04; ++ BOOTRAM[3047] = 0xF0; ++ BOOTRAM[3048] = 0xA3; ++ BOOTRAM[3049] = 0x74; ++ BOOTRAM[3050] = 0x81; ++ BOOTRAM[3051] = 0xF0; ++ BOOTRAM[3052] = 0xA3; ++ BOOTRAM[3053] = 0x74; ++ BOOTRAM[3054] = 0x81; ++ BOOTRAM[3055] = 0xF0; ++ BOOTRAM[3056] = 0xA3; ++ BOOTRAM[3057] = 0xEB; ++ BOOTRAM[3058] = 0xF0; ++ BOOTRAM[3059] = 0xA3; ++ BOOTRAM[3060] = 0x74; ++ BOOTRAM[3061] = 0x81; ++ BOOTRAM[3062] = 0xF0; ++ BOOTRAM[3063] = 0xA3; ++ BOOTRAM[3064] = 0x74; ++ BOOTRAM[3065] = 0x82; ++ BOOTRAM[3066] = 0xF0; ++ BOOTRAM[3067] = 0x7A; ++ BOOTRAM[3068] = 0x81; ++ BOOTRAM[3069] = 0x79; ++ BOOTRAM[3070] = 0x80; ++ BOOTRAM[3071] = 0x12; ++ BOOTRAM[3072] = 0x0C; ++ BOOTRAM[3073] = 0x47; ++ BOOTRAM[3074] = 0x7B; ++ BOOTRAM[3075] = 0x01; ++ BOOTRAM[3076] = 0x7A; ++ BOOTRAM[3077] = 0x81; ++ BOOTRAM[3078] = 0x79; ++ BOOTRAM[3079] = 0x7E; ++ BOOTRAM[3080] = 0x12; ++ BOOTRAM[3081] = 0x0D; ++ BOOTRAM[3082] = 0xF3; ++ BOOTRAM[3083] = 0x90; ++ BOOTRAM[3084] = 0x81; ++ BOOTRAM[3085] = 0x7E; ++ BOOTRAM[3086] = 0xE0; ++ BOOTRAM[3087] = 0xFE; ++ BOOTRAM[3088] = 0xA3; ++ BOOTRAM[3089] = 0xE0; ++ BOOTRAM[3090] = 0xFF; ++ BOOTRAM[3091] = 0x02; ++ BOOTRAM[3092] = 0x0E; ++ BOOTRAM[3093] = 0x9E; ++ BOOTRAM[3094] = 0x90; ++ BOOTRAM[3095] = 0x81; ++ BOOTRAM[3096] = 0x80; ++ BOOTRAM[3097] = 0xEE; ++ BOOTRAM[3098] = 0xF0; ++ BOOTRAM[3099] = 0xA3; ++ BOOTRAM[3100] = 0xEF; ++ BOOTRAM[3101] = 0xF0; ++ BOOTRAM[3102] = 0xE4; ++ BOOTRAM[3103] = 0xFF; ++ BOOTRAM[3104] = 0xEF; ++ BOOTRAM[3105] = 0x25; ++ BOOTRAM[3106] = 0xE0; ++ BOOTRAM[3107] = 0x24; ++ BOOTRAM[3108] = 0x50; ++ BOOTRAM[3109] = 0xF5; ++ BOOTRAM[3110] = 0x82; ++ BOOTRAM[3111] = 0xE4; ++ BOOTRAM[3112] = 0x34; ++ BOOTRAM[3113] = 0x81; ++ BOOTRAM[3114] = 0xF5; ++ BOOTRAM[3115] = 0x83; ++ BOOTRAM[3116] = 0xE0; ++ BOOTRAM[3117] = 0xB5; ++ BOOTRAM[3118] = 0x05; ++ BOOTRAM[3119] = 0x0F; ++ BOOTRAM[3120] = 0xEF; ++ BOOTRAM[3121] = 0x25; ++ BOOTRAM[3122] = 0xE0; ++ BOOTRAM[3123] = 0x24; ++ BOOTRAM[3124] = 0x51; ++ BOOTRAM[3125] = 0xF5; ++ BOOTRAM[3126] = 0x82; ++ BOOTRAM[3127] = 0xE4; ++ BOOTRAM[3128] = 0x34; ++ BOOTRAM[3129] = 0x81; ++ BOOTRAM[3130] = 0xF5; ++ BOOTRAM[3131] = 0x83; ++ BOOTRAM[3132] = 0xE0; ++ BOOTRAM[3133] = 0xFF; ++ BOOTRAM[3134] = 0x22; ++ BOOTRAM[3135] = 0x0F; ++ BOOTRAM[3136] = 0xEF; ++ BOOTRAM[3137] = 0xB4; ++ BOOTRAM[3138] = 0x0C; ++ BOOTRAM[3139] = 0xDC; ++ BOOTRAM[3140] = 0x7F; ++ BOOTRAM[3141] = 0xFF; ++ BOOTRAM[3142] = 0x22; ++ BOOTRAM[3143] = 0x90; ++ BOOTRAM[3144] = 0x00; ++ BOOTRAM[3145] = 0x1D; ++ BOOTRAM[3146] = 0xE0; ++ BOOTRAM[3147] = 0x12; ++ BOOTRAM[3148] = 0x04; ++ BOOTRAM[3149] = 0x33; ++ BOOTRAM[3150] = 0x90; ++ BOOTRAM[3151] = 0x00; ++ BOOTRAM[3152] = 0x1C; ++ BOOTRAM[3153] = 0xE0; ++ BOOTRAM[3154] = 0xFF; ++ BOOTRAM[3155] = 0x90; ++ BOOTRAM[3156] = 0x81; ++ BOOTRAM[3157] = 0x86; ++ BOOTRAM[3158] = 0xE0; ++ BOOTRAM[3159] = 0xFB; ++ BOOTRAM[3160] = 0xA3; ++ BOOTRAM[3161] = 0xE0; ++ BOOTRAM[3162] = 0xFA; ++ BOOTRAM[3163] = 0xA3; ++ BOOTRAM[3164] = 0xE0; ++ BOOTRAM[3165] = 0xF9; ++ BOOTRAM[3166] = 0xEF; ++ BOOTRAM[3167] = 0x12; ++ BOOTRAM[3168] = 0x04; ++ BOOTRAM[3169] = 0x33; ++ BOOTRAM[3170] = 0x90; ++ BOOTRAM[3171] = 0x00; ++ BOOTRAM[3172] = 0x1B; ++ BOOTRAM[3173] = 0xE0; ++ BOOTRAM[3174] = 0xFF; ++ BOOTRAM[3175] = 0x90; ++ BOOTRAM[3176] = 0x81; ++ BOOTRAM[3177] = 0x89; ++ BOOTRAM[3178] = 0xE0; ++ BOOTRAM[3179] = 0xFB; ++ BOOTRAM[3180] = 0xA3; ++ BOOTRAM[3181] = 0xE0; ++ BOOTRAM[3182] = 0xFA; ++ BOOTRAM[3183] = 0xA3; ++ BOOTRAM[3184] = 0xE0; ++ BOOTRAM[3185] = 0xF9; ++ BOOTRAM[3186] = 0xEF; ++ BOOTRAM[3187] = 0x02; ++ BOOTRAM[3188] = 0x04; ++ BOOTRAM[3189] = 0x33; ++ BOOTRAM[3190] = 0x90; ++ BOOTRAM[3191] = 0x19; ++ BOOTRAM[3192] = 0x08; ++ BOOTRAM[3193] = 0xE0; ++ BOOTRAM[3194] = 0xFE; ++ BOOTRAM[3195] = 0xED; ++ BOOTRAM[3196] = 0x70; ++ BOOTRAM[3197] = 0x0F; ++ BOOTRAM[3198] = 0x04; ++ BOOTRAM[3199] = 0xA8; ++ BOOTRAM[3200] = 0x07; ++ BOOTRAM[3201] = 0x08; ++ BOOTRAM[3202] = 0x80; ++ BOOTRAM[3203] = 0x02; ++ BOOTRAM[3204] = 0xC3; ++ BOOTRAM[3205] = 0x33; ++ BOOTRAM[3206] = 0xD8; ++ BOOTRAM[3207] = 0xFC; ++ BOOTRAM[3208] = 0xF4; ++ BOOTRAM[3209] = 0x5E; ++ BOOTRAM[3210] = 0xFE; ++ BOOTRAM[3211] = 0x80; ++ BOOTRAM[3212] = 0x0D; ++ BOOTRAM[3213] = 0x74; ++ BOOTRAM[3214] = 0x01; ++ BOOTRAM[3215] = 0xA8; ++ BOOTRAM[3216] = 0x07; ++ BOOTRAM[3217] = 0x08; ++ BOOTRAM[3218] = 0x80; ++ BOOTRAM[3219] = 0x02; ++ BOOTRAM[3220] = 0xC3; ++ BOOTRAM[3221] = 0x33; ++ BOOTRAM[3222] = 0xD8; ++ BOOTRAM[3223] = 0xFC; ++ BOOTRAM[3224] = 0x4E; ++ BOOTRAM[3225] = 0xFE; ++ BOOTRAM[3226] = 0xAF; ++ BOOTRAM[3227] = 0x06; ++ BOOTRAM[3228] = 0x90; ++ BOOTRAM[3229] = 0x19; ++ BOOTRAM[3230] = 0x08; ++ BOOTRAM[3231] = 0xEE; ++ BOOTRAM[3232] = 0xF0; ++ BOOTRAM[3233] = 0x22; ++ BOOTRAM[3234] = 0x90; ++ BOOTRAM[3235] = 0x19; ++ BOOTRAM[3236] = 0x00; ++ BOOTRAM[3237] = 0xE0; ++ BOOTRAM[3238] = 0xFE; ++ BOOTRAM[3239] = 0xED; ++ BOOTRAM[3240] = 0x70; ++ BOOTRAM[3241] = 0x0F; ++ BOOTRAM[3242] = 0x04; ++ BOOTRAM[3243] = 0xA8; ++ BOOTRAM[3244] = 0x07; ++ BOOTRAM[3245] = 0x08; ++ BOOTRAM[3246] = 0x80; ++ BOOTRAM[3247] = 0x02; ++ BOOTRAM[3248] = 0xC3; ++ BOOTRAM[3249] = 0x33; ++ BOOTRAM[3250] = 0xD8; ++ BOOTRAM[3251] = 0xFC; ++ BOOTRAM[3252] = 0xF4; ++ BOOTRAM[3253] = 0x5E; ++ BOOTRAM[3254] = 0xFE; ++ BOOTRAM[3255] = 0x80; ++ BOOTRAM[3256] = 0x0D; ++ BOOTRAM[3257] = 0x74; ++ BOOTRAM[3258] = 0x01; ++ BOOTRAM[3259] = 0xA8; ++ BOOTRAM[3260] = 0x07; ++ BOOTRAM[3261] = 0x08; ++ BOOTRAM[3262] = 0x80; ++ BOOTRAM[3263] = 0x02; ++ BOOTRAM[3264] = 0xC3; ++ BOOTRAM[3265] = 0x33; ++ BOOTRAM[3266] = 0xD8; ++ BOOTRAM[3267] = 0xFC; ++ BOOTRAM[3268] = 0x4E; ++ BOOTRAM[3269] = 0xFE; ++ BOOTRAM[3270] = 0xAF; ++ BOOTRAM[3271] = 0x06; ++ BOOTRAM[3272] = 0x90; ++ BOOTRAM[3273] = 0x19; ++ BOOTRAM[3274] = 0x00; ++ BOOTRAM[3275] = 0xEE; ++ BOOTRAM[3276] = 0xF0; ++ BOOTRAM[3277] = 0x22; ++ BOOTRAM[3278] = 0x90; ++ BOOTRAM[3279] = 0x19; ++ BOOTRAM[3280] = 0x03; ++ BOOTRAM[3281] = 0xE0; ++ BOOTRAM[3282] = 0xFE; ++ BOOTRAM[3283] = 0xED; ++ BOOTRAM[3284] = 0x70; ++ BOOTRAM[3285] = 0x0F; ++ BOOTRAM[3286] = 0x04; ++ BOOTRAM[3287] = 0xA8; ++ BOOTRAM[3288] = 0x07; ++ BOOTRAM[3289] = 0x08; ++ BOOTRAM[3290] = 0x80; ++ BOOTRAM[3291] = 0x02; ++ BOOTRAM[3292] = 0xC3; ++ BOOTRAM[3293] = 0x33; ++ BOOTRAM[3294] = 0xD8; ++ BOOTRAM[3295] = 0xFC; ++ BOOTRAM[3296] = 0xF4; ++ BOOTRAM[3297] = 0x5E; ++ BOOTRAM[3298] = 0xFE; ++ BOOTRAM[3299] = 0x80; ++ BOOTRAM[3300] = 0x0D; ++ BOOTRAM[3301] = 0x74; ++ BOOTRAM[3302] = 0x01; ++ BOOTRAM[3303] = 0xA8; ++ BOOTRAM[3304] = 0x07; ++ BOOTRAM[3305] = 0x08; ++ BOOTRAM[3306] = 0x80; ++ BOOTRAM[3307] = 0x02; ++ BOOTRAM[3308] = 0xC3; ++ BOOTRAM[3309] = 0x33; ++ BOOTRAM[3310] = 0xD8; ++ BOOTRAM[3311] = 0xFC; ++ BOOTRAM[3312] = 0x4E; ++ BOOTRAM[3313] = 0xFE; ++ BOOTRAM[3314] = 0xAF; ++ BOOTRAM[3315] = 0x06; ++ BOOTRAM[3316] = 0x90; ++ BOOTRAM[3317] = 0x19; ++ BOOTRAM[3318] = 0x03; ++ BOOTRAM[3319] = 0xEE; ++ BOOTRAM[3320] = 0xF0; ++ BOOTRAM[3321] = 0x22; ++ BOOTRAM[3322] = 0x90; ++ BOOTRAM[3323] = 0x19; ++ BOOTRAM[3324] = 0x04; ++ BOOTRAM[3325] = 0xE0; ++ BOOTRAM[3326] = 0xFE; ++ BOOTRAM[3327] = 0xED; ++ BOOTRAM[3328] = 0x70; ++ BOOTRAM[3329] = 0x0F; ++ BOOTRAM[3330] = 0x04; ++ BOOTRAM[3331] = 0xA8; ++ BOOTRAM[3332] = 0x07; ++ BOOTRAM[3333] = 0x08; ++ BOOTRAM[3334] = 0x80; ++ BOOTRAM[3335] = 0x02; ++ BOOTRAM[3336] = 0xC3; ++ BOOTRAM[3337] = 0x33; ++ BOOTRAM[3338] = 0xD8; ++ BOOTRAM[3339] = 0xFC; ++ BOOTRAM[3340] = 0xF4; ++ BOOTRAM[3341] = 0x5E; ++ BOOTRAM[3342] = 0xFE; ++ BOOTRAM[3343] = 0x80; ++ BOOTRAM[3344] = 0x0D; ++ BOOTRAM[3345] = 0x74; ++ BOOTRAM[3346] = 0x01; ++ BOOTRAM[3347] = 0xA8; ++ BOOTRAM[3348] = 0x07; ++ BOOTRAM[3349] = 0x08; ++ BOOTRAM[3350] = 0x80; ++ BOOTRAM[3351] = 0x02; ++ BOOTRAM[3352] = 0xC3; ++ BOOTRAM[3353] = 0x33; ++ BOOTRAM[3354] = 0xD8; ++ BOOTRAM[3355] = 0xFC; ++ BOOTRAM[3356] = 0x4E; ++ BOOTRAM[3357] = 0xFE; ++ BOOTRAM[3358] = 0xAF; ++ BOOTRAM[3359] = 0x06; ++ BOOTRAM[3360] = 0x90; ++ BOOTRAM[3361] = 0x19; ++ BOOTRAM[3362] = 0x04; ++ BOOTRAM[3363] = 0xEE; ++ BOOTRAM[3364] = 0xF0; ++ BOOTRAM[3365] = 0x22; ++ BOOTRAM[3366] = 0xAD; ++ BOOTRAM[3367] = 0x07; ++ BOOTRAM[3368] = 0x74; ++ BOOTRAM[3369] = 0x01; ++ BOOTRAM[3370] = 0x7E; ++ BOOTRAM[3371] = 0x00; ++ BOOTRAM[3372] = 0xA8; ++ BOOTRAM[3373] = 0x05; ++ BOOTRAM[3374] = 0x08; ++ BOOTRAM[3375] = 0x80; ++ BOOTRAM[3376] = 0x05; ++ BOOTRAM[3377] = 0xC3; ++ BOOTRAM[3378] = 0x33; ++ BOOTRAM[3379] = 0xCE; ++ BOOTRAM[3380] = 0x33; ++ BOOTRAM[3381] = 0xCE; ++ BOOTRAM[3382] = 0xD8; ++ BOOTRAM[3383] = 0xF9; ++ BOOTRAM[3384] = 0xFF; ++ BOOTRAM[3385] = 0x24; ++ BOOTRAM[3386] = 0x00; ++ BOOTRAM[3387] = 0xFB; ++ BOOTRAM[3388] = 0xEE; ++ BOOTRAM[3389] = 0x34; ++ BOOTRAM[3390] = 0x18; ++ BOOTRAM[3391] = 0x8B; ++ BOOTRAM[3392] = 0x82; ++ BOOTRAM[3393] = 0xF5; ++ BOOTRAM[3394] = 0x83; ++ BOOTRAM[3395] = 0xE0; ++ BOOTRAM[3396] = 0xFD; ++ BOOTRAM[3397] = 0xEF; ++ BOOTRAM[3398] = 0x5D; ++ BOOTRAM[3399] = 0x60; ++ BOOTRAM[3400] = 0x05; ++ BOOTRAM[3401] = 0x7E; ++ BOOTRAM[3402] = 0x00; ++ BOOTRAM[3403] = 0x7F; ++ BOOTRAM[3404] = 0x01; ++ BOOTRAM[3405] = 0x22; ++ BOOTRAM[3406] = 0xE4; ++ BOOTRAM[3407] = 0xFE; ++ BOOTRAM[3408] = 0xFF; ++ BOOTRAM[3409] = 0x22; ++ BOOTRAM[3410] = 0xED; ++ BOOTRAM[3411] = 0x54; ++ BOOTRAM[3412] = 0x01; ++ BOOTRAM[3413] = 0xFE; ++ BOOTRAM[3414] = 0xA8; ++ BOOTRAM[3415] = 0x07; ++ BOOTRAM[3416] = 0x08; ++ BOOTRAM[3417] = 0x80; ++ BOOTRAM[3418] = 0x02; ++ BOOTRAM[3419] = 0xC3; ++ BOOTRAM[3420] = 0x33; ++ BOOTRAM[3421] = 0xD8; ++ BOOTRAM[3422] = 0xFC; ++ BOOTRAM[3423] = 0xFD; ++ BOOTRAM[3424] = 0x74; ++ BOOTRAM[3425] = 0x01; ++ BOOTRAM[3426] = 0x7E; ++ BOOTRAM[3427] = 0x00; ++ BOOTRAM[3428] = 0xA8; ++ BOOTRAM[3429] = 0x07; ++ BOOTRAM[3430] = 0x08; ++ BOOTRAM[3431] = 0x80; ++ BOOTRAM[3432] = 0x05; ++ BOOTRAM[3433] = 0xC3; ++ BOOTRAM[3434] = 0x33; ++ BOOTRAM[3435] = 0xCE; ++ BOOTRAM[3436] = 0x33; ++ BOOTRAM[3437] = 0xCE; ++ BOOTRAM[3438] = 0xD8; ++ BOOTRAM[3439] = 0xF9; ++ BOOTRAM[3440] = 0x24; ++ BOOTRAM[3441] = 0x00; ++ BOOTRAM[3442] = 0xFF; ++ BOOTRAM[3443] = 0xEE; ++ BOOTRAM[3444] = 0x34; ++ BOOTRAM[3445] = 0x18; ++ BOOTRAM[3446] = 0x8F; ++ BOOTRAM[3447] = 0x82; ++ BOOTRAM[3448] = 0xF5; ++ BOOTRAM[3449] = 0x83; ++ BOOTRAM[3450] = 0xED; ++ BOOTRAM[3451] = 0xF0; ++ BOOTRAM[3452] = 0x22; ++ BOOTRAM[3453] = 0x90; ++ BOOTRAM[3454] = 0x10; ++ BOOTRAM[3455] = 0x2C; ++ BOOTRAM[3456] = 0xE0; ++ BOOTRAM[3457] = 0xFD; ++ BOOTRAM[3458] = 0xA3; ++ BOOTRAM[3459] = 0xE0; ++ BOOTRAM[3460] = 0xFF; ++ BOOTRAM[3461] = 0xED; ++ BOOTRAM[3462] = 0xCF; ++ BOOTRAM[3463] = 0x8F; ++ BOOTRAM[3464] = 0xF0; ++ BOOTRAM[3465] = 0x12; ++ BOOTRAM[3466] = 0x04; ++ BOOTRAM[3467] = 0x57; ++ BOOTRAM[3468] = 0x90; ++ BOOTRAM[3469] = 0x10; ++ BOOTRAM[3470] = 0x2E; ++ BOOTRAM[3471] = 0xE0; ++ BOOTRAM[3472] = 0xFD; ++ BOOTRAM[3473] = 0xA3; ++ BOOTRAM[3474] = 0xE0; ++ BOOTRAM[3475] = 0xF9; ++ BOOTRAM[3476] = 0xED; ++ BOOTRAM[3477] = 0xFF; ++ BOOTRAM[3478] = 0x90; ++ BOOTRAM[3479] = 0x81; ++ BOOTRAM[3480] = 0x91; ++ BOOTRAM[3481] = 0xE0; ++ BOOTRAM[3482] = 0xFB; ++ BOOTRAM[3483] = 0xA3; ++ BOOTRAM[3484] = 0xE0; ++ BOOTRAM[3485] = 0xFA; ++ BOOTRAM[3486] = 0xA3; ++ BOOTRAM[3487] = 0xE0; ++ BOOTRAM[3488] = 0xC9; ++ BOOTRAM[3489] = 0x8F; ++ BOOTRAM[3490] = 0xF0; ++ BOOTRAM[3491] = 0x02; ++ BOOTRAM[3492] = 0x04; ++ BOOTRAM[3493] = 0x57; ++ BOOTRAM[3494] = 0xEF; ++ BOOTRAM[3495] = 0x24; ++ BOOTRAM[3496] = 0x10; ++ BOOTRAM[3497] = 0xFB; ++ BOOTRAM[3498] = 0xE4; ++ BOOTRAM[3499] = 0x34; ++ BOOTRAM[3500] = 0x28; ++ BOOTRAM[3501] = 0x8B; ++ BOOTRAM[3502] = 0x82; ++ BOOTRAM[3503] = 0xF5; ++ BOOTRAM[3504] = 0x83; ++ BOOTRAM[3505] = 0xE0; ++ BOOTRAM[3506] = 0x54; ++ BOOTRAM[3507] = 0xCF; ++ BOOTRAM[3508] = 0x4D; ++ BOOTRAM[3509] = 0xFE; ++ BOOTRAM[3510] = 0xEF; ++ BOOTRAM[3511] = 0x24; ++ BOOTRAM[3512] = 0x10; ++ BOOTRAM[3513] = 0xFD; ++ BOOTRAM[3514] = 0xE4; ++ BOOTRAM[3515] = 0x34; ++ BOOTRAM[3516] = 0x28; ++ BOOTRAM[3517] = 0x8D; ++ BOOTRAM[3518] = 0x82; ++ BOOTRAM[3519] = 0xF5; ++ BOOTRAM[3520] = 0x83; ++ BOOTRAM[3521] = 0xEE; ++ BOOTRAM[3522] = 0xF0; ++ BOOTRAM[3523] = 0x22; ++ BOOTRAM[3524] = 0x7E; ++ BOOTRAM[3525] = 0x02; ++ BOOTRAM[3526] = 0x90; ++ BOOTRAM[3527] = 0x08; ++ BOOTRAM[3528] = 0x00; ++ BOOTRAM[3529] = 0x74; ++ BOOTRAM[3530] = 0x08; ++ BOOTRAM[3531] = 0xF0; ++ BOOTRAM[3532] = 0x74; ++ BOOTRAM[3533] = 0x76; ++ BOOTRAM[3534] = 0xA3; ++ BOOTRAM[3535] = 0xF0; ++ BOOTRAM[3536] = 0xEE; ++ BOOTRAM[3537] = 0xA3; ++ BOOTRAM[3538] = 0xF0; ++ BOOTRAM[3539] = 0x90; ++ BOOTRAM[3540] = 0x08; ++ BOOTRAM[3541] = 0x00; ++ BOOTRAM[3542] = 0xF0; ++ BOOTRAM[3543] = 0x90; ++ BOOTRAM[3544] = 0x08; ++ BOOTRAM[3545] = 0x05; ++ BOOTRAM[3546] = 0x74; ++ BOOTRAM[3547] = 0xFF; ++ BOOTRAM[3548] = 0xF0; ++ BOOTRAM[3549] = 0xA3; ++ BOOTRAM[3550] = 0xF0; ++ BOOTRAM[3551] = 0x22; ++ BOOTRAM[3552] = 0xAD; ++ BOOTRAM[3553] = 0x07; ++ BOOTRAM[3554] = 0xAC; ++ BOOTRAM[3555] = 0x06; ++ BOOTRAM[3556] = 0xEC; ++ BOOTRAM[3557] = 0xFF; ++ BOOTRAM[3558] = 0xAE; ++ BOOTRAM[3559] = 0x05; ++ BOOTRAM[3560] = 0x90; ++ BOOTRAM[3561] = 0x00; ++ BOOTRAM[3562] = 0x0A; ++ BOOTRAM[3563] = 0xEF; ++ BOOTRAM[3564] = 0xF0; ++ BOOTRAM[3565] = 0x90; ++ BOOTRAM[3566] = 0x00; ++ BOOTRAM[3567] = 0x09; ++ BOOTRAM[3568] = 0xEE; ++ BOOTRAM[3569] = 0xF0; ++ BOOTRAM[3570] = 0x22; ++ BOOTRAM[3571] = 0x90; ++ BOOTRAM[3572] = 0x00; ++ BOOTRAM[3573] = 0x1F; ++ BOOTRAM[3574] = 0xE0; ++ BOOTRAM[3575] = 0xFF; ++ BOOTRAM[3576] = 0x90; ++ BOOTRAM[3577] = 0x00; ++ BOOTRAM[3578] = 0x1E; ++ BOOTRAM[3579] = 0xE0; ++ BOOTRAM[3580] = 0xFD; ++ BOOTRAM[3581] = 0xEF; ++ BOOTRAM[3582] = 0xFF; ++ BOOTRAM[3583] = 0xED; ++ BOOTRAM[3584] = 0xCF; ++ BOOTRAM[3585] = 0x8F; ++ BOOTRAM[3586] = 0xF0; ++ BOOTRAM[3587] = 0x02; ++ BOOTRAM[3588] = 0x04; ++ BOOTRAM[3589] = 0x57; ++ BOOTRAM[3590] = 0x90; ++ BOOTRAM[3591] = 0x00; ++ BOOTRAM[3592] = 0x00; ++ BOOTRAM[3593] = 0xE4; ++ BOOTRAM[3594] = 0xF0; ++ BOOTRAM[3595] = 0x90; ++ BOOTRAM[3596] = 0x00; ++ BOOTRAM[3597] = 0x08; ++ BOOTRAM[3598] = 0x04; ++ BOOTRAM[3599] = 0xF0; ++ BOOTRAM[3600] = 0xE4; ++ BOOTRAM[3601] = 0xF0; ++ BOOTRAM[3602] = 0x90; ++ BOOTRAM[3603] = 0x37; ++ BOOTRAM[3604] = 0x08; ++ BOOTRAM[3605] = 0x04; ++ BOOTRAM[3606] = 0xF0; ++ BOOTRAM[3607] = 0x22; ++ BOOTRAM[3608] = 0x12; ++ BOOTRAM[3609] = 0x0E; ++ BOOTRAM[3610] = 0x80; ++ BOOTRAM[3611] = 0x12; ++ BOOTRAM[3612] = 0x0E; ++ BOOTRAM[3613] = 0x67; ++ BOOTRAM[3614] = 0x12; ++ BOOTRAM[3615] = 0x0E; ++ BOOTRAM[3616] = 0xE9; ++ BOOTRAM[3617] = 0x90; ++ BOOTRAM[3618] = 0x37; ++ BOOTRAM[3619] = 0x00; ++ BOOTRAM[3620] = 0xE4; ++ BOOTRAM[3621] = 0xF0; ++ BOOTRAM[3622] = 0x02; ++ BOOTRAM[3623] = 0x0E; ++ BOOTRAM[3624] = 0x3A; ++ BOOTRAM[3625] = 0x7E; ++ BOOTRAM[3626] = 0x00; ++ BOOTRAM[3627] = 0x74; ++ BOOTRAM[3628] = 0x17; ++ BOOTRAM[3629] = 0x90; ++ BOOTRAM[3630] = 0x10; ++ BOOTRAM[3631] = 0x2A; ++ BOOTRAM[3632] = 0xF0; ++ BOOTRAM[3633] = 0xEE; ++ BOOTRAM[3634] = 0xA3; ++ BOOTRAM[3635] = 0xF0; ++ BOOTRAM[3636] = 0x90; ++ BOOTRAM[3637] = 0x10; ++ BOOTRAM[3638] = 0x29; ++ BOOTRAM[3639] = 0x04; ++ BOOTRAM[3640] = 0xF0; ++ BOOTRAM[3641] = 0x22; ++ BOOTRAM[3642] = 0x90; ++ BOOTRAM[3643] = 0x37; ++ BOOTRAM[3644] = 0x08; ++ BOOTRAM[3645] = 0x74; ++ BOOTRAM[3646] = 0x01; ++ BOOTRAM[3647] = 0xF0; ++ BOOTRAM[3648] = 0xA3; ++ BOOTRAM[3649] = 0x04; ++ BOOTRAM[3650] = 0xF0; ++ BOOTRAM[3651] = 0x90; ++ BOOTRAM[3652] = 0x37; ++ BOOTRAM[3653] = 0x0B; ++ BOOTRAM[3654] = 0x74; ++ BOOTRAM[3655] = 0x08; ++ BOOTRAM[3656] = 0xF0; ++ BOOTRAM[3657] = 0x22; ++ BOOTRAM[3658] = 0x90; ++ BOOTRAM[3659] = 0x00; ++ BOOTRAM[3660] = 0x08; ++ BOOTRAM[3661] = 0x74; ++ BOOTRAM[3662] = 0x01; ++ BOOTRAM[3663] = 0xF0; ++ BOOTRAM[3664] = 0xE4; ++ BOOTRAM[3665] = 0xF0; ++ BOOTRAM[3666] = 0x90; ++ BOOTRAM[3667] = 0x00; ++ BOOTRAM[3668] = 0x00; ++ BOOTRAM[3669] = 0xF0; ++ BOOTRAM[3670] = 0x74; ++ BOOTRAM[3671] = 0x21; ++ BOOTRAM[3672] = 0xF0; ++ BOOTRAM[3673] = 0x22; ++ BOOTRAM[3674] = 0x12; ++ BOOTRAM[3675] = 0x0D; ++ BOOTRAM[3676] = 0xC4; ++ BOOTRAM[3677] = 0x12; ++ BOOTRAM[3678] = 0x04; ++ BOOTRAM[3679] = 0x76; ++ BOOTRAM[3680] = 0x7F; ++ BOOTRAM[3681] = 0x01; ++ BOOTRAM[3682] = 0x7E; ++ BOOTRAM[3683] = 0x00; ++ BOOTRAM[3684] = 0x02; ++ BOOTRAM[3685] = 0x0E; ++ BOOTRAM[3686] = 0x95; ++ BOOTRAM[3687] = 0x90; ++ BOOTRAM[3688] = 0x08; ++ BOOTRAM[3689] = 0x00; ++ BOOTRAM[3690] = 0x74; ++ BOOTRAM[3691] = 0x08; ++ BOOTRAM[3692] = 0xF0; ++ BOOTRAM[3693] = 0x90; ++ BOOTRAM[3694] = 0x37; ++ BOOTRAM[3695] = 0x09; ++ BOOTRAM[3696] = 0x74; ++ BOOTRAM[3697] = 0x02; ++ BOOTRAM[3698] = 0xF0; ++ BOOTRAM[3699] = 0x22; ++ BOOTRAM[3700] = 0x90; ++ BOOTRAM[3701] = 0x00; ++ BOOTRAM[3702] = 0x05; ++ BOOTRAM[3703] = 0xEF; ++ BOOTRAM[3704] = 0xF0; ++ BOOTRAM[3705] = 0xA3; ++ BOOTRAM[3706] = 0xED; ++ BOOTRAM[3707] = 0xF0; ++ BOOTRAM[3708] = 0xA3; ++ BOOTRAM[3709] = 0xEB; ++ BOOTRAM[3710] = 0xF0; ++ BOOTRAM[3711] = 0x22; ++ BOOTRAM[3712] = 0x90; ++ BOOTRAM[3713] = 0x28; ++ BOOTRAM[3714] = 0x08; ++ BOOTRAM[3715] = 0xE4; ++ BOOTRAM[3716] = 0xF0; ++ BOOTRAM[3717] = 0xA3; ++ BOOTRAM[3718] = 0xF0; ++ BOOTRAM[3719] = 0xA3; ++ BOOTRAM[3720] = 0x04; ++ BOOTRAM[3721] = 0xF0; ++ BOOTRAM[3722] = 0x22; ++ BOOTRAM[3723] = 0xEF; ++ BOOTRAM[3724] = 0x60; ++ BOOTRAM[3725] = 0x03; ++ BOOTRAM[3726] = 0x02; ++ BOOTRAM[3727] = 0x09; ++ BOOTRAM[3728] = 0x58; ++ BOOTRAM[3729] = 0x12; ++ BOOTRAM[3730] = 0x0B; ++ BOOTRAM[3731] = 0x8C; ++ BOOTRAM[3732] = 0x22; ++ BOOTRAM[3733] = 0xEF; ++ BOOTRAM[3734] = 0x90; ++ BOOTRAM[3735] = 0x28; ++ BOOTRAM[3736] = 0x08; ++ BOOTRAM[3737] = 0xF0; ++ BOOTRAM[3738] = 0xEE; ++ BOOTRAM[3739] = 0xA3; ++ BOOTRAM[3740] = 0xF0; ++ BOOTRAM[3741] = 0x22; ++ BOOTRAM[3742] = 0x90; ++ BOOTRAM[3743] = 0x81; ++ BOOTRAM[3744] = 0x83; ++ BOOTRAM[3745] = 0xEE; ++ BOOTRAM[3746] = 0xF0; ++ BOOTRAM[3747] = 0xA3; ++ BOOTRAM[3748] = 0xEF; ++ BOOTRAM[3749] = 0xF0; ++ BOOTRAM[3750] = 0x22; ++ BOOTRAM[3751] = 0x90; ++ BOOTRAM[3752] = 0x00; ++ BOOTRAM[3753] = 0x00; ++ BOOTRAM[3754] = 0xE4; ++ BOOTRAM[3755] = 0xF0; ++ BOOTRAM[3756] = 0x74; ++ BOOTRAM[3757] = 0x11; ++ BOOTRAM[3758] = 0xF0; ++ BOOTRAM[3759] = 0x22; ++ BOOTRAM[3760] = 0x90; ++ BOOTRAM[3761] = 0x00; ++ BOOTRAM[3762] = 0x00; ++ BOOTRAM[3763] = 0xE4; ++ BOOTRAM[3764] = 0xF0; ++ BOOTRAM[3765] = 0x74; ++ BOOTRAM[3766] = 0x09; ++ BOOTRAM[3767] = 0xF0; ++ BOOTRAM[3768] = 0x22; ++ BOOTRAM[3769] = 0x90; ++ BOOTRAM[3770] = 0x00; ++ BOOTRAM[3771] = 0x00; ++ BOOTRAM[3772] = 0xE4; ++ BOOTRAM[3773] = 0xF0; ++ BOOTRAM[3774] = 0x74; ++ BOOTRAM[3775] = 0x21; ++ BOOTRAM[3776] = 0xF0; ++ BOOTRAM[3777] = 0x22; ++ BOOTRAM[3778] = 0x90; ++ BOOTRAM[3779] = 0x28; ++ BOOTRAM[3780] = 0x00; ++ BOOTRAM[3781] = 0xE0; ++ BOOTRAM[3782] = 0x44; ++ BOOTRAM[3783] = 0x01; ++ BOOTRAM[3784] = 0xF0; ++ BOOTRAM[3785] = 0x22; ++ BOOTRAM[3786] = 0x90; ++ BOOTRAM[3787] = 0x28; ++ BOOTRAM[3788] = 0x00; ++ BOOTRAM[3789] = 0xE0; ++ BOOTRAM[3790] = 0x54; ++ BOOTRAM[3791] = 0xFE; ++ BOOTRAM[3792] = 0xF0; ++ BOOTRAM[3793] = 0x22; ++ BOOTRAM[3794] = 0x90; ++ BOOTRAM[3795] = 0x28; ++ BOOTRAM[3796] = 0x0B; ++ BOOTRAM[3797] = 0xE0; ++ BOOTRAM[3798] = 0x44; ++ BOOTRAM[3799] = 0xA1; ++ BOOTRAM[3800] = 0xF0; ++ BOOTRAM[3801] = 0x22; ++ BOOTRAM[3802] = 0x7C; ++ BOOTRAM[3803] = 0x00; ++ BOOTRAM[3804] = 0x7D; ++ BOOTRAM[3805] = 0x1A; ++ BOOTRAM[3806] = 0x12; ++ BOOTRAM[3807] = 0x04; ++ BOOTRAM[3808] = 0x45; ++ BOOTRAM[3809] = 0x22; ++ BOOTRAM[3810] = 0x90; ++ BOOTRAM[3811] = 0x28; ++ BOOTRAM[3812] = 0x0A; ++ BOOTRAM[3813] = 0x74; ++ BOOTRAM[3814] = 0x01; ++ BOOTRAM[3815] = 0xF0; ++ BOOTRAM[3816] = 0x22; ++ BOOTRAM[3817] = 0x90; ++ BOOTRAM[3818] = 0x10; ++ BOOTRAM[3819] = 0x29; ++ BOOTRAM[3820] = 0x74; ++ BOOTRAM[3821] = 0x04; ++ BOOTRAM[3822] = 0xF0; ++ BOOTRAM[3823] = 0x22; ++ BOOTRAM[3824] = 0x3F; ++ BOOTRAM[3825] = 0x78; ++ BOOTRAM[3826] = 0x7D; ++ BOOTRAM[3827] = 0x01; ++ return BOOTRAM; ++} ++ ++EXPORT_SYMBOL(load_data_init); ++ +diff --git a/arch/arm/plat-goke/sd.c b/arch/arm/plat-goke/sd.c +new file mode 100644 +index 00000000..5c06c7e3 +--- /dev/null ++++ b/arch/arm/plat-goke/sd.c +@@ -0,0 +1,1196 @@ ++/* ++ * arch/arm/mach-gk/generic/sd.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* ==========================================================================*/ ++#ifdef MODULE_PARAM_PREFIX ++#undef MODULE_PARAM_PREFIX ++#endif ++#define MODULE_PARAM_PREFIX "gk_config." ++ ++extern u64 gk_dmamask; ++ ++/* ==========================================================================*/ ++typedef void (*mmc_dc_fn)(struct mmc_host *host, unsigned long delay); ++ ++static DEFINE_SPINLOCK(gk_sd0_int_lock); ++static u32 gk_sd0_int = 0; ++static u32 gk_sdio0_int = 0; ++#ifdef CONFIG_GK710XS_SDIO2 ++static DEFINE_SPINLOCK(gk_sd1_int_lock); ++static u32 gk_sd1_int = 0; ++static u32 gk_sdio1_int = 0; ++#endif ++ ++/*----------------------------------------------------------------------------*/ ++/* registers */ ++/*----------------------------------------------------------------------------*/ ++ ++/* ==========================================================================*/ ++struct resource gk_sd0_resources[] = { ++ [0] = { ++ .start = GK_VA_SDC, ++ .end = GK_VA_SDC + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SD_IRQ, ++ .end = SD_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++void gk_sd0_slot1_request(void) ++{ ++ return; ++} ++ ++void gk_sd0_slot1_release(void) ++{ ++ //fio_unlock(SELECT_FIO_SD); ++ return; ++} ++ ++#if (SD_HAS_INTERNAL_MUXER == 1) ++void gk_sd_slot2_request(void) ++{ ++ //fio_select_lock(SELECT_FIO_SDIO); ++ return; ++} ++ ++void gk_sd_slot2_release(void) ++{ ++ //fio_unlock(SELECT_FIO_SDIO); ++ return; ++} ++#endif ++ ++int gk_sd0_is_enable(void) ++{ ++ return 1; ++} ++ ++void gk_sd0_set_int(u32 mask, u32 on) ++{ ++ unsigned long flags; ++ u32 int_flag; ++ ++ spin_lock_irqsave(&gk_sd0_int_lock, flags); ++ int_flag = gk_sd_readw(SD_NISEN_REG); ++ int_flag |= (gk_sd_readw(SD_EISEN_REG) << 16); ++ if (on) ++ int_flag |= mask; ++ else ++ int_flag &= ~mask; ++ gk_sd0_int = int_flag; ++ if (gk_sd0_is_enable()) { ++ gk_sd_writew(SD_NISEN_REG, int_flag); ++ gk_sd_writew(SD_EISEN_REG, int_flag >> 16); ++ gk_sd_writew(SD_NIXEN_REG, int_flag); ++ gk_sd_writew(SD_EIXEN_REG, int_flag >> 16); ++ } ++ spin_unlock_irqrestore(&gk_sd0_int_lock, flags); ++ return; ++} ++ ++int gk_sdio_is_enable(void) ++{ ++ return 1; ++} ++ ++void gk_sdio_set_int(u32 mask, u32 on) ++{ ++ unsigned long flags; ++ u32 int_flag; ++ ++ spin_lock_irqsave(&gk_sd0_int_lock, flags); ++ int_flag = gk_sd_readw(SD_NISEN_REG); ++ int_flag |= (gk_sd_readw(SD_EISEN_REG) << 16); ++ if (on) ++ int_flag |= mask; ++ else ++ int_flag &= ~mask; ++ gk_sdio0_int = int_flag; ++ if (gk_sdio_is_enable()) { ++ gk_sd_writew(SD_NISEN_REG, int_flag); ++ gk_sd_writew(SD_EISEN_REG, int_flag >> 16); ++ gk_sd_writew(SD_NIXEN_REG, int_flag); ++ gk_sd_writew(SD_EIXEN_REG, int_flag >> 16); ++ } ++ spin_unlock_irqrestore(&gk_sd0_int_lock, flags); ++} ++ ++struct gk_sd_controller gk_sd_controller0 = { ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .num_slots = 1, ++#else ++ .num_slots = 1, ++#endif ++ .slot[0] = { ++ .pmmc_host = NULL, ++ ++ .default_caps = MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SDIO_IRQ | ++ MMC_CAP_ERASE | ++ MMC_CAP_BUS_WIDTH_TEST, ++ .active_caps = 0, ++ .default_caps2 = 0, ++ .active_caps2 = 0, ++ .private_caps = GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK, ++ ++ .ext_power = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .ext_reset = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .fixed_cd = -1, ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = SDCD_IRQ, ++ .irq_type = IRQ_TYPE_EDGE_BOTH, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_TYPE_INPUT_SD_CD_N, ++ }, ++#else ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = -1, ++ .irq_type = -1, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_FUNC_SW_INPUT, ++ }, ++#endif ++ .cd_delay = 100, ++ .fixed_wp = -1, ++ .gpio_wp = { ++ .gpio_id = -1, ++ .active_level = GPIO_HIGH, ++ .active_delay = 1, ++ }, ++ ++ .check_owner = gk_sd0_is_enable, ++ .request = gk_sd0_slot1_request, ++ .release = gk_sd0_slot1_release, ++ .set_int = gk_sd0_set_int, ++ .set_vdd = NULL, ++ .set_bus_timing = NULL, ++ }, ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .slot[1] = { ++ .pmmc_host = NULL, ++ ++ .default_caps = MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SDIO_IRQ | ++ MMC_CAP_ERASE | ++ MMC_CAP_BUS_WIDTH_TEST, ++ .active_caps = 0, ++ .default_caps2 = 0, ++ .active_caps2 = 0, ++ .private_caps = GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK, ++ ++ .ext_power = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .ext_reset = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .fixed_cd = -1, ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = -1, ++ .irq_type = -1, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_FUNC_SW_INPUT, ++ }, ++ .cd_delay = 100, ++ .fixed_wp = -1, ++ .gpio_wp = { ++ .gpio_id = -1, ++ .active_level = GPIO_HIGH, ++ .active_delay = 1, ++ }, ++ ++ .check_owner = gk_sdio_is_enable, ++ .request = gk_sd_slot2_request, ++ .release = gk_sd_slot2_release, ++ .set_int = gk_sdio_set_int, ++ .set_vdd = NULL, ++ .set_bus_timing = NULL, ++ }, ++#endif ++ .set_pll = set_sd_rct, ++ .get_pll = get_sd_freq_hz, ++ ++ .max_blk_mask = SD_BLK_SZ_64KB, /*SD_BLK_SZ_128KB*/ ++ .max_clock = 48000000, ++ .active_clock = 0, ++ .wait_tmo = ((5 * HZ) / 2), ++ .pwr_delay = 1, ++ ++ .dma_fix = 0, ++#if (SD_SUPPORT_PLL_SCALER == 1) ++ .support_pll_scaler = 1, ++#else ++ .support_pll_scaler = 0, ++#endif ++}; ++ ++ ++struct platform_device gk_sd0 = { ++ .name = "gk-sd", ++ .id = 0, ++ .resource = gk_sd0_resources, ++ .num_resources = ARRAY_SIZE(gk_sd0_resources), ++ .dev = { ++ .platform_data = &gk_sd_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++#ifdef CONFIG_GK710XS_SDIO2 ++struct resource gk_sd1_resources[] = { ++ [0] = { ++ .start = GK_VA_SDC1, ++ .end = GK_VA_SDC1 + 0x0FFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = SD1_IRQ, ++ .end = SD1_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++void gk_sd1_slot1_request(void) ++{ ++ return; ++} ++ ++void gk_sd1_slot1_release(void) ++{ ++ //fio_unlock(SELECT_FIO_SD); ++ return; ++} ++ ++#if (SD_HAS_INTERNAL_MUXER == 1) ++void gk_sd1_slot2_request(void) ++{ ++ //fio_select_lock(SELECT_FIO_SDIO); ++ return; ++} ++ ++void gk_sd1_slot2_release(void) ++{ ++ //fio_unlock(SELECT_FIO_SDIO); ++ return; ++} ++#endif ++ ++int gk_sd1_is_enable(void) ++{ ++ return 1; ++} ++ ++void gk_sd1_set_int(u32 mask, u32 on) ++{ ++ unsigned long flags; ++ u32 int_flag; ++ ++ spin_lock_irqsave(&gk_sd1_int_lock, flags); ++ int_flag = gk_sd_readw(SD1_NISEN_REG); ++ int_flag |= (gk_sd_readw(SD1_EISEN_REG) << 16); ++ if (on) ++ int_flag |= mask; ++ else ++ int_flag &= ~mask; ++ gk_sd1_int = int_flag; ++ if (gk_sd1_is_enable()) { ++ gk_sd_writew(SD1_NISEN_REG, int_flag); ++ gk_sd_writew(SD1_EISEN_REG, int_flag >> 16); ++ gk_sd_writew(SD1_NIXEN_REG, int_flag); ++ gk_sd_writew(SD1_EIXEN_REG, int_flag >> 16); ++ } ++ spin_unlock_irqrestore(&gk_sd1_int_lock, flags); ++ return; ++} ++ ++int gk_sdio2_is_enable(void) ++{ ++ return 1; ++} ++ ++void gk_sdio2_set_int(u32 mask, u32 on) ++{ ++ unsigned long flags; ++ u32 int_flag; ++ ++ spin_lock_irqsave(&gk_sd1_int_lock, flags); ++ int_flag = gk_sd_readw(SD1_NISEN_REG); ++ int_flag |= (gk_sd_readw(SD1_EISEN_REG) << 16); ++ if (on) ++ int_flag |= mask; ++ else ++ int_flag &= ~mask; ++ gk_sdio1_int = int_flag; ++ if (gk_sdio2_is_enable()) { ++ gk_sd_writew(SD1_NISEN_REG, int_flag); ++ gk_sd_writew(SD1_EISEN_REG, int_flag >> 16); ++ gk_sd_writew(SD1_NIXEN_REG, int_flag); ++ gk_sd_writew(SD1_EIXEN_REG, int_flag >> 16); ++ } ++ spin_unlock_irqrestore(&gk_sd1_int_lock, flags); ++} ++ ++struct gk_sd_controller gk_sd1_controller0 = { ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .num_slots = 1, ++#else ++ .num_slots = 1, ++#endif ++ .slot[0] = { ++ .pmmc_host = NULL, ++ ++ .default_caps = MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SDIO_IRQ | ++ MMC_CAP_ERASE | ++ MMC_CAP_BUS_WIDTH_TEST, ++ .active_caps = 0, ++ .default_caps2 = 0, ++ .active_caps2 = 0, ++ .private_caps = GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK, ++ ++ .ext_power = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .ext_reset = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .fixed_cd = -1, ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = SD1CD_IRQ, ++ .irq_type = IRQ_TYPE_EDGE_BOTH, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_FUNC_HW, ++ }, ++#else ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = -1, ++ .irq_type = -1, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_TYPE_INPUT_SD_CD_N, ++ }, ++#endif ++ .cd_delay = 100, ++ .fixed_wp = -1, ++ .gpio_wp = { ++ .gpio_id = -1, ++ .active_level = GPIO_HIGH, ++ .active_delay = 1, ++ }, ++ ++ .check_owner = gk_sd1_is_enable, ++ .request = gk_sd1_slot1_request, ++ .release = gk_sd1_slot1_release, ++ .set_int = gk_sd1_set_int, ++ .set_vdd = NULL, ++ .set_bus_timing = NULL, ++ }, ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ .slot[1] = { ++ .pmmc_host = NULL, ++ ++ .default_caps = MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SDIO_IRQ | ++ MMC_CAP_ERASE | ++ MMC_CAP_BUS_WIDTH_TEST, ++ .active_caps = 0, ++ .default_caps2 = 0, ++ .active_caps2 = 0, ++ .private_caps = GK_SD_PRIVATE_CAPS_DTO_BY_SDCLK, ++ ++ .ext_power = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .ext_reset = { ++ .gpio_id = -1, ++ .active_level = GPIO_LOW, ++ .active_delay = 1, ++ }, ++ .fixed_cd = -1, ++ .gpio_cd = { ++ .irq_gpio = -1, ++ .irq_line = -1, ++ .irq_type = -1, ++ .irq_gpio_val = GPIO_LOW, ++ .irq_gpio_mode = GPIO_FUNC_SW_INPUT, ++ }, ++ .cd_delay = 100, ++ .fixed_wp = -1, ++ .gpio_wp = { ++ .gpio_id = -1, ++ .active_level = GPIO_HIGH, ++ .active_delay = 1, ++ }, ++ ++ .check_owner = gk_sdio2_is_enable, ++ .request = gk_sd1_slot2_request, ++ .release = gk_sd1_slot2_release, ++ .set_int = gk_sdio2_set_int, ++ .set_vdd = NULL, ++ .set_bus_timing = NULL, ++ }, ++#endif ++ .set_pll = set_sd_rct, ++ .get_pll = get_sd_freq_hz, ++ ++ .max_blk_mask = SD_BLK_SZ_64KB, /*SD_BLK_SZ_128KB*/ ++ .max_clock = 24000000, ++ .active_clock = 0, ++ .wait_tmo = ((5 * HZ) / 2), ++ .pwr_delay = 1, ++ ++ .dma_fix = 0, ++#if (SD_SUPPORT_PLL_SCALER == 1) ++ .support_pll_scaler = 1, ++#else ++ .support_pll_scaler = 0, ++#endif ++}; ++ ++ ++struct platform_device gk_sd1 = { ++ .name = "gk-sd", ++ .id = 1, ++ .resource = gk_sd1_resources, ++ .num_resources = ARRAY_SIZE(gk_sd1_resources), ++ .dev = { ++ .platform_data = &gk_sd1_controller0, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++typedef union { /* SDIO_Control01Reg */ ++ u8 all; ++ struct { ++ u8 datatimeoutcountervalue : 4; ++ u8 : 4; ++ } bitc; ++} GH_SDIO_TMO_S; ++ ++typedef union { /* SDIO_Control01Reg */ ++ u8 all; ++ struct { ++ u8 softwareresetcmdline : 1; ++ u8 softwareresetall : 1; ++ u8 softwareresetdatline : 1; ++ u8 : 5; ++ } bitc; ++} GH_SDIO_RST_S; ++ ++typedef union { /* SDIO_Control01Reg */ ++ u16 all; ++ struct { ++ u16 internalclken : 1; ++ u16 internalclkstable : 1; ++ u16 sdclken : 1; ++ u16 : 5; ++ u16 sdclkfreselect : 8; ++ } bitc; ++} GH_SDIO_CLK_S; ++ ++typedef union { /* SDIO_Control00Reg */ ++ u8 all; ++ struct { ++ u8 ledcontrol : 1; ++ u8 datatrawidth : 1; ++ u8 sd8bitmode : 1; ++ u8 hostspeeden : 1; ++ u8 : 2; ++ u8 carddetecttestlevel : 1; ++ u8 carddetectsigdet : 1; ++ } bitc; ++} GH_SDIO_HOST_S; ++ ++typedef union { /* SDIO_Control00Reg */ ++ u8 all; ++ struct { ++ u8 sdbuspower : 1; ++ u8 sdbusvoltageselect : 3; ++ u8 : 4; ++ } bitc; ++} GH_SDIO_PWR_S; ++ ++void GH_SDIO_set_Control01Reg_SoftwareResetAll(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD_RESET_REG); ++ d.bitc.softwareresetall = data; ++ gk_sd_writeb(SD_RESET_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_SoftwareResetCmdLine(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD_RESET_REG); ++ d.bitc.softwareresetcmdline = data; ++ gk_sd_writeb(SD_RESET_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_SoftwareResetDatLine(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD_RESET_REG); ++ d.bitc.softwareresetdatline = data; ++ gk_sd_writeb(SD_RESET_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_SdClkEn(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD_CLK_REG); ++ d.bitc.sdclken = data; ++ gk_sd_writew(SD_CLK_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_SdclkFreSelect(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD_CLK_REG); ++ d.bitc.sdclkfreselect = data; ++ gk_sd_writew(SD_CLK_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_InternalClkEn(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD_CLK_REG); ++ d.bitc.internalclken = data; ++ gk_sd_writew(SD_CLK_REG, d.all); ++} ++ ++u16 GH_SDIO_get_Control01Reg(void) ++{ ++ u16 value = gk_sd_readw(SD_CLK_REG); ++ ++ return value; ++} ++ ++void GH_SDIO_set_Control00Reg_SdBusVoltageSelect(u8 data) ++{ ++ GH_SDIO_PWR_S d; ++ d.all = gk_sd_readb(SD_PWR_REG); ++ d.bitc.sdbusvoltageselect = data; ++ gk_sd_writeb(SD_PWR_REG, d.all); ++} ++ ++u32 GH_SDIO_get_CapReg(void) ++{ ++ u32 value = gk_sd_readl(SD_CAP_REG); ++ return value; ++} ++ ++void GH_SDIO_set_Control00Reg_SdBusPower(u8 data) ++{ ++ GH_SDIO_PWR_S d; ++ d.all = gk_sd_readb(SD_PWR_REG); ++ d.bitc.sdbuspower = data; ++ gk_sd_writeb(SD_PWR_REG, d.all); ++} ++ ++void GH_SDIO_set_Control01Reg_DataTimeoutCounterValue(u8 data) ++{ ++ GH_SDIO_TMO_S d; ++ d.all = gk_sd_readb(SD_TMO_REG); ++ d.bitc.datatimeoutcountervalue = data; ++ gk_sd_writeb(SD_TMO_REG, d.all); ++} ++ ++void GH_SDIO_set_Control00Reg_HostSpeedEn(u8 data) ++{ ++ GH_SDIO_HOST_S d; ++ d.all = gk_sd_readb(SD_HOST_REG); ++ d.bitc.hostspeeden = data; ++ gk_sd_writeb(SD_HOST_REG, d.all); ++} ++ ++void GH_SDIO_set_Control00Reg_DataTraWidth(u8 data) ++{ ++ GH_SDIO_HOST_S d; ++ d.all = gk_sd_readb(SD_HOST_REG); ++ d.bitc.datatrawidth = data; ++ gk_sd_writeb(SD_HOST_REG, d.all); ++} ++ ++void GH_SDIO_set_NorIntStatusReg(u16 data) ++{ ++ gk_sd_writew(SD_NIS_REG, data); ++} ++ ++u16 GH_SDIO_get_NorIntStatusReg(void) ++{ ++ u16 value = gk_sd_readw(SD_NIS_REG); ++ return value; ++} ++ ++void GH_SDIO_set_ErrIntStatusReg(u16 data) ++{ ++ gk_sd_writew(SD_EIS_REG, data); ++} ++ ++u16 GH_SDIO_get_ErrIntStatusReg(void) ++{ ++ u16 value = gk_sd_readw(SD_EIS_REG); ++ return value; ++} ++ ++void GH_SDIO_set_NorIntStatusEnReg(u16 data) ++{ ++ gk_sd_writew(SD_NISEN_REG, data); ++} ++ ++void GH_SDIO_set_ErrIntStatusEnReg(u16 data) ++{ ++ gk_sd_writew(SD_EISEN_REG, data); ++} ++ ++void GH_SDIO_set_NorIntSigEnReg(u16 data) ++{ ++ gk_sd_writew(SD_NIXEN_REG, data); ++} ++ ++void GH_SDIO_set_ErrIntSigEnReg(u16 data) ++{ ++ gk_sd_writew(SD_EIXEN_REG, data); ++} ++ ++#ifdef CONFIG_GK710XS_SDIO2 ++void GH_SDIO1_set_Control01Reg_SoftwareResetAll(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD1_RESET_REG); ++ d.bitc.softwareresetall = data; ++ gk_sd_writeb(SD1_RESET_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_SoftwareResetCmdLine(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD1_RESET_REG); ++ d.bitc.softwareresetcmdline = data; ++ gk_sd_writeb(SD1_RESET_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_SoftwareResetDatLine(u8 data) ++{ ++ GH_SDIO_RST_S d; ++ d.all = gk_sd_readb(SD1_RESET_REG); ++ d.bitc.softwareresetdatline = data; ++ gk_sd_writeb(SD1_RESET_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_SdClkEn(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD1_CLK_REG); ++ d.bitc.sdclken = data; ++ gk_sd_writew(SD1_CLK_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_SdclkFreSelect(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD1_CLK_REG); ++ d.bitc.sdclkfreselect = data; ++ gk_sd_writew(SD1_CLK_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_InternalClkEn(u8 data) ++{ ++ GH_SDIO_CLK_S d; ++ d.all = gk_sd_readw(SD1_CLK_REG); ++ d.bitc.internalclken = data; ++ gk_sd_writew(SD1_CLK_REG, d.all); ++} ++ ++u16 GH_SDIO1_get_Control01Reg(void) ++{ ++ u16 value = gk_sd_readw(SD1_CLK_REG); ++ ++ return value; ++} ++ ++void GH_SDIO1_set_Control00Reg_SdBusVoltageSelect(u8 data) ++{ ++ GH_SDIO_PWR_S d; ++ d.all = gk_sd_readb(SD1_PWR_REG); ++ d.bitc.sdbusvoltageselect = data; ++ gk_sd_writeb(SD1_PWR_REG, d.all); ++} ++ ++u32 GH_SDIO1_get_CapReg(void) ++{ ++ u32 value = gk_sd_readl(SD1_CAP_REG); ++ return value; ++} ++ ++void GH_SDIO1_set_Control00Reg_SdBusPower(u8 data) ++{ ++ GH_SDIO_PWR_S d; ++ d.all = gk_sd_readb(SD1_PWR_REG); ++ d.bitc.sdbuspower = data; ++ gk_sd_writeb(SD1_PWR_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control01Reg_DataTimeoutCounterValue(u8 data) ++{ ++ GH_SDIO_TMO_S d; ++ d.all = gk_sd_readb(SD1_TMO_REG); ++ d.bitc.datatimeoutcountervalue = data; ++ gk_sd_writeb(SD1_TMO_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control00Reg_HostSpeedEn(u8 data) ++{ ++ GH_SDIO_HOST_S d; ++ d.all = gk_sd_readb(SD1_HOST_REG); ++ d.bitc.hostspeeden = data; ++ gk_sd_writeb(SD1_HOST_REG, d.all); ++} ++ ++void GH_SDIO1_set_Control00Reg_DataTraWidth(u8 data) ++{ ++ GH_SDIO_HOST_S d; ++ d.all = gk_sd_readb(SD1_HOST_REG); ++ d.bitc.datatrawidth = data; ++ gk_sd_writeb(SD1_HOST_REG, d.all); ++} ++ ++void GH_SDIO1_set_NorIntStatusReg(u16 data) ++{ ++ gk_sd_writew(SD1_NIS_REG, data); ++} ++ ++u16 GH_SDIO1_get_NorIntStatusReg(void) ++{ ++ u16 value = gk_sd_readw(SD1_NIS_REG); ++ return value; ++} ++ ++void GH_SDIO1_set_ErrIntStatusReg(u16 data) ++{ ++ gk_sd_writew(SD1_EIS_REG, data); ++} ++ ++u16 GH_SDIO1_get_ErrIntStatusReg(void) ++{ ++ u16 value = gk_sd_readw(SD1_EIS_REG); ++ return value; ++} ++ ++void GH_SDIO1_set_NorIntStatusEnReg(u16 data) ++{ ++ gk_sd_writew(SD1_NISEN_REG, data); ++} ++ ++void GH_SDIO1_set_ErrIntStatusEnReg(u16 data) ++{ ++ gk_sd_writew(SD1_EISEN_REG, data); ++} ++ ++void GH_SDIO1_set_NorIntSigEnReg(u16 data) ++{ ++ gk_sd_writew(SD1_NIXEN_REG, data); ++} ++ ++void GH_SDIO1_set_ErrIntSigEnReg(u16 data) ++{ ++ gk_sd_writew(SD1_EIXEN_REG, data); ++} ++ ++void gk_set_sd1_detect_pin(u32 gpio_pin) ++{ ++ gk_sd1_controller0.slot[0].gpio_cd.irq_gpio = gpio_pin; ++} ++ ++#endif ++ ++static void sdioSoftReset(u8 index) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_Control01Reg_SoftwareResetAll(1); ++ GH_SDIO_set_Control01Reg_SoftwareResetCmdLine(1); ++ GH_SDIO_set_Control01Reg_SoftwareResetDatLine(1); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index ==1) ++ { ++ GH_SDIO1_set_Control01Reg_SoftwareResetAll(1); ++ GH_SDIO1_set_Control01Reg_SoftwareResetCmdLine(1); ++ GH_SDIO1_set_Control01Reg_SoftwareResetDatLine(1); ++ } ++#endif ++} ++ ++static void sdioClockOnOff(u8 index, u32 on) ++{ ++ if(index == 0) ++ { ++ if (on == 0) ++ { ++ GH_SDIO_set_Control01Reg_SdClkEn(0); ++ } ++ else ++ { ++ GH_SDIO_set_Control01Reg_SdClkEn(1); ++ } ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ if (on == 0) ++ { ++ GH_SDIO1_set_Control01Reg_SdClkEn(0); ++ } ++ else ++ { ++ GH_SDIO1_set_Control01Reg_SdClkEn(1); ++ } ++ } ++#endif ++} ++ ++static void sdioSelectVoltage(u8 index) ++{ ++ u32 caps; ++ if(index == 0) ++ { ++ caps=GH_SDIO_get_CapReg(); ++ ++ if(caps & 0x1<<24) ++ { ++ GH_SDIO_set_Control00Reg_SdBusVoltageSelect(0x7); ++ GH_SDIO_set_Control00Reg_SdBusPower(1); ++ ++ } ++ else if(caps & 0x1<<25) ++ { ++ GH_SDIO_set_Control00Reg_SdBusVoltageSelect(0x6); ++ GH_SDIO_set_Control00Reg_SdBusPower(1); ++ } ++ else if(caps & 0x1<<26) ++ { ++ GH_SDIO_set_Control00Reg_SdBusVoltageSelect(0x5); ++ GH_SDIO_set_Control00Reg_SdBusPower(1); ++ } ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ caps=GH_SDIO1_get_CapReg(); ++ ++ if(caps & 0x1<<24) ++ { ++ GH_SDIO1_set_Control00Reg_SdBusVoltageSelect(0x7); ++ GH_SDIO1_set_Control00Reg_SdBusPower(1); ++ ++ } ++ else if(caps & 0x1<<25) ++ { ++ GH_SDIO1_set_Control00Reg_SdBusVoltageSelect(0x6); ++ GH_SDIO1_set_Control00Reg_SdBusPower(1); ++ } ++ else if(caps & 0x1<<26) ++ { ++ GH_SDIO1_set_Control00Reg_SdBusVoltageSelect(0x5); ++ GH_SDIO1_set_Control00Reg_SdBusPower(1); ++ } ++ } ++#endif ++} ++ ++static void sdioSetClockDiv(u8 index, u8 div) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_Control01Reg_SdclkFreSelect(div); ++ GH_SDIO_set_Control01Reg_InternalClkEn(1); ++ ++ while(1) ++ { ++ if((GH_SDIO_get_Control01Reg() & (0x1<<1))) ++ break; ++ } ++ sdioClockOnOff(index, 1); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_Control01Reg_SdclkFreSelect(div); ++ GH_SDIO1_set_Control01Reg_InternalClkEn(1); ++ ++ while(1) ++ { ++ if((GH_SDIO1_get_Control01Reg() & (0x1<<1))) ++ break; ++ } ++ sdioClockOnOff(index, 1); ++ } ++#endif ++} ++ ++static void sdioSetTimeoutControl(u8 index, u8 timeout) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_Control01Reg_DataTimeoutCounterValue(timeout); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_Control01Reg_DataTimeoutCounterValue(timeout); ++ } ++#endif ++} ++ ++static void sdioSetHostctlSpeed(u8 index, u8 mode) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_Control00Reg_HostSpeedEn(mode); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_Control00Reg_HostSpeedEn(mode); ++ } ++#endif ++} ++ ++static void sdioSetHostctlWidth(u8 index, u8 mode) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_Control00Reg_DataTraWidth(mode); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_Control00Reg_DataTraWidth(mode); ++ } ++#endif ++} ++ ++#define SDIO_INT_STATUS_EN (1 | 1<<1 | 1<<3 | 1<<4 |1<<5 | 1<<6 | 1<<7) ++#define SDIO_INT_SIG_EN (1 | 1<<1 | 1<<3 | 1<<4 |1<<5 | 1<<6 | 1<<7) ++static void sdioEnableIntStatus(u8 index) ++{ ++ /*clear int*/ ++ if(index == 0) ++ { ++ if(GH_SDIO_get_NorIntStatusReg() & (0x1 << 15)) ++ { ++ GH_SDIO_set_ErrIntStatusReg(GH_SDIO_get_ErrIntStatusReg()); ++ } ++ ++ GH_SDIO_set_NorIntStatusEnReg(0x0); ++ GH_SDIO_set_NorIntStatusEnReg(SDIO_INT_STATUS_EN); ++ GH_SDIO_set_ErrIntStatusEnReg(0xffff); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ if(GH_SDIO1_get_NorIntStatusReg() & (0x1 << 15)) ++ { ++ GH_SDIO1_set_ErrIntStatusReg(GH_SDIO1_get_ErrIntStatusReg()); ++ } ++ ++ GH_SDIO1_set_NorIntStatusEnReg(0x0); ++ GH_SDIO1_set_NorIntStatusEnReg(SDIO_INT_STATUS_EN); ++ GH_SDIO1_set_ErrIntStatusEnReg(0xffff); ++ } ++#endif ++} ++ ++static void sdioEnableIntSig(u8 index) ++{ ++ if(index == 0) ++ { ++ GH_SDIO_set_NorIntSigEnReg(0); ++ GH_SDIO_set_NorIntSigEnReg(SDIO_INT_SIG_EN); ++ GH_SDIO_set_ErrIntSigEnReg(0xffff); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_NorIntSigEnReg(0); ++ GH_SDIO1_set_NorIntSigEnReg(SDIO_INT_SIG_EN); ++ GH_SDIO1_set_ErrIntSigEnReg(0xffff); ++ } ++#endif ++} ++ ++static void GD_SDIO_Rest(u8 index) ++{ ++ sdioSoftReset(index); ++ sdioClockOnOff(index, 0); ++ sdioSetClockDiv(index, 0x00); ++ sdioSelectVoltage(index); ++ sdioSetTimeoutControl(index, 0xe); ++ sdioSetHostctlSpeed(index, 0); ++ sdioSetHostctlWidth(index, 1); ++ /*clear interrupt status*/ ++ if(index == 0) ++ { ++ GH_SDIO_set_NorIntStatusReg(GH_SDIO_get_NorIntStatusReg()); ++ GH_SDIO_set_ErrIntStatusReg(GH_SDIO_get_ErrIntStatusReg()); ++ } ++#ifdef CONFIG_GK710XS_SDIO2 ++ else if(index == 1) ++ { ++ GH_SDIO1_set_NorIntStatusReg(GH_SDIO1_get_NorIntStatusReg()); ++ GH_SDIO1_set_ErrIntStatusReg(GH_SDIO1_get_ErrIntStatusReg()); ++ } ++#endif ++ sdioEnableIntStatus(index); ++ sdioEnableIntSig(index); ++} ++ ++int __init gk_init_sd(void) ++{ ++ int retval = 0; ++ ++ GD_SDIO_Rest(0); ++#ifdef CONFIG_GK710XS_SDIO2 ++ GD_SDIO_Rest(1); ++#endif ++ return retval; ++} ++ ++void gk_set_sd_detect_pin(u32 gpio_pin) ++{ ++ gk_sd_controller0.slot[0].gpio_cd.irq_gpio = gpio_pin; ++} ++ ++void gk_detect_sd_slot(int bus, int slot, int fixed_cd) ++{ ++ struct gk_sd_slot *pslotinfo = NULL; ++ mmc_dc_fn mmc_dc = NULL; ++ ++ printk("%s:%d[%d:%d:%d]\n", __func__, __LINE__, bus, slot, fixed_cd); ++ if ((bus == 0) && (slot == 0)) { ++ pslotinfo = &gk_sd_controller0.slot[0]; ++ } ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ if ((bus == 0) && (slot == 1)) { ++ pslotinfo = &gk_sd_controller0.slot[1]; ++ } ++#endif ++ ++ ++#if defined(CONFIG_MMC) ++ mmc_dc = mmc_detect_change; ++#else ++#if defined(CONFIG_KALLSYMS) ++ mmc_dc = (mmc_dc_fn)module_kallsyms_lookup_name("mmc_detect_change"); ++#endif ++#endif ++ if (pslotinfo && mmc_dc && pslotinfo->pmmc_host) { ++ pslotinfo->fixed_cd = fixed_cd; ++ mmc_dc(pslotinfo->pmmc_host, pslotinfo->cd_delay); ++ printk("%s:%d[%p:%p:%p:%d]\n", __func__, __LINE__, pslotinfo, ++ mmc_dc, pslotinfo->pmmc_host, pslotinfo->cd_delay); ++ } ++} ++EXPORT_SYMBOL(gk_detect_sd_slot); ++ ++#ifdef CONFIG_GK710XS_SDIO2 ++void gk_detect_sd1_slot(int bus, int slot, int fixed_cd) ++{ ++ struct gk_sd_slot *pslotinfo = NULL; ++ mmc_dc_fn mmc_dc = NULL; ++ ++ printk("%s:%d[%d:%d:%d]\n", __func__, __LINE__, bus, slot, fixed_cd); ++ if ((bus == 0) && (slot == 0)) { ++ pslotinfo = &gk_sd1_controller0.slot[0]; ++ } ++#if (SD_HAS_INTERNAL_MUXER == 1) ++ if ((bus == 0) && (slot == 1)) { ++ pslotinfo = &gk_sd1_controller0.slot[1]; ++ } ++#endif ++ ++ ++#if defined(CONFIG_MMC) ++ mmc_dc = mmc_detect_change; ++#else ++#if defined(CONFIG_KALLSYMS) ++ mmc_dc = (mmc_dc_fn)module_kallsyms_lookup_name("mmc_detect_change"); ++#endif ++#endif ++ if (pslotinfo && mmc_dc && pslotinfo->pmmc_host) { ++ pslotinfo->fixed_cd = fixed_cd; ++ mmc_dc(pslotinfo->pmmc_host, pslotinfo->cd_delay); ++ printk("%s:%d[%p:%p:%p:%d]\n", __func__, __LINE__, pslotinfo, ++ mmc_dc, pslotinfo->pmmc_host, pslotinfo->cd_delay); ++ } ++} ++EXPORT_SYMBOL(gk_detect_sd1_slot); ++#endif ++ ++ +diff --git a/arch/arm/plat-goke/switch.c b/arch/arm/plat-goke/switch.c +new file mode 100644 +index 00000000..9523784a +--- /dev/null ++++ b/arch/arm/plat-goke/switch.c +@@ -0,0 +1,495 @@ ++/*! ++***************************************************************************** ++** \file arch/arm/mach-gk/switch.c ++** ++** \version ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++ ++ ++#define GK_USB_SWITCH_NAME "usb_switch" ++#define GK_AUDIO_SWITCH_NAME "audio_switch" ++#define GK_CVBS_SWITCH_NAME "cvbs_switch" ++#define GK_PHY_SWITCH_NAME "phy_switch" ++#define GK_ADC_SWITCH_NAME "adc_switch" ++#define BUFER_COUNT 50 ++#define CHECK_COUNT {if(count>=(BUFER_COUNT-1))count=(BUFER_COUNT-1);} ++ ++static u8 usb_status = 1; ++static int usb_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ int len = 0; ++ ++ if (off) ++ { ++ *eof = 1; ++ return ret; ++ } ++ ++ len = sprintf(page, "%s\n", usb_status==0?"off":"on"); ++ ++ return len; ++} ++ ++static int usb_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[BUFER_COUNT]; ++ ++ CHECK_COUNT; ++ if (copy_from_user(buf, buffer, count)) { ++ retval = -EFAULT; ++ } ++ ++ switch(buf[0]) ++ { ++ case '0': ++ usb_status = 0; ++ gk_usb_setbitsl(GK_VA_USB_PHY, 0x0000FFC4); ++ break; ++ case '1': ++ usb_status = 1; ++ gk_usb_clrbitsl(GK_VA_USB_PHY, 0x0000FFC4); ++ break; ++ } ++ return count; ++} ++ ++static int create_usb_proc_node(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *usb_entry; ++ ++ usb_entry = create_proc_entry(GK_USB_SWITCH_NAME, S_IRUGO | S_IWUGO, get_gk_proc_dir()); ++ ++ if (!usb_entry) ++ { ++ err_code = -EINVAL; ++ } ++ else ++ { ++ usb_entry->read_proc = usb_read_proc; ++ usb_entry->write_proc = usb_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static u8 audio_status = 1; ++static int audio_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ int len = 0; ++ ++ if (off) ++ { ++ *eof = 1; ++ return ret; ++ } ++ ++ audio_status = gk_aud_readl(AUDC_ANALOG_CTRL00_REG); ++ len = sprintf(page, "%s\n", audio_status==0?"off":"on"); ++ ++ return len; ++} ++ ++static int audio_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[BUFER_COUNT]; ++ u32 addr = 0; ++ ++ CHECK_COUNT; ++ if (copy_from_user(buf, buffer, count)) { ++ retval = -EFAULT; ++ } ++ ++ switch(buf[0]) ++ { ++ case '0': ++ // 0x90022474 set to 0x000003FF ++ // Audio ++ //0x90021C00~0x90021C34 address space clear (0) ++ //0x90020C00~0x90020D6C address space clear (0) ++ for(addr = GK_VA_AUDIO_CODEC_ANALOG; addr <= (GK_VA_AUDIO_CODEC_ANALOG + 0x34); addr+=4) ++ { ++ //printk("[%s] 0x%08x=0x%08x\n", __func__, addr, gk_readl(addr)); ++ gk_aud_writel( addr, 0x00000000); ++ } ++ for(addr = GK_VA_AUDIO_CODEC_DIGITAL; addr <= (GK_VA_AUDIO_CODEC_DIGITAL + 0x16C); addr+=4) ++ { ++ //printk("[%s] 0x%08x=0x%08x\n", __func__, addr, gk_readl(addr)); ++ gk_aud_writel( addr, 0x00000000); ++ } ++ audio_status = 0; ++ break; ++ case '1': ++ // 0x90022474 set to 0x000003FF ++ gk_aud_writel(AUDC_ANALOG_CTRL00_REG, 0x8040); ++ gk_aud_writel(AUDC_ANALOG_CTRL03_REG, 0x4004); ++ gk_aud_writel(AUDC_ANALOG_CTRL04_REG, 0x2000); ++ gk_aud_writel(AUDC_ANALOG_CTRL06_REG, 0x4); ++ gk_aud_writel(AUDC_ANALOG_CTRL11_REG, 0x0); ++ gk_aud_writel(AUDC_ANALOG_CTRL13_REG, 0x6000); ++ gk_aud_writel(AUDC_ANALOG_CTRL00_REG, 0x8040); ++ gk_aud_writel(AUDC_ANALOG_CTRL03_REG, 0x401c); ++ gk_aud_writel(AUDC_ANALOG_CTRL04_REG, 0x233a); ++ gk_aud_writel(AUDC_ANALOG_CTRL05_REG, 0x280c); ++ gk_aud_writel(AUDC_ANALOG_CTRL06_REG, 0x8407); ++ gk_aud_writel(AUDC_ANALOG_CTRL07_REG, 0x3802); ++ gk_aud_writel(AUDC_ANALOG_CTRL08_REG, 0xf8); ++ gk_aud_writel(AUDC_ANALOG_CTRL09_REG, 0x0); ++ gk_aud_writel(AUDC_ANALOG_CTRL10_REG, 0xc0c0); ++ gk_aud_writel(AUDC_ANALOG_CTRL11_REG, 0x9080); ++ gk_aud_writel(AUDC_ANALOG_CTRL12_REG, 0x0); ++ gk_aud_writel(AUDC_ANALOG_CTRL13_REG, 0x6000); ++ gk_aud_writel(AUDC_DIGITAL_MMP1_DPGA_CFG1_REG, 0x5); ++ gk_aud_writel(AUDC_DIGITAL_MMP2_DPGA_CFG1_REG, 0x5); ++ gk_aud_writel(AUDC_DIGITAL_SYS_RST_CTRL0_REG, 0xe000); ++ gk_aud_writel(AUDC_DIGITAL_SYS_RST_CTRL0_REG, 0x0); ++ gk_aud_writel(AUDC_DIGITAL_AUDIOBAND_CTRL0_REG, 0x2); ++ gk_aud_writel(AUDC_DIGITAL_CKG_CTRL0_REG, 0x3); ++ gk_aud_writel(AUDC_DIGITAL_TIMING_CTRL0_REG, 0x33f); ++ gk_aud_writel(AUDC_DIGITAL_TIMING_CTRL1_REG, 0xf3e); ++ gk_aud_writel(AUDC_DIGITAL_AUDIOBAND_CTRL2_REG, 0xfaaf); ++ gk_aud_writel(AUDC_DIGITAL_SDM_CTRL0_REG, 0x15); ++ gk_aud_writel(AUDC_DIGITAL_MMP1_DPGA_CFG1_REG, 0x0); ++ gk_aud_writel(AUDC_DIGITAL_MMP2_DPGA_CFG1_REG, 0x0); ++ gk_aud_writel(AUDC_DIGITAL_TIMING_CTRL0_REG, 0x23f); ++ gk_aud_writel(AUDC_DIGITAL_MIX_CTRL0_REG, 0x2500); ++ gk_aud_writel(AUDC_DIGITAL_TIMING_CTRL1_REG, 0x23e); ++ gk_aud_writel(AUDC_DIGITAL_AUDIOBAND_CTRL1_REG, 0xea82); ++ gk_aud_writel(AUDC_DIGITAL_AUDIOBAND_CTRL2_REG, 0xaaaf); ++ gk_aud_writel(AUDC_ANALOG_CTRL02_REG, 0x8); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_1_NF_H_REG, 0x000000BB); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_1_NF_L_REG, 0x00008000); ++ mdelay(1); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_1_NF_H_REG, 0x0000C0BB); ++ mdelay(1); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_1_NF_H_REG, 0x000000BB); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_2_NF_H_REG, 0x000000c0); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_2_NF_L_REG, 0x00000000); ++ mdelay(1); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_2_NF_H_REG, 0x0000c0c0); ++ mdelay(1); ++ gk_aud_writel(AUDC_DIGITAL_NF_SYNTH_2_NF_H_REG, 0x0000c0); ++ gk_aud_writel(AUDC_DIGITAL_FIFO_TH_CTRL0_REG, 0x402); ++ gk_aud_writel(AUDC_DIGITAL_FIFO_CTRL_REG, 0x8808); ++ gk_aud_writel(AUDC_DIGITAL_FIFO_CTRL_REG, 0x8888); ++ gk_greg_writel(AHB_GENNERNAL1_REG, 0x00000001); ++ audio_status = 1; ++ break; ++ } ++ return count; ++} ++ ++static int create_audio_proc_node(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *audio_entry; ++ ++ audio_entry = create_proc_entry(GK_AUDIO_SWITCH_NAME, S_IRUGO | S_IWUGO, get_gk_proc_dir()); ++ ++ if (!audio_entry) ++ { ++ err_code = -EINVAL; ++ } ++ else ++ { ++ audio_entry->read_proc = audio_read_proc; ++ audio_entry->write_proc = audio_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static int cvbs_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ int len = 0; ++ u32 cvbs_status; ++ ++ if (off) ++ { ++ *eof = 1; ++ return ret; ++ } ++ cvbs_status = gk_vout_readl(GK_VA_VEDIO_DAC); ++ cvbs_status &= 0x00000001; ++ len = sprintf(page, "%s\n", cvbs_status==0?"off":"on"); ++ ++ return len; ++} ++ ++static int cvbs_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[BUFER_COUNT]; ++ CHECK_COUNT; ++ ++ if (copy_from_user(buf, buffer, count)) { ++ retval = -EFAULT; ++ } ++ ++ switch(buf[0]) ++ { ++ case '0': ++ gk_vout_clrbitsl(GK_VA_VEDIO_DAC, 0x00000001); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x04, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x08, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x10, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x14, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x18, 0x00); ++ break; ++ case '1': ++ gk_vout_setbitsl(GK_VA_VEDIO_DAC, 0x00000001); ++ //config video DAC for CVBS ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x00, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x04, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x08, 0x00); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x10, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x14, 0x01); ++ gk_vout_writel( GK_VA_VEDIO_DAC + 0x18, 0x3F); ++ break; ++ } ++ return count; ++} ++ ++static int create_cvbs_proc_node(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *cvbs_entry; ++ ++ cvbs_entry = create_proc_entry(GK_CVBS_SWITCH_NAME, S_IRUGO | S_IWUGO, get_gk_proc_dir()); ++ ++ if (!cvbs_entry) ++ { ++ err_code = -EINVAL; ++ } ++ else ++ { ++ cvbs_entry->read_proc = cvbs_read_proc; ++ cvbs_entry->write_proc = cvbs_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static int phy_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ int len = 0; ++ u32 phy_status; ++ if (off) ++ { ++ *eof = 1; ++ return ret; ++ } ++ phy_status = gk_eth_readl(GK_VA_ETH_PHY + 0x474); ++ len = sprintf(page, "%s\n", phy_status==0x000003FF?"off":"on"); ++ ++ return len; ++} ++ ++static int phy_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[BUFER_COUNT]; ++ CHECK_COUNT; ++ ++ if (copy_from_user(buf, buffer, count)) { ++ retval = -EFAULT; ++ } ++ ++ switch(buf[0]) ++ { ++ case '0': ++ // 0x90022474 set to 0x000003FF ++ gk_eth_writel(GK_VA_ETH_PHY + 0x474, 0x000003FF); ++ break; ++ case '1': ++ // 0x90022474 set to 0x000003FF ++ gk_eth_writel(GK_VA_ETH_PHY + 0x474, 0x00000000); ++ break; ++ } ++ return count; ++} ++ ++static int create_phy_proc_node(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *phy_entry; ++ ++ phy_entry = create_proc_entry(GK_PHY_SWITCH_NAME, S_IRUGO | S_IWUGO, get_gk_proc_dir()); ++ ++ if (!phy_entry) ++ { ++ err_code = -EINVAL; ++ } ++ else ++ { ++ phy_entry->read_proc = phy_read_proc; ++ phy_entry->write_proc = phy_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static int adc_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int ret = 0; ++ int len = 0; ++ u32 adc_status; ++ if (off) ++ { ++ *eof = 1; ++ return ret; ++ } ++ adc_status = gk_adc_readl(GK_VA_ADC + 0x00); ++ len = sprintf(page, "%s\n", adc_status&0x00000001?"off":"on"); ++ ++ return len; ++} ++ ++static int adc_write_proc(struct file *file, const char __user *buffer, ++ unsigned long count, void *data) ++{ ++ int retval = 0; ++ char buf[BUFER_COUNT]; ++ CHECK_COUNT; ++ ++ if (copy_from_user(buf, buffer, count)) { ++ retval = -EFAULT; ++ } ++ ++ switch(buf[0]) ++ { ++ case '0': ++ gk_vout_setbitsl(GK_VA_ADC + 0x00, 0x00000001); ++ gk_vout_clrbitsl(GK_VA_ADC2 + 0x18, 0x00000001); ++ break; ++ case '1': ++ gk_vout_clrbitsl(GK_VA_ADC + 0x00, 0x00000001); ++ gk_vout_setbitsl(GK_VA_ADC2 + 0x18, 0x00000001); ++ break; ++ } ++ return count; ++} ++ ++static int create_adc_proc_node(void) ++{ ++ int err_code = 0; ++ struct proc_dir_entry *adc_entry; ++ ++ adc_entry = create_proc_entry(GK_ADC_SWITCH_NAME, S_IRUGO | S_IWUGO, get_gk_proc_dir()); ++ ++ if (!adc_entry) ++ { ++ err_code = -EINVAL; ++ } ++ else ++ { ++ adc_entry->read_proc = adc_read_proc; ++ adc_entry->write_proc = adc_write_proc; ++ } ++ ++ return err_code; ++} ++ ++static int __init switch_init(void) ++{ ++ create_usb_proc_node(); ++ create_audio_proc_node(); ++ create_cvbs_proc_node(); ++ create_phy_proc_node(); ++ create_adc_proc_node(); ++ return 0; ++} ++ ++static void __exit switch_exit(void) ++{ ++} ++ ++module_init(switch_init); ++module_exit(switch_exit); ++MODULE_DESCRIPTION("gk swith driver"); ++MODULE_LICENSE("Proprietary"); ++ +diff --git a/arch/arm/plat-goke/sync_proc.c b/arch/arm/plat-goke/sync_proc.c +new file mode 100644 +index 00000000..39400917 +--- /dev/null ++++ b/arch/arm/plat-goke/sync_proc.c +@@ -0,0 +1,338 @@ ++/* ++ * arch/arm/mach-gk/sync_proc.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++ ++int gk_sync_proc_hinit(struct gk_sync_proc_hinfo *hinfo) ++{ ++ hinfo->maxid = GK_SYNC_PROC_MAX_ID; ++ init_waitqueue_head(&hinfo->sync_proc_head); ++ atomic_set(&hinfo->sync_proc_flag, 0); ++ idr_init(&hinfo->sync_proc_idr); ++ mutex_init(&hinfo->sync_proc_lock); ++ hinfo->sync_read_proc = NULL; ++ ++ return 0; ++} ++EXPORT_SYMBOL(gk_sync_proc_hinit); ++ ++int gk_sync_proc_open(struct inode *inode, struct file *file) ++{ ++ int retval = 0; ++ struct gk_sync_proc_pinfo *pinfo = file->private_data; ++ struct proc_dir_entry *dp; ++ struct gk_sync_proc_hinfo *hinfo; ++ int id; ++ dp = PDE(inode); ++ hinfo = (struct gk_sync_proc_hinfo *)dp->data; ++ if (!hinfo) { ++ retval = -EPERM; ++ goto gk_sync_proc_open_exit; ++ } ++ if (hinfo->maxid > GK_SYNC_PROC_MAX_ID) { ++ retval = -EPERM; ++ goto gk_sync_proc_open_exit; ++ } ++ ++ if (pinfo) { ++ retval = -EPERM; ++ goto gk_sync_proc_open_exit; ++ } ++ pinfo = kmalloc(sizeof(*pinfo), GFP_KERNEL); ++ if (!pinfo) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_open_exit; ++ } ++ memset(pinfo, 0, sizeof(*pinfo)); ++ ++ if (idr_pre_get(&hinfo->sync_proc_idr, GFP_KERNEL) == 0) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_open_kfree_p; ++ } ++ mutex_lock(&hinfo->sync_proc_lock); ++ retval = idr_get_new_above(&hinfo->sync_proc_idr, pinfo, 0, &id); ++ mutex_unlock(&hinfo->sync_proc_lock); ++ if (retval != 0) ++ goto gk_sync_proc_open_kfree_p; ++ if (id > 31) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_open_remove_id; ++ } ++ ++ if (!(pinfo->page = (char*) __get_free_page(GFP_KERNEL))) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_open_remove_id; ++ } ++ pinfo->id = id; ++ pinfo->mask = (0x01 << id); ++ ++ file->private_data = pinfo; ++ file->f_version = 0; ++ file->f_mode &= ~FMODE_PWRITE; ++ ++ goto gk_sync_proc_open_exit; ++ ++gk_sync_proc_open_remove_id: ++ mutex_lock(&hinfo->sync_proc_lock); ++ idr_remove(&hinfo->sync_proc_idr, id); ++ mutex_unlock(&hinfo->sync_proc_lock); ++ ++gk_sync_proc_open_kfree_p: ++ kfree(pinfo); ++ ++gk_sync_proc_open_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_sync_proc_open); ++ ++int gk_sync_proc_release(struct inode *inode, struct file *file) ++{ ++ int retval = 0; ++ struct gk_sync_proc_pinfo *pinfo = file->private_data; ++ struct proc_dir_entry *dp; ++ struct gk_sync_proc_hinfo *hinfo; ++ dp = PDE(inode); ++ ++ hinfo = (struct gk_sync_proc_hinfo *)dp->data; ++ if (!hinfo) { ++ retval = -EPERM; ++ goto gk_sync_proc_release_exit; ++ } ++ ++ if (!pinfo) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_release_exit; ++ } ++ ++ mutex_lock(&hinfo->sync_proc_lock); ++ idr_remove(&hinfo->sync_proc_idr, pinfo->id); ++ mutex_unlock(&hinfo->sync_proc_lock); ++ ++ free_page((unsigned long)pinfo->page); ++ kfree(pinfo); ++ file->private_data = NULL; ++ ++gk_sync_proc_release_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_sync_proc_release); ++ ++/* Note: ignore ppos*/ ++ssize_t gk_sync_proc_read(struct file *file, char __user *buf, ++ size_t size, loff_t *ppos) ++{ ++ int retval = 0; ++ struct gk_sync_proc_pinfo *pinfo = file->private_data; ++ struct proc_dir_entry *dp; ++ struct gk_sync_proc_hinfo *hinfo; ++ struct inode *inode = file->f_path.dentry->d_inode; ++ char *start; ++ int len; ++ size_t count; ++ dp = PDE(inode); ++ hinfo = (struct gk_sync_proc_hinfo *)dp->data; ++ if (!hinfo) { ++ retval = -EPERM; ++ goto gk_sync_proc_read_exit; ++ } ++ if (!hinfo->sync_read_proc) { ++ retval = -EPERM; ++ goto gk_sync_proc_read_exit; ++ } ++ ++ if (!pinfo) { ++ retval = -ENOMEM; ++ goto gk_sync_proc_read_exit; ++ } ++ ++ count = min_t(size_t, GK_SYNC_PROC_PAGE_SIZE, size); ++ start = pinfo->page; ++ len = 0; ++ while (1) { ++ wait_event_interruptible(hinfo->sync_proc_head, ++ (atomic_read(&hinfo->sync_proc_flag) & pinfo->mask)); ++ atomic_clear_mask(pinfo->mask, ++ (unsigned long *)&hinfo->sync_proc_flag); ++ ++ len = hinfo->sync_read_proc(start, hinfo->sync_read_data); ++ if (len < count) { ++ start += len; ++ count -= len; ++ } else if (len == count) { ++ start += len; ++ count -= len; ++ break; ++ } else { ++ break; ++ } ++ } ++ len = start - pinfo->page; ++ if (len == 0) { ++ retval = -EFAULT; ++ } else { ++ if (copy_to_user(buf, pinfo->page, len)) { ++ retval = -EFAULT; ++ } else { ++ retval = len; ++ } ++ } ++ ++gk_sync_proc_read_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_sync_proc_read); ++ ++ssize_t gk_sync_proc_write(struct file *file, const char __user *buf, ++ size_t size, loff_t *ppos) ++{ ++ int retval = 0; ++ struct proc_dir_entry *dp; ++ struct gk_sync_proc_hinfo *hinfo; ++ struct inode *inode = file->f_path.dentry->d_inode; ++ ++ dp = PDE(inode); ++ hinfo = (struct gk_sync_proc_hinfo *)dp->data; ++ ++ if (!hinfo) { ++ retval = -EPERM; ++ goto gk_sync_proc_write_exit; ++ } ++ ++ atomic_set(&hinfo->sync_proc_flag, 0xFFFFFFFF); ++ wake_up_all(&hinfo->sync_proc_head); ++ ++ retval = size; ++ ++gk_sync_proc_write_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_sync_proc_write); ++ ++#define GET_PROC_DATA_FROM_FILEP(filp) (struct gk_async_proc_info *)(PDE(filp->f_path.dentry->d_inode)->data) ++ ++static int gk_async_proc_open(struct inode *inode, struct file *filp) ++{ ++ struct gk_async_proc_info *pinfo; ++ ++ pinfo = GET_PROC_DATA_FROM_FILEP(filp); ++ ++ mutex_lock(&pinfo->op_mutex); ++ pinfo->use_count++; ++ filp->f_op = &pinfo->fops; ++ filp->private_data = pinfo->private_data; ++ mutex_unlock(&pinfo->op_mutex); ++ ++ return 0; ++} ++ ++static int gk_async_proc_fasync(int fd, struct file * filp, int on) ++{ ++ int retval; ++ struct gk_async_proc_info *pinfo; ++ ++ pinfo = GET_PROC_DATA_FROM_FILEP(filp); ++ ++ mutex_lock(&pinfo->op_mutex); ++ retval = fasync_helper(fd, filp, on, &pinfo->fasync_queue); ++ mutex_unlock(&pinfo->op_mutex); ++ ++ return retval; ++} ++ ++static int gk_async_proc_release(struct inode *inode, struct file *filp) ++{ ++ int retval; ++ struct gk_async_proc_info *pinfo; ++ ++ pinfo = GET_PROC_DATA_FROM_FILEP(filp); ++ ++ mutex_lock(&pinfo->op_mutex); ++ retval = fasync_helper(-1, filp, 0, &pinfo->fasync_queue); ++ pinfo->use_count--; ++ mutex_unlock(&pinfo->op_mutex); ++ ++ return retval; ++} ++ ++int gk_async_proc_create(struct gk_async_proc_info *pinfo) ++{ ++ int retval = 0; ++ struct proc_dir_entry *entry; ++ ++ if (!pinfo) { ++ retval = -EINVAL; ++ goto gk_async_proc_create_exit; ++ } ++ ++ pinfo->fops.open = gk_async_proc_open; ++ pinfo->fops.fasync = gk_async_proc_fasync; ++ pinfo->fops.release = gk_async_proc_release; ++ mutex_init(&pinfo->op_mutex); ++ pinfo->use_count = 0; ++ pinfo->fasync_queue = NULL; ++ ++ entry = proc_create_data(pinfo->proc_name, S_IRUGO, ++ get_gk_proc_dir(), &pinfo->fops, pinfo); ++ if (!entry) { ++ retval = -EINVAL; ++ } ++ ++gk_async_proc_create_exit: ++ return retval; ++} ++EXPORT_SYMBOL(gk_async_proc_create); ++ ++int gk_async_proc_remove(struct gk_async_proc_info *pinfo) ++{ ++ int retval = 0; ++ ++ if (!pinfo) { ++ retval = -EINVAL; ++ } else { ++ remove_proc_entry(pinfo->proc_name, get_gk_proc_dir()); ++ } ++ ++ return retval; ++} ++EXPORT_SYMBOL(gk_async_proc_remove); ++ +diff --git a/arch/arm/plat-goke/timer.c b/arch/arm/plat-goke/timer.c +new file mode 100644 +index 00000000..6b699d3a +--- /dev/null ++++ b/arch/arm/plat-goke/timer.c +@@ -0,0 +1,350 @@ ++/* ++ * arch/arm/mach-gk/timer.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Default clock is from APB. ++ * Timer 3 is used as clock_event_device. ++ * Timer 2 is used as free-running clocksource ++ * if CONFIG_GK_SUPPORT_CLOCKSOURCE is defined ++ * Timer 1 is not used. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++/* ==========================================================================*/ ++#define GK_TIMER_FREQ (get_apb_bus_freq_hz()) ++#define GK_TIMER_RATING (300) ++ ++static struct clock_event_device gk_clkevt; ++static struct irqaction gk_ce_timer_irq; ++static u32 timer_reload = 0; ++static u32 timer_Mhz = 69; ++ ++/* ==========================================================================*/ ++#define GK_CE_TIMER_STATUS_REG TIMER3_STATUS_REG ++#define GK_CE_TIMER_RELOAD_REG TIMER3_RELOAD_REG ++#define GK_CE_TIMER_MATCH1_REG TIMER3_MATCH1_REG ++#define GK_CE_TIMER_MATCH2_REG TIMER3_MATCH2_REG ++#define GK_CE_TIMER_IRQ TIMER3_IRQ ++#define GK_CE_TIMER_CTR_EN TIMER_CTR_EN3 ++#define GK_CE_TIMER_CTR_OF TIMER_CTR_OF3 ++#define GK_CE_TIMER_CTR_CSL TIMER_CTR_CSL3 ++#define GK_CE_TIMER_CTR_MASK 0x00000F00 ++ ++int gk_start_highres_timer(u32 ms_to_timeout); ++ ++int gk_init_highres_timer(void *pcallback); ++ ++ ++ ++static inline void gk_ce_timer_disable(void) ++{ ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_CE_TIMER_CTR_EN); ++} ++ ++static inline void gk_ce_timer_enable(void) ++{ ++ gk_timer_setbitsl(TIMER_CTR_REG, GK_CE_TIMER_CTR_EN); ++} ++ ++static inline void gk_ce_timer_misc(void) ++{ ++ gk_timer_setbitsl(TIMER_CTR_REG, (GK_CE_TIMER_CTR_OF | GK_CE_TIMER_CTR_CSL)); ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_CE_TIMER_CTR_CSL); ++} ++ ++static inline void gk_ce_timer_set_periodic(void) ++{ ++ u32 cnt; ++ ++ cnt = GK_TIMER_FREQ / HZ; ++ gk_timer_writel(GK_CE_TIMER_STATUS_REG, cnt); ++ gk_timer_writel(GK_CE_TIMER_RELOAD_REG, cnt); ++ timer_reload = cnt; ++ timer_Mhz = GK_TIMER_FREQ/1000000; ++ gk_timer_writel(GK_CE_TIMER_MATCH1_REG, 0x0); ++ gk_timer_writel(GK_CE_TIMER_MATCH2_REG, 0x0); ++ gk_ce_timer_misc(); ++} ++ ++static inline void gk_ce_timer_set_oneshot(void) ++{ ++ gk_timer_writel(GK_CE_TIMER_STATUS_REG, 0x0); ++ gk_timer_writel(GK_CE_TIMER_RELOAD_REG, 0xffffffff); ++ gk_timer_writel(GK_CE_TIMER_MATCH1_REG, 0x0); ++ gk_timer_writel(GK_CE_TIMER_MATCH2_REG, 0x0); ++ gk_ce_timer_misc(); ++} ++ ++static void gk_ce_timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *evt) ++{ ++ switch (mode) { ++ case CLOCK_EVT_MODE_PERIODIC: ++ gk_ce_timer_disable(); ++ gk_ce_timer_set_periodic(); ++ gk_ce_timer_enable(); ++ break; ++ case CLOCK_EVT_MODE_ONESHOT: ++ gk_ce_timer_disable(); ++ gk_ce_timer_set_oneshot(); ++ gk_ce_timer_enable(); ++ break; ++ case CLOCK_EVT_MODE_UNUSED: ++ remove_irq(gk_clkevt.irq, &gk_ce_timer_irq); ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ gk_ce_timer_disable(); ++ break; ++ case CLOCK_EVT_MODE_RESUME: ++ break; ++ } ++ pr_debug("%s:%d\n", __func__, mode); ++} ++ ++static int gk_ce_timer_set_next_event(unsigned long delta, ++ struct clock_event_device *dev) ++{ ++ gk_timer_writel(GK_CE_TIMER_STATUS_REG, delta); ++ ++ return 0; ++} ++ ++static void gk_timer_irq_clr(u32 timer_irq) ++{ ++ if((timer_irq > TIMER3_IRQ)&&(timer_irq < TIMER1_IRQ)) ++ { ++ printk("Error Timer Irq = %d!\n", timer_irq); ++ } ++ ++ gk_irq_writel(VIC_EDGE_CLR_REG, (1 << timer_irq)); ++} ++ ++static struct clock_event_device gk_clkevt = { ++ .name = "gk-clkevt", ++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .rating = GK_TIMER_RATING, ++ .set_next_event = gk_ce_timer_set_next_event, ++ .set_mode = gk_ce_timer_set_mode, ++ .mode = CLOCK_EVT_MODE_UNUSED, ++ .irq = GK_CE_TIMER_IRQ, ++}; ++ ++static irqreturn_t gk_ce_timer_interrupt(int irq, void *dev_id) ++{ ++ gk_timer_irq_clr(irq); ++ gk_clkevt.event_handler(&gk_clkevt); ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction gk_ce_timer_irq = { ++ .name = "tick-timer", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, ++ .handler = gk_ce_timer_interrupt, ++}; ++ ++/* ==========================================================================*/ ++#if defined(CONFIG_SUPPORT_CLOCKSOURCE) ++#define GK_CS_TIMER_STATUS_REG TIMER2_STATUS_REG ++#define GK_CS_TIMER_RELOAD_REG TIMER2_RELOAD_REG ++#define GK_CS_TIMER_MATCH1_REG TIMER2_MATCH1_REG ++#define GK_CS_TIMER_MATCH2_REG TIMER2_MATCH2_REG ++#define GK_CS_TIMER_CTR_EN TIMER_CTR_EN2 ++#define GK_CS_TIMER_CTR_OF TIMER_CTR_OF2 ++#define GK_CS_TIMER_CTR_CSL TIMER_CTR_CSL2 ++#define GK_CS_TIMER_CTR_MASK 0x000000F0 ++ ++static inline void gk_cs_timer_init(void) ++{ ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_CS_TIMER_CTR_EN); ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_CS_TIMER_CTR_OF); ++ gk_timer_clrbitsl(TIMER_CTR_REG, GK_CS_TIMER_CTR_CSL); ++ gk_timer_writel(GK_CS_TIMER_STATUS_REG, 0xffffffff); ++ gk_timer_writel(GK_CS_TIMER_RELOAD_REG, 0xffffffff); ++ gk_timer_writel(GK_CS_TIMER_MATCH1_REG, 0x0); ++ gk_timer_writel(GK_CS_TIMER_MATCH2_REG, 0x0); ++ gk_timer_setbitsl(TIMER_CTR_REG, GK_CS_TIMER_CTR_EN); ++} ++ ++static cycle_t gk_cs_timer_read(struct clocksource *cs) ++{ ++ return ((cycle_t)gk_timer_readl(GK_CS_TIMER_STATUS_REG)); ++} ++ ++static struct clocksource gk_cs_timer_clksrc = ++{ ++ .name = "gk-cs-timer", ++ .rating = GK_TIMER_RATING, ++ .read = gk_cs_timer_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .mult = 2236962133u, ++ .shift = 27, ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++#endif ++ ++/* ==========================================================================*/ ++static void __init gk_timer_init(void) ++{ ++ printk("mach gk init timer...\n"); ++#if defined(CONFIG_SUPPORT_CLOCKSOURCE) ++ gk_cs_timer_init(); ++ clocks_calc_mult_shift(&gk_cs_timer_clksrc.mult, ++ &gk_cs_timer_clksrc.shift, ++ GK_TIMER_FREQ, NSEC_PER_SEC, 60); ++ pr_debug("%s: mult = %u, shift = %u\n", ++ gk_cs_timer_clksrc.name, ++ gk_cs_timer_clksrc.mult, ++ gk_cs_timer_clksrc.shift); ++ clocksource_register(&gk_cs_timer_clksrc); ++#endif ++ ++ gk_clkevt.cpumask = cpumask_of(0); ++ setup_irq(gk_clkevt.irq, &gk_ce_timer_irq); ++ clockevents_config_and_register(&gk_clkevt, GK_TIMER_FREQ, 0x01, 0xffffffff); ++ ++ ++ return; ++ ++} ++ ++unsigned long gk_timer_offset(void) ++{ ++ u32 val = (timer_reload - gk_timer_readl(GK_CE_TIMER_STATUS_REG))/timer_Mhz; ++ ++ return val; ++} ++ ++ ++struct sys_timer gk_sys_timer = { ++ .init = gk_timer_init, ++ .offset = gk_timer_offset, ++}; ++ ++int __init gk_init_timer(void) ++{ ++ int errCode = 0; ++ ++ /* Reset all timers */ ++ //gk_timer_writel(TIMER_CTR_REG, 0x0); ++ timer_reload = gk_timer_readl(GK_CE_TIMER_RELOAD_REG); ++ gk_init_highres_timer(NULL); ++ gk_start_highres_timer(100); ++ ++ return errCode; ++} ++ ++//---------------------------------------- ++typedef void (* HIGH_RES_TIMER_CALLBACK) (void); ++ ++static HIGH_RES_TIMER_CALLBACK s_pCallback_high_res = NULL; ++ ++static u32 dev_id = 0; ++static u32 timer_ms_delay = 12; ++static u32 timer_intr_cnt = 0; ++static void init_hw_timer(void) ++{ ++ u32 interrupt_interval_in_ms = 1; ++ u32 apb_clk = get_apb_bus_freq_hz(); ++ u32 timer_clk = apb_clk * interrupt_interval_in_ms /100; ++ gk_timer_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN2); ++ gk_timer_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF2); ++ gk_timer_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL2); ++ gk_timer_writel(TIMER2_STATUS_REG, timer_clk); ++ gk_timer_writel(TIMER2_RELOAD_REG, timer_clk); ++ gk_timer_writel(TIMER2_MATCH1_REG, 0x0); ++ gk_timer_writel(TIMER2_MATCH2_REG, 0x0); ++ ++ gk_timer_setbitsl(TIMER_CTR_REG, (TIMER_CTR_OF2 | TIMER_CTR_CSL2)); ++ gk_timer_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL2); ++ //gk_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN2); ++} ++ ++static void deinit_hw_timer(void) ++{ ++ gk_timer_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN2); ++} ++ ++static irqreturn_t hw_timer_irq_handler(int irqno, void *dev_id) ++{ ++ gk_timer_irq_clr(irqno); ++ ++ //printk("timer2 irq...%d\n", timer_intr_cnt); ++ ++ if (timer_intr_cnt++ != timer_ms_delay) ++ return IRQ_HANDLED; ++ ++ timer_intr_cnt = 0; ++ //run callback, the callback must be fast enough to be put into interrupt context ++ if(s_pCallback_high_res) ++ s_pCallback_high_res(); ++ return IRQ_HANDLED; ++} ++ ++ ++ ++int gk_init_highres_timer(void *pcallback) ++{ ++ int rval; ++ HIGH_RES_TIMER_CALLBACK ptimercb = (HIGH_RES_TIMER_CALLBACK)pcallback; ++ ++ printk("Init HW timer for DSP communication\n"); ++ ++ s_pCallback_high_res = ptimercb; ++ rval = request_irq(TIMER2_IRQ, hw_timer_irq_handler, IRQF_SHARED | IRQF_TIMER | IRQF_TRIGGER_RISING, "HW Timer2", &dev_id); ++ ++ if (rval < 0) ++ printk("%s, %d, Can NOT request_irq %d\n",__func__,__LINE__,rval); ++ init_hw_timer(); ++ return 0; ++} ++ ++int gk_start_highres_timer(u32 ms_to_timeout) ++{ ++ unsigned long flags; ++ local_irq_save(flags); ++ timer_ms_delay = ms_to_timeout; ++ timer_intr_cnt = 0; ++ local_irq_restore(flags); ++ gk_timer_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN2); ++ return 0; ++} ++ ++int gk_deinit_highres_timer(void) ++{ ++ s_pCallback_high_res = NULL; ++ deinit_hw_timer(); ++ return 0; ++} ++ +diff --git a/arch/arm/plat-goke/uart.c b/arch/arm/plat-goke/uart.c +new file mode 100644 +index 00000000..14cc6752 +--- /dev/null ++++ b/arch/arm/plat-goke/uart.c +@@ -0,0 +1,302 @@ ++/* ++ * arch/arm/mach-gk/uart.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++extern u64 gk_dmamask; ++ ++/* ==========================================================================*/ ++ ++static void gk_uart_stop_tx(unsigned char __iomem *membase); ++#if (UART_INSTANCES >= 2) ++static u32 gk_uart_read_ms(unsigned char __iomem *membase); ++#endif ++ ++/* ==========================================================================*/ ++/* Serial port registrations */ ++ ++static struct uart_port gk_uart_port_resource[] = ++{ ++ [0] = { ++ .type = PORT_UART00, ++ .iotype = UPIO_MEM, ++ .membase = (void *)UART0_VA_ADDR, ++ .mapbase = (unsigned long)UART0_PA_ADDR, ++ .irq = UART0_IRQ, ++ .uartclk = GK_UART_FREQ/*12500000*/, ++ .fifosize = UART_FIFO_SIZE, ++ .line = 0, ++ }, ++#if (UART_INSTANCES >= 2) ++ [1] = { ++ .type = PORT_UART00, ++ .iotype = UPIO_MEM, ++ .membase = (void *)UART1_VA_ADDR, ++ .mapbase = (unsigned long)UART1_PA_ADDR, ++ .irq = UART1_IRQ, ++ .uartclk = GK_UART_FREQ/*12500000*/, ++ .fifosize = UART_FIFO_SIZE, ++ .line = 0, ++ }, ++#endif ++#if (UART_INSTANCES >= 3) ++ [2] = { ++ .type = PORT_UART00, ++ .iotype = UPIO_MEM, ++ .membase = (void *)UART2_VA_ADDR, ++ .mapbase = (unsigned long)UART2_PA_ADDR, ++ .irq = UART2_IRQ, ++ .uartclk = GK_UART_FREQ/*12500000*/, ++ .fifosize = UART_FIFO_SIZE, ++ .line = 0, ++ }, ++#endif ++}; ++ ++struct gk_uart_platform_info gk_uart_ports = ++{ ++ .total_port_num = ARRAY_SIZE(gk_uart_port_resource), ++ .registed_port_num = 0, ++ .port[0] = { ++ .port = &gk_uart_port_resource[0], ++ .mcr = DEFAULT_UART_MCR, ++ .fcr = DEFAULT_UART_FCR, ++ .ier = DEFAULT_UART_IER, ++ .stop_tx = gk_uart_stop_tx, ++ .set_pll = NULL, ++ .get_pll = get_uart_freq_hz, ++ .get_ms = gk_uart_read_ms, ++ }, ++#if (UART_INSTANCES >= 2) ++ .port[1] = { ++ .port = &gk_uart_port_resource[1], ++ .mcr = DEFAULT_UART_MCR, ++ .fcr = DEFAULT_UART_FCR, ++ .ier = DEFAULT_UART_IER, ++ .stop_tx = gk_uart_stop_tx, ++ .set_pll = NULL, ++ .get_pll = get_uart_freq_hz, ++ .get_ms = gk_uart_read_ms, ++ }, ++#endif ++#if (UART_INSTANCES >= 3) ++ .port[2] = { ++ .port = &gk_uart_port_resource[2], ++ .mcr = DEFAULT_UART_MCR, ++ .fcr = DEFAULT_UART_FCR, ++ .ier = DEFAULT_UART_IER, ++ .stop_tx = gk_uart_stop_tx, ++ .set_pll = NULL, ++ .get_pll = get_uart_freq_hz, ++ .get_ms = gk_uart_read_ms, ++ }, ++#endif ++ ++}; ++ ++struct platform_device gk_uart0 = ++{ ++ .name = "uart", ++ .id = 0, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &gk_uart_ports, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#if (UART_INSTANCES >= 2) ++struct platform_device gk_uart1 = ++{ ++ .name = "uart", ++ .id = 1, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &gk_uart_ports, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++#if (UART_INSTANCES >= 3) ++struct platform_device gk_uart2 = ++{ ++ .name = "uart", ++ .id = 2, ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &gk_uart_ports, ++ .dma_mask = &gk_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++#endif ++ ++/* uart devices */ ++struct platform_device *gk_uart_devs[UART_INSTANCES] = { ++ &gk_uart0, ++#if (UART_INSTANCES >= 2) ++ &gk_uart1, ++#endif ++#if (UART_INSTANCES >= 3) ++ &gk_uart2, ++#endif ++}; ++ ++/* ==========================================================================*/ ++ ++static void gk_uart_stop_tx(unsigned char __iomem *membase) ++{ ++ gk_uart_clrbitsl((unsigned int)(membase + UART_IE_OFFSET), UART_IE_ETBEI); ++} ++ ++#if (UART_INSTANCES >= 2) ++static u32 gk_uart_read_ms(unsigned char __iomem *membase) ++{ ++ return gk_uart_readl((unsigned int)(membase + UART_MS_OFFSET)); ++} ++#endif ++ ++ ++ ++/* uart registration process */ ++static int __init gk_arch_init(void) ++{ ++ int ret; ++ ++ ret = platform_add_devices(gk_uart_devs, ARRAY_SIZE(gk_uart_devs)); ++ if(ret < 0) ++ { ++ printk(KERN_ERR "%s: failed to add uart device err=%d\n", __FUNCTION__, ret); ++ } ++ return ret; ++} ++ ++arch_initcall(gk_arch_init); ++ ++ ++#ifdef KE_DEBUG ++ ++#define vtop(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) ++#define ptov(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) ++ ++static inline void ke_putc(int c) ++{ ++ while (!(gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_LS_OFFSET) & UART_LS_TEMT)); ++ gk_uart_writel(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_TH_OFFSET, c); ++} ++ ++static inline void ke_flush(void) ++{ ++ unsigned int dump; ++ ++ while (gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_LS_OFFSET) & UART_LS_DR) ++ { ++ dump = gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_RB_OFFSET); ++ } ++} ++ ++static void ke_putstr(const char *ptr) ++{ ++ char c; ++ ++ while ((c = *ptr++) != '\0') { ++ if (c == '\n') ++ ke_putc('\r'); ++ ke_putc(c); ++ } ++ ++ ke_flush(); ++} ++ ++void __init ke_print(const char *str, ...) ++{ ++ char buf[256]; ++ va_list ap; ++ ++ va_start(ap, str); ++ vsnprintf(buf, sizeof(buf), str, ap); ++ va_end(ap); ++ ++ ke_putstr(buf); ++} ++ ++/** ++ * Put a character out to the UART controller. ++ */ ++static void after_putc(int c) ++{ ++ while (!(gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_LS_OFFSET) & UART_LS_TEMT)); ++ gk_uart_writel(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_TH_OFFSET, c); ++} ++ ++static void after_flush(void) ++{ ++ unsigned int dump; ++ ++ while (gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_LS_OFFSET) & UART_LS_DR) ++ { ++ dump = gk_uart_readl(gk_uart_devs[0]->dev.platform_data->port[0].port->membase+UART_RB_OFFSET); ++ } ++} ++ ++static void after_putstr(const char *ptr) ++{ ++ char c; ++ ++ while ((c = *ptr++) != '\0') { ++ if (c == '\n') ++ after_putc('\r'); ++ after_putc(c); ++ } ++ ++ after_flush(); ++} ++ ++ ++void after_print(const char *str, ...) ++{ ++ char buf[256]; ++ va_list ap; ++ ++ va_start(ap, str); ++ vsnprintf(buf, sizeof(buf), str, ap); ++ va_end(ap); ++ ++ after_putstr(buf); ++} ++ ++#endif ++ +diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types +index f9c9f33f..f30b5082 100644 +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1169,3 +1169,7 @@ elite_ulk MACH_ELITE_ULK ELITE_ULK 3888 + pov2 MACH_POV2 POV2 3889 + ipod_touch_2g MACH_IPOD_TOUCH_2G IPOD_TOUCH_2G 3890 + da850_pqab MACH_DA850_PQAB DA850_PQAB 3891 ++goke_ipc MACH_GOKE_IPC GOKE_IPC 3988 ++#gk7102s_elec_sc1135_v1 MACH_GK7102S_ELEC_SC1135_V1_00 GK7102S_ELEC_SC1135_V1_00 3988 ++ ++# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number +diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S +index 323ce1a6..50a724a8 100644 +--- a/arch/arm/vfp/entry.S ++++ b/arch/arm/vfp/entry.S +@@ -28,6 +28,7 @@ ENTRY(do_vfp) + str r11, [r10, #TI_PREEMPT] + #endif + enable_irq ++ str r2, [sp, #S_PC] @ update regs->ARM_pc for Thumb 2 case + ldr r4, .LCvfp + ldr r11, [r10, #TI_CPU] @ CPU number + add r10, r10, #TI_VFPSTATE @ r10 = workspace +diff --git a/drivers/base/Makefile b/drivers/base/Makefile +index b6d1b9c4..220ae825 100644 +--- a/drivers/base/Makefile ++++ b/drivers/base/Makefile +@@ -1,7 +1,7 @@ + # Makefile for the Linux device tree + + obj-y := core.o bus.o dd.o syscore.o \ +- driver.o class.o platform.o \ ++ driver.o class.o platform.o ipcbus.o \ + cpu.o firmware.o init.o map.o devres.o \ + attribute_container.o transport_class.o \ + topology.o +diff --git a/drivers/base/ipcbus.c b/drivers/base/ipcbus.c +new file mode 100644 +index 00000000..38e610ee +--- /dev/null ++++ b/drivers/base/ipcbus.c +@@ -0,0 +1,193 @@ ++/*! ++***************************************************************************** ++** \file drivers/base/ipcbus.c ++** ++** \version $Id$ ++** ++** \brief ++** ++** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS ++** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ++** OMMISSIONS ++** ++** (C) Copyright 2012-2015 by GOKE MICROELECTRONICS CO.,LTD ++** ++***************************************************************************** ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct device gk_bus = { ++ .init_name = "ipc_bus" ++}; ++ ++struct ipc_dev { ++ struct device dev; ++ struct device *next; ++}; ++ ++#define to_gk_dev(x) container_of((x), struct ipc_dev, dev) ++ ++static int gk_bus_match(struct device *dev, struct device_driver *driver) ++{ ++ struct ipc_driver *ipc_driver = to_ipc_driver(driver); ++ ++ if (dev->platform_data == ipc_driver) { ++ if (!ipc_driver->match || ipc_driver->match(dev)) ++ return 1; ++ dev->platform_data = NULL; ++ } ++ return 0; ++} ++ ++static int gk_bus_probe(struct device *dev) ++{ ++ struct ipc_driver *ipc_driver = dev->platform_data; ++ ++ if (ipc_driver->probe) ++ return ipc_driver->probe(dev); ++ ++ return 0; ++} ++ ++static int gk_bus_remove(struct device *dev) ++{ ++ struct ipc_driver *ipc_driver = dev->platform_data; ++ ++ if (ipc_driver->remove) ++ return ipc_driver->remove(dev); ++ ++ return 0; ++} ++ ++static void gk_bus_shutdown(struct device *dev) ++{ ++ struct ipc_driver *ipc_driver = dev->platform_data; ++ ++ if (ipc_driver->shutdown) ++ ipc_driver->shutdown(dev); ++} ++ ++static int gk_bus_suspend(struct device *dev, pm_message_t state) ++{ ++ struct ipc_driver *ipc_driver = dev->platform_data; ++ ++ if (ipc_driver->suspend) ++ return ipc_driver->suspend(dev, state); ++ ++ return 0; ++} ++ ++static int gk_bus_resume(struct device *dev) ++{ ++ struct ipc_driver *ipc_driver = dev->platform_data; ++ ++ if (ipc_driver->resume) ++ return ipc_driver->resume(dev); ++ ++ return 0; ++} ++ ++static struct bus_type gk_bus_type = { ++ .name = "ipc_bus", ++ .match = gk_bus_match, ++ .probe = gk_bus_probe, ++ .remove = gk_bus_remove, ++ .shutdown = gk_bus_shutdown, ++ .suspend = gk_bus_suspend, ++ .resume = gk_bus_resume ++}; ++ ++static void gk_dev_release(struct device *dev) ++{ ++ kfree(to_gk_dev(dev)); ++} ++ ++void ipc_unregister_driver(struct ipc_driver *ipc_driver) ++{ ++ struct device *dev = ipc_driver->devices; ++ ++ while (dev) { ++ struct device *tmp = to_gk_dev(dev)->next; ++ device_unregister(dev); ++ dev = tmp; ++ } ++ driver_unregister(&ipc_driver->driver); ++} ++EXPORT_SYMBOL(ipc_unregister_driver); ++ ++int ipc_register_driver(struct ipc_driver *ipc_driver) ++{ ++ int error; ++ unsigned int id; ++ ++ ipc_driver->driver.bus = &gk_bus_type; ++ ipc_driver->devices = NULL; ++ ++ error = driver_register(&ipc_driver->driver); ++ if (error) ++ return error; ++ ++ for (id = 0; id < 1; id++) { ++ struct ipc_dev *ipc_dev; ++ ++ ipc_dev = kzalloc(sizeof *ipc_dev, GFP_KERNEL); ++ if (!ipc_dev) { ++ error = -ENOMEM; ++ break; ++ } ++ ++ ipc_dev->dev.parent = &gk_bus; ++ ipc_dev->dev.bus = &gk_bus_type; ++ ++ dev_set_name(&ipc_dev->dev, "%s", ++ ipc_driver->driver.name); ++ ipc_dev->dev.platform_data = ipc_driver; ++ ipc_dev->dev.release = gk_dev_release; ++ ++ ipc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(24); ++ ipc_dev->dev.dma_mask = &ipc_dev->dev.coherent_dma_mask; ++ ++ error = device_register(&ipc_dev->dev); ++ if (error) { ++ put_device(&ipc_dev->dev); ++ break; ++ } ++ ++ if (ipc_dev->dev.platform_data) { ++ ipc_dev->next = ipc_driver->devices; ++ ipc_driver->devices = &ipc_dev->dev; ++ } else ++ device_unregister(&ipc_dev->dev); ++ } ++ ++ if (!error && !ipc_driver->devices) ++ error = -ENODEV; ++ ++ if (error) ++ ipc_unregister_driver(ipc_driver); ++ ++ return error; ++} ++EXPORT_SYMBOL(ipc_register_driver); ++ ++static int __init gk_bus_init(void) ++{ ++ int error; ++ ++ error = bus_register(&gk_bus_type); ++ if (!error) { ++ error = device_register(&gk_bus); ++ if (error) ++ bus_unregister(&gk_bus_type); ++ } ++ return error; ++} ++ ++device_initcall(gk_bus_init); +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 112c16e0..c487ab68 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -253,8 +253,10 @@ static ssize_t gpio_direction_store(struct device *dev, + status = gpio_direction_output(gpio, 1); + else if (sysfs_streq(buf, "out") || sysfs_streq(buf, "low")) + status = gpio_direction_output(gpio, 0); +- else if (sysfs_streq(buf, "in")) +- status = gpio_direction_input(gpio); ++ else if (sysfs_streq(buf, "in") || sysfs_streq(buf, "in0")) ++ status = gpio_direction_input(gpio, 0); ++ else if (sysfs_streq(buf, "in1")) ++ status = gpio_direction_input(gpio, 1); + else + status = -EINVAL; + +@@ -1300,7 +1302,7 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label) + set_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags); + + if (flags & GPIOF_DIR_IN) +- err = gpio_direction_input(gpio); ++ err = gpio_direction_input(gpio, 0); + else + err = gpio_direction_output(gpio, + (flags & GPIOF_INIT_HIGH) ? 1 : 0); +@@ -1386,7 +1388,7 @@ EXPORT_SYMBOL_GPL(gpiochip_is_requested); + * rely on gpio_request() having been called beforehand. + */ + +-int gpio_direction_input(unsigned gpio) ++int gpio_direction_input(unsigned gpio, int val) + { + unsigned long flags; + struct gpio_chip *chip; +@@ -1425,7 +1427,7 @@ int gpio_direction_input(unsigned gpio) + } + } + +- status = chip->direction_input(chip, gpio); ++ status = chip->direction_input(chip, gpio, val); + if (status == 0) + clear_bit(FLAG_IS_OUT, &desc->flags); + +@@ -1450,11 +1452,11 @@ int gpio_direction_output(unsigned gpio, int value) + + /* Open drain pin should not be driven to 1 */ + if (value && test_bit(FLAG_OPEN_DRAIN, &desc->flags)) +- return gpio_direction_input(gpio); ++ return gpio_direction_input(gpio, 0); + + /* Open source pin should not be driven to 0 */ + if (!value && test_bit(FLAG_OPEN_SOURCE, &desc->flags)) +- return gpio_direction_input(gpio); ++ return gpio_direction_input(gpio, 0); + + spin_lock_irqsave(&gpio_lock, flags); + +@@ -1604,7 +1606,7 @@ static void _gpio_set_open_drain_value(unsigned gpio, + { + int err = 0; + if (value) { +- err = chip->direction_input(chip, gpio - chip->base); ++ err = chip->direction_input(chip, gpio - chip->base, 0); + if (!err) + clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags); + } else { +@@ -1633,7 +1635,7 @@ static void _gpio_set_open_source_value(unsigned gpio, + if (!err) + set_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags); + } else { +- err = chip->direction_input(chip, gpio - chip->base); ++ err = chip->direction_input(chip, gpio - chip->base, 0); + if (!err) + clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags); + } +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index ea8736bc..2ba35466 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -285,6 +285,18 @@ config I2C_POWERMAC + + comment "I2C system bus drivers (mostly embedded / system-on-chip)" + ++config I2C_GOKE ++ tristate "goke ipc I2C bus support" ++ depends on GK_I2C ++ select I2C_MUX if MACH_GK7101_EVB_SUPPORT_I2C_MUX ++ select I2C_MUX_GK7101 if MACH_GK7101_EVB_SUPPORT_I2C_MUX ++ help ++ This driver supports the goke ipc ++ I2C Bus master controller ++ ++ This driver can also be built as a module. If so, the module ++ will be called goke_i2c_vxx. ++ + config I2C_AT91 + tristate "Atmel AT91 I2C Two-Wire interface (TWI)" + depends on ARCH_AT91 && EXPERIMENTAL && BROKEN +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index 2f05d7b6..4395f856 100644 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -28,6 +28,9 @@ obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o + obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o + + # Embedded system I2C/SMBus host controller drivers ++ifdef CONFIG_I2C_GOKE ++obj-$(CONFIG_GK_I2C_V1_00) += i2c-goke_v1_00.o ++endif + obj-$(CONFIG_I2C_AT91) += i2c-at91.o + obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o + obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o +diff --git a/drivers/i2c/busses/i2c-goke_v1_00.c b/drivers/i2c/busses/i2c-goke_v1_00.c +new file mode 100644 +index 00000000..419e3cb7 +--- /dev/null ++++ b/drivers/i2c/busses/i2c-goke_v1_00.c +@@ -0,0 +1,863 @@ ++/* linux/drivers/i2c/busses/i2c-gk.c ++ * ++ * History: ++ * 2014/07/30 - [Kewell Liu] created file ++ * ++ * Copyright (C) 2002-2014, Goke Microelectronics China. ++ * ++ * GK I2C Controller ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#ifndef CONFIG_I2C_GK_RETRIES ++#define CONFIG_I2C_GK_RETRIES (3) ++#endif ++ ++#ifndef CONFIG_I2C_GK_ACK_TIMEOUT ++#define CONFIG_I2C_GK_ACK_TIMEOUT (1 * HZ) ++#endif ++ ++#define CONFIG_I2C_GK_BULK_RETRY_NUM (4) ++ ++/* i2c controller state */ ++enum gk_i2c_state { ++ I2C_STATE_IDLE, ++ I2C_STATE_START, ++ I2C_STATE_START_TEN, ++ I2C_STATE_START_NEW, ++ I2C_STATE_READ, ++ I2C_STATE_READ_STOP, ++ I2C_STATE_WRITE, ++ I2C_STATE_WRITE_WAIT_ACK, ++ I2C_STATE_BULK_WRITE, ++ I2C_STATE_NO_ACK, ++ I2C_STATE_ERROR ++}; ++ ++struct gk_i2c { ++ spinlock_t lock; ++ unsigned int suspended; ++ ++ struct i2c_msg *msg; ++ unsigned int msg_num; ++ unsigned int msg_idx; ++ unsigned int msg_ptr; ++ unsigned int msg_addr; ++ wait_queue_head_t msg_wait; ++ ++ unsigned int irq; ++ ++ enum gk_i2c_state state; ++ ++ void __iomem *regbase; ++ struct device *dev; ++ struct resource *ioarea; ++ struct i2c_adapter adap; ++ ++ struct gk_platform_i2c *pdata; ++ ++}; ++ ++static inline void gk_i2c_start_single_msg(struct gk_i2c *i2c) ++{ ++ if (i2c->msg->flags & I2C_M_TEN) ++ { ++ i2c->state = I2C_STATE_START_TEN; ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_DATA_OFFSET), ++ (0xf0 | ((i2c->msg_addr >> 8) & 0x07))); ++ } ++ else ++ { ++ i2c->state = I2C_STATE_START; ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_DATA_OFFSET), ++ (i2c->msg_addr & 0xff)); ++ } ++ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_CTRL_OFFSET), ++ IDC_CTRL_START); ++} ++ ++static inline void gk_i2c_bulk_write(struct gk_i2c *i2c, u32 fifosize) ++{ ++ do ++ { ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMDATA_OFFSET), ++ i2c->msg->buf[i2c->msg_idx]); ++ i2c->msg_idx++; ++ fifosize--; ++ ++ if (i2c->msg_idx >= i2c->msg->len) ++ { ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMCTRL_OFFSET), ++ (IDC_FMCTRL_IF | IDC_FMCTRL_STOP)); ++ return; ++ } ++ } while (fifosize > 1); ++ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMCTRL_OFFSET), ++ IDC_FMCTRL_IF); ++} ++ ++static inline void gk_i2c_start_bulk_msg_write(struct gk_i2c *i2c) ++{ ++ u32 fifosize = IDC_FIFO_BUF_SIZE; ++ ++ i2c->state = I2C_STATE_BULK_WRITE; ++ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMCTRL_OFFSET), ++ IDC_FMCTRL_START); ++ ++ if (i2c->msg->flags & I2C_M_TEN) { ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMDATA_OFFSET), ++ (0xf0 | ((i2c->msg_addr >> 8) & 0x07))); ++ fifosize--; ++ } ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_FMDATA_OFFSET), ++ (i2c->msg_addr & 0xff)); ++ fifosize -= 2; ++ ++ gk_i2c_bulk_write(i2c, fifosize); ++} ++ ++/* gk_i2c_message_start ++ * ++ * put the start of a message onto the bus ++ */ ++static void gk_i2c_message_start(struct gk_i2c *i2c) ++{ ++ struct i2c_msg *msg = i2c->msg; ++ i2c->msg_idx = 0; ++ ++ i2c->msg_addr = ((msg->addr & 0x7f) << 1); ++ ++ if (msg->flags & I2C_M_RD) ++ i2c->msg_addr |= 1; ++ ++ if (msg->flags & I2C_M_REV_DIR_ADDR) ++ i2c->msg_addr ^= 1; ++ ++ if (msg->flags & I2C_M_RD) { ++ gk_i2c_start_single_msg(i2c); ++ } else if (msg->len > i2c->pdata->bulk_write_num) { ++ gk_i2c_start_bulk_msg_write(i2c); ++ } else { ++ gk_i2c_start_single_msg(i2c); ++ } ++ ++ dev_dbg(i2c->dev, "msg_addr[0x%x], len[0x%x]", i2c->msg_addr, i2c->msg->len); ++ ++} ++ ++static inline void gk_i2c_stop(struct gk_i2c *i2c, enum gk_i2c_state state, u32 *pack) ++{ ++ if(state != I2C_STATE_IDLE) { ++ //dev_warn(i2c->dev, "gk_i2c_stop[%d] from %d to %d\n", i2c->msg_num, i2c->state, state); ++ *pack |= IDC_CTRL_ACK; ++ } ++ ++ i2c->state = state; ++ i2c->msg = NULL; ++ i2c->msg_num = 0; ++ ++ *pack |= IDC_CTRL_STOP; ++ // StevenYu:Do not check state. ++ //if(i2c->state == I2C_STATE_IDLE) ++ wake_up(&i2c->msg_wait); ++} ++ ++static inline u32 gk_i2c_check_ack(struct gk_i2c *i2c, u32 *pack, u32 retry) ++{ ++ u32 retVal = IDC_CTRL_ACK; ++ //printk("gk_i2c_check_ack...\n"); ++ ++gk_i2c_check_ack_enter: ++ if (((*pack) & IDC_CTRL_ACK)==0) ++ //if (unlikely((*pack) & IDC_CTRL_ACK)) ++ { ++ //printk("pack: 0x%x\n", *pack); ++ if (i2c->msg->flags & I2C_M_IGNORE_NAK) ++ goto gk_i2c_check_ack_exit; ++ ++ if ((i2c->msg->flags & I2C_M_RD) && ++ (i2c->msg->flags & I2C_M_NO_RD_ACK)) ++ goto gk_i2c_check_ack_exit; ++ ++ if (retry--) { ++ udelay(100); ++ *pack = gk_i2c_readl((unsigned int)(i2c->regbase + IDC_CTRL_OFFSET)); ++ //printk("pack = 0x%x \n", *pack); ++ goto gk_i2c_check_ack_enter; ++ } ++ retVal = 0; ++ gk_i2c_stop(i2c, I2C_STATE_NO_ACK, pack); ++ } ++ ++gk_i2c_check_ack_exit: ++ return retVal; ++ ++} ++ ++/* gk_i2c_set_clk ++ * ++ * work out a divisor for the user requested frequency setting, ++ * either by the requested frequency, or scanning the acceptable ++ * range of frequencies until something is found ++*/ ++static void gk_i2c_set_clk(struct gk_i2c *i2c) ++{ ++ unsigned int apb_clk; ++ unsigned int idc_prescale; ++ ++ apb_clk = i2c->pdata->get_clock(); ++ //apb_clk = 30000000; ++ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_ENR_OFFSET), ++ IDC_ENR_DISABLE); ++ ++ if ((i2c->pdata->clk_limit < 1000) || ++ (i2c->pdata->clk_limit > 400000)) ++ { ++ i2c->pdata->clk_limit = 100000; ++ } ++ ++// prescale = ((GD_GET_APB_ClkHz()/(U32)openParamsP->speed - 2) >> 2) - 1; ++ ++ idc_prescale = ((apb_clk / i2c->pdata->clk_limit -2) >> 2) - 1; ++ ++ //dev_dbg(i2c->dev, "apb_clk[%dHz]\n", apb_clk); ++ //dev_dbg(i2c->dev, "idc_prescale[%d]\n", idc_prescale); ++ //dev_dbg(i2c->dev, "clk[%dHz]\n", i2c->pdata->clk_limit); ++ ++ //dev_dbg(i2c->dev, "regbase 0x%08x\n", i2c->regbase); ++ ++ //gk_writel(i2c->regbase + IDC_PSLL_OFFSET, (idc_prescale & 0xff)); ++ //gk_writel(i2c->regbase + IDC_PSLH_OFFSET, ((idc_prescale & 0xff00) >> 8)); ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_PSLL_OFFSET), ++ (idc_prescale & 0xffff)); ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_ENR_OFFSET), ++ (IDC_ENR_ENABLE)); ++ ++ //dev_info(i2c->dev, "IDC_PSLL_OFFSET 0x%08x\n", gk_readb(i2c->regbase + IDC_PSLL_OFFSET)); ++ //dev_info(i2c->dev, "IDC_PSLH_OFFSET 0x%08x\n", gk_readb(i2c->regbase + IDC_PSLH_OFFSET)); ++ //dev_info(i2c->dev, "IDC_ENR_OFFSET 0x%08x\n", gk_readb(i2c->regbase + IDC_ENR_OFFSET)); ++ ++} ++ ++static inline void gk_i2c_hw_off(struct gk_i2c *i2c) ++{ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_ENR_OFFSET), ++ IDC_ENR_DISABLE); ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_PSLL_OFFSET), 0); ++ //gk_writeb(i2c->regbase + IDC_PSLH_OFFSET, 0); ++} ++ ++/* gk_i2c_init ++ * ++ * initialise the controller, set the IO lines and frequency ++*/ ++static int gk_i2c_init(struct gk_i2c *i2c) ++{ ++ gk_i2c_set_clk(i2c); ++ ++ i2c->msg = NULL; ++ i2c->msg_num = 0; ++ i2c->state = I2C_STATE_IDLE; ++ ++ return 0; ++} ++ ++static irqreturn_t gk_i2c_irq(int irqno, void *dev_id) ++{ ++ struct platform_device *pdev; ++ struct gk_i2c *i2c; ++ ++ u32 status_reg; ++ u32 control_reg; ++ u32 ack_control = IDC_CTRL_CLS; ++ ++ i2c = (struct gk_i2c *)dev_id; ++ pdev = (struct platform_device *)i2c->dev->platform_data; ++ ++ status_reg = gk_i2c_readl((unsigned int)(i2c->regbase + IDC_STS_OFFSET)); ++ control_reg = gk_i2c_readl((unsigned int)(i2c->regbase + IDC_CTRL_OFFSET)); ++ ++ //dev_dbg(i2c->dev, "i2c[%d]:state[0x%x]\n", pdev->id, i2c->state); ++ //dev_dbg(i2c->dev, "i2c[%d]:status_reg[0x%x]\n", pdev->id, status_reg); ++ //dev_dbg(i2c->dev, "i2c[%d]:control_reg[0x%x]\n", pdev->id, control_reg); ++ ++ switch (i2c->state) ++ { ++ case I2C_STATE_START: ++ if (gk_i2c_check_ack(i2c, &control_reg, 0) == IDC_CTRL_ACK) ++ { ++ if (i2c->msg->flags & I2C_M_RD) ++ { ++ if (i2c->msg->len == 1) ++ ack_control |= IDC_CTRL_ACK; ++ i2c->state = I2C_STATE_READ; ++ } ++ else ++ { ++ i2c->state = I2C_STATE_WRITE; ++ goto i2c_irq_write; ++ } ++ } ++ break; ++ case I2C_STATE_START_TEN: ++ i2c->state = I2C_STATE_START; ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_DATA_OFFSET), ++ (i2c->msg_addr & 0xff)); ++ break; ++ case I2C_STATE_START_NEW: ++i2c_irq_start_new: ++ gk_i2c_message_start(i2c); ++ goto i2c_irq_exit; ++ break; ++ case I2C_STATE_READ_STOP: ++ i2c->msg->buf[i2c->msg_idx] = ++ gk_i2c_readl((unsigned int)(i2c->regbase + IDC_DATA_OFFSET)); ++ i2c->msg_idx++; ++i2c_irq_read_stop: ++ gk_i2c_stop(i2c, I2C_STATE_IDLE, &ack_control); ++ break; ++ case I2C_STATE_READ: ++ i2c->msg->buf[i2c->msg_idx] = ++ gk_i2c_readl((unsigned int)(i2c->regbase + IDC_DATA_OFFSET)); ++ i2c->msg_idx++; ++ ++ if (i2c->msg_idx >= i2c->msg->len - 1) ++ { ++ if (i2c->msg_num > 1) ++ { ++ i2c->msg++; ++ i2c->state = I2C_STATE_START_NEW; ++ i2c->msg_num--; ++ } ++ else ++ { ++ if (i2c->msg_idx > i2c->msg->len - 1) ++ { ++ goto i2c_irq_read_stop; ++ } ++ else ++ { ++ i2c->state = I2C_STATE_READ_STOP; ++ ack_control |= IDC_CTRL_ACK; ++ } ++ } ++ } ++ //ack_control |= IDC_CTRL_ACK; ++ break; ++ case I2C_STATE_WRITE: ++i2c_irq_write: ++ i2c->state = I2C_STATE_WRITE_WAIT_ACK; ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_DATA_OFFSET), ++ i2c->msg->buf[i2c->msg_idx]); ++ break; ++ case I2C_STATE_WRITE_WAIT_ACK: ++ if (gk_i2c_check_ack(i2c, &control_reg, 0) == IDC_CTRL_ACK) ++ { ++ i2c->state = I2C_STATE_WRITE; ++ i2c->msg_idx++; ++ ++ if (i2c->msg_idx >= i2c->msg->len) ++ { ++ if (i2c->msg_num > 1) ++ { ++ i2c->msg++; ++ i2c->state = I2C_STATE_START_NEW; ++ i2c->msg_num--; ++ goto i2c_irq_start_new; ++ } ++ gk_i2c_stop(i2c, I2C_STATE_IDLE, &ack_control); ++ } ++ else ++ { ++ goto i2c_irq_write; ++ } ++ } ++ break; ++ case I2C_STATE_BULK_WRITE: ++ if (gk_i2c_check_ack(i2c, &control_reg, CONFIG_I2C_GK_BULK_RETRY_NUM) == IDC_CTRL_ACK) ++ { ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_CTRL_OFFSET), ++ IDC_CTRL_ACK); ++ if (i2c->msg_idx >= i2c->msg->len) ++ { ++ if (i2c->msg_num > 1) ++ { ++ i2c->msg++; ++ i2c->state = I2C_STATE_START_NEW; ++ i2c->msg_num--; ++ goto i2c_irq_start_new; ++ } ++ gk_i2c_stop(i2c, I2C_STATE_IDLE, &ack_control); ++ } ++ else ++ { ++ gk_i2c_bulk_write(i2c, IDC_FIFO_BUF_SIZE); ++ } ++ goto i2c_irq_exit; ++ } ++ else ++ { ++ ack_control = IDC_CTRL_ACK; ++ } ++ break; ++ default: ++ dev_err(i2c->dev, "i2c[%d]:gk_i2c_irq in wrong state[0x%x]\n", pdev->id, i2c->state); ++ //dev_err(i2c->dev, "i2c[%d]:status_reg[0x%x]\n", pdev->id, status_reg); ++ //dev_err(i2c->dev, "i2c[%d]:control_reg[0x%x]\n", pdev->id, control_reg); ++ ack_control = IDC_CTRL_STOP | IDC_CTRL_ACK; ++ i2c->state = I2C_STATE_ERROR; ++ break; ++ } ++ ++ gk_i2c_writel((unsigned int)(i2c->regbase + IDC_CTRL_OFFSET), ack_control); ++ ++i2c_irq_exit: ++ return IRQ_HANDLED; ++ ++} ++ ++/* gk_i2c_doxfer ++ * ++ * this starts an i2c transfer ++ */ ++static int gk_i2c_doxfer(struct gk_i2c *i2c, struct i2c_msg *msgs, int num) ++{ ++ unsigned long timeout; ++ int ret; ++ ++ if (i2c->suspended) return -EIO; ++ ++ spin_lock_irq(&i2c->lock); ++ ++ i2c->msg = msgs; ++ i2c->msg_num = num; ++ i2c->msg_ptr = 0; ++ i2c->msg_idx = 0; ++ i2c->state = I2C_STATE_START; ++ ++ gk_i2c_message_start(i2c); ++ spin_unlock_irq(&i2c->lock); ++ ++ // StevenYu:delete the delay. ++ //mdelay(1); ++ timeout = wait_event_timeout(i2c->msg_wait, i2c->msg_num == 0, CONFIG_I2C_GK_ACK_TIMEOUT); ++ ++ ret = i2c->msg_idx; ++ ++ /* having these next two as dev_err() makes life very ++ * noisy when doing an i2cdetect */ ++ ++ if (timeout == 0) ++ dev_dbg(i2c->dev, "timeout\n"); ++ else if (ret != num) ++ dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); ++ ++ /* ensure the stop has been through the bus */ ++ dev_dbg(i2c->dev, "%ld jiffies left.\n", timeout); ++ ++ if (i2c->state != I2C_STATE_IDLE) ++ { ++ dev_err(i2c->dev,"I2C state 0x%d, please check address 0x%x!\n", i2c->state, i2c->msg_addr); ++ ret = -EAGAIN; ++ } ++ ++ return ret; ++ ++} ++ ++static int gk_i2c_doxfer_noevent(struct gk_i2c *i2c, struct i2c_msg *msgs, int num) ++{ ++ unsigned long timeout; ++ int ret; ++ unsigned long flags; ++ ++ if (i2c->suspended) return -EIO; ++ ++ spin_lock_irq(&i2c->lock); ++ i2c->msg = msgs; ++ i2c->msg_num = num; ++ i2c->msg_ptr = 0; ++ i2c->msg_idx = 0; ++ i2c->state = I2C_STATE_START; ++ gk_i2c_message_start(i2c); ++ spin_unlock_irq(&i2c->lock); ++ ++ while(i2c->state != I2C_STATE_IDLE) ++ { ++ udelay(10); ++ } ++ ++ ret = i2c->msg_idx; ++ ++ /* having these next two as dev_err() makes life very ++ * noisy when doing an i2cdetect */ ++ ++ if (timeout == 0) ++ dev_dbg(i2c->dev, "timeout\n"); ++ else if (ret != num) ++ dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); ++ ++ /* ensure the stop has been through the bus */ ++ dev_dbg(i2c->dev, "%ld jiffies left.\n", timeout); ++ ++ if (i2c->state != I2C_STATE_IDLE) ++ { ++ dev_err(i2c->dev,"I2C state 0x%d, please check address 0x%x!\n", i2c->state, i2c->msg_addr); ++ ret = -EAGAIN; ++ } ++ ++ return ret; ++} ++ ++/* gk_i2c_xfer ++ * ++ * first port of call from the i2c bus code when an message needs ++ * transferring across the i2c bus. ++ */ ++ ++static int gk_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) ++{ ++ struct gk_i2c *i2c = (struct gk_i2c *)adap->algo_data; ++ int retry; ++ int ret; ++ ++ //pm_runtime_get_sync(&adap->dev); ++ ++ for (retry = 0; retry < adap->retries; retry++) ++ { ++ if (i2c->state != I2C_STATE_IDLE) ++ { ++ gk_i2c_init(i2c); ++ } ++ ++ ret = gk_i2c_doxfer(i2c, msgs, num); ++ //printk("do xfer ret: %d \n", ret); ++ if (ret != -EAGAIN) ++ { ++ //pm_runtime_put_sync(&adap->dev); ++ return num;//ret; ++ } ++ ++ dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); ++ ++ udelay(100); ++ } ++ ++ //pm_runtime_put_sync(&adap->dev); ++ return -EREMOTEIO; ++ ++} ++ ++ ++static int gk_i2c_xfer_noevent(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) ++{ ++ struct gk_i2c *i2c = (struct gk_i2c *)adap->algo_data; ++ int retry; ++ int ret; ++ ++ //pm_runtime_get_sync(&adap->dev); ++ ++ for (retry = 0; retry < adap->retries; retry++) ++ { ++ if (i2c->state != I2C_STATE_IDLE) ++ { ++ gk_i2c_init(i2c); ++ } ++ ++ ret = gk_i2c_doxfer_noevent(i2c, msgs, num); ++ //printk("do xfer ret: %d \n", ret); ++ if (ret != -EAGAIN) ++ { ++ //pm_runtime_put_sync(&adap->dev); ++ return num;//ret; ++ } ++ ++ dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); ++ ++ udelay(100); ++ } ++ ++ //pm_runtime_put_sync(&adap->dev); ++ return -EREMOTEIO; ++ ++} ++/* declare our i2c functionality */ ++static u32 gk_i2c_func(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; ++} ++ ++/* i2c bus registration info */ ++ ++static const struct i2c_algorithm gk_i2c_algorithm = { ++ .master_xfer = gk_i2c_xfer, ++ .master_xfer_noevent = gk_i2c_xfer_noevent, ++ .functionality = gk_i2c_func, ++}; ++ ++/* gk_i2c_probe ++ * ++ * called by the bus driver when a suitable device is found ++ */ ++ ++static int gk_i2c_probe(struct platform_device *pdev) ++{ ++ struct gk_i2c *i2c; ++ struct gk_platform_i2c *pdata = NULL; ++ struct resource *res; ++ ++ int ret; ++ ++ pdata = (struct gk_platform_i2c *)pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "i2c[%d]: Can't get platform_data!\n", pdev->id); ++ return -EINVAL; ++ } ++ ++ i2c = devm_kzalloc(&pdev->dev, sizeof(struct gk_i2c), GFP_KERNEL); ++ if (!i2c) { ++ dev_err(&pdev->dev, "no memory for i2c[%d]\n", pdev->id); ++ return -ENOMEM; ++ } ++ ++ /* setup info block for the i2c core */ ++ strlcpy(i2c->adap.name, pdev->name, sizeof(i2c->adap.name)); ++ i2c->adap.owner = THIS_MODULE; ++ i2c->adap.algo = &gk_i2c_algorithm; ++ i2c->adap.retries = CONFIG_I2C_GK_RETRIES; ++ i2c->adap.class = (I2C_CLASS_HWMON | I2C_CLASS_SPD); ++ i2c->adap.nr = pdev->id; ++ i2c->adap.algo_data = i2c; ++ i2c->adap.dev.parent = &pdev->dev; ++ ++ i2c->pdata = pdata; ++ ++ spin_lock_init(&i2c->lock); ++ init_waitqueue_head(&i2c->msg_wait); ++ ++ /* find the clock and enable it */ ++ i2c->dev = &pdev->dev; ++ ++ /* map the registers */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(&pdev->dev, "Get I2C[%d] mem resource failed!\n", pdev->id); ++ ret = -ENOENT; ++ goto err_noclk; ++ } ++#if 0 ++ ++ i2c->ioarea = request_mem_region(res->start, resource_size(res), pdev->name); ++ if (i2c->ioarea == NULL) { ++ dev_err(&pdev->dev, "Request I2C[%d] ioarea failed!\n", pdev->id); ++ ret = -ENXIO; ++ goto err_noclk; ++ } ++ ++ ++ i2c->regbase = ioremap(res->start, resource_size(res)); ++ if (i2c->regbase == NULL) { ++ dev_err(&pdev->dev, "i2c[%d] cannot map IO\n", pdev->id); ++ ret = -ENXIO; ++ goto err_ioarea; ++ } ++ dev_err(&pdev->dev, "i2c[%d]:registers %p (%p, %p)\n", pdev->id, i2c->regbase, i2c->ioarea, res); ++#else ++ i2c->regbase = (void __iomem*)res->start; ++ printk("i2c regbase: 0x%x \n", (u32)i2c->regbase); ++#endif ++ ++ /* initialise the i2c controller */ ++ ret = gk_i2c_init(i2c); ++ if (ret != 0) ++ goto err_iomap; ++ ++ /* find the IRQ for this unit (note, this relies on the init call to ++ * ensure no current IRQs pending ++ */ ++ i2c->irq = ret = platform_get_irq(pdev, 0); ++ if (ret <= 0) { ++ dev_err(&pdev->dev, "Get I2C[%d] irq resource failed!\n", pdev->id); ++ goto err_iomap; ++ } ++ ++ dev_info(&pdev->dev, "i2c irq:registers %d\n", i2c->irq); ++ ret = request_irq(i2c->irq, gk_i2c_irq, IRQF_TRIGGER_HIGH, dev_name(&pdev->dev), i2c); ++ if (ret != 0) { ++ dev_err(&pdev->dev, "Request i2c[%d] IRQ=%d failed!\n", pdev->id, i2c->irq); ++ goto err_iomap; ++ } ++ ++ i2c_set_adapdata(&i2c->adap, i2c); ++ /* Note, previous versions of the driver used i2c_add_adapter() ++ * to add the bus at any number. We now pass the bus number via ++ * the platform data, so if unset it will now default to always ++ * being bus 0. ++ */ ++ ret = i2c_add_numbered_adapter(&i2c->adap); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "i2c[%d] Failed to add bus to i2c core\n", pdev->id); ++ goto err_irq; ++ } ++ ++ platform_set_drvdata(pdev, i2c); ++ ++ //pm_runtime_enable(&pdev->dev); ++ //pm_runtime_enable(&i2c->adap.dev); ++ ++ dev_info(&pdev->dev, "GK I2C[%d] adapter[%s] probed!\n", pdev->id, dev_name(&i2c->adap.dev)); ++ return 0; ++ ++ err_irq: ++ free_irq(i2c->irq, i2c); ++ ++ err_iomap: ++// iounmap(i2c->regbase); ++ ++ //err_ioarea: ++ //release_mem_region(i2c->ioarea->start, (i2c->ioarea->end - i2c->ioarea->start) + 1); ++ kfree(i2c); ++ ++ err_noclk: ++ return ret; ++ ++} ++ ++/* gk_i2c_remove ++ * ++ * called when device is removed from the bus ++*/ ++ ++static int gk_i2c_remove(struct platform_device *pdev) ++{ ++ struct gk_i2c *i2c = platform_get_drvdata(pdev); ++ ++ if(i2c) ++ { ++ gk_i2c_hw_off(i2c); ++ ++ //pm_runtime_disable(&i2c->adap.dev); ++ //pm_runtime_disable(&pdev->dev); ++ ++ i2c_del_adapter(&i2c->adap); ++ free_irq(i2c->irq, i2c); ++#if 0 ++ iounmap(i2c->regbase); ++ ++ release_mem_region(i2c->ioarea->start, (i2c->ioarea->end - i2c->ioarea->start) + 1); ++#endif ++ kfree(i2c); ++ } ++ ++ return 0; ++ ++} ++ ++#ifdef CONFIG_PM ++static int gk_i2c_suspend_noirq(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct gk_i2c *i2c = platform_get_drvdata(pdev); ++ ++ if(i2c){ ++ i2c->suspended = 1; ++ disable_irq(i2c->irq); ++ } ++ ++ dev_dbg(&pdev->dev, "%s\n", __func__); ++ ++ return 0; ++} ++ ++static int gk_i2c_resume(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct gk_i2c *i2c = platform_get_drvdata(pdev); ++ ++ if(i2c){ ++ i2c->suspended = 0; ++ gk_i2c_init(i2c); ++ } ++ ++ dev_dbg(&pdev->dev, "%s\n", __func__); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops gk_i2c_dev_pm_ops = { ++ .suspend_noirq = gk_i2c_suspend_noirq, ++ .resume = gk_i2c_resume, ++}; ++ ++#define GK_I2C_DEV_PM_OPS (&gk_i2c_dev_pm_ops) ++#else ++#define GK_I2C_DEV_PM_OPS NULL ++#endif ++ ++/* device driver for platform bus bits */ ++static struct platform_driver gk_i2c_driver = { ++ .probe = gk_i2c_probe, ++ .remove = gk_i2c_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "i2c", ++ .pm = GK_I2C_DEV_PM_OPS, ++ }, ++}; ++ ++static int __init gk_i2c_adap_init(void) ++{ ++ return platform_driver_register(&gk_i2c_driver); ++} ++subsys_initcall(gk_i2c_adap_init); ++ ++static void __exit gk_i2c_adap_exit(void) ++{ ++ platform_driver_unregister(&gk_i2c_driver); ++} ++module_exit(gk_i2c_adap_exit); ++ ++MODULE_DESCRIPTION("GK I2C Bus driver"); ++MODULE_AUTHOR("Kewell Liu, "); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c +index feb7dc35..c1485fc6 100644 +--- a/drivers/i2c/i2c-core.c ++++ b/drivers/i2c/i2c-core.c +@@ -1366,6 +1366,40 @@ int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) + } + EXPORT_SYMBOL(i2c_transfer); + ++int i2c_transfer_noevent(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) ++{ ++ unsigned long orig_jiffies; ++ int ret, try; ++ ++ /* REVISIT the fault reporting model here is weak: ++ * ++ * - When we get an error after receiving N bytes from a slave, ++ * there is no way to report "N". ++ * ++ * - When we get a NAK after transmitting N bytes to a slave, ++ * there is no way to report "N" ... or to let the master ++ * continue executing the rest of this combined message, if ++ * that's the appropriate response. ++ * ++ * - When for example "num" is two and we successfully complete ++ * the first message but get an error part way through the ++ * second, it's unclear whether that should be reported as ++ * one (discarding status on the second message) or errno ++ * (discarding status on the first one). ++ */ ++ /* Retry automatically on arbitration loss */ ++ orig_jiffies = jiffies; ++ for (ret = 0, try = 0; try <= adap->retries; try++) { ++ ret = adap->algo->master_xfer_noevent(adap, msgs, num); ++ if (ret != -EAGAIN) ++ break; ++ if (time_after(jiffies, orig_jiffies + adap->timeout)) ++ break; ++ } ++ return ret; ++} ++EXPORT_SYMBOL(i2c_transfer_noevent); ++ + /** + * i2c_master_send - issue a single I2C message in master transmit mode + * @client: Handle to slave device +diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig +index 90b7a016..c2e955ce 100644 +--- a/drivers/i2c/muxes/Kconfig ++++ b/drivers/i2c/muxes/Kconfig +@@ -17,6 +17,17 @@ config I2C_MUX_GPIO + This driver can also be built as a module. If so, the module + will be called gpio-i2cmux. + ++config I2C_MUX_GOKE ++ tristate "goke ipc I2C multiplexer" ++ depends on I2C_GOKE ++ help ++ If you say yes to this option, support will be included for a ++ goke ipc I2C multiplexer. This driver provides access to ++ I2C busses with an internal MUX, which is controlled ++ through GPIO pin functions. ++ This driver can also be built as a module. If so, the module ++ will be called goke-i2cmux_v1_00. ++ + config I2C_MUX_PCA9541 + tristate "NXP PCA9541 I2C Master Selector" + depends on EXPERIMENTAL +diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile +index 4640436e..d9996612 100644 +--- a/drivers/i2c/muxes/Makefile ++++ b/drivers/i2c/muxes/Makefile +@@ -5,4 +5,8 @@ obj-$(CONFIG_I2C_MUX_GPIO) += gpio-i2cmux.o + obj-$(CONFIG_I2C_MUX_PCA9541) += pca9541.o + obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o + ++ifdef CONFIG_I2C_MUX_GOKE ++obj-$(CONFIG_GK_I2C_V1_00) += goke-i2cmux_v1_00.o ++endif ++ + ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG +diff --git a/drivers/i2c/muxes/goke-i2cmux_v1_00.c b/drivers/i2c/muxes/goke-i2cmux_v1_00.c +new file mode 100644 +index 00000000..98ae11da +--- /dev/null ++++ b/drivers/i2c/muxes/goke-i2cmux_v1_00.c +@@ -0,0 +1,134 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct gk_mux { ++ struct i2c_adapter *parent; ++ struct i2c_adapter *adap; /* child busses */ ++ struct gk_i2cmux_platform_data data; ++}; ++ ++static int gk_mux_select(struct i2c_adapter *adap, void *data, u32 chan) ++{ ++ struct gk_mux *mux = data; ++ ++ gk_gpio_config(mux->data.gpio, mux->data.select_function); ++ ++ return 0; ++} ++ ++static int gk_mux_deselect(struct i2c_adapter *adap, void *data, u32 chan) ++{ ++ struct gk_mux *mux = data; ++ ++ gk_gpio_config(mux->data.gpio, mux->data.deselect_function); ++ ++ return 0; ++} ++ ++static int __devinit gk_mux_probe(struct platform_device *pdev) ++{ ++ struct gk_mux *mux; ++ struct gk_i2cmux_platform_data *pdata; ++ struct i2c_adapter *parent; ++ int ret = 0; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "Missing platform data\n"); ++ return -ENODEV; ++ } ++ ++ parent = i2c_get_adapter(pdata->parent); ++ if (!parent) { ++ dev_err(&pdev->dev, "Parent adapter (%d) not found\n", ++ pdata->parent); ++ return -ENODEV; ++ } ++ ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ if (!mux) { ++ ret = -ENOMEM; ++ goto alloc_failed; ++ } ++ ++ mux->parent = parent; ++ mux->data = *pdata; ++ mux->adap = i2c_add_mux_adapter(parent, mux, pdata->number, 0, ++ gk_mux_select, gk_mux_deselect); ++ if (!mux->adap) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "Failed to add mux adapter\n"); ++ goto add_adapter_failed; ++ } ++ ++ gk_mux_deselect(mux->adap, mux, 0); ++ dev_info(&pdev->dev, "mux on %s adapter\n", parent->name); ++ ++ platform_set_drvdata(pdev, mux); ++ ++ goto gk_mux_probe_exit; ++ ++add_adapter_failed: ++ i2c_del_mux_adapter(mux->adap); ++ kfree(mux); ++ ++alloc_failed: ++ i2c_put_adapter(parent); ++ ++gk_mux_probe_exit: ++ return ret; ++} ++ ++static int __devexit gk_mux_remove(struct platform_device *pdev) ++{ ++ struct gk_mux *mux; ++ ++ mux = platform_get_drvdata(pdev); ++ if (mux) { ++ i2c_del_mux_adapter(mux->adap); ++ platform_set_drvdata(pdev, NULL); ++ i2c_put_adapter(mux->parent); ++ kfree(mux); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver gk_mux_driver = { ++ .probe = gk_mux_probe, ++ .remove = __devexit_p(gk_mux_remove), ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "gk-i2cmux", ++ }, ++}; ++ ++static int __init gk_mux_init(void) ++{ ++ return platform_driver_register(&gk_mux_driver); ++} ++ ++static void __exit gk_mux_exit(void) ++{ ++ platform_driver_unregister(&gk_mux_driver); ++} ++ ++subsys_initcall(gk_mux_init); ++module_exit(gk_mux_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("GOKE MICROELECTRONICS Inc."); ++MODULE_DESCRIPTION("GOKE I2C Driver"); ++ +diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig +index 7faf4a7f..957397f6 100644 +--- a/drivers/input/misc/Kconfig ++++ b/drivers/input/misc/Kconfig +@@ -12,6 +12,12 @@ menuconfig INPUT_MISC + + if INPUT_MISC + ++config INPUT_GOKE_IR ++ tristate "Support goke ipc IR" ++ depends on GK_IR ++ help ++ gk7101 general input. It can support Virtual input from proc, IR and GPIO. ++ + config INPUT_88PM860X_ONKEY + tristate "88PM860x ONKEY support" + depends on MFD_88PM860X +diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile +index f55cdf49..b43b7aa5 100644 +--- a/drivers/input/misc/Makefile ++++ b/drivers/input/misc/Makefile +@@ -4,6 +4,10 @@ + + # Each configuration option enables a list of files. + ++ifdef CONFIG_INPUT_GOKE_IR ++obj-$(CONFIG_GK_IR_V1_00) += gk_ir_v1_00.o ++endif ++ + obj-$(CONFIG_INPUT_88PM860X_ONKEY) += 88pm860x_onkey.o + obj-$(CONFIG_INPUT_AB8500_PONKEY) += ab8500-ponkey.o + obj-$(CONFIG_INPUT_AD714X) += ad714x.o +diff --git a/drivers/input/misc/gk_ir_nec.c b/drivers/input/misc/gk_ir_nec.c +new file mode 100644 +index 00000000..2d298375 +--- /dev/null ++++ b/drivers/input/misc/gk_ir_nec.c +@@ -0,0 +1,320 @@ ++/* ++ * drivers/input/misc/gk_ir_nec.c ++ * ++ */ ++ ++#include ++#include ++ ++#include ++ ++/** ++ * Pulse-Width-Coded Signals vary the length of pulses to code the information. ++ * In this case if the pulse width is short (approximately 550us) it ++ * corresponds to a logical zero or a low. If the pulse width is long ++ * (approximately 2200us) it corresponds to a logical one or a high. ++ * ++ * +--+ +--+ +----+ +----+ ++ * | | | | | | | | ++ * ---+ +--+ +--+ +--+ +--- ++ * 0 0 1 1 ++ */ ++ ++/* NEC - APEX - HITACHI - PIONEER */ ++#define NEC_DEFAULT_FREQUENCY 36000 /* 36KHz */ ++#define NEC_DEFAULT_SMALLER_TIME 560 /* T, 560 microseconds. */ ++ ++/** bit 0 [1120us] ++ * ---+ +----+ ++ * | | | ++ * +----+ +--- ++ * -T +T ++ */ ++ ++/** bit 1 [2240us] ++ * ---+ +------------+ ++ * | | | ++ * +----+ +--- ++ * -T +3T ++ */ ++ ++/** start [13.3ms] ++ * ---+ +---------------+ ++ * | | | ++ * +--------------------------------+ +--- ++ * -16T(9ms) +7.5T(4.2ms) ++ */ ++ ++/** Subsequent Frame [11.3ms] ++ * ---+ +--------+ +--- ++ * | | | | ++ * +--------------------------------+ +--+ ++ * -16T(9ms) +4T(2.2ms) ++ */ ++ ++#define NEC_LEADER_LOW_UPBOUND 123 /* default 9ms */ ++#define NEC_LEADER_LOW_LOWBOUND 113 ++#define NEC_LEADER_HIGH_UPBOUND 63 /* default 4.2ms */ ++#define NEC_LEADER_HIGH_LOWBOUND 52 ++ ++#define SAM_LEADER_LOW_UPBOUND 64 /* default 4.5ms */ ++#define SAM_LEADER_LOW_LOWBOUND 50 ++#define SAM_LEADER_HIGH_UPBOUND 64 /* default 4.5ms */ ++#define SAM_LEADER_HIGH_LOWBOUND 50 ++ ++#define NEC_REPEAT_LOW_UPBOUND 123 /* default 9ms */ ++#define NEC_REPEAT_LOW_LOWBOUND 113 ++#define NEC_REPEAT_HIGH_UPBOUND 33 /* default 2.2ms */ ++#define NEC_REPEAT_HIGH_LOWBOUND 23 ++ ++#define NEC_DATA_LOW_UPBOUND 12 /* default 560us */ ++#define NEC_DATA_LOW_LOWBOUND 1 ++#define NEC_DATA_0_HIGH_UPBOUND 12 /* default 560us */ ++#define NEC_DATA_0_HIGH_LOWBOUND 1 ++#define NEC_DATA_1_HIGH_UPBOUND 26 /* default 1680us */ ++#define NEC_DATA_1_HIGH_LOWBOUND 15 ++ ++/** ++ * Check the waveform data is leader code or not. ++ */ ++static int gk_ir_nec_pulse_leader_code(struct gk_ir_info *pinfo) ++{ ++ int check_sam = 0; ++ ++ u16 val = gk_ir_read_data(pinfo, pinfo->ir_pread); ++ ++ if ((val < NEC_LEADER_LOW_UPBOUND) && ++ (val > NEC_LEADER_LOW_LOWBOUND)) { ++ } else { ++ if ((val < SAM_LEADER_LOW_UPBOUND) && ++ (val > SAM_LEADER_LOW_LOWBOUND)) { ++ check_sam = 1; ++ } else { ++ return 0; ++ } ++ } ++ ++ if ((pinfo->ir_pread + 1) >= MAX_IR_BUFFER) { ++ val = gk_ir_read_data(pinfo, 0); ++ } else { ++ val = gk_ir_read_data(pinfo, pinfo->ir_pread + 1); ++ } ++ ++ if (check_sam) { ++ if ((val < SAM_LEADER_HIGH_UPBOUND) && ++ (val > SAM_LEADER_HIGH_LOWBOUND) ) ++ return 1; ++ else ++ return 0; ++ } else { ++ if ((val < NEC_LEADER_HIGH_UPBOUND) && ++ (val > NEC_LEADER_HIGH_LOWBOUND) ) ++ return 1; ++ else ++ return 0; ++ } ++} ++ ++static int gk_ir_nec_find_head(struct gk_ir_info *pinfo) ++{ ++ int i, val = 0; ++ ++ i = gk_ir_get_tick_size(pinfo) - pinfo->frame_info.frame_head_size + 1; ++ ++ while(i--) { ++ if(gk_ir_nec_pulse_leader_code(pinfo)) { ++ dev_dbg(&pinfo->pinput_dev->dev, "find leader code, i [%d]\n", i); ++ val = 1; ++ break; ++ } else { ++ dev_dbg(&pinfo->pinput_dev->dev, "didn't find leader code, i [%d]\n", i); ++ gk_ir_move_read_ptr(pinfo, 1); ++ } ++ } ++ ++ return val ; ++} ++/** ++ * Check the waveform data is subsequent code or not. ++ */ ++static int gk_ir_nec_pulse_subsequent_code(struct gk_ir_info *pinfo) ++{ ++ u16 val = gk_ir_read_data(pinfo, pinfo->ir_pread); ++ ++ if ((val < NEC_REPEAT_LOW_UPBOUND) && ++ (val > NEC_REPEAT_LOW_LOWBOUND)) { ++ } else { ++ return 0; ++ } ++ ++ if ((pinfo->ir_pread + 1) >= MAX_IR_BUFFER) { ++ val = gk_ir_read_data(pinfo, 0); ++ } else { ++ val = gk_ir_read_data(pinfo, pinfo->ir_pread + 1); ++ } ++ ++ if ((val < NEC_REPEAT_HIGH_UPBOUND) && ++ (val > NEC_REPEAT_HIGH_LOWBOUND) ) ++ return 1; ++ else ++ return 0; ++} ++ ++static int gk_ir_nec_find_subsequent(struct gk_ir_info *pinfo) ++{ ++ int i, val = 0; ++ ++ i = gk_ir_get_tick_size(pinfo) - pinfo->frame_info.frame_head_size + 1; ++ ++ while(i--) { ++ if(gk_ir_nec_pulse_subsequent_code(pinfo)) { ++ dev_dbg(&pinfo->pinput_dev->dev, "find leader code, i [%d]\n", i); ++ val = 1; ++ break; ++ } else { ++ dev_dbg(&pinfo->pinput_dev->dev, "didn't find leader code, i [%d]\n", i); ++ gk_ir_move_read_ptr(pinfo, 1); ++ } ++ } ++ ++ return val ; ++} ++ ++/** ++ * Check the waveform data is 0 bit or not. ++ */ ++static int gk_ir_nec_pulse_code_0(struct gk_ir_info *pinfo) ++{ ++ u16 val = gk_ir_read_data(pinfo, pinfo->ir_pread); ++ if ((val < NEC_DATA_LOW_UPBOUND) && ++ (val > NEC_DATA_LOW_LOWBOUND)) { ++ } else { ++ return 0; ++ } ++ ++ if ((pinfo->ir_pread + 1) >= MAX_IR_BUFFER) { ++ val = gk_ir_read_data(pinfo, 0); ++ } else { ++ val = gk_ir_read_data(pinfo, pinfo->ir_pread + 1); ++ } ++ ++ if ((val < NEC_DATA_0_HIGH_UPBOUND) && ++ (val > NEC_DATA_0_HIGH_LOWBOUND) ) ++ return 1; ++ else ++ return 0; ++} ++ ++/** ++ * Check the waveform data is 1 bit or not. ++ */ ++static int gk_ir_nec_pulse_code_1(struct gk_ir_info *pinfo) ++{ ++ u16 val = gk_ir_read_data(pinfo, pinfo->ir_pread); ++ ++ if ((val < NEC_DATA_LOW_UPBOUND) && ++ (val > NEC_DATA_LOW_LOWBOUND)) { ++ } else { ++ return 0; ++ } ++ ++ if ((pinfo->ir_pread + 1) >= MAX_IR_BUFFER) { ++ val = gk_ir_read_data(pinfo, 0); ++ } else { ++ val = gk_ir_read_data(pinfo, pinfo->ir_pread + 1); ++ } ++ ++ if ((val < NEC_DATA_1_HIGH_UPBOUND) && ++ (val > NEC_DATA_1_HIGH_LOWBOUND) ) ++ return 1; ++ else ++ return 0; ++} ++ ++static int gk_ir_nec_pulse_data_translate(struct gk_ir_info *pinfo, u8 * data) ++{ ++ int i; ++ *data = 0; ++ ++ for (i = 7; i >= 0; i--) { ++ if (gk_ir_nec_pulse_code_0(pinfo)) { ++ ++ } else if (gk_ir_nec_pulse_code_1(pinfo)) { ++ *data |= 1 << i; ++ } else { ++ dev_dbg(&pinfo->pinput_dev->dev, "%d ERROR, the waveform can't match\n", i); ++ return -1; ++ } ++ gk_ir_move_read_ptr(pinfo, 2); ++ } ++ ++ return 0; ++} ++ ++static int gk_ir_nec_pulse_decode(struct gk_ir_info *pinfo, u32 *uid) ++{ ++ u8 addr = 0, inv_addr = 0, data = 0, inv_data = 0; ++ int rval; ++ ++ /* Then follows 32 bits of data, broken down in 4 bytes of 8 bits. */ ++ ++ /* The first 8 bits is the Address. */ ++ rval = gk_ir_nec_pulse_data_translate(pinfo, &addr); ++ if (rval < 0) ++ return rval; ++ ++ /* The second 8 bits is the Address Complement. */ ++ rval = gk_ir_nec_pulse_data_translate(pinfo, &inv_addr); ++ if (rval < 0) ++ return rval; ++ ++ /* The third 8 bits is the data. */ ++ rval = gk_ir_nec_pulse_data_translate(pinfo, &data); ++ if (rval < 0) ++ return rval; ++ ++ /* The fourth 8 bits is the data Complement. */ ++ rval = gk_ir_nec_pulse_data_translate(pinfo, &inv_data); ++ if (rval < 0) ++ return rval; ++ ++ dev_dbg(&pinfo->pinput_dev->dev, "addr\tinv_addr\tdata\tinv_data\n"); ++ dev_dbg(&pinfo->pinput_dev->dev, "0x%x\t0x%x\t\t0x%x\t0x%x\n", addr, inv_addr, data, inv_data); ++ ++ *uid = (addr << 24) | (inv_addr << 16) | (data << 8) | inv_data; ++ ++ return 0; ++} ++ ++int gk_ir_nec_parse(struct gk_ir_info *pinfo, u32 *uid) ++{ ++ int rval; ++ int cur_ptr = pinfo->ir_pread; ++ ++ if ((gk_ir_nec_find_head(pinfo) || (gk_ir_nec_find_subsequent(pinfo))) ++ && gk_ir_get_tick_size(pinfo) >= pinfo->frame_info.frame_data_size ++ + pinfo->frame_info.frame_head_size) ++ { ++ dev_dbg(&pinfo->pinput_dev->dev, "go to decode statge\n"); ++ gk_ir_move_read_ptr(pinfo, pinfo->frame_info.frame_head_size);//move ptr to data ++ rval = gk_ir_nec_pulse_decode(pinfo, uid); ++ } else { ++ return -1; ++ } ++ ++ if (rval >= 0) { ++ dev_dbg(&pinfo->pinput_dev->dev, "buffer[%d]-->mornal key\n", cur_ptr); ++ return 0; ++ } ++ ++ return (-1); ++} ++ ++void gk_ir_get_nec_info(struct gk_ir_frame_info *pframe_info) ++{ ++ pframe_info->frame_head_size = 2; ++ pframe_info->frame_data_size = 64; ++ pframe_info->frame_end_size = 1; ++ pframe_info->frame_repeat_head_size = 4; ++} ++ +diff --git a/drivers/input/misc/gk_ir_v1_00.c b/drivers/input/misc/gk_ir_v1_00.c +new file mode 100644 +index 00000000..01221545 +--- /dev/null ++++ b/drivers/input/misc/gk_ir_v1_00.c +@@ -0,0 +1,1134 @@ ++/* ++ * drivers/input/misc/gk_ir_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++ ++#define BOARD_FPGA 1 ++#ifdef BOARD_FPGA ++#define IR_INPUT_CLK 24000000 // for 27MHZ Crystal ++#else ++#define IR_INPUT_CLK 24000000 // for 24MHZ Crystal ++#endif ++ ++#define IR_FREQ 38 // for NEC unit:MHz ++ ++#define IRR_MAX_DATA 0x0100 ++static u16 IrBuffer[IRR_MAX_DATA] = {0}; ++static u16 IrWritePointer = 0; ++static u16 IrDataNumber = 0; //number of the received data. ++static u16 IrSeqNumber = 0; //number of the sequence command ++static u16 IrReadPointer = 0; ++static u8 IrBufferOver = 0; ++static u8 IrBufferOverApi = 0; ++static u8 IRDataAvailable = 0; ++ ++static uint32_t lastKey = 0; ++static uint32_t lastDeviceId = 0; ++static uint32_t lastRepeatFlag = 0; ++ ++ ++/* ========================================================================= */ ++#define MAX_IR_BUFFER (512) ++#define HW_FIFO_BUFFER (48) ++#define MSC_GKIRKEYINFO 0x5 ++#define GK_IR_KEYPRESS_TIMEOUT 300 ++ ++static struct gk_key_table keymap[] = ++{ ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_POWER, 3, 0x0b}}}, //POWER ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_0, 3, 0x0c}}}, //KEY 0 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_1, 3, 0x1b}}}, //KEY 1 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_2, 3, 0x0f}}}, //KEY 2 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_3, 3, 0x03}}}, //KEY 3 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_4, 3, 0x19}}}, //KEY 4 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_5, 3, 0x11}}}, //KEY 5 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_6, 3, 0x01}}}, //KEY 6 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_7, 3, 0x09}}}, //KEY 7 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_8, 3, 0x1d}}}, //KEY 8 ++ {GKINPUT_IR_KEY, {.ir_key = {KEY_9, 3, 0x0d}}}, //KEY 9 ++ ++ {GKINPUT_END}, ++}; ++ ++/* ========================================================================= */ ++struct gk_ir_frame_info ++{ ++ u32 frame_head_size; ++ u32 frame_data_size; ++ u32 frame_end_size; ++ u32 frame_repeat_head_size; ++}; ++ ++struct gk_ir_info ++{ ++ struct input_dev *pinput_dev; ++ unsigned char __iomem *regbase; ++ ++ u32 id; ++ ++ unsigned int irq; ++ ++ int (*ir_parse)(struct gk_ir_info *pirinfo, u32 *uid); ++ int ir_pread; ++ int ir_pwrite; ++ u16 tick_buf[MAX_IR_BUFFER]; ++ ++ struct gk_ir_frame_info frame_info; ++ u32 frame_data_to_received; ++ ++ u32 last_ir_uid; ++ u32 last_ir_flag; ++ spinlock_t keylock; ++ ++ struct gk_key_table *pkeymap; ++ struct gk_ir_controller *pcontroller_info; ++}; ++ ++typedef enum ++{ ++ GD_IR_RECEIVER = 1, //!< Receiver function. ++ GD_IR_TRANSMITTER, //!< Transmitter function. ++} GD_IR_TYPE_E; ++ ++/* ========================================================================= */ ++static void gk_ir_disable(struct gk_ir_info *pirinfo) ++{ ++ disable_irq(pirinfo->irq); ++} ++ ++static void gk_ir_enable(struct gk_ir_info *pirinfo) ++{ ++ u32 edges; ++ ++ pirinfo->frame_data_to_received = pirinfo->frame_info.frame_head_size ++ + pirinfo->frame_info.frame_data_size; ++ ++ BUG_ON(pirinfo->frame_data_to_received > MAX_IR_BUFFER); ++ ++ if (pirinfo->frame_data_to_received > HW_FIFO_BUFFER) ++ { ++ edges = HW_FIFO_BUFFER; ++ pirinfo->frame_data_to_received -= HW_FIFO_BUFFER; ++ } ++ else ++ { ++ edges = pirinfo->frame_data_to_received; ++ pirinfo->frame_data_to_received = 0; ++ } ++ ++ enable_irq(pirinfo->irq); ++} ++ ++static int gk_ir_get_tick_size(struct gk_ir_info *pirinfo) ++{ ++ int size = 0; ++ ++ if (pirinfo->ir_pread > pirinfo->ir_pwrite) ++ size = MAX_IR_BUFFER - pirinfo->ir_pread + pirinfo->ir_pwrite; ++ else ++ size = pirinfo->ir_pwrite - pirinfo->ir_pread; ++ ++ return size; ++} ++ ++void gk_ir_inc_read_ptr(struct gk_ir_info *pirinfo) ++{ ++ BUG_ON(pirinfo->ir_pread == pirinfo->ir_pwrite); ++ ++ pirinfo->ir_pread++; ++ if (pirinfo->ir_pread >= MAX_IR_BUFFER) ++ pirinfo->ir_pread = 0; ++} ++ ++void gk_ir_move_read_ptr(struct gk_ir_info *pirinfo, int offset) ++{ ++ for (; offset > 0; offset--) ++ { ++ gk_ir_inc_read_ptr(pirinfo); ++ } ++} ++ ++static u16 gk_ir_read_data( struct gk_ir_info *pirinfo, int pointer) ++{ ++ BUG_ON(pointer < 0); ++ BUG_ON(pointer >= MAX_IR_BUFFER); ++ BUG_ON(pointer == pirinfo->ir_pwrite); ++ ++ return pirinfo->tick_buf[pointer]; ++} ++ ++static inline void gk_ir_write_data(struct gk_ir_info *pirinfo, u16 val) ++{ ++ BUG_ON(pirinfo->ir_pwrite < 0); ++ BUG_ON(pirinfo->ir_pwrite >= MAX_IR_BUFFER); ++ ++ pirinfo->tick_buf[pirinfo->ir_pwrite] = val; ++ ++ pirinfo->ir_pwrite++; ++ ++ if (pirinfo->ir_pwrite >= MAX_IR_BUFFER) ++ pirinfo->ir_pwrite = 0; ++} ++ ++#if 0 ++static int gk_input_report_ir(struct gk_ir_info *pirinfo, u32 uid) ++{ ++ ++ if (!pirinfo->pkeymap) ++ return -1; ++ ++ if ((pirinfo->last_ir_uid == uid) && (pirinfo->last_ir_flag)) ++ { ++ pirinfo->last_ir_flag--; ++ return 0; ++ } ++ pirinfo->last_ir_uid = uid; ++ ++ //input_report_key(pirinfo->pinput_dev, pirinfo->pkeymap[i].ir_key.key_code, 1); ++ //input_report_key(pirinfo->pinput_dev, pirinfo->pkeymap[i].ir_key.key_code, 0); ++ //printk( "IR_KEY [%d]\n", pirinfo->pkeymap[i].ir_key.key_code); ++ ++ return 0; ++} ++#endif ++ ++ ++#include "gk_ir_nec.c" ++ ++void gk_ir_set_protocol(struct gk_ir_info *pirinfo, ++ enum gk_ir_protocol protocol_id) ++{ ++ memset(pirinfo->tick_buf, 0x0, sizeof(pirinfo->tick_buf)); ++ pirinfo->ir_pread = 0; ++ pirinfo->ir_pwrite = 0; ++ ++ switch (protocol_id) ++ { ++ case GK_IR_PROTOCOL_NEC: ++ default: ++ printk("Protocol NEC[%d]\n", protocol_id); ++ pirinfo->ir_parse = gk_ir_nec_parse; ++ gk_ir_get_nec_info(&pirinfo->frame_info); ++ break; ++ } ++} ++ ++static void gk_ir_init(struct gk_ir_info *pirinfo) ++{ ++ u16 prescaler; ++ int i; ++ ++ prescaler = (u16)((IR_INPUT_CLK/(IR_FREQ * 1000)) - 1); ++ ++ gk_ir_writel( REG_PMU_IRQ_EN, 0x0); ++ gk_ir_writel( REG_PMU_IRQ_CLR_RTC, IRQ_EN_RTC); ++ gk_ir_writel( REG_PMU_IRQ_CLR_IRR, IRQ_EN_IRR); ++ gk_ir_writel( REG_PMU_IRQ_CLR_FPC, IRQ_EN_FPC); ++ gk_ir_writel( REG_PMU_IRQ_CLR_GPIO, IRQ_EN_GPIO); ++ gk_ir_writel( REG_PMU_IRQ_CLR_CEC, IRQ_EN_CEC); ++ gk_ir_writel( REG_PMU_IRQ_CLR_ADC, IRQ_EN_ADC); ++ gk_ir_writel( REG_PMU_IRQ_CLR_IRT, IRQ_EN_IRT); ++ ++ gk_ir_writel( REG_PMU_IRQ_EN, IRQ_EN_IRT | IRQ_EN_RTC | IRQ_EN_IRR); ++ ++ gk_ir_disable(pirinfo); ++ ++ gk_ir_writel( REG_IRR_PROG, 0x08); ++ gk_ir_writel( REG_IRR_PRESCALER_H, (u8)(((prescaler) >> 8) & 0xff)); ++ gk_ir_writel( REG_IRR_PRESCALER_L, (u8)(prescaler & 0xff)); ++ ++ gk_ir_writel( REG_IRR_PROG, 0x02); ++ gk_ir_writel( REG_IRR_IRQMASK_H, 0xFF); ++ gk_ir_writel( REG_IRR_IRQMASK_L, 0xFF); ++ ++ IrDataNumber = 0; ++ IrSeqNumber = 0; ++ IrReadPointer = 0; ++ IrWritePointer = 0; ++ IrBufferOver = 0; ++ IRDataAvailable = 0; ++ memset(&IrBuffer, 0, sizeof(IrBuffer)); ++ ++ if (pirinfo->pcontroller_info->protocol >= GK_IR_PROTOCOL_END) ++ pirinfo->pcontroller_info->protocol = GK_IR_PROTOCOL_NEC; ++ gk_ir_set_protocol(pirinfo, pirinfo->pcontroller_info->protocol); ++ ++ gk_ir_enable(pirinfo); ++ ++ for(i=0; ipinput_dev->evbit); ++ set_bit(pirinfo->pkeymap[i].ir_key.raw_id, ++ pirinfo->pinput_dev->keybit); ++ } ++} ++ ++typedef union /* IRR_IRR_Read */ ++{ ++ u32 all; ++ struct ++ { ++ u32 irr_pulse27 : 6; ++ u32 edge : 1; ++ u32 valid : 1; ++ u32 : 24; ++ } bitc; ++} GH_IRR_IRR_READ_S; ++ ++static u16 ir_count2time(u32 count) ++{ ++ return (u16)((10000 * count) /(IR_FREQ * 10)); ++} ++ ++ ++/*! ++******************************************************************************* ++** ++** \brief Checks the status of an instance. ++** ++** This function returns the status the of the receiver or transmitter. ++** If receiving is complete, it returns the number of received data. ++** If transmitting is complete, it returns the number of transmitted ++** data. ++** ++** \param handle Handle of receiver or transmitter to check. ++** \param pNum Number of time data stored in the IR buffer. ++** ++** \return Possible return codes: ++** - #GD_OK ++** - #GD_ERR_IR_NO_SEQUENCE Receiving is not completed yet. ++** - #GD_ERR_OUT_OF_MEMORY Receiver buffer overflow ++** - #GD_ERR_IR_TRANSMIT_INPROCESS Transmitting is not yet complete. ++** - #GD_ERR_INVALID_HANDLE ++** ++******************************************************************************/ ++ ++int GD_IR_Status(GD_IR_TYPE_E handle, u16* pNum) ++{ ++ u32 ReturnValue; ++ ++ if(handle == GD_IR_RECEIVER ) ++ { ++ ReturnValue = -1; ++ if (IrDataNumber) ++ ReturnValue = 0; ++ if (IrBufferOverApi) ++ { ++ IrBufferOverApi = 0; ++ ReturnValue = -1; ++ } ++ *pNum = IrSeqNumber; ++ return ReturnValue; ++ } ++ else ++ return -1; ++} ++ ++ ++/*! ++******************************************************************************* ++** ++** \brief Reads data from the IR receice buffer. ++** ++** \param handle Handle of IR receiver. ++** \param pData Pointer to data array. ++** \param num Number of data to be read. ++** ++** \return Possible return codes: ++** - #GD_OK ++** - #GD_ERR_INVALID_HANDLE ++** ++******************************************************************************/ ++int GD_IR_Receive(GD_IR_TYPE_E handle, u16 *pData, u16 num) ++{ ++ u16 TimeData; ++ u16 ix; ++ ++ if (handle != GD_IR_RECEIVER) return -1; ++ ++ for (ix=0; ix= IRR_MAX_DATA) ++ IrReadPointer = 0; ++ } ++ ++ return 0; ++} ++ ++ ++/*! ++******************************************************************************* ++ ++This function decodes the Infrared data of NEC mode. ++ ++\note The device ID is a 16-bit custom code (Custom Code, Custom Code?. ++ Where the upper 8 bits refer to the Custom Code and the lower 8 bits ++ refer to the Custom Code'. ++ ++\param handle Handle of the receiver device in the IR driver. ++\param pKeyValue Pointer to IR key value. ++\param pRepeatFlag Pointer to repeat flag of remote controller. ++\param pDeviceID Pointer to device ID of the remote controller. ++ ++\return Return values from GD_IR_Status, most important are: ++ \c GD_OK ++ \c GD_ERR_IR_NO_SEQUENCE = no signal received ++ own return values: ++ \c GM_ERR_IR_INVAL_SEQ = no valid sequence detected ++ ++******************************************************************************/ ++int GM_IRR_NEC_Mode(u16 *pDeviceID, u8 *pKeyValue, u8 *pRepeatFlag) ++{ ++ u16 Data = 0,nData = 0,TmpData = 0; ++ u8 CtlData=0; ++ u8 NCtlData=0; ++ u8 IRData=0; ++ u8 NIRData=0; ++ u16 ix, iy=0; ++ u8 RepeatFlg=0 ; ++ u8 IR_State=0; /* must init this value as 0 !*/ ++ int err; ++ static u8 firstRepeat = 1; ++ ++ /* preset return values to 0 */ ++ *pKeyValue = 0; ++ *pRepeatFlag = 0; ++ *pDeviceID = 0; ++ ++ err = GD_IR_Status(GD_IR_RECEIVER, &nData); ++ if(err) ++ return(err); ++ else ++ { ++ for (ix=0; ix<=nData; ix++) ++ { ++ GD_IR_Receive(GD_IR_RECEIVER,&Data,1); ++ //if ( Data & GD_IR_EDGE_FLAG) ++ { ++ TmpData = Data; ++ if ( IR_State == 0 ) ++ { ++ if ( ( TmpData < 5500 ) && ( TmpData > 4500 ) ) ++ { ++ RepeatFlg=0; ++ IR_State= 1; ++ CtlData=0; ++ NCtlData=0; ++ IRData=0; ++ NIRData=0; ++ iy = 0; ++ } ++ else if ( ( TmpData < 3000 ) && ( TmpData > 2500 ) ) ++ { ++ RepeatFlg=1; ++ IR_State= 20; ++ CtlData=0; ++ NCtlData=0; ++ IRData=0; ++ NIRData=0; ++ iy = 0; ++ } ++ else ++ { ++ IR_State = 20; ++ } ++ } ++ else if ( IR_State == 1 ) ++ { ++ if ( ( TmpData < 1200 ) && ( TmpData > 850 ) ) ++ { ++ CtlData = CtlData; ++ iy ++; ++ if ( iy == 8 ) ++ { ++ IR_State = 2; ++ iy = 0; ++ } ++ } ++ else if ( ( TmpData < 2300 ) && ( TmpData > 2000 ) ) ++ { ++ CtlData = CtlData + (1< 850 ) ) ++ { ++ NCtlData = NCtlData ; ++ iy ++; ++ if ( iy == 8 ) ++ { ++ IR_State = 3; ++ iy = 0; ++ } ++ } ++ else if ( ( TmpData < 2300 ) && ( TmpData > 2000 ) ) ++ { ++ NCtlData = NCtlData + (1< 850 ) ) ++ { ++ IRData = IRData ; ++ iy ++; ++ if ( iy == 8 ) ++ { ++ IR_State = 4; ++ iy = 0; ++ } ++ } ++ else if ( ( TmpData < 2300 ) && ( TmpData > 2000 ) ) ++ { ++ IRData = IRData + (1< 850 ) ) ++ { ++ NIRData = NIRData ; ++ iy ++; ++ if ( iy == 8 ) ++ { ++ IR_State = 5; ++ iy = 0; ++ } ++ } ++ else if ( ( TmpData < 2300 ) && ( TmpData > 2000 ) ) ++ { ++ NIRData = NIRData + (1<MAX_HI_TIME)) ++ return 1; // if 'illegal' timing values ++ if (OneBitsSeq) ++ { ++ // if 'receiveing '1'-bit sequence ++ RC5_Dataword = RC5_Dataword << 1; // shift up previous data bits ++ RC5_Dataword |= 0x0001; // add '1'-bit ++ BitCount++; ++ } ++ if (IrTimeVal>=LNG_HI_TIME) ++ OneBitsSeq = 0; // if transition into 'receiving '0'-bits sequence ++ } ++ else ++ { ++ // else expecting a 'NegativeSignalEdge' ++ ExpectPosEdge = 1; ++ if (!nData) ++ { ++ // if expecting final 'stop' time-duration ++ if (IrTimeValMAX_LO_TIME)) ++ return 3; // if 'illegal' timing values ++ if (!OneBitsSeq) ++ { ++ // if 'receiveing '0'-bit sequence ++ // shift up previous data bits, insert '0'-bit ++ RC5_Dataword = RC5_Dataword << 1; ++ BitCount++; ++ } ++ if (IrTimeVal>=LNG_LO_TIME) ++ OneBitsSeq = 1; // if transition into 'receiving '1'-bits sequence ++ } ++ } ++// GM_PrStr("\nResultBits:"); GM_PrHex(BitCount,2); ++ if (BitCount!=14) return 4; ++ *pIrData = RC5_Dataword; ++ return 0; ++} ++ ++ ++/*! ++******************************************************************************* ++ ++This function decodes the Infrared data of RC-5 mode. ++ ++\note The device ID is a 16-bit custom code (Custom Code, Custom Code). ++ Where the upper 8 bits refer to the Custom Code and the lower 8 bits ++ refer to the Custom Code'. ++ ++\param handle Handle of the receiver device in the IR driver. ++\param pKeyValue Pointer to IR key value. ++\param pRepeatFlag Pointer to repeat flag of remote controller. ++\param pDeviceID Pointer to device ID of the remote controller. ++ ++\return Return values from GD_IR_Status, most important are: ++ \c GD_OK ++ \c GD_ERR_IR_NO_SEQUENCE = no signal received ++ own return values: ++ \c GM_ERR_IR_INVAL_SEQ = no valid sequence detected ++ ++******************************************************************************/ ++int GM_IRR_RC5_Mode(u16 *pDeviceID, u8 *pKeyValue, u8 *pRepeatFlag) ++{ ++ static u8 LastTogInfo=0; ++ u16 nNewIrcTimingData; ++ u16 DecodedData; ++ int err, ix, Count, KVal, KRep, KDev; ++ ++ //-- preset return values -- ++ KVal = 0; ++ KRep = 0; ++ KDev = 0; ++ ++ err = GD_IR_Status(GD_IR_RECEIVER, &nNewIrcTimingData); ++ if(err) ++ { ++ return(err); ++ } ++ ++ nNewIrcTimingData += 1; // plus 'Stop' Timing value ++ Count = nNewIrcTimingData; ++ do ++ { ++ // transfer IR-Timing data (to local RxBuffer) ++ ix = Count; // (multiple chuncs 'invalid data' if necessary) ++ if (ix>MAX_IR_DATA) ++ ix = MAX_IR_DATA; ++ Count -= ix; ++ GD_IR_Receive(GD_IR_RECEIVER, IRC_ActIrData, ix); // 'empty' IR-Data ++ } while (Count); ++ err = -1; // def. return code ++ ++ if (nNewIrcTimingData"); GM_PrHex(DecodedData,4); ++ KVal = DecodedData & 0x3F; ++ if (!(DecodedData&0x1000)) KVal |= 0x40; ++ KDev = (DecodedData>>6) & 0x1F; ++ ix = (DecodedData>>11) & 1; // get Toggle Info ++ if (ix==(int)LastTogInfo) KRep = 1; // if not 'Toggling' => Set Repeat-Flag ++ LastTogInfo = ix; // save for next time ++ err = 0; ++ } ++ } ++// else GM_PrStr("\n{CanNotBeRc5Data}"); ++ *pKeyValue = KVal ; ++ *pRepeatFlag = KRep; ++ *pDeviceID = KDev; ++ return err; ++} ++ ++ ++/* ---------------------------------------------------------------------- */ ++static void gk_ir_event_Notifier(struct gk_ir_info *pirinfo) ++{ ++ uint32_t deviceId = 0; ++ uint32_t scancode = 0; ++ uint32_t repeatFlag = 0; ++ uint32_t keyInfo = 0; ++ unsigned long flags; ++ ++ ++ spin_lock_irqsave(&pirinfo->keylock, flags); ++ /* Get IR key */ ++ if(GM_IRR_NEC_Mode((uint16_t*)&deviceId, (uint8_t*)&scancode, (uint8_t*)&repeatFlag) == 0) ++ { ++ ++ if(!deviceId) ++ { ++ deviceId = lastDeviceId; ++ } ++ /*report if deviceId or keytype changed*/ ++ if(deviceId != lastDeviceId || repeatFlag != lastRepeatFlag) ++ { ++ lastDeviceId = deviceId; ++ lastRepeatFlag = repeatFlag; ++ ++ keyInfo = (lastDeviceId<<16) | lastRepeatFlag; ++ //printk("keyInfo: %x\n", keyInfo); ++ ++ //input_event(pirinfo->pinput_dev, EV_MSC, MSC_GKIRKEYINFO, keyInfo); ++ //input_sync(pirinfo->pinput_dev); ++ } ++ ++ //currentKeydownJiffies = jiffies; ++ ++ if(repeatFlag == 0) ++ { ++ lastKey = scancode; ++ } ++ /* key repeat message must be in a certain time interval */ ++ //else if (currentKeydownJiffies - lastKeyJiffies > msecs_to_jiffies(GK_IR_KEYPRESS_TIMEOUT)) { ++ // lastKeyJiffies = currentKeydownJiffies; ++ // printk("No sequence is received\n"); ++ // goto out; ++ //} ++ else ++ { ++ scancode = lastKey; ++ } ++ //lastKeyJiffies = currentKeydownJiffies; ++ ++ //printk("report key: 0x%02x\n", scancode); ++ /*key event is triggered by key pressed*/ ++ input_report_key(pirinfo->pinput_dev, scancode, 1); ++ input_report_key(pirinfo->pinput_dev, scancode, 0); ++ input_sync(pirinfo->pinput_dev); ++#if 0 ++ /*can't get status of key released, just to released key without report */ ++ if(!!test_bit(scancode, pirinfo->pinput_dev->key) == 1) ++ { ++ clear_bit(scancode, pirinfo->pinput_dev->key); ++ } ++#endif ++ } ++ else ++ { ++ //printk("GM_IRR_NEC_Mode: error\n"); ++ } ++ ++ spin_unlock_irqrestore(&pirinfo->keylock, flags); ++ return; ++} ++ ++ ++static irqreturn_t gk_ir_irq(int irq, void *devid) ++{ ++ struct gk_ir_info *pirinfo; ++ //int key_val; ++ //u32 uid; ++ //u32 edges; ++ ++ u32 irdata = 0,irtdata = 0,irq_flag = 0; ++ u16 tmp_value = 0; ++ GH_IRR_IRR_READ_S m_irr_read; ++ ++ pirinfo = (struct gk_ir_info *)devid; ++ ++ BUG_ON(pirinfo->ir_pread < 0); ++ BUG_ON(pirinfo->ir_pread >= MAX_IR_BUFFER); ++ ++ irq_flag = gk_ir_readl(REG_PMU_IRQ_STATUS); ++ //printk("irq status = 0x%x \n", irq_flag); ++ ++ if(irq_flag & IRQ_EN_IRR) // irr irq ++ { ++ irdata = gk_ir_readl(REG_IRR_IRR_READ); ++ irtdata = gk_ir_readl(REG_IRR_IRT_READ); ++ ++ m_irr_read.all = irdata; ++ if (m_irr_read.bitc.valid == 1) ++ { ++ tmp_value = ((irtdata & 0x00000003) | ((irdata << 2) & 0x000000fc)); ++ ++ ++ if (tmp_value < 0xfC) ++ { ++ gk_ir_writel( REG_IRR_PROG, 0x03); ++ tmp_value = ir_count2time(tmp_value); ++ ++ //printk("ir value = 0x%x\n", tmp_value); ++ ++ IrBuffer[IrWritePointer++] = tmp_value; ++ IrDataNumber++; ++ IrSeqNumber++; ++ IRDataAvailable = 1; ++ } ++ else if (tmp_value >= 0xfC) ++ { ++ gk_ir_writel( REG_IRR_PROG,0x02); ++ //printk("ir value = 0x%x\n", tmp_value); ++ gk_ir_event_Notifier(pirinfo); ++ IrDataNumber = 0; ++ IrSeqNumber = 0; ++ IrReadPointer = 0; ++ IrWritePointer = 0; ++ memset(&IrBuffer, 0, sizeof(IrBuffer)); ++ } ++ if (IrDataNumber>=IRR_MAX_DATA) ++ { ++ IrBufferOverApi = 1; ++ } ++ if (IrWritePointer >= IRR_MAX_DATA) ++ { ++ IrWritePointer = 0; ++ } ++ } ++ gk_ir_writel( REG_PMU_IRQ_CLR_IRR, IRQ_EN_IRR); // clear irr irq ++ ++ } ++ ++ if(irq_flag & IRQ_EN_IRT) // irt irq ++ { ++ gk_ir_writel( REG_PMU_SYS_REG_CFG1, 1); ++ gk_ir_writel( REG_PMU_IRQ_CLR_IRT, IRQ_EN_IRT); // clear irt irq ++ } ++ ++ if(irq_flag & IRQ_EN_RTC) // rtc irq ++ { ++ *(volatile u32 *)(0xf0080000 + (0x8*4)) = 0x01; // clear ir irq ++ *(volatile u32 *)(0xf0080000 + (0x8*4)) = 0x00; // clear ir irq ++ gk_ir_writel( REG_PMU_IRQ_CLR_RTC, IRQ_EN_RTC); // clear rtc irq ++ } ++ if(irq_flag & IRQ_EN_FPC) // fpc irq ++ { ++ gk_ir_writel( REG_PMU_IRQ_CLR_FPC, IRQ_EN_FPC); // clear fpc irq ++ } ++ if(irq_flag & IRQ_EN_GPIO) // gpio irq ++ { ++ u32 regval = 0; ++ regval = gk_ir_readl(PMU_GPIO_RIS); ++ gk_ir_writel( PMU_GPIO_IC, regval); ++ gk_ir_writel( REG_PMU_IRQ_CLR_GPIO, IRQ_EN_GPIO); // clear gpio irq ++ } ++ if(irq_flag & IRQ_EN_CEC) // cec irq ++ { ++ gk_ir_writel( REG_PMU_IRQ_CLR_CEC, IRQ_EN_CEC); // clear cec irq ++ } ++ if(irq_flag & IRQ_EN_ADC) // adc irq ++ { ++ gk_ir_writel( REG_PMU_IRQ_CLR_ADC, IRQ_EN_ADC); // clear adc irq ++ } ++ return IRQ_HANDLED; ++} ++ ++static int __devinit gk_ir_probe(struct platform_device *pdev) ++{ ++ int retval; ++ ++ struct gk_ir_info *pirinfo; ++ ++ //struct proc_dir_entry *input_file; ++ struct input_dev *pinput_dev; ++ ++ pinput_dev = input_allocate_device(); ++ if (!pinput_dev) ++ { ++ dev_err(&pdev->dev, "input_allocate_device fail!\n"); ++ retval = -ENOMEM; ++ goto ir_errorCode_na; ++ } ++ pinput_dev->name = "GKInput"; ++ pinput_dev->phys = "gk/input0"; ++ pinput_dev->id.bustype = BUS_HOST; ++ ++ retval = input_register_device(pinput_dev); ++ if (retval) ++ { ++ dev_err(&pdev->dev, "Register input_dev failed!\n"); ++ goto gk_input_probe_free_input_dev; ++ } ++ //pbinfo->pdev = pdev; ++ //pbinfo->pinput_dev = pinput_dev; ++ ++ pirinfo = kzalloc(sizeof(struct gk_ir_info), GFP_KERNEL); ++ if (!pirinfo) ++ { ++ dev_err(&pdev->dev, "Failed to allocate pirinfo!\n"); ++ retval = -ENOMEM; ++ goto gk_input_probe_unregister_input_dev; ++ } ++ ++ pirinfo->pcontroller_info = (struct gk_ir_controller *)pdev->dev.platform_data; ++ if ((pirinfo->pcontroller_info == NULL) ) ++ { ++ dev_err(&pdev->dev, "Platform data is NULL!\n"); ++ retval = -ENXIO; ++ goto ir_errorCode_pinfo; ++ } ++ ++ pirinfo->regbase = (unsigned char __iomem *)MCU_IRR_BASE; ++ pirinfo->id = pdev->id; ++ pirinfo->irq = IR_IRQ; ++ ++ pirinfo->last_ir_uid = 0; ++ pirinfo->last_ir_flag = 0; ++ pirinfo->pinput_dev = pinput_dev; ++ //pirinfo->pinput_dev = pboard_info->pinput_dev; ++ pirinfo->pkeymap = keymap; ++ ++ platform_set_drvdata(pdev, pirinfo); ++ ++ gk_ir_init(pirinfo); ++ ++ retval = request_irq(pirinfo->irq, gk_ir_irq, IRQF_TRIGGER_LOW, ++ dev_name(&pdev->dev), pirinfo); ++ if (retval) ++ { ++ dev_err(&pdev->dev, "Request IRQ failed!\n"); ++ goto ir_errorCode_free_platform; ++ } ++ printk("ir request irq: %d \n", pirinfo->irq); ++ ++ printk("IR Host Controller probed!\n"); ++ ++ goto ir_errorCode_na; ++ ++ir_errorCode_free_platform: ++ platform_set_drvdata(pdev, NULL); ++ ++ir_errorCode_pinfo: ++ kfree(pirinfo); ++ ++gk_input_probe_unregister_input_dev: ++ input_unregister_device(pinput_dev); ++ ++ return retval; ++ ++gk_input_probe_free_input_dev: ++ input_free_device(pinput_dev); ++ //pbinfo->pdev = NULL; ++ //pbinfo->pinput_dev = NULL; ++ ++ir_errorCode_na: ++ return retval; ++} ++ ++static int __devexit gk_ir_remove(struct platform_device *pdev) ++{ ++ struct gk_ir_info *pirinfo; ++ int retval = 0; ++ ++ pirinfo = platform_get_drvdata(pdev); ++ ++ if (pirinfo) ++ { ++ free_irq(pirinfo->irq, pirinfo); ++ input_unregister_device(pirinfo->pinput_dev); ++ platform_set_drvdata(pdev, NULL); ++ kfree(pirinfo); ++ } ++ ++ dev_notice(&pdev->dev, ++ "Remove GK IR Controller.\n"); ++ ++ return retval; ++} ++ ++static struct platform_driver gk_ir_driver = ++{ ++ .probe = gk_ir_probe, ++ .remove = __devexit_p(gk_ir_remove), ++ .driver = ++ { ++ .name = "ir", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init gk_input_init(void) ++{ ++ int retval = 0; ++ ++ retval = platform_driver_register(&gk_ir_driver); ++ if (retval) ++ printk(KERN_ERR "Register gk_input_driver failed %d!\n", ++ retval); ++ ++ return retval; ++} ++ ++static void __exit gk_input_exit(void) ++{ ++ platform_driver_unregister(&gk_ir_driver); ++} ++ ++module_init(gk_input_init); ++module_exit(gk_input_exit); ++ ++MODULE_DESCRIPTION("GOKE Input Driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index c7795096..81e4a315 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -4,6 +4,21 @@ + + menu "Misc devices" + ++config ADC_GOKE ++ tristate "goke ipc ADC support" ++ depends on GK_ADC ++ help ++ This driver exports functions to choose ADC channel and read ADC ++ data. ++ ++config PWM_GOKE ++ tristate "goke ipc PWM support" ++ depends on GK_PWM ++ help ++ This driver exports functions to enable/disble/config/free Pulse ++ Width Modulation in the GOKE IPC Chip. ++ It is used by led and backlight driver to control the intensity. ++ + config SENSORS_LIS3LV02D + tristate + depends on INPUT +diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile +index 3e1d8010..6208f079 100644 +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -49,3 +49,9 @@ obj-y += carma/ + obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o + obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ + obj-$(CONFIG_MAX8997_MUIC) += max8997-muic.o ++ifdef CONFIG_ADC_GOKE ++obj-$(CONFIG_GK_ADC_V1_00) += gk_adc_v1_00.o ++endif ++ifdef CONFIG_PWM_GOKE ++obj-$(CONFIG_GK_PWM_V1_00) += gk_pwm_v1_00.o ++endif +diff --git a/drivers/misc/gk_adc_v1_00.c b/drivers/misc/gk_adc_v1_00.c +new file mode 100644 +index 00000000..12295ae6 +--- /dev/null ++++ b/drivers/misc/gk_adc_v1_00.c +@@ -0,0 +1,354 @@ ++/* ++ * drivers/misc/gk_adc_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define DEVICE_NAME "adc" ++ ++/*----------------------------------------------------------------------------*/ ++/* registers */ ++/*----------------------------------------------------------------------------*/ ++#define ADC_VA_BASE (GK_VA_ADC2) ++#define ADC_REG(x) (ADC_VA_BASE + (x)) ++ ++#define ADC_ANALOG_VA_BASE (GK_VA_ADC) ++#define ADC_ANALOG_REG(x) (ADC_ANALOG_VA_BASE + (x)) ++ ++#define REG_ADC_AUX_ATOP ADC_ANALOG_REG(0x00) /* read/write */ ++#define REG_ADC_GPIO ADC_ANALOG_REG(0x04) /* read/write */ ++#define REG_ADC_CONTROL ADC_REG(0x000) /* read/write */ ++#define REG_ADC_READDATA ADC_REG(0x004) /* read */ ++#define REG_ADC_ENABLE ADC_REG(0x018) /* read/write */ ++#define REG_ADC_INTCONTROL ADC_REG(0x044) /* read/write */ ++ ++#define GK_ADC_IOC_MAGIC 'A' ++#define IOC_ADC_SET_CHANNEL _IOW(GK_ADC_IOC_MAGIC, 0, unsigned int) ++#define IOC_ADC_GET_CHANNEL _IOR(GK_ADC_IOC_MAGIC, 1, unsigned int) ++#define IOC_ADC_GET_DATA _IOR(GK_ADC_IOC_MAGIC, 2, unsigned int) ++/*---------------------------------------------------------------------------*/ ++/* types, enums and structures */ ++/*---------------------------------------------------------------------------*/ ++/*! ++******************************************************************************* ++** ++** \brief ADC channel number. ++** ++** \sa ADC_OPEN_PARAMS_S ++** ++******************************************************************************/ ++typedef enum ++{ ++ ADC_CHANNEL_ONE = 0, //!< ADC channel 1. ++ ADC_CHANNEL_TWO, //!< ADC channel 2. ++ ADC_CHANNEL_COUNT, //!< ADC channel count ++ ADC_CHANNEL_NONE = -1, ++}ADC_CHANNEL_E; ++ ++/*----------------------------------------------------------------------------*/ ++/* bit group structures */ ++/*----------------------------------------------------------------------------*/ ++typedef union { /* ADC_AUX_ATOP */ ++ uint32_t all; ++ struct { ++ uint32_t sar_maxsel : 4; ++ uint32_t sar_maxnsel : 3; ++ uint32_t sar_pd : 1; ++ uint32_t sar_oneshot : 1; ++ uint32_t sar_freerun : 1; ++ uint32_t sar_refnsel : 2; ++ uint32_t sar_refsel : 3; ++ uint32_t sar_pd_tsi : 1; ++ uint32_t : 16; ++ } bitc; ++} ADC_AUX_ATOP_S; ++ ++typedef union { /* ADC_GPIO */ ++ uint32_t all; ++ struct { ++ uint32_t sar_test : 4; ++ uint32_t sar_key_pge : 4; ++ uint32_t sar_key_aie : 4; ++ uint32_t oen_sar_key : 4; ++ uint32_t : 16; ++ } bitc; ++} ADC_GPIO_S; ++ ++typedef union { /* ADC_Control */ ++ uint32_t all; ++ struct { ++ uint32_t status : 1; ++ uint32_t start : 1; ++ uint32_t : 1; ++ uint32_t channel : 3; ++ uint32_t : 26; ++ } bitc; ++} ADC_CONTROL_S; ++ ++ ++/*---------------------------------------------------------------------------*/ ++/* ADC state structure */ ++/*---------------------------------------------------------------------------*/ ++typedef struct ++{ ++ ADC_CHANNEL_E channel; ++ uint32_t data; ++} ADC_STATE_MACHINE_S; ++ ++static struct mutex adc_mutex; ++static uint32_t in_use; ++static ADC_CHANNEL_E cur_ch; ++ ++void ADC_set_Control(uint32_t data) ++{ ++ gk_adc_writel(REG_ADC_CONTROL, data); ++} ++ ++uint32_t ADC_get_Control_status(void) ++{ ++ ADC_CONTROL_S d; ++ d.all = gk_adc_readl(REG_ADC_CONTROL); ++ return d.bitc.status; ++} ++ ++void ADC_set_Control_status(uint8_t data) ++{ ++ ADC_CONTROL_S d; ++ d.all = gk_adc_readl(REG_ADC_CONTROL); ++ d.bitc.status = data; ++ gk_adc_writel(REG_ADC_CONTROL, d.all); ++} ++ ++void ADC_set_Control_start(uint8_t data) ++{ ++ ADC_CONTROL_S d; ++ d.all = gk_adc_readl(REG_ADC_CONTROL); ++ d.bitc.start = data; ++ gk_adc_writel(REG_ADC_CONTROL, d.all); ++} ++ ++void ADC_set_Control_channel(uint8_t data) ++{ ++ ADC_CONTROL_S d; ++ d.all = gk_adc_readl(REG_ADC_CONTROL); ++ d.bitc.channel = data; ++ gk_adc_writel(REG_ADC_CONTROL, d.all); ++} ++ ++static uint32_t ADC_get_ReadData(uint8_t index) ++{ ++ uint32_t value; ++ value = gk_adc_readl(REG_ADC_READDATA + (index * 0x4)); ++ return value; ++} ++ ++static void ADC_set_Enable(uint32_t data) ++{ ++ gk_adc_writel(REG_ADC_ENABLE, data); ++} ++ ++static void ADC_set_AUX_ATOP(uint32_t data) ++{ ++ gk_adc_writel(REG_ADC_AUX_ATOP, data); ++} ++ ++static void ADC_set_AUX_ATOP_sar_maxsel(uint8_t data) ++{ ++ ADC_AUX_ATOP_S d; ++ d.all = gk_adc_readl(REG_ADC_AUX_ATOP); ++ d.bitc.sar_maxsel = data; ++ gk_adc_writel(REG_ADC_AUX_ATOP, d.all); ++} ++ ++static void ADC_select_channel(ADC_CHANNEL_E channel) ++{ ++ if(channel == ADC_CHANNEL_ONE){ ++ ADC_set_AUX_ATOP_sar_maxsel(0x05); ++ ADC_set_Control_channel(0x01); ++ }else if(channel == ADC_CHANNEL_TWO){ ++ ADC_set_AUX_ATOP_sar_maxsel(0x06); ++ ADC_set_Control_channel(0x02); ++ }else{ ++ printk(KERN_ERR "Invalid channel number.\n"); ++ } ++} ++ ++static int gk_adc_open(struct inode *inode, struct file *filp) ++{ ++ mutex_lock(&adc_mutex); ++ if(1 == in_use){ ++ return -EBUSY; ++ } else { ++ in_use = 1; ++ } ++ cur_ch = ADC_CHANNEL_NONE; ++ mutex_unlock(&adc_mutex); ++ ++ return 0; ++} ++ ++static int gk_adc_close(struct inode *inode, struct file *filp) ++{ ++ mutex_lock(&adc_mutex); ++ in_use = 0; ++ mutex_unlock(&adc_mutex); ++ return 0; ++} ++ ++static long gk_adc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ uint32_t cnt = 0; ++ ADC_STATE_MACHINE_S adc_state; ++ ++ switch (cmd) ++ { ++ case IOC_ADC_SET_CHANNEL: //set ADC channel ++ { ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&adc_state, (void __user *)arg, sizeof(ADC_STATE_MACHINE_S))) ++ return -EFAULT; ++ ++ if((adc_state.channel == ADC_CHANNEL_ONE) ++ || (adc_state.channel == ADC_CHANNEL_TWO)){ ++ mutex_lock(&adc_mutex); ++ cur_ch = adc_state.channel; ++ mutex_unlock(&adc_mutex); ++ ADC_select_channel(cur_ch); ++ }else { ++ printk(KERN_ERR "Invalid param, ADC only has two channel.\n"); ++ return -EINVAL; ++ } ++ break; ++ } ++ case IOC_ADC_GET_CHANNEL: ++ { ++ if(copy_to_user((void __user *)arg, &adc_state, sizeof(ADC_STATE_MACHINE_S))) ++ return -EFAULT; ++ break; ++ } ++ case IOC_ADC_GET_DATA: ++ { ++ if (copy_from_user(&adc_state, (void __user *)arg, sizeof(ADC_STATE_MACHINE_S))) ++ return -EFAULT; ++ if((adc_state.channel == ADC_CHANNEL_ONE) ++ || (adc_state.channel == ADC_CHANNEL_TWO)){ ++ mutex_lock(&adc_mutex); ++ if(adc_state.channel != cur_ch){ ++ cur_ch = adc_state.channel; ++ ADC_select_channel(cur_ch); ++ ADC_set_Control_status(0); ++ while(0 == ADC_get_Control_status()){ ++ cnt++; ++ if (cnt > 10){ ++ break; ++ } ++ mdelay(1); ++ } ++ adc_state.data = ADC_get_ReadData((u32)cur_ch); ++ } ++ else { ++ adc_state.data = ADC_get_ReadData((u32)cur_ch); ++ } ++ mutex_unlock(&adc_mutex); ++ }else { ++ printk(KERN_ERR "Invalid param, ADC only has two channel.\n"); ++ return -EINVAL; ++ } ++ if(copy_to_user((void __user *)arg, &adc_state, sizeof(ADC_STATE_MACHINE_S))) ++ return -EFAULT; ++ break; ++ } ++ default: ++ return -EINVAL; ++ } ++ return 0; //³É¹¦·µ»Ø ++} ++ ++ ++/*initalize structure file operations for adc*/ ++static struct file_operations dev_fops = { ++ .owner = THIS_MODULE, ++ .open = gk_adc_open, ++ .release = gk_adc_close, ++// .read = gk_adc_read, ++ .unlocked_ioctl = gk_adc_ioctl, ++}; ++ ++static struct miscdevice misc = { ++ .minor = 11, /*MISC_DYNAMIC_MINOR,*/ ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ADC_AUX_ATOP_S data; ++ mutex_init(&adc_mutex); ++ in_use = 0; ++ ADC_set_Enable(1); ++ data.all = 0; ++ data.bitc.sar_maxnsel = 0x05; ++ data.bitc.sar_maxsel = 0x05; ++ data.bitc.sar_freerun = 0x01; ++ ADC_set_AUX_ATOP(data.all); ++ // 001 0 1 0 ++ ADC_set_Control(0x000A); ++ ret = misc_register(&misc); //register a misc device ++ printk (DEVICE_NAME" initialized (10:11)\n"); ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); //unregister a misc device ++ mutex_destroy(&adc_mutex); ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_DESCRIPTION("GK ADC Driver"); +diff --git a/drivers/misc/gk_pwm_v1_00.c b/drivers/misc/gk_pwm_v1_00.c +new file mode 100644 +index 00000000..c4df48ac +--- /dev/null ++++ b/drivers/misc/gk_pwm_v1_00.c +@@ -0,0 +1,546 @@ ++/* ++ * drivers/drivers/misc/gk_pwm_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++#define DEVICE_NAME "pwm" //É豸Ãû, major 10 ++#define NODE_NAME "gk_pwm" ++#define MAX_CHANNEL 4 ++ ++//¶¨Òåºê±äÁ¿,ÓÃÓÚºóÃæµÄ ioctl ÖеĿØÖÆÃüÁî ++#define GK_PWM_IOCTL_MAGIC 'k' ++ ++#define _PWM_IO(IOCTL) _IO(GK_PWM_IOCTL_MAGIC, IOCTL) ++#define _PWM_IOR(IOCTL, param) _IOR(GK_PWM_IOCTL_MAGIC, IOCTL, param) ++#define _PWM_IOW(IOCTL, param) _IOW(GK_PWM_IOCTL_MAGIC, IOCTL, param) ++#define _PWM_IOWR(IOCTL, param) _IOWR(GK_PWM_IOCTL_MAGIC, IOCTL, param) ++ ++extern u32 get_apb_bus_freq_hz(void); ++ ++typedef struct pwm_status_s ++{ ++ u8 channel; ++ u8 enable; ++}pwm_status_t; ++ ++typedef struct pwm_mode_s ++{ ++ u8 channel; /* 0 ~ 3*/ ++ u8 mode; /* 0: normal speed 1: sync speed */ ++}pwm_mode_t; ++ ++typedef struct pwm_speed_s ++{ ++ u8 channel; /* 0 ~ 3 */ ++ u32 speed; /* 0x01 ~ 0x3ff*/ ++}pwm_speed_t; ++ ++typedef struct ++{ ++ u8 channel; /* 0 ~ 3 */ ++ u16 xon; /* 0x00 ~ 0xffff */ ++ u16 xoff; /* 0x00 ~ 0xffff */ ++}pwm_duty_t; ++ ++ ++enum { ++ IOCTL_ENABLE = 0x10, ++ IOCTL_DISABLE, ++ IOCTL_SET_DUTY, ++ IOCTL_GET_DUTY, ++ IOCTL_SET_MODE, ++ IOCTL_GET_MODE, ++ IOCTL_SET_SPEED, ++ IOCTL_GET_SPEED, ++ IOCTL_GET_STATUS, ++}; ++ ++#define GK_PWM_IOCTL_ENABLE _PWM_IO(IOCTL_ENABLE) ++#define GK_PWM_IOCTL_DISABLE _PWM_IO(IOCTL_DISABLE) ++#define GK_PWM_IOCTL_SET_DUTY _PWM_IOW(IOCTL_SET_DUTY, pwm_duty_t*) ++#define GK_PWM_IOCTL_GET_DUTY _PWM_IOR(IOCTL_GET_DUTY, pwm_duty_t*) ++#define GK_PWM_IOCTL_SET_MODE _PWM_IOW(IOCTL_SET_MODE, pwm_mode_t*) ++#define GK_PWM_IOCTL_GET_MODE _PWM_IOR(IOCTL_GET_MODE, pwm_mode_t*) ++#define GK_PWM_IOCTL_SET_SPEED _PWM_IOW(IOCTL_SET_SPEED, pwm_speed_t*) ++#define GK_PWM_IOCTL_GET_SPEED _PWM_IOR(IOCTL_GET_SPEED, pwm_speed_t*) ++#define GK_PWM_IOCTL_GET_STATUS _PWM_IOR(IOCTL_GET_STATUS, pwm_status_t*) ++ ++/*----------------------------------------------------------------------------*/ ++/* registers */ ++/*----------------------------------------------------------------------------*/ ++#define PWM_VA_BASE GK_VA_PWM0 ++#define REG_PWM_ENABLE (PWM_VA_BASE + 0x0000) /* read/write */ ++#define REG_PWM_CONTROL (PWM_VA_BASE + 0x0004) /* read/write */ ++#define REG_PWM_CONTROL1 (PWM_VA_BASE + 0x0008) /* read/write */ ++#define REG_PWM_MODE (PWM_VA_BASE + 0x000C) /* read/write */ ++ ++typedef enum ++{ ++ GD_NORMAL_SPEED, ++ GD_SYNC_SPEED, ++}GD_PWM_MODE_E; ++ ++static struct semaphore lock; ++ ++typedef union { /* PWM_Mode */ ++ u32 all; ++ struct { ++ u32 divider : 10; ++ u32 mode : 1; ++ u32 : 21; ++ } bitc; ++} GH_PWM_MODE_S; ++ ++static u32 speed_ctl[5][2] = ++{ ++// speed div clk div max:xon+1+xoff=1 ++ {20000, 1}, // 69000000 / 1 = 69000000 / 2000 = 34500 ++ { 2000, 10}, // 69000000 / 10 = 6900000 / 200 = 34500 ++ { 200, 100}, // 69000000 / 100 = 690000 / 20 = 34500 ++ { 20, 1000}, // 69000000 / 1000 = 69000 / 2 = 34500 ++ { 1, 10000}, // 69000000 / 10000 = 6900 / 1 = 6900 ++}; ++static u32 g_duty[MAX_CHANNEL] = {1000, 1000, 1000, 1000}; ++static u32 g_dutyset[MAX_CHANNEL] = { 499, 499, 499, 499}; ++static void gk_pwm_set_duty(pwm_duty_t *pwm_duty); ++static void gk_pwm_get_duty(pwm_duty_t *pwm_duty); ++ ++/* pwm enable */ ++static inline void GH_PWM_set_Enable(u8 index, u32 data) ++{ ++ gk_pwm_writel(REG_PWM_ENABLE + index * (0x00001000), data); ++} ++ ++/* get pwm enable status */ ++static inline u32 GH_PWM_get_Enable(u8 index) ++{ ++ return gk_pwm_readl(REG_PWM_ENABLE + index * (0x00001000)); ++} ++ ++/* get pwm speed mode */ ++static inline u32 GH_PWM_get_Mode(u8 index) ++{ ++ GH_PWM_MODE_S d; ++ d.all = gk_pwm_readl(REG_PWM_MODE + index * (0x00001000)); ++ return d.bitc.mode; ++ ++} ++ ++/* set pwm speed mode */ ++static inline void GH_PWM_set_Mode(u8 index, u32 data) ++{ ++ GH_PWM_MODE_S d; ++ ++ d.all = gk_pwm_readl(REG_PWM_MODE + index * (0x00001000)); ++ if(data) ++ d.bitc.mode = 1; ++ else ++ d.bitc.mode = 0; ++ gk_pwm_writel(REG_PWM_MODE + index * (0x00001000), d.all); ++} ++ ++/* set pwm divider params */ ++static inline void GH_PWM_set_Mode_divider(u8 index, u16 data) ++{ ++ GH_PWM_MODE_S d; ++ d.all = gk_pwm_readl(REG_PWM_MODE + index * (0x00001000)); ++ d.bitc.divider = data; ++ gk_pwm_writel(REG_PWM_MODE + index * (0x00001000), d.all); ++} ++ ++/* get pwm divider params */ ++static inline u16 GH_PWM_get_Mode_divider(u8 index) ++{ ++ GH_PWM_MODE_S d; ++ d.all = gk_pwm_readl(REG_PWM_MODE + index * (0x00001000)); ++ return d.bitc.divider; ++} ++ ++/* set value of control0 */ ++static inline void GH_PWM_set_Control(u8 index, u32 data) ++{ ++ gk_pwm_writel(REG_PWM_CONTROL + index * (0x00001000), data); ++} ++ ++/* get value of control0 */ ++static inline u32 GH_PWM_get_Control(u8 index) ++{ ++ return gk_pwm_readl(REG_PWM_CONTROL + index * (0x00001000)); ++} ++ ++/* set value of control1 */ ++static inline void GH_PWM_set_Control1(u8 index, u32 data) ++{ ++ gk_pwm_writel(REG_PWM_CONTROL1 + index * (0x00001000), data); ++} ++ ++/* get value of control1 */ ++static inline u32 GH_PWM_get_Control1(u8 index) ++{ ++ return gk_pwm_readl(REG_PWM_CONTROL1 + index * (0x00001000)); ++} ++ ++static inline s32 GH_PWM_get_freq(u8 channel) ++{ ++ u32 frq; ++ if(GH_PWM_get_Mode(channel)) ++ { ++ return -EINVAL;// because we can not get the vi pclk ++ } ++ else ++ { ++ frq = get_apb_bus_freq_hz(); ++ //printk("frq=%d\n", frq); ++ } ++ ++ return frq; ++ ++} ++ ++/* set pwm speed */ ++static int gk_pwm_set_speed(u8 channel, u32 speed) ++{ ++ s32 frq = 0; ++ u16 fdiv = 0; ++ u16 i = 0; ++ pwm_duty_t pwm_duty; ++ pwm_duty.channel = channel; ++ ++ frq = GH_PWM_get_freq(channel); ++ if(frq <= 0) return -EINVAL; ++ ++ fdiv = 1000; ++ for(i=0;i<5;i++) ++ { ++ if(speed >= speed_ctl[i][0]) ++ { ++ fdiv = speed_ctl[i][1]; ++ g_duty[channel] = frq / fdiv / speed; ++ if(g_duty[channel] == 0) ++ { ++ g_duty[channel] = 1; ++ } ++ break; ++ } ++ } ++ if(fdiv == 0) return -EINVAL; ++ ++ //printk(KERN_INFO "\npwm: freq:%d.%03dKHz, pwm freq:%dHz\n", frq/1000, frq%1000, frq/fdiv); ++ if(GH_PWM_get_Mode(channel)) ++ { ++ return -EINVAL;// because we can not get the vi pclk ++ } ++ else ++ { ++ gk_pwm_writel( GK_VA_RCT + 0x060, fdiv); ++ } ++ pwm_duty.xoff = g_dutyset[pwm_duty.channel]; ++ pwm_duty.xon = 998 - g_dutyset[pwm_duty.channel]; ++ // reset duty ++ gk_pwm_set_duty(&pwm_duty); ++ ++ return 0; ++} ++ ++/* get pwm speed */ ++static long gk_pwm_get_speed(u8 channel, u32 *speed) ++{ ++ s32 frq = 0; ++ u32 fdiv = 0; ++ ++ if(GH_PWM_get_Mode(channel)) ++ { ++ //fdiv = GH_PWM_get_Mode_divider(channel); ++ //fdiv += 1; ++ return -EINVAL;// because we can not get the vi pclk ++ } ++ else ++ { ++ fdiv = gk_pwm_readl( GK_VA_RCT + 0x060); ++ } ++ ++ frq = GH_PWM_get_freq(channel); ++ if(frq <= 0) return -EINVAL; ++ ++ *speed = frq / fdiv / g_duty[channel]; ++ ++ return 0; ++} ++ ++/* set pwm duty rate */ ++static void gk_pwm_set_duty(pwm_duty_t *pwm_duty) ++{ ++ u32 mode; ++ ++ g_dutyset[pwm_duty->channel] = pwm_duty->xoff; ++ pwm_duty->xoff = (pwm_duty->xoff + 1) * g_duty[pwm_duty->channel] / 1000; ++ pwm_duty->xon = (pwm_duty->xon + 1) * g_duty[pwm_duty->channel] / 1000; ++ if(pwm_duty->xoff) ++ pwm_duty->xoff --; ++ if(pwm_duty->xon) ++ pwm_duty->xon --; ++ ++ mode = GH_PWM_get_Mode(pwm_duty->channel); ++ if(mode == GD_NORMAL_SPEED){ ++ GH_PWM_set_Control(pwm_duty->channel,(pwm_duty->xoff << 16| pwm_duty->xon)); ++ } ++ else if(mode == GD_SYNC_SPEED){ ++ GH_PWM_set_Control1(pwm_duty->channel,(pwm_duty->xoff << 16| pwm_duty->xon)); ++ } ++} ++ ++/* get pwm duty rate */ ++static void gk_pwm_get_duty(pwm_duty_t *pwm_duty) ++{ ++ u32 mode = 0; ++ u32 duty_data = 0; ++ ++ mode = GH_PWM_get_Mode(pwm_duty->channel); ++ if(mode == GD_NORMAL_SPEED){ ++ duty_data = GH_PWM_get_Control(pwm_duty->channel); ++ } ++ else if(mode == GD_SYNC_SPEED){ ++ duty_data = GH_PWM_get_Control1(pwm_duty->channel); ++ } ++ pwm_duty->xoff = (duty_data >> 16) & 0xffff; ++ pwm_duty->xon = duty_data & 0xffff; ++ // fix to pwm_duty->xoff + 1 + pwm_duty->xon + 1 = 1000 (adi) ++ pwm_duty->xoff = (pwm_duty->xoff + 1) * 1000 / g_duty[pwm_duty->channel]; ++ pwm_duty->xon = (pwm_duty->xon + 1) * 1000 / g_duty[pwm_duty->channel]; ++ if(pwm_duty->xoff) ++ pwm_duty->xoff --; ++ if(pwm_duty->xon) ++ pwm_duty->xon --; ++} ++ ++/* open file description of pwm */ ++static int gk_pwm_open(struct inode *inode, struct file *file) ++{ ++ if (!down_trylock(&lock)) //ÊÇ·ñ»ñµÃÐźÅÁ¿,ÊÇ down_trylock(&lock)=0,·ñÔò·Ç 0 ++ { ++ //configure PWM function. ++ gk_gpio_config(gk_all_gpio_cfg.pwm0, GPIO_TYPE_OUTPUT_PWM0_OUT); ++ gk_gpio_config(gk_all_gpio_cfg.pwm1, GPIO_TYPE_OUTPUT_PWM1_OUT); ++ gk_gpio_config(gk_all_gpio_cfg.pwm2, GPIO_TYPE_OUTPUT_PWM2_OUT); ++ gk_gpio_config(gk_all_gpio_cfg.pwm3, GPIO_TYPE_OUTPUT_PWM3_OUT); ++ return 0; ++ } ++ else ++ return -EBUSY; //·µ»Ø´íÎóÐÅÏ¢:ÇëÇóµÄ×ÊÔ´²»¿ÉÓà ++} ++/* close pwm */ ++static int gk_pwm_close(struct inode *inode, struct file *file) ++{ ++ GH_PWM_set_Enable(0,0); ++ GH_PWM_set_Enable(1,0); ++ GH_PWM_set_Enable(2,0); ++ GH_PWM_set_Enable(3,0); ++ // logout PWM function. ++ gk_gpio_config(gk_all_gpio_cfg.pwm0, GPIO_TYPE_UNDEFINED); ++ gk_gpio_config(gk_all_gpio_cfg.pwm1, GPIO_TYPE_UNDEFINED); ++ gk_gpio_config(gk_all_gpio_cfg.pwm2, GPIO_TYPE_UNDEFINED); ++ gk_gpio_config(gk_all_gpio_cfg.pwm3, GPIO_TYPE_UNDEFINED); ++ up(&lock); //ÊÍ·ÅÐźÅÁ¿ lock ++ ++ return 0; ++} ++ ++/* pwm ioctl */ ++static long gk_pwm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++// pwm_ctrl_t pwm_ctrl; ++ long error = 0; ++ pwm_mode_t pwm_mode; ++ pwm_duty_t pwm_duty; ++ pwm_speed_t pwm_speed; ++ pwm_status_t pwm_status; ++ switch (cmd) ++ { ++ case GK_PWM_IOCTL_DISABLE: //disabel channel ++ if(arg >= MAX_CHANNEL) return -EINVAL; ++ ++ GH_PWM_set_Enable(arg, 0); ++ break; ++ ++ case GK_PWM_IOCTL_ENABLE: //enabel channel ++ if(arg >= MAX_CHANNEL) return -EINVAL; ++ ++ GH_PWM_set_Enable(arg, 1); ++ break; ++ ++ ++ case GK_PWM_IOCTL_SET_MODE: //config pwm mode. ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&pwm_mode, (void __user *)arg, sizeof(pwm_mode_t))) ++ return -EFAULT; ++ ++ //printk("set mode channel:%d mode:%d\n", pwm_mode.channel, pwm_mode.mode); ++ GH_PWM_set_Mode(pwm_mode.channel, pwm_mode.mode); ++ ++ break; ++ ++ case GK_PWM_IOCTL_GET_MODE: //get pwm mode. ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&pwm_mode, (void __user *)arg, sizeof(pwm_mode_t))) ++ return -EFAULT; ++ ++ pwm_mode.mode = GH_PWM_get_Mode(pwm_mode.channel); ++ ++ if (copy_to_user((void __user *)arg, &pwm_mode, sizeof(pwm_mode_t))) ++ return -EFAULT; ++ ++ break; ++ ++ case GK_PWM_IOCTL_SET_SPEED://set pwm speed. ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&pwm_speed, (void __user *)arg, sizeof(pwm_speed_t))) ++ return -EFAULT; ++ ++ //printk("set speed channel:%d speed:%d\n", pwm_speed.channel, pwm_speed.speed); ++ return gk_pwm_set_speed(pwm_speed.channel, pwm_speed.speed); ++ ++ break; ++ ++ case GK_PWM_IOCTL_GET_SPEED://get pwm speed. ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&pwm_speed, (void __user *)arg, sizeof(pwm_speed_t))) ++ return -EFAULT; ++ ++ error = gk_pwm_get_speed(pwm_speed.channel, &pwm_speed.speed); ++ if(error != 0) ++ return error; ++ ++ if (copy_to_user((void __user *)arg, &pwm_speed, sizeof(pwm_speed_t))) ++ return -EFAULT; ++ ++ break; ++ ++ case GK_PWM_IOCTL_SET_DUTY://set pwm duty. ++ if (arg == 0) ++ return -EINVAL; //·µ»Ø´íÎóÐÅÏ¢,±íʾÏò²ÎÊý´«µÝÁËÎÞЧµÄ²ÎÊý ++ ++ if (copy_from_user(&pwm_duty, (void __user *)arg, sizeof(pwm_duty_t))) ++ return -EFAULT; ++ gk_pwm_set_duty(&pwm_duty); ++ ++ break; ++ ++ case GK_PWM_IOCTL_GET_DUTY://get pwm duty. ++ if (arg == 0) ++ return -EINVAL; //·µ»Ø´íÎóÐÅÏ¢,±íʾÏò²ÎÊý´«µÝÁËÎÞЧµÄ²ÎÊý ++ ++ if (copy_from_user(&pwm_duty, (void __user *)arg, sizeof(pwm_duty_t))) ++ return -EFAULT; ++ ++ gk_pwm_get_duty(&pwm_duty); ++ ++ if (copy_to_user((void __user *)arg, &pwm_duty, sizeof(pwm_duty_t))) ++ return -EFAULT; ++ ++ break; ++ ++ case GK_PWM_IOCTL_GET_STATUS: ++ if (arg == 0) ++ return -EINVAL; ++ ++ if (copy_from_user(&pwm_status, (void __user *)arg, sizeof(pwm_status_t))) ++ return -EFAULT; ++ ++ pwm_status.enable = (GH_PWM_get_Enable(pwm_status.channel) > 0) ? 1 : 0; ++ ++ if (copy_to_user((void __user *)arg, &pwm_status, sizeof(pwm_status_t))) ++ return -EFAULT; ++ ++ break; ++ ++ default: ++ printk(KERN_ERR "\npwm:bad params\n"); ++ return -EINVAL; ++ break; ++ } ++ return 0; //normal return ++} ++ ++ ++/*³õʼ»¯É豸µÄÎļþ²Ù×÷µÄ½á¹¹Ìå*/ ++static struct file_operations dev_fops = { ++ .owner = THIS_MODULE, ++ .open = gk_pwm_open, ++ .release = gk_pwm_close, ++ .unlocked_ioctl = gk_pwm_ioctl, ++}; ++ ++static struct miscdevice misc = { ++ .minor = 10, /*MISC_DYNAMIC_MINOR,*/ ++ .name = DEVICE_NAME, ++ .nodename = NODE_NAME, ++ .fops = &dev_fops, ++}; ++ ++ ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ sema_init(&lock, 1); //³õʼ»¯Ò»¸ö»¥³âËø ++ ret = misc_register(&misc); //×¢²áÒ»¸ö misc É豸 ++ printk (DEVICE_NAME" initialized (10:10)\n"); ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); //×¢ÏúÉ豸 ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_DESCRIPTION("GK PWM Driver"); +diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig +index 2bc06e73..1ac19e69 100644 +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -4,6 +4,14 @@ + + comment "MMC/SD/SDIO Host Controller Drivers" + ++config MMC_GOKE ++ tristate "goke ipc SD/MMC Host Controller driver" ++ depends on GK_SDIO ++ help ++ This selects the goke ipc Media Processor Multimedia Card ++ Interface support. If you have an goke Media Processor ++ platform with a Multimedia Card slot, say Y here. ++ + config MMC_ARMMMCI + tristate "ARM AMBA Multimedia Card Interface support" + depends on ARM_AMBA +diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile +index 3e7e26d0..7477add4 100644 +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -2,6 +2,9 @@ + # Makefile for MMC/SD host controller drivers + # + ++ifdef CONFIG_MMC_GOKE ++obj-$(CONFIG_GK_SDIO2_V1_00) += gk_sdio2_v1_00.o ++endif + obj-$(CONFIG_MMC_ARMMMCI) += mmci.o + obj-$(CONFIG_MMC_PXA) += pxamci.o + obj-$(CONFIG_MMC_IMX) += imxmmc.o +diff --git a/drivers/mmc/host/gk_sdio2_v1_00.c b/drivers/mmc/host/gk_sdio2_v1_00.c +new file mode 100644 +index 00000000..d3d4295b +--- /dev/null ++++ b/drivers/mmc/host/gk_sdio2_v1_00.c +@@ -0,0 +1,2077 @@ ++/* ++ * drivers/mmc/host/gk_sdio2_v1_00.c ++ * ++ * Author: louis liang ++ * Copyright (C) 2014-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++ ++/*----------------------------------------------------------------------------*/ ++/* registers base: GK_VA_SDC */ ++/*----------------------------------------------------------------------------*/ ++ ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++ ++/* ==========================================================================*/ ++/* ==========================================================================*/ ++#define CONFIG_SD_GK_TIMEOUT_VAL (0xe) ++#define CONFIG_SD_GK_WAIT_TIMEOUT (HZ / 100) ++#define CONFIG_SD_GK_WAIT_COUNTER_LIMIT (100000) ++#define CONFIG_SD_GK_DEFAULT_CLOCK (48000000) ++#define CONFIG_SD_GK_MAX_TIMEOUT (10 * HZ) ++ ++//#define CONFIG_SD_GK_DEBUG ++#undef CONFIG_SD_GK_DEBUG_VERBOSE ++ ++#define gk_sd_printk(level, phcinfo, format, arg...) \ ++ printk("-- %s.%u: " format, \ ++ dev_name(((struct gk_sd_controller_info *)phcinfo->pinfo)->dev),\ ++ phcinfo->slot_id, ## arg) ++ ++#define gk_sd_err(phcinfo, format, arg...) \ ++ gk_sd_printk(KERN_ERR, phcinfo, format, ## arg) ++#define gk_sd_warn(phcinfo, format, arg...) \ ++ gk_sd_printk(KERN_WARNING, phcinfo, format, ## arg) ++#define gk_sd_info(phcinfo, format, arg...) \ ++ gk_sd_printk(KERN_INFO, phcinfo, format, ## arg) ++#define gk_sd_rtdbg(phcinfo, format, arg...) \ ++ gk_sd_printk(KERN_DEBUG, phcinfo, format, ## arg) ++ ++#ifdef CONFIG_SD_GK_DEBUG ++#define gk_sd_dbg(phcinfo, format, arg...) \ ++ gk_sd_printk(KERN_DEBUG, phcinfo, format, ## arg) ++#else ++#define gk_sd_dbg(phcinfo, format, arg...) \ ++ ({ if (0) gk_sd_printk(KERN_DEBUG, phcinfo, format, ##arg); 0; }) ++#endif ++ ++/* ==========================================================================*/ ++enum gk_sd_state { ++ GK_SD_STATE_IDLE, ++ GK_SD_STATE_CMD, ++ GK_SD_STATE_DATA, ++ GK_SD_STATE_RESET, ++ GK_SD_STATE_ERR ++}; ++ ++#define REG_WR(reg,value) (*((volatile u32 *)(reg))=(value)) ++ ++struct gk_sd_mmc_info { ++ struct mmc_host *mmc; ++ struct mmc_request *mrq; ++ ++ wait_queue_head_t wait; ++ ++ enum gk_sd_state state; ++ ++ struct scatterlist *sg; ++ u32 sg_len; ++ u32 wait_tmo; ++ u16 blk_sz; ++ u16 blk_cnt; ++ u32 arg_reg; ++ u16 xfr_reg; ++ u16 cmd_reg; ++ u16 sta_reg; ++ u8 tmo; ++ u8 use_adma; ++ u32 sta_counter; ++ ++ char *buf_vaddress; ++ dma_addr_t buf_paddress; ++ u32 dma_address; ++ u32 dma_size; ++ ++ void (*pre_dma)(void *data); ++ void (*post_dma)(void *data); ++ ++ struct gk_sd_slot *plat_info; ++ u32 slot_id; ++ void *pinfo; ++ u32 valid; ++ ++ struct notifier_block system_event; ++ struct semaphore system_event_sem; ++}; ++ ++struct gk_sd_controller_info { ++ unsigned char __iomem *regbase; ++ struct device *dev; ++ unsigned int irq; ++ u32 dma_fix; ++ u32 clk_limit; ++ u32 reset_error; ++ ++ u32 max_blk_sz; ++ struct kmem_cache *buf_cache; ++ ++ struct gk_sd_controller *pcontroller; ++ struct gk_sd_mmc_info *pslotinfo[GK_SD_MAX_SLOT_NUM]; ++ struct mmc_ios controller_ios; ++}; ++ ++/* ==========================================================================*/ ++#ifdef CONFIG_SD_GK_DEBUG_VERBOSE ++static void gk_sd_show_info(struct gk_sd_mmc_info *pslotinfo) ++{ ++ gk_sd_dbg(pslotinfo, "Enter %s\n", __func__); ++ gk_sd_dbg(pslotinfo, "sg = 0x%x.\n", (u32)pslotinfo->sg); ++ gk_sd_dbg(pslotinfo, "sg_len = 0x%x.\n", pslotinfo->sg_len); ++ gk_sd_dbg(pslotinfo, "tmo = 0x%x.\n", pslotinfo->tmo); ++ gk_sd_dbg(pslotinfo, "blk_sz = 0x%x.\n", pslotinfo->blk_sz); ++ gk_sd_dbg(pslotinfo, "blk_cnt = 0x%x.\n", pslotinfo->blk_cnt); ++ gk_sd_dbg(pslotinfo, "arg_reg = 0x%x.\n", pslotinfo->arg_reg); ++ gk_sd_dbg(pslotinfo, "xfr_reg = 0x%x.\n", pslotinfo->xfr_reg); ++ gk_sd_dbg(pslotinfo, "cmd_reg = 0x%x.\n", pslotinfo->cmd_reg); ++ gk_sd_dbg(pslotinfo, "buf_vaddress = 0x%x.\n", (u32)pslotinfo->buf_vaddress); ++ gk_sd_dbg(pslotinfo, "buf_paddress = 0x%x.\n", pslotinfo->buf_paddress); ++ gk_sd_dbg(pslotinfo, "dma_address = 0x%x.\n", pslotinfo->dma_address); ++ gk_sd_dbg(pslotinfo, "dma_size = 0x%x.\n", pslotinfo->dma_size); ++ gk_sd_dbg(pslotinfo, "pre_dma = 0x%x.\n", (u32)pslotinfo->pre_dma); ++ gk_sd_dbg(pslotinfo, "post_dma = 0x%x.\n", (u32)pslotinfo->post_dma); ++ gk_sd_dbg(pslotinfo, "SD: state = 0x%x.\n", pslotinfo->state); ++ gk_sd_dbg(pslotinfo, "Exit %s\n", __func__); ++} ++#endif ++ ++ ++static u32 gk_sd_check_dma_boundary( ++ struct gk_sd_mmc_info *pslotinfo, ++ u32 address, u32 size, u32 max_size) ++{ ++ u32 start_512kb; ++ u32 end_512kb; ++ ++ start_512kb = (address) & (~(max_size - 1)); ++ end_512kb = (address + size - 1) & (~(max_size - 1)); ++ ++ if (start_512kb != end_512kb) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static u32 gk_sd_dma_mask_to_size(u32 mask) ++{ ++ u32 size; ++ ++ switch (mask) { ++ case SD_BLK_SZ_512KB: ++ size = 0x80000; ++ break; ++ case SD_BLK_SZ_256KB: ++ size = 0x40000; ++ break; ++ case SD_BLK_SZ_128KB: ++ size = 0x20000; ++ break; ++ case SD_BLK_SZ_64KB: ++ size = 0x10000; ++ break; ++ case SD_BLK_SZ_32KB: ++ size = 0x8000; ++ break; ++ case SD_BLK_SZ_16KB: ++ size = 0x4000; ++ break; ++ case SD_BLK_SZ_8KB: ++ size = 0x2000; ++ break; ++ case SD_BLK_SZ_4KB: ++ size = 0x1000; ++ break; ++ default: ++ size = 0; ++ BUG_ON(1); ++ break; ++ } ++ ++ return size; ++} ++ ++static void gk_sd_pre_sg_to_dma(void *data) ++{ ++ struct gk_sd_mmc_info *pslotinfo; ++ struct gk_sd_controller_info *pinfo; ++ int i; ++ //int j; ++ u32 offset; ++ //u32 *res; ++ ++ pslotinfo = (struct gk_sd_mmc_info *)data; ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ ++ for (i = 0, offset = 0; i < pslotinfo->sg_len; i++) { ++ //printk("copy: 0x%0x - 0x%0x len=%d\n", pslotinfo->buf_vaddress + offset, ++ // sg_virt(&pslotinfo->sg[i]), pslotinfo->sg[i].length); ++#if 0 ++ res = (u32*)(pslotinfo->buf_vaddress + offset); ++ for(j=0;jsg[i].length/4;j++) ++ printk("0x%0x \n", res[j]); ++ printk("\n"); ++#endif ++ ++ memcpy(pslotinfo->buf_vaddress + offset, ++ sg_virt(&pslotinfo->sg[i]), ++ pslotinfo->sg[i].length); ++ offset += pslotinfo->sg[i].length; ++ } ++ ++ BUG_ON(offset != pslotinfo->dma_size); ++ dma_sync_single_for_device(pinfo->dev, pslotinfo->buf_paddress, ++ pslotinfo->dma_size, DMA_TO_DEVICE); ++ pslotinfo->dma_address = pslotinfo->buf_paddress; ++ pslotinfo->blk_sz |= SD_BLK_SZ_512KB; ++} ++ ++static void gk_sd_post_sg_to_dma(void *data) ++{ ++ struct gk_sd_mmc_info *pslotinfo; ++ struct gk_sd_controller_info *pinfo; ++ ++ ++ pslotinfo = (struct gk_sd_mmc_info *)data; ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ dma_sync_single_for_cpu(pinfo->dev, pslotinfo->buf_paddress, ++ pslotinfo->dma_size, DMA_TO_DEVICE); ++} ++ ++static void gk_sd_pre_dma_to_sg(void *data) ++{ ++ struct gk_sd_mmc_info *pslotinfo; ++ struct gk_sd_controller_info *pinfo; ++ ++ pslotinfo = (struct gk_sd_mmc_info *)data; ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ dma_sync_single_for_device(pinfo->dev, pslotinfo->buf_paddress, pslotinfo->dma_size, DMA_FROM_DEVICE); ++ //printk("dma_sync_single_for_device: buf=0x%x size=%d\n", pslotinfo->buf_paddress, pslotinfo->dma_size); ++ pslotinfo->dma_address = pslotinfo->buf_paddress; ++ pslotinfo->blk_sz |= SD_BLK_SZ_512KB; ++} ++ ++static void gk_sd_post_dma_to_sg(void *data) ++{ ++ struct gk_sd_mmc_info *pslotinfo; ++ struct gk_sd_controller_info *pinfo; ++ int i; ++ //int j; ++ //u8 *res; ++ u32 offset; ++ ++ pslotinfo = (struct gk_sd_mmc_info *)data; ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ dma_sync_single_for_cpu(pinfo->dev, pslotinfo->buf_paddress, ++ pslotinfo->dma_size, DMA_FROM_DEVICE); ++ for (i = 0, offset = 0; i < pslotinfo->sg_len; i++) { ++ ++ //printk("copy: 0x%0x - 0x%0x len=%d\n", sg_virt(&pslotinfo->sg[i]), ++ // pslotinfo->buf_vaddress + offset, pslotinfo->sg[i].length); ++#if 0 ++ res = (u8*)(pslotinfo->buf_vaddress + offset); ++ for(j=0;jsg[i].length;j=j+8) ++ printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x \n", ++ res[j], res[j+1], res[j+2], res[j+3], ++ res[j+4], res[j+5], res[j+6], res[j+7]); ++ printk("\n"); ++#endif ++ memcpy(sg_virt(&pslotinfo->sg[i]), ++ pslotinfo->buf_vaddress + offset, ++ pslotinfo->sg[i].length); ++ offset += pslotinfo->sg[i].length; ++ } ++ BUG_ON(offset != pslotinfo->dma_size); ++} ++ ++static void gk_sd_request_bus(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ ++ down(&pslotinfo->system_event_sem); ++ ++ if (pslotinfo->plat_info->request) ++ pslotinfo->plat_info->request(); ++} ++ ++static void gk_sd_release_bus(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ ++ if (pslotinfo->plat_info->release) ++ pslotinfo->plat_info->release(); ++ ++ up(&pslotinfo->system_event_sem); ++} ++ ++static void gk_sd_enable_int(struct mmc_host *mmc, u32 mask) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ ++ pslotinfo->plat_info->set_int(mask, 1); ++} ++ ++static void gk_sd_disable_int(struct mmc_host *mmc, u32 mask) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ ++ pslotinfo->plat_info->set_int(mask, 0); ++} ++ ++static void gk_sd_set_iclk(struct mmc_host *mmc, u16 clk_div) ++{ ++ u16 clkreg; ++ u32 counter = 0; ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++// printk("set clock div\n"); ++ ++ ++#if 1 ++ clk_div <<= 8; ++ clk_div |= SD_CLK_ICLK_EN; ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CLK_OFFSET, clk_div); ++ //printk("## 1set clock div = %d \n", clk_div); ++ while (1) { ++ clkreg = gk_sd_readw((unsigned int)pinfo->regbase + SD_CLK_OFFSET); ++ if (clkreg & SD_CLK_ICLK_STABLE) ++ break; ++ if ((clkreg & ~SD_CLK_ICLK_STABLE) != clk_div) { ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CLK_OFFSET, clk_div); ++ //printk("## 2set clock div = %d \n", clk_div); ++ udelay(1); ++ } ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, ++ "Wait SD_CLK_ICLK_STABLE = %d @ 0x%x\n", ++ counter, clkreg); ++ break; ++ } ++ } ++#endif ++} ++ ++static void gk_sd_clear_clken(struct mmc_host *mmc) ++{ ++ u16 clkreg; ++ u32 counter = 0; ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ while (1) { ++ clkreg = gk_sd_readw((unsigned int)pinfo->regbase + SD_CLK_OFFSET); ++ if (clkreg & SD_CLK_EN) { ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CLK_OFFSET, ++ (clkreg & ~SD_CLK_EN)); ++ udelay(1); ++ } else { ++ break; ++ } ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, "%s(%d @ 0x%x)\n", ++ __func__, counter, clkreg); ++ break; ++ } ++ } ++} ++ ++static void gk_sd_set_clken(struct mmc_host *mmc) ++{ ++ u16 clkreg; ++ u32 counter = 0; ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ while (1) { ++ clkreg = gk_sd_readw((unsigned int)pinfo->regbase + SD_CLK_OFFSET); ++ if (clkreg & SD_CLK_EN) { ++ break; ++ } else { ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CLK_OFFSET, (clkreg | SD_CLK_EN)); ++ //printk("## 3set clock div = %d \n", (clkreg | SD_CLK_EN)); ++ udelay(1); ++ } ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, "%s(%d @ 0x%x)\n", ++ __func__, counter, clkreg); ++ break; ++ } ++ } ++} ++ ++static void gk_sd_reset_all(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u32 nis_flag = 0; ++ u32 eis_flag = 0; ++ u32 counter = 0; ++ u8 reset_reg; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ //printk(pslotinfo, "Enter %s with state %u\n", __func__, pslotinfo->state); ++ ++ gk_sd_disable_int(mmc, 0xFFFFFFFF); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_NIS_OFFSET, 0xFFFF); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_EIS_OFFSET, 0xFFFF); ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_RESET_OFFSET, SD_RESET_ALL); ++ while (1) { ++ reset_reg = gk_sd_readb((unsigned int)pinfo->regbase + SD_RESET_OFFSET); ++ if (!(reset_reg & SD_RESET_ALL)) ++ break; ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, "Wait SD_RESET_ALL....\n"); ++ break; ++ } ++ } ++ ++ gk_sd_set_iclk(mmc, 0x0000); ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_TMO_OFFSET, ++ CONFIG_SD_GK_TIMEOUT_VAL); ++ ++ nis_flag = SD_NISEN_REMOVAL | ++ SD_NISEN_INSERT | ++ SD_NISEN_DMA | ++ SD_NISEN_BLOCK_GAP | ++ SD_NISEN_XFR_DONE | ++ SD_NISEN_CMD_DONE; ++ eis_flag = SD_EISEN_ACMD12_ERR | ++ SD_EISEN_CURRENT_ERR | ++ SD_EISEN_DATA_BIT_ERR | ++ SD_EISEN_DATA_CRC_ERR | ++ SD_EISEN_DATA_TMOUT_ERR | ++ SD_EISEN_CMD_IDX_ERR | ++ SD_EISEN_CMD_BIT_ERR | ++ SD_EISEN_CMD_CRC_ERR | ++ SD_EISEN_CMD_TMOUT_ERR; ++ ++ gk_sd_enable_int(mmc, (eis_flag << 16) | nis_flag); ++ ++ //GD_SDIO_Rest(); ++ ++ pslotinfo->state = GK_SD_STATE_RESET; ++ pinfo->reset_error = 0; ++ ++ gk_sd_dbg(pslotinfo, "Exit %s with counter %u\n", __func__, counter); ++} ++ ++static void gk_sd_reset_cmd_line(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u32 counter = 0; ++ u8 reset_reg; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_RESET_OFFSET, SD_RESET_CMD); ++ while (1) { ++ reset_reg = gk_sd_readb((unsigned int)pinfo->regbase + SD_RESET_OFFSET); ++ if (!(reset_reg & SD_RESET_CMD)) ++ break; ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ //printk("Wait SD_RESET_CMD...\n"); ++ pinfo->reset_error = 1; ++ break; ++ } ++ } ++} ++ ++static void gk_sd_reset_data_line(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u32 counter = 0; ++ u8 reset_reg; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ gk_sd_dbg(pslotinfo, "Enter %s with state %u\n", ++ __func__, pslotinfo->state); ++ ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_RESET_OFFSET, SD_RESET_DAT); ++ while (1) { ++ reset_reg = gk_sd_readb((unsigned int)pinfo->regbase + SD_RESET_OFFSET); ++ if (!(reset_reg & SD_RESET_DAT)) ++ break; ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, "Wait SD_RESET_DAT...\n"); ++ pinfo->reset_error = 1; ++ break; ++ } ++ } ++ gk_sd_dbg(pslotinfo, "Exit %s with counter %u\n", __func__, counter); ++} ++ ++static inline void gk_sd_data_done( ++ struct gk_sd_mmc_info *pslotinfo, u16 nis, u16 eis) ++{ ++ struct mmc_data *data; ++ ++ if ((pslotinfo->state == GK_SD_STATE_CMD) && ++ ((pslotinfo->cmd_reg & 0x3) == SD_CMD_RSP_48BUSY)) { ++ if (eis) { ++ pslotinfo->state = GK_SD_STATE_ERR; ++ } else { ++ pslotinfo->state = GK_SD_STATE_IDLE; ++ } ++ wake_up(&pslotinfo->wait); ++ return; ++ } ++ if (pslotinfo->mrq == NULL) { ++ gk_sd_dbg(pslotinfo, "%s: mrq is NULL, nis[0x%x] eis[0x%x]\n", ++ __func__, nis, eis); ++ return; ++ } ++ if (pslotinfo->mrq->data == NULL) { ++ gk_sd_dbg(pslotinfo, "%s: data is NULL, nis[0x%x] eis[0x%x]\n", ++ __func__, nis, eis); ++ return; ++ } ++ ++ data = pslotinfo->mrq->data; ++ ++ //printk("### CMD[%u] get eis[0x%x]\n", pslotinfo->mrq->cmd->opcode, eis); ++ ++ if (eis) { ++ if (eis & SD_EIS_DATA_BIT_ERR) { ++ data->error = -EILSEQ; ++ } else if (eis & SD_EIS_DATA_CRC_ERR) { ++ data->error = -EILSEQ; ++ } else if (eis & SD_EIS_DATA_TMOUT_ERR) { ++ data->error = -ETIMEDOUT; ++ } else { ++ data->error = -EIO; ++ } ++//#ifdef CONFIG_SD_GK_DEBUG_VERBOSE ++ //printk("error -- %s: CMD[%u] get eis[0x%x]\n", __func__, ++ // pslotinfo->mrq->cmd->opcode, eis); ++//#endif ++ pslotinfo->state = GK_SD_STATE_ERR; ++ wake_up(&pslotinfo->wait); ++ return; ++ } else { ++ data->bytes_xfered = pslotinfo->dma_size; ++ } ++ ++ pslotinfo->state = GK_SD_STATE_IDLE; ++ wake_up(&pslotinfo->wait); ++} ++ ++static inline void gk_sd_cmd_done( ++ struct gk_sd_mmc_info *pslotinfo, u16 nis, u16 eis) ++{ ++ struct mmc_command *cmd; ++ u32 rsp0, rsp1, rsp2, rsp3; ++ struct gk_sd_controller_info *pinfo; ++ u16 ac12es; ++ ++ if (pslotinfo->mrq == NULL) { ++ printk("%s: mrq is NULL, nis[0x%x] eis[0x%x]\n", ++ __func__, nis, eis); ++ return; ++ } ++ if (pslotinfo->mrq->cmd == NULL) { ++ printk( "%s: cmd is NULL, nis[0x%x] eis[0x%x]\n", ++ __func__, nis, eis); ++ return; ++ } ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ cmd = pslotinfo->mrq->cmd; ++ ++ //printk("#### CMD[%u] get eis[0x%x]\n", pslotinfo->mrq->cmd->opcode, eis); ++ ++ if (eis) { ++ if (eis & SD_EIS_CMD_BIT_ERR) { ++ cmd->error = -EILSEQ; ++ } else if (eis & SD_EIS_CMD_CRC_ERR) { ++ cmd->error = -EILSEQ; ++ } else if (eis & SD_EIS_CMD_TMOUT_ERR) { ++ cmd->error = -ETIMEDOUT; ++ } else if (eis & SD_EIS_ACMD12_ERR) { ++ ac12es = gk_sd_readl((unsigned int)pinfo->regbase + SD_AC12ES_OFFSET); ++ if (ac12es & SD_AC12ES_TMOUT_ERROR) { ++ cmd->error = -ETIMEDOUT; ++ } else if (eis & SD_AC12ES_CRC_ERROR) { ++ cmd->error = -EILSEQ; ++ } else { ++ cmd->error = -EIO; ++ } ++ ++ if (pslotinfo->mrq->stop) { ++ pslotinfo->mrq->stop->error = cmd->error; ++ } else { ++ gk_sd_err(pslotinfo, "%s NULL stop 0x%x %u\n", ++ __func__, ac12es, cmd->error); ++ } ++ } else { ++ cmd->error = -EIO; ++ } ++//#ifdef CONFIG_SD_GK_DEBUG_VERBOSE ++ ++//#endif ++ pslotinfo->state = GK_SD_STATE_ERR; ++ ++ //printk("error - %s: CMD[%u] get eis[0x%x] state= [%s]\n", __func__, ++ // pslotinfo->mrq->cmd->opcode, eis, sd_state(pslotinfo->state)); ++ ++ wake_up(&pslotinfo->wait); ++ return; ++ } ++//printk("cmd handle ok...get reponse\n"); ++ if (cmd->flags & MMC_RSP_136) { ++ rsp0 = gk_sd_readl((unsigned int)pinfo->regbase + SD_RSP0_OFFSET); ++ rsp1 = gk_sd_readl((unsigned int)pinfo->regbase + SD_RSP1_OFFSET); ++ rsp2 = gk_sd_readl((unsigned int)pinfo->regbase + SD_RSP2_OFFSET); ++ rsp3 = gk_sd_readl((unsigned int)pinfo->regbase + SD_RSP3_OFFSET); ++ cmd->resp[0] = ((rsp3 << 8) | (rsp2 >> 24)); ++ cmd->resp[1] = ((rsp2 << 8) | (rsp1 >> 24)); ++ cmd->resp[2] = ((rsp1 << 8) | (rsp0 >> 24)); ++ cmd->resp[3] = (rsp0 << 8); ++ ++ //printk("response1: [0x%x] [0x%x] [0x%x] [0x%x] \n", cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); ++ } else { ++ cmd->resp[0] = gk_sd_readl((unsigned int)pinfo->regbase + SD_RSP0_OFFSET); ++ //printk("response2: [0x%x] \n", cmd->resp[0]); ++ } ++ ++ if ((pslotinfo->state == GK_SD_STATE_CMD) && ++ ((pslotinfo->cmd_reg & 0x3) != SD_CMD_RSP_48BUSY)) { ++ pslotinfo->state = GK_SD_STATE_IDLE; ++ wake_up(&pslotinfo->wait); ++ } ++} ++ ++static irqreturn_t gk_sd_irq(int irq, void *devid) ++{ ++ struct gk_sd_controller_info *pinfo; ++ struct gk_sd_mmc_info *pslotinfo = NULL; ++ u16 nis=0; ++ u16 eis=0; ++ u32 enabled = 0; ++ u32 i; ++ ++ pinfo = (struct gk_sd_controller_info *)devid; ++ ++ /* Read the interrupt registers */ ++ nis = gk_sd_readw((unsigned int)pinfo->regbase + SD_NIS_OFFSET); ++ eis = gk_sd_readw((unsigned int)pinfo->regbase + SD_EIS_OFFSET); ++ //printk("-- nis = 0x%x eis = 0x%x\n", nis, eis); ++#if 0 ++ switch(nis) ++ { ++ case SD_NIS_ERROR: ++ printk("-- SD_NIS_ERROR\n"); ++ break; ++ case SD_NIS_CARD: ++ printk("-- SD_NIS_CARD\n"); ++ break; ++ case SD_NIS_REMOVAL: ++ printk("-- SD_NIS_REMOVAL\n"); ++ break; ++ case SD_NIS_INSERT: ++ printk("-- SD_NIS_INSERT\n"); ++ break; ++ case SD_NIS_READ_READY: ++ printk("-- SD_NIS_READ_READY\n"); ++ break; ++ case SD_NIS_WRITE_READY: ++ printk("-- SD_NIS_WRITE_READY\n"); ++ break; ++ case SD_NIS_DMA: ++ printk("-- SD_NIS_DMA\n"); ++ break; ++ case SD_NIS_BLOCK_GAP: ++ printk("-- SD_NIS_BLOCK_GAP\n"); ++ break; ++ case SD_NIS_XFR_DONE: ++ printk("-- SD_NIS_XFR_DONE\n"); ++ break; ++ case SD_NIS_CMD_DONE: ++ printk("-- SD_NIS_CMD_DONE\n"); ++ break; ++ default: ++ printk("-- unknow nis -- 0x%x\n", nis); ++ break; ++ } ++#endif ++ switch(eis) ++ { ++ case SD_EIS_ACMD12_ERR: ++ printk("-- SD_EIS_ACMD12_ERR\n"); ++ break; ++ case SD_EIS_CURRENT_ERR: ++ printk("-- SD_EIS_CURRENT_ERR\n"); ++ break; ++ case SD_EIS_DATA_BIT_ERR: ++ printk("-- SD_EIS_DATA_BIT_ERR\n"); ++ break; ++ case SD_EIS_DATA_CRC_ERR: ++ printk("-- SD_EIS_DATA_CRC_ERR\n"); ++ break; ++ case SD_EIS_DATA_TMOUT_ERR: ++ printk("-- SD_EIS_DATA_TMOUT_ERR\n"); ++ break; ++ case SD_EIS_CMD_IDX_ERR: ++ printk("-- SD_EIS_CMD_IDX_ERR\n"); ++ break; ++ case SD_EIS_CMD_BIT_ERR: ++ printk("-- SD_EIS_CMD_BIT_ERR\n"); ++ break; ++ case SD_EIS_CMD_CRC_ERR: ++ printk("-- SD_EIS_CMD_CRC_ERR\n"); ++ break; ++ case SD_EIS_CMD_TMOUT_ERR: ++ //printk("-- SD_EIS_CMD_TMOUT_ERR\n"); ++ break; ++ default: ++ break; ++ } ++ ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ enabled = pslotinfo->plat_info->check_owner(); ++ if (enabled) ++ break; ++ } ++ ++ /* Clear interrupt */ ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_NIS_OFFSET, nis); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_EIS_OFFSET, eis); ++ if (enabled) { ++ //printk("-- %s nis = 0x%x, eis = 0x%x & [%s]\n", ++ //__func__, nis, eis, sd_state(pslotinfo->state)); ++ } else { ++ gk_sd_dbg(pslotinfo, "%s[false] nis = 0x%x, eis = 0x%x\n", ++ __func__, nis, eis); ++ if (eis) { ++ gk_sd_reset_all(pslotinfo->mmc); ++ } ++ goto gk_sd_irq_exit; ++ } ++ ++ if (nis & SD_NIS_CARD) { ++ //printk("SD_NIS_CARD -- mmc_signal_sdio_irq\n"); ++ mmc_signal_sdio_irq(pslotinfo->mmc); ++ } ++ ++ //if (!gk_is_valid_gpio_irq(&pslotinfo->plat_info->gpio_cd) && ++ // (pslotinfo->plat_info->fixed_cd == -1)) ++ { ++ if (nis & SD_NIS_REMOVAL) { ++ //printk("SD_NIS_REMOVAL -- mmc_detect_change\n"); ++ mmc_detect_change(pslotinfo->mmc, pslotinfo->plat_info->cd_delay); ++ } else if (nis & SD_NIS_INSERT) { ++ //printk("SD_NIS_INSERT -- mmc_detect_change\n"); ++ mmc_detect_change(pslotinfo->mmc, pslotinfo->plat_info->cd_delay); ++ } ++ } ++ ++ if (eis) { ++ if (eis & (SD_EIS_CMD_TMOUT_ERR | SD_EIS_CMD_CRC_ERR | ++ SD_EIS_CMD_BIT_ERR | SD_EIS_CMD_IDX_ERR | ++ SD_EIS_ACMD12_ERR)) { ++ gk_sd_reset_cmd_line(pslotinfo->mmc); ++ } ++ if (eis & (SD_EIS_DATA_TMOUT_ERR | SD_EIS_DATA_CRC_ERR)) { ++ gk_sd_reset_data_line(pslotinfo->mmc); ++ } ++ if (eis & (SD_EIS_DATA_BIT_ERR | SD_EIS_CURRENT_ERR)) { ++ gk_sd_reset_all(pslotinfo->mmc); ++ } ++ if (pslotinfo->state == GK_SD_STATE_CMD) { ++ gk_sd_cmd_done(pslotinfo, nis, eis); ++ } else if (pslotinfo->state == GK_SD_STATE_DATA) { ++ gk_sd_data_done(pslotinfo, nis, eis); ++ } ++ } else { ++ if (nis & SD_NIS_CMD_DONE) { ++ gk_sd_cmd_done(pslotinfo, nis, eis); ++ } ++ if (nis & SD_NIS_XFR_DONE) { ++ gk_sd_data_done(pslotinfo, nis, eis); ++ } ++#if 0 ++ if (nis & SD_NIS_DMA) { ++ gk_sd_writel((unsigned int)pinfo->regbase + SD_DMA_ADDR_OFFSET, ++ gk_sd_readl((unsigned int)pinfo->regbase + SD_DMA_ADDR_OFFSET)); ++ } ++#endif ++ } ++ ++gk_sd_irq_exit: ++ //printk("-----------handle irq end-------------\n"); ++ return IRQ_HANDLED; ++} ++ ++static int gk_sd_gpio_cd_check_val(struct gk_sd_mmc_info *pslotinfo) ++{ ++ u32 val = -1; ++ ++ gk_gpio_config(pslotinfo->plat_info->gpio_cd.irq_gpio, GPIO_TYPE_INPUT_0); ++ val = gk_gpio_get(pslotinfo->plat_info->gpio_cd.irq_gpio); ++ ++ gk_gpio_config(pslotinfo->plat_info->gpio_cd.irq_gpio, pslotinfo->plat_info->gpio_cd.irq_gpio_mode); ++ val = (val == pslotinfo->plat_info->gpio_cd.irq_gpio_val) ? 1 : 0; ++ ++ gk_sd_dbg(pslotinfo, "%s:%u\n", (val == 1) ? ++ "card insert" : "card eject", ++ pslotinfo->plat_info->cd_delay); ++ ++ pslotinfo->plat_info->fixed_cd = val; ++ ++ return val; ++} ++ ++static irqreturn_t gk_sd_gpio_cd_irq(int irq, void *devid) ++{ ++ struct gk_sd_mmc_info *pslotinfo; ++ ++ pslotinfo = (struct gk_sd_mmc_info *)devid; ++ if (pslotinfo->valid && ++ (gk_sd_gpio_cd_check_val(pslotinfo) != -1)) { ++ mmc_detect_change(pslotinfo->mmc, ++ pslotinfo->plat_info->cd_delay); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void gk_sd_set_clk(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u16 clk_div = 0x0000; ++ u32 sd_clk; ++ u32 desired_clk; ++ u32 actual_clk; ++ u32 bneed_div = 1; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ gk_sd_clear_clken(mmc); ++ if (ios->clock == 0) { ++ pinfo->pcontroller->active_clock = 0; ++ } else { ++ desired_clk = ios->clock; ++ if (desired_clk > pinfo->clk_limit) ++ desired_clk = pinfo->clk_limit; ++ ++ if (pinfo->pcontroller->support_pll_scaler) { ++ if (desired_clk < 10000000) { ++ /* Below 10Mhz, divide by sd controller */ ++ pinfo->pcontroller->set_pll(pinfo->clk_limit); ++ } else { ++ pinfo->pcontroller->set_pll(desired_clk); ++ actual_clk = pinfo->pcontroller->get_pll(); ++ bneed_div = 0; ++ } ++ } ++ ++ if (bneed_div) { ++ sd_clk = pinfo->pcontroller->get_pll(); ++ for (clk_div = 0x0; clk_div <= 0x80;) { ++ if (clk_div == 0) ++ actual_clk = sd_clk; ++ else ++ actual_clk = sd_clk / (clk_div << 1); ++ ++ if (actual_clk <= desired_clk) ++ break; ++ ++ if (clk_div >= 0x80) ++ break; ++ ++ if (clk_div == 0x0) ++ clk_div = 0x1; ++ else ++ clk_div <<= 1; ++ } ++ } ++ //printk("sd_pll = %u.\n",pinfo->pcontroller->get_pll()); ++ //printk("desired_clk = %u.\n", desired_clk); ++ //printk("actual_clk = %u.\n", actual_clk); ++ //printk("clk_div = %u.\n", clk_div); ++ pinfo->pcontroller->active_clock = actual_clk; ++ gk_sd_set_iclk(mmc, clk_div); ++ gk_sd_set_clken(mmc); ++ } ++} ++ ++static void gk_sd_set_pwr(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ //printk("gk_sd_set_pwr ....\n"); ++ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ if (ios->power_mode == MMC_POWER_OFF) { ++ //printk("power off\n"); ++ gk_sd_reset_all(pslotinfo->mmc); ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_PWR_OFFSET, SD_PWR_OFF); ++ //gk_set_gpio_output_can_sleep( ++ // &pslotinfo->plat_info->ext_reset, 1, 1); ++ //gk_set_gpio_output_can_sleep( ++ // &pslotinfo->plat_info->ext_power, 0, 1); ++ if (pslotinfo->plat_info->set_vdd) { ++ pslotinfo->plat_info->set_vdd(0); ++ } ++ } else if (ios->power_mode == MMC_POWER_UP) { ++ if (pslotinfo->plat_info->set_vdd) { ++ pslotinfo->plat_info->set_vdd(3300); ++ } ++ //printk("power up...\n"); ++ //gk_set_gpio_output_can_sleep( ++ // &pslotinfo->plat_info->ext_power, 1, 1); ++ //gk_set_gpio_output_can_sleep( ++ // &pslotinfo->plat_info->ext_reset, 0, 1); ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_PWR_OFFSET, ++ (SD_PWR_ON | SD_PWR_3_3V)); ++ } else if (ios->power_mode == MMC_POWER_ON) { ++ //printk("power on...\n"); ++ switch (1 << ios->vdd) { ++ case MMC_VDD_32_33: ++ case MMC_VDD_33_34: ++ break; ++ default: ++ gk_sd_err(pslotinfo, "%s Wrong voltage[%u]!\n", ++ __func__, ios->vdd); ++ break; ++ } ++ } ++ msleep(pinfo->pcontroller->pwr_delay); ++ gk_sd_dbg(pslotinfo, "pwr = 0x%x.\n", ++ gk_sd_readb((unsigned int)pinfo->regbase + SD_PWR_OFFSET)); ++ ++} ++ ++static void gk_sd_set_bus(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u8 hostr = 0; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ hostr = gk_sd_readb((unsigned int)pinfo->regbase + SD_HOST_OFFSET); ++ if (ios->bus_width == MMC_BUS_WIDTH_8) { ++ hostr |= SD_HOST_8BIT; ++ hostr &= ~(SD_HOST_4BIT); ++ } else if (ios->bus_width == MMC_BUS_WIDTH_4) { ++ hostr &= ~(SD_HOST_8BIT); ++ hostr |= SD_HOST_4BIT; ++ } else if (ios->bus_width == MMC_BUS_WIDTH_1) { ++ hostr &= ~(SD_HOST_8BIT); ++ hostr &= ~(SD_HOST_4BIT); ++ } else { ++ gk_sd_err(pslotinfo, "Unknown bus_width[%u], assume 1bit.\n", ++ ios->bus_width); ++ hostr &= ~(SD_HOST_8BIT); ++ hostr &= ~(SD_HOST_4BIT); ++ } ++ // Steven Yu: ++ // do not set this bit, would cause xc card rw failed. ++ hostr &= ~SD_HOST_HIGH_SPEED; ++ //hostr |= SD_HOST_HIGH_SPEED; ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_HOST_OFFSET, hostr); ++ ++ gk_sd_dbg(pslotinfo, "hostr = 0x%x.\n", hostr); ++} ++ ++static void gk_sd_check_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ if ((pinfo->controller_ios.power_mode != ios->power_mode) || ++ (pinfo->controller_ios.vdd != ios->vdd) || ++ (pslotinfo->state == GK_SD_STATE_RESET)) { ++ gk_sd_set_pwr(mmc, ios); ++ pinfo->controller_ios.power_mode = ios->power_mode; ++ pinfo->controller_ios.vdd = ios->vdd; ++ } ++ ++ if ((pinfo->controller_ios.clock != ios->clock) || ++ (pslotinfo->state == GK_SD_STATE_RESET)) { ++ gk_sd_set_clk(mmc, ios); ++ pinfo->controller_ios.clock = ios->clock; ++ } ++ ++ if ((pinfo->controller_ios.bus_width != ios->bus_width) || ++ (pinfo->controller_ios.timing != ios->timing) || ++ //(pinfo->controller_ios.ddr != ios->ddr) || ++ (pslotinfo->state == GK_SD_STATE_RESET)) { ++ gk_sd_set_bus(mmc, ios); ++ pinfo->controller_ios.bus_width = ios->bus_width; ++ pinfo->controller_ios.timing = ios->timing; ++ //pinfo->controller_ios.ddr = ios->ddr; ++ } ++ ++ if (pslotinfo->state == GK_SD_STATE_RESET) { ++ pslotinfo->state = GK_SD_STATE_IDLE; ++ } ++} ++ ++static u32 gk_sd_check_cd(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ int cdpin; ++ u32 valid_cd = 0; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ if (pslotinfo->plat_info->fixed_cd == 1) { ++ valid_cd = 1; ++ } else if (pslotinfo->plat_info->fixed_cd == 0) { ++ valid_cd = 0; ++ } else { ++ ++ printk("gk_sd_check_cd\n"); ++ cdpin = gk_sd_gpio_cd_check_val(pslotinfo); ++ if (cdpin == 1) { ++ valid_cd = 1; ++ } else if (cdpin == -1) { ++ if (gk_sd_tstbitsl((unsigned int)pinfo->regbase + SD_STA_OFFSET, ++ SD_STA_CARD_INSERTED)) { ++ valid_cd = 1; ++ } ++ } ++ } ++ ++ return valid_cd; ++} ++ ++static inline void gk_sd_prepare_tmo( ++ struct gk_sd_mmc_info *pslotinfo, ++ struct mmc_data *pmmcdata) ++{ ++ struct gk_sd_controller_info *pinfo; ++#if defined(CONFIG_SD_GK_CALIB_TMO) ++ u32 actual_cycle_ns; ++ u32 desired_tmo; ++ u32 actual_tmo; ++ u32 actual_hz; ++#endif ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++#if defined(CONFIG_SD_GK_CALIB_TMO) ++ if (pinfo->pcontroller->active_clock >= HZ) { ++ actual_hz = pinfo->pcontroller->active_clock / HZ; ++ actual_cycle_ns = ((1000000000 / HZ) / actual_hz); ++ desired_tmo = pmmcdata->timeout_ns / actual_cycle_ns; ++ desired_tmo += pmmcdata->timeout_clks; ++ for (pslotinfo->tmo = 0; pslotinfo->tmo < 0xe; ++ pslotinfo->tmo++) { ++ actual_tmo = (0x1 << (13 + pslotinfo->tmo)); ++ if (actual_tmo >= desired_tmo) ++ break; ++ } ++ pslotinfo->wait_tmo = (actual_tmo + actual_hz - 1); ++ pslotinfo->wait_tmo /= actual_hz; ++ } else { ++ pslotinfo->tmo = CONFIG_SD_GK_TIMEOUT_VAL; ++ pslotinfo->wait_tmo = pinfo->pcontroller->wait_tmo; ++ } ++ if ((pslotinfo->wait_tmo > 0) && (pslotinfo->wait_tmo < ++ CONFIG_SD_GK_MAX_TIMEOUT)) { ++ pslotinfo->sta_counter = CONFIG_SD_GK_MAX_TIMEOUT; ++ pslotinfo->sta_counter /= pslotinfo->wait_tmo; ++ } else { ++ pslotinfo->sta_counter = 1; ++ pslotinfo->wait_tmo = (1 * HZ); ++ } ++#else ++ pslotinfo->tmo = CONFIG_SD_GK_TIMEOUT_VAL; ++ pslotinfo->wait_tmo = pinfo->pcontroller->wait_tmo; ++ if ((pslotinfo->wait_tmo > 0) && (pslotinfo->wait_tmo < ++ CONFIG_SD_GK_MAX_TIMEOUT)) { ++ pslotinfo->sta_counter = CONFIG_SD_GK_MAX_TIMEOUT; ++ pslotinfo->sta_counter /= pslotinfo->wait_tmo; ++ } else { ++ pslotinfo->sta_counter = 1; ++ pslotinfo->wait_tmo = (1 * HZ); ++ } ++#endif ++ gk_sd_dbg(pslotinfo, "timeout_ns = %u, timeout_clks = %u @ %uHz, " ++ "wait_tmo = %u, tmo = %u, sta_counter = %u.\n", ++ pmmcdata->timeout_ns, pmmcdata->timeout_clks, ++ pinfo->pcontroller->active_clock, pslotinfo->wait_tmo, ++ pslotinfo->tmo, pslotinfo->sta_counter); ++} ++ ++static inline void gk_sd_pre_cmd( ++ struct gk_sd_mmc_info *pslotinfo) ++{ ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ pslotinfo->state = GK_SD_STATE_CMD; ++ pslotinfo->sg_len = 0; ++ pslotinfo->sg = NULL; ++ pslotinfo->blk_sz = 0; ++ pslotinfo->blk_cnt = 0; ++ pslotinfo->arg_reg = 0; ++ pslotinfo->cmd_reg = 0; ++ pslotinfo->sta_reg = 0; ++ pslotinfo->tmo = CONFIG_SD_GK_TIMEOUT_VAL; ++ pslotinfo->wait_tmo = (1 * HZ); ++ pslotinfo->xfr_reg = 0; ++ pslotinfo->dma_address = 0; ++ pslotinfo->dma_size = 0; ++ ++ if (pslotinfo->mrq->stop) { ++ //if (likely(pslotinfo->mrq->stop->opcode == MMC_STOP_TRANSMISSION)) { ++ if ((pslotinfo->mrq->stop->opcode == MMC_STOP_TRANSMISSION)) { ++ pslotinfo->xfr_reg = SD_XFR_AC12_EN; ++ } else { ++ gk_sd_err(pslotinfo, "%s strange stop cmd%u\n", ++ __func__, pslotinfo->mrq->stop->opcode); ++ } ++ } ++ ++ if (!(pslotinfo->mrq->cmd->flags & MMC_RSP_PRESENT)) ++ pslotinfo->cmd_reg = SD_CMD_RSP_NONE; ++ else if (pslotinfo->mrq->cmd->flags & MMC_RSP_136) ++ pslotinfo->cmd_reg = SD_CMD_RSP_136; ++ else if (pslotinfo->mrq->cmd->flags & MMC_RSP_BUSY) ++ pslotinfo->cmd_reg = SD_CMD_RSP_48BUSY; ++ else ++ pslotinfo->cmd_reg = SD_CMD_RSP_48; ++ if (pslotinfo->mrq->cmd->flags & MMC_RSP_CRC) ++ { ++ //printk("add crc check...\n"); ++ pslotinfo->cmd_reg |= SD_CMD_CHKCRC; ++ } ++ ++ if (pslotinfo->mrq->cmd->flags & MMC_RSP_OPCODE) ++ pslotinfo->cmd_reg |= SD_CMD_CHKIDX; ++ ++ //printk("## cmd = %d ##\n", pslotinfo->mrq->cmd->opcode); ++ pslotinfo->cmd_reg |= SD_CMD_IDX(pslotinfo->mrq->cmd->opcode); ++ pslotinfo->arg_reg = pslotinfo->mrq->cmd->arg; ++ ++//printk(" cmd_reg = 0x%x arg_reg = 0x%x \n", pslotinfo->cmd_reg, pslotinfo->arg_reg); ++ ++ if (pslotinfo->mrq->data) { ++ pslotinfo->state = GK_SD_STATE_DATA; ++ gk_sd_prepare_tmo(pslotinfo, pslotinfo->mrq->data); ++ pslotinfo->blk_sz = (pslotinfo->mrq->data->blksz & 0xFFF); ++ pslotinfo->dma_size = pslotinfo->mrq->data->blksz * pslotinfo->mrq->data->blocks; ++ //printk("blk size = %d dma_size = %d \n", pslotinfo->blk_sz, pslotinfo->dma_size); ++ ++ pslotinfo->sg_len = pslotinfo->mrq->data->sg_len; ++ pslotinfo->sg = pslotinfo->mrq->data->sg; ++ pslotinfo->xfr_reg |= SD_XFR_DMA_EN; ++ pslotinfo->cmd_reg |= SD_CMD_DATA; ++ pslotinfo->blk_cnt = pslotinfo->mrq->data->blocks; ++ if (pslotinfo->blk_cnt > 1) { ++ pslotinfo->xfr_reg |= SD_XFR_MUL_SEL; ++ pslotinfo->xfr_reg |= SD_XFR_BLKCNT_EN; ++ } ++ if (pslotinfo->mrq->data->flags & MMC_DATA_STREAM) { ++ pslotinfo->xfr_reg |= SD_XFR_MUL_SEL; ++ pslotinfo->xfr_reg &= ~SD_XFR_BLKCNT_EN; ++ } ++ if (pslotinfo->mrq->data->flags & MMC_DATA_WRITE) { ++ pslotinfo->xfr_reg &= ~SD_XFR_CTH_SEL; ++ pslotinfo->sta_reg = (SD_STA_WRITE_XFR_ACTIVE | ++ SD_STA_DAT_ACTIVE); ++ pslotinfo->pre_dma = &gk_sd_pre_sg_to_dma; ++ pslotinfo->post_dma = &gk_sd_post_sg_to_dma; ++ } else { ++ pslotinfo->xfr_reg |= SD_XFR_CTH_SEL; ++ pslotinfo->sta_reg = (SD_STA_READ_XFR_ACTIVE | ++ SD_STA_DAT_ACTIVE); ++ pslotinfo->pre_dma = &gk_sd_pre_dma_to_sg; ++ pslotinfo->post_dma = &gk_sd_post_dma_to_sg; ++ } ++ //printk("-----pre dma handle----\n"); ++ pslotinfo->pre_dma(pslotinfo); ++ if (pinfo->dma_fix) { ++ pslotinfo->dma_address |= pinfo->dma_fix; ++ } ++ } ++} ++ ++static inline void gk_sd_send_cmd( ++ struct gk_sd_mmc_info *pslotinfo) ++{ ++ struct gk_sd_controller_info *pinfo; ++ u32 valid_request = 0; ++ u32 counter = 0; ++ u32 sta_reg; ++ u32 tmpreg; ++ long timeout; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ gk_sd_request_bus(pslotinfo->mmc); ++ ++ valid_request = gk_sd_check_cd(pslotinfo->mmc); ++ //printk("send cmd = %u valid_request = %u.\n", pslotinfo->mrq->cmd->opcode, valid_request); ++ ++ if (!valid_request) { ++ pslotinfo->mrq->cmd->error = -ENOMEDIUM; ++ pslotinfo->state = GK_SD_STATE_ERR; ++ //printk("send cmd error...\n"); ++ goto gk_sd_send_cmd_exit; ++ } ++ ++ gk_sd_check_ios(pslotinfo->mmc, &pslotinfo->mmc->ios); ++ if (pslotinfo->mrq->data) { ++ while (1) { ++ sta_reg = gk_sd_readl((unsigned int)pinfo->regbase + SD_STA_OFFSET); ++ if ((sta_reg & SD_STA_CMD_INHIBIT_DAT) == 0) { ++ break; ++ } ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ printk( ++ "Wait SD_STA_CMD_INHIBIT_DAT...\n"); ++ pslotinfo->state = GK_SD_STATE_ERR; ++ pinfo->reset_error = 1; ++ goto gk_sd_send_cmd_exit; ++ } ++ } ++ //printk("@@ write cmd arg...\n"); ++ gk_sd_writeb((unsigned int)pinfo->regbase + SD_TMO_OFFSET, pslotinfo->tmo); ++ gk_sd_writel((unsigned int)pinfo->regbase + SD_DMA_ADDR_OFFSET, ++ pslotinfo->dma_address); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_BLK_SZ_OFFSET, ++ pslotinfo->blk_sz); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_BLK_CNT_OFFSET, ++ pslotinfo->blk_cnt); ++ gk_sd_writel((unsigned int)pinfo->regbase + SD_ARG_OFFSET, pslotinfo->arg_reg); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_XFR_OFFSET, ++ pslotinfo->xfr_reg); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CMD_OFFSET, ++ pslotinfo->cmd_reg); ++ } else { ++ while (1) { ++ sta_reg = gk_sd_readl((unsigned int)pinfo->regbase + SD_STA_OFFSET); ++ if ((sta_reg & SD_STA_CMD_INHIBIT_CMD) == 0) { ++ break; ++ } ++ counter++; ++ if (counter > CONFIG_SD_GK_WAIT_COUNTER_LIMIT) { ++ gk_sd_warn(pslotinfo, ++ "Wait SD_STA_CMD_INHIBIT_CMD...\n"); ++ pslotinfo->state = GK_SD_STATE_ERR; ++ pinfo->reset_error = 1; ++ goto gk_sd_send_cmd_exit; ++ } ++ } ++ ++ gk_sd_writel((unsigned int)pinfo->regbase + SD_ARG_OFFSET, pslotinfo->arg_reg); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_XFR_OFFSET, ++ 0x00); ++ gk_sd_writew((unsigned int)pinfo->regbase + SD_CMD_OFFSET, ++ pslotinfo->cmd_reg); ++ } ++ ++gk_sd_send_cmd_exit: ++ if (pslotinfo->state == GK_SD_STATE_CMD) { ++ timeout = wait_event_timeout(pslotinfo->wait, ++ (pslotinfo->state != GK_SD_STATE_CMD), ++ pslotinfo->wait_tmo); ++ if (pslotinfo->state == GK_SD_STATE_CMD) { ++ printk("@cmd%u %u@[%ld:%u], sta=0x%04x\n", ++ pslotinfo->mrq->cmd->opcode, ++ pslotinfo->state, timeout, pslotinfo->wait_tmo, ++ gk_sd_readl((unsigned int)pinfo->regbase + SD_STA_OFFSET)); ++ pslotinfo->mrq->cmd->error = -ETIMEDOUT; ++ } ++ } else if (pslotinfo->state == GK_SD_STATE_DATA) { ++ do { ++ timeout = wait_event_timeout(pslotinfo->wait, ++ (pslotinfo->state != GK_SD_STATE_DATA), ++ pslotinfo->wait_tmo); ++ sta_reg = gk_sd_readl((unsigned int)pinfo->regbase + SD_STA_OFFSET); ++ if ((pslotinfo->state == GK_SD_STATE_DATA) && ++ (sta_reg & pslotinfo->sta_reg)) { ++ printk("#data%u %u@[%ld:%u:%u:%u], sta=0x%04x:0x%04x\n", ++ pslotinfo->mrq->cmd->opcode, ++ pslotinfo->state, timeout, ++ pslotinfo->wait_tmo, ++ pslotinfo->mrq->data->timeout_ns, ++ pslotinfo->mrq->data->timeout_clks, ++ sta_reg, pslotinfo->sta_reg); ++ printk("#DMA %u in %u sg [0x%08x:0x%08x]\n", ++ pslotinfo->dma_size, ++ pslotinfo->sg_len, ++ pslotinfo->dma_address, ++ pslotinfo->dma_size); ++ tmpreg = gk_sd_readw((unsigned int)pinfo->regbase + ++ SD_BLK_CNT_OFFSET); ++ if (tmpreg) { ++ gk_sd_rtdbg(pslotinfo, ++ "SD_DMA_ADDR_OFFSET[0x%08X]\n", ++ gk_sd_readl((unsigned int)pinfo->regbase + ++ SD_DMA_ADDR_OFFSET)); ++ gk_sd_writel(((unsigned int)pinfo->regbase + ++ SD_DMA_ADDR_OFFSET), ++ gk_sd_readl((unsigned int)pinfo->regbase + ++ SD_DMA_ADDR_OFFSET)); ++ } else { ++ gk_sd_rtdbg(pslotinfo, ++ "SD_DATA_OFFSET[0x%08X]\n", ++ gk_sd_readl((unsigned int)pinfo->regbase + ++ SD_DATA_OFFSET)); ++ gk_sd_rtdbg(pslotinfo, ++ "SD_STA_OFFSET[0x%08X]\n", ++ gk_sd_readl((unsigned int)pinfo->regbase + ++ SD_STA_OFFSET)); ++ } ++ } else { ++ break; ++ } ++ } while (pslotinfo->sta_counter--); ++ if (pslotinfo->state == GK_SD_STATE_DATA) { ++ printk( ++ "#data%u %u@%u, sta=0x%04x:0x%04x\n", ++ pslotinfo->mrq->cmd->opcode, ++ pslotinfo->state, ++ pslotinfo->wait_tmo, ++ sta_reg, pslotinfo->sta_reg); ++ pslotinfo->mrq->data->error = -ETIMEDOUT; ++ } ++ } ++} ++ ++static inline void gk_sd_post_cmd( ++ struct gk_sd_mmc_info *pslotinfo) ++{ ++ struct gk_sd_controller_info *pinfo; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ if (pslotinfo->state == GK_SD_STATE_IDLE) { ++ gk_sd_release_bus(pslotinfo->mmc); ++ if (pslotinfo->mrq->data) { ++ pslotinfo->post_dma(pslotinfo); ++ } ++ } else { ++#ifdef CONFIG_SD_GK_DEBUG_VERBOSE ++ u32 counter = 0; ++ ++ gk_sd_err(pslotinfo, "CMD%u retries[%u] state[%u].\n", ++ pslotinfo->mrq->cmd->opcode, ++ pslotinfo->mrq->cmd->retries, ++ pslotinfo->state); ++ for (counter = 0; counter < 0x100; counter += 4) { ++ gk_sd_err(pslotinfo, "0x%04x: 0x%08x\n", ++ counter, gk_sd_readl((unsigned int)pinfo->regbase + counter)); ++ } ++ gk_sd_show_info(pslotinfo); ++#endif ++ if (pinfo->reset_error) { ++ gk_sd_reset_all(pslotinfo->mmc); ++ } ++ gk_sd_release_bus(pslotinfo->mmc); ++ } ++} ++ ++static void gk_sd_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ ++ //if(pslotinfo->mrq && pslotinfo->mrq->cmd) ++ // printk("- %s: CMD[%u] \n", __func__, pslotinfo->mrq->cmd->opcode); ++ //printk("\n"); ++ pslotinfo->mrq = mrq; ++ //if(mrq && mrq->cmd) printk("######### mmc cmd request: CMD[%u] \n", mrq->cmd->opcode); ++ //if(mrq && mrq->data) printk("######### mmc data request: blksz=%d blocks=%d\n", mrq->data->blksz, mrq->data->blocks); ++ //if(mrq && mrq->stop) printk("######### mmc stop request: CMD[%u] \n", mrq->stop->opcode); ++ ++ gk_sd_pre_cmd(pslotinfo); ++ gk_sd_send_cmd(pslotinfo); ++ gk_sd_post_cmd(pslotinfo); ++ ++ pslotinfo->mrq = NULL; ++ mmc_request_done(mmc, mrq); ++ //printk("######### mmc request done-\n"); ++} ++ ++static void gk_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ gk_sd_request_bus(mmc); ++ gk_sd_check_ios(mmc, ios); ++ gk_sd_release_bus(mmc); ++} ++ ++static int gk_sd_get_ro(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ struct gk_sd_controller_info *pinfo; ++ u32 wpspl; ++ ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ gk_sd_request_bus(mmc); ++ ++ if (pslotinfo->plat_info->fixed_wp < 0) { ++ if (pslotinfo->plat_info->gpio_wp.gpio_id != -1) { ++ wpspl = gk_get_gpio_input(&pslotinfo->plat_info->gpio_wp); ++ } else { ++ wpspl = gk_sd_readl((unsigned int)pinfo->regbase + SD_STA_OFFSET); ++ wpspl &= SD_STA_WPS_PL; //1 read only, 0 write ++ } ++ } else { ++ wpspl = pslotinfo->plat_info->fixed_wp; ++ } ++ ++ gk_sd_release_bus(mmc); ++ ++ gk_sd_dbg(pslotinfo, "RO[0x%x].\n", wpspl); ++ ++ return wpspl ? SD_STA_READ_ONLY : SD_STA_WRITABLE; ++} ++ ++static int gk_sd_get_cd(struct mmc_host *mmc) ++{ ++ struct gk_sd_mmc_info *pslotinfo = mmc_priv(mmc); ++ u32 cdpin; ++ ++ gk_sd_request_bus(mmc); ++ cdpin = gk_sd_check_cd(mmc); ++ gk_sd_release_bus(mmc); ++ ++ gk_sd_dbg(pslotinfo, "CD[%u].\n", cdpin); ++ return cdpin ? 1 : 0; ++} ++ ++static void gk_sd_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ if (enable) ++ gk_sd_enable_int(mmc, SD_NISEN_CARD); ++ else ++ gk_sd_disable_int(mmc, SD_NISEN_CARD); ++} ++ ++static const struct mmc_host_ops gk_sd_host_ops = { ++ .request = gk_sd_request, ++ .set_ios = gk_sd_ios, ++ .get_ro = gk_sd_get_ro, ++ .get_cd = gk_sd_get_cd, ++ .enable_sdio_irq = gk_sd_enable_sdio_irq, ++}; ++ ++static int gk_sd_system_event(struct notifier_block *nb, ++ unsigned long val, void *data) ++{ ++ int retval = NOTIFY_OK; ++ struct gk_sd_mmc_info *pslotinfo; ++ struct gk_sd_controller_info *pinfo; ++ ++ pslotinfo = container_of(nb, struct gk_sd_mmc_info, ++ system_event); ++ pinfo = (struct gk_sd_controller_info *)pslotinfo->pinfo; ++ ++ switch (val) { ++ case GK_EVENT_PRE_CPUFREQ: ++ pr_debug("%s[%u]: Pre Change\n", __func__, pslotinfo->slot_id); ++ down(&pslotinfo->system_event_sem); ++ break; ++ ++ case GK_EVENT_POST_CPUFREQ: ++ pr_debug("%s[%u]: Post Change\n", __func__, pslotinfo->slot_id); ++ gk_sd_set_clk(pslotinfo->mmc, &pinfo->controller_ios); ++ up(&pslotinfo->system_event_sem); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return retval; ++} ++ ++/* ==========================================================================*/ ++static int __devinit gk_sd_probe(struct platform_device *pdev) ++{ ++ int retval = 0; ++ struct gk_sd_controller_info *pinfo; ++ struct gk_sd_mmc_info *pslotinfo = NULL; ++ struct resource *irq; ++ struct resource *mem; ++ struct mmc_host *mmc; ++ u32 hc_cap = 0; ++ u32 i; ++ u32 clock_min; ++ u32 hc_timeout_clk = 0; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (mem == NULL) { ++ dev_err(&pdev->dev, "Get SD/MMC mem resource failed!\n"); ++ retval = -ENXIO; ++ goto gk_sd_probe_na; ++ } ++ ++ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (irq == NULL) { ++ dev_err(&pdev->dev, "Get SD/MMC irq resource failed!\n"); ++ retval = -ENXIO; ++ goto gk_sd_probe_na; ++ } ++ dev_dbg(&pdev->dev, "sdio get irq: %d \n", irq->start); ++ ++ pinfo = kzalloc(sizeof(struct gk_sd_controller_info), ++ GFP_KERNEL); ++ if (pinfo == NULL) { ++ dev_err(&pdev->dev, "Out of memory!\n"); ++ retval = -ENOMEM; ++ goto gk_sd_probe_na; ++ } ++ pinfo->regbase = (unsigned char __iomem *)mem->start; ++ //printk("regbase = 0x%x \n", pinfo->regbase); ++ pinfo->dev = &pdev->dev; ++ pinfo->irq = irq->start; ++ pinfo->pcontroller = (struct gk_sd_controller *)pdev->dev.platform_data; ++ if ((pinfo->pcontroller == NULL) || ++ (pinfo->pcontroller->get_pll == NULL) || ++ (pinfo->pcontroller->set_pll == NULL)) { ++ dev_err(&pdev->dev, "Need SD/MMC controller info!\n"); ++ retval = -EPERM; ++ goto gk_sd_probe_free_pinfo; ++ } ++ ++ pinfo->dma_fix = pinfo->pcontroller->dma_fix; ++ if (pinfo->pcontroller->wait_tmo < CONFIG_SD_GK_WAIT_TIMEOUT) { ++ dev_notice(&pdev->dev, "Change wait timeout from %u to %u.\n", ++ pinfo->pcontroller->wait_tmo, ++ CONFIG_SD_GK_WAIT_TIMEOUT); ++ pinfo->pcontroller->wait_tmo = ++ CONFIG_SD_GK_WAIT_TIMEOUT; ++ } ++ ++ pinfo->pcontroller->set_pll(pinfo->pcontroller->max_clock ? ++ pinfo->pcontroller->max_clock : ++ CONFIG_SD_GK_DEFAULT_CLOCK); ++ ++ pinfo->clk_limit = pinfo->pcontroller->get_pll(); ++ clock_min = pinfo->clk_limit >> 8; ++ if (pinfo->clk_limit < clock_min) { ++ pinfo->clk_limit = clock_min; ++ dev_err(&pdev->dev, "Wrong clk_limit %uHz vs %uHz!\n", ++ pinfo->clk_limit, clock_min); ++ retval = -EPERM; ++ goto gk_sd_probe_free_pinfo; ++ } ++ if (pinfo->pcontroller->max_clock != pinfo->clk_limit) { ++ pinfo->pcontroller->max_clock = pinfo->clk_limit; ++ } ++ pinfo->max_blk_sz = gk_sd_dma_mask_to_size( ++ pinfo->pcontroller->max_blk_mask); ++ pinfo->buf_cache = kmem_cache_create(dev_name(&pdev->dev), ++ pinfo->max_blk_sz, pinfo->max_blk_sz, 0, NULL); ++ if (!pinfo->buf_cache) { ++ dev_err(&pdev->dev, "Can't alloc DMA Cache"); ++ retval = -ENOMEM; ++ goto gk_sd_probe_free_pinfo; ++ } ++ ++ dev_dbg(&pdev->dev, "## max blk sz = %d \n", pinfo->max_blk_sz); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ mmc = mmc_alloc_host(sizeof(struct gk_sd_mmc_info), &pdev->dev); ++ if (!mmc) { ++ dev_err(&pdev->dev, "Failed to allocate mmc host" ++ " for slot%u!\n", i); ++ retval = -ENOMEM; ++ goto gk_sd_probe_free_host; ++ } ++ dev_dbg(&pdev->dev, "mmc_alloc_host ok...\n"); ++ mmc->ops = &gk_sd_host_ops; ++ ++ pinfo->pslotinfo[i] = pslotinfo = mmc_priv(mmc); ++ pslotinfo->mmc = mmc; ++ init_waitqueue_head(&pslotinfo->wait); ++ pslotinfo->state = GK_SD_STATE_ERR; ++ pslotinfo->plat_info = &(pinfo->pcontroller->slot[i]); ++ if ((pslotinfo->plat_info == NULL) || ++ (pslotinfo->plat_info->check_owner == NULL) || ++ (pslotinfo->plat_info->set_int == NULL)) { ++ dev_err(&pdev->dev, "Need SD/MMC slot info!\n"); ++ retval = -EPERM; ++ goto gk_sd_probe_free_host; ++ } ++ pslotinfo->slot_id = i; ++ pslotinfo->pinfo = pinfo; ++ sema_init(&pslotinfo->system_event_sem, 1); ++ ++ gk_sd_request_bus(mmc); ++ ++ gk_sd_reset_all(mmc); ++ //GD_SDIO_Rest(); ++ ++ hc_cap = gk_sd_readl((unsigned int)pinfo->regbase + SD_CAP_OFFSET); ++ hc_timeout_clk = SD_CAP_TOCLK_FREQ(hc_cap); ++ if (hc_cap & SD_CAP_TOCLK_MHZ) { ++ hc_timeout_clk *= 1000; ++ } ++ dev_dbg(&pdev->dev, "## Timeout Clock Frequency: %uKHz.\n", hc_timeout_clk); ++ ++ mmc->f_min = clock_min; ++ mmc->f_max = pinfo->clk_limit; ++ dev_dbg(&pdev->dev, "## SD Clock: base[%uMHz], min[%uHz], max[%uHz].\n", ++ SD_CAP_BASE_FREQ(hc_cap), ++ mmc->f_min, ++ mmc->f_max); ++ ++ if (hc_cap & SD_CAP_MAX_2KB_BLK) ++ mmc->max_blk_size = 2048; ++ else if (hc_cap & SD_CAP_MAX_1KB_BLK) ++ mmc->max_blk_size = 1024; ++ else if (hc_cap & SD_CAP_MAX_512B_BLK) ++ mmc->max_blk_size = 512; ++ ++ //mmc->max_blk_size = 512; ++ dev_dbg(&pdev->dev, "## SD max_blk_size: %u.\n", mmc->max_blk_size); ++ ++ mmc->caps = pslotinfo->plat_info->default_caps; ++ if (pinfo->clk_limit > 25000000) { ++ mmc->caps |= MMC_CAP_SD_HIGHSPEED; ++ mmc->caps |= MMC_CAP_MMC_HIGHSPEED; ++ } ++ if (hc_cap & SD_CAP_DMA) { ++ dev_dbg(&pdev->dev, "HW support DMA!\n"); ++ } else { ++ dev_dbg(&pdev->dev, "HW do not support DMA!\n"); ++ retval = -ENODEV; ++ goto gk_sd_probe_free_host; ++ } ++ if (hc_cap & SD_CAP_SUS_RES) { ++ dev_dbg(&pdev->dev, "HW support Suspend/Resume!\n"); ++ } else { ++ dev_dbg(&pdev->dev, "HW do not support Suspend/Resume!\n"); ++ } ++ ++ mmc->ocr_avail = 0; ++ if (hc_cap & SD_CAP_VOL_3_3V) { ++ mmc->ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; ++ } ++ if (mmc->ocr_avail == 0) { ++ dev_dbg(&pdev->dev, "Hardware report wrong voltages[0x%x].!\n", ++ hc_cap); ++ retval = -ENODEV; ++ goto gk_sd_probe_free_host; ++ } ++ ++ if (hc_cap & SD_CAP_INTMODE) { ++ dev_dbg(&pdev->dev, "HW support Interrupt mode!\n"); ++ } else { ++ dev_dbg(&pdev->dev, "HW do not support Interrupt mode!\n"); ++ retval = -ENODEV; ++ goto gk_sd_probe_free_host; ++ } ++ ++ mmc->max_blk_count = 0xFFFF; ++ mmc->max_seg_size = pinfo->max_blk_sz; ++ mmc->max_segs = mmc->max_seg_size / PAGE_SIZE; ++ mmc->max_req_size = min(mmc->max_seg_size, mmc->max_blk_size * mmc->max_blk_count); ++ dev_dbg(&pdev->dev, "## max req size = %d \n", mmc->max_req_size); ++ pslotinfo->buf_vaddress = kmem_cache_alloc(pinfo->buf_cache, GFP_KERNEL); ++ if (!pslotinfo->buf_vaddress) { ++ gk_sd_err(pslotinfo, "Can't alloc DMA memory"); ++ retval = -ENOMEM; ++ goto gk_sd_probe_free_host; ++ } ++ pslotinfo->buf_paddress = dma_map_single( ++ pinfo->dev, pslotinfo->buf_vaddress, ++ mmc->max_req_size, DMA_BIDIRECTIONAL); ++ if (gk_sd_check_dma_boundary(pslotinfo, ++ pslotinfo->buf_paddress, mmc->max_req_size, ++ pinfo->max_blk_sz) == 0) { ++ dev_dbg(&pdev->dev, "DMA boundary err!\n"); ++ retval = -ENOMEM; ++ goto gk_sd_probe_free_host; ++ } ++ dev_dbg(&pdev->dev, "Slot%u use bounce buffer[" ++ "0x%p<->0x%08x]\n", pslotinfo->slot_id, ++ pslotinfo->buf_vaddress, ++ pslotinfo->buf_paddress); ++ ++ pslotinfo->plat_info->active_caps = mmc->caps; ++ dev_dbg(&pdev->dev, "SD caps: 0x%lx.\n", mmc->caps); ++ dev_dbg(&pdev->dev, "SD ocr: 0x%x.\n", mmc->ocr_avail); ++ dev_notice(&pdev->dev, "Slot%u req_size=0x%08X, " ++ "segs=%u, seg_size=0x%08X\n", ++ pslotinfo->slot_id, mmc->max_req_size, ++ mmc->max_segs, mmc->max_seg_size); ++/* ++ if (pslotinfo->plat_info->ext_power.gpio_id != -1) { ++ retval = gpio_request( ++ pslotinfo->plat_info->ext_power.gpio_id, ++ pdev->name); ++ if (retval < 0) { ++ gk_sd_err(pslotinfo, "Can't get Power GPIO%d\n", ++ pslotinfo->plat_info->ext_power.gpio_id); ++ pslotinfo->plat_info->ext_power.gpio_id = -1; ++ } ++ } ++ ++ if (pslotinfo->plat_info->ext_reset.gpio_id != -1) { ++ retval = gpio_request( ++ pslotinfo->plat_info->ext_reset.gpio_id, ++ pdev->name); ++ if (retval < 0) { ++ gk_sd_err(pslotinfo, "Can't get Reset GPIO%d\n", ++ pslotinfo->plat_info->ext_reset.gpio_id); ++ pslotinfo->plat_info->ext_reset.gpio_id = -1; ++ } ++ } ++ ++ if (pslotinfo->plat_info->gpio_wp.gpio_id != -1) { ++ retval = gpio_request( ++ pslotinfo->plat_info->gpio_wp.gpio_id, ++ pdev->name); ++ if (retval < 0) { ++ gk_sd_err(pslotinfo, "Can't get WP GPIO%d\n", ++ pslotinfo->plat_info->gpio_wp.gpio_id); ++ pslotinfo->plat_info->gpio_wp.gpio_id = -1; ++ } ++ } ++*/ ++ gk_sd_release_bus(mmc); ++ } ++ ++ retval = request_irq(pinfo->irq, gk_sd_irq, ++ IRQF_SHARED | IRQF_TRIGGER_HIGH, ++ "sd_control", pinfo); ++ if (retval) { ++ dev_err(&pdev->dev, "Can't Request IRQ%u!\n", pinfo->irq); ++ goto gk_sd_probe_free_host; ++ } ++ //printk("-- request %d irq ok\n", pinfo->irq); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ pslotinfo->system_event.notifier_call = gk_sd_system_event; ++ gk_register_event_notifier(&pslotinfo->system_event); ++ ++ //if (gk_is_valid_gpio_irq( &pslotinfo->plat_info->gpio_cd)) ++ { ++ /* louis add ++ retval = gpio_request( ++ pslotinfo->plat_info->gpio_cd.irq_gpio, ++ pdev->name); ++ if (retval < 0) { ++ gk_sd_err(pslotinfo, "Can't get CD GPIO%d\n", ++ pslotinfo->plat_info->gpio_cd.irq_gpio); ++ pslotinfo->plat_info->gpio_cd.irq_gpio = -1; ++ continue; ++ } ++ */ ++ gk_sd_gpio_cd_check_val(pslotinfo); ++ retval = request_irq( ++ pslotinfo->plat_info->gpio_cd.irq_line, ++ gk_sd_gpio_cd_irq, ++ pslotinfo->plat_info->gpio_cd.irq_type, ++ "sd_card_detect", pslotinfo); ++ if (retval) { ++ printk( ++ "Can't Request GPIO(%d) CD IRQ(%d)!\n", ++ pslotinfo->plat_info->gpio_cd.irq_gpio, ++ pslotinfo->plat_info->gpio_cd.irq_line); ++ } ++ //else printk("-- request detect irq %d ok\n", pslotinfo->plat_info->gpio_cd.irq_line); ++ } ++ } ++ ++ platform_set_drvdata(pdev, pinfo); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ pslotinfo->plat_info->pmmc_host = pslotinfo->mmc; ++ pslotinfo->valid = 1; ++ retval = mmc_add_host(pslotinfo->mmc); ++ if (retval) { ++ gk_sd_err(pslotinfo, "Can't add mmc host!\n"); ++ } ++ } ++ ++ dev_notice(&pdev->dev, ++ "GK SD/MMC[%d] has %u slots @ %uHz, [0x%08x:0x%08x]\n", ++ pdev->id, pinfo->pcontroller->num_slots, ++ pinfo->clk_limit, hc_cap, pinfo->dma_fix); ++ retval = 0; ++ goto gk_sd_probe_na; ++ ++gk_sd_probe_free_host: ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ if (pslotinfo->plat_info->gpio_wp.gpio_id != -1) ++ gpio_free(pslotinfo->plat_info->gpio_wp.gpio_id); ++ if (pslotinfo->plat_info->ext_power.gpio_id != -1) ++ gpio_free(pslotinfo->plat_info->ext_power.gpio_id); ++ if (pslotinfo->plat_info->ext_reset.gpio_id != -1) ++ gpio_free(pslotinfo->plat_info->ext_reset.gpio_id); ++ if (pslotinfo->buf_paddress) { ++ dma_unmap_single(pinfo->dev, pslotinfo->buf_paddress, ++ pslotinfo->mmc->max_req_size, ++ DMA_BIDIRECTIONAL); ++ pslotinfo->buf_paddress = (dma_addr_t)NULL; ++ } ++ if (pslotinfo->buf_vaddress) { ++ kmem_cache_free(pinfo->buf_cache, ++ pslotinfo->buf_vaddress); ++ pslotinfo->buf_vaddress = NULL; ++ } ++ if (pslotinfo->mmc) { ++ mmc_free_host(pslotinfo->mmc); ++ } ++ } ++ if (pinfo->buf_cache) { ++ kmem_cache_destroy(pinfo->buf_cache); ++ pinfo->buf_cache = NULL; ++ } ++ ++gk_sd_probe_free_pinfo: ++ kfree(pinfo); ++ ++gk_sd_probe_na: ++ return retval; ++} ++ ++static int __devexit gk_sd_remove(struct platform_device *pdev) ++{ ++ int retval = 0; ++ struct gk_sd_controller_info *pinfo; ++ struct gk_sd_mmc_info *pslotinfo; ++ u32 i; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ if (pinfo) { ++ platform_set_drvdata(pdev, NULL); ++ ++ free_irq(pinfo->irq, pinfo); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ pslotinfo->plat_info->pmmc_host = NULL; ++ gk_unregister_event_notifier( ++ &pslotinfo->system_event); ++ ++ free_irq(pslotinfo->plat_info->gpio_cd.irq_line, pslotinfo); ++ gpio_free(pslotinfo->plat_info->gpio_cd.irq_gpio); ++ ++ if (pslotinfo->mmc) { ++ mmc_remove_host(pslotinfo->mmc); ++ } ++ } ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ if (pslotinfo->plat_info->ext_power.gpio_id != -1) { ++ gpio_free( ++ pslotinfo->plat_info->ext_power.gpio_id); ++ } ++ if (pslotinfo->plat_info->ext_reset.gpio_id != -1) { ++ gpio_free( ++ pslotinfo->plat_info->ext_reset.gpio_id); ++ } ++ if (pslotinfo->plat_info->gpio_wp.gpio_id != -1) { ++ gpio_free( ++ pslotinfo->plat_info->gpio_wp.gpio_id); ++ } ++ if (pslotinfo->buf_paddress) { ++ dma_unmap_single(pinfo->dev, ++ pslotinfo->buf_paddress, ++ pslotinfo->mmc->max_req_size, ++ DMA_BIDIRECTIONAL); ++ pslotinfo->buf_paddress = (dma_addr_t)NULL; ++ } ++ if (pslotinfo->buf_vaddress) { ++ kmem_cache_free(pinfo->buf_cache, ++ pslotinfo->buf_vaddress); ++ pslotinfo->buf_vaddress = NULL; ++ } ++ if (pslotinfo->mmc) { ++ mmc_free_host(pslotinfo->mmc); ++ } ++ } ++ if (pinfo->buf_cache) { ++ kmem_cache_destroy(pinfo->buf_cache); ++ pinfo->buf_cache = NULL; ++ } ++ kfree(pinfo); ++ } ++ ++ dev_notice(&pdev->dev, ++ "Remove GK Media Processor SD/MMC Host Controller.\n"); ++ ++ return retval; ++} ++ ++#ifdef CONFIG_PM ++static int gk_sd_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ int retval = 0; ++ struct gk_sd_controller_info *pinfo; ++ struct gk_sd_mmc_info *pslotinfo; ++ u32 i; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ if (pslotinfo->mmc) { ++ retval = mmc_suspend_host(pslotinfo->mmc); ++ if (retval) { ++ gk_sd_err(pslotinfo, ++ "mmc_suspend_host[%d] failed[%d]!\n", ++ i, retval); ++ } ++ } ++ } ++ ++ disable_irq(pinfo->irq); ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ disable_irq(pslotinfo->plat_info->gpio_cd.irq_line); ++ } ++ ++ dev_dbg(&pdev->dev, "%s exit with %d @ %d\n", ++ __func__, retval, state.event); ++ return retval; ++} ++ ++static int gk_sd_resume(struct platform_device *pdev) ++{ ++ int retval = 0; ++ struct gk_sd_controller_info *pinfo; ++ struct gk_sd_mmc_info *pslotinfo; ++ u32 i; ++ ++ pinfo = platform_get_drvdata(pdev); ++ pinfo->pcontroller->set_pll(pinfo->clk_limit); ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ gk_sd_reset_all(pslotinfo->mmc); ++ enable_irq(pslotinfo->plat_info->gpio_cd.irq_line); ++ } ++ enable_irq(pinfo->irq); ++ ++ for (i = 0; i < pinfo->pcontroller->num_slots; i++) { ++ pslotinfo = pinfo->pslotinfo[i]; ++ if (pslotinfo->mmc) { ++ retval = mmc_resume_host(pslotinfo->mmc); ++ if (retval) { ++ gk_sd_err(pslotinfo, ++ "mmc_resume_host[%d] failed[%d]!\n", ++ i, retval); ++ } ++ } ++ } ++ ++ dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, retval); ++ ++ return retval; ++} ++#endif ++ ++static struct platform_driver gk_sd_driver = { ++ .probe = gk_sd_probe, ++ .remove = __devexit_p(gk_sd_remove), ++#ifdef CONFIG_PM ++ .suspend = gk_sd_suspend, ++ .resume = gk_sd_resume, ++#endif ++ .driver = { ++ .name = "gk-sd", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init gk_sd_init(void) ++{ ++ int retval = 0; ++ ++ retval = platform_driver_register(&gk_sd_driver); ++ if (retval) { ++ printk(KERN_ERR "%s: Register failed %d!\n", ++ __func__, retval); ++ } ++ ++ return retval; ++} ++ ++static void __exit gk_sd_exit(void) ++{ ++ platform_driver_unregister(&gk_sd_driver); ++} ++ ++fs_initcall(gk_sd_init); ++module_exit(gk_sd_exit); ++ ++MODULE_DESCRIPTION("GOKE Media Processor SD/MMC Host Controller"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c +index 273306c6..7dc3a267 100644 +--- a/drivers/mmc/host/mmc_spi.c ++++ b/drivers/mmc/host/mmc_spi.c +@@ -190,6 +190,8 @@ mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) + host->data_dma, sizeof(*host->data), + DMA_FROM_DEVICE); + ++ spi_message_add_tail(&host->status, &host->readback); ++ + return status; + } + +@@ -955,12 +957,22 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, + t->len); + + if (direction == DMA_TO_DEVICE) ++ { + status = mmc_spi_writeblock(host, t, timeout); ++ if(length) ++ spi_message_add_tail(&host->token, &host->m); ++ } + else + status = mmc_spi_readblock(host, t, timeout); + if (status < 0) + break; +- ++ if(length) ++ { ++ spi_message_add_tail(t, &host->m); ++ spi_message_add_tail(&host->crc, &host->m); ++ if (direction == DMA_TO_DEVICE) ++ spi_message_add_tail(&host->early_status, &host->m); ++ } + data->bytes_xfered += t->len; + length -= t->len; + +diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig +index 27143e04..a5d975c2 100644 +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -322,6 +322,8 @@ source "drivers/mtd/devices/Kconfig" + + source "drivers/mtd/nand/Kconfig" + ++source "drivers/mtd/spinand/Kconfig" ++ + source "drivers/mtd/onenand/Kconfig" + + source "drivers/mtd/lpddr/Kconfig" +diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile +index f9013542..e5ebd5b9 100644 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -30,6 +30,6 @@ obj-$(CONFIG_MTD_SWAP) += mtdswap.o + nftl-objs := nftlcore.o nftlmount.o + inftl-objs := inftlcore.o inftlmount.o + +-obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ ++obj-y += chips/ lpddr/ maps/ devices/ nand/ spinand/ onenand/ tests/ + + obj-$(CONFIG_MTD_UBI) += ubi/ +diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig +index 4cdb2af7..d82a37df 100644 +--- a/drivers/mtd/devices/Kconfig ++++ b/drivers/mtd/devices/Kconfig +@@ -96,6 +96,37 @@ config MTD_M25P80 + if you want to specify device partitioning or to use a device which + doesn't support the JEDEC ID instruction. + ++config MTD_SFLASH_GOKE ++ tristate "Support most Serial Flash on goke ipc (S25FL128P,MX25L12845E...)" ++ depends on EXPERIMENTAL ++ depends on GK_SFLASH ++ ++if MTD_SFLASH_GOKE ++choice SFLASH_WR_MODE ++ default SFLASH_W_1X_R_1X_MODE ++ prompt 'SFLASH read write mode' ++ help ++ SFLASH read write mode. ++config SFLASH_1X_R_1X_W_MODE ++ bool 'USE 1X mode read and 1X mode write' ++ depends on MTD_SFLASH_GOKE ++ help ++ Enable USE 1X mode read write. ++ ++config SFLASH_4X_R_1X_W_MODE ++ bool 'USE 4X mode read and 1X mode write' ++ depends on MTD_SFLASH_GOKE ++ help ++ Enable USE 4X mode read and 1X mode write. ++ ++config SFLASH_4X_R_4X_W_MODE ++ bool 'USE 4X mode read and 4X mode write' ++ depends on MTD_SFLASH_GOKE ++ help ++ Enable USE 4X mode read and 4X mode write. ++endchoice ++endif # if INET ++ + config M25PXX_USE_FAST_READ + bool "Use FAST_READ OPCode allowing SPI CLK <= 50MHz" + depends on MTD_M25P80 +diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile +index a4dd1d82..6d6ce50f 100644 +--- a/drivers/mtd/devices/Makefile ++++ b/drivers/mtd/devices/Makefile +@@ -1,6 +1,9 @@ + # + # linux/drivers/mtd/devices/Makefile + # ++ifdef CONFIG_MTD_SFLASH_GOKE ++obj-$(CONFIG_GK_SFLASH_V1_00) += gk_sflash_v1_00.o ++endif + + obj-$(CONFIG_MTD_DOC2000) += doc2000.o + obj-$(CONFIG_MTD_DOC2001) += doc2001.o +@@ -20,4 +23,4 @@ obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o + +-CFLAGS_docg3.o += -I$(src) +\ No newline at end of file ++CFLAGS_docg3.o += -I$(src) +diff --git a/drivers/mtd/devices/gk_sflash_v1_00.c b/drivers/mtd/devices/gk_sflash_v1_00.c +new file mode 100644 +index 00000000..109d030b +--- /dev/null ++++ b/drivers/mtd/devices/gk_sflash_v1_00.c +@@ -0,0 +1,2879 @@ ++/* ++ * drivers/mtd/devices/gk_sflash_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/*get register address*/ ++#include ++/*include write and read function*/ ++#include ++#include ++ ++#include "gk_sflash_v1_00.h" ++ ++/****************************************************************************/ ++/* ++******************************************************************************* ++** ++** gd_sflash_devices_supported is an array containing serial flash ++** geometry and information data of all supported devices, it will ++** be used during GD_SFLASH_Init() to find the connected serial ++** flash decive ++** ++******************************************************************************* ++*/ ++#define GD_SFLASH_USE_BUFFER 0 ++/* ++******************************************************************************* ++** ++** serial flash specific commands for Spansion flash devices ++** ++******************************************************************************* ++*/ ++static const goke_sflash_cmd_s sflash_commands_mx = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x38, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++static const goke_sflash_cmd_s sflash_commands_spansion = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x32, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0x35, ++}; ++ ++/*-------------------------------------------------------------------------------*/ ++/* serial flash specific commands for STmicro flash devices */ ++/*-------------------------------------------------------------------------------*/ ++static const goke_sflash_cmd_s sflash_commands_stmicro = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0x00, ++ /* read_io4 */ 0x00, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x00, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++ ++/*-------------------------------------------------------------------------------*/ ++/* serial flash specific commands for Atmel flash devices */ ++/*-------------------------------------------------------------------------------*/ ++static const goke_sflash_cmd_s sflash_commands_atmel = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0x00, ++ /* read_io4 */ 0x00, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x00, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++ ++/*-------------------------------------------------------------------------------*/ ++/* serial flash specific commands for NUMONYX flash devices */ ++/*-------------------------------------------------------------------------------*/ ++static const goke_sflash_cmd_s sflash_commands_numonyx = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0xd2, ++ /* program_page4 */ 0x12, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++ ++static const goke_sflash_cmd_s sflash_commands_wb = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x32, ++ /* read_ext_addr */ 0xC8, ++ /* write_ext_addr */ 0xC5, ++ /* read_status2 */ 0x35, ++}; ++ ++static const goke_sflash_cmd_s sflash_command_sst = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0x20, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x80, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0x00, ++ /* read_io4 */ 0x0B, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x32, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++static const goke_sflash_cmd_s sflash_commands_gd = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x32, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0x35, ++}; ++static const goke_sflash_cmd_s sflash_commands_eon = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0x00, ++ /* read_io4 */ 0x0b, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x02, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++ ++static const goke_sflash_cmd_s sflash_commands_issi = ++{ ++ /* read_ID */ 0x9F, ++ /* write_enable */ 0x06, ++ /* write_disable */ 0x04, ++ /* read_status */ 0x05, ++ /* write_status */ 0x01, ++ /* read_data */ 0x03, ++ /* read_data_fast */ 0x0B, ++ /* erase_sector */ 0xD8, ++ /* erase_chip */ 0xC7, ++ /* program_page */ 0x02, ++ /* status_mask_wip */ 0x01, ++ /* status_mask_wel */ 0x02, ++ /* read_io2 */ 0xbb, ++ /* read_io4 */ 0xeb, ++ /* program_page2 */ 0x00, ++ /* program_page4 */ 0x38, ++ /* read_ext_addr */ 0xFF, ++ /* write_ext_addr */ 0xFF, ++ /* read_status2 */ 0xFF, ++}; ++/*-------------------------------------------------------------------------------*/ ++/* serial flash geometry and information data of all supported devices */ ++/*-------------------------------------------------------------------------------*/ ++static goke_sflash_dev_s sflash_devices_supported[] = ++{ ++ ++ /* ++ ** Spansion seem to use unique sectors ++ ** with 64kBytes each, they increment the ++ ** number of sectors for bigger chips ++ */ ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x0212, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "S25FL004A", ++ /* device_bytes */ 524288, ++ /* sector_count */ 8, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x0213, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "S25FL008A", ++ /* device_bytes */ 1048576, ++ /* sector_count */ 16, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x0214, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "S25FL016A", ++ /* device_bytes */ 2097152, ++ /* sector_count */ 32, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x0215, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "S25FL032P", ++ /* device_bytes */ 4194304, ++ /* sector_count */ 64, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x0216, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "S25FL064A", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x01, ++ /* device_ID */ 0x2018, ++ /* manufacture_name */ "Spansion", ++ /* device_name */ "FL128PIFL", ++ /* device_bytes */ 16777216, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_spansion, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x9CF5, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ ++ /* ++ ** MX seem to use unique sectors ++ ** with 64kBytes each, they increment the ++ ** number of sectors for bigger chips ++ */ ++ /* gk6105 8M SFlash */ ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x2617, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX25L6455E", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufactureID */ 0xc2, ++ /* deviceID */ 0x2017, ++ /* manufactureName */ "MX", ++ /* deviceName */ "MX25L6465E", ++ /* deviceBytes */ 8388608, ++ /* sectorCount */ 128, ++ /* sectorBytes */ 65536, ++ /* sectorPages */ 256, ++ /* pageBytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* ioMode */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x2018, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX25L12845", ++ /* device_bytes */ 16777216, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x5e16, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX253235D", ++ /* device_bytes */ 4194304, ++ /* sector_count */ 64, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x2415, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX25L1605D", ++ /* device_bytes */ 2097152, ++ /* sector_count */ 32, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x2415, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX25L1635D", ++ /* device_bytes */ 2097152, ++ /* sector_count */ 32, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xc2, ++ /* device_ID */ 0x9e16, ++ /* manufacture_name */ "MX", ++ /* device_name */ "MX25L3255D", ++ /* device_bytes */ 4194304, ++ /* sector_count */ 64, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_mx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x00BC, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xef, ++ /* device_ID */ 0x4015, ++ /* manufacture_name */ "Winbond", ++ /* device_name */ "W25Q16BV", ++ /* device_bytes */ 2097152, ++ /* sector_count */ 32, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_wb, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x1C00, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xef, ++ /* device_ID */ 0x4017, ++ /* manufacture_name */ "Winbond", ++ /* device_name */ "W25Q64FV", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_wb, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x1C00, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufactureID */ 0xef, ++ /* deviceID */ 0x4018, ++ /* manufactureName */ "Winbond", ++ /* deviceName */ "W25Q128FV", ++ /* deviceBytes */ 16777216, ++ /* sectorCount */ 256, ++ /* sectorBytes */ 65536, ++ /* sectorPages */ 256, ++ /* pageBytes */ 256, ++ /* commands */ &sflash_commands_wb, ++ /* ioMode */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x1C00, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufactureID */ 0xef, ++ /* deviceID */ 0x4019, ++ /* manufactureName */ "Winbond", ++ /* deviceName */ "W25Q256FV", ++ /* deviceBytes */ (1024*1024*32), ++ /* sectorCount */ 512, ++ /* sectorBytes */ 65536, ++ /* sectorPages */ 256, ++ /* pageBytes */ 256, ++ /* commands */ &sflash_commands_wb, ++ /* ioMode */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x3C00, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xbf, ++ /* device_ID */ 0x2601, ++ /* manufacture_name */ "SST", ++ /* device_name */ "SST26VF016", ++ /* device_bytes */ 2097152, ++ /* sector_count */ 512, ++ /* sector_bytes */ 4096, ++ /* sector_pages */ 16, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_command_sst, ++ /* iomode */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFFFF, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x20, ++ /* device_ID */ 0xba18, ++ /* manufacture_name */ "numonyx", ++ /* device_name */ "N25Q128", ++ /* device_bytes */ 8388608*2, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_numonyx, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFFFF, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xC8, ++ /* device_ID */ 0x4017, ++ /* manufacture_name */ "giga", ++ /* device_name */ "GD25Q64C", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_gd, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFC79, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0xC8, ++ /* device_ID */ 0x4018, ++ /* manufacture_name */ "giga", ++ /* device_name */ "GD25Q128C", ++ /* device_bytes */ 8388608*2, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_gd, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFC79, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x1c, ++ /* device_ID */ 0x3017, ++ /* manufacture_name */ "EON", ++ /* device_name */ "EN25Q64", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_eon, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x003C, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x1c, ++ /* device_ID */ 0x7017, ++ /* manufacture_name */ "EON", ++ /* device_name */ "ENQH64A", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_eon, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x003C, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x1c, ++ /* device_ID */ 0x7018, ++ /* manufacture_name */ "EON", ++ /* device_name */ "EN25Q128", ++ /* device_bytes */ 8388608*2, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_eon, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0x003C, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x9D, ++ /* device_ID */ 0x6017, ++ /* manufacture_name */ "ISSI", ++ /* device_name */ "IC25LP064", ++ /* device_bytes */ 8388608, ++ /* sector_count */ 128, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_issi, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFFFF, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ }, ++ { ++ /* manufacture_ID */ 0x9D, ++ /* device_ID */ 0x6018, ++ /* manufacture_name */ "ISSI", ++ /* device_name */ "IC25LP128", ++ /* device_bytes */ 8388608*2, ++ /* sector_count */ 256, ++ /* sector_bytes */ 65536, ++ /* sector_pages */ 256, ++ /* page_bytes */ 256, ++ /* commands */ &sflash_commands_issi, ++ /* feature */ GD_SFLASH_1X_WRITE | GD_SFLASH_1X_READ, ++ /* lock_mask */ 0xFFFF, ++ /* io4_mask */ 0xFFFF, ++ /* channel */ 0x0, ++ } ++ ++}; ++static goke_sflash_feature_e old_feature = GOKE_SFLASH_FEATURE_IO1; ++static u32 sflash_write_enable(goke_sflash_dev_s *device); ++ ++struct gk_sflash ++{ ++ struct mutex lock; ++ struct mtd_info mtd; ++ goke_sflash_dev_s *device; ++}; ++static u32 sflash_cmd_bit_set(goke_sflash_command_s *sflashCmd, u32 *cmdBitSet); ++ ++static inline struct gk_sflash* mtd_to_gk_flash(struct mtd_info *mtd) ++{ ++ return container_of(mtd, struct gk_sflash, mtd); ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_CE (read/write) */ ++/*----------------------------------------------------------------------------*/ ++ ++__inline static void sflash_set_ce(u32 data) ++{ ++ gk_sf_writel(REG_SFLASH_CE, data); ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_Command (read/write) */ ++/*----------------------------------------------------------------------------*/ ++ ++__inline static void sflash_set_speed(u32 data) ++{ ++ gk_sf_writel(REG_SFLASH_SPEED, data); ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_Command (read/write) */ ++/*----------------------------------------------------------------------------*/ ++ ++__inline static void sflash_set_command(u32 data) ++{ ++ gk_sf_writel(REG_SFLASH_COMMAND, data); ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_Data (read/write) */ ++/*----------------------------------------------------------------------------*/ ++ ++__inline static void sflash_set_data(u32 data) ++{ ++ gk_flash_write(data); ++} ++ ++__inline static u32 sflash_get_data(void) ++{ ++ return gk_flash_read(); ++} ++ ++static u32 sflash_wip_done_wait(goke_sflash_dev_s *device) ++{ ++ u8 wip_mask; ++ goke_sflash_command_s sflash_cmd; ++ u32 cmd_bit_set = 0; ++ ++ cmd_bit_set |= (device->commands->read_status| ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ (1<manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= (SFLASH_CMD_MODE_4X|SFLASH_DATA_CYCLE_NUM_2); ++ } ++ else ++ { ++ cmd_bit_set |= (SFLASH_CMD_MODE_1X|SFLASH_DATA_CYCLE_NUM_0); ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ ++ wip_mask = device->commands->status_mask_wip; ++ while(1) ++ { ++ sflash_set_command(sflash_cmd.all); ++ ++ if((sflash_get_data() & wip_mask) != wip_mask) /*flash device ready*/ ++ { ++ return(0); ++ } ++ } ++ return 1; ++} ++ ++static u32 sflash_wel_done_wait(goke_sflash_dev_s *device) ++{ ++ u8 wel_mask; ++ goke_sflash_command_s sflash_cmd; ++ u32 cmd_bit_set = 0; ++ ++ cmd_bit_set |= (device->commands->read_status| ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ (1<manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= (SFLASH_CMD_MODE_4X|SFLASH_DATA_CYCLE_NUM_2); ++ } ++ else ++ { ++ cmd_bit_set |= (SFLASH_CMD_MODE_1X|SFLASH_DATA_CYCLE_NUM_0); ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ ++ wel_mask = device->commands->status_mask_wel; ++ while(1) ++ { ++ sflash_set_command(sflash_cmd.all); ++ ++ if((sflash_get_data() & wel_mask) == wel_mask) /*flash enable ready*/ ++ { ++ return(0); ++ } ++ } ++ return 1; ++} ++ ++/*! ++******************************************************************************** ++** ++** \brief unlock the serial flash ++** ++** This function unlock the serial flash. ++** ++** \return ++** - GD_ERR_INVALID_HANDLE if the given handle parameter points to 0 ++** - GD_OK if unlock operation successfully ++** ++******************************************************************************** ++*/ ++static u32 sflash_Unlock(goke_sflash_dev_s *device) ++{ ++ goke_sflash_command_s sflash_cmd; ++ u32 cmd_bit_set = 0; ++ u8 status; ++ u16 sflashData; ++ ulong CESetting = 0x38; ++ ++ CESetting = CESetting | ((ulong)device->channel << 6); ++ sflash_set_ce(CESetting); ++ ++ /* write enable the device */ ++ sflash_write_enable(device); ++ ++ cmd_bit_set = (device->commands->read_status | // command ++ SFLASH_SEND_CMD | // transfer the command ++ SFLASH_SEND_ADDR_BYTE_NUM_0 | // address num ++ SFLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ SFLASH_RWN_READ | // read data ++ SFLASH_CMD_MODE_1X | // set the sflash cmd mode ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ SFLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1<commands->read_status2 != 0xFF) ++ { ++ cmd_bit_set = (device->commands->read_status2| // command ++ SFLASH_SEND_CMD | // transfer the command ++ SFLASH_SEND_ADDR_BYTE_NUM_0 | // address num ++ SFLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ SFLASH_RWN_READ | // read data ++ SFLASH_CMD_MODE_1X | // set the sflash cmd mode ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ SFLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1<commands->write_status| // command ++ SFLASH_SEND_CMD | // transfer the command ++ SFLASH_SEND_ADDR_BYTE_NUM_0 | // address num ++ SFLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ SFLASH_RWN_WRITE | // write data ++ SFLASH_CMD_MODE_1X | // set the sflash cmd mode ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ SFLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1<commands->read_status2 != 0xFF) ++ { ++ sflash_cmd.bitc.data_num = 0x2; // transfer data ++ } ++ sflashData &= ~(device->lock_mask); ++ if(device->manufacture_ID == 0x01) ++ { ++ sflashData |= 0x0024; ++ } ++ ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(sflashData); ++ ++ sflash_wip_done_wait(device); ++ CESetting = CESetting & (~((ulong)device->channel << 6)); ++ sflash_set_ce(CESetting); ++ return(0); ++} ++ ++static goke_sflash_dev_s* jedec_probe(struct platform_device *dev) ++{ ++ u32 sflash_data; ++ u8 manufacture_ID; ++ u16 device_ID; ++ u32 index; ++ u32 count; ++ u32 cmd_bit_set = 0; ++ u8 command,status; ++ u32 prot1; ++ u32 prot2; ++ goke_sflash_dev_s *device; ++ goke_sflash_command_s sflash_cmd; ++ u32 ce_setting = 0x0E; ++ GD_SFLASH_SPEED_MODE speed_mode = GOKE_SFLASH_FREQ_DIV2; ++ goke_sflash_channel_e channel = GOKE_SFLASH_CHANNEL_0; ++#ifdef CONFIG_OF ++ if (of_property_read_u32(dev->dev.of_node, "gofortune-semi,channel", &channel) || ++ of_property_read_u32(dev->dev.of_node, "gofortune-semi,speed", &speed_mode)) { ++ return NULL; ++ } ++#else /* CONFIG_OF */ ++ struct sflash_platform_data *platform_data = dev->dev.platform_data; ++ ++ channel = platform_data->channel; ++ speed_mode = platform_data->speed_mode; ++#endif /* !CONFIG_OF */ ++ printk(KERN_ERR "speed_mod is %d\n", speed_mode); ++ if(channel >= GOKE_SFLASH_CHANNEL_NUM) ++ { ++ return NULL; ++ } ++ ++ ce_setting = ce_setting | ((u32)channel << 6); ++ ++ sflash_set_ce(ce_setting); ++ sflash_set_speed(speed_mode); /*0 -- 1/2freq 1--1/4freq 2....4*/ ++ ++ count = sizeof(sflash_devices_supported)/sizeof(goke_sflash_dev_s); ++ ++ for(index=0; index < count; index++) ++ { ++ device = &(sflash_devices_supported[index]); ++ ++ command = device->commands->read_ID; ++ ++ sflash_set_ce(ce_setting); ++ cmd_bit_set |= (SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (3<> 16); ++ device_ID = (u16)(sflash_data & 0x0000FFFF); ++ if((manufacture_ID == device->manufacture_ID) ++ && (device_ID == device->device_ID)) ++ { ++ if(manufacture_ID == 0xbf) /*SST sflash which support most quad IO cmd*/ ++ { ++ cmd_bit_set |= (0x38| /*enable quad command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write*/ ++ SFLASH_CMD_MODE_1X| /*set command mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<> 16); ++ device_ID = (u16)(sflash_data & 0x0000FFFF); ++ ++ if(manufacture_ID != 0xbf || device_ID!= 0x2601) ++ { ++ return(NULL); ++ } ++ ++ /*ok read the protection bit for each block*/ ++ sflash_cmd.bitc.code = 0x72; /*read block protection register*/ ++ sflash_cmd.bitc.data_num = 0x6; /*transfer data number*/ ++ ++ sflash_set_command(sflash_cmd.all); ++ prot1 = sflash_get_data(); ++ prot2 = sflash_get_data(); ++ ++ /*ok write enable the device*/ ++ sflash_cmd.bitc.code = 0x06; /*enable quad command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_NOTHING>>15; /*3; no read/write*/ ++ sflash_cmd.bitc.data_num = 0; ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ ++ /*program the prot bit*/ ++ sflash_cmd.bitc.code = 0x42; /*enable quad command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_WRITE>>15; /*write*/ ++ sflash_cmd.bitc.data_num = 6; ++ prot1 = 0x0; ++ prot2=0x0; ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(prot1); ++ sflash_set_data(prot2); ++ ++ /*wait the program*/ ++ sflash_cmd.bitc.code = 0x05; /*read status*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_READ>>15; /*read*/ ++ sflash_cmd.bitc.data_num = 1; ++ do ++ { ++ sflash_set_command(sflash_cmd.all); ++ status = sflash_get_data()&0xff; ++ }while((status&0x80) == 0x80); ++ ++ /*ok read the protection bit for each block*/ ++ sflash_cmd.bitc.code = 0x72; /*enable quad command*/ ++ sflash_cmd.bitc.data_num = 0x6; /*transfer data number*/ ++ sflash_set_command(sflash_cmd.all); ++ prot1 = sflash_get_data(); ++ prot2 = sflash_get_data(); ++ ++#ifdef CONFIG_SFLASH_1X_R_1X_W_MODE ++ device->feature = GD_SFLASH_1X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 1X mode read and 1X mode write\n"); ++#else ++#ifdef CONFIG_SFLASH_4X_R_1X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 4X mode read and 1X mode write\n"); ++#endif ++#ifdef CONFIG_SFLASH_4X_R_4X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_4X_WRITE; ++ printk("USE 4X mode read and 4X mode write\n"); ++#endif ++#endif ++ } ++ else if(device->manufacture_ID == 0x0c2) ++ { ++ cmd_bit_set |= (0x2b| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (1<commands->write_enable; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_NOTHING>>15; /* not read & write*/ ++ sflash_cmd.bitc.data_num = 0x0; /*not transfer data*/ ++ sflash_set_command( sflash_cmd.all ); ++ sflash_get_data(); ++ sflash_cmd.bitc.code = 0x05; /*read status*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_READ>>15; /*read*/ ++ sflash_cmd.bitc.data_num = 1; ++ do ++ { ++ sflash_set_command(sflash_cmd.all); ++ status = sflash_get_data()&0xff; ++ }while((status&0x01) == 0x01); ++ ++ sflash_cmd.bitc.code = 0x98; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_NOTHING>>15; /* not read & write*/ ++ sflash_cmd.bitc.data_num = 0x0; /*not transfer data*/ ++ sflash_set_command( sflash_cmd.all ); ++ sflash_get_data(); ++ sflash_cmd.bitc.code = 0x05; /*read status*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_READ>>15; /*read*/ ++ sflash_cmd.bitc.data_num = 1; ++ do ++ { ++ sflash_set_command( sflash_cmd.all ); ++ status = sflash_get_data()&0xff; ++ }while((status&0x01) == 0x01); ++ } ++ // check if the chip support 4X read mode? ++ cmd_bit_set |= (0x5A| /*command RDSFDP*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_1| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4| /*transfer data number*/ ++ SFLASH_HOLD_TIME_100ns ++ ); ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(0x30); ++ sflash_data = sflash_get_data(); ++ ++#ifdef CONFIG_SFLASH_1X_R_1X_W_MODE ++ device->feature = GD_SFLASH_1X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 1X mode read and 1X mode write\n"); ++#else ++#ifdef CONFIG_SFLASH_4X_R_1X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 4X mode read and 1X mode write\n"); ++#endif ++#ifdef CONFIG_SFLASH_4X_R_4X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_4X_WRITE; ++ printk("USE 4X mode read and 4X mode write\n"); ++#endif ++#endif ++ // command-address-data ++ // 0x32[bit12]=1:1-2-2 ++ // 0x32[bit13]=1:1-2-4 ++ // 0x32[bit14]=1:1-4-4 ++ // sflash_data=0x30 31 32 33 ++ if((sflash_data != 0x00000000) || (sflash_data != 0xFFFFFFFF)) ++ { ++ device->feature &= 0xFFFFFFF8; ++ if(sflash_data & 0x00006000) ++ { ++ //device->feature |= GD_SFLASH_4X_READ; ++ printk("support 4X mode read:0x%08x\n", sflash_data); ++ } ++ else ++ { ++ device->feature |= GD_SFLASH_1X_READ; ++ printk("not support 4X mode read:0x%08x\n", sflash_data); ++ } ++ } ++ } ++ else ++ { ++#ifdef CONFIG_SFLASH_1X_R_1X_W_MODE ++ device->feature = GD_SFLASH_1X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 1X mode read and 1X mode write\n"); ++#else ++#ifdef CONFIG_SFLASH_4X_R_1X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_1X_WRITE; ++ printk("USE 4X mode read and 1X mode write\n"); ++#endif ++#ifdef CONFIG_SFLASH_4X_R_4X_W_MODE ++ device->feature = GD_SFLASH_4X_READ | GD_SFLASH_4X_WRITE; ++ printk("USE 4X mode read and 4X mode write\n"); ++#endif ++#endif ++ } ++ device->channel = channel; ++ sflash_Unlock(device); ++#if GD_SFLASH_USE_BUFFER ++ device->buffer_size = device->sector_bytes; ++ device->buffer = kmalloc(device->buffer_size, GFP_KERNEL); ++ device->offset = 0xFFFFFFFF; ++ if(device->buffer) ++ { ++ return device; ++ } ++ else ++ { ++ return NULL; ++ } ++#else ++ return device; ++#endif ++ } ++ } ++ return NULL; ++} ++ ++static u32 sflash_enable_io4(goke_sflash_dev_s* device ) ++{ ++ u8 status1 = 0; ++ u8 status2 = 0; ++ u32 data = 0; ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ u32 ce_setting = 0x38; ++ ++ if( !device ) ++ return(EINVAL); ++ ++ /*for IO4 mode only*/ ++ ce_setting = ce_setting | ((u32)device->channel << 6); ++ sflash_set_ce(ce_setting); ++ ++ /*after Init, the SST enter IO4 mode*/ ++ if(device->manufacture_ID == 0xbf) ++ { ++ return 0; ++ } ++ if(device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= (0x38| /*enable quad command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /*dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write*/ ++ SFLASH_CMD_MODE_1X| /*set command mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<commands->read_status| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (1<manufacture_ID == 0xef) /*winbond read status2*/ ++ ||(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ ||(device->manufacture_ID == 0xc8)) /*for GD liujinyng2011-10-12*/ ++ { ++ sflash_cmd.bitc.code = 0x35; /*command*/ ++ sflash_set_command( sflash_cmd.all ); ++ status2 = sflash_get_data()&0xff; ++ } ++ ++ /* write enable the device */ ++ sflash_cmd.bitc.code = device->commands->write_enable; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_NOTHING>>15; /* not read & write*/ ++ sflash_cmd.bitc.data_num = 0x0; /*not transfer data*/ ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ ++ ++ if(device->manufacture_ID == 0xc2) ++ { ++ data = status1|0x40; ++ } ++ else if(device->manufacture_ID == 0xef) ++ { ++ data = (status1<<8)+(status2|0x2); ++ } ++ else if(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ { ++ data = (status1<<8)+(status2|0x2); ++ } ++ else if(device->manufacture_ID == 0xc8) ++ { ++ data = status2|0x2; ++ } ++ ++ /* write the status register */ ++ sflash_cmd.bitc.code = device->commands->write_status; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_WRITE>>15; /*write*/ ++ if(device->manufacture_ID == 0xc2) ++ { ++ sflash_cmd.bitc.data_num = 0x1; /*transfer 1 byte data*/ ++ } ++ else if(device->manufacture_ID == 0xef) ++ { ++ sflash_cmd.bitc.data_num = 0x2; /*transfer 2 byte data*/ ++ } ++ else if(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ { ++ sflash_cmd.bitc.data_num = 0x2; /*transfer data*/ ++ } ++ else if(device->manufacture_ID == 0xc8) ++ { ++ sflash_cmd.bitc.code = 0x31; ++ sflash_cmd.bitc.data_num = 0x1; /*transfer data*/ ++ } ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(data); ++ sflash_wip_done_wait(device); ++ ++ return 0; ++} ++ ++static u32 sflash_disenable_io4( goke_sflash_dev_s* device ) ++{ ++ u8 status1 = 0; ++ u8 status2 = 0; ++ u32 data = 0; ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ u32 ce_setting = 0x0E; ++ ++ if( !device ) ++ return(EINVAL); ++ ++ /*fix configuration for no pull-high W/P pin*/ ++ ce_setting = ce_setting | ((u32)device->channel << 6); ++ sflash_set_ce(ce_setting); ++ ++ /*SST sflash support IO4 mode. don't exit this mode*/ ++ if(device->manufacture_ID == 0xbf) ++ { ++ return 0; ++ } ++ if(device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= (0xff| /*enable quad command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write*/ ++ SFLASH_CMD_MODE_4X| /*set command mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<commands->read_status| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (1<manufacture_ID == 0xef) /*winbond read status2*/ ++ ||(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ ||(device->manufacture_ID == 0xc8)) /*for GD liujinyng2011-10-12*/ ++ { ++ sflash_cmd.bitc.code = 0x35; /*command*/ ++ sflash_set_command(sflash_cmd.all); ++ status2 = sflash_get_data()&0xff; ++ } ++ ++ /* write enable the device */ ++ sflash_cmd.bitc.code = device->commands->write_enable; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_NOTHING>>15; /* not read & write*/ ++ sflash_cmd.bitc.data_num = 0x0; /*not transfer data*/ ++ sflash_set_command( sflash_cmd.all ); ++ sflash_get_data(); ++ ++ if(device->manufacture_ID == 0xc2) ++ { ++ //Steven Yu: // clear quad ++ //for GK workaround do not enable reset mode otherwise code can not bootup ++ //data = status1&(~0x40); /*clear quad*/ ++ //write back status1 ++ data = status1; ++ } ++ else if(device->manufacture_ID == 0xef) ++ { ++ data = (status1<<8)+ (status2 & (~0x2)); /*clear the quad*/ ++ } ++ else if(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ { ++ data = (status1<<8)+ (status2 & (~0x2)); /*clear the quad*/ ++ } ++ else if(device->manufacture_ID == 0xc8) ++ { ++ data = status2 & (~0x2); ++ } ++ ++ /* write the status register */ ++ sflash_cmd.bitc.code = device->commands->write_status; /*command*/ ++ sflash_cmd.bitc.rwn = SFLASH_RWN_WRITE>>15; /*write*/ ++ if(device->manufacture_ID == 0xc2) ++ { ++ sflash_cmd.bitc.data_num = 0x1; /*transfer data*/ ++ } ++ else if(device->manufacture_ID == 0xef) ++ { ++ sflash_cmd.bitc.data_num = 0x2; /*transfer data*/ ++ } ++ else if(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ { ++ sflash_cmd.bitc.data_num = 0x2; /*transfer data*/ ++ } ++ else if(device->manufacture_ID == 0xc8) ++ { ++ sflash_cmd.bitc.code = 0x31; ++ sflash_cmd.bitc.data_num = 0x1; /*transfer data*/ ++ } ++ ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(data); ++ sflash_wip_done_wait(device); ++ ++ return 0; ++} ++ ++static u32 sflash_write_enable(goke_sflash_dev_s *device) ++{ ++ goke_sflash_command_s sflash_cmd; ++ u32 cmd_bit_set = 0; ++ ++ cmd_bit_set = (device->commands->write_enable| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_4X; /*set the sflash cmd mode*/ ++ } ++ else ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_1X; /*set the sflash cmd mode*/ ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ ++ return sflash_wel_done_wait(device); ++} ++ ++static u32 sflash_set_ext_addr(goke_sflash_dev_s* device, u8 offset) ++{ ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ u8 extadd = 0; ++ ++ sflash_write_enable(device); ++ ++ cmd_bit_set = (device->commands->read_ext_addr|/*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (2<commands->write_ext_addr|/*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_WRITE| /*write data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (1<commands->read_data| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4| /*transfer data number*/ ++ SFLASH_HOLD_TIME_100ns ++ ); ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ ++ while(data_len--) ++ { ++ *buffer++ = sflash_get_data(); ++ } ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ ++ return 0; ++} ++ ++static int sflash_read_io2( goke_sflash_dev_s* device, u32 offset, u32* buffer, u32 data_len ) ++{ ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ ++ if( !device ) ++ return(EINVAL); ++ ++ if(device->manufacture_ID == 0x20) ++ { ++ cmd_bit_set |= (device->commands->read_io2| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_2| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_1| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_1| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ else ++ { ++ cmd_bit_set |= (device->commands->read_io2| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_1| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_1| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_1| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ ++ while(data_len--) ++ { ++ *buffer++ = sflash_get_data(); ++ } ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ ++ return 0; ++} ++ ++static int sflash_read_io4( goke_sflash_dev_s* device, u32 offset, u32* buffer, u32 data_len ) ++{ ++ u32 cmd_bit_set = 0; ++ u32 err = 0; ++ goke_sflash_command_s sflash_cmd; ++ ++ if( !device ) ++ return(EINVAL); ++ if(device->manufacture_ID == 0x20) ++ { ++ err = 0; ++ } ++ else ++ { ++ err = sflash_enable_io4(device); /*enable the IO4 mode*/ ++ } ++ if(err != 0) ++ { ++ return err; ++ } ++ ++ if(device->manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= (device->commands->read_io4| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_1| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_4X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_2| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_2| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ else if(device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= (device->commands->read_io4| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_3| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_4X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_2| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_2| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ else if(device->manufacture_ID == 0x20) ++ { ++ cmd_bit_set |= (device->commands->read_io4| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_5| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_2| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_2| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ else ++ { ++ cmd_bit_set |= (device->commands->read_io4| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_3| /*dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_2| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_2| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4 /*transfer data number*/ ++ ); ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ ++ while(data_len--) ++ { ++ *buffer++ = sflash_get_data(); ++ } ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ ++ //if(device->manufacture_ID == 0x20) ++ //{ ++ // err = sflash_wip_done_wait(device); ++ //} ++ //else ++ //{ ++ // err = sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ //} ++ ++ return err; ++} ++ ++ ++static int sflash_write_io1( goke_sflash_dev_s* device, u32 offset, u32* buffer, u32 data_len ) ++{ ++ u32 count = 0; ++ u32 page_words; ++ u32 write_words = data_len; ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ u32 result = 0; ++ u32 extadd = 0; ++ ++ if( !device ) ++ return(EINVAL); ++ ++ page_words = device->page_bytes / sizeof(u32); ++ ++ while(write_words--) ++ { ++ if(count == 0) ++ { ++ // >16MB ++ if((extadd == 0) && (offset >= GD_SFLASH_16M_SIZE)) ++ { ++ extadd = 1; ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ ++ /*issue a write command sequence to prepare the device for data to be written*/ ++ cmd_bit_set |= (device->commands->write_enable| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<commands->program_page| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_WRITE| /*write data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ SFLASH_TRANSFER_BYTE_NUM_4| /*transfer data number*/ ++ SFLASH_HOLD_TIME_100ns ++ ); ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ } ++ ++ sflash_set_data(*buffer++); ++ count++; ++ offset += 4; ++ ++ if((offset % device->page_bytes) == 0) ++ { ++ /* we are at a page boundary so we have to ++ wait until the WIP status to be cleared by the device*/ ++ result = sflash_wip_done_wait(device); ++ if( result != 0 ) ++ { ++ break; ++ } ++ count = 0; ++ } ++ } ++ ++ /*new added for the case that words < page_words*/ ++ //if(data_len < page_words) ++ { ++ result = sflash_wip_done_wait(device); ++ if(result != 0) ++ { ++ return(result); ++ } ++ } ++ ++ if(extadd) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ cmd_bit_set |= (device->commands->read_status| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (1<page_bytes / sizeof(u32); ++ ++ while(write_words--) ++ { ++ if(count == 0) ++ { ++ // >16MB ++ if((extadd == 0) && (offset >= GD_SFLASH_16M_SIZE)) ++ { ++ extadd = 1; ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ /* issue a write command sequence to prepare the device for data to be written*/ ++ cmd_bit_set |= (device->commands->write_enable| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /*dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<commands->program_page2| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /*dummy cycle*/ ++ SFLASH_RWN_WRITE| /*write data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_1| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_1| /*set the sflash data mode*/ ++ (0x1f<16MB ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ } ++ ++ sflash_set_data(*buffer++); ++ count++; ++ offset += 4; ++ ++ if((offset % device->page_bytes ) == 0) ++ { ++ /*we are at a page boundary so we have to ++ wait until the WIP status to be cleared by the device*/ ++ result = sflash_wip_done_wait(device); ++ if(result != 0) ++ { ++ break; ++ } ++ count = 0; ++ } ++ } ++ ++ /*new added for the case that words < page_words*/ ++ //if(data_len < page_words) ++ { ++ result = sflash_wip_done_wait(device); ++ if(result != 0) ++ { ++ return(result); ++ } ++ } ++ ++ if(extadd) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ cmd_bit_set |= (device->commands->read_status| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_CMD_MODE_1X| /*set the sflash cmd mode*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_1| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_1| /*set the sflash data mode*/ ++ (1<page_bytes / sizeof(u32); ++ ++ while(write_words--) ++ { ++ if(count == 0) ++ { ++ // >16MB ++ if((extadd == 0) && (offset >= GD_SFLASH_16M_SIZE)) ++ { ++ extadd = 1; ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ //if(device->manufacture_ID != 0x20) ++ // sflash_enable_io4(device); ++ /*issue a write command sequence to prepare the device for data to be written*/ ++ cmd_bit_set |= (device->commands->write_enable| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_4X; /*set the sflash cmd mode*/ ++ } ++ else if(device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_4X; /*set the sflash cmd mode*/ ++ } ++ else ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_1X; /*set the sflash cmd mode*/ ++ } ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ ++ cmd_bit_set |= (device->commands->program_page4| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_WRITE| /*write data*/ ++ SFLASH_DATA_CYCLE_NUM_2| /*set the sflash data mode*/ ++ (0x1f<manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_4X; /*set the sflash cmd mode*/ ++ } ++ else if (device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_4X; ++ } ++ else ++ { ++ cmd_bit_set |= SFLASH_CMD_MODE_1X; /*set the sflash cmd mode*/ ++ } ++ ++ ++ if(device->manufacture_ID == 0xc2) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_2; /*set the sflash adr mode*/ ++ } ++ else if(device->manufacture_ID == 0xbf) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_2; /*set the sflash adr mode*/ ++ } ++ else if(device->manufacture_ID == 0xef) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_0; /*set the sflash adr mode*/ ++ } ++ else if(device->manufacture_ID == 0x01) /*for FL064P;Tom.wang;2010-10-21*/ ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_0; /*set the sflash adr mode*/ ++ } ++ else if(device->manufacture_ID == 0x20) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_2; ++ } ++ else if(device->manufacture_ID == 0xc8) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_0; ++ } ++ else if(device->manufacture_ID == 0x1c) ++ { ++ cmd_bit_set |= SFLASH_ADDR_DUMMY_CYCLE_NUM_2; ++ } ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_set_data(offset); ++ } ++ ++ sflash_set_data(*buffer++); ++ count++; ++ offset += 4; ++ ++ if((offset % device->page_bytes) == 0) ++ { ++ //if(device->manufacture_ID != 0x20) ++ //sflash_disenable_io4(device); ++ /* we are at a page boundary so we have to ++ wait until the WIP status to be cleared by the device*/ ++ result = sflash_wip_done_wait(device); ++ if(result != 0) ++ { ++ break; ++ } ++ count = 0; ++ } ++ } ++ ++ //if(device->manufacture_ID != 0x20) ++ //{ ++ // sflash_disenable_io4(device); ++ //} ++ ++ /*new added for the case that words < page_words*/ ++ //if(data_len < page_words) ++ { ++ result = sflash_wip_done_wait(device); ++ if(result != 0) ++ { ++ return(result); ++ } ++ } ++ if(extadd) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ cmd_bit_set |= (device->commands->read_status| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_0| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_READ| /*read data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ (1<manufacture_ID == 0xbf) ++ { ++ /*set the sflash cmd mode, set the sflash data mode*/ ++ cmd_bit_set |= (SFLASH_CMD_MODE_4X|SFLASH_DATA_CYCLE_NUM_2); ++ } ++ else ++ { ++ /*set the sflash cmd mode, set the sflash data mode*/ ++ cmd_bit_set |= (SFLASH_CMD_MODE_1X|SFLASH_DATA_CYCLE_NUM_0); ++ } ++ ++ sflash_cmd_bit_set(&sflash_cmd,&cmd_bit_set); ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ ++ return(result); ++} ++ ++static int sflash_erase_chip(goke_sflash_dev_s* device) ++{ ++ goke_sflash_command_s sflash_cmd; ++ ulong CESetting = 0x38; ++ CESetting = CESetting | ((ulong)device->channel << 6); ++ sflash_set_ce(CESetting); ++ ++ if(old_feature == GOKE_SFLASH_FEATURE_IO4) ++ { ++ old_feature = GOKE_SFLASH_FEATURE_IO1; ++ if(device->manufacture_ID != 0x20) ++ { ++ sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ if( !device ) ++ return(EINVAL); ++ ++ ++ sflash_wip_done_wait(device); ++ ++ sflash_write_enable(device); ++ ++ sflash_cmd.bitc.code = device->commands->erase_chip; //command ++ sflash_cmd.bitc.data_num = 0x1f; ++ sflash_set_command( sflash_cmd.all ); ++ ++ sflash_wip_done_wait( device ); ++ ++ //sflash_write_disable(device); ++ ++ return 0; ++} ++ ++static int sflash_erase_sector(goke_sflash_dev_s* device, uint32_t offset) ++{ ++ u32 cmd_bit_set = 0; ++ goke_sflash_command_s sflash_cmd; ++ u32 result; ++ ulong CESetting = 0x38; ++ ++ if( !device ) ++ return(EINVAL); ++ ++ CESetting = CESetting | ((ulong)device->channel << 6); ++ sflash_set_ce(CESetting); ++ if( (offset + device->sector_bytes) > device->device_bytes ) ++ return(EINVAL); ++ ++ // >16MB ++ if(offset >= GD_SFLASH_16M_SIZE) ++ { ++ sflash_set_ext_addr(device, offset/GD_SFLASH_16M_SIZE); ++ } ++ if(old_feature == GOKE_SFLASH_FEATURE_IO4) ++ { ++ old_feature = GOKE_SFLASH_FEATURE_IO1; ++ if(device->manufacture_ID != 0x20) ++ { ++ sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ ++ sflash_write_enable(device); ++ ++ cmd_bit_set |= (device->commands->erase_sector| /*command*/ ++ SFLASH_SEND_CMD| /*transfer the command*/ ++ SFLASH_SEND_ADDR_BYTE_NUM_3| /*address num*/ ++ SFLASH_SEND_DUMMY_BYTE_NUM_0| /* dummy cycle*/ ++ SFLASH_RWN_NOTHING| /*no read/write data*/ ++ SFLASH_ADDR_DUMMY_CYCLE_NUM_0| /*set the sflash adr mode*/ ++ SFLASH_DATA_CYCLE_NUM_0| /*set the sflash data mode*/ ++ (0<= GD_SFLASH_16M_SIZE) ++ { ++ //restore to 0x00 ++ sflash_set_ext_addr(device, 0x00); ++ } ++ ++ sflash_cmd.bitc.code = device->commands->write_disable; /*command*/ ++ if(device->manufacture_ID == 0xbf) ++ { ++ sflash_cmd.bitc.cmd_mode = 2; /*set the sflash cmd mode*/ ++ } ++ else if(device->manufacture_ID == 0x1c) ++ { ++ sflash_cmd.bitc.cmd_mode = 0; ++ } ++ else ++ { ++ sflash_cmd.bitc.cmd_mode = 0; /*set the sflash cmd mode*/ ++ } ++ sflash_cmd.bitc.adr_num = 0; /*address num*/ ++ ++ sflash_set_command(sflash_cmd.all); ++ sflash_get_data(); ++ CESetting = CESetting & (~((ulong)device->channel << 6)); ++ sflash_set_ce(CESetting); ++ return(result); ++} ++ ++static goke_sflash_feature_e sflash_get_feature(goke_sflash_dev_s* device, goke_sflash_type_e type) ++{ ++ goke_sflash_feature_e feature = GOKE_SFLASH_FEATURE_IO1; ++ u8 temp = 0; ++ ++ if( !device ) ++ { ++ return feature; ++ } ++ if(type == GOKE_SFLASH_TYPE_READ) ++ { ++ temp = device->feature & 0x0F; ++ } ++ else ++ { ++ temp = (device->feature & 0xF0) >> 4; ++ } ++ switch(temp) ++ { ++ case 0x01: ++ feature = GOKE_SFLASH_FEATURE_IO1; ++ break; ++ case 0x02: ++ feature = GOKE_SFLASH_FEATURE_IO2; ++ break; ++ case 0x04: ++ feature = GOKE_SFLASH_FEATURE_IO4; ++ break; ++ default: ++ break; ++ } ++ return feature; ++} ++ ++static u32 sflash_cmd_bit_set(goke_sflash_command_s *sflashCmd, u32 *cmd_bit_set) ++{ ++ if(!sflashCmd) ++ { ++ return -1; ++ } ++ ++ sflashCmd->all = (*cmd_bit_set); ++ (*cmd_bit_set) = 0; ++ ++ return 0; ++} ++ ++static int sflash_write_iox( goke_sflash_dev_s* device, uint32_t address, ++ uint32_t* buffer, uint32_t words ) ++{ ++ goke_sflash_feature_e feature = GOKE_SFLASH_FEATURE_IO1; ++ uint32_t CESetting = 0x38; ++ uint32_t err = 0; ++ ++ feature = sflash_get_feature(device, GOKE_SFLASH_TYPE_WRITE); ++ ++ CESetting = CESetting | ((ulong)device->channel << 6); ++ sflash_set_ce(CESetting); ++ if(feature == GOKE_SFLASH_FEATURE_IO4) //support IO4 mode ++ { ++ sflash_set_ce(0x38 | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_enable_io4(device); /*enable the IO4 mode*/ ++ } ++ if(err != 0) ++ { ++ return err; ++ } ++ } ++ sflash_write_io4( device, address, buffer, words ); ++ } ++ else if( feature == GOKE_SFLASH_FEATURE_IO2) //support IO2 mode ++ { ++ sflash_set_ce(0x0E | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ sflash_write_io2( device, address, buffer, words ); ++ } ++ else ++ { ++ sflash_set_ce(0x0E | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ sflash_write_io1( device, address, buffer, words ); ++ } ++ ++ CESetting = CESetting & (~((ulong)device->channel << 6)); ++ sflash_set_ce(CESetting); ++ ++ return 0; ++} ++ ++static int sflash_read_iox( goke_sflash_dev_s* device, uint32_t address, ++ uint32_t* buffer, uint32_t words ) ++{ ++ goke_sflash_feature_e feature = GOKE_SFLASH_FEATURE_IO1; ++ uint32_t CESetting = 0x38; ++ uint32_t err = 0; ++ ++ feature = sflash_get_feature(device, GOKE_SFLASH_TYPE_READ); ++ CESetting = CESetting | ((ulong)device->channel << 6); ++ sflash_set_ce(CESetting); ++ ++ if(feature == GOKE_SFLASH_FEATURE_IO4) //support IO4 mode ++ { ++ sflash_set_ce(0x38 | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_enable_io4(device); /*enable the IO4 mode*/ ++ } ++ if(err != 0) ++ { ++ return err; ++ } ++ } ++ sflash_read_io4( device, address, buffer, words ); ++ } ++ else if( feature == GOKE_SFLASH_FEATURE_IO2) //support IO2 mode ++ { ++ sflash_set_ce(0x0E | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ sflash_read_io2( device, address, buffer, words ); ++ } ++ else ++ { ++ sflash_set_ce(0x0E | ((u32)device->channel << 6)); ++ if(old_feature != feature) ++ { ++ old_feature = feature; ++ if(device->manufacture_ID != 0x20) ++ { ++ err = sflash_disenable_io4(device); /*disable the IO4 mode*/ ++ } ++ } ++ sflash_read_io1( device, address, buffer, words ); ++ } ++ ++ CESetting = CESetting & (~((ulong)device->channel << 6)); ++ sflash_set_ce(CESetting); ++ return err; ++} ++ ++/* ++ * Write an address range to the flash chip. Data must be written in ++ * FLASH_PAGESIZE chunks. The address range may be any size provided ++ * it is within the physical boundaries. ++ */ ++static int mtd_flash_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct gk_sflash *flash = mtd_to_gk_flash(mtd); ++ ++ uint32_t addr,left,align_data; ++ uint32_t *wptr = NULL; ++ ++ if (!flash) ++ return -EINVAL; ++ ++ if( !(flash->device) ) ++ return -EINVAL; ++ ++ if (retlen) ++ *retlen = 0; ++ ++ /* sanity checks */ ++ if (!len) ++ return(0); ++ ++ if (to + len > flash->mtd.size) ++ return -EINVAL; ++ ++ mutex_lock(&flash->lock); ++ ++ addr = to; ++ wptr = (uint32_t*)buf; ++ left = len % (sizeof(uint32_t)); ++#if GD_SFLASH_USE_BUFFER ++ if(((addr>=flash->device->offset) && (addr<(flash->device->offset+flash->device->buffer_size))) || ++ (((addr+len)>=flash->device->offset) && ((addr+len)<(flash->device->offset+flash->device->buffer_size)))) ++ { ++ flash->device->offset = 0xFFFFFFFF; ++ //printk("[%s %d] 0x%08x 0x%08x 0x%08x\n", __func__, __LINE__, flash->device->offset, addr, len); ++ } ++#endif ++ ++ sflash_write_iox( flash->device, addr, wptr, len / (sizeof(uint32_t)) ); ++ ++ if(left > 0) ++ { ++ sflash_read_iox( flash->device, addr + (len - left), &align_data, 1 ); ++ memcpy( (u_char*)&align_data, buf + (len - left), left ); ++ sflash_write_iox( flash->device, addr + (len - left), &align_data, 1); ++ } ++ ++ *retlen = len; ++ ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++} ++ ++/* ++ * Read an address range from the flash chip. The address range ++ * may be any size provided it is within the physical boundaries. ++ */ ++static int mtd_flash_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct gk_sflash *flash = mtd_to_gk_flash(mtd); ++ ++ unsigned int addr; ++ unsigned int end; ++ unsigned int off_set = 0; ++#if GD_SFLASH_USE_BUFFER ++ unsigned int left_bytes; ++#else ++ unsigned char buffer[256 + 10]; ++ unsigned int rd_pages = 0; ++ unsigned int cnt; ++ unsigned int start_addr; ++ unsigned int p_start, p_end; ++#endif ++ ++ if (!flash) ++ return -EINVAL; ++ ++ if( !(flash->device) ) ++ return -EINVAL; ++ ++ /* sanity checks */ ++ if (!len) ++ return 0; ++ ++ if (from + len > flash->mtd.size) ++ return -EINVAL; ++ ++ /* Byte count starts at zero. */ ++ if (retlen) ++ *retlen = 0; ++ ++ mutex_lock(&flash->lock); ++ addr = from; ++ off_set = 0; ++ end = addr + len; ++#if GD_SFLASH_USE_BUFFER ++ if((len >= flash->device->buffer_size) && ((addr%4) == 0x00) && ((len%4) == 0x00) && (((u32)buf%4) == 0x00)) ++ { ++ sflash_read_iox(flash->device, addr, (uint32_t*)buf, len / 4); ++ *retlen = len; ++ mutex_unlock(&flash->lock); ++ return 0; ++ } ++ ++ if((addr>=flash->device->offset) && (addr<(flash->device->offset+flash->device->buffer_size))) ++ { ++ } ++ else ++ { ++ flash->device->offset = addr - (addr % flash->device->buffer_size); ++ sflash_read_iox(flash->device, flash->device->offset, (uint32_t*)flash->device->buffer, flash->device->buffer_size / 4); ++ } ++ do ++ { ++ if((addr>=flash->device->offset) && (addr<(flash->device->offset+flash->device->buffer_size))) ++ { ++ left_bytes = flash->device->buffer_size - (addr - flash->device->offset); ++ if(left_bytes >= len) ++ { ++ memcpy(buf + off_set, flash->device->buffer + (addr - flash->device->offset), len); ++ *retlen = len; ++ mutex_unlock(&flash->lock); ++ return 0; ++ } ++ memcpy(buf + off_set, flash->device->buffer + (addr - flash->device->offset), left_bytes); ++ off_set += left_bytes; ++ len -= left_bytes; ++ addr += left_bytes; ++ sflash_read_iox(flash->device, flash->device->offset+flash->device->buffer_size, (uint32_t*)flash->device->buffer, flash->device->buffer_size / 4); ++ flash->device->offset += flash->device->buffer_size; ++ } ++ }while(1); ++#else ++ ++ if(((addr%4) == 0x00) && ((len%4) == 0x00) && (((u32)buf%4) == 0x00)) ++ { ++ sflash_read_iox( flash->device, addr, (uint32_t*)buf, len / 4); ++ mutex_unlock(&flash->lock); ++ *retlen = len; ++ return 0; ++ } ++ if (addr%256 == 0) { ++ start_addr = addr; ++ } else { ++ start_addr = addr - (addr % 256); ++ } ++ ++ if (addr%256 != 0) { ++ if ((addr + len) > (start_addr + 256)) { ++ p_start = start_addr + 256; ++ rd_pages += 1; ++ } else { ++ p_start = start_addr; ++ } ++ ++ } else { ++ p_start = start_addr; ++ } ++ ++ if (end%256 != 0) { ++ rd_pages += 1; ++ p_end = end - (end%256); ++ } else { ++ p_end = end; ++ } ++ ++ rd_pages += (p_end - p_start) / 256; ++ ++ //printk("\n\nread addr : 0x%08x, start : 0x%08x, len : %d, rd_pages : %d, p_start : 0x%x, p_end : 0x%x\n", addr, start_addr, len, rd_pages, p_start, p_end); ++ ++ for (cnt = 0; cnt < rd_pages;) { ++ sflash_read_iox( flash->device, start_addr + cnt*256, (uint32_t*)buffer, 64); ++ if (cnt == 0) { ++ if (addr + len < start_addr + 256) { ++ memcpy(buf + off_set, buffer + (addr % 256), len); ++ off_set += len; ++ } else { ++ memcpy(buf + off_set, buffer + (addr % 256), 256 - addr%256); ++ off_set += (256 - addr%256); ++ } ++ ++ //printk("cnt : %d, offset : %d\n", cnt, off_set); ++ } else if (cnt == (rd_pages - 1)) { ++ if (end % 256 == 0) { ++ memcpy(buf + off_set, buffer, 256); ++ off_set += 256; ++ } else { ++ memcpy(buf + off_set, buffer, end % 256); ++ off_set += (end % 256); ++ } ++ //printk("cnt : %d, offset : %d\n", cnt, off_set); ++ } else { ++ memcpy(buf + off_set, buffer, 256); ++ off_set += 256; ++ //printk("cnt : %d, offset : %d, read num : %d\n", cnt, off_set, 256); ++ } ++ ++ cnt++; ++ } ++ ++#endif ++ ++ *retlen = len; ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++ ++} ++ ++/* ++ * Erase an address range on the flash chip. The address range may extend ++ * one or more erase sectors. Return an error is there is a problem erasing. ++ */ ++static int mtd_flash_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct gk_sflash *flash = mtd_to_gk_flash(mtd); ++ uint32_t addr,len; ++ uint32_t rem; ++ ++ if( !flash) ++ return -EINVAL; ++ ++ if( !(flash->device) ) ++ return -EINVAL; ++ ++ /* sanity checks */ ++ if (instr->addr + instr->len > flash->mtd.size) ++ return -EINVAL; ++ ++ div_u64_rem(instr->len, mtd->erasesize, &rem); ++ if (rem) ++ return -EINVAL; ++ ++ addr = instr->addr; ++ len = instr->len; ++ ++ //printk("erase, addr : 0x%08x, len : %d\n", addr, len); ++ ++ mutex_lock(&flash->lock); ++#if GD_SFLASH_USE_BUFFER ++ if(((addr>=flash->device->offset) && (addr<(flash->device->offset+flash->device->buffer_size))) || ++ (((addr+len)>=flash->device->offset) && ((addr+len)<(flash->device->offset+flash->device->buffer_size)))) ++ { ++ flash->device->offset = 0xFFFFFFFF; ++ //printk("[%s %d] 0x%08x 0x%08x 0x%08x\n", __func__, __LINE__, flash->device->offset, addr, len); ++ } ++#endif ++ ++ /* whole-chip erase? */ ++ if (len == flash->mtd.size) ++ { ++ if (sflash_erase_chip(flash->device)) ++ { ++ instr->state = MTD_ERASE_FAILED; ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++ /* REVISIT in some cases we could speed up erasing large regions ++ * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up ++ * to use "small sector erase", but that's not always optimal. ++ */ ++ ++ /* "sector"-at-a-time erase */ ++ } ++ else ++ { ++ while (len) ++ { ++ if (sflash_erase_sector(flash->device, addr)) ++ { ++ instr->state = MTD_ERASE_FAILED; ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++ addr += mtd->erasesize; ++ len -= mtd->erasesize; ++ } ++ } ++ ++ mutex_unlock(&flash->lock); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++ ++} ++ ++ ++static int gk_flash_probe(struct platform_device *dev) ++{ ++ struct gk_sflash *flash; ++ goke_sflash_dev_s *chip_info; ++ struct mtd_part_parser_data ppdata; ++ struct sflash_platform_data *data = dev->dev.platform_data; ++ unsigned i; ++ int ret; ++ ++ chip_info = jedec_probe(dev); ++ ++ if (!chip_info){ ++ printk(KERN_ERR "detect sflash fail\n"); ++ return -ENODEV; ++ } ++ ++ flash = kzalloc(sizeof *flash, GFP_KERNEL); ++ if (!flash) ++ return -ENOMEM; ++ ++ flash->device = chip_info; ++ mutex_init(&flash->lock); ++ platform_set_drvdata(dev, flash); ++ ++ flash->mtd.name = dev->name; ++ ++ flash->mtd.type = MTD_NORFLASH; ++ flash->mtd.writesize = 1; ++ flash->mtd.flags = MTD_CAP_NORFLASH; ++ flash->mtd.size = chip_info->device_bytes; ++ flash->mtd._erase = mtd_flash_erase; ++ flash->mtd._read = mtd_flash_read; ++ flash->mtd._write = mtd_flash_write; ++ ++ flash->mtd.erasesize = chip_info->sector_bytes; ++ ++ ppdata.of_node = dev->dev.of_node; ++ flash->mtd.dev.parent = &dev->dev; ++ flash->mtd.writebufsize = chip_info->page_bytes; ++ ++ dev_info(&dev->dev, "%s (%lld Kbytes)\n", chip_info->device_name, ++ (long long)flash->mtd.size >> 10); ++ ++ if (flash->mtd.numeraseregions) ++ for (i = 0; i < flash->mtd.numeraseregions; i++) ++ printk("mtd.eraseregions[%d] = { .offset = 0x%llx, " ++ ".erasesize = 0x%.8x (%uKiB), " ++ ".numblocks = %d }\n", ++ i, (long long)flash->mtd.eraseregions[i].offset, ++ flash->mtd.eraseregions[i].erasesize, ++ flash->mtd.eraseregions[i].erasesize / 1024, ++ flash->mtd.eraseregions[i].numblocks); ++ ++ /* partitions should match sector boundaries; and it may be good to ++ * use readonly partitions for writeprotected sectors (BP2..BP0). ++ */ ++ ret = mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ data ? data->parts : NULL, ++ data ? data->nr_parts : 0); ++ // printk(KERN_ERR "sflash dev_t = 0x%x\n", flash->mtd.dev.devt); ++ ++ return ret; ++} ++ ++ ++static int gk_flash_remove(struct platform_device *dev) ++{ ++ struct gk_sflash *flash = platform_get_drvdata(dev); ++ int status; ++ ++ /* Clean up MTD stuff. */ ++ status = mtd_device_unregister(&flash->mtd); ++ if (status == 0) { ++ kfree(flash); ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static struct of_device_id match_table[] = { ++ { .compatible = "mxic,mx25l12845e" }, ++ { .compatible = "spansion,s25fl128p" }, ++ { } /* end */ ++}; ++#else /* CONFIG_OF */ ++#define match_table NULL ++ ++#endif /* !CONFIG_OF */ ++ ++static struct platform_driver gk_flash_driver = ++{ ++ .driver = ++ { ++ .name = "gk_flash", ++ .owner = THIS_MODULE, ++ .of_match_table = match_table, ++ }, ++ .probe = gk_flash_probe, ++ .remove = gk_flash_remove, ++}; ++ ++ ++#ifdef CONFIG_OF ++module_platform_driver(gk_flash_driver); ++#else /* CONFIG_OF */ ++static int gk_flash_init(void) ++{ ++ int retval = 0; ++ ++// printk(KERN_ERR "sflash pa = 0x%x, va = 0x%x\n",(unsigned int)GK_PA_SFLASH ,(unsigned int)GK_VA_SFLASH); ++ ++ retval = platform_driver_register(&gk_flash_driver); ++// printk(KERN_ERR "sflash init ret = %d\n", retval); ++ ++ return retval; ++} ++ ++static void gk_flash_exit(void) ++{ ++ platform_driver_unregister(&gk_flash_driver); ++} ++ ++ ++module_init(gk_flash_init); ++module_exit(gk_flash_exit); ++#endif /* !CONFIG_OF */ ++ ++MODULE_DESCRIPTION("GOKE MTD serial flash driver for MTD"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/mtd/devices/gk_sflash_v1_00.h b/drivers/mtd/devices/gk_sflash_v1_00.h +new file mode 100644 +index 00000000..cc6bb20a +--- /dev/null ++++ b/drivers/mtd/devices/gk_sflash_v1_00.h +@@ -0,0 +1,237 @@ ++/* ++ * drivers/mtd/devices/gk_sflash_v1_v00.h ++ * ++ * gk soc ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++ ++ ++#include ++#include ++#include ++ ++/* send cmd or not [ 8]*/ ++#define SFLASH_SEND_CMD 0x00000100 ++#define SFLASH_NO_SEND_CMD 0x00000000 ++ ++/* byte number of address to send [11:9]*/ ++#define SFLASH_SEND_ADDR_BYTE_NUM_0 0x00000000 ++#define SFLASH_SEND_ADDR_BYTE_NUM_1 0x00000200 ++#define SFLASH_SEND_ADDR_BYTE_NUM_2 0x00000400 ++#define SFLASH_SEND_ADDR_BYTE_NUM_3 0x00000600 ++#define SFLASH_SEND_ADDR_BYTE_NUM_4 0x00000800 ++#define SFLASH_SEND_ADDR_BYTE_NUM_5 0x00000a00 ++#define SFLASH_SEND_ADDR_BYTE_NUM_6 0x00000c00 ++#define SFLASH_SEND_ADDR_BYTE_NUM_7 0x00000e00 ++ ++/*Byte number of dummy cycle to send [14:12]*/ ++ ++#define SFLASH_SEND_DUMMY_BYTE_NUM_0 0x000000000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_1 0x000001000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_2 0x000002000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_3 0x000003000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_4 0x000004000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_5 0x000005000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_6 0x000006000 ++#define SFLASH_SEND_DUMMY_BYTE_NUM_7 0x000007000 ++ ++/* Command operation[16:15]: 00 for read data from SF; 01 for write data to SF; 11 for nothing to do */ ++ ++#define SFLASH_RWN_READ 0x00000000 ++#define SFLASH_RWN_WRITE 0x00008000 ++#define SFLASH_RWN_NOTHING 0x00018000 ++ ++/*I/O mode of command cycle to SF[18:17]: 00 for x1; 01 for x2; 10 for x4*/ ++#define SFLASH_CMD_MODE_1X 0x00000000 ++#define SFLASH_CMD_MODE_2X 0x00020000 ++#define SFLASH_CMD_MODE_4X 0x00040000 ++ ++/* I/O mode of address and dummy cycle to SF[20:19]*/ ++#define SFLASH_ADDR_DUMMY_CYCLE_NUM_0 0x00000000 ++#define SFLASH_ADDR_DUMMY_CYCLE_NUM_1 0x00080000 ++#define SFLASH_ADDR_DUMMY_CYCLE_NUM_2 0x00100000 ++#define SFLASH_ADDR_DUMMY_CYCLE_NUM_3 0x00180000 ++ ++/*I/O mode of data cycle to or from SF [22:21] */ ++ ++#define SFLASH_DATA_CYCLE_NUM_0 0x00000000 ++#define SFLASH_DATA_CYCLE_NUM_1 0x00200000 ++#define SFLASH_DATA_CYCLE_NUM_2 0x00400000 ++#define SFLASH_DATA_CYCLE_NUM_3 0x00600000 ++ ++/*Transfer data byte number to or from SF[27:23]. For 11111 case, transfer 4bytes per request. For other case, transfer number bytes.*/ ++ ++#define SFLASH_TRANSFER_BYTE_NUM_4 0x0f800000 ++#define SFLASH_TRANSFER_BYTE_LOC 23 ++ ++#define SFLASH_HOLD_TIME_100ns 0x00000000 ++#define SFLASH_HOLD_TIME_3us 0x10000000 ++#define SFLASH_HOLD_TIME_100us 0x20000000 ++ ++#define GD_SFLASH_1X_READ 0x01 ++#define GD_SFLASH_2X_READ 0x02 ++#define GD_SFLASH_4X_READ 0x04 ++#define GD_SFLASH_1X_WRITE 0x10 ++#define GD_SFLASH_2X_WRITE 0x20 ++#define GD_SFLASH_4X_WRITE 0x40 ++ ++#define GD_SFLASH_16M_SIZE 0x1000000 ++ ++/*----------------------------------------------------------------------------*/ ++/* bit group structures */ ++/*----------------------------------------------------------------------------*/ ++typedef union { /* SFLASH_Command */ ++ u32 all; ++ struct { ++ u32 code : 8; ++ u32 send_cmd : 1; ++ u32 adr_num : 3; ++ u32 dummy_num : 3; ++ u32 rwn : 2; ++ u32 cmd_mode : 2; ++ u32 adr_mode : 2; ++ u32 data_mode : 2; ++ u32 data_num : 5; ++ u32 hold_time : 2; ++ u32 : 2; ++ } bitc; ++} goke_sflash_command_s; ++ ++typedef union { /* SFLASH_CE */ ++ u32 all; ++ struct { ++ u32 ce : 1; ++ u32 wp : 1; ++ u32 hold : 1; ++ u32 ce_mode : 1; ++ u32 wp_mode : 1; ++ u32 hold_mode : 1; ++ u32 ch_select : 1; ++ u32 : 25; ++ } bitc; ++} goke_sflash_ce_s; ++ ++typedef union { /* SFLASH_Speed */ ++ u32 all; ++ struct { ++ u32 sf_sclk_sel : 3; ++ u32 : 29; ++ } bitc; ++} goke_sflash_speed_s; ++ ++typedef union { /* SFLASH_PARA_XIP */ ++ u32 all; ++ struct { ++ u32 sflash_command : 8; ++ u32 : 1; ++ u32 adr_num : 3; ++ u32 dummy_num : 3; ++ u32 : 2; ++ u32 cmd_mod : 2; ++ u32 adr_mod : 2; ++ u32 data_mod : 2; ++ u32 : 1; ++ u32 dumy_data : 8; ++ } bitc; ++} goke_sflash_para_xip_s; ++ ++/*-------------------------------------------------------------------------------*/ ++/* \brief Flash channel number. */ ++/*-------------------------------------------------------------------------------*/ ++ ++typedef enum ++{ ++ GOKE_SFLASH_CHANNEL_0 = 0, ++ GOKE_SFLASH_CHANNEL_1, ++ GOKE_SFLASH_CHANNEL_NUM ++}goke_sflash_channel_e; ++ ++/*-------------------------------------------------------------------------------*/ ++/* \brief Flash I/O feature. */ ++/*-------------------------------------------------------------------------------*/ ++ ++typedef enum ++{ ++ GOKE_SFLASH_FEATURE_IO1 = 0, ++ GOKE_SFLASH_FEATURE_IO2, ++ GOKE_SFLASH_FEATURE_IO4 ++}goke_sflash_feature_e; ++ ++/*-------------------------------------------------------------------------------*/ ++/* \brief Flash feature type. */ ++/*-------------------------------------------------------------------------------*/ ++ ++typedef enum ++{ ++ GOKE_SFLASH_TYPE_READ = 0, ++ GOKE_SFLASH_TYPE_WRITE ++}goke_sflash_type_e; ++ ++/*-------------------------------------------------------------------------------*/ ++/* serial flash specific commands and statis register bit definitions */ ++/*-------------------------------------------------------------------------------*/ ++ ++typedef struct ++{ ++ u8 read_ID; /*!< command to read the chip identification*/ ++ u8 write_enable; /*!< command to enable a write/erase sequence*/ ++ u8 write_disable; /*!< command to disable a write/erase sequence*/ ++ u8 read_status; /*!< command to read from status register*/ ++ u8 write_status; /*!< command to write to status register*/ ++ u8 read_data; /*!< command to read data*/ ++ u8 read_data_fast; /*!< command to read data in fast mode*/ ++ u8 erase_sector; /*!< command to erase a single sector*/ ++ u8 erase_chip; /*!< command to erase the entire chip*/ ++ u8 program_page; /*!< command to program a sector page*/ ++ u32 status_mask_wip; /*!< status register mask for bit write-in-progress*/ ++ u32 status_mask_wel; /*!< status register mask for bit write-enable-latch*/ ++ u8 read_io2; /*!< command to read data by IO2*/ ++ u8 read_io4; /*!< command to read data by IO4*/ ++ u8 program_page2; /*!< command to program a sector page by IO2*/ ++ u8 program_page4; /*!< command to program a sector page by IO4*/ ++ u8 read_ext_addr; /*!< command to read the extenden address*/ ++ u8 write_ext_addr; /*!< command to write the extenden address*/ ++ u8 read_status2; /*!< command to read from status2 register*/ ++}goke_sflash_cmd_s; ++ ++/*-------------------------------------------------------------------------------*/ ++/* serial flash specific geometry and information data structure */ ++/*-------------------------------------------------------------------------------*/ ++ ++typedef struct ++{ ++ u8 manufacture_ID; /*!< Manufacture identification*/ ++ u16 device_ID; /*!< Device identification (memory type/capacity)*/ ++ char* manufacture_name; /*!< Pointer to manufacture name*/ ++ char* device_name; /*!< Pointer to device name*/ ++ u32 device_bytes; /*!< Size of flash device in bytes*/ ++ u32 sector_count; /*!< Number of sectors*/ ++ u32 sector_bytes; /*!< Size of a single flash sector in bytes*/ ++ u32 sector_pages; /*!< Number of pages per sector*/ ++ u32 page_bytes; /*!< Size of a programmable page in bytes*/ ++ const goke_sflash_cmd_s* commands; /*!< Device specific access commands*/ ++ u32 feature; /*! ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "gk_spinand_v1_00.h" ++#include "spinand.h" ++ ++#if 1 ++#define uswap_32(x) x ++#else ++#define uswap_32(x) \ ++ ((((x) & 0xff000000) >> 24) | \ ++ (((x) & 0x00ff0000) >> 8) | \ ++ (((x) & 0x0000ff00) << 8) | \ ++ (((x) & 0x000000ff) << 24)) ++#endif ++ ++#define gk_spi_nand_driver_version "GK-MTD_01.00_Linux3.4.43_20150115" ++ ++ ++#define BAD_BLOCK 0 ++#define BAD_BLOCK_OFF 0x00 ++ ++struct gk_spinand_host { ++ struct spinand_chip chip; ++ struct mtd_info mtd; ++ ++ /* page size of attached chip */ ++ unsigned int page_size; ++ int use_ecc; ++ int cs; ++ ++ void __iomem *io_base; ++ struct device *dev; ++ struct completion comp; ++ struct mutex lock; ++}; ++ ++/******************************************************/ ++/* SPI Nand Part ( Hardware Dependent ) */ ++/******************************************************/ ++ ++/** ++ OOB area specification layout: Total available free bytes. ++*/ ++static struct nand_ecclayout spinand_ecc_64_layout_gd = { ++ .eccbytes = 16, ++ .eccpos = { 0x0c, 0x0d, 0x0e, 0x0f, ++ 0x1c, 0x1d, 0x1e, 0x1f, ++ 0x2c, 0x2d, 0x2e, 0x2f, ++ 0x3c, 0x3d, 0x3e, 0x3f,}, ++ .oobavail = 32, ++ .oobfree = { ++ {.offset = 0x04, .length = 8}, ++ {.offset = 0x14, .length = 8}, ++ {.offset = 0x24, .length = 8}, ++ {.offset = 0x34, .length = 8}, ++ } ++}; ++ ++static struct nand_ecclayout spinand_ecc_64_layout_esmt = { ++ .eccbytes = 28, ++ .eccpos = { 0x01, 0x02, 0x03, ++ 0x04, 0x05, 0x06, 0x07, ++ 0x11, 0x12, 0x13, ++ 0x14, 0x15, 0x16, 0x17, ++ 0x21, 0x22, 0x23, ++ 0x24, 0x25, 0x26, 0x27, ++ 0x31, 0x32, 0x33, ++ 0x34, 0x35, 0x36, 0x37,}, ++ .oobavail = 32, ++ .oobfree = { ++ {.offset = 0x08, .length = 8}, ++ {.offset = 0x18, .length = 8}, ++ {.offset = 0x28, .length = 8}, ++ {.offset = 0x38, .length = 8}, ++ } ++}; ++ ++static struct nand_ecclayout spinand_ecc_64_layout_ato = { ++ .eccbytes = 20, ++ .eccpos = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, ++ 0x28, 0x29, 0x2a, 0x2b, 0x2c, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c,}, ++ .oobavail = 0, ++ .oobfree = { ++ {.offset = 0x04, .length = 8}, ++ {.offset = 0x14, .length = 8}, ++ {.offset = 0x24, .length = 8}, ++ {.offset = 0x34, .length = 8}, ++ } ++}; ++ ++static struct nand_ecclayout spinand_ecc_64_layout_wb = { ++ .eccbytes = 24, ++ .eccpos = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, ++ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d,}, ++ .oobavail = 8, ++ .oobfree = { ++ {.offset = 0x02, .length = 2}, ++ {.offset = 0x12, .length = 2}, ++ {.offset = 0x22, .length = 2}, ++ {.offset = 0x32, .length = 2}, ++ } ++}; ++ ++/** ++ SPI Nand command set. ++*/ ++spinand_cmd_t spinand_commands_gd = ++{ ++ /* writeEnable */ 0x06, ++ /* writeDisable */ 0x04, ++ /* getFeatures */ 0x0f, ++ /* setFeatures */ 0x1f, ++ /* pageRead */ 0x13, ++ /* readCache */ 0x0b, //0x03 ++ /* readCacheX2 */ 0x3b, ++ /* readCacheX4 */ 0x6b, ++ /* readCacheIO2 */ 0xbb, ++ /* readCacheIO4 */ 0xeb, ++ /* readID */ 0x9f, ++ /* programLoad */ 0x02, ++ /* programLoadX4 */ 0x32, ++ /* progExecute */ 0x10, ++ /* progLoadRand */ 0x84, ++ /* progLoadRandX4 */ 0xc4, ++ /* progLoadRandIO2 */ 0x72, ++ /* blockErase */ 0xd8, ++ /* reset */ 0xff ++}; ++ ++spinand_cmd_t spinand_commands_esmt = ++{ ++ /* writeEnable */ 0x06, ++ /* writeDisable */ 0x04, ++ /* getFeatures */ 0x0f, ++ /* setFeatures */ 0x1f, ++ /* pageRead */ 0x13, ++ /* readCache */ 0x0b, //0x03 ++ /* readCacheX2 */ 0x3b, ++ /* readCacheX4 */ 0x6b, ++ /* readCacheIO2 */ 0xbb, ++ /* readCacheIO4 */ 0xeb, ++ /* readID */ 0x9f, ++ /* programLoad */ 0x02, ++ /* programLoadX4 */ 0x32, ++ /* progExecute */ 0x10, ++ /* progLoadRand */ 0x84, ++ /* progLoadRandX4 */ 0x34, ++ /* progLoadRandIO2 */ 0x72, ++ /* blockErase */ 0xd8, ++ /* reset */ 0xff ++}; ++ ++spinand_cmd_t spinand_commands_ato = ++{ ++ /* writeEnable */ 0x06, ++ /* writeDisable */ 0x04, ++ /* getFeatures */ 0x0f, ++ /* setFeatures */ 0x1f, ++ /* pageRead */ 0x13, ++ /* readCache */ 0x0b, //0x03 ++ /* readCacheX2 */ 0x3b, //not supported ++ /* readCacheX4 */ 0x6b, ++ /* readCacheIO2 */ 0xbb, //not supported ++ /* readCacheIO4 */ 0xeb, //not supported ++ /* readID */ 0x9f, ++ /* programLoad */ 0x02, ++ /* programLoadX4 */ 0x32, ++ /* progExecute */ 0x10, ++ /* progLoadRand */ 0x84, ++ /* progLoadRandX4 */ 0x34, ++ /* progLoadRandIO2 */ 0x72, //not supported ++ /* blockErase */ 0xd8, ++ /* reset */ 0xff ++}; ++ ++spinand_cmd_t spinand_commands_wb = ++{ ++ /* writeEnable */ 0x06, ++ /* writeDisable */ 0x04, ++ /* getFeatures */ 0x0f, ++ /* setFeatures */ 0x1f, ++ /* pageRead */ 0x13, ++ /* readCache */ 0x0b, //0x03 ++ /* readCacheX2 */ 0x3b, ++ /* readCacheX4 */ 0x6b, ++ /* readCacheIO2 */ 0xbb, ++ /* readCacheIO4 */ 0xeb, ++ /* readID */ 0x9f, ++ /* programLoad */ 0x02, ++ /* programLoadX4 */ 0x32, ++ /* progExecute */ 0x10, ++ /* progLoadRand */ 0x84, ++ /* progLoadRandX4 */ 0x34, ++ /* progLoadRandIO2 */ 0x72, ++ /* blockErase */ 0xd8, ++ /* reset */ 0xff ++}; ++ ++static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; ++ ++static struct nand_bbt_descr badblock_ptn_gd = { ++ .options = 0, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern, ++}; ++ ++static struct nand_bbt_descr badblock_ptn_esmt = { ++ .options = NAND_BBT_SCAN2NDPAGE, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern, ++}; ++ ++static struct nand_bbt_descr badblock_ptn_ato = { ++ .options = 0, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern, ++}; ++ ++static struct nand_bbt_descr badblock_ptn_wb = { ++ .options = 0, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern, ++}; ++ ++/* ++******************************************************************************* ++** ++** gd_sflash_devices_supported is an array containing serial flash ++** geometry and information data of all supported devices, it will ++** be used during GD_SFLASH_Init() to find the connected serial ++** flash decive ++** ++******************************************************************************* ++*/ ++struct spinand_info spinand_devices_supported[] = ++{ ++ { ++ /* manufactureID */ 0xC8, ++ /* deviceID */ 0xF1, ++ /* manufactureName */ "GigaDevice", ++ /* deviceName */ "GD5F1GQ4UAYIG", ++ /* nand_size */ (1024 * (2048 + 64) * 64), ++ /* usable_size */ (1024 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 1024, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_gd, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_gd, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_gd ++ }, ++ { ++ /* manufactureID */ 0xC8, ++ /* deviceID */ 0xF2, ++ /* manufactureName */ "GigaDevice", ++ /* deviceName */ "GD5F2GQ4UAYIG", ++ /* nand_size */ (2048 * (2048 + 64) * 64), ++ /* usable_size */ (2048 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 2048, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_gd, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_gd, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_gd ++ }, ++ { ++ /* manufactureID */ 0xC8, ++ /* deviceID */ 0xF4, ++ /* manufactureName */ "GigaDevice", ++ /* deviceName */ "GD5F4GQ4UAYIG", ++ /* nand_size */ (4096 * (2048 + 64) * 64), ++ /* usable_size */ (4096 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 4096, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_gd, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_gd, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_gd ++ }, ++ { ++ /* manufactureID */ 0xC8, ++ /* deviceID */ 0x20, ++ /* manufactureName */ "ESMT", ++ /* deviceName */ "F50L512M41A", ++ /* nand_size */ (512 * (2048 + 64) * 64), ++ /* usable_size */ (512 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 512, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_esmt, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_esmt, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_esmt ++ }, ++ { ++ /* manufactureID */ 0x9b, ++ /* deviceID */ 0x12, ++ /* manufactureName */ "ATO", ++ /* deviceName */ "ATO25D1GA", ++ /* nand_size */ (1024 * (2048 + 64) * 64), ++ /* usable_size */ (1024 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 1024, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_ato, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_ato, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_ato ++ }, ++ { ++ /* manufactureID */ 0xEF, ++ /* deviceID */ 0xAA21, ++ /* manufactureName */ "Winbond", ++ /* deviceName */ "W25N01GV", ++ /* nand_size */ (1024 * (2048 + 64) * 64), ++ /* usable_size */ (1024 * 2048 * 64), ++ /* block_size */ ((2048 + 64) * 64), ++ /* block_main_size */ (2048 * 64), ++ /* block_per_chip */ 1024, ++ /* page_size */ (2048 + 64), ++ /* page_main_size */ 2048, ++ /* page_spare_size */ 64, ++ /* page_per_block */ 64, ++ /* block_shift */ 17, ++ /* block_mask */ 0x1ffff, ++ /* page_shift */ 11, ++ /* page_mask */ 0x7ff, ++ /* commands */ &spinand_commands_wb, ++ /* feature */ SPINAND_1X_WRITE | SPINAND_4X_READ, ++ /* channel */ 1, ++ /* nand_ecclayout */ &spinand_ecc_64_layout_wb, ++ /* badblockbits */ 8, ++ /* badblock_pattern */ &badblock_ptn_wb ++ }, ++}; ++ ++struct gk_spinand_platform_data ++{ ++ uint32_t speed_mode; ++ uint32_t channel; ++ struct mtd_partition *parts; ++ unsigned int nr_parts; ++}; ++ ++static struct mtd_partition gk_spinand_partitions[ ] = { ++ [0] = { ++ .name = "uboot", ++ .offset = 0, ++ .size = SZ_1M, ++ }, ++ [1] = { ++ .name = "uboot-env", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_1M, ++ }, ++ [2] = { ++ .name = "user", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_4M, ++ }, ++ [3] = { ++ .name = "config", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_1M, ++ }, ++ [4] = { ++ .name = "kernel", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_4M, ++ }, ++ [5] = { ++ .name = "rootfs", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_4M * 28, // 1g bit nand sflash ++ }, ++ [6] = { ++ .name = "resource", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = SZ_4M, ++ }, ++}; ++ ++#define NUM_PARTITIONS (ARRAY_SIZE(gk_spinand_partitions)) ++ ++static int gk_spinand_set_channel(struct spinand_info *info) ++{ ++ uint32_t ce_setting = 0; ++ uint32_t new_ce_setting = 0; ++ ++ if( info && info->mid) ++ { ++ ce_setting = spinand_get_ce(); ++ new_ce_setting = (ce_setting & ~(1 << 6)) | ((uint32_t)info->channel << 6); ++ if(ce_setting != new_ce_setting) ++ { ++ spinand_set_ce_chselect((uint8_t)info->channel); ++ } ++ return 0; ++ } ++ return -EINVAL; ++} ++ ++static int gk_spinand_release_channel(struct spinand_info *info) ++{ ++ uint32_t ce_setting = 0; ++ uint32_t new_ce_setting = 0; ++ ++ if( info && info->mid) ++ { ++ ce_setting = spinand_get_ce(); ++ new_ce_setting = ce_setting & (~((uint32_t)info->channel << 6)); ++ if(ce_setting != new_ce_setting) ++ { ++ spinand_set_ce_chselect(!((uint8_t)info->channel)); ++ } ++ return 0; ++ } ++ return -EINVAL; ++} ++/** ++ * gk_spinand_write_enable - send command 0x06 to enable write or erase the Nand cells ++ * ++ * Description: ++ * Before write and erase the Nand cells, the write enable has to be set. ++ * After the write or erase, the write enable bit is automatically cleared( status register bit 2 ) ++ * Set the bit 2 of the status register has the same effect ++ */ ++static uint32_t gk_spinand_write_enable(struct spinand_chip *chip, bool enable) ++{ ++ struct spinand_info *info = chip->info; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ uint32_t sflashData; ++ uint32_t cmdBitSet = 0; ++ ++ // ++ // issue a write command sequence to prepare ++ // the device for data to be written ++ // ++ cmdBitSet |= (FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_0 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_NOTHING | // no read/write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (0 << FLASH_TRANSFER_BYTE_LOC) | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ if(enable == WR_ENABLE) ++ { ++ cmdBitSet |= (uint32_t)info->commands->writeEnable; // command ++ } ++ else ++ { ++ cmdBitSet |= (uint32_t)info->commands->writeDisable; // command ++ } ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ sflashData = spinand_get_data(); ++ ++ return sflashData; ++ ++} ++ ++/** ++ * gk_spinand_set_feature - send command 0x1f to the SPI Nand status register ++ * ++ * Description: ++ * After read, write, or erase, the Nand device is expected to set the busy status. ++ * This function is to allow reading the status of the command: read, write, and erase. ++ * Once the status turns to be ready, the other status bits also are valid status bits. ++ */ ++static int gk_spinand_set_feature(struct spinand_chip *chip, uint32_t off, uint8_t input) ++{ ++ struct spinand_info *info = chip->info; ++ ++ uint32_t cmdBitSet = 0; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ cmdBitSet |= (info->commands->setFeatures | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_1 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1 << FLASH_TRANSFER_BYTE_LOC) | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(off); ++ spinand_set_data(input); ++ ++ return 0; ++ ++} ++ ++/** ++ * gk_spinand_get_feature - send command 0xf to the SPI Nand status register ++ * ++ * Description: ++ * After read, write, or erase, the Nand device is expected to set the busy status. ++ * This function is to allow reading the status of the command: read, write, and erase. ++ * Once the status turns to be ready, the other status bits also are valid status bits. ++ */ ++static int gk_spinand_get_feature(struct spinand_chip *chip, uint32_t off, uint32_t *output) ++{ ++ struct spinand_info *info = chip->info; ++ ++ uint32_t sflashData; ++ uint32_t cmdBitSet = 0; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ cmdBitSet |= (info->commands->getFeatures | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_1 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_READ | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1 << FLASH_TRANSFER_BYTE_LOC) | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(off); ++ ++ sflashData = spinand_get_data(); ++ *output = sflashData; ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_reset- send reset command "0xff" to the Nand device ++ * ++ * Description: ++ * Reset the SPI Nand with the reset command 0xff ++ */ ++static int gk_spinand_reset(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ ++ uint32_t cmdBitSet = 0; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ gk_spinand_set_channel(info); ++ ++ cmdBitSet |= (info->commands->reset | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_0 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_NOTHING | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ (1 << FLASH_TRANSFER_BYTE_LOC) | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ gk_spinand_release_channel(info); ++ return 0; ++ ++} ++/** ++ * spinand_read_id- Read SPI Nand ID ++ * ++ * Description: ++ * Read ID: read two ID bytes from the SPI Nand device ++ */ ++static int gk_spinand_read_id(struct spinand_chip *chip, uint32_t* id) ++{ ++ struct spinand_info *info = chip->info; ++ ++ uint32_t sflashData; ++ uint32_t cmdBitSet = 0; ++ ++ flash_command_s SflashCmd; ++ ++ gk_spinand_set_channel(info); ++ ++ // spi nand flash: send readID cmd ++ cmdBitSet |= (FLASH_SEND_CMD| // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_1| // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0| // dummy cycle ++ FLASH_RWN_READ| // read data ++ FLASH_CMD_MODE_1X| // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0| // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0| // set the sflash data mode ++ (3 << FLASH_TRANSFER_BYTE_LOC) // transfer data number ++ ); ++ ++ cmdBitSet |= (uint32_t)info->commands->readID; // readID command ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(0x00); ++ sflashData = spinand_get_data(); ++ ++ *id = sflashData; ++ ++ gk_spinand_release_channel(info); ++ ++ return 0; ++ ++} ++ ++/** ++ * gk_spinand_unlock_allblock- send write register 0x1f command to the Nand device ++ * ++ * Description: ++ * After power up, all the Nand blocks are locked. This function allows ++ * one to unlock the blocks, and so it can be wriiten or erased. ++ */ ++static int gk_spinand_unlock_allblock(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ ++ gk_spinand_set_channel(info); ++ gk_spinand_set_feature(chip , REG_PROTECTION, BL_ALL_UNLOCKED); ++ gk_spinand_release_channel(info); ++ return 0; ++} ++ ++#if 0 ++ ++/** ++ * gk_spinand_enable_bbi - send command 0x1f to write the SPI Nand OTP register ++ * ++ * Description: ++ * There is one bit( bit 0x10 ) to set or to clear the internal ECC. ++ * Enable chip internal BBI, set the bit to 1 ++ * Disable chip internal BBI, clear the bit to 0 ++ */ ++static int gk_spinand_enable_bbi(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ uint32_t ufeature = 0; ++ ++ gk_spinand_set_channel(info); ++ ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ ++ if ((ufeature & OTP_BBI_MASK) == OTP_BBI_MASK) ++ { ++ return 0; ++ } ++ else ++ { ++ ufeature |= OTP_BBI_MASK; ++ gk_spinand_set_feature(chip, REG_FEATURE, (uint8_t)(ufeature & 0xff)); ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ return ufeature; ++ } ++} ++ ++static int gk_spinand_disable_bbi(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ uint32_t ufeature = 0; ++ ++ gk_spinand_set_channel(info); ++ ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ ++ if ((ufeature & OTP_BBI_MASK) == OTP_BBI_MASK) ++ { ++ ufeature &= ~OTP_BBI_MASK; ++ gk_spinand_set_feature(chip, REG_FEATURE, (uint8_t)(ufeature & 0xff)); ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ return ufeature; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++#endif ++ ++/** ++ * gk_spinand_enable_ecc - send command 0x1f to write the SPI Nand OTP register ++ * ++ * Description: ++ * There is one bit( bit 0x10 ) to set or to clear the internal ECC. ++ * Enable chip internal ECC, set the bit to 1 ++ * Disable chip internal ECC, clear the bit to 0 ++ */ ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++static int gk_spinand_enable_ecc(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ uint32_t ufeature = 0; ++ ++ gk_spinand_set_channel(info); ++ ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ ++ if ((ufeature & OTP_ECC_MASK) == OTP_ECC_MASK) ++ { ++ gk_spinand_release_channel(info); ++ return 0; ++ } ++ else ++ { ++ ufeature |= OTP_ECC_MASK; ++ gk_spinand_set_feature(chip, REG_FEATURE, (uint8_t)(ufeature & 0xff)); ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ gk_spinand_release_channel(info); ++ return ufeature; ++ } ++} ++#endif ++ ++static int gk_spinand_disable_ecc(struct spinand_chip *chip) ++{ ++ struct spinand_info *info = chip->info; ++ uint32_t ufeature = 0; ++ ++ gk_spinand_set_channel(info); ++ ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ ++ if ((ufeature & OTP_ECC_MASK) == OTP_ECC_MASK) ++ { ++ ufeature &= ~OTP_ECC_MASK; ++ gk_spinand_set_feature(chip, REG_FEATURE, (uint8_t)(ufeature & 0xff)); ++ gk_spinand_get_feature(chip, REG_FEATURE, &ufeature); ++ gk_spinand_release_channel(info); ++ return ufeature; ++ } ++ else ++ { ++ gk_spinand_release_channel(info); ++ return 0; ++ } ++} ++ ++static int gk_spinand_read_page_to_cache(struct spinand_chip *chip, uint32_t page_id) ++{ ++ struct spinand_info *info = chip->info; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ uint32_t cmdBitSet = 0; ++ ++ // 1. page read to cache ++ cmdBitSet |= (info->commands->pageRead | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_3 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_READ | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 // transfer data number ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(page_id); // here address should be page/block address, ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_read_from_cache- send command 0x03 to read out the data from the cache register( 2112 bytes max ) ++ * ++ * Description: ++ * The read can specify 1 to 2112 bytes of data read at the coresponded locations. ++ * No tRd delay. ++ */ ++static int gk_spinand_read_from_cache( ++ struct spinand_chip *chip, ++ uint32_t byte_id, uint32_t len, ++ uint8_t* rbuf) ++{ ++ struct spinand_info *info = chip->info; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ uint32_t i, ilen, tmpData; ++ uint32_t cmdBitSet = 0; ++ uint32_t feature = FLASH_FEATURE_IO1; ++ uint32_t *pData = (uint32_t*)chip->tmpbuf; ++ ++ switch((info->feature & 0x0f)) ++ { ++ default: ++ case 0x01: ++ feature = FLASH_FEATURE_IO1; ++ break; ++ case 0x02: ++ feature = FLASH_FEATURE_IO2; ++ break; ++ case 0x04: ++ feature = FLASH_FEATURE_IO4; ++ break; ++ } ++ ++ // 3. read from cache ++ if(feature == FLASH_FEATURE_IO4) ++ { ++ cmdBitSet |= (info->commands->readCacheX4 | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_1 | // dummy cycle ++ FLASH_RWN_READ | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_2 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 // transfer data number ++ ); ++ } ++ else if(feature == FLASH_FEATURE_IO2) ++ { ++ cmdBitSet |= (info->commands->readCacheX2 | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_1 | // dummy cycle ++ FLASH_RWN_READ | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_1 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 // transfer data number ++ ); ++ } ++ else ++ { ++ cmdBitSet |= (info->commands->readCache | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_1 | // dummy cycle ++ FLASH_RWN_READ | // read data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 // transfer data number ++ ); ++ } ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(byte_id); // Set the start address what you want to read ++ ++ ilen = ((len - 1) >> 2) + 1; ++ ++ for(i = 0; i < ilen; i++) ++ { ++ tmpData = spinand_get_data(); ++ *pData++ = uswap_32(tmpData); ++ } ++ ++ memcpy(rbuf, (uint8_t*)chip->tmpbuf, len); ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_read_page_raw-to read a page with: ++ * @page_id: the physical page number ++ * @offset: the location from 0 to 2111 ++ * @len: number of bytes to read ++ * @rbuf: read buffer to hold @len bytes ++ * ++ * Description: ++ * The read icludes two commands to the Nand: 0x13 and 0x03 commands ++ * Poll to read status to wait for tRD time. ++ */ ++static int gk_spinand_read_page_raw( ++ struct spinand_chip *chip, ++ uint32_t page_id, uint32_t offset, ++ uint32_t len, uint8_t* rbuf) ++{ ++ ssize_t retval; ++ uint32_t status = 0; ++ struct spinand_info *info = chip->info; ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[%s]: PageID = 0x%08x, Offset = 0x%08x, len = %d, rbufadd = 0x%x\n", ++ __FUNCTION__, page_id, offset, len, rbuf); ++ #endif ++ ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++ gk_spinand_disable_ecc(chip); ++#endif ++ ++ gk_spinand_set_channel(info); ++ ++ retval = gk_spinand_read_page_to_cache(chip, page_id); ++ ++ while (1) ++ { ++ gk_spinand_get_feature(chip, REG_STATUS, &status); ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[%s_%d]: status = 0x%08x\n", ++ __FUNCTION__, __LINE__,status); ++ #endif ++ ++ if ((status & STATUS_OIP_MASK) == STATUS_READY) ++ { ++ break; ++ } ++ } ++ ++ retval = gk_spinand_read_from_cache(chip, offset, len, rbuf); ++ ++ gk_spinand_release_channel(info); ++ ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++ gk_spinand_enable_ecc(chip); ++#endif ++ ++ return retval; ++ ++} ++ ++ ++/** ++ * spinand_read_page-to read a page with: ++ * @page_id: the physical page number ++ * @offset: the location from 0 to 2111 ++ * @len: number of bytes to read ++ * @rbuf: read buffer to hold @len bytes ++ * ++ * Description: ++ * The read icludes two commands to the Nand: 0x13 and 0x03 commands ++ * Poll to read status to wait for tRD time. ++ */ ++static int gk_spinand_read_page( ++ struct spinand_chip *chip, ++ uint32_t page_id, uint32_t offset, ++ uint32_t len, uint8_t* rbuf) ++{ ++ struct spinand_info *info = chip->info; ++ ssize_t retval; ++ uint32_t status = 0; ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[%s]: PageID = 0x%08x, Offset = 0x%08x, len = %d, rbufadd = 0x%x\n", ++ __FUNCTION__, page_id, offset, len, rbuf); ++ #endif ++ ++ gk_spinand_set_channel(info); ++ ++ retval = gk_spinand_read_page_to_cache(chip, page_id); ++ ++ while (1) ++ { ++ gk_spinand_get_feature(chip, REG_STATUS, &status); ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[%s_%d]: status = 0x%08x\n", ++ __FUNCTION__, __LINE__,status); ++ #endif ++ ++ if ((status & STATUS_OIP_MASK) == STATUS_READY) ++ { ++ if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) ++ { ++ pr_err("[%s]ecc error, page = 0x%08x\n", __FUNCTION__, page_id); ++ return -1; ++ } ++ break; ++ } ++ } ++ ++ retval = gk_spinand_read_from_cache(chip, offset, len, rbuf); ++ ++ gk_spinand_release_channel(info); ++ ++ return 0; ++ ++} ++ ++#define RET_OK 0 ++ ++#define WRITE_BYTE 0x1 ++#define WRITE_WORD 0x2 ++#define WRITE_LWORD 0x4 ++#define WRITE_CLWORD 0x1f ++ ++ ++static int gk_spinand_write_to_cache( ++ struct spinand_chip *chip, uint32_t offset, uint32_t dflag) ++{ ++ struct spinand_info *info = chip->info; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ uint32_t cmdBitSet = 0; ++ uint32_t feature = FLASH_FEATURE_IO1; ++ ++#ifdef CONFIG_DEBUG_W ++ printk("[DEBUG_W]: %s\n", __FUNCTION__); ++ { ++ int i = 0, j = 0; ++ uint8_t* buf = (uint8_t*)chip->tmpbuf; ++ ++ for(i = 0,j = 0; i < 128; i++,j++) ++ { ++ if(j % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", buf[i]); ++ } ++ ++ printk("\n"); ++ } ++#endif ++ ++ ++ switch(((info->feature >> 4) & 0x0f)) ++ { ++ default: ++ case 0x01: ++ feature = FLASH_FEATURE_IO1; ++ break; ++ case 0x02: ++ feature = FLASH_FEATURE_IO2; ++ break; ++ case 0x04: ++ feature = FLASH_FEATURE_IO4; ++ break; ++ } ++ ++ if(feature == FLASH_FEATURE_IO4) ++ { ++ cmdBitSet |= (info->commands->programLoadX4 | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_2 | // set the sflash data mode ++ dflag << FLASH_TRANSFER_BYTE_LOC | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ } ++ else if(feature == FLASH_FEATURE_IO2) ++ { ++ /* no supported */ ++ cmdBitSet |= (info->commands->programLoad | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_1 | // set the sflash data mode ++ dflag << FLASH_TRANSFER_BYTE_LOC | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ } ++ else ++ { ++ cmdBitSet |= (info->commands->programLoad | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_2 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ dflag << FLASH_TRANSFER_BYTE_LOC | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ } ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(offset); // Set the start address what you want to write ++ ++ return RET_OK; ++ ++} ++ ++/** ++ * gk_spinand_program_data_to_cache -- to write a page to cache with: ++ * @byte_id: the location to write to the cache ++ * @len: number of bytes to write ++ * @rbuf: read buffer to hold @len bytes ++ * ++ * Description: ++ * The write command used here is 0x84--indicating that the cache is not cleared first. ++ * Since it is writing the data to cache, there is no tPROG time. ++ */ ++static int gk_spinand_program_data_to_cache( ++ struct spinand_chip *chip, uint32_t offset, ++ uint32_t len, uint8_t* wbuf) ++{ ++ ++ ++ uint32_t i, u4Len, uleftLen, dflag = WRITE_CLWORD, wdata, doff; ++ uint32_t uTmpData; ++ ++#ifndef CONFIG_NAND_SPL ++ uint32_t *pData = (uint32_t*)chip->tmpbuf; ++#else ++ uint32_t *pData = (uint32_t*)wbuf; ++#endif ++ ++ /* calc the length of data(unit:long word) */ ++ u4Len = len >> 2; ++ uleftLen = len % 4; ++ doff = 0; ++ ++#ifndef CONFIG_NAND_SPL ++ /* copy data to temporary 4 bytes align buffer */ ++ memcpy((uint8_t*)pData, (wbuf + offset), (u4Len << 2)); ++#endif ++ ++ /* write the data which length is a multiple of 4 bytes to cache firstly */ ++ if(u4Len > 0) ++ { ++ dflag = WRITE_CLWORD; ++ gk_spinand_write_to_cache(chip, offset, dflag); ++ for(i = 0; i < u4Len; i++) ++ { ++ uTmpData = *pData++; ++ uTmpData = uswap_32(uTmpData); ++ spinand_set_data(uTmpData); ++ } ++ ++ doff += (u4Len << 2); ++ } ++ ++ i = 0; ++ ++ /* write the left data to cache */ ++ while(uleftLen) ++ { ++ dflag = WRITE_BYTE; ++ doff += i; ++ wdata = (uint32_t)wbuf[doff]; ++ gk_spinand_write_to_cache(chip, (offset + doff), dflag); ++ spinand_set_data(wdata); ++ uleftLen--; ++ } ++ ++ return RET_OK; ++ ++} ++ ++/** ++ * gk_spinand_program_execute -- to write a page from cache to the Nand array with: ++ * @page_id: the physical page location to write the page. ++ * ++ * Description: ++ * The write command used here is 0x10--indicating the cache is writing to the Nand array. ++ * Need to wait for tPROG time to finish the transaction. ++ */ ++static int gk_spinand_program_execute(struct spinand_chip *chip, uint32_t page_id) ++{ ++ struct spinand_info *info = chip->info; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ uint32_t cmdBitSet = 0; ++ ++ cmdBitSet |= (info->commands->progExecute | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_3 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(page_id); // here address should be page/block address, ++ ++ return 0; ++ ++} ++ ++/** ++ * gk_spinand_program_page_raw--to write a page with: ++ * @page_id: the physical page location to write the page. ++ * @offset: the location from the cache starting from 0 to 2111 ++ * @len: the number of bytes to write ++ * @wbuf: the buffer to hold the number of bytes ++ * ++ * Description: ++ * The commands used here are 0x06, 0x84, and 0x10--indicating that the write enable is first ++ * sent, the write cache command, and the write execute command ++ * Poll to wait for the tPROG time to finish the transaction. ++ */ ++static int gk_spinand_program_page_raw( ++ struct spinand_chip *chip, ++ uint32_t page_id, uint32_t offset, ++ uint32_t len, uint8_t* wbuf) ++{ ++ ssize_t retval; ++ uint32_t status = 0; ++ struct spinand_info *info = chip->info; ++ ++ #ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: PageID = 0x%08x, rbufadd = 0x%x\n", ++ __FUNCTION__, page_id, wbuf); ++ #endif ++ ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++ gk_spinand_disable_ecc(chip); ++#endif ++ ++ gk_spinand_set_channel(info); ++ ++ retval = gk_spinand_write_enable(chip, WR_ENABLE); ++ ++ retval = gk_spinand_program_data_to_cache(chip, offset, len, wbuf); ++ ++ retval = gk_spinand_program_execute(chip, page_id); ++ ++ while (1) ++ { ++ gk_spinand_get_feature(chip, REG_STATUS, &status); ++ ++ if ((status & STATUS_OIP_MASK) == STATUS_READY) ++ { ++ break; ++ } ++ } ++ ++ gk_spinand_release_channel(info); ++ ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++ gk_spinand_enable_ecc(chip); ++#endif ++ ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_program_page--to write a page with: ++ * @page_id: the physical page location to write the page. ++ * @offset: the location from the cache starting from 0 to 2111 ++ * @len: the number of bytes to write ++ * @wbuf: the buffer to hold the number of bytes ++ * ++ * Description: ++ * The commands used here are 0x06, 0x84, and 0x10--indicating that the write enable is first ++ * sent, the write cache command, and the write execute command ++ * Poll to wait for the tPROG time to finish the transaction. ++ */ ++static int gk_spinand_program_page( ++ struct spinand_chip *chip, ++ uint32_t page_id, uint32_t offset, ++ uint32_t len, uint8_t* wbuf) ++{ ++ struct spinand_info *info = chip->info; ++ ssize_t retval; ++ uint32_t status = 0; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: blockId = %d, PageID = 0x%08x\n", ++ __FUNCTION__, page_id/info->page_per_block, page_id); ++#endif ++ ++ gk_spinand_set_channel(info); ++ ++ retval = gk_spinand_write_enable(chip, WR_ENABLE); ++ ++ retval = gk_spinand_program_data_to_cache(chip, offset, len, wbuf); ++ ++ retval = gk_spinand_program_execute(chip, page_id); ++ ++ while (1) ++ { ++ gk_spinand_get_feature(chip, REG_STATUS, &status); ++ ++ if ((status & STATUS_OIP_MASK) == STATUS_READY) ++ { ++ if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) ++ { ++ pr_err("[%s]: program error, page = 0x%08x\n", __FUNCTION__, page_id); ++ gk_spinand_release_channel(info); ++ return -1; ++ } ++ else ++ { ++ break; ++ } ++ } ++ } ++ gk_spinand_release_channel(info); ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_erase_block_do -- to erase a block with: ++ * @block_id: the physical block location to erase. ++ * ++ * Description: ++ * The command used here is 0xd8--indicating an erase command to erase one block--64 pages ++ * Need to wait for tERS. ++ */ ++static int gk_spinand_erase_block_do(struct spinand_chip *chip, uint32_t block_id) ++{ ++ struct spinand_info *info = chip->info; ++ ++ uint32_t cmdBitSet = 0; ++ ++ flash_command_s SflashCmd = {0}; ++ ++ cmdBitSet |= (info->commands->blockErase | // command ++ FLASH_SEND_CMD | // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_3 | // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0 | // dummy cycle ++ FLASH_RWN_WRITE | // write data ++ FLASH_CMD_MODE_1X | // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0 | // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0 | // set the sflash data mode ++ FLASH_TRANSFER_BYTE_NUM_4 | // transfer data number ++ FLASH_HOLD_TIME_100ns ++ ); ++ ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(block_id); ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_erase_block--to erase a page with: ++ * @block_id: the physical block location to erase. ++ * ++ * Description: ++ * The commands used here are 0x06 and 0xd8--indicating an erase command to erase one block--64 pages ++ * It will first to enable the write enable bit ( 0x06 command ), and then send the 0xd8 erase command ++ * Poll to wait for the tERS time to complete the tranaction. ++ */ ++static int gk_spinand_erase_block(struct spinand_chip *chip, uint32_t block_id) ++{ ++ struct spinand_info *info = chip->info; ++ ssize_t retval; ++ uint32_t status = 0; ++ ++ gk_spinand_set_channel(info); ++ ++ retval = gk_spinand_write_enable(chip, WR_ENABLE); ++ ++ retval = gk_spinand_erase_block_do(chip, block_id); ++ ++ while(1) ++ { ++ gk_spinand_get_feature(chip, REG_STATUS, &status); ++ ++ if ((status & STATUS_OIP_MASK) == STATUS_READY) ++ { ++ if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) ++ { ++ pr_err("%s: erase error, block = %d\n", __FUNCTION__, block_id/info->page_per_block); ++ gk_spinand_release_channel(info); ++ return -1; ++ } ++ else ++ break; ++ } ++ } ++ gk_spinand_release_channel(info); ++ ++ return 0; ++ ++} ++ ++/**************************************************************/ ++/* */ ++/**************************************************************/ ++static struct spinand_info* gk_get_spinand_info(struct platform_device *dev) ++{ ++ uint32_t sflashData; ++ uint8_t mID; ++ uint16_t dID; ++ uint32_t index; ++ uint32_t count; ++ uint32_t CESetting = 0x0E; ++ uint32_t cmdBitSet = 0; ++ ++ struct spinand_info* sninfo; ++ struct gk_spinand_platform_data *platform_data = dev->dev.platform_data; ++ flash_command_s SflashCmd; ++ ++ uint32_t channel = platform_data->channel; ++ uint32_t speed_mode = platform_data->speed_mode; ++ ++ pr_info("%s: SPINAND Channel = %d, SpeedMode = %d !\n", __FUNCTION__, channel, speed_mode); ++ ++ if(channel >= FLASH_CHANNEL_NUM) ++ { ++ return NULL; ++ } ++ ++ CESetting = CESetting | ((uint32_t)channel << 6); ++ ++ spinand_set_ce (CESetting); ++ spinand_set_speed (speed_mode); //0 -- 1/2freq 1--1/4freq 2....4 ++ ++ CESetting = spinand_get_ce(); ++ speed_mode = spinand_get_speed(); ++// pr_info("%s: CE = 0x%08x, SpeedMode = 0x%08x !\n", __FUNCTION__, CESetting, speed_mode); ++ ++ // spi nand flash: send readID cmd ++ cmdBitSet |= (FLASH_SEND_CMD| // transfer the command ++ FLASH_SEND_ADDR_BYTE_NUM_1| // address num ++ FLASH_SEND_DUMMY_BYTE_NUM_0| // dummy cycle ++ FLASH_RWN_READ| // read data ++ FLASH_CMD_MODE_1X| // set the sflash cmd mode ++ FLASH_ADDR_DUMMY_CYCLE_NUM_0| // set the sflash adr mode ++ FLASH_DATA_CYCLE_NUM_0| // set the sflash data mode ++ (3 << FLASH_TRANSFER_BYTE_LOC) // transfer data number ++ ); ++ ++ cmdBitSet |= CMD_READ_ID; // readID command ++ SflashCmd.all = cmdBitSet; ++ spinand_set_command(SflashCmd.all); ++ spinand_set_data(0x00); ++ sflashData = spinand_get_data(); ++ ++ mID = (uint8_t)((sflashData & 0x00FF0000) >> 16); ++ dID = (uint16_t)(sflashData & 0x0000FFFF); ++ ++ pr_info("%s: SPINAND MID = 0x%x, DID = 0x%x, Data = 0x%x !\n", ++ __FUNCTION__, mID, dID, sflashData); ++ ++ count = sizeof(spinand_devices_supported)/sizeof(struct spinand_info); ++ ++ for(index = 0; index < count; index++) ++ { ++ sninfo = &(spinand_devices_supported[index]); ++ if((mID == sninfo->mid) && ++ (dID == sninfo->did)) ++ { ++ spinand_set_ce_chselect(!channel); ++ return( sninfo ); ++ } ++ } ++ spinand_set_ce_chselect(!channel); ++ ++ return NULL; ++ ++} ++ ++/** ++ * spinand_probe - [spinand Interface] ++* @spi_nand: registered device driver. ++ * ++ * Description: ++ * To set up the device driver parameters to make the device available. ++ */ ++static int __devinit gk_spinand_probe(struct platform_device *pdev) ++{ ++ struct gk_spinand_host *host; ++ struct spinand_chip *chip; ++ struct spinand_info *info; ++ ++ int res = 0; ++ ++ info = gk_get_spinand_info(pdev); ++ if (!info) ++ { ++ dev_err(&pdev->dev, "No support this SPI nand!\n"); ++ return -ENOMEM; ++ } ++ ++ pr_err("%s: %s (%lld Kbytes)\n", __FUNCTION__, info->deviceName, ++ (long long)info->nand_size >> 10); ++ ++ host = kzalloc(sizeof(struct gk_spinand_host), GFP_KERNEL); ++ if (!host) ++ { ++ dev_err(&pdev->dev, "no memory for NAND host context\n"); ++ return -ENOMEM; ++ } ++ host->io_base = (void*)REG_SFLASH_DATA; ++ ++ platform_set_drvdata(pdev, host); ++ ++ /* Initialize the SPI nand chip information */ ++ chip = &(host->chip); ++ chip->mtd = &host->mtd; ++ chip->priv = host; ++ chip->info = info; ++ ++ chip->reset = gk_spinand_reset; ++ chip->read_id = gk_spinand_read_id; ++ chip->read_page = gk_spinand_read_page; ++ chip->read_page_raw = gk_spinand_read_page_raw; ++ chip->program_page = gk_spinand_program_page; ++ chip->program_page_raw = gk_spinand_program_page_raw; ++ chip->erase_block = gk_spinand_erase_block; ++ chip->scan_bbt = NULL; ++ chip->block_markbad = NULL; ++ chip->block_bad = NULL; ++ chip->chip_delay = 50; ++ chip->chip_id = info->channel; ++ chip->chipsize = info->usable_size; ++ chip->options = NAND_NO_READRDY; ++ ++ chip->badblockpos = info->badblock_pattern->offs; ++ chip->badblockbits = info->badblockbits; ++// chip->bbt_options = NAND_BBT_NO_OOB | NAND_BBT_USE_FLASH ++// | NAND_BBT_CREATE | NAND_BBT_WRITE; ++ chip->bbt_options = NAND_BBT_NO_OOB | NAND_BBT_CREATE | NAND_BBT_WRITE; ++ chip->bbt_erase_shift = chip->phys_erase_shift = ffs(info->block_main_size) - 1; ++ chip->page_shift = info->page_shift; ++ chip->bbt = NULL; ++ chip->bbt_td = NULL; ++ chip->bbt_md = NULL; ++ chip->badblock_pattern = info->badblock_pattern; ++ ++ /* Convert chipsize to number of pages per chip -1. */ ++ chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; ++ ++ mutex_init(&chip->lock); ++ ++ chip->buffers = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL); ++ if (!chip->buffers) ++ { ++ dev_err(&pdev->dev, "[%s]no memory for NAND data buffer\n", __FUNCTION__); ++ res = -ENOMEM; ++ goto fail_err0; ++ } ++ chip->pagebuf = chip->buffers->databuf; ++ ++ /* Set the internal oob buffer location, just after the page data */ ++ chip->oob_poi = (chip->pagebuf + info->page_main_size); ++ ++ chip->oobbuf = kzalloc((info->page_size + 7), GFP_KERNEL); ++ if (!chip->oobbuf) ++ { ++ dev_err(&pdev->dev, "[%s]no memory for NAND tmp data buffer\n", __FUNCTION__); ++ res = -ENOMEM; ++ goto fail_err1; ++ } ++ ++ chip->tmpbuf = (uint32_t*)(((uint32_t)(chip->oobbuf + 3)) & 0xfffffffc);/* 4bytes alige */ ++ ++ res = gk_spinand_unlock_allblock(chip); ++#ifdef CONFIG_MTD_SPINAND_INTERECC ++ res = gk_spinand_enable_ecc(chip); ++#else ++ res = gk_spinand_disable_ecc(chip); ++#endif ++ ++ /* Initialize the SPI nand MTD information */ ++ host->mtd.priv = chip; ++ host->mtd.dev.parent = &pdev->dev; ++ res = spinand_scan(&(host->mtd)); ++ if (res) ++ { ++ dev_err(&pdev->dev, "[%s_%d]NAND scan failed with %d\n", __FUNCTION__, __LINE__, res); ++ res = -ENOMEM; ++ goto fail_err2; ++ } ++ ++ res = mtd_device_register(&(host->mtd), gk_spinand_partitions, NUM_PARTITIONS); ++ if (res) ++ { ++ dev_err(&pdev->dev, "[%s_%d]MTD device register error!\n", __FUNCTION__, __LINE__); ++ res = -ENOMEM; ++ goto fail_err2; ++ } ++ ++ return 0; ++ ++fail_err2: ++ kfree(chip->oobbuf); ++fail_err1: ++ kfree(chip->buffers); ++fail_err0: ++ kfree(host); ++ ++ return res; ++ ++} ++ ++/** ++ * __devexit spinand_remove--Remove the device driver ++ * @spi: the spi device. ++ * ++ * Description: ++ * To remove the device driver parameters and free up allocated memories. ++ */ ++static int __devexit gk_spinand_remove(struct platform_device *pdev) ++{ ++ struct mtd_info *mtd; ++ struct spinand_chip *chip; ++ struct gk_spinand_host *host; ++ ++ pr_info("%s: remove\n", dev_name(&pdev->dev)); ++ ++ host = dev_get_drvdata(&pdev->dev); ++ ++ mtd = &host->mtd; ++ mtd_device_unregister(mtd); ++ ++ chip = &host->chip; ++ ++ kfree(chip->oobbuf); ++ kfree(chip->buffers); ++ kfree(host); ++ ++ return 0; ++ ++} ++ ++#ifdef CONFIG_PM ++static int gk_spinand_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int gk_spinand_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++#else ++#define gk_spinand_suspend NULL ++#define gk_spinand_resume NULL ++#endif ++ ++static struct gk_spinand_platform_data gk_spinand_data = ++{ ++ .speed_mode = SYSTEM_SFLASH_FREQ, // LindengYu: use the 138 div 2 = 69MHz ++ .channel = 1, ++ .parts = gk_spinand_partitions, ++ .nr_parts = NUM_PARTITIONS, ++}; ++ ++/** ++ * Device name structure description ++*/ ++static struct platform_device gk_spinand_device = { ++ ++ .name = "gk_spi_nand", ++ .id = 1, ++ .dev = ++ { ++ .platform_data = &gk_spinand_data, ++ }, ++}; ++ ++ ++/** ++ * Device name structure description ++*/ ++static struct platform_driver gk_spinand_driver = { ++ .driver = { ++ .name = "gk_spi_nand", ++ .bus = &platform_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ ++ .probe = gk_spinand_probe, ++ .remove = __devexit_p(gk_spinand_remove), ++ .suspend = gk_spinand_suspend, ++ .resume = gk_spinand_resume, ++}; ++ ++/** ++ * Device driver registration ++*/ ++static int __init gk_spinand_init(void) ++{ ++ int ret = 0; ++ ++ ret = platform_driver_register(&gk_spinand_driver); ++ ++ if(!ret) ++ { ++ ret = platform_device_register(&gk_spinand_device); ++ if(ret) ++ { ++ platform_driver_unregister(&gk_spinand_driver); ++ } ++ } ++ return ret; ++} ++ ++/** ++ * unregister Device driver. ++*/ ++static void __exit gk_spinand_exit(void) ++{ ++ platform_device_unregister(&gk_spinand_device); ++ platform_driver_unregister(&gk_spinand_driver); ++} ++ ++module_init(gk_spinand_init); ++module_exit(gk_spinand_exit); ++ ++MODULE_DESCRIPTION("GOKE SPI NAND driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ ++ +diff --git a/drivers/mtd/spinand/gk_spinand_v1_00.h b/drivers/mtd/spinand/gk_spinand_v1_00.h +new file mode 100644 +index 00000000..dce7791a +--- /dev/null ++++ b/drivers/mtd/spinand/gk_spinand_v1_00.h +@@ -0,0 +1,669 @@ ++/* ++ * drivers/mtd/spinand/gk_spinand_v1_00.h ++ * ++ * gk soc ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++#include ++ ++/* send cmd or not [ 8]*/ ++#define FLASH_SEND_CMD 0x00000100 ++#define FLASH_NO_SEND_CMD 0x00000000 ++ ++ /* byte number of address to send [11:9]*/ ++#define FLASH_SEND_ADDR_BYTE_NUM_0 0x00000000 ++#define FLASH_SEND_ADDR_BYTE_NUM_1 0x00000200 ++#define FLASH_SEND_ADDR_BYTE_NUM_2 0x00000400 ++#define FLASH_SEND_ADDR_BYTE_NUM_3 0x00000600 ++#define FLASH_SEND_ADDR_BYTE_NUM_4 0x00000800 ++#define FLASH_SEND_ADDR_BYTE_NUM_5 0x00000a00 ++#define FLASH_SEND_ADDR_BYTE_NUM_6 0x00000c00 ++#define FLASH_SEND_ADDR_BYTE_NUM_7 0x00000e00 ++ ++ /*Byte number of dummy cycle to send [14:12]*/ ++ ++#define FLASH_SEND_DUMMY_BYTE_NUM_0 0x000000000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_1 0x000001000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_2 0x000002000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_3 0x000003000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_4 0x000004000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_5 0x000005000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_6 0x000006000 ++#define FLASH_SEND_DUMMY_BYTE_NUM_7 0x000007000 ++ ++ /* Command operation[16:15]: 00 for read data from SF; 01 for write data to SF; 11 for nothing to do */ ++ ++#define FLASH_RWN_READ 0x00000000 ++#define FLASH_RWN_WRITE 0x00008000 ++#define FLASH_RWN_NOTHING 0x00018000 ++ ++ /*I/O mode of command cycle to SF[18:17]: 00 for x1; 01 for x2; 10 for x4*/ ++#define FLASH_CMD_MODE_1X 0x00000000 ++#define FLASH_CMD_MODE_2X 0x00020000 ++#define FLASH_CMD_MODE_4X 0x00040000 ++ ++ /* I/O mode of address and dummy cycle to SF[20:19]*/ ++#define FLASH_ADDR_DUMMY_CYCLE_NUM_0 0x00000000 ++#define FLASH_ADDR_DUMMY_CYCLE_NUM_1 0x00080000 ++#define FLASH_ADDR_DUMMY_CYCLE_NUM_2 0x00100000 ++#define FLASH_ADDR_DUMMY_CYCLE_NUM_3 0x00180000 ++ ++ /*I/O mode of data cycle to or from SF [22:21] */ ++ ++#define FLASH_DATA_CYCLE_NUM_0 0x00000000 ++#define FLASH_DATA_CYCLE_NUM_1 0x00200000 ++#define FLASH_DATA_CYCLE_NUM_2 0x00400000 ++#define FLASH_DATA_CYCLE_NUM_3 0x00600000 ++ ++ /*Transfer data byte number to or from SF[27:23]. For 11111 case, transfer 4bytes per request. For other case, transfer number bytes.*/ ++ ++#define FLASH_TRANSFER_BYTE_NUM_4 0x0f800000 ++#define FLASH_TRANSFER_BYTE_LOC 23 ++ ++#define FLASH_HOLD_TIME_100ns 0x00000000 ++#define FLASH_HOLD_TIME_3us 0x10000000 ++#define FLASH_HOLD_TIME_100us 0x20000000 ++ ++ /*! ++ ******************************************************************************* ++ ** ++ ** \brief Flash channel number. ++ ** ++ ******************************************************************************* ++ */ ++ typedef enum ++ { ++ FLASH_CHANNEL_0 = 0, ++ FLASH_CHANNEL_1, ++ FLASH_CHANNEL_NUM ++ }flash_channel_e; ++ ++ /*! ++ ******************************************************************************* ++ ** ++ ** \brief Flash I/O feature. ++ ** ++ ******************************************************************************* ++ */ ++ typedef enum ++ { ++ FLASH_FEATURE_IO1 = 0, ++ FLASH_FEATURE_IO2, ++ FLASH_FEATURE_IO4 ++ }flash_feature_e; ++ ++ ++/*----------------------------------------------------------------------------*/ ++/* bit group structures */ ++/*----------------------------------------------------------------------------*/ ++typedef union { /* SFLASH_Command */ ++ uint32_t all; ++ struct { ++ uint32_t code : 8; ++ uint32_t sendcmd : 1; ++ uint32_t adrnum : 3; ++ uint32_t dummynum : 3; ++ uint32_t rwn : 2; ++ uint32_t cmdmode : 2; ++ uint32_t adrmode : 2; ++ uint32_t datamode : 2; ++ uint32_t datanum : 5; ++ uint32_t holdtime : 2; ++ uint32_t : 2; ++ } bitc; ++}flash_command_s; ++ ++ typedef union { /* SFLASH_CE */ ++ uint32_t all; ++ struct { ++ uint32_t ce : 1; ++ uint32_t wp : 1; ++ uint32_t hold : 1; ++ uint32_t cemode : 1; ++ uint32_t wpmode : 1; ++ uint32_t holdmode : 1; ++ uint32_t chselect : 1; ++ uint32_t : 25; ++ } bitc; ++}flash_ce_s; ++ ++typedef union { /* SFLASH_Speed */ ++ uint32_t all; ++ struct { ++ uint32_t sf_sclk_sel : 3; ++ uint32_t : 29; ++ } bitc; ++} flash_speed_s; ++ ++typedef union { /* SFLASH_PARA_XIP */ ++ uint32_t all; ++ struct { ++ uint32_t sflash_command : 8; ++ uint32_t : 1; ++ uint32_t adr_num : 3; ++ uint32_t dummy_num : 3; ++ uint32_t : 2; ++ uint32_t cmd_mod : 2; ++ uint32_t adr_mod : 2; ++ uint32_t data_mod : 2; ++ uint32_t : 1; ++ uint32_t dumy_data : 8; ++ } bitc; ++} flash_para_xip_s; ++ ++ /*----------------------------------------------------------------------------*/ ++/* register SFLASH_Data (read/write) */ ++/*----------------------------------------------------------------------------*/ ++void spinand_set_data (uint32_t data) ++{ ++ gk_ssi_writel(REG_SFLASH_DATA, data); ++ //*(volatile uint32_t *)REG_SFLASH_DATA = data; ++} ++uint32_t spinand_get_data (void) ++{ ++ return gk_ssi_readl(REG_SFLASH_DATA); ++ //return (*(volatile uint32_t *)REG_SFLASH_DATA); ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_Command (read/write) */ ++/*----------------------------------------------------------------------------*/ ++void spinand_set_command(uint32_t data) ++{ ++ gk_ssi_writel(REG_SFLASH_COMMAND, data); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = data; ++} ++uint32_t spinand_get_command (void) ++{ ++ return gk_ssi_readl(REG_SFLASH_COMMAND); ++ //return (*(volatile uint32_t *)REG_SFLASH_COMMAND); ++} ++void spinand_set_command_code(uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.code = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_code(void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.code; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.code; ++} ++void spinand_set_command_sendcmd(uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.sendcmd = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_sendcmd(void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.sendcmd; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.sendcmd; ++} ++void spinand_set_command_adrnum (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.adrnum = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_adrnum (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.adrnum; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.adrnum; ++} ++void spinand_set_command_dummynum (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.dummynum = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_dummynum (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.dummynum; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.dummynum; ++} ++void spinand_set_command_rwn(uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.rwn = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_rwn (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.rwn; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.rwn; ++} ++void spinand_set_command_cmdmode (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.cmdmode = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_cmdmode (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.cmdmode; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.cmdmode; ++} ++void spinand_set_command_adrmode (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.adrmode = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_adrmode (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.adrmode; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.adrmode; ++} ++void spinand_set_command_datamode(uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.datamode = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_datamode(void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.datamode; ++ ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.datamode; ++} ++void spinand_set_command_datanum (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.datanum = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_datanum (void) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.datanum; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.datanum; ++} ++void spinand_set_command_holdtime (uint8_t data) ++{ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_COMMAND; ++ d.bitc.holdtime = data; ++ gk_ssi_writel(REG_SFLASH_COMMAND, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_COMMAND = d.all; ++} ++uint8_t spinand_get_command_holdtime (void) ++{ ++ ++ flash_command_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_COMMAND); ++ return d.bitc.holdtime; ++ ++ //return (*(volatile flash_command_s *)REG_SFLASH_COMMAND).bitc.holdtime; ++} ++ ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_CE (read/write) */ ++/*----------------------------------------------------------------------------*/ ++void spinand_set_ce (uint32_t data) ++{ ++ gk_ssi_writel(REG_SFLASH_CE, data); ++ //*(volatile uint32_t *)REG_SFLASH_CE = data; ++} ++uint32_t spinand_get_ce(void) ++{ ++ return gk_ssi_readl(REG_SFLASH_CE); ++ //return (*(volatile uint32_t *)REG_SFLASH_CE); ++} ++void spinand_set_ce_ce(uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.ce = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_ce(void) ++{ ++ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.ce; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.ce; ++} ++void spinand_set_ce_wp(uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.wp = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_wp(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.wp; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.wp; ++} ++void spinand_set_ce_hold (uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.hold = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_hold(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.hold; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.hold; ++} ++void spinand_set_ce_cemode (uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.cemode = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_cemode(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.cemode; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.cemode; ++} ++void spinand_set_ce_wpmode (uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.wpmode = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_wpmode(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.wpmode; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.wpmode; ++} ++void spinand_set_ce_holdmode (uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.holdmode = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_holdmode(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.holdmode; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.holdmode; ++} ++void spinand_set_ce_chselect (uint8_t data) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_CE; ++ d.bitc.chselect = data; ++ gk_ssi_writel(REG_SFLASH_CE, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_CE = d.all; ++} ++uint8_t spinand_get_ce_chselect(void) ++{ ++ flash_ce_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_CE); ++ return d.bitc.chselect; ++ ++ //return (*(volatile flash_ce_s *)REG_SFLASH_CE).bitc.chselect; ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_Speed (read/write) */ ++/*----------------------------------------------------------------------------*/ ++void spinand_set_speed (uint32_t data) ++{ ++ gk_ssi_writel(REG_SFLASH_SPEED, data); ++ //*(volatile uint32_t *)REG_SFLASH_SPEED = data; ++} ++uint32_t spinand_get_speed(void) ++{ ++ return gk_ssi_readl(REG_SFLASH_SPEED); ++ //return (*(volatile uint32_t *)REG_SFLASH_SPEED); ++} ++void spinand_set_speed_sf_sclk_sel (uint8_t data) ++{ ++ flash_speed_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_SPEED); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_SPEED; ++ d.bitc.sf_sclk_sel = data; ++ gk_ssi_writel(REG_SFLASH_SPEED, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_SPEED = d.all; ++} ++uint8_t spinand_get_speed_sf_sclk_sel(void) ++{ ++ flash_speed_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_SPEED); ++ return d.bitc.sf_sclk_sel; ++ ++ //return (*(volatile flash_speed_s *)REG_SFLASH_SPEED).bitc.sf_sclk_sel; ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* register SFLASH_PARA_XIP (read/write) */ ++/*----------------------------------------------------------------------------*/ ++void spinand_set_para_xip (uint32_t data) ++{ ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, data); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = data; ++} ++uint32_t spinand_get_para_xip(void) ++{ ++ return gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //return (*(volatile uint32_t *)REG_SFLASH_PARA_XIP); ++} ++void spinand_set_para_xip_sflash_command (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.sflash_command = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_sflash_command(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.sflash_command; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.sflash_command; ++} ++void spinand_set_para_xip_adr_num (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.adr_num = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_adr_num(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.adr_num; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.adr_num; ++} ++void spinand_set_para_xip_nummy_num (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.dummy_num = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_nummy_num(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.dummy_num; ++ ++ // return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.dummy_num; ++} ++void spinand_set_para_xip_cmd_mod (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ // d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.cmd_mod = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_cmd_mod(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.cmd_mod; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.cmd_mod; ++} ++void spinand_set_para_xip_adr_mod (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.adr_mod = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_adr_mod(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.adr_mod; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.adr_mod; ++} ++void spinand_set_para_xip_data_mod (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.data_mod = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_data_mod(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.data_mod; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.data_mod; ++} ++void spinand_set_para_xip_nummy_data (uint8_t data) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ //d.all = *(volatile uint32_t *)REG_SFLASH_PARA_XIP; ++ d.bitc.dumy_data = data; ++ gk_ssi_writel(REG_SFLASH_PARA_XIP, d.all); ++ //*(volatile uint32_t *)REG_SFLASH_PARA_XIP = d.all; ++} ++uint8_t spinand_get_para_xip_nummy_data(void) ++{ ++ flash_para_xip_s d; ++ d.all = gk_ssi_readl(REG_SFLASH_PARA_XIP); ++ return d.bitc.dumy_data; ++ ++ //return (*(volatile flash_para_xip_s *)REG_SFLASH_PARA_XIP).bitc.dumy_data; ++} ++ +diff --git a/drivers/mtd/spinand/spinand.h b/drivers/mtd/spinand/spinand.h +new file mode 100644 +index 00000000..50559bd2 +--- /dev/null ++++ b/drivers/mtd/spinand/spinand.h +@@ -0,0 +1,244 @@ ++/* ++ linux/drivers/mtd/spinand/spinand.h ++ ++ Copyright (c) 2013 Gofortune Semiconductor Corporation. ++ Kewell Liu ++ ++ This software is licensed under the terms of the GNU General Public ++ License version 2, as published by the Free Software Foundation, and ++ may be copied, distributed, and modified under those terms. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ based on nand.h ++*/ ++ ++#ifndef __LINUX_MTD_SPINAND_H ++#define __LINUX_MTD_SPINAND_H ++ ++#include ++#include ++#include ++ ++#define SPINAND_OOBSIZE 128 ++#define SPINAND_PAGESIZE 2048 ++#define SPINAND_PAGENUMB 2048 ++#define SPINAND_BLOCKNUM 2048 ++ ++#define WR_ENABLE 1 ++#define WR_DISABLE 0 ++ ++/* i/o mode */ ++#define SPINAND_1X_READ 0x01 ++#define SPINAND_2X_READ 0x02 ++#define SPINAND_4X_READ 0x04 ++#define SPINAND_1X_WRITE 0x10 ++#define SPINAND_2X_WRITE 0x20 ++#define SPINAND_4X_WRITE 0x40 ++ ++ ++/* The max num of chip select current support */ ++#define NUM_CHIP_SELECT (2) ++ ++/* cmd */ ++#define CMD_READ 0x13 ++#define CMD_READ_RDM 0x03 ++#define CMD_PROG_PAGE_CLRCACHE 0x02 ++#define CMD_PROG_PAGE 0x84 ++#define CMD_PROG_PAGE_EXC 0x10 ++#define CMD_ERASE_BLK 0xd8 ++#define CMD_WR_ENABLE 0x06 ++#define CMD_WR_DISABLE 0x04 ++#define CMD_READ_ID 0x9f ++#define CMD_RESET 0xff ++#define CMD_READ_REG 0x0f ++#define CMD_WRITE_REG 0x1f ++ ++/* feature/ status reg */ ++#define REG_PROTECTION 0xa0 ++#define REG_FEATURE 0xb0 ++#define REG_STATUS 0xc0 /* timing */ ++#define REG_OUTPUT_DRIVER 0xd0 ++ ++/* status */ ++#define STATUS_OIP_MASK 0x01 ++#define STATUS_READY 0 << 0 ++#define STATUS_BUSY 1 << 0 ++ ++#define STATUS_E_FAIL_MASK 0x04 ++#define STATUS_E_FAIL 1 << 2 ++ ++#define STATUS_P_FAIL_MASK 0x08 ++#define STATUS_P_FAIL 1 << 3 ++ ++#define STATUS_ECC_MASK 0x30 ++#define STATUS_ECC_1BIT_CORRECTED 1 << 4 ++#define STATUS_ECC_ERROR 2 << 4 ++#define STATUS_ECC_RESERVED 3 << 4 ++ ++/* Output Driver */ ++#define OPD_DRV_MASK 0x60 ++#define OPD_DRV_S1_MASK 0x40 ++#define OPD_DRV_S0_MASK 0x20 ++ ++/* ECC enable defines */ ++#define OTP_ECC_MASK 0x10 ++//#define OTP_ECC_OFF 0 ++//#define OTP_ECC_ON 1 ++ ++//#define ECC_DISABLED ++//#define ECC_IN_NAND ++//#define ECC_SOFT ++ ++/* block lock */ ++#define BL_ALL_LOCKED 0x38 ++#define BL_1_2_LOCKED 0x30 ++#define BL_1_4_LOCKED 0x28 ++#define BL_1_8_LOCKED 0x20 ++#define BL_1_16_LOCKED 0x18 ++#define BL_1_32_LOCKED 0x10 ++#define BL_1_64_LOCKED 0x08 ++#define BL_ALL_UNLOCKED 0 ++ ++/****************************************************************************/ ++/* ++******************************************************************************* ++** ++** serial flash specific commands and statis register bit definitions ++** ++******************************************************************************* ++*/ ++typedef struct ++{ ++ uint32_t writeEnable; // command to enable a write/erase sequence ++ uint32_t writeDisable; // command to disable a write/erase sequence ++ uint32_t getFeatures; // command to read from status register ++ uint32_t setFeatures; // command to write to status register ++ uint32_t pageRead; // command to read data to cache ++ uint32_t readCache; // command to read data from cache ++ uint32_t readCacheX2; // command to read data from cache X 2 ++ uint32_t readCacheX4; // command to read data from cache X 4 ++ uint32_t readCacheIO2; // command to read data from cache by IO2 ++ uint32_t readCacheIO4; // command to read data from cache by IO4 ++ uint32_t readID; // command to read the chip identification ++ uint32_t programLoad; // command to program a page ++ uint32_t programLoadX4; // command to program a page X 4 ++ uint32_t progExecute; // command to program execute ++ uint32_t progLoadRand; // command to program a page ++ uint32_t progLoadRandX4; // command to program a page X 4 ++ uint32_t progLoadRandIO2; // command to program a page by IO2 ++ uint32_t blockErase; // command to erase a block ++ uint32_t reset; // status register mask for bit write-in-progress ++ ++}spinand_cmd_t; ++ ++/* ++******************************************************************************* ++** ++** serial flash specific geometry and information data structure ++** ++******************************************************************************* ++*/ ++struct spinand_info { ++ uint8_t mid; ++ uint16_t did; ++ char* manuname; ++ char* deviceName; // Pointer to device name ++ uint32_t nand_size; ++ uint32_t usable_size; ++ ++ uint32_t block_size; ++ uint32_t block_main_size; ++ uint32_t block_per_chip; ++ ++ uint32_t page_size; ++ uint32_t page_main_size; ++ uint32_t page_spare_size; ++ uint32_t page_per_block; ++ ++ uint32_t block_shift; ++ uint32_t block_mask; ++ ++ uint32_t page_shift; ++ uint32_t page_mask; /* use to calc the offset address of byte in page */ ++ ++ spinand_cmd_t* commands; /* Device specific access commands */ ++ uint32_t feature; /* bit0(IO1 read) bit1(IO2 read) bit2(IO4 read) ++ bit4(IO1 write) bit5(IO2 write) bit6(IO4 write) */ ++ uint32_t channel; ++ ++ struct nand_ecclayout *ecclayout; ++ ++ int badblockbits; ++ struct nand_bbt_descr *badblock_pattern; ++ ++}; ++ ++struct spinand_chip { /* used for multi chip */ ++ ++ struct mutex lock; ++ struct spinand_info *info; ++ struct mtd_info *mtd; ++ ++ int (*reset) (struct spinand_chip *chip); ++ int (*read_id) (struct spinand_chip *chip, uint32_t* id); ++ int (*read_page) (struct spinand_chip *chip, uint32_t page_id, ++ uint32_t offset, uint32_t len, uint8_t* rbuf); ++ int (*read_page_raw) (struct spinand_chip *chip, uint32_t page_id, ++ uint32_t offset, uint32_t len, uint8_t* rbuf); ++ int (*program_page) (struct spinand_chip *chip, uint32_t page_id, ++ uint32_t offset, uint32_t len, uint8_t* wbuf); ++ int (*program_page_raw) (struct spinand_chip *chip, uint32_t page_id, ++ uint32_t offset, uint32_t len, uint8_t* wbuf); ++ int (*erase_block) (struct spinand_chip *chip, uint32_t block_id); ++ int (*scan_bbt)(struct mtd_info *mtd); ++ int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); ++ int (*block_bad)(struct mtd_info *mtd, loff_t ofs); ++ ++ u8 *pagebuf; ++ u8 *oobbuf; /* temp buffer */ ++ ++ unsigned int *tmpbuf; /* temp buffer */ ++ ++ int page_id; ++ int phys_erase_shift; ++ int bbt_erase_shift; ++ int page_shift; ++ int pagemask; ++ int chip_id; ++ uint64_t chipsize; ++ int badblockpos; ++ int badblockbits; ++ ++ int chip_delay; ++ unsigned int options; ++ unsigned int bbt_options; ++ ++ uint8_t *oob_poi; ++ struct nand_ecclayout *ecclayout; ++ struct nand_buffers *buffers; ++ ++ uint8_t *bbt; ++ struct nand_bbt_descr *bbt_td; ++ struct nand_bbt_descr *bbt_md; ++ ++ struct nand_bbt_descr *badblock_pattern; ++ ++ void *priv; ++ ++}; ++ ++extern int spinand_scan(struct mtd_info * mtd); ++extern int spinand_update_bbt(struct mtd_info *mtd, loff_t offs); ++extern int spinand_default_bbt(struct mtd_info *mtd); ++extern int spinand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); ++extern int spinand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt); ++ ++ ++#endif /* __LINUX_MTD_SPINAND_H */ ++ ++ ++ +diff --git a/drivers/mtd/spinand/spinand_base.c b/drivers/mtd/spinand/spinand_base.c +new file mode 100644 +index 00000000..74c452e0 +--- /dev/null ++++ b/drivers/mtd/spinand/spinand_base.c +@@ -0,0 +1,1496 @@ ++/* ++ * drivers/mtd/spinand/spinand_base.c ++ * ++ * Overview: ++ * This is the generic MTD driver for SPI NAND flash devices. It should be ++ * capable of working with almost all SPI NAND chips currently available. ++ * ++ * Copyright (c) 2013 Gofortune Semiconductor Corporation. ++ * Kewell Liu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "spinand.h" ++ ++ ++/******************************************************/ ++/* MTD Part ( Hardware Independent ) */ ++/******************************************************/ ++ ++static int spinand_check_offs_len(struct mtd_info *mtd, ++ loff_t ofs, uint64_t len) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ int ret = 0; ++ ++ /* Start address must align on block boundary */ ++ if (ofs & ((1 << chip->phys_erase_shift) - 1)) { ++ pr_err("%s: unaligned address\n", __func__); ++ ret = -EINVAL; ++ } ++ ++ /* Length must align on block boundary */ ++ if (len & ((1 << chip->phys_erase_shift) - 1)) { ++ pr_err("%s: length not block aligned\n", __func__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++ ++} ++ ++/** ++ * nand_transfer_oob - [INTERN] Transfer oob to client buffer ++ * @chip: nand chip structure ++ * @oob: oob destination address ++ * @ops: oob ops structure ++ * @len: size of oob to transfer ++ */ ++static int spinand_transfer_oob(struct spinand_chip *chip, uint8_t *oob, ++ struct mtd_oob_ops *ops, size_t len) ++{ ++ struct spinand_info *info = chip->info; ++ ++ switch (ops->mode) { ++ ++ case MTD_OPS_PLACE_OOB: ++ case MTD_OPS_RAW: ++ memcpy(oob, (chip->oob_poi + ops->ooboffs), len); ++ ops->ooboffs = 0; //for second read ++ return 0; ++ ++ case MTD_OPS_AUTO_OOB: { ++ struct nand_oobfree *free = info->ecclayout->oobfree; ++ uint32_t boffs = 0, roffs = ops->ooboffs; ++ size_t bytes = 0; ++ ++ for (; free->length && len; free++, len -= bytes) { ++ /* Read request not from offset 0? */ ++ if (unlikely(roffs)) { ++ if (roffs >= free->length) { ++ roffs -= free->length; ++ continue; ++ } ++ boffs = free->offset + roffs; ++ bytes = min_t(size_t, len, ++ (free->length - roffs)); ++ roffs = 0; ++ } else { ++ bytes = min_t(size_t, len, free->length); ++ boffs = free->offset; ++ } ++ memcpy(oob, (chip->oob_poi + boffs), bytes); ++ oob += bytes; ++ } ++ return 0; ++ } ++ default: ++ BUG(); ++ } ++ ++ return -EINVAL; ++ ++} ++ ++/** ++ * spinand_fill_oob - [INTERN] Transfer client buffer to oob ++ * @mtd: MTD device structure ++ * @oob: oob data buffer ++ * @len: oob data write length ++ * @ops: oob ops structure ++ */ ++static int spinand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, ++ struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ ++ /* ++ * Initialise to all 0xFF, to avoid the possibility of left over OOB ++ * data from a previous OOB read. ++ */ ++ memset(chip->oob_poi, 0xff, mtd->oobsize); ++ ++ switch (ops->mode) { ++ ++ case MTD_OPS_PLACE_OOB: ++ case MTD_OPS_RAW: ++ memcpy(chip->oob_poi + ops->ooboffs, oob, len); ++ ops->ooboffs = 0; //for second write ++ return 0; ++ ++ case MTD_OPS_AUTO_OOB: { ++ struct nand_oobfree *free = info->ecclayout->oobfree; ++ uint32_t boffs = 0, woffs = ops->ooboffs; ++ size_t bytes = 0; ++ ++ for (; free->length && len; free++, len -= bytes) { ++ /* Write request not from offset 0? */ ++ if (unlikely(woffs)) { ++ if (woffs >= free->length) { ++ woffs -= free->length; ++ continue; ++ } ++ boffs = free->offset + woffs; ++ bytes = min_t(size_t, len, ++ (free->length - woffs)); ++ woffs = 0; ++ } else { ++ bytes = min_t(size_t, len, free->length); ++ boffs = free->offset; ++ } ++ memcpy(chip->oob_poi + boffs, oob, bytes); ++ oob += bytes; ++ } ++ return 0; ++ } ++ default: ++ BUG(); ++ } ++ ++ return -EINVAL; ++ ++} ++ ++/** ++ * spinand_check_wp - [GENERIC] check if the chip is write protected ++ * @mtd: MTD device structure ++ * ++ * Check, if the device is write protected. The function expects, that the ++ * device is already selected. ++ */ ++static int spinand_check_wp(struct mtd_info *mtd) ++{ ++ //struct spinand_chip *chip = mtd->priv; ++ ++ /* Broken xD cards report WP despite being writable */ ++ ++ /* Check the WP bit */ ++ //chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); ++ //return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; ++ return 0; ++} ++ ++/** ++ * spinand_block_checkbad - [GENERIC] Check if a block is marked bad ++ * @mtd: MTD device structure ++ * @ofs: offset from device start ++ * @allowbbt: 1, if its allowed to access the bbt area ++ * ++ * Check, if the block is bad. Either by reading the bad block table or ++ * calling of the scan function. ++ */ ++static int spinand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ ++ if (!chip->bbt) ++ return chip->block_bad(mtd, ofs); ++ ++ /* Return info from the table */ ++ return spinand_isbad_bbt(mtd, ofs, allowbbt); ++} ++ ++/** ++ * spinand_do_read_oob - [INTERN] NAND read out-of-band ++ * @mtd: MTD device structure ++ * @from: offset to read from ++ * @ops: oob operations description structure ++ * ++ * NAND read out-of-band data from the spare area. ++ */ ++static int spinand_do_read_oob(struct mtd_info *mtd, loff_t from, ++ struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ uint32_t page_id, oob_num; ++ ++ uint32_t count; ++ uint32_t oob_ok, oob_left; ++ ++ int readlen = ops->ooblen; ++ int ooblen; ++ ++ signed int retval; ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("%s: from = 0x%08Lx, len = %i\n", ++ __func__, (unsigned long long)from, readlen); ++ #endif ++ ++ if (ops->mode == MTD_OPS_AUTO_OOB) ++ { ++ ooblen = mtd->oobavail; ++ } ++ else ++ { ++ ooblen = mtd->oobsize; ++ } ++ ++ if (unlikely(ops->ooboffs >= ooblen)) { ++ dev_err(&mtd->dev, "%s: attempt to start read outside oob\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely(from >= mtd->size || ++ ops->ooboffs + readlen > ((mtd->size >> info->page_shift) - ++ (from >> info->page_shift)) * ooblen)) { ++ dev_err(&mtd->dev, "%s: attempt to read beyond end of device\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Shift to get page */ ++ page_id = (uint32_t)(from >> info->page_shift); ++ ++ /* for oob */ ++ oob_num = (ops->ooblen + ooblen -1) / ooblen; ++ ++ count = 0; ++ ++ oob_left = ops->ooblen; ++ oob_ok = 0; ++ ++#ifdef CONFIG_DEBUG_R ++ pr_info("page_id 0x%08x\n" ++ "oob_num 0x%08x\n" ++ "ooblen 0x%08x\n" ++ "oob_left 0x%08x\n", ++ page_id, ++ oob_num, ++ ooblen, ++ oob_left); ++#endif ++ ++ while (1) ++ { ++ if (count < oob_num) ++ { ++ memset(chip->oob_poi, 0, info->page_spare_size); ++ if(ops->mode == MTD_OPS_RAW) ++ { ++ retval = chip->read_page_raw(chip, (page_id + count), info->page_main_size, ++ info->page_spare_size, chip->oob_poi); ++ } ++ else ++ { ++ retval = chip->read_page(chip, (page_id + count), info->page_main_size, ++ info->page_spare_size, chip->oob_poi); ++ } ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "%s: fail, block = %d, PageId = 0x%08x\n", __FUNCTION__, ++ ((page_id + count)/info->page_per_block), (page_id + count)); ++ return -EBADMSG; ++ } ++ ++ #ifdef CONFIG_DEBUG_R ++ { ++ int i = 0; ++ ++ for(i = 0; i < mtd->oobsize; i++) ++ { ++ if(i % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", chip->oob_poi[i]); ++ } ++ ++ printk("\n"); ++ } ++ #endif ++ } ++ else ++ { ++ break; ++ } ++ ++ if (count < oob_num && ops->oobbuf && chip->oob_poi) ++ { ++ int size; ++ ++ /* copy oobbuf to ops oobbuf */ ++ if (oob_left < ooblen) ++ { ++ size = oob_left; ++ } ++ else ++ { ++ size = ooblen; ++ } ++ ++ retval = spinand_transfer_oob(chip, (ops->oobbuf + oob_ok), ops, size); ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail oob mode = %d!\n", __FUNCTION__, ops->mode); ++ return -EUCLEAN; ++ } ++ ++ oob_ok += size; ++ oob_left -= size; ++ ++ ops->oobretlen = oob_ok; ++ ++ } ++ ++ count++; ++ ++ } ++ ++ return 0; ++ ++} ++ ++ ++static int spinand_do_read_ops(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ uint32_t page_id, page_offset, page_num, oob_num = 0; ++ ++ uint32_t count; ++ uint32_t main_ok, main_left, main_offset; ++ uint32_t oob_ok, oob_left; ++ ++ signed int retval; ++ int ooblen; ++ ++ if (!chip->buffers) ++ return -ENOMEM; ++ ++ if (ops->mode == MTD_OPS_AUTO_OOB) ++ { ++ ooblen = mtd->oobavail; ++ } ++ else ++ { ++ ooblen = mtd->oobsize; ++ } ++ ++ page_id = (uint32_t)(from >> info->page_shift); ++ ++ /* for main data */ ++ page_offset = (uint32_t)(from & info->page_mask); ++ page_num = (page_offset + ops->len + info->page_main_size -1 ) / info->page_main_size; ++ ++ /* for oob */ ++ if(ooblen) ++ oob_num = (ops->ooblen + ooblen - 1) / ooblen; ++ ++ count = 0; ++ ++ main_left = ops->len; ++ main_ok = 0; ++ main_offset = page_offset; ++ ++ oob_left = ops->ooblen; ++ oob_ok = 0; ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[DEBUG_R]:%s\n",__FUNCTION__); ++ pr_info("page_id 0x%08x\n" ++ "page_offset 0x%08x\n" ++ "page_num 0x%08x\n" ++ "oob_num 0x%08x\n" ++ "main_left 0x%08x\n" ++ "main_offset 0x%08x\n" ++ "oob_left 0x%08x\n", ++ page_id, ++ page_offset, ++ page_num, ++ oob_num, ++ main_left, ++ main_offset, ++ oob_left); ++ #endif ++ ++ while (1) ++ { ++ if (count < page_num || count < oob_num) ++ { ++ memset(chip->pagebuf, 0, info->page_size); ++ retval = chip->read_page(chip, (page_id + count), 0, info->page_size, chip->pagebuf); ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "%s: fail, block = %d, PageId = 0x%08x\n", __FUNCTION__, ++ ((page_id + count)/info->page_per_block), (page_id + count)); ++ return -EBADMSG; ++ } ++ } ++ else ++ { ++ break; ++ } ++ ++ if (count < page_num && ops->datbuf) ++ { ++ int size; ++ ++ if ((main_offset + main_left) < info->page_main_size) ++ { ++ size = main_left; ++ } ++ else ++ { ++ size = info->page_main_size - main_offset; ++ } ++ ++ memcpy((ops->datbuf + main_ok), (chip->pagebuf + main_offset), size); ++ ++ main_ok += size; ++ main_left -= size; ++ main_offset = 0; ++ ++ ops->retlen = main_ok; ++ } ++ ++ if (count < oob_num && ops->oobbuf && chip->oob_poi) ++ { ++ int size; ++ ++ /* copy oobbuf to ops oobbuf */ ++ if (oob_left < ooblen) ++ { ++ size = oob_left; ++ } ++ else ++ { ++ size = ooblen; ++ } ++ ++ retval = spinand_transfer_oob(chip, (ops->oobbuf + oob_ok), ops, size); ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail oob mode = %d!\n", __FUNCTION__, ops->mode); ++ return -EUCLEAN; ++ } ++ ++ oob_ok += size; ++ oob_left -= size; ++ ++ ops->oobretlen = oob_ok; ++ ++ } ++ ++ count++; ++ ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_do_write_oob - [MTD Interface] NAND write out-of-band ++ * @mtd: MTD device structure ++ * @to: offset to write to ++ * @ops: oob operation description structure ++ * ++ * NAND write out-of-band. ++ */ ++static int spinand_do_write_oob(struct mtd_info *mtd, loff_t to, ++ struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ uint32_t page_id, oob_num; ++ ++ uint32_t count; ++ uint32_t oob_ok, oob_left; ++ ++ uint32_t ooblen; ++ ++ signed int retval; ++ ++ #ifdef CONFIG_DEBUG_W ++ pr_info("%s: to = 0x%08x, len = %i\n", ++ __func__, (unsigned int)to, (int)ops->ooblen); ++ #endif ++ ++ if (ops->mode == MTD_OPS_AUTO_OOB) ++ ooblen = mtd->oobavail; ++ else ++ ooblen = mtd->oobsize; ++ ++ /* Do not allow write past end of page */ ++ if ((ops->ooboffs + ops->ooblen) > ooblen) { ++ dev_err(&mtd->dev, "%s: attempt to write past end of page\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely(ops->ooboffs >= ooblen)) { ++ dev_err(&mtd->dev, "%s: attempt to start write outside oob\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Do not allow write past end of device */ ++ if (unlikely(to >= mtd->size || ++ ops->ooboffs + ops->ooblen > ++ ((mtd->size >> info->page_shift) - ++ (to >> info->page_shift)) * ooblen)) { ++ dev_err(&mtd->dev, "%s: attempt to write beyond end of device\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Shift to get page */ ++ page_id = (uint32_t)(to >> info->page_shift); ++ ++ /* Check, if it is write protected */ ++ if (spinand_check_wp(mtd)) ++ return -EROFS; ++ ++ /* Invalidate the page cache, if we write to the cached page */ ++ if (page_id == chip->page_id) ++ chip->page_id = -1; ++ ++ /* for oob */ ++ oob_num = (ops->ooblen + ooblen - 1) / ooblen; ++ ++ count = 0; ++ ++ oob_left = ops->ooblen; ++ oob_ok = 0; ++ ++ memset(chip->pagebuf, 0xff, mtd->writesize); ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("page_id 0x%08x\n" ++ "oob_num 0x%08x\n" ++ "ooblen 0x%08x\n" ++ "oob_left 0x%08x\n", ++ page_id, ++ oob_num, ++ ooblen, ++ oob_left); ++#endif ++ while (1) ++ { ++ uint32_t size; ++ ++ if(count >= oob_num) ++ { ++ break; ++ } ++ ++ if (oob_left < ooblen) ++ { ++ size = oob_left; ++ } ++ else ++ { ++ size = ooblen; ++ } ++ ++ if (ops->oobbuf && chip->oob_poi) ++ { ++ retval = spinand_fill_oob(mtd, (ops->oobbuf + oob_ok), size, ops); ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail oob mode = %d!\n", __FUNCTION__, ops->mode); ++ return -EPERM; ++ } ++ oob_ok += size; ++ ops->oobretlen = oob_ok; ++ ++ #ifdef CONFIG_DEBUG_W ++ { ++ int i = 0, j = 0; ++ ++ for(i = 0,j = 0; i < mtd->oobsize; i++,j++) ++ { ++ if(j % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", chip->oob_poi[i]); ++ } ++ ++ printk("\n"); ++ } ++ #endif ++ } ++ ++ if (ops->mode == MTD_OPS_RAW) ++ { ++ retval = chip->program_page_raw(chip, (page_id + count), ++ info->page_main_size, info->page_spare_size, chip->pagebuf); ++ } ++ else ++ { ++ retval = chip->program_page(chip, (page_id + count), ++ info->page_main_size, info->page_spare_size, chip->pagebuf); ++ } ++ ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail, block = %d, PageId = 0x%08x\n", __FUNCTION__, ++ ((page_id + count)/info->page_per_block), (page_id + count)); ++ return -EPERM; ++ } ++ ++ count++; ++ ++ } ++ ++ return 0; ++ ++} ++ ++static int spinand_do_write_ops(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ ++ uint32_t page_id, page_offset, page_num, oob_num = 0; ++ ++ int count; ++ ++ int main_ok, main_left, main_offset; ++ int oob_ok, oob_left; ++ ++ uint32_t ooblen; ++ ++ signed int retval; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("%s: \n" ++ "to = 0x%08x,\n" ++ "len = %i,\n" ++ "ooblen = %i\n", __func__, (unsigned int)to, (int)ops->len,(int)ops->ooblen); ++#endif ++ ++ if (!chip->buffers) ++ return -ENOMEM; ++ ++ if (ops->mode == MTD_OPS_AUTO_OOB) ++ ooblen = mtd->oobavail; ++ else ++ ooblen = mtd->oobsize; ++ ++ page_id = (uint32_t)(to >> info->page_shift); ++ ++ /* Check, if it is write protected */ ++ if (spinand_check_wp(mtd)) ++ return -EROFS; ++ ++ /* for main data */ ++ page_offset = to & info->page_mask; ++ page_num = (page_offset + ops->len + info->page_main_size - 1 ) / info->page_main_size; ++ ++ /* for oob */ ++ if(ooblen) ++ oob_num = (ops->ooblen + ooblen - 1) / ooblen; ++ ++ count = 0; ++ ++ main_left = ops->len; ++ main_ok = 0; ++ main_offset = page_offset; ++ ++ oob_left = ops->ooblen; ++ oob_ok = 0; ++ ++#ifdef CONFIG_DEBUG_W ++ ++ pr_info("page_id 0x%08x\n" ++ "page_offset 0x%08x\n" ++ "page_num 0x%08x\n" ++ "oob_num 0x%08x\n" ++ "main_left 0x%08x\n" ++ "main_offset 0x%08x\n" ++ "oob_left 0x%08x\n", ++ page_id, ++ page_offset, ++ page_num, ++ oob_num, ++ main_left, ++ main_offset, ++ oob_left); ++#endif ++ ++ while (1) ++ { ++ if (count < page_num || count < oob_num) ++ { ++ memset(chip->pagebuf, 0xFF, info->page_size); ++ } ++ else ++ { ++ break; ++ } ++ ++ if (count < page_num && ops->datbuf) ++ { ++ int size; ++ ++ if ((main_offset + main_left) < info->page_main_size) ++ { ++ size = main_left; ++ } ++ else ++ { ++ size = info->page_main_size - main_offset; ++ } ++ ++ memcpy ((chip->pagebuf + main_offset), (ops->datbuf + main_ok), size); ++ ++ main_ok += size; ++ main_left -= size; ++ } ++ ++ if (count < oob_num && ops->oobbuf && chip->oob_poi) ++ { ++ int size; ++ ++ if (oob_left < ooblen) ++ { ++ size = oob_left; ++ } ++ else ++ { ++ size = ooblen; ++ } ++ ++ retval = spinand_fill_oob(mtd, (ops->oobbuf + oob_ok), size, ops); ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail oob mode = %d!\n", __FUNCTION__, ops->mode); ++ return -EPERM; ++ } ++ ++ oob_ok += size; ++ oob_left -= size; ++ ++ } ++ ++ if (count < page_num || count < oob_num) ++ { ++ #ifdef CONFIG_DEBUG_W ++ { ++ int i = 0; ++ ++ for(i = 0; i < 64; i++) ++ { ++ if(i % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", chip->pagebuf[i]); ++ } ++ ++ printk("\n"); ++ } ++ #endif ++ ++ if(oob_num > 0) ++ { ++ retval = chip->program_page(chip, (page_id + count), main_offset, ++ info->page_size, chip->pagebuf); ++ } ++ else ++ { ++ retval = chip->program_page(chip, (page_id + count), main_offset, ++ info->page_main_size, chip->pagebuf); ++ } ++ ++ if (retval != 0) ++ { ++ dev_err(&mtd->dev, "[%s]: fail, block = %d, PageId = 0x%08x\n", __FUNCTION__, ++ ((page_id + count)/info->page_per_block), (page_id + count)); ++ return -EPERM; ++ } ++ ++ main_offset = 0; ++ ++ } ++ ++ if (count < page_num && ops->datbuf) ++ { ++ ops->retlen = main_ok; ++ } ++ ++ if (count < oob_num && ops->oobbuf && chip->oob_poi) ++ { ++ ops->oobretlen = oob_ok; ++ } ++ ++ count++; ++ ++ } ++ ++ return 0; ++ ++} ++ ++static int spinand_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct mtd_oob_ops ops = {0}; ++ int ret; ++ ++ /* Do not allow reads past end of device */ ++ if ((from + len) > mtd->size) ++ return -EINVAL; ++ ++ if (!len) ++ return 0; ++ ++ mutex_lock(&chip->lock); ++ ++ ops.mode = 0; ++ ops.len = len; ++ ops.datbuf = buf; ++ ops.ooblen = 0; ++ ops.oobbuf = NULL; ++ ++ #ifdef CONFIG_DEBUG_R ++ pr_info("[DEBUG_R]:%s\n",__FUNCTION__); ++ pr_info("from 0x%llx\n" ++ "len 0x%x\n", ++ from, ++ len); ++ #endif ++ ++ ret = spinand_do_read_ops(mtd, from, &ops); ++ ++ *retlen = ops.retlen; ++ ++ mutex_unlock(&chip->lock); ++ ++ return ret; ++ ++} ++ ++static int spinand_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct mtd_oob_ops ops = {0}; ++ int ret; ++ ++ /* Do not allow reads past end of device */ ++ if ((to + len) > mtd->size) ++ return -EINVAL; ++ if (!len) ++ return 0; ++ ++ mutex_lock(&chip->lock); ++ ++ ops.len = len; ++ ops.datbuf = (uint8_t *)buf; ++ ops.ooblen = 0; ++ ops.oobbuf = NULL; ++ ops.mode = 0; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[DEBUG_W]:%s\n",__FUNCTION__); ++ pr_info("to 0x%llx\n" ++ "len 0x%x\n", ++ to, ++ len); ++#endif ++ ++ ret = spinand_do_write_ops(mtd, to, &ops); ++ ++ *retlen = ops.retlen; ++ ++ mutex_unlock(&chip->lock); ++ ++ return ret; ++ ++} ++ ++static int spinand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ int ret = -ENOTSUPP; ++ ++ ops->retlen = 0; ++ ++ /* Do not allow reads past end of device */ ++ if (ops->datbuf && (from + ops->len) > mtd->size) { ++ dev_err(&mtd->dev, "%s: attempt to read beyond end of device\n", __func__); ++ return -EINVAL; ++ } ++ ++ switch (ops->mode) { ++ case MTD_OPS_PLACE_OOB: ++ case MTD_OPS_AUTO_OOB: ++ case MTD_OPS_RAW: ++ break; ++ ++ default: ++ dev_err(&mtd->dev, "%s: The mode = %d no supported\n", __func__, ops->mode); ++ goto out; ++ } ++ ++ mutex_lock(&chip->lock); ++ ++ if (!ops->datbuf) ++ ret = spinand_do_read_oob(mtd, from, ops); ++ else ++ ret = spinand_do_read_ops(mtd, from, ops); ++ ++ mutex_unlock(&chip->lock); ++out: ++ ++ return ret; ++ ++} ++ ++/** ++ * spinand_write_oob - [MTD Interface] NAND write data and/or out-of-band ++ * @mtd: MTD device structure ++ * @to: offset to write to ++ * @ops: oob operation description structure ++ */ ++static int spinand_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ int ret = -ENOTSUPP; ++ ++ ops->retlen = 0; ++ ++ /* Do not allow writes past end of device */ ++ if (ops->datbuf && (to + ops->len) > mtd->size) { ++ pr_debug("%s: attempt to write beyond end of device\n", __func__); ++ return -EINVAL; ++ } ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[DEBUG_W]:%s\n",__FUNCTION__); ++ pr_info("to 0x%llx\n" ++ "len 0x%x\n" ++ "ooblen 0x%x\n", ++ to, ++ ops->len, ops->ooblen); ++#endif ++ ++ ++ switch (ops->mode) { ++ case MTD_OPS_PLACE_OOB: ++ case MTD_OPS_AUTO_OOB: ++ case MTD_OPS_RAW: ++ break; ++ ++ default: ++ dev_err(&mtd->dev, "%s: The mode = %d no supported\n", __func__, ops->mode); ++ goto out; ++ } ++ ++ mutex_lock(&chip->lock); ++ ++ if (!ops->datbuf) ++ ret = spinand_do_write_oob(mtd, to, ops); ++ else ++ ret = spinand_do_write_ops(mtd, to, ops); ++ ++ mutex_unlock(&chip->lock); ++ ++out: ++ ++ return ret; ++ ++} ++ ++#define BBT_PAGE_MASK 0xffffff3f ++/** ++ * spinand_erase_nand - [INTERN] erase block(s) ++ * @mtd: MTD device structure ++ * @instr: erase instruction ++ * @allowbbt: allow erasing the bbt area ++ * ++ * Erase one ore more blocks. ++ */ ++int spinand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt) ++{ ++ int page, pages_per_block, ret; ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ ++ loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; ++ unsigned int bbt_masked_page = 0xffffffff; ++ loff_t len; ++ ++ pr_debug("%s: start = 0x%012llx, len = %llu\n", ++ __func__, (unsigned long long)instr->addr, ++ (unsigned long long)instr->len); ++ ++ if (spinand_check_offs_len(mtd, instr->addr, instr->len)) ++ return -EINVAL; ++ ++ /* Do not allow erase past end of device */ ++ if ((instr->len + instr->addr) > info->usable_size) { ++ pr_err("%s: Erase past end of device\n",__FUNCTION__); ++ return -EINVAL; ++ } ++ ++ mutex_lock(&chip->lock); ++ ++ /* Grab the lock and see if the device is available */ ++ //nand_get_device(chip, mtd, FL_ERASING); ++ ++ /* Shift to get first page */ ++ page = (int)(instr->addr >> chip->page_shift); ++ page &= chip->pagemask; ++ ++ /* Calculate pages in each block */ ++ pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); ++ ++ /* Check, if it is write protected */ ++ if (spinand_check_wp(mtd)) { ++ pr_debug("%s: device is write protected!\n", __func__); ++ instr->state = MTD_ERASE_FAILED; ++ goto erase_exit; ++ } ++ ++ /* ++ * If BBT requires refresh, set the BBT page mask to see if the BBT ++ * should be rewritten. Otherwise the mask is set to 0xffffffff which ++ * can not be matched. This is also done when the bbt is actually ++ * erased to avoid recursive updates. ++ */ ++ if (chip->options & BBT_AUTO_REFRESH && !allowbbt) ++ bbt_masked_page = chip->bbt_td->pages[0] & BBT_PAGE_MASK; ++ ++ /* Loop through the pages */ ++ len = instr->len; ++ ++ instr->state = MTD_ERASING; ++ ++ while (len) ++ { ++ /* Check if we have a bad block, we do not erase bad blocks! */ ++ if (spinand_block_checkbad(mtd, ((loff_t) page) << chip->page_shift, allowbbt)) ++ { ++ pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", __func__, page); ++ instr->state = MTD_ERASE_FAILED; ++ goto erase_exit; ++ } ++ ++ ret = chip->erase_block(chip, (uint32_t)page); ++ ++ /* See if block erase succeeded */ ++ if (ret != 0) ++ { ++ ret = chip->erase_block(chip, (uint32_t)page); ++ if (ret != 0) ++ { ++ pr_err("%s: failed erase, block = %d!\n", __FUNCTION__, ++ (uint32_t)(page/pages_per_block)); ++ instr->state = MTD_ERASE_FAILED; ++ instr->fail_addr = ((loff_t)page << chip->page_shift); ++ goto erase_exit; ++ } ++ } ++ ++ /* ++ * If BBT requires refresh, set the BBT rewrite flag to the ++ * page being erased. ++ */ ++ if (bbt_masked_page != 0xffffffff && (page & BBT_PAGE_MASK) == bbt_masked_page) ++ rewrite_bbt[0] = ((loff_t)page << chip->page_shift); ++ ++ /* Increment page address and decrement length */ ++ len -= (1 << chip->phys_erase_shift); ++ page += pages_per_block; ++ ++ } ++ instr->state = MTD_ERASE_DONE; ++ ++erase_exit: ++ ++ mutex_unlock(&chip->lock); ++ ++ ret = (instr->state == MTD_ERASE_DONE ? 0 : -EIO); ++ ++ /* Do call back function */ ++ if (!ret) ++ mtd_erase_callback(instr); ++ ++ /* ++ * If BBT requires refresh and erase was successful, rewrite any ++ * selected bad block tables. ++ */ ++ if (bbt_masked_page == 0xffffffff || ret) ++ return ret; ++ ++ if (rewrite_bbt[0]) ++ { ++ /* Update the BBT for chip */ ++ pr_debug("%s: update_bbt (0x%0llx 0x%08x)\n", ++ __func__, rewrite_bbt[0], chip->bbt_td->pages[0]); ++ spinand_update_bbt(mtd, rewrite_bbt[0]); ++ } ++ ++ /* Return more or less happy */ ++ return ret; ++ ++} ++ ++/** ++ * spinand_erase - [MTD Interface] erase block(s) ++ * @mtd: MTD device structure ++ * @instr: erase instruction ++ * ++ * Erase one ore more blocks. ++ */ ++static int spinand_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ return spinand_erase_nand(mtd, instr, 0); ++} ++ ++ ++/** ++ * spinand_sync - [MTD Interface] sync ++ * @param mtd MTD device structure ++ * ++ * Sync is actually a wait for chip ready function ++ */ ++static void spinand_sync(struct mtd_info *mtd) ++{ ++ dev_err(&mtd->dev, "spinand_sync: called\n"); ++} ++ ++/** ++ * spinand_block_isbad - [MTD Interface] Check if block at offset is bad ++ * @mtd: MTD device structure ++ * @offs: offset relative to mtd start ++ */ ++static int spinand_block_isbad(struct mtd_info *mtd, loff_t offs) ++{ ++ return spinand_block_checkbad(mtd, offs, 0); ++} ++ ++/** ++ * spinand_block_bad - [DEFAULT] Read bad block marker from the chip ++ * @mtd: MTD device structure ++ * @ofs: offset from device start ++ * ++ * Check, if the block is bad. ++ */ ++static int spinand_block_bad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ struct nand_bbt_descr *badblock_ptn = info->badblock_pattern; ++ uint32_t page_id; ++ uint16_t is_bad = 0; ++ int i = 0, res = 0; ++ ++ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) ++ ofs += mtd->erasesize - mtd->writesize; ++ ++ page_id = (uint32_t)(ofs >> chip->page_shift) & chip->pagemask; ++ ++ #ifdef KE_DEBUG_R ++ pr_debug("[%s]: page_id = 0x%08x, Ofs = 0x%08x\n", ++ __FUNCTION__, page_id, ofs); ++ #endif ++ ++ do ++ { ++ if (chip->options & NAND_BUSWIDTH_16) ++ { ++ chip->read_page(chip, page_id, ++ (info->page_main_size + chip->badblockpos), badblock_ptn->len, (uint8_t*)&is_bad); ++ is_bad = cpu_to_le16(is_bad); ++ if (chip->badblockpos & 0x1) ++ is_bad >>= 8; ++ else ++ is_bad &= 0xFF; ++ } ++ else ++ { ++ chip->read_page(chip, page_id, ++ (info->page_main_size + chip->badblockpos), badblock_ptn->len, (uint8_t*)&is_bad); ++ } ++ ++ if (likely(chip->badblockbits == 8)) ++ { ++ res = is_bad != 0xFF; ++ } ++ else ++ { ++ res = hweight8(is_bad) < chip->badblockbits; ++ } ++ ofs += mtd->writesize; ++ page_id = (uint32_t)(ofs >> chip->page_shift) & chip->pagemask; ++ i++; ++ } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); ++ ++ #ifdef KE_DEBUG_R ++ pr_debug("[%s]: Block = 0x%04x, is %s\n", ++ __FUNCTION__, (uint32_t)(ofs >> chip->bbt_erase_shift), (res > 0)? "bad":"good"); ++ #endif ++ ++ return res; ++ ++} ++ ++#if 0 ++ ++/** ++ * spinand_default_block_bad - [DEFAULT] Read bad block marker from the chip ++ * @mtd: MTD device structure ++ * @ofs: offset from device start ++ * ++ * Check, if the block is bad. ++ */ ++static int spinand_default_block_bad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ uint32_t page_id; ++ uint8_t is_bad = 0; ++ int ret = 0; ++ ++ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) ++ ofs += mtd->erasesize - mtd->writesize; ++ ++ page_id = (uint32_t)(ofs >> chip->page_shift); ++ ++ mutex_lock(&chip->lock); ++ ++ chip->read_page(chip, page_id, ++ (info->page_main_size + chip->badblockpos), 1, &is_bad); ++ ++ mutex_unlock(&chip->lock); ++ ++ if (is_bad != 0xff) ++ { ++ ret = 1; ++ } ++ ++ return ret; ++ ++} ++ ++#endif ++ ++/** ++ * spinand_default_block_markbad - [DEFAULT] mark a block bad ++ * @mtd: MTD device structure ++ * @ofs: offset from device start ++ * ++ * This is the default implementation, which can be overridden by a hardware ++ * specific driver. We try operations in the following order, according to our ++ * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): ++ * (1) erase the affected block, to allow OOB marker to be written cleanly ++ * (2) update in-memory BBT ++ * (3) write bad block marker to OOB area of affected block ++ * (4) update flash-based BBT ++ * Note that we retain the first error encountered in (3) or (4), finish the ++ * procedures, and dump the error in the end. ++*/ ++static int spinand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ uint8_t buf[2] = { 0, 0 }; ++ int block, res, ret = 0, i = 0; ++ int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); ++ ++ if (write_oob) { ++ struct erase_info einfo; ++ ++ /* Attempt erase before marking OOB */ ++ memset(&einfo, 0, sizeof(einfo)); ++ einfo.mtd = mtd; ++ einfo.addr = ofs; ++ einfo.len = 1 << chip->phys_erase_shift; ++ spinand_erase_nand(mtd, &einfo, 0); ++ } ++ ++ /* Get block number */ ++ block = (int)(ofs >> chip->bbt_erase_shift); ++ /* Mark block bad in memory-based BBT */ ++ if (chip->bbt) ++ chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); ++ ++ /* Write bad block marker to OOB */ ++ if (write_oob) ++ { ++ struct mtd_oob_ops ops; ++ loff_t wr_ofs = ofs; ++ ++ //nand_get_device(chip, mtd, FL_WRITING); ++ ++ ops.datbuf = NULL; ++ ops.oobbuf = buf; ++ ops.ooboffs = chip->badblockpos; ++ if (chip->options & NAND_BUSWIDTH_16) { ++ ops.ooboffs &= ~0x01; ++ ops.len = ops.ooblen = 2; ++ } else { ++ ops.len = ops.ooblen = 1; ++ } ++ ops.mode = MTD_OPS_PLACE_OOB; ++ ++ /* Write to first/last page(s) if necessary */ ++ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) ++ wr_ofs += mtd->erasesize - mtd->writesize; ++ do { ++ res = spinand_do_write_oob(mtd, wr_ofs, &ops); ++ if (!ret) ++ ret = res; ++ ++ i++; ++ wr_ofs += mtd->writesize; ++ } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); ++ ++ //nand_release_device(mtd); ++ } ++ ++ /* Update flash-based bad block table */ ++ if (chip->bbt_options & NAND_BBT_USE_FLASH) { ++ res = spinand_update_bbt(mtd, ofs); ++ if (!ret) ++ ret = res; ++ } ++ ++ if (!ret) ++ mtd->ecc_stats.badblocks++; ++ ++ return ret; ++ ++} ++ ++/** ++ * spinand_block_markbad - [MTD Interface] Mark bad block ++ * @param mtd MTD device structure ++ * @param ofs Bad block number ++ */ ++static int spinand_block_markbad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ uint32_t ret = 0; ++ ++ ret = spinand_block_isbad(mtd, ofs); ++ if (ret) ++ { ++ /* If it was bad already, return success and do nothing */ ++ if (ret > 0) ++ return 0; ++ return ret; ++ } ++ ++ return chip->block_markbad(mtd, ofs); ++} ++ ++ ++/** ++ * spinand_suspend - [MTD Interface] Suspend the spinand flash ++ * @param mtd MTD device structure ++ */ ++static int spinand_suspend(struct mtd_info *mtd) ++{ ++ return 0; ++} ++ ++/** ++ * spinand_resume - [MTD Interface] Resume the spinand flash ++ * @param mtd MTD device structure ++ */ ++static void spinand_resume(struct mtd_info *mtd) ++{ ++ return; ++} ++ ++/* Set default functions */ ++static void spinand_set_defaults(struct spinand_chip *chip) ++{ ++ /* check for proper chip_delay setup, set 20us if not */ ++ if (!chip->chip_delay) ++ chip->chip_delay = 20; ++ ++ if (!chip->scan_bbt) ++ chip->scan_bbt = spinand_default_bbt; ++ ++ if (!chip->block_markbad) ++ chip->block_markbad = spinand_default_block_markbad; ++ ++ if (!chip->block_bad) ++ chip->block_bad = spinand_block_bad; ++} ++ ++ ++/** ++ * spinand_scan - [SpiNAND Interface] Scan for the SpiNAND device ++ * @param mtd MTD device structure ++ * ++ * This fills out all the not initialized function pointers ++ * with the defaults. ++ * The flash ID is read and the mtd/chip structures are ++ * filled with the appropriate values. ++ */ ++int spinand_scan(struct mtd_info *mtd) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ struct spinand_info *info = chip->info; ++ ++ //chip->state = FL_READY; ++ //init_waitqueue_head(&chip->wq); ++ //spin_lock_init(&chip->chip_lock); ++ spinand_set_defaults(chip); ++ ++ mtd->name = info->deviceName; ++ mtd->size = info->usable_size; ++ mtd->erasesize = info->block_main_size; ++ mtd->writesize = info->page_main_size; ++ mtd->writebufsize = info->page_main_size; ++ mtd->oobsize = info->page_spare_size; ++ mtd->oobavail = info->ecclayout->oobavail; ++ mtd->owner = THIS_MODULE; ++ mtd->type = MTD_NANDFLASH; ++ mtd->flags = MTD_CAP_NANDFLASH; ++ mtd->ecclayout = info->ecclayout; ++ ++ mtd->_erase = spinand_erase; ++ mtd->_point = NULL; ++ mtd->_unpoint = NULL; ++ mtd->_read = spinand_read; ++ mtd->_write = spinand_write; ++ mtd->_read_oob = spinand_read_oob; ++ mtd->_write_oob = spinand_write_oob; ++ mtd->_sync = spinand_sync; ++ mtd->_lock = NULL; ++ mtd->_unlock = NULL; ++ mtd->_suspend = spinand_suspend; ++ mtd->_resume = spinand_resume; ++ mtd->_block_isbad = spinand_block_isbad; ++ mtd->_block_markbad = spinand_block_markbad; ++ ++ /* Check, if we should skip the bad block table scan */ ++ if (chip->options & NAND_SKIP_BBTSCAN) ++ return 0; ++ ++ /* Build bad block table */ ++ return chip->scan_bbt(mtd); ++ ++} ++ ++EXPORT_SYMBOL_GPL(spinand_scan); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Kewell Liu, "); ++MODULE_DESCRIPTION("SPI NAND driver code"); +diff --git a/drivers/mtd/spinand/spinand_bbt.c b/drivers/mtd/spinand/spinand_bbt.c +new file mode 100644 +index 00000000..9e2da341 +--- /dev/null ++++ b/drivers/mtd/spinand/spinand_bbt.c +@@ -0,0 +1,1602 @@ ++/* ++ * drivers/mtd/spinand/spinand_bbt.c ++ * ++ * Overview: ++ * Bad block table support for the SPI NAND driver ++ * ++ * Copyright (c) 2013 Gofortune Semiconductor Corporation. ++ * Kewell Liu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Description: ++ * ++ * When nand_scan_bbt is called, then it tries to find the bad block table ++ * depending on the options in the BBT descriptor(s). If no flash based BBT ++ * (NAND_BBT_USE_FLASH) is specified then the device is scanned for factory ++ * marked good / bad blocks. This information is used to create a memory BBT. ++ * Once a new bad block is discovered then the "factory" information is updated ++ * on the device. ++ * If a flash based BBT is specified then the function first tries to find the ++ * BBT on flash. If a BBT is found then the contents are read and the memory ++ * based BBT is created. If a mirrored BBT is selected then the mirror is ++ * searched too and the versions are compared. If the mirror has a greater ++ * version number than the mirror BBT is used to build the memory based BBT. ++ * If the tables are not versioned, then we "or" the bad block information. ++ * If one of the BBTs is out of date or does not exist it is (re)created. ++ * If no BBT exists at all then the device is scanned for factory marked ++ * good / bad blocks and the bad block tables are created. ++ * ++ * For manufacturer created BBTs like the one found on M-SYS DOC devices ++ * the BBT is searched and read but never created ++ * ++ * The auto generated bad block table is located in the last good blocks ++ * of the device. The table is mirrored, so it can be updated eventually. ++ * The table is marked in the OOB area with an ident pattern and a version ++ * number which indicates which of both tables is more up to date. If the NAND ++ * controller needs the complete OOB area for the ECC information then the ++ * option NAND_BBT_NO_OOB should be used (along with NAND_BBT_USE_FLASH, of ++ * course): it moves the ident pattern and the version byte into the data area ++ * and the OOB area will remain untouched. ++ * ++ * The table uses 2 bits per block ++ * 11b: block is good ++ * 00b: block is factory marked bad ++ * 01b, 10b: block is marked bad due to wear ++ * ++ * The memory bad block table uses the following scheme: ++ * 00b: block is good ++ * 01b: block is marked bad due to wear ++ * 10b: block is reserved (to protect the bbt area) ++ * 11b: block is factory marked bad ++ * ++ * Multichip devices like DOC store the bad block info per floor. ++ * ++ * Following assumptions are made: ++ * - bbts start at a page boundary, if autolocated on a block boundary ++ * - the space necessary for a bbt in FLASH does not exceed a block boundary ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "spinand.h" ++ ++#ifdef CONFIG_SELF_START_BLOCK ++#define START_BLOCK 18 ++#else ++#define START_BLOCK 0 ++#endif ++ ++ ++static int spinand_check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) ++{ ++ int ret; ++ ++ ret = memcmp(buf, td->pattern, td->len); ++ if (!ret) ++ return ret; ++ return -1; ++} ++ ++/** ++ * spinand_check_pattern - [GENERIC] check if a pattern is in the buffer ++ * @buf: the buffer to search ++ * @len: the length of buffer to search ++ * @paglen: the pagelength ++ * @td: search pattern descriptor ++ * ++ * Check for a pattern at the given place. Used to search bad block tables and ++ * good / bad block identifiers. If the SCAN_EMPTY option is set then check, if ++ * all bytes except the pattern area contain 0xff. ++ */ ++static int spinand_check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) ++{ ++ int i, end = 0; ++ uint8_t *p = buf; ++ ++ if (td->options & NAND_BBT_NO_OOB) ++ return spinand_check_pattern_no_oob(buf, td); ++ ++ end = paglen + td->offs; ++ if (td->options & NAND_BBT_SCANEMPTY) ++ { ++ for (i = 0; i < end; i++) ++ { ++ if (p[i] != 0xff) ++ return -1; ++ } ++ } ++ p += end; ++ ++ /* Compare the pattern */ ++ if (memcmp(p, td->pattern, td->len)) ++ return -1; ++ ++ if (td->options & NAND_BBT_SCANEMPTY) ++ { ++ p += td->len; ++ end += td->len; ++ for (i = end; i < len; i++) ++ { ++ if (*p++ != 0xff) ++ return -1; ++ } ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_check_short_pattern - [GENERIC] check if a pattern is in the buffer ++ * @buf: the buffer to search ++ * @td: search pattern descriptor ++ * ++ * Check for a pattern at the given place. Used to search bad block tables and ++ * good / bad block identifiers. Same as check_pattern, but no optional empty ++ * check. ++ */ ++static int spinand_check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td) ++{ ++ int i; ++ uint8_t *p = buf; ++ ++ /* Compare the pattern */ ++ for (i = 0; i < td->len; i++) { ++ if (p[td->offs + i] != td->pattern[i]) ++ return -1; ++ } ++ return 0; ++} ++ ++/** ++ * spinand_add_marker_len - compute the length of the marker in data area ++ * @td: BBT descriptor used for computation ++ * ++ * The length will be 0 if the marker is located in OOB area. ++ */ ++static u32 spinand_add_marker_len(struct nand_bbt_descr *td) ++{ ++ u32 len; ++ ++ if (!(td->options & NAND_BBT_NO_OOB)) ++ return 0; ++ ++ len = td->len; ++ if (td->options & NAND_BBT_VERSION) ++ len++; ++ return len; ++} ++ ++/** ++ * spinand_read_bbt - [GENERIC] Read the bad block table starting from page ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @page: the starting page ++ * @num: the number of bbt descriptors to read ++ * @td: the bbt describtion table ++ * @offs: offset in the memory table ++ * ++ * Read the bad block table starting from page. ++ */ ++static int spinand_read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, ++ struct nand_bbt_descr *td, int offs) ++{ ++ int res, ret = 0, i, j, act = 0; ++ struct spinand_chip *this = mtd->priv; ++ size_t retlen, len, totlen; ++ loff_t from; ++ int bits = td->options & NAND_BBT_NRBITS_MSK; ++ uint8_t msk = (uint8_t)((1 << bits) - 1); ++ u32 marker_len; ++ int reserved_block_code = td->reserved_block_code; ++ ++ totlen = (num * bits) >> 3; ++ marker_len = spinand_add_marker_len(td); ++ from = ((loff_t)page) << this->page_shift; ++ ++#ifdef CONFIG_DEBUG_R ++ ++ pr_info("[%s]: read bbt >>>\n", __FUNCTION__); ++ pr_info("BlockNum %d\n" ++ "totlen %d\n" ++ "marker_len %d\n" ++ "from 0x%llx\n", ++ totlen, ++ marker_len, ++ from); ++ ++#endif ++ ++ ++ while (totlen) ++ { ++ len = min(totlen, (size_t)(1 << this->bbt_erase_shift)); ++ if (marker_len) { ++ /* ++ * In case the BBT marker is not in the OOB area it ++ * will be just in the first page. ++ */ ++ len -= marker_len; ++ from += marker_len; ++ marker_len = 0; ++ } ++ ++ res = mtd_read(mtd, from, len, &retlen, buf); ++ if (res < 0) ++ { ++ if (mtd_is_eccerr(res)) { ++ pr_info("%s: ECC error in BBT at 0x%012llx\n", __FUNCTION__,from & ~mtd->writesize); ++ return res; ++ } else if (mtd_is_bitflip(res)) { ++ pr_info("%s: corrected error in BBT at 0x%012llx\n", __FUNCTION__,from & ~mtd->writesize); ++ ret = res; ++ } else { ++ pr_info("%s: error reading BBT\n",__FUNCTION__); ++ return res; ++ } ++ } ++ ++ /* Analyse data */ ++ for (i = 0; i < len; i++) ++ { ++ uint8_t dat = buf[i]; ++ for (j = 0; j < 8; j += bits, act += 2) ++ { ++ uint8_t tmp = (dat >> j) & msk; ++ if (tmp == msk) ++ continue; ++ if (reserved_block_code && (tmp == reserved_block_code)) ++ { ++ pr_info("%s: reserved block at 0x%012llx\n",__FUNCTION__, ++ (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); ++ this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); ++ mtd->ecc_stats.bbtblocks++; ++ continue; ++ } ++ ++ /* ++ * Leave it for now, if it's matured we can ++ * move this message to pr_debug. ++ */ ++ pr_info("%s: bad block at 0x%012llx\n",__FUNCTION__, ++ (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); ++ ++ /* Factory marked bad or worn out? */ ++ if (tmp == 0) ++ this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); ++ else ++ this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); ++ mtd->ecc_stats.badblocks++; ++ ++ } ++ } ++ ++ totlen -= len; ++ from += len; ++ ++ } ++ ++ return ret; ++ ++} ++ ++/** ++ * spinand_read_abs_bbt - [GENERIC] Read the bad block table starting at a given page ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @td: descriptor for the bad block table ++ * ++ * Read the bad block table for all chips starting at a given page. We assume ++ * that the bbt bits are in consecutive order. ++ */ ++static int spinand_read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int res = 0; ++ ++ res = spinand_read_bbt(mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, td, 0); ++ if (res) ++ return res; ++ ++ return 0; ++} ++ ++/** ++ * spinand_scan_read_raw_data - [GENERIC] Scan read raw data from flash ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @offs: offset in the memory table ++ * @readlen: the length of the data to read ++ * ++ * Scan read raw data from flash, BBT marker is in the first page, no OOB ++ */ ++static int spinand_scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs, ++ struct nand_bbt_descr *td) ++{ ++ size_t retlen; ++ size_t len; ++ ++ len = td->len; ++ if (td->options & NAND_BBT_VERSION) ++ len++; ++ ++ return mtd_read(mtd, offs, len, &retlen, buf); ++} ++ ++/** ++ * spinand_scan_read_raw_oob - [GENERIC] Scan read oob raw data from flash ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @offs: offset in the memory table ++ * @readlen: the length of the data to read ++ * ++ * Scan read oob raw data from flash ++ */ ++static int spinand_scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs, ++ size_t readlen) ++{ ++ struct mtd_oob_ops ops; ++ int res; ++ ++ ops.mode = MTD_OPS_RAW; ++ ops.ooboffs = 0; ++ ops.ooblen = mtd->oobsize; ++ ++ while (readlen > 0) ++ { ++ ops.datbuf = buf; ++ ops.len = min(readlen, (size_t)mtd->writesize); ++ ops.oobbuf = buf + ops.len; ++ ++ res = mtd_read_oob(mtd, offs, &ops); ++ ++ if (res) ++ { ++ return res; ++ } ++ ++ buf += mtd->oobsize + mtd->writesize; ++ readlen -= mtd->writesize; ++ offs += mtd->writesize; ++ } ++ ++ return 0; ++ ++} ++ ++static int spinand_scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs, ++ size_t len, struct nand_bbt_descr *td) ++{ ++ if (td->options & NAND_BBT_NO_OOB) ++ return spinand_scan_read_raw_data(mtd, buf, offs, td); ++ else ++ return spinand_scan_read_raw_oob(mtd, buf, offs, len); ++} ++ ++/** ++ * spinand_scan_write_bbt - [GENERIC] Scan write data with oob to flash ++ * @mtd: MTD device structure ++ * @offs: offset to write ++ * @len: the length of the data to write ++ * @buf: temporary buffer for main data ++ * @oob: temporary buffer for oob data ++ * ++ * Scan write data with oob to flash ++ */ ++static int spinand_scan_write_bbt(struct mtd_info *mtd, loff_t offs, size_t len, ++ uint8_t *buf, uint8_t *oob) ++{ ++ struct mtd_oob_ops ops; ++ ++ ops.mode = MTD_OPS_PLACE_OOB; ++ ops.ooboffs = 0; ++ ops.ooblen = mtd->oobsize; ++ ops.datbuf = buf; ++ ops.oobbuf = oob; ++ ops.len = len; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: scan write bbt >>>\n", __FUNCTION__); ++ pr_info("offs 0x%llx\n" ++ "len 0x%x\n" ++ "oobbuf 0x%x\n", ++ offs, ++ len, oob); ++ ++#endif ++ ++ return mtd_write_oob(mtd, offs, &ops); ++} ++ ++static u32 spinand_bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td) ++{ ++ u32 ver_offs = td->veroffs; ++ ++ if (!(td->options & NAND_BBT_NO_OOB)) ++ ver_offs += mtd->writesize; ++ return ver_offs; ++} ++ ++/** ++ * spinand_read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @td: descriptor for the bad block table ++ * @md: descriptor for the bad block table mirror ++ * ++ * Read the bad block table(s) for all chips starting at a given page. We ++ * assume that the bbt bits are in consecutive order. ++ */ ++static int spinand_read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, ++ struct nand_bbt_descr *td, struct nand_bbt_descr *md) ++{ ++ struct spinand_chip *this = mtd->priv; ++ ++ /* Read the primary version, if available */ ++ if (td->options & NAND_BBT_VERSION) ++ { ++ spinand_scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift, mtd->writesize, td); ++ td->version[0] = buf[spinand_bbt_get_ver_offs(mtd, td)]; ++ pr_info("line%d: TD BBT at page %d, version 0x%02X\n", __LINE__,td->pages[0], td->version[0]); ++ } ++ ++ /* Read the mirror version, if available */ ++ if (md && (md->options & NAND_BBT_VERSION)) ++ { ++ spinand_scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift, mtd->writesize, md); ++ md->version[0] = buf[spinand_bbt_get_ver_offs(mtd, md)]; ++ pr_info("Line%d: MD BBT at page %d, version 0x%02X\n", __LINE__,md->pages[0], md->version[0]); ++ } ++ ++ return 1; ++ ++} ++ ++/** ++ * spinand_scan_block_full - [GENERIC] Scan a given block full ++ * @mtd: MTD device structure ++ * @bd: descriptor for the good/bad block search pattern ++ * @offs: address offset of spi nand(from) ++ * @buf: temporary buffer ++ * @readlen: the length of the data to read ++ * @scanlen: the length of the data to scan ++ * @rpagenum: the number of the pages to read ++ * ++ * Scan the full pages in a given block ++ */ ++static int spinand_scan_block_full( ++ struct mtd_info *mtd, struct nand_bbt_descr *bd, ++ loff_t offs, uint8_t *buf, size_t readlen, ++ int scanlen, int rpagenum) ++{ ++ int ret, j; ++ ++ /* read oob raw */ ++ ret = spinand_scan_read_raw_oob(mtd, buf, offs, readlen); ++ ++ /* Ignore ECC errors when checking for BBM */ ++ if (ret && !mtd_is_bitflip_or_eccerr(ret)) ++ return ret; ++ ++ /* check pattern per page */ ++ for (j = 0; j < rpagenum; j++, buf += scanlen) { ++ if (spinand_check_pattern(buf, scanlen, mtd->writesize, bd)) ++ return 1; ++ } ++ return 0; ++} ++ ++/** ++ * spinand_scan_block_fast - [GENERIC] Scan a given block partially ++ * @mtd: MTD device structure ++ * @bd: descriptor for the good/bad block search pattern ++ * @offs: address offset of spi nand(from) ++ * @buf: temporary buffer ++ * @rpagenum: the number of the pages to read ++ * ++ * Scan the partially pages in a given block ++ */ ++static int spinand_scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd, ++ loff_t offs, uint8_t *buf, int rpagenum) ++{ ++ struct mtd_oob_ops ops; ++ int j, ret; ++ ++ ops.ooblen = mtd->oobsize; ++ ops.oobbuf = buf; ++ ops.ooboffs = 0; ++ ops.datbuf = NULL; ++ ops.mode = MTD_OPS_RAW; ++ ops.len = 0; ++ ++ for (j = 0; j < rpagenum; j++) ++ { ++ /* ++ * Read the full oob until read_oob is fixed to handle single ++ * byte reads for 16 bit buswidth. ++ */ ++ ret = mtd_read_oob(mtd, offs, &ops); ++// printk("read oob return val is 0x%x\n", ret); ++ /* Ignore ECC errors when checking for BBM */ ++ if (ret && !mtd_is_bitflip_or_eccerr(ret)) ++ return ret; ++ ++ if (spinand_check_short_pattern(buf, bd)) ++ return 1; ++ ++ offs += mtd->writesize; ++ } ++ return 0; ++} ++ ++/** ++ * spinand_create_bbt - [GENERIC] Create a bad block table by scanning the device ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @bd: descriptor for the good/bad block search pattern ++ * @chip: create the table for a specific chip, -1 read all chips; applies only ++ * if NAND_BBT_PERCHIP option is set ++ * ++ * Create a bad block table by scanning the device for the given good/bad block ++ * identify pattern. ++ */ ++static int spinand_create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int i, numblocks, rpagenum, scanlen; ++ int startblock; ++ loff_t from; ++ size_t readlen; ++ ++ pr_info("%s: Scanning device for bad blocks\n", __FUNCTION__); ++ ++ /* get the page numbers what we want to scan */ ++ if (bd->options & NAND_BBT_SCANALLPAGES) ++ rpagenum = 1 << (this->bbt_erase_shift - this->page_shift); ++ else if (bd->options & NAND_BBT_SCAN2NDPAGE) ++ rpagenum = 2; ++ else ++ rpagenum = 1; ++ ++ if (!(bd->options & NAND_BBT_SCANEMPTY)) { ++ /* We need only read few bytes from the OOB area */ ++ scanlen = 0; ++ readlen = bd->len; ++ } else { ++ /* Full page content should be read */ ++ scanlen = mtd->writesize + mtd->oobsize; ++ readlen = rpagenum * mtd->writesize; ++ } ++ ++ /* ++ * Note that numblocks is 2 * (real numblocks) here, see i+=2 ++ * below as it makes shifting and masking less painful ++ */ ++ numblocks = mtd->size >> (this->bbt_erase_shift - 1); ++ startblock = 0; ++ from = 0; ++ ++ /* only scan the last page */ ++ if (this->bbt_options & NAND_BBT_SCANLASTPAGE) ++ from += mtd->erasesize - (mtd->writesize * rpagenum); ++ ++ for (i = startblock; i < numblocks;) ++ { ++ int ret; ++ ++ BUG_ON(bd->options & NAND_BBT_NO_OOB); ++ ++ if (bd->options & NAND_BBT_SCANALLPAGES) ++ ret = spinand_scan_block_full(mtd, bd, from, buf, readlen, scanlen, rpagenum); ++ else ++ ret = spinand_scan_block_fast(mtd, bd, from, buf, rpagenum); ++ ++ if (ret < 0) ++ { ++ pr_err("[%s]Never go here!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ if (ret) { ++ this->bbt[i >> 3] |= 0x03 << (i & 0x6); ++ pr_info("Bad eraseblock %d at 0x%012llx\n", ++ i >> 1, (unsigned long long)from); ++ mtd->ecc_stats.badblocks++; ++ } ++ ++ i += 2; ++ from += (1 << this->bbt_erase_shift); ++ ++ } ++ ++#ifdef CONFIG_DEBUG_R ++{ ++ pr_info("%s: BBT content:\n", __FUNCTION__); ++ ++ int i = 0, j = 0; ++ ++ for(i = 0,j = 0; i < 512; i++,j++) ++ { ++ if(j % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", this->bbt[i]); ++ } ++ ++ printk("\n"); ++} ++#endif ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_search_bbt - [GENERIC] scan the device for a specific bad block table ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @td: descriptor for the bad block table ++ * ++ * Read the bad block table by searching for a given ident pattern. Search is ++ * preformed either from the beginning up or from the end of the device ++ * downwards. The search starts always at the start of a block. If the option ++ * NAND_BBT_PERCHIP is given, each chip is searched for a bbt, which contains ++ * the bad block information of this chip. This is necessary to provide support ++ * for certain DOC devices. ++ * ++ * The bbt ident pattern resides in the oob area of the first page in a block. ++ */ ++static int spinand_search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) ++{ ++ struct spinand_chip *this = mtd->priv; ++ ++ int startblock, block, dir; ++ int scanlen = mtd->writesize + mtd->oobsize; ++ int bbtblocks; ++ int blocktopage = this->bbt_erase_shift - this->page_shift; ++ ++#ifdef CONFIG_DEBUG_R ++ ++ pr_info("[%s]: search bbt >>>\n", __FUNCTION__); ++ ++#endif ++ ++ ++ /* Search direction top -> down? */ ++ if (td->options & NAND_BBT_LASTBLOCK) ++ { ++ startblock = (mtd->size >> this->bbt_erase_shift) - 1; ++ dir = -1; ++ } ++ else ++ { ++ startblock = START_BLOCK; ++ dir = 1; ++ } ++ ++ /* calc block number on device */ ++ bbtblocks = mtd->size >> this->bbt_erase_shift; ++ ++ /* Reset version information */ ++ td->version[0] = 0; ++ td->pages[0] = -1; ++ ++ /* Scan the maximum number of blocks */ ++ for (block = 0; block < td->maxblocks; block++) ++ { ++ int actblock = startblock + dir * block; ++ loff_t offs = (loff_t)actblock << this->bbt_erase_shift; ++ ++#ifdef CONFIG_DEBUG_R ++ ++ pr_info("actblock 0x%08x\n" ++ "offs 0x%llx\n", ++ actblock, ++ offs); ++ ++#endif ++ ++ /* Read first page */ ++ spinand_scan_read_raw(mtd, buf, offs, mtd->writesize, td); ++ ++#ifdef CONFIG_DEBUG_R ++ printk("Pattern: %c,%c,%c,%c\n",td->pattern[0],td->pattern[1],td->pattern[2],td->pattern[3]); ++ printk("Pattern: %x,%x,%x,%x",td->pattern[0],td->pattern[1],td->pattern[2],td->pattern[3]); ++ ++ { ++ int i = 0, j = 0; ++ ++ for(i = 0,j = 0; i < 128; i++,j++) ++ { ++ if(j % 16 == 0) ++ { ++ printk("\n"); ++ } ++ printk("%02x ", buf[i]); ++ } ++ ++ printk("\n"); ++ } ++#endif ++ ++ if (!spinand_check_pattern(buf, scanlen, mtd->writesize, td)) ++ { ++ td->pages[0] = actblock << blocktopage; ++ if (td->options & NAND_BBT_VERSION) ++ { ++ offs = spinand_bbt_get_ver_offs(mtd, td); ++ td->version[0] = buf[offs]; ++ } ++ break; ++ } ++ } ++ ++ /* Check, if we found a bbt */ ++ if (td->pages[0] == -1) ++ pr_warn("Bad block table not found\n"); ++ else ++ pr_info("Bad block table found at page %d, version 0x%02X\n", td->pages[0], td->version[0]); ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_search_read_bbts - [GENERIC] scan the device for bad block table(s) ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @td: descriptor for the bad block table ++ * @md: descriptor for the bad block table mirror ++ * ++ * Search and read the bad block table(s). ++ */ ++static int spinand_search_read_bbts( ++ struct mtd_info *mtd, uint8_t * buf, ++ struct nand_bbt_descr *td, struct nand_bbt_descr *md) ++{ ++ /* Search the primary table */ ++ spinand_search_bbt(mtd, buf, td); ++ ++ /* Search the mirror table */ ++ if (md) ++ spinand_search_bbt(mtd, buf, md); ++ ++ /* Force result check */ ++ return 1; ++} ++ ++/** ++ * spinand_write_bbt - [GENERIC] (Re)write the bad block table ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @td: descriptor for the bad block table ++ * @md: descriptor for the bad block table mirror ++ * ++ * (Re)write the bad block table. ++ */ ++static int spinand_write_bbt(struct mtd_info *mtd, uint8_t *buf, ++ struct nand_bbt_descr *td, struct nand_bbt_descr *md) ++{ ++ struct spinand_chip *this = mtd->priv; ++ struct erase_info einfo; ++ int i, j, res; ++ int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; ++ int bbtoffs, pageoffs, ooboffs; ++ uint8_t msk[4]; ++ uint8_t rcode = td->reserved_block_code; ++ size_t retlen, len = 0; ++ loff_t to; ++ struct mtd_oob_ops ops; ++ ++ ops.ooblen = mtd->oobsize; ++ ops.ooboffs = 0; ++ ops.datbuf = NULL; ++ ops.mode = MTD_OPS_PLACE_OOB; ++ ops.len = 0; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: write bbt start >>>\n", __FUNCTION__); ++#endif ++ ++ if (!rcode) ++ rcode = 0xff; ++ ++ /* Write bad block table per chip rather than per device? */ ++ numblocks = (int)(mtd->size >> this->bbt_erase_shift); ++ ++ /* ++ * There was already a version of the table, reuse the page ++ * This applies for absolute placement too, as we have the ++ * page nr. in td->pages. ++ */ ++ if (td->pages[0] != -1) { ++ page = td->pages[0]; ++ goto write; ++ } ++ ++ /* ++ * Automatic placement of the bad block table. Search direction ++ * top -> down? ++ */ ++ if (td->options & NAND_BBT_LASTBLOCK) { ++ startblock = numblocks - 1; ++ dir = -1; ++ } else { ++ startblock = START_BLOCK; ++ dir = 1; ++ } ++ ++ for (i = 0; i < td->maxblocks; i++) ++ { ++ int block = startblock + dir * i; ++ ++ /* Check, if the block is bad */ ++ switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) ++ { ++ case 0x01: ++ case 0x03: ++ continue; ++ } ++ page = block << (this->bbt_erase_shift - this->page_shift); ++ ++ /* Check, if the block is used by the mirror table */ ++ if (!md || md->pages[0] != page) ++ goto write; ++ } ++ ++ pr_err("No space left to write bad block table\n"); ++ return -ENOSPC; ++ ++write: ++ ++ /* Set up shift count and masks for the flash table */ ++ bits = td->options & NAND_BBT_NRBITS_MSK; ++ msk[2] = ~rcode; ++ switch (bits) { ++ case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; ++ msk[3] = 0x01; ++ break; ++ case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; ++ msk[3] = 0x03; ++ break; ++ case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; ++ msk[3] = 0x0f; ++ break; ++ case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; ++ msk[3] = 0xff; ++ break; ++ default: return -EINVAL; ++ } ++ ++ bbtoffs = 0; ++ ++ to = ((loff_t)page) << this->page_shift; ++ ++ /* Must we save the block contents? */ ++ if (td->options & NAND_BBT_SAVECONTENT) ++ { ++ /* Make it block aligned */ ++ to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1)); ++ len = 1 << this->bbt_erase_shift; ++ res = mtd_read(mtd, to, len, &retlen, buf); ++ if (res < 0) ++ { ++ if (retlen != len) { ++ pr_info("nand_bbt: error reading block for writing the bad block table\n"); ++ return res; ++ } ++ pr_warn("nand_bbt: ECC error while reading block for writing bad block table\n"); ++ } ++ ++ /* Read oob data */ ++ ops.ooblen = (len >> this->page_shift) * mtd->oobsize; ++ ops.oobbuf = &buf[len]; ++ res = mtd_read_oob(mtd, to + mtd->writesize, &ops); ++ if (res < 0 || ops.oobretlen != ops.ooblen) ++ goto outerr; ++ ++ /* Calc the byte offset in the buffer */ ++ pageoffs = page - (int)(to >> this->page_shift); ++ offs = pageoffs << this->page_shift; ++ /* Preset the bbt area with 0xff */ ++ memset(&buf[offs], 0xff, (size_t)(numblocks >> sft)); ++ ooboffs = len + (pageoffs * mtd->oobsize); ++ ++ } ++ else if (td->options & NAND_BBT_NO_OOB) ++ { ++ ooboffs = 0; ++ offs = td->len; ++ ++ /* The version byte */ ++ if (td->options & NAND_BBT_VERSION) ++ offs++; ++ /* Calc length */ ++ len = (size_t)(numblocks >> sft); ++ len += offs; ++ /* Make it page aligned! */ ++ len = ALIGN(len, mtd->writesize); ++ ++#ifdef CONFIG_DEBUG_W ++ ++ pr_info("[%s]: must go here >>>\n", __FUNCTION__); ++ pr_info(" len = %d\n", len); ++ ++#endif ++ ++ ++ /* Preset the buffer with 0xff */ ++ memset(buf, 0xff, len); ++ /* Pattern is located at the begin of first page */ ++ memcpy(buf, td->pattern, td->len); ++ } ++ else ++ { ++ /* Calc length */ ++ len = (size_t)(numblocks >> sft); ++ /* Make it page aligned! */ ++ len = ALIGN(len, mtd->writesize); ++ /* Preset the buffer with 0xff */ ++ memset(buf, 0xff, len + ++ (len >> this->page_shift)* mtd->oobsize); ++ offs = 0; ++ ooboffs = len; ++ /* Pattern is located in oob area of first page */ ++ memcpy(&buf[ooboffs + td->offs], td->pattern, td->len); ++ } ++ ++ if (td->options & NAND_BBT_VERSION) ++ buf[ooboffs + td->veroffs] = td->version[0]; ++ ++ /* Walk through the memory table */ ++ for (i = 0; i < numblocks;) ++ { ++ uint8_t dat; ++ dat = this->bbt[bbtoffs + (i >> 2)]; ++ for (j = 0; j < 4; j++, i++) ++ { ++ int sftcnt = (i << (3 - sft)) & sftmsk; ++ /* Do not store the reserved bbt blocks! */ ++ buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt); ++ dat >>= 2; ++ } ++ } ++ ++ memset(&einfo, 0, sizeof(einfo)); ++ einfo.mtd = mtd; ++ einfo.addr = to; ++ einfo.len = 1 << this->bbt_erase_shift; ++ res = spinand_erase_nand(mtd, &einfo, 1); ++ if (res < 0) ++ goto outerr; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: erase OK! len = %d >>>\n", __FUNCTION__, len); ++#endif ++ ++ ++ res = spinand_scan_write_bbt(mtd, to, len, buf, ++ td->options & NAND_BBT_NO_OOB ? NULL : &buf[len]); ++ if (res < 0) ++ goto outerr; ++ ++ pr_info("Bad block table written to 0x%012llx, version 0x%02X\n", ++ (unsigned long long)to, td->version[0]); ++ ++ /* Mark it as used */ ++ td->pages[0] = page; ++ ++ return 0; ++ ++ outerr: ++ pr_warn("write_bbt: error while writing bbt block = 0x%llx, %d\n",to,res); ++ return res; ++ ++} ++ ++/** ++ * spinand_memory_bbt - [GENERIC] create a memory based bad block table ++ * @mtd: MTD device structure ++ * @bd: descriptor for the good/bad block search pattern ++ * ++ * The function creates a memory based bbt by scanning the device for ++ * manufacturer / software marked good / bad blocks. ++ */ ++static inline int spinand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) ++{ ++ struct spinand_chip *chip = mtd->priv; ++ ++ bd->options &= ~NAND_BBT_SCANEMPTY; ++ return spinand_create_bbt(mtd, chip->buffers->databuf, bd); ++} ++ ++/** ++ * spinand_check_create - [GENERIC] create and write bbt(s) if necessary ++ * @mtd: MTD device structure ++ * @buf: temporary buffer ++ * @bd: descriptor for the good/bad block search pattern ++ * ++ * The function checks the results of the previous call to read_bbt and creates ++ * / updates the bbt(s) if necessary. Creation is necessary if no bbt was found ++ * for the chip/device. Update is necessary if one of the tables is missing or ++ * the version nr. of one table is less than the other. ++ */ ++static int spinand_check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) ++{ ++ int writeops, create, res, res2, tpageno, mpageno; ++ struct spinand_chip *this = mtd->priv; ++ struct nand_bbt_descr *td = this->bbt_td; ++ struct nand_bbt_descr *md = this->bbt_md; ++ struct nand_bbt_descr *rd, *rd2; ++ uint8_t tversion, mversion; ++ ++ writeops = 0; ++ create = 0; ++ rd = NULL; ++ rd2 = NULL; ++ res = res2 = 0; ++ tpageno = td->pages[0]; ++ mpageno = md->pages[0]; ++ tversion = td->version[0]; ++ mversion = md->version[0]; ++ ++#ifdef CONFIG_DEBUG_R ++ ++ pr_info("[%s]: check & create >>>\n", __FUNCTION__); ++ pr_info("tpageno 0x%08x\n" ++ "mpageno 0x%08x\n" ++ "tversion 0x%08x\n" ++ "mversion 0x%08x\n", ++ tpageno, ++ mpageno, ++ tversion, ++ mversion); ++ ++#endif ++ ++ ++ /* Mirrored table available? */ ++ if (md) ++ { ++ if (tpageno == -1 && mpageno == -1) { ++ create = 1; ++ writeops = 0x03; ++ } else if (tpageno == -1) { ++ rd = md; ++ writeops = 0x01; ++ } else if (mpageno == -1) { ++ rd = td; ++ writeops = 0x02; ++ } else if (tversion == mversion) { ++ rd = td; ++ if (!(td->options & NAND_BBT_VERSION)) ++ rd2 = md; ++ } else if (((int8_t)(tversion - mversion)) > 0) { ++ rd = td; ++ writeops = 0x02; ++ } else { ++ rd = md; ++ writeops = 0x01; ++ } ++ } ++ else { ++ if (tpageno == -1) { ++ create = 1; ++ writeops = 0x01; ++ } else { ++ rd = td; ++ } ++ } ++ ++ if (create) ++ { ++ /* Create the bad block table by scanning the device? */ ++ if (!(td->options & NAND_BBT_CREATE)) ++ goto out; ++ ++ /* Create the table in memory by scanning the chip(s) */ ++ if (!(this->bbt_options & NAND_BBT_CREATE_EMPTY)) ++ spinand_create_bbt(mtd, buf, bd); ++ ++ td->version[0] = 1; ++ if (md) ++ md->version[0] = 1; ++ } ++ ++ /* Read back first? */ ++ if (rd) ++ { ++ res = spinand_read_abs_bbt(mtd, buf, rd); ++ if (mtd_is_eccerr(res)) { ++ /* Mark table as invalid */ ++ rd->pages[0] = -1; ++ rd->version[0] = 0; ++ goto out;; ++ } ++ } ++ ++ /* If they weren't versioned, read both */ ++ if (rd2) ++ { ++ res2 = spinand_read_abs_bbt(mtd, buf, rd2); ++ if (mtd_is_eccerr(res2)) { ++ /* Mark table as invalid */ ++ rd2->pages[0] = -1; ++ rd2->version[0] = 0; ++ goto out;; ++ } ++ } ++ ++ /* Scrub the flash table(s)? */ ++ if (mtd_is_bitflip(res) || mtd_is_bitflip(res2)) ++ writeops = 0x03; ++ ++ /* Update version numbers before writing */ ++ if (md) { ++ td->version[0] = max(td->version[0], md->version[0]); ++ md->version[0] = td->version[0]; ++ } ++ ++ /* Write the bad block table to the device? */ ++ if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { ++ res = spinand_write_bbt(mtd, buf, td, md); ++ if (res < 0) ++ return res; ++ } ++ ++ /* Write the mirror bad block table to the device? */ ++ if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { ++ res = spinand_write_bbt(mtd, buf, md, td); ++ if (res < 0) ++ return res; ++ } ++ ++out: ++ ++ return 0; ++ ++} ++ ++/** ++ * spinand_update_bbt - [NAND Interface] update bad block table(s) ++ * @mtd: MTD device structure ++ * @offs: the offset of the newly marked block ++ * ++ * The function updates the bad block table(s). ++ */ ++int spinand_update_bbt(struct mtd_info *mtd, loff_t offs) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int len, res = 0; ++ uint8_t *buf; ++ struct nand_bbt_descr *td = this->bbt_td; ++ struct nand_bbt_descr *md = this->bbt_md; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: update bbt >>>\n", __FUNCTION__); ++#endif ++ ++ if (!this->bbt || !td) ++ return -EINVAL; ++ ++ /* Allocate a temporary buffer for one eraseblock incl. oob */ ++ len = (1 << this->bbt_erase_shift); ++ len += (len >> this->page_shift) * mtd->oobsize; ++ buf = kmalloc(len, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ td->version[0]++; ++ if (md) ++ md->version[0]++; ++ ++ /* Write the bad block table to the device? */ ++ if (td->options & NAND_BBT_WRITE) ++ { ++ res = spinand_write_bbt(mtd, buf, td, md); ++ if (res < 0) ++ goto out; ++ } ++ ++ /* Write the mirror bad block table to the device? */ ++ if (md && (md->options & NAND_BBT_WRITE)) ++ { ++ res = spinand_write_bbt(mtd, buf, md, td); ++ } ++ ++ out: ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: update bbt ret = %d <<<\n", __FUNCTION__, res); ++#endif ++ ++ kfree(buf); ++ return res; ++ ++} ++ ++/** ++ * spinand_mark_bbt_regions - [GENERIC] mark the bad block table regions ++ * @mtd: MTD device structure ++ * @td: bad block table descriptor ++ * ++ * The bad block table regions are marked as "bad" to prevent accidental ++ * erasures / writes. The regions are identified by the mark 0x02. ++ */ ++static void spinand_mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int j, block, nrblocks, update; ++ uint8_t oldval, newval; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: mark start >>>\n", __FUNCTION__); ++#endif ++ ++ ++ /* calc the block number */ ++ nrblocks = (int)(mtd->size >> this->bbt_erase_shift); ++ ++ if ((td->options & NAND_BBT_ABSPAGE) || !(td->options & NAND_BBT_WRITE)) ++ { ++ if (td->pages[0] == -1) ++ return; ++ block = td->pages[0] >> (this->bbt_erase_shift - this->page_shift); ++ block <<= 1; ++ oldval = this->bbt[(block >> 3)]; ++ newval = oldval | (0x2 << (block & 0x06)); ++ this->bbt[(block >> 3)] = newval; ++ if ((oldval != newval) && td->reserved_block_code) ++ spinand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1)); ++ return; ++ } ++ ++ update = 0; ++ /* get the first block */ ++ if (td->options & NAND_BBT_LASTBLOCK) ++ block = nrblocks - td->maxblocks; ++ else ++ block = START_BLOCK; ++ ++ block <<= 1; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info(" block : %d\n" ++ " maxblock : %d\n", block, td->maxblocks); ++#endif ++ ++ for (j = 0; j < td->maxblocks; j++) ++ { ++ oldval = this->bbt[(block >> 3)]; ++ newval = oldval | (0x2 << (block & 0x06)); ++ this->bbt[(block >> 3)] = newval; ++ if (oldval != newval) ++ update = 1; ++ block += 2; ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("Reserve block:\n"); ++ pr_info(" oldval : %d\n" ++ " newval : %d\n" ++ " block : %d\n", oldval, newval, (block - 2)); ++#endif ++ } ++ ++ /* ++ * If we want reserved blocks to be recorded to flash, and some ++ * new ones have been marked, then we need to update the stored ++ * bbts. This should only happen once. ++ */ ++ if (update && td->reserved_block_code) ++ spinand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1)); ++ ++#ifdef CONFIG_DEBUG_W ++ pr_info("[%s]: mark end <<<\n", __FUNCTION__); ++#endif ++ ++} ++ ++/** ++ * spinand_verify_bbt_descr - verify the bad block description ++ * @mtd: MTD device structure ++ * @bd: the table to verify ++ * ++ * This functions performs a few sanity checks on the bad block description ++ * table. ++ */ ++static void spinand_verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) ++{ ++ struct spinand_chip *this = mtd->priv; ++ u32 pattern_len; ++ u32 bits; ++ u32 table_size; ++ ++ if (!bd) ++ { ++ return; ++ } ++ ++ pattern_len = bd->len; ++ bits = bd->options & NAND_BBT_NRBITS_MSK; ++ ++ BUG_ON((this->bbt_options & NAND_BBT_NO_OOB) && ++ !(this->bbt_options & NAND_BBT_USE_FLASH)); ++ BUG_ON(!bits); ++ ++ if (bd->options & NAND_BBT_VERSION) ++ { ++ pattern_len++; ++ } ++ ++ if (bd->options & NAND_BBT_NO_OOB) ++ { ++ BUG_ON(!(this->bbt_options & NAND_BBT_USE_FLASH)); ++ BUG_ON(!(this->bbt_options & NAND_BBT_NO_OOB)); ++ BUG_ON(bd->offs); ++ if (bd->options & NAND_BBT_VERSION) ++ { ++ BUG_ON(bd->veroffs != bd->len); ++ } ++ BUG_ON(bd->options & NAND_BBT_SAVECONTENT); ++ } ++ ++ table_size = mtd->size >> this->bbt_erase_shift; ++ ++ table_size >>= 3; ++ table_size *= bits; ++ if (bd->options & NAND_BBT_NO_OOB) ++ { ++ table_size += pattern_len; ++ } ++ ++ BUG_ON(table_size > (1 << this->bbt_erase_shift)); ++ ++} ++ ++/** ++ * spinand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s) ++ * @mtd: MTD device structure ++ * @bd: descriptor for the good/bad block search pattern ++ * ++ * The function checks, if a bad block table(s) is/are already available. If ++ * not it scans the device for manufacturer marked good / bad blocks and writes ++ * the bad block table(s) to the selected place. ++ * ++ * The bad block table memory is allocated here. It must be freed by calling ++ * the nand_free_bbt function. ++ */ ++int spinand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int len, res = 0; ++ uint8_t *buf; ++ struct nand_bbt_descr *td = this->bbt_td; ++ struct nand_bbt_descr *md = this->bbt_md; ++ ++ len = mtd->size >> (this->bbt_erase_shift + 2); ++ /* ++ * Allocate memory (2bit per block) and clear the memory bad block ++ * table. ++ */ ++ this->bbt = kzalloc(len, GFP_KERNEL); ++ if (!this->bbt) ++ { ++ pr_err("scan_bbt: no memory for bad block\n"); ++ return -ENOMEM; ++ } ++ ++ /* ++ * If no primary table decriptor is given, scan the device to build a ++ * memory based bad block table. ++ */ ++ if (!td) { ++ if ((res = spinand_memory_bbt(mtd, bd))) { ++ pr_err("scan_bbt: can't scan flash and build the RAM-based BBT\n"); ++ kfree(this->bbt); ++ this->bbt = NULL; ++ } ++ return res; ++ } ++ spinand_verify_bbt_descr(mtd, td); ++ spinand_verify_bbt_descr(mtd, md); ++ ++ /* Allocate a temporary buffer for one eraseblock incl. oob */ ++ len = (1 << this->bbt_erase_shift); ++ len += (len >> this->page_shift) * mtd->oobsize; ++ buf = vmalloc(len); ++ if (!buf) { ++ kfree(this->bbt); ++ this->bbt = NULL; ++ return -ENOMEM; ++ } ++ ++ /* Is the bbt at a given page? */ ++ if (td->options & NAND_BBT_ABSPAGE) { ++ res = spinand_read_abs_bbts(mtd, buf, td, md); ++ } else { ++ /* Search the bad block table using a pattern in oob */ ++ res = spinand_search_read_bbts(mtd, buf, td, md); ++ } ++ ++ /* create a new BBT */ ++ if (res) ++ { ++ res = spinand_check_create(mtd, buf, bd); ++ } ++ ++ /* Prevent the bbt regions from erasing / writing */ ++ spinand_mark_bbt_region(mtd, td); ++ if (md) ++ { ++ spinand_mark_bbt_region(mtd, md); ++ } ++ ++ /* free the above temporary buffer */ ++ vfree(buf); ++ return res; ++ ++} ++ ++/* ++ * Define some generic bad / good block scan pattern which are used ++ * while scanning a device for factory marked good / bad blocks. ++ */ ++static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; ++ ++/* Generic flash bbt descriptors */ ++static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; ++static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; ++ ++static struct nand_bbt_descr spinand_bbt_main = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE ++ | NAND_BBT_2BIT | NAND_BBT_VERSION , ++ .offs = 8, ++ .len = 4, ++ .veroffs = 12, ++ .maxblocks = 4, ++ .pattern = bbt_pattern ++}; ++ ++static struct nand_bbt_descr spinand_bbt_mirror = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE ++ | NAND_BBT_2BIT | NAND_BBT_VERSION , ++ .offs = 8, ++ .len = 4, ++ .veroffs = 12, ++ .maxblocks = 4, ++ .pattern = mirror_pattern ++}; ++ ++static struct nand_bbt_descr spinand_bbt_main_no_bbt = { ++ .options = NAND_BBT_CREATE | NAND_BBT_WRITE ++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_NO_OOB, ++ .len = 4, ++ .veroffs = 4, ++ .maxblocks = 4, ++ //.reserved_block_code = 2, ++ .pattern = bbt_pattern ++}; ++ ++static struct nand_bbt_descr spinand_bbt_mirror_no_bbt = { ++ .options = NAND_BBT_CREATE | NAND_BBT_WRITE ++ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_NO_OOB, ++ .len = 4, ++ .veroffs = 4, ++ .maxblocks = 4, ++ //.reserved_block_code = 2, ++ .pattern = mirror_pattern ++}; ++ ++#define BADBLOCK_SCAN_MASK (~NAND_BBT_NO_OOB) ++/** ++ * spinand_create_badblock_pattern - [INTERN] Creates a BBT descriptor structure ++ * @this: NAND chip to create descriptor for ++ * ++ * This function allocates and initializes a nand_bbt_descr for BBM detection ++ * based on the properties of @this. The new descriptor is stored in ++ * this->badblock_pattern. Thus, this->badblock_pattern should be NULL when ++ * passed to this function. ++ */ ++static int spinand_create_badblock_pattern(struct spinand_chip *this) ++{ ++ struct nand_bbt_descr *bd; ++ if (this->badblock_pattern) { ++ pr_warn("Bad block pattern already allocated; not replacing\n"); ++ return -EINVAL; ++ } ++ bd = kzalloc(sizeof(*bd), GFP_KERNEL); ++ if (!bd) ++ return -ENOMEM; ++ bd->options = this->bbt_options & BADBLOCK_SCAN_MASK; ++ bd->offs = this->badblockpos; ++ bd->len = (this->options & NAND_BUSWIDTH_16) ? 2 : 1; ++ bd->pattern = scan_ff_pattern; ++ bd->options |= NAND_BBT_DYNAMICSTRUCT; ++ this->badblock_pattern = bd; ++ return 0; ++} ++ ++/** ++ * spinand_default_bbt - [NAND Interface] Select a default bad block table for the device ++ * @mtd: MTD device structure ++ * ++ * This function selects the default bad block table support for the device and ++ * calls the nand_scan_bbt function. ++ */ ++int spinand_default_bbt(struct mtd_info *mtd) ++{ ++ struct spinand_chip *this = mtd->priv; ++ ++ ++ /* Is a flash based bad block table requested? */ ++ if (this->bbt_options & NAND_BBT_USE_FLASH) { ++ /* Use the default pattern descriptors */ ++ if (!this->bbt_td) { ++ if (this->bbt_options & NAND_BBT_NO_OOB) { ++ this->bbt_td = &spinand_bbt_main_no_bbt; ++ this->bbt_md = &spinand_bbt_mirror_no_bbt; ++ } else { ++ this->bbt_td = &spinand_bbt_main; ++ this->bbt_md = &spinand_bbt_mirror; ++ } ++ } ++ } else { ++ this->bbt_td = NULL; ++ this->bbt_md = NULL; ++ } ++ ++ if (!this->badblock_pattern) ++ spinand_create_badblock_pattern(this); ++ ++ return spinand_scan_bbt(mtd, this->badblock_pattern); ++ ++} ++ ++/** ++ * spinand_isbad_bbt - [NAND Interface] Check if a block is bad ++ * @mtd: MTD device structure ++ * @offs: offset in the device ++ * @allowbbt: allow access to bad block table region ++ */ ++int spinand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) ++{ ++ struct spinand_chip *this = mtd->priv; ++ int block; ++ uint8_t res; ++ ++ /* Get block number * 2 */ ++ block = (int)(offs >> (this->bbt_erase_shift - 1)); ++ res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; ++ ++ pr_debug("spinand_isbad_bbt(): bbt info for offs 0x%08x: " ++ "(block %d) 0x%02x\n",(unsigned int)offs, block >> 1, res); ++ ++ switch ((int)res) { ++ case 0x00: ++ return 0; ++ case 0x01: ++ return 1; ++ case 0x02: ++ return allowbbt ? 0 : 1; ++ } ++ return 1; ++ ++} ++ ++EXPORT_SYMBOL(spinand_isbad_bbt); ++EXPORT_SYMBOL(spinand_scan_bbt); ++EXPORT_SYMBOL(spinand_default_bbt); ++ +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index c63a64cb..c45318b0 100644 +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -33,6 +33,7 @@ source "drivers/net/ethernet/chelsio/Kconfig" + source "drivers/net/ethernet/cirrus/Kconfig" + source "drivers/net/ethernet/cisco/Kconfig" + source "drivers/net/ethernet/davicom/Kconfig" ++source "drivers/net/ethernet/goke/Kconfig" + + config DNET + tristate "Dave ethernet support (DNET)" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index 9676a510..7b90703a 100644 +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -2,6 +2,7 @@ + # Makefile for the Linux network Ethernet device drivers. + # + ++obj-$(CONFIG_GK_ETH) += goke/ + obj-$(CONFIG_NET_VENDOR_3COM) += 3com/ + obj-$(CONFIG_NET_VENDOR_8390) += 8390/ + obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/ +diff --git a/drivers/net/ethernet/goke/Kconfig b/drivers/net/ethernet/goke/Kconfig +new file mode 100644 +index 00000000..7a02ba0c +--- /dev/null ++++ b/drivers/net/ethernet/goke/Kconfig +@@ -0,0 +1,14 @@ ++# ++# Acorn Network device configuration ++# These are for Acorn's Expansion card network interfaces ++# ++ ++config ETH_GOKE ++ tristate "Goke 10/100/1000 GMAC Ethernet support" ++ depends on GK_ETH ++ select CRC32 ++ select PHYLIB ++ select MII ++ help ++ This driver supports Goke 10/100/1000 GMAC Ethernet. ++ +diff --git a/drivers/net/ethernet/goke/Makefile b/drivers/net/ethernet/goke/Makefile +new file mode 100644 +index 00000000..17758d82 +--- /dev/null ++++ b/drivers/net/ethernet/goke/Makefile +@@ -0,0 +1,9 @@ ++# File: drivers/net/arm/Makefile ++# ++# Makefile for the ARM network device drivers ++# ++ ++ifdef CONFIG_ETH_GOKE ++obj-$(CONFIG_GK_ETH_EMAC_V1_00) += gk_eth_v1_00.o ++obj-$(CONFIG_GK_ETH_EMAC_V1_01) += gk_eth_v1_01.o ++endif +diff --git a/drivers/net/ethernet/goke/gk_eth_v1_00.c b/drivers/net/ethernet/goke/gk_eth_v1_00.c +new file mode 100644 +index 00000000..cc05fc6f +--- /dev/null ++++ b/drivers/net/ethernet/goke/gk_eth_v1_00.c +@@ -0,0 +1,2478 @@ ++/* ++ * drivers/net/arm/gk_eth.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* ==========================================================================*/ ++#define GKETH_PACKET_MAXFRAME (1536) ++#define GKETH_RX_COPYBREAK (1518) ++#define GKETH_RX_RNG_MIN (8) ++#define GKETH_TX_RNG_MIN (4) ++ ++#define GKETH_RXDMA_STATUS (ETH_DMA_STATUS_OVF | ETH_DMA_STATUS_RI | \ ++ ETH_DMA_STATUS_RU | ETH_DMA_STATUS_RPS | \ ++ ETH_DMA_STATUS_RWT) ++#define GKETH_RXDMA_INTEN (ETH_DMA_INTEN_OVE | ETH_DMA_INTEN_RIE | \ ++ ETH_DMA_INTEN_RUE | ETH_DMA_INTEN_RSE | \ ++ ETH_DMA_INTEN_RWE) ++#define GKETH_TXDMA_STATUS (ETH_DMA_STATUS_TI | ETH_DMA_STATUS_TPS | \ ++ ETH_DMA_STATUS_TU | ETH_DMA_STATUS_TJT | \ ++ ETH_DMA_STATUS_UNF) ++#define GKETH_TXDMA_INTEN (ETH_DMA_INTEN_TIE | ETH_DMA_INTEN_TSE | \ ++ ETH_DMA_INTEN_TUE | ETH_DMA_INTEN_TJE | \ ++ ETH_DMA_INTEN_UNE) ++#define GKETH_DMA_INTEN (ETH_DMA_INTEN_NIE | ETH_DMA_INTEN_AIE | \ ++ ETH_DMA_INTEN_FBE | GKETH_RXDMA_INTEN | \ ++ GKETH_TXDMA_INTEN) ++ ++#define GKETH_TDES0_ATOMIC_CHECK ++#undef GKETH_TDES0_ATOMIC_CHECK_ALL ++#define GKETH_RDES0_ATOMIC_CHECK ++#undef GKETH_RDES0_ATOMIC_CHECK_ALL ++ ++/* ==========================================================================*/ ++struct GKETH_desc { ++ u32 status; ++ u32 length; ++ u32 buffer1; ++ u32 buffer2; ++} __attribute((packed)); ++ ++struct GKETH_rng_info { ++ struct sk_buff *skb; ++ dma_addr_t mapping; ++ unsigned long buf_size; ++}; ++ ++struct GKETH_tx_rngmng { ++ unsigned int cur_tx; ++ unsigned int dirty_tx; ++ struct GKETH_rng_info *rng_tx; ++ struct GKETH_desc *desc_tx; ++}; ++ ++struct GKETH_rx_rngmng { ++ unsigned int cur_rx; ++ unsigned int dirty_rx; ++ struct GKETH_rng_info *rng_rx; ++ struct GKETH_desc *desc_rx; ++}; ++ ++struct GKETH_info { ++ unsigned int rx_count; ++ struct GKETH_rx_rngmng rx; ++ unsigned int tx_count; ++ unsigned int tx_irq_count; ++ struct GKETH_tx_rngmng tx; ++ dma_addr_t rx_dma_desc; ++ dma_addr_t tx_dma_desc; ++ spinlock_t lock; ++ int oldspeed; ++ int oldduplex; ++ int oldlink; ++ ++ struct net_device_stats stats; ++ struct napi_struct napi; ++ struct net_device *ndev; ++ struct mii_bus new_bus; ++ struct phy_device *phydev; ++ uint32_t msg_enable; ++ ++ unsigned char __iomem *regbase; ++ struct gk_eth_platform_info *platform_info; ++}; ++ ++/* ==========================================================================*/ ++extern uint8_t cmdline_phytype; ++static int msg_level = -1; ++module_param (msg_level, int, 0); ++MODULE_PARM_DESC (msg_level, "Override default message level"); ++ ++typedef union { /* EPHY_SPEED */ ++ u16 all; ++ struct { ++ u16 ltp_f : 8; ++ u16 isolate : 1; ++ u16 rptr : 1; ++ u16 duplex : 1; ++ u16 speed : 1; ++ u16 ane : 1; ++ u16 ldps : 1; ++ u16 disable_eee_force : 1; ++ u16 : 1; ++ } bitc; ++} GH_EPHY_SPEED_S; ++ ++static void GK_EPHY_POWER_OFF(void) ++{ ++ u16 dat; ++ ++ dat = gk_eth_readl(REG_EPHY_POWER); ++ //printk("power reg : 0x%04x\n", dat); ++ ++ gk_eth_writel(REG_EPHY_POWER, 0x03ff); ++} ++ ++static void GK_EPHY_POWER_ON(void) ++{ ++ u16 dat; ++ ++ dat = gk_eth_readl(REG_EPHY_POWER); ++ //printk("power reg : 0x%04x\n", dat); ++ ++ gk_eth_writel(REG_EPHY_POWER, 0); ++} ++ ++static void GH_EPHY_set_SPEED_ane(u8 data) ++{ ++ GH_EPHY_SPEED_S d; ++ d.all = gk_eth_readl(REG_EPHY_SPEED); ++ //d.all = *(volatile u16 *)REG_EPHY_SPEED; ++ d.bitc.ane = data; ++ gk_eth_writel(REG_EPHY_SPEED, d.all); ++ //*(volatile u16 *)REG_EPHY_SPEED = d.all; ++} ++ ++static void MHal_EMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ u32 address = REG_EPHY_CONTROL + (bank-0x32)*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ gk_eth_writeb(address, val); ++ //*( ( volatile u8* ) address ) = val; ++} ++ ++static u8 MHal_EMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ u32 address = REG_EPHY_CONTROL + (bank-0x32)*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ val = gk_eth_readb(address); ++ //val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++/* ==========================================================================*/ ++static inline int gkhw_dma_reset(struct GKETH_info *lp) ++{ ++ int errorCode = 0; ++ u32 counter = 0; ++ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ ETH_DMA_BUS_MODE_SWR); ++ do { ++ if (counter++ > 1000) { ++ errorCode = -EIO; ++ break; ++ } ++ mdelay(1); ++ } while (gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ ETH_DMA_BUS_MODE_SWR)); ++ ++ if (errorCode && netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "DMA Error: Check PHY.\n"); ++ //else printk("dma reset ok\n"); ++ ++ return errorCode; ++} ++ ++static inline void gkhw_dma_int_enable(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_DMA_INTEN); ++} ++ ++static inline void gkhw_dma_int_disable(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), 0); ++} ++ ++static inline void gkhw_dma_rx_start(struct GKETH_info *lp) ++{ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_SR); ++} ++ ++static inline void gkhw_dma_rx_stop(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_SR); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & ETH_DMA_STATUS_RS_MASK) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop RX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++} ++ ++static inline void gkhw_dma_tx_start(struct GKETH_info *lp) ++{ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_ST); ++} ++ ++static inline void gkhw_dma_tx_stop(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_ST); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & ETH_DMA_STATUS_TS_MASK) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop TX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_FTF); ++} ++ ++static inline void gkhw_dma_tx_restart(struct GKETH_info *lp, u32 entry) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_DESC_LIST_OFFSET), ++ (u32)lp->tx_dma_desc + (entry * sizeof(struct GKETH_desc))); ++ gkhw_dma_tx_start(lp); ++} ++ ++static inline void gkhw_dma_tx_poll(struct GKETH_info *lp, u32 entry) ++{ ++ lp->tx.desc_tx[entry].status = ETH_TDES0_OWN; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_POLL_DMD_OFFSET), 0x01); ++} ++ ++static inline void gkhw_stop_tx_rx(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_RE); ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ (ETH_DMA_OPMODE_SR | ETH_DMA_OPMODE_ST)); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & (ETH_DMA_STATUS_TS_MASK | ++ ETH_DMA_STATUS_RS_MASK)) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop TX/RX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_TE); ++} ++ ++static inline void gkhw_set_dma_desc(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_RX_DESC_LIST_OFFSET), ++ lp->rx_dma_desc); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_DESC_LIST_OFFSET), ++ lp->tx_dma_desc); ++} ++ ++static inline phy_interface_t gkhw_get_interface(struct GKETH_info *lp) ++{ ++ return gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_PS) ? PHY_INTERFACE_MODE_RMII : ++ PHY_INTERFACE_MODE_RMII; ++ ++} ++ ++static inline void gkhw_set_hwaddr(struct GKETH_info *lp, u8 *hwaddr) ++{ ++ u32 val; ++ ++ val = (hwaddr[5] << 8) | hwaddr[4]; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_MAC0_HI_OFFSET), val); ++ udelay(4); ++ val = (hwaddr[3] << 24) | (hwaddr[2] << 16) | ++ (hwaddr[1] << 8) | hwaddr[0]; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_MAC0_LO_OFFSET), val); ++} ++ ++static inline void gkhw_get_hwaddr(struct GKETH_info *lp, u8 *hwaddr) ++{ ++ u32 hval; ++ u32 lval; ++ ++ hval = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_MAC0_HI_OFFSET)); ++ lval = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_MAC0_LO_OFFSET)); ++ hwaddr[5] = ((hval >> 8) & 0xff); ++ hwaddr[4] = ((hval >> 0) & 0xff); ++ hwaddr[3] = ((lval >> 24) & 0xff); ++ hwaddr[2] = ((lval >> 16) & 0xff); ++ hwaddr[1] = ((lval >> 8) & 0xff); ++ hwaddr[0] = ((lval >> 0) & 0xff); ++} ++ ++static inline void gkhw_set_link_mode_speed(struct GKETH_info *lp) ++{ ++ u32 val; ++ ++ val = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET)); ++ switch (lp->oldspeed) { ++ case SPEED_1000: ++ val &= ~(ETH_MAC_CFG_PS); ++ break; ++ case SPEED_100: ++ case SPEED_10: ++ default: ++ val |= ETH_MAC_CFG_PS; ++ break; ++ } ++ if (lp->oldduplex) { ++ val &= ~(ETH_MAC_CFG_DO); ++ val |= ETH_MAC_CFG_DM; ++ } else { ++ // Steven Yu: if DO==1, would disable the receive. ++ //val &= ~(ETH_MAC_CFG_DO); ++ val &= ~(ETH_MAC_CFG_DO); ++ // Steven Yu: if DM==0, phytype==0, TX Error: No Carrier. ++ //val &= ~(ETH_MAC_CFG_DM); ++ val |= ETH_MAC_CFG_DM; ++ } ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), val); ++} ++ ++static inline int gkhw_enable(struct GKETH_info *lp) ++{ ++ int errorCode = 0; ++ ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 1); ++ //gk_set_gpio_reset(&lp->platform_info->mii_reset); ++ ++ errorCode = gkhw_dma_reset(lp); ++ if (errorCode) ++ goto gkhw_init_exit; ++ ++ gkhw_set_hwaddr(lp, lp->ndev->dev_addr); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ lp->platform_info->default_dma_bus_mode); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_FRAME_FILTER_OFFSET), 0); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ lp->platform_info->default_dma_opmode); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_TSF); ++#endif ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET))); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ (ETH_MAC_CFG_TE | ETH_MAC_CFG_RE | (1<<4)| (1<<7)| (1<<8))); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_IPC); ++#endif ++ ++gkhw_init_exit: ++ return errorCode; ++} ++ ++static inline void gkhw_disable(struct GKETH_info *lp) ++{ ++ gkhw_stop_tx_rx(lp); ++ gkhw_dma_int_disable(lp); ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 0); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 1); ++} ++ ++static inline void gkhw_dump(struct GKETH_info *lp) ++{ ++ u32 i; ++ ++ dev_info(&lp->ndev->dev, "RX Info: cur_rx %d, dirty_rx %d.\n", ++ lp->rx.cur_rx, lp->rx.dirty_rx); ++ dev_info(&lp->ndev->dev, "RX Info: RX descriptor " ++ "0x%08x 0x%08x 0x%08x 0x%08x.\n", ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].status, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].length, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].buffer1, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].buffer2); ++ dev_info(&lp->ndev->dev, "TX Info: cur_tx %d, dirty_tx %d.\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx); ++ for (i = lp->tx.dirty_tx; i < lp->tx.cur_tx; i++) { ++ dev_info(&lp->ndev->dev, "TX Info: TX descriptor[%d] " ++ "0x%08x 0x%08x 0x%08x 0x%08x.\n", i, ++ lp->tx.desc_tx[i % lp->tx_count].status, ++ lp->tx.desc_tx[i % lp->tx_count].length, ++ lp->tx.desc_tx[i % lp->tx_count].buffer1, ++ lp->tx.desc_tx[i % lp->tx_count].buffer2); ++ } ++ for (i = 0; i <= 21; i++) { ++ dev_info(&lp->ndev->dev, "GMAC[%d]: 0x%08x.\n", i, ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET + (i << 2)))); ++ } ++ for (i = 0; i <= 54; i++) { ++ dev_info(&lp->ndev->dev, "GDMA[%d]: 0x%08x.\n", i, ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET + (i << 2)))); ++ } ++} ++ ++/* ==========================================================================*/ ++static int gkhw_mdio_read(struct mii_bus *bus, ++ int mii_id, int regnum) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ struct GKETH_info *lp; ++ int val; ++ int limit; ++ int addr; ++ ++ if(cmdline_phytype != 0){ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Preread tmo!\n"); ++ val = 0xFFFFFFFF; ++ goto gkhw_mdio_read_exit; ++ } ++ ++ val = ETH_MAC_GMII_ADDR_PA(mii_id) | ETH_MAC_GMII_ADDR_GR(regnum); ++ val |= ETH_MAC_GMII_ADDR_CR_100_150MHZ | ETH_MAC_GMII_ADDR_GB; ++ //val |= ETH_MAC_GMII_ADDR_CR_60_100MHZ | ETH_MAC_GMII_ADDR_GB; ++ //val |= ETH_MAC_GMII_ADDR_CR_250_300MHZ | ETH_MAC_GMII_ADDR_GB; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), val); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Postread tmo!\n"); ++ val = 0xFFFFFFFF; ++ goto gkhw_mdio_read_exit; ++ } ++ ++ val = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_GMII_DATA_OFFSET)); ++ ++ gkhw_mdio_read_exit: ++ if (netif_msg_hw(lp)) ++ { ++ printk("mdio read error\n"); ++ dev_info(&lp->ndev->dev, ++ "MII Read: id[0x%02x], add[0x%02x], val[0x%04x].\n", ++ mii_id, regnum, val); ++ } ++ ++ return val; ++ } else { ++//#else ++ ++ lp = (struct GKETH_info *)bus->priv; ++ addr = REG_EPHY_CONTROL + regnum * 4; ++ val = gk_eth_readl((unsigned int)(REG_EPHY_CONTROL + regnum * 4)); ++ if(regnum == 1){ ++ if((gk_eth_readl((unsigned int)(REG_EPHY_CONTROL + 4)) & (0x1 << 5)) != 0) ++ val |= 0x1 << 2; ++ } ++ return val; ++ } ++//#endif ++} ++ ++static int gkhw_mdio_write(struct mii_bus *bus, ++ int mii_id, int regnum, u16 value) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++#define INTER_PHY_BASE 0xF0022000 ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ int val; ++ int limit = 0; ++ ++ if(cmdline_phytype != 0){ ++ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ if (netif_msg_hw(lp)) ++ dev_info(&lp->ndev->dev, ++ "MII Write: id[0x%02x], add[0x%02x], val[0x%04x].\n", ++ mii_id, regnum, value); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Prewrite tmo!\n"); ++ errorCode = -EIO; ++ goto gkhw_mdio_write_exit; ++ } ++ ++ val = value; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_DATA_OFFSET), val); ++ val = ETH_MAC_GMII_ADDR_PA(mii_id) | ETH_MAC_GMII_ADDR_GR(regnum); ++ val |= ETH_MAC_GMII_ADDR_CR_100_150MHZ | ETH_MAC_GMII_ADDR_GW | ++ //val |= ETH_MAC_GMII_ADDR_CR_60_100MHZ | ETH_MAC_GMII_ADDR_GW | ++ //val |= ETH_MAC_GMII_ADDR_CR_250_300MHZ | ETH_MAC_GMII_ADDR_GW | ++ ETH_MAC_GMII_ADDR_GB; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), val); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Postwrite tmo!\n"); ++ errorCode = -EIO; ++ goto gkhw_mdio_write_exit; ++ } ++ ++gkhw_mdio_write_exit: ++ return errorCode; ++ } else { ++//#else ++ ++ lp = (struct GKETH_info *)bus->priv; ++ gk_eth_writel((unsigned int)(INTER_PHY_BASE + regnum * 4), value); ++ return 0; ++ } ++//#endif ++} ++ ++static int gkhw_mdio_reset(struct mii_bus *bus) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ // LindengYu: Add reset to here ++ printk("###### PHY Reset.1.0.2\n"); ++ gk_set_gpio_output(&lp->platform_info->phy_reset, 0); ++ mdelay(10);//100ms ++ gk_set_gpio_output(&lp->platform_info->phy_reset, 1); ++ // RTL8201 need 200ms ++ mdelay(100);//100ms ++ return errorCode; ++} ++ ++#if 0 ++static int gkhw_phy_reset(struct GKETH_info *lp) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ printk("cmdline_phytype = %d\n", cmdline_phytype); ++ if(cmdline_phytype != 0){ ++ struct gk_eth_platform_info *pf; ++ ++ pf = lp->platform_info; ++ ++ if(pf != NULL) ++ { ++ //dev_err(&lp->ndev->dev,"###### PHY Reset.1.0.1\n"); ++ printk("###### PHY Reset.1.0.1\n"); ++ gk_set_gpio_output(&pf->phy_reset, 0); ++ mdelay(50);//100ms ++ gk_set_gpio_output(&pf->phy_reset, 1); ++ mdelay(200);//100ms ++ } ++ ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 0); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 1); ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 1); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 0); ++ } ++//#endif ++ return 0; ++ ++} ++#endif ++ ++/* ==========================================================================*/ ++static void GKETH_adjust_link(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ struct phy_device *phydev; ++ int need_update = 0; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ if (phydev->link) ++ { ++ if (phydev->duplex != lp->oldduplex) ++ { ++ need_update = 1; ++ lp->oldduplex = phydev->duplex; ++ } ++ if (phydev->speed != lp->oldspeed) ++ { ++ switch (phydev->speed) ++ { ++ case SPEED_1000: ++ case SPEED_100: ++ case SPEED_10: ++ need_update = 1; ++ lp->oldspeed = phydev->speed; ++ break; ++ default: ++ if (netif_msg_link(lp)) ++ dev_warn(&lp->ndev->dev, ++ "Unknown Speed(%d).\n", ++ phydev->speed); ++ break; ++ } ++ } ++ if (lp->oldlink != phydev->link) ++ { ++ need_update = 1; ++ lp->oldlink = phydev->link; ++ } ++ } ++ else if (lp->oldlink) ++ { ++ need_update = 1; ++ lp->oldlink = PHY_DOWN; ++ lp->oldspeed = 0; ++ lp->oldduplex = -1; ++ } ++ ++ if (need_update) ++ { ++ u16 rmii; ++ gkhw_set_link_mode_speed(lp); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr , 0x01); ++ //printk("#############-------------reg1 %04x--------\n", rmii); ++ if (phydev->link) ++ { ++ switch (phydev->speed) ++ { ++ case SPEED_100: ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_OUTPUT_EPHY_LED_3); ++ } ++ GH_GPIO_set_INPUT_CFG_in_sel(GPIO_GET_IN_SEL(GPIO_TYPE_INPUT_ENET_PHY_RXD_3) - 2, 0x01); ++ break; ++ case SPEED_10: ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_OUTPUT_EPHY_LED_2); ++ } ++ GH_GPIO_set_INPUT_CFG_in_sel(GPIO_GET_IN_SEL(GPIO_TYPE_INPUT_ENET_PHY_RXD_3) - 2, 0x00); ++ break; ++ default: ++ break; ++ } ++ } ++ else ++ { ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_INPUT_0); ++ } ++ } ++ if (netif_msg_link(lp)) ++ phy_print_status(phydev); ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++} ++ ++typedef union { /* EPHY_MII_RMII */ ++ u32 all; ++ struct { ++ u32 usb_tm1 : 1; ++ u32 rmii : 1; ++ u32 : 30; ++ } bitc; ++} GH_EPHY_MII_RMII_S; ++ ++#define REG_EPHY_MII_RMII GK_VA_AHB_GREG //(0xF0020E00) /* read/write */ ++ ++void GH_EPHY_set_MII_RMII_rmii(u8 data) ++{ ++ GH_EPHY_MII_RMII_S d; ++ d.all = gk_eth_readl(REG_EPHY_MII_RMII); ++ //d.all = *(volatile u32 *)REG_EPHY_MII_RMII; ++ d.bitc.rmii = data; ++ gk_eth_writel(REG_EPHY_MII_RMII, d.all); ++ //*(volatile u32 *)REG_EPHY_MII_RMII = d.all; ++} ++ ++static int GKETH_phy_start(struct GKETH_info *lp) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ int errorCode = 0; ++ struct phy_device *phydev; ++ phy_interface_t interface; ++ struct net_device *ndev; ++ int phy_addr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (phydev) ++ goto GKETH_init_phy_exit; ++ ++ ndev = lp->ndev; ++ lp->oldlink = PHY_DOWN; ++ lp->oldspeed = 0; ++ lp->oldduplex = -1; ++ ++ if(cmdline_phytype != 0) ++ { ++ phy_addr = lp->platform_info->mii_id; ++ if ((phy_addr >= 0) && (phy_addr < PHY_MAX_ADDR)) ++ { ++ if (lp->new_bus.phy_map[phy_addr]) ++ { ++ phydev = lp->new_bus.phy_map[phy_addr]; ++ if (phydev->phy_id == lp->platform_info->phy_id) ++ { ++ goto GKETH_init_phy_default; ++ } ++ } ++ dev_notice(&lp->ndev->dev, ++ "Could not find default PHY in %d.\n", phy_addr); ++ } ++ goto GKETH_init_phy_scan; ++ ++ GKETH_init_phy_default: ++ printk("GKETH_init_phy_default ...\n"); ++ if (netif_msg_hw(lp)) ++ dev_info(&lp->ndev->dev, "Find default PHY in %d!\n", phy_addr); ++ goto GKETH_init_phy_connect; ++ ++ GKETH_init_phy_scan: ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { ++ if (lp->new_bus.phy_map[phy_addr]) { ++ phydev = lp->new_bus.phy_map[phy_addr]; ++ if (phydev->phy_id == lp->platform_info->phy_id) ++ goto GKETH_init_phy_connect; ++ } ++ } ++ if (!phydev) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "No PHY device.\n"); ++ errorCode = -ENODEV; ++ goto GKETH_init_phy_exit; ++ } else { ++ if (netif_msg_drv(lp)) ++ dev_notice(&lp->ndev->dev, ++ "Try PHY[%d] whose id is 0x%08x!\n", ++ phydev->addr, phydev->phy_id); ++ } ++ ++ GKETH_init_phy_connect: ++ interface = gkhw_get_interface(lp); ++ ++ phydev = phy_connect(ndev, dev_name(&phydev->dev), ++ &GKETH_adjust_link, 0, interface); ++ if (IS_ERR(phydev)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "Could not attach to PHY!\n"); ++ errorCode = PTR_ERR(phydev); ++ goto GKETH_init_phy_exit; ++ } ++ ++ //phydev->supported &= lp->platform_info->phy_supported; ++ phydev->supported = lp->platform_info->phy_supported; ++ phydev->advertising = phydev->supported; ++ ++ //GH_EPHY_set_MII_RMII_rmii(0x0); ++ ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ lp->phydev = phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_start_aneg...\n"); ++ ++ errorCode = phy_start_aneg(phydev); ++ ++ GKETH_init_phy_exit: ++ return errorCode; ++ } else { ++ ++//#else ++ interface = gkhw_get_interface(lp); ++ phydev = lp->new_bus.phy_map[0]; ++ phydev = phy_connect(ndev, dev_name(&phydev->dev), ++ &GKETH_adjust_link, 0, interface); ++ if (IS_ERR(phydev)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "Could not attach to PHY!\n"); ++ errorCode = PTR_ERR(phydev); ++ return errorCode; ++ } ++ ++ phydev->supported = lp->platform_info->phy_supported; ++ phydev->advertising = phydev->supported; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ lp->phydev = phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_start_aneg...\n"); ++ ++ errorCode = phy_start_aneg(phydev); ++ return 0; ++ } ++} ++ ++static void GKETH_phy_stop(struct GKETH_info *lp) ++{ ++ struct phy_device *phydev; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_stop\n"); ++ lp->phydev = NULL; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (phydev) ++ phy_disconnect(phydev); ++} ++ ++static inline int GKETH_rx_rngmng_check_skb(struct GKETH_info *lp, u32 entry) ++{ ++ int errorCode = 0; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ ++ if (lp->rx.rng_rx[entry].skb == NULL) { ++ skb = dev_alloc_skb(GKETH_PACKET_MAXFRAME); ++ if (skb == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: dev_alloc_skb.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_rx_rngmng_skb_exit; ++ } ++ ++ skb->dev = lp->ndev; ++ lp->rx.rng_rx[entry].buf_size = GKETH_PACKET_MAXFRAME; ++ mapping = dma_map_single(&lp->ndev->dev, ++ skb->data, ++ lp->rx.rng_rx[entry].buf_size, ++ DMA_FROM_DEVICE); ++ ++ lp->rx.rng_rx[entry].skb = skb; ++ lp->rx.rng_rx[entry].mapping = mapping; ++ lp->rx.desc_rx[entry].buffer1 = mapping; ++ } ++ ++GKETH_rx_rngmng_skb_exit: ++ return errorCode; ++} ++ ++static inline void GKETH_rx_rngmng_init(struct GKETH_info *lp) ++{ ++ int i; ++ ++ lp->rx.cur_rx = 0; ++ lp->rx.dirty_rx = 0; ++ for (i = 0; i < lp->rx_count; i++) { ++ if (GKETH_rx_rngmng_check_skb(lp, i)) ++ break; ++ lp->rx.desc_rx[i].status = ETH_RDES0_OWN; ++ lp->rx.desc_rx[i].length = ++ ETH_RDES1_RCH | GKETH_PACKET_MAXFRAME; ++ lp->rx.desc_rx[i].buffer2 = (u32)lp->rx_dma_desc + ++ ((i + 1) * sizeof(struct GKETH_desc)); ++ } ++ lp->rx.desc_rx[lp->rx_count - 1].buffer2 = (u32)lp->rx_dma_desc; ++} ++ ++static inline void GKETH_rx_rngmng_refill(struct GKETH_info *lp) ++{ ++ u32 entry; ++ ++ while (lp->rx.cur_rx > lp->rx.dirty_rx) { ++ entry = lp->rx.dirty_rx % lp->rx_count; ++ if (GKETH_rx_rngmng_check_skb(lp, entry)) ++ break; ++ lp->rx.desc_rx[entry].status = ETH_RDES0_OWN; ++ lp->rx.dirty_rx++; ++ } ++} ++ ++static inline void GKETH_rx_rngmng_del(struct GKETH_info *lp) ++{ ++ int i; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ ++ for (i = 0; i < lp->rx_count; i++) { ++ if (lp->rx.rng_rx) { ++ skb = lp->rx.rng_rx[i].skb; ++ mapping = lp->rx.rng_rx[i].mapping; ++ lp->rx.rng_rx[i].skb = NULL; ++ lp->rx.rng_rx[i].mapping = 0; ++ if (skb) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ lp->rx.rng_rx[i].buf_size, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ } ++ lp->rx.rng_rx[i].buf_size = 0; ++ } ++ if (lp->rx.desc_rx) { ++ lp->rx.desc_rx[i].status = 0; ++ lp->rx.desc_rx[i].length = 0; ++ lp->rx.desc_rx[i].buffer1 = 0xBADF00D0; ++ lp->rx.desc_rx[i].buffer2 = 0xBADF00D0; ++ } ++ } ++} ++ ++static inline void GKETH_tx_rngmng_init(struct GKETH_info *lp) ++{ ++ int i; ++ ++ lp->tx.cur_tx = 0; ++ lp->tx.dirty_tx = 0; ++ for (i = 0; i < lp->tx_count; i++) { ++ lp->tx.rng_tx[i].mapping = 0 ; ++ lp->tx.desc_tx[i].length = (ETH_TDES1_LS | ETH_TDES1_FS | ++ ETH_TDES1_TCH); ++ lp->tx.desc_tx[i].buffer1 = 0; ++ lp->tx.desc_tx[i].buffer2 = (u32)lp->tx_dma_desc + ++ ((i + 1) * sizeof(struct GKETH_desc)); ++ } ++ lp->tx.desc_tx[lp->tx_count - 1].buffer2 = (u32)lp->tx_dma_desc; ++} ++ ++static inline void GKETH_tx_rngmng_del(struct GKETH_info *lp) ++{ ++ int i; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ unsigned int dirty_tx; ++ u32 entry; ++ u32 status; ++ ++ for (dirty_tx = lp->tx.dirty_tx; lp->tx.cur_tx > dirty_tx; dirty_tx++) { ++ entry = dirty_tx % lp->tx_count; ++ if (lp->tx.desc_tx) { ++ status = lp->tx.desc_tx[entry].status; ++ if (status & ETH_TDES0_OWN) ++ lp->stats.tx_dropped++; ++ } ++ } ++ for (i = 0; i < lp->tx_count; i++) { ++ if (lp->tx.rng_tx) { ++ skb = lp->tx.rng_tx[i].skb; ++ mapping = lp->tx.rng_tx[i].mapping; ++ lp->tx.rng_tx[i].skb = NULL; ++ lp->tx.rng_tx[i].mapping = 0; ++ if (skb) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb(skb); ++ } ++ } ++ if (lp->tx.desc_tx) { ++ lp->tx.desc_tx[i].status = 0; ++ lp->tx.desc_tx[i].length = 0; ++ lp->tx.desc_tx[i].buffer1 = 0xBADF00D0; ++ lp->tx.desc_tx[i].buffer2 = 0xBADF00D0; ++ } ++ } ++} ++ ++static inline void GKETH_check_dma_error(struct GKETH_info *lp, ++ u32 irq_status) ++{ ++ u32 miss_ov = 0; ++ ++ if (unlikely(irq_status & ETH_DMA_STATUS_AIS)) { ++ if (irq_status & (ETH_DMA_STATUS_RU | ETH_DMA_STATUS_OVF)) ++ miss_ov = gk_eth_readl((unsigned int)(lp->regbase + ++ ETH_DMA_MISS_FRAME_BOCNT_OFFSET)); ++ ++ if (irq_status & ETH_DMA_STATUS_FBI) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Fatal Bus Error 0x%x.\n", ++ (irq_status & ETH_DMA_STATUS_EB_MASK)); ++ } ++ if (irq_status & ETH_DMA_STATUS_ETI) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Early Transmit.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RWT) { ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Watchdog Timeout.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RPS) { ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Process Stopped.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RU) { ++ if (miss_ov & ETH_DMA_MISS_FRAME_BOCNT_FRAME) { ++ lp->stats.rx_dropped += ++ ETH_DMA_MISS_FRAME_BOCNT_HOST(miss_ov); ++ } ++ gkhw_dma_rx_stop(lp); ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Buffer Unavailable, %d.\n", ++ ETH_DMA_MISS_FRAME_BOCNT_HOST(miss_ov)); ++ } ++ if (irq_status & ETH_DMA_STATUS_UNF) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Underflow.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_OVF) { ++ if (miss_ov & ETH_DMA_MISS_FRAME_BOCNT_FIFO) { ++ lp->stats.rx_fifo_errors += ++ ETH_DMA_MISS_FRAME_BOCNT_APP(miss_ov); ++ } ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive FIFO Overflow, %d.\n", ++ ETH_DMA_MISS_FRAME_BOCNT_APP(miss_ov)); ++ } ++ if (irq_status & ETH_DMA_STATUS_TJT) { ++ lp->stats.tx_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Jabber Timeout.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_TPS) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Process Stopped.\n"); ++ } ++ if (netif_msg_tx_err(lp) || netif_msg_rx_err(lp)) { ++ dev_err(&lp->ndev->dev, "DMA Error: Abnormal: 0x%x.\n", ++ irq_status); ++ gkhw_dump(lp); ++ } ++ } ++} ++ ++static inline void GKETH_interrupt_rx(struct GKETH_info *lp, u32 irq_status) ++{ ++ if (irq_status & GKETH_RXDMA_STATUS) { ++ dev_vdbg(&lp->ndev->dev, "RX IRQ[0x%x]!\n", irq_status); ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_RXDMA_INTEN); ++ napi_schedule(&lp->napi); ++ } ++} ++ ++static inline u32 GKETH_check_tdes0_status(struct GKETH_info *lp, ++ unsigned int status) ++{ ++ u32 tx_retry = 0; ++ ++ if (status & ETH_TDES0_JT) { ++ lp->stats.tx_heartbeat_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Jabber Timeout.\n"); ++ } ++ if (status & ETH_TDES0_FF) { ++ lp->stats.tx_dropped++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Frame Flushed.\n"); ++ } ++ if (status & ETH_TDES0_PCE) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Payload Checksum Error.\n"); ++ } ++ if (status & ETH_TDES0_LCA) { ++ lp->stats.tx_carrier_errors++; ++ dev_err(&lp->ndev->dev, "TX Error: Loss of Carrier.\n"); ++ } ++ if (status & ETH_TDES0_NC) { ++ lp->stats.tx_carrier_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: No Carrier.\n"); ++ } ++ if (status & ETH_TDES0_LCO) { ++ lp->stats.tx_aborted_errors++; ++ lp->stats.collisions++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Late Collision.\n"); ++ } ++ if (status & ETH_TDES0_EC) { ++ lp->stats.tx_aborted_errors++; ++ lp->stats.collisions += ETH_TDES0_CC(status); ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Excessive Collision %d.\n", ++ ETH_TDES0_CC(status)); ++ } ++ if (status & ETH_TDES0_VF) { ++ if (netif_msg_drv(lp)) ++ dev_info(&lp->ndev->dev, "TX Info: VLAN Frame.\n"); ++ } ++ if (status & ETH_TDES0_ED) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Excessive Deferral.\n"); ++ } ++ if (status & ETH_TDES0_UF) { ++ tx_retry = 1; ++ if (netif_msg_tx_err(lp)) { ++ dev_err(&lp->ndev->dev, "TX Error: Underflow Error.\n"); ++ gkhw_dump(lp); ++ } ++ } ++ if (status & ETH_TDES0_DB) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Deferred Bit.\n"); ++ } ++ ++ return tx_retry; ++} ++ ++static inline void GKETH_interrupt_tx(struct GKETH_info *lp, u32 irq_status) ++{ ++ unsigned int dirty_tx; ++ unsigned int dirty_to_tx; ++ u32 entry; ++ u32 status; ++ ++ if (irq_status & GKETH_TXDMA_STATUS) ++ { ++ dev_vdbg(&lp->ndev->dev, "cur_tx[%d], dirty_tx[%d], 0x%x.\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx, irq_status); ++ for (dirty_tx = lp->tx.dirty_tx; dirty_tx < lp->tx.cur_tx; dirty_tx++) ++ { ++ entry = dirty_tx % lp->tx_count; ++ status = lp->tx.desc_tx[entry].status; ++ ++ if (status & ETH_TDES0_OWN) ++ break; ++ ++ if (unlikely(status & ETH_TDES0_ES)) ++ { ++#if defined(GKETH_TDES0_ATOMIC_CHECK) ++ if ((status & ETH_TDES0_ES_MASK) == ++ ETH_TDES0_ES) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, ++ "TX Error: Wrong ES" ++ " 0x%08x vs 0x%08x.\n", ++ status, ++ lp->tx.desc_tx[entry].status); ++ gkhw_dump(lp); ++ } ++ break; ++ } ++#endif ++ if (GKETH_check_tdes0_status(lp, status)) { ++ gkhw_dma_tx_stop(lp); ++ gkhw_dma_tx_restart(lp, entry); ++ gkhw_dma_tx_poll(lp, entry); ++ break; ++ } else { ++ lp->stats.tx_errors++; ++ } ++ } ++ else ++ { ++#if defined(GKETH_TDES0_ATOMIC_CHECK_ALL) ++ udelay(1); ++ if (unlikely(status != ++ lp->tx.desc_tx[entry].status)) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, ++ "TX Error: Wrong status" ++ " 0x%08x vs 0x%08x.\n", ++ status, ++ lp->tx.desc_tx[entry].status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if (unlikely(status & ETH_TDES0_IHE)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: IP Header Error.\n"); ++ } ++#endif ++ lp->stats.tx_bytes += ++ lp->tx.rng_tx[entry].skb->len; ++ lp->stats.tx_packets++; ++ } ++ ++ dma_unmap_single(&lp->ndev->dev, ++ lp->tx.rng_tx[entry].mapping, ++ lp->tx.rng_tx[entry].skb->len, ++ DMA_TO_DEVICE); ++ dev_kfree_skb_irq(lp->tx.rng_tx[entry].skb); ++ lp->tx.rng_tx[entry].skb = NULL; ++ lp->tx.rng_tx[entry].mapping = 0; ++ } ++ ++ dirty_to_tx = lp->tx.cur_tx - dirty_tx; ++ if (unlikely(dirty_to_tx > lp->tx_count)) { ++ netif_stop_queue(lp->ndev); ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: TX OV.\n"); ++ gkhw_dump(lp); ++ gkhw_dma_tx_stop(lp); ++ GKETH_tx_rngmng_del(lp); ++ GKETH_tx_rngmng_init(lp); ++ dirty_tx = dirty_to_tx = 0; ++ } ++ if (likely(dirty_to_tx < (lp->tx_count / 2))) { ++ dev_vdbg(&lp->ndev->dev, "TX Info: Now gap %d.\n", ++ dirty_to_tx); ++ netif_wake_queue(lp->ndev); ++ } ++ lp->tx.dirty_tx = dirty_tx; ++ } ++} ++ ++static irqreturn_t GKETH_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ u32 irq_status; ++ unsigned long flags; ++ ++ ndev = (struct net_device *)dev_id; ++ lp = netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ irq_status = gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ GKETH_check_dma_error(lp, irq_status); ++ GKETH_interrupt_rx(lp, irq_status); ++ GKETH_interrupt_tx(lp, irq_status); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET), irq_status); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static int GKETH_start_hw(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ dev_err(&lp->ndev->dev,"###### GKETH_start_hw\n"); ++ ++ #if 1 ++ //kewell add ++ //LindengYu: if reset, might change the phy address. So, reset the phy before at the get phy id. ++ //gkhw_phy_reset(lp); ++ //GKETH_phy_start(lp); ++ #else ++ gkhw_phy_set_high(lp); ++ gkhw_phy_reset(lp); ++ GH_EPHY_set_MII_RMII_rmii(0x1); ++ #endif ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ errorCode = gkhw_enable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (errorCode) ++ goto GKETH_start_hw_exit; ++ ++ lp->rx.rng_rx = kmalloc((sizeof(struct GKETH_rng_info) * ++ lp->rx_count), GFP_KERNEL); ++ if (lp->rx.rng_rx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "alloc rng_rx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ lp->rx.desc_rx = dma_alloc_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->rx_count), ++ &lp->rx_dma_desc, GFP_KERNEL); ++ if (lp->rx.desc_rx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "dma_alloc_coherent desc_rx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ memset(lp->rx.rng_rx, 0, ++ (sizeof(struct GKETH_rng_info) * lp->rx_count)); ++ memset(lp->rx.desc_rx, 0, ++ (sizeof(struct GKETH_desc) * lp->rx_count)); ++ GKETH_rx_rngmng_init(lp); ++ ++ lp->tx.rng_tx = kmalloc((sizeof(struct GKETH_rng_info) * ++ lp->tx_count), GFP_KERNEL); ++ if (lp->tx.rng_tx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "alloc rng_tx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ lp->tx.desc_tx = dma_alloc_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->tx_count), ++ &lp->tx_dma_desc, GFP_KERNEL); ++ if (lp->tx.desc_tx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "dma_alloc_coherent desc_tx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ memset(lp->tx.rng_tx, 0, ++ (sizeof(struct GKETH_rng_info) * lp->tx_count)); ++ memset(lp->tx.desc_tx, 0, ++ (sizeof(struct GKETH_desc) * lp->tx_count)); ++ GKETH_tx_rngmng_init(lp); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_set_dma_desc(lp); ++ gkhw_dma_rx_start(lp); ++ gkhw_dma_tx_start(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_start_hw_exit: ++ return errorCode; ++} ++ ++static void GKETH_stop_hw(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_disable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ GKETH_tx_rngmng_del(lp); ++ if (lp->tx.desc_tx) { ++ dma_free_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->tx_count), ++ lp->tx.desc_tx, lp->tx_dma_desc); ++ lp->tx.desc_tx = NULL; ++ } ++ if (lp->tx.rng_tx) { ++ kfree(lp->tx.rng_tx); ++ lp->tx.rng_tx = NULL; ++ } ++ ++ GKETH_rx_rngmng_del(lp); ++ if (lp->rx.desc_rx) { ++ dma_free_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->rx_count), ++ lp->rx.desc_rx, lp->rx_dma_desc); ++ lp->rx.desc_rx = NULL; ++ } ++ if (lp->rx.rng_rx) { ++ kfree(lp->rx.rng_rx); ++ lp->rx.rng_rx = NULL; ++ } ++} ++ ++static int GKETH_open(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ u32 rmii; ++//#endif ++ ++ if(!(cmdline_phytype != 0)) { ++ GK_EPHY_POWER_ON(); ++ udelay(1000); ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ errorCode = GKETH_start_hw(ndev); ++ if (errorCode) ++ goto GKETH_open_exit; ++ ++ errorCode = request_irq(ndev->irq, GKETH_interrupt, ++ IRQF_SHARED | IRQF_TRIGGER_HIGH, ndev->name, ndev); ++ if (errorCode) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "Request_irq[%d] fail.\n", ndev->irq); ++ goto GKETH_open_exit; ++ } ++ ++ napi_enable(&lp->napi); ++ netif_start_queue(ndev); ++ ++ ++ netif_carrier_off(ndev); ++ ++ ++ gkhw_dma_int_enable(lp); ++ ++ errorCode = GKETH_phy_start(lp); ++ ++#if 0 ++{ ++ u32 ii; ++ u32 phy_register_value = 0; ++ ++ for(ii = 0; ii < 32; ii++) ++ { ++ phy_register_value = gkhw_mdio_read(&lp->new_bus, 3 , ii); ++ //printk(" [%02d]: 0x%08x\n", ii, phy_register_value); ++ printk( "MII Read: id[0x03], add[0x%02x], val[0x%04x].\n", ++ ii, phy_register_value); ++ } ++} ++#endif ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype != 0) ++ { ++ if(lp->new_bus.phy_used->phy_id == 0x02430c54) // IP101g ++ { ++ // LindengYu: I don't known why do not go into effect. ++ // change to page 3 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x03); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ rmii &= 0x3FFF; ++ rmii |= 0x4000; ++ // change to LED0 mode1, Link/Act mode ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10, rmii); ++ // restore to page 16 ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ } ++ else// if(lp->new_bus.phy_used->phy_id == 0x001CC815) // rtl820x ++ { ++ // change to rmii mode ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 25); ++ rmii |= (1<<10); ++ rmii &= ~(1<<11); ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 25, rmii); ++ } ++ } ++ ++//#endif ++ ++GKETH_open_exit: ++ if (errorCode) { ++ printk("eth open error\n"); ++ GKETH_phy_stop(lp); ++ GKETH_stop_hw(ndev); ++ } ++ ++ return errorCode; ++} ++ ++static int GKETH_stop(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ netif_stop_queue(ndev); ++ napi_disable(&lp->napi); ++ flush_scheduled_work(); ++ free_irq(ndev->irq, ndev); ++ GKETH_phy_stop(lp); ++ GKETH_stop_hw(ndev); ++ ++ //printk("GKETH_stop\n"); ++ GK_EPHY_POWER_OFF(); ++ ++ return errorCode; ++} ++ ++static int GKETH_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ dma_addr_t mapping; ++ u32 entry; ++ unsigned int dirty_to_tx; ++ u32 tx_flag; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ entry = lp->tx.cur_tx % lp->tx_count; ++ dirty_to_tx = lp->tx.cur_tx - lp->tx.dirty_tx; ++ if (dirty_to_tx >= lp->tx_count) { ++ netif_stop_queue(ndev); ++ errorCode = -ENOMEM; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ goto GKETH_hard_start_xmit_exit; ++ } ++ ++ mapping = dma_map_single(&lp->ndev->dev, ++ skb->data, skb->len, DMA_TO_DEVICE); ++ tx_flag = ETH_TDES1_LS | ETH_TDES1_FS | ETH_TDES1_TCH; ++ if (dirty_to_tx >= lp->tx_irq_count) { ++ netif_stop_queue(ndev); ++ tx_flag |= ETH_TDES1_IC; ++ } ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ tx_flag |= ETH_TDES1_CIC_TUI | ETH_TDES1_CIC_HDR; ++ } ++#endif ++ lp->tx.rng_tx[entry].skb = skb; ++ lp->tx.rng_tx[entry].mapping = mapping; ++ lp->tx.desc_tx[entry].buffer1 = mapping; ++ lp->tx.desc_tx[entry].length = ETH_TDES1_TBS1x(skb->len) | tx_flag; ++ lp->tx.cur_tx++; ++ gkhw_dma_tx_poll(lp, entry); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ ndev->trans_start = jiffies; ++ dev_vdbg(&lp->ndev->dev, "TX Info: cur_tx[%d], dirty_tx[%d], " ++ "entry[%d], len[%d], data_len[%d], ip_summed[%d], " ++ "csum_start[%d], csum_offset[%d].\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx, entry, skb->len, skb->data_len, ++ skb->ip_summed, skb->csum_start, skb->csum_offset); ++ ++GKETH_hard_start_xmit_exit: ++ return errorCode; ++} ++ ++static void GKETH_timeout(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ u32 irq_status; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ dev_info(&lp->ndev->dev, "OOM Info:...\n"); ++ spin_lock_irqsave(&lp->lock, flags); ++ irq_status = gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ GKETH_interrupt_tx(lp, irq_status | GKETH_TXDMA_STATUS); ++ gkhw_dump(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ netif_wake_queue(ndev); ++} ++ ++static struct net_device_stats *GKETH_get_stats(struct net_device *ndev) ++{ ++ struct GKETH_info *lp = netdev_priv(ndev); ++ ++ return &lp->stats; ++} ++ ++static inline void GKETH_check_rdes0_status(struct GKETH_info *lp, ++ unsigned int status) ++{ ++ if (status & ETH_RDES0_DE) { ++ lp->stats.rx_frame_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Descriptor Error.\n"); ++ } ++ if (status & ETH_RDES0_SAF) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Source Address Filter Fail.\n"); ++ } ++ if (status & ETH_RDES0_LE) { ++ lp->stats.rx_length_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Length Error.\n"); ++ } ++ if (status & ETH_RDES0_OE) { ++ lp->stats.rx_over_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Overflow Error.\n"); ++ } ++ if (status & ETH_RDES0_VLAN) { ++ if (netif_msg_drv(lp)) ++ dev_info(&lp->ndev->dev, "RX Info: VLAN.\n"); ++ } ++ if (status & ETH_RDES0_IPC) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: IPC Checksum/Giant Frame.\n"); ++ } ++ if (status & ETH_RDES0_LC) { ++ lp->stats.collisions++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Late Collision.\n"); ++ } ++ if (status & ETH_RDES0_FT) { ++ if (netif_msg_rx_err(lp)) ++ dev_info(&lp->ndev->dev, ++ "RX Info: Ethernet-type frame.\n"); ++ } ++ if (status & ETH_RDES0_RWT) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Watchdog Timeout.\n"); ++ } ++ if (status & ETH_RDES0_RE) { ++ lp->stats.rx_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Receive.\n"); ++ } ++ if (status & ETH_RDES0_DBE) { ++ if (gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_PS)) { ++ lp->stats.rx_length_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Dribble Bit.\n"); ++ } ++ } ++ if (status & ETH_RDES0_CE) { ++ lp->stats.rx_crc_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: CRC.\n"); ++ } ++ if (status & ETH_RDES0_RX) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Rx MAC Address/Payload Checksum.\n"); ++ } ++} ++ ++static inline void GKETH_napi_rx(struct GKETH_info *lp, u32 status, u32 entry) ++{ ++ short pkt_len; ++ struct sk_buff *skb; ++ dma_addr_t mapping; ++ ++ pkt_len = ETH_RDES0_FL(status) - 4; ++ ++ if (unlikely(pkt_len > GKETH_RX_COPYBREAK)) { ++ dev_warn(&lp->ndev->dev, "Bogus packet size %d.\n", pkt_len); ++ pkt_len = GKETH_RX_COPYBREAK; ++ lp->stats.rx_length_errors++; ++ } ++ ++ skb = lp->rx.rng_rx[entry].skb; ++ mapping = lp->rx.rng_rx[entry].mapping; ++ if (likely(skb && mapping)) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ lp->rx.rng_rx[entry].buf_size, DMA_FROM_DEVICE); ++ skb->len = 0; ++ skb_put(skb, pkt_len); ++ skb->protocol = eth_type_trans(skb, lp->ndev); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if ((status & ETH_RDES0_COE_MASK) == ETH_RDES0_COE_NOCHKERROR) { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ skb->ip_summed = CHECKSUM_NONE; ++ if (netif_msg_rx_err(lp)) { ++ dev_err(&lp->ndev->dev, ++ "RX Error: RDES0_COE[0x%x].\n", status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++ netif_receive_skb(skb); ++ lp->rx.rng_rx[entry].skb = NULL; ++ lp->rx.rng_rx[entry].mapping = 0; ++ lp->ndev->last_rx = jiffies; ++ lp->stats.rx_packets++; ++ lp->stats.rx_bytes += pkt_len; ++ } else { ++ if (netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "RX Error: %d skb[%p], map[0x%08X].\n", ++ entry, skb, mapping); ++ gkhw_dump(lp); ++ } ++ } ++} ++ ++int GKETH_napi(struct napi_struct *napi, int budget) ++{ ++ int rx_budget = budget; ++ struct GKETH_info *lp; ++ u32 entry; ++ u32 status; ++ unsigned long flags; ++ ++ lp = container_of(napi, struct GKETH_info, napi); ++ ++ if (unlikely(!netif_carrier_ok(lp->ndev))) ++ goto GKETH_poll_complete; ++ ++ while (rx_budget > 0) { ++ entry = lp->rx.cur_rx % lp->rx_count; ++ status = lp->rx.desc_rx[entry].status; ++ if (status & ETH_RDES0_OWN) ++ break; ++#if defined(GKETH_RDES0_ATOMIC_CHECK) ++ if (unlikely((status & (ETH_RDES0_FS | ETH_RDES0_LS)) != ++ (ETH_RDES0_FS | ETH_RDES0_LS))) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, "RX Error: Wrong FS/LS" ++ " cur_rx[%d] status 0x%08x.\n", ++ lp->rx.cur_rx, status); ++ gkhw_dump(lp); ++ } ++ break; ++ } ++#endif ++#if defined(GKETH_TDES0_ATOMIC_CHECK_ALL) ++ udelay(1); ++ if (unlikely(status != lp->rx.desc_rx[entry].status)) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, "RX Error: Wrong status" ++ " 0x%08x vs 0x%08x.\n", ++ status, lp->rx.desc_rx[entry].status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++ if (likely((status & ETH_RDES0_ES) != ETH_RDES0_ES)) { ++ GKETH_napi_rx(lp, status, entry); ++ } else { ++ GKETH_check_rdes0_status(lp, status); ++ } ++ rx_budget--; ++ lp->rx.cur_rx++; ++ ++ if ((lp->rx.cur_rx - lp->rx.dirty_rx) > (lp->rx_count / 4)) ++ GKETH_rx_rngmng_refill(lp); ++ } ++ ++GKETH_poll_complete: ++ if (rx_budget > 0) { ++ GKETH_rx_rngmng_refill(lp); ++ spin_lock_irqsave(&lp->lock, flags); ++ napi_complete(&lp->napi); ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_RXDMA_INTEN); ++ gkhw_dma_rx_start(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ } ++ ++ return (budget - rx_budget); ++} ++ ++static inline u32 gkhw_hashtable_crc(unsigned char *mac) ++{ ++ unsigned char tmpbuf[ETH_ALEN]; ++ int i; ++ u32 crc; ++ ++ for (i = 0; i < ETH_ALEN; i++) ++ tmpbuf[i] = bitrev8(mac[i]); ++ crc = crc32_be(~0, tmpbuf, ETH_ALEN); ++ ++ return (crc ^ ~0); ++} ++ ++static inline void gkhw_hashtable_get(struct net_device *ndev, u32 *hat) ++{ ++ struct netdev_hw_addr *ha; ++ unsigned int bitnr; ++#if 0 ++ unsigned char test1[] = {0x1F,0x52,0x41,0x9C,0xB6,0xAF}; ++ unsigned char test2[] = {0xA0,0x0A,0x98,0x00,0x00,0x45}; ++ dev_info(&ndev->dev, ++ "Test1: 0x%08X.\n", gkhw_hashtable_crc(test1)); ++ dev_info(&ndev->dev, ++ "Test2: 0x%08X.\n", gkhw_hashtable_crc(test2)); ++#endif ++ ++ hat[0] = hat[1] = 0; ++ netdev_for_each_mc_addr(ha, ndev) { ++ if (!(ha->addr[0] & 1)) ++ continue; ++ bitnr = gkhw_hashtable_crc(ha->addr); ++ bitnr >>= 26; ++ bitnr &= 0x3F; ++ hat[bitnr >> 5] |= 1 << (bitnr & 31); ++ } ++} ++ ++static int GKETH_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ struct sockaddr *saddr; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ saddr = (struct sockaddr *)(addr); ++ ++ //if (netif_running(ndev)) ++ // goto fail1; ++ ++ if (!is_valid_ether_addr(saddr->sa_data)) ++ goto fail2; ++ ++ dev_dbg(&lp->ndev->dev, "MAC address[%pM].\n", saddr->sa_data); ++ ++ memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len); ++ gkhw_set_hwaddr(lp, ndev->dev_addr); ++ gkhw_get_hwaddr(lp, ndev->dev_addr); ++ memcpy(lp->platform_info->mac_addr, ndev->dev_addr, GKETH_MAC_SIZE); ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ return 0; ++ ++fail2: ++ spin_unlock_irqrestore(&lp->lock, flags); ++ return -EADDRNOTAVAIL; ++} ++ ++static void GKETH_set_multicast_list(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned int mac_filter; ++ u32 hat[2]; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ ++ mac_filter = gk_eth_readl((unsigned int)(lp->regbase + ++ ETH_MAC_FRAME_FILTER_OFFSET)); ++ hat[0] = 0; ++ hat[1] = 0; ++ ++ if (ndev->flags & IFF_PROMISC) { ++ mac_filter |= ETH_MAC_FRAME_FILTER_PR; ++ } else if (ndev->flags & (~IFF_PROMISC)) { ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PR; ++ } ++ ++ if (ndev->flags & IFF_ALLMULTI) { ++ hat[0] = 0xFFFFFFFF; ++ hat[1] = 0xFFFFFFFF; ++ mac_filter |= ETH_MAC_FRAME_FILTER_PM; ++ } else if (!netdev_mc_empty(ndev)) { ++ gkhw_hashtable_get(ndev, hat); ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PM; ++ mac_filter |= ETH_MAC_FRAME_FILTER_HMC; ++ } else if (ndev->flags & (~IFF_ALLMULTI)) { ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PM; ++ mac_filter |= ETH_MAC_FRAME_FILTER_HMC; ++ } ++ ++ if (netif_msg_hw(lp)) { ++ dev_info(&lp->ndev->dev, "MC Info: flags 0x%x.\n", ndev->flags); ++ dev_info(&lp->ndev->dev, "MC Info: mc_count 0x%x.\n", ++ netdev_mc_count(ndev)); ++ dev_info(&lp->ndev->dev, "MC Info: mac_filter 0x%x.\n", ++ mac_filter); ++ dev_info(&lp->ndev->dev, "MC Info: hat[0x%x:0x%x].\n", ++ hat[1], hat[0]); ++ } ++ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_HASH_HI_OFFSET), hat[1]); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_HASH_LO_OFFSET), hat[0]); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_FRAME_FILTER_OFFSET), mac_filter); ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++} ++ ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void GKETH_poll_controller(struct net_device *ndev) ++{ ++ GKETH_interrupt(ndev->irq, ndev); ++} ++#endif ++ ++static int GKETH_get_settings(struct net_device *ndev, ++ struct ethtool_cmd *ecmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_ethtool_gset(lp->phydev, ecmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++static int GKETH_set_settings(struct net_device *ndev, ++ struct ethtool_cmd *ecmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_ethtool_sset(lp->phydev, ecmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++static int GKETH_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_mii_ioctl(lp->phydev, ifr, cmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++/* ==========================================================================*/ ++static const struct net_device_ops GKETH_netdev_ops = { ++ .ndo_open = GKETH_open, ++ .ndo_stop = GKETH_stop, ++ .ndo_start_xmit = GKETH_hard_start_xmit, ++ .ndo_set_mac_address = GKETH_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_do_ioctl = GKETH_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_tx_timeout = GKETH_timeout, ++ .ndo_get_stats = GKETH_get_stats, ++ .ndo_set_rx_mode = GKETH_set_multicast_list, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = GKETH_poll_controller, ++#endif ++}; ++ ++static const struct ethtool_ops GKETH_ethtool_ops = { ++ .get_settings = GKETH_get_settings, ++ .set_settings = GKETH_set_settings, ++ .get_link = ethtool_op_get_link, ++}; ++ ++static int __devinit GKETH_drv_probe(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ struct gk_eth_platform_info *platform_info; ++ struct resource *reg_res; ++ struct resource *irq_res; ++ ++ void __iomem *eth_base; ++ int i; ++//#ifndef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ u8 uRegVal; ++//#else ++ u32 rmii; ++//#endif ++ ++ ++ platform_info = (struct gk_eth_platform_info *)pdev->dev.platform_data; ++ if (platform_info == NULL) { ++ dev_err(&pdev->dev, "Can't get platform_data!\n"); ++ errorCode = - EPERM; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ if (platform_info->is_enabled) { ++ if (!platform_info->is_enabled()) { ++ dev_err(&pdev->dev, "Not enabled, check HW config!\n"); ++ errorCode = -EPERM; ++ goto GKETH_drv_probe_exit; ++ } ++ } ++ ++ reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (reg_res == NULL) { ++ dev_err(&pdev->dev, "Get reg_res failed!\n"); ++ errorCode = -ENXIO; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (irq_res == NULL) { ++ dev_err(&pdev->dev, "Get irq_res failed!\n"); ++ errorCode = -ENXIO; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ ndev = alloc_etherdev(sizeof(struct GKETH_info)); ++ if (ndev == NULL) { ++ dev_err(&pdev->dev, "alloc_etherdev fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_drv_probe_exit; ++ } ++#if 0 ++ /* get the memory region for the watchdog timer */ ++ size = resource_size(reg_res); ++ if (!request_mem_region(reg_res->start, size, pdev->name)) { ++ dev_err(&pdev->dev, "Failed to get eth's memory region\n"); ++ errorCode = -EBUSY; ++ goto GKETH_drv_probe_free_netdev; ++ } ++ ++ eth_base = ioremap(reg_res->start, size); ++ if (eth_base == NULL) { ++ dev_err(&pdev->dev, "failed to ioremap() region\n"); ++ errorCode = -EINVAL; ++ goto GKTH_drv_probe_free_res; ++ } ++#else ++ eth_base = (void __iomem *)reg_res->start; ++#endif ++ ++#define KE_DEBUG ++#ifdef KE_DEBUG ++ printk("[%s] eth_base = 0x%08x\n", __FUNCTION__, (u32)eth_base); ++#endif ++ ++ SET_NETDEV_DEV(ndev, &pdev->dev); ++ ndev->dev.dma_mask = pdev->dev.dma_mask; ++ ndev->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask; ++ ndev->irq = irq_res->start; ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ ndev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; ++#endif ++ lp = netdev_priv(ndev); ++ spin_lock_init(&lp->lock); ++ lp->ndev = ndev; ++ lp->regbase = (unsigned char __iomem *)eth_base; ++ lp->platform_info = platform_info; ++ lp->rx_count = lp->platform_info->default_rx_ring_size; ++ if (lp->rx_count < GKETH_RX_RNG_MIN) ++ lp->rx_count = GKETH_RX_RNG_MIN; ++ lp->tx_count = lp->platform_info->default_tx_ring_size; ++ if (lp->tx_count < GKETH_TX_RNG_MIN) ++ lp->tx_count = GKETH_TX_RNG_MIN; ++ lp->tx_irq_count = (lp->tx_count * 2) / 3; ++ lp->msg_enable = netif_msg_init(msg_level, NETIF_MSG_DRV | NETIF_MSG_LINK); ++ ++ lp->new_bus.name = "goke MII Bus", ++ lp->new_bus.read = &gkhw_mdio_read; ++ lp->new_bus.write = &gkhw_mdio_write; ++ lp->new_bus.reset = &gkhw_mdio_reset; ++ //pdev->id = 0x3; ++ //lp->platform_info->mii_id = pdev->id; ++ printk("mii id = %d \n", pdev->id); ++ snprintf(lp->new_bus.id, MII_BUS_ID_SIZE, "%x", pdev->id); ++ lp->new_bus.priv = lp; ++ lp->new_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); ++ if (lp->new_bus.irq == NULL) { ++ dev_err(&pdev->dev, "alloc new_bus.irq fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_drv_probe_free_mii_gpio_irq; ++ } ++ for(i = 0; i < PHY_MAX_ADDR; ++i) ++ lp->new_bus.irq[i] = PHY_POLL; ++ lp->new_bus.parent = &pdev->dev; ++ lp->new_bus.state = MDIOBUS_ALLOCATED; ++//#ifndef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype == 0){ ++ lp->new_bus.phy_mask = 0xFFFFFFFE; ++ } ++//#endif ++ ++ //printk("mdiobus register ...\n"); ++ errorCode = mdiobus_register(&lp->new_bus); ++ if (errorCode) { ++ dev_err(&pdev->dev, "mdiobus_register fail%d.\n", errorCode); ++ goto GKETH_drv_probe_kfree_mdiobus; ++ } ++ //printk("ok\n"); ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype != 0) ++ { ++ GH_EPHY_set_MII_RMII_rmii(0x1); ++ // RMII mode GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 used as 10/100M indicator ++ gk_set_phy_speed_led(GPIO_TYPE_INPUT_0); ++ ++ if(lp->new_bus.phy_used->phy_id == 0x02430c54) // IP101g ++ { ++ // LindengYu: I don't known why do not go into effect. ++ // change to page 3 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x03); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ rmii &= 0x3FFF; ++ rmii |= 0x4000; ++ // change to LED0 mode1, Link/Act mode ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10, rmii); ++ // restore to page 16 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x10); ++ } ++ else// if(lp->new_bus.phy_used->phy_id == 0x001CC815) // rtl820x ++ { ++ // change to rmii mode ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 25); ++ rmii |= (1<<10); ++ rmii &= ~(1<<11); ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 25, rmii); ++ } ++#if 0 ++ { ++ u16 reglist[24][2]= ++ { ++ {0x10, 0x00},{0x10, 0x01},{0x10, 0x02},{0x10, 0x03}, ++ {0x10, 0x04},{0x10, 0x05},{0x10, 0x06},{0x10, 0x07}, ++ {0x10, 0x08},{0x10, 0x10},{0x10, 0x11},{0x10, 0x12}, ++ {0x10, 0x14},{0x01, 0x11},{0x01, 0x12},{0x01, 0x17}, ++ {0x02, 0x12},{0x08, 0x11},{0x0B, 0x12},{0x12, 0x11}, ++ {0x03, 0x10},{0x04, 0x10},{0x05, 0x10},{0x11, 0x11}, ++ }; ++ // page 16 ++ u16 regdata; ++ u16 regpage=0x00; ++ u32 i; ++ printk("Page Addr Data\n"); ++ for(i=0;i<24;i++) ++ { ++ if(regpage != reglist[i][0]) ++ { ++ regpage = reglist[i][0]; ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x14, regpage); ++ } ++ regdata = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, reglist[i][1]); ++ printk("%02d %02d 0x%04x\n",reglist[i][0] ,reglist[i][1] ,regdata); ++ } ++ } ++#endif ++ //EPHY POWER OFF ++ //printk("net probe ephy power off\n"); ++ GK_EPHY_POWER_OFF(); ++ } ++ else ++ { ++//#else ++ GH_EPHY_set_MII_RMII_rmii(0x0); ++ #if 0 ++ gk_eth_writel(0xF0022540, 0x00000000); ++ gk_eth_writel(0xF00220C8, 0x0000C400); // reg_test_out(debug_bus_out) ++ gk_eth_writel(0xF00220E0, 0x0000810A); // debug mode ++ gk_eth_writel(0xF0022588, 0x00000007); // DAC 100M clk gate for 10M TX ++ #else ++ gk_eth_writel(GK_VA_ETH_PHY + 0x0540, 0x00000000); ++ gk_eth_writel(GK_VA_ETH_PHY + 0x00C8, 0x0000C400); // reg_test_out(debug_bus_out) ++ gk_eth_writel(GK_VA_ETH_PHY + 0x00E0, 0x0000810A); // debug mode ++ gk_eth_writel(GK_VA_ETH_PHY + 0x0588, 0x00000007); // DAC 100M clk gate for 10M TX ++ #endif ++ MHal_EMAC_WritReg8(0x0033, 0xde, 0x59); ++ MHal_EMAC_WritReg8(0x0033, 0xf4, 0x21); ++ MHal_EMAC_WritReg8(0x0032, 0x72, 0x80); ++ MHal_EMAC_WritReg8(0x0033, 0xfc, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xb7, 0x07); ++ MHal_EMAC_WritReg8(0x0033, 0xcb, 0x11); ++ MHal_EMAC_WritReg8(0x0033, 0xcc, 0x80); ++ MHal_EMAC_WritReg8(0x0033, 0xcd, 0xd1); ++ MHal_EMAC_WritReg8(0x0033, 0xd4, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xb9, 0x40); ++ MHal_EMAC_WritReg8(0x0033, 0xbb, 0x05); ++ MHal_EMAC_WritReg8(0x0033, 0xea, 0x46); ++ MHal_EMAC_WritReg8(0x0033, 0xa1, 0x00); ++ MHal_EMAC_WritReg8(0x0034, 0x3a, 0x03); ++ MHal_EMAC_WritReg8(0x0034, 0x3b, 0x00); ++ ++ //gain shift ++ MHal_EMAC_WritReg8(0x0033, 0xb4, 0x56); ++ ++ //det max ++ MHal_EMAC_WritReg8(0x0033, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(0x0033, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(0x0033, 0x77, 0x18); ++ ++ //snr k value ++ MHal_EMAC_WritReg8(0x0033, 0x43, 0x15); ++ ++ //100 gat ++ MHal_EMAC_WritReg8(0x0034, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(0x0034, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(0x0034, 0x39, 0x41); ++ ++ //10T waveform ++ uRegVal = MHal_EMAC_ReadReg8(0x0034, 0xe8); ++ uRegVal &= 0xf8; ++ uRegVal |= 0x06; ++ MHal_EMAC_WritReg8(0x0034, 0xe8, uRegVal); ++ MHal_EMAC_WritReg8(0x0032, 0x2b, 0x00); ++ ++ //analog ++ MHal_EMAC_WritReg8(0x0033, 0xd8, 0xb0); ++ MHal_EMAC_WritReg8(0x0033, 0xd9, 0x30); ++ ++ //disable EEE ++ uRegVal = MHal_EMAC_ReadReg8(0x0032, 0x2d); ++ uRegVal |= 0x40; ++ MHal_EMAC_WritReg8(0x0032, 0x2d, uRegVal); ++ ++ GH_EPHY_set_SPEED_ane(0x01); ++ } ++//#endif ++ ++ ether_setup(ndev); ++ ndev->netdev_ops = &GKETH_netdev_ops; ++ ndev->watchdog_timeo = lp->platform_info->watchdog_timeo; ++ netif_napi_add(ndev, &lp->napi, GKETH_napi, ++ lp->platform_info->napi_weight); ++ if (!is_valid_ether_addr(lp->platform_info->mac_addr)) ++ random_ether_addr(lp->platform_info->mac_addr); ++ memcpy(ndev->dev_addr, lp->platform_info->mac_addr, GKETH_MAC_SIZE); ++ ++ SET_ETHTOOL_OPS(ndev, &GKETH_ethtool_ops); ++ errorCode = register_netdev(ndev); ++ if (errorCode) { ++ dev_err(&pdev->dev, " register_netdev fail%d.\n", errorCode); ++ goto GKETH_drv_probe_netif_napi_del; ++ } ++ ++ platform_set_drvdata(pdev, ndev); ++ dev_notice(&pdev->dev, "MAC Address[%pM].\n", ndev->dev_addr); ++ ++ goto GKETH_drv_probe_exit; ++ ++GKETH_drv_probe_netif_napi_del: ++ netif_napi_del(&lp->napi); ++ mdiobus_unregister(&lp->new_bus); ++ ++GKETH_drv_probe_kfree_mdiobus: ++ kfree(lp->new_bus.irq); ++ ++GKETH_drv_probe_free_mii_gpio_irq: ++ //iounmap(eth_base); ++ ++//GKTH_drv_probe_free_res: ++ //release_mem_region(reg_res->start, size); ++ ++ ++//GKETH_drv_probe_free_netdev: ++ free_netdev(ndev); ++ ++GKETH_drv_probe_exit: ++ return errorCode; ++} ++ ++static int __devexit GKETH_drv_remove(struct platform_device *pdev) ++{ ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ unregister_netdev(ndev); ++ netif_napi_del(&lp->napi); ++ mdiobus_unregister(&lp->new_bus); ++ kfree(lp->new_bus.irq); ++ platform_set_drvdata(pdev, NULL); ++ free_netdev(ndev); ++ dev_notice(&pdev->dev, "Removed.\n"); ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int GKETH_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ if (!netif_running(ndev)) ++ goto GKETH_drv_suspend_exit; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ napi_disable(&lp->napi); ++ netif_device_detach(ndev); ++ disable_irq(ndev->irq); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_disable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ } ++ ++GKETH_drv_suspend_exit: ++ dev_dbg(&pdev->dev, "%s exit with %d @ %d\n", ++ __func__, errorCode, state.event); ++ return errorCode; ++} ++ ++static int GKETH_drv_resume(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ if (!netif_running(ndev)) ++ goto GKETH_drv_resume_exit; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ errorCode = gkhw_enable(lp); ++ gkhw_set_link_mode_speed(lp); ++ GKETH_rx_rngmng_init(lp); ++ GKETH_tx_rngmng_init(lp); ++ gkhw_set_dma_desc(lp); ++ gkhw_dma_rx_start(lp); ++ gkhw_dma_tx_start(lp); ++ gkhw_dma_int_enable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ if (errorCode) { ++ dev_err(&pdev->dev, "gkhw_enable.\n"); ++ } else { ++ enable_irq(ndev->irq); ++ netif_device_attach(ndev); ++ napi_enable(&lp->napi); ++ } ++ } ++ ++GKETH_drv_resume_exit: ++ dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, errorCode); ++ return errorCode; ++} ++#endif ++ ++static struct platform_driver GKETH_driver = { ++ .probe = GKETH_drv_probe, ++ .remove = __devexit_p(GKETH_drv_remove), ++#ifdef CONFIG_PM ++ .suspend = GKETH_drv_suspend, ++ .resume = GKETH_drv_resume, ++#endif ++ .driver = { ++ .name = "gk-eth", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init GKETH_init(void) ++{ ++ printk("%s\n", __FUNCTION__); ++ return platform_driver_register(&GKETH_driver); ++} ++ ++static void __exit GKETH_exit(void) ++{ ++ platform_driver_unregister(&GKETH_driver); ++} ++ ++module_init(GKETH_init); ++module_exit(GKETH_exit); ++ ++MODULE_DESCRIPTION("Goke GK Ethernet Driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/net/ethernet/goke/gk_eth_v1_01.c b/drivers/net/ethernet/goke/gk_eth_v1_01.c +new file mode 100644 +index 00000000..4bf06c03 +--- /dev/null ++++ b/drivers/net/ethernet/goke/gk_eth_v1_01.c +@@ -0,0 +1,2524 @@ ++/* ++ * drivers/net/arm/gk_eth.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* ==========================================================================*/ ++#define GKETH_PACKET_MAXFRAME (1536) ++#define GKETH_RX_COPYBREAK (1518) ++#define GKETH_RX_RNG_MIN (8) ++#define GKETH_TX_RNG_MIN (4) ++ ++#define GKETH_RXDMA_STATUS (ETH_DMA_STATUS_OVF | ETH_DMA_STATUS_RI | \ ++ ETH_DMA_STATUS_RU | ETH_DMA_STATUS_RPS | \ ++ ETH_DMA_STATUS_RWT) ++#define GKETH_RXDMA_INTEN (ETH_DMA_INTEN_OVE | ETH_DMA_INTEN_RIE | \ ++ ETH_DMA_INTEN_RUE | ETH_DMA_INTEN_RSE | \ ++ ETH_DMA_INTEN_RWE) ++#define GKETH_TXDMA_STATUS (ETH_DMA_STATUS_TI | ETH_DMA_STATUS_TPS | \ ++ ETH_DMA_STATUS_TU | ETH_DMA_STATUS_TJT | \ ++ ETH_DMA_STATUS_UNF) ++#define GKETH_TXDMA_INTEN (ETH_DMA_INTEN_TIE | ETH_DMA_INTEN_TSE | \ ++ ETH_DMA_INTEN_TUE | ETH_DMA_INTEN_TJE | \ ++ ETH_DMA_INTEN_UNE) ++#define GKETH_DMA_INTEN (ETH_DMA_INTEN_NIE | ETH_DMA_INTEN_AIE | \ ++ ETH_DMA_INTEN_FBE | GKETH_RXDMA_INTEN | \ ++ GKETH_TXDMA_INTEN) ++ ++#define GKETH_TDES0_ATOMIC_CHECK ++#undef GKETH_TDES0_ATOMIC_CHECK_ALL ++#define GKETH_RDES0_ATOMIC_CHECK ++#undef GKETH_RDES0_ATOMIC_CHECK_ALL ++ ++/* ==========================================================================*/ ++struct GKETH_desc { ++ u32 status; ++ u32 length; ++ u32 buffer1; ++ u32 buffer2; ++} __attribute((packed)); ++ ++struct GKETH_rng_info { ++ struct sk_buff *skb; ++ dma_addr_t mapping; ++ unsigned long buf_size; ++}; ++ ++struct GKETH_tx_rngmng { ++ unsigned int cur_tx; ++ unsigned int dirty_tx; ++ struct GKETH_rng_info *rng_tx; ++ struct GKETH_desc *desc_tx; ++}; ++ ++struct GKETH_rx_rngmng { ++ unsigned int cur_rx; ++ unsigned int dirty_rx; ++ struct GKETH_rng_info *rng_rx; ++ struct GKETH_desc *desc_rx; ++}; ++ ++struct GKETH_info { ++ unsigned int rx_count; ++ struct GKETH_rx_rngmng rx; ++ unsigned int tx_count; ++ unsigned int tx_irq_count; ++ struct GKETH_tx_rngmng tx; ++ dma_addr_t rx_dma_desc; ++ dma_addr_t tx_dma_desc; ++ spinlock_t lock; ++ int oldspeed; ++ int oldduplex; ++ int oldlink; ++ ++ struct net_device_stats stats; ++ struct napi_struct napi; ++ struct net_device *ndev; ++ struct mii_bus new_bus; ++ struct phy_device *phydev; ++ uint32_t msg_enable; ++ ++ unsigned char __iomem *regbase; ++ struct gk_eth_platform_info *platform_info; ++}; ++ ++/* ==========================================================================*/ ++extern uint8_t cmdline_phytype; ++static int msg_level = -1; ++module_param (msg_level, int, 0); ++MODULE_PARM_DESC (msg_level, "Override default message level"); ++ ++typedef union { /* EPHY_SPEED */ ++ u16 all; ++ struct { ++ u16 ltp_f : 8; ++ u16 isolate : 1; ++ u16 rptr : 1; ++ u16 duplex : 1; ++ u16 speed : 1; ++ u16 ane : 1; ++ u16 ldps : 1; ++ u16 disable_eee_force : 1; ++ u16 : 1; ++ } bitc; ++} GH_EPHY_SPEED_S; ++ ++static void GK_EPHY_POWER_OFF(void) ++{ ++ u16 dat; ++ ++ dat = gk_eth_readl(REG_EPHY_POWER); ++ //printk("power reg : 0x%04x\n", dat); ++ ++ gk_eth_writel(REG_EPHY_POWER, 0x03ff); ++} ++ ++static void GK_EPHY_POWER_ON(void) ++{ ++ u16 dat; ++ ++ dat = gk_eth_readl(REG_EPHY_POWER); ++ //printk("power reg : 0x%04x\n", dat); ++ ++ gk_eth_writel(REG_EPHY_POWER, 0); ++} ++ ++static void GH_EPHY_set_SPEED_ane(u8 data) ++{ ++ GH_EPHY_SPEED_S d; ++ d.all = gk_eth_readl(REG_EPHY_SPEED); ++ //d.all = *(volatile u16 *)REG_EPHY_SPEED; ++ d.bitc.ane = data; ++ gk_eth_writel(REG_EPHY_SPEED, d.all); ++ //*(volatile u16 *)REG_EPHY_SPEED = d.all; ++} ++ ++static void MHal_EMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ u32 address = REG_EPHY_CONTROL + (bank-0x32)*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ gk_eth_writeb(address, val); ++ //*( ( volatile u8* ) address ) = val; ++} ++ ++static u8 MHal_EMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ u32 address = REG_EPHY_CONTROL + (bank-0x32)*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ val = gk_eth_readb(address); ++ //val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++/* ==========================================================================*/ ++static inline int gkhw_dma_reset(struct GKETH_info *lp) ++{ ++ int errorCode = 0; ++ u32 counter = 0; ++ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ ETH_DMA_BUS_MODE_SWR); ++ do { ++ if (counter++ > 1000) { ++ errorCode = -EIO; ++ break; ++ } ++ mdelay(1); ++ } while (gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ ETH_DMA_BUS_MODE_SWR)); ++ ++ if (errorCode && netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "DMA Error: Check PHY.\n"); ++ //else printk("dma reset ok\n"); ++ ++ return errorCode; ++} ++ ++static inline void gkhw_dma_int_enable(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_DMA_INTEN); ++} ++ ++static inline void gkhw_dma_int_disable(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), 0); ++} ++ ++static inline void gkhw_dma_rx_start(struct GKETH_info *lp) ++{ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_SR); ++} ++ ++static inline void gkhw_dma_rx_stop(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_SR); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & ETH_DMA_STATUS_RS_MASK) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop RX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++} ++ ++static inline void gkhw_dma_tx_start(struct GKETH_info *lp) ++{ ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_ST); ++} ++ ++static inline void gkhw_dma_tx_stop(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_ST); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & ETH_DMA_STATUS_TS_MASK) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop TX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_FTF); ++} ++ ++static inline void gkhw_dma_tx_restart(struct GKETH_info *lp, u32 entry) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_DESC_LIST_OFFSET), ++ (u32)lp->tx_dma_desc + (entry * sizeof(struct GKETH_desc))); ++ gkhw_dma_tx_start(lp); ++} ++ ++static inline void gkhw_dma_tx_poll(struct GKETH_info *lp, u32 entry) ++{ ++ lp->tx.desc_tx[entry].status = ETH_TDES0_OWN; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_POLL_DMD_OFFSET), 0x01); ++} ++ ++static inline void gkhw_stop_tx_rx(struct GKETH_info *lp) ++{ ++ unsigned int irq_status; ++ int i = 1300; ++ ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_RE); ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ (ETH_DMA_OPMODE_SR | ETH_DMA_OPMODE_ST)); ++ do { ++ udelay(1); ++ irq_status = ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ } while ((irq_status & (ETH_DMA_STATUS_TS_MASK | ++ ETH_DMA_STATUS_RS_MASK)) && --i); ++ if ((i <= 0) && netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Stop TX/RX status=0x%x, opmode=0x%x.\n", ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET))); ++ } ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_TE); ++} ++ ++static inline void gkhw_set_dma_desc(struct GKETH_info *lp) ++{ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_RX_DESC_LIST_OFFSET), ++ lp->rx_dma_desc); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_TX_DESC_LIST_OFFSET), ++ lp->tx_dma_desc); ++} ++ ++static inline phy_interface_t gkhw_get_interface(struct GKETH_info *lp) ++{ ++ return gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_PS) ? PHY_INTERFACE_MODE_RMII : ++ PHY_INTERFACE_MODE_RMII; ++ ++} ++ ++static inline void gkhw_set_hwaddr(struct GKETH_info *lp, u8 *hwaddr) ++{ ++ u32 val; ++ ++ val = (hwaddr[5] << 8) | hwaddr[4]; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_MAC0_HI_OFFSET), val); ++ udelay(4); ++ val = (hwaddr[3] << 24) | (hwaddr[2] << 16) | ++ (hwaddr[1] << 8) | hwaddr[0]; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_MAC0_LO_OFFSET), val); ++} ++ ++static inline void gkhw_get_hwaddr(struct GKETH_info *lp, u8 *hwaddr) ++{ ++ u32 hval; ++ u32 lval; ++ ++ hval = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_MAC0_HI_OFFSET)); ++ lval = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_MAC0_LO_OFFSET)); ++ hwaddr[5] = ((hval >> 8) & 0xff); ++ hwaddr[4] = ((hval >> 0) & 0xff); ++ hwaddr[3] = ((lval >> 24) & 0xff); ++ hwaddr[2] = ((lval >> 16) & 0xff); ++ hwaddr[1] = ((lval >> 8) & 0xff); ++ hwaddr[0] = ((lval >> 0) & 0xff); ++} ++ ++static inline void gkhw_set_link_mode_speed(struct GKETH_info *lp) ++{ ++ u32 val; ++ ++ val = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET)); ++ switch (lp->oldspeed) { ++ case SPEED_1000: ++ val &= ~(ETH_MAC_CFG_PS); ++ break; ++ case SPEED_100: ++ case SPEED_10: ++ default: ++ val |= ETH_MAC_CFG_PS; ++ break; ++ } ++ if (lp->oldduplex) { ++ val &= ~(ETH_MAC_CFG_DO); ++ val |= ETH_MAC_CFG_DM; ++ } else { ++ // Steven Yu: if DO==1, would disable the receive. ++ val |= (ETH_MAC_CFG_DO); ++ //val &= ~(ETH_MAC_CFG_DO); ++ // Steven Yu: if DM==0, phytype==0, TX Error: No Carrier. ++ val &= ~(ETH_MAC_CFG_DM); ++ //val |= ETH_MAC_CFG_DM; ++ } ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), val); ++} ++ ++static inline int gkhw_enable(struct GKETH_info *lp) ++{ ++ int errorCode = 0; ++ ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 1); ++ //gk_set_gpio_reset(&lp->platform_info->mii_reset); ++ ++ errorCode = gkhw_dma_reset(lp); ++ if (errorCode) ++ goto gkhw_init_exit; ++ ++ gkhw_set_hwaddr(lp, lp->ndev->dev_addr); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET), ++ lp->platform_info->default_dma_bus_mode); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_FRAME_FILTER_OFFSET), 0); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ lp->platform_info->default_dma_opmode); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_OPMODE_OFFSET), ++ ETH_DMA_OPMODE_TSF); ++#endif ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET), ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET))); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ (ETH_MAC_CFG_TE | ETH_MAC_CFG_RE | (1<<4)| (1<<7)| (1<<8))); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_IPC); ++#endif ++ ++gkhw_init_exit: ++ return errorCode; ++} ++ ++static inline void gkhw_disable(struct GKETH_info *lp) ++{ ++ gkhw_stop_tx_rx(lp); ++ gkhw_dma_int_disable(lp); ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 0); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 1); ++} ++ ++static inline void gkhw_dump(struct GKETH_info *lp) ++{ ++ u32 i; ++ ++ dev_info(&lp->ndev->dev, "RX Info: cur_rx %d, dirty_rx %d.\n", ++ lp->rx.cur_rx, lp->rx.dirty_rx); ++ dev_info(&lp->ndev->dev, "RX Info: RX descriptor " ++ "0x%08x 0x%08x 0x%08x 0x%08x.\n", ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].status, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].length, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].buffer1, ++ lp->rx.desc_rx[lp->rx.dirty_rx % lp->rx_count].buffer2); ++ dev_info(&lp->ndev->dev, "TX Info: cur_tx %d, dirty_tx %d.\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx); ++ for (i = lp->tx.dirty_tx; i < lp->tx.cur_tx; i++) { ++ dev_info(&lp->ndev->dev, "TX Info: TX descriptor[%d] " ++ "0x%08x 0x%08x 0x%08x 0x%08x.\n", i, ++ lp->tx.desc_tx[i % lp->tx_count].status, ++ lp->tx.desc_tx[i % lp->tx_count].length, ++ lp->tx.desc_tx[i % lp->tx_count].buffer1, ++ lp->tx.desc_tx[i % lp->tx_count].buffer2); ++ } ++ for (i = 0; i <= 21; i++) { ++ dev_info(&lp->ndev->dev, "GMAC[%d]: 0x%08x.\n", i, ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET + (i << 2)))); ++ } ++ for (i = 0; i <= 54; i++) { ++ dev_info(&lp->ndev->dev, "GDMA[%d]: 0x%08x.\n", i, ++ gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_BUS_MODE_OFFSET + (i << 2)))); ++ } ++} ++ ++/* ==========================================================================*/ ++static int gkhw_mdio_read(struct mii_bus *bus, ++ int mii_id, int regnum) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ struct GKETH_info *lp; ++ int val; ++ int limit; ++ int addr; ++ ++// printk("%s miid %d regnum:%d ",__FUNCTION__,mii_id,regnum); ++ if(cmdline_phytype != 0){ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Preread tmo!\n"); ++ val = 0xFFFFFFFF; ++ goto gkhw_mdio_read_exit; ++ } ++ ++ val = ETH_MAC_GMII_ADDR_PA(mii_id) | ETH_MAC_GMII_ADDR_GR(regnum); ++ //val |= ETH_MAC_GMII_ADDR_CR_100_150MHZ | ETH_MAC_GMII_ADDR_GB; ++ val |= ETH_MAC_GMII_ADDR_CR_60_100MHZ | ETH_MAC_GMII_ADDR_GB; ++ //val |= ETH_MAC_GMII_ADDR_CR_250_300MHZ | ETH_MAC_GMII_ADDR_GB; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), val); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Postread tmo!\n"); ++ val = 0xFFFFFFFF; ++ goto gkhw_mdio_read_exit; ++ } ++ ++ val = gk_eth_readl((unsigned int)(lp->regbase + ETH_MAC_GMII_DATA_OFFSET)); ++ ++ gkhw_mdio_read_exit: ++ if (netif_msg_hw(lp)) ++ { ++ printk("mdio read error\n"); ++ dev_info(&lp->ndev->dev, ++ "MII Read: id[0x%02x], add[0x%02x], val[0x%04x].\n", ++ mii_id, regnum, val); ++ } ++ ++ if(val==0) ++ val=0xffff; ++//printk("value:%x\n",val); ++ return val; ++ } else { ++//#else ++ ++ lp = (struct GKETH_info *)bus->priv; ++ addr = REG_EPHY_CONTROL + regnum * 4; ++ val = gk_eth_readl((unsigned int)(REG_EPHY_CONTROL + regnum * 4)); ++ if(regnum == 1){ ++ if((gk_eth_readl((unsigned int)(REG_EPHY_CONTROL + 4)) & (0x1 << 5)) != 0) ++ val |= 0x1 << 2; ++ } ++ return val; ++ } ++//#endif ++} ++ ++static int gkhw_mdio_write(struct mii_bus *bus, ++ int mii_id, int regnum, u16 value) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++#define INTER_PHY_BASE 0xF0022000 ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ int val; ++ int limit = 0; ++ ++ if(cmdline_phytype != 0){ ++ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ if (netif_msg_hw(lp)) ++ dev_info(&lp->ndev->dev, ++ "MII Write: id[0x%02x], add[0x%02x], val[0x%04x].\n", ++ mii_id, regnum, value); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Prewrite tmo!\n"); ++ errorCode = -EIO; ++ goto gkhw_mdio_write_exit; ++ } ++ ++ val = value; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_DATA_OFFSET), val); ++ val = ETH_MAC_GMII_ADDR_PA(mii_id) | ETH_MAC_GMII_ADDR_GR(regnum); ++ //val |= ETH_MAC_GMII_ADDR_CR_100_150MHZ | ETH_MAC_GMII_ADDR_GW | ++ val |= ETH_MAC_GMII_ADDR_CR_60_100MHZ | ETH_MAC_GMII_ADDR_GW | ++ //val |= ETH_MAC_GMII_ADDR_CR_250_300MHZ | ETH_MAC_GMII_ADDR_GW | ++ ETH_MAC_GMII_ADDR_GB; ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), val); ++ ++ for (limit = lp->platform_info->mii_retry_limit; limit > 0; limit--) { ++ if (!gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_GMII_ADDR_OFFSET), ++ ETH_MAC_GMII_ADDR_GB)) ++ break; ++ udelay(lp->platform_info->mii_retry_tmo); ++ } ++ if ((limit <= 0) && netif_msg_hw(lp)) { ++ dev_err(&lp->ndev->dev, "MII Error: Postwrite tmo!\n"); ++ errorCode = -EIO; ++ goto gkhw_mdio_write_exit; ++ } ++ ++gkhw_mdio_write_exit: ++ return errorCode; ++ } else { ++//#else ++ ++ lp = (struct GKETH_info *)bus->priv; ++ gk_eth_writel((unsigned int)(INTER_PHY_BASE + regnum * 4), value); ++ return 0; ++ } ++//#endif ++} ++ ++static int gkhw_mdio_reset(struct mii_bus *bus) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ ++ lp = (struct GKETH_info *)bus->priv; ++ ++ // LindengYu: Add reset to here ++ printk("###### PHY Reset.1.0.2\n"); ++ //gk_set_gpio_output(&lp->platform_info->phy_reset, 0); ++ gk_gpio_set_out(lp->platform_info->phy_reset.gpio_id, 0); ++ //*(u32 *)(GK_VA_GPIO0 + REG_GPIO_OUTPUT_CFG_OFFSET + 6*4) = 0X0; ++ mdelay(10);//100ms ++ //gk_set_gpio_output(&lp->platform_info->phy_reset, 1); ++ gk_gpio_set_out(lp->platform_info->phy_reset.gpio_id, 1); ++ //*(u32 *)(GK_VA_GPIO0 + REG_GPIO_OUTPUT_CFG_OFFSET + 6*4) = 0X1; ++ // RTL8201 need 200ms ++ mdelay(100);//100ms ++ //gk_set_gpio_reset_can_sleep(&lp->platform_info->phy_reset, 50); ++ return errorCode; ++} ++ ++#if 0 ++static int gkhw_phy_reset(struct GKETH_info *lp) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ printk("cmdline_phytype = %d\n", cmdline_phytype); ++ if(cmdline_phytype != 0){ ++ struct gk_eth_platform_info *pf; ++ ++ pf = lp->platform_info; ++ ++ if(pf != NULL) ++ { ++ //dev_err(&lp->ndev->dev,"###### PHY Reset.1.0.1\n"); ++ printk("###### PHY Reset.1.0.1\n"); ++ gk_set_gpio_output(&pf->phy_reset, 0); ++ mdelay(50);//100ms ++ gk_set_gpio_output(&pf->phy_reset, 1); ++ mdelay(200);//100ms ++ } ++ ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 0); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 1); ++ //gk_set_gpio_output(&lp->platform_info->mii_power, 1); ++ //gk_set_gpio_output(&lp->platform_info->mii_reset, 0); ++ } ++//#endif ++ return 0; ++ ++} ++#endif ++ ++/* ==========================================================================*/ ++static void GKETH_adjust_link(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ struct phy_device *phydev; ++ int need_update = 0; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ if (phydev->link) ++ { ++ if (phydev->duplex != lp->oldduplex) ++ { ++ need_update = 1; ++ lp->oldduplex = phydev->duplex; ++ } ++ if (phydev->speed != lp->oldspeed) ++ { ++ switch (phydev->speed) ++ { ++ case SPEED_1000: ++ case SPEED_100: ++ case SPEED_10: ++ need_update = 1; ++ lp->oldspeed = phydev->speed; ++ break; ++ default: ++ if (netif_msg_link(lp)) ++ dev_warn(&lp->ndev->dev, ++ "Unknown Speed(%d).\n", ++ phydev->speed); ++ break; ++ } ++ } ++ if (lp->oldlink != phydev->link) ++ { ++ need_update = 1; ++ lp->oldlink = phydev->link; ++ } ++ } ++ else if (lp->oldlink) ++ { ++ need_update = 1; ++ lp->oldlink = PHY_DOWN; ++ lp->oldspeed = 0; ++ lp->oldduplex = -1; ++ } ++ ++ if (need_update) ++ { ++ u16 rmii; ++ gkhw_set_link_mode_speed(lp); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr , 0x01); ++// printk("#############-------------reg1 %04x--------\n", rmii); ++ if(cmdline_phytype == 0) ++ { ++ if (phydev->link) ++ { ++ switch (phydev->speed) ++ { ++ case SPEED_100: ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_OUTPUT_EPHY_LED_3); ++ } ++ GH_GPIO_set_INPUT_CFG_in_sel(GPIO_GET_IN_SEL(GPIO_TYPE_INPUT_ENET_PHY_RXD_3) - 2, 0x01); ++ break; ++ case SPEED_10: ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_OUTPUT_EPHY_LED_2); ++ } ++ GH_GPIO_set_INPUT_CFG_in_sel(GPIO_GET_IN_SEL(GPIO_TYPE_INPUT_ENET_PHY_RXD_3) - 2, 0x00); ++ break; ++ default: ++ break; ++ } ++ } ++ else ++ { ++ if(cmdline_phytype == 0) ++ { ++ gk_set_phy_speed_led(GPIO_TYPE_INPUT_0); ++ } ++ } ++ } ++ if (netif_msg_link(lp)) ++ phy_print_status(phydev); ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++} ++ ++typedef union { /* EPHY_MII_RMII */ ++ u32 all; ++ struct { ++ u32 usb_tm1 : 1; ++ u32 rmii : 1; ++ u32 : 30; ++ } bitc; ++} GH_EPHY_MII_RMII_S; ++ ++#define REG_EPHY_MII_RMII GK_VA_AHB_GREG //(0xF0020E00) /* read/write */ ++ ++void GH_EPHY_set_MII_RMII_rmii(u8 data) ++{ ++ GH_EPHY_MII_RMII_S d; ++ d.all = gk_eth_readl(REG_EPHY_MII_RMII); ++ //d.all = *(volatile u32 *)REG_EPHY_MII_RMII; ++ d.bitc.rmii = data; ++ gk_eth_writel(REG_EPHY_MII_RMII, d.all); ++ //*(volatile u32 *)REG_EPHY_MII_RMII = d.all; ++} ++ ++static int GKETH_phy_start(struct GKETH_info *lp) ++{ ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ int errorCode = 0; ++ struct phy_device *phydev; ++ phy_interface_t interface; ++ struct net_device *ndev; ++ int phy_addr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (phydev) ++ goto GKETH_init_phy_exit; ++ ++ ndev = lp->ndev; ++ lp->oldlink = PHY_DOWN; ++ lp->oldspeed = 0; ++ lp->oldduplex = -1; ++ ++ if(cmdline_phytype != 0) ++ { ++ phy_addr = lp->platform_info->mii_id; ++ if ((phy_addr >= 0) && (phy_addr < PHY_MAX_ADDR)) ++ { ++ if (lp->new_bus.phy_map[phy_addr]) ++ { ++ phydev = lp->new_bus.phy_map[phy_addr]; ++ if (phydev->phy_id == lp->platform_info->phy_id) ++ { ++ goto GKETH_init_phy_default; ++ } ++ } ++ dev_notice(&lp->ndev->dev, ++ "Could not find default PHY in %d.\n", phy_addr); ++ } ++ goto GKETH_init_phy_scan; ++ ++ GKETH_init_phy_default: ++ printk("GKETH_init_phy_default ...\n"); ++ if (netif_msg_hw(lp)) ++ dev_info(&lp->ndev->dev, "Find default PHY in %d!\n", phy_addr); ++ goto GKETH_init_phy_connect; ++ ++ GKETH_init_phy_scan: ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { ++ if (lp->new_bus.phy_map[phy_addr]) { ++ phydev = lp->new_bus.phy_map[phy_addr]; ++ if (phydev->phy_id == lp->platform_info->phy_id) ++ goto GKETH_init_phy_connect; ++ } ++ } ++ if (!phydev) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "No PHY device.\n"); ++ errorCode = -ENODEV; ++ goto GKETH_init_phy_exit; ++ } else { ++ if (netif_msg_drv(lp)) ++ dev_notice(&lp->ndev->dev, ++ "Try PHY[%d] whose id is 0x%08x!\n", ++ phydev->addr, phydev->phy_id); ++ } ++ ++ GKETH_init_phy_connect: ++ interface = gkhw_get_interface(lp); ++ ++ phydev = phy_connect(ndev, dev_name(&phydev->dev), ++ &GKETH_adjust_link, 0, interface); ++ if (IS_ERR(phydev)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "Could not attach to PHY!\n"); ++ errorCode = PTR_ERR(phydev); ++ goto GKETH_init_phy_exit; ++ } ++ ++ //phydev->supported &= lp->platform_info->phy_supported; ++ phydev->supported = lp->platform_info->phy_supported; ++ phydev->advertising = phydev->supported; ++ ++ //GH_EPHY_set_MII_RMII_rmii(0x0); ++ ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ lp->phydev = phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_start_aneg...\n"); ++ ++ errorCode = phy_start_aneg(phydev); ++ ++ GKETH_init_phy_exit: ++ return errorCode; ++ } else { ++ ++//#else ++ interface = gkhw_get_interface(lp); ++ phydev = lp->new_bus.phy_map[0]; ++ phydev = phy_connect(ndev, dev_name(&phydev->dev), ++ &GKETH_adjust_link, 0, interface); ++ if (IS_ERR(phydev)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "Could not attach to PHY!\n"); ++ errorCode = PTR_ERR(phydev); ++ return errorCode; ++ } ++ ++ phydev->supported = lp->platform_info->phy_supported; ++ phydev->advertising = phydev->supported; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ lp->phydev = phydev; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_start_aneg...\n"); ++ ++ errorCode = phy_start_aneg(phydev); ++ return 0; ++ } ++} ++ ++static void GKETH_phy_stop(struct GKETH_info *lp) ++{ ++ struct phy_device *phydev; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ phydev = lp->phydev; ++ dev_err(&lp->ndev->dev,"###### GKETH_phy_stop\n"); ++ lp->phydev = NULL; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (phydev) ++ phy_disconnect(phydev); ++} ++ ++static inline int GKETH_rx_rngmng_check_skb(struct GKETH_info *lp, u32 entry) ++{ ++ int errorCode = 0; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ ++ if (lp->rx.rng_rx[entry].skb == NULL) { ++ skb = dev_alloc_skb(GKETH_PACKET_MAXFRAME); ++ if (skb == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: dev_alloc_skb.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_rx_rngmng_skb_exit; ++ } ++ ++ skb->dev = lp->ndev; ++ lp->rx.rng_rx[entry].buf_size = GKETH_PACKET_MAXFRAME; ++ mapping = dma_map_single(&lp->ndev->dev, ++ skb->data, ++ lp->rx.rng_rx[entry].buf_size, ++ DMA_FROM_DEVICE); ++ ++ lp->rx.rng_rx[entry].skb = skb; ++ lp->rx.rng_rx[entry].mapping = mapping; ++ lp->rx.desc_rx[entry].buffer1 = mapping; ++ } ++ ++GKETH_rx_rngmng_skb_exit: ++ return errorCode; ++} ++ ++static inline void GKETH_rx_rngmng_init(struct GKETH_info *lp) ++{ ++ int i; ++ ++ lp->rx.cur_rx = 0; ++ lp->rx.dirty_rx = 0; ++ for (i = 0; i < lp->rx_count; i++) { ++ if (GKETH_rx_rngmng_check_skb(lp, i)) ++ break; ++ lp->rx.desc_rx[i].status = ETH_RDES0_OWN; ++ lp->rx.desc_rx[i].length = ++ ETH_RDES1_RCH | GKETH_PACKET_MAXFRAME; ++ lp->rx.desc_rx[i].buffer2 = (u32)lp->rx_dma_desc + ++ ((i + 1) * sizeof(struct GKETH_desc)); ++ } ++ lp->rx.desc_rx[lp->rx_count - 1].buffer2 = (u32)lp->rx_dma_desc; ++} ++ ++static inline void GKETH_rx_rngmng_refill(struct GKETH_info *lp) ++{ ++ u32 entry; ++ ++ while (lp->rx.cur_rx > lp->rx.dirty_rx) { ++ entry = lp->rx.dirty_rx % lp->rx_count; ++ if (GKETH_rx_rngmng_check_skb(lp, entry)) ++ break; ++ lp->rx.desc_rx[entry].status = ETH_RDES0_OWN; ++ lp->rx.dirty_rx++; ++ } ++} ++ ++static inline void GKETH_rx_rngmng_del(struct GKETH_info *lp) ++{ ++ int i; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ ++ for (i = 0; i < lp->rx_count; i++) { ++ if (lp->rx.rng_rx) { ++ skb = lp->rx.rng_rx[i].skb; ++ mapping = lp->rx.rng_rx[i].mapping; ++ lp->rx.rng_rx[i].skb = NULL; ++ lp->rx.rng_rx[i].mapping = 0; ++ if (skb) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ lp->rx.rng_rx[i].buf_size, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ } ++ lp->rx.rng_rx[i].buf_size = 0; ++ } ++ if (lp->rx.desc_rx) { ++ lp->rx.desc_rx[i].status = 0; ++ lp->rx.desc_rx[i].length = 0; ++ lp->rx.desc_rx[i].buffer1 = 0xBADF00D0; ++ lp->rx.desc_rx[i].buffer2 = 0xBADF00D0; ++ } ++ } ++} ++ ++static inline void GKETH_tx_rngmng_init(struct GKETH_info *lp) ++{ ++ int i; ++ ++ lp->tx.cur_tx = 0; ++ lp->tx.dirty_tx = 0; ++ for (i = 0; i < lp->tx_count; i++) { ++ lp->tx.rng_tx[i].mapping = 0 ; ++ lp->tx.desc_tx[i].length = (ETH_TDES1_LS | ETH_TDES1_FS | ++ ETH_TDES1_TCH); ++ lp->tx.desc_tx[i].buffer1 = 0; ++ lp->tx.desc_tx[i].buffer2 = (u32)lp->tx_dma_desc + ++ ((i + 1) * sizeof(struct GKETH_desc)); ++ } ++ lp->tx.desc_tx[lp->tx_count - 1].buffer2 = (u32)lp->tx_dma_desc; ++} ++ ++static inline void GKETH_tx_rngmng_del(struct GKETH_info *lp) ++{ ++ int i; ++ dma_addr_t mapping; ++ struct sk_buff *skb; ++ unsigned int dirty_tx; ++ u32 entry; ++ u32 status; ++ ++ for (dirty_tx = lp->tx.dirty_tx; lp->tx.cur_tx > dirty_tx; dirty_tx++) { ++ entry = dirty_tx % lp->tx_count; ++ if (lp->tx.desc_tx) { ++ status = lp->tx.desc_tx[entry].status; ++ if (status & ETH_TDES0_OWN) ++ lp->stats.tx_dropped++; ++ } ++ } ++ for (i = 0; i < lp->tx_count; i++) { ++ if (lp->tx.rng_tx) { ++ skb = lp->tx.rng_tx[i].skb; ++ mapping = lp->tx.rng_tx[i].mapping; ++ lp->tx.rng_tx[i].skb = NULL; ++ lp->tx.rng_tx[i].mapping = 0; ++ if (skb) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb(skb); ++ } ++ } ++ if (lp->tx.desc_tx) { ++ lp->tx.desc_tx[i].status = 0; ++ lp->tx.desc_tx[i].length = 0; ++ lp->tx.desc_tx[i].buffer1 = 0xBADF00D0; ++ lp->tx.desc_tx[i].buffer2 = 0xBADF00D0; ++ } ++ } ++} ++ ++static inline void GKETH_check_dma_error(struct GKETH_info *lp, ++ u32 irq_status) ++{ ++ u32 miss_ov = 0; ++ ++ if (unlikely(irq_status & ETH_DMA_STATUS_AIS)) { ++ if (irq_status & (ETH_DMA_STATUS_RU | ETH_DMA_STATUS_OVF)) ++ miss_ov = gk_eth_readl((unsigned int)(lp->regbase + ++ ETH_DMA_MISS_FRAME_BOCNT_OFFSET)); ++ ++ if (irq_status & ETH_DMA_STATUS_FBI) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Fatal Bus Error 0x%x.\n", ++ (irq_status & ETH_DMA_STATUS_EB_MASK)); ++ } ++ if (irq_status & ETH_DMA_STATUS_ETI) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Early Transmit.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RWT) { ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Watchdog Timeout.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RPS) { ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Process Stopped.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_RU) { ++ if (miss_ov & ETH_DMA_MISS_FRAME_BOCNT_FRAME) { ++ lp->stats.rx_dropped += ++ ETH_DMA_MISS_FRAME_BOCNT_HOST(miss_ov); ++ } ++ gkhw_dma_rx_stop(lp); ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive Buffer Unavailable, %d.\n", ++ ETH_DMA_MISS_FRAME_BOCNT_HOST(miss_ov)); ++ } ++ if (irq_status & ETH_DMA_STATUS_UNF) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Underflow.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_OVF) { ++ if (miss_ov & ETH_DMA_MISS_FRAME_BOCNT_FIFO) { ++ lp->stats.rx_fifo_errors += ++ ETH_DMA_MISS_FRAME_BOCNT_APP(miss_ov); ++ } ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Receive FIFO Overflow, %d.\n", ++ ETH_DMA_MISS_FRAME_BOCNT_APP(miss_ov)); ++ } ++ if (irq_status & ETH_DMA_STATUS_TJT) { ++ lp->stats.tx_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Jabber Timeout.\n"); ++ } ++ if (irq_status & ETH_DMA_STATUS_TPS) { ++ if (netif_msg_tx_err(lp)) ++ dev_err(&lp->ndev->dev, ++ "DMA Error: Transmit Process Stopped.\n"); ++ } ++ if (netif_msg_tx_err(lp) || netif_msg_rx_err(lp)) { ++ dev_err(&lp->ndev->dev, "DMA Error: Abnormal: 0x%x.\n", ++ irq_status); ++ gkhw_dump(lp); ++ } ++ } ++} ++ ++static inline void GKETH_interrupt_rx(struct GKETH_info *lp, u32 irq_status) ++{ ++ if (irq_status & GKETH_RXDMA_STATUS) { ++ dev_vdbg(&lp->ndev->dev, "RX IRQ[0x%x]!\n", irq_status); ++ gk_eth_clrbitsl((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_RXDMA_INTEN); ++ napi_schedule(&lp->napi); ++ } ++} ++ ++static inline u32 GKETH_check_tdes0_status(struct GKETH_info *lp, ++ unsigned int status) ++{ ++ u32 tx_retry = 0; ++ ++ if (status & ETH_TDES0_JT) { ++ lp->stats.tx_heartbeat_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Jabber Timeout.\n"); ++ } ++ if (status & ETH_TDES0_FF) { ++ lp->stats.tx_dropped++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Frame Flushed.\n"); ++ } ++ if (status & ETH_TDES0_PCE) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Payload Checksum Error.\n"); ++ } ++ if (status & ETH_TDES0_LCA) { ++ lp->stats.tx_carrier_errors++; ++ dev_err(&lp->ndev->dev, "TX Error: Loss of Carrier.\n"); ++ } ++ if (status & ETH_TDES0_NC) { ++ lp->stats.tx_carrier_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: No Carrier.\n"); ++ } ++ if (status & ETH_TDES0_LCO) { ++ lp->stats.tx_aborted_errors++; ++ lp->stats.collisions++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Late Collision.\n"); ++ } ++ if (status & ETH_TDES0_EC) { ++ lp->stats.tx_aborted_errors++; ++ lp->stats.collisions += ETH_TDES0_CC(status); ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Excessive Collision %d.\n", ++ ETH_TDES0_CC(status)); ++ } ++ if (status & ETH_TDES0_VF) { ++ if (netif_msg_drv(lp)) ++ dev_info(&lp->ndev->dev, "TX Info: VLAN Frame.\n"); ++ } ++ if (status & ETH_TDES0_ED) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: Excessive Deferral.\n"); ++ } ++ if (status & ETH_TDES0_UF) { ++ tx_retry = 1; ++ if (netif_msg_tx_err(lp)) { ++ dev_err(&lp->ndev->dev, "TX Error: Underflow Error.\n"); ++ gkhw_dump(lp); ++ } ++ } ++ if (status & ETH_TDES0_DB) { ++ lp->stats.tx_fifo_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: Deferred Bit.\n"); ++ } ++ ++ return tx_retry; ++} ++ ++static inline void GKETH_interrupt_tx(struct GKETH_info *lp, u32 irq_status) ++{ ++ unsigned int dirty_tx; ++ unsigned int dirty_to_tx; ++ u32 entry; ++ u32 status; ++ ++ if (irq_status & GKETH_TXDMA_STATUS) ++ { ++ dev_vdbg(&lp->ndev->dev, "cur_tx[%d], dirty_tx[%d], 0x%x.\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx, irq_status); ++ for (dirty_tx = lp->tx.dirty_tx; dirty_tx < lp->tx.cur_tx; dirty_tx++) ++ { ++ entry = dirty_tx % lp->tx_count; ++ status = lp->tx.desc_tx[entry].status; ++ ++ if (status & ETH_TDES0_OWN) ++ break; ++ ++ if (unlikely(status & ETH_TDES0_ES)) ++ { ++#if defined(GKETH_TDES0_ATOMIC_CHECK) ++ if ((status & ETH_TDES0_ES_MASK) == ++ ETH_TDES0_ES) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, ++ "TX Error: Wrong ES" ++ " 0x%08x vs 0x%08x.\n", ++ status, ++ lp->tx.desc_tx[entry].status); ++ gkhw_dump(lp); ++ } ++ break; ++ } ++#endif ++ if (GKETH_check_tdes0_status(lp, status)) { ++ gkhw_dma_tx_stop(lp); ++ gkhw_dma_tx_restart(lp, entry); ++ gkhw_dma_tx_poll(lp, entry); ++ break; ++ } else { ++ lp->stats.tx_errors++; ++ } ++ } ++ else ++ { ++#if defined(GKETH_TDES0_ATOMIC_CHECK_ALL) ++ udelay(1); ++ if (unlikely(status != ++ lp->tx.desc_tx[entry].status)) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, ++ "TX Error: Wrong status" ++ " 0x%08x vs 0x%08x.\n", ++ status, ++ lp->tx.desc_tx[entry].status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if (unlikely(status & ETH_TDES0_IHE)) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "TX Error: IP Header Error.\n"); ++ } ++#endif ++ lp->stats.tx_bytes += ++ lp->tx.rng_tx[entry].skb->len; ++ lp->stats.tx_packets++; ++ } ++ ++ dma_unmap_single(&lp->ndev->dev, ++ lp->tx.rng_tx[entry].mapping, ++ lp->tx.rng_tx[entry].skb->len, ++ DMA_TO_DEVICE); ++ dev_kfree_skb_irq(lp->tx.rng_tx[entry].skb); ++ lp->tx.rng_tx[entry].skb = NULL; ++ lp->tx.rng_tx[entry].mapping = 0; ++ } ++ ++ dirty_to_tx = lp->tx.cur_tx - dirty_tx; ++ if (unlikely(dirty_to_tx > lp->tx_count)) { ++ netif_stop_queue(lp->ndev); ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "TX Error: TX OV.\n"); ++ gkhw_dump(lp); ++ gkhw_dma_tx_stop(lp); ++ GKETH_tx_rngmng_del(lp); ++ GKETH_tx_rngmng_init(lp); ++ dirty_tx = dirty_to_tx = 0; ++ } ++ if (likely(dirty_to_tx < (lp->tx_count / 2))) { ++ dev_vdbg(&lp->ndev->dev, "TX Info: Now gap %d.\n", ++ dirty_to_tx); ++ netif_wake_queue(lp->ndev); ++ } ++ lp->tx.dirty_tx = dirty_tx; ++ } ++} ++ ++static irqreturn_t GKETH_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ u32 irq_status; ++ unsigned long flags; ++ ++ ndev = (struct net_device *)dev_id; ++ lp = netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ irq_status = gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ GKETH_check_dma_error(lp, irq_status); ++ GKETH_interrupt_rx(lp, irq_status); ++ GKETH_interrupt_tx(lp, irq_status); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET), irq_status); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static int GKETH_start_hw(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ dev_err(&lp->ndev->dev,"###### GKETH_start_hw\n"); ++ ++ #if 1 ++ //kewell add ++ //LindengYu: if reset, might change the phy address. So, reset the phy before at the get phy id. ++ //gkhw_phy_reset(lp); ++ //GKETH_phy_start(lp); ++ #else ++ gkhw_phy_set_high(lp); ++ gkhw_phy_reset(lp); ++ GH_EPHY_set_MII_RMII_rmii(0x1); ++ #endif ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ errorCode = gkhw_enable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ if (errorCode) ++ goto GKETH_start_hw_exit; ++ ++ lp->rx.rng_rx = kmalloc((sizeof(struct GKETH_rng_info) * ++ lp->rx_count), GFP_KERNEL); ++ if (lp->rx.rng_rx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "alloc rng_rx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ lp->rx.desc_rx = dma_alloc_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->rx_count), ++ &lp->rx_dma_desc, GFP_KERNEL); ++ if (lp->rx.desc_rx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "dma_alloc_coherent desc_rx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ memset(lp->rx.rng_rx, 0, ++ (sizeof(struct GKETH_rng_info) * lp->rx_count)); ++ memset(lp->rx.desc_rx, 0, ++ (sizeof(struct GKETH_desc) * lp->rx_count)); ++ GKETH_rx_rngmng_init(lp); ++ ++ lp->tx.rng_tx = kmalloc((sizeof(struct GKETH_rng_info) * ++ lp->tx_count), GFP_KERNEL); ++ if (lp->tx.rng_tx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "alloc rng_tx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ lp->tx.desc_tx = dma_alloc_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->tx_count), ++ &lp->tx_dma_desc, GFP_KERNEL); ++ if (lp->tx.desc_tx == NULL) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "dma_alloc_coherent desc_tx fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_start_hw_exit; ++ } ++ memset(lp->tx.rng_tx, 0, ++ (sizeof(struct GKETH_rng_info) * lp->tx_count)); ++ memset(lp->tx.desc_tx, 0, ++ (sizeof(struct GKETH_desc) * lp->tx_count)); ++ GKETH_tx_rngmng_init(lp); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_set_dma_desc(lp); ++ gkhw_dma_rx_start(lp); ++ gkhw_dma_tx_start(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_start_hw_exit: ++ return errorCode; ++} ++ ++static void GKETH_stop_hw(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_disable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ GKETH_tx_rngmng_del(lp); ++ if (lp->tx.desc_tx) { ++ dma_free_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->tx_count), ++ lp->tx.desc_tx, lp->tx_dma_desc); ++ lp->tx.desc_tx = NULL; ++ } ++ if (lp->tx.rng_tx) { ++ kfree(lp->tx.rng_tx); ++ lp->tx.rng_tx = NULL; ++ } ++ ++ GKETH_rx_rngmng_del(lp); ++ if (lp->rx.desc_rx) { ++ dma_free_coherent(&lp->ndev->dev, ++ (sizeof(struct GKETH_desc) * lp->rx_count), ++ lp->rx.desc_rx, lp->rx_dma_desc); ++ lp->rx.desc_rx = NULL; ++ } ++ if (lp->rx.rng_rx) { ++ kfree(lp->rx.rng_rx); ++ lp->rx.rng_rx = NULL; ++ } ++} ++ ++static int GKETH_open(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ u32 rmii; ++//#endif ++ ++ if(!(cmdline_phytype != 0)) { ++ GK_EPHY_POWER_ON(); ++ udelay(1000); ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ errorCode = GKETH_start_hw(ndev); ++ if (errorCode) ++ goto GKETH_open_exit; ++ ++ errorCode = request_irq(ndev->irq, GKETH_interrupt, ++ IRQF_SHARED | IRQF_TRIGGER_HIGH, ndev->name, ndev); ++ if (errorCode) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "Request_irq[%d] fail.\n", ndev->irq); ++ goto GKETH_open_exit; ++ } ++ ++ napi_enable(&lp->napi); ++ netif_start_queue(ndev); ++ ++ ++ netif_carrier_off(ndev); ++ ++ ++ gkhw_dma_int_enable(lp); ++ ++ errorCode = GKETH_phy_start(lp); ++ ++#if 0 ++{ ++ u32 ii; ++ u32 phy_register_value = 0; ++ ++ for(ii = 0; ii < 32; ii++) ++ { ++ phy_register_value = gkhw_mdio_read(&lp->new_bus, 3 , ii); ++ //printk(" [%02d]: 0x%08x\n", ii, phy_register_value); ++ printk( "MII Read: id[0x03], add[0x%02x], val[0x%04x].\n", ++ ii, phy_register_value); ++ } ++} ++#endif ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype != 0) ++ { ++ if(lp->new_bus.phy_used->phy_id == 0x02430c54) // IP101g ++ { ++ // LindengYu: I don't known why do not go into effect. ++ // change to page 3 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x03); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ rmii &= 0x3FFF; ++ rmii |= 0x4000; ++ // change to LED0 mode1, Link/Act mode ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10, rmii); ++ // restore to page 16 ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ } ++ else// if(lp->new_bus.phy_used->phy_id == 0x001CC815) // rtl820x ++ { ++ // change to rmii mode ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 25); ++ //rmii |= (1<<10); ++ rmii &= ~(1<<10); ++ rmii &= ~(1<<11); ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 25, rmii); ++ } ++ } ++ ++//#endif ++ ++GKETH_open_exit: ++ if (errorCode) { ++ printk("eth open error\n"); ++ GKETH_phy_stop(lp); ++ GKETH_stop_hw(ndev); ++ } ++ ++ return errorCode; ++} ++ ++static int GKETH_stop(struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ netif_stop_queue(ndev); ++ napi_disable(&lp->napi); ++ flush_scheduled_work(); ++ free_irq(ndev->irq, ndev); ++ GKETH_phy_stop(lp); ++ GKETH_stop_hw(ndev); ++ ++ //printk("GKETH_stop\n"); ++ GK_EPHY_POWER_OFF(); ++ ++ return errorCode; ++} ++ ++static int GKETH_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ dma_addr_t mapping; ++ u32 entry; ++ unsigned int dirty_to_tx; ++ u32 tx_flag; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ entry = lp->tx.cur_tx % lp->tx_count; ++ dirty_to_tx = lp->tx.cur_tx - lp->tx.dirty_tx; ++ if (dirty_to_tx >= lp->tx_count) { ++ netif_stop_queue(ndev); ++ errorCode = -ENOMEM; ++ spin_unlock_irqrestore(&lp->lock, flags); ++ goto GKETH_hard_start_xmit_exit; ++ } ++ ++ mapping = dma_map_single(&lp->ndev->dev, ++ skb->data, skb->len, DMA_TO_DEVICE); ++ tx_flag = ETH_TDES1_LS | ETH_TDES1_FS | ETH_TDES1_TCH; ++ if (dirty_to_tx >= lp->tx_irq_count) { ++ netif_stop_queue(ndev); ++ tx_flag |= ETH_TDES1_IC; ++ } ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ tx_flag |= ETH_TDES1_CIC_TUI | ETH_TDES1_CIC_HDR; ++ } ++#endif ++ lp->tx.rng_tx[entry].skb = skb; ++ lp->tx.rng_tx[entry].mapping = mapping; ++ lp->tx.desc_tx[entry].buffer1 = mapping; ++ lp->tx.desc_tx[entry].length = ETH_TDES1_TBS1x(skb->len) | tx_flag; ++ lp->tx.cur_tx++; ++ gkhw_dma_tx_poll(lp, entry); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ ndev->trans_start = jiffies; ++ dev_vdbg(&lp->ndev->dev, "TX Info: cur_tx[%d], dirty_tx[%d], " ++ "entry[%d], len[%d], data_len[%d], ip_summed[%d], " ++ "csum_start[%d], csum_offset[%d].\n", ++ lp->tx.cur_tx, lp->tx.dirty_tx, entry, skb->len, skb->data_len, ++ skb->ip_summed, skb->csum_start, skb->csum_offset); ++ ++GKETH_hard_start_xmit_exit: ++ return errorCode; ++} ++ ++static void GKETH_timeout(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ u32 irq_status; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ dev_info(&lp->ndev->dev, "OOM Info:...\n"); ++ spin_lock_irqsave(&lp->lock, flags); ++ irq_status = gk_eth_readl((unsigned int)(lp->regbase + ETH_DMA_STATUS_OFFSET)); ++ GKETH_interrupt_tx(lp, irq_status | GKETH_TXDMA_STATUS); ++ gkhw_dump(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ netif_wake_queue(ndev); ++} ++ ++static struct net_device_stats *GKETH_get_stats(struct net_device *ndev) ++{ ++ struct GKETH_info *lp = netdev_priv(ndev); ++ ++ return &lp->stats; ++} ++ ++static inline void GKETH_check_rdes0_status(struct GKETH_info *lp, ++ unsigned int status) ++{ ++ if (status & ETH_RDES0_DE) { ++ lp->stats.rx_frame_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Descriptor Error.\n"); ++ } ++ if (status & ETH_RDES0_SAF) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Source Address Filter Fail.\n"); ++ } ++ if (status & ETH_RDES0_LE) { ++ lp->stats.rx_length_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Length Error.\n"); ++ } ++ if (status & ETH_RDES0_OE) { ++ lp->stats.rx_over_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Overflow Error.\n"); ++ } ++ if (status & ETH_RDES0_VLAN) { ++ if (netif_msg_drv(lp)) ++ dev_info(&lp->ndev->dev, "RX Info: VLAN.\n"); ++ } ++ if (status & ETH_RDES0_IPC) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: IPC Checksum/Giant Frame.\n"); ++ } ++ if (status & ETH_RDES0_LC) { ++ lp->stats.collisions++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Late Collision.\n"); ++ } ++ if (status & ETH_RDES0_FT) { ++ if (netif_msg_rx_err(lp)) ++ dev_info(&lp->ndev->dev, ++ "RX Info: Ethernet-type frame.\n"); ++ } ++ if (status & ETH_RDES0_RWT) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Watchdog Timeout.\n"); ++ } ++ if (status & ETH_RDES0_RE) { ++ lp->stats.rx_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: Receive.\n"); ++ } ++ if (status & ETH_RDES0_DBE) { ++ if (gk_eth_tstbitsl((unsigned int)(lp->regbase + ETH_MAC_CFG_OFFSET), ++ ETH_MAC_CFG_PS)) { ++ lp->stats.rx_length_errors++; ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Dribble Bit.\n"); ++ } ++ } ++ if (status & ETH_RDES0_CE) { ++ lp->stats.rx_crc_errors++; ++ if (netif_msg_rx_err(lp)) ++ dev_err(&lp->ndev->dev, "RX Error: CRC.\n"); ++ } ++ if (status & ETH_RDES0_RX) { ++ if (netif_msg_drv(lp)) ++ dev_err(&lp->ndev->dev, ++ "RX Error: Rx MAC Address/Payload Checksum.\n"); ++ } ++} ++ ++static inline void GKETH_napi_rx(struct GKETH_info *lp, u32 status, u32 entry) ++{ ++ short pkt_len; ++ struct sk_buff *skb; ++ dma_addr_t mapping; ++ ++ pkt_len = ETH_RDES0_FL(status) - 4; ++ ++ if (unlikely(pkt_len > GKETH_RX_COPYBREAK)) { ++ dev_warn(&lp->ndev->dev, "Bogus packet size %d.\n", pkt_len); ++ pkt_len = GKETH_RX_COPYBREAK; ++ lp->stats.rx_length_errors++; ++ } ++ ++ skb = lp->rx.rng_rx[entry].skb; ++ mapping = lp->rx.rng_rx[entry].mapping; ++ if (likely(skb && mapping)) { ++ dma_unmap_single(&lp->ndev->dev, mapping, ++ lp->rx.rng_rx[entry].buf_size, DMA_FROM_DEVICE); ++ skb->len = 0; ++ skb_put(skb, pkt_len); ++ skb->protocol = eth_type_trans(skb, lp->ndev); ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ if ((status & ETH_RDES0_COE_MASK) == ETH_RDES0_COE_NOCHKERROR) { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ skb->ip_summed = CHECKSUM_NONE; ++ if (netif_msg_rx_err(lp)) { ++ dev_err(&lp->ndev->dev, ++ "RX Error: RDES0_COE[0x%x].\n", status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++ netif_receive_skb(skb); ++ lp->rx.rng_rx[entry].skb = NULL; ++ lp->rx.rng_rx[entry].mapping = 0; ++ lp->ndev->last_rx = jiffies; ++ lp->stats.rx_packets++; ++ lp->stats.rx_bytes += pkt_len; ++ } else { ++ if (netif_msg_drv(lp)) { ++ dev_err(&lp->ndev->dev, ++ "RX Error: %d skb[%p], map[0x%08X].\n", ++ entry, skb, mapping); ++ gkhw_dump(lp); ++ } ++ } ++} ++ ++int GKETH_napi(struct napi_struct *napi, int budget) ++{ ++ int rx_budget = budget; ++ struct GKETH_info *lp; ++ u32 entry; ++ u32 status; ++ unsigned long flags; ++ ++ lp = container_of(napi, struct GKETH_info, napi); ++ ++ if (unlikely(!netif_carrier_ok(lp->ndev))) ++ goto GKETH_poll_complete; ++ ++ while (rx_budget > 0) { ++ entry = lp->rx.cur_rx % lp->rx_count; ++ status = lp->rx.desc_rx[entry].status; ++ if (status & ETH_RDES0_OWN) ++ break; ++#if defined(GKETH_RDES0_ATOMIC_CHECK) ++ if (unlikely((status & (ETH_RDES0_FS | ETH_RDES0_LS)) != ++ (ETH_RDES0_FS | ETH_RDES0_LS))) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, "RX Error: Wrong FS/LS" ++ " cur_rx[%d] status 0x%08x.\n", ++ lp->rx.cur_rx, status); ++ gkhw_dump(lp); ++ } ++ break; ++ } ++#endif ++#if defined(GKETH_TDES0_ATOMIC_CHECK_ALL) ++ udelay(1); ++ if (unlikely(status != lp->rx.desc_rx[entry].status)) { ++ if (netif_msg_probe(lp)) { ++ dev_err(&lp->ndev->dev, "RX Error: Wrong status" ++ " 0x%08x vs 0x%08x.\n", ++ status, lp->rx.desc_rx[entry].status); ++ gkhw_dump(lp); ++ } ++ } ++#endif ++ if (likely((status & ETH_RDES0_ES) != ETH_RDES0_ES)) { ++ GKETH_napi_rx(lp, status, entry); ++ } else { ++ GKETH_check_rdes0_status(lp, status); ++ } ++ rx_budget--; ++ lp->rx.cur_rx++; ++ ++ if ((lp->rx.cur_rx - lp->rx.dirty_rx) > (lp->rx_count / 4)) ++ GKETH_rx_rngmng_refill(lp); ++ } ++ ++GKETH_poll_complete: ++ if (rx_budget > 0) { ++ GKETH_rx_rngmng_refill(lp); ++ spin_lock_irqsave(&lp->lock, flags); ++ napi_complete(&lp->napi); ++ gk_eth_setbitsl((unsigned int)(lp->regbase + ETH_DMA_INTEN_OFFSET), ++ GKETH_RXDMA_INTEN); ++ gkhw_dma_rx_start(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ } ++ ++ return (budget - rx_budget); ++} ++ ++static inline u32 gkhw_hashtable_crc(unsigned char *mac) ++{ ++ unsigned char tmpbuf[ETH_ALEN]; ++ int i; ++ u32 crc; ++ ++ for (i = 0; i < ETH_ALEN; i++) ++ tmpbuf[i] = bitrev8(mac[i]); ++ crc = crc32_be(~0, tmpbuf, ETH_ALEN); ++ ++ return (crc ^ ~0); ++} ++ ++static inline void gkhw_hashtable_get(struct net_device *ndev, u32 *hat) ++{ ++ struct netdev_hw_addr *ha; ++ unsigned int bitnr; ++#if 0 ++ unsigned char test1[] = {0x1F,0x52,0x41,0x9C,0xB6,0xAF}; ++ unsigned char test2[] = {0xA0,0x0A,0x98,0x00,0x00,0x45}; ++ dev_info(&ndev->dev, ++ "Test1: 0x%08X.\n", gkhw_hashtable_crc(test1)); ++ dev_info(&ndev->dev, ++ "Test2: 0x%08X.\n", gkhw_hashtable_crc(test2)); ++#endif ++ ++ hat[0] = hat[1] = 0; ++ netdev_for_each_mc_addr(ha, ndev) { ++ if (!(ha->addr[0] & 1)) ++ continue; ++ bitnr = gkhw_hashtable_crc(ha->addr); ++ bitnr >>= 26; ++ bitnr &= 0x3F; ++ hat[bitnr >> 5] |= 1 << (bitnr & 31); ++ } ++} ++ ++static int GKETH_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ struct GKETH_info *lp; ++ unsigned long flags; ++ struct sockaddr *saddr; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ saddr = (struct sockaddr *)(addr); ++ ++ //if (netif_running(ndev)) ++ // goto fail1; ++ ++ if (!is_valid_ether_addr(saddr->sa_data)) ++ goto fail2; ++ ++ dev_dbg(&lp->ndev->dev, "MAC address[%pM].\n", saddr->sa_data); ++ ++ memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len); ++ gkhw_set_hwaddr(lp, ndev->dev_addr); ++ gkhw_get_hwaddr(lp, ndev->dev_addr); ++ memcpy(lp->platform_info->mac_addr, ndev->dev_addr, GKETH_MAC_SIZE); ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ return 0; ++ ++fail2: ++ spin_unlock_irqrestore(&lp->lock, flags); ++ return -EADDRNOTAVAIL; ++} ++ ++static void GKETH_set_multicast_list(struct net_device *ndev) ++{ ++ struct GKETH_info *lp; ++ unsigned int mac_filter; ++ u32 hat[2]; ++ unsigned long flags; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ ++ mac_filter = gk_eth_readl((unsigned int)(lp->regbase + ++ ETH_MAC_FRAME_FILTER_OFFSET)); ++ hat[0] = 0; ++ hat[1] = 0; ++ ++ if (ndev->flags & IFF_PROMISC) { ++ mac_filter |= ETH_MAC_FRAME_FILTER_PR; ++ } else if (ndev->flags & (~IFF_PROMISC)) { ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PR; ++ } ++ ++ if (ndev->flags & IFF_ALLMULTI) { ++ hat[0] = 0xFFFFFFFF; ++ hat[1] = 0xFFFFFFFF; ++ mac_filter |= ETH_MAC_FRAME_FILTER_PM; ++ } else if (!netdev_mc_empty(ndev)) { ++ gkhw_hashtable_get(ndev, hat); ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PM; ++ mac_filter |= ETH_MAC_FRAME_FILTER_HMC; ++ } else if (ndev->flags & (~IFF_ALLMULTI)) { ++ mac_filter &= ~ETH_MAC_FRAME_FILTER_PM; ++ mac_filter |= ETH_MAC_FRAME_FILTER_HMC; ++ } ++ ++ if (netif_msg_hw(lp)) { ++ dev_info(&lp->ndev->dev, "MC Info: flags 0x%x.\n", ndev->flags); ++ dev_info(&lp->ndev->dev, "MC Info: mc_count 0x%x.\n", ++ netdev_mc_count(ndev)); ++ dev_info(&lp->ndev->dev, "MC Info: mac_filter 0x%x.\n", ++ mac_filter); ++ dev_info(&lp->ndev->dev, "MC Info: hat[0x%x:0x%x].\n", ++ hat[1], hat[0]); ++ } ++ ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_HASH_HI_OFFSET), hat[1]); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_HASH_LO_OFFSET), hat[0]); ++ gk_eth_writel((unsigned int)(lp->regbase + ETH_MAC_FRAME_FILTER_OFFSET), mac_filter); ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++} ++ ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void GKETH_poll_controller(struct net_device *ndev) ++{ ++ GKETH_interrupt(ndev->irq, ndev); ++} ++#endif ++ ++static int GKETH_get_settings(struct net_device *ndev, ++ struct ethtool_cmd *ecmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_ethtool_gset(lp->phydev, ecmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++static int GKETH_set_settings(struct net_device *ndev, ++ struct ethtool_cmd *ecmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_ethtool_sset(lp->phydev, ecmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++static int GKETH_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) ++{ ++ int errorCode = 0; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ if (!netif_running(ndev)) { ++ errorCode = -EINVAL; ++ goto GKETH_get_settings_exit; ++ } ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ spin_lock_irqsave(&lp->lock, flags); ++ if (lp->phydev) { ++ errorCode = phy_mii_ioctl(lp->phydev, ifr, cmd); ++ } else { ++ errorCode = -EINVAL; ++ } ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++GKETH_get_settings_exit: ++ return errorCode; ++} ++ ++/* ==========================================================================*/ ++static const struct net_device_ops GKETH_netdev_ops = { ++ .ndo_open = GKETH_open, ++ .ndo_stop = GKETH_stop, ++ .ndo_start_xmit = GKETH_hard_start_xmit, ++ .ndo_set_mac_address = GKETH_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_do_ioctl = GKETH_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_tx_timeout = GKETH_timeout, ++ .ndo_get_stats = GKETH_get_stats, ++ .ndo_set_rx_mode = GKETH_set_multicast_list, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = GKETH_poll_controller, ++#endif ++}; ++ ++static const struct ethtool_ops GKETH_ethtool_ops = { ++ .get_settings = GKETH_get_settings, ++ .set_settings = GKETH_set_settings, ++ .get_link = ethtool_op_get_link, ++}; ++ ++static int __devinit GKETH_drv_probe(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ struct gk_eth_platform_info *platform_info; ++ struct resource *reg_res; ++ struct resource *irq_res; ++ ++ void __iomem *eth_base; ++ int i; ++//#ifndef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ u8 uRegVal; ++//#else ++ u32 rmii; ++//#endif ++ ++ ++ platform_info = (struct gk_eth_platform_info *)pdev->dev.platform_data; ++ if (platform_info == NULL) { ++ dev_err(&pdev->dev, "Can't get platform_data!\n"); ++ errorCode = - EPERM; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ if (platform_info->is_enabled) { ++ if (!platform_info->is_enabled()) { ++ dev_err(&pdev->dev, "Not enabled, check HW config!\n"); ++ errorCode = -EPERM; ++ goto GKETH_drv_probe_exit; ++ } ++ } ++ ++ reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (reg_res == NULL) { ++ dev_err(&pdev->dev, "Get reg_res failed!\n"); ++ errorCode = -ENXIO; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (irq_res == NULL) { ++ dev_err(&pdev->dev, "Get irq_res failed!\n"); ++ errorCode = -ENXIO; ++ goto GKETH_drv_probe_exit; ++ } ++ ++ ndev = alloc_etherdev(sizeof(struct GKETH_info)); ++ if (ndev == NULL) { ++ dev_err(&pdev->dev, "alloc_etherdev fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_drv_probe_exit; ++ } ++#if 0 ++ /* get the memory region for the watchdog timer */ ++ size = resource_size(reg_res); ++ if (!request_mem_region(reg_res->start, size, pdev->name)) { ++ dev_err(&pdev->dev, "Failed to get eth's memory region\n"); ++ errorCode = -EBUSY; ++ goto GKETH_drv_probe_free_netdev; ++ } ++ ++ eth_base = ioremap(reg_res->start, size); ++ if (eth_base == NULL) { ++ dev_err(&pdev->dev, "failed to ioremap() region\n"); ++ errorCode = -EINVAL; ++ goto GKTH_drv_probe_free_res; ++ } ++#else ++ eth_base = (void __iomem *)reg_res->start; ++#endif ++ ++#define KE_DEBUG ++#ifdef KE_DEBUG ++ printk("[%s] eth_base = 0x%08x\n", __FUNCTION__, (u32)eth_base); ++#endif ++ ++ SET_NETDEV_DEV(ndev, &pdev->dev); ++ ndev->dev.dma_mask = pdev->dev.dma_mask; ++ ndev->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask; ++ ndev->irq = irq_res->start; ++#if defined(CONFIG_GK_ETH_SUPPORT_IPC) ++ ndev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; ++#endif ++ lp = netdev_priv(ndev); ++ spin_lock_init(&lp->lock); ++ lp->ndev = ndev; ++ lp->regbase = (unsigned char __iomem *)eth_base; ++ lp->platform_info = platform_info; ++ lp->rx_count = lp->platform_info->default_rx_ring_size; ++ if (lp->rx_count < GKETH_RX_RNG_MIN) ++ lp->rx_count = GKETH_RX_RNG_MIN; ++ lp->tx_count = lp->platform_info->default_tx_ring_size; ++ if (lp->tx_count < GKETH_TX_RNG_MIN) ++ lp->tx_count = GKETH_TX_RNG_MIN; ++ lp->tx_irq_count = (lp->tx_count * 2) / 3; ++ lp->msg_enable = netif_msg_init(msg_level, NETIF_MSG_DRV | NETIF_MSG_LINK); ++ ++ lp->new_bus.name = "goke MII Bus", ++ lp->new_bus.read = &gkhw_mdio_read; ++ lp->new_bus.write = &gkhw_mdio_write; ++ lp->new_bus.reset = &gkhw_mdio_reset; ++ //pdev->id = 0x3; ++ //lp->platform_info->mii_id = pdev->id; ++ printk("mii id = %d \n", pdev->id); ++ snprintf(lp->new_bus.id, MII_BUS_ID_SIZE, "%x", pdev->id); ++ lp->new_bus.priv = lp; ++ lp->new_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); ++ if (lp->new_bus.irq == NULL) { ++ dev_err(&pdev->dev, "alloc new_bus.irq fail.\n"); ++ errorCode = -ENOMEM; ++ goto GKETH_drv_probe_free_mii_gpio_irq; ++ } ++ for(i = 0; i < PHY_MAX_ADDR; ++i) ++ lp->new_bus.irq[i] = PHY_POLL; ++ lp->new_bus.parent = &pdev->dev; ++ lp->new_bus.state = MDIOBUS_ALLOCATED; ++//#ifndef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype == 0){ ++ lp->new_bus.phy_mask = 0xFFFFFFFE; ++ } ++//#endif ++ ++ //printk("mdiobus register ...\n"); ++ errorCode = mdiobus_register(&lp->new_bus); ++ if (errorCode) { ++ dev_err(&pdev->dev, "mdiobus_register fail%d.\n", errorCode); ++ goto GKETH_drv_probe_kfree_mdiobus; ++ } ++ //printk("ok\n"); ++//#ifdef CONFIG_SYSTEM_USE_EXTERN_ETHPHY ++ if(cmdline_phytype != 0) ++ { ++#if 0//ephy rmii mode ++ GH_EPHY_set_MII_RMII_rmii(0x1); ++ // RMII mode GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 used as 10/100M indicator ++ gk_set_phy_speed_led(GPIO_TYPE_INPUT_0); ++ ++ if(lp->new_bus.phy_used->phy_id == 0x02430c54) // IP101g ++ { ++ // LindengYu: I don't known why do not go into effect. ++ // change to page 3 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x03); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ rmii &= 0x3FFF; ++ rmii |= 0x4000; ++ // change to LED0 mode1, Link/Act mode ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10, rmii); ++ // restore to page 16 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x10); ++ } ++ else// if(lp->new_bus.phy_used->phy_id == 0x001CC815) // rtl820x ++ { ++ // change to rmii mode ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 25); ++ rmii |= (1<<10); ++ rmii &= ~(1<<11); ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 25, rmii); ++ } ++#else //ephy mii mode ++ GH_EPHY_set_MII_RMII_rmii(0x0); ++ // RMII mode GPIO_TYPE_OUTPUT_ENET_PHY_TXD_3 used as 10/100M indicator ++#if 0 ++ gk_set_phy_speed_led(GPIO_TYPE_INPUT_0); ++#endif ++// printk("cmdline_phytype0:%d \n",cmdline_phytype); ++ if(lp->new_bus.phy_used->phy_id == 0x02430c54) // IP101g ++ { ++ // LindengYu: I don't known why do not go into effect. ++ // change to page 3 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x03); ++ rmii = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10); ++ rmii &= 0x3FFF; ++ rmii |= 0x4000; ++ // change to LED0 mode1, Link/Act mode ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x10, rmii); ++ // restore to page 16 ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 20, 0x10); ++ } ++ else// if(lp->new_bus.phy_used->phy_id == 0x001CC815) // rtl820x ++ { ++ // change to rmii mode ++// printk("read 25 reg nuw bus 0x%x\n",&(lp->new_bus)); ++ rmii = gkhw_mdio_read(&(lp->new_bus), lp->new_bus.phy_used->addr, 25); ++// printk("cmdline_phytype1:%d\n",cmdline_phytype); ++ rmii &= ~(1<<10); ++ rmii &= ~(1<<11); ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 25, rmii); ++ } ++ ++#endif ++#if 0 ++ { ++ u16 reglist[24][2]= ++ { ++ {0x10, 0x00},{0x10, 0x01},{0x10, 0x02},{0x10, 0x03}, ++ {0x10, 0x04},{0x10, 0x05},{0x10, 0x06},{0x10, 0x07}, ++ {0x10, 0x08},{0x10, 0x10},{0x10, 0x11},{0x10, 0x12}, ++ {0x10, 0x14},{0x01, 0x11},{0x01, 0x12},{0x01, 0x17}, ++ {0x02, 0x12},{0x08, 0x11},{0x0B, 0x12},{0x12, 0x11}, ++ {0x03, 0x10},{0x04, 0x10},{0x05, 0x10},{0x11, 0x11}, ++ }; ++ // page 16 ++ u16 regdata; ++ u16 regpage=0x00; ++ u32 i; ++ printk("Page Addr Data\n"); ++ for(i=0;i<24;i++) ++ { ++ if(regpage != reglist[i][0]) ++ { ++ regpage = reglist[i][0]; ++ gkhw_mdio_write(&lp->new_bus, lp->new_bus.phy_used->addr, 0x14, regpage); ++ } ++ regdata = gkhw_mdio_read(&lp->new_bus, lp->new_bus.phy_used->addr, reglist[i][1]); ++ printk("%02d %02d 0x%04x\n",reglist[i][0] ,reglist[i][1] ,regdata); ++ } ++ } ++#endif ++ //EPHY POWER OFF ++ //printk("net probe ephy power off\n"); ++ GK_EPHY_POWER_OFF(); ++ } ++ else ++ { ++//#else ++ GH_EPHY_set_MII_RMII_rmii(0x0); ++ #if 0 ++ gk_eth_writel(0xF0022540, 0x00000000); ++ gk_eth_writel(0xF00220C8, 0x0000C400); // reg_test_out(debug_bus_out) ++ gk_eth_writel(0xF00220E0, 0x0000810A); // debug mode ++ gk_eth_writel(0xF0022588, 0x00000007); // DAC 100M clk gate for 10M TX ++ #else ++ gk_eth_writel(GK_VA_ETH_PHY + 0x0540, 0x00000000); ++ gk_eth_writel(GK_VA_ETH_PHY + 0x00C8, 0x0000C400); // reg_test_out(debug_bus_out) ++ gk_eth_writel(GK_VA_ETH_PHY + 0x00E0, 0x0000810A); // debug mode ++ gk_eth_writel(GK_VA_ETH_PHY + 0x0588, 0x00000007); // DAC 100M clk gate for 10M TX ++ #endif ++ MHal_EMAC_WritReg8(0x0033, 0xde, 0x59); ++ MHal_EMAC_WritReg8(0x0033, 0xf4, 0x21); ++ MHal_EMAC_WritReg8(0x0032, 0x72, 0x80); ++ MHal_EMAC_WritReg8(0x0033, 0xfc, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xb7, 0x07); ++ MHal_EMAC_WritReg8(0x0033, 0xcb, 0x11); ++ MHal_EMAC_WritReg8(0x0033, 0xcc, 0x80); ++ MHal_EMAC_WritReg8(0x0033, 0xcd, 0xd1); ++ MHal_EMAC_WritReg8(0x0033, 0xd4, 0x00); ++ MHal_EMAC_WritReg8(0x0033, 0xb9, 0x40); ++ MHal_EMAC_WritReg8(0x0033, 0xbb, 0x05); ++ MHal_EMAC_WritReg8(0x0033, 0xea, 0x46); ++ MHal_EMAC_WritReg8(0x0033, 0xa1, 0x00); ++ MHal_EMAC_WritReg8(0x0034, 0x3a, 0x03); ++ MHal_EMAC_WritReg8(0x0034, 0x3b, 0x00); ++ ++ //gain shift ++ MHal_EMAC_WritReg8(0x0033, 0xb4, 0x56); ++ ++ //det max ++ MHal_EMAC_WritReg8(0x0033, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(0x0033, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(0x0033, 0x77, 0x18); ++ ++ //snr k value ++ MHal_EMAC_WritReg8(0x0033, 0x43, 0x15); ++ ++ //100 gat ++ MHal_EMAC_WritReg8(0x0034, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(0x0034, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(0x0034, 0x39, 0x41); ++ ++ //10T waveform ++ uRegVal = MHal_EMAC_ReadReg8(0x0034, 0xe8); ++ uRegVal &= 0xf8; ++ uRegVal |= 0x06; ++ MHal_EMAC_WritReg8(0x0034, 0xe8, uRegVal); ++ MHal_EMAC_WritReg8(0x0032, 0x2b, 0x00); ++ ++ //analog ++ MHal_EMAC_WritReg8(0x0033, 0xd8, 0xb0); ++ MHal_EMAC_WritReg8(0x0033, 0xd9, 0x30); ++ ++ //disable EEE ++ uRegVal = MHal_EMAC_ReadReg8(0x0032, 0x2d); ++ uRegVal |= 0x40; ++ MHal_EMAC_WritReg8(0x0032, 0x2d, uRegVal); ++ ++ GH_EPHY_set_SPEED_ane(0x01); ++ } ++//#endif ++ ++ ether_setup(ndev); ++ ndev->netdev_ops = &GKETH_netdev_ops; ++ ndev->watchdog_timeo = lp->platform_info->watchdog_timeo; ++ netif_napi_add(ndev, &lp->napi, GKETH_napi, ++ lp->platform_info->napi_weight); ++ if (!is_valid_ether_addr(lp->platform_info->mac_addr)) ++ random_ether_addr(lp->platform_info->mac_addr); ++ memcpy(ndev->dev_addr, lp->platform_info->mac_addr, GKETH_MAC_SIZE); ++ ++ SET_ETHTOOL_OPS(ndev, &GKETH_ethtool_ops); ++ errorCode = register_netdev(ndev); ++ if (errorCode) { ++ dev_err(&pdev->dev, " register_netdev fail%d.\n", errorCode); ++ goto GKETH_drv_probe_netif_napi_del; ++ } ++ ++ platform_set_drvdata(pdev, ndev); ++ dev_notice(&pdev->dev, "MAC Address[%pM].\n", ndev->dev_addr); ++ ++ goto GKETH_drv_probe_exit; ++ ++GKETH_drv_probe_netif_napi_del: ++ netif_napi_del(&lp->napi); ++ mdiobus_unregister(&lp->new_bus); ++ ++GKETH_drv_probe_kfree_mdiobus: ++ kfree(lp->new_bus.irq); ++ ++GKETH_drv_probe_free_mii_gpio_irq: ++ //iounmap(eth_base); ++ ++//GKTH_drv_probe_free_res: ++ //release_mem_region(reg_res->start, size); ++ ++ ++//GKETH_drv_probe_free_netdev: ++ free_netdev(ndev); ++ ++GKETH_drv_probe_exit: ++ return errorCode; ++} ++ ++static int __devexit GKETH_drv_remove(struct platform_device *pdev) ++{ ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ unregister_netdev(ndev); ++ netif_napi_del(&lp->napi); ++ mdiobus_unregister(&lp->new_bus); ++ kfree(lp->new_bus.irq); ++ platform_set_drvdata(pdev, NULL); ++ free_netdev(ndev); ++ dev_notice(&pdev->dev, "Removed.\n"); ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int GKETH_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ if (!netif_running(ndev)) ++ goto GKETH_drv_suspend_exit; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ napi_disable(&lp->napi); ++ netif_device_detach(ndev); ++ disable_irq(ndev->irq); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ gkhw_disable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ } ++ ++GKETH_drv_suspend_exit: ++ dev_dbg(&pdev->dev, "%s exit with %d @ %d\n", ++ __func__, errorCode, state.event); ++ return errorCode; ++} ++ ++static int GKETH_drv_resume(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ struct net_device *ndev; ++ struct GKETH_info *lp; ++ unsigned long flags; ++ ++ ndev = platform_get_drvdata(pdev); ++ if (ndev) { ++ if (!netif_running(ndev)) ++ goto GKETH_drv_resume_exit; ++ ++ lp = (struct GKETH_info *)netdev_priv(ndev); ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ errorCode = gkhw_enable(lp); ++ gkhw_set_link_mode_speed(lp); ++ GKETH_rx_rngmng_init(lp); ++ GKETH_tx_rngmng_init(lp); ++ gkhw_set_dma_desc(lp); ++ gkhw_dma_rx_start(lp); ++ gkhw_dma_tx_start(lp); ++ gkhw_dma_int_enable(lp); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ if (errorCode) { ++ dev_err(&pdev->dev, "gkhw_enable.\n"); ++ } else { ++ enable_irq(ndev->irq); ++ netif_device_attach(ndev); ++ napi_enable(&lp->napi); ++ } ++ } ++ ++GKETH_drv_resume_exit: ++ dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, errorCode); ++ return errorCode; ++} ++#endif ++ ++static struct platform_driver GKETH_driver = { ++ .probe = GKETH_drv_probe, ++ .remove = __devexit_p(GKETH_drv_remove), ++#ifdef CONFIG_PM ++ .suspend = GKETH_drv_suspend, ++ .resume = GKETH_drv_resume, ++#endif ++ .driver = { ++ .name = "gk-eth", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init GKETH_init(void) ++{ ++ printk("%s\n", __FUNCTION__); ++ return platform_driver_register(&GKETH_driver); ++} ++ ++static void __exit GKETH_exit(void) ++{ ++ platform_driver_unregister(&GKETH_driver); ++} ++ ++module_init(GKETH_init); ++module_exit(GKETH_exit); ++ ++MODULE_DESCRIPTION("Goke GK Ethernet Driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c +index 8985cc62..1ebd058b 100644 +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -99,7 +99,7 @@ static struct class mdio_bus_class = { + */ + int mdiobus_register(struct mii_bus *bus) + { +- int i, err; ++ int i, j, err; + + if (NULL == bus || NULL == bus->name || + NULL == bus->read || +@@ -124,18 +124,32 @@ int mdiobus_register(struct mii_bus *bus) + + if (bus->reset) + bus->reset(bus); +- +- for (i = 0; i < PHY_MAX_ADDR; i++) { +- if ((bus->phy_mask & (1 << i)) == 0) { +- struct phy_device *phydev; +- +- phydev = mdiobus_scan(bus, i); +- if (IS_ERR(phydev)) { +- err = PTR_ERR(phydev); +- goto error; +- } +- } +- } ++ for(j=0;j<5;j++) ++ { ++ for (i = 0; i < PHY_MAX_ADDR; i++) { ++ if ((bus->phy_mask & (1 << i)) == 0) { ++ struct phy_device *phydev; ++ ++ phydev = mdiobus_scan(bus, i); ++ if (IS_ERR(phydev)) { ++ err = PTR_ERR(phydev); ++ goto error; ++ } ++ } ++ ++ } ++ for (i = 0; i < PHY_MAX_ADDR; i++) ++ { ++ if(bus->phy_used) ++ { ++ printk("%s: PHY[%d] whose id 0x%08x \n", __func__, j, bus->phy_used->phy_id); ++ goto find_phy; ++ } ++ ++ } ++ mdelay(100); ++ } ++find_phy: + + bus->state = MDIOBUS_REGISTERED; + pr_info("%s: probed\n", bus->name); +diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c +index e8c42d6a..896ca045 100644 +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -181,6 +181,7 @@ static struct phy_device* phy_device_create(struct mii_bus *bus, + + dev->state = PHY_DOWN; + ++ bus->phy_used = dev; + mutex_init(&dev->lock); + INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); + +diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile +index 98db7619..e7649432 100644 +--- a/drivers/net/wireless/Makefile ++++ b/drivers/net/wireless/Makefile +@@ -24,6 +24,8 @@ obj-$(CONFIG_B43LEGACY) += b43legacy/ + obj-$(CONFIG_ZD1211RW) += zd1211rw/ + obj-$(CONFIG_RTL8180) += rtl818x/ + obj-$(CONFIG_RTL8187) += rtl818x/ ++obj-$(CONFIG_RTL8189ES) += rtl818x/ ++obj-$(CONFIG_RTL8189EU) += rtl818x/ + obj-$(CONFIG_RTLWIFI) += rtlwifi/ + + # 16-bit wireless PCMCIA client drivers +@@ -61,3 +63,5 @@ obj-$(CONFIG_MWIFIEX) += mwifiex/ + + obj-$(CONFIG_BRCMFMAC) += brcm80211/ + obj-$(CONFIG_BRCMSMAC) += brcm80211/ ++#obj-$(CONFIG_RTL8189ES) += rtl8189es/ ++#obj-$(CONFIG_RTL8188EU) += rtl8189eu/ +diff --git a/drivers/net/wireless/rtl818x/Kconfig b/drivers/net/wireless/rtl818x/Kconfig +index 17d80fe5..7d6c6419 100644 +--- a/drivers/net/wireless/rtl818x/Kconfig ++++ b/drivers/net/wireless/rtl818x/Kconfig +@@ -85,4 +85,17 @@ config RTL8187_LEDS + bool + depends on RTL8187 && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = RTL8187) + default y ++ ++config RTL8189ES ++ tristate "Realtek 8189E SDIO WiFi" ++ #depends on USB ++ ---help--- ++ Help message of RTL8189ES ++ ++config RTL8189EU ++ tristate "Realtek 8189E USB WiFi" ++ depends on USB ++ ---help--- ++ Help message of RTL8189EU ++ + +diff --git a/drivers/net/wireless/rtl818x/Makefile b/drivers/net/wireless/rtl818x/Makefile +index 99756907..2c93804d 100644 +--- a/drivers/net/wireless/rtl818x/Makefile ++++ b/drivers/net/wireless/rtl818x/Makefile +@@ -1,2 +1,4 @@ + obj-$(CONFIG_RTL8180) += rtl8180/ + obj-$(CONFIG_RTL8187) += rtl8187/ ++obj-$(CONFIG_RTL8189ES) += rtl8189/ ++obj-$(CONFIG_RTL8189EU) += rtl8189/ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/Makefile b/drivers/net/wireless/rtl818x/rtl8189/Makefile +new file mode 100644 +index 00000000..a5aa51f5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/Makefile +@@ -0,0 +1,872 @@ ++EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS) ++EXTRA_CFLAGS += -O1 ++#EXTRA_CFLAGS += -O3 ++#EXTRA_CFLAGS += -Wall ++#EXTRA_CFLAGS += -Wextra ++#EXTRA_CFLAGS += -Werror ++#EXTRA_CFLAGS += -pedantic ++#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes ++ ++EXTRA_CFLAGS += -Wno-unused-variable ++EXTRA_CFLAGS += -Wno-unused-value ++EXTRA_CFLAGS += -Wno-unused-label ++EXTRA_CFLAGS += -Wno-unused-parameter ++EXTRA_CFLAGS += -Wno-unused-function ++EXTRA_CFLAGS += -Wno-unused ++ ++EXTRA_CFLAGS += -Wno-uninitialized ++ ++EXTRA_CFLAGS += -I$(src)/include ++ ++CONFIG_AUTOCFG_CP = n ++ ++ifeq ($(CONFIG_RTL8189ES), y) ++CONFIG_USB_HCI = n ++CONFIG_SDIO_HCI = y ++else ++CONFIG_USB_HCI = y ++CONFIG_SDIO_HCI = n ++endif ++ ++CONFIG_RTL8192C = n ++CONFIG_RTL8192D = n ++CONFIG_RTL8723A = n ++CONFIG_RTL8188E = y ++ ++#CONFIG_USB_HCI = n ++CONFIG_PCI_HCI = n ++#CONFIG_SDIO_HCI = y ++CONFIG_GSPI_HCI = n ++ ++CONFIG_MP_INCLUDED = y ++CONFIG_POWER_SAVING = y ++CONFIG_USB_AUTOSUSPEND = n ++CONFIG_HW_PWRP_DETECTION = n ++CONFIG_WIFI_TEST = n ++CONFIG_BT_COEXIST = n ++CONFIG_RTL8192CU_REDEFINE_1X1 = n ++CONFIG_INTEL_WIDI = n ++CONFIG_WAPI_SUPPORT = n ++CONFIG_EFUSE_CONFIG_FILE = n ++CONFIG_EXT_CLK = n ++CONFIG_FTP_PROTECT = n ++CONFIG_WOWLAN = n ++CONFIG_GPIO_WAKEUP = n ++CONFIG_ODM_ADAPTIVITY = n ++CONFIG_MMC_PM_KEEP_POWER = n ++ ++CONFIG_PLATFORM_I386_PC = n ++CONFIG_PLATFORM_ANDROID_X86 = n ++CONFIG_PLATFORM_JB_X86 = n ++CONFIG_PLATFORM_ARM_S3C2K4 = n ++CONFIG_PLATFORM_ARM_PXA2XX = n ++CONFIG_PLATFORM_ARM_S3C6K4 = n ++CONFIG_PLATFORM_MIPS_RMI = n ++CONFIG_PLATFORM_RTD2880B = n ++CONFIG_PLATFORM_MIPS_AR9132 = n ++CONFIG_PLATFORM_RTK_DMP = n ++CONFIG_PLATFORM_MIPS_PLM = n ++CONFIG_PLATFORM_MSTAR389 = n ++CONFIG_PLATFORM_MT53XX = n ++CONFIG_PLATFORM_ARM_MX51_241H = n ++CONFIG_PLATFORM_ACTIONS_ATJ227X = n ++CONFIG_PLATFORM_TEGRA3_CARDHU = n ++CONFIG_PLATFORM_TEGRA4_DALMORE = n ++CONFIG_PLATFORM_ARM_TCC8900 = n ++CONFIG_PLATFORM_ARM_TCC8920 = n ++CONFIG_PLATFORM_ARM_TCC8920_JB42 = n ++CONFIG_PLATFORM_ARM_RK2818 = n ++CONFIG_PLATFORM_ARM_URBETTER = n ++CONFIG_PLATFORM_ARM_TI_PANDA = n ++CONFIG_PLATFORM_MIPS_JZ4760 = n ++CONFIG_PLATFORM_DMP_PHILIPS = n ++CONFIG_PLATFORM_TI_DM365 = n ++CONFIG_PLATFORM_MSTAR_TITANIA12 = n ++CONFIG_PLATFORM_MSTAR = n ++CONFIG_PLATFORM_SZEBOOK = n ++CONFIG_PLATFORM_ARM_SUNxI = n ++CONFIG_PLATFORM_ARM_SUN6I = n ++CONFIG_PLATFORM_ARM_SUN7I = n ++CONFIG_PLATFORM_ACTIONS_ATM702X = n ++CONFIG_PLATFORM_MN10300 = n ++CONFIG_PLATFORM_ACTIONS_ATV5201 = n ++CONFIG_PLATFORM_GOKE_IPC = y ++ ++CONFIG_DRVEXT_MODULE = n ++ ++export TopDIR ?= $(shell pwd) ++ ++ ++OUTSRC_FILES := hal/OUTSRC/odm_debug.o \ ++ hal/OUTSRC/odm_interface.o\ ++ hal/OUTSRC/odm_HWConfig.o\ ++ hal/OUTSRC/odm.o\ ++ hal/OUTSRC/HalPhyRf.o ++ ++ifeq ($(CONFIG_RTL8192C), y) ++RTL871X = rtl8192c ++ ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8192cu ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192CUFWImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192CUPHYImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192CUMACImg_CE.o ++endif ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8192ce ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192CEFWImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192CEPHYImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192CEMACImg_CE.o ++endif ++ ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/odm_RTL8192C.o\ ++ hal/OUTSRC/$(RTL871X)/HalDMOutSrc8192C_CE.o ++ ++CHIP_FILES := \ ++ hal/$(RTL871X)/$(RTL871X)_sreset.o \ ++ hal/$(RTL871X)/$(RTL871X)_xmit.o ++CHIP_FILES += $(OUTSRC_FILES) ++ ++endif ++ ++ifeq ($(CONFIG_RTL8192D), y) ++RTL871X = rtl8192d ++ ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8192du ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192DUFWImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192DUPHYImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192DUMACImg_CE.o ++endif ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8192de ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192DEFWImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192DEPHYImg_CE.o \ ++ hal/OUTSRC/$(RTL871X)/Hal8192DEMACImg_CE.o ++endif ++ ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/odm_RTL8192D.o\ ++ hal/OUTSRC/$(RTL871X)/HalDMOutSrc8192D_CE.o ++CHIP_FILES := \ ++ hal/$(RTL871X)/$(RTL871X)_xmit.o ++CHIP_FILES += $(OUTSRC_FILES) ++endif ++ ++ifeq ($(CONFIG_RTL8723A), y) ++ ++RTL871X = rtl8723a ++ ++HAL_COMM_FILES := hal/$(RTL871X)/$(RTL871X)_xmit.o \ ++ hal/$(RTL871X)/$(RTL871X)_sreset.o ++ ++ifeq ($(CONFIG_GSPI_HCI), y) ++MODULE_NAME = 8723as ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723SHWImg_CE.o ++endif ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++MODULE_NAME = 8723as ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723SHWImg_CE.o ++endif ++ ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8723au ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723UHWImg_CE.o ++endif ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8723ae ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723EHWImg_CE.o ++endif ++ ++#hal/OUTSRC/$(RTL871X)/HalHWImg8723A_FW.o ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8723A_BB.o\ ++ hal/OUTSRC/$(RTL871X)/HalHWImg8723A_MAC.o\ ++ hal/OUTSRC/$(RTL871X)/HalHWImg8723A_RF.o\ ++ hal/OUTSRC/$(RTL871X)/odm_RegConfig8723A.o ++ ++OUTSRC_FILES += hal/OUTSRC/rtl8192c/HalDMOutSrc8192C_CE.o ++clean_more ?= ++clean_more += clean_odm-8192c ++ ++PWRSEQ_FILES := hal/HalPwrSeqCmd.o \ ++ hal/$(RTL871X)/Hal8723PwrSeq.o ++ ++CHIP_FILES += $(HAL_COMM_FILES) $(OUTSRC_FILES) $(PWRSEQ_FILES) ++ ++ifeq ($(CONFIG_BT_COEXIST), y) ++CHIP_FILES += hal/$(RTL871X)/rtl8723a_bt-coexist.o ++endif ++ ++endif ++ ++ifeq ($(CONFIG_RTL8188E), y) ++ ++RTL871X = rtl8188e ++HAL_COMM_FILES := hal/$(RTL871X)/$(RTL871X)_xmit.o\ ++ hal/$(RTL871X)/$(RTL871X)_sreset.o ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++MODULE_NAME = 8189es ++endif ++ ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8188eu ++endif ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8188ee ++endif ++ ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8188E_MAC.o\ ++ hal/OUTSRC/$(RTL871X)/HalHWImg8188E_BB.o\ ++ hal/OUTSRC/$(RTL871X)/HalHWImg8188E_RF.o\ ++ hal/OUTSRC/$(RTL871X)/Hal8188EFWImg_CE.o\ ++ hal/OUTSRC/$(RTL871X)/HalPhyRf_8188e.o\ ++ hal/OUTSRC/$(RTL871X)/odm_RegConfig8188E.o\ ++ hal/OUTSRC/$(RTL871X)/Hal8188ERateAdaptive.o\ ++ hal/OUTSRC/$(RTL871X)/odm_RTL8188E.o ++ ++ifeq ($(CONFIG_RTL8188E), y) ++ifeq ($(CONFIG_WOWLAN), y) ++OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o ++endif ++endif ++ ++PWRSEQ_FILES := hal/HalPwrSeqCmd.o \ ++ hal/$(RTL871X)/Hal8188EPwrSeq.o ++ ++CHIP_FILES += $(HAL_COMM_FILES) $(OUTSRC_FILES) $(PWRSEQ_FILES) ++ ++endif ++ ++ ++ifeq ($(CONFIG_GSPI_HCI), y) ++HCI_NAME = gspi ++endif ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++HCI_NAME = sdio ++endif ++ ++ifeq ($(CONFIG_USB_HCI), y) ++HCI_NAME = usb ++endif ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++HCI_NAME = pci ++endif ++ ++ ++_OS_INTFS_FILES := os_dep/osdep_service.o \ ++ os_dep/linux/os_intfs.o \ ++ os_dep/linux/$(HCI_NAME)_intf.o \ ++ os_dep/linux/$(HCI_NAME)_ops_linux.o \ ++ os_dep/linux/ioctl_linux.o \ ++ os_dep/linux/xmit_linux.o \ ++ os_dep/linux/mlme_linux.o \ ++ os_dep/linux/recv_linux.o \ ++ os_dep/linux/ioctl_cfg80211.o \ ++ os_dep/linux/rtw_android.o ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o ++_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o ++endif ++ ++ifeq ($(CONFIG_GSPI_HCI), y) ++_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o ++_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o ++endif ++ ++_HAL_INTFS_FILES := hal/hal_intf.o \ ++ hal/hal_com.o \ ++ hal/$(RTL871X)/$(RTL871X)_hal_init.o \ ++ hal/$(RTL871X)/$(RTL871X)_phycfg.o \ ++ hal/$(RTL871X)/$(RTL871X)_rf6052.o \ ++ hal/$(RTL871X)/$(RTL871X)_dm.o \ ++ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ ++ hal/$(RTL871X)/$(RTL871X)_cmd.o \ ++ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ ++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ ++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ ++ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o ++else ++ifeq ($(CONFIG_GSPI_HCI), y) ++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o ++else ++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o ++endif ++endif ++ ++ifeq ($(CONFIG_MP_INCLUDED), y) ++_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_mp.o ++endif ++ ++_HAL_INTFS_FILES += $(CHIP_FILES) ++ ++ ++ifeq ($(CONFIG_AUTOCFG_CP), y) ++CURR_DIR = $(shell pwd)/drivers/net/wireless/rtl818x/rtl8189 ++$(shell cp $(CURR_DIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(CURR_DIR)/include/autoconf.h) ++#ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy) ++#$(shell cp $(CURR_DIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(CURR_DIR)/include/autoconf.h) ++#else ++#$(shell cp $(CURR_DIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(CURR_DIR)/include/autoconf.h) ++#endif ++endif ++ ++ ++ifeq ($(CONFIG_USB_HCI), y) ++ifeq ($(CONFIG_USB_AUTOSUSPEND), y) ++EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND ++endif ++endif ++ ++ifeq ($(CONFIG_MP_INCLUDED), y) ++EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED ++endif ++ ++ifeq ($(CONFIG_POWER_SAVING), y) ++EXTRA_CFLAGS += -DCONFIG_POWER_SAVING ++endif ++ ++ifeq ($(CONFIG_HW_PWRP_DETECTION), y) ++EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION ++endif ++ ++ifeq ($(CONFIG_WIFI_TEST), y) ++EXTRA_CFLAGS += -DCONFIG_WIFI_TEST ++endif ++ ++ifeq ($(CONFIG_BT_COEXIST), y) ++EXTRA_CFLAGS += -DCONFIG_BT_COEXIST ++endif ++ ++ifeq ($(CONFIG_RTL8192CU_REDEFINE_1X1), y) ++EXTRA_CFLAGS += -DRTL8192C_RECONFIG_TO_1T1R ++endif ++ ++ifeq ($(CONFIG_INTEL_WIDI), y) ++EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI ++endif ++ ++ifeq ($(CONFIG_WAPI_SUPPORT), y) ++EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT ++endif ++ ++ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y) ++EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE ++endif ++ ++ifeq ($(CONFIG_EXT_CLK), y) ++EXTRA_CFLAGS += -DCONFIG_EXT_CLK ++endif ++ ++ifeq ($(CONFIG_FTP_PROTECT), y) ++EXTRA_CFLAGS += -DCONFIG_FTP_PROTECT ++endif ++ ++ifeq ($(CONFIG_ODM_ADAPTIVITY), y) ++EXTRA_CFLAGS += -DCONFIG_ODM_ADAPTIVITY ++endif ++ ++ifeq ($(CONFIG_MMC_PM_KEEP_POWER), y) ++EXTRA_CFLAGS += -DCONFIG_MMC_PM_KEEP_POWER ++endif ++ ++ifeq ($(CONFIG_RTL8188E), y) ++ifeq ($(CONFIG_WOWLAN), y) ++EXTRA_CFLAGS += -DCONFIG_WOWLAN ++EXTRA_CFLAGS += -DCONFIG_MMC_PM_KEEP_POWER ++endif ++ifeq ($(CONFIG_GPIO_WAKEUP), y) ++EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP ++endif ++endif ++ ++ifeq ($(CONFIG_RTL8188E), y) ++ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y) ++EXTRA_CFLAGS += -DCONFIG_RF_GAIN_OFFSET ++endif ++endif ++ ++ifeq ($(CONFIG_PLATFORM_I386_PC), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ++ARCH ?= $(SUBARCH) ++CROSS_COMPILE ?= ++KVER := $(shell uname -r) ++KSRC := /lib/modules/$(KVER)/build ++MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ ++INSTALL_PREFIX := ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X ++#ARCH := arm ++ARCH := $(R_ARCH) ++#CROSS_COMPILE := arm-none-linux-gnueabi- ++CROSS_COMPILE := $(R_CROSS_COMPILE) ++KVER:= 3.4.0 ++#KSRC := ../../../../build/out/kernel ++KSRC := $(KERNEL_BUILD_PATH) ++MODULE_NAME :=wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TI_AM3517), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE ++CROSS_COMPILE := arm-eabi- ++KSRC := $(shell pwd)/../../../Android/kernel ++ARCH := arm ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12 ++ARCH:=mips ++CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu- ++KVER:= 2.6.28.9 ++KSRC:= /usr/src/Mstar_kernel/2.6.28.9/ ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MSTAR), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR ++ARCH:=arm ++CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi- ++KVER:= 3.1.10 ++KSRC:= /usr/src/Mstar_kernel/3.1.10/ ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ++ARCH := $(SUBARCH) ++CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu- ++KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel ++MODULE_NAME :=wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_JB_X86), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS ++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ++ARCH := $(SUBARCH) ++CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android- ++KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/ ++MODULE_NAME :=wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-none-linux-gnueabi- ++KVER := 2.6.34.1 ++KSRC ?= /usr/src/linux-2.6.34.1 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-linux- ++KVER := 2.6.24.7_$(ARCH) ++KSRC := /usr/src/kernels/linux-$(KVER) ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-none-linux-gnueabi- ++KVER := 2.6.34.1 ++KSRC ?= /usr/src/linux-2.6.34.1 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_RTD2880B), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B ++ARCH:= ++CROSS_COMPILE:= ++KVER:= ++KSRC:= ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH:=mips ++CROSS_COMPILE:=mipsisa32r2-uclibc- ++KVER:= ++KSRC:= /root/work/kernel_realtek ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ++ARCH:=mips ++CROSS_COMPILE:=mipsisa32r2-uclibc- ++KVER:= ++KSRC:= /root/work/kernel_realtek ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MSTAR389), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389 ++ARCH:=mips ++CROSS_COMPILE:= mips-linux-gnu- ++KVER:= 2.6.28.10 ++KSRC:= /home/mstar/mstar_linux/2.6.28.9/ ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ++ARCH := mips ++CROSS_COMPILE := mips-openwrt-linux- ++KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM ++ARCH := mips ++#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux- ++CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux- ++KSRC ?=/usr/local/Jupiter/linux-2.6.12 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_RTK_DMP), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM ++ARCH:=mips ++CROSS_COMPILE:=mipsel-linux- ++KVER:= ++KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MT53XX), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX ++ARCH:= arm ++CROSS_COMPILE:= arm11_mtk_le- ++KVER:= 2.6.27 ++KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM ++ARCH := arm ++CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi- ++KVER := 2.6.31 ++KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X ++ARCH := mips ++CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu- ++KVER := 2.6.27 ++KSRC := /home/cnsd4/project/actions/linux-2.6.27.28 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TI_DM365), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365 ++ARCH := arm ++CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le- ++KVER := 2.6.18 ++KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- ++KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- ++KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE ++ifeq ($(CONFIG_SDIO_HCI), y) ++EXTRA_CFLAGS += -DCONFIG_DETECT_CPWM_BY_POLLING -DCONFIG_DETECT_C2H_BY_POLLING ++endif ++ARCH := arm ++CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi- ++KSRC := /usr/src/release_fae_version/kernel25_A7_281x ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH := arm ++CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi- ++KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH := arm ++#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104 ++CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /media/DATA-1/android-4.0/panda_kernel/omap ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH ?= mips ++CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu- ++KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel ++endif ++ ++ifeq ($(CONFIG_PLATFORM_SZEBOOK), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ++ARCH:=arm ++CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi- ++KVER:= 2.6.31.6 ++KSRC:= ../code/linux-2.6.31.6-2020/ ++endif ++ ++#Add setting for MN10300 ++ifeq ($(CONFIG_PLATFORM_MN10300), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300 ++ARCH := mn10300 ++CROSS_COMPILE := mn10300-linux- ++KVER := 2.6.32.2 ++KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2 ++INSTALL_PREFIX := ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ARM_SUNxI ++ifeq ($(CONFIG_USB_HCI), y) ++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX ++endif ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DDCONFIG_P2P_IPS ++# default setting for A10-EVB mmc0 ++ifeq ($(CONFIG_SDIO_HCI), y) ++#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13 ++endif ++ARCH := arm ++#CROSS_COMPILE := arm-none-linux-gnueabi- ++CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi- ++KVER := 3.0.8 ++#KSRC:= ../lichee/linux-3.0/ ++KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I ++ifeq ($(CONFIG_USB_HCI), y) ++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX ++endif ++# default setting for A31-EVB mmc0 ++ifeq ($(CONFIG_SDIO_HCI), y) ++EXTRA_CFLAGS += -DCONFIG_A31_EVB ++endif ++ ++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION ++ARCH := arm ++CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi- ++KVER := 3.3.0 ++#KSRC:= ../lichee/linux-3.3/ ++KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3 ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME := 8188eu_sw ++endif ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I ++ifeq ($(CONFIG_USB_HCI), y) ++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX ++endif ++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT ++# default setting for Android 4.1, 4.2 ++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ++EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION ++ARCH := arm ++# Cross compile setting for Android 4.2 SDK ++#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/sugar/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- ++#KVER := 3.3.0 ++#KSRC :=/home/android_sdk/Allwinner/a20/sugar/lichee/linux-3.3 ++# Cross compile setting for Android 4.3 SDK ++CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- ++KVER := 3.4.39 ++KSRC :=/home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4 ++endif ++ ++ ++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201 ++ARCH := mips ++CROSS_COMPILE := mipsel-linux-gnu- ++KVER := $(KERNEL_VER) ++KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER) ++endif ++ ++ ++ifeq ($(CONFIG_PLATFORM_GOKE_IPC), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_GOKE_IPC ++endif ++ ++ifneq ($(USER_MODULE_NAME),) ++MODULE_NAME := $(USER_MODULE_NAME) ++endif ++ ++ifneq ($(KERNELRELEASE),) ++ ++rtk_core := core/rtw_cmd.o \ ++ core/rtw_security.o \ ++ core/rtw_debug.o \ ++ core/rtw_io.o \ ++ core/rtw_ioctl_query.o \ ++ core/rtw_ioctl_set.o \ ++ core/rtw_ieee80211.o \ ++ core/rtw_mlme.o \ ++ core/rtw_mlme_ext.o \ ++ core/rtw_wlan_util.o \ ++ core/rtw_pwrctrl.o \ ++ core/rtw_rf.o \ ++ core/rtw_recv.o \ ++ core/rtw_sta_mgt.o \ ++ core/rtw_ap.o \ ++ core/rtw_xmit.o \ ++ core/rtw_p2p.o \ ++ core/rtw_tdls.o \ ++ core/rtw_br_ext.o \ ++ core/rtw_iol.o \ ++ core/rtw_led.o \ ++ core/rtw_sreset.o \ ++ core/rtw_odm.o ++ ++$(MODULE_NAME)-y += $(rtk_core) ++ ++$(MODULE_NAME)-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o ++ ++$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \ ++ core/rtw_wapi_sms4.o ++ ++$(MODULE_NAME)-y += core/efuse/rtw_efuse.o ++ ++$(MODULE_NAME)-y += $(_HAL_INTFS_FILES) ++ ++$(MODULE_NAME)-y += $(_OS_INTFS_FILES) ++ ++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o \ ++ core/rtw_mp_ioctl.o ++ifeq ($(CONFIG_RTL8723A), y) ++ ++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o ++endif ++ ++ifeq ($(CONFIG_RTL8189ES), y) ++obj-$(CONFIG_RTL8189ES) := $(MODULE_NAME).o ++else ++obj-$(CONFIG_RTL8189EU) := $(MODULE_NAME).o ++endif ++ ++else ++ ++ifeq ($(CONFIG_RTL8189EU), y) ++export CONFIG_RTL8189EU = m ++else ++export CONFIG_RTL8189ES = m ++endif ++ ++ ++all: modules ++ ++modules: ++ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules ++ ++strip: ++ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded ++ ++install: ++ install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR) ++ /sbin/depmod -a ${KVER} ++ ++uninstall: ++ rm -f $(MODDESTDIR)/$(MODULE_NAME).ko ++ /sbin/depmod -a ${KVER} ++ ++config_r: ++ @echo "make config" ++ /bin/bash script/Configure script/config.in ++ ++.PHONY: modules clean clean_odm-8192c ++ ++clean_odm-8192c: ++ cd hal/OUTSRC/rtl8192c ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ ++clean: $(clean_more) ++ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~ ++ rm -fr .tmp_versions ++ rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order ++ cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/$(RTL871X)/$(HCI_NAME) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/OUTSRC/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/OUTSRC/ ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/clean b/drivers/net/wireless/rtl818x/rtl8189/clean +new file mode 100644 +index 00000000..87664218 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/clean +@@ -0,0 +1,5 @@ ++#!/bin/bash ++rmmod 8192cu ++rmmod 8192ce ++rmmod 8192du ++rmmod 8192de +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/efuse/rtw_efuse.c b/drivers/net/wireless/rtl818x/rtl8189/core/efuse/rtw_efuse.c +new file mode 100644 +index 00000000..d7307b48 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/efuse/rtw_efuse.c +@@ -0,0 +1,1283 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_EFUSE_C_ ++ ++#include ++#include ++#include ++ ++#include ++ ++ ++ ++/*------------------------Define local variable------------------------------*/ ++u8 fakeEfuseBank=0; ++u32 fakeEfuseUsedBytes=0; ++u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]={0}; ++u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]={0}; ++u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]={0}; ++ ++u32 BTEfuseUsedBytes=0; ++u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++ ++u32 fakeBTEfuseUsedBytes=0; ++u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++/*------------------------Define local variable------------------------------*/ ++ ++//------------------------------------------------------------------------------ ++#define REG_EFUSE_CTRL 0x0030 ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++//------------------------------------------------------------------------------ ++ ++BOOLEAN ++Efuse_Read1ByteFromFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u8 *Value ); ++BOOLEAN ++Efuse_Read1ByteFromFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u8 *Value ) ++{ ++ if(Offset >= EFUSE_MAX_HW_SIZE) ++ { ++ return _FALSE; ++ } ++ //DbgPrint("Read fake content, offset = %d\n", Offset); ++ if(fakeEfuseBank == 0) ++ *Value = fakeEfuseContent[Offset]; ++ else ++ *Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset]; ++ return _TRUE; ++} ++ ++BOOLEAN ++Efuse_Write1ByteToFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value ); ++BOOLEAN ++Efuse_Write1ByteToFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value ) ++{ ++ if(Offset >= EFUSE_MAX_HW_SIZE) ++ { ++ return _FALSE; ++ } ++ if(fakeEfuseBank == 0) ++ fakeEfuseContent[Offset] = Value; ++ else ++ { ++ fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value; ++ } ++ return _TRUE; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: Efuse_PowerSwitch ++ * ++ * Overview: When we want to enable write operation, we should change to ++ * pwr on state. When we stop write, we should switch to 500k mode ++ * and disable LDO 2.5V. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/17/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++Efuse_PowerSwitch( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_GetCurrentSize ++ * ++ * Overview: Get current efuse size!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/16/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++u16 ++Efuse_GetCurrentSize( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ ++ return ret; ++} ++ ++/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ ++u8 ++Efuse_CalculateWordCnts(IN u8 word_en) ++{ ++ u8 word_cnts = 0; ++ if(!(word_en & BIT(0))) word_cnts++; // 0 : write enable ++ if(!(word_en & BIT(1))) word_cnts++; ++ if(!(word_en & BIT(2))) word_cnts++; ++ if(!(word_en & BIT(3))) word_cnts++; ++ return word_cnts; ++} ++ ++// ++// Description: ++// Execute E-Fuse read byte operation. ++// Refered from SD1 Richard. ++// ++// Assumption: ++// 1. Boot from E-Fuse and successfully auto-load. ++// 2. PASSIVE_LEVEL (USB interface) ++// ++// Created by Roger, 2008.10.21. ++// ++VOID ++ReadEFuseByte( ++ PADAPTER Adapter, ++ u16 _offset, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest) ++{ ++ u32 value32; ++ u8 readbyte; ++ u16 retry; ++ //u32 start=rtw_get_current_time(); ++ ++ if(bPseudoTest) ++ { ++ Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); ++ return; ++ } ++ ++ //Write Address ++ rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff)); ++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+2); ++ rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); ++ ++ //Write bit 32 0 ++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+3); ++ rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f)); ++ ++ //Check bit 32 read-ready ++ retry = 0; ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10)) ++ while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000)) ++ { ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ retry++; ++ } ++ ++ // 20100205 Joseph: Add delay suggested by SD1 Victor. ++ // This fix the problem that Efuse read error in high temperature condition. ++ // Designer says that there shall be some delay after ready bit is set, or the ++ // result will always stay on last data we read. ++ rtw_udelay_os(50); ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ ++ *pbuf = (u8)(value32 & 0xff); ++ //DBG_871X("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); ++ ++} ++ ++ ++// ++// Description: ++// 1. Execute E-Fuse read byte operation according as map offset and ++// save to E-Fuse table. ++// 2. Refered from SD1 Richard. ++// ++// Assumption: ++// 1. Boot from E-Fuse and successfully auto-load. ++// 2. PASSIVE_LEVEL (USB interface) ++// ++// Created by Roger, 2008.10.21. ++// ++// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description. ++// 2. Add efuse utilization collect. ++// 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1 ++// write addr must be after sec5. ++// ++ ++VOID ++efuse_ReadEFuse( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ); ++VOID ++efuse_ReadEFuse( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); ++} ++ ++VOID ++EFUSE_GetEfuseDefinition( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u8 type, ++ OUT void *pOut, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_Read1Byte ++ * ++ * Overview: Copy from WMAC fot EFUSE read 1 byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/23/2008 MHC Copy from WMAC. ++ * ++ *---------------------------------------------------------------------------*/ ++u8 ++EFUSE_Read1Byte( ++ IN PADAPTER Adapter, ++ IN u16 Address) ++{ ++ u8 data; ++ u8 Bytetemp = {0x00}; ++ u8 temp = {0x00}; ++ u32 k=0; ++ u16 contentLen=0; ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); ++ ++ if (Address < contentLen) //E-fuse 512Byte ++ { ++ //Write E-fuse Register address bit0~7 ++ temp = Address & 0xFF; ++ rtw_write8(Adapter, EFUSE_CTRL+1, temp); ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); ++ //Write E-fuse Register address bit8~9 ++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); ++ rtw_write8(Adapter, EFUSE_CTRL+2, temp); ++ ++ //Write 0x30[31]=0 ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ temp = Bytetemp & 0x7F; ++ rtw_write8(Adapter, EFUSE_CTRL+3, temp); ++ ++ //Wait Write-ready (0x30[31]=1) ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ while(!(Bytetemp & 0x80)) ++ { ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ k++; ++ if(k==1000) ++ { ++ k=0; ++ break; ++ } ++ } ++ data=rtw_read8(Adapter, EFUSE_CTRL); ++ return data; ++ } ++ else ++ return 0xFF; ++ ++}/* EFUSE_Read1Byte */ ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_Write1Byte ++ * ++ * Overview: Copy from WMAC fot EFUSE write 1 byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/23/2008 MHC Copy from WMAC. ++ * ++ *---------------------------------------------------------------------------*/ ++ ++void ++EFUSE_Write1Byte( ++ IN PADAPTER Adapter, ++ IN u16 Address, ++ IN u8 Value); ++void ++EFUSE_Write1Byte( ++ IN PADAPTER Adapter, ++ IN u16 Address, ++ IN u8 Value) ++{ ++ u8 Bytetemp = {0x00}; ++ u8 temp = {0x00}; ++ u32 k=0; ++ u16 contentLen=0; ++ ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value)); ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); ++ ++ if( Address < contentLen) //E-fuse 512Byte ++ { ++ rtw_write8(Adapter, EFUSE_CTRL, Value); ++ ++ //Write E-fuse Register address bit0~7 ++ temp = Address & 0xFF; ++ rtw_write8(Adapter, EFUSE_CTRL+1, temp); ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); ++ ++ //Write E-fuse Register address bit8~9 ++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); ++ rtw_write8(Adapter, EFUSE_CTRL+2, temp); ++ ++ //Write 0x30[31]=1 ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ temp = Bytetemp | 0x80; ++ rtw_write8(Adapter, EFUSE_CTRL+3, temp); ++ ++ //Wait Write-ready (0x30[31]=0) ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ while(Bytetemp & 0x80) ++ { ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ k++; ++ if(k==100) ++ { ++ k=0; ++ break; ++ } ++ } ++ } ++}/* EFUSE_Write1Byte */ ++ ++/* 11/16/2008 MH Read one byte from real Efuse. */ ++u8 ++efuse_OneByteRead( ++ IN PADAPTER pAdapter, ++ IN u16 addr, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 tmpidx = 0; ++ u8 bResult; ++ ++ if(bPseudoTest) ++ { ++ bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data); ++ return bResult; ++ } ++ // -----------------e-fuse reg ctrl --------------------------------- ++ //address ++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff)); ++ rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) | ++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )); ++ ++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);//read cmd ++ ++ while(!(0x80 &rtw_read8(pAdapter, EFUSE_CTRL+3))&&(tmpidx<100)) ++ { ++ tmpidx++; ++ } ++ if(tmpidx<100) ++ { ++ *data=rtw_read8(pAdapter, EFUSE_CTRL); ++ bResult = _TRUE; ++ } ++ else ++ { ++ *data = 0xff; ++ bResult = _FALSE; ++ } ++ return bResult; ++} ++ ++/* 11/16/2008 MH Write one byte to reald Efuse. */ ++u8 ++efuse_OneByteWrite( ++ IN PADAPTER pAdapter, ++ IN u16 addr, ++ IN u8 data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 tmpidx = 0; ++ u8 bResult; ++ ++ if(bPseudoTest) ++ { ++ bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data); ++ return bResult; ++ } ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr = %x Data=%x\n", addr, data)); ++ ++ //return 0; ++ ++ // -----------------e-fuse reg ctrl --------------------------------- ++ //address ++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff)); ++ rtw_write8(pAdapter, EFUSE_CTRL+2, ++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )|(u8)((addr>>8)&0x03) ); ++ rtw_write8(pAdapter, EFUSE_CTRL, data);//data ++ ++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);//write cmd ++ ++ while((0x80 & rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100) ){ ++ tmpidx++; ++ } ++ ++ if(tmpidx<100) ++ { ++ bResult = _TRUE; ++ } ++ else ++ { ++ bResult = _FALSE; ++ } ++ ++ return bResult; ++} ++ ++int ++Efuse_PgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest); ++ ++ return ret; ++} ++ ++int ++Efuse_PgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++ ++int ++Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ ret = pAdapter->HalFunc.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_WordEnableDataRead ++ * ++ * Overview: Read allowed word in current efuse section data. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/16/2008 MHC Create Version 0. ++ * 11/21/2008 MHC Fix Write bug when we only enable late word. ++ * ++ *---------------------------------------------------------------------------*/ ++void ++efuse_WordEnableDataRead(IN u8 word_en, ++ IN u8 *sourdata, ++ IN u8 *targetdata) ++{ ++ if (!(word_en&BIT(0))) ++ { ++ targetdata[0] = sourdata[0]; ++ targetdata[1] = sourdata[1]; ++ } ++ if (!(word_en&BIT(1))) ++ { ++ targetdata[2] = sourdata[2]; ++ targetdata[3] = sourdata[3]; ++ } ++ if (!(word_en&BIT(2))) ++ { ++ targetdata[4] = sourdata[4]; ++ targetdata[5] = sourdata[5]; ++ } ++ if (!(word_en&BIT(3))) ++ { ++ targetdata[6] = sourdata[6]; ++ targetdata[7] = sourdata[7]; ++ } ++} ++ ++ ++u8 ++Efuse_WordEnableDataWrite( IN PADAPTER pAdapter, ++ IN u16 efuse_addr, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ret=0; ++ ++ ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value) ++{ ++ return efuse_OneByteRead(padapter,address, value, _FALSE); ++} ++ ++static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value) ++{ ++ return efuse_OneByteWrite(padapter,address, *value, _FALSE); ++} ++ ++/* ++ * read/wirte raw efuse data ++ */ ++u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data) ++{ ++ int i = 0; ++ u16 real_content_len = 0, max_available_size = 0; ++ u8 res = _FAIL ; ++ u8 (*rw8)(PADAPTER, u16, u8*); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE); ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if (start_addr > real_content_len) ++ return _FAIL; ++ ++ if (_TRUE == bWrite) { ++ if ((start_addr + cnts) > max_available_size) ++ return _FAIL; ++ rw8 = &efuse_write8; ++ } else ++ rw8 = &efuse_read8; ++ ++ Efuse_PowerSwitch(padapter, bWrite, _TRUE); ++ ++ // e-fuse one byte read / write ++ for (i = 0; i < cnts; i++) { ++ if (start_addr >= real_content_len) { ++ res = _FAIL; ++ break; ++ } ++ ++ res = rw8(padapter, start_addr++, data++); ++ if (_FAIL == res) break; ++ } ++ ++ Efuse_PowerSwitch(padapter, bWrite, _FALSE); ++ ++ return res; ++} ++//------------------------------------------------------------------------------ ++u16 efuse_GetMaxSize(PADAPTER padapter) ++{ ++ u16 max_size; ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE); ++ return max_size; ++} ++//------------------------------------------------------------------------------ ++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size) ++{ ++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE); ++ *size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE); ++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE); ++ ++ return _SUCCESS; ++} ++//------------------------------------------------------------------------------ ++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) ++{ ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ if ((addr + cnts) > mapLen) ++ return _FAIL; ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE); ++ ++ efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE); ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE); ++ ++ return _SUCCESS; ++} ++ ++u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) ++{ ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ if ((addr + cnts) > mapLen) ++ return _FAIL; ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE); ++ ++ efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE); ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE); ++ ++ return _SUCCESS; ++} ++//------------------------------------------------------------------------------ ++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) ++{ ++ u8 offset, word_en; ++ u8 *map; ++ u8 newdata[PGPKT_DATA_SIZE]; ++ s32 i, j, idx; ++ u8 ret = _SUCCESS; ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ if ((addr + cnts) > mapLen) ++ return _FAIL; ++ ++ map = rtw_zmalloc(mapLen); ++ if(map == NULL){ ++ return _FAIL; ++ } ++ ++ ret = rtw_efuse_map_read(padapter, 0, mapLen, map); ++ if (ret == _FAIL) goto exit; ++ ++ Efuse_PowerSwitch(padapter, _TRUE, _TRUE); ++ ++ offset = (addr >> 3); ++ word_en = 0xF; ++ _rtw_memset(newdata, 0xFF, PGPKT_DATA_SIZE); ++ i = addr & 0x7; // index of one package ++ j = 0; // index of new package ++ idx = 0; // data index ++ ++ if (i & 0x1) { ++ // odd start ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i-1] = map[addr+idx-1]; ++ newdata[i] = data[idx]; ++ } ++ i++; ++ idx++; ++ } ++ do { ++ for (; i < PGPKT_DATA_SIZE; i += 2) ++ { ++ if (cnts == idx) break; ++ if ((cnts - idx) == 1) { ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = map[addr+idx+1]; ++ } ++ idx++; ++ break; ++ } else { ++ if ((data[idx] != map[addr+idx]) || ++ (data[idx+1] != map[addr+idx+1])) ++ { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = data[idx + 1]; ++ } ++ idx += 2; ++ } ++ if (idx == cnts) break; ++ } ++ ++ if (word_en != 0xF) { ++ ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE); ++ DBG_871X("offset=%x \n",offset); ++ DBG_871X("word_en=%x \n",word_en); ++ ++ for(i=0;i mapLen) ++ return _FAIL; ++ ++ map = rtw_zmalloc(mapLen); ++ if(map == NULL){ ++ return _FAIL; ++ } ++ ++ ret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map); ++ if (ret == _FAIL) goto exit; ++ ++ Efuse_PowerSwitch(padapter, _TRUE, _TRUE); ++ ++ offset = (addr >> 3); ++ word_en = 0xF; ++ _rtw_memset(newdata, 0xFF, PGPKT_DATA_SIZE); ++ i = addr & 0x7; // index of one package ++ j = 0; // index of new package ++ idx = 0; // data index ++ ++ if (i & 0x1) { ++ // odd start ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i-1] = map[addr+idx-1]; ++ newdata[i] = data[idx]; ++ } ++ i++; ++ idx++; ++ } ++ do { ++ for (; i < PGPKT_DATA_SIZE; i += 2) ++ { ++ if (cnts == idx) break; ++ if ((cnts - idx) == 1) { ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = map[addr+idx+1]; ++ } ++ idx++; ++ break; ++ } else { ++ if ((data[idx] != map[addr+idx]) || ++ (data[idx+1] != map[addr+idx+1])) ++ { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = data[idx + 1]; ++ } ++ idx += 2; ++ } ++ if (idx == cnts) break; ++ } ++ ++ if (word_en != 0xF) ++ { ++ DBG_871X("%s: offset=%#X\n", __FUNCTION__, offset); ++ DBG_871X("%s: word_en=%#X\n", __FUNCTION__, word_en); ++ DBG_871X("%s: data=", __FUNCTION__); ++ for (i=0; iefuse_eeprom_data[Offset]; ++ ++} // EFUSE_ShadowRead1Byte ++ ++//---------------Read Two Bytes ++static VOID ++efuse_ShadowRead2Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u16 *Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ *Value = pEEPROM->efuse_eeprom_data[Offset]; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8; ++ ++} // EFUSE_ShadowRead2Byte ++ ++//---------------Read Four Bytes ++static VOID ++efuse_ShadowRead4Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u32 *Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ *Value = pEEPROM->efuse_eeprom_data[Offset]; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24; ++ ++} // efuse_ShadowRead4Byte ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_ShadowWrite1Byte ++ * efuse_ShadowWrite2Byte ++ * efuse_ShadowWrite4Byte ++ * ++ * Overview: Write efuse modify map by one/two/four byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++#ifdef PLATFORM ++static VOID ++efuse_ShadowWrite1Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value); ++#endif //PLATFORM ++static VOID ++efuse_ShadowWrite1Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = Value; ++ ++} // efuse_ShadowWrite1Byte ++ ++//---------------Write Two Bytes ++static VOID ++efuse_ShadowWrite2Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u16 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = Value&0x00FF; ++ pEEPROM->efuse_eeprom_data[Offset+1] = Value>>8; ++ ++} // efuse_ShadowWrite1Byte ++ ++//---------------Write Four Bytes ++static VOID ++efuse_ShadowWrite4Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u32 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF); ++ pEEPROM->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF); ++ pEEPROM->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF); ++ pEEPROM->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF); ++ ++} // efuse_ShadowWrite1Byte ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowMapUpdate ++ * ++ * Overview: Transfer current EFUSE content to shadow init and modify map. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/13/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++void EFUSE_ShadowMapUpdate( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); ++ ++ if (pEEPROM->bautoload_fail_flag == _TRUE) ++ { ++ _rtw_memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen); ++ } ++ else ++ { ++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM)) { ++ #endif ++ ++ Efuse_ReadAllMap(pAdapter, efuseType, pEEPROM->efuse_eeprom_data, bPseudoTest); ++ ++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM); ++ } ++ #endif ++ } ++ ++ //PlatformMoveMemory((PVOID)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], ++ //(PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); ++}// EFUSE_ShadowMapUpdate ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowRead ++ * ++ * Overview: Read from efuse init map !!!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++void ++EFUSE_ShadowRead( ++ IN PADAPTER pAdapter, ++ IN u8 Type, ++ IN u16 Offset, ++ IN OUT u32 *Value ) ++{ ++ if (Type == 1) ++ efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); ++ else if (Type == 2) ++ efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); ++ else if (Type == 4) ++ efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); ++ ++} // EFUSE_ShadowRead ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowWrite ++ * ++ * Overview: Write efuse modify map for later update operation to use!!!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++EFUSE_ShadowWrite( ++ IN PADAPTER pAdapter, ++ IN u8 Type, ++ IN u16 Offset, ++ IN OUT u32 Value); ++VOID ++EFUSE_ShadowWrite( ++ IN PADAPTER pAdapter, ++ IN u8 Type, ++ IN u16 Offset, ++ IN OUT u32 Value) ++{ ++#if (MP_DRIVER == 0) ++ return; ++#endif ++ if ( pAdapter->registrypriv.mp_mode == 0) ++ return; ++ ++ ++ if (Type == 1) ++ efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value); ++ else if (Type == 2) ++ efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value); ++ else if (Type == 4) ++ efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value); ++ ++} // EFUSE_ShadowWrite ++ ++VOID ++Efuse_InitSomeVar( ++ IN PADAPTER pAdapter ++ ); ++VOID ++Efuse_InitSomeVar( ++ IN PADAPTER pAdapter ++ ) ++{ ++ u8 i; ++ ++ _rtw_memset((PVOID)&fakeEfuseContent[0], 0xff, EFUSE_MAX_HW_SIZE); ++ _rtw_memset((PVOID)&fakeEfuseInitMap[0], 0xff, EFUSE_MAX_MAP_LEN); ++ _rtw_memset((PVOID)&fakeEfuseModifiedMap[0], 0xff, EFUSE_MAX_MAP_LEN); ++ ++ for(i=0; i ++ ++ int isAdaptorInfoFileValid(void) ++{ ++ return _TRUE; ++} ++ ++int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv) ++{ ++ int ret =_SUCCESS; ++ ++ if(path && eeprom_priv) { ++ ret = rtw_store_to_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE_512); ++ if(ret == EEPROM_MAX_SIZE) ++ ret = _SUCCESS; ++ else ++ ret = _FAIL; ++ } else { ++ DBG_871X("%s NULL pointer\n",__FUNCTION__); ++ ret = _FAIL; ++ } ++ return ret; ++} ++ ++int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv) ++{ ++ int ret = _SUCCESS; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && eeprom_priv) { ++ ++ ret = rtw_retrive_from_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE); ++ ++ if(ret == EEPROM_MAX_SIZE) ++ ret = _SUCCESS; ++ else ++ ret = _FAIL; ++ ++ #if 0 ++ if(isAdaptorInfoFileValid()) { ++ return 0; ++ } else { ++ return _FAIL; ++ } ++ #endif ++ ++ } else { ++ DBG_871X("%s NULL pointer\n",__FUNCTION__); ++ ret = _FAIL; ++ } ++ return ret; ++} ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++#endif //PLATFORM_LINUX ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ap.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ap.c +new file mode 100644 +index 00000000..70df9b1a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ap.c +@@ -0,0 +1,2960 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_AP_C_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++extern unsigned char RTW_WPA_OUI[]; ++extern unsigned char WMM_OUI[]; ++extern unsigned char WPS_OUI[]; ++extern unsigned char P2P_OUI[]; ++extern unsigned char WFD_OUI[]; ++ ++void init_mlme_ap_info(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ ++ ++ _rtw_spinlock_init(&pmlmepriv->bcn_update_lock); ++ ++ //for ACL ++ _rtw_init_queue(&pacl_list->acl_node_q); ++ ++ //pmlmeext->bstart_bss = _FALSE; ++ ++ start_ap_mode(padapter); ++} ++ ++void free_mlme_ap_info(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //stop_ap_mode(padapter); ++ ++ pmlmepriv->update_bcn = _FALSE; ++ pmlmeext->bstart_bss = _FALSE; ++ ++ rtw_sta_flush(padapter); ++ ++ pmlmeinfo->state = _HW_STATE_NOLINK_; ++ ++ //free_assoc_sta_resources ++ rtw_free_all_stainfo(padapter); ++ ++ //free bc/mc sta_info ++ psta = rtw_get_bcmc_stainfo(padapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); ++ ++} ++ ++static void update_BCNTIM(_adapter *padapter) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); ++ unsigned char *pie = pnetwork_mlmeext->IEs; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ //update TIM IE ++ //if(pstapriv->tim_bitmap) ++ if(_TRUE) ++ { ++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL; ++ u16 tim_bitmap_le; ++ uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen; ++ ++ tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); ++ ++ p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_); ++ if (p != NULL && tim_ielen>0) ++ { ++ tim_ielen += 2; ++ ++ premainder_ie = p+tim_ielen; ++ ++ tim_ie_offset = (sint)(p -pie); ++ ++ remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen; ++ ++ //append TIM IE from dst_ie offset ++ dst_ie = p; ++ } ++ else ++ { ++ tim_ielen = 0; ++ ++ //calucate head_len ++ offset = _FIXED_IE_LENGTH_; ++ ++ /* get ssid_ie len */ ++ p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); ++ if (p != NULL) ++ offset += tmp_len+2; ++ ++ // get supported rates len ++ p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); ++ if (p != NULL) ++ { ++ offset += tmp_len+2; ++ } ++ ++ //DS Parameter Set IE, len=3 ++ offset += 3; ++ ++ premainder_ie = pie + offset; ++ ++ remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen; ++ ++ //append TIM IE from offset ++ dst_ie = pie + offset; ++ ++ } ++ ++ ++ if(remainder_ielen>0) ++ { ++ pbackup_remainder_ie = rtw_malloc(remainder_ielen); ++ if(pbackup_remainder_ie && premainder_ie) ++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); ++ } ++ ++ *dst_ie++=_TIM_IE_; ++ ++ if((pstapriv->tim_bitmap&0xff00) && (pstapriv->tim_bitmap&0x00fc)) ++ tim_ielen = 5; ++ else ++ tim_ielen = 4; ++ ++ *dst_ie++= tim_ielen; ++ ++ *dst_ie++=0;//DTIM count ++ *dst_ie++=1;//DTIM peroid ++ ++ if(pstapriv->tim_bitmap&BIT(0))//for bc/mc frames ++ *dst_ie++ = BIT(0);//bitmap ctrl ++ else ++ *dst_ie++ = 0; ++ ++ if(tim_ielen==4) ++ { ++ *dst_ie++ = *(u8*)&tim_bitmap_le; ++ } ++ else if(tim_ielen==5) ++ { ++ _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); ++ dst_ie+=2; ++ } ++ ++ //copy remainder IE ++ if(pbackup_remainder_ie) ++ { ++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); ++ ++ rtw_mfree(pbackup_remainder_ie, remainder_ielen); ++ } ++ ++ offset = (uint)(dst_ie - pie); ++ pnetwork_mlmeext->IELength = offset + remainder_ielen; ++ ++ } ++ ++#ifndef CONFIG_INTERRUPT_BASED_TXBCN ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ set_tx_beacon_cmd(padapter); ++#endif ++#endif //!CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++} ++ ++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len) ++{ ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 bmatch = _FALSE; ++ u8 *pie = pnetwork->IEs; ++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL; ++ u32 i, offset, ielen, ie_offset, remainder_ielen = 0; ++ ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); ++ ++ if (pIE->ElementID > index) ++ { ++ break; ++ } ++ else if(pIE->ElementID == index) // already exist the same IE ++ { ++ p = (u8 *)pIE; ++ ielen = pIE->Length; ++ bmatch = _TRUE; ++ break; ++ } ++ ++ p = (u8 *)pIE; ++ ielen = pIE->Length; ++ i += (pIE->Length + 2); ++ } ++ ++ if (p != NULL && ielen>0) ++ { ++ ielen += 2; ++ ++ premainder_ie = p+ielen; ++ ++ ie_offset = (sint)(p -pie); ++ ++ remainder_ielen = pnetwork->IELength - ie_offset - ielen; ++ ++ if(bmatch) ++ dst_ie = p; ++ else ++ dst_ie = (p+ielen); ++ } ++ ++ if(remainder_ielen>0) ++ { ++ pbackup_remainder_ie = rtw_malloc(remainder_ielen); ++ if(pbackup_remainder_ie && premainder_ie) ++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); ++ } ++ ++ *dst_ie++=index; ++ *dst_ie++=len; ++ ++ _rtw_memcpy(dst_ie, data, len); ++ dst_ie+=len; ++ ++ //copy remainder IE ++ if(pbackup_remainder_ie) ++ { ++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); ++ ++ rtw_mfree(pbackup_remainder_ie, remainder_ielen); ++ } ++ ++ offset = (uint)(dst_ie - pie); ++ pnetwork->IELength = offset + remainder_ielen; ++} ++ ++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index) ++{ ++ u8 *p, *dst_ie, *premainder_ie=NULL, *pbackup_remainder_ie=NULL; ++ uint offset, ielen, ie_offset, remainder_ielen = 0; ++ u8 *pie = pnetwork->IEs; ++ ++ p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_); ++ if (p != NULL && ielen>0) ++ { ++ ielen += 2; ++ ++ premainder_ie = p+ielen; ++ ++ ie_offset = (sint)(p -pie); ++ ++ remainder_ielen = pnetwork->IELength - ie_offset - ielen; ++ ++ dst_ie = p; ++ } ++ else { ++ return; ++ } ++ ++ if(remainder_ielen>0) ++ { ++ pbackup_remainder_ie = rtw_malloc(remainder_ielen); ++ if(pbackup_remainder_ie && premainder_ie) ++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); ++ } ++ ++ //copy remainder IE ++ if(pbackup_remainder_ie) ++ { ++ _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); ++ ++ rtw_mfree(pbackup_remainder_ie, remainder_ielen); ++ } ++ ++ offset = (uint)(dst_ie - pie); ++ pnetwork->IELength = offset + remainder_ielen; ++} ++ ++ ++u8 chk_sta_is_alive(struct sta_info *psta); ++u8 chk_sta_is_alive(struct sta_info *psta) ++{ ++ u8 ret = _FALSE; ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" ++ , MAC_ARG(psta->hwaddr) ++ , psta->rssi_stat.UndecoratedSmoothedPWDB ++ //, STA_RX_PKTS_ARG(psta) ++ , STA_RX_PKTS_DIFF_ARG(psta) ++ , psta->expire_to ++ , psta->state&WIFI_SLEEP_STATE?"PS, ":"" ++ , psta->state&WIFI_STA_ALIVE_CHK_STATE?"SAC, ":"" ++ , psta->sleepq_len ++ ); ++ #endif ++ ++ //if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) ++ if((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) ++ { ++ #if 0 ++ if(psta->state&WIFI_SLEEP_STATE) ++ ret = _TRUE; ++ #endif ++ } ++ else ++ { ++ ret = _TRUE; ++ } ++ ++ sta_update_last_rx_pkts(psta); ++ ++ return ret; ++} ++ ++void expire_timeout_chk(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ u8 updated; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 chk_alive_num = 0; ++ char chk_alive_list[NUM_STA]; ++ int i; ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ phead = &pstapriv->auth_list; ++ plist = get_next(phead); ++ ++ //check auth_queue ++ #ifdef DBG_EXPIRATION_CHK ++ if (rtw_end_of_queue_search(phead, plist) == _FALSE) { ++ DBG_871X(FUNC_NDEV_FMT" auth_list, cnt:%u\n" ++ , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->auth_list_cnt); ++ } ++ #endif ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, auth_list); ++ plist = get_next(plist); ++ ++ ++#ifdef CONFIG_ATMEL_RC_PATCH ++ if (_TRUE == _rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->hwaddr), ETH_ALEN)) ++ continue; ++ if (psta->flag_atmel_rc) ++ continue; ++#endif ++ if(psta->expire_to>0) ++ { ++ psta->expire_to--; ++ if (psta->expire_to == 0) ++ { ++ rtw_list_delete(&psta->auth_list); ++ pstapriv->auth_list_cnt--; ++ ++ DBG_871X("auth expire %02X%02X%02X%02X%02X%02X\n", ++ psta->hwaddr[0],psta->hwaddr[1],psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]); ++ ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ } ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ psta = NULL; ++ ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //check asoc_queue ++ #ifdef DBG_EXPIRATION_CHK ++ if (rtw_end_of_queue_search(phead, plist) == _FALSE) { ++ DBG_871X(FUNC_NDEV_FMT" asoc_list, cnt:%u\n" ++ , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->asoc_list_cnt); ++ } ++ #endif ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ plist = get_next(plist); ++#ifdef CONFIG_ATMEL_RC_PATCH ++ DBG_871X("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__, ++ psta,pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->hwaddr[0], psta->hwaddr[5]); ++ if (_TRUE == _rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->hwaddr), ETH_ALEN)) ++ continue; ++ if (psta->flag_atmel_rc) ++ continue; ++ DBG_871X("%s: debug line:%d \n", __func__, __LINE__); ++#endif ++ if (chk_sta_is_alive(psta) || !psta->expire_to) { ++ psta->expire_to = pstapriv->expire_to; ++ psta->keep_alive_trycnt = 0; ++ #ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++ #endif // CONFIG_TX_MCAST2UNI ++ } else { ++ psta->expire_to--; ++ } ++ ++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++#ifdef CONFIG_TX_MCAST2UNI ++#ifdef CONFIG_80211N_HT ++ if ( (psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking) ) { ++ // check sta by delba(addba) for 11n STA ++ // ToDo: use CCX report to check for all STAs ++ //DBG_871X("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); ++ ++ if ( psta->expire_to <= (pstapriv->expire_to - 50 ) ) { ++ DBG_871X("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); ++ psta->under_exist_checking = 0; ++ psta->expire_to = 0; ++ } else if ( psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking==0)) { ++ DBG_871X("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); ++ psta->under_exist_checking = 1; ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ } ++ } ++#endif //CONFIG_80211N_HT ++#endif // CONFIG_TX_MCAST2UNI ++#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ ++ if (psta->expire_to <= 0) ++ { ++ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if (padapter->registrypriv.wifi_spec == 1) ++ { ++ psta->expire_to = pstapriv->expire_to; ++ continue; ++ } ++ ++ if (psta->state & WIFI_SLEEP_STATE) { ++ if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) { ++ //to check if alive by another methods if staion is at ps mode. ++ psta->expire_to = pstapriv->expire_to; ++ psta->state |= WIFI_STA_ALIVE_CHK_STATE; ++ ++ //DBG_871X("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); ++ ++ //to update bcn with tim_bitmap for this station ++ pstapriv->tim_bitmap |= BIT(psta->aid); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ ++ if(!pmlmeext->active_keep_alive_check) ++ continue; ++ } ++ } ++ ++ if (pmlmeext->active_keep_alive_check) { ++ int stainfo_offset; ++ ++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta); ++ if (stainfo_offset_valid(stainfo_offset)) { ++ chk_alive_list[chk_alive_num++] = stainfo_offset; ++ } ++ ++ continue; ++ } ++ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ ++ ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ ++ DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); ++ updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING); ++ } ++ else ++ { ++ /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ ++ if (psta->sleepq_len > (NR_XMITFRAME/pstapriv->asoc_list_cnt) ++ && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME/pstapriv->asoc_list_cnt)/2) ++ ){ ++ DBG_871X("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__ ++ , MAC_ARG(psta->hwaddr) ++ , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); ++ wakeup_sta_to_xmit(padapter, psta); ++ } ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++if (chk_alive_num) { ++ ++ u8 backup_oper_channel=0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ /* switch to correct channel of current network before issue keep-alive frames */ ++ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { ++ backup_oper_channel = rtw_get_oper_ch(padapter); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ } ++ ++ /* issue null data to check sta alive*/ ++ for (i = 0; i < chk_alive_num; i++) { ++ ++ int ret = _FAIL; ++ ++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); ++#ifdef CONFIG_ATMEL_RC_PATCH ++ if (_TRUE == _rtw_memcmp( pstapriv->atmel_rc_pattern, psta->hwaddr, ETH_ALEN)) ++ continue; ++ if (psta->flag_atmel_rc) ++ continue; ++#endif ++ if(!(psta->state &_FW_LINKED)) ++ continue; ++ ++ if (psta->state & WIFI_SLEEP_STATE) ++ ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); ++ else ++ ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); ++ ++ psta->keep_alive_trycnt++; ++ if (ret == _SUCCESS) ++ { ++ DBG_871X("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr)); ++ psta->expire_to = pstapriv->expire_to; ++ psta->keep_alive_trycnt = 0; ++ continue; ++ } ++ else if (psta->keep_alive_trycnt <= 3) ++ { ++ DBG_871X("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); ++ psta->expire_to = 1; ++ continue; ++ } ++ ++ psta->keep_alive_trycnt = 0; ++ ++ DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if (rtw_is_list_empty(&psta->asoc_list)==_FALSE) { ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING); ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ ++ if (backup_oper_channel>0) /* back to the original operation channel */ ++ SelectChannel(padapter, backup_oper_channel); ++} ++#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ ++ ++ associated_clients_update(padapter, updated); ++} ++ ++void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level) ++{ ++ int i; ++ u8 rf_type; ++ u32 init_rate=0; ++ unsigned char sta_band = 0, raid, shortGIrate = _FALSE; ++ unsigned char limit; ++ unsigned int tx_ra_bitmap=0; ++ struct ht_priv *psta_ht = NULL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ ++#ifdef CONFIG_80211N_HT ++ if(psta) ++ psta_ht = &psta->htpriv; ++ else ++ return; ++#endif //CONFIG_80211N_HT ++ ++ if(!(psta->state & _FW_LINKED)) ++ return; ++ ++ //b/g mode ra_bitmap ++ for (i=0; ibssrateset); i++) ++ { ++ if (psta->bssrateset[i]) ++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); ++ } ++#ifdef CONFIG_80211N_HT ++ //n mode ra_bitmap ++ if(psta_ht->ht_option) ++ { ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if(rf_type == RF_2T2R) ++ limit=16;// 2R ++ else ++ limit=8;// 1R ++ ++ for (i=0; iht_cap.supp_mcs_set[i/8] & BIT(i%8)) ++ tx_ra_bitmap |= BIT(i+12); ++ } ++ ++ //max short GI rate ++ shortGIrate = psta_ht->sgi; ++ } ++#endif //CONFIG_80211N_HT ++ ++#if 0//gtest ++ if(get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R) ++ { ++ //is this a 2r STA? ++ if((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid))) ++ { ++ priv->pshare->has_2r_sta |= BIT(pstat->aid); ++ if(rtw_read16(padapter, 0x102501f6) != 0xffff) ++ { ++ rtw_write16(padapter, 0x102501f6, 0xffff); ++ reset_1r_sta_RA(priv, 0xffff); ++ Switch_1SS_Antenna(priv, 3); ++ } ++ } ++ else// bg or 1R STA? ++ { ++ if((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0) ++ { ++ if(rtw_read16(padapter, 0x102501f6) != 0x7777) ++ { // MCS7 SGI ++ rtw_write16(padapter, 0x102501f6,0x7777); ++ reset_1r_sta_RA(priv, 0x7777); ++ Switch_1SS_Antenna(priv, 2); ++ } ++ } ++ } ++ ++ } ++ ++ if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) ++ { ++ if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) ++ pstat->rssi_level = 1; ++ else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || ++ ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && ++ (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && ++ (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) ++ pstat->rssi_level = 2; ++ else ++ pstat->rssi_level = 3; ++ } ++ ++ // rate adaptive by rssi ++ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len) ++ { ++ if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x100f0000; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x100ff000; ++ break; ++ case 3: ++ if (priv->pshare->is_40m_bw) ++ pstat->tx_ra_bitmap &= 0x100ff005; ++ else ++ pstat->tx_ra_bitmap &= 0x100ff001; ++ ++ break; ++ } ++ } ++ else ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x1f0f0000; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x1f0ff000; ++ break; ++ case 3: ++ if (priv->pshare->is_40m_bw) ++ pstat->tx_ra_bitmap &= 0x000ff005; ++ else ++ pstat->tx_ra_bitmap &= 0x000ff001; ++ ++ break; ++ } ++ ++ // Don't need to mask high rates due to new rate adaptive parameters ++ //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta ++ // pstat->tx_ra_bitmap &= 0x81ffffff; ++ ++ // NIC driver will report not supporting MCS15 and MCS14 in asoc req ++ //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) ++ // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14 ++ } ++ } ++ else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x00000f00; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x00000ff0; ++ break; ++ case 3: ++ pstat->tx_ra_bitmap &= 0x00000ff5; ++ break; ++ } ++ } ++ else ++ { ++ pstat->tx_ra_bitmap &= 0x0000000d; ++ } ++ ++ // disable tx short GI when station cannot rx MCS15(AP is 2T2R) ++ // disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R) ++ // if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate ++ if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) || ++ (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R))) ++ { ++ pstat->tx_ra_bitmap &= ~BIT(28); ++ } ++#endif ++ ++ if ( pcur_network->Configuration.DSConfig > 14 ) { ++ // 5G band ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_5N ; ++ ++ if (tx_ra_bitmap & 0xff0) ++ sta_band |= WIRELESS_11A; ++ ++ } else { ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_24N; ++ ++ if (tx_ra_bitmap & 0xff0) ++ sta_band |= WIRELESS_11G; ++ ++ if (tx_ra_bitmap & 0x0f) ++ sta_band |= WIRELESS_11B; ++ } ++ ++ psta->wireless_mode = sta_band; ++ ++ raid = networktype_to_raid(sta_band); ++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f; ++ ++ if (psta->aid < NUM_STA) ++ { ++ u8 arg = 0; ++ ++ arg = psta->mac_id&0x1f; ++ ++ arg |= BIT(7);//support entry 2~31 ++ ++ if (shortGIrate==_TRUE) ++ arg |= BIT(5); ++ ++ tx_ra_bitmap |= ((raid<<28)&0xf0000000); ++ ++ DBG_871X("%s=> mac_id:%d , raid:%d , bitmap=0x%x, arg=0x%x\n", ++ __FUNCTION__ , psta->mac_id, raid ,tx_ra_bitmap, arg); ++ ++ //bitmap[0:27] = tx_rate_bitmap ++ //bitmap[28:31]= Rate Adaptive id ++ //arg[0:4] = macid ++ //arg[5] = Short GI ++ rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, rssi_level); ++ ++ ++ if (shortGIrate==_TRUE) ++ init_rate |= BIT(6); ++ ++ //set ra_id, init_rate ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ } ++ else ++ { ++ DBG_871X("station aid %d exceed the max number\n", psta->aid); ++ } ++ ++} ++ ++void update_bmc_sta(_adapter *padapter) ++{ ++ _irqL irqL; ++ u32 init_rate=0; ++ unsigned char network_type, raid; ++ int i, supportRateNum = 0; ++ unsigned int tx_ra_bitmap=0; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); ++ ++ if(psta) ++ { ++ psta->aid = 0;//default set to 0 ++ //psta->mac_id = psta->aid+4; ++ psta->mac_id = psta->aid + 1; ++ ++ psta->qos_option = 0; ++#ifdef CONFIG_80211N_HT ++ psta->htpriv.ht_option = _FALSE; ++#endif //CONFIG_80211N_HT ++ ++ psta->ieee8021x_blocked = 0; ++ ++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); ++ ++ //psta->dot118021XPrivacy = _NO_PRIVACY_;//!!! remove it, because it has been set before this. ++ ++ ++ ++ //prepare for add_RATid ++ supportRateNum = rtw_get_rateset_len((u8*)&pcur_network->SupportedRates); ++ network_type = rtw_check_network_type((u8*)&pcur_network->SupportedRates, supportRateNum, 1); ++ ++ _rtw_memcpy(psta->bssrateset, &pcur_network->SupportedRates, supportRateNum); ++ psta->bssratelen = supportRateNum; ++ ++ //b/g mode ra_bitmap ++ for (i=0; ibssrateset[i]) ++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); ++ } ++ ++ if ( pcur_network->Configuration.DSConfig > 14 ) { ++ //force to A mode. 5G doesn't support CCK rates ++ network_type = WIRELESS_11A; ++ tx_ra_bitmap = 0x150; // 6, 12, 24 Mbps ++ } else { ++ //force to b mode ++ network_type = WIRELESS_11B; ++ tx_ra_bitmap = 0xf; ++ } ++ ++ //tx_ra_bitmap = update_basic_rate(pcur_network->SupportedRates, supportRateNum); ++ ++ raid = networktype_to_raid(network_type); ++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f; ++ ++ //DBG_871X("Add id %d val %08x to ratr for bmc sta\n", psta->aid, tx_ra_bitmap); ++ //ap mode ++ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); ++ ++ //if(pHalData->fw_ractrl == _TRUE) ++ { ++ u8 arg = 0; ++ ++ arg = psta->mac_id&0x1f; ++ ++ arg |= BIT(7); ++ ++ //if (shortGIrate==_TRUE) ++ // arg |= BIT(5); ++ ++ tx_ra_bitmap |= ((raid<<28)&0xf0000000); ++ ++ DBG_871X("update_bmc_sta, mask=0x%x, arg=0x%x\n", tx_ra_bitmap, arg); ++ ++ //bitmap[0:27] = tx_rate_bitmap ++ //bitmap[28:31]= Rate Adaptive id ++ //arg[0:4] = macid ++ //arg[5] = Short GI ++ rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, 0); ++ ++ } ++ ++ //set ra_id, init_rate ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ rtw_sta_media_status_rpt(padapter, psta, 1); ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ psta->state = _FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ } ++ else ++ { ++ DBG_871X("add_RATid_bmc_sta error!\n"); ++ } ++ ++} ++ ++//notes: ++//AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode ++//MAC_ID = AID+1 for sta in ap/adhoc mode ++//MAC_ID = 1 for bc/mc for sta/ap/adhoc ++//MAC_ID = 0 for bssid for sta/ap/adhoc ++//CAM_ID = //0~3 for default key, cmd_id=macid + 3, macid=aid+1; ++ ++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++#ifdef CONFIG_80211N_HT ++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; ++ struct ht_priv *phtpriv_sta = &psta->htpriv; ++#endif //CONFIG_80211N_HT ++ //set intf_tag to if1 ++ //psta->intf_tag = 0; ++ ++ //psta->mac_id = psta->aid+4; ++ psta->mac_id = psta->aid+1; ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ //ap mode ++ rtw_hal_set_odm_var(padapter,HAL_ODM_STA_INFO,psta,_TRUE); ++ ++ if(psecuritypriv->dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) ++ psta->ieee8021x_blocked = _TRUE; ++ else ++ psta->ieee8021x_blocked = _FALSE; ++ ++ ++ //update sta's cap ++ ++ //ERP ++ VCS_update(padapter, psta); ++#ifdef CONFIG_80211N_HT ++ //HT related cap ++ if(phtpriv_sta->ht_option) ++ { ++ //check if sta supports rx ampdu ++ phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable; ++ ++ //check if sta support s Short GI ++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ++ { ++ phtpriv_sta->sgi = _TRUE; ++ } ++ ++ // bwmode ++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) ++ { ++ //phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_40; ++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode; ++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; ++ ++ } ++ ++ psta->qos_option = _TRUE; ++ ++ } ++ else ++ { ++ phtpriv_sta->ampdu_enable = _FALSE; ++ ++ phtpriv_sta->sgi = _FALSE; ++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20; ++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ //Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ phtpriv_sta->agg_enable_bitmap = 0x0;//reset ++ phtpriv_sta->candidate_tid_bitmap = 0x0;//reset ++#endif //CONFIG_80211N_HT ++ ++ //todo: init other variables ++ ++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); ++ ++ ++ //add ratid ++ //add_RATid(padapter, psta);//move to ap_sta_info_defer_update() ++ ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ psta->state |= _FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ ++} ++ ++static void update_hw_ht_param(_adapter *padapter) ++{ ++ unsigned char max_AMPDU_len; ++ unsigned char min_MPDU_spacing; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ++ //handle A-MPDU parameter field ++ /* ++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k ++ AMPDU_para [4:2]:Min MPDU Start Spacing ++ */ ++ max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; ++ ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); ++ ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ //pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++ ++} ++ ++static void start_bss_network(_adapter *padapter, u8 *pbuf) ++{ ++ u8 *p; ++ u8 val8, cur_channel, cur_bwmode, cur_ch_offset; ++ u16 bcn_interval; ++ u32 acparm; ++ int ie_len; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); ++ struct HT_info_element *pht_info=NULL; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; ++ cur_channel = pnetwork->Configuration.DSConfig; ++ cur_bwmode = HT_CHANNEL_WIDTH_20;; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ ++ //check if there is wps ie, ++ //if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, ++ //and at first time the security ie ( RSN/WPA IE) will not include in beacon. ++ if(NULL == rtw_get_wps_ie(pnetwork->IEs+_FIXED_IE_LENGTH_, pnetwork->IELength-_FIXED_IE_LENGTH_, NULL, NULL)) ++ { ++ pmlmeext->bstart_bss = _TRUE; ++ } ++ ++ //todo: update wmm, ht cap ++ //pmlmeinfo->WMM_enable; ++ //pmlmeinfo->HT_enable; ++ if(pmlmepriv->qospriv.qos_option) ++ pmlmeinfo->WMM_enable = _TRUE; ++#ifdef CONFIG_80211N_HT ++ if(pmlmepriv->htpriv.ht_option) ++ { ++ pmlmeinfo->WMM_enable = _TRUE; ++ pmlmeinfo->HT_enable = _TRUE; ++ //pmlmeinfo->HT_info_enable = _TRUE; ++ //pmlmeinfo->HT_caps_enable = _TRUE; ++ ++ update_hw_ht_param(padapter); ++ } ++#endif //#CONFIG_80211N_HT ++ ++ ++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time ++ { ++ //WEP Key will be set before this function, do not clear CAM. ++ if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) ++ flush_all_cam_entry(padapter); //clear CAM ++ } ++ ++ //set MSR to AP_Mode ++ Set_MSR(padapter, _HW_STATE_AP_); ++ ++ //Set BSSID REG ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress); ++ ++ //Set EDCA param reg ++#ifdef CONFIG_CONCURRENT_MODE ++ acparm = 0x005ea42b; ++#else ++ acparm = 0x002F3217; // VO ++#endif ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E4317; // VI ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ //acparm = 0x00105320; // BE ++ acparm = 0x005ea42b; ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A444; // BK ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ ++ //Set Security ++ val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; ++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //Beacon Control related register ++ rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); ++ ++ ++ UpdateBrateTbl(padapter, pnetwork->SupportedRates); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); ++ ++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time ++ { ++ //u32 initialgain; ++ ++ //initialgain = 0x1e; ++ ++ ++ //disable dynamic functions, such as high power, DIG ++ //Save_DM_Func_Flag(padapter); ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->adapter_type > PRIMARY_ADAPTER) ++ { ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ ++ //turn on all dynamic functions on PRIMARY_ADAPTER, dynamic functions only runs at PRIMARY_ADAPTER ++ Switch_DM_Func(pbuddy_adapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); ++ ++ //rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ } ++ } ++ else ++#endif ++ { ++ //turn on all dynamic functions ++ Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); ++ ++ //rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ } ++ ++ } ++#ifdef CONFIG_80211N_HT ++ //set channel, bwmode ++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ ++ if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode ++ //pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch (pht_info->infos[0] & 0x3) ++ { ++ case 1: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ } ++ ++ } ++#endif //CONFIG_80211N_HT ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_set_ap_channel_bandwidth(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++#else ++ //TODO: need to judge the phy parameters on concurrent mode for single phy ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++#ifdef CONFIG_CONCURRENT_MODE ++ if(!check_buddy_fwstate(padapter, _FW_LINKED|_FW_UNDER_LINKING|_FW_UNDER_SURVEY)) ++ { ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ } ++ else if(check_buddy_fwstate(padapter, _FW_LINKED)==_TRUE)//only second adapter can enter AP Mode ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ //To sync cur_channel/cur_bwmode/cur_ch_offset with primary adapter ++ DBG_871X("primary iface is at linked state, sync cur_channel/cur_bwmode/cur_ch_offset\n"); ++ DBG_871X("primary adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ DBG_871X("second adapter, CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ cur_channel = pbuddy_mlmeext->cur_channel; ++ if(cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ if(pht_info) ++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); ++ ++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ ++ //to update cur_ch_offset value in beacon ++ if(pht_info) ++ { ++ switch(cur_ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ pht_info->infos[0] |= 0x1; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ pht_info->infos[0] |= 0x3; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ default: ++ break; ++ } ++ } ++ ++ } ++ else if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) ++ { ++ cur_bwmode = HT_CHANNEL_WIDTH_20; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ if(cur_channel>0 && cur_channel<5) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x1; ++ ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ } ++ ++ if(cur_channel>7 && cur_channel<(14+1)) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x3; ++ ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ } ++ ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ } ++ ++ } ++ ++ // to update channel value in beacon ++ pnetwork->Configuration.DSConfig = cur_channel; ++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if(p && ie_len>0) ++ *(p + 2) = cur_channel; ++ ++ if(pht_info) ++ pht_info->primary_channel = cur_channel; ++ } ++#else ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++#endif //CONFIG_CONCURRENT_MODE ++ ++ DBG_871X("CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ // ++ pmlmeext->cur_channel = cur_channel; ++ pmlmeext->cur_bwmode = cur_bwmode; ++ pmlmeext->cur_ch_offset = cur_ch_offset; ++#endif //CONFIG_DUALMAC_CONCURRENT ++ pmlmeext->cur_wireless_mode = pmlmepriv->cur_network.network_type; ++ ++ //let pnetwork_mlmeext == pnetwork_mlme. ++ _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); ++ ++ //update cur_wireless_mode ++ update_wireless_mode(padapter); ++ ++ //udpate capability after cur_wireless_mode updated ++ update_capinfo(padapter, rtw_get_capability((WLAN_BSSID_EX *)pnetwork)); ++ ++#ifdef CONFIG_P2P ++ _rtw_memcpy(pwdinfo->p2p_group_ssid, pnetwork->Ssid.Ssid, pnetwork->Ssid.SsidLength); ++ pwdinfo->p2p_group_ssid_len = pnetwork->Ssid.SsidLength; ++#endif //CONFIG_P2P ++ ++ if(_TRUE == pmlmeext->bstart_bss) ++ { ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ ++#ifndef CONFIG_INTERRUPT_BASED_TXBCN //other case will tx beacon when bcn interrupt coming in. ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ //issue beacon frame ++ if(send_beacon(padapter)==_FAIL) ++ { ++ DBG_871X("issue_beacon, fail!\n"); ++ } ++#endif ++#endif //!CONFIG_INTERRUPT_BASED_TXBCN ++ ++ } ++ ++ ++ //update bc/mc sta_info ++ update_bmc_sta(padapter); ++ ++ //pmlmeext->bstart_bss = _TRUE; ++ ++} ++ ++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) ++{ ++ int ret=_SUCCESS; ++ u8 *p; ++ u8 *pHT_caps_ie=NULL; ++ u8 *pHT_info_ie=NULL; ++ struct sta_info *psta = NULL; ++ u16 cap, ht_cap=_FALSE; ++ uint ie_len = 0; ++ int group_cipher, pairwise_cipher; ++ u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; ++ int supportRateNum = 0; ++ u8 OUI1[] = {0x00, 0x50, 0xf2,0x01}; ++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *ie = pbss_network->IEs; ++ ++ ++ /* SSID */ ++ /* Supported rates */ ++ /* DS Params */ ++ /* WLAN_EID_COUNTRY */ ++ /* ERP Information element */ ++ /* Extended supported rates */ ++ /* WPA/WPA2 */ ++ /* Wi-Fi Wireless Multimedia Extensions */ ++ /* ht_capab, ht_oper */ ++ /* WPS IE */ ++ ++ DBG_871X("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return _FAIL; ++ ++ ++ if(len>MAX_IE_SZ) ++ return _FAIL; ++ ++ pbss_network->IELength = len; ++ ++ _rtw_memset(ie, 0, MAX_IE_SZ); ++ ++ _rtw_memcpy(ie, pbuf, pbss_network->IELength); ++ ++ ++ if(pbss_network->InfrastructureMode!=Ndis802_11APMode) ++ return _FAIL; ++ ++ pbss_network->Rssi = 0; ++ ++ _rtw_memcpy(pbss_network->MacAddress, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ //beacon interval ++ p = rtw_get_beacon_interval_from_ie(ie);//ie + 8; // 8: TimeStamp, 2: Beacon Interval 2:Capability ++ //pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); ++ pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p); ++ ++ //capability ++ //cap = *(unsigned short *)rtw_get_capability_from_ie(ie); ++ //cap = le16_to_cpu(cap); ++ cap = RTW_GET_LE16(ie); ++ ++ //SSID ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength -_BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len); ++ pbss_network->Ssid.SsidLength = ie_len; ++ } ++ ++ //chnnel ++ channel = 0; ++ pbss_network->Configuration.Length = 0; ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ channel = *(p + 2); ++ ++ pbss_network->Configuration.DSConfig = channel; ++ ++ ++ _rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX); ++ // get supported rates ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if (p != NULL) ++ { ++ _rtw_memcpy(supportRate, p+2, ie_len); ++ supportRateNum = ie_len; ++ } ++ ++ //get ext_supported rates ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); ++ if (p != NULL) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len); ++ supportRateNum += ie_len; ++ ++ } ++ ++ network_type = rtw_check_network_type(supportRate, supportRateNum, channel); ++ ++ rtw_set_supported_rate(pbss_network->SupportedRates, network_type); ++ ++ ++ //parsing ERP_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); ++ } ++ ++ //update privacy/security ++ if (cap & BIT(4)) ++ pbss_network->Privacy = 1; ++ else ++ pbss_network->Privacy = 0; ++ ++ psecuritypriv->wpa_psk = 0; ++ ++ //wpa2 ++ group_cipher = 0; pairwise_cipher = 0; ++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; ++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ if(rtw_parse_wpa2_ie(p, ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ ++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x ++ psecuritypriv->wpa_psk |= BIT(1); ++ ++ psecuritypriv->wpa2_group_cipher = group_cipher; ++ psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher; ++#if 0 ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa2_group_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa2_group_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa2_group_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa2_group_cipher = _WEP104_; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa2_pairwise_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa2_pairwise_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa2_pairwise_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa2_pairwise_cipher = _WEP104_; ++ break; ++ } ++#endif ++ } ++ ++ } ++ ++ //wpa ++ ie_len = 0; ++ group_cipher = 0; pairwise_cipher = 0; ++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; ++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; ++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) ++ { ++ p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if ((p) && (_rtw_memcmp(p+2, OUI1, 4))) ++ { ++ if(rtw_parse_wpa_ie(p, ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ ++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x ++ ++ psecuritypriv->wpa_psk |= BIT(0); ++ ++ psecuritypriv->wpa_group_cipher = group_cipher; ++ psecuritypriv->wpa_pairwise_cipher = pairwise_cipher; ++ ++#if 0 ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa_group_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa_group_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa_group_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa_group_cipher = _WEP104_; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa_pairwise_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa_pairwise_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa_pairwise_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa_pairwise_cipher = _WEP104_; ++ break; ++ } ++#endif ++ } ++ ++ break; ++ ++ } ++ ++ if ((p == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ ++ } ++ ++ //wmm ++ ie_len = 0; ++ pmlmepriv->qospriv.qos_option = 0; ++ if(pregistrypriv->wmm_enable) ++ { ++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) ++ { ++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if((p) && _rtw_memcmp(p+2, WMM_PARA_IE, 6)) ++ { ++ pmlmepriv->qospriv.qos_option = 1; ++ ++ *(p+8) |= BIT(7);//QoS Info, support U-APSD ++ ++ /* disable all ACM bits since the WMM admission control is not supported */ ++ *(p + 10) &= ~BIT(4); /* BE */ ++ *(p + 14) &= ~BIT(4); /* BK */ ++ *(p + 18) &= ~BIT(4); /* VI */ ++ *(p + 22) &= ~BIT(4); /* VO */ ++ ++ break; ++ } ++ ++ if ((p == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ } ++ } ++#ifdef CONFIG_80211N_HT ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ u8 rf_type; ++ ++ struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p+2); ++ ++ pHT_caps_ie=p; ++ ++ ++ ht_cap = _TRUE; ++ network_type |= WIRELESS_11_24N; ++ ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ if((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || ++ (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) ++ { ++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2)); ++ } ++ else ++ { ++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); ++ } ++ ++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & 0x03); //set Max Rx AMPDU size to 64K ++ ++ if(rf_type == RF_1T1R) ++ { ++ pht_cap->supp_mcs_set[0] = 0xff; ++ pht_cap->supp_mcs_set[1] = 0x0; ++ } ++ ++ _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p+2, ie_len); ++ ++ } ++ ++ //parsing HT_INFO_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ pHT_info_ie=p; ++ } ++#endif //CONFIG_80211N_HT ++ switch(network_type) ++ { ++ case WIRELESS_11B: ++ pbss_network->NetworkTypeInUse = Ndis802_11DS; ++ break; ++ case WIRELESS_11G: ++ case WIRELESS_11BG: ++ case WIRELESS_11G_24N: ++ case WIRELESS_11BG_24N: ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; ++ break; ++ case WIRELESS_11A: ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM5; ++ break; ++ default : ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; ++ break; ++ } ++ ++ pmlmepriv->cur_network.network_type = network_type; ++ ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->htpriv.ht_option = _FALSE; ++ ++ if( (psecuritypriv->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) || ++ (psecuritypriv->wpa_pairwise_cipher&WPA_CIPHER_TKIP)) ++ { ++ //todo: ++ //ht_cap = _FALSE; ++ } ++ ++ //ht_cap ++ if(pregistrypriv->ht_enable && ht_cap==_TRUE) ++ { ++ pmlmepriv->htpriv.ht_option = _TRUE; ++ pmlmepriv->qospriv.qos_option = 1; ++ ++ if(pregistrypriv->ampdu_enable==1) ++ { ++ pmlmepriv->htpriv.ampdu_enable = _TRUE; ++ } ++ ++ HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie); ++ ++ HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie); ++ } ++#endif ++ ++ ++ pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); ++ ++ //issue beacon to start bss network ++ start_bss_network(padapter, (u8*)pbss_network); ++ ++ ++ //alloc sta_info for ap itself ++ psta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); ++ if(!psta) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); ++ if (psta == NULL) ++ { ++ return _FAIL; ++ } ++ } ++ psta->state |= WIFI_AP_STATE; //Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 ++ rtw_indicate_connect( padapter); ++ ++ pmlmepriv->cur_network.join_res = _TRUE;//for check if already set beacon ++ ++ //update bc/mc sta_info ++ //update_bmc_sta(padapter); ++ ++ return ret; ++ ++} ++ ++void rtw_set_macaddr_acl(_adapter *padapter, int mode) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ ++ DBG_871X("%s, mode=%d\n", __func__, mode); ++ ++ pacl_list->mode = mode; ++} ++ ++int rtw_acl_add_sta(_adapter *padapter, u8 *addr) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ u8 added = _FALSE; ++ int i, ret=0; ++ struct rtw_wlan_acl_node *paclnode; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ _queue *pacl_node_q =&pacl_list->acl_node_q; ++ ++ DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr)); ++ ++ if((NUM_ACL-1) < pacl_list->num) ++ return (-1); ++ ++ ++ _enter_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ phead = get_list_head(pacl_node_q); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN)) ++ { ++ if(paclnode->valid == _TRUE) ++ { ++ added = _TRUE; ++ DBG_871X("%s, sta has been added\n", __func__); ++ break; ++ } ++ } ++ } ++ ++ _exit_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ ++ if(added == _TRUE) ++ return ret; ++ ++ ++ _enter_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ for(i=0; i< NUM_ACL; i++) ++ { ++ paclnode = &pacl_list->aclnode[i]; ++ ++ if(paclnode->valid == _FALSE) ++ { ++ _rtw_init_listhead(&paclnode->list); ++ ++ _rtw_memcpy(paclnode->addr, addr, ETH_ALEN); ++ ++ paclnode->valid = _TRUE; ++ ++ rtw_list_insert_tail(&paclnode->list, get_list_head(pacl_node_q)); ++ ++ pacl_list->num++; ++ ++ break; ++ } ++ } ++ ++ DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num); ++ ++ _exit_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ return ret; ++} ++ ++int rtw_acl_remove_sta(_adapter *padapter, u8 *addr) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ int i, ret=0; ++ struct rtw_wlan_acl_node *paclnode; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ _queue *pacl_node_q =&pacl_list->acl_node_q; ++ ++ DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr)); ++ ++ _enter_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ phead = get_list_head(pacl_node_q); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN)) ++ { ++ if(paclnode->valid == _TRUE) ++ { ++ paclnode->valid = _FALSE; ++ ++ rtw_list_delete(&paclnode->list); ++ ++ pacl_list->num--; ++ } ++ } ++ } ++ ++ _exit_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ ++static void update_bcn_fixed_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_erpinfo_ie(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); ++ unsigned char *p, *ie = pnetwork->IEs; ++ u32 len = 0; ++ ++ DBG_871X("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable); ++ ++ if(!pmlmeinfo->ERP_enable) ++ return; ++ ++ //parsing ERP_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if(p && len>0) ++ { ++ PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p; ++ ++ if (pmlmepriv->num_sta_non_erp == 1) ++ pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION; ++ else ++ pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION); ++ ++ if(pmlmepriv->num_sta_no_short_preamble > 0) ++ pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE; ++ else ++ pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE); ++ ++ ERP_IE_handler(padapter, pIE); ++ } ++ ++} ++ ++static void update_bcn_htcap_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_htinfo_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_rsn_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wpa_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wmm_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wps_ie(_adapter *padapter) ++{ ++ u8 *pwps_ie=NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie=NULL; ++ uint wps_ielen=0, wps_offset, remainder_ielen; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); ++ unsigned char *ie = pnetwork->IEs; ++ u32 ielen = pnetwork->IELength; ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pwps_ie = rtw_get_wps_ie(ie+_FIXED_IE_LENGTH_, ielen-_FIXED_IE_LENGTH_, NULL, &wps_ielen); ++ ++ if(pwps_ie==NULL || wps_ielen==0) ++ return; ++ ++ wps_offset = (uint)(pwps_ie-ie); ++ ++ premainder_ie = pwps_ie + wps_ielen; ++ ++ remainder_ielen = ielen - wps_offset - wps_ielen; ++ ++ if(remainder_ielen>0) ++ { ++ pbackup_remainder_ie = rtw_malloc(remainder_ielen); ++ if(pbackup_remainder_ie) ++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); ++ } ++ ++ ++ pwps_ie_src = pmlmepriv->wps_beacon_ie; ++ if(pwps_ie_src == NULL) ++ return; ++ ++ ++ wps_ielen = (uint)pwps_ie_src[1];//to get ie data len ++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen+2); ++ pwps_ie += (wps_ielen+2); ++ ++ if(pbackup_remainder_ie) ++ _rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen); ++ ++ //update IELength ++ pnetwork->IELength = wps_offset + (wps_ielen+2) + remainder_ielen; ++ } ++ ++ if(pbackup_remainder_ie) ++ rtw_mfree(pbackup_remainder_ie, remainder_ielen); ++ ++} ++ ++static void update_bcn_p2p_ie(_adapter *padapter) ++{ ++ ++} ++ ++static void update_bcn_vendor_spec_ie(_adapter *padapter, u8*oui) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if(_rtw_memcmp(RTW_WPA_OUI, oui, 4)) ++ { ++ update_bcn_wpa_ie(padapter); ++ } ++ else if(_rtw_memcmp(WMM_OUI, oui, 4)) ++ { ++ update_bcn_wmm_ie(padapter); ++ } ++ else if(_rtw_memcmp(WPS_OUI, oui, 4)) ++ { ++ update_bcn_wps_ie(padapter); ++ } ++ else if(_rtw_memcmp(P2P_OUI, oui, 4)) ++ { ++ update_bcn_p2p_ie(padapter); ++ } ++ else ++ { ++ DBG_871X("unknown OUI type!\n"); ++ } ++ ++ ++} ++ ++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv; ++ struct mlme_ext_priv *pmlmeext; ++ //struct mlme_ext_info *pmlmeinfo; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if(!padapter) ++ return; ++ ++ pmlmepriv = &(padapter->mlmepriv); ++ pmlmeext = &(padapter->mlmeextpriv); ++ //pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(_FALSE == pmlmeext->bstart_bss) ++ return; ++ ++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++ switch(ie_id) ++ { ++ case 0xFF: ++ ++ update_bcn_fixed_ie(padapter);//8: TimeStamp, 2: Beacon Interval 2:Capability ++ ++ break; ++ ++ case _TIM_IE_: ++ ++ update_BCNTIM(padapter); ++ ++ break; ++ ++ case _ERPINFO_IE_: ++ ++ update_bcn_erpinfo_ie(padapter); ++ ++ break; ++ ++ case _HT_CAPABILITY_IE_: ++ ++ update_bcn_htcap_ie(padapter); ++ ++ break; ++ ++ case _RSN_IE_2_: ++ ++ update_bcn_rsn_ie(padapter); ++ ++ break; ++ ++ case _HT_ADD_INFO_IE_: ++ ++ update_bcn_htinfo_ie(padapter); ++ ++ break; ++ ++ case _VENDOR_SPECIFIC_IE_: ++ ++ update_bcn_vendor_spec_ie(padapter, oui); ++ ++ break; ++ ++ default: ++ break; ++ } ++ ++ pmlmepriv->update_bcn = _TRUE; ++ ++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++#ifndef CONFIG_INTERRUPT_BASED_TXBCN ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ if(tx) ++ { ++ //send_beacon(padapter);//send_beacon must execute on TSR level ++ set_tx_beacon_cmd(padapter); ++ } ++#else ++ { ++ //PCI will issue beacon when BCN interrupt occurs. ++ } ++#endif ++#endif //!CONFIG_INTERRUPT_BASED_TXBCN ++ ++} ++ ++#ifdef CONFIG_80211N_HT ++ ++/* ++op_mode ++Set to 0 (HT pure) under the followign conditions ++ - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or ++ - all STAs in the BSS are 20 MHz HT in 20 MHz BSS ++Set to 1 (HT non-member protection) if there may be non-HT STAs ++ in both the primary and the secondary channel ++Set to 2 if only HT STAs are associated in BSS, ++ however and at least one 20 MHz HT STA is associated ++Set to 3 (HT mixed mode) when one or more non-HT STAs are associated ++ (currently non-GF HT station is considered as non-HT STA also) ++*/ ++static int rtw_ht_operation_update(_adapter *padapter) ++{ ++ u16 cur_op_mode, new_op_mode; ++ int op_mode_changes = 0; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; ++ ++ if(pmlmepriv->htpriv.ht_option == _TRUE) ++ return 0; ++ ++ //if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed) ++ // return 0; ++ ++ DBG_871X("%s current operation mode=0x%X\n", ++ __FUNCTION__, pmlmepriv->ht_op_mode); ++ ++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) ++ && pmlmepriv->num_sta_ht_no_gf) { ++ pmlmepriv->ht_op_mode |= ++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; ++ op_mode_changes++; ++ } else if ((pmlmepriv->ht_op_mode & ++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) && ++ pmlmepriv->num_sta_ht_no_gf == 0) { ++ pmlmepriv->ht_op_mode &= ++ ~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; ++ op_mode_changes++; ++ } ++ ++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && ++ (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) { ++ pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; ++ op_mode_changes++; ++ } else if ((pmlmepriv->ht_op_mode & ++ HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && ++ (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) { ++ pmlmepriv->ht_op_mode &= ++ ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; ++ op_mode_changes++; ++ } ++ ++ /* Note: currently we switch to the MIXED op mode if HT non-greenfield ++ * station is associated. Probably it's a theoretical case, since ++ * it looks like all known HT STAs support greenfield. ++ */ ++ new_op_mode = 0; ++ if (pmlmepriv->num_sta_no_ht || ++ (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)) ++ new_op_mode = OP_MODE_MIXED; ++ else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ++ && pmlmepriv->num_sta_ht_20mhz) ++ new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED; ++ else if (pmlmepriv->olbc_ht) ++ new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS; ++ else ++ new_op_mode = OP_MODE_PURE; ++ ++ cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; ++ if (cur_op_mode != new_op_mode) { ++ pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK; ++ pmlmepriv->ht_op_mode |= new_op_mode; ++ op_mode_changes++; ++ } ++ ++ DBG_871X("%s new operation mode=0x%X changes=%d\n", ++ __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes); ++ ++ return op_mode_changes; ++ ++} ++ ++#endif /* CONFIG_80211N_HT */ ++ ++void associated_clients_update(_adapter *padapter, u8 updated) ++{ ++ //update associcated stations cap. ++ if(updated == _TRUE) ++ { ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //check asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ VCS_update(padapter, psta); ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ ++} ++ ++/* called > TSR LEVEL for USB or SDIO Interface*/ ++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) ++{ ++ u8 beacon_updated = _FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ ++#if 0 ++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) && ++ !psta->no_short_preamble_set) { ++ psta->no_short_preamble_set = 1; ++ pmlmepriv->num_sta_no_short_preamble++; ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 1)) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ ++ if(!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) ++ { ++ if(!psta->no_short_preamble_set) ++ { ++ psta->no_short_preamble_set = 1; ++ ++ pmlmepriv->num_sta_no_short_preamble++; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 1)) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ ++ } ++ } ++ else ++ { ++ if(psta->no_short_preamble_set) ++ { ++ psta->no_short_preamble_set = 0; ++ ++ pmlmepriv->num_sta_no_short_preamble--; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 0)) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ ++ } ++ } ++ ++#if 0 ++ if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) { ++ psta->nonerp_set = 1; ++ pmlmepriv->num_sta_non_erp++; ++ if (pmlmepriv->num_sta_non_erp == 1) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ if(psta->flags & WLAN_STA_NONERP) ++ { ++ if(!psta->nonerp_set) ++ { ++ psta->nonerp_set = 1; ++ ++ pmlmepriv->num_sta_non_erp++; ++ ++ if (pmlmepriv->num_sta_non_erp == 1) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ } ++ ++ } ++ else ++ { ++ if(psta->nonerp_set) ++ { ++ psta->nonerp_set = 0; ++ ++ pmlmepriv->num_sta_non_erp--; ++ ++ if (pmlmepriv->num_sta_non_erp == 0) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ } ++ ++ } ++ ++ ++#if 0 ++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) && ++ !psta->no_short_slot_time_set) { ++ psta->no_short_slot_time_set = 1; ++ pmlmepriv->num_sta_no_short_slot_time++; ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 1)) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ if(!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) ++ { ++ if(!psta->no_short_slot_time_set) ++ { ++ psta->no_short_slot_time_set = 1; ++ ++ pmlmepriv->num_sta_no_short_slot_time++; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 1)) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ ++ } ++ } ++ else ++ { ++ if(psta->no_short_slot_time_set) ++ { ++ psta->no_short_slot_time_set = 0; ++ ++ pmlmepriv->num_sta_no_short_slot_time--; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 0)) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ } ++ } ++ ++#ifdef CONFIG_80211N_HT ++ ++ if (psta->flags & WLAN_STA_HT) ++ { ++ u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); ++ ++ DBG_871X("HT: STA " MAC_FMT " HT Capabilities " ++ "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); ++ ++ if (psta->no_ht_set) { ++ psta->no_ht_set = 0; ++ pmlmepriv->num_sta_no_ht--; ++ } ++ ++ if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { ++ if (!psta->no_ht_gf_set) { ++ psta->no_ht_gf_set = 1; ++ pmlmepriv->num_sta_ht_no_gf++; ++ } ++ DBG_871X("%s STA " MAC_FMT " - no " ++ "greenfield, num of non-gf stations %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_ht_no_gf); ++ } ++ ++ if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { ++ if (!psta->ht_20mhz_set) { ++ psta->ht_20mhz_set = 1; ++ pmlmepriv->num_sta_ht_20mhz++; ++ } ++ DBG_871X("%s STA " MAC_FMT " - 20 MHz HT, " ++ "num of 20MHz HT STAs %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_ht_20mhz); ++ } ++ ++ } ++ else ++ { ++ if (!psta->no_ht_set) { ++ psta->no_ht_set = 1; ++ pmlmepriv->num_sta_no_ht++; ++ } ++ if(pmlmepriv->htpriv.ht_option == _TRUE) { ++ DBG_871X("%s STA " MAC_FMT ++ " - no HT, num of non-HT stations %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_no_ht); ++ } ++ } ++ ++ if (rtw_ht_operation_update(padapter) > 0) ++ { ++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); ++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); ++ } ++ ++#endif /* CONFIG_80211N_HT */ ++ ++ //update associcated stations cap. ++ associated_clients_update(padapter, beacon_updated); ++ ++ DBG_871X("%s, updated=%d\n", __func__, beacon_updated); ++ ++} ++ ++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) ++{ ++ u8 beacon_updated = _FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ if(!psta) ++ return beacon_updated; ++ ++ if (psta->no_short_preamble_set) { ++ psta->no_short_preamble_set = 0; ++ pmlmepriv->num_sta_no_short_preamble--; ++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B ++ && pmlmepriv->num_sta_no_short_preamble == 0) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ } ++ ++ if (psta->nonerp_set) { ++ psta->nonerp_set = 0; ++ pmlmepriv->num_sta_non_erp--; ++ if (pmlmepriv->num_sta_non_erp == 0) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ } ++ ++ if (psta->no_short_slot_time_set) { ++ psta->no_short_slot_time_set = 0; ++ pmlmepriv->num_sta_no_short_slot_time--; ++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B ++ && pmlmepriv->num_sta_no_short_slot_time == 0) ++ { ++ beacon_updated = _TRUE; ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ } ++ ++#ifdef CONFIG_80211N_HT ++ ++ if (psta->no_ht_gf_set) { ++ psta->no_ht_gf_set = 0; ++ pmlmepriv->num_sta_ht_no_gf--; ++ } ++ ++ if (psta->no_ht_set) { ++ psta->no_ht_set = 0; ++ pmlmepriv->num_sta_no_ht--; ++ } ++ ++ if (psta->ht_20mhz_set) { ++ psta->ht_20mhz_set = 0; ++ pmlmepriv->num_sta_ht_20mhz--; ++ } ++ ++ if (rtw_ht_operation_update(padapter) > 0) ++ { ++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); ++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); ++ } ++ ++#endif /* CONFIG_80211N_HT */ ++ ++ //update associcated stations cap. ++ //associated_clients_update(padapter, beacon_updated); //move it to avoid deadlock ++ ++ DBG_871X("%s, updated=%d\n", __func__, beacon_updated); ++ ++ return beacon_updated; ++ ++} ++ ++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason) ++{ ++ _irqL irqL; ++ u8 beacon_updated = _FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(!psta) ++ return beacon_updated; ++ ++ if (active == _TRUE) ++ { ++#ifdef CONFIG_80211N_HT ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ ++#endif //CONFIG_80211N_HT ++ ++ issue_deauth(padapter, psta->hwaddr, reason); ++ } ++ ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ ++ //report_del_sta_event(padapter, psta->hwaddr, reason); ++ ++ //clear cam entry / key ++ //clear_cam_entry(padapter, (psta->mac_id + 3)); ++ rtw_clearstakey_cmd(padapter, (u8*)psta, (u8)(psta->mac_id + 3), _TRUE); ++ ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ psta->state &= ~_FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ #ifdef CONFIG_IOCTL_CFG80211 ++ if (1) { ++ #ifdef COMPAT_KERNEL_RELEASE ++ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); ++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); ++ #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */ ++ #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ } else ++ #endif //CONFIG_IOCTL_CFG80211 ++ { ++ rtw_indicate_sta_disassoc_event(padapter, psta); ++ } ++ ++ report_del_sta_event(padapter, psta->hwaddr, reason); ++ ++ beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ ++ return beacon_updated; ++ ++} ++ ++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return ret; ++ ++ DBG_871X(FUNC_NDEV_FMT" with ch:%u, offset:%u\n", ++ FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset); ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ /* for each sta in asoc_queue */ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ plist = get_next(plist); ++ ++ issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset); ++ psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2); ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset); ++ ++ return ret; ++} ++ ++int rtw_sta_flush(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 chk_alive_num = 0; ++ char chk_alive_list[NUM_STA]; ++ int i; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return ret; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { ++ int stainfo_offset; ++ ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ plist = get_next(plist); ++ ++ /* Remove sta from asoc_list */ ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ ++ /* Keep sta for ap_free_sta() beyond this asoc_list loop */ ++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta); ++ if (stainfo_offset_valid(stainfo_offset)) { ++ chk_alive_list[chk_alive_num++] = stainfo_offset; ++ } ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ ++ /* For each sta in chk_alive_list, call ap_free_sta */ ++ for (i = 0; i < chk_alive_num; i++) { ++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); ++ ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING); ++ } ++ ++ issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ associated_clients_update(padapter, _TRUE); ++ ++ return ret; ++ ++} ++ ++/* called > TSR LEVEL for USB or SDIO Interface*/ ++void sta_info_update(_adapter *padapter, struct sta_info *psta) ++{ ++ int flags = psta->flags; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ++ //update wmm cap. ++ if(WLAN_STA_WME&flags) ++ psta->qos_option = 1; ++ else ++ psta->qos_option = 0; ++ ++ if(pmlmepriv->qospriv.qos_option == 0) ++ psta->qos_option = 0; ++ ++ ++#ifdef CONFIG_80211N_HT ++ //update 802.11n ht cap. ++ if(WLAN_STA_HT&flags) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ psta->qos_option = 1; ++ } ++ else ++ { ++ psta->htpriv.ht_option = _FALSE; ++ } ++ ++ if(pmlmepriv->htpriv.ht_option == _FALSE) ++ psta->htpriv.ht_option = _FALSE; ++#endif ++ ++ ++ update_sta_info_apmode(padapter, psta); ++ ++ ++} ++ ++/* called >= TSR LEVEL for USB or SDIO Interface*/ ++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) ++{ ++ if(psta->state & _FW_LINKED) ++ { ++ //add ratid ++ add_RATid(padapter, psta, 0);//DM_RATR_STA_INIT ++ } ++} ++/* restore hw setting from sw data structures */ ++void rtw_ap_restore_network(_adapter *padapter) ++{ ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ _irqL irqL; ++ _list *phead, *plist; ++ u8 chk_alive_num = 0; ++ char chk_alive_list[NUM_STA]; ++ int i; ++ ++ rtw_setopmode_cmd(padapter, Ndis802_11APMode,_FALSE); ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ start_bss_network(padapter, (u8*)&mlmepriv->cur_network.network); ++ ++ if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) ++ { ++ /* restore group key, WEP keys is restored in ips_leave() */ ++ rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0,_FALSE); ++ } ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { ++ int stainfo_offset; ++ ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ plist = get_next(plist); ++ ++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta); ++ if (stainfo_offset_valid(stainfo_offset)) { ++ chk_alive_list[chk_alive_num++] = stainfo_offset; ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ for (i = 0; i < chk_alive_num; i++) { ++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); ++ ++ if (psta == NULL) { ++ DBG_871X(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter)); ++ } ++ else if(psta->state &_FW_LINKED) ++ { ++ Update_RA_Entry(padapter, psta); ++ //pairwise key ++ /* per sta pairwise key and settings */ ++ if( (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) ++ { ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE,_FALSE); ++ } ++ } ++ } ++ ++} ++ ++void start_ap_mode(_adapter *padapter) ++{ ++ int i; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ ++ pmlmepriv->update_bcn = _FALSE; ++ ++ //init_mlme_ap_info(padapter); ++ pmlmeext->bstart_bss = _FALSE; ++ ++ pmlmepriv->num_sta_non_erp = 0; ++ ++ pmlmepriv->num_sta_no_short_slot_time = 0; ++ ++ pmlmepriv->num_sta_no_short_preamble = 0; ++ ++ pmlmepriv->num_sta_ht_no_gf = 0; ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->num_sta_no_ht = 0; ++#endif //CONFIG_80211N_HT ++ pmlmepriv->num_sta_ht_20mhz = 0; ++ ++ pmlmepriv->olbc = _FALSE; ++ ++ pmlmepriv->olbc_ht = _FALSE; ++ ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->ht_op_mode = 0; ++#endif ++ ++ for(i=0; ista_aid[i] = NULL; ++ ++ pmlmepriv->wps_beacon_ie = NULL; ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ ++ pmlmepriv->p2p_beacon_ie = NULL; ++ pmlmepriv->p2p_probe_resp_ie = NULL; ++ ++ ++ //for ACL ++ _rtw_init_listhead(&(pacl_list->acl_node_q.queue)); ++ pacl_list->num = 0; ++ pacl_list->mode = 0; ++ for(i = 0; i < NUM_ACL; i++) ++ { ++ _rtw_init_listhead(&pacl_list->aclnode[i].list); ++ pacl_list->aclnode[i].valid = _FALSE; ++ } ++ ++} ++ ++void stop_ap_mode(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ struct rtw_wlan_acl_node *paclnode; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ _queue *pacl_node_q =&pacl_list->acl_node_q; ++ ++ pmlmepriv->update_bcn = _FALSE; ++ pmlmeext->bstart_bss = _FALSE; ++ //_rtw_spinlock_free(&pmlmepriv->bcn_update_lock); ++ ++ //reset and init security priv , this can refine with rtw_reset_securitypriv ++ _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; ++ ++ //for ACL ++ _enter_critical_bh(&(pacl_node_q->lock), &irqL); ++ phead = get_list_head(pacl_node_q); ++ plist = get_next(phead); ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); ++ plist = get_next(plist); ++ ++ if(paclnode->valid == _TRUE) ++ { ++ paclnode->valid = _FALSE; ++ ++ rtw_list_delete(&paclnode->list); ++ ++ pacl_list->num--; ++ } ++ } ++ _exit_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ DBG_871X("%s, free acl_node_queue, num=%d\n", __func__, pacl_list->num); ++ ++ rtw_sta_flush(padapter); ++ ++ //free_assoc_sta_resources ++ rtw_free_all_stainfo(padapter); ++ ++ psta = rtw_get_bcmc_stainfo(padapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ rtw_init_bcmc_stainfo(padapter); ++ ++ rtw_free_mlme_priv_ie_data(pmlmepriv); ++ ++} ++ ++#endif //CONFIG_NATIVEAP_MLME ++#endif //CONFIG_AP_MODE ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_br_ext.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_br_ext.c +new file mode 100644 +index 00000000..44ff8275 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_br_ext.c +@@ -0,0 +1,1700 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_BR_EXT_C_ ++ ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#if 1 // rtw_wifi_driver ++#include ++#include ++#include "rtw_br_ext.h" ++#else // rtw_wifi_driver ++#include "./8192cd_cfg.h" ++ ++#ifndef __KERNEL__ ++#include "./sys-support.h" ++#endif ++ ++#include "./8192cd.h" ++#include "./8192cd_headers.h" ++#include "./8192cd_br_ext.h" ++#include "./8192cd_debug.h" ++#endif // rtw_wifi_driver ++ ++#ifdef CL_IPV6_PASS ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#endif ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ ++//#define BR_EXT_DEBUG ++ ++#define NAT25_IPV4 01 ++#define NAT25_IPV6 02 ++#define NAT25_IPX 03 ++#define NAT25_APPLE 04 ++#define NAT25_PPPOE 05 ++ ++#define RTL_RELAY_TAG_LEN (ETH_ALEN) ++#define TAG_HDR_LEN 4 ++ ++#define MAGIC_CODE 0x8186 ++#define MAGIC_CODE_LEN 2 ++#define WAIT_TIME_PPPOE 5 // waiting time for pppoe server in sec ++ ++/*----------------------------------------------------------------- ++ How database records network address: ++ 0 1 2 3 4 5 6 7 8 9 10 ++ |----|----|----|----|----|----|----|----|----|----|----| ++ IPv4 |type| | IP addr | ++ IPX |type| Net addr | Node addr | ++ IPX |type| Net addr |Sckt addr| ++ Apple |type| Network |node| ++ PPPoE |type| SID | AC MAC | ++-----------------------------------------------------------------*/ ++ ++ ++//Find a tag in pppoe frame and return the pointer ++static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type) ++{ ++ unsigned char *cur_ptr, *start_ptr; ++ unsigned short tagLen, tagType; ++ ++ start_ptr = cur_ptr = (unsigned char *)ph->tag; ++ while((cur_ptr - start_ptr) < ntohs(ph->length)) { ++ // prevent un-alignment access ++ tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]); ++ tagLen = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]); ++ if(tagType == type) ++ return cur_ptr; ++ cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen; ++ } ++ return 0; ++} ++ ++ ++static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag) ++{ ++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); ++ int data_len; ++ ++ data_len = tag->tag_len + TAG_HDR_LEN; ++ if (skb_tailroom(skb) < data_len) { ++ _DEBUG_ERR("skb_tailroom() failed in add SID tag!\n"); ++ return -1; ++ } ++ ++ skb_put(skb, data_len); ++ // have a room for new tag ++ memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); ++ ph->length = htons(ntohs(ph->length) + data_len); ++ memcpy((unsigned char *)ph->tag, tag, data_len); ++ return data_len; ++} ++ ++static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len) ++{ ++ int tail_len; ++ unsigned long end, tail; ++ ++ if ((src+len) > skb_tail_pointer(skb) || skb->len < len) ++ return -1; ++ ++ tail = (unsigned long)skb_tail_pointer(skb); ++ end = (unsigned long)src+len; ++ if (tail < end) ++ return -1; ++ ++ tail_len = (int)(tail-end); ++ if (tail_len > 0) ++ memmove(src, src+len, tail_len); ++ ++ skb_trim(skb, skb->len-len); ++ return 0; ++} ++ ++static __inline__ unsigned long __nat25_timeout(_adapter *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies - NAT25_AGEING_TIME*HZ; ++ ++ return timeout; ++} ++ ++ ++static __inline__ int __nat25_has_expired(_adapter *priv, ++ struct nat25_network_db_entry *fdb) ++{ ++ if(time_before_eq(fdb->ageing_timer, __nat25_timeout(priv))) ++ return 1; ++ ++ return 0; ++} ++ ++ ++static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr, ++ unsigned int *ipAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPV4; ++ memcpy(networkAddr+7, (unsigned char *)ipAddr, 4); ++} ++ ++ ++static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, ++ unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPX; ++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); ++ memcpy(networkAddr+5, ipxNodeAddr, 6); ++} ++ ++ ++static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr, ++ unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPX; ++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); ++ memcpy(networkAddr+5, (unsigned char *)ipxSocketAddr, 2); ++} ++ ++ ++static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, ++ unsigned short *network, unsigned char *node) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_APPLE; ++ memcpy(networkAddr+1, (unsigned char *)network, 2); ++ networkAddr[3] = *node; ++} ++ ++ ++static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr, ++ unsigned char *ac_mac, unsigned short *sid) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_PPPOE; ++ memcpy(networkAddr+1, (unsigned char *)sid, 2); ++ memcpy(networkAddr+3, (unsigned char *)ac_mac, 6); ++} ++ ++ ++#ifdef CL_IPV6_PASS ++static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr, ++ unsigned int *ipAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPV6; ++ memcpy(networkAddr+1, (unsigned char *)ipAddr, 16); ++} ++ ++ ++static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b) ++{ ++ while (len > 0) { ++ if (*data == tag && *(data+1) == len8b && len >= len8b*8) ++ return data+2; ++ ++ len -= (*(data+1))*8; ++ data += (*(data+1))*8; ++ } ++ return NULL; ++} ++ ++ ++static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac) ++{ ++ struct icmp6hdr *icmphdr = (struct icmp6hdr *)data; ++ unsigned char *mac; ++ ++ if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) { ++ if (len >= 8) { ++ mac = scan_tlv(&data[8], len-8, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) { ++ if (len >= 16) { ++ mac = scan_tlv(&data[16], len-16, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { ++ if (len >= 24) { ++ mac = scan_tlv(&data[24], len-24, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) { ++ if (len >= 24) { ++ mac = scan_tlv(&data[24], len-24, 2, 1); ++ if (mac) { ++ _DEBUG_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_REDIRECT) { ++ if (len >= 40) { ++ mac = scan_tlv(&data[40], len-40, 2, 1); ++ if (mac) { ++ _DEBUG_INFO("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ return 0; ++} ++ ++ ++static void convert_ipv6_mac_to_mc(struct sk_buff *skb) ++{ ++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); ++ unsigned char *dst_mac = skb->data; ++ ++ //dst_mac[0] = 0xff; ++ //dst_mac[1] = 0xff; ++ /*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/ ++ dst_mac[0] = 0x33; ++ dst_mac[1] = 0x33; ++ memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4); ++ #if defined(__LINUX_2_6__) ++ /*modified by qinjunjie,warning:should not remove next line*/ ++ skb->pkt_type = PACKET_MULTICAST; ++ #endif ++} ++#endif /* CL_IPV6_PASS */ ++ ++ ++static __inline__ int __nat25_network_hash(unsigned char *networkAddr) ++{ ++ if(networkAddr[0] == NAT25_IPV4) ++ { ++ unsigned long x; ++ ++ x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_IPX) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ ++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_APPLE) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_PPPOE) ++ { ++ unsigned long x; ++ ++ x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++#ifdef CL_IPV6_PASS ++ else if(networkAddr[0] == NAT25_IPV6) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ ++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^ ++ networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^ ++ networkAddr[16]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++#endif ++ else ++ { ++ unsigned long x = 0; ++ int i; ++ ++ for (i=0; ibr_ext_lock, &irqL); ++ ++ ent->next_hash = priv->nethash[hash]; ++ if(ent->next_hash != NULL) ++ ent->next_hash->pprev_hash = &ent->next_hash; ++ priv->nethash[hash] = ent; ++ ent->pprev_hash = &priv->nethash[hash]; ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) ++{ ++ // Caller must _enter_critical_bh already! ++ //_irqL irqL; ++ //_enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ *(ent->pprev_hash) = ent->next_hash; ++ if(ent->next_hash != NULL) ++ ent->next_hash->pprev_hash = ent->pprev_hash; ++ ent->next_hash = NULL; ++ ent->pprev_hash = NULL; ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static int __nat25_db_network_lookup_and_replace(_adapter *priv, ++ struct sk_buff *skb, unsigned char *networkAddr) ++{ ++ struct nat25_network_db_entry *db; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ db = priv->nethash[__nat25_network_hash(networkAddr)]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) ++ { ++ if(!__nat25_has_expired(priv, db)) ++ { ++ // replace the destination mac address ++ memcpy(skb->data, db->macAddr, ETH_ALEN); ++ atomic_inc(&db->use_count); ++ ++#ifdef CL_IPV6_PASS ++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10], ++ db->networkAddr[11], ++ db->networkAddr[12], ++ db->networkAddr[13], ++ db->networkAddr[14], ++ db->networkAddr[15], ++ db->networkAddr[16]); ++#else ++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10]); ++#endif ++ } ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return 1; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return 0; ++} ++ ++ ++static void __nat25_db_network_insert(_adapter *priv, ++ unsigned char *macAddr, unsigned char *networkAddr) ++{ ++ struct nat25_network_db_entry *db; ++ int hash; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ hash = __nat25_network_hash(networkAddr); ++ db = priv->nethash[hash]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) ++ { ++ memcpy(db->macAddr, macAddr, ETH_ALEN); ++ db->ageing_timer = jiffies; ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db)); ++ if(db == NULL) { ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return; ++ } ++ ++ memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); ++ memcpy(db->macAddr, macAddr, ETH_ALEN); ++ atomic_set(&db->use_count, 1); ++ db->ageing_timer = jiffies; ++ ++ __network_hash_link(priv, db, hash); ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static void __nat25_db_print(_adapter *priv) ++{ ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++#ifdef BR_EXT_DEBUG ++ static int counter = 0; ++ int i, j; ++ struct nat25_network_db_entry *db; ++ ++ counter++; ++ if((counter % 16) != 0) ++ return; ++ ++ for(i=0, j=0; inethash[i]; ++ ++ while (db != NULL) ++ { ++#ifdef CL_IPV6_PASS ++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ j, ++ i, ++ atomic_read(&db->use_count), ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10], ++ db->networkAddr[11], ++ db->networkAddr[12], ++ db->networkAddr[13], ++ db->networkAddr[14], ++ db->networkAddr[15], ++ db->networkAddr[16]); ++#else ++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ j, ++ i, ++ atomic_read(&db->use_count), ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10]); ++#endif ++ j++; ++ ++ db = db->next_hash; ++ } ++ } ++#endif ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++ ++ ++/* ++ * NAT2.5 interface ++ */ ++ ++void nat25_db_cleanup(_adapter *priv) ++{ ++ int i; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ for(i=0; inethash[i]; ++ while (f != NULL) { ++ struct nat25_network_db_entry *g; ++ ++ g = f->next_hash; ++ if(priv->scdb_entry == f) ++ { ++ memset(priv->scdb_mac, 0, ETH_ALEN); ++ memset(priv->scdb_ip, 0, 4); ++ priv->scdb_entry = NULL; ++ } ++ __network_hash_unlink(f); ++ rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); ++ ++ f = g; ++ } ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++void nat25_db_expire(_adapter *priv) ++{ ++ int i; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ //if(!priv->ethBrExtInfo.nat25_disable) ++ { ++ for (i=0; inethash[i]; ++ ++ while (f != NULL) ++ { ++ struct nat25_network_db_entry *g; ++ g = f->next_hash; ++ ++ if(__nat25_has_expired(priv, f)) ++ { ++ if(atomic_dec_and_test(&f->use_count)) ++ { ++#ifdef BR_EXT_DEBUG ++#ifdef CL_IPV6_PASS ++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ i, ++ f->macAddr[0], ++ f->macAddr[1], ++ f->macAddr[2], ++ f->macAddr[3], ++ f->macAddr[4], ++ f->macAddr[5], ++ f->networkAddr[0], ++ f->networkAddr[1], ++ f->networkAddr[2], ++ f->networkAddr[3], ++ f->networkAddr[4], ++ f->networkAddr[5], ++ f->networkAddr[6], ++ f->networkAddr[7], ++ f->networkAddr[8], ++ f->networkAddr[9], ++ f->networkAddr[10], ++ f->networkAddr[11], ++ f->networkAddr[12], ++ f->networkAddr[13], ++ f->networkAddr[14], ++ f->networkAddr[15], ++ f->networkAddr[16]); ++#else ++ ++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ i, ++ f->macAddr[0], ++ f->macAddr[1], ++ f->macAddr[2], ++ f->macAddr[3], ++ f->macAddr[4], ++ f->macAddr[5], ++ f->networkAddr[0], ++ f->networkAddr[1], ++ f->networkAddr[2], ++ f->networkAddr[3], ++ f->networkAddr[4], ++ f->networkAddr[5], ++ f->networkAddr[6], ++ f->networkAddr[7], ++ f->networkAddr[8], ++ f->networkAddr[9], ++ f->networkAddr[10]); ++#endif ++#endif ++ if(priv->scdb_entry == f) ++ { ++ memset(priv->scdb_mac, 0, ETH_ALEN); ++ memset(priv->scdb_ip, 0, 4); ++ priv->scdb_entry = NULL; ++ } ++ __network_hash_unlink(f); ++ rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); ++ } ++ } ++ ++ f = g; ++ } ++ } ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++#ifdef SUPPORT_TX_MCAST2UNI ++static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip) ++{ ++ struct stat_info *pstat; ++ struct list_head *phead, *plist; ++ int i; ++ ++ phead = &priv->asoc_list; ++ plist = phead->next; ++ ++ while (plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ plist = plist->next; ++ ++ if (pstat->ipmc_num == 0) ++ continue; ++ ++ for (i=0; iipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip)+1, 3)) { ++ memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN); ++ return 1; ++ } ++ } ++ } ++ return 0; ++} ++#endif ++ ++int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) ++{ ++ unsigned short protocol; ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++ ++ if(skb == NULL) ++ return -1; ++ ++ if((method <= NAT25_MIN) || (method >= NAT25_MAX)) ++ return -1; ++ ++ protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); ++ ++ /*---------------------------------------------------*/ ++ /* Handle IP frame */ ++ /*---------------------------------------------------*/ ++ if(protocol == __constant_htons(ETH_P_IP)) ++ { ++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); ++ ++ if(((unsigned char*)(iph) + (iph->ihl<<2)) >= (skb->data + ETH_HLEN + skb->len)) ++ { ++ DEBUG_WARN("NAT25: malformed IP packet !\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ //some muticast with source IP is all zero, maybe other case is illegal ++ //in class A, B, C, host address is all zero or all one is illegal ++ if (iph->saddr == 0) ++ return 0; ++ DEBUG_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); ++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr); ++ //record source IP address and , source mac address into db ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); ++#ifdef SUPPORT_TX_MCAST2UNI ++ if (priv->pshare->rf_ft_var.mc2u_disable || ++ ((((OPMODE & (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ++ == (WIFI_STATION_STATE|WIFI_ASOC_STATE)) && ++ !checkIPMcAndReplace(priv, skb, &iph->daddr)) || ++ (OPMODE & WIFI_ADHOC_STATE))) ++#endif ++ { ++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr); ++ ++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { ++ if (*((unsigned char *)&iph->daddr + 3) == 0xff) { ++ // L2 is unicast but L3 is broadcast, make L2 bacome broadcast ++ DEBUG_INFO("NAT25: Set DA as boardcast\n"); ++ memset(skb->data, 0xff, ETH_ALEN); ++ } ++ else { ++ // forward unknow IP packet to upper TCP/IP ++ DEBUG_INFO("NAT25: Replace DA with BR's MAC\n"); ++ if ( (*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac+4)) == 0 ) { ++ void netdev_br_init(struct net_device *netdev); ++ printk("Re-init netdev_br_init() due to br_mac==0!\n"); ++ netdev_br_init(priv->pnetdev); ++ } ++ memcpy(skb->data, priv->br_mac, ETH_ALEN); ++ } ++ } ++ } ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle ARP frame */ ++ /*---------------------------------------------------*/ ++ else if(protocol == __constant_htons(ETH_P_ARP)) ++ { ++ struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN); ++ unsigned char *arp_ptr = (unsigned char *)(arp + 1); ++ unsigned int *sender, *target; ++ ++ if(arp->ar_pro != __constant_htons(ETH_P_IP)) ++ { ++ DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro)); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return 0; // skb_copy for all ARP frame ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0], ++ arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]); ++ ++ // change to ARP sender mac address to wlan STA address ++ memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); ++ ++ arp_ptr += arp->ar_hln; ++ sender = (unsigned int *)arp_ptr; ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, sender); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup ARP\n"); ++ ++ arp_ptr += arp->ar_hln; ++ sender = (unsigned int *)arp_ptr; ++ arp_ptr += (arp->ar_hln + arp->ar_pln); ++ target = (unsigned int *)arp_ptr; ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, target); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // change to ARP target mac address to Lookup result ++ arp_ptr = (unsigned char *)(arp + 1); ++ arp_ptr += (arp->ar_hln + arp->ar_pln); ++ memcpy(arp_ptr, skb->data, ETH_ALEN); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle IPX and Apple Talk frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(ETH_P_IPX)) || ++ (protocol <= __constant_htons(ETH_FRAME_LEN))) ++ { ++ unsigned char ipx_header[2] = {0xFF, 0xFF}; ++ struct ipxhdr *ipx = NULL; ++ struct elapaarp *ea = NULL; ++ struct ddpehdr *ddp = NULL; ++ unsigned char *framePtr = skb->data + ETH_HLEN; ++ ++ if(protocol == __constant_htons(ETH_P_IPX)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet II)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else if(protocol <= __constant_htons(ETH_FRAME_LEN)) ++ { ++ if(!memcmp(ipx_header, framePtr, 2)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else ++ { ++ unsigned char ipx_8022_type = 0xE0; ++ unsigned char snap_8022_type = 0xAA; ++ ++ if(*framePtr == snap_8022_type) ++ { ++ unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; // IPX SNAP ID ++ unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; // Apple Talk AARP SNAP ID ++ unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; // Apple Talk DDP SNAP ID ++ ++ framePtr += 3; // eliminate the 802.2 header ++ ++ if(!memcmp(ipx_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else if(!memcmp(aarp_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ ea = (struct elapaarp *)framePtr; ++ } ++ else if(!memcmp(ddp_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ ddp = (struct ddpehdr *)framePtr; ++ } ++ else ++ { ++ DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0], ++ framePtr[1], framePtr[2], framePtr[3], framePtr[4]); ++ return -1; ++ } ++ } ++ else if(*framePtr == ipx_8022_type) ++ { ++ framePtr += 3; // eliminate the 802.2 header ++ ++ if(!memcmp(ipx_header, framePtr, 2)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else ++ return -1; ++ } ++ else ++ return -1; ++ } ++ } ++ else ++ return -1; ++ ++ /* IPX */ ++ if(ipx != NULL) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Check IPX skb_copy\n"); ++ return 0; ++ } ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n", ++ ipx->ipx_dest.net, ++ ipx->ipx_dest.node[0], ++ ipx->ipx_dest.node[1], ++ ipx->ipx_dest.node[2], ++ ipx->ipx_dest.node[3], ++ ipx->ipx_dest.node[4], ++ ipx->ipx_dest.node[5], ++ ipx->ipx_dest.sock, ++ ipx->ipx_source.net, ++ ipx->ipx_source.node[0], ++ ipx->ipx_source.node[1], ++ ipx->ipx_source.node[2], ++ ipx->ipx_source.node[3], ++ ipx->ipx_source.node[4], ++ ipx->ipx_source.node[5], ++ ipx->ipx_source.sock); ++ ++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Use IPX Net, and Socket as network addr\n"); ++ ++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock); ++ ++ // change IPX source node addr to wlan STA address ++ memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN); ++ } ++ else ++ { ++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node); ++ } ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ if(!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n"); ++ ++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // replace IPX destination node addr with Lookup destination MAC addr ++ memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN); ++ } ++ else ++ { ++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ } ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /* AARP */ ++ else if(ea != NULL) ++ { ++ /* Sanity check fields. */ ++ if(ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) ++ { ++ DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return 0; ++ ++ case NAT25_INSERT: ++ { ++ // change to AARP source mac address to wlan STA address ++ memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN); ++ ++ DEBUG_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n", ++ ea->pa_src_net, ++ ea->pa_src_node, ++ ea->pa_dst_net, ++ ea->pa_dst_node); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n", ++ ea->pa_src_net, ++ ea->pa_src_node, ++ ea->pa_dst_net, ++ ea->pa_dst_node); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // change to AARP destination mac address to Lookup result ++ memcpy(ea->hw_dst, skb->data, ETH_ALEN); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /* DDP */ ++ else if(ddp != NULL) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n", ++ ddp->deh_snet, ++ ddp->deh_snode, ++ ddp->deh_dnet, ++ ddp->deh_dnode); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n", ++ ddp->deh_snet, ++ ddp->deh_snode, ++ ddp->deh_dnet, ++ ddp->deh_dnode); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ return -1; ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle PPPoE frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(ETH_P_PPP_DISC)) || ++ (protocol == __constant_htons(ETH_P_PPP_SES))) ++ { ++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); ++ unsigned short *pMagic; ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if (ph->sid == 0) ++ return 0; ++ return 1; ++ ++ case NAT25_INSERT: ++ if(ph->sid == 0) // Discovery phase according to tag ++ { ++ if(ph->code == PADI_CODE || ph->code == PADR_CODE) ++ { ++ if (priv->ethBrExtInfo.addPPPoETag) { ++ struct pppoe_tag *tag, *pOldTag; ++ unsigned char tag_buf[40]; ++ int old_tag_len=0; ++ ++ tag = (struct pppoe_tag *)tag_buf; ++ pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID)); ++ if (pOldTag) { // if SID existed, copy old value and delete it ++ old_tag_len = ntohs(pOldTag->tag_len); ++ if (old_tag_len+TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN > sizeof(tag_buf)) { ++ DEBUG_ERR("SID tag length too long!\n"); ++ return -1; ++ } ++ ++ memcpy(tag->tag_data+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN, ++ pOldTag->tag_data, old_tag_len); ++ ++ if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN+old_tag_len) < 0) { ++ DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n"); ++ return -1; ++ } ++ ph->length = htons(ntohs(ph->length)-TAG_HDR_LEN-old_tag_len); ++ } ++ ++ tag->tag_type = PTT_RELAY_SID; ++ tag->tag_len = htons(MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN+old_tag_len); ++ ++ // insert the magic_code+client mac in relay tag ++ pMagic = (unsigned short *)tag->tag_data; ++ *pMagic = htons(MAGIC_CODE); ++ memcpy(tag->tag_data+MAGIC_CODE_LEN, skb->data+ETH_ALEN, ETH_ALEN); ++ ++ //Add relay tag ++ if(__nat25_add_pppoe_tag(skb, tag) < 0) ++ return -1; ++ ++ DEBUG_INFO("NAT25: Insert PPPoE, forward %s packet\n", ++ (ph->code == PADI_CODE ? "PADI" : "PADR")); ++ } ++ else { // not add relay tag ++ if (priv->pppoe_connection_in_progress && ++ memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { ++ DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n"); ++ return -2; ++ } ++ ++ if (priv->pppoe_connection_in_progress == 0) ++ memcpy(priv->pppoe_addr, skb->data+ETH_ALEN, ETH_ALEN); ++ ++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; ++ } ++ } ++ else ++ return -1; ++ } ++ else // session phase ++ { ++ DEBUG_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name); ++ ++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid)); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ ++ if (!priv->ethBrExtInfo.addPPPoETag && ++ priv->pppoe_connection_in_progress && ++ !memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) ++ priv->pppoe_connection_in_progress = 0; ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ if(ph->code == PADO_CODE || ph->code == PADS_CODE) ++ { ++ if (priv->ethBrExtInfo.addPPPoETag) { ++ struct pppoe_tag *tag; ++ unsigned char *ptr; ++ unsigned short tagType, tagLen; ++ int offset=0; ++ ++ if((ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID))) == 0) { ++ DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n"); ++ return -1; ++ } ++ ++ tag = (struct pppoe_tag *)ptr; ++ tagType = (unsigned short)((ptr[0] << 8) + ptr[1]); ++ tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]); ++ ++ if((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN))) { ++ DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen); ++ return -1; ++ } ++ ++ pMagic = (unsigned short *)tag->tag_data; ++ if (ntohs(*pMagic) != MAGIC_CODE) { ++ DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n", ++ (ph->code == PADO_CODE ? "PADO" : "PADS")); ++ return -1; ++ } ++ ++ memcpy(skb->data, tag->tag_data+MAGIC_CODE_LEN, ETH_ALEN); ++ ++ if (tagLen > MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN) ++ offset = TAG_HDR_LEN; ++ ++ if (skb_pull_and_merge(skb, ptr+offset, TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset) < 0) { ++ DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n"); ++ return -1; ++ } ++ ph->length = htons(ntohs(ph->length)-(TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset)); ++ if (offset > 0) ++ tag->tag_len = htons(tagLen-MAGIC_CODE_LEN-RTL_RELAY_TAG_LEN); ++ ++ DEBUG_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n", ++ (ph->code == PADO_CODE ? "PADO" : "PADS"), skb->dev->name); ++ } ++ else { // not add relay tag ++ if (!priv->pppoe_connection_in_progress) { ++ DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n"); ++ return -1; ++ } ++ memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); ++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; ++ } ++ } ++ else { ++ if(ph->sid != 0) ++ { ++ DEBUG_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name); ++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data+ETH_ALEN, &(ph->sid)); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ else ++ return -1; ++ ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle EAP frame */ ++ /*---------------------------------------------------*/ ++ else if(protocol == __constant_htons(0x888e)) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ return 0; ++ ++ case NAT25_LOOKUP: ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle C-Media proprietary frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(0xe2ae)) || ++ (protocol == __constant_htons(0xe2af))) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ return 0; ++ ++ case NAT25_LOOKUP: ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle IPV6 frame */ ++ /*---------------------------------------------------*/ ++#ifdef CL_IPV6_PASS ++ else if(protocol == __constant_htons(ETH_P_IPV6)) ++ { ++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); ++ ++ if (sizeof(*iph) >= (skb->len - ETH_HLEN)) ++ { ++ DEBUG_WARN("NAT25: malformed IPv6 packet !\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if (skb->data[0] & 1) ++ return 0; ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," ++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", ++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], ++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], ++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], ++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); ++ ++ if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { ++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr); ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ __nat25_db_print(priv); ++ ++ if (iph->nexthdr == IPPROTO_ICMPV6 && ++ skb->len > (ETH_HLEN + sizeof(*iph) + 4)) { ++ if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph), ++ skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) { ++ struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph)); ++ hdr->icmp6_cksum = 0; ++ hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr, ++ iph->payload_len, ++ IPPROTO_ICMPV6, ++ csum_partial((__u8 *)hdr, iph->payload_len, 0)); ++ } ++ } ++ } ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ DEBUG_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," ++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", ++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], ++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], ++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], ++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); ++ ++ ++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr); ++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { ++#ifdef SUPPORT_RX_UNI2MCAST ++ if (iph->daddr.s6_addr[0] == 0xff) ++ convert_ipv6_mac_to_mc(skb); ++#endif ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++#endif // CL_IPV6_PASS ++ ++ return -1; ++} ++ ++ ++int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) ++{ ++#ifdef BR_EXT_DEBUG ++ if((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) ++ { ++ panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n", ++ skb->data[0], ++ skb->data[1], ++ skb->data[2], ++ skb->data[3], ++ skb->data[4], ++ skb->data[5], ++ skb->data[6], ++ skb->data[7], ++ skb->data[8], ++ skb->data[9], ++ skb->data[10], ++ skb->data[11]); ++ } ++#endif ++ ++ if(!(skb->data[0] & 1)) ++ { ++ int is_vlan_tag=0, i, retval=0; ++ unsigned short vlan_hdr=0; ++ ++ if (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ vlan_hdr = *((unsigned short *)(skb->data+ETH_ALEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+ETH_ALEN*2+2-i*2)) = *((unsigned short *)(skb->data+ETH_ALEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ ++ if (!priv->ethBrExtInfo.nat25_disable) ++ { ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ /* ++ * This function look up the destination network address from ++ * the NAT2.5 database. Return value = -1 means that the ++ * corresponding network protocol is NOT support. ++ */ ++ if (!priv->ethBrExtInfo.nat25sc_disable && ++ (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && ++ !memcmp(priv->scdb_ip, skb->data+ETH_HLEN+16, 4)) { ++ memcpy(skb->data, priv->scdb_mac, ETH_ALEN); ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ } ++ else { ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); ++ } ++ } ++ else { ++ if (((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && ++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+16, 4)) || ++ ((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_ARP)) && ++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+24, 4))) { ++ // for traffic to upper TCP/IP ++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); ++ } ++ } ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+ETH_ALEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+ETH_ALEN*2+2)) = vlan_hdr; ++ } ++ ++ if(retval == -1) { ++ //DEBUG_ERR("NAT25: Lookup fail!\n"); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++#if 0 ++void mac_clone(_adapter *priv, unsigned char *addr) ++{ ++ struct sockaddr sa; ++ ++ memcpy(sa.sa_data, addr, ETH_ALEN); ++ DEBUG_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n", ++ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); ++ rtl8192cd_set_hwaddr(priv->dev, &sa); ++} ++ ++ ++int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb) ++{ ++ if(priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) ++ { ++ if(!(skb->data[ETH_ALEN] & 1)) //// check any other particular MAC add ++ { ++ if(memcmp(skb->data+ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) && ++ ((priv->dev->br_port) && ++ memcmp(skb->data+ETH_ALEN, priv->br_mac, ETH_ALEN))) ++ { ++ mac_clone(priv, skb->data+ETH_ALEN); ++ priv->macclone_completed = 1; ++ } ++ } ++ } ++ ++ return 0; ++} ++#endif // 0 ++ ++#define SERVER_PORT 67 ++#define CLIENT_PORT 68 ++#define DHCP_MAGIC 0x63825363 ++#define BROADCAST_FLAG 0x8000 ++ ++struct dhcpMessage { ++ u_int8_t op; ++ u_int8_t htype; ++ u_int8_t hlen; ++ u_int8_t hops; ++ u_int32_t xid; ++ u_int16_t secs; ++ u_int16_t flags; ++ u_int32_t ciaddr; ++ u_int32_t yiaddr; ++ u_int32_t siaddr; ++ u_int32_t giaddr; ++ u_int8_t chaddr[16]; ++ u_int8_t sname[64]; ++ u_int8_t file[128]; ++ u_int32_t cookie; ++ u_int8_t options[308]; /* 312 - cookie */ ++}; ++ ++void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb) ++{ ++ if(skb == NULL) ++ return; ++ ++ if(!priv->ethBrExtInfo.dhcp_bcst_disable) ++ { ++ unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); ++ ++ if(protocol == __constant_htons(ETH_P_IP)) // IP ++ { ++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); ++ ++ if(iph->protocol == IPPROTO_UDP) // UDP ++ { ++ struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2)); ++ ++ if((udph->source == __constant_htons(CLIENT_PORT)) ++ && (udph->dest == __constant_htons(SERVER_PORT))) // DHCP request ++ { ++ struct dhcpMessage *dhcph = ++ (struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr)); ++ ++ if(dhcph->cookie == __constant_htonl(DHCP_MAGIC)) // match magic word ++ { ++ if(!(dhcph->flags & htons(BROADCAST_FLAG))) // if not broadcast ++ { ++ register int sum = 0; ++ ++ DEBUG_INFO("DHCP: change flag of DHCP request to broadcast.\n"); ++ // or BROADCAST flag ++ dhcph->flags |= htons(BROADCAST_FLAG); ++ // recalculate checksum ++ sum = ~(udph->check) & 0xffff; ++ sum += dhcph->flags; ++ while(sum >> 16) ++ sum = (sum & 0xffff) + (sum >> 16); ++ udph->check = ~sum; ++ } ++ } ++ } ++ } ++ } ++ } ++} ++ ++ ++void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, ++ unsigned char *ipAddr) ++{ ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++ struct nat25_network_db_entry *db; ++ int hash; ++ //_irqL irqL; ++ //_enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr); ++ hash = __nat25_network_hash(networkAddr); ++ db = priv->nethash[hash]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return (void *)db; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return NULL; ++} ++ ++#endif // CONFIG_BR_EXT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_bt_mp.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_bt_mp.c +new file mode 100644 +index 00000000..e3e0f3d9 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_bt_mp.c +@@ -0,0 +1,1735 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#include "rtw_bt_mp.h" ++#include ++#include ++ ++#ifdef CONFIG_RTL8723A ++ ++void MPh2c_timeout_handle(void *FunctionContext) ++{ ++ _adapter *pAdapter = (_adapter *)FunctionContext; ++ PMPT_CONTEXT pMptCtx=&pAdapter->mppriv.MptCtx; ++ ++ DBG_8192C("[MPT], MPh2c_timeout_handle \n"); ++ ++ pMptCtx->bMPh2c_timeout=_TRUE; ++ ++ _rtw_up_sema(&pMptCtx->MPh2c_Sema); ++ ++ //_cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer); ++ ++ return; ++} ++u32 WaitC2Hevent( PADAPTER pAdapter,BOOLEAN *C2H_event ,u32 delay_time) ++{ ++ PMPT_CONTEXT pMptCtx=&(pAdapter->mppriv.MptCtx); ++ pMptCtx->bMPh2c_timeout=_FALSE; ++ DBG_8192C("WaitC2Hevent _set_timer \n"); ++ _set_timer( &pMptCtx->MPh2c_timeout_timer, delay_time ); ++ ++ _rtw_down_sema(&pMptCtx->MPh2c_Sema); ++ ++ if( pMptCtx->bMPh2c_timeout == _TRUE ) ++ { ++ C2H_event =_FALSE; ++ DBG_8192C("WaitC2Hevent bMPh2c_timeout _TRUE \n"); ++ return _FALSE; ++ } ++ ++ return _TRUE; ++ ++} ++ ++BT_CTRL_STATUS ++mptbt_CheckC2hFrame( ++ PADAPTER Adapter, ++ PBT_H2C pH2c, ++ PBT_EXT_C2H pExtC2h ++ ) ++{ ++ BT_CTRL_STATUS c2hStatus = BT_STATUS_C2H_SUCCESS; ++ ++ //DBG_8192C("[MPT], MPT rsp C2H hex: %x %x %x %x %x %x \n"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); ++ ++ DBG_8192C("[MPT], statusCode = 0x%x\n", pExtC2h->statusCode); ++ DBG_8192C("[MPT], retLen = %d\n", pExtC2h->retLen); ++ DBG_8192C("[MPT], opCodeVer : req/rsp=%d/%d\n", pH2c->opCodeVer, pExtC2h->opCodeVer); ++ DBG_8192C("[MPT], reqNum : req/rsp=%d/%d\n", pH2c->reqNum, pExtC2h->reqNum); ++ if(pExtC2h->reqNum != pH2c->reqNum) ++ { ++ c2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH; ++ DBG_8192C("[MPT], Error!! C2H reqNum Mismatch!!\n"); ++ } ++ else if(pExtC2h->opCodeVer != pH2c->opCodeVer) ++ { ++ c2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH; ++ DBG_8192C("[MPT], Error!! OPCode version L mismatch!!\n"); ++ } ++ ++ return c2hStatus; ++} ++ ++extern s32 FillH2CCmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); ++ ++BT_CTRL_STATUS ++mptbt_SendH2c( ++ PADAPTER Adapter, ++ PBT_H2C pH2c, ++ u2Byte h2cCmdLen ++ ) ++{ ++ //KIRQL OldIrql = KeGetCurrentIrql(); ++ BT_CTRL_STATUS h2cStatus=BT_STATUS_H2C_SUCCESS; ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ u1Byte i; ++ ++ DBG_8192C("[MPT], mptbt_SendH2c()=========>\n"); ++ ++ //PlatformResetEvent(&pMptCtx->MptH2cRspEvent); ++ //PlatformResetEvent(&pMptCtx->MptBtC2hEvent); ++ ++// if(OldIrql == PASSIVE_LEVEL) ++// { ++ //RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, ("[MPT], MPT H2C hex: \n"), pH2c, h2cCmdLen); ++ ++ for(i=0; ih2cReqNum++; ++ pMptCtx->h2cReqNum %= 16; ++ ++ if(WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 200)) ++ { ++ DBG_8192C("[MPT], Received WiFi MptH2cRspEvent!!!\n"); ++ if(WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 800)) ++ { ++ DBG_8192C("[MPT], Received BT MptBtC2hEvent!!!\n"); ++ break; ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!!BT MptBtC2hEvent timeout!!\n"); ++ h2cStatus = BT_STATUS_H2C_BT_NO_RSP; ++ } ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!!WiFi MptH2cRspEvent timeout!!\n"); ++ h2cStatus = BT_STATUS_H2C_TIMTOUT; ++ } ++ } ++// } ++// else ++// { ++// RT_ASSERT(FALSE, ("[MPT], mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\n")); ++// h2cStatus = BT_STATUS_WRONG_LEVEL; ++// } ++ ++ DBG_8192C("[MPT], mptbt_SendH2c()<=========\n"); ++ return h2cStatus; ++} ++ ++ ++ ++BT_CTRL_STATUS ++mptbt_CheckBtRspStatus( ++ PADAPTER Adapter, ++ PBT_EXT_C2H pExtC2h ++ ) ++{ ++ BT_CTRL_STATUS retStatus=BT_OP_STATUS_SUCCESS; ++ ++ switch(pExtC2h->statusCode) ++ { ++ case BT_OP_STATUS_SUCCESS: ++ retStatus = BT_STATUS_BT_OP_SUCCESS; ++ DBG_8192C("[MPT], BT status : BT_STATUS_SUCCESS\n"); ++ break; ++ case BT_OP_STATUS_VERSION_MISMATCH: ++ retStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH; ++ DBG_8192C("[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\n"); ++ break; ++ case BT_OP_STATUS_UNKNOWN_OPCODE: ++ retStatus = BT_STATUS_UNKNOWN_OPCODE_L; ++ DBG_8192C("[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\n"); ++ break; ++ case BT_OP_STATUS_ERROR_PARAMETER: ++ retStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L; ++ DBG_8192C("[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\n"); ++ break; ++ default: ++ retStatus = BT_STATUS_UNKNOWN_STATUS_L; ++ DBG_8192C("[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\n"); ++ break; ++ } ++ ++ return retStatus; ++} ++ ++ ++ ++BT_CTRL_STATUS ++mptbt_BtFwOpCodeProcess( ++ PADAPTER Adapter, ++ u1Byte btFwOpCode, ++ u1Byte opCodeVer, ++ pu1Byte pH2cPar, ++ u1Byte h2cParaLen ++ ) ++{ ++ u1Byte H2C_Parameter[6] ={0}; ++ PBT_H2C pH2c=(PBT_H2C)&H2C_Parameter[0]; ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; ++ u2Byte paraLen=0,i; ++ BT_CTRL_STATUS h2cStatus=BT_STATUS_H2C_SUCCESS, c2hStatus=BT_STATUS_C2H_SUCCESS; ++ BT_CTRL_STATUS retStatus=BT_STATUS_H2C_BT_NO_RSP; ++ ++ pH2c->opCode = btFwOpCode; ++ pH2c->opCodeVer = opCodeVer; ++ pH2c->reqNum = pMptCtx->h2cReqNum; ++ //PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); ++ //_rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); ++ _rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen); ++ ++ DBG_8192C("[MPT], pH2c->opCode=%d\n", pH2c->opCode); ++ DBG_8192C("[MPT], pH2c->opCodeVer=%d\n", pH2c->opCodeVer); ++ DBG_8192C("[MPT], pH2c->reqNum=%d\n", pH2c->reqNum); ++ DBG_8192C("[MPT], h2c parameter length=%d\n", h2cParaLen); ++ if(h2cParaLen) ++ { ++ DBG_8192C("[MPT], parameters(hex): \n"); ++ for(i=0;ibuf[i]); ++ } ++ } ++ ++ h2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen+2); ++ if(BT_STATUS_H2C_SUCCESS == h2cStatus) ++ { ++ // if reach here, it means H2C get the correct c2h response, ++ c2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h); ++ if(BT_STATUS_C2H_SUCCESS == c2hStatus) ++ { ++ retStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h); ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!! C2H failed for pH2c->opCode=%d\n", pH2c->opCode); ++ // check c2h status error, return error status code to upper layer. ++ retStatus = c2hStatus; ++ } ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!! H2C failed for pH2c->opCode=%d\n", pH2c->opCode); ++ // check h2c status error, return error status code to upper layer. ++ retStatus = h2cStatus; ++ } ++ ++ return retStatus; ++} ++ ++ ++ ++ ++u2Byte ++mptbt_BtReady( ++ PADAPTER Adapter, ++ PBT_REQ_CMD pBtReq, ++ PBT_RSP_CMD pBtRsp ++ ) ++{ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; ++ u1Byte i; ++ u1Byte btFwVer=0, bdAddr[6]={0}; ++ u2Byte btRealFwVer=0; ++ pu2Byte pu2Tmp=NULL; ++ ++ // ++ // check upper layer parameters ++ // ++ ++ // 1. check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ ++ pBtRsp->pParamStart[0] = MP_BT_NOT_READY; ++ paraLen = 10; ++ // ++ // execute lower layer opcodes ++ // ++ ++ // Get BT FW version ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_GET_BT_VERSION; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ else ++ { ++ pu2Tmp = (pu2Byte)&pExtC2h->buf[0]; ++ btRealFwVer = *pu2Tmp; ++ btFwVer = pExtC2h->buf[1]; ++ DBG_8192C("[MPT], btRealFwVer=0x%x, btFwVer=0x%x\n", btRealFwVer, btFwVer); ++ } ++ ++ // Get BD Address ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_GET_BD_ADDR_L; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ else ++ { ++ bdAddr[5] = pExtC2h->buf[0]; ++ bdAddr[4] = pExtC2h->buf[1]; ++ bdAddr[3] = pExtC2h->buf[2]; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_GET_BD_ADDR_H; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ else ++ { ++ bdAddr[2] = pExtC2h->buf[0]; ++ bdAddr[1] = pExtC2h->buf[1]; ++ bdAddr[0] = pExtC2h->buf[2]; ++ } ++ DBG_8192C("[MPT], Local BDAddr:"); ++ for(i=0; i<6; i++) ++ { ++ DBG_8192C(" 0x%x ", bdAddr[i]); ++ } ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ pBtRsp->pParamStart[0] = MP_BT_READY; ++ pu2Tmp = (pu2Byte)&pBtRsp->pParamStart[1]; ++ *pu2Tmp = btRealFwVer; ++ pBtRsp->pParamStart[3] = btFwVer; ++ for(i=0; i<6; i++) ++ { ++ pBtRsp->pParamStart[4+i] = bdAddr[5-i]; ++ } ++ ++ return paraLen; ++} ++ ++void mptbt_close_WiFiRF(PADAPTER Adapter) ++{ ++ PHY_SetBBReg(Adapter, 0x824, 0xF, 0x0); ++ PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x0); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x0); ++} ++ ++void mptbt_open_WiFiRF(PADAPTER Adapter) ++{ ++ PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3); ++ PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x3); ++} ++ ++u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter) ++{ ++ u2Byte tmp_2byte = 0; ++ ++ //Enter test mode ++ if (Enter) { ++ ////1>. close WiFi RF ++ mptbt_close_WiFiRF(Adapter); ++ ++ ////2>. change ant switch to BT ++ tmp_2byte = rtw_read16(Adapter, 0x860); ++ tmp_2byte = tmp_2byte | BIT(9); ++ tmp_2byte = tmp_2byte & (~BIT(8)); ++ rtw_write16(Adapter, 0x860, tmp_2byte); ++ rtw_write16(Adapter, 0x870, 0x300); ++ } else { ++ ////1>. Open WiFi RF ++ mptbt_open_WiFiRF(Adapter); ++ ++ ////2>. change ant switch back ++ tmp_2byte = rtw_read16(Adapter, 0x860); ++ tmp_2byte = tmp_2byte | BIT(8); ++ tmp_2byte = tmp_2byte & (~BIT(9)); ++ rtw_write16(Adapter, 0x860, tmp_2byte); ++ rtw_write16(Adapter, 0x870, 0x300); ++ } ++ ++ return 0; ++} ++ ++u2Byte ++mptbt_BtSetMode( ++ PADAPTER Adapter, ++ PBT_REQ_CMD pBtReq, ++ PBT_RSP_CMD pBtRsp ++ ) ++{ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ u1Byte btModeToSet=0; ++ ++ // ++ // check upper layer parameters ++ // ++ // 1. check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ // 2. check upper layer parameter length ++ if(1 == pBtReq->paraLength) ++ { ++ btModeToSet = pBtReq->pParamStart[0]; ++ DBG_8192C("[MPT], BtTestMode=%d \n", btModeToSet); ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ ++ // ++ // execute lower layer opcodes ++ // ++ ++ // 1. fill h2c parameters ++ // check bt mode ++ btOpcode = BT_LO_OP_SET_BT_MODE; ++ if(btModeToSet >= MP_BT_MODE_MAX) ++ { ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ mptbt_switch_RF(Adapter, 1); ++ ++ h2cParaBuf[0] = btModeToSet; ++ h2cParaLen = 1; ++ // 2. execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // 3. construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS == retStatus) ++ { ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ } ++ else ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ } ++ ++ return paraLen; ++} ++ ++ ++VOID ++MPTBT_FwC2hBtMpCtrl( ++ PADAPTER Adapter, ++ pu1Byte tmpBuf, ++ u1Byte length ++ ) ++{ ++ u32 i; ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)tmpBuf; ++ ++ if(Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0 ) ++ { ++ DBG_8192C("[MPT], %s,bBTFWReady == _FALSE\n",__func__); ++ return; ++ } ++ //cancel_timeout for h2c handle ++ _cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer); ++ ++ DBG_8192C("[MPT], MPTBT_FwC2hBtMpCtrl(), hex: \n"); ++ for(i=0;i<=length;i++) ++ { ++ //DBG_8192C("[MPT], MPTBT_FwC2hBtMpCtrl(), hex: \n",tmpBuf[i], length); ++ DBG_8192C(" 0x%x ",tmpBuf[i]); ++ } ++ DBG_8192C("\n [MPT], pExtC2h->extendId=0x%x\n", pExtC2h->extendId); ++ ++ switch(pExtC2h->extendId) ++ { ++ case EXT_C2H_WIFI_FW_ACTIVE_RSP: ++ DBG_8192C("[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\n"); ++ DBG_8192C("[MPT], pExtC2h->buf hex: \n"); ++ if( length > 32 || length < 3 ) ++ break ; ++ for(i=0;i<=(length-3);i++) ++ DBG_8192C(" 0x%x ",pExtC2h->buf[i]); ++ //PlatformSetEvent(&pMptCtx->MptH2cRspEvent); ++ pMptCtx->MptH2cRspEvent=_TRUE; ++ _rtw_up_sema(&pMptCtx->MPh2c_Sema); ++ break; ++ case EXT_C2H_TRIG_BY_BT_FW: ++ DBG_8192C("[MPT], EXT_C2H_TRIG_BY_BT_FW\n"); ++ //PlatformMoveMemory(&pMptCtx->c2hBuf[0], tmpBuf, length); ++ _rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length); ++ DBG_8192C("[MPT], pExtC2h->statusCode=0x%x\n", pExtC2h->statusCode); ++ DBG_8192C("[MPT], pExtC2h->retLen=0x%x\n", pExtC2h->retLen); ++ DBG_8192C("[MPT], pExtC2h->opCodeVer=0x%x\n", pExtC2h->opCodeVer); ++ DBG_8192C("[MPT], pExtC2h->reqNum=0x%x\n", pExtC2h->reqNum); ++ DBG_8192C("[MPT], pExtC2h->buf hex: \n"); ++ for(i=0;i<=(length-3);i++) ++ DBG_8192C(" 0x%x ",pExtC2h->buf[0]); ++ //PlatformSetEvent(&pMptCtx->MptBtC2hEvent); ++ pMptCtx->MptBtC2hEvent=_TRUE; ++ _rtw_up_sema(&pMptCtx->MPh2c_Sema); ++ break; ++ default: ++ DBG_8192C("[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\n",pExtC2h->extendId,pExtC2h->reqNum); ++ break; ++ } ++ ++ ++ ++} ++ ++ ++u2Byte ++mptbt_BtGetGeneral( ++ IN PADAPTER Adapter, ++ IN PBT_REQ_CMD pBtReq, ++ IN PBT_RSP_CMD pBtRsp ++ ) ++{ ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode, bdAddr[6]={0}; ++ u1Byte btOpcodeVer=0; ++ u1Byte getType=0, i; ++ u2Byte getParaLen=0, validParaLen=0; ++ u1Byte regType=0, reportType=0; ++ u4Byte regAddr=0, regValue=0; ++ pu4Byte pu4Tmp; ++ pu2Byte pu2Tmp; ++ pu1Byte pu1Tmp; ++ ++ // ++ // check upper layer parameters ++ // ++ ++ // check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ // check upper layer parameter length ++ if(pBtReq->paraLength < 1) ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ getParaLen = pBtReq->paraLength - 1; ++ getType = pBtReq->pParamStart[0]; ++ ++ DBG_8192C("[MPT], getType=%d, getParaLen=%d\n", getType, getParaLen); ++ ++ // check parameter first ++ switch(getType) ++ { ++ case BT_GGET_REG: ++ DBG_8192C("[MPT], [BT_GGET_REG]\n"); ++ validParaLen = 5; ++ if(getParaLen == validParaLen) ++ { ++ btOpcode = BT_LO_OP_READ_REG; ++ regType = pBtReq->pParamStart[1]; ++ pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2]; ++ regAddr = *pu4Tmp; ++ DBG_8192C("[MPT], BT_GGET_REG regType=0x%x, regAddr=0x%x!!\n", ++ regType, regAddr); ++ if(regType >= BT_REG_MAX) ++ { ++ pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ if( ((BT_REG_RF==regType)&&(regAddr>0x7f)) || ++ ((BT_REG_MODEM==regType)&&(regAddr>0x1ff)) || ++ ((BT_REG_BLUEWIZE==regType)&&(regAddr>0xfff)) || ++ ((BT_REG_VENDOR==regType)&&(regAddr>0xfff)) || ++ ((BT_REG_LE==regType)&&(regAddr>0xfff)) ) ++ { ++ pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ } ++ } ++ break; ++ case BT_GGET_STATUS: ++ DBG_8192C("[MPT], [BT_GGET_STATUS]\n"); ++ validParaLen = 0; ++ break; ++ case BT_GGET_REPORT: ++ DBG_8192C("[MPT], [BT_GGET_REPORT]\n"); ++ validParaLen = 1; ++ if(getParaLen == validParaLen) ++ { ++ reportType = pBtReq->pParamStart[1]; ++ DBG_8192C("[MPT], BT_GGET_REPORT reportType=0x%x!!\n", reportType); ++ if(reportType >= BT_REPORT_MAX) ++ { ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ } ++ break; ++ default: ++ { ++ DBG_8192C("[MPT], Error!! getType=%d, out of range\n", getType); ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ break; ++ } ++ if(getParaLen != validParaLen) ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n", ++ getParaLen, getType, validParaLen); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ ++ // ++ // execute lower layer opcodes ++ // ++ if(BT_GGET_REG == getType) ++ { ++ // fill h2c parameters ++ // here we should write reg value first then write the address, adviced by Austin ++ btOpcode = BT_LO_OP_READ_REG; ++ h2cParaBuf[0] = regType; ++ h2cParaBuf[1] = pBtReq->pParamStart[2]; ++ h2cParaBuf[2] = pBtReq->pParamStart[3]; ++ h2cParaLen = 3; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ pu2Tmp = (pu2Byte)&pExtC2h->buf[0]; ++ regValue = *pu2Tmp; ++ DBG_8192C("[MPT], read reg regType=0x%x, regAddr=0x%x, regValue=0x%x\n", ++ regType, regAddr, regValue); ++ ++ pu4Tmp = (pu4Byte)&pBtRsp->pParamStart[0]; ++ *pu4Tmp = regValue; ++ paraLen = 4; ++ } ++ else if(BT_GGET_STATUS == getType) ++ { ++ btOpcode = BT_LO_OP_GET_BT_STATUS; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ pBtRsp->pParamStart[0] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[1] = pExtC2h->buf[1]; ++ DBG_8192C("[MPT], read bt status, testMode=0x%x, testStatus=0x%x\n", ++ pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]); ++ paraLen = 2; ++ } ++ else if(BT_GGET_REPORT == getType) ++ { ++ switch(reportType) ++ { ++ case BT_REPORT_RX_PACKET_CNT: ++ { ++ DBG_8192C("[MPT], [Rx Packet Counts]\n"); ++ btOpcode = BT_LO_OP_GET_RX_PKT_CNT_L; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[0] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[1] = pExtC2h->buf[1]; ++ ++ btOpcode = BT_LO_OP_GET_RX_PKT_CNT_H; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[2] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[3] = pExtC2h->buf[1]; ++ paraLen = 4; ++ } ++ break; ++ case BT_REPORT_RX_ERROR_BITS: ++ { ++ DBG_8192C("[MPT], [Rx Error Bits]\n"); ++ btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[0] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[1] = pExtC2h->buf[1]; ++ ++ btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[2] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[3] = pExtC2h->buf[1]; ++ paraLen = 4; ++ } ++ break; ++ case BT_REPORT_RSSI: ++ { ++ DBG_8192C("[MPT], [RSSI]\n"); ++ btOpcode = BT_LO_OP_GET_RSSI; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[0] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[1] = pExtC2h->buf[1]; ++ paraLen = 2; ++ } ++ break; ++ case BT_REPORT_CFO_HDR_QUALITY: ++ { ++ DBG_8192C("[MPT], [CFO & Header Quality]\n"); ++ btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[0] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[1] = pExtC2h->buf[1]; ++ ++ btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ pBtRsp->pParamStart[2] = pExtC2h->buf[0]; ++ pBtRsp->pParamStart[3] = pExtC2h->buf[1]; ++ paraLen = 4; ++ } ++ break; ++ case BT_REPORT_CONNECT_TARGET_BD_ADDR: ++ { ++ DBG_8192C("[MPT], [Connected Target BD ADDR]\n"); ++ btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ bdAddr[5] = pExtC2h->buf[0]; ++ bdAddr[4] = pExtC2h->buf[1]; ++ bdAddr[3] = pExtC2h->buf[2]; ++ ++ btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ bdAddr[2] = pExtC2h->buf[0]; ++ bdAddr[1] = pExtC2h->buf[1]; ++ bdAddr[0] = pExtC2h->buf[2]; ++ ++ DBG_8192C("[MPT], Connected Target BDAddr:%s", bdAddr); ++ for(i=0; i<6; i++) ++ { ++ pBtRsp->pParamStart[i] = bdAddr[5-i]; ++ } ++ paraLen = 6; ++ } ++ break; ++ default: ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ break; ++ } ++ } ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ return paraLen; ++} ++ ++ ++ ++u2Byte ++mptbt_BtSetGeneral( ++ IN PADAPTER Adapter, ++ IN PBT_REQ_CMD pBtReq, ++ IN PBT_RSP_CMD pBtRsp ++ ) ++{ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ u1Byte setType=0; ++ u2Byte setParaLen=0, validParaLen=0; ++ u1Byte regType=0, bdAddr[6]={0}, calVal=0; ++ u4Byte regAddr=0, regValue=0; ++ pu4Byte pu4Tmp; ++ pu2Byte pu2Tmp; ++ pu1Byte pu1Tmp; ++ ++ // ++ // check upper layer parameters ++ // ++ ++ // check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ // check upper layer parameter length ++ if(pBtReq->paraLength < 1) ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ setParaLen = pBtReq->paraLength - 1; ++ setType = pBtReq->pParamStart[0]; ++ ++ DBG_8192C("[MPT], setType=%d, setParaLen=%d\n", setType, setParaLen); ++ ++ // check parameter first ++ switch(setType) ++ { ++ case BT_GSET_REG: ++ DBG_8192C ("[MPT], [BT_GSET_REG]\n"); ++ validParaLen = 9; ++ if(setParaLen == validParaLen) ++ { ++ btOpcode = BT_LO_OP_WRITE_REG_VALUE; ++ regType = pBtReq->pParamStart[1]; ++ pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2]; ++ regAddr = *pu4Tmp; ++ pu4Tmp = (pu4Byte)&pBtReq->pParamStart[6]; ++ regValue = *pu4Tmp; ++ DBG_8192C("[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\n", ++ regType, regAddr, regValue); ++ if(regType >= BT_REG_MAX) ++ { ++ pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ if( ((BT_REG_RF==regType)&&(regAddr>0x7f)) || ++ ((BT_REG_MODEM==regType)&&(regAddr>0x1ff)) || ++ ((BT_REG_BLUEWIZE==regType)&&(regAddr>0xfff)) || ++ ((BT_REG_VENDOR==regType)&&(regAddr>0xfff)) || ++ ((BT_REG_LE==regType)&&(regAddr>0xfff)) ) ++ { ++ pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ } ++ } ++ break; ++ case BT_GSET_RESET: ++ DBG_8192C("[MPT], [BT_GSET_RESET]\n"); ++ validParaLen = 0; ++ break; ++ case BT_GSET_TARGET_BD_ADDR: ++ DBG_8192C("[MPT], [BT_GSET_TARGET_BD_ADDR]\n"); ++ validParaLen = 6; ++ if(setParaLen == validParaLen) ++ { ++ btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H; ++ if( (pBtReq->pParamStart[1]==0) && ++ (pBtReq->pParamStart[2]==0) && ++ (pBtReq->pParamStart[3]==0) && ++ (pBtReq->pParamStart[4]==0) && ++ (pBtReq->pParamStart[5]==0) && ++ (pBtReq->pParamStart[6]==0) ) ++ { ++ DBG_8192C("[MPT], Error!! targetBDAddr=all zero\n"); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ if( (pBtReq->pParamStart[1]==0xff) && ++ (pBtReq->pParamStart[2]==0xff) && ++ (pBtReq->pParamStart[3]==0xff) && ++ (pBtReq->pParamStart[4]==0xff) && ++ (pBtReq->pParamStart[5]==0xff) && ++ (pBtReq->pParamStart[6]==0xff) ) ++ { ++ DBG_8192C("[MPT], Error!! targetBDAddr=all 0xf\n"); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ bdAddr[0] = pBtReq->pParamStart[6]; ++ bdAddr[1] = pBtReq->pParamStart[5]; ++ bdAddr[2] = pBtReq->pParamStart[4]; ++ bdAddr[3] = pBtReq->pParamStart[3]; ++ bdAddr[4] = pBtReq->pParamStart[2]; ++ bdAddr[5] = pBtReq->pParamStart[1]; ++ DBG_8192C ("[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\n", ++ bdAddr[0],bdAddr[1],bdAddr[2],bdAddr[3],bdAddr[4],bdAddr[5]); ++ } ++ break; ++ case BT_GSET_TX_PWR_FINETUNE: ++ DBG_8192C("[MPT], [BT_GSET_TX_PWR_FINETUNE]\n"); ++ validParaLen = 1; ++ if(setParaLen == validParaLen) ++ { ++ btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION; ++ calVal = pBtReq->pParamStart[1]; ++ if( (calVal<1) || (calVal>9) ) ++ { ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ DBG_8192C ("[MPT], calVal=%d\n", calVal); ++ } ++ break; ++ case BT_SET_TRACKING_INTERVAL: ++ DBG_871X("[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d \n",setParaLen); ++ ++ validParaLen = 1; ++ if(setParaLen == validParaLen) ++ calVal = pBtReq->pParamStart[1]; ++ break; ++ case BT_SET_THERMAL_METER: ++ DBG_871X("[MPT], [BT_SET_THERMAL_METER] setParaLen =%d \n",setParaLen); ++ validParaLen = 1; ++ if(setParaLen == validParaLen) ++ calVal = pBtReq->pParamStart[1]; ++ break; ++ case BT_ENABLE_CFO_TRACKING: ++ DBG_871X("[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d \n",setParaLen); ++ validParaLen = 1; ++ if(setParaLen == validParaLen) ++ calVal = pBtReq->pParamStart[1]; ++ break; ++ case BT_GSET_UPDATE_BT_PATCH: ++ if(IS_HARDWARE_TYPE_8723AE(Adapter) && Adapter->bFWReady) ++ { ++ u1Byte i; ++ DBG_8192C ("[MPT], write regs for load patch\n"); ++ //BTFwPatch8723A(Adapter); ++ PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x2d); ++ rtw_msleep_os(50); ++ PlatformEFIOWrite4Byte(Adapter, 0x68, 0xa005000c); ++ rtw_msleep_os(50); ++ PlatformEFIOWrite4Byte(Adapter, 0x68, 0xb005000c); ++ rtw_msleep_os(50); ++ PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x29); ++ for(i=0; i<12; i++) ++ rtw_msleep_os(100); ++//#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++// BTFwPatch8723A(Adapter); ++//#endif ++ DBG_8192C("[MPT], load BT FW Patch finished!!!\n"); ++ } ++ break; ++ default: ++ { ++ DBG_8192C ("[MPT], Error!! setType=%d, out of range\n", setType); ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ break; ++ } ++ if(setParaLen != validParaLen) ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n", ++ setParaLen, setType, validParaLen); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ ++ // ++ // execute lower layer opcodes ++ // ++ if(BT_GSET_REG == setType) ++ { ++ // fill h2c parameters ++ // here we should write reg value first then write the address, adviced by Austin ++ btOpcode = BT_LO_OP_WRITE_REG_VALUE; ++ h2cParaBuf[0] = pBtReq->pParamStart[6]; ++ h2cParaBuf[1] = pBtReq->pParamStart[7]; ++ h2cParaBuf[2] = pBtReq->pParamStart[8]; ++ h2cParaLen = 3; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // write reg address ++ btOpcode = BT_LO_OP_WRITE_REG_ADDR; ++ h2cParaBuf[0] = regType; ++ h2cParaBuf[1] = pBtReq->pParamStart[2]; ++ h2cParaBuf[2] = pBtReq->pParamStart[3]; ++ h2cParaLen = 3; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_GSET_RESET == setType) ++ { ++ btOpcode = BT_LO_OP_RESET; ++ h2cParaLen = 0; ++ // execute h2c and check respond c2h from bt fw is correct or not ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_GSET_TARGET_BD_ADDR == setType) ++ { ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L; ++ h2cParaBuf[0] = pBtReq->pParamStart[1]; ++ h2cParaBuf[1] = pBtReq->pParamStart[2]; ++ h2cParaBuf[2] = pBtReq->pParamStart[3]; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H; ++ h2cParaBuf[0] = pBtReq->pParamStart[4]; ++ h2cParaBuf[1] = pBtReq->pParamStart[5]; ++ h2cParaBuf[2] = pBtReq->pParamStart[6]; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_GSET_TX_PWR_FINETUNE == setType) ++ { ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION; ++ h2cParaBuf[0] = calVal; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_SET_TRACKING_INTERVAL == setType) ++ { ++ // BT_LO_OP_SET_TRACKING_INTERVAL = 0x22, ++ // BT_LO_OP_SET_THERMAL_METER = 0x23, ++ // BT_LO_OP_ENABLE_CFO_TRACKING = 0x24, ++ btOpcode = BT_LO_OP_SET_TRACKING_INTERVAL; ++ h2cParaBuf[0] = calVal; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_SET_THERMAL_METER == setType) ++ { ++ btOpcode = BT_LO_OP_SET_THERMAL_METER; ++ h2cParaBuf[0] = calVal; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ else if(BT_ENABLE_CFO_TRACKING == setType) ++ { ++ btOpcode = BT_LO_OP_ENABLE_CFO_TRACKING; ++ h2cParaBuf[0] = calVal; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ } ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ return paraLen; ++} ++ ++ ++ ++u2Byte ++mptbt_BtSetTxRxPars( ++ IN PADAPTER Adapter, ++ IN PBT_REQ_CMD pBtReq, ++ IN PBT_RSP_CMD pBtRsp ++ ) ++{ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ PBT_TXRX_PARAMETERS pTxRxPars=(PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0]; ++ u2Byte lenTxRx=sizeof(BT_TXRX_PARAMETERS); ++ u1Byte i; ++ u1Byte bdAddr[6]={0}; ++ ++ // ++ // check upper layer parameters ++ // ++ ++ // 1. check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ // 2. check upper layer parameter length ++ if(pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) ++ { ++ DBG_8192C ("[MPT], pTxRxPars->txrxChannel=0x%x \n", pTxRxPars->txrxChannel); ++ DBG_8192C ("[MPT], pTxRxPars->txrxTxPktCnt=0x%8x \n", pTxRxPars->txrxTxPktCnt); ++ DBG_8192C ("[MPT], pTxRxPars->txrxTxPktInterval=0x%x \n", pTxRxPars->txrxTxPktInterval); ++ DBG_8192C ("[MPT], pTxRxPars->txrxPayloadType=0x%x \n", pTxRxPars->txrxPayloadType); ++ DBG_8192C ("[MPT], pTxRxPars->txrxPktType=0x%x \n", pTxRxPars->txrxPktType); ++ DBG_8192C ("[MPT], pTxRxPars->txrxPayloadLen=0x%x \n", pTxRxPars->txrxPayloadLen); ++ DBG_8192C ("[MPT], pTxRxPars->txrxPktHeader=0x%x \n", pTxRxPars->txrxPktHeader); ++ DBG_8192C ("[MPT], pTxRxPars->txrxWhitenCoeff=0x%x \n", pTxRxPars->txrxWhitenCoeff); ++ bdAddr[0] = pTxRxPars->txrxBdaddr[5]; ++ bdAddr[1] = pTxRxPars->txrxBdaddr[4]; ++ bdAddr[2] = pTxRxPars->txrxBdaddr[3]; ++ bdAddr[3] = pTxRxPars->txrxBdaddr[2]; ++ bdAddr[4] = pTxRxPars->txrxBdaddr[1]; ++ bdAddr[5] = pTxRxPars->txrxBdaddr[0]; ++ DBG_8192C ("[MPT], pTxRxPars->txrxBdaddr: %s", &bdAddr[0]); ++ DBG_8192C ("[MPT], pTxRxPars->txrxTxGainIndex=0x%x \n", pTxRxPars->txrxTxGainIndex); ++ } ++ else ++ { ++ DBG_8192C ("[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\n", pBtReq->paraLength, lenTxRx); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ ++ // ++ // execute lower layer opcodes ++ // ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_PKT_HEADER; ++ if(pTxRxPars->txrxPktHeader > 0x3ffff) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\n", pTxRxPars->txrxPktHeader); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ h2cParaBuf[0] = (u1Byte)(pTxRxPars->txrxPktHeader&0xff); ++ h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPktHeader&0xff00)>>8); ++ h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPktHeader&0xff0000)>>16); ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_PKT_TYPE_LEN; ++ { ++ u2Byte payloadLenLimit=0; ++ switch(pTxRxPars->txrxPktType) ++ { ++ case MP_BT_PKT_DH1: ++ payloadLenLimit = 27*8; ++ break; ++ case MP_BT_PKT_DH3: ++ payloadLenLimit = 183*8; ++ break; ++ case MP_BT_PKT_DH5: ++ payloadLenLimit = 339*8; ++ break; ++ case MP_BT_PKT_2DH1: ++ payloadLenLimit = 54*8; ++ break; ++ case MP_BT_PKT_2DH3: ++ payloadLenLimit = 367*8; ++ break; ++ case MP_BT_PKT_2DH5: ++ payloadLenLimit = 679*8; ++ break; ++ case MP_BT_PKT_3DH1: ++ payloadLenLimit = 83*8; ++ break; ++ case MP_BT_PKT_3DH3: ++ payloadLenLimit = 552*8; ++ break; ++ case MP_BT_PKT_3DH5: ++ payloadLenLimit = 1021*8; ++ break; ++ case MP_BT_PKT_LE: ++ payloadLenLimit = 39*8; ++ break; ++ default: ++ { ++ DBG_8192C ("[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ break; ++ } ++ ++ if(pTxRxPars->txrxPayloadLen > payloadLenLimit) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\n", ++ pTxRxPars->txrxPayloadLen, payloadLenLimit); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ ++ h2cParaBuf[0] = pTxRxPars->txrxPktType; ++ h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPayloadLen&0xff)); ++ h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPayloadLen&0xff00)>>8); ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE; ++ if(pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\n", pTxRxPars->txrxPayloadType); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff)); ++ h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff00)>>8); ++ h2cParaBuf[2] = pTxRxPars->txrxPayloadType; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV; ++ if(pTxRxPars->txrxTxPktInterval > 15) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\n", pTxRxPars->txrxTxPktInterval); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff0000)>>16); ++ h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff000000)>>24); ++ h2cParaBuf[2] = pTxRxPars->txrxTxPktInterval; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_WHITENCOEFF; ++ { ++ h2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_CHNL_TX_GAIN; ++ if( (pTxRxPars->txrxChannel > 78) || ++ (pTxRxPars->txrxTxGainIndex > 7) ) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\n", pTxRxPars->txrxChannel); ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\n", pTxRxPars->txrxTxGainIndex); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ h2cParaBuf[0] = pTxRxPars->txrxChannel; ++ h2cParaBuf[1] = pTxRxPars->txrxTxGainIndex; ++ h2cParaLen = 2; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ // fill h2c parameters ++ btOpcode = BT_LO_OP_SET_BD_ADDR_L; ++ if( (pTxRxPars->txrxBdaddr[0]==0) && ++ (pTxRxPars->txrxBdaddr[1]==0) && ++ (pTxRxPars->txrxBdaddr[2]==0) && ++ (pTxRxPars->txrxBdaddr[3]==0) && ++ (pTxRxPars->txrxBdaddr[4]==0) && ++ (pTxRxPars->txrxBdaddr[5]==0) ) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\n"); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ if( (pTxRxPars->txrxBdaddr[0]==0xff) && ++ (pTxRxPars->txrxBdaddr[1]==0xff) && ++ (pTxRxPars->txrxBdaddr[2]==0xff) && ++ (pTxRxPars->txrxBdaddr[3]==0xff) && ++ (pTxRxPars->txrxBdaddr[4]==0xff) && ++ (pTxRxPars->txrxBdaddr[5]==0xff) ) ++ { ++ DBG_8192C ("[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\n"); ++ pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ ++ { ++ h2cParaBuf[0] = pTxRxPars->txrxBdaddr[0]; ++ h2cParaBuf[1] = pTxRxPars->txrxBdaddr[1]; ++ h2cParaBuf[2] = pTxRxPars->txrxBdaddr[2]; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ btOpcode = BT_LO_OP_SET_BD_ADDR_H; ++ { ++ h2cParaBuf[0] = pTxRxPars->txrxBdaddr[3]; ++ h2cParaBuf[1] = pTxRxPars->txrxBdaddr[4]; ++ h2cParaBuf[2] = pTxRxPars->txrxBdaddr[5]; ++ h2cParaLen = 3; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ // ckeck bt return status. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ return paraLen; ++} ++ ++ ++ ++u2Byte ++mptbt_BtTestCtrl( ++ IN PADAPTER Adapter, ++ IN PBT_REQ_CMD pBtReq, ++ IN PBT_RSP_CMD pBtRsp ++ ) ++{ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ u1Byte testCtrl=0; ++ ++ // ++ // check upper layer parameters ++ // ++ ++ // 1. check upper layer opcode version ++ if(pBtReq->opCodeVer != 1) ++ { ++ DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); ++ pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; ++ return paraLen; ++ } ++ // 2. check upper layer parameter length ++ if(1 == pBtReq->paraLength) ++ { ++ testCtrl = pBtReq->pParamStart[0]; ++ DBG_8192C("[MPT], testCtrl=%d \n", testCtrl); ++ } ++ else ++ { ++ DBG_8192C("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength); ++ pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; ++ return paraLen; ++ } ++ ++ // ++ // execute lower layer opcodes ++ // ++ ++ // 1. fill h2c parameters ++ // check bt mode ++ btOpcode = BT_LO_OP_TEST_CTRL; ++ if(testCtrl >= MP_BT_TEST_MAX) ++ { ++ DBG_8192C("[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\n", ++ testCtrl, MP_BT_TEST_MAX-1); ++ pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; ++ return paraLen; ++ } ++ else ++ { ++ h2cParaBuf[0] = testCtrl; ++ h2cParaLen = 1; ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ } ++ ++ // 3. construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ return paraLen; ++} ++ ++ ++u2Byte ++mptbt_TestBT( ++ IN PADAPTER Adapter, ++ IN PBT_REQ_CMD pBtReq, ++ IN PBT_RSP_CMD pBtRsp ++ ) ++{ ++ ++ u1Byte h2cParaBuf[6] ={0}; ++ u1Byte h2cParaLen=0; ++ u2Byte paraLen=0; ++ u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; ++ u1Byte btOpcode; ++ u1Byte btOpcodeVer=0; ++ u1Byte testCtrl=0; ++ ++ // 1. fill h2c parameters ++ btOpcode = 0x11; ++ h2cParaBuf[0] = 0x11; ++ h2cParaBuf[1] = 0x0; ++ h2cParaBuf[2] = 0x0; ++ h2cParaBuf[3] = 0x0; ++ h2cParaBuf[4] = 0x0; ++ h2cParaLen = 1; ++ // retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); ++ retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen); ++ ++ ++ // 3. construct respond status code and data. ++ if(BT_STATUS_BT_OP_SUCCESS != retStatus) ++ { ++ pBtRsp->status = ((btOpcode<<8)|retStatus); ++ DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); ++ return paraLen; ++ } ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ return paraLen; ++} ++ ++VOID ++mptbt_BtControlProcess( ++ PADAPTER Adapter, ++ PVOID pInBuf ++ ) ++{ ++ u1Byte H2C_Parameter[6] ={0}; ++ PBT_H2C pH2c=(PBT_H2C)&H2C_Parameter[0]; ++ PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); ++ PBT_REQ_CMD pBtReq=(PBT_REQ_CMD)pInBuf; ++ PBT_RSP_CMD pBtRsp=(PBT_RSP_CMD)&pMptCtx->mptOutBuf[0]; ++ u1Byte i; ++ ++ DBG_8192C("[MPT], mptbt_BtControlProcess()=========>\n"); ++ ++ DBG_8192C("[MPT], input opCodeVer=%d\n", pBtReq->opCodeVer); ++ DBG_8192C("[MPT], input OpCode=%d\n", pBtReq->OpCode); ++ DBG_8192C("[MPT], paraLength=%d \n", pBtReq->paraLength); ++ if(pBtReq->paraLength) ++ { ++ //DBG_8192C("[MPT], parameters(hex):0x%x %d \n",&pBtReq->pParamStart[0], pBtReq->paraLength); ++ } ++ ++ // The following we should maintain the User OP codes sent by upper layer ++ ++ pBtRsp->status = BT_STATUS_SUCCESS; ++ pMptCtx->mptOutLen = 4; //length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) ++ pBtRsp->paraLength = 0x0; ++ ++ _rtw_memset((PVOID)&pMptCtx->mptOutBuf[0], '\0',100); ++ ++ switch(pBtReq->OpCode) ++ { ++ case BT_UP_OP_BT_READY: ++ DBG_8192C("[MPT], OPcode : [BT_READY]\n"); ++ pBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_BT_SET_MODE: ++ DBG_8192C("[MPT], OPcode : [BT_SET_MODE]\n"); ++ pBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_BT_SET_TX_RX_PARAMETER: ++ DBG_8192C("[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\n"); ++ pBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_BT_SET_GENERAL: ++ DBG_8192C("[MPT], OPcode : [BT_SET_GENERAL]\n"); ++ pBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_BT_GET_GENERAL: ++ DBG_8192C("[MPT], OPcode : [BT_GET_GENERAL]\n"); ++ pBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_BT_TEST_CTRL: ++ DBG_8192C("[MPT], OPcode : [BT_TEST_CTRL]\n"); ++ pBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp); ++ break; ++ case BT_UP_OP_TEST_BT: ++ DBG_8192C("[MPT], OPcode : [TEST_BT]\n"); ++ pBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp); ++ break; ++ default: ++ DBG_8192C("[MPT], Error!! OPcode : UNDEFINED!!!!\n"); ++ pBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U; ++ pBtRsp->paraLength = 0x0; ++ break; ++ } ++ ++ DBG_8192C("pBtRsp->paraLength =%d \n",pBtRsp->paraLength); ++ ++ pMptCtx->mptOutLen += pBtRsp->paraLength; ++ ++ DBG_8192C("\n [MPT], OUT to DLL pMptCtx->mptOutLen=%d ,pBtRsp->paraLength =%d ",pMptCtx->mptOutLen,pBtRsp->paraLength); ++ ++ DBG_8192C("\n [MPT], mptbt_BtControlProcess()<=========\n"); ++} ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_cmd.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_cmd.c +new file mode 100644 +index 00000000..79bdc71a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_cmd.c +@@ -0,0 +1,3281 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_CMD_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_BR_EXT ++#include ++#endif //CONFIG_BR_EXT ++ ++#ifdef CONFIG_BT_COEXIST ++#include ++#endif // CONFIG_BT_COEXIST ++ ++/* ++Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. ++No irqsave is necessary. ++*/ ++ ++sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); ++ //_rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); ++ _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0); ++ ++ ++ _rtw_init_queue(&(pcmdpriv->cmd_queue)); ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ++ pcmdpriv->cmd_seq = 1; ++ ++ pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ); ++ ++ if (pcmdpriv->cmd_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ( (SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1)); ++ ++ pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); ++ ++ if (pcmdpriv->rsp_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ( (SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); ++ ++ pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#ifdef CONFIG_C2H_WK ++static void c2h_wk_callback(_workitem *work); ++#endif ++sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) ++{ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++#ifdef CONFIG_H2CLBK ++ _rtw_init_sema(&(pevtpriv->lbkevt_done), 0); ++ pevtpriv->lbkevt_limit = 0; ++ pevtpriv->lbkevt_num = 0; ++ pevtpriv->cmdevt_parm = NULL; ++#endif ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ATOMIC_SET(&pevtpriv->event_seq, 0); ++ pevtpriv->evt_done_cnt = 0; ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ ++ _rtw_init_sema(&(pevtpriv->evt_notify), 0); ++ _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0); ++ ++ pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); ++ if (pevtpriv->evt_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3); ++ ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ +4); ++ ++ if (pevtpriv->allocated_c2h_mem == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4\ ++ - ( (u32)(pevtpriv->allocated_c2h_mem) & 3); ++#ifdef PLATFORM_OS_XP ++ pevtpriv->pc2h_mdl= IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL); ++ ++ if(pevtpriv->pc2h_mdl == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl); ++#endif ++#endif //end of CONFIG_SDIO_HCI ++ ++ _rtw_init_queue(&(pevtpriv->evt_queue)); ++ ++exit: ++ ++#endif //end of CONFIG_EVENT_THREAD_MODE ++ ++#ifdef CONFIG_C2H_WK ++ _init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL); ++ pevtpriv->c2h_wk_alive = _FALSE; ++ pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN+1); ++#endif ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void _rtw_free_evt_priv (struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("+_rtw_free_evt_priv \n")); ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _rtw_free_sema(&(pevtpriv->evt_notify)); ++ _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema)); ++ ++ ++ if (pevtpriv->evt_allocated_buf) ++ rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); ++#endif ++ ++#ifdef CONFIG_C2H_WK ++ _cancel_workitem_sync(&pevtpriv->c2h_wk); ++ while(pevtpriv->c2h_wk_alive) ++ rtw_msleep_os(10); ++ ++ while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) { ++ void *c2h; ++ if ((c2h = rtw_cbuf_pop(pevtpriv->c2h_queue)) != NULL ++ && c2h != (void *)pevtpriv) { ++ rtw_mfree(c2h, 16); ++ } ++ } ++ rtw_cbuf_free(pevtpriv->c2h_queue); ++#endif ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("-_rtw_free_evt_priv \n")); ++ ++_func_exit_; ++ ++} ++ ++void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ ++ if(pcmdpriv){ ++ _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); ++ _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); ++ //_rtw_free_sema(&(pcmdpriv->cmd_done_sema)); ++ _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema)); ++ ++ if (pcmdpriv->cmd_allocated_buf) ++ rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); ++ ++ if (pcmdpriv->rsp_allocated_buf) ++ rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); ++ } ++_func_exit_; ++} ++ ++/* ++Calling Context: ++ ++rtw_enqueue_cmd can only be called between kernel thread, ++since only spin_lock is used. ++ ++ISR/Call-Back functions can't call this sub-function. ++ ++*/ ++ ++sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj) ++{ ++ _irqL irqL; ++ ++_func_enter_; ++ ++ if (obj == NULL) ++ goto exit; ++ ++ //_enter_critical_bh(&queue->lock, &irqL); ++ _enter_critical(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&obj->list, &queue->queue); ++ ++ //_exit_critical_bh(&queue->lock, &irqL); ++ _exit_critical(&queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) ++{ ++ _irqL irqL; ++ struct cmd_obj *obj; ++ ++_func_enter_; ++ ++ //_enter_critical_bh(&(queue->lock), &irqL); ++ _enter_critical(&queue->lock, &irqL); ++ if (rtw_is_list_empty(&(queue->queue))) ++ obj = NULL; ++ else ++ { ++ obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list); ++ rtw_list_delete(&obj->list); ++ } ++ ++ //_exit_critical_bh(&(queue->lock), &irqL); ++ _exit_critical(&queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return obj; ++} ++ ++u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) ++{ ++ u32 res; ++_func_enter_; ++ res = _rtw_init_cmd_priv (pcmdpriv); ++_func_exit_; ++ return res; ++} ++ ++u32 rtw_init_evt_priv (struct evt_priv *pevtpriv) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_init_evt_priv(pevtpriv); ++_func_exit_; ++ return res; ++} ++ ++void rtw_free_evt_priv (struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_evt_priv\n")); ++ _rtw_free_evt_priv(pevtpriv); ++_func_exit_; ++} ++ ++void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_cmd_priv\n")); ++ _rtw_free_cmd_priv(pcmdpriv); ++_func_exit_; ++} ++ ++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj); ++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) ++{ ++ u8 bAllow = _FALSE; //set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE ++ ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ //To decide allow or not ++ if( (adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect) ++ &&(!pcmdpriv->padapter->registrypriv.usbss_enable) ++ ) ++ { ++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ) ++ { ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; ++ if(pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) ++ { ++ //DBG_871X("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); ++ bAllow = _TRUE; ++ } ++ } ++ } ++ #endif ++ ++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan)) ++ bAllow = _TRUE; ++ ++ if( (pcmdpriv->padapter->hw_init_completed ==_FALSE && bAllow == _FALSE) ++ || pcmdpriv->cmdthd_running== _FALSE //com_thread not running ++ ) ++ { ++ //DBG_871X("%s:%s: drop cmdcode:%u, hw_init_completed:%u, cmdthd_running:%u\n", caller_func, __FUNCTION__, ++ // cmd_obj->cmdcode, ++ // pcmdpriv->padapter->hw_init_completed, ++ // pcmdpriv->cmdthd_running ++ //); ++ ++ return _FAIL; ++ } ++ return _SUCCESS; ++} ++ ++ ++ ++u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) ++{ ++ int res = _FAIL; ++ PADAPTER padapter = pcmdpriv->padapter; ++ ++_func_enter_; ++ ++ if (cmd_obj == NULL) { ++ goto exit; ++ } ++ ++ cmd_obj->padapter = padapter; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ //change pcmdpriv to primary's pcmdpriv ++ if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter) ++ pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv); ++#endif ++ ++ if( _FAIL == (res=rtw_cmd_filter(pcmdpriv, cmd_obj)) ) { ++ rtw_free_cmd_obj(cmd_obj); ++ goto exit; ++ } ++ ++ res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj); ++ ++ if(res == _SUCCESS) ++ _rtw_up_sema(&pcmdpriv->cmd_queue_sema); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) ++{ ++ struct cmd_obj *cmd_obj; ++ ++_func_enter_; ++ ++ cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); ++ ++_func_exit_; ++ return cmd_obj; ++} ++ ++void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ pcmdpriv->cmd_done_cnt++; ++ //_rtw_up_sema(&(pcmdpriv->cmd_done_sema)); ++_func_exit_; ++} ++ ++void rtw_free_cmd_obj(struct cmd_obj *pcmd) ++{ ++_func_enter_; ++ ++ if((pcmd->cmdcode!=_JoinBss_CMD_) &&(pcmd->cmdcode!= _CreateBss_CMD_)) ++ { ++ //free parmbuf in cmd_obj ++ rtw_mfree((unsigned char*)pcmd->parmbuf, pcmd->cmdsz); ++ } ++ ++ if(pcmd->rsp!=NULL) ++ { ++ if(pcmd->rspsz!= 0) ++ { ++ //free rsp in cmd_obj ++ rtw_mfree((unsigned char*)pcmd->rsp, pcmd->rspsz); ++ } ++ } ++ ++ //free cmd_obj ++ rtw_mfree((unsigned char*)pcmd, sizeof(struct cmd_obj)); ++ ++_func_exit_; ++} ++ ++ ++void rtw_stop_cmd_thread(_adapter *adapter) ++{ ++ if(adapter->cmdThread && adapter->cmdpriv.cmdthd_running == _TRUE ++ && adapter->cmdpriv.stop_req == 0) ++ { ++ adapter->cmdpriv.stop_req = 1; ++ _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); ++ _rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema); ++ } ++} ++ ++thread_return rtw_cmd_thread(thread_context context) ++{ ++ u8 ret; ++ struct cmd_obj *pcmd; ++ u8 *pcmdbuf, *prspbuf; ++ u8 (*cmd_hdl)(_adapter *padapter, u8* pbuf); ++ void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); ++ PADAPTER padapter = (PADAPTER)context; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ ++_func_enter_; ++ ++ thread_enter("RTW_CMD_THREAD"); ++ ++ pcmdbuf = pcmdpriv->cmd_buf; ++ prspbuf = pcmdpriv->rsp_buf; ++ ++ pcmdpriv->stop_req = 0; ++ pcmdpriv->cmdthd_running=_TRUE; ++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("start r871x rtw_cmd_thread !!!!\n")); ++ ++ while(1) ++ { ++ if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter)); ++ break; ++ } ++ ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved == _TRUE)) ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: DriverStopped(%d) SurpriseRemoved(%d) break at line %d\n", ++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved, __LINE__); ++ break; ++ } ++ ++ if (pcmdpriv->stop_req) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req); ++ break; ++ } ++ ++ if(rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) ++ { ++ //DBG_871X("%s: cmd queue is empty!\n", __func__); ++ continue; ++ } ++ ++#ifdef CONFIG_LPS_LCLK ++ if (rtw_register_cmd_alive(padapter) != _SUCCESS) ++ { ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: wait to leave LPS_LCLK\n", __FUNCTION__)); ++ continue; ++ } ++#endif ++ ++_next: ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: DriverStopped(%d) SurpriseRemoved(%d) break at line %d\n", ++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved, __LINE__); ++ break; ++ } ++ ++ if(!(pcmd = rtw_dequeue_cmd(pcmdpriv))) { ++#ifdef CONFIG_LPS_LCLK ++ rtw_unregister_cmd_alive(padapter); ++#endif ++ continue; ++ } ++ ++ if( _FAIL == rtw_cmd_filter(pcmdpriv, pcmd) ) ++ { ++ pcmd->res = H2C_DROPPED; ++ goto post_process; ++ } ++ ++ pcmdpriv->cmd_issued_cnt++; ++ ++ pcmd->cmdsz = _RND4((pcmd->cmdsz));//_RND4 ++ ++ _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz); ++ ++ if(pcmd->cmdcode <= (sizeof(wlancmds) /sizeof(struct cmd_hdl))) ++ { ++ cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns; ++ ++ if (cmd_hdl) ++ { ++ ret = cmd_hdl(pcmd->padapter, pcmdbuf); ++ pcmd->res = ret; ++ } ++ ++ pcmdpriv->cmd_seq++; ++ } ++ else ++ { ++ pcmd->res = H2C_PARAMETERS_ERROR; ++ } ++ ++ cmd_hdl = NULL; ++ ++post_process: ++ ++ //call callback function for post-processed ++ if(pcmd->cmdcode <= (sizeof(rtw_cmd_callback) /sizeof(struct _cmd_callback))) ++ { ++ pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; ++ if(pcmd_callback == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode)); ++ rtw_free_cmd_obj(pcmd); ++ } ++ else ++ { ++ //todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) ++ pcmd_callback(pcmd->padapter, pcmd);//need conider that free cmd_obj in rtw_cmd_callback ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("%s: cmdcode=0x%x callback not defined!\n", __FUNCTION__, pcmd->cmdcode)); ++ rtw_free_cmd_obj(pcmd); ++ } ++ ++ flush_signals_thread(); ++ ++ goto _next; ++ ++ } ++ pcmdpriv->cmdthd_running=_FALSE; ++ ++ ++ // free all cmd_obj resources ++ do{ ++ pcmd = rtw_dequeue_cmd(pcmdpriv); ++ if(pcmd==NULL) { ++#ifdef CONFIG_LPS_LCLK ++ rtw_unregister_cmd_alive(padapter); ++#endif ++ break; ++ } ++ ++ //DBG_871X("%s: leaving... drop cmdcode:%u\n", __FUNCTION__, pcmd->cmdcode); ++ ++ rtw_free_cmd_obj(pcmd); ++ }while(1); ++ ++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); ++ ++_func_exit_; ++ ++ thread_exit(); ++ ++} ++ ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) ++{ ++ _irqL irqL; ++ int res; ++ _queue *queue = &pevtpriv->evt_queue; ++ ++_func_enter_; ++ ++ res = _SUCCESS; ++ ++ if (obj == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&obj->list, &queue->queue); ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ //rtw_evt_notify_isr(pevtpriv); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++struct evt_obj *rtw_dequeue_evt(_queue *queue) ++{ ++ _irqL irqL; ++ struct evt_obj *pevtobj; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ if (rtw_is_list_empty(&(queue->queue))) ++ pevtobj = NULL; ++ else ++ { ++ pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list); ++ rtw_list_delete(&pevtobj->list); ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pevtobj; ++} ++ ++void rtw_free_evt_obj(struct evt_obj *pevtobj) ++{ ++_func_enter_; ++ ++ if(pevtobj->parmbuf) ++ rtw_mfree((unsigned char*)pevtobj->parmbuf, pevtobj->evtsz); ++ ++ rtw_mfree((unsigned char*)pevtobj, sizeof(struct evt_obj)); ++ ++_func_exit_; ++} ++ ++void rtw_evt_notify_isr(struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ pevtpriv->evt_done_cnt++; ++ _rtw_up_sema(&(pevtpriv->evt_notify)); ++_func_exit_; ++} ++#endif ++ ++ ++/* ++u8 rtw_setstandby_cmd(unsigned char *adapter) ++*/ ++u8 rtw_setstandby_cmd(_adapter *padapter, uint action) ++{ ++ struct cmd_obj* ph2c; ++ struct usb_suspend_parm* psetusbsuspend; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ ++ u8 ret = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ psetusbsuspend = (struct usb_suspend_parm*)rtw_zmalloc(sizeof(struct usb_suspend_parm)); ++ if (psetusbsuspend == NULL) { ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ psetusbsuspend->action = action; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend)); ++ ++ ret = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++/* ++rtw_sitesurvey_cmd(~) ++ ### NOTE:#### (!!!!) ++ MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock ++*/ ++u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, ++ struct rtw_ieee80211_channel *ch, int ch_num) ++{ ++ u8 res = _FAIL; ++ struct cmd_obj *ph2c; ++ struct sitesurvey_parm *psurveyPara; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++#ifdef CONFIG_LPS ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE){ ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1); ++ } ++#endif ++ ++#ifdef CONFIG_P2P_PS ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); ++ } ++#endif //CONFIG_P2P_PS ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) ++ return _FAIL; ++ ++ psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm)); ++ if (psurveyPara == NULL) { ++ rtw_mfree((unsigned char*) ph2c, sizeof(struct cmd_obj)); ++ return _FAIL; ++ } ++ ++ rtw_free_network_queue(padapter, _FALSE); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("%s: flush network queue\n", __FUNCTION__)); ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); ++ ++ /* psurveyPara->bsslimit = 48; */ ++ psurveyPara->scan_mode = pmlmepriv->scan_mode; ++ ++ /* prepare ssid list */ ++ if (ssid) { ++ int i; ++ for (i=0; issid[i], &ssid[i], sizeof(NDIS_802_11_SSID)); ++ psurveyPara->ssid_num++; ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter), ++ psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); ++ } ++ } ++ } ++ ++ /* prepare channel list */ ++ if (ch) { ++ int i; ++ for (i=0; ich[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); ++ psurveyPara->ch_num++; ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), ++ psurveyPara->ch[i].hw_value); ++ } ++ } ++ } ++ ++ set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++ if(res == _SUCCESS) { ++ ++ pmlmepriv->scan_start_time = rtw_get_current_time(); ++ ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE) ++ _set_timer(&pmlmepriv->scan_to_timer, SURVEY_TO * ( padapter->mlmeextpriv.max_chan_nums + ( padapter->mlmeextpriv.max_chan_nums / RTW_SCAN_NUM_OF_CH ) * RTW_STAY_AP_CH_MILLISECOND ) + 1000 ); ++ else ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ _set_timer(&pmlmepriv->scan_to_timer, SCANNING_TIMEOUT); ++ ++ rtw_led_control(padapter, LED_CTL_SITE_SURVEY); ++ ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ } else { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) ++{ ++ struct cmd_obj* ph2c; ++ struct setdatarate_parm* pbsetdataratepara; ++ struct cmd_priv* pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pbsetdataratepara = (struct setdatarate_parm*)rtw_zmalloc(sizeof(struct setdatarate_parm)); ++ if (pbsetdataratepara == NULL) { ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate)); ++#ifdef MP_FIRMWARE_OFFLOAD ++ pbsetdataratepara->curr_rateidx = *(u32*)rateset; ++// _rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32)); ++#else ++ pbsetdataratepara->mac_id = 5; ++ _rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates); ++#endif ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset) ++{ ++ struct cmd_obj* ph2c; ++ struct setbasicrate_parm* pssetbasicratepara; ++ struct cmd_priv* pcmdpriv=&padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ res= _FAIL; ++ goto exit; ++ } ++ pssetbasicratepara = (struct setbasicrate_parm*)rtw_zmalloc(sizeof(struct setbasicrate_parm)); ++ ++ if (pssetbasicratepara == NULL) { ++ rtw_mfree((u8*) ph2c, sizeof(struct cmd_obj)); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_); ++ ++ _rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++ ++/* ++unsigned char rtw_setphy_cmd(unsigned char *adapter) ++ ++1. be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program ++2. for AdHoc/Ap mode or mp mode? ++ ++*/ ++u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch) ++{ ++ struct cmd_obj* ph2c; ++ struct setphy_parm* psetphypara; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++// struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++// struct registry_priv* pregistry_priv = &padapter->registrypriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetphypara = (struct setphy_parm*)rtw_zmalloc(sizeof(struct setphy_parm)); ++ ++ if(psetphypara==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("CH=%d, modem=%d", ch, modem)); ++ ++ psetphypara->modem = modem; ++ psetphypara->rfchannel = ch; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_setbbreg_cmd(_adapter*padapter, u8 offset, u8 val) ++{ ++ struct cmd_obj* ph2c; ++ struct writeBB_parm* pwritebbparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pwritebbparm = (struct writeBB_parm*)rtw_zmalloc(sizeof(struct writeBB_parm)); ++ ++ if(pwritebbparm==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg)); ++ ++ pwritebbparm->offset = offset; ++ pwritebbparm->value = val; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct readBB_parm* prdbbparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ prdbbparm = (struct readBB_parm*)rtw_zmalloc(sizeof(struct readBB_parm)); ++ ++ if(prdbbparm ==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ return _FAIL; ++ } ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetBBReg); ++ ph2c->parmbuf = (unsigned char *)prdbbparm; ++ ph2c->cmdsz = sizeof(struct readBB_parm); ++ ph2c->rsp = pval; ++ ph2c->rspsz = sizeof(struct readBB_rsp); ++ ++ prdbbparm ->offset = offset; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val) ++{ ++ struct cmd_obj* ph2c; ++ struct writeRF_parm* pwriterfparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pwriterfparm = (struct writeRF_parm*)rtw_zmalloc(sizeof(struct writeRF_parm)); ++ ++ if(pwriterfparm==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg)); ++ ++ pwriterfparm->offset = offset; ++ pwriterfparm->value = val; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct readRF_parm* prdrfparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ prdrfparm = (struct readRF_parm*)rtw_zmalloc(sizeof(struct readRF_parm)); ++ if(prdrfparm ==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetRFReg); ++ ph2c->parmbuf = (unsigned char *)prdrfparm; ++ ph2c->cmdsz = sizeof(struct readRF_parm); ++ ph2c->rsp = pval; ++ ph2c->rspsz = sizeof(struct readRF_rsp); ++ ++ prdrfparm ->offset = offset; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_getbbrfreg_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _func_enter_; ++ ++ //rtw_free_cmd_obj(pcmd); ++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); ++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ padapter->mppriv.workparam.bcompleted= _TRUE; ++#endif ++_func_exit_; ++} ++ ++void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _func_enter_; ++ ++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); ++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ padapter->mppriv.workparam.bcompleted= _TRUE; ++#endif ++ ++_func_exit_; ++} ++ ++u8 rtw_createbss_cmd(_adapter *padapter) ++{ ++ struct cmd_obj* pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ rtw_led_control(padapter, LED_CTL_START_TO_LINK); ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0){ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for Any SSid:%s\n",pmlmepriv->assoc_ssid.Ssid)); ++ } else { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = _CreateBss_CMD_; ++ pcmd->parmbuf = (unsigned char *)pdev_network; ++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX*)pdev_network); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ pdev_network->Length = pcmd->cmdsz; ++ ++#ifdef CONFIG_RTL8712 ++ //notes: translate IELength & Length after assign the Length to cmdsz; ++ pdev_network->Length = cpu_to_le32(pcmd->cmdsz); ++ pdev_network->IELength = cpu_to_le32(pdev_network->IELength); ++ pdev_network->Ssid.SsidLength = cpu_to_le32(pdev_network->Ssid.SsidLength); ++#endif ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz) ++{ ++ struct cmd_obj* pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = GEN_CMD_CODE(_CreateBss); ++ pcmd->parmbuf = pbss; ++ pcmd->cmdsz = sz; ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork) ++{ ++ u8 *auth, res = _SUCCESS; ++ uint t_len = 0; ++ WLAN_BSSID_EX *psecnetwork; ++ struct cmd_obj *pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++#ifdef CONFIG_80211N_HT ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++#endif //CONFIG_80211N_HT ++ NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++_func_enter_; ++ ++ rtw_led_control(padapter, LED_CTL_START_TO_LINK); ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0){ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n")); ++ } else { ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n")); ++ goto exit; ++ } ++ /* // for IEs is pointer ++ t_len = sizeof (ULONG) + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + ++ sizeof (NDIS_802_11_SSID) + sizeof (ULONG) + ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + ++ sizeof (NDIS_802_11_CONFIGURATION) + ++ sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) + ++ sizeof (NDIS_802_11_RATES_EX)+ sizeof(WLAN_PHY_INFO)+ sizeof (ULONG) + MAX_IE_SZ; ++ */ ++ //for IEs is fix buf size ++ t_len = sizeof(WLAN_BSSID_EX); ++ ++ ++ //for hidden ap to set fw_state here ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) != _TRUE) ++ { ++ switch(ndis_network_mode) ++ { ++ case Ndis802_11IBSS: ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ break; ++ ++ case Ndis802_11Infrastructure: ++ set_fwstate(pmlmepriv, WIFI_STATION_STATE); ++ break; ++ ++ case Ndis802_11APMode: ++ case Ndis802_11AutoUnknown: ++ case Ndis802_11InfrastructureMax: ++ break; ++ ++ } ++ } ++ ++ psecnetwork=(WLAN_BSSID_EX *)&psecuritypriv->sec_bss; ++ if(psecnetwork==NULL) ++ { ++ if(pcmd !=NULL) ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ ++ res=_FAIL; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n")); ++ ++ goto exit; ++ } ++ ++ _rtw_memset(psecnetwork, 0, t_len); ++ ++ _rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network)); ++ ++ auth=&psecuritypriv->authenticator_ie[0]; ++ psecuritypriv->authenticator_ie[0]=(unsigned char)psecnetwork->IELength; ++ ++ if((psecnetwork->IELength-12) < (256-1)) { ++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength-12); ++ } else { ++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256-1)); ++ } ++ ++ psecnetwork->IELength = 0; ++ // Added by Albert 2009/02/18 ++ // If the the driver wants to use the bssid to create the connection. ++ // If not, we have to copy the connecting AP's MAC address to it so that ++ // the driver just has the bssid information for PMKIDList searching. ++ ++ if ( pmlmepriv->assoc_by_bssid == _FALSE ) ++ { ++ _rtw_memcpy( &pmlmepriv->assoc_bssid[ 0 ], &pnetwork->network.MacAddress[ 0 ], ETH_ALEN ); ++ } ++ ++ psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); ++ ++ ++ pqospriv->qos_option = 0; ++ ++ if(pregistrypriv->wmm_enable) ++ { ++ u32 tmp_len; ++ ++ tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); ++ ++ if (psecnetwork->IELength != tmp_len) ++ { ++ psecnetwork->IELength = tmp_len; ++ pqospriv->qos_option = 1; //There is WMM IE in this corresp. beacon ++ } ++ else ++ { ++ pqospriv->qos_option = 0;//There is no WMM IE in this corresp. beacon ++ } ++ } ++ ++#ifdef CONFIG_80211N_HT ++ phtpriv->ht_option = _FALSE; ++ if(pregistrypriv->ht_enable) ++ { ++ // Added by Albert 2010/06/23 ++ // For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. ++ // Especially for Realtek 8192u SoftAP. ++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_ ) && ++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_ ) && ++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_ )) ++ { ++ //rtw_restructure_ht_ie ++ rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], ++ pnetwork->network.IELength, &psecnetwork->IELength); ++ } ++ } ++ ++#endif ++ ++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength); ++ ++ if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_TENDA) ++ adapter_to_pwrctl(padapter)->smart_ps = 0; ++ else ++ adapter_to_pwrctl(padapter)->smart_ps = padapter->registrypriv.smart_ps; ++ ++ DBG_871X("%s: smart_ps=%d\n", __func__, adapter_to_pwrctl(padapter)->smart_ps); ++ ++ #if 0 ++ psecuritypriv->supplicant_ie[0]=(u8)psecnetwork->IELength; ++ ++ if(psecnetwork->IELength < (256-1)) ++ { ++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength); ++ } ++ else ++ { ++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256-1)); ++ } ++ #endif ++ ++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz(psecnetwork);//get cmdsz before endian conversion ++ ++#ifdef CONFIG_RTL8712 ++ //wlan_network endian conversion ++ psecnetwork->Length = cpu_to_le32(psecnetwork->Length); ++ psecnetwork->Ssid.SsidLength= cpu_to_le32(psecnetwork->Ssid.SsidLength); ++ psecnetwork->Privacy = cpu_to_le32(psecnetwork->Privacy); ++ psecnetwork->Rssi = cpu_to_le32(psecnetwork->Rssi); ++ psecnetwork->NetworkTypeInUse = cpu_to_le32(psecnetwork->NetworkTypeInUse); ++ psecnetwork->Configuration.ATIMWindow = cpu_to_le32(psecnetwork->Configuration.ATIMWindow); ++ psecnetwork->Configuration.BeaconPeriod = cpu_to_le32(psecnetwork->Configuration.BeaconPeriod); ++ psecnetwork->Configuration.DSConfig = cpu_to_le32(psecnetwork->Configuration.DSConfig); ++ psecnetwork->Configuration.FHConfig.DwellTime=cpu_to_le32(psecnetwork->Configuration.FHConfig.DwellTime); ++ psecnetwork->Configuration.FHConfig.HopPattern=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopPattern); ++ psecnetwork->Configuration.FHConfig.HopSet=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopSet); ++ psecnetwork->Configuration.FHConfig.Length=cpu_to_le32(psecnetwork->Configuration.FHConfig.Length); ++ psecnetwork->Configuration.Length = cpu_to_le32(psecnetwork->Configuration.Length); ++ psecnetwork->InfrastructureMode = cpu_to_le32(psecnetwork->InfrastructureMode); ++ psecnetwork->IELength = cpu_to_le32(psecnetwork->IELength); ++#endif ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = _JoinBss_CMD_;//GEN_CMD_CODE(_JoinBss) ++ pcmd->parmbuf = (unsigned char *)psecnetwork; ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_disassoc_cmd(_adapter*padapter, u32 deauth_timeout_ms, bool enqueue) /* for sta_mode */ ++{ ++ struct cmd_obj *cmdobj = NULL; ++ struct disconnect_parm *param = NULL; ++ struct cmd_priv *cmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n")); ++ ++ /* prepare cmd parameter */ ++ param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); ++ if (param == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ param->deauth_timeout_ms = deauth_timeout_ms; ++ ++ if (enqueue) { ++ /* need enqueue, prepare cmd_obj and enqueue */ ++ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); ++ if (cmdobj == NULL) { ++ res = _FAIL; ++ rtw_mfree((u8 *)param, sizeof(*param)); ++ goto exit; ++ } ++ init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_); ++ res = rtw_enqueue_cmd(cmdpriv, cmdobj); ++ } else { ++ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ ++ if (H2C_SUCCESS != disconnect_hdl(padapter, (u8 *)param)) ++ res = _FAIL; ++ rtw_mfree((u8 *)param, sizeof(*param)); ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue) ++{ ++ struct cmd_obj* ph2c; ++ struct setopmode_parm* psetop; ++ ++ struct cmd_priv *pcmdpriv= &padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ psetop = (struct setopmode_parm*)rtw_zmalloc(sizeof(struct setopmode_parm)); ++ ++ if(psetop==NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ psetop->mode = (u8)networktype; ++ ++ if(enqueue){ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ rtw_mfree((u8 *)psetop, sizeof(*psetop)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else{ ++ setopmode_hdl(padapter, (u8 *)psetop); ++ rtw_mfree((u8 *)psetop, sizeof(*psetop)); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key, bool enqueue) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct set_stakey_rsp *psetstakey_rsp = NULL; ++ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct sta_info* sta = (struct sta_info* )psta; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ _rtw_memcpy(psetstakey_para->addr, sta->hwaddr,ETH_ALEN); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)){ ++#ifdef CONFIG_TDLS ++ if(sta->tdls_sta_state&TDLS_LINKED_STATE) ++ psetstakey_para->algorithm=(u8)sta->dot118021XPrivacy; ++ else ++#endif //CONFIG_TDLS ++ psetstakey_para->algorithm =(unsigned char) psecuritypriv->dot11PrivacyAlgrthm; ++ }else{ ++ GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); ++ } ++ ++ if (unicast_key == _TRUE) { ++#ifdef CONFIG_TDLS ++ if((sta->tdls_sta_state&TDLS_LINKED_STATE)==TDLS_LINKED_STATE) ++ _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16); ++ else ++#endif //CONFIG_TDLS ++ _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); ++ } ++ else { ++ _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); ++ } ++ ++ //jeff: set this becasue at least sw key is ready ++ padapter->securitypriv.busetkipkey=_TRUE; ++ ++ if(enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp)); ++ if(psetstakey_rsp == NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ph2c->rsp = (u8 *) psetstakey_rsp; ++ ph2c->rspsz = sizeof(struct set_stakey_rsp); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else{ ++ set_stakey_hdl(padapter, (u8 *)psetstakey_para); ++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct set_stakey_rsp *psetstakey_rsp = NULL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct sta_info* sta = (struct sta_info* )psta; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ if(!enqueue) ++ { ++ clear_cam_entry(padapter, entry); ++ } ++ else ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp)); ++ if(psetstakey_rsp == NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ph2c->rsp = (u8 *) psetstakey_rsp; ++ ph2c->rspsz = sizeof(struct set_stakey_rsp); ++ ++ _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); ++ ++ psetstakey_para->algorithm = _NO_PRIVACY_; ++ ++ psetstakey_para->id = entry; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table) ++{ ++ struct cmd_obj* ph2c; ++ struct setratable_parm * psetrttblparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetrttblparm = (struct setratable_parm*)rtw_zmalloc(sizeof(struct setratable_parm)); ++ ++ if(psetrttblparm==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); ++ ++ _rtw_memcpy(psetrttblparm,prate_table,sizeof(struct setratable_parm)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct getratable_parm * pgetrttblparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pgetrttblparm = (struct getratable_parm*)rtw_zmalloc(sizeof(struct getratable_parm)); ++ ++ if(pgetrttblparm==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++// init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetRaTable); ++ ph2c->parmbuf = (unsigned char *)pgetrttblparm; ++ ph2c->cmdsz = sizeof(struct getratable_parm); ++ ph2c->rsp = (u8*)pval; ++ ph2c->rspsz = sizeof(struct getratable_rsp); ++ ++ pgetrttblparm ->rsvd = 0x0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr) ++{ ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct cmd_obj* ph2c; ++ struct set_assocsta_parm *psetassocsta_para; ++ struct set_stakey_rsp *psetassocsta_rsp = NULL; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetassocsta_para = (struct set_assocsta_parm*)rtw_zmalloc(sizeof(struct set_assocsta_parm)); ++ if(psetassocsta_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ psetassocsta_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_assocsta_rsp)); ++ if(psetassocsta_rsp==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm)); ++ return _FAIL; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_); ++ ph2c->rsp = (u8 *) psetassocsta_rsp; ++ ph2c->rspsz = sizeof(struct set_assocsta_rsp); ++ ++ _rtw_memcpy(psetassocsta_para->addr, mac_addr,ETH_ALEN); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ } ++ ++u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr) ++{ ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct cmd_obj* ph2c; ++ struct addBaReq_parm *paddbareq_parm; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ paddbareq_parm = (struct addBaReq_parm*)rtw_zmalloc(sizeof(struct addBaReq_parm)); ++ if(paddbareq_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ paddbareq_parm->tid = tid; ++ _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN); ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq)); ++ ++ //DBG_871X("rtw_addbareq_cmd, tid=%d\n", tid); ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++//add for CONFIG_IEEE80211W, none 11w can use it ++u8 rtw_reset_securitypriv_cmd(_adapter*padapter) ++{ ++ struct cmd_obj* ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtw_free_assoc_resources_cmd(_adapter*padapter) ++{ ++ struct cmd_obj* ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtw_dynamic_chk_wk_cmd(_adapter*padapter) ++{ ++ struct cmd_obj* ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter) ++ pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv); ++#endif ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) ++{ ++ struct cmd_obj *pcmdobj; ++ struct set_ch_parm *set_ch_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", ++ FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset); ++ ++ /* check input parameter */ ++ ++ /* prepare cmd parameter */ ++ set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm)); ++ if (set_ch_parm == NULL) { ++ res= _FAIL; ++ goto exit; ++ } ++ set_ch_parm->ch = ch; ++ set_ch_parm->bw = bw; ++ set_ch_parm->ch_offset = ch_offset; ++ ++ if (enqueue) { ++ /* need enqueue, prepare cmd_obj and enqueue */ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ } else { ++ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ ++ if( H2C_SUCCESS !=set_ch_hdl(padapter, (u8 *)set_ch_parm) ) ++ res = _FAIL; ++ ++ rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); ++ } ++ ++ /* do something based on res... */ ++ ++exit: ++ ++ DBG_871X(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enqueue) ++{ ++ struct cmd_obj* pcmdobj; ++ struct SetChannelPlan_param *setChannelPlan_param; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_chplan_cmd\n")); ++ ++ //check input parameter ++ if(!rtw_is_channel_plan_valid(chplan)) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ //prepare cmd parameter ++ setChannelPlan_param = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(struct SetChannelPlan_param)); ++ if(setChannelPlan_param == NULL) { ++ res= _FAIL; ++ goto exit; ++ } ++ setChannelPlan_param->channel_plan=chplan; ++ ++ if(enqueue) ++ { ++ //need enqueue, prepare cmd_obj and enqueue ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelPlan_param, GEN_CMD_CODE(_SetChannelPlan)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ } ++ else ++ { ++ //no need to enqueue, do the cmd hdl directly and free cmd parameter ++ if( H2C_SUCCESS !=set_chplan_hdl(padapter, (unsigned char *)setChannelPlan_param) ) ++ res = _FAIL; ++ ++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param)); ++ } ++ ++ //do something based on res... ++ if(res == _SUCCESS) ++ padapter->mlmepriv.ChannelPlan = chplan; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed) ++{ ++ struct cmd_obj* pcmdobj; ++ struct LedBlink_param *ledBlink_param; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param)); ++ if(ledBlink_param == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ ledBlink_param->pLed=pLed; ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no) ++{ ++ struct cmd_obj* pcmdobj; ++ struct SetChannelSwitch_param*setChannelSwitch_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ setChannelSwitch_param = (struct SetChannelSwitch_param *)rtw_zmalloc(sizeof(struct SetChannelSwitch_param)); ++ if(setChannelSwitch_param == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ setChannelSwitch_param->new_ch_no=new_ch_no; ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelSwitch_param, GEN_CMD_CODE(_SetChannelSwitch)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) ++{ ++ struct cmd_obj* pcmdobj; ++ struct TDLSoption_param *TDLSoption; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++#ifdef CONFIG_TDLS ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ TDLSoption= (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param)); ++ if(TDLSoption == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_spinlock(&(padapter->tdlsinfo.cmd_lock)); ++ _rtw_memcpy(TDLSoption->addr, addr, 6); ++ TDLSoption->option = option; ++ _rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock)); ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++#endif //CONFIG_TDLS ++ ++exit: ++ ++ ++_func_exit_; ++ ++ return res; ++} ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++u8 rtw_event_polling_cmd(_adapter*padapter) ++{ ++ struct cmd_obj* ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++#if defined(CONFIG_CONCURRENT_MODE) ++ if (padapter->adapter_type != PRIMARY_ADAPTER) ++ { ++ return _FAIL; ++ } ++#endif ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = EVENT_POLLING_CID; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = (u8 *)padapter; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ _func_exit_; ++ ++ return res; ++} ++#endif ++ ++static void traffic_status_watchdog(_adapter *padapter) ++{ ++#ifdef CONFIG_LPS ++ u8 bEnterPS; ++#endif ++ u16 BusyThreshold = 200;// 100; ++ u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; ++ u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; ++#ifdef CONFIG_FTP_PROTECT ++ u16 bPktCount = 0; ++#endif ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); ++#endif //CONFIG_TDLS ++ ++ RT_LINK_DETECT_T * link_detect = &pmlmepriv->LinkDetectInfo; ++ ++ // ++ // Determine if our traffic is busy now ++ // ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) ++ { ++ // if we raise bBusyTraffic in last watchdog, using lower threshold. ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic) ++ BusyThreshold =180; // 75; ++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold || ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold ) ++ { ++ bBusyTraffic = _TRUE; ++ ++ if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) ++ bRxBusyTraffic = _TRUE; ++ else ++ bTxBusyTraffic = _TRUE; ++ } ++ ++ // Higher Tx/Rx data. ++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 || ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000 ) ++ { ++ bHigherBusyTraffic = _TRUE; ++ ++ if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) ++ bHigherBusyRxTraffic = _TRUE; ++ else ++ bHigherBusyTxTraffic = _TRUE; ++ } ++ ++#ifdef CONFIG_FTP_PROTECT ++ DBG_871X("RX in period:%d, TX in period:%d, ftp_lock_flag:%d\n", ++ pmlmepriv->LinkDetectInfo.NumRxOkInPeriod, ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, ++ pmlmepriv->ftp_lock_flag); ++ ++ bPktCount = pmlmepriv->LinkDetectInfo.NumRxOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod; ++ if (bPktCount > 20 && !pmlmepriv->ftp_lock_flag) { ++ pmlmepriv->ftp_lock_flag = 1; ++ rtw_lock_suspend(); ++ } else if(bPktCount == 0 && pmlmepriv->ftp_lock_flag) { ++ pmlmepriv->ftp_lock_flag = 0; ++ rtw_unlock_suspend(); ++ } ++#endif //CONFIG_KEEP_FTP_TRANSMIT ++ ++#ifdef CONFIG_TRAFFIC_PROTECT ++#define TX_ACTIVE_TH 2 ++#define RX_ACTIVE_TH 1 ++#define TRAFFIC_PROTECT_PERIOD_MS 4500 ++ ++ if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH ++ || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) { ++ ++ DBG_871X_LEVEL(_drv_info_, FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n", ++ FUNC_ADPT_ARG(padapter), ++ TRAFFIC_PROTECT_PERIOD_MS, ++ link_detect->NumTxOkInPeriod, ++ link_detect->NumRxUnicastOkInPeriod); ++ ++ rtw_lock_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS); ++ } ++#endif ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_TDLS_AUTOSETUP ++ if( ( ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD ) == 0 ) //10 * 2sec, periodically sending ++ issue_tdls_dis_req( padapter, NULL ); ++ ptdlsinfo->watchdog_count++; ++#endif //CONFIG_TDLS_AUTOSETUP ++#endif //CONFIG_TDLS ++ ++#ifdef CONFIG_LPS ++#ifdef CONFIG_BT_COEXIST ++ if (BT_1Ant(padapter) == _FALSE) ++#endif ++ { ++ // check traffic for powersaving. ++ if( ((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8 ) || ++ (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) ) ++ { ++ //DBG_871X("Tx = %d, Rx = %d \n",pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); ++ bEnterPS= _FALSE; ++ } ++ else ++ { ++ bEnterPS= _TRUE; ++ } ++ ++ // LeisurePS only work in infra mode. ++ if(bEnterPS) ++ { ++ LPS_Enter(padapter); ++ } ++ else ++ { ++ LPS_Leave(padapter); ++ } ++ } ++#endif // CONFIG_LPS ++ } ++ else ++ { ++#ifdef CONFIG_LPS ++ LPS_Leave(padapter); ++#endif ++ } ++ ++ pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic; ++ pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic; ++} ++ ++void dynamic_chk_wk_hdl(_adapter *padapter, u8 *pbuf, int sz); ++void dynamic_chk_wk_hdl(_adapter *padapter, u8 *pbuf, int sz) ++{ ++ struct mlme_priv *pmlmepriv; ++ ++ padapter = (_adapter *)pbuf; ++ pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ expire_timeout_chk(padapter); ++ } ++#endif ++#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ rtw_hal_sreset_xmit_status_check(padapter); ++ #endif ++ ++ //if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) ++ { ++ linked_status_chk(padapter); ++ traffic_status_watchdog(padapter); ++ } ++ ++ rtw_hal_dm_watchdog(padapter); ++ ++ //check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ ++#ifdef CONFIG_BT_COEXIST ++ // ++ // BT-Coexist ++ // ++ BT_CoexistMechanism(padapter); ++#endif ++} ++ ++#ifdef CONFIG_LPS ++ ++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type); ++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 mstatus; ++ ++_func_enter_; ++ ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ { ++ return; ++ } ++ ++ switch(lps_ctrl_type) ++ { ++ case LPS_CTRL_SCAN: ++ //DBG_871X("LPS_CTRL_SCAN \n"); ++#ifdef CONFIG_BT_COEXIST ++ BT_WifiScanNotify(padapter, _TRUE); ++ if (BT_1Ant(padapter) == _FALSE) ++#endif ++ { ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { //connect ++ LPS_Leave(padapter); ++ } ++ } ++ break; ++ case LPS_CTRL_JOINBSS: ++ //DBG_871X("LPS_CTRL_JOINBSS \n"); ++ LPS_Leave(padapter); ++ break; ++ case LPS_CTRL_CONNECT: ++ //DBG_871X("LPS_CTRL_CONNECT \n"); ++ mstatus = 1;//connect ++ // Reset LPS Setting ++ pwrpriv->LpsIdleCount = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); ++#ifdef CONFIG_BT_COEXIST ++ BT_WifiMediaStatusNotify(padapter, mstatus); ++#endif ++ break; ++ case LPS_CTRL_DISCONNECT: ++ //DBG_871X("LPS_CTRL_DISCONNECT \n"); ++ mstatus = 0;//disconnect ++#ifdef CONFIG_BT_COEXIST ++ BT_WifiMediaStatusNotify(padapter, mstatus); ++ if (BT_1Ant(padapter) == _FALSE) ++#endif ++ { ++ LPS_Leave(padapter); ++ } ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); ++ break; ++ case LPS_CTRL_SPECIAL_PACKET: ++ //DBG_871X("LPS_CTRL_SPECIAL_PACKET \n"); ++ pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time(); ++#ifdef CONFIG_BT_COEXIST ++ BT_SpecialPacketNotify(padapter); ++ if (BT_1Ant(padapter) == _FALSE) ++#endif ++ { ++ LPS_Leave(padapter); ++ } ++ break; ++ case LPS_CTRL_LEAVE: ++ //DBG_871X("LPS_CTRL_LEAVE \n"); ++#ifdef CONFIG_BT_COEXIST ++ BT_LpsLeave(padapter); ++ if (BT_1Ant(padapter) == _FALSE) ++#endif ++ { ++ LPS_Leave(padapter); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ //struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ //if(!pwrctrlpriv->bLeisurePs) ++ // return res; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->iface_type != IFACE_PORT0) ++ return res; ++#endif ++ ++ if(enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID; ++ pdrvextra_cmd_parm->type_size = lps_ctrl_type; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else ++ { ++ lps_ctrl_wk_hdl(padapter, lps_ctrl_type); ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#endif ++ ++#if (RATE_ADAPTIVE_SUPPORT==1) ++void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime) ++{ ++ rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime)); ++} ++ ++u8 rtw_rpt_timer_cfg_cmd(_adapter*padapter, u16 minRptTime) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID; ++ pdrvextra_cmd_parm->type_size = minRptTime; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#endif ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++void antenna_select_wk_hdl(_adapter *padapter, u8 antenna) ++{ ++ rtw_hal_set_hwreg(padapter, HW_VAR_ANTENNA_DIVERSITY_SELECT, (u8 *)(&antenna)); ++} ++ ++u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 bSupportAntDiv = _FALSE; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); ++ if(_FALSE == bSupportAntDiv ) return res; ++ ++ if(_TRUE == enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID; ++ pdrvextra_cmd_parm->type_size = antenna; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else{ ++ antenna_select_wk_hdl(padapter,antenna ); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++#endif ++ ++void power_saving_wk_hdl(_adapter *padapter, u8 *pbuf, int sz); ++void power_saving_wk_hdl(_adapter *padapter, u8 *pbuf, int sz) ++{ ++ rtw_ps_processor(padapter); ++} ++ ++//add for CONFIG_IEEE80211W, none 11w can use it ++void reset_securitypriv_hdl(_adapter *padapter) ++{ ++ rtw_reset_securitypriv(padapter); ++} ++ ++void free_assoc_resources_hdl(_adapter *padapter) ++{ ++ rtw_free_assoc_resources(padapter, 1); ++} ++ ++#ifdef CONFIG_P2P ++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ return res; ++ } ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID; ++ pdrvextra_cmd_parm->type_size = intCmdType; // As the command tppe. ++ pdrvextra_cmd_parm->pbuf = NULL; // Must be NULL here ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++#endif //CONFIG_P2P ++ ++u8 rtw_ps_cmd(_adapter*padapter) ++{ ++ struct cmd_obj *ppscmd; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res = _SUCCESS; ++_func_enter_; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->adapter_type != PRIMARY_ADAPTER) ++ goto exit; ++#endif ++ ++ ppscmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ppscmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ppscmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#ifdef CONFIG_AP_MODE ++ ++static void rtw_chk_hi_queue_hdl(_adapter *padapter) ++{ ++ int cnt=0; ++ struct sta_info *psta_bmc; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(!psta_bmc) ++ return; ++ ++ if(psta_bmc->sleepq_len==0) ++ { ++ u8 val = 0; ++ ++ //while((rtw_read32(padapter, 0x414)&0x00ffff00)!=0) ++ //while((rtw_read32(padapter, 0x414)&0x0000ff00)!=0) ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &val); ++ ++ while(_FALSE == val) ++ { ++ rtw_msleep_os(100); ++ ++ cnt++; ++ ++ if(cnt>10) ++ break; ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &val); ++ } ++ ++ if(cnt<=10) ++ { ++ pstapriv->tim_bitmap &= ~BIT(0); ++ pstapriv->sta_dz_bitmap &= ~BIT(0); ++ ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ else //re check again ++ { ++ rtw_chk_hi_queue_cmd(padapter); ++ } ++ ++ } ++ ++} ++ ++u8 rtw_chk_hi_queue_cmd(_adapter*padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++#endif ++ ++u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if (pdrvextra_cmd_parm == NULL) { ++ rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = C2H_WK_CID; ++ pdrvextra_cmd_parm->type_size = c2h_evt?16:0; ++ pdrvextra_cmd_parm->pbuf = c2h_evt; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++} ++ ++s32 c2h_evt_hdl(_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter) ++{ ++ s32 ret = _FAIL; ++ u8 buf[16]; ++ ++ if (!c2h_evt) { ++ /* No c2h event in cmd_obj, read c2h event before handling*/ ++ if (c2h_evt_read(adapter, buf) == _SUCCESS) { ++ c2h_evt = (struct c2h_evt_hdr *)buf; ++ ++ if (filter && filter(c2h_evt->id) == _FALSE) ++ goto exit; ++ ++ ret = rtw_hal_c2h_handler(adapter, c2h_evt); ++ } ++ } else { ++ ++ if (filter && filter(c2h_evt->id) == _FALSE) ++ goto exit; ++ ++ ret = rtw_hal_c2h_handler(adapter, c2h_evt); ++ } ++exit: ++ return ret; ++} ++ ++#ifdef CONFIG_C2H_WK ++static void c2h_wk_callback(_workitem *work) ++{ ++ struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk); ++ _adapter *adapter = container_of(evtpriv, _adapter, evtpriv); ++ struct c2h_evt_hdr *c2h_evt; ++ c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter); ++ ++ evtpriv->c2h_wk_alive = _TRUE; ++ ++ while (!rtw_cbuf_empty(evtpriv->c2h_queue)) { ++ if ((c2h_evt = (struct c2h_evt_hdr *)rtw_cbuf_pop(evtpriv->c2h_queue)) != NULL) { ++ /* This C2H event is read, clear it */ ++ c2h_evt_clear(adapter); ++ } else if ((c2h_evt = (struct c2h_evt_hdr *)rtw_malloc(16)) != NULL) { ++ /* This C2H event is not read, read & clear now */ ++ if (c2h_evt_read(adapter, (u8*)c2h_evt) != _SUCCESS) ++ continue; ++ } ++ ++ /* Special pointer to trigger c2h_evt_clear only */ ++ if ((void *)c2h_evt == (void *)evtpriv) ++ continue; ++ ++ if (!c2h_evt_exist(c2h_evt)) { ++ rtw_mfree((u8*)c2h_evt, 16); ++ continue; ++ } ++ ++ if (ccx_id_filter(c2h_evt->id) == _TRUE) { ++ /* Handle CCX report here */ ++ rtw_hal_c2h_handler(adapter, c2h_evt); ++ rtw_mfree((u8*)c2h_evt, 16); ++ } else { ++ /* Enqueue into cmd_thread for others */ ++ rtw_c2h_wk_cmd(adapter, (u8 *)c2h_evt); ++ } ++ } ++ ++ evtpriv->c2h_wk_alive = _FALSE; ++} ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++void event_polling_hdl(_adapter *padapter, u8 *pbuf, int sz) ++{ ++ c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(padapter); ++ u8 check_c2hcmd, check_ccx; ++ ++ //check_c2hcmd = rtw_read8(padapter, REG_C2HEVT_CLEAR); ++ //check_ccx= rtw_read8(padapter, REG_C2HEVT_MSG_NORMAL); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_C2HEVT_CLEAR, (u8 *)(&check_c2hcmd)); ++ rtw_hal_get_hwreg(padapter, HW_VAR_C2HEVT_MSG_NORMAL, (u8 *)(&check_ccx)); ++ ++ if (check_c2hcmd != 0) ++ { ++ struct c2h_evt_hdr *c2h_evt; ++ ++ if (check_c2hcmd != 0xFF) ++ { ++ c2h_evt_clear(padapter); ++ } ++ else if (ccx_id_filter(check_ccx & 0x0F) == _FALSE) ++ { ++ if ((c2h_evt = (struct c2h_evt_hdr *)rtw_zmalloc(16)) != NULL) { ++ if (c2h_evt_read(padapter, (u8 *)c2h_evt) == _SUCCESS) { ++ rtw_hal_c2h_handler(padapter, c2h_evt); ++ } ++ rtw_mfree((u8*)c2h_evt, 16); ++ } else { ++ /* Error handling for malloc fail */ ++ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) ++ DBG_871X("%s rtw_cbuf_push fail\n", __func__); ++ _set_workitem(&padapter->evtpriv.c2h_wk); ++ } ++ } ++ else ++ { ++ if (padapter->xmitpriv.ack_tx == _FALSE) ++ { ++ c2h_evt_clear(padapter); ++ } ++ } ++ } ++} ++#endif ++ ++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct drvextra_cmd_parm *pdrvextra_cmd; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ pdrvextra_cmd = (struct drvextra_cmd_parm*)pbuf; ++ ++ switch(pdrvextra_cmd->ec_id) ++ { ++ case DYNAMIC_CHK_WK_CID: ++ dynamic_chk_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ break; ++ case POWER_SAVING_CTRL_WK_CID: ++ power_saving_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ break; ++#ifdef CONFIG_LPS ++ case LPS_CTRL_WK_CID: ++ lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type_size); ++ break; ++#endif ++#if (RATE_ADAPTIVE_SUPPORT==1) ++ case RTP_TIMER_CFG_WK_CID: ++ rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type_size); ++ break; ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case ANT_SELECT_WK_CID: ++ antenna_select_wk_hdl(padapter, pdrvextra_cmd->type_size); ++ break; ++#endif ++#ifdef CONFIG_P2P_PS ++ case P2P_PS_WK_CID: ++ p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type_size); ++ break; ++#endif // CONFIG_P2P_PS ++#ifdef CONFIG_P2P ++ case P2P_PROTO_WK_CID: ++ // Commented by Albert 2011/07/01 ++ // I used the type_size as the type command ++ p2p_protocol_wk_hdl( padapter, pdrvextra_cmd->type_size ); ++ break; ++#endif ++#ifdef CONFIG_AP_MODE ++ case CHECK_HIQ_WK_CID: ++ rtw_chk_hi_queue_hdl(padapter); ++ break; ++#endif //CONFIG_AP_MODE ++#ifdef CONFIG_INTEL_WIDI ++ case INTEl_WIDI_WK_CID: ++ intel_widi_wk_hdl(padapter, pdrvextra_cmd->type_size, pdrvextra_cmd->pbuf); ++ break; ++#endif //CONFIG_INTEL_WIDI ++ //add for CONFIG_IEEE80211W, none 11w can use it ++ case RESET_SECURITYPRIV: ++ reset_securitypriv_hdl(padapter); ++ break; ++ case FREE_ASSOC_RESOURCES: ++ free_assoc_resources_hdl(padapter); ++ break; ++ case C2H_WK_CID: ++ c2h_evt_hdl(padapter, (struct c2h_evt_hdr *)pdrvextra_cmd->pbuf, NULL); ++ break; ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ case EVENT_POLLING_CID: ++ event_polling_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ break; ++#endif ++ default: ++ break; ++ } ++ ++ if (pdrvextra_cmd->pbuf && pdrvextra_cmd->type_size>0) ++ { ++ rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ } ++ ++ return H2C_SUCCESS; ++} ++ ++void rtw_survey_cmd_callback(_adapter* padapter , struct cmd_obj *pcmd) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if(pcmd->res == H2C_DROPPED) ++ { ++ //TODO: cancel timer and do timeout handler directly... ++ //need to make timeout handlerOS independent ++ _set_timer(&pmlmepriv->scan_to_timer, 1); ++ } ++ else if (pcmd->res != H2C_SUCCESS) { ++ _set_timer(&pmlmepriv->scan_to_timer, 1); ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n.")); ++ } ++ ++ // free cmd ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++void rtw_disassoc_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if (pcmd->res != H2C_SUCCESS) ++ { ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ***Error: disconnect_cmd_callback Fail ***\n.")); ++ ++ goto exit; ++ } ++#ifdef CONFIG_BR_EXT ++ else //clear bridge database ++ nat25_db_cleanup(padapter); ++#endif //CONFIG_BR_EXT ++ ++ // free cmd ++ rtw_free_cmd_obj(pcmd); ++ ++exit: ++ ++_func_exit_; ++} ++ ++ ++void rtw_joinbss_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if(pcmd->res == H2C_DROPPED) ++ { ++ //TODO: cancel timer and do timeout handler directly... ++ //need to make timeout handlerOS independent ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ } ++ else if(pcmd->res != H2C_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("********Error:rtw_select_and_join_from_scanned_queue Wait Sema Fail ************\n")); ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ } ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++ ++void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ u8 timer_cancelled; ++ struct sta_info *psta = NULL; ++ struct wlan_network *pwlan = NULL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)pcmd->parmbuf; ++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network); ++ ++_func_enter_; ++ ++ if((pcmd->res != H2C_SUCCESS)) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: rtw_createbss_cmd_callback Fail ************\n\n.")); ++ _set_timer(&pmlmepriv->assoc_timer, 1 ); ++ } ++ ++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); ++ ++#ifdef CONFIG_FW_MLMLE ++ //endian_convert ++ pnetwork->Length = le32_to_cpu(pnetwork->Length); ++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength); ++ pnetwork->Privacy =le32_to_cpu(pnetwork->Privacy); ++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi); ++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse); ++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow); ++ //pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod); ++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig); ++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime); ++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern); ++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet); ++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length); ++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length); ++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode); ++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength); ++#endif ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) ) ++ { ++ psta = rtw_get_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ if(!psta) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ if (psta == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n")); ++ goto createbss_cmd_fail ; ++ } ++ } ++ ++ rtw_indicate_connect( padapter); ++ } ++ else ++ { ++ _irqL irqL; ++ ++ pwlan = _rtw_alloc_network(pmlmepriv); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ if ( pwlan == NULL) ++ { ++ pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); ++ if( pwlan == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n Error: can't get pwlan in rtw_joinbss_event_callback \n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto createbss_cmd_fail; ++ } ++ pwlan->last_scanned = rtw_get_current_time(); ++ } ++ else ++ { ++ rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); ++ } ++ ++ pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); ++ _rtw_memcpy(&(pwlan->network), pnetwork, pnetwork->Length); ++ //pwlan->fixed = _TRUE; ++ ++ //rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); ++ ++ // copy pdev_network information to pmlmepriv->cur_network ++ _rtw_memcpy(&tgt_network->network, pnetwork, (get_WLAN_BSSID_EX_sz(pnetwork))); ++ ++ // reset DSConfig ++ //tgt_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pnetwork->Configuration.DSConfig); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++#if 0 ++ if((pmlmepriv->fw_state) & WIFI_AP_STATE) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ ++ if (psta == NULL) { // for AP Mode & Adhoc Master Mode ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n")); ++ goto createbss_cmd_fail ; ++ } ++ ++ rtw_indicate_connect( padapter); ++ } ++ else { ++ ++ //rtw_indicate_disconnect(dev); ++ } ++#endif ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) ++ ++ } ++ ++createbss_cmd_fail: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++ ++} ++ ++ ++ ++void rtw_setstaKey_cmdrsp_callback(_adapter* padapter , struct cmd_obj *pcmd) ++{ ++ ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct set_stakey_rsp* psetstakey_rsp = (struct set_stakey_rsp*) (pcmd->rsp); ++ struct sta_info* psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); ++ ++_func_enter_; ++ ++ if(psta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n")); ++ goto exit; ++ } ++ ++ //psta->aid = psta->mac_id = psetstakey_rsp->keyid; //CAM_ID(CAM_ENTRY) ++ ++exit: ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++ ++} ++void rtw_setassocsta_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct set_assocsta_parm* passocsta_parm = (struct set_assocsta_parm*)(pcmd->parmbuf); ++ struct set_assocsta_rsp* passocsta_rsp = (struct set_assocsta_rsp*) (pcmd->rsp); ++ struct sta_info* psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); ++ ++_func_enter_; ++ ++ if(psta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n")); ++ goto exit; ++ } ++ ++ psta->aid = psta->mac_id = passocsta_rsp->cam_id; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)) ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++ ++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); ++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++_func_enter_; ++ ++ rtw_free_cmd_obj(pcmd); ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ padapter->mppriv.workparam.bcompleted=_TRUE; ++#endif ++ ++_func_exit_; ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_debug.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_debug.c +new file mode 100644 +index 00000000..d2fc13c0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_debug.c +@@ -0,0 +1,1370 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_DEBUG_C_ ++ ++ ++#include ++ ++#ifdef CONFIG_DEBUG_RTL871X ++ ++ u32 GlobalDebugLevel = _drv_err_; ++ ++ u64 GlobalDebugComponents = \ ++ _module_rtl871x_xmit_c_ | ++ _module_xmit_osdep_c_ | ++ _module_rtl871x_recv_c_ | ++ _module_recv_osdep_c_ | ++ _module_rtl871x_mlme_c_ | ++ _module_mlme_osdep_c_ | ++ _module_rtl871x_sta_mgt_c_ | ++ _module_rtl871x_cmd_c_ | ++ _module_cmd_osdep_c_ | ++ _module_rtl871x_io_c_ | ++ _module_io_osdep_c_ | ++ _module_os_intfs_c_| ++ _module_rtl871x_security_c_| ++ _module_rtl871x_eeprom_c_| ++ _module_hal_init_c_| ++ _module_hci_hal_init_c_| ++ _module_rtl871x_ioctl_c_| ++ _module_rtl871x_ioctl_set_c_| ++ _module_rtl871x_ioctl_query_c_| ++ _module_rtl871x_pwrctrl_c_| ++ _module_hci_intfs_c_| ++ _module_hci_ops_c_| ++ _module_hci_ops_os_c_| ++ _module_rtl871x_ioctl_os_c| ++ _module_rtl8712_cmd_c_| ++ _module_hal_xmit_c_| ++ _module_rtl8712_recv_c_ | ++ _module_mp_ | ++ _module_efuse_; ++ ++#endif ++ ++#ifdef CONFIG_PROC_DEBUG ++#include ++ ++int proc_get_drv_version(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "%s\n", DRIVERVERSION); ++ ++ *eof = 1; ++ return len; ++} ++ ++#ifdef DBG_MEM_ALLOC ++int proc_get_mstat(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ int len = 0; ++ ++ len += _rtw_mstat_dump(page+len, count-len); ++ *eof = 1; ++ ++ return len; ++} ++#endif /* DBG_MEM_ALLOC */ ++ ++int proc_get_write_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ *eof = 1; ++ return 0; ++} ++ ++int proc_set_write_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 addr, val, len; ++ ++ if (count < 3) ++ { ++ DBG_871X("argument size is less than 3\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x %x %x", &addr, &val, &len); ++ ++ if (num != 3) { ++ DBG_871X("invalid write_reg parameter!\n"); ++ return count; ++ } ++ ++ switch(len) ++ { ++ case 1: ++ rtw_write8(padapter, addr, (u8)val); ++ break; ++ case 2: ++ rtw_write16(padapter, addr, (u16)val); ++ break; ++ case 4: ++ rtw_write32(padapter, addr, val); ++ break; ++ default: ++ DBG_871X("error write length=%d", len); ++ break; ++ } ++ ++ } ++ ++ return count; ++ ++} ++ ++static u32 proc_get_read_addr=0xeeeeeeee; ++static u32 proc_get_read_len=0x4; ++ ++int proc_get_read_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ int len = 0; ++ ++ if(proc_get_read_addr==0xeeeeeeee) ++ { ++ *eof = 1; ++ return len; ++ } ++ ++ switch(proc_get_read_len) ++ { ++ case 1: ++ len += snprintf(page + len, count - len, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr)); ++ break; ++ case 2: ++ len += snprintf(page + len, count - len, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr)); ++ break; ++ case 4: ++ len += snprintf(page + len, count - len, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr)); ++ break; ++ default: ++ len += snprintf(page + len, count - len, "error read length=%d\n", proc_get_read_len); ++ break; ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_set_read_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ char tmp[16]; ++ u32 addr, len; ++ ++ if (count < 2) ++ { ++ DBG_871X("argument size is less than 2\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x %x", &addr, &len); ++ ++ if (num != 2) { ++ DBG_871X("invalid read_reg parameter!\n"); ++ return count; ++ } ++ ++ proc_get_read_addr = addr; ++ ++ proc_get_read_len = len; ++ } ++ ++ return count; ++ ++} ++ ++int proc_get_fwstate(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "fwstate=0x%x\n", get_fwstate(pmlmepriv)); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_sec_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", ++ psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_mlmext_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_qos_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "qos_option=%d\n", pmlmepriv->qospriv.qos_option); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_ht_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++#ifdef CONFIG_80211N_HT ++ len += snprintf(page + len, count - len, "ht_option=%d\n", pmlmepriv->htpriv.ht_option); ++#endif //CONFIG_80211N_HT ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_rf_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n", ++ pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_ap_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct sta_info *psta; ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ int len = 0; ++ ++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(psta) ++ { ++ int i; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++ len += snprintf(page + len, count - len, "SSID=%s\n", cur_network->network.Ssid.Ssid); ++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ len += snprintf(page + len, count - len, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++#ifdef CONFIG_80211N_HT ++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++#endif //CONFIG_80211N_HT ++ ++ for(i=0;i<16;i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ if(preorder_ctrl->enable) ++ { ++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ else ++ { ++ len += snprintf(page + len, count - len, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_adapter_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "bSurpriseRemoved=%d, bDriverStopped=%d\n", ++ padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_trx_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ int i; ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct hw_xmit *phwxmit; ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" ++ ", free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d" ++ ", free_recvframe_cnt=%d\n", ++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, ++ pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, ++ precvpriv->free_recvframe_cnt); ++ ++ for(i = 0; i < 4; i++) ++ { ++ phwxmit = pxmitpriv->hwxmits + i; ++ len += snprintf(page + len, count - len, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); ++ } ++ ++#ifdef CONFIG_USB_HCI ++ len += snprintf(page + len, count - len, "rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt); ++#endif ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_mac_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n"); ++ ++ for(i=0x0;i<0x300;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_mac_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n"); ++ memset(page, 0, count); ++ for(i=0x300;i<0x600;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_mac_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= MAC REG =======\n"); ++ ++ for(i=0x600;i<0x800;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_bb_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n"); ++ for(i=0x800;i<0xB00;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_bb_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n"); ++ for(i=0xB00;i<0xE00;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_bb_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1; ++ ++ len += snprintf(page + len, count - len, "\n======= BB REG =======\n"); ++ for(i=0xE00;i<0x1000;i+=4) ++ { ++ if(j%4==1) len += snprintf(page + len, count - len,"0x%02x",i); ++ len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) len += snprintf(page + len, count - len,"\n"); ++ } ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_rf_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1,path; ++ u32 value; ++ ++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n"); ++ path = 1; ++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path); ++ for(i=0;i<0xC0;i++) ++ { ++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord); ++ value = rtw_hal_read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i); ++ len += snprintf(page + len, count - len, " 0x%08x ",value); ++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n"); ++ } ++ ++ *eof = 1; ++ return len; ++} ++ ++ ++int proc_get_rf_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1,path; ++ u32 value; ++ ++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n"); ++ path = 1; ++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path); ++ for(i=0xC0;i<0x100;i++) ++ { ++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord); ++ value = rtw_hal_read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i); ++ len += snprintf(page + len, count - len, " 0x%08x ",value); ++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n"); ++ } ++ *eof = 1; ++ return len; ++} ++ ++ ++int proc_get_rf_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1,path; ++ u32 value; ++ ++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n"); ++ path = 2; ++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path); ++ for(i=0;i<0xC0;i++) ++ { ++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord); ++ value = rtw_hal_read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i); ++ len += snprintf(page + len, count - len, " 0x%08x ",value); ++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n"); ++ } ++ ++ *eof = 1; ++ return len; ++} ++ ++ ++int proc_get_rf_reg_dump4(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ int i,j=1,path; ++ u32 value; ++ ++ len += snprintf(page + len, count - len, "\n======= RF REG =======\n"); ++ path = 2; ++ len += snprintf(page + len, count - len, "\nRF_Path(%x)\n",path); ++ for(i=0xC0;i<0x100;i++) ++ { ++ //value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord); ++ value = rtw_hal_read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) len += snprintf(page + len, count - len, "0x%02x ",i); ++ len += snprintf(page + len, count - len, " 0x%08x ",value); ++ if((j++)%4==0) len += snprintf(page + len, count - len, "\n"); ++ } ++ *eof = 1; ++ return len; ++} ++ ++ ++ ++int proc_get_rx_signal(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, ++ "rssi:%d\n" ++ "rxpwdb:%d\n" ++ "signal_strength:%u\n" ++ "signal_qual:%u\n" ++ "noise:%u\n", ++ padapter->recvpriv.rssi, ++ padapter->recvpriv.rxpwdb, ++ padapter->recvpriv.signal_strength, ++ padapter->recvpriv.signal_qual, ++ padapter->recvpriv.noise ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_rx_signal(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 is_signal_dbg, signal_strength; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); ++ ++ is_signal_dbg = is_signal_dbg==0?0:1; ++ ++ if(is_signal_dbg && num!=2) ++ return count; ++ ++ signal_strength = signal_strength>100?100:signal_strength; ++ signal_strength = signal_strength<0?0:signal_strength; ++ ++ padapter->recvpriv.is_signal_dbg = is_signal_dbg; ++ padapter->recvpriv.signal_strength_dbg=signal_strength; ++ ++ if(is_signal_dbg) ++ DBG_871X("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength); ++ else ++ DBG_871X("set %s\n", "HW_SIGNAL_STRENGTH"); ++ ++ } ++ ++ return count; ++ ++} ++#ifdef CONFIG_80211N_HT ++ ++int proc_get_ht_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ int len = 0; ++ ++ if(pregpriv) ++ len += snprintf(page + len, count - len, ++ "%d\n", ++ pregpriv->ht_enable ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_ht_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ char tmp[32]; ++ u32 mode; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d ", &mode); ++ ++ if( pregpriv && mode >= 0 && mode < 2 ) ++ { ++ pregpriv->ht_enable= mode; ++ printk("ht_enable=%d\n", pregpriv->ht_enable); ++ } ++ } ++ ++ return count; ++ ++} ++ ++int proc_get_cbw40_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ int len = 0; ++ ++ if(pregpriv) ++ len += snprintf(page + len, count - len, ++ "%d\n", ++ pregpriv->cbw40_enable ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_cbw40_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ char tmp[32]; ++ u32 mode; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d ", &mode); ++ ++ if( pregpriv && mode >= 0 && mode < 2 ) ++ { ++ ++ pregpriv->cbw40_enable= mode; ++ printk("cbw40_enable=%d\n", mode); ++ ++ } ++ } ++ ++ return count; ++ ++} ++ ++int proc_get_ampdu_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ int len = 0; ++ ++ if(pregpriv) ++ len += snprintf(page + len, count - len, ++ "%d\n", ++ pregpriv->ampdu_enable ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_ampdu_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ char tmp[32]; ++ u32 mode; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d ", &mode); ++ ++ if( pregpriv && mode >= 0 && mode < 3 ) ++ { ++ pregpriv->ampdu_enable= mode; ++ printk("ampdu_enable=%d\n", mode); ++ } ++ ++ } ++ ++ return count; ++ ++} ++#endif //CONFIG_80211N_HT ++ ++int proc_get_two_path_rssi(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ int len = 0; ++ ++ if(padapter) ++ len += snprintf(page + len, count - len, ++ "%d %d\n", ++ padapter->recvpriv.RxRssi[0], ++ padapter->recvpriv.RxRssi[1] ++ ); ++ ++ *eof = 1; ++ return len; ++} ++#ifdef CONFIG_80211N_HT ++int proc_get_rx_stbc(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ int len = 0; ++ ++ if(pregpriv) ++ len += snprintf(page + len, count - len, ++ "%d\n", ++ pregpriv->rx_stbc ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_rx_stbc(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ char tmp[32]; ++ u32 mode; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d ", &mode); ++ ++ if( pregpriv && (mode == 0 || mode == 1|| mode == 2|| mode == 3)) ++ { ++ pregpriv->rx_stbc= mode; ++ printk("rx_stbc=%d\n", mode); ++ } ++ } ++ ++ return count; ++ ++} ++#endif //CONFIG_80211N_HT ++ ++ ++int proc_get_rssi_disp(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ *eof = 1; ++ return 0; ++} ++ ++int proc_set_rssi_disp(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 enable=0; ++ ++ if (count < 1) ++ { ++ DBG_8192C("argument size is less than 1\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x", &enable); ++ ++ if (num != 1) { ++ DBG_8192C("invalid set_rssi_disp parameter!\n"); ++ return count; ++ } ++ ++ if(enable) ++ { ++ DBG_8192C("Turn On Rx RSSI Display Function\n"); ++ padapter->bRxRSSIDisplay = enable ; ++ } ++ else ++ { ++ DBG_8192C("Turn Off Rx RSSI Display Function\n"); ++ padapter->bRxRSSIDisplay = 0 ; ++ } ++ ++ } ++ ++ return count; ++ ++} ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++int proc_get_all_sta_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ _irqL irqL; ++ struct sta_info *psta; ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ int i, j; ++ _list *plist, *phead; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ int len = 0; ++ ++ ++ len += snprintf(page + len, count - len, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ //if(extra_arg == psta->aid) ++ { ++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++#ifdef CONFIG_80211N_HT ++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++#endif //CONFIG_80211N_HT ++ len += snprintf(page + len, count - len, "sleepq_len=%d\n", psta->sleepq_len); ++ len += snprintf(page + len, count - len, "capability=0x%x\n", psta->capability); ++ len += snprintf(page + len, count - len, "flags=0x%x\n", psta->flags); ++ len += snprintf(page + len, count - len, "wpa_psk=0x%x\n", psta->wpa_psk); ++ len += snprintf(page + len, count - len, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); ++ len += snprintf(page + len, count - len, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); ++ len += snprintf(page + len, count - len, "qos_info=0x%x\n", psta->qos_info); ++ len += snprintf(page + len, count - len, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); ++ ++ for(j=0;j<16;j++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[j]; ++ if(preorder_ctrl->enable) ++ { ++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#include ++extern atomic_t _malloc_cnt;; ++extern atomic_t _malloc_size;; ++ ++int proc_get_malloc_cnt(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt)); ++ len += snprintf(page + len, count - len, "_malloc_size=%d\n", atomic_read(&_malloc_size)); ++ ++ *eof = 1; ++ return len; ++} ++#endif /* DBG_MEMORY_LEAK */ ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++int proc_get_best_channel(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ int len = 0; ++ u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; ++ ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ if ( pmlmeext->channel_set[i].ChannelNum == 1) ++ index_24G = i; ++ if ( pmlmeext->channel_set[i].ChannelNum == 36) ++ index_5G = i; ++ } ++ ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ // 2.4G ++ if ( pmlmeext->channel_set[i].ChannelNum == 6 ) { ++ if ( pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count ) { ++ index_24G = i; ++ best_channel_24G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++ ++ // 5G ++ if ( pmlmeext->channel_set[i].ChannelNum >= 36 ++ && pmlmeext->channel_set[i].ChannelNum < 140 ) { ++ // Find primary channel ++ if ( (( pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) ++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { ++ index_5G = i; ++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++ ++ if ( pmlmeext->channel_set[i].ChannelNum >= 149 ++ && pmlmeext->channel_set[i].ChannelNum < 165) { ++ // find primary channel ++ if ( (( pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) ++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { ++ index_5G = i; ++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++#if 1 // debug ++ len += snprintf(page + len, count - len, "The rx cnt of channel %3d = %d\n", ++ pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count); ++#endif ++ } ++ ++ len += snprintf(page + len, count - len, "best_channel_5G = %d\n", best_channel_5G); ++ len += snprintf(page + len, count - len, "best_channel_24G = %d\n", best_channel_24G); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_set_best_channel(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ char tmp[32]; ++ ++ if(count < 1) ++ return -EFAULT; ++ ++ if(buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) ++ { ++ int i; ++ for(i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) ++ { ++ pmlmeext->channel_set[i].rx_count = 0; ++ } ++ ++ DBG_871X("set %s\n", "Clean Best Channel Count"); ++ } ++ ++ return count; ++} ++#endif /* CONFIG_FIND_BEST_CHANNEL */ ++#ifdef CONFIG_BT_COEXIST ++#define _bt_dbg_off_ 0 ++#define _bt_dbg_on_ 1 ++ ++extern u32 BTCoexDbgLevel; ++int proc_get_btcoex_dbg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ int len = 0; ++ ++ if(pregpriv) ++ len += snprintf(page + len, count - len, ++ "%d\n", ++ BTCoexDbgLevel ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_btcoex_dbg(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ char tmp[32]; ++ u32 mode; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d ", &mode); ++ ++ if( pregpriv && (mode == 0 || mode == 1|| mode == 2|| mode == 3)) ++ { ++ BTCoexDbgLevel= mode; ++ printk("btcoex_dbg=%d\n", BTCoexDbgLevel); ++ } ++ } ++ ++ return count; ++ ++} ++#endif /* CONFIG_BT_COEXIST */ ++ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++#include ++int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_sreset(struct file *file, const char *buffer, unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ s32 trigger_point; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%d", &trigger_point); ++ ++ if (trigger_point == SRESET_TGP_NULL) ++ rtw_hal_sreset_reset(padapter); ++ else ++ sreset_set_trigger_point(padapter, trigger_point); ++ } ++ ++ return count; ++ ++} ++#endif /* DBG_CONFIG_ERROR_DETECT */ ++ ++int proc_get_odm_dbg_comp(char *page, char **start, off_t offset, int count, int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ ++ len += _rtw_odm_dbg_comp_msg(adapter, page, count); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_odm_dbg_comp(struct file *file, const char *buffer, unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ ++ u64 dbg_comp; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%llx", &dbg_comp); ++ ++ if (num != 1) ++ return count; ++ ++ rtw_odm_dbg_comp_set(adapter, dbg_comp); ++ } ++ ++ return count; ++} ++ ++int proc_get_odm_dbg_level(char *page, char **start, off_t offset, int count, int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ ++ len += _rtw_odm_dbg_level_msg(adapter, page, count); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_odm_dbg_level(struct file *file, const char *buffer, unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ ++ u32 dbg_level; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%u", &dbg_level); ++ ++ if (num != 1) ++ return count; ++ ++ rtw_odm_dbg_level_set(adapter, dbg_level); ++ } ++ ++ return count; ++} ++ ++int proc_get_odm_adaptivity(char *page, char **start, off_t offset, int count, int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ ++ len += _rtw_odm_adaptivity_parm_msg(padapter, page, count); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_odm_adaptivity(struct file *file, const char *buffer, unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 TH_L2H_ini; ++ s8 TH_EDCCA_HL_diff; ++ u32 IGI_Base; ++ int ForceEDCCA; ++ u8 AdapEn_RSSI; ++ u8 IGI_LowerBound; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x %hhd %x %d %hhu %hhu", ++ &TH_L2H_ini, &TH_EDCCA_HL_diff, &IGI_Base, &ForceEDCCA, &AdapEn_RSSI, &IGI_LowerBound); ++ ++ if (num != 6) ++ return count; ++ ++ rtw_odm_adaptivity_parm_set(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff, (s8)IGI_Base, (bool)ForceEDCCA, AdapEn_RSSI, IGI_LowerBound); ++ } ++ ++ return count; ++} ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_eeprom.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_eeprom.c +new file mode 100644 +index 00000000..fd07d64d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_eeprom.c +@@ -0,0 +1,423 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_EEPROM_C_ ++ ++#include ++#include ++#include ++ ++void up_clk(_adapter* padapter, u16 *x) ++{ ++_func_enter_; ++ *x = *x | _EESK; ++ rtw_write8(padapter, EE_9346CR, (u8)*x); ++ rtw_udelay_os(CLOCK_RATE); ++ ++_func_exit_; ++ ++} ++ ++void down_clk(_adapter * padapter, u16 *x ) ++{ ++_func_enter_; ++ *x = *x & ~_EESK; ++ rtw_write8(padapter, EE_9346CR, (u8)*x); ++ rtw_udelay_os(CLOCK_RATE); ++_func_exit_; ++} ++ ++void shift_out_bits(_adapter * padapter, u16 data, u16 count) ++{ ++ u16 x,mask; ++_func_enter_; ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ mask = 0x01 << (count - 1); ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDO | _EEDI); ++ ++ do ++ { ++ x &= ~_EEDI; ++ if(data & mask) ++ x |= _EEDI; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++ rtw_udelay_os(CLOCK_RATE); ++ up_clk(padapter, &x); ++ down_clk(padapter, &x); ++ mask = mask >> 1; ++ } while(mask); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x &= ~_EEDI; ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++out: ++_func_exit_; ++} ++ ++u16 shift_in_bits (_adapter * padapter) ++{ ++ u16 x,d=0,i; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~( _EEDO | _EEDI); ++ d = 0; ++ ++ for(i=0; i<16; i++) ++ { ++ d = d << 1; ++ up_clk(padapter, &x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDI); ++ if(x & _EEDO) ++ d |= 1; ++ ++ down_clk(padapter, &x); ++ } ++out: ++_func_exit_; ++ ++ return d; ++} ++ ++void standby(_adapter * padapter ) ++{ ++ u8 x; ++_func_enter_; ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EECS | _EESK); ++ rtw_write8(padapter, EE_9346CR,x); ++ ++ rtw_udelay_os(CLOCK_RATE); ++ x |= _EECS; ++ rtw_write8(padapter, EE_9346CR, x); ++ rtw_udelay_os(CLOCK_RATE); ++_func_exit_; ++} ++ ++u16 wait_eeprom_cmd_done(_adapter* padapter) ++{ ++ u8 x; ++ u16 i,res=_FALSE; ++_func_enter_; ++ standby(padapter ); ++ for (i=0; i<200; i++) ++ { ++ x = rtw_read8(padapter, EE_9346CR); ++ if (x & _EEDO){ ++ res=_TRUE; ++ goto exit; ++ } ++ rtw_udelay_os(CLOCK_RATE); ++ } ++exit: ++_func_exit_; ++ return res; ++} ++ ++void eeprom_clean(_adapter * padapter) ++{ ++ u16 x; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x &= ~(_EECS | _EEDI); ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ up_clk(padapter, &x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ down_clk(padapter, &x); ++out: ++_func_exit_; ++} ++ ++void eeprom_write16(_adapter * padapter, u16 reg, u16 data) ++{ ++ u8 x; ++#ifdef CONFIG_RTL8712 ++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; ++ tmp8_ori=rtw_read8(padapter, 0x102502f1); ++ tmp8_new=tmp8_ori & 0xf7; ++ if(tmp8_ori != tmp8_new){ ++ rtw_write8(padapter, 0x102502f1, tmp8_new); ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); ++ } ++ tmp8_clk_ori=rtw_read8(padapter,0x10250003); ++ tmp8_clk_new=tmp8_clk_ori|0x20; ++ if(tmp8_clk_new!=tmp8_clk_ori){ ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); ++ rtw_write8(padapter, 0x10250003, tmp8_clk_new); ++ } ++#endif ++_func_enter_; ++ ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, x); ++ ++ shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5); ++ ++ if(padapter->EepromAddressSize==8) //CF+ and SDIO ++ shift_out_bits(padapter, 0, 6); ++ else //USB ++ shift_out_bits(padapter, 0, 4); ++ ++ standby( padapter); ++ ++// Commented out by rcnjko, 2004.0 ++// // Erase this particular word. Write the erase opcode and register ++// // number in that order. The opcode is 3bits in length; reg is 6 bits long. ++// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3); ++// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize); ++// ++// if (wait_eeprom_cmd_done(Adapter ) == FALSE) ++// { ++// return; ++// } ++ ++ ++ standby(padapter ); ++ ++ // write the new word to the EEPROM ++ ++ // send the write opcode the EEPORM ++ shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3); ++ ++ // select which word in the EEPROM that we are writing to. ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ // write the data to the selected EEPROM word. ++ shift_out_bits(padapter, data, 16); ++ ++ if (wait_eeprom_cmd_done(padapter ) == _FALSE) ++ { ++ ++ goto exit; ++ } ++ ++ standby(padapter ); ++ ++ shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5); ++ shift_out_bits(padapter, reg, 4); ++ ++ eeprom_clean(padapter ); ++exit: ++#ifdef CONFIG_RTL8712 ++ if(tmp8_clk_new!=tmp8_clk_ori) ++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori); ++ if(tmp8_new!=tmp8_ori) ++ rtw_write8(padapter, 0x102502f1, tmp8_ori); ++ ++#endif ++_func_exit_; ++ return; ++} ++ ++u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom ++{ ++ ++ u16 x; ++ u16 data=0; ++#ifdef CONFIG_RTL8712 ++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; ++ tmp8_ori= rtw_read8(padapter, 0x102502f1); ++ tmp8_new = tmp8_ori & 0xf7; ++ if(tmp8_ori != tmp8_new){ ++ rtw_write8(padapter, 0x102502f1, tmp8_new); ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); ++ } ++ tmp8_clk_ori=rtw_read8(padapter,0x10250003); ++ tmp8_clk_new=tmp8_clk_ori|0x20; ++ if(tmp8_clk_new!=tmp8_clk_ori){ ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); ++ rtw_write8(padapter, 0x10250003, tmp8_clk_new); ++ } ++#endif ++_func_enter_; ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ // select EEPROM, reset bits, set _EECS ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, (unsigned char)x); ++ ++ // write the read opcode and register number in that order ++ // The opcode is 3bits in length, reg is 6 bits long ++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ // Now read the data (16 bits) in from the selected EEPROM word ++ data = shift_in_bits(padapter); ++ ++ eeprom_clean(padapter); ++out: ++#ifdef CONFIG_RTL8712 ++ if(tmp8_clk_new!=tmp8_clk_ori) ++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori); ++ if(tmp8_new!=tmp8_ori) ++ rtw_write8(padapter, 0x102502f1, tmp8_ori); ++ ++#endif ++_func_exit_; ++ return data; ++ ++ ++} ++ ++ ++ ++ ++//From even offset ++void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz) ++{ ++ ++ u16 x, data16; ++ u32 i; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ // select EEPROM, reset bits, set _EECS ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, (unsigned char)x); ++ ++ // write the read opcode and register number in that order ++ // The opcode is 3bits in length, reg is 6 bits long ++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ ++ for(i=0; i>8; ++ } ++ ++ eeprom_clean(padapter); ++out: ++_func_exit_; ++ ++ ++ ++} ++ ++ ++//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) ++u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf) ++{ ++ u8 quotient, remainder, addr_2align_odd; ++ u16 reg, stmp , i=0, idx = 0; ++_func_enter_; ++ reg = (u16)(addr_off >> 1); ++ addr_2align_odd = (u8)(addr_off & 0x1); ++ ++ if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,... ++ { ++ stmp = eeprom_read16(padapter, reg); ++ rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short ++ reg++; sz--; ++ } ++ ++ quotient = sz >> 1; ++ remainder = sz & 0x1; ++ ++ for( i=0 ; i < quotient; i++) ++ { ++ stmp = eeprom_read16(padapter, reg+i); ++ rbuf[idx++] = (u8) (stmp&0xff); ++ rbuf[idx++] = (u8) ((stmp>>8)&0xff); ++ } ++ ++ reg = reg+i; ++ if(remainder){ //end of read at lower part of short : 0,2,4,6,... ++ stmp = eeprom_read16(padapter, reg); ++ rbuf[idx] = (u8)(stmp & 0xff); ++ } ++_func_exit_; ++ return _TRUE; ++} ++ ++ ++ ++VOID read_eeprom_content(_adapter * padapter) ++{ ++ ++_func_enter_; ++ ++ ++_func_exit_; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ieee80211.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ieee80211.c +new file mode 100644 +index 00000000..af32123c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ieee80211.c +@@ -0,0 +1,2187 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IEEE80211_C ++ ++#include ++#include ++#include ++#include ++#include ++ ++u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; ++u16 RTW_WPA_VERSION = 1; ++u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 }; ++u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 }; ++u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 }; ++u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; ++u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; ++u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; ++u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 }; ++u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; ++u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; ++ ++u16 RSN_VERSION_BSD = 1; ++u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 }; ++u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 }; ++u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; ++u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; ++u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; ++u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; ++u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; ++u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; ++//----------------------------------------------------------- ++// for adhoc-master to generate ie and provide supported-rate to fw ++//----------------------------------------------------------- ++ ++static u8 WIFI_CCKRATES[] = ++{(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)}; ++ ++static u8 WIFI_OFDMRATES[] = ++{(IEEE80211_OFDM_RATE_6MB), ++ (IEEE80211_OFDM_RATE_9MB), ++ (IEEE80211_OFDM_RATE_12MB), ++ (IEEE80211_OFDM_RATE_18MB), ++ (IEEE80211_OFDM_RATE_24MB), ++ IEEE80211_OFDM_RATE_36MB, ++ IEEE80211_OFDM_RATE_48MB, ++ IEEE80211_OFDM_RATE_54MB}; ++ ++ ++int rtw_get_bit_value_from_ieee_value(u8 val) ++{ ++ unsigned char dot11_rate_table[]={2,4,11,22,12,18,24,36,48,72,96,108,0}; // last element must be zero!! ++ ++ int i=0; ++ while(dot11_rate_table[i] != 0) { ++ if (dot11_rate_table[i] == val) ++ return BIT(i); ++ i++; ++ } ++ return 0; ++} ++ ++uint rtw_is_cckrates_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ i++; ++ } ++ ++ return _FALSE; ++} ++ ++uint rtw_is_cckratesonly_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ ++ return _FALSE; ++ ++ i++; ++ } ++ ++ return _TRUE; ++ ++} ++ ++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel) ++{ ++ if (channel > 14) ++ { ++ if ((rtw_is_cckrates_included(rate)) == _TRUE) ++ return WIRELESS_INVALID; ++ else ++ return WIRELESS_11A; ++ } ++ else // could be pure B, pure G, or B/G ++ { ++ if ((rtw_is_cckratesonly_included(rate)) == _TRUE) ++ return WIRELESS_11B; ++ else if((rtw_is_cckrates_included(rate)) == _TRUE) ++ return WIRELESS_11BG; ++ else ++ return WIRELESS_11G; ++ } ++ ++} ++ ++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, ++ unsigned int *frlen) ++{ ++ _rtw_memcpy((void *)pbuf, (void *)source, len); ++ *frlen = *frlen + len; ++ return (pbuf + len); ++} ++ ++// rtw_set_ie will update frame length ++u8 *rtw_set_ie ++( ++ u8 *pbuf, ++ sint index, ++ uint len, ++ u8 *source, ++ uint *frlen //frame length ++) ++{ ++_func_enter_; ++ *pbuf = (u8)index; ++ ++ *(pbuf + 1) = (u8)len; ++ ++ if (len > 0) ++ _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); ++ ++ *frlen = *frlen + (len + 2); ++ ++ return (pbuf + len + 2); ++_func_exit_; ++} ++ ++inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, ++ u8 new_ch, u8 ch_switch_cnt) ++{ ++ u8 ie_data[3]; ++ ++ ie_data[0] = ch_switch_mode; ++ ie_data[1] = new_ch; ++ ie_data[2] = ch_switch_cnt; ++ return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH, 3, ie_data, buf_len); ++} ++ ++inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) ++{ ++ if (ch_offset == SCN) ++ return HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ else if(ch_offset == SCA) ++ return HAL_PRIME_CHNL_OFFSET_UPPER; ++ else if(ch_offset == SCB) ++ return HAL_PRIME_CHNL_OFFSET_LOWER; ++ ++ return HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++} ++ ++inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) ++{ ++ if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ++ return SCN; ++ else if(ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ return SCB; ++ else if(ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) ++ return SCA; ++ ++ return SCN; ++} ++ ++inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset) ++{ ++ return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET, 1, &secondary_ch_offset, buf_len); ++} ++ ++inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, ++ u8 flags, u16 reason, u16 precedence) ++{ ++ u8 ie_data[6]; ++ ++ ie_data[0] = ttl; ++ ie_data[1] = flags; ++ RTW_PUT_LE16((u8*)&ie_data[2], reason); ++ RTW_PUT_LE16((u8*)&ie_data[4], precedence); ++ ++ return rtw_set_ie(buf, 0x118, 6, ie_data, buf_len); ++} ++ ++/*---------------------------------------------------------------------------- ++index: the information element id index, limit is the limit for search ++-----------------------------------------------------------------------------*/ ++u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) ++{ ++ sint tmp,i; ++ u8 *p; ++_func_enter_; ++ if (limit < 1){ ++ _func_exit_; ++ return NULL; ++ } ++ ++ p = pbuf; ++ i = 0; ++ *len = 0; ++ while(1) ++ { ++ if (*p == index) ++ { ++ *len = *(p + 1); ++ return (p); ++ } ++ else ++ { ++ tmp = *(p + 1); ++ p += (tmp + 2); ++ i += (tmp + 2); ++ } ++ if (i >= limit) ++ break; ++ } ++_func_exit_; ++ return NULL; ++} ++ ++/** ++ * rtw_get_ie_ex - Search specific IE from a series of IEs ++ * @in_ie: Address of IEs to search ++ * @in_len: Length limit from in_ie ++ * @eid: Element ID to match ++ * @oui: OUI to match ++ * @oui_len: OUI length ++ * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE ++ * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE ++ * ++ * Returns: The address of the specific IE found, or NULL ++ */ ++u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen) ++{ ++ uint cnt; ++ u8 *target_ie = NULL; ++ ++ ++ if(ielen) ++ *ielen = 0; ++ ++ if(!in_ie || in_len<=0) ++ return target_ie; ++ ++ cnt = 0; ++ ++ while(cnt 12) ++ break; ++ ++ i++; ++ } ++_func_exit_; ++ return i; ++} ++ ++int rtw_generate_ie(struct registry_priv *pregistrypriv) ++{ ++ u8 wireless_mode; ++ int sz = 0, rateLen; ++ WLAN_BSSID_EX* pdev_network = &pregistrypriv->dev_network; ++ u8* ie = pdev_network->IEs; ++ ++_func_enter_; ++ ++ //timestamp will be inserted by hardware ++ sz += 8; ++ ie += sz; ++ ++ //beacon interval : 2bytes ++ *(u16*)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod);//BCN_INTERVAL; ++ sz += 2; ++ ie += 2; ++ ++ //capability info ++ *(u16*)ie = 0; ++ ++ *(u16*)ie |= cpu_to_le16(cap_IBSS); ++ ++ if(pregistrypriv->preamble == PREAMBLE_SHORT) ++ *(u16*)ie |= cpu_to_le16(cap_ShortPremble); ++ ++ if (pdev_network->Privacy) ++ *(u16*)ie |= cpu_to_le16(cap_Privacy); ++ ++ sz += 2; ++ ie += 2; ++ ++ //SSID ++ ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz); ++ ++ //supported rates ++ if(pregistrypriv->wireless_mode == WIRELESS_11ABGN) ++ { ++ if(pdev_network->Configuration.DSConfig > 14) ++ wireless_mode = WIRELESS_11A_5N; ++ else ++ wireless_mode = WIRELESS_11BG_24N; ++ } ++ else ++ { ++ wireless_mode = pregistrypriv->wireless_mode; ++ } ++ ++ rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ; ++ ++ rateLen = rtw_get_rateset_len(pdev_network->SupportedRates); ++ ++ if (rateLen > 8) ++ { ++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz); ++ //ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); ++ } ++ else ++ { ++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz); ++ } ++ ++ //DS parameter set ++ ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz); ++ ++ ++ //IBSS Parameter Set ++ ++ ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz); ++ ++ if (rateLen > 8) ++ { ++ ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ //HT Cap. ++ if(((pregistrypriv->wireless_mode&WIRELESS_11_5N)||(pregistrypriv->wireless_mode&WIRELESS_11_24N)) ++ && (pregistrypriv->ht_enable==_TRUE)) ++ { ++ //todo: ++ } ++#endif //CONFIG_80211N_HT ++ ++ //pdev_network->IELength = sz; //update IELength ++ ++_func_exit_; ++ ++ //return _SUCCESS; ++ ++ return sz; ++ ++} ++ ++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit) ++{ ++ int len; ++ u16 val16; ++ unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01}; ++ u8 *pbuf = pie; ++ int limit_new = limit; ++ ++ while(1) ++ { ++ pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new); ++ ++ if (pbuf) { ++ ++ //check if oui matches... ++ if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof (wpa_oui_type)) == _FALSE) { ++ ++ goto check_next_ie; ++ } ++ ++ //check version... ++ _rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16)); ++ ++ val16 = le16_to_cpu(val16); ++ if (val16 != 0x0001) ++ goto check_next_ie; ++ ++ *wpa_ie_len = *(pbuf + 1); ++ ++ return pbuf; ++ ++ } ++ else { ++ ++ *wpa_ie_len = 0; ++ return NULL; ++ } ++ ++check_next_ie: ++ ++ limit_new = limit - (pbuf - pie) - 2 - len; ++ ++ if (limit_new <= 0) ++ break; ++ ++ pbuf += (2 + len); ++ ++ } ++ ++ *wpa_ie_len = 0; ++ ++ return NULL; ++ ++} ++ ++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit) ++{ ++ ++ return rtw_get_ie(pie, _WPA2_IE_ID_,rsn_ie_len, limit); ++ ++} ++ ++int rtw_get_wpa_cipher_suite(u8 *s) ++{ ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_NONE; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP40; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_TKIP; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_CCMP; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP104; ++ ++ return 0; ++} ++ ++int rtw_get_wpa2_cipher_suite(u8 *s) ++{ ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_NONE; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP40; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_TKIP; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_CCMP; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP104; ++ ++ return 0; ++} ++ ++ ++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) ++{ ++ int i, ret=_SUCCESS; ++ int left, count; ++ u8 *pos; ++ u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1}; ++ ++ if (wpa_ie_len <= 0) { ++ /* No WPA IE - fail silently */ ++ return _FAIL; ++ } ++ ++ ++ if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie+1) != (u8)(wpa_ie_len - 2)) || ++ (_rtw_memcmp(wpa_ie+2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE) ) ++ { ++ return _FAIL; ++ } ++ ++ pos = wpa_ie; ++ ++ pos += 8; ++ left = wpa_ie_len - 8; ++ ++ ++ //group_cipher ++ if (left >= WPA_SELECTOR_LEN) { ++ ++ *group_cipher = rtw_get_wpa_cipher_suite(pos); ++ ++ pos += WPA_SELECTOR_LEN; ++ left -= WPA_SELECTOR_LEN; ++ ++ } ++ else if (left > 0) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); ++ ++ return _FAIL; ++ } ++ ++ ++ //pairwise_cipher ++ if (left >= 2) ++ { ++ //count = le16_to_cpu(*(u16*)pos); ++ count = RTW_GET_LE16(pos); ++ pos += 2; ++ left -= 2; ++ ++ if (count == 0 || left < count * WPA_SELECTOR_LEN) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " ++ "count %u left %u", __FUNCTION__, count, left)); ++ return _FAIL; ++ } ++ ++ for (i = 0; i < count; i++) ++ { ++ *pairwise_cipher |= rtw_get_wpa_cipher_suite(pos); ++ ++ pos += WPA_SELECTOR_LEN; ++ left -= WPA_SELECTOR_LEN; ++ } ++ ++ } ++ else if (left == 1) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); ++ return _FAIL; ++ } ++ ++ if (is_8021x) { ++ if (left >= 6) { ++ pos += 2; ++ if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s : there has 802.1x auth\n", __FUNCTION__)); ++ *is_8021x = 1; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) ++{ ++ int i, ret=_SUCCESS; ++ int left, count; ++ u8 *pos; ++ u8 SUITE_1X[4] = {0x00,0x0f, 0xac, 0x01}; ++ ++ if (rsn_ie_len <= 0) { ++ /* No RSN IE - fail silently */ ++ return _FAIL; ++ } ++ ++ ++ if ((*rsn_ie!= _WPA2_IE_ID_) || (*(rsn_ie+1) != (u8)(rsn_ie_len - 2))) ++ { ++ return _FAIL; ++ } ++ ++ pos = rsn_ie; ++ pos += 4; ++ left = rsn_ie_len - 4; ++ ++ //group_cipher ++ if (left >= RSN_SELECTOR_LEN) { ++ ++ *group_cipher = rtw_get_wpa2_cipher_suite(pos); ++ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ ++ } else if (left > 0) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); ++ return _FAIL; ++ } ++ ++ //pairwise_cipher ++ if (left >= 2) ++ { ++ //count = le16_to_cpu(*(u16*)pos); ++ count = RTW_GET_LE16(pos); ++ pos += 2; ++ left -= 2; ++ ++ if (count == 0 || left < count * RSN_SELECTOR_LEN) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " ++ "count %u left %u", __FUNCTION__, count, left)); ++ return _FAIL; ++ } ++ ++ for (i = 0; i < count; i++) ++ { ++ *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); ++ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ } ++ ++ } ++ else if (left == 1) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); ++ ++ return _FAIL; ++ } ++ ++ if (is_8021x) { ++ if (left >= 6) { ++ pos += 2; ++ if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s (): there has 802.1x auth\n", __FUNCTION__)); ++ *is_8021x = 1; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_WAPI_SUPPORT ++int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len) ++{ ++ u8 authmode, i; ++ uint cnt; ++ u8 wapi_oui1[4]={0x0,0x14,0x72,0x01}; ++ u8 wapi_oui2[4]={0x0,0x14,0x72,0x02}; ++ ++_func_enter_; ++ cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_); ++ while(cnt found WPS_IE.....\n"); ++ *wps_ielen = ie_ptr[1]+2; ++ match=_TRUE; ++ } ++ return match; ++} ++ ++u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type) ++{ ++ u8* wps = NULL; ++ ++ DBG_871X( "[%s] frame_type = %d\n", __FUNCTION__, frame_type ); ++ switch( frame_type ) ++ { ++ case 1: ++ case 3: ++ { // Beacon or Probe Response ++ wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen); ++ break; ++ } ++ case 2: ++ { // Probe Request ++ wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen); ++ break; ++ } ++ } ++ return wps; ++} ++ ++/** ++ * rtw_get_wps_ie - Search WPS IE from a series of IEs ++ * @in_ie: Address of IEs to search ++ * @in_len: Length limit from in_ie ++ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie ++ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE ++ * ++ * Returns: The address of the WPS IE found, or NULL ++ */ ++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) ++{ ++ uint cnt; ++ u8 *wpsie_ptr=NULL; ++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ if(wps_ielen) ++ *wps_ielen = 0; ++ ++ if(!in_ie || in_len<=0) ++ return wpsie_ptr; ++ ++ cnt = 0; ++ ++ while(cntwpa_ie = pos; ++ elems->wpa_ie_len = elen; ++ break; ++ case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */ ++ if (elen < 5) { ++ DBG_871X("short WME " ++ "information element ignored " ++ "(len=%lu)\n", ++ (unsigned long) elen); ++ return -1; ++ } ++ switch (pos[4]) { ++ case WME_OUI_SUBTYPE_INFORMATION_ELEMENT: ++ case WME_OUI_SUBTYPE_PARAMETER_ELEMENT: ++ elems->wme = pos; ++ elems->wme_len = elen; ++ break; ++ case WME_OUI_SUBTYPE_TSPEC_ELEMENT: ++ elems->wme_tspec = pos; ++ elems->wme_tspec_len = elen; ++ break; ++ default: ++ DBG_871X("unknown WME " ++ "information element ignored " ++ "(subtype=%d len=%lu)\n", ++ pos[4], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ case 4: ++ /* Wi-Fi Protected Setup (WPS) IE */ ++ elems->wps_ie = pos; ++ elems->wps_ie_len = elen; ++ break; ++ default: ++ DBG_871X("Unknown Microsoft " ++ "information element ignored " ++ "(type=%d len=%lu)\n", ++ pos[3], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ ++ case OUI_BROADCOM: ++ switch (pos[3]) { ++ case VENDOR_HT_CAPAB_OUI_TYPE: ++ elems->vendor_ht_cap = pos; ++ elems->vendor_ht_cap_len = elen; ++ break; ++ default: ++ DBG_871X("Unknown Broadcom " ++ "information element ignored " ++ "(type=%d len=%lu)\n", ++ pos[3], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ ++ default: ++ DBG_871X("unknown vendor specific information " ++ "element ignored (vendor OUI %02x:%02x:%02x " ++ "len=%lu)\n", ++ pos[0], pos[1], pos[2], (unsigned long) elen); ++ return -1; ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * ieee802_11_parse_elems - Parse information elements in management frames ++ * @start: Pointer to the start of IEs ++ * @len: Length of IE buffer in octets ++ * @elems: Data structure for parsed elements ++ * @show_errors: Whether to show parsing errors in debug log ++ * Returns: Parsing result ++ */ ++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, ++ struct rtw_ieee802_11_elems *elems, ++ int show_errors) ++{ ++ uint left = len; ++ u8 *pos = start; ++ int unknown = 0; ++ ++ _rtw_memset(elems, 0, sizeof(*elems)); ++ ++ while (left >= 2) { ++ u8 id, elen; ++ ++ id = *pos++; ++ elen = *pos++; ++ left -= 2; ++ ++ if (elen > left) { ++ if (show_errors) { ++ DBG_871X("IEEE 802.11 element " ++ "parse failed (id=%d elen=%d " ++ "left=%lu)\n", ++ id, elen, (unsigned long) left); ++ } ++ return ParseFailed; ++ } ++ ++ switch (id) { ++ case WLAN_EID_SSID: ++ elems->ssid = pos; ++ elems->ssid_len = elen; ++ break; ++ case WLAN_EID_SUPP_RATES: ++ elems->supp_rates = pos; ++ elems->supp_rates_len = elen; ++ break; ++ case WLAN_EID_FH_PARAMS: ++ elems->fh_params = pos; ++ elems->fh_params_len = elen; ++ break; ++ case WLAN_EID_DS_PARAMS: ++ elems->ds_params = pos; ++ elems->ds_params_len = elen; ++ break; ++ case WLAN_EID_CF_PARAMS: ++ elems->cf_params = pos; ++ elems->cf_params_len = elen; ++ break; ++ case WLAN_EID_TIM: ++ elems->tim = pos; ++ elems->tim_len = elen; ++ break; ++ case WLAN_EID_IBSS_PARAMS: ++ elems->ibss_params = pos; ++ elems->ibss_params_len = elen; ++ break; ++ case WLAN_EID_CHALLENGE: ++ elems->challenge = pos; ++ elems->challenge_len = elen; ++ break; ++ case WLAN_EID_ERP_INFO: ++ elems->erp_info = pos; ++ elems->erp_info_len = elen; ++ break; ++ case WLAN_EID_EXT_SUPP_RATES: ++ elems->ext_supp_rates = pos; ++ elems->ext_supp_rates_len = elen; ++ break; ++ case WLAN_EID_VENDOR_SPECIFIC: ++ if (rtw_ieee802_11_parse_vendor_specific(pos, elen, ++ elems, ++ show_errors)) ++ unknown++; ++ break; ++ case WLAN_EID_RSN: ++ elems->rsn_ie = pos; ++ elems->rsn_ie_len = elen; ++ break; ++ case WLAN_EID_PWR_CAPABILITY: ++ elems->power_cap = pos; ++ elems->power_cap_len = elen; ++ break; ++ case WLAN_EID_SUPPORTED_CHANNELS: ++ elems->supp_channels = pos; ++ elems->supp_channels_len = elen; ++ break; ++ case WLAN_EID_MOBILITY_DOMAIN: ++ elems->mdie = pos; ++ elems->mdie_len = elen; ++ break; ++ case WLAN_EID_FAST_BSS_TRANSITION: ++ elems->ftie = pos; ++ elems->ftie_len = elen; ++ break; ++ case WLAN_EID_TIMEOUT_INTERVAL: ++ elems->timeout_int = pos; ++ elems->timeout_int_len = elen; ++ break; ++ case WLAN_EID_HT_CAP: ++ elems->ht_capabilities = pos; ++ elems->ht_capabilities_len = elen; ++ break; ++ case WLAN_EID_HT_OPERATION: ++ elems->ht_operation = pos; ++ elems->ht_operation_len = elen; ++ break; ++ default: ++ unknown++; ++ if (!show_errors) ++ break; ++ DBG_871X("IEEE 802.11 element parse " ++ "ignored unknown element (id=%d elen=%d)\n", ++ id, elen); ++ break; ++ } ++ ++ left -= elen; ++ pos += elen; ++ } ++ ++ if (left) ++ return ParseFailed; ++ ++ return unknown ? ParseUnknown : ParseOK; ++ ++} ++ ++static u8 key_char2num(u8 ch); ++static u8 key_char2num(u8 ch) ++{ ++ if((ch>='0')&&(ch<='9')) ++ return ch - '0'; ++ else if ((ch>='a')&&(ch<='f')) ++ return ch - 'a' + 10; ++ else if ((ch>='A')&&(ch<='F')) ++ return ch - 'A' + 10; ++ else ++ return 0xff; ++} ++ ++u8 str_2char2num(u8 hch, u8 lch); ++u8 str_2char2num(u8 hch, u8 lch) ++{ ++ return ((key_char2num(hch) * 10 ) + key_char2num(lch)); ++} ++ ++u8 key_2char2num(u8 hch, u8 lch); ++u8 key_2char2num(u8 hch, u8 lch) ++{ ++ return ((key_char2num(hch) << 4) | key_char2num(lch)); ++} ++ ++u8 convert_ip_addr(u8 hch, u8 mch, u8 lch) ++{ ++ return ((key_char2num(hch) * 100) + (key_char2num(mch) * 10 ) + key_char2num(lch)); ++} ++ ++extern char* rtw_initmac; ++void rtw_macaddr_cfg(u8 *mac_addr) ++{ ++ u8 mac[ETH_ALEN]; ++ if(mac_addr == NULL) return; ++ ++ if ( rtw_initmac ) ++ { // Users specify the mac address ++ int jj,kk; ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk+ 1]); ++ } ++ _rtw_memcpy(mac_addr, mac, ETH_ALEN); ++ } ++ else ++ { // Use the mac address stored in the Efuse ++ _rtw_memcpy(mac, mac_addr, ETH_ALEN); ++ } ++ ++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) && ++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) || ++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) && ++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0))) ++ { ++ mac[0] = 0x00; ++ mac[1] = 0xe0; ++ mac[2] = 0x4c; ++ mac[3] = 0x87; ++ mac[4] = 0x00; ++ mac[5] = 0x00; ++ // use default mac addresss ++ _rtw_memcpy(mac_addr, mac, ETH_ALEN); ++ DBG_871X("MAC Address from efuse error, assign default one !!!\n"); ++ } ++ ++ DBG_871X("rtw_macaddr_cfg MAC Address = "MAC_FMT"\n", MAC_ARG(mac_addr)); ++} ++ ++void dump_ies(u8 *buf, u32 buf_len) ++{ ++ u8* pos = (u8*)buf; ++ u8 id, len; ++ ++ while(pos-buf<=buf_len){ ++ id = *pos; ++ len = *(pos+1); ++ ++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); ++ dump_wps_ie(pos, len); ++ #ifdef CONFIG_P2P ++ dump_p2p_ie(pos, len); ++ #ifdef CONFIG_WFD ++ dump_wfd_ie(pos, len); ++ #endif ++ #endif ++ ++ pos+=(2+len); ++ } ++} ++ ++void dump_wps_ie(u8 *ie, u32 ie_len) ++{ ++ u8* pos = (u8*)ie; ++ u16 id; ++ u16 len; ++ ++ u8 *wps_ie; ++ uint wps_ielen; ++ ++ wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); ++ if(wps_ie != ie || wps_ielen == 0) ++ return; ++ ++ pos+=6; ++ while(pos-ie < ie_len){ ++ id = RTW_GET_BE16(pos); ++ len = RTW_GET_BE16(pos + 2); ++ ++ DBG_871X("%s ID:0x%04x, LEN:%u\n", __FUNCTION__, id, len); ++ ++ pos+=(4+len); ++ } ++} ++ ++#ifdef CONFIG_P2P ++/** ++ * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies. ++ * @in_ie: Pointer of the first p2p ie ++ * @in_len: Total len of muiltiple p2p ies ++ * Returns: Length of merged p2p ie length ++ */ ++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len) ++{ ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; ++ int i=0; ++ int j=0, len=0; ++ ++ while( i < in_len) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i); ++ ++ if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) ) ++ { ++ len += pIE->Length-4; // 4 is P2P OUI length, don't count it in this loop ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return len + 4; // Append P2P OUI length at last. ++} ++ ++/** ++ * rtw_p2p_merge_ies - Merge muitiple p2p ies into one ++ * @in_ie: Pointer of the first p2p ie ++ * @in_len: Total len of muiltiple p2p ies ++ * @merge_ie: Pointer of merged ie ++ * Returns: Length of merged p2p ie ++ */ ++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie) ++{ ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 len = 0; ++ u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; ++ u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 }; //EID;Len;OUI, Len would copy at the end of function ++ int i=0; ++ ++ if( merge_ie != NULL) ++ { ++ //Set first P2P OUI ++ _rtw_memcpy(merge_ie, ELOUI, 6); ++ merge_ie += 6; ++ ++ while( i < in_len) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i); ++ ++ // Take out the rest of P2P OUIs ++ if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) ) ++ { ++ _rtw_memcpy( merge_ie, pIE->data +4, pIE->Length -4); ++ len += pIE->Length-4; ++ merge_ie += pIE->Length-4; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return len + 4; // 4 is for P2P OUI ++ ++ } ++ ++ return 0; ++} ++ ++void dump_p2p_ie(u8 *ie, u32 ie_len) { ++ u8* pos = (u8*)ie; ++ u8 id; ++ u16 len; ++ ++ u8 *p2p_ie; ++ uint p2p_ielen; ++ ++ p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); ++ if(p2p_ie != ie || p2p_ielen == 0) ++ return; ++ ++ pos+=6; ++ while(pos-ie < ie_len){ ++ id = *pos; ++ len = RTW_GET_LE16(pos+1); ++ ++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); ++ ++ pos+=(3+len); ++ } ++} ++ ++u8 *rtw_get_p2p_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type) ++{ ++ u8* p2p = NULL; ++ ++ DBG_871X( "[%s] frame_type = %d\n", __FUNCTION__, frame_type ); ++ switch( frame_type ) ++ { ++ case 1: ++ case 3: ++ { // Beacon or Probe Response ++ p2p = rtw_get_p2p_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, p2p_ie, p2p_ielen); ++ break; ++ } ++ case 2: ++ { // Probe Request ++ p2p = rtw_get_p2p_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , p2p_ie, p2p_ielen); ++ break; ++ } ++ } ++ return p2p; ++} ++ ++/** ++ * rtw_get_p2p_ie - Search P2P IE from a series of IEs ++ * @in_ie: Address of IEs to search ++ * @in_len: Length limit from in_ie ++ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie ++ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE ++ * ++ * Returns: The address of the P2P IE found, or NULL ++ */ ++u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) ++{ ++ uint cnt = 0; ++ u8 *p2p_ie_ptr; ++ u8 eid, p2p_oui[4]={0x50,0x6F,0x9A,0x09}; ++ ++ if ( p2p_ielen != NULL ) ++ *p2p_ielen = 0; ++ ++ while(cnt MAX_IE_SZ)) { ++#ifdef PLATFORM_LINUX ++ dump_stack(); ++#endif ++ return NULL; ++ } ++ if( ( eid == _VENDOR_SPECIFIC_IE_ ) && ( _rtw_memcmp( &in_ie[cnt+2], p2p_oui, 4) == _TRUE ) ) ++ { ++ p2p_ie_ptr = in_ie + cnt; ++ ++ if ( p2p_ie != NULL ) ++ { ++ _rtw_memcpy( p2p_ie, &in_ie[ cnt ], in_ie[ cnt + 1 ] + 2 ); ++ } ++ ++ if ( p2p_ielen != NULL ) ++ { ++ *p2p_ielen = in_ie[ cnt + 1 ] + 2; ++ } ++ ++ return p2p_ie_ptr; ++ ++ break; ++ } ++ else ++ { ++ cnt += in_ie[ cnt + 1 ] +2; //goto next ++ } ++ ++ } ++ ++ return NULL; ++ ++} ++ ++/** ++ * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE ++ * @p2p_ie: Address of P2P IE to search ++ * @p2p_ielen: Length limit from p2p_ie ++ * @target_attr_id: The attribute ID of P2P attribute to search ++ * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr ++ * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute ++ * ++ * Returns: the address of the specific WPS attribute found, or NULL ++ */ ++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr) ++{ ++ u8 *attr_ptr = NULL; ++ u8 *target_attr_ptr = NULL; ++ u8 p2p_oui[4]={0x50,0x6F,0x9A,0x09}; ++ ++ if(len_attr) ++ *len_attr = 0; ++ ++ if ( !p2p_ie || ( p2p_ie[0] != _VENDOR_SPECIFIC_IE_ ) || ++ ( _rtw_memcmp( p2p_ie + 2, p2p_oui , 4 ) != _TRUE ) ) ++ { ++ return attr_ptr; ++ } ++ ++ // 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) ++ attr_ptr = p2p_ie + 6; //goto first attr ++ ++ while(attr_ptr - p2p_ie < p2p_ielen) ++ { ++ // 3 = 1(Attribute ID) + 2(Length) ++ u8 attr_id = *attr_ptr; ++ u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1); ++ u16 attr_len = attr_data_len + 3; ++ ++ //DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); ++ if( attr_id == target_attr_id ) ++ { ++ target_attr_ptr = attr_ptr; ++ ++ if(buf_attr) ++ _rtw_memcpy(buf_attr, attr_ptr, attr_len); ++ ++ if(len_attr) ++ *len_attr = attr_len; ++ ++ break; ++ } ++ else ++ { ++ attr_ptr += attr_len; //goto next ++ } ++ ++ } ++ ++ return target_attr_ptr; ++} ++ ++/** ++ * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE ++ * @p2p_ie: Address of P2P IE to search ++ * @p2p_ielen: Length limit from p2p_ie ++ * @target_attr_id: The attribute ID of P2P attribute to search ++ * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content ++ * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content ++ * ++ * Returns: the address of the specific P2P attribute content found, or NULL ++ */ ++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content) ++{ ++ u8 *attr_ptr; ++ u32 attr_len; ++ ++ if(len_content) ++ *len_content = 0; ++ ++ attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len); ++ ++ if(attr_ptr && attr_len) ++ { ++ if(buf_content) ++ _rtw_memcpy(buf_content, attr_ptr+3, attr_len-3); ++ ++ if(len_content) ++ *len_content = attr_len-3; ++ ++ return attr_ptr+3; ++ } ++ ++ return NULL; ++} ++ ++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr) ++{ ++ u32 a_len; ++ ++ *pbuf = attr_id; ++ ++ //*(u16*)(pbuf + 1) = cpu_to_le16(attr_len); ++ RTW_PUT_LE16(pbuf + 1, attr_len); ++ ++ if(pdata_attr) ++ _rtw_memcpy(pbuf + 3, pdata_attr, attr_len); ++ ++ a_len = attr_len + 3; ++ ++ return a_len; ++} ++ ++static uint rtw_p2p_attr_remove(u8 *ie, uint ielen_ori, u8 attr_id) ++{ ++ u8 *target_attr; ++ u32 target_attr_len; ++ uint ielen = ielen_ori; ++ int index=0; ++ ++ while(1) { ++ target_attr=rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len); ++ if(target_attr && target_attr_len) ++ { ++ u8 *next_attr = target_attr+target_attr_len; ++ uint remain_len = ielen-(next_attr-ie); ++ //dump_ies(ie, ielen); ++ #if 0 ++ DBG_871X("[%d] ie:%p, ielen:%u\n" ++ "target_attr:%p, target_attr_len:%u\n" ++ "next_attr:%p, remain_len:%u\n" ++ , index++ ++ , ie, ielen ++ , target_attr, target_attr_len ++ , next_attr, remain_len ++ ); ++ #endif ++ ++ _rtw_memset(target_attr, 0, target_attr_len); ++ _rtw_memcpy(target_attr, next_attr, remain_len); ++ _rtw_memset(target_attr+remain_len, 0, target_attr_len); ++ *(ie+1) -= target_attr_len; ++ ielen-=target_attr_len; ++ } ++ else ++ { ++ //if(index>0) ++ // dump_ies(ie, ielen); ++ break; ++ } ++ } ++ ++ return ielen; ++} ++ ++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) ++{ ++ u8 *p2p_ie; ++ uint p2p_ielen, p2p_ielen_ori; ++ int cnt; ++ ++ if( (p2p_ie=rtw_get_p2p_ie(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen_ori)) ) ++ { ++ #if 0 ++ if(rtw_get_p2p_attr(p2p_ie, p2p_ielen_ori, attr_id, NULL, NULL)) { ++ DBG_871X("rtw_get_p2p_attr: GOT P2P_ATTR:%u!!!!!!!!\n", attr_id); ++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_); ++ } ++ #endif ++ ++ p2p_ielen=rtw_p2p_attr_remove(p2p_ie, p2p_ielen_ori, attr_id); ++ if(p2p_ielen != p2p_ielen_ori) { ++ ++ u8 *next_ie_ori = p2p_ie+p2p_ielen_ori; ++ u8 *next_ie = p2p_ie+p2p_ielen; ++ uint remain_len = bss_ex->IELength-(next_ie_ori-bss_ex->IEs); ++ ++ _rtw_memcpy(next_ie, next_ie_ori, remain_len); ++ _rtw_memset(next_ie+remain_len, 0, p2p_ielen_ori-p2p_ielen); ++ bss_ex->IELength -= p2p_ielen_ori-p2p_ielen; ++ ++ #if 0 ++ DBG_871X("remove P2P_ATTR:%u!\n", attr_id); ++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_); ++ #endif ++ } ++ } ++} ++ ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_WFD ++void dump_wfd_ie(u8 *ie, u32 ie_len) ++{ ++ u8* pos = (u8*)ie; ++ u8 id; ++ u16 len; ++ ++ u8 *wfd_ie; ++ uint wfd_ielen; ++ ++ if(rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen) == _FALSE) ++ return; ++ ++ pos+=6; ++ while(pos-ie < ie_len){ ++ id = *pos; ++ len = RTW_GET_BE16(pos+1); ++ ++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); ++ ++ pos+=(3+len); ++ } ++} ++ ++int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) ++{ ++ int match; ++ uint cnt = 0; ++ u8 eid, wfd_oui[4]={0x50,0x6F,0x9A,0x0A}; ++ ++ ++ match=_FALSE; ++ ++ if ( in_len < 0 ) ++ { ++ return match; ++ } ++ ++ while(cnt 1 byte for attribute ID field, 2 bytes for length field ++ if(attr_content) ++ _rtw_memcpy( attr_content, &wfd_ie[ cnt + 3 ], attrlen ); ++ ++ if(attr_contentlen) ++ *attr_contentlen = attrlen; ++ ++ cnt += attrlen + 3; ++ ++ match = _TRUE; ++ break; ++ } ++ else ++ { ++ cnt += attrlen + 3; //goto next ++ } ++ ++ } ++ ++ return match; ++ ++} ++#endif // CONFIG_WFD ++ ++//Baron adds to avoid FreeBSD warning ++int ieee80211_is_empty_essid(const char *essid, int essid_len) ++{ ++ /* Single white space is for Linksys APs */ ++ if (essid_len == 1 && essid[0] == ' ') ++ return 1; ++ ++ /* Otherwise, if the entire essid is 0, we assume it is hidden */ ++ while (essid_len) { ++ essid_len--; ++ if (essid[essid_len] != '\0') ++ return 0; ++ } ++ ++ return 1; ++} ++ ++int ieee80211_get_hdrlen(u16 fc) ++{ ++ int hdrlen = 24; ++ ++ switch (WLAN_FC_GET_TYPE(fc)) { ++ case RTW_IEEE80211_FTYPE_DATA: ++ if (fc & RTW_IEEE80211_STYPE_QOS_DATA) ++ hdrlen += 2; ++ if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS)) ++ hdrlen += 6; /* Addr4 */ ++ break; ++ case RTW_IEEE80211_FTYPE_CTL: ++ switch (WLAN_FC_GET_STYPE(fc)) { ++ case RTW_IEEE80211_STYPE_CTS: ++ case RTW_IEEE80211_STYPE_ACK: ++ hdrlen = 10; ++ break; ++ default: ++ hdrlen = 16; ++ break; ++ } ++ break; ++ } ++ ++ return hdrlen; ++} ++ ++int rtw_get_cipher_info(struct wlan_network *pnetwork) ++{ ++ u32 wpa_ielen; ++ unsigned char *pbuf; ++ int group_cipher = 0, pairwise_cipher = 0, is8021x = 0; ++ int ret = _FAIL; ++ pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ ++ if(pbuf && (wpa_ielen>0)) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_cipher_info: wpa_ielen: %d", wpa_ielen)); ++ if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is8021x)) { ++ ++ pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; ++ pnetwork->BcnInfo.group_cipher = group_cipher; ++ pnetwork->BcnInfo.is_8021x = is8021x; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s: pnetwork->pairwise_cipher: %d, is_8021x is %d", ++ __func__, pnetwork->BcnInfo.pairwise_cipher, pnetwork->BcnInfo.is_8021x)); ++ ret = _SUCCESS; ++ } ++ } else { ++ ++ pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ ++ if(pbuf && (wpa_ielen>0)) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("get RSN IE\n")); ++ if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is8021x)) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("get RSN IE OK!!!\n")); ++ pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; ++ pnetwork->BcnInfo.group_cipher = group_cipher; ++ pnetwork->BcnInfo.is_8021x = is8021x; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s: pnetwork->pairwise_cipher: %d," ++ "pnetwork->group_cipher is %d, is_8021x is %d", __func__, pnetwork->BcnInfo.pairwise_cipher, ++ pnetwork->BcnInfo.group_cipher,pnetwork->BcnInfo.is_8021x)); ++ ret = _SUCCESS; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++void rtw_get_bcn_info(struct wlan_network *pnetwork) ++{ ++ unsigned short cap = 0; ++ u8 bencrypt = 0; ++ //u8 wpa_ie[255],rsn_ie[255]; ++ u16 wpa_len=0,rsn_len=0; ++ struct HT_info_element *pht_info = NULL; ++ struct rtw_ieee80211_ht_cap *pht_cap = NULL; ++ unsigned int len; ++ unsigned char *p; ++ ++ _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); ++ cap = le16_to_cpu(cap); ++ if (cap & WLAN_CAPABILITY_PRIVACY) { ++ bencrypt = 1; ++ pnetwork->network.Privacy = 1; ++ } else { ++ pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS; ++ } ++ rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,NULL,&rsn_len,NULL,&wpa_len); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: ssid=%s\n",pnetwork->network.Ssid.Ssid)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: ssid=%s\n",pnetwork->network.Ssid.Ssid)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); ++ ++ if (rsn_len > 0) { ++ pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2; ++ } else if (wpa_len > 0) { ++ pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA; ++ } else { ++ if (bencrypt) ++ pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP; ++ } ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", ++ pnetwork->BcnInfo.encryp_protocol)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", ++ pnetwork->BcnInfo.encryp_protocol)); ++ rtw_get_cipher_info(pnetwork); ++ ++ /* get bwmode and ch_offset */ ++ /* parsing HT_CAP_IE */ ++ p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); ++ if(p && len>0) { ++ pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); ++ pnetwork->BcnInfo.ht_cap_info = pht_cap->cap_info; ++ } else { ++ pnetwork->BcnInfo.ht_cap_info = 0; ++ } ++ /* parsing HT_INFO_IE */ ++ p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); ++ if(p && len>0) { ++ pht_info = (struct HT_info_element *)(p + 2); ++ pnetwork->BcnInfo.ht_info_infos_0 = pht_info->infos[0]; ++ } else { ++ pnetwork->BcnInfo.ht_info_infos_0 = 0; ++ } ++} ++ ++//show MCS rate, unit: 100Kbps ++u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate) ++{ ++ u16 max_rate = 0; ++ ++ if(rf_type == RF_1T1R) ++ { ++ if(MCS_rate[0] & BIT(7)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1500:1350):((short_GI_20)?722:650); ++ else if(MCS_rate[0] & BIT(6)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1350:1215):((short_GI_20)?650:585); ++ else if(MCS_rate[0] & BIT(5)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520); ++ else if(MCS_rate[0] & BIT(4)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390); ++ else if(MCS_rate[0] & BIT(3)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260); ++ else if(MCS_rate[0] & BIT(2)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?450:405):((short_GI_20)?217:195); ++ else if(MCS_rate[0] & BIT(1)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130); ++ else if(MCS_rate[0] & BIT(0)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?150:135):((short_GI_20)?72:65); ++ } ++ else ++ { ++ if(MCS_rate[1]) ++ { ++ if(MCS_rate[1] & BIT(7)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?3000:2700):((short_GI_20)?1444:1300); ++ else if(MCS_rate[1] & BIT(6)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?2700:2430):((short_GI_20)?1300:1170); ++ else if(MCS_rate[1] & BIT(5)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?2400:2160):((short_GI_20)?1156:1040); ++ else if(MCS_rate[1] & BIT(4)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1800:1620):((short_GI_20)?867:780); ++ else if(MCS_rate[1] & BIT(3)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520); ++ else if(MCS_rate[1] & BIT(2)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390); ++ else if(MCS_rate[1] & BIT(1)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260); ++ else if(MCS_rate[1] & BIT(0)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130); ++ } ++ else ++ { ++ if(MCS_rate[0] & BIT(7)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1500:1350):((short_GI_20)?722:650); ++ else if(MCS_rate[0] & BIT(6)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1350:1215):((short_GI_20)?650:585); ++ else if(MCS_rate[0] & BIT(5)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?1200:1080):((short_GI_20)?578:520); ++ else if(MCS_rate[0] & BIT(4)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?900:810):((short_GI_20)?433:390); ++ else if(MCS_rate[0] & BIT(3)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?600:540):((short_GI_20)?289:260); ++ else if(MCS_rate[0] & BIT(2)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?450:405):((short_GI_20)?217:195); ++ else if(MCS_rate[0] & BIT(1)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?300:270):((short_GI_20)?144:130); ++ else if(MCS_rate[0] & BIT(0)) ++ max_rate = (bw_40MHz) ? ((short_GI_40)?150:135):((short_GI_20)?72:65); ++ } ++ } ++ return max_rate; ++} ++ ++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action) ++{ ++ const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); ++ u16 fc; ++ u8 c, a; ++ ++ fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl); ++ ++ if ((fc & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)) ++ != (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION) ++ ) ++ { ++ return _FALSE; ++ } ++ ++ c = frame_body[0]; ++ ++ switch(c) { ++ case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */ ++ break; ++ default: ++ a = frame_body[1]; ++ } ++ ++ if (category) ++ *category = c; ++ if (action) ++ *action = a; ++ ++ return _TRUE; ++} ++ ++static const char *_action_public_str[] = { ++ "ACT_PUB_BSSCOEXIST", ++ "ACT_PUB_DSE_ENABLE", ++ "ACT_PUB_DSE_DEENABLE", ++ "ACT_PUB_DSE_REG_LOCATION", ++ "ACT_PUB_EXT_CHL_SWITCH", ++ "ACT_PUB_DSE_MSR_REQ", ++ "ACT_PUB_DSE_MSR_RPRT", ++ "ACT_PUB_MP", ++ "ACT_PUB_DSE_PWR_CONSTRAINT", ++ "ACT_PUB_VENDOR", ++ "ACT_PUB_GAS_INITIAL_REQ", ++ "ACT_PUB_GAS_INITIAL_RSP", ++ "ACT_PUB_GAS_COMEBACK_REQ", ++ "ACT_PUB_GAS_COMEBACK_RSP", ++ "ACT_PUB_TDLS_DISCOVERY_RSP", ++ "ACT_PUB_LOCATION_TRACK", ++ "ACT_PUB_RSVD", ++}; ++ ++const char *action_public_str(u8 action) ++{ ++ action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action; ++ return _action_public_str[action]; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_io.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_io.c +new file mode 100644 +index 00000000..26797830 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_io.c +@@ -0,0 +1,509 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/* ++ ++The purpose of rtw_io.c ++ ++a. provides the API ++ ++b. provides the protocol engine ++ ++c. provides the software interface between caller and the hardware interface ++ ++ ++Compiler Flag Option: ++ ++1. CONFIG_SDIO_HCI: ++ a. USE_SYNC_IRP: Only sync operations are provided. ++ b. USE_ASYNC_IRP:Both sync/async operations are provided. ++ ++2. CONFIG_USB_HCI: ++ a. USE_ASYNC_IRP: Both sync/async operations are provided. ++ ++3. CONFIG_CFIO_HCI: ++ b. USE_SYNC_IRP: Only sync operations are provided. ++ ++ ++Only sync read/rtw_write_mem operations are provided. ++ ++jackson@realtek.com.tw ++ ++*/ ++ ++#define _RTW_IO_C_ ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++#ifdef CONFIG_GSPI_HCI ++#include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++#define rtw_le16_to_cpu(val) val ++#define rtw_le32_to_cpu(val) val ++#define rtw_cpu_to_le16(val) val ++#define rtw_cpu_to_le32(val) val ++#else ++#define rtw_le16_to_cpu(val) le16_to_cpu(val) ++#define rtw_le32_to_cpu(val) le32_to_cpu(val) ++#define rtw_cpu_to_le16(val) cpu_to_le16(val) ++#define rtw_cpu_to_le32(val) cpu_to_le32(val) ++#endif ++ ++ ++u8 _rtw_read8(_adapter *adapter, u32 addr) ++{ ++ u8 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read8 = pintfhdl->io_ops._read8; ++ ++ r_val = _read8(pintfhdl, addr); ++ _func_exit_; ++ return r_val; ++} ++ ++u16 _rtw_read16(_adapter *adapter, u32 addr) ++{ ++ u16 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read16 = pintfhdl->io_ops._read16; ++ ++ r_val = _read16(pintfhdl, addr); ++ _func_exit_; ++ return rtw_le16_to_cpu(r_val); ++} ++ ++u32 _rtw_read32(_adapter *adapter, u32 addr) ++{ ++ u32 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read32 = pintfhdl->io_ops._read32; ++ ++ r_val = _read32(pintfhdl, addr); ++ _func_exit_; ++ return rtw_le32_to_cpu(r_val); ++ ++} ++ ++int _rtw_write8(_adapter *adapter, u32 addr, u8 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int ret; ++ _func_enter_; ++ _write8 = pintfhdl->io_ops._write8; ++ ++ ret = _write8(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write16(_adapter *adapter, u32 addr, u16 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int ret; ++ _func_enter_; ++ _write16 = pintfhdl->io_ops._write16; ++ ++ val = rtw_cpu_to_le16(val); ++ ret = _write16(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write32(_adapter *adapter, u32 addr, u32 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ int ret; ++ _func_enter_; ++ _write32 = pintfhdl->io_ops._write32; ++ ++ val = rtw_cpu_to_le32(val); ++ ret = _write32(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++ ++int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf)); ++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata); ++ int ret; ++ _func_enter_; ++ _writeN = pintfhdl->io_ops._writeN; ++ ++ ret = _writeN(pintfhdl, addr,length,pdata); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int ret; ++ _func_enter_; ++ _write8_async = pintfhdl->io_ops._write8_async; ++ ++ ret = _write8_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int ret; ++ _func_enter_; ++ _write16_async = pintfhdl->io_ops._write16_async; ++ val = rtw_cpu_to_le16(val); ++ ret = _write16_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ int ret; ++ _func_enter_; ++ _write32_async = pintfhdl->io_ops._write32_async; ++ val = rtw_cpu_to_le32(val); ++ ret = _write32_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++ ++void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved)); ++ return; ++ } ++ ++ _read_mem = pintfhdl->io_ops._read_mem; ++ ++ _read_mem(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ _write_mem = pintfhdl->io_ops._write_mem; ++ ++ _write_mem(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved)); ++ return; ++ } ++ ++ _read_port = pintfhdl->io_ops._read_port; ++ ++ _read_port(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_read_port_cancel(_adapter *adapter) ++{ ++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl); ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _read_port_cancel = pintfhdl->io_ops._read_port_cancel; ++ ++ if(_read_port_cancel) ++ _read_port_cancel(pintfhdl); ++ ++} ++ ++u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u32 ret = _SUCCESS; ++ ++ _func_enter_; ++ ++ _write_port = pintfhdl->io_ops._write_port; ++ ++ ret = _write_port(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms) ++{ ++ int ret = _SUCCESS; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem; ++ struct submit_ctx sctx; ++ ++ rtw_sctx_init(&sctx, timeout_ms); ++ pxmitbuf->sctx = &sctx; ++ ++ ret = _rtw_write_port(adapter, addr, cnt, pmem); ++ ++ if (ret == _SUCCESS) ++ ret = rtw_sctx_wait(&sctx); ++ ++ return ret; ++} ++ ++void _rtw_write_port_cancel(_adapter *adapter) ++{ ++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl); ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _write_port_cancel = pintfhdl->io_ops._write_port_cancel; ++ ++ if(_write_port_cancel) ++ _write_port_cancel(pintfhdl); ++ ++} ++ ++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops)) ++{ ++ struct io_priv *piopriv = &padapter->iopriv; ++ struct intf_hdl *pintf = &piopriv->intf; ++ ++ if (set_intf_ops == NULL) ++ return _FAIL; ++ ++ piopriv->padapter = padapter; ++ pintf->padapter = padapter; ++ pintf->pintf_dev = adapter_to_dvobj(padapter); ++ ++ set_intf_ops(&pintf->io_ops); ++ ++ return _SUCCESS; ++} ++ ++/* ++* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR ++* @return _TRUE: ++* @return _FALSE: ++*/ ++int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj) ++{ ++ int ret = _FALSE; ++ int value; ++ if( (value=ATOMIC_INC_RETURN(&dvobj->continual_io_error)) > MAX_CONTINUAL_IO_ERR) { ++ DBG_871X("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR); ++ ret = _TRUE; ++ } else { ++ //DBG_871X("[dvobj:%p] continual_io_error:%d\n", dvobj, value); ++ } ++ return ret; ++} ++ ++/* ++* Set the continual_io_error of this @param dvobjprive to 0 ++*/ ++void rtw_reset_continual_io_error(struct dvobj_priv *dvobj) ++{ ++ ATOMIC_SET(&dvobj->continual_io_error, 0); ++} ++ ++#ifdef DBG_IO ++ ++u16 read_sniff_ranges[][2] = { ++ //{0x550, 0x551}, ++}; ++ ++u16 write_sniff_ranges[][2] = { ++ //{0x550, 0x551}, ++ //{0x4c, 0x4c}, ++}; ++ ++int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2; ++int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2; ++ ++bool match_read_sniff_ranges(u16 addr, u16 len) ++{ ++ int i; ++ for (i = 0; i read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1]) ++ return _TRUE; ++ } ++ ++ return _FALSE; ++} ++ ++bool match_write_sniff_ranges(u16 addr, u16 len) ++{ ++ int i; ++ for (i = 0; i write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1]) ++ return _TRUE; ++ } ++ ++ return _FALSE; ++} ++ ++u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line) ++{ ++ u8 val = _rtw_read8(adapter, addr); ++ ++ if (match_read_sniff_ranges(addr, 1)) ++ DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val); ++ ++ return val; ++} ++ ++u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line) ++{ ++ u16 val = _rtw_read16(adapter, addr); ++ ++ if (match_read_sniff_ranges(addr, 2)) ++ DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val); ++ ++ return val; ++} ++ ++u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line) ++{ ++ u32 val = _rtw_read32(adapter, addr); ++ ++ if (match_read_sniff_ranges(addr, 4)) ++ DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val); ++ ++ return val; ++} ++ ++int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 1)) ++ DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val); ++ ++ return _rtw_write8(adapter, addr, val); ++} ++int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 2)) ++ DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val); ++ ++ return _rtw_write16(adapter, addr, val); ++} ++int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 4)) ++ DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val); ++ ++ return _rtw_write32(adapter, addr, val); ++} ++int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, length)) ++ DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length); ++ ++ return _rtw_writeN(adapter, addr, length, data); ++} ++#endif ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_query.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_query.c +new file mode 100644 +index 00000000..06018867 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_query.c +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_IOCTL_QUERY_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_WINDOWS ++// ++// Added for WPA2-PSK, by Annie, 2005-09-20. ++// ++u8 ++query_802_11_capability( ++ _adapter* Adapter, ++ u8* pucBuf, ++ u32 * pulOutLen ++) ++{ ++ static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = ++ { ++ {Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled}, ++ {Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled}, ++ {Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled}, ++ {Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled}, ++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled} ++ }; ++ static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); ++ NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf; ++ u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported; ++ ++ ++ pCap->Length = sizeof(NDIS_802_11_CAPABILITY); ++ if(ulNumOfPairSupported > 1 ) ++ pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); ++ ++ pCap->Version = 2; ++ pCap->NoOfPMKIDs = NUM_PMKID_CACHE; ++ pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported; ++ ++ if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size. ++ { ++ _rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) ); ++ *pulOutLen = pCap->Length; ++ return _TRUE; ++ } ++ else ++ { ++ *pulOutLen = 0; ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n")); ++ return _FALSE; ++ } ++} ++ ++u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo) ++{ ++ struct wlan_network *tgt_network; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv *psecuritypriv=&(padapter->securitypriv); ++ WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss); ++ u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ unsigned char i,*auth_ie,*supp_ie; ++ ++ //NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); ++ _rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); ++ //pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ ++ //------------------------------------------------------ ++ // Association Request related information ++ //------------------------------------------------------ ++ // Req_1. AvailableRequestFixedIEs ++ if(psecnetwork!=NULL){ ++ ++ pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS; ++ pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10]; ++ _rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress, ++ & psecnetwork->MacAddress, 6); ++ ++ pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ ++ if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE) ++ { ++ ++ if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2) ++ pDest[0] =48; //RSN Information Element ++ else ++ pDest[0] =221; //WPA(SSN) Information Element ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0])); ++ supp_ie=&psecuritypriv->supplicant_ie[0]; ++ for(i=0;inetwork.IELength=%d\n\n", i,(int)psecnetwork->IELength)); ++ while((iRequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4); ++ ++ } ++ ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n")); ++ ++ } ++ ++ ++ //------------------------------------------------------ ++ // Association Response related information ++ //------------------------------------------------------ ++ ++ if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE) ++ { ++ tgt_network =&(pmlmepriv->cur_network); ++ if(tgt_network!=NULL){ ++ pAssocInfo->AvailableResponseFixedIEs = ++ NDIS_802_11_AI_RESFI_CAPABILITIES ++ |NDIS_802_11_AI_RESFI_ASSOCIATIONID ++ ; ++ ++ pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10]; ++ pAssocInfo->ResponseFixedIEs.StatusCode = 0; ++ pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid; ++ ++ pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength; ++ auth_ie=&psecuritypriv->authenticator_ie[0]; ++ ++ for(i=0;i0){ ++ _rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i); ++ pAssocInfo->ResponseIELength =i; ++ } ++ ++ ++ pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength; ++ ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n")); ++ } ++ } ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n")); ++_func_exit_; ++ ++ return _TRUE; ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_rtl.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_rtl.c +new file mode 100644 +index 00000000..d0454a97 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_rtl.c +@@ -0,0 +1,1032 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_IOCTL_RTL_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_MP_INCLUDED ++#include ++#include ++#endif ++ ++struct oid_obj_priv oid_rtl_seg_01_01[] = ++{ ++ {1, &oid_null_function}, //0x80 ++ {1, &oid_null_function}, //0x81 ++ {1, &oid_null_function}, //0x82 ++ {1, &oid_null_function}, //0x83//OID_RT_SET_SNIFFER_MODE ++ {1, &oid_rt_get_signal_quality_hdl}, //0x84 ++ {1, &oid_rt_get_small_packet_crc_hdl}, //0x85 ++ {1, &oid_rt_get_middle_packet_crc_hdl}, //0x86 ++ {1, &oid_rt_get_large_packet_crc_hdl}, //0x87 ++ {1, &oid_rt_get_tx_retry_hdl}, //0x88 ++ {1, &oid_rt_get_rx_retry_hdl}, //0x89 ++ {1, &oid_rt_pro_set_fw_dig_state_hdl}, //0x8A ++ {1, &oid_rt_pro_set_fw_ra_state_hdl} , //0x8B ++ {1, &oid_null_function}, //0x8C ++ {1, &oid_null_function}, //0x8D ++ {1, &oid_null_function}, //0x8E ++ {1, &oid_null_function}, //0x8F ++ {1, &oid_rt_get_rx_total_packet_hdl}, //0x90 ++ {1, &oid_rt_get_tx_beacon_ok_hdl}, //0x91 ++ {1, &oid_rt_get_tx_beacon_err_hdl}, //0x92 ++ {1, &oid_rt_get_rx_icv_err_hdl}, //0x93 ++ {1, &oid_rt_set_encryption_algorithm_hdl}, //0x94 ++ {1, &oid_null_function}, //0x95 ++ {1, &oid_rt_get_preamble_mode_hdl}, //0x96 ++ {1, &oid_null_function}, //0x97 ++ {1, &oid_rt_get_ap_ip_hdl}, //0x98 ++ {1, &oid_rt_get_channelplan_hdl}, //0x99 ++ {1, &oid_rt_set_preamble_mode_hdl}, //0x9A ++ {1, &oid_rt_set_bcn_intvl_hdl}, //0x9B ++ {1, &oid_null_function}, //0x9C ++ {1, &oid_rt_dedicate_probe_hdl}, //0x9D ++ {1, &oid_null_function}, //0x9E ++ {1, &oid_null_function}, //0x9F ++ {1, &oid_null_function}, //0xA0 ++ {1, &oid_null_function}, //0xA1 ++ {1, &oid_null_function}, //0xA2 ++ {1, &oid_null_function}, //0xA3 ++ {1, &oid_null_function}, //0xA4 ++ {1, &oid_null_function}, //0xA5 ++ {1, &oid_null_function}, //0xA6 ++ {1, &oid_rt_get_total_tx_bytes_hdl}, //0xA7 ++ {1, &oid_rt_get_total_rx_bytes_hdl}, //0xA8 ++ {1, &oid_rt_current_tx_power_level_hdl}, //0xA9 ++ {1, &oid_rt_get_enc_key_mismatch_count_hdl}, //0xAA ++ {1, &oid_rt_get_enc_key_match_count_hdl}, //0xAB ++ {1, &oid_rt_get_channel_hdl}, //0xAC ++ {1, &oid_rt_set_channelplan_hdl}, //0xAD ++ {1, &oid_rt_get_hardware_radio_off_hdl}, //0xAE ++ {1, &oid_null_function}, //0xAF ++ {1, &oid_null_function}, //0xB0 ++ {1, &oid_null_function}, //0xB1 ++ {1, &oid_null_function}, //0xB2 ++ {1, &oid_null_function}, //0xB3 ++ {1, &oid_rt_get_key_mismatch_hdl}, //0xB4 ++ {1, &oid_null_function}, //0xB5 ++ {1, &oid_null_function}, //0xB6 ++ {1, &oid_null_function}, //0xB7 ++ {1, &oid_null_function}, //0xB8 ++ {1, &oid_null_function}, //0xB9 ++ {1, &oid_null_function}, //0xBA ++ {1, &oid_rt_supported_wireless_mode_hdl}, //0xBB ++ {1, &oid_rt_get_channel_list_hdl}, //0xBC ++ {1, &oid_rt_get_scan_in_progress_hdl}, //0xBD ++ {1, &oid_null_function}, //0xBE ++ {1, &oid_null_function}, //0xBF ++ {1, &oid_null_function}, //0xC0 ++ {1, &oid_rt_forced_data_rate_hdl}, //0xC1 ++ {1, &oid_rt_wireless_mode_for_scan_list_hdl}, //0xC2 ++ {1, &oid_rt_get_bss_wireless_mode_hdl}, //0xC3 ++ {1, &oid_rt_scan_with_magic_packet_hdl}, //0xC4 ++ {1, &oid_null_function}, //0xC5 ++ {1, &oid_null_function}, //0xC6 ++ {1, &oid_null_function}, //0xC7 ++ {1, &oid_null_function}, //0xC8 ++ {1, &oid_null_function}, //0xC9 ++ {1, &oid_null_function}, //0xCA ++ {1, &oid_null_function}, //0xCB ++ {1, &oid_null_function}, //0xCC ++ {1, &oid_null_function}, //0xCD ++ {1, &oid_null_function}, //0xCE ++ {1, &oid_null_function}, //0xCF ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_01_03[] = ++{ ++ {1, &oid_rt_ap_get_associated_station_list_hdl}, //0x00 ++ {1, &oid_null_function}, //0x01 ++ {1, &oid_rt_ap_switch_into_ap_mode_hdl}, //0x02 ++ {1, &oid_null_function}, //0x03 ++ {1, &oid_rt_ap_supported_hdl}, //0x04 ++ {1, &oid_rt_ap_set_passphrase_hdl}, //0x05 ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_01_11[] = ++{ ++ {1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER ++ {1, &oid_null_function}, //0xC1 OID_CE_USB_WRITE_REGISTRY ++ {1, &oid_null_function}, //0xC2 OID_CE_USB_READ_REGISTRY ++ {1, &oid_null_function}, //0xC3 OID_RT_PRO_SET_INITIAL_GAIN ++ {1, &oid_null_function}, //0xC4 OID_RT_PRO_SET_BB_RF_STANDBY_MODE ++ {1, &oid_null_function}, //0xC5 OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE ++ {1, &oid_null_function}, //0xC6 OID_RT_PRO_SET_TX_CHARGE_PUMP ++ {1, &oid_null_function}, //0xC7 OID_RT_PRO_SET_RX_CHARGE_PUMP ++ {1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8 ++ {1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9 ++ {1, &oid_null_function} //0xCA OID_RT_PRO_QUERY_RF_TYPE ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_03_00[] = ++{ ++ {1, &oid_null_function}, //0x00 ++ {1, &oid_rt_get_connect_state_hdl}, //0x01 ++ {1, &oid_null_function}, //0x02 ++ {1, &oid_null_function}, //0x03 ++ {1, &oid_rt_set_default_key_id_hdl}, //0x04 ++ ++ ++}; ++ ++ ++//************** oid_rtl_seg_01_01 section start ************** ++ ++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ ++ _func_enter_; ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm)) ++ { ++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); ++ if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ ++ _func_enter_; ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ ++ if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm)) ++ { ++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); ++ if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ //DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl \n")); ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++#if 0 ++ if(pMgntInfo->mAssoc || pMgntInfo->mIbss) ++ { ++ ulInfo = pAdapter->RxStats.SignalQuality; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer. ++ } ++ break; ++#endif ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++ ++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(u32)) ++ { ++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); ++ *(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG preamblemode = 0 ; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ if(padapter->registrypriv.preamble == PREAMBLE_LONG) ++ preamblemode = 0; ++ else if (padapter->registrypriv.preamble == PREAMBLE_AUTO) ++ preamblemode = 1; ++ else if (padapter->registrypriv.preamble == PREAMBLE_SHORT) ++ preamblemode = 2; ++ ++ ++ *(ULONG *)poid_par_priv->information_buf = preamblemode ; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ *(u16 *)poid_par_priv->information_buf = peeprompriv->channel_plan ; ++ ++ return status; ++} ++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv; ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ peeprompriv->channel_plan = *(u16 *)poid_par_priv->information_buf ; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG preamblemode = 0; ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ preamblemode = *(ULONG *)poid_par_priv->information_buf ; ++ if( preamblemode == 0) ++ padapter->registrypriv.preamble = PREAMBLE_LONG; ++ else if (preamblemode==1 ) ++ padapter->registrypriv.preamble = PREAMBLE_AUTO; ++ else if ( preamblemode==2 ) ++ padapter->registrypriv.preamble = PREAMBLE_SHORT; ++ ++ *(ULONG *)poid_par_priv->information_buf = preamblemode ; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ *(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); ++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ NDIS_802_11_CONFIGURATION *pnic_Config; ++ ++ ULONG channelnum; ++ ++ _func_enter_; ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ pnic_Config = &pmlmepriv->cur_network.network.Configuration; ++ else ++ pnic_Config = &padapter->registrypriv.dev_network.Configuration; ++ ++ channelnum = pnic_Config->DSConfig; ++ *(ULONG *)poid_par_priv->information_buf = channelnum; ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ _func_exit_; ++ ++ ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG ulInfo = 0 ; ++ //DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n")); ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG)){ ++ ulInfo |= 0x0100; //WIRELESS_MODE_B ++ ulInfo |= 0x0200; //WIRELESS_MODE_G ++ ulInfo |= 0x0400; //WIRELESS_MODE_A ++ ++ *(ULONG *) poid_par_priv->information_buf = ulInfo; ++ //DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else{ ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++ ++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++//************** oid_rtl_seg_01_01 section end ************** ++ ++//************** oid_rtl_seg_01_03 section start ************** ++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++//************** oid_rtl_seg_01_03 section end ************** ++ ++//**************** oid_rtl_seg_01_11 section start **************** ++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ _func_enter_; ++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl \n")); ++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) ++ { ++ //RegOffsetValue - The offset of RF register to write. ++ //RegDataWidth - The data width of RF register to write. ++ //RegDataValue - The value to write. ++ //RegOffsetValue = *((unsigned long*)InformationBuffer); ++ //RegDataWidth = *((unsigned long*)InformationBuffer+1); ++ //RegDataValue = *((unsigned long*)InformationBuffer+2); ++ if(!rtw_setrfreg_cmd(Adapter, ++ *(unsigned char*)poid_par_priv->information_buf, ++ (unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2)))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ _func_enter_; ++ ++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl \n")); ++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) ++ { ++ if(Adapter->mppriv.act_in_progress == _TRUE) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ else ++ { ++ //init workparam ++ Adapter->mppriv.act_in_progress = _TRUE; ++ Adapter->mppriv.workparam.bcompleted= _FALSE; ++ Adapter->mppriv.workparam.act_type = MPT_READ_RF; ++ Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf; ++ Adapter->mppriv.workparam.io_value = 0xcccccccc; ++ ++ //RegOffsetValue - The offset of RF register to read. ++ //RegDataWidth - The data width of RF register to read. ++ //RegDataValue - The value to read. ++ //RegOffsetValue = *((unsigned long*)InformationBuffer); ++ //RegDataWidth = *((unsigned long*)InformationBuffer+1); ++ //RegDataValue = *((unsigned long*)InformationBuffer+2); ++ if(!rtw_getrfreg_cmd(Adapter, ++ *(unsigned char*)poid_par_priv->information_buf, ++ (unsigned char*)&Adapter->mppriv.workparam.io_value)) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ } ++ ++ ++ } ++ else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++ ++//**************** oid_rtl_seg_01_11 section end**************** ++ ++ ++//************** oid_rtl_seg_03_00 section start ************** ++enum _CONNECT_STATE_{ ++ CHECKINGSTATUS, ++ ASSOCIATED, ++ ADHOCMODE, ++ NOTASSOCIATED ++}; ++ ++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ULONG ulInfo; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ // nStatus==0 CheckingStatus ++ // nStatus==1 Associated ++ // nStatus==2 AdHocMode ++ // nStatus==3 NotAssociated ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) ++ ulInfo = CHECKINGSTATUS; ++ else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ ulInfo = ASSOCIATED; ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)== _TRUE) ++ ulInfo = ADHOCMODE; ++ else ++ ulInfo = NOTASSOCIATED ; ++ ++ *(ULONG *)poid_par_priv->information_buf = ulInfo; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++#if 0 ++ // Rearrange the order to let the UI still shows connection when scan is in progress ++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n")); ++ if(pMgntInfo->mAssoc) ++ ulInfo = 1; ++ else if(pMgntInfo->mIbss) ++ ulInfo = 2; ++ else if(pMgntInfo->bScanInProgress) ++ ulInfo = 0; ++ else ++ ulInfo = 3; ++ ulInfoLen = sizeof(ULONG); ++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo)); ++#endif ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//************** oid_rtl_seg_03_00 section end ************** ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_set.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_set.c +new file mode 100644 +index 00000000..d2d07d7e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_ioctl_set.c +@@ -0,0 +1,1486 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_IOCTL_SET_C_ ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#include ++#endif ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++#ifdef CONFIG_GSPI_HCI ++#include ++#endif ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++ ++#define IS_MAC_ADDRESS_BROADCAST(addr) \ ++( \ ++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ ++ (addr[2] == 0xff) && (addr[3] == 0xff) && \ ++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ ++) ++ ++u8 rtw_validate_bssid(u8 *bssid) ++{ ++ u8 ret = _TRUE; ++ ++ if (is_zero_mac_addr(bssid) ++ || is_broadcast_mac_addr(bssid) ++ || is_multicast_mac_addr(bssid) ++ ) { ++ ret = _FALSE; ++ } ++ ++ return ret; ++} ++ ++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) ++{ ++ u8 i; ++ u8 ret=_TRUE; ++ ++_func_enter_; ++ ++ if (ssid->SsidLength > 32) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n")); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++#ifdef CONFIG_VALIDATE_SSID ++ for(i = 0; i < ssid->SsidLength; i++) ++ { ++ //wifi, printable ascii code must be supported ++ if(!( (ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e) )){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n")); ++ ret= _FALSE; ++ break; ++ } ++ } ++#endif /* CONFIG_VALIDATE_SSID */ ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_do_join(_adapter * padapter); ++u8 rtw_do_join(_adapter * padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ u8* pibss = NULL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist)); ++ ++ pmlmepriv->cur_network.join_res = -2; ++ ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ pmlmepriv->pscanned = plist; ++ ++ pmlmepriv->to_join = _TRUE; ++ ++ if(_rtw_queue_empty(queue)== _TRUE) ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ //when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty ++ //we try to issue sitesurvey firstly ++ ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic ==_FALSE ++ || rtw_to_roaming(padapter) > 0 ++ ) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_do_join(): site survey if scanned_queue is empty\n.")); ++ // submit site_survey_cmd ++ if(_SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ) { ++ pmlmepriv->to_join = _FALSE; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_do_join(): site survey return error\n.")); ++ } ++ } ++ else ++ { ++ pmlmepriv->to_join = _FALSE; ++ ret = _FAIL; ++ } ++ ++ goto exit; ++ } ++ else ++ { ++ int select_ret; ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ if((select_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))==_SUCCESS) ++ { ++ pmlmepriv->to_join = _FALSE; ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ } ++ else ++ { ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) ++ { ++ // submit createbss_cmd to change to a ADHOC_MASTER ++ ++ //pmlmepriv->lock has been acquired by caller... ++ WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network); ++ ++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; ++ ++ pibss = padapter->registrypriv.dev_network.MacAddress; ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(padapter); ++ ++ rtw_generate_random_ibss(pibss); ++ ++ if(rtw_createbss_cmd(padapter)!=_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>do_goin: rtw_createbss_cmd status FAIL*** \n ")); ++ ret = _FALSE; ++ goto exit; ++ } ++ ++ pmlmepriv->to_join = _FALSE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode*** \n ")); ++ ++ } ++ else ++ { ++ // can't associate ; reset under-linking ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++#if 0 ++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) ++ { ++ if(_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) ++ { ++ // for funk to do roaming ++ // funk will reconnect, but funk will not sitesurvey before reconnect ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("for funk to do roaming")); ++ if(pmlmepriv->sitesurveyctrl.traffic_busy==_FALSE) ++ rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); ++ } ++ ++ } ++#endif ++ ++ //when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue ++ //we try to issue sitesurvey firstly ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE ++ || rtw_to_roaming(padapter) > 0 ++ ) ++ { ++ //DBG_871X("rtw_do_join() when no desired bss in scanning queue \n"); ++ if( _SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ){ ++ pmlmepriv->to_join = _FALSE; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("do_join(): site survey return error\n.")); ++ } ++ } ++ else ++ { ++ ret = _FAIL; ++ pmlmepriv->to_join = _FALSE; ++ } ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++#ifdef PLATFORM_WINDOWS ++u8 rtw_pnp_set_power_wakeup(_adapter* padapter) ++{ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_wakeup!!!\n")); ++ ++ res = rtw_setstandby_cmd(padapter, 0); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_wakeup!!!\n")); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_pnp_set_power_sleep(_adapter* padapter) ++{ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_sleep!!!\n")); ++ //DbgPrint("+rtw_pnp_set_power_sleep\n"); ++ ++ res = rtw_setstandby_cmd(padapter, 1); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_sleep!!!\n")); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults) ++{ ++_func_enter_; ++ ++ switch( reloadDefaults) ++ { ++ case Ndis802_11ReloadWEPKeys: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n")); ++ break; ++ } ++ ++ // SecClearAllKeys(Adapter); ++ // 8711 CAM was not for En/Decrypt only ++ // so, we can't clear all keys. ++ // should we disable WPAcfg (ox0088) bit 1-2, instead of clear all CAM ++ ++ //TO DO... ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++u8 set_802_11_test(_adapter* padapter, NDIS_802_11_TEST *test) ++{ ++ u8 ret=_TRUE; ++ ++_func_enter_; ++ ++ switch(test->Type) ++ { ++ case 1: ++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->AuthenticationEvent, test->Length - 8); ++ NdisMIndicateStatusComplete(padapter->hndis_adapter); ++ break; ++ ++ case 2: ++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->RssiTrigger, sizeof(NDIS_802_11_RSSI)); ++ NdisMIndicateStatusComplete(padapter->hndis_adapter); ++ break; ++ ++ default: ++ ret=_FALSE; ++ break; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_pmkid(_adapter* padapter, NDIS_802_11_PMKID *pmkid) ++{ ++ u8 ret=_SUCCESS; ++ ++ return ret; ++} ++ ++#endif ++ ++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid) ++{ ++ _irqL irqL; ++ u8 status=_SUCCESS; ++ u32 cur_time = 0; ++ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "set bssid:%pM\n", bssid); ++ ++ if ((bssid[0]==0x00 && bssid[1]==0x00 && bssid[2]==0x00 && bssid[3]==0x00 && bssid[4]==0x00 &&bssid[5]==0x00) || ++ (bssid[0]==0xFF && bssid[1]==0xFF && bssid[2]==0xFF && bssid[3]==0xFF && bssid[4]==0xFF &&bssid[5]==0xFF)) ++ { ++ status = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ DBG_871X("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ goto handle_tkip_countermeasure; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ goto release_mlme_lock; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); ++ ++ if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) ++ { ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) ++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. ++ } else { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set BSSID not the same bssid\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_bssid="MAC_FMT"\n", MAC_ARG(bssid) )); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress) )); ++ ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ } ++ ++handle_tkip_countermeasure: ++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ ++ _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); ++ pmlmepriv->assoc_by_bssid=_TRUE; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ pmlmepriv->to_join = _TRUE; ++ } ++ else { ++ status = rtw_do_join(padapter); ++ } ++ ++release_mlme_lock: ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("rtw_set_802_11_bssid: status=%d\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++u8 rtw_set_802_11_ssid(_adapter* padapter, NDIS_802_11_SSID *ssid) ++{ ++ _irqL irqL; ++ u8 status = _SUCCESS; ++ u32 cur_time = 0; ++ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *pnetwork = &pmlmepriv->cur_network; ++ ++_func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "set ssid [%s] fw_state=0x%08x\n", ++ ssid->Ssid, get_fwstate(pmlmepriv)); ++ ++ if(padapter->hw_init_completed==_FALSE){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ DBG_871X("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ goto handle_tkip_countermeasure; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ goto release_mlme_lock; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ++ ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); ++ ++ if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && ++ (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) ++ { ++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("Set SSID is the same ssid, fw_state=0x%08x\n", ++ get_fwstate(pmlmepriv))); ++ ++ if(rtw_is_same_ibss(padapter, pnetwork) == _FALSE) ++ { ++ //if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ else ++ { ++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. ++ } ++ } ++#ifdef CONFIG_LPS ++ else { ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1); ++ } ++#endif ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set SSID not the same ssid\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength)); ++ ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ } ++ ++handle_tkip_countermeasure: ++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ ++ if (rtw_validate_ssid(ssid) == _FALSE) { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ ++ _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); ++ pmlmepriv->assoc_by_bssid=_FALSE; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ pmlmepriv->to_join = _TRUE; ++ } ++ else { ++ status = rtw_do_join(padapter); ++ } ++ ++release_mlme_lock: ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("-rtw_set_802_11_ssid: status=%d\n", status)); ++ ++_func_exit_; ++ ++ return status; ++ ++} ++ ++u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid) ++{ ++ _irqL irqL; ++ u8 status = _SUCCESS; ++ u32 cur_time = 0; ++ bool bssid_valid = _TRUE; ++ bool ssid_valid = _TRUE; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if (!ssid || rtw_validate_ssid(ssid) == _FALSE) ++ ssid_valid = _FALSE; ++ ++ if (!bssid || rtw_validate_bssid(bssid) == _FALSE) ++ bssid_valid = _FALSE; ++ ++ if (ssid_valid == _FALSE && bssid_valid == _FALSE) { ++ DBG_871X(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n", ++ FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ if(padapter->hw_init_completed==_FALSE){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" fw_state=0x%08x\n", ++ FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ goto handle_tkip_countermeasure; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ goto release_mlme_lock; ++ } ++ ++handle_tkip_countermeasure: ++ if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ ++ if (ssid && ssid_valid) ++ _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); ++ ++ if (bssid && bssid_valid) { ++ _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); ++ pmlmepriv->assoc_by_bssid = _TRUE; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ pmlmepriv->to_join = _TRUE; ++ } ++ else { ++ status = rtw_do_join(padapter); ++ } ++ ++release_mlme_lock: ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return status; ++} ++ ++u8 rtw_set_802_11_infrastructure_mode(_adapter* padapter, ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networktype) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &pmlmepriv->cur_network; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE* pold_state = &(cur_network->network.InfrastructureMode); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_notice_, ++ ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n", ++ *pold_state, networktype, get_fwstate(pmlmepriv))); ++ ++ if(*pold_state != networktype) ++ { ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,(" change mode!")); ++ //DBG_871X("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); ++ ++ if(*pold_state==Ndis802_11APMode) ++ { ++ //change to other mode from Ndis802_11APMode ++ cur_network->join_res = -1; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ stop_ap_mode(padapter); ++#endif ++ } ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ||(*pold_state==Ndis802_11IBSS)) ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)== _TRUE) ) ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if((*pold_state == Ndis802_11Infrastructure) ||(*pold_state == Ndis802_11IBSS)) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ rtw_indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not ++ } ++ } ++ ++ *pold_state = networktype; ++ ++ _clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE); ++ ++ switch(networktype) ++ { ++ case Ndis802_11IBSS: ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ break; ++ ++ case Ndis802_11Infrastructure: ++ set_fwstate(pmlmepriv, WIFI_STATION_STATE); ++ break; ++ ++ case Ndis802_11APMode: ++ set_fwstate(pmlmepriv, WIFI_AP_STATE); ++#ifdef CONFIG_NATIVEAP_MLME ++ start_ap_mode(padapter); ++ //rtw_indicate_connect(padapter); ++#endif ++ ++ break; ++ ++ case Ndis802_11AutoUnknown: ++ case Ndis802_11InfrastructureMax: ++ break; ++ } ++ ++ //SecClearAllKeys(adapter); ++ ++ //RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", ++ // get_fwstate(pmlmepriv) )); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ } ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++ ++u8 rtw_set_802_11_disassociate(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct mlme_priv * pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n")); ++ ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ rtw_indicate_disconnect(padapter); ++ //modify for CONFIG_IEEE80211W, none 11w can use it ++ rtw_free_assoc_resources_cmd(padapter); ++ rtw_pwr_wakeup(padapter); ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ u8 res=_TRUE; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("+rtw_set_802_11_bssid_list_scan(), fw_state=%x\n", get_fwstate(pmlmepriv))); ++ ++ if (padapter == NULL) { ++ res=_FALSE; ++ goto exit; ++ } ++ if (padapter->hw_init_completed==_FALSE){ ++ res = _FALSE; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n===rtw_set_802_11_bssid_list_scan:hw_init_completed==_FALSE===\n")); ++ goto exit; ++ } ++ ++ if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || ++ (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) ++ { ++ // Scan or linking is in progress, do nothing. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_bssid_list_scan fail since fw_state = %x\n", get_fwstate(pmlmepriv))); ++ res = _TRUE; ++ ++ if(check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n\n")); ++ } else { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###pmlmepriv->sitesurveyctrl.traffic_busy==_TRUE\n\n")); ++ } ++ } else { ++ if (rtw_is_scan_deny(padapter)) { ++ DBG_871X(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter)); ++ indicate_wx_scan_complete_event(padapter); ++ return _SUCCESS; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_802_11_authentication_mode(_adapter* padapter, NDIS_802_11_AUTHENTICATION_MODE authmode) ++{ ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ int res; ++ u8 ret; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_802_11_auth.mode(): mode=%x\n", authmode)); ++ ++ psecuritypriv->ndisauthtype=authmode; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype)); ++ ++ if(psecuritypriv->ndisauthtype>3) ++ psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_8021X; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(psecuritypriv->ndisauthtype == 6) ++ psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_WAPI; ++#endif ++ ++ res=rtw_set_auth(padapter,psecuritypriv); ++ ++ if(res==_SUCCESS) ++ ret=_TRUE; ++ else ++ ret=_FALSE; ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_add_wep(_adapter* padapter, NDIS_802_11_WEP *wep){ ++ ++ u8 bdefaultkey; ++ u8 btransmitkey; ++ sint keyid,res; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ bdefaultkey=(wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; //for ??? ++ btransmitkey= (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; //for ??? ++ keyid=wep->KeyIndex & 0x3fffffff; ++ ++ if(keyid>4) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n")); ++ ret=_FALSE; ++ goto exit; ++ } ++ ++ switch(wep->KeyLength) ++ { ++ case 5: ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n")); ++ break; ++ case 13: ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n")); ++ break; ++ default: ++ psecuritypriv->dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n")); ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n",wep->KeyLength,wep->KeyIndex,keyid)); ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]),&(wep->KeyMaterial),wep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[keyid]=wep->KeyLength; ++ ++ psecuritypriv->dot11PrivacyKeyIndex=keyid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x \n", ++ psecuritypriv->dot11DefKey[keyid].skey[0],psecuritypriv->dot11DefKey[keyid].skey[1],psecuritypriv->dot11DefKey[keyid].skey[2], ++ psecuritypriv->dot11DefKey[keyid].skey[3],psecuritypriv->dot11DefKey[keyid].skey[4],psecuritypriv->dot11DefKey[keyid].skey[5], ++ psecuritypriv->dot11DefKey[keyid].skey[6],psecuritypriv->dot11DefKey[keyid].skey[7],psecuritypriv->dot11DefKey[keyid].skey[8], ++ psecuritypriv->dot11DefKey[keyid].skey[9],psecuritypriv->dot11DefKey[keyid].skey[10],psecuritypriv->dot11DefKey[keyid].skey[11], ++ psecuritypriv->dot11DefKey[keyid].skey[12])); ++ ++ res=rtw_set_key(padapter,psecuritypriv, keyid, 1,_TRUE); ++ ++ if(res==_FAIL) ++ ret= _FALSE; ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++u8 rtw_set_802_11_remove_wep(_adapter* padapter, u32 keyindex){ ++ ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (keyindex >= 0x80000000 || padapter == NULL){ ++ ++ ret=_FALSE; ++ goto exit; ++ ++ } ++ else ++ { ++ int res; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ if( keyindex < 4 ){ ++ ++ _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16); ++ ++ res=rtw_set_key(padapter,psecuritypriv,keyindex, 0,_TRUE); ++ ++ psecuritypriv->dot11DefKeylen[keyindex]=0; ++ ++ if(res==_FAIL) ++ ret=_FAIL; ++ ++ } ++ else ++ { ++ ret=_FAIL; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++u8 rtw_set_802_11_add_key(_adapter* padapter, NDIS_802_11_KEY *key){ ++ ++ uint encryptionalgo; ++ u8 * pbssid; ++ struct sta_info *stainfo; ++ u8 bgroup = _FALSE; ++ u8 bgrouptkey = _FALSE;//can be remove later ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)){ ++ ++ // It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, ++ // it must fail the request and return NDIS_STATUS_INVALID_DATA. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ",(int)(key->KeyIndex & 0x80000000) == 0)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: key->KeyIndex=%d \n" ,(int)key->KeyIndex)); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if(key->KeyIndex & 0x40000000) ++ { ++ // Pairwise key ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n")); ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv, pbssid); ++ ++ if((stainfo!=NULL)&&(padapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n")); ++ encryptionalgo=stainfo->dot118021XPrivacy; ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n")); ++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n",encryptionalgo )); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n",padapter->securitypriv.dot11PrivacyAlgrthm)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n",padapter->securitypriv.dot11AuthAlgrthm)); ++ ++ if((stainfo!=NULL)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy)); ++ } ++ ++ if(key->KeyIndex & 0x000000FF){ ++ // The key index is specified in the lower 8 bits by values of zero to 255. ++ // The key index should be set to zero for a Pairwise key, and the driver should fail with ++ // NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" key->KeyIndex & 0x000000FF.\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // check BSSID ++ if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE){ ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MacAddr_isBcst(key->BSSID)\n")); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++ // Check key length for TKIP. ++ //if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) ++ if((encryptionalgo== _TKIP_)&& (key->KeyLength != 32)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("TKIP KeyLength:0x%x != 32\n", key->KeyLength)); ++ ret=_FAIL; ++ goto exit; ++ ++ } ++ ++ // Check key length for AES. ++ if((encryptionalgo== _AES_)&& (key->KeyLength != 16)) { ++ // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. ++ if(key->KeyLength == 32) { ++ key->KeyLength = 16; ++ } else { ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ ++ // Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. ++ if( (encryptionalgo== _WEP40_|| encryptionalgo== _WEP104_) && (key->KeyLength != 5 || key->KeyLength != 13)) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength)); ++ ret=_FAIL; ++ goto exit; ++ } ++ ++ bgroup = _FALSE; ++ ++ // Check the pairwise key. Added by Annie, 2005-07-06. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Pairwise Key set]\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ ++ } ++ else ++ { ++ // Group key - KeyIndex(BIT30==0) ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Group key +++++\n")); ++ ++ ++ // when add wep key through add key and didn't assigned encryption type before ++ if((padapter->securitypriv.ndisauthtype<=3)&&(padapter->securitypriv.dot118021XGrpPrivacy==0)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n", key->KeyLength,padapter->securitypriv.dot11PrivacyAlgrthm,padapter->securitypriv.dot118021XGrpPrivacy)); ++ ++ switch(key->KeyLength) ++ { ++ case 5: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ case 13: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ default: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u \n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ } ++ ++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm)); ++ ++ } ++ else ++ { ++ encryptionalgo=padapter->securitypriv.dot118021XGrpPrivacy; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n", padapter->securitypriv.dot11PrivacyAlgrthm,encryptionalgo,padapter->securitypriv.dot118021XGrpPrivacy,key->KeyLength)); ++ ++ } ++ ++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" IBSS but BSSID is not Broadcast Address.\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // Check key length for TKIP ++ if((encryptionalgo== _TKIP_) && (key->KeyLength != 32)) { ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" TKIP GTK KeyLength:%u != 32\n", key->KeyLength)); ++ ret= _FAIL; ++ goto exit; ++ ++ } else if(encryptionalgo== _AES_ && (key->KeyLength != 16 && key->KeyLength != 32) ) { ++ ++ // Check key length for AES ++ // For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength)); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. ++ if((encryptionalgo== _AES_) && (key->KeyLength == 32) ) { ++ key->KeyLength = 16; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("AES key length changed: %u\n", key->KeyLength) ); ++ } ++ ++ if(key->KeyIndex & 0x8000000) {//error ??? 0x8000_0000 ++ bgrouptkey = _TRUE; ++ } ++ ++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE)&&(check_fwstate(&padapter->mlmepriv, _FW_LINKED)==_TRUE)) ++ { ++ bgrouptkey = _TRUE; ++ } ++ ++ bgroup = _TRUE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n") ); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Group Key set]\n") ); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")) ; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)) ; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ ++ } ++ ++ // If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). ++ if((padapter->securitypriv.dot11AuthAlgrthm !=dot11AuthAlgrthm_8021X)&&(encryptionalgo== _WEP40_ || encryptionalgo== _WEP104_)) ++ { ++ u8 ret; ++ u32 keyindex; ++ u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; ++ NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ WEP key +++++\n")); ++ ++ wep->Length = len; ++ keyindex = key->KeyIndex&0x7fffffff; ++ wep->KeyIndex = keyindex ; ++ wep->KeyLength = key->KeyLength; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:Before memcpy \n")); ++ ++ _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); ++ _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); ++ ++ padapter->securitypriv.dot11DefKeylen[keyindex]=key->KeyLength; ++ padapter->securitypriv.dot11PrivacyKeyIndex=keyindex; ++ ++ ret = rtw_set_802_11_add_wep(padapter, wep); ++ ++ goto exit; ++ ++ } ++ ++ if(key->KeyIndex & 0x20000000){ ++ // SetRSC ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n")); ++ if(bgroup == _TRUE) ++ { ++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; ++ _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); ++ } ++ else ++ { ++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; ++ _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8); ++ } ++ ++ } ++ ++ // Indicate this key idx is used for TX ++ // Save the key in KeyMaterial ++ if(bgroup == _TRUE) // Group transmit key ++ { ++ int res; ++ ++ if(bgrouptkey == _TRUE) ++ { ++ padapter->securitypriv.dot118021XGrpKeyid=(u8)key->KeyIndex; ++ } ++ ++ if((key->KeyIndex&0x3) == 0){ ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ ++ if((key->KeyIndex & 0x10000000)) ++ { ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); ++ ++ } ++ else ++ { ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); ++ ++ } ++ ++ //set group key by index ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength); ++ ++ key->KeyIndex=key->KeyIndex & 0x03; ++ ++ padapter->securitypriv.binstallGrpkey=_TRUE; ++ ++ padapter->securitypriv.bcheck_grpkey=_FALSE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("reset group key")); ++ ++ res=rtw_set_key(padapter,&padapter->securitypriv, key->KeyIndex, 1,_TRUE); ++ ++ if(res==_FAIL) ++ ret= _FAIL; ++ ++ goto exit; ++ ++ } ++ else // Pairwise Key ++ { ++ u8 res; ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); ++ ++ if(stainfo!=NULL) ++ { ++ _rtw_memset( &stainfo->dot118021x_UncstKey, 0, 16);// clear keybuffer ++ ++ _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16); ++ ++ if(encryptionalgo== _TKIP_) ++ { ++ padapter->securitypriv.busetkipkey=_FALSE; ++ ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n ==========_set_timer\n")); ++ ++ // if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] ++ if((key->KeyIndex & 0x10000000)){ ++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); ++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8); ++ ++ } else { ++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8); ++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8); ++ ++ } ++ ++ } ++ else if(encryptionalgo == _AES_) ++ { ++ ++ } ++ ++ ++ //Set key to CAM through H2C command ++ if(bgrouptkey)//never go to here ++ { ++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _FALSE, _TRUE); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n")); ++ } ++ else{ ++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _TRUE, _TRUE); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); ++ } ++ ++ if(res ==_FALSE) ++ ret= _FAIL; ++ ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_remove_key(_adapter* padapter, NDIS_802_11_REMOVE_KEY *key){ ++ ++ uint encryptionalgo; ++ u8 * pbssid; ++ struct sta_info *stainfo; ++ u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE: _TRUE; ++ u8 keyIndex = (u8)key->KeyIndex & 0x03; ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if ((key->KeyIndex & 0xbffffffc) > 0) { ++ ret=_FAIL; ++ goto exit; ++ } ++ ++ if (bgroup == _TRUE) { ++ encryptionalgo= padapter->securitypriv.dot118021XGrpPrivacy; ++ // clear group key by index ++ //NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); ++ //Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; ++ ++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16); ++ ++ //! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. ++ ++ } else { ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); ++ if(stainfo !=NULL){ ++ encryptionalgo=stainfo->dot118021XPrivacy; ++ ++ // clear key by BSSID ++ _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); ++ ++ //! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. ++ ++ } ++ else{ ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return _TRUE; ++ ++} ++ ++/* ++* rtw_get_cur_max_rate - ++* @adapter: pointer to _adapter structure ++* ++* Return 0 or 100Kbps ++*/ ++u16 rtw_get_cur_max_rate(_adapter *adapter) ++{ ++ int i = 0; ++ u8 *p; ++ u16 rate = 0, max_rate = 0; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct registry_priv *pregistrypriv = &adapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++#ifdef CONFIG_80211N_HT ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ u8 rf_type = 0; ++ u8 bw_40MHz=0, short_GI_20=0, short_GI_40=0; ++ u16 mcs_rate=0; ++ u32 ht_ielen = 0; ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (adapter->registrypriv.mp_mode == 1) ++ { ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ return 0; ++ } ++#endif ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) ++ && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE)) ++ return 0; ++ ++#ifdef CONFIG_80211N_HT ++ if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N|WIRELESS_11_5N)) { ++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12); ++ if(p && ht_ielen>0) ++ { ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ ++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); ++ ++ //bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; ++ //cur_bwmod is updated by beacon, pmlmeinfo is updated by association response ++ bw_40MHz = (pmlmeext->cur_bwmode && (HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH & pmlmeinfo->HT_info.infos[0])) ? 1:0; ++ ++ //short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; ++ short_GI_20 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_20) ? 1:0; ++ short_GI_40 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_40) ? 1:0; ++ ++ rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ max_rate = rtw_mcs_rate( ++ rf_type, ++ bw_40MHz & (pregistrypriv->cbw40_enable), ++ short_GI_20, ++ short_GI_40, ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate ++ ); ++ } ++ } ++ else ++#endif //CONFIG_80211N_HT ++ { ++ while( (pcur_bss->SupportedRates[i]!=0) && (pcur_bss->SupportedRates[i]!=0xFF)) ++ { ++ rate = pcur_bss->SupportedRates[i]&0x7F; ++ if(rate>max_rate) ++ max_rate = rate; ++ i++; ++ } ++ ++ max_rate = max_rate*10/2; ++ } ++ ++ return max_rate; ++} ++ ++/* ++* rtw_set_scan_mode - ++* @adapter: pointer to _adapter structure ++* @scan_mode: ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) ++{ ++ if(scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE) ++ return _FAIL; ++ ++ adapter->mlmepriv.scan_mode = scan_mode; ++ ++ return _SUCCESS; ++} ++ ++/* ++* rtw_set_channel_plan - ++* @adapter: pointer to _adapter structure ++* @channel_plan: ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) ++{ ++ struct registry_priv *pregistrypriv = &adapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ //handle by cmd_thread to sync with scan operation ++ return rtw_set_chplan_cmd(adapter, channel_plan, 1); ++} ++ ++/* ++* rtw_set_country - ++* @adapter: pointer to _adapter structure ++* @country_code: string of country code ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_country(_adapter *adapter, const char *country_code) ++{ ++ int channel_plan = RT_CHANNEL_DOMAIN_WORLD_WIDE_5G; ++ ++ DBG_871X("%s country_code:%s\n", __func__, country_code); ++ ++ //TODO: should have a table to match country code and RT_CHANNEL_DOMAIN ++ //TODO: should consider 2-character and 3-character country code ++ if(0 == strcmp(country_code, "US")) ++ channel_plan = RT_CHANNEL_DOMAIN_FCC; ++ else if(0 == strcmp(country_code, "EU")) ++ channel_plan = RT_CHANNEL_DOMAIN_ETSI; ++ else if(0 == strcmp(country_code, "JP")) ++ channel_plan = RT_CHANNEL_DOMAIN_MKK; ++ else if(0 == strcmp(country_code, "CN")) ++ channel_plan = RT_CHANNEL_DOMAIN_CHINA; ++ else if(0 == strcmp(country_code, "IN")) ++ channel_plan = RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN; ++ else ++ DBG_871X("%s unknown country_code:%s\n", __FUNCTION__, country_code); ++ ++ return rtw_set_channel_plan(adapter, channel_plan); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_iol.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_iol.c +new file mode 100644 +index 00000000..0e833be8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_iol.c +@@ -0,0 +1,403 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++ ++#ifdef CONFIG_IOL ++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter) ++{ ++ struct xmit_frame *xmit_frame; ++ struct xmit_buf *xmitbuf; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); ++ ++#if 1 ++ if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__); ++ rtw_free_xmitframe(pxmitpriv, xmit_frame); ++ xmit_frame=NULL; ++ goto exit; ++ } ++ ++ xmit_frame->frame_tag = MGNT_FRAMETAG; ++ xmit_frame->pxmitbuf = xmitbuf; ++ xmit_frame->buf_addr = xmitbuf->pbuf; ++ xmitbuf->priv_data = xmit_frame; ++ ++ pattrib = &xmit_frame->attrib; ++ update_mgntframe_attrib(adapter, pattrib); ++ pattrib->qsel = 0x10;//Beacon ++ pattrib->subtype = WIFI_BEACON; ++ pattrib->pktlen = pattrib->last_txcmdsz = 0; ++ ++#else ++ if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__); ++ } ++ else { ++ pattrib = &xmit_frame->attrib; ++ update_mgntframe_attrib(adapter, pattrib); ++ pattrib->qsel = 0x10; ++ pattrib->pktlen = pattrib->last_txcmdsz = 0; ++ } ++#endif ++ ++exit: ++ return xmit_frame; ++} ++ ++ ++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len) ++{ ++ struct pkt_attrib *pattrib = &xmit_frame->attrib; ++ u16 buf_offset; ++ u32 ori_len; ++ ++ buf_offset = TXDESC_OFFSET; ++ ori_len = buf_offset+pattrib->pktlen; ++ ++ //check if the io_buf can accommodate new cmds ++ if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) { ++ DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__ ++ , ori_len + cmd_len + 8, MAX_XMITBUF_SZ); ++ return _FAIL; ++ } ++ ++ _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len); ++ pattrib->pktlen += cmd_len; ++ pattrib->last_txcmdsz += cmd_len; ++ ++ //DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); ++ ++ return _SUCCESS; ++} ++bool rtw_IOL_applied(ADAPTER *adapter) ++{ ++ if(1 == adapter->registrypriv.fw_iol) ++ return _TRUE; ++ ++#ifdef CONFIG_USB_HCI ++ if((2 == adapter->registrypriv.fw_iol) && (!adapter_to_dvobj(adapter)->ishighspeed)) ++ return _TRUE; ++#endif ++ ++ return _FALSE; ++} ++/* ++bool rtw_IOL_applied(ADAPTER *adapter) ++{ ++ if(adapter->registrypriv.fw_iol) ++ return _TRUE; ++ ++#ifdef CONFIG_USB_HCI ++ if(!adapter_to_dvobj(adapter)->ishighspeed) ++ return _TRUE; ++#endif ++ ++ return _FALSE; ++} ++*/ ++ ++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) ++{ ++ return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms,bndy_cnt); ++} ++ ++#ifdef CONFIG_IOL_NEW_GENERATION ++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) ++{ ++ return _SUCCESS; ++} ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask) ++{ ++ struct ioreg_cfg cmd = {8,IOREG_CMD_WB_REG,0x0, 0x0,0x0}; ++ ++ //RTW_PUT_LE16((u8*)&cmd.address, addr); ++ //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); ++ cmd.address = cpu_to_le16(addr); ++ cmd.data = cpu_to_le32(value); ++ ++ if(mask!=0xFF) ++ { ++ cmd.length = 12; ++ //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); ++ cmd.mask = cpu_to_le32(mask); ++ } ++ ++ //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); ++ ++} ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask) ++{ ++ struct ioreg_cfg cmd = {8,IOREG_CMD_WW_REG,0x0, 0x0,0x0}; ++ ++ //RTW_PUT_LE16((u8*)&cmd.address, addr); ++ //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); ++ cmd.address = cpu_to_le16(addr); ++ cmd.data = cpu_to_le32(value); ++ ++ if(mask!=0xFFFF) ++ { ++ cmd.length = 12; ++ //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); ++ cmd.mask = cpu_to_le32(mask); ++ } ++ ++ //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); ++ ++} ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask) ++{ ++ struct ioreg_cfg cmd = {8,IOREG_CMD_WD_REG,0x0, 0x0,0x0}; ++ ++ //RTW_PUT_LE16((u8*)&cmd.address, addr); ++ //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); ++ cmd.address = cpu_to_le16(addr); ++ cmd.data = cpu_to_le32(value); ++ ++ if(mask!=0xFFFFFFFF) ++ { ++ cmd.length = 12; ++ //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); ++ cmd.mask = cpu_to_le32(mask); ++ } ++ ++ //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); ++ ++} ++ ++int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask) ++{ ++ struct ioreg_cfg cmd = {8,IOREG_CMD_W_RF,0x0, 0x0,0x0}; ++ ++ //RTW_PUT_LE16((u8*)&cmd.address, addr); ++ //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); ++ cmd.address = (rf_path<<8) |((addr) &0xFF); ++ cmd.data = cpu_to_le32(value); ++ ++ if(mask!=0x000FFFFF) ++ { ++ cmd.length = 12; ++ //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); ++ cmd.mask = cpu_to_le32(mask); ++ } ++ ++ //DBG_871X("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); ++ ++} ++ ++ ++ ++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) ++{ ++ struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0}; ++ //RTW_PUT_LE16((u8*)&cmd.address, us); ++ cmd.address = cpu_to_le16(us); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, us); ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); ++} ++ ++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) ++{ ++ struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0}; ++ ++ //RTW_PUT_LE16((u8*)&cmd.address, ms); ++ cmd.address = cpu_to_le16(ms); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, ms); ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); ++} ++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) ++{ ++ struct ioreg_cfg cmd = {4,IOREG_CMD_END,0xFFFF, 0xFF,0x0}; ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); ++ ++} ++ ++u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame) ++{ ++ u8 is_cmd_bndy = _FALSE; ++ if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256){ ++ rtw_IOL_append_END_cmd(pxmit_frame); ++ pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256 ); ++ ++ //printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen); ++ pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen; ++ is_cmd_bndy = _TRUE; ++ } ++ return is_cmd_bndy; ++} ++ ++void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf) ++{ ++ int i; ++ int j=1; ++ ++ printk("###### %s ######\n",__FUNCTION__); ++ for(i=0;i< buf_len;i++){ ++ printk("%02x-",*(pbuf+i)); ++ ++ if(j%32 ==0) printk("\n");j++; ++ } ++ printk("\n"); ++ printk("============= ioreg_cmd len = %d =============== \n",buf_len); ++} ++ ++ ++#else //CONFIG_IOL_NEW_GENERATION ++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0}; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0}; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0}; ++ u8* pos = (u8 *)&cmd; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++#ifdef DBG_IO ++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 1)) ++ DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value); ++} ++ ++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 2)) ++ DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value); ++} ++ ++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line) ++{ ++ if (match_write_sniff_ranges(addr, 4)) ++ DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value); ++} ++#endif ++ ++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)us); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, us); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)ms); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, ms); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) ++{ ++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; ++ ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&end_cmd, 8); ++ ++} ++ ++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms) ++{ ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL) ++ return _FAIL; ++ ++ if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL) ++ return _FAIL; ++ ++ return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,0); ++} ++ ++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms) ++{ ++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; ++ return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms); ++} ++#endif //CONFIG_IOL_NEW_GENERATION ++ ++ ++ ++ ++#endif //CONFIG_IOL ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_led.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_led.c +new file mode 100644 +index 00000000..7710f324 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_led.c +@@ -0,0 +1,2422 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++ ++// ++// Description: ++// Callback function of LED BlinkTimer, ++// it just schedules to corresponding BlinkWorkItem/led_blink_hdl ++// ++void BlinkTimerCallback(void *data) ++{ ++ PLED_871x pLed = (PLED_871x)data; ++ _adapter *padapter = pLed->padapter; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ return; ++ } ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++ #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD ++ rtw_led_blink_cmd(padapter, pLed); ++ #else ++ _set_workitem(&(pLed->BlinkWorkItem)); ++ #endif ++#elif defined(CONFIG_PCI_HCI) ++ BlinkHandler(pLed); ++#endif ++ ++} ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++// ++// Description: ++// Callback function of LED BlinkWorkItem. ++// We dispatch acture LED blink action according to LedStrategy. ++// ++void BlinkWorkItemCallback(struct work_struct *work) ++{ ++ PLED_871x pLed = container_of(work, LED_871x, BlinkWorkItem); ++ BlinkHandler(pLed); ++} ++#endif ++ ++// ++// Description: ++// Reset status of LED_871x object. ++// ++void ResetLedStatus(PLED_871x pLed) { ++ ++ pLed->CurrLedState = RTW_LED_OFF; // Current LED state. ++ pLed->bLedOn = _FALSE; // true if LED is ON, false if LED is OFF. ++ ++ pLed->bLedBlinkInProgress = _FALSE; // true if it is blinking, false o.w.. ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ ++ pLed->BlinkTimes = 0; // Number of times to toggle led state for blinking. ++ pLed->BlinkingLedState = LED_UNKNOWN; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ pLed->bLedStartToLinkBlinkInProgress = _FALSE; ++ pLed->bLedScanBlinkInProgress = _FALSE; ++#endif ++} ++ ++ // ++// Description: ++// Initialize an LED_871x object. ++// ++void ++InitLed871x( ++ _adapter *padapter, ++ PLED_871x pLed, ++ LED_PIN_871x LedPin ++ ) ++{ ++ pLed->padapter = padapter; ++ pLed->LedPin = LedPin; ++ ++ ResetLedStatus(pLed); ++ ++ _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed); ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++ _init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed); ++#endif ++} ++ ++ ++// ++// Description: ++// DeInitialize an LED_871x object. ++// ++void ++DeInitLed871x( ++ PLED_871x pLed ++ ) ++{ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ _cancel_workitem_sync(&(pLed->BlinkWorkItem)); ++#endif ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ ResetLedStatus(pLed); ++} ++ ++ ++// ++// Description: ++// Implementation of LED blinking behavior. ++// It toggle off LED and schedule corresponding timer if necessary. ++// ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ ++void SwLedOn(_adapter *padapter, PLED_871x pLed); ++void SwLedOff(_adapter *padapter, PLED_871x pLed); ++ ++#define CONFIG_LED_REMOVE_HAL ++ ++void ++SwLedBlink( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ // Determine if we shall change LED state again. ++ pLed->BlinkTimes--; ++ switch(pLed->CurrLedState) ++ { ++ ++ case LED_BLINK_NORMAL: ++ if(pLed->BlinkTimes == 0) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ case LED_BLINK_StartToBlink: ++ if( check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if( check_fwstate(pmlmepriv, _FW_LINKED) && ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ else if(pLed->BlinkTimes == 0) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ ++ default: ++ bStopBlinking = _TRUE; ++ break; ++ ++ } ++ ++ if(bStopBlinking) ++ { ++ //if(adapter_to_pwrctl(padapter)->cpwm >= PS_STATE_S2) ++ if(0) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (pLed->bLedOn == _FALSE)) ++ { ++ SwLedOn(padapter, pLed); ++ } ++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && pLed->bLedOn == _TRUE) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ ++ pLed->BlinkTimes = 0; ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ // Assign LED state to toggle. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ ++ // Schedule a timer to toggle LED state. ++ switch( pLed->CurrLedState ) ++ { ++ case LED_BLINK_NORMAL: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ break; ++ ++ case LED_BLINK_SLOWLY: ++ case LED_BLINK_StartToBlink: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ break; ++ ++ case LED_BLINK_WPS: ++ { ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ else ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ break; ++ ++ default: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ break; ++ } ++ } ++} ++ ++void ++SwLedBlink1( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++#ifndef CONFIG_LED_REMOVE_HAL ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#endif ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ u8 bStopBlinking = _FALSE; ++ ++#ifndef CONFIG_LED_REMOVE_HAL ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++#endif ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++#ifndef CONFIG_LED_REMOVE_HAL ++ if(pHalData->EEPROMCustomerID == RT_CID_DEFAULT) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ if(!pLed1->bSWLedCtrl) ++ { ++ SwLedOn(padapter, pLed1); ++ pLed1->bSWLedCtrl = _TRUE; ++ } ++ else if(!pLed1->bLedOn) ++ SwLedOn(padapter, pLed1); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn on pLed1\n")); ++ } ++ else ++ { ++ if(!pLed1->bSWLedCtrl) ++ { ++ SwLedOff(padapter, pLed1); ++ pLed1->bSWLedCtrl = _TRUE; ++ } ++ else if(pLed1->bLedOn) ++ SwLedOff(padapter, pLed1); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn off pLed1\n")); ++ } ++ } ++ ++#endif ++ ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ ResetLedStatus(pLed); ++ return; ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SLOWLY: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_NORMAL: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_SCAN: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_BLINK_TXRX: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->BlinkTimes = 0; ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS success ++ if(pLed->BlinkingLedState == RTW_LED_ON) ++ bStopBlinking = _FALSE; ++ else ++ bStopBlinking = _TRUE; ++ ++ if(bStopBlinking) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++} ++ ++void ++SwLedBlink2( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SCAN: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_TXRX: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++} ++ ++void ++SwLedBlink3( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ if(pLed->CurrLedState != LED_BLINK_WPS_STOP) ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SCAN: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ if( !pLed->bLedOn ) ++ SwLedOn(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if( pLed->bLedOn ) ++ SwLedOff(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_TXRX: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ ++ if( !pLed->bLedOn ) ++ SwLedOn(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ ++ if( pLed->bLedOn ) ++ SwLedOff(padapter, pLed); ++ ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS success ++ if(pLed->BlinkingLedState == RTW_LED_ON) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ bStopBlinking = _FALSE; ++ } ++ else ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++} ++ ++ ++void ++SwLedBlink4( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ if(!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) ++ { ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ pLed1->CurrLedState = RTW_LED_OFF; ++ SwLedOff(padapter, pLed1); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SLOWLY: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_StartToBlink: ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_BLINK_SCAN: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _FALSE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_TXRX: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS authentication fail ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ break; ++ ++ case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap ++ pLed->BlinkTimes--; ++ if(pLed->BlinkTimes == 0) ++ { ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkTimes = 1; ++ } ++ else ++ { ++ bStopBlinking = _TRUE; ++ } ++ } ++ ++ if(bStopBlinking) ++ { ++ pLed->BlinkTimes = 10; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState)); ++ ++ ++} ++ ++void ++SwLedBlink5( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SCAN: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if(pLed->bLedOn) ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ if(!pLed->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ ++ case LED_BLINK_TXRX: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if(pLed->bLedOn) ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ if(!pLed->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); ++ ++ ++} ++ ++void ++SwLedBlink6( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == RTW_LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink6\n")); ++} ++ ++static void ++SwLedControlMode0( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ PLED_871x pLed = &(ledpriv->SwLed1); ++ ++ // Decide led state ++ switch(LedAction) ++ { ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ pLed->BlinkTimes = 2; ++ ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ pLed->BlinkTimes = 24; ++ ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ pLed->CurrLedState = RTW_LED_ON; ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ SwLedOn(padapter, pLed); ++ } ++ break; ++ ++ case LED_CTL_NO_LINK: ++ pLed->CurrLedState = RTW_LED_OFF; ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ if(pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ SwLedOff(padapter, pLed); ++ break; ++ ++ case LED_CTL_START_WPS: ++ if( pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == RTW_LED_ON) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_WPS; ++ pLed->BlinkTimes = 20; ++ ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedBlinkInProgress) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++ ++} ++ ++ //ALPHA, added by chiyoko, 20090106 ++static void ++SwLedControlMode1( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++#ifndef CONFIG_LED_REMOVE_HAL ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#endif ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifndef CONFIG_LED_REMOVE_HAL ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++#endif ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ if( pLed->bLedLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SCAN; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_TXRX; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ } ++ else ++ { ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ } ++ ++ pLed->CurrLedState = LED_BLINK_WPS_STOP; ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if( pLed->bLedNoLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ SwLedOff(padapter, pLed); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ //Arcadyan/Sitecom , added by chiyoko, 20090216 ++static void ++SwLedControlMode2( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_SITE_SURVEY: ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SCAN; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_TXRX; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if(!IS_LED_BLINKING(pLed)) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++} ++ ++ //COREGA, added by chiyoko, 20090316 ++ static void ++ SwLedControlMode3( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_SITE_SURVEY: ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SCAN; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_TXRX; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ } ++ ++ pLed->CurrLedState = LED_BLINK_WPS_STOP; ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if(!IS_LED_BLINKING(pLed)) ++ { ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++} ++ ++ ++ //Edimax-Belkin, added by chiyoko, 20090413 ++static void ++SwLedControlMode4( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_START_TO_LINK: ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ pLed1->CurrLedState = RTW_LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ if( pLed->bLedStartToLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedStartToLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ case LED_CTL_NO_LINK: ++ //LED1 settings ++ if(LedAction == LED_CTL_LINK) ++ { ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ pLed1->CurrLedState = RTW_LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ } ++ ++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SCAN; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_TXRX; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ pLed1->CurrLedState = RTW_LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: //WPS connect success ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ //LED1 settings ++ if(pLed1->bLedWPSBlinkInProgress) ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ else ++ pLed1->bLedWPSBlinkInProgress = _TRUE; ++ ++ pLed1->CurrLedState = LED_BLINK_WPS_STOP; ++ if( pLed1->bLedOn ) ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed1->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ //LED1 settings ++ if(pLed1->bLedWPSBlinkInProgress) ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ else ++ pLed1->bLedWPSBlinkInProgress = _TRUE; ++ ++ pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP; ++ pLed1->BlinkTimes = 10; ++ if( pLed1->bLedOn ) ++ pLed1->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed1->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ ++ if( pLed->bLedNoLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedStartToLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedStartToLinkBlinkInProgress = _FALSE; ++ } ++ ++ if( pLed1->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed1->BlinkingLedState = LED_UNKNOWN; ++ SwLedOff(padapter, pLed); ++ SwLedOff(padapter, pLed1); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ ++ ++ //Sercomm-Belkin, added by chiyoko, 20090415 ++static void ++SwLedControlMode5( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++#ifndef CONFIG_LED_REMOVE_HAL ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#endif ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++#ifndef CONFIG_LED_REMOVE_HAL ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++#endif ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_NO_LINK: ++ case LED_CTL_LINK: //solid blue ++ pLed->CurrLedState = RTW_LED_ON; ++ pLed->BlinkingLedState = RTW_LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SCAN; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_BLINK_SCAN) ++ { ++ return; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_TXRX; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ else ++ pLed->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = RTW_LED_OFF; ++ pLed->BlinkingLedState = RTW_LED_OFF; ++ ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ SwLedOff(padapter, pLed); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ //WNC-Corega, added by chiyoko, 20090902 ++static void ++SwLedControlMode6( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed0 = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_LINK: ++ case LED_CTL_NO_LINK: ++ _cancel_timer_ex(&(pLed0->BlinkTimer)); ++ pLed0->CurrLedState = RTW_LED_ON; ++ pLed0->BlinkingLedState = RTW_LED_ON; ++ _set_timer(&(pLed0->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ SwLedOff(padapter, pLed0); ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("ledcontrol 6 Led %d\n", pLed0->CurrLedState)); ++} ++ ++// ++// Description: ++// Handler function of LED Blinking. ++// We dispatch acture LED blink action according to LedStrategy. ++// ++void BlinkHandler(PLED_871x pLed) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ //DBG_871X("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ return; ++ } ++ ++ switch(ledpriv->LedStrategy) ++ { ++ case SW_LED_MODE0: ++ SwLedBlink(pLed); ++ break; ++ ++ case SW_LED_MODE1: ++ SwLedBlink1(pLed); ++ break; ++ ++ case SW_LED_MODE2: ++ SwLedBlink2(pLed); ++ break; ++ ++ case SW_LED_MODE3: ++ SwLedBlink3(pLed); ++ break; ++ ++ case SW_LED_MODE4: ++ SwLedBlink4(pLed); ++ break; ++ ++ case SW_LED_MODE5: ++ SwLedBlink5(pLed); ++ break; ++ ++ case SW_LED_MODE6: ++ SwLedBlink6(pLed); ++ break; ++ ++ default: ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("BlinkWorkItemCallback 0x%x \n", pHalData->LedStrategy)); ++ //SwLedBlink(pLed); ++ break; ++ } ++} ++ ++void ++LedControl871x( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++ ) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE) ++ ||(padapter->hw_init_completed == _FALSE) ) ++ { ++ return; ++ } ++ ++ ++ if( ledpriv->bRegUseLed == _FALSE) ++ return; ++ ++ //if (!priv->up) ++ // return; ++ ++ //if(priv->bInHctTest) ++ // return; ++ ++ if( (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && ++ adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) && ++ (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX || ++ LedAction == LED_CTL_SITE_SURVEY || ++ LedAction == LED_CTL_LINK || ++ LedAction == LED_CTL_NO_LINK || ++ LedAction == LED_CTL_POWER_ON) ) ++ { ++ return; ++ } ++ ++ switch(ledpriv->LedStrategy) ++ { ++ case SW_LED_MODE0: ++ //SwLedControlMode0(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE1: ++ SwLedControlMode1(padapter, LedAction); ++ break; ++ case SW_LED_MODE2: ++ SwLedControlMode2(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE3: ++ SwLedControlMode3(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE4: ++ SwLedControlMode4(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE5: ++ SwLedControlMode5(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE6: ++ SwLedControlMode6(padapter, LedAction); ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy,LedAction)); ++} ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme.c +new file mode 100644 +index 00000000..f6c7581a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme.c +@@ -0,0 +1,4154 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MLME_C_ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++extern u8 rtw_do_join(_adapter * padapter); ++ ++#ifdef CONFIG_DISABLE_MCS13TO15 ++extern unsigned char MCS_rate_2R_MCS13TO15_OFF[16]; ++extern unsigned char MCS_rate_2R[16]; ++#else //CONFIG_DISABLE_MCS13TO15 ++extern unsigned char MCS_rate_2R[16]; ++#endif //CONFIG_DISABLE_MCS13TO15 ++extern unsigned char MCS_rate_1R[16]; ++ ++sint _rtw_init_mlme_priv (_adapter* padapter) ++{ ++ sint i; ++ u8 *pbuf; ++ struct wlan_network *pnetwork; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ sint res = _SUCCESS; ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); ++ ++ pmlmepriv->nic_hdl = (u8 *)padapter; ++ ++ pmlmepriv->pscanned = NULL; ++ pmlmepriv->fw_state = 0; ++ pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; ++ pmlmepriv->scan_mode=SCAN_ACTIVE;// 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) ++ ++ _rtw_spinlock_init(&(pmlmepriv->lock)); ++ _rtw_init_queue(&(pmlmepriv->free_bss_pool)); ++ _rtw_init_queue(&(pmlmepriv->scanned_queue)); ++ ++ set_scanned_network_val(pmlmepriv, 0); ++ ++ _rtw_memset(&pmlmepriv->assoc_ssid,0,sizeof(NDIS_802_11_SSID)); ++ ++ pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network))); ++ ++ if (pbuf == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ pmlmepriv->free_bss_buf = pbuf; ++ ++ pnetwork = (struct wlan_network *)pbuf; ++ ++ for(i = 0; i < MAX_BSS_CNT; i++) ++ { ++ _rtw_init_listhead(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue)); ++ ++ pnetwork++; ++ } ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ++ rtw_clear_scan_deny(padapter); ++ ++ #ifdef CONFIG_FTP_PROTECT ++ pmlmepriv->ftp_lock_flag = 0; ++ #endif //CONFIG_FTP_PROTECT ++ ++ rtw_init_mlme_timer(padapter); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv); ++void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv) ++{ ++ _rtw_spinlock_free(&pmlmepriv->lock); ++ _rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock)); ++ _rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock)); ++} ++ ++static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen) ++{ ++ if(*ppie) ++ { ++ rtw_mfree(*ppie, *plen); ++ *plen = 0; ++ *ppie=NULL; ++ } ++} ++ ++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) ++{ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); ++ rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); ++ ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); ++#endif ++ ++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) ++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len); ++#endif ++ ++} ++ ++void _rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) ++{ ++_func_enter_; ++ ++ rtw_free_mlme_priv_ie_data(pmlmepriv); ++ ++ if(pmlmepriv){ ++ rtw_mfree_mlme_priv_lock (pmlmepriv); ++ ++ if (pmlmepriv->free_bss_buf) { ++ rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); ++ } ++ } ++_func_exit_; ++} ++ ++sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) ++{ ++ _irqL irqL; ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&pnetwork->list, &queue->queue); ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct wlan_network *_rtw_dequeue_network(_queue *queue) ++{ ++ _irqL irqL; ++ ++ struct wlan_network *pnetwork; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(queue) == _TRUE) ++ ++ pnetwork = NULL; ++ ++ else ++ { ++ pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pnetwork; ++} ++ ++struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) ++{ ++ _irqL irqL; ++ struct wlan_network *pnetwork; ++ _queue *free_queue = &pmlmepriv->free_bss_pool; ++ _list* plist = NULL; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(free_queue) == _TRUE) { ++ pnetwork=NULL; ++ goto exit; ++ } ++ plist = get_next(&(free_queue->queue)); ++ ++ pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list); ++ ++ rtw_list_delete(&pnetwork->list); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist)); ++ pnetwork->network_type = 0; ++ pnetwork->fixed = _FALSE; ++ pnetwork->last_scanned = rtw_get_current_time(); ++ pnetwork->aid=0; ++ pnetwork->join_res=0; ++ ++ pmlmepriv->num_of_scanned ++; ++ ++exit: ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pnetwork; ++} ++ ++void _rtw_free_network(struct mlme_priv *pmlmepriv ,struct wlan_network *pnetwork, u8 isfreeall) ++{ ++ u32 curr_time, delta_time; ++ u32 lifetime = SCANQUEUE_LIFETIME; ++ _irqL irqL; ++ _queue *free_queue = &(pmlmepriv->free_bss_pool); ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ if (pnetwork->fixed == _TRUE) ++ goto exit; ++ ++ curr_time = rtw_get_current_time(); ++ ++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) ++ lifetime = 1; ++ ++ if(!isfreeall) ++ { ++#ifdef PLATFORM_WINDOWS ++ ++ delta_time = (curr_time -pnetwork->last_scanned)/10; ++ ++ if(delta_time < lifetime*1000000)// unit:usec ++ { ++ goto exit; ++ } ++ ++#endif ++ ++#ifdef PLATFORM_LINUX ++ ++ delta_time = (curr_time -pnetwork->last_scanned)/HZ; ++ ++ if(delta_time < lifetime)// unit:sec ++ { ++ goto exit; ++ } ++ ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++ //i think needs to check again ++ delta_time = (curr_time -pnetwork->last_scanned)/hz; ++ ++ if(delta_time < lifetime)// unit:sec ++ { ++ goto exit; ++ } ++ ++#endif ++ } ++ ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list),&(free_queue->queue)); ++ ++ pmlmepriv->num_of_scanned --; ++ ++ ++ //DBG_871X("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); ++ ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork) ++{ ++ ++ _queue *free_queue = &(pmlmepriv->free_bss_pool); ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ if (pnetwork->fixed == _TRUE) ++ goto exit; ++ ++ //_enter_critical(&free_queue->lock, &irqL); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue)); ++ ++ pmlmepriv->num_of_scanned --; ++ ++ //_exit_critical(&free_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++ return the wlan_network with the matching addr ++ ++ Shall be calle under atomic context... to avoid possible racing condition... ++*/ ++struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) ++{ ++ ++ //_irqL irqL; ++ _list *phead, *plist; ++ struct wlan_network *pnetwork = NULL; ++ u8 zero_addr[ETH_ALEN] = {0,0,0,0,0,0}; ++ ++_func_enter_; ++ ++ if(_rtw_memcmp(zero_addr, addr, ETH_ALEN)){ ++ pnetwork=NULL; ++ goto exit; ++ } ++ ++ //_enter_critical_bh(&scanned_queue->lock, &irqL); ++ ++ phead = get_list_head(scanned_queue); ++ plist = get_next(phead); ++ ++ while (plist != phead) ++ { ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network ,list); ++ ++ if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) ++ break; ++ ++ plist = get_next(plist); ++ } ++ ++ if(plist == phead) ++ pnetwork = NULL; ++ ++ //_exit_critical_bh(&scanned_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return pnetwork; ++ ++} ++ ++ ++void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ struct wlan_network *pnetwork; ++ struct mlme_priv* pmlmepriv = &padapter->mlmepriv; ++ _queue *scanned_queue = &pmlmepriv->scanned_queue; ++ ++_func_enter_; ++ ++ ++ _enter_critical_bh(&scanned_queue->lock, &irqL); ++ ++ phead = get_list_head(scanned_queue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ plist = get_next(plist); ++ ++ _rtw_free_network(pmlmepriv,pnetwork, isfreeall); ++ ++ } ++ ++ _exit_critical_bh(&scanned_queue->lock, &irqL); ++ ++_func_exit_; ++ ++} ++ ++ ++ ++ ++sint rtw_if_up(_adapter *padapter) { ++ ++ sint res; ++_func_enter_; ++ ++ if( padapter->bDriverStopped || padapter->bSurpriseRemoved || ++ (check_fwstate(&padapter->mlmepriv, _FW_LINKED)== _FALSE)){ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ res=_FALSE; ++ } ++ else ++ res= _TRUE; ++ ++_func_exit_; ++ return res; ++} ++ ++ ++void rtw_generate_random_ibss(u8* pibss) ++{ ++ u32 curtime = rtw_get_current_time(); ++ ++_func_enter_; ++ pibss[0] = 0x02; //in ad-hoc mode bit1 must set to 1 ++ pibss[1] = 0x11; ++ pibss[2] = 0x87; ++ pibss[3] = (u8)(curtime & 0xff) ;//p[0]; ++ pibss[4] = (u8)((curtime>>8) & 0xff) ;//p[1]; ++ pibss[5] = (u8)((curtime>>16) & 0xff) ;//p[2]; ++_func_exit_; ++ return; ++} ++ ++u8 *rtw_get_capability_from_ie(u8 *ie) ++{ ++ return (ie + 8 + 2); ++} ++ ++ ++u16 rtw_get_capability(WLAN_BSSID_EX *bss) ++{ ++ u16 val; ++_func_enter_; ++ ++ _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); ++ ++_func_exit_; ++ return le16_to_cpu(val); ++} ++ ++u8 *rtw_get_timestampe_from_ie(u8 *ie) ++{ ++ return (ie + 0); ++} ++ ++u8 *rtw_get_beacon_interval_from_ie(u8 *ie) ++{ ++ return (ie + 8); ++} ++ ++ ++int rtw_init_mlme_priv (_adapter *padapter)//(struct mlme_priv *pmlmepriv) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_init_mlme_priv(padapter);// (pmlmepriv); ++_func_exit_; ++ return res; ++} ++ ++void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_mlme_priv\n")); ++ _rtw_free_mlme_priv (pmlmepriv); ++_func_exit_; ++} ++ ++int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); ++int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_enqueue_network(queue, pnetwork); ++_func_exit_; ++ return res; ++} ++ ++ ++#ifndef PLATFORM_FREEBSD //Baron ++static struct wlan_network *rtw_dequeue_network(_queue *queue) ++{ ++ struct wlan_network *pnetwork; ++_func_enter_; ++ pnetwork = _rtw_dequeue_network(queue); ++_func_exit_; ++ return pnetwork; ++} ++#endif //PLATFORM_FREEBSD ++ ++struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv ); ++struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) ++{ ++ struct wlan_network *pnetwork; ++_func_enter_; ++ pnetwork = _rtw_alloc_network(pmlmepriv); ++_func_exit_; ++ return pnetwork; ++} ++ ++void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall); ++void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)//(struct wlan_network *pnetwork, _queue *free_queue) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); ++ _rtw_free_network(pmlmepriv, pnetwork, is_freeall); ++_func_exit_; ++} ++ ++void rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork ); ++void rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork ) ++{ ++_func_enter_; ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); ++ _rtw_free_network_nolock(pmlmepriv, pnetwork); ++_func_exit_; ++} ++ ++ ++void rtw_free_network_queue(_adapter* dev, u8 isfreeall) ++{ ++_func_enter_; ++ _rtw_free_network_queue(dev, isfreeall); ++_func_exit_; ++} ++ ++/* ++ return the wlan_network with the matching addr ++ ++ Shall be calle under atomic context... to avoid possible racing condition... ++*/ ++struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) ++{ ++ struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); ++ ++ return pnetwork; ++} ++ ++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork) ++{ ++ int ret=_TRUE; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ ++ if ( (psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ ) && ++ ( pnetwork->network.Privacy == 0 ) ) ++ { ++ ret=_FALSE; ++ } ++ else if((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_ ) && ++ ( pnetwork->network.Privacy == 1 ) ) ++ { ++ ret=_FALSE; ++ } ++ else ++ { ++ ret=_TRUE; ++ } ++ ++ return ret; ++ ++} ++ ++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b); ++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) ++{ ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n", ++ // a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength)); ++ return (a->Ssid.SsidLength == b->Ssid.SsidLength) ++ && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength)==_TRUE; ++} ++ ++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) ++{ ++ u16 s_cap, d_cap; ++ ++_func_enter_; ++ ++#ifdef PLATFORM_OS_XP ++ if ( ((uint)dst) <= 0x7fffffff || ++ ((uint)src) <= 0x7fffffff || ++ ((uint)&s_cap) <= 0x7fffffff || ++ ((uint)&d_cap) <= 0x7fffffff) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n@@@@ error address of dst\n")); ++ ++ KeBugCheckEx(0x87110000, (ULONG_PTR)dst, (ULONG_PTR)src,(ULONG_PTR)&s_cap, (ULONG_PTR)&d_cap); ++ ++ return _FALSE; ++ } ++#endif ++ ++ ++ _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2); ++ _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2); ++ ++ ++ s_cap = le16_to_cpu(s_cap); ++ d_cap = le16_to_cpu(d_cap); ++ ++_func_exit_; ++ ++#ifdef CONFIG_P2P ++ if ((feature == 1) && // 1: P2P supported ++ (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE) ++ ) { ++ return _TRUE; ++ } ++#endif ++ ++ return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && ++ // (src->Configuration.DSConfig == dst->Configuration.DSConfig) && ++ ( (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && ++ ( (_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && ++ ((s_cap & WLAN_CAPABILITY_IBSS) == ++ (d_cap & WLAN_CAPABILITY_IBSS)) && ++ ((s_cap & WLAN_CAPABILITY_BSS) == ++ (d_cap & WLAN_CAPABILITY_BSS))); ++ ++} ++ ++struct wlan_network * rtw_get_oldest_wlan_network(_queue *scanned_queue) ++{ ++ _list *plist, *phead; ++ ++ ++ struct wlan_network *pwlan = NULL; ++ struct wlan_network *oldest = NULL; ++_func_enter_; ++ phead = get_list_head(scanned_queue); ++ ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pwlan= LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ if(pwlan->fixed!=_TRUE) ++ { ++ if (oldest == NULL ||time_after(oldest->last_scanned, pwlan->last_scanned)) ++ oldest = pwlan; ++ } ++ ++ plist = get_next(plist); ++ } ++_func_exit_; ++ return oldest; ++ ++} ++ ++void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, ++ _adapter * padapter, bool update_ie) ++{ ++ u8 ss_ori = dst->PhyInfo.SignalStrength; ++ u8 sq_ori = dst->PhyInfo.SignalQuality; ++ long rssi_ori = dst->Rssi; ++ ++ u8 ss_smp = src->PhyInfo.SignalStrength; ++ u8 sq_smp = src->PhyInfo.SignalQuality; ++ long rssi_smp = src->Rssi; ++ ++ u8 ss_final; ++ u8 sq_final; ++ long rssi_final; ++ ++_func_enter_; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ rtw_hal_antdiv_rssi_compared(padapter, dst, src); //this will update src.Rssi, need consider again ++#endif ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 ++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n" ++ , FUNC_ADPT_ARG(padapter) ++ , src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig ++ ,ss_ori, sq_ori, rssi_ori ++ ,ss_smp, sq_smp, rssi_smp ++ ); ++ } ++ #endif ++ ++ /* The rule below is 1/5 for sample value, 4/5 for history value */ ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) { ++ /* Take the recvpriv's value for the connected AP*/ ++ ss_final = padapter->recvpriv.signal_strength; ++ sq_final = padapter->recvpriv.signal_qual; ++ /* the rssi value here is undecorated, and will be used for antenna diversity */ ++ if(sq_smp != 101) /* from the right channel */ ++ rssi_final = (src->Rssi+dst->Rssi*4)/5; ++ else ++ rssi_final = rssi_ori; ++ } ++ else { ++ if(sq_smp != 101) { /* from the right channel */ ++ ss_final = ((u32)(src->PhyInfo.SignalStrength)+(u32)(dst->PhyInfo.SignalStrength)*4)/5; ++ sq_final = ((u32)(src->PhyInfo.SignalQuality)+(u32)(dst->PhyInfo.SignalQuality)*4)/5; ++ rssi_final = (src->Rssi+dst->Rssi*4)/5; ++ } else { ++ /* bss info not receving from the right channel, use the original RX signal infos */ ++ ss_final = dst->PhyInfo.SignalStrength; ++ sq_final = dst->PhyInfo.SignalQuality; ++ rssi_final = dst->Rssi; ++ } ++ ++ } ++ ++ if (update_ie) { ++ dst->Reserved[0] = src->Reserved[0]; ++ dst->Reserved[1] = src->Reserved[1]; ++ _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src)); ++ } ++ ++ dst->PhyInfo.SignalStrength = ss_final; ++ dst->PhyInfo.SignalQuality = sq_final; ++ dst->Rssi = rssi_final; ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 ++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n" ++ , FUNC_ADPT_ARG(padapter) ++ , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi); ++ } ++ #endif ++ ++#if 0 // old codes, may be useful one day... ++// DBG_871X("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) ++ { ++ ++ //DBG_871X("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); ++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; ++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; ++ padapter->recvpriv.signal_qual_data.total_val -= last_evm; ++ } ++ padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi); ++ ++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi); ++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ padapter->recvpriv.signal_qual_data.index = 0; ++ ++ //DBG_871X("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); ++ ++ // <1> Showed on UI for user,in percentage. ++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; ++ padapter->recvpriv.signal=(u8)tmpVal;//Link quality ++ ++ src->Rssi= translate_percentage_to_dbm(padapter->recvpriv.signal) ; ++ } ++ else{ ++// DBG_871X("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); ++ src->Rssi=(src->Rssi +dst->Rssi)/2;//dBM ++ } ++ ++// DBG_871X("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); ++ ++#endif ++ ++_func_exit_; ++} ++ ++static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) ++{ ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++_func_enter_; ++ ++#ifdef PLATFORM_OS_XP ++ if ((unsigned long)(&(pmlmepriv->cur_network.network)) < 0x7ffffff) ++ { ++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)(&(pmlmepriv->cur_network.network)), 0, 0,0); ++ } ++#endif ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n"); ++ ++ //if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) ++ { ++ update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter, _TRUE); ++ rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), ++ pmlmepriv->cur_network.network.IELength); ++ } ++ } ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++ ++Caller must hold pmlmepriv->lock first. ++ ++ ++*/ ++void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ ULONG bssid_ex_sz; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(adapter->wdinfo); ++#endif ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *oldest = NULL; ++ int target_find = 0; ++ u8 feature = 0; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++#ifdef CONFIG_P2P ++ if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ feature = 1; // p2p enable ++#endif ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ if ((unsigned long)(pnetwork) < 0x7ffffff) ++ { ++#ifdef PLATFORM_OS_XP ++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)pnetwork, 0, 0,0); ++#endif ++ } ++ ++ if (is_same_network(&(pnetwork->network), target, feature)) { ++ target_find = 1; ++ break; ++ } ++ ++ if ((oldest == ((struct wlan_network *)0)) || ++ time_after(oldest->last_scanned, pnetwork->last_scanned)) ++ oldest = pnetwork; ++ ++ plist = get_next(plist); ++ ++ } ++ ++ ++ /* If we didn't find a match, then get a new network slot to initialize ++ * with this beacon's information */ ++ //if (rtw_end_of_queue_search(phead,plist)== _TRUE) { ++ if (!target_find) { ++ ++ if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { ++ /* If there are no more slots, expire the oldest */ ++ //list_del_init(&oldest->list); ++ pnetwork = oldest; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna;//optimum_antenna=>For antenna diversity ++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna)); ++#endif ++ _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); ++ //pnetwork->last_scanned = rtw_get_current_time(); ++ // variable initialize ++ pnetwork->fixed = _FALSE; ++ pnetwork->last_scanned = rtw_get_current_time(); ++ ++ pnetwork->network_type = 0; ++ pnetwork->aid=0; ++ pnetwork->join_res=0; ++ ++ /* bss info not receving from the right channel */ ++ if (pnetwork->network.PhyInfo.SignalQuality == 101) ++ pnetwork->network.PhyInfo.SignalQuality = 0; ++ } ++ else { ++ /* Otherwise just pull from the free list */ ++ ++ pnetwork = rtw_alloc_network(pmlmepriv); // will update scan_time ++ ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n\nsomething wrong here\n\n\n")); ++ goto exit; ++ } ++ ++ bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); ++ target->Length = bssid_ex_sz; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna; ++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna)); ++#endif ++ _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz ); ++ ++ pnetwork->last_scanned = rtw_get_current_time(); ++ ++ /* bss info not receving from the right channel */ ++ if (pnetwork->network.PhyInfo.SignalQuality == 101) ++ pnetwork->network.PhyInfo.SignalQuality = 0; ++ ++ rtw_list_insert_tail(&(pnetwork->list),&(queue->queue)); ++ ++ } ++ } ++ else { ++ /* we have an entry and we are going to update it. But this entry may ++ * be already expired. In this case we do the same as we found a new ++ * net and call the new_net handler ++ */ ++ bool update_ie = _TRUE; ++ ++ pnetwork->last_scanned = rtw_get_current_time(); ++ ++ //target.Reserved[0]==1, means that scaned network is a bcn frame. ++ // probe resp(3) > beacon(1) > probe req(2) ++ if ((target->Reserved[0] != 2) && ++ (target->Reserved[0] >= pnetwork->network.Reserved[0]) ++ ) { ++ update_ie = _TRUE; ++ } ++ else { ++ update_ie = _FALSE; ++ } ++ ++ update_network(&(pnetwork->network), target,adapter, update_ie); ++ } ++ ++exit: ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++} ++ ++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); ++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); ++ //_queue *queue = &(pmlmepriv->scanned_queue); ++ ++_func_enter_; ++ ++ //_enter_critical_bh(&queue->lock, &irqL); ++ ++ #if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) ++ rtw_WLAN_BSSID_EX_remove_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); ++ #endif ++ ++ update_current_network(adapter, pnetwork); ++ ++ rtw_update_scanned_network(adapter, pnetwork); ++ ++ //_exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++} ++ ++//select the desired network based on the capability of the (i)bss. ++// check items: (1) security ++// (2) network_type ++// (3) WMM ++// (4) HT ++// (5) others ++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); ++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) ++{ ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u32 desired_encmode; ++ u32 privacy; ++ ++ //u8 wps_ie[512]; ++ uint wps_ielen; ++ ++ int bselected = _TRUE; ++ ++ desired_encmode = psecuritypriv->ndisencryptstatus; ++ privacy = pnetwork->network.Privacy; ++ ++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) ++ { ++ if(rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen)!=NULL) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ } ++ if (adapter->registrypriv.wifi_spec == 1) //for correct flow of 8021X to do.... ++ { ++ u8 *p=NULL; ++ uint ie_len=0; ++ ++ if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0)) ++ bselected = _FALSE; ++ ++ if ( psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { ++ p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); ++ if (p && ie_len>0) { ++ bselected = _TRUE; ++ } else { ++ bselected = _FALSE; ++ } ++ } ++ } ++ ++ ++ if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) { ++ DBG_871X("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy); ++ bselected = _FALSE; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) ++ bselected = _FALSE; ++ } ++ ++ ++ return bselected; ++} ++ ++/* TODO: Perry : For Power Management */ ++void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("receive atimdone_evet\n")); ++_func_exit_; ++ return; ++} ++ ++ ++void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ u32 len; ++ WLAN_BSSID_EX *pnetwork; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++_func_enter_; ++ ++ pnetwork = (WLAN_BSSID_EX *)pbuf; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid)); ++ ++#ifdef CONFIG_RTL8712 ++ //endian_convert ++ pnetwork->Length = le32_to_cpu(pnetwork->Length); ++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength); ++ pnetwork->Privacy =le32_to_cpu( pnetwork->Privacy); ++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi); ++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse); ++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow); ++ pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod); ++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig); ++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime); ++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern); ++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet); ++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length); ++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length); ++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode); ++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength); ++#endif ++ ++ len = get_WLAN_BSSID_EX_sz(pnetwork); ++ if(len > (sizeof(WLAN_BSSID_EX))) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n ****rtw_survey_event_callback: return a wrong bss ***\n")); ++ return; ++ } ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ // update IBSS_network 's timestamp ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n"); ++ if(_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) ++ { ++ struct wlan_network* ibss_wlan = NULL; ++ _irqL irqL; ++ ++ _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); ++ if(ibss_wlan) ++ { ++ _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto exit; ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ } ++ } ++ ++ // lock pmlmepriv->lock when you accessing network_q ++ if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) ++ { ++ if( pnetwork->Ssid.Ssid[0] == 0 ) ++ { ++ pnetwork->Ssid.SsidLength = 0; ++ } ++ rtw_add_network(adapter, pnetwork); ++ } ++ ++exit: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++_func_exit_; ++ ++ return; ++} ++ ++ ++ ++void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ u8 timer_cancelled = _FALSE; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++#ifdef CONFIG_MLME_EXT ++ ++ mlmeext_surveydone_event_callback(adapter); ++ ++#endif ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ if(pmlmepriv->wps_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_req_ie_len; ++ pmlmepriv->wps_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); ++ pmlmepriv->wps_probe_req_ie = NULL; ++ } ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv))); ++ ++ if (check_fwstate(pmlmepriv,_FW_UNDER_SURVEY)) ++ { ++ //u8 timer_cancelled; ++ ++ timer_cancelled = _TRUE; ++ //_cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++ else { ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("nic status =%x, survey done event comes too late!\n", get_fwstate(pmlmepriv))); ++ } ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if(timer_cancelled) ++ _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled); ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&adapter->recvpriv); ++ #endif ++ ++ if(pmlmepriv->to_join == _TRUE) ++ { ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) ) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)==_FALSE) ++ { ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ if(rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS) ++ { ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT ); ++ } ++ else ++ { ++ WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); ++ u8 *pibss = adapter->registrypriv.dev_network.MacAddress; ++ ++ //pmlmepriv->fw_state ^= _FW_UNDER_SURVEY;//because don't set assoc_timer ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("switching to adhoc master\n")); ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(adapter); ++ rtw_generate_random_ibss(pibss); ++ ++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; ++ ++ if(rtw_createbss_cmd(adapter)!=_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error=>rtw_createbss_cmd status FAIL\n")); ++ } ++ ++ pmlmepriv->to_join = _FALSE; ++ } ++ } ++ } ++ else ++ { ++ int s_ret; ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ pmlmepriv->to_join = _FALSE; ++ if(_SUCCESS == (s_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))) ++ { ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ } ++ else if(s_ret == 2)//there is no need to wait for join ++ { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ DBG_871X("try_to_join, but select scanning queue fail, to_roaming:%d\n", rtw_to_roaming(adapter)); ++ #ifdef CONFIG_LAYER2_ROAMING ++ if (rtw_to_roaming(adapter) != 0) { ++ if( --pmlmepriv->to_roaming == 0 ++ || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0) ++ ) { ++ rtw_set_roaming(adapter, 0); ++#ifdef CONFIG_INTEL_WIDI ++ if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) ++ { ++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); ++ intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL); ++ DBG_871X("change to widi listen\n"); ++ } ++#endif // CONFIG_INTEL_WIDI ++ rtw_free_assoc_resources(adapter, 1); ++ rtw_indicate_disconnect(adapter); ++ } else { ++ pmlmepriv->to_join = _TRUE; ++ } ++ } ++ else ++ #endif ++ { ++ rtw_indicate_disconnect(adapter); ++ } ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ } ++ } ++ } ++ ++ indicate_wx_scan_complete_event(adapter); ++ //DBG_871X("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++#ifdef CONFIG_P2P_PS ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); ++ } ++#endif // CONFIG_P2P_PS ++ ++ rtw_os_xmit_schedule(adapter); ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_os_xmit_schedule(adapter->pbuddy_adapter); ++#endif ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_resume_xmit(adapter); ++#endif ++ ++#ifdef CONFIG_DRVEXT_MODULE_WSC ++ drvext_surveydone_callback(&adapter->drvextpriv); ++#endif ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ if(pmlmeext->sitesurvey_res.bss_cnt == 0){ ++ //rtw_hal_sreset_reset(adapter); ++ } ++ } ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_surveydone_event_callback(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++_func_exit_; ++ ++} ++ ++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++} ++ ++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++} ++ ++static void free_scanqueue(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL, irqL0; ++ _queue *free_queue = &pmlmepriv->free_bss_pool; ++ _queue *scan_queue = &pmlmepriv->scanned_queue; ++ _list *plist, *phead, *ptemp; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n")); ++ _enter_critical_bh(&scan_queue->lock, &irqL0); ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ phead = get_list_head(scan_queue); ++ plist = get_next(phead); ++ ++ while (plist != phead) ++ { ++ ptemp = get_next(plist); ++ rtw_list_delete(plist); ++ rtw_list_insert_tail(plist, &free_queue->queue); ++ plist =ptemp; ++ pmlmepriv->num_of_scanned --; ++ } ++ ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ _exit_critical_bh(&scan_queue->lock, &irqL0); ++ ++_func_exit_; ++} ++ ++/* ++*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) ++{ ++ _irqL irqL; ++ struct wlan_network* pwlan = NULL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++#endif //CONFIG_TDLS ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n")); ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("tgt_network->network.MacAddress="MAC_FMT" ssid=%s\n", ++ MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid)); ++ ++ if(check_fwstate( pmlmepriv, WIFI_STATION_STATE|WIFI_AP_STATE)) ++ { ++ struct sta_info* psta; ++ ++ psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->setup_state != TDLS_STATE_NONE) ++ { ++ rtw_tdls_cmd(adapter, myid(&(adapter->eeprompriv)), TDLS_RS_RCR); ++ rtw_reset_tdls_info(adapter); ++ rtw_free_all_stainfo(adapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ } ++ else ++#endif //CONFIG_TDLS ++ { ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ } ++ ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ } ++ ++ if(check_fwstate( pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)) ++ { ++ struct sta_info* psta; ++ ++ rtw_free_all_stainfo(adapter); ++ ++ psta = rtw_get_bcmc_stainfo(adapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ rtw_init_bcmc_stainfo(adapter); ++ } ++ ++ if(lock_scanned_queue) ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if(pwlan) ++ { ++ pwlan->fixed = _FALSE; ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) ++ { ++ u32 p2p_ielen=0; ++ u8 *p2p_ie; ++ //u16 capability; ++ u8 *pcap = NULL; ++ u32 capability_len=0; ++ ++ //DBG_871X("free disconnecting network\n"); ++ //rtw_free_network_nolock(pmlmepriv, pwlan); ++ ++ if((p2p_ie=rtw_get_p2p_ie(pwlan->network.IEs+_FIXED_IE_LENGTH_, pwlan->network.IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen))) ++ { ++ pcap = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, NULL, &capability_len); ++ if(pcap && capability_len==2) ++ { ++ u16 cap = *(u16*)pcap ; ++ *(u16*)pcap = cap&0x00ff;//clear group capability when free this network ++ } ++ } ++ ++ rtw_set_scan_deny(adapter, 2000); ++ //rtw_clear_scan_deny(adapter); ++ } ++#endif //CONFIG_P2P ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_assoc_resources : pwlan== NULL \n\n")); ++ } ++ ++ ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count== 1)) ++ /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) ++ { ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ ++ if(lock_scanned_queue) ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ adapter->securitypriv.key_mask = 0; ++ ++_func_exit_; ++ ++} ++ ++/* ++*rtw_indicate_connect: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_indicate_connect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n")); ++ ++ pmlmepriv->to_join = _FALSE; ++ ++ if(!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) ++ { ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ rtw_hal_set_hwreg(padapter, HW_VAR_ANTENNA_DIVERSITY_LINK, 0); ++#endif ++ ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ ++ rtw_led_control(padapter, LED_CTL_LINK); ++ ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ if(padapter->drvextpriv.enable_wpa) ++ { ++ indicate_l2_connect(padapter); ++ } ++ else ++#endif ++ { ++ rtw_os_indicate_connect(padapter); ++ } ++ ++ } ++ ++ rtw_set_roaming(padapter, 0); ++#ifdef CONFIG_INTEL_WIDI ++ if(padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) ++ { ++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); ++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL); ++ DBG_871X("change to widi listen\n"); ++ } ++#endif // CONFIG_INTEL_WIDI ++ ++ rtw_set_scan_deny(padapter, 3000); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_indicate_disconnect( _adapter *padapter ) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n")); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING|WIFI_UNDER_WPS); ++ ++ //DBG_871X("clear wps when %s\n", __func__); ++ ++ if(rtw_to_roaming(padapter) > 0) ++ _clr_fwstate_(pmlmepriv, _FW_LINKED); ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ psta = rtw_get_stainfo(pstapriv,cur_network->MacAddress); ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ rtw_wapi_return_one_sta_info(padapter, psta->hwaddr); ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || ++ check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) ++ { ++ rtw_wapi_return_all_sta_info(padapter); ++ } ++#endif ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED) ++ || (rtw_to_roaming(padapter) <= 0) ++ ) ++ { ++ rtw_os_indicate_disconnect(padapter); ++ ++ //set ips_deny_time to avoid enter IPS before LPS leave ++ adapter_to_pwrctl(padapter)->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(3000); ++ ++ _clr_fwstate_(pmlmepriv, _FW_LINKED); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ rtw_clear_scan_deny(padapter); ++ ++ } ++ ++#ifdef CONFIG_P2P_PS ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++#endif // CONFIG_P2P_PS ++ ++#ifdef CONFIG_LPS ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1); ++#endif ++ ++_func_exit_; ++} ++ ++inline void rtw_indicate_scan_done( _adapter *padapter, bool aborted) ++{ ++ rtw_os_indicate_scan_done(padapter, aborted); ++} ++ ++void rtw_scan_abort(_adapter *adapter) ++{ ++ u32 cnt=0; ++ u32 start; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); ++ ++ start = rtw_get_current_time(); ++ pmlmeext->scan_abort = _TRUE; ++ while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) ++ && rtw_get_passing_time_ms(start) <= 200) { ++ ++ if (adapter->bDriverStopped || adapter->bSurpriseRemoved) ++ break; ++ ++ DBG_871X(FUNC_NDEV_FMT"fw_state=_FW_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev)); ++ rtw_msleep_os(20); ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { ++ if (!adapter->bDriverStopped && !adapter->bSurpriseRemoved) ++ DBG_871X(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev)); ++ #ifdef CONFIG_PLATFORM_MSTAR ++ //_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ set_survey_timer(pmlmeext, 0); ++ _set_timer(&pmlmepriv->scan_to_timer, 50); ++ #endif ++ rtw_indicate_scan_done(adapter, _TRUE); ++ } ++ pmlmeext->scan_abort = _FALSE; ++} ++ ++static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) ++{ ++ int i; ++ struct sta_info *bmc_sta, *psta=NULL; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress); ++ if(psta==NULL) { ++ psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress); ++ } ++ ++ if(psta) //update ptarget_sta ++ { ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ psta->aid = pnetwork->join_res; ++#ifdef CONFIG_CONCURRENT_MODE ++ ++ if(PRIMARY_ADAPTER == padapter->adapter_type) ++ psta->mac_id=0; ++ else ++ psta->mac_id=2; ++#else ++ psta->mac_id=0; ++#endif ++ ++ //sta mode ++ rtw_hal_set_odm_var(padapter,HAL_ODM_STA_INFO,psta,_TRUE); ++ ++ //security related ++ if(padapter->securitypriv.dot11AuthAlgrthm== dot11AuthAlgrthm_8021X) ++ { ++ padapter->securitypriv.binstallGrpkey=_FALSE; ++ padapter->securitypriv.busetkipkey=_FALSE; ++ padapter->securitypriv.bgrpkey_handshake=_FALSE; ++ ++ psta->ieee8021x_blocked=_TRUE; ++ psta->dot118021XPrivacy=padapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof (union Keytype)); ++ ++ _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof (union Keytype)); ++ _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof (union Keytype)); ++ ++ _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof (union pn48)); ++#ifdef CONFIG_IEEE80211W ++ _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof (union pn48)); ++#endif //CONFIG_IEEE80211W ++ _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof (union pn48)); ++ } ++ ++ // Commented by Albert 2012/07/21 ++ // When doing the WPS, the wps_ie_len won't equal to 0 ++ // And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. ++ if ( padapter->securitypriv.wps_ie_len != 0 ) ++ { ++ psta->ieee8021x_blocked=_TRUE; ++ padapter->securitypriv.wps_ie_len = 0; ++ } ++ ++ ++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info ++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff ++ //todo: check if AP can send A-MPDU packets ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ ++ ++ bmc_sta = rtw_get_bcmc_stainfo(padapter); ++ if(bmc_sta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++ ++ ++ //misc. ++ update_sta_info(padapter, psta); ++ ++ } ++ ++ return psta; ++ ++} ++ ++//pnetwork : returns from rtw_joinbss_event_callback ++//ptarget_wlan: found from scanned_queue ++static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\nfw_state:%x, BSSID:"MAC_FMT"\n" ++ ,get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress))); ++ ++ ++ // why not use ptarget_wlan?? ++ _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length); ++ // some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs ++ cur_network->network.IELength = ptarget_wlan->network.IELength; ++ _rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ); ++ ++ cur_network->aid = pnetwork->join_res; ++ ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; ++ padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; ++ //the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) ++ padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 ++ DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" ++ "\n" ++ , FUNC_ADPT_ARG(padapter) ++ , padapter->recvpriv.signal_strength ++ , padapter->recvpriv.rssi ++ , padapter->recvpriv.signal_qual ++ ); ++ #endif ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ ++ //update fw_state //will clr _FW_UNDER_LINKING here indirectly ++ switch(pnetwork->network.InfrastructureMode) ++ { ++ case Ndis802_11Infrastructure: ++ ++ if(pmlmepriv->fw_state&WIFI_UNDER_WPS) ++ pmlmepriv->fw_state = WIFI_STATION_STATE|WIFI_UNDER_WPS; ++ else ++ pmlmepriv->fw_state = WIFI_STATION_STATE; ++ ++ break; ++ case Ndis802_11IBSS: ++ pmlmepriv->fw_state = WIFI_ADHOC_STATE; ++ break; ++ default: ++ pmlmepriv->fw_state = WIFI_NULL_STATE; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Invalid network_mode\n")); ++ break; ++ } ++ ++ rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), ++ (cur_network->network.IELength)); ++ ++#ifdef CONFIG_80211N_HT ++ rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength); ++#endif ++ ++ ++} ++ ++//Notes: the fucntion could be > passive_level (the same context as Rx tasklet) ++//pnetwork : returns from rtw_joinbss_event_callback ++//ptarget_wlan: found from scanned_queue ++//if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist. ++//if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist. ++//if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL). ++// ++//#define REJOIN ++void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL,irqL2; ++ static u8 retry=0; ++ u8 timer_cancelled; ++ struct sta_info *ptarget_sta= NULL, *pcur_sta = NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL; ++ unsigned int the_same_macaddr = _FALSE; ++ ++_func_enter_; ++ ++#ifdef CONFIG_RTL8712 ++ //endian_convert ++ pnetwork->join_res = le32_to_cpu(pnetwork->join_res); ++ pnetwork->network_type = le32_to_cpu(pnetwork->network_type); ++ pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length); ++ pnetwork->network.Ssid.SsidLength = le32_to_cpu(pnetwork->network.Ssid.SsidLength); ++ pnetwork->network.Privacy =le32_to_cpu( pnetwork->network.Privacy); ++ pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi); ++ pnetwork->network.NetworkTypeInUse =le32_to_cpu(pnetwork->network.NetworkTypeInUse) ; ++ pnetwork->network.Configuration.ATIMWindow = le32_to_cpu(pnetwork->network.Configuration.ATIMWindow); ++ pnetwork->network.Configuration.BeaconPeriod = le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod); ++ pnetwork->network.Configuration.DSConfig = le32_to_cpu(pnetwork->network.Configuration.DSConfig); ++ pnetwork->network.Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime); ++ pnetwork->network.Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern); ++ pnetwork->network.Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet); ++ pnetwork->network.Configuration.FHConfig.Length=le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length); ++ pnetwork->network.Configuration.Length = le32_to_cpu(pnetwork->network.Configuration.Length); ++ pnetwork->network.InfrastructureMode = le32_to_cpu(pnetwork->network.InfrastructureMode); ++ pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength ); ++#endif ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("joinbss event call back received with res=%d\n", pnetwork->join_res)); ++ ++ rtw_get_encrypt_decrypt_from_registrypriv(adapter); ++ ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ joinbss event call back for Any SSid\n")); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN); ++ ++ pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network); ++ if(pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n")); ++ goto ignore_joinbss_callback; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n rtw_joinbss_event_callback !! _enter_critical \n")); ++ ++ if(pnetwork->join_res > 0) ++ { ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ retry = 0; ++ if (check_fwstate(pmlmepriv,_FW_UNDER_LINKING) ) ++ { ++ //s1. find ptarget_wlan ++ if(check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ if(the_same_macaddr == _TRUE) ++ { ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ } ++ else ++ { ++ pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ if(pcur_wlan) pcur_wlan->fixed = _FALSE; ++ ++ pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(pcur_sta){ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ rtw_free_stainfo(adapter, pcur_sta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ } ++ ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ } ++ } ++ ++ } ++ else ++ { ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ } ++ } ++ ++ //s2. update cur_network ++ if(ptarget_wlan) ++ { ++ rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't find ptarget_wlan when joinbss_event callback\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ ++ ++ //s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork); ++ if(ptarget_sta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't update stainfo when joinbss_event callback\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ } ++ ++ //s4. indicate connect ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ pmlmepriv->cur_network_scanned = ptarget_wlan; ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ //adhoc mode will rtw_indicate_connect when rtw_stassoc_event_callback ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("adhoc mode, fw_state:%x", get_fwstate(pmlmepriv))); ++ } ++ ++ ++ //s5. Cancle assoc_timer ++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("Cancle assoc_timer \n")); ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ } ++ else if(pnetwork->join_res == -4) ++ { ++ rtw_reset_securitypriv(adapter); ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ ++ //rtw_free_assoc_resources(adapter, 1); ++ ++ if((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv))); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ } ++ ++ } ++ else //if join_res < 0 (join fails), then try again ++ { ++ ++ #ifdef REJOIN ++ res = _FAIL; ++ if(retry < 2) { ++ res = rtw_select_and_join_from_scanned_queue(pmlmepriv); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_select_and_join_from_scanned_queue again! res:%d\n",res)); ++ } ++ ++ if(res == _SUCCESS) ++ { ++ //extend time of assoc_timer ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ retry++; ++ } ++ else if(res == 2)//there is no need to wait for join ++ { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Set Assoc_Timer = 1; can't find match ssid in scanned_q \n")); ++ #endif ++ ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ //rtw_free_assoc_resources(adapter, 1); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ #ifdef REJOIN ++ retry = 0; ++ } ++ #endif ++ } ++ ++ignore_joinbss_callback: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ _func_exit_; ++} ++ ++void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf; ++ ++_func_enter_; ++ ++ mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); ++ ++ rtw_os_xmit_schedule(adapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_os_xmit_schedule(adapter->pbuddy_adapter); ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_resume_xmit(adapter); ++#endif ++ ++_func_exit_; ++} ++ ++u8 search_max_mac_id(_adapter *padapter) ++{ ++ u8 mac_id, aid; ++#if (RATE_ADAPTIVE_SUPPORT==1) //for 88E RA ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)){ ++ ++ for (aid = (pstapriv->max_num_sta); aid > 0; aid--) ++ { ++ if (pstapriv->sta_aid[aid-1] != NULL) ++ break; ++ } ++/* ++ for (mac_id = (pstapriv->max_num_sta-1); mac_id >= 0; mac_id--) ++ { ++ if (pstapriv->sta_aid[mac_id] != NULL) ++ break; ++ } ++*/ ++ mac_id = aid + 1; ++ } ++ else ++#endif ++ {//adhoc id = 31~2 ++ for (mac_id = (NUM_STA-1); mac_id >= IBSS_START_MAC_ID ; mac_id--) ++ { ++ if (pmlmeinfo->FW_sta_info[mac_id].status == 1) ++ { ++ break; ++ } ++ } ++ } ++#endif ++ return mac_id; ++ ++} ++ ++//FOR STA, AP ,AD-HOC mode ++void rtw_sta_media_status_rpt(_adapter *adapter,struct sta_info *psta, u32 mstatus) ++{ ++ u16 media_status_rpt; ++ ++ if(psta==NULL) return; ++ ++ #if (RATE_ADAPTIVE_SUPPORT==1) //for 88E RA ++ { ++ u8 macid = search_max_mac_id(adapter); ++ rtw_hal_set_hwreg(adapter,HW_VAR_TX_RPT_MAX_MACID, (u8*)&macid); ++ } ++ #endif ++ media_status_rpt = (u16)((psta->mac_id<<8)|mstatus); // MACID|OPMODE:1 connect ++ rtw_hal_set_hwreg(adapter,HW_VAR_H2C_MEDIA_STATUS_RPT,(u8 *)&media_status_rpt); ++} ++ ++void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ struct sta_info *psta; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct stassoc_event *pstassoc = (struct stassoc_event*)pbuf; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wlan_network *ptarget_wlan = NULL; ++ ++_func_enter_; ++ ++ if(rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE) ++ return; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if(psta) ++ { ++ u8 *passoc_req = NULL; ++ u32 assoc_req_len = 0; ++ ++ rtw_sta_media_status_rpt(adapter, psta, 1); ++ ++#ifndef CONFIG_AUTO_AP_MODE ++ ++ ap_sta_info_defer_update(adapter, psta); ++ ++ //report to upper layer ++ DBG_871X("indicate_sta_assoc_event to upper layer - hostapd\n"); ++#ifdef CONFIG_IOCTL_CFG80211 ++ _enter_critical_bh(&psta->lock, &irqL); ++ if(psta->passoc_req && psta->assoc_req_len>0) ++ { ++ passoc_req = rtw_zmalloc(psta->assoc_req_len); ++ if(passoc_req) ++ { ++ assoc_req_len = psta->assoc_req_len; ++ _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); ++ ++ rtw_mfree(psta->passoc_req , psta->assoc_req_len); ++ psta->passoc_req = NULL; ++ psta->assoc_req_len = 0; ++ } ++ } ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ if(passoc_req && assoc_req_len>0) ++ { ++ rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); ++ ++ rtw_mfree(passoc_req, assoc_req_len); ++ } ++#else //!CONFIG_IOCTL_CFG80211 ++ rtw_indicate_sta_assoc_event(adapter, psta); ++#endif //!CONFIG_IOCTL_CFG80211 ++#endif //!CONFIG_AUTO_AP_MODE ++ } ++ goto exit; ++ } ++#endif //defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ ++ //for AD-HOC mode ++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if( psta != NULL) ++ { ++ //the sta have been in sta_info_queue => do nothing ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error: rtw_stassoc_event_callback: sta has been in sta_hash_queue \n")); ++ ++ goto exit; //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY) ++ } ++ ++ psta = rtw_alloc_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if (psta == NULL) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't alloc sta_info when rtw_stassoc_event_callback\n")); ++ goto exit; ++ } ++ ++ //to do : init sta_info variable ++ psta->qos_option = 0; ++ psta->mac_id = (uint)pstassoc->cam_id; ++ //psta->aid = (uint)pstassoc->cam_id; ++ DBG_871X("%s\n",__FUNCTION__); ++ //for ad-hoc mode ++ rtw_hal_set_odm_var(adapter,HAL_ODM_STA_INFO,psta,_TRUE); ++ ++ rtw_sta_media_status_rpt(adapter, psta, 1); ++ ++ if(adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) ++ psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) ++ { ++ if(adapter->stapriv.asoc_sta_count== 2) ++ { ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ pmlmepriv->cur_network_scanned = ptarget_wlan; ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // a sta + bc/mc_stainfo (not Ibss_stainfo) ++ rtw_indicate_connect(adapter); ++ } ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ mlmeext_sta_add_event_callback(adapter, psta); ++ ++#ifdef CONFIG_RTL8711 ++ //submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta ++ rtw_setstakey_cmd(adapter, (unsigned char*)psta, _FALSE, _TRUE); ++#endif ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL,irqL2; ++ int mac_id=-1; ++ struct sta_info *psta; ++ struct wlan_network* pwlan = NULL; ++ WLAN_BSSID_EX *pdev_network=NULL; ++ u8* pibss = NULL; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct stadel_event *pstadel = (struct stadel_event*)pbuf; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network); ++ ++_func_enter_; ++ ++ psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); ++ if(psta) ++ mac_id = psta->mac_id; ++ else ++ mac_id = pstadel->mac_id; ++ ++ DBG_871X("%s(mac_id=%d)=" MAC_FMT "\n", __func__, mac_id, MAC_ARG(pstadel->macaddr)); ++ ++ if(mac_id>=0){ ++ u16 media_status; ++ media_status = (mac_id<<8)|0; // MACID|OPMODE:0 means disconnect ++ //for STA,AP,ADHOC mode, report disconnect stauts to FW ++ rtw_hal_set_hwreg(adapter, HW_VAR_H2C_MEDIA_STATUS_RPT, (u8 *)&media_status); ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++#ifdef CONFIG_IOCTL_CFG80211 ++ #ifdef COMPAT_KERNEL_RELEASE ++ ++ #elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16*)pstadel->rsvd); ++ #endif //(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ return; ++ } ++ ++ ++ mlmeext_sta_del_event_callback(adapter); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL2); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) ++ { ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(adapter->registrypriv.wifi_spec==1) ++ rtw_set_roaming(adapter, 0); /* don't roam */ ++ else if (rtw_to_roaming(adapter) > 0) ++ pmlmepriv->to_roaming--; /* this stadel_event is caused by roaming, decrease to_roaming */ ++ else if (rtw_to_roaming(adapter) == 0) ++ rtw_set_roaming(adapter, adapter->registrypriv.max_roaming_times); ++#ifdef CONFIG_INTEL_WIDI ++ if(adapter->mlmepriv.widi_state != INTEL_WIDI_STATE_CONNECTED) ++#endif // CONFIG_INTEL_WIDI ++ if(*((unsigned short *)(pstadel->rsvd)) != WLAN_REASON_EXPIRATION_CHK) ++ rtw_set_roaming(adapter, 0); /* don't roam */ ++ #endif ++ ++ rtw_free_uc_swdec_pending_queue(adapter); ++ ++ rtw_free_assoc_resources(adapter, 1); ++ rtw_indicate_disconnect(adapter); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // remove the network entry in scanned_queue ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if (pwlan) { ++ pwlan->fixed = _FALSE; ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ _rtw_roaming(adapter, tgt_network); ++ #else ++#ifdef CONFIG_INTEL_WIDI ++ process_intel_widi_disconnect(adapter, 1); ++#endif // CONFIG_INTEL_WIDI ++ #endif //CONFIG_LAYER2_ROAMING ++ ++ } ++ ++ if ( check_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE) || ++ check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) ++ { ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ if(adapter->stapriv.asoc_sta_count== 1) //a sta + bc/mc_stainfo (not Ibss_stainfo) ++ { ++ //rtw_indicate_disconnect(adapter);//removed@20091105 ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ //free old ibss network ++ //pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if(pwlan) ++ { ++ pwlan->fixed = _FALSE; ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ //re-create ibss ++ pdev_network = &(adapter->registrypriv.dev_network); ++ pibss = adapter->registrypriv.dev_network.MacAddress; ++ ++ _rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network)); ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(adapter); ++ ++ rtw_generate_random_ibss(pibss); ++ ++ if(check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) ++ { ++ set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ ++ if(rtw_createbss_cmd(adapter)!=_SUCCESS) ++ { ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>stadel_event_callback: rtw_createbss_cmd status FAIL*** \n ")); ++ ++ } ++ ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL2); ++ ++_func_exit_; ++ ++} ++ ++ ++void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf) ++{ ++#ifdef CONFIG_LPS_LCLK ++ struct reportpwrstate_parm *preportpwrstate; ++#endif ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("+rtw_cpwm_event_callback !!!\n")); ++#ifdef CONFIG_LPS_LCLK ++ preportpwrstate = (struct reportpwrstate_parm*)pbuf; ++ preportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80); ++ cpwm_int_hdl(padapter, preportpwrstate); ++#endif ++ ++_func_exit_; ++ ++} ++ ++/* ++* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss ++* @adapter: pointer to _adapter structure ++*/ ++void _rtw_join_timeout_handler (_adapter *adapter) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++#ifdef CONFIG_LAYER2_ROAMING ++ int do_join_r; ++#endif //CONFIG_LAYER2_ROAMING ++ ++#if 0 ++ if (adapter->bDriverStopped == _TRUE){ ++ _rtw_up_sema(&pmlmepriv->assoc_terminate); ++ return; ++ } ++#endif ++ ++_func_enter_; ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_lock(NULL); ++ if (callout_pending(&adapter->mlmepriv.assoc_timer.callout)) { ++ /* callout was reset */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ if (!callout_active(&adapter->mlmepriv.assoc_timer.callout)) { ++ /* callout was stopped */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ callout_deactivate(&adapter->mlmepriv.assoc_timer.callout); ++ ++ ++#endif ++ ++ DBG_871X("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ ++ if(adapter->bDriverStopped ||adapter->bSurpriseRemoved) ++ return; ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if (rtw_to_roaming(adapter) > 0) { /* join timeout caused by roaming */ ++ while(1) { ++ pmlmepriv->to_roaming--; ++ if (rtw_to_roaming(adapter) != 0) { /* try another */ ++ DBG_871X("%s try another roaming\n", __FUNCTION__); ++ if( _SUCCESS!=(do_join_r=rtw_do_join(adapter)) ) { ++ DBG_871X("%s roaming do_join return %d\n", __FUNCTION__ ,do_join_r); ++ continue; ++ } ++ break; ++ } else { ++#ifdef CONFIG_INTEL_WIDI ++ if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) ++ { ++ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); ++ intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL); ++ DBG_871X("change to widi listen\n"); ++ } ++#endif // CONFIG_INTEL_WIDI ++ DBG_871X("%s We've try roaming but fail\n", __FUNCTION__); ++ rtw_indicate_disconnect(adapter); ++ break; ++ } ++ } ++ ++ } else ++ #endif ++ { ++ rtw_indicate_disconnect(adapter); ++ free_scanqueue(pmlmepriv);//??? ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ //indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED ++ rtw_cfg80211_indicate_disconnect(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++#ifdef CONFIG_DRVEXT_MODULE_WSC ++ drvext_assoc_fail_indicate(&adapter->drvextpriv); ++#endif ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_unlock(NULL); ++#endif ++ ++_func_exit_; ++ ++} ++ ++/* ++* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey ++* @adapter: pointer to _adapter structure ++*/ ++void rtw_scan_timeout_handler (_adapter *adapter) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ DBG_871X(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ rtw_indicate_scan_done(adapter, _TRUE); ++ ++} ++ ++static void rtw_auto_scan_handler(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++ //auto site survey per 60sec ++ if(pmlmepriv->scan_interval >0) ++ { ++ pmlmepriv->scan_interval--; ++ if(pmlmepriv->scan_interval==0) ++ { ++/* ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_871X("exit %s when _FW_UNDER_SURVEY|_FW_UNDER_LINKING -> \n", __FUNCTION__); ++ return; ++ } ++ ++ if(pmlmepriv->sitesurveyctrl.traffic_busy == _TRUE) ++ { ++ DBG_871X("%s exit cause traffic_busy(%x)\n",__FUNCTION__, pmlmepriv->sitesurveyctrl.traffic_busy); ++ return; ++ } ++*/ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (rtw_buddy_adapter_up(padapter)) ++ { ++ if ((check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || ++ (padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)) ++ { ++ DBG_871X("%s, but buddy_intf is under scanning or linking or BusyTraffic\n", __FUNCTION__); ++ return; ++ } ++ } ++#endif ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ rtw_set_802_11_bssid_list_scan(padapter, NULL, 0); ++ ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ ++ } ++ ++ } ++ ++} ++ ++void rtw_dynamic_check_timer_handlder(_adapter *adapter) ++{ ++#ifdef CONFIG_AP_MODE ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++#endif //CONFIG_AP_MODE ++ struct registry_priv *pregistrypriv = &adapter->registrypriv; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = adapter->pbuddy_adapter; ++#endif ++ ++ if(!adapter) ++ return; ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ if(adapter->HalFunc.hal_checke_bt_hang) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if (adapter->adapter_type == PRIMARY_ADAPTER) ++#endif ++ adapter->HalFunc.hal_checke_bt_hang(adapter); ++ } ++#endif ++ if(adapter->hw_init_completed == _FALSE) ++ return; ++ ++ if ((adapter->bDriverStopped == _TRUE)||(adapter->bSurpriseRemoved== _TRUE)) ++ return; ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_adapter) ++ { ++ if(adapter->net_closed == _TRUE && pbuddy_adapter->net_closed == _TRUE) ++ { ++ return; ++ } ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ if(adapter->net_closed == _TRUE) ++ { ++ return; ++ } ++ ++ rtw_dynamic_chk_wk_cmd(adapter); ++ ++ if(pregistrypriv->wifi_spec==1) ++ { ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++#endif ++ { ++ //auto site survey ++ rtw_auto_scan_handler(adapter); ++ } ++ } ++ ++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ expire_timeout_chk(adapter); ++ } ++#endif ++#endif //!CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if( adapter->pnetdev->br_port ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if( rcu_dereference(adapter->pnetdev->rx_handler_data) ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ // expire NAT2.5 entry ++ void nat25_db_expire(_adapter *priv); ++ nat25_db_expire(adapter); ++ ++ if (adapter->pppoe_connection_in_progress > 0) { ++ adapter->pppoe_connection_in_progress--; ++ } ++ ++ // due to rtw_dynamic_check_timer_handlder() is called every 2 seconds ++ if (adapter->pppoe_connection_in_progress > 0) { ++ adapter->pppoe_connection_in_progress--; ++ } ++ } ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++#endif // CONFIG_BR_EXT ++ ++} ++ ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++inline bool rtw_is_scan_deny(_adapter *adapter) ++{ ++ struct mlme_priv *mlmepriv = &adapter->mlmepriv; ++ return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE; ++} ++ ++inline void rtw_clear_scan_deny(_adapter *adapter) ++{ ++ struct mlme_priv *mlmepriv = &adapter->mlmepriv; ++ ATOMIC_SET(&mlmepriv->set_scan_deny, 0); ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); ++} ++ ++void rtw_set_scan_deny_timer_hdl(_adapter *adapter) ++{ ++ rtw_clear_scan_deny(adapter); ++} ++ ++void rtw_set_scan_deny(_adapter *adapter, u32 ms) ++{ ++ struct mlme_priv *mlmepriv = &adapter->mlmepriv; ++#ifdef CONFIG_CONCURRENT_MODE ++ struct mlme_priv *b_mlmepriv; ++#endif ++ ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); ++ ATOMIC_SET(&mlmepriv->set_scan_deny, 1); ++ _set_timer(&mlmepriv->set_scan_deny_timer, ms); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (!adapter->pbuddy_adapter) ++ return; ++ ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter->pbuddy_adapter)); ++ b_mlmepriv = &adapter->pbuddy_adapter->mlmepriv; ++ ATOMIC_SET(&b_mlmepriv->set_scan_deny, 1); ++ _set_timer(&b_mlmepriv->set_scan_deny_timer, ms); ++#endif ++ ++} ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++void rtw_event_polling_timer_hdl(_adapter *adapter) ++{ ++ rtw_event_polling_cmd(adapter); ++} ++#endif ++ ++#if defined(IEEE80211_SCAN_RESULT_EXPIRE) ++#define RTW_SCAN_RESULT_EXPIRE IEEE80211_SCAN_RESULT_EXPIRE/HZ*1000 -1000 //3000 -1000 ++#else ++#define RTW_SCAN_RESULT_EXPIRE 2000 ++#endif ++ ++#ifndef PLATFORM_FREEBSD ++/* ++* Select a new join candidate from the original @param candidate and @param competitor ++* @return _TRUE: candidate is updated ++* @return _FALSE: candidate is not updated ++*/ ++static int rtw_check_join_candidate(struct mlme_priv *pmlmepriv ++ , struct wlan_network **candidate, struct wlan_network *competitor) ++{ ++ int updated = _FALSE; ++ _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++ ++ //check bssid, if needed ++ if(pmlmepriv->assoc_by_bssid==_TRUE) { ++ if(_rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN) ==_FALSE) ++ goto exit; ++ } ++ ++ //check ssid, if needed ++ if(pmlmepriv->assoc_ssid.Ssid && pmlmepriv->assoc_ssid.SsidLength) { ++ if( competitor->network.Ssid.SsidLength != pmlmepriv->assoc_ssid.SsidLength ++ || _rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength) == _FALSE ++ ) ++ goto exit; ++ } ++ ++ if(rtw_is_desired_network(adapter, competitor) == _FALSE) ++ goto exit; ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ if(rtw_to_roaming(adapter) > 0) { ++ if( rtw_get_passing_time_ms((u32)competitor->last_scanned) >= RTW_SCAN_RESULT_EXPIRE ++ || is_same_ess(&competitor->network, &pmlmepriv->cur_network.network) == _FALSE ++ ) ++ goto exit; ++ } ++#endif ++ ++ if(*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ ++#if 0 ++ if(pmlmepriv->assoc_by_bssid==_TRUE) { // associate with bssid ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && _rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0 ) { // associate with ssid, but ssidlength is 0 ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } else ++#ifdef CONFIG_LAYER2_ROAMING ++ if(rtw_to_roaming(adapter)) { // roaming ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && is_same_ess(&competitor->network, &pmlmepriv->cur_network.network) ++ //&&(!is_same_network(&competitor->network, &pmlmepriv->cur_network.network)) ++ && rtw_get_passing_time_ms((u32)competitor->last_scanned) < RTW_SCAN_RESULT_EXPIRE ++ && rtw_is_desired_network(adapter, competitor) ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ ++ } else ++#endif ++ { // associate with ssid ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && (competitor->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength) ++ &&((_rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE) ++ && rtw_is_desired_network(adapter, competitor) ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } ++#endif ++ ++ if(updated){ ++ DBG_871X("[by_bssid:%u][assoc_ssid:%s]" ++ #ifdef CONFIG_LAYER2_ROAMING ++ "[to_roaming:%u] " ++ #endif ++ "new candidate: %s("MAC_FMT") rssi:%d\n", ++ pmlmepriv->assoc_by_bssid, ++ pmlmepriv->assoc_ssid.Ssid, ++ #ifdef CONFIG_LAYER2_ROAMING ++ rtw_to_roaming(adapter), ++ #endif ++ (*candidate)->network.Ssid.Ssid, ++ MAC_ARG((*candidate)->network.MacAddress), ++ (int)(*candidate)->network.Rssi ++ ); ++ } ++ ++exit: ++ return updated; ++} ++ ++/* ++Calling context: ++The caller of the sub-routine will be in critical section... ++ ++The caller must hold the following spinlock ++ ++pmlmepriv->lock ++ ++ ++*/ ++ ++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv ) ++{ ++ _irqL irqL; ++ int ret; ++ _list *phead; ++ _adapter *adapter; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *candidate = NULL; ++ u8 bSupportAntDiv = _FALSE; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ adapter = (_adapter *)pmlmepriv->nic_hdl; ++ ++ pmlmepriv->pscanned = get_next( phead ); ++ ++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ #if 0 ++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid); ++ #endif ++ ++ rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork); ++ ++ } ++ ++ if(candidate == NULL) { ++ DBG_871X("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); ++#ifdef CONFIG_WOWLAN ++ _clr_fwstate_(pmlmepriv, _FW_LINKED|_FW_UNDER_LINKING); ++#endif ++ ret = _FAIL; ++ goto exit; ++ } else { ++ DBG_871X("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, ++ candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), ++ candidate->network.Configuration.DSConfig); ++ } ++ ++ ++ // check for situation of _FW_LINKED ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ DBG_871X("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__); ++ ++ #if 0 // for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... ++ if(is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) ++ { ++ DBG_871X("%s: _FW_LINKED and is same network, it needn't join again\n", __FUNCTION__); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ ++ ret = 2; ++ goto exit; ++ } ++ else ++ #endif ++ { ++ rtw_disassoc_cmd(adapter, 0, _TRUE); ++ rtw_indicate_disconnect(adapter); ++ rtw_free_assoc_resources(adapter, 0); ++ } ++ } ++ ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); ++ if(_TRUE == bSupportAntDiv) ++ { ++ u8 CurrentAntenna; ++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna)); ++ DBG_871X("#### Opt_Ant_(%s) , cur_Ant(%s)\n", ++ (2==candidate->network.PhyInfo.Optimum_antenna)?"A":"B", ++ (2==CurrentAntenna)?"A":"B" ++ ); ++ } ++ #endif ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ret = rtw_joinbss_cmd(adapter, candidate); ++ ++exit: ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++_func_exit_; ++ ++ return ret; ++} ++#else ++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv ) ++{ ++ _irqL irqL; ++ _list *phead; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ u8 CurrentAntenna; ++#endif ++ unsigned char *dst_ssid, *src_ssid; ++ _adapter *adapter; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *pnetwork_max_rssi = NULL; ++ #ifdef CONFIG_LAYER2_ROAMING ++ struct wlan_network * roaming_candidate=NULL; ++ u32 cur_time=rtw_get_current_time(); ++ #endif ++ ++_func_enter_; ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ adapter = (_adapter *)pmlmepriv->nic_hdl; ++ ++ pmlmepriv->pscanned = get_next( phead ); ++ ++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(2)rtw_select_and_join_from_scanned_queue return _FAIL:(pnetwork==NULL)\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return _FAIL; ++ } ++ ++ dst_ssid = pnetwork->network.Ssid.Ssid; ++ src_ssid = pmlmepriv->assoc_ssid.Ssid; ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ #if 0 ++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid); ++ #endif ++ ++ if(pmlmepriv->assoc_by_bssid==_TRUE) ++ { ++ if(_rtw_memcmp(pnetwork->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE) ++ { ++ //remove the condition @ 20081125 ++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)|| ++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode) ++ // goto ask_for_joinbss; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network), 0) ++ { ++ //DBG_871X("select_and_join(1): _FW_LINKED and is same network, it needn't join again\n"); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return 2; ++ } ++ else ++ { ++ rtw_disassoc_cmd(adapter, 0, _TRUE); ++ rtw_indicate_disconnect(adapter); ++ rtw_free_assoc_resources(adapter, 0); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ ++ } ++ } ++ else ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ ++ } ++ ++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0) { ++ goto ask_for_joinbss;//anyway, join first selected(dequeued) pnetwork if ssid_len=0 ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ } else if (rtw_to_roaming(adapter) > 0) { ++ ++ if( (roaming_candidate == NULL ||roaming_candidate->network.Rssinetwork.Rssi ) ++ && is_same_ess(&pnetwork->network, &pmlmepriv->cur_network.network) ++ //&&(!is_same_network(&pnetwork->network, &pmlmepriv->cur_network.network, 0)) ++ && rtw_get_time_interval_ms((u32)pnetwork->last_scanned,cur_time) < 5000 ++ ) { ++ roaming_candidate = pnetwork; ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_, ++ DBG_871X ++ ("roaming_candidate???: %s("MAC_FMT")\n", ++ roaming_candidate->network.Ssid.Ssid, MAC_ARG(roaming_candidate->network.MacAddress) ) ++ //) ++ ; ++ } ++ continue; ++ #endif ++ ++ } else if ( (pnetwork->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength) ++ &&((_rtw_memcmp(dst_ssid, src_ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE) ++ ) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("dst_ssid=%s, src_ssid=%s \n", dst_ssid, src_ssid)); ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ rtw_hal_get_def_var(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna)); ++ DBG_871X("#### dst_ssid=(%s) Opt_Ant_(%s) , cur_Ant(%s)\n", dst_ssid, ++ (2==pnetwork->network.PhyInfo.Optimum_antenna)?"A":"B", ++ (2==CurrentAntenna)?"A":"B"); ++#endif ++ //remove the condition @ 20081125 ++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)|| ++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode) ++ //{ ++ // _rtw_memcpy(pmlmepriv->assoc_bssid, pnetwork->network.MacAddress, ETH_ALEN); ++ // goto ask_for_joinbss; ++ //} ++ ++ if(pmlmepriv->assoc_by_rssi==_TRUE)//if the ssid is the same, select the bss which has the max rssi ++ { ++ if( NULL==pnetwork_max_rssi|| pnetwork->network.Rssi > pnetwork_max_rssi->network.Rssi) ++ pnetwork_max_rssi = pnetwork; ++ } ++ else if(rtw_is_desired_network(adapter, pnetwork) == _TRUE) ++ { ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++#if 0 ++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) ++ { ++ DBG_871X("select_and_join(2): _FW_LINKED and is same network, it needn't join again\n"); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ ++ return 2; ++ } ++ else ++#endif ++ { ++ rtw_disassoc_cmd(adapter, 0, _TRUE); ++ //rtw_indicate_disconnect(adapter);// ++ rtw_free_assoc_resources(adapter, 0); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ } ++ else ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ ++ } ++ ++ ++ } ++ ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(rtw_to_roaming(adapter) > 0 && roaming_candidate ){ ++ pnetwork=roaming_candidate; ++ DBG_871X("select_and_join_from_scanned_queue: roaming_candidate: %s("MAC_FMT")\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); ++ goto ask_for_joinbss; ++ } ++ #endif ++ ++ if((pmlmepriv->assoc_by_rssi==_TRUE) && (pnetwork_max_rssi!=NULL)) ++ { ++ pnetwork = pnetwork_max_rssi; ++ DBG_871X("select_and_join_from_scanned_queue: pnetwork_max_rssi: %s("MAC_FMT")\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); ++ goto ask_for_joinbss; ++ } ++ ++ DBG_871X("(1)rtw_select_and_join_from_scanned_queue return _FAIL\n"); ++ ++_func_exit_; ++ ++ return _FAIL; ++ ++ask_for_joinbss: ++ ++_func_exit_; ++ ++ return rtw_joinbss_cmd(adapter, pnetwork); ++ ++} ++#endif //PLATFORM_FREEBSD ++ ++ ++sint rtw_set_auth(_adapter * adapter,struct security_priv *psecuritypriv) ++{ ++ struct cmd_obj* pcmd; ++ struct setauth_parm *psetauthparm; ++ struct cmd_priv *pcmdpriv=&(adapter->cmdpriv); ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; //try again ++ goto exit; ++ } ++ ++ psetauthparm=(struct setauth_parm*)rtw_zmalloc(sizeof(struct setauth_parm)); ++ if(psetauthparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm)); ++ psetauthparm->mode=(unsigned char)psecuritypriv->dot11AuthAlgrthm; ++ ++ pcmd->cmdcode = _SetAuth_CMD_; ++ pcmd->parmbuf = (unsigned char *)psetauthparm; ++ pcmd->cmdsz = (sizeof(struct setauth_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++ ++sint rtw_set_key(_adapter * adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx, bool enqueue) ++{ ++ u8 keylen; ++ struct cmd_obj *pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ if(psecuritypriv->dot11AuthAlgrthm ==dot11AuthAlgrthm_8021X){ ++ psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d \n", psetkeyparm->algorithm)); ++ } ++ else{ ++ psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d \n", psetkeyparm->algorithm)); ++ ++ } ++ psetkeyparm->keyid = (u8)keyid;//0~3 ++ psetkeyparm->set_tx = set_tx; ++ if (is_wep_enc(psetkeyparm->algorithm)) ++ psecuritypriv->key_mask |= BIT(psetkeyparm->keyid); ++ ++ DBG_871X("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n",psetkeyparm->algorithm,psetkeyparm->keyid, psecuritypriv->key_mask); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d \n",psetkeyparm->algorithm, keyid)); ++ ++ switch(psetkeyparm->algorithm){ ++ ++ case _WEP40_: ++ keylen=5; ++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); ++ break; ++ case _WEP104_: ++ keylen=13; ++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); ++ break; ++ case _TKIP_: ++ keylen=16; ++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); ++ psetkeyparm->grpkey=1; ++ break; ++ case _AES_: ++ keylen=16; ++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); ++ psetkeyparm->grpkey=1; ++ break; ++ default: ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n",psecuritypriv->dot11PrivacyAlgrthm)); ++ res= _FAIL; ++ rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); ++ goto exit; ++ } ++ ++ ++ if(enqueue){ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); ++ res= _FAIL; //try again ++ goto exit; ++ } ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ //_rtw_init_sema(&(pcmd->cmd_sem), 0); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ } ++ else{ ++ setkey_hdl(adapter, (u8 *)psetkeyparm); ++ rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm)); ++ } ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++ ++//adjust IEs for rtw_joinbss_cmd in WMM ++int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) ++{ ++ unsigned int ielength=0; ++ unsigned int i, j; ++ ++ i = 12; //after the fixed IE ++ while(i=0 :if there is pre-auth key, and return the entry id ++// ++// ++ ++static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) ++{ ++ struct security_priv *psecuritypriv=&Adapter->securitypriv; ++ int i=0; ++ ++ do ++ { ++ if( ( psecuritypriv->PMKIDList[i].bUsed ) && ++ ( _rtw_memcmp( psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN ) == _TRUE ) ) ++ { ++ break; ++ } ++ else ++ { ++ i++; ++ //continue; ++ } ++ ++ }while(isecuritypriv; ++ ++ if(ie[13]<=20){ ++ // The RSN IE didn't include the PMK ID, append the PMK information ++ ie[ie_len]=1; ++ ie_len++; ++ ie[ie_len]=0; //PMKID count = 0x0100 ++ ie_len++; ++ _rtw_memcpy( &ie[ie_len], &psecuritypriv->PMKIDList[iEntry].PMKID, 16); ++ ++ ie_len+=16; ++ ie[13]+=18;//PMKID length = 2+16 ++ ++ } ++ return (ie_len); ++ ++} ++sint rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie, u8 *out_ie, uint in_len) ++{ ++ u8 authmode, securitytype, match; ++ u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; ++ u8 wpa_oui[4]={0x0, 0x50, 0xf2, 0x01}; ++ uint ielength, cnt, remove_cnt; ++ int iEntry; ++ ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct security_priv *psecuritypriv=&adapter->securitypriv; ++ uint ndisauthmode=psecuritypriv->ndisauthtype; ++ uint ndissecuritytype = psecuritypriv->ndisencryptstatus; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ++ ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n", ++ ndisauthmode, ndissecuritytype)); ++ ++ //copy fixed ie only ++ _rtw_memcpy(out_ie, in_ie,12); ++ ielength=12; ++ if((ndisauthmode==Ndis802_11AuthModeWPA)||(ndisauthmode==Ndis802_11AuthModeWPAPSK)) ++ authmode=_WPA_IE_ID_; ++ if((ndisauthmode==Ndis802_11AuthModeWPA2)||(ndisauthmode==Ndis802_11AuthModeWPA2PSK)) ++ authmode=_WPA2_IE_ID_; ++ ++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) ++ { ++ _rtw_memcpy(out_ie+ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); ++ ++ ielength += psecuritypriv->wps_ie_len; ++ } ++ else if((authmode==_WPA_IE_ID_)||(authmode==_WPA2_IE_ID_)) ++ { ++ //copy RSN or SSN ++ _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1]+2); ++ /* debug for CONFIG_IEEE80211W ++ { ++ int jj; ++ printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2); ++ for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++) ++ printk(" %02x ", psecuritypriv->supplicant_ie[jj]); ++ printk("\n"); ++ }*/ ++ ielength+=psecuritypriv->supplicant_ie[1]+2; ++ rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie); ++#endif ++ } ++ ++ iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); ++ if(iEntry<0) ++ { ++ return ielength; ++ } ++ else ++ { ++ if(authmode == _WPA2_IE_ID_) ++ { ++ ielength=rtw_append_pmkid(adapter, iEntry, out_ie, ielength); ++ } ++ } ++ ++_func_exit_; ++ ++ return ielength; ++} ++ ++void rtw_init_registrypriv_dev_network( _adapter* adapter) ++{ ++ struct registry_priv* pregistrypriv = &adapter->registrypriv; ++ struct eeprom_priv* peepriv = &adapter->eeprompriv; ++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; ++ u8 *myhwaddr = myid(peepriv); ++ ++_func_enter_; ++ ++ _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID)); ++ ++ pdev_network->Configuration.Length=sizeof(NDIS_802_11_CONFIGURATION); ++ pdev_network->Configuration.BeaconPeriod = 100; ++ pdev_network->Configuration.FHConfig.Length = 0; ++ pdev_network->Configuration.FHConfig.HopPattern = 0; ++ pdev_network->Configuration.FHConfig.HopSet = 0; ++ pdev_network->Configuration.FHConfig.DwellTime = 0; ++ ++ ++_func_exit_; ++ ++} ++ ++void rtw_update_registrypriv_dev_network(_adapter* adapter) ++{ ++ int sz=0; ++ struct registry_priv* pregistrypriv = &adapter->registrypriv; ++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; ++ struct security_priv* psecuritypriv = &adapter->securitypriv; ++ struct wlan_network *cur_network = &adapter->mlmepriv.cur_network; ++ //struct xmit_priv *pxmitpriv = &adapter->xmitpriv; ++ ++_func_enter_; ++ ++#if 0 ++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; ++ pxmitpriv->vcs = pregistrypriv->vcs_type; ++ pxmitpriv->vcs_type = pregistrypriv->vcs_type; ++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; ++ pxmitpriv->frag_len = pregistrypriv->frag_thresh; ++ ++ adapter->qospriv.qos_option = pregistrypriv->wmm_enable; ++#endif ++ ++ pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; // adhoc no 802.1x ++ ++ pdev_network->Rssi = 0; ++ ++ switch(pregistrypriv->wireless_mode) ++ { ++ case WIRELESS_11B: ++ pdev_network->NetworkTypeInUse = (Ndis802_11DS); ++ break; ++ case WIRELESS_11G: ++ case WIRELESS_11BG: ++ case WIRELESS_11_24N: ++ case WIRELESS_11G_24N: ++ case WIRELESS_11BG_24N: ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); ++ break; ++ case WIRELESS_11A: ++ case WIRELESS_11A_5N: ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); ++ break; ++ case WIRELESS_11ABGN: ++ if(pregistrypriv->channel > 14) ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); ++ else ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); ++ break; ++ default : ++ // TODO ++ break; ++ } ++ ++ pdev_network->Configuration.DSConfig = (pregistrypriv->channel); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig)); ++ ++ if(cur_network->network.InfrastructureMode == Ndis802_11IBSS) ++ pdev_network->Configuration.ATIMWindow = (0); ++ ++ pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode); ++ ++ // 1. Supported rates ++ // 2. IE ++ ++ //rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; // will be called in rtw_generate_ie ++ sz = rtw_generate_ie(pregistrypriv); ++ ++ pdev_network->IELength = sz; ++ ++ pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network); ++ ++ //notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); ++ //pdev_network->IELength = cpu_to_le32(sz); ++ ++_func_exit_; ++ ++} ++ ++void rtw_get_encrypt_decrypt_from_registrypriv(_adapter* adapter) ++{ ++_func_enter_; ++ ++ ++_func_exit_; ++ ++} ++ ++//the fucntion is at passive_level ++void rtw_joinbss_reset(_adapter *padapter) ++{ ++ u8 threshold; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++#ifdef CONFIG_80211N_HT ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++#endif ++ ++ //todo: if you want to do something io/reg/hw setting before join_bss, please add code here ++ ++ ++ ++ ++#ifdef CONFIG_80211N_HT ++ ++ pmlmepriv->num_FortyMHzIntolerant = 0; ++ ++ pmlmepriv->num_sta_no_ht = 0; ++ ++ phtpriv->ampdu_enable = _FALSE;//reset to disabled ++ ++#ifdef CONFIG_USB_HCI ++ // TH=1 => means that invalidate usb rx aggregation ++ // TH=0 => means that validate usb rx aggregation, use init value. ++ if(phtpriv->ht_option) ++ { ++ if(padapter->registrypriv.wifi_spec==1) ++ threshold = 1; ++ else ++ threshold = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } ++ else ++ { ++ threshold = 1; ++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } ++#endif ++ ++#endif ++ ++} ++ ++ ++#ifdef CONFIG_80211N_HT ++ ++//the fucntion is >= passive_level ++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) ++{ ++ u32 ielen, out_len; ++ HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; ++ unsigned char *p, *pframe; ++ struct rtw_ieee80211_ht_cap ht_capie; ++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ ++ phtpriv->ht_option = _FALSE; ++ ++ p = rtw_get_ie(in_ie+12, _HT_CAPABILITY_IE_, &ielen, in_len-12); ++ ++ if(p && ielen>0) ++ { ++ if(pqospriv->qos_option == 0) ++ { ++ out_len = *pout_len; ++ pframe = rtw_set_ie(out_ie+out_len, _VENDOR_SPECIFIC_IE_, ++ _WMM_IE_Length_, WMM_IE, pout_len); ++ ++ pqospriv->qos_option = 1; ++ } ++ ++ out_len = *pout_len; ++ ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC | ++ IEEE80211_HT_CAP_DSSSCCK40; ++ ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ //if(max_recvbuf_sz-rx_packet_offset>(8191-256)) { ++ // DBG_871X("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__); ++ // ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ //} ++ } ++ /* ++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k ++ AMPDU_para [4:2]:Min MPDU Start Spacing ++ */ ++ ++ /* ++ #if defined(CONFIG_RTL8188E )&& defined (CONFIG_SDIO_HCI) ++ ht_capie.ampdu_params_info = 2; ++ #else ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ #endif ++ */ ++ ++ rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); ++ ht_capie.ampdu_params_info = (max_rx_ampdu_factor&0x03); ++ ++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ) ++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2)); ++ else ++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); ++ ++ ++ pframe = rtw_set_ie(out_ie+out_len, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, pout_len); ++ ++ ++ //_rtw_memcpy(out_ie+out_len, p, ielen+2);//gtest ++ //*pout_len = *pout_len + (ielen+2); ++ ++ ++ phtpriv->ht_option = _TRUE; ++ ++ p = rtw_get_ie(in_ie+12, _HT_ADD_INFO_IE_, &ielen, in_len-12); ++ if(p && (ielen==sizeof(struct ieee80211_ht_addt_info))) ++ { ++ out_len = *pout_len; ++ pframe = rtw_set_ie(out_ie+out_len, _HT_ADD_INFO_IE_, ielen, p+2 , pout_len); ++ } ++ ++ } ++ ++ return (phtpriv->ht_option); ++ ++} ++ ++//the fucntion is > passive_level (in critical_section) ++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len) ++{ ++ u8 *p, max_ampdu_sz; ++ int len; ++ //struct sta_info *bmc_sta, *psta; ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ struct ieee80211_ht_addt_info *pht_addtinfo; ++ //struct recv_reorder_ctrl *preorder_ctrl; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ //struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ //struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(!phtpriv->ht_option) ++ return; ++ ++ if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable)) ++ return; ++ ++ DBG_871X("+rtw_update_ht_cap()\n"); ++ ++ //maybe needs check if ap supports rx ampdu. ++ if((phtpriv->ampdu_enable==_FALSE) &&(pregistrypriv->ampdu_enable==1)) ++ { ++ if(pregistrypriv->wifi_spec==1) ++ { ++ phtpriv->ampdu_enable = _FALSE; ++ } ++ else ++ { ++ phtpriv->ampdu_enable = _TRUE; ++ } ++ } ++ else if(pregistrypriv->ampdu_enable==2) ++ { ++ phtpriv->ampdu_enable = _TRUE; ++ } ++ ++ ++ //check Max Rx A-MPDU Size ++ len = 0; ++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); ++ if(p && len>0) ++ { ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR); ++ max_ampdu_sz = 1 << (max_ampdu_sz+3); // max_ampdu_sz (kbytes); ++ ++ //DBG_871X("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); ++ phtpriv->rx_ampdu_maxlen = max_ampdu_sz; ++ ++ } ++ ++ ++ len=0; ++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); ++ if(p && len>0) ++ { ++ pht_addtinfo = (struct ieee80211_ht_addt_info *)(p+2); ++ //todo: ++ } ++ ++ ++ //update cur_bwmode & cur_ch_offset ++ if ((pregistrypriv->cbw40_enable) && ++ (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && ++ (pmlmeinfo->HT_info.infos[0] & BIT(2))) ++ { ++ int i; ++ u8 rf_type; ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ if((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) ++ { ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ else ++ { ++ #ifdef CONFIG_DISABLE_MCS13TO15 ++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1 ) ++ { ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R_MCS13TO15_OFF[i]; ++ } ++ else ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i]; ++ #else ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i]; ++ #endif //CONFIG_DISABLE_MCS13TO15 ++ } ++ #ifdef RTL8192C_RECONFIG_TO_1T1R ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ #endif ++ } ++ //switch to the 40M Hz mode accoring to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) ++ { ++ case HT_EXTCHNL_OFFSET_UPPER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case HT_EXTCHNL_OFFSET_LOWER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ } ++ ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++ ++ ++ ++#if 0 //move to rtw_update_sta_info_client() ++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info ++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff ++ //todo: check if AP can send A-MPDU packets ++ bmc_sta = rtw_get_bcmc_stainfo(padapter); ++ if(bmc_sta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); ++ if(psta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++#endif ++ ++} ++ ++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ u8 issued; ++ int priority; ++ struct sta_info *psta=NULL; ++ struct ht_priv *phtpriv; ++ struct pkt_attrib *pattrib =&pxmitframe->attrib; ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ ++ //if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE)) ++ if(bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod<100)) ++ return; ++ ++ priority = pattrib->priority; ++ ++ if (pattrib->psta) ++ psta = pattrib->psta; ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return; ++ } ++ ++ ++ phtpriv = &psta->htpriv; ++ ++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) ++ { ++ issued = (phtpriv->agg_enable_bitmap>>priority)&0x1; ++ issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1; ++ ++ if(0==issued) ++ { ++ DBG_871X("rtw_issue_addbareq_cmd, p=%d\n", priority); ++ psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); ++ rtw_addbareq_cmd(padapter,(u8) priority, pattrib->ra); ++ } ++ } ++ ++} ++ ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++inline void rtw_set_roaming(_adapter *adapter, u8 to_roaming) ++{ ++ if (to_roaming == 0) ++ adapter->mlmepriv.to_join = _FALSE; ++ adapter->mlmepriv.to_roaming = to_roaming; ++} ++ ++inline u8 rtw_to_roaming(_adapter *adapter) ++{ ++ return adapter->mlmepriv.to_roaming; ++} ++ ++void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _rtw_roaming(padapter, tgt_network); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int do_join_r; ++ ++ struct wlan_network *pnetwork; ++ ++ if(tgt_network != NULL) ++ pnetwork = tgt_network; ++ else ++ pnetwork = &pmlmepriv->cur_network; ++ ++ if(0 < rtw_to_roaming(padapter)) { ++ DBG_871X("roaming from %s("MAC_FMT"), length:%d\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), ++ pnetwork->network.Ssid.SsidLength); ++ _rtw_memcpy(&pmlmepriv->assoc_ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID)); ++ ++ pmlmepriv->assoc_by_bssid = _FALSE; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_return_all_sta_info(padapter); ++#endif ++ ++ while(1) { ++ if( _SUCCESS==(do_join_r=rtw_do_join(padapter)) ) { ++ break; ++ } else { ++ DBG_871X("roaming do_join return %d\n", do_join_r); ++ pmlmepriv->to_roaming--; ++ ++ if(0< rtw_to_roaming(padapter)) { ++ continue; ++ } else { ++ DBG_871X("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__,__LINE__); ++ rtw_indicate_disconnect(padapter); ++ break; ++ } ++ } ++ } ++ } ++ ++} ++#endif ++ ++sint rtw_linked_check(_adapter *padapter) ++{ ++ if( (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ if(padapter->stapriv.asoc_sta_count > 2) ++ return _TRUE; ++ } ++ else ++ { //Station mode ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)== _TRUE) ++ return _TRUE; ++ } ++ return _FALSE; ++} ++ ++#ifdef CONFIG_CONCURRENT_MODE ++sint rtw_buddy_adapter_up(_adapter *padapter) ++{ ++ sint res = _FALSE; ++ ++ if(padapter == NULL) ++ return res; ++ ++ ++ if(padapter->pbuddy_adapter == NULL) ++ { ++ res = _FALSE; ++ } ++ else if( (padapter->pbuddy_adapter->bDriverStopped) || (padapter->pbuddy_adapter->bSurpriseRemoved) || ++ (padapter->pbuddy_adapter->bup == _FALSE) || (padapter->pbuddy_adapter->hw_init_completed == _FALSE)) ++ { ++ res = _FALSE; ++ } ++ else ++ { ++ res = _TRUE; ++ } ++ ++ return res; ++ ++} ++ ++sint check_buddy_fwstate(_adapter *padapter, sint state) ++{ ++ if(padapter == NULL) ++ return _FALSE; ++ ++ if(padapter->pbuddy_adapter == NULL) ++ return _FALSE; ++ ++ if ((state == WIFI_FW_NULL_STATE) && ++ (padapter->pbuddy_adapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE)) ++ return _TRUE; ++ ++ if (padapter->pbuddy_adapter->mlmepriv.fw_state & state) ++ return _TRUE; ++ ++ return _FALSE; ++} ++ ++u8 rtw_get_buddy_bBusyTraffic(_adapter *padapter) ++{ ++ if(padapter == NULL) ++ return _FALSE; ++ ++ if(padapter->pbuddy_adapter == NULL) ++ return _FALSE; ++ ++ return padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic; ++} ++ ++#endif //CONFIG_CONCURRENT_MODE ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme_ext.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme_ext.c +new file mode 100644 +index 00000000..b244cef0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mlme_ext.c +@@ -0,0 +1,13543 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MLME_EXT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_BT_COEXIST ++#include ++#endif ++ ++struct mlme_handler mlme_sta_tbl[]={ ++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, ++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, ++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, ++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, ++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, ++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, ++ ++ /*---------------------------------------------------------- ++ below 2 are reserved ++ -----------------------------------------------------------*/ ++ {0, "DoReserved", &DoReserved}, ++ {0, "DoReserved", &DoReserved}, ++ {WIFI_BEACON, "OnBeacon", &OnBeacon}, ++ {WIFI_ATIM, "OnATIM", &OnAtim}, ++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, ++ {WIFI_AUTH, "OnAuth", &OnAuthClient}, ++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, ++ {WIFI_ACTION, "OnAction", &OnAction}, ++}; ++ ++#ifdef _CONFIG_NATIVEAP_MLME_ ++struct mlme_handler mlme_ap_tbl[]={ ++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, ++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, ++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, ++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, ++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, ++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, ++ ++ /*---------------------------------------------------------- ++ below 2 are reserved ++ -----------------------------------------------------------*/ ++ {0, "DoReserved", &DoReserved}, ++ {0, "DoReserved", &DoReserved}, ++ {WIFI_BEACON, "OnBeacon", &OnBeacon}, ++ {WIFI_ATIM, "OnATIM", &OnAtim}, ++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, ++ {WIFI_AUTH, "OnAuth", &OnAuth}, ++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, ++ {WIFI_ACTION, "OnAction", &OnAction}, ++}; ++#endif ++ ++struct action_handler OnAction_tbl[]={ ++ {RTW_WLAN_CATEGORY_SPECTRUM_MGMT, "ACTION_SPECTRUM_MGMT", on_action_spct}, ++ {RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos}, ++ {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, ++ {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, ++ {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, ++ {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, ++ {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved}, ++ {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, ++#ifdef CONFIG_IEEE80211W ++ {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query}, ++#else ++ {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved}, ++#endif //CONFIG_IEEE80211W ++ //add for CONFIG_IEEE80211W ++ {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, ++ {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, ++ {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, ++ {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, ++}; ++ ++ ++u8 null_addr[ETH_ALEN]= {0,0,0,0,0,0}; ++ ++/************************************************** ++OUI definitions for the vendor specific IE ++***************************************************/ ++unsigned char RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01}; ++unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02}; ++unsigned char WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04}; ++unsigned char P2P_OUI[] = {0x50,0x6F,0x9A,0x09}; ++unsigned char WFD_OUI[] = {0x50,0x6F,0x9A,0x0A}; ++ ++unsigned char WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; ++unsigned char WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ ++unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02}; ++unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02}; ++ ++extern unsigned char REALTEK_96B_IE[]; ++ ++/******************************************************** ++MCS rate definitions ++*********************************************************/ ++#ifdef CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_2R_MCS13TO15_OFF[16] = {0xff, 0x1f, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++unsigned char MCS_rate_2R[16] = {0xff, 0xff, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++#else //CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_2R[16] = {0xff, 0xff, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++#endif //CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_1R[16] = {0xff, 0x00, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++ ++/******************************************************** ++ChannelPlan definitions ++*********************************************************/ ++/*static RT_CHANNEL_PLAN DefaultChannelPlan[RT_CHANNEL_DOMAIN_MAX] = { ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},32}, // 0x00, RT_CHANNEL_DOMAIN_FCC ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},31}, // 0x01, RT_CHANNEL_DOMAIN_IC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x02, RT_CHANNEL_DOMAIN_ETSI ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x03, RT_CHANNEL_DOMAIN_SPAIN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x04, RT_CHANNEL_DOMAIN_FRANCE ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x05, RT_CHANNEL_DOMAIN_MKK ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x06, RT_CHANNEL_DOMAIN_MKK1 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, // 0x07, RT_CHANNEL_DOMAIN_ISRAEL ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // 0x08, RT_CHANNEL_DOMAIN_TELEC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13 ++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},26}, // 0x0B, RT_CHANNEL_DOMAIN_TAIWAN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,149,153,157,161,165},18}, // 0x0C, RT_CHANNEL_DOMAIN_CHINA ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, // 0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},31}, // 0x0E, RT_CHANNEL_DOMAIN_KOREA ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, // 0x0F, RT_CHANNEL_DOMAIN_TURKEY ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x10, RT_CHANNEL_DOMAIN_JAPAN ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,149,153,157,161,165},20}, // 0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48},17}, // 0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},37}, // 0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G ++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,149,153,157,161,165},19}, // 0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS ++};*/ ++ ++static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[RT_CHANNEL_DOMAIN_2G_MAX] = { ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x00, RT_CHANNEL_DOMAIN_2G_WORLD , Passive scan CH 12, 13 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x01, RT_CHANNEL_DOMAIN_2G_ETSI1 ++ {{1,2,3,4,5,6,7,8,9,10,11},11}, // 0x02, RT_CHANNEL_DOMAIN_2G_FCC1 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x03, RT_CHANNEL_DOMAIN_2G_MIKK1 ++ {{10,11,12,13},4}, // 0x04, RT_CHANNEL_DOMAIN_2G_ETSI2 ++ {{},0}, // 0x05, RT_CHANNEL_DOMAIN_2G_NULL ++}; ++ ++static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[RT_CHANNEL_DOMAIN_5G_MAX] = { ++ {{},0}, // 0x00, RT_CHANNEL_DOMAIN_5G_NULL ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x01, RT_CHANNEL_DOMAIN_5G_ETSI1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x02, RT_CHANNEL_DOMAIN_5G_ETSI2 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165},22}, // 0x03, RT_CHANNEL_DOMAIN_5G_ETSI3 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x04, RT_CHANNEL_DOMAIN_5G_FCC1 ++ {{36,40,44,48,149,153,157,161,165},9}, // 0x05, RT_CHANNEL_DOMAIN_5G_FCC2 ++ {{36,40,44,48,52,56,60,64,149,153,157,161,165},13}, // 0x06, RT_CHANNEL_DOMAIN_5G_FCC3 ++ {{36,40,44,48,52,56,60,64,149,153,157,161},12}, // 0x07, RT_CHANNEL_DOMAIN_5G_FCC4 ++ {{149,153,157,161,165},5}, // 0x08, RT_CHANNEL_DOMAIN_5G_FCC5 ++ {{36,40,44,48,52,56,60,64},8}, // 0x09, RT_CHANNEL_DOMAIN_5G_FCC6 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},20}, // 0x0A, RT_CHANNEL_DOMAIN_5G_FCC7_IC1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},20}, // 0x0B, RT_CHANNEL_DOMAIN_5G_KCC1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x0C, RT_CHANNEL_DOMAIN_5G_MKK1 ++ {{36,40,44,48,52,56,60,64},8}, // 0x0D, RT_CHANNEL_DOMAIN_5G_MKK2 ++ {{100,104,108,112,116,120,124,128,132,136,140},11}, // 0x0E, RT_CHANNEL_DOMAIN_5G_MKK3 ++ {{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},15}, // 0x0F, RT_CHANNEL_DOMAIN_5G_NCC1 ++ {{56,60,64,149,153,157,161,165},8}, // 0x10, RT_CHANNEL_DOMAIN_5G_NCC2 ++ ++ //===== Driver self defined for old channel plan Compatible ,Remember to modify if have new channel plan definition ===== ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},21}, // 0x11, RT_CHANNEL_DOMAIN_5G_FCC ++ {{36,40,44,48},4}, // 0x12, RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS ++ {{36,40,44,48,149,153,157,161},8}, // 0x13, RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS ++}; ++ ++static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[RT_CHANNEL_DOMAIN_MAX] = { ++ //===== 0x00 ~ 0x1F , Old Define ===== ++ {0x02,0x11}, //0x00, RT_CHANNEL_DOMAIN_FCC ++ {0x02,0x0A}, //0x01, RT_CHANNEL_DOMAIN_IC ++ {0x01,0x01}, //0x02, RT_CHANNEL_DOMAIN_ETSI ++ {0x01,0x00}, //0x03, RT_CHANNEL_DOMAIN_SPAIN ++ {0x01,0x00}, //0x04, RT_CHANNEL_DOMAIN_FRANCE ++ {0x03,0x00}, //0x05, RT_CHANNEL_DOMAIN_MKK ++ {0x03,0x00}, //0x06, RT_CHANNEL_DOMAIN_MKK1 ++ {0x01,0x09}, //0x07, RT_CHANNEL_DOMAIN_ISRAEL ++ {0x03,0x09}, //0x08, RT_CHANNEL_DOMAIN_TELEC ++ {0x03,0x00}, //0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN ++ {0x00,0x00}, //0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13 ++ {0x02,0x0F}, //0x0B, RT_CHANNEL_DOMAIN_TAIWAN ++ {0x01,0x08}, //0x0C, RT_CHANNEL_DOMAIN_CHINA ++ {0x02,0x06}, //0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO ++ {0x02,0x0B}, //0x0E, RT_CHANNEL_DOMAIN_KOREA ++ {0x02,0x09}, //0x0F, RT_CHANNEL_DOMAIN_TURKEY ++ {0x01,0x01}, //0x10, RT_CHANNEL_DOMAIN_JAPAN ++ {0x02,0x05}, //0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS ++ {0x01,0x12}, //0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS ++ {0x00,0x04}, //0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G ++ {0x02,0x10}, //0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS ++ {0x00,0x12}, //0x15, RT_CHANNEL_DOMAIN_ETSI_NO_DFS ++ {0x00,0x13}, //0x16, RT_CHANNEL_DOMAIN_KOREA_NO_DFS ++ {0x03,0x12}, //0x17, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS ++ {0x05,0x08}, //0x18, RT_CHANNEL_DOMAIN_PAKISTAN_NO_DFS ++ {0x02,0x08}, //0x19, RT_CHANNEL_DOMAIN_TAIWAN2_NO_DFS ++ {0x00,0x00}, //0x1A, ++ {0x00,0x00}, //0x1B, ++ {0x00,0x00}, //0x1C, ++ {0x00,0x00}, //0x1D, ++ {0x00,0x00}, //0x1E, ++ {0x05,0x04}, //0x1F, RT_CHANNEL_DOMAIN_WORLD_WIDE_ONLY_5G ++ //===== 0x20 ~ 0x7F ,New Define ===== ++ {0x00,0x00}, //0x20, RT_CHANNEL_DOMAIN_WORLD_NULL ++ {0x01,0x00}, //0x21, RT_CHANNEL_DOMAIN_ETSI1_NULL ++ {0x02,0x00}, //0x22, RT_CHANNEL_DOMAIN_FCC1_NULL ++ {0x03,0x00}, //0x23, RT_CHANNEL_DOMAIN_MKK1_NULL ++ {0x04,0x00}, //0x24, RT_CHANNEL_DOMAIN_ETSI2_NULL ++ {0x02,0x04}, //0x25, RT_CHANNEL_DOMAIN_FCC1_FCC1 ++ {0x00,0x01}, //0x26, RT_CHANNEL_DOMAIN_WORLD_ETSI1 ++ {0x03,0x0C}, //0x27, RT_CHANNEL_DOMAIN_MKK1_MKK1 ++ {0x00,0x0B}, //0x28, RT_CHANNEL_DOMAIN_WORLD_KCC1 ++ {0x00,0x05}, //0x29, RT_CHANNEL_DOMAIN_WORLD_FCC2 ++ {0x00,0x00}, //0x2A, ++ {0x00,0x00}, //0x2B, ++ {0x00,0x00}, //0x2C, ++ {0x00,0x00}, //0x2D, ++ {0x00,0x00}, //0x2E, ++ {0x00,0x00}, //0x2F, ++ {0x00,0x06}, //0x30, RT_CHANNEL_DOMAIN_WORLD_FCC3 ++ {0x00,0x07}, //0x31, RT_CHANNEL_DOMAIN_WORLD_FCC4 ++ {0x00,0x08}, //0x32, RT_CHANNEL_DOMAIN_WORLD_FCC5 ++ {0x00,0x09}, //0x33, RT_CHANNEL_DOMAIN_WORLD_FCC6 ++ {0x02,0x0A}, //0x34, RT_CHANNEL_DOMAIN_FCC1_FCC7 ++ {0x00,0x02}, //0x35, RT_CHANNEL_DOMAIN_WORLD_ETSI2 ++ {0x00,0x03}, //0x36, RT_CHANNEL_DOMAIN_WORLD_ETSI3 ++ {0x03,0x0D}, //0x37, RT_CHANNEL_DOMAIN_MKK1_MKK2 ++ {0x03,0x0E}, //0x38, RT_CHANNEL_DOMAIN_MKK1_MKK3 ++ {0x02,0x0F}, //0x39, RT_CHANNEL_DOMAIN_FCC1_NCC1 ++ {0x00,0x00}, //0x3A, ++ {0x00,0x00}, //0x3B, ++ {0x00,0x00}, //0x3C, ++ {0x00,0x00}, //0x3D, ++ {0x00,0x00}, //0x3E, ++ {0x00,0x00}, //0x3F, ++ {0x02,0x10}, //0x40, RT_CHANNEL_DOMAIN_FCC1_NCC2 ++ {0x03,0x00}, //0x41, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G ++}; ++ ++static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = {0x03,0x02}; //use the conbination for max channel numbers ++ ++/* ++ * Search the @param channel_num in given @param channel_set ++ * @ch_set: the given channel set ++ * @ch: the given channel number ++ * ++ * return the index of channel_num in channel_set, -1 if not found ++ */ ++int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) ++{ ++ int i; ++ for(i=0;ch_set[i].ChannelNum!=0;i++){ ++ if(ch == ch_set[i].ChannelNum) ++ break; ++ } ++ ++ if(i >= ch_set[i].ChannelNum) ++ return -1; ++ return i; ++} ++ ++/**************************************************************************** ++ ++Following are the initialization functions for WiFi MLME ++ ++*****************************************************************************/ ++ ++int init_hw_mlme_ext(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ //set_opmode_cmd(padapter, infra_client_with_mlme);//removed ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ return _SUCCESS; ++} ++ ++static void init_mlme_ext_priv_value(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++#ifdef CONFIG_TDLS ++ u8 i; ++#endif ++ ++ //unsigned char default_channel_set[MAX_CHANNEL_NUM] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0}; ++ unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_,_9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff}; ++ unsigned char mixed_basicrate[NumRates] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _12M_RATE_, _24M_RATE_, 0xff,}; ++ ++ ATOMIC_SET(&pmlmeext->event_seq, 0); ++ pmlmeext->mgnt_seq = 0;//reset to zero when disconnect at client mode ++#ifdef CONFIG_IEEE80211W ++ pmlmeext->sa_query_seq = 0; ++ pmlmeext->mgnt_80211w_IPN=0; ++ pmlmeext->mgnt_80211w_IPN_rx=0; ++#endif //CONFIG_IEEE80211W ++ pmlmeext->cur_channel = padapter->registrypriv.channel; ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ pmlmeext->retry = 0; ++ ++ pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; ++ ++ //_rtw_memcpy(pmlmeext->channel_set, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Channel, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Len); ++ //_rtw_memcpy(pmlmeext->channel_set, default_channel_set, MAX_CHANNEL_NUM); ++ _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates); ++ _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates); ++ ++ if(pmlmeext->cur_channel > 14) ++ pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB; ++ else ++ pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB; ++ ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ pmlmeext->scan_abort = _FALSE; ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ pmlmeinfo->reauth_count = 0; ++ pmlmeinfo->reassoc_count = 0; ++ pmlmeinfo->link_count = 0; ++ pmlmeinfo->auth_seq = 0; ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; ++ pmlmeinfo->key_index = 0; ++ pmlmeinfo->iv = 0; ++ ++ pmlmeinfo->enc_algo = _NO_PRIVACY_; ++ pmlmeinfo->authModeToggle = 0; ++ ++ _rtw_memset(pmlmeinfo->chg_txt, 0, 128); ++ ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ pmlmeinfo->preamble_mode = PREAMBLE_AUTO; ++ ++ pmlmeinfo->dialogToken = 0; ++ ++ pmlmeext->action_public_rxseq = 0xffff; ++ pmlmeext->action_public_dialog_token = 0xff; ++} ++ ++static int has_channel(RT_CHANNEL_INFO *channel_set, ++ u8 chanset_size, ++ u8 chan) { ++ int i; ++ ++ for (i = 0; i < chanset_size; i++) { ++ if (channel_set[i].ChannelNum == chan) { ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set, ++ u8 chanset_size, ++ struct p2p_channels *channel_list) { ++ ++ struct p2p_oper_class_map op_class[] = { ++ { IEEE80211G, 81, 1, 13, 1, BW20 }, ++ { IEEE80211G, 82, 14, 14, 1, BW20 }, ++#if 0 /* Do not enable HT40 on 2 GHz */ ++ { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, ++ { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, ++#endif ++ { IEEE80211A, 115, 36, 48, 4, BW20 }, ++ { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, ++ { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, ++ { IEEE80211A, 124, 149, 161, 4, BW20 }, ++ { IEEE80211A, 125, 149, 169, 4, BW20 }, ++ { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, ++ { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, ++ { -1, 0, 0, 0, 0, BW20 } ++ }; ++ ++ int cla, op; ++ ++ cla = 0; ++ ++ for (op = 0; op_class[op].op_class; op++) { ++ u8 ch; ++ struct p2p_oper_class_map *o = &op_class[op]; ++ struct p2p_reg_class *reg = NULL; ++ ++ for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { ++ if (!has_channel(channel_set, chanset_size, ch)) { ++ continue; ++ } ++ ++ if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc)) ++ continue; ++ ++ if ((0 == (padapter->registrypriv.cbw40_enable & BIT(1))) && ++ ((BW40MINUS == o->bw) || (BW40PLUS == o->bw))) ++ continue; ++ ++ if (reg == NULL) { ++ reg = &channel_list->reg_class[cla]; ++ cla++; ++ reg->reg_class = o->op_class; ++ reg->channels = 0; ++ } ++ reg->channel[reg->channels] = ch; ++ reg->channels++; ++ } ++ } ++ channel_list->reg_classes = cla; ++ ++} ++ ++static u8 init_channel_set(_adapter* padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) ++{ ++ u8 index,chanset_size = 0; ++ u8 b5GBand = _FALSE, b2_4GBand = _FALSE; ++ u8 Index2G = 0, Index5G=0; ++ ++ _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO)*MAX_CHANNEL_NUM); ++ ++ if(ChannelPlan >= RT_CHANNEL_DOMAIN_MAX && ChannelPlan != RT_CHANNEL_DOMAIN_REALTEK_DEFINE) ++ { ++ DBG_871X("ChannelPlan ID %x error !!!!!\n",ChannelPlan); ++ return chanset_size; ++ } ++ ++ if(padapter->registrypriv.wireless_mode & WIRELESS_11G) ++ { ++ b2_4GBand = _TRUE; ++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan) ++ Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; ++ else ++ Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; ++ } ++ ++ if(padapter->registrypriv.wireless_mode & WIRELESS_11A) ++ { ++ b5GBand = _TRUE; ++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan) ++ Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; ++ else ++ Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; ++ } ++ ++ if(b2_4GBand) ++ { ++ for(index=0;index= 1 && channel_set[chanset_size].ChannelNum <= 11) ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ else if((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ else if(RT_CHANNEL_DOMAIN_WORLD_WIDE_13 == ChannelPlan || ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan || ++ RT_CHANNEL_DOMAIN_2G_WORLD == Index2G)// channel 12~13, passive scan ++ { ++ if(channel_set[chanset_size].ChannelNum <= 11) ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ else ++ { ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ } ++ ++ chanset_size++; ++ } ++ } ++ ++ if(b5GBand) ++ { ++ for(index=0;index= 149 ) ++ { ++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan)//passive scan for all 5G channels ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ } ++ else ++ { ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ chanset_size++; ++#else /* CONFIG_DFS */ ++ if ( RTW_ChannelPlan5G[Index5G].Channel[index] <= 48 ++ || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149 ) { ++ channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; ++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan)//passive scan for all 5G channels ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ DBG_871X("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum); ++ chanset_size++; ++ } ++#endif /* CONFIG_DFS */ ++ } ++ } ++ ++ return chanset_size; ++} ++ ++int init_mlme_ext_priv(_adapter* padapter) ++{ ++ int res = _SUCCESS; ++ struct registry_priv* pregistrypriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); ++ ++ pmlmeext->padapter = padapter; ++ ++ //fill_fwpriv(padapter, &(pmlmeext->fwpriv)); ++ ++ init_mlme_ext_priv_value(padapter); ++ pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq; ++ ++ init_mlme_ext_timer(padapter); ++ ++#ifdef CONFIG_AP_MODE ++ init_mlme_ap_info(padapter); ++#endif ++ ++ pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan,pmlmeext->channel_set); ++ init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); ++ ++ pmlmeext->chan_scan_time = SURVEY_TO; ++ pmlmeext->mlmeext_init = _TRUE; ++ ++ ++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ pmlmeext->active_keep_alive_check = _TRUE; ++#endif ++ ++#ifdef DBG_FIXED_CHAN ++ pmlmeext->fixed_chan = 0xFF; ++#endif ++ ++ return res; ++ ++} ++ ++void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext) ++{ ++ _adapter *padapter = pmlmeext->padapter; ++ ++ if (!padapter) ++ return; ++ ++ if (padapter->bDriverStopped == _TRUE) ++ { ++ _cancel_timer_ex(&pmlmeext->survey_timer); ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ //_cancel_timer_ex(&pmlmeext->ADDBA_timer); ++ } ++} ++ ++static u8 cmp_pkt_chnl_diff(_adapter *padapter,u8* pframe,uint packet_len) ++{ // if the channel is same, return 0. else return channel differential ++ uint len; ++ u8 channel; ++ u8 *p; ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_); ++ if (p) ++ { ++ channel = *(p + 2); ++ if(padapter->mlmeextpriv.cur_channel >= channel) ++ { ++ return (padapter->mlmeextpriv.cur_channel - channel); ++ } ++ else ++ { ++ return (channel-padapter->mlmeextpriv.cur_channel); ++ } ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame) ++{ ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ ++ if(ptable->func) ++ { ++ //receive the frames that ra(a1) is my address or ra(a1) is bc address. ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) && ++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) ++ { ++ return; ++ } ++ ++ ptable->func(padapter, precv_frame); ++ } ++ ++} ++ ++void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int index; ++ struct mlme_handler *ptable; ++#ifdef CONFIG_AP_MODE ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#endif //CONFIG_AP_MODE ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(pframe)); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ++ ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n", ++ GetFrameType(pframe), GetFrameSubType(pframe))); ++ ++#if 0 ++ { ++ u8 *pbuf; ++ pbuf = GetAddr1Ptr(pframe); ++ DBG_871X("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ pbuf = GetAddr2Ptr(pframe); ++ DBG_871X("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ pbuf = GetAddr3Ptr(pframe); ++ DBG_871X("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ } ++#endif ++ ++ if (GetFrameType(pframe) != WIFI_MGT_TYPE) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe))); ++ return; ++ } ++ ++ //receive the frames that ra(a1) is my address or ra(a1) is bc address. ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) && ++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) ++ { ++ return; ++ } ++ ++ ptable = mlme_sta_tbl; ++ ++ index = GetFrameSubType(pframe) >> 4; ++ ++#ifdef CONFIG_TDLS ++ if((index << 4)==WIFI_ACTION){ ++ //category==public (4), action==TDLS_DISCOVERY_RESPONSE ++ if(*(pframe+24)==0x04 && *(pframe+25)==TDLS_DISCOVERY_RESPONSE){ ++ DBG_871X("recv tdls discovery response frame\n"); ++ On_TDLS_Dis_Rsp(padapter, precv_frame); ++ } ++ } ++#endif //CONFIG_TDLS ++ ++ if (index > 13) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Currently we do not support reserved sub-fr-type=%d\n", index)); ++ return; ++ } ++ ptable += index; ++ ++#if 1 ++ if (psta != NULL) ++ { ++ if (GetRetry(pframe)) ++ { ++ if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) ++ { ++ /* drop the duplicate management frame */ ++ DBG_871X("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); ++ return; ++ } ++ } ++ psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num; ++ } ++#else ++ ++ if(GetRetry(pframe)) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); ++ //return; ++ } ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ switch (GetFrameSubType(pframe)) ++ { ++ case WIFI_AUTH: ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ ptable->func = &OnAuth; ++ else ++ ptable->func = &OnAuthClient; ++ //pass through ++ case WIFI_ASSOCREQ: ++ case WIFI_REASSOCREQ: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++#ifdef CONFIG_HOSTAPD_MLME ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++#endif ++ break; ++ case WIFI_PROBEREQ: ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_HOSTAPD_MLME ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++#else ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++#endif ++ } ++ else ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ case WIFI_BEACON: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ case WIFI_ACTION: ++ //if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ default: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++ break; ++ } ++#else ++ ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ ++#endif ++ ++} ++ ++#ifdef CONFIG_P2P ++u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) ++{ ++ bool response = _TRUE; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ { ++ if(padapter->cfg80211_wdinfo.is_ro_ch == _FALSE ++ || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel ++ || wdev_to_priv(padapter->rtw_wdev)->p2p_enabled == _FALSE ++ || padapter->mlmepriv.wps_probe_resp_ie == NULL ++ || padapter->mlmepriv.p2p_probe_resp_ie == NULL ++ ) ++ { ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p, ", ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled, ++ padapter->mlmepriv.wps_probe_resp_ie, ++ padapter->mlmepriv.p2p_probe_resp_ie); ++ DBG_871X("is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n", ++ padapter->cfg80211_wdinfo.is_ro_ch, ++ rtw_get_oper_ch(padapter), ++ padapter->wdinfo.listen_channel); ++#endif ++ response = _FALSE; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ if( padapter->wdinfo.driver_interface == DRIVER_WEXT ) ++ { ++ // do nothing if the device name is empty ++ if ( !padapter->wdinfo.device_name_len ) ++ { ++ response = _FALSE; ++ } ++ } ++ ++ if (response == _TRUE) ++ issue_probersp_p2p( padapter, da); ++ ++ return _SUCCESS; ++} ++#endif //CONFIG_P2P ++ ++ ++/**************************************************************************** ++ ++Following are the callback functions for each subtype of the management frames ++ ++*****************************************************************************/ ++ ++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int ielen; ++ unsigned char *p; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ u8 is_valid_p2p_probereq = _FALSE; ++ ++#ifdef CONFIG_ATMEL_RC_PATCH ++ u8 *target_ie=NULL, *wps_ie=NULL; ++ u8 *start; ++ uint search_len = 0, wps_ielen = 0, target_ielen = 0; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ u8 wifi_test_chk_rate = 1; ++ ++ if ( !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) && ++ !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) ++ ) ++ { ++ // Commented by Albert 2011/03/17 ++ // mcs_rate = 0 -> CCK 1M rate ++ // mcs_rate = 1 -> CCK 2M rate ++ // mcs_rate = 2 -> CCK 5.5M rate ++ // mcs_rate = 3 -> CCK 11M rate ++ // In the P2P mode, the driver should not support the CCK rate ++ ++ // Commented by Kurt 2012/10/16 ++ // IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client ++#ifdef CONFIG_WIFI_TEST ++ if ( pattrib->mcs_rate <= 3 ) ++ { ++ wifi_test_chk_rate = 0; ++ } ++#endif //CONFIG_WIFI_TEST ++ ++ if( wifi_test_chk_rate == 1 ) ++ { ++ if((is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len)) == _TRUE) ++ { ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) ++ { ++#ifndef CONFIG_IOCTL_CFG80211 ++// FIXME ++ report_survey_event(padapter, precv_frame); ++#endif ++ p2p_listen_state_process( padapter, get_sa(pframe)); ++ ++ return _SUCCESS; ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ goto _continue; ++ } ++ } ++ } ++ } ++ ++_continue: ++#endif //CONFIG_P2P ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ return _SUCCESS; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && ++ check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)==_FALSE) ++ { ++ return _SUCCESS; ++ } ++ ++ ++ //DBG_871X("+OnProbeReq\n"); ++ ++ ++#ifdef CONFIG_ATMEL_RC_PATCH ++ if ((wps_ie = rtw_get_wps_ie( ++ pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_, ++ NULL, &wps_ielen))) { ++ ++ target_ie = rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen); ++ } ++ if ((target_ie && (target_ielen == 4)) && (_TRUE ==_rtw_memcmp((void *)target_ie, "Ozmo",4 ))) { ++ //psta->flag_atmel_rc = 1; ++ unsigned char *sa_addr = get_sa(pframe); ++ DBG_871X("%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x \n\n", ++ __func__, *sa_addr, *(sa_addr+1), *(sa_addr+2), *(sa_addr+3), *(sa_addr+4), *(sa_addr+5)); ++ _rtw_memcpy( pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN); ++ } ++#endif ++#ifdef CONFIG_CONCURRENT_MODE ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) ++ { ++ //don't process probe req ++ return _SUCCESS; ++ } ++#endif ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ ++ //check (wildcard) SSID ++ if (p != NULL) ++ { ++ if(is_valid_p2p_probereq == _TRUE) ++ { ++ goto _issue_probersp; ++ } ++ ++ if ( (ielen != 0 && _FALSE ==_rtw_memcmp((void *)(p+2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) ++ || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) ++ ) ++ { ++ return _SUCCESS; ++ } ++ ++_issue_probersp: ++ ++ if(((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && ++ pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) ++ { ++ //DBG_871X("+issue_probersp during ap mode\n"); ++ issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); ++ } ++ ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *psta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) ++ { ++ if( _rtw_memcmp( pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) ++ { ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) ++ { ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ issue_p2p_provision_request( padapter, ++ pwdinfo->tx_prov_disc_info.ssid.Ssid, ++ pwdinfo->tx_prov_disc_info.ssid.SsidLength, ++ pwdinfo->tx_prov_disc_info.peerDevAddr ); ++ } ++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ issue_p2p_provision_request( padapter, ++ NULL, ++ 0, ++ pwdinfo->tx_prov_disc_info.peerDevAddr ); ++ } ++ } ++ } ++ return _SUCCESS; ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ if ( _TRUE == pwdinfo->nego_req_info.benable ) ++ { ++ DBG_871X( "[%s] P2P State is GONEGO ING!\n", __FUNCTION__ ); ++ if( _rtw_memcmp( pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) ++ { ++ pwdinfo->nego_req_info.benable = _FALSE; ++ issue_p2p_GO_request( padapter, pwdinfo->nego_req_info.peerDevAddr); ++ } ++ } ++ } ++ else if( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) ) ++ { ++ if ( _TRUE == pwdinfo->invitereq_info.benable ) ++ { ++ DBG_871X( "[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__ ); ++ if( _rtw_memcmp( pwdinfo->invitereq_info.peer_macaddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) ++ { ++ pwdinfo->invitereq_info.benable = _FALSE; ++ issue_p2p_invitation_request( padapter, pwdinfo->invitereq_info.peer_macaddr ); ++ } ++ } ++ } ++#endif //CONFIG_P2P ++ ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ report_survey_event(padapter, precv_frame); ++#ifdef CONFIG_CONCURRENT_MODE ++ report_survey_event(padapter->pbuddy_adapter, precv_frame); ++#endif //CONFIG_CONCURRENT_MODE ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_report_survey_event(padapter, precv_frame); ++#endif //CONFIG_DUALMAC_CONCURRENT ++ return _SUCCESS; ++ } ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) ++ { ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ psta->sta_stats.rx_mgnt_pkts++; ++ } ++ } ++ } ++ #endif ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int cam_idx; ++ struct sta_info *psta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ WLAN_BSSID_EX *pbss; ++ int ret = _SUCCESS; ++ u8 *p = NULL; ++ u32 ielen = 0; ++ ++#ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR ++ p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, precv_frame->u.hdr.len -sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_); ++ if ((p != NULL) && (ielen > 0)) ++ { ++ if ((*(p + 1 + ielen) == 0x2D) && (*(p + 2 + ielen) != 0x2D)) ++ { ++ /* Invalid value 0x2D is detected in Extended Supported Rates (ESR) IE. Try to fix the IE length to avoid failed Beacon parsing. */ ++ DBG_871X("[WIFIDBG] Error in ESR IE is detected in Beacon of BSSID:"MAC_FMT". Fix the length of ESR IE to avoid failed Beacon parsing.\n", MAC_ARG(GetAddr3Ptr(pframe))); ++ *(p + 1) = ielen - 1; ++ } ++ } ++#endif ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ report_survey_event(padapter, precv_frame); ++#ifdef CONFIG_CONCURRENT_MODE ++ report_survey_event(padapter->pbuddy_adapter, precv_frame); ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_report_survey_event(padapter, precv_frame); ++#endif ++ ++ return _SUCCESS; ++ } ++ ++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) ++ { ++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) ++ { ++ //we should update current network before auth, or some IE is wrong ++ pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX)); ++ if (pbss) { ++ if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { ++ update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); ++ rtw_get_bcn_info(&(pmlmepriv->cur_network)); ++ } ++ rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX)); ++ } ++ ++ //check the vendor of the assoc AP ++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ //update TSF Value ++ update_TSF(pmlmeext, pframe, len); ++ ++ //start auth ++ start_clnt_auth(padapter); ++ ++ return _SUCCESS; ++ } ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ #ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL ++ //Merge from 8712 FW code ++ if (cmp_pkt_chnl_diff(padapter,pframe,len) != 0) ++ { // join wrong channel, deauth and reconnect ++ issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ ++ report_del_sta_event(padapter,(&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL); ++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS); ++ return _SUCCESS; ++ } ++ #endif //CONFIG_PATCH_JOIN_WRONG_CHANNEL ++ ++ ret = rtw_check_bcn_info(padapter, pframe, len); ++ if (!ret) { ++ DBG_871X_LEVEL(_drv_always_, "ap has changed, disconnect now\n "); ++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0); ++ return _SUCCESS; ++ } ++ //update WMM, ERP in the beacon ++ //todo: the timer is used instead of the number of the beacon received ++ if ((sta_rx_pkts(psta) & 0xf) == 0) ++ { ++ //DBG_871X("update_bcn_info\n"); ++ update_beacon_info(padapter, pframe, len, psta); ++ } ++ ++#ifdef CONFIG_DFS ++ process_csa_ie(padapter, pframe, len); //channel switch announcement ++#endif //CONFIG_DFS ++ ++#ifdef CONFIG_P2P_PS ++ process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); ++#endif //CONFIG_P2P_PS ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ psta->sta_stats.rx_mgnt_pkts++; ++ #endif ++ } ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ //update WMM, ERP in the beacon ++ //todo: the timer is used instead of the number of the beacon received ++ if ((sta_rx_pkts(psta) & 0xf) == 0) ++ { ++ //DBG_871X("update_bcn_info\n"); ++ update_beacon_info(padapter, pframe, len, psta); ++ } ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ psta->sta_stats.rx_mgnt_pkts++; ++ #endif ++ } ++ else ++ { ++ //allocate a new CAM entry for IBSS station ++ if ((cam_idx = allocate_fw_sta_entry(padapter)) == NUM_STA) ++ { ++ goto _END_ONBEACON_; ++ } ++ ++ //get supported rate ++ if (update_sta_support_rate(padapter, (pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_), (len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_), cam_idx) == _FAIL) ++ { ++ pmlmeinfo->FW_sta_info[cam_idx].status = 0; ++ goto _END_ONBEACON_; ++ } ++ ++ //update TSF Value ++ update_TSF(pmlmeext, pframe, len); ++ ++ //report sta add event ++ report_add_sta_event(padapter, GetAddr2Ptr(pframe), cam_idx); ++ } ++ } ++ } ++ ++_END_ONBEACON_: ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ _irqL irqL; ++ unsigned int auth_mode, seq, ie_len; ++ unsigned char *sa, *p; ++ u16 algorithm; ++ int status; ++ static struct sta_info stat; ++ struct sta_info *pstat=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) ++ { ++ //don't process auth request; ++ return _SUCCESS; ++ } ++#endif //CONFIG_CONCURRENT_MODE ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return _FAIL; ++ ++ DBG_871X("+OnAuth\n"); ++ ++ sa = GetAddr2Ptr(pframe); ++ ++ auth_mode = psecuritypriv->dot11AuthAlgrthm; ++ seq = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + 2)); ++ algorithm = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN)); ++ ++ if (GetPrivacy(pframe)) ++ { ++#if 0 //TODO: SW rtw_wep_decrypt ++ if (SWCRYPTO) ++ { ++ status = rtw_wep_decrypt(priv, pframe, pfrinfo->pktlen, ++ priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm); ++ if (status == FALSE) ++ { ++ SAVE_INT_AND_CLI(flags); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"wep-decrypt a Auth frame error!\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ } ++ ++ seq = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4 + 2)); ++ algorithm = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4)); ++#endif ++ } ++ ++ ++ DBG_871X("auth alg=%x, seq=%X\n", algorithm, seq); ++ ++ if (auth_mode == 2 && ++ psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ && ++ psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) ++ auth_mode = 0; ++ ++ if ((algorithm > 0 && auth_mode == 0) || // rx a shared-key auth but shared not enabled ++ (algorithm == 0 && auth_mode == 1) ) // rx a open-system auth but shared-key is enabled ++ { ++ DBG_871X("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n", ++ algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); ++ ++ status = _STATS_NO_SUPP_ALG_; ++ ++ goto auth_fail; ++ } ++ ++#if 0 //ACL control ++ phead = &priv->wlan_acl_list; ++ plist = phead->next; ++ //check sa ++ if (acl_mode == 1) // 1: positive check, only those on acl_list can be connected. ++ res = FAIL; ++ else ++ res = SUCCESS; ++ ++ while(plist != phead) ++ { ++ paclnode = list_entry(plist, struct rtw_wlan_acl_node, list); ++ plist = plist->next; ++ if (!memcmp((void *)sa, paclnode->addr, 6)) { ++ if (paclnode->mode & 2) { // deny ++ res = FAIL; ++ break; ++ } ++ else { ++ res = SUCCESS; ++ break; ++ } ++ } ++ } ++ ++ if (res != SUCCESS) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"auth abort because ACL!\n"); ++ return FAIL; ++ } ++#else ++ if(rtw_access_ctrl(padapter, sa) == _FALSE) ++ { ++ status = _STATS_UNABLE_HANDLE_STA_; ++ goto auth_fail; ++ } ++#endif ++ ++ pstat = rtw_get_stainfo(pstapriv, sa); ++ if (pstat == NULL) ++ { ++ // allocate a new one ++ DBG_871X("going to alloc stainfo for sa="MAC_FMT"\n", MAC_ARG(sa)); ++ pstat = rtw_alloc_stainfo(pstapriv, sa); ++ if (pstat == NULL) ++ { ++ DBG_871X(" Exceed the upper limit of supported clients...\n"); ++ status = _STATS_UNABLE_HANDLE_STA_; ++ goto auth_fail; ++ } ++ ++ pstat->state = WIFI_FW_AUTH_NULL; ++ pstat->auth_seq = 0; ++ ++ //pstat->flags = 0; ++ //pstat->capability = 0; ++ } ++ else ++ { ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&pstat->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&pstat->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ if (pstat->expire_to > 0) ++ { ++ //TODO: STA re_auth within expire_to ++ } ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ if (seq==1) { ++ //TODO: STA re_auth and auth timeout ++ } ++ } ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ if (rtw_is_list_empty(&pstat->auth_list)) ++ { ++ rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list); ++ pstapriv->auth_list_cnt++; ++ } ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ if (pstat->auth_seq == 0) ++ pstat->expire_to = pstapriv->auth_to; ++ ++ if ((pstat->auth_seq + 1) != seq) ++ { ++ DBG_871X("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ ++ if (algorithm==0 && (auth_mode == 0 || auth_mode == 2)) ++ { ++ if (seq == 1) ++ { ++ pstat->state &= ~WIFI_FW_AUTH_NULL; ++ pstat->state |= WIFI_FW_AUTH_SUCCESS; ++ pstat->expire_to = pstapriv->assoc_to; ++ pstat->authalg = algorithm; ++ } ++ else ++ { ++ DBG_871X("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ } ++ else // shared system or auto authentication ++ { ++ if (seq == 1) ++ { ++ //prepare for the challenging txt... ++ ++ //get_random_bytes((void *)pstat->chg_txt, 128);//TODO: ++ ++ pstat->state &= ~WIFI_FW_AUTH_NULL; ++ pstat->state |= WIFI_FW_AUTH_STATE; ++ pstat->authalg = algorithm; ++ pstat->auth_seq = 2; ++ } ++ else if (seq == 3) ++ { ++ //checking for challenging txt... ++ DBG_871X("checking for challenging txt...\n"); ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len, ++ len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4); ++ ++ if((p==NULL) || (ie_len<=0)) ++ { ++ DBG_871X("auth rejected because challenge failure!(1)\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ ++ if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) ++ { ++ pstat->state &= (~WIFI_FW_AUTH_STATE); ++ pstat->state |= WIFI_FW_AUTH_SUCCESS; ++ // challenging txt is correct... ++ pstat->expire_to = pstapriv->assoc_to; ++ } ++ else ++ { ++ DBG_871X("auth rejected because challenge failure!\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ } ++ else ++ { ++ DBG_871X("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ } ++ ++ ++ // Now, we are going to issue_auth... ++ pstat->auth_seq = seq + 1; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_)); ++#endif ++ ++ if (pstat->state & WIFI_FW_AUTH_SUCCESS) ++ pstat->auth_seq = 0; ++ ++ ++ return _SUCCESS; ++ ++auth_fail: ++ ++ if(pstat) ++ rtw_free_stainfo(padapter , pstat); ++ ++ pstat = &stat; ++ _rtw_memset((char *)pstat, '\0', sizeof(stat)); ++ pstat->auth_seq = 2; ++ _rtw_memcpy(pstat->hwaddr, sa, 6); ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_auth(padapter, pstat, (unsigned short)status); ++#endif ++ ++#endif ++ return _FAIL; ++ ++} ++ ++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int seq, len, status, algthm, offset; ++ unsigned char *p; ++ unsigned int go2asoc = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++ ++ if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) ++ return _SUCCESS; ++ ++ offset = (GetPrivacy(pframe))? 4: 0; ++ ++ algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); ++ seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); ++ status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4)); ++ ++ if (status != 0) ++ { ++ DBG_871X("clnt auth fail, status: %d\n", status); ++ if(status == 13)//&& pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) ++ { ++ if(pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; ++ else ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; ++ //pmlmeinfo->reauth_count = 0; ++ } ++ ++ set_link_timer(pmlmeext, 1); ++ goto authclnt_fail; ++ } ++ ++ if (seq == 2) ++ { ++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ { ++ // legendary shared system ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len, ++ pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_); ++ ++ if (p == NULL) ++ { ++ //DBG_871X("marc: no challenge text?\n"); ++ goto authclnt_fail; ++ } ++ ++ _rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len); ++ pmlmeinfo->auth_seq = 3; ++ issue_auth(padapter, NULL, 0); ++ set_link_timer(pmlmeext, REAUTH_TO); ++ ++ return _SUCCESS; ++ } ++ else ++ { ++ // open system ++ go2asoc = 1; ++ } ++ } ++ else if (seq == 4) ++ { ++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ { ++ go2asoc = 1; ++ } ++ else ++ { ++ goto authclnt_fail; ++ } ++ } ++ else ++ { ++ // this is also illegal ++ //DBG_871X("marc: clnt auth failed due to illegal seq=%x\n", seq); ++ goto authclnt_fail; ++ } ++ ++ if (go2asoc) ++ { ++ DBG_871X_LEVEL(_drv_always_, "auth success, start assoc\n"); ++ start_clnt_assoc(padapter); ++ return _SUCCESS; ++ } ++ ++authclnt_fail: ++ ++ //pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); ++ ++ return _FAIL; ++ ++} ++ ++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ _irqL irqL; ++ u16 capab_info, listen_interval; ++ struct rtw_ieee802_11_elems elems; ++ struct sta_info *pstat; ++ unsigned char reassoc, *p, *pos, *wpa_ie; ++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; ++ int i, ie_len, wpa_ie_len, left; ++ unsigned char supportRate[16]; ++ int supportRateNum; ++ unsigned short status = _STATS_SUCCESSFUL_; ++ unsigned short frame_type, ie_offset=0; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 p2p_status_code = P2P_STATUS_SUCCESS; ++ u8 *p2pie; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#endif // CONFIG_WFD ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) ++ { ++ //don't process assoc request; ++ return _SUCCESS; ++ } ++#endif //CONFIG_CONCURRENT_MODE ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return _FAIL; ++ ++ frame_type = GetFrameSubType(pframe); ++ if (frame_type == WIFI_ASSOCREQ) ++ { ++ reassoc = 0; ++ ie_offset = _ASOCREQ_IE_OFFSET_; ++ } ++ else // WIFI_REASSOCREQ ++ { ++ reassoc = 1; ++ ie_offset = _REASOCREQ_IE_OFFSET_; ++ } ++ ++ ++ if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) { ++ DBG_871X("handle_assoc(reassoc=%d) - too short payload (len=%lu)" ++ "\n", reassoc, (unsigned long)pkt_len); ++ return _FAIL; ++ } ++ ++ pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if (pstat == (struct sta_info *)NULL) ++ { ++ status = _RSON_CLS2_; ++ goto asoc_class2_error; ++ } ++ ++ capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); ++ //capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ //listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); ++ listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN+2); ++ ++ left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); ++ pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ // check if this stat has been successfully authenticated/assocated ++ if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) ++ { ++ if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) ++ { ++ status = _RSON_CLS2_; ++ goto asoc_class2_error; ++ } ++ else ++ { ++ pstat->state &= (~WIFI_FW_ASSOC_SUCCESS); ++ pstat->state |= WIFI_FW_ASSOC_STATE; ++ } ++ } ++ else ++ { ++ pstat->state &= (~WIFI_FW_AUTH_SUCCESS); ++ pstat->state |= WIFI_FW_ASSOC_STATE; ++ } ++ ++ ++#if 0// todo:tkip_countermeasures ++ if (hapd->tkip_countermeasures) { ++ resp = WLAN_REASON_MICHAEL_MIC_FAILURE; ++ goto fail; ++ } ++#endif ++ ++ pstat->capability = capab_info; ++ ++#if 0//todo: ++ //check listen_interval ++ if (listen_interval > hapd->conf->max_listen_interval) { ++ hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211, ++ HOSTAPD_LEVEL_DEBUG, ++ "Too large Listen Interval (%d)", ++ listen_interval); ++ resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE; ++ goto fail; ++ } ++ ++ pstat->listen_interval = listen_interval; ++#endif ++ ++ //now parse all ieee802_11 ie to point to elems ++ if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || ++ !elems.ssid) { ++ DBG_871X("STA " MAC_FMT " sent invalid association request\n", ++ MAC_ARG(pstat->hwaddr)); ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ ++ ++ // now we should check all the fields... ++ // checking SSID ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, ++ pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p == NULL) ++ { ++ status = _STATS_FAILURE_; ++ } ++ ++ if (ie_len == 0) // broadcast ssid, however it is not allowed in assocreq ++ status = _STATS_FAILURE_; ++ else ++ { ++ // check if ssid match ++ if (!_rtw_memcmp((void *)(p+2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) ++ status = _STATS_FAILURE_; ++ ++ if (ie_len != cur->Ssid.SsidLength) ++ status = _STATS_FAILURE_; ++ } ++ ++ if(_STATS_SUCCESSFUL_ != status) ++ goto OnAssocReqFail; ++ ++ // check if the supported rate is ok ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SUPPORTEDRATES_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p == NULL) { ++ DBG_871X("Rx a sta assoc-req which supported rate is empty!\n"); ++ // use our own rate set as statoin used ++ //_rtw_memcpy(supportRate, AP_BSSRATE, AP_BSSRATE_LEN); ++ //supportRateNum = AP_BSSRATE_LEN; ++ ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ else { ++ _rtw_memcpy(supportRate, p+2, ie_len); ++ supportRateNum = ie_len; ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _EXT_SUPPORTEDRATES_IE_ , &ie_len, ++ pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p != NULL) { ++ ++ if(supportRateNum<=sizeof(supportRate)) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len); ++ supportRateNum += ie_len; ++ } ++ } ++ } ++ ++ //todo: mask supportRate between AP & STA -> move to update raid ++ //get_matched_rate(pmlmeext, supportRate, &supportRateNum, 0); ++ ++ //update station supportRate ++ pstat->bssratelen = supportRateNum; ++ _rtw_memcpy(pstat->bssrateset, supportRate, supportRateNum); ++ UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen); ++ ++ //check RSN/WPA/WPS ++ pstat->dot8021xalg = 0; ++ pstat->wpa_psk = 0; ++ pstat->wpa_group_cipher = 0; ++ pstat->wpa2_group_cipher = 0; ++ pstat->wpa_pairwise_cipher = 0; ++ pstat->wpa2_pairwise_cipher = 0; ++ _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); ++ if((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { ++ ++ int group_cipher=0, pairwise_cipher=0; ++ ++ wpa_ie = elems.rsn_ie; ++ wpa_ie_len = elems.rsn_ie_len; ++ ++ if(rtw_parse_wpa2_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ pstat->dot8021xalg = 1;//psk, todo:802.1x ++ pstat->wpa_psk |= BIT(1); ++ ++ pstat->wpa2_group_cipher = group_cipher&psecuritypriv->wpa2_group_cipher; ++ pstat->wpa2_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa2_pairwise_cipher; ++ ++ if(!pstat->wpa2_group_cipher) ++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; ++ ++ if(!pstat->wpa2_pairwise_cipher) ++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; ++ } ++ else ++ { ++ status = WLAN_STATUS_INVALID_IE; ++ } ++ ++ } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { ++ ++ int group_cipher=0, pairwise_cipher=0; ++ ++ wpa_ie = elems.wpa_ie; ++ wpa_ie_len = elems.wpa_ie_len; ++ ++ if(rtw_parse_wpa_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ pstat->dot8021xalg = 1;//psk, todo:802.1x ++ pstat->wpa_psk |= BIT(0); ++ ++ pstat->wpa_group_cipher = group_cipher&psecuritypriv->wpa_group_cipher; ++ pstat->wpa_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa_pairwise_cipher; ++ ++ if(!pstat->wpa_group_cipher) ++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; ++ ++ if(!pstat->wpa_pairwise_cipher) ++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; ++ ++ } ++ else ++ { ++ status = WLAN_STATUS_INVALID_IE; ++ } ++ ++ } else { ++ wpa_ie = NULL; ++ wpa_ie_len = 0; ++ } ++ ++ if(_STATS_SUCCESSFUL_ != status) ++ goto OnAssocReqFail; ++ ++ pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); ++ //if (hapd->conf->wps_state && wpa_ie == NULL) { //todo: to check ap if supporting WPS ++ if(wpa_ie == NULL) { ++ if (elems.wps_ie) { ++ DBG_871X("STA included WPS IE in " ++ "(Re)Association Request - assume WPS is " ++ "used\n"); ++ pstat->flags |= WLAN_STA_WPS; ++ //wpabuf_free(sta->wps_ie); ++ //sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, ++ // elems.wps_ie_len - 4); ++ } else { ++ DBG_871X("STA did not include WPA/RSN IE " ++ "in (Re)Association Request - possible WPS " ++ "use\n"); ++ pstat->flags |= WLAN_STA_MAYBE_WPS; ++ } ++ ++ ++ // AP support WPA/RSN, and sta is going to do WPS, but AP is not ready ++ // that the selected registrar of AP is _FLASE ++ if((psecuritypriv->wpa_psk >0) ++ && (pstat->flags & (WLAN_STA_WPS|WLAN_STA_MAYBE_WPS))) ++ { ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ u8 selected_registrar = 0; ++ ++ rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); ++ ++ if(!selected_registrar) ++ { ++ DBG_871X("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); ++ ++ status = _STATS_UNABLE_HANDLE_STA_; ++ ++ goto OnAssocReqFail; ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ int copy_len; ++ ++ if(psecuritypriv->wpa_psk == 0) ++ { ++ DBG_871X("STA " MAC_FMT ": WPA/RSN IE in association " ++ "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); ++ ++ status = WLAN_STATUS_INVALID_IE; ++ ++ goto OnAssocReqFail; ++ ++ } ++ ++ if (elems.wps_ie) { ++ DBG_871X("STA included WPS IE in " ++ "(Re)Association Request - WPS is " ++ "used\n"); ++ pstat->flags |= WLAN_STA_WPS; ++ copy_len=0; ++ } ++ else ++ { ++ copy_len = ((wpa_ie_len+2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)):(wpa_ie_len+2); ++ } ++ ++ ++ if(copy_len>0) ++ _rtw_memcpy(pstat->wpa_ie, wpa_ie-2, copy_len); ++ ++ } ++ ++ ++ // check if there is WMM IE & support WWM-PS ++ pstat->flags &= ~WLAN_STA_WME; ++ pstat->qos_option = 0; ++ pstat->qos_info = 0; ++ pstat->has_legacy_ac = _TRUE; ++ pstat->uapsd_vo = 0; ++ pstat->uapsd_vi = 0; ++ pstat->uapsd_be = 0; ++ pstat->uapsd_bk = 0; ++ if (pmlmepriv->qospriv.qos_option) ++ { ++ p = pframe + WLAN_HDR_A3_LEN + ie_offset; ie_len = 0; ++ for (;;) ++ { ++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p != NULL) { ++ if (_rtw_memcmp(p+2, WMM_IE, 6)) { ++ ++ pstat->flags |= WLAN_STA_WME; ++ ++ pstat->qos_option = 1; ++ pstat->qos_info = *(p+8); ++ ++ pstat->max_sp_len = (pstat->qos_info>>5)&0x3; ++ ++ if((pstat->qos_info&0xf) !=0xf) ++ pstat->has_legacy_ac = _TRUE; ++ else ++ pstat->has_legacy_ac = _FALSE; ++ ++ if(pstat->qos_info&0xf) ++ { ++ if(pstat->qos_info&BIT(0)) ++ pstat->uapsd_vo = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_vo = 0; ++ ++ if(pstat->qos_info&BIT(1)) ++ pstat->uapsd_vi = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_vi = 0; ++ ++ if(pstat->qos_info&BIT(2)) ++ pstat->uapsd_bk = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_bk = 0; ++ ++ if(pstat->qos_info&BIT(3)) ++ pstat->uapsd_be = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_be = 0; ++ ++ } ++ ++ break; ++ } ++ } ++ else { ++ break; ++ } ++ p = p + ie_len + 2; ++ } ++ } ++ ++ ++#ifdef CONFIG_80211N_HT ++ /* save HT capabilities in the sta object */ ++ _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) ++ { ++ pstat->flags |= WLAN_STA_HT; ++ ++ pstat->flags |= WLAN_STA_WME; ++ ++ _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ } else ++ pstat->flags &= ~WLAN_STA_HT; ++ ++ ++ if((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags&WLAN_STA_HT)) ++ { ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ ++ ++ if ((pstat->flags & WLAN_STA_HT) && ++ ((pstat->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) || ++ (pstat->wpa_pairwise_cipher&WPA_CIPHER_TKIP))) ++ { ++ DBG_871X("HT: " MAC_FMT " tried to " ++ "use TKIP with HT association\n", MAC_ARG(pstat->hwaddr)); ++ ++ //status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY; ++ //goto OnAssocReqFail; ++ } ++#endif /* CONFIG_80211N_HT */ ++ ++ // ++ //if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G)//? ++ pstat->flags |= WLAN_STA_NONERP; ++ for (i = 0; i < pstat->bssratelen; i++) { ++ if ((pstat->bssrateset[i] & 0x7f) > 22) { ++ pstat->flags &= ~WLAN_STA_NONERP; ++ break; ++ } ++ } ++ ++ if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) ++ pstat->flags |= WLAN_STA_SHORT_PREAMBLE; ++ else ++ pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; ++ ++ ++ ++ if (status != _STATS_SUCCESSFUL_) ++ goto OnAssocReqFail; ++ ++#ifdef CONFIG_P2P ++ pstat->is_p2p_device = _FALSE; ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if( (p2pie=rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen))) ++ { ++ pstat->is_p2p_device = _TRUE; ++ if((p2p_status_code=(u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat))>0) ++ { ++ pstat->p2p_status_code = p2p_status_code; ++ status = _STATS_CAP_FAIL_; ++ goto OnAssocReqFail; ++ } ++ } ++#ifdef CONFIG_WFD ++ if(rtw_get_wfd_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , wfd_ie, &wfd_ielen )) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ } ++ } ++#endif ++ } ++ pstat->p2p_status_code = p2p_status_code; ++#endif //CONFIG_P2P ++ ++ //TODO: identify_proprietary_vendor_ie(); ++ // Realtek proprietary IE ++ // identify if this is Broadcom sta ++ // identify if this is ralink sta ++ // Customer proprietary IE ++ ++ ++ ++ /* get a unique AID */ ++ if (pstat->aid > 0) { ++ DBG_871X(" old AID %d\n", pstat->aid); ++ } else { ++ for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) ++ if (pstapriv->sta_aid[pstat->aid - 1] == NULL) ++ break; ++ ++ //if (pstat->aid > NUM_STA) { ++ if (pstat->aid > pstapriv->max_num_sta) { ++ ++ pstat->aid = 0; ++ ++ DBG_871X(" no room for more AIDs\n"); ++ ++ status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; ++ ++ goto OnAssocReqFail; ++ ++ ++ } else { ++ pstapriv->sta_aid[pstat->aid - 1] = pstat; ++ DBG_871X("allocate new AID = (%d)\n", pstat->aid); ++ } ++ } ++ ++ ++ pstat->state &= (~WIFI_FW_ASSOC_STATE); ++ pstat->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ if (!rtw_is_list_empty(&pstat->auth_list)) ++ { ++ rtw_list_delete(&pstat->auth_list); ++ pstapriv->auth_list_cnt--; ++ } ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if (rtw_is_list_empty(&pstat->asoc_list)) ++ { ++ pstat->expire_to = pstapriv->expire_to; ++ rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list); ++ pstapriv->asoc_list_cnt++; ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ // now the station is qualified to join our BSS... ++ if(pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_==status)) ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ //.1 bss_cap_update & sta_info_update ++ bss_cap_update_on_sta_join(padapter, pstat); ++ sta_info_update(padapter, pstat); ++ ++ //.2 issue assoc rsp before notify station join event. ++ if (frame_type == WIFI_ASSOCREQ) ++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); ++ else ++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ _enter_critical_bh(&pstat->lock, &irqL); ++ if(pstat->passoc_req) ++ { ++ rtw_mfree(pstat->passoc_req, pstat->assoc_req_len); ++ pstat->passoc_req = NULL; ++ pstat->assoc_req_len = 0; ++ } ++ ++ pstat->passoc_req = rtw_zmalloc(pkt_len); ++ if(pstat->passoc_req) ++ { ++ _rtw_memcpy(pstat->passoc_req, pframe, pkt_len); ++ pstat->assoc_req_len = pkt_len; ++ } ++ _exit_critical_bh(&pstat->lock, &irqL); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ //.3-(1) report sta add event ++ report_add_sta_event(padapter, pstat->hwaddr, pstat->aid); ++ ++#endif //CONFIG_NATIVEAP_MLME ++ } ++ ++ return _SUCCESS; ++ ++asoc_class2_error: ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status); ++#endif ++ ++ return _FAIL; ++ ++OnAssocReqFail: ++ ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ pstat->aid = 0; ++ if (frame_type == WIFI_ASSOCREQ) ++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); ++ else ++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); ++#endif ++ ++ ++#endif /* CONFIG_AP_MODE */ ++ ++ return _FAIL; ++ ++} ++ ++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ uint i; ++ int res; ++ unsigned short status; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++ PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++ ++ if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) ++ return _SUCCESS; ++ ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ return _SUCCESS; ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //status ++ if ((status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2))) > 0) ++ { ++ DBG_871X("assoc reject, status code: %d\n", status); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ res = -4; ++ goto report_assoc_result; ++ } ++ ++ //get capabilities ++ pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ //set slot time ++ pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10))? 9: 20; ++ ++ //AID ++ res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4))&0x3fff); ++ ++ //following are moved to join event callback function ++ //to handle HT, WMM, rate adaptive, update MAC reg ++ //for not to handle the synchronous IO in the tasklet ++ for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM ++ { ++ WMM_param_handler(padapter, pIE); ++ } ++#if defined(CONFIG_P2P) && defined(CONFIG_WFD) ++ else if ( _rtw_memcmp(pIE->data, WFD_OUI, 4)) //WFD ++ { ++ DBG_871X( "[%s] Found WFD IE\n", __FUNCTION__ ); ++ WFD_info_handler( padapter, pIE ); ++ } ++#endif ++ break; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ case _WAPI_IE_: ++ pWapiIE = pIE; ++ break; ++#endif ++ ++ case _HT_CAPABILITY_IE_: //HT caps ++ HT_caps_handler(padapter, pIE); ++ break; ++ ++ case _HT_EXTRA_INFO_IE_: //HT info ++ HT_info_handler(padapter, pIE); ++ break; ++ ++ case _ERPINFO_IE_: ++ ERP_IE_handler(padapter, pIE); ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_on_assoc_ok(padapter, pIE); ++#endif ++ ++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE); ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ //Update Basic Rate Table for spec, 2010-12-28 , by thomas ++ UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates); ++ ++report_assoc_result: ++ if (res > 0) { ++ rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len); ++ } else { ++ rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); ++ } ++ ++ report_join_res(padapter, res); ++ ++ return _SUCCESS; ++} ++ ++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned short reason; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ //check A3 ++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++#ifdef CONFIG_P2P ++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ++ { ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); ++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); ++ } ++#endif //CONFIG_P2P ++ ++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason); ++ ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _irqL irqL; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ //rtw_free_stainfo(padapter, psta); ++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ DBG_871X_LEVEL(_drv_always_, "ap recv deauth reason code(%d) sta:%pM\n", ++ reason, GetAddr2Ptr(pframe)); ++ ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if(psta) ++ { ++ u8 updated; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ updated = ap_free_sta(padapter, psta, _FALSE, reason); ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ associated_clients_update(padapter, updated); ++ } ++ ++ ++ return _SUCCESS; ++ } ++ else ++#endif ++ { ++ int ignore_received_deauth = 0; ++ ++ // Commented by Albert 20130604 ++ // Before sending the auth frame to start the STA/GC mode connection with AP/GO, ++ // we will send the deauth first. ++ // However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. ++ // Added the following code to avoid this case. ++ if ( ( pmlmeinfo->state & WIFI_FW_AUTH_STATE ) || ++ ( pmlmeinfo->state & WIFI_FW_ASSOC_STATE ) ) ++ { ++ if ( reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA ) ++ { ++ ignore_received_deauth = 1; ++ } else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) { ++ // TODO: 802.11r ++ ignore_received_deauth = 1; ++ } ++ } ++ ++ DBG_871X_LEVEL(_drv_always_, "sta recv deauth reason code(%d) sta:%pM, ignore = %d\n", ++ reason, GetAddr3Ptr(pframe), ignore_received_deauth); ++ ++ if ( 0 == ignore_received_deauth ) ++ { ++ receive_disconnect(padapter, GetAddr3Ptr(pframe) ,reason); ++ } ++ } ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned short reason; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ //check A3 ++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++#ifdef CONFIG_P2P ++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ++ { ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); ++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); ++ } ++#endif //CONFIG_P2P ++ ++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason); ++ ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _irqL irqL; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ //rtw_free_stainfo(padapter, psta); ++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ DBG_871X_LEVEL(_drv_always_, "ap recv disassoc reason code(%d) sta:%pM\n", ++ reason, GetAddr2Ptr(pframe)); ++ ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if(psta) ++ { ++ u8 updated; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ updated = ap_free_sta(padapter, psta, _FALSE, reason); ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ associated_clients_update(padapter, updated); ++ } ++ ++ return _SUCCESS; ++ } ++ else ++#endif ++ { ++ DBG_871X_LEVEL(_drv_always_, "ap recv disassoc reason code(%d) sta:%pM\n", ++ reason, GetAddr3Ptr(pframe)); ++ ++ receive_disconnect(padapter, GetAddr3Ptr(pframe), reason); ++ } ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ return _SUCCESS; ++} ++ ++unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len) ++{ ++ unsigned int ret = _FAIL; ++ struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(mlmeext->mlmext_info); ++ ++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { ++ ret = _SUCCESS; ++ goto exit; ++ } ++ ++ if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { ++ ++ int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1; ++ int ch_offset = -1; ++ u8 bwmode; ++ struct ieee80211_info_element *ie; ++ ++ DBG_871X(FUNC_NDEV_FMT" from "MAC_FMT"\n", ++ FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr)); ++ ++ for_each_ie(ie, ies, ies_len) { ++ if (ie->id == WLAN_EID_CHANNEL_SWITCH) { ++ ch_switch_mode = ie->data[0]; ++ ch = ie->data[1]; ++ ch_switch_cnt = ie->data[2]; ++ DBG_871X("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n", ++ ch_switch_mode, ch, ch_switch_cnt); ++ } ++ else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) { ++ ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]); ++ DBG_871X("ch_offset:%d\n", ch_offset); ++ } ++ } ++ ++ if (ch == -1) ++ return _SUCCESS; ++ ++ if (ch_offset == -1) ++ bwmode = mlmeext->cur_bwmode; ++ else ++ bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ? ++ HT_CHANNEL_WIDTH_20 : HT_CHANNEL_WIDTH_40; ++ ++ ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset; ++ ++ /* todo: ++ * 1. the decision of channel switching ++ * 2. things after channel switching ++ */ ++ ++ ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE); ++ } ++ ++exit: ++ return ret; ++} ++ ++unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int ret = _FAIL; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint frame_len = precv_frame->u.hdr.len; ++ u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ u8 category; ++ u8 action; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); ++ ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ ++ if (!psta) ++ goto exit; ++ ++ category = frame_body[0]; ++ if(category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT) ++ goto exit; ++ ++ action = frame_body[1]; ++ switch (action) { ++ case RTW_WLAN_ACTION_SPCT_MSR_REQ: ++ case RTW_WLAN_ACTION_SPCT_MSR_RPRT: ++ case RTW_WLAN_ACTION_SPCT_TPC_REQ: ++ case RTW_WLAN_ACTION_SPCT_TPC_RPRT: ++ break; ++ case RTW_WLAN_ACTION_SPCT_CHL_SWITCH: ++ #ifdef CONFIG_SPCT_CH_SWITCH ++ ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2], ++ frame_len-(frame_body-pframe)-2); ++ #endif ++ break; ++ default: ++ break; ++ } ++ ++exit: ++ return ret; ++} ++ ++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ u8 *addr; ++ struct sta_info *psta=NULL; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ unsigned char *frame_body; ++ unsigned char category, action; ++ unsigned short tid, status, reason_code = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++#ifdef CONFIG_80211N_HT ++ //check RA matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode ++ return _SUCCESS; ++ ++/* ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++*/ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ return _SUCCESS; ++ ++ addr = GetAddr2Ptr(pframe); ++ psta = rtw_get_stainfo(pstapriv, addr); ++ ++ if(psta==NULL) ++ return _SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ if (category == RTW_WLAN_CATEGORY_BACK)// representing Block Ack ++ { ++#ifdef CONFIG_TDLS ++ if((psta->tdls_sta_state & TDLS_LINKED_STATE) && ++ (psta->htpriv.ht_option==_TRUE) && ++ (psta->htpriv.ampdu_enable==_TRUE) ) ++ { ++ //do nothing; just don't want to return _SUCCESS; ++ } ++ else ++#endif //CONFIG_TDLS ++ if (!pmlmeinfo->HT_enable) ++ { ++ return _SUCCESS; ++ } ++ ++ action = frame_body[1]; ++ DBG_871X("%s, action=%d\n", __FUNCTION__, action); ++ switch (action) ++ { ++ case RTW_WLAN_ACTION_ADDBA_REQ: //ADDBA request ++ ++ _rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request)); ++ //process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); ++ process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), addr); ++ ++ if(pmlmeinfo->bAcceptAddbaReq == _TRUE) ++ { ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 0); ++ } ++ else ++ { ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 37);//reject ADDBA Req ++ } ++ ++ break; ++ ++ case RTW_WLAN_ACTION_ADDBA_RESP: //ADDBA response ++ ++ //status = frame_body[3] | (frame_body[4] << 8); //endian issue ++ status = RTW_GET_LE16(&frame_body[3]); ++ tid = ((frame_body[5] >> 2) & 0x7); ++ ++ if (status == 0) ++ { //successful ++ DBG_871X("agg_enable for TID=%d\n", tid); ++ psta->htpriv.agg_enable_bitmap |= 1 << tid; ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); ++ } ++ else ++ { ++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid); ++ } ++ ++ //DBG_871X("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); ++ break; ++ ++ case RTW_WLAN_ACTION_DELBA: //DELBA ++ if ((frame_body[3] & BIT(3)) == 0) ++ { ++ psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); ++ psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); ++ ++ //reason_code = frame_body[4] | (frame_body[5] << 8); ++ reason_code = RTW_GET_LE16(&frame_body[4]); ++ } ++ else if((frame_body[3] & BIT(3)) == BIT(3)) ++ { ++ tid = (frame_body[3] >> 4) & 0x0F; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[tid]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ } ++ ++ DBG_871X("%s(): DELBA: %x(%x)\n", __FUNCTION__,pmlmeinfo->agg_enable_bitmap, reason_code); ++ //todo: how to notify the host while receiving DELETE BA ++ break; ++ ++ default: ++ break; ++ } ++ } ++#endif //CONFIG_80211N_HT ++ return _SUCCESS; ++} ++ ++#ifdef CONFIG_P2P ++ ++static int get_reg_classes_full_count(struct p2p_channels channel_list) { ++ int cnt = 0; ++ int i; ++ ++ for (i = 0; i < channel_list.reg_classes; i++) { ++ cnt += channel_list.reg_class[i].channels; ++ } ++ ++ return cnt; ++} ++ ++static void get_channel_cnt_24g_5gl_5gh( struct mlme_ext_priv *pmlmeext, u8* p24g_cnt, u8* p5gl_cnt, u8* p5gh_cnt ) ++{ ++ int i = 0; ++ ++ *p24g_cnt = 0; ++ *p5gl_cnt = 0; ++ *p5gh_cnt = 0; ++ ++ for( i = 0; i < pmlmeext->max_chan_nums; i++ ) ++ { ++ if ( pmlmeext->channel_set[ i ].ChannelNum <= 14 ) ++ { ++ (*p24g_cnt)++; ++ } ++ else if ( ( pmlmeext->channel_set[ i ].ChannelNum > 14 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 48 ) ) ++ { ++ // Just include the channel 36, 40, 44, 48 channels for 5G low ++ (*p5gl_cnt)++; ++ } ++ else if ( ( pmlmeext->channel_set[ i ].ChannelNum >= 149 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 161 ) ) ++ { ++ // Just include the channel 149, 153, 157, 161 channels for 5G high ++ (*p5gh_cnt)++; ++ } ++ } ++} ++ ++void issue_p2p_GO_request(_adapter *padapter, u8* raddr) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_REQ; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 wpsielen = 0, p2pielen = 0, i; ++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; ++ u16 len_channellist_attr = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pwdinfo->negotiation_dialog_token = 1; // Initialize the dialog value ++ pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen)); ++ ++ ++ ++ // WPS Section ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Device Password ID ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); ++ } ++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); ++ } ++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); ++ } ++ ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110306 ++ // According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes ++ // 1. P2P Capability ++ // 2. Group Owner Intent ++ // 3. Configuration Timeout ++ // 4. Listen Channel ++ // 5. Extended Listen Timing ++ // 6. Intended P2P Interface Address ++ // 7. Channel List ++ // 8. P2P Device Info ++ // 9. Operating Channel ++ ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; ++ } ++ ++ ++ // Group Owner Intent ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Todo the tie breaker bit. ++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) ); ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ ++ // Listen Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listening channel number ++ ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ ++ // Intended P2P Interface Address ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ // Country String(3) ++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) ++ // + number of channels in all classes ++ len_channellist_attr = 3 ++ + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes) ++ + get_reg_classes_full_count(pmlmeext->channel_list); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ } ++#else ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ ++#endif ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ // Operating Class ++ if ( pbuddy_mlmeext->cur_channel > 14 ) ++ { ++ if ( pbuddy_mlmeext->cur_channel >= 149 ) ++ { ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ ++ // Number of Channels ++ // Just support 1 channel and this channel is AP's channel ++ p2pie[ p2pielen++ ] = 1; ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; ++ } ++ else ++ { ++ int i,j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#else // CONFIG_CONCURRENT_MODE ++ { ++ int i,j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ if ( pwdinfo->operating_channel <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++ ++void issue_p2p_GO_response(_adapter *padapter, u8* raddr, u8* frame_body,uint len, u8 result) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_RESP; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0, i; ++ uint wpsielen = 0; ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh; ++ u16 len_channellist_attr = 0; ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_871X( "[%s] In, result = %d\n", __FUNCTION__, result ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pwdinfo->negotiation_dialog_token = frame_body[7]; // The Dialog Token of provisioning discovery request frame. ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); ++ ++ // Commented by Albert 20110328 ++ // Try to get the device password ID from the WPS IE of group negotiation request frame ++ // WiFi Direct test plan 5.1.15 ++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); ++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ _rtw_memset( wpsie, 0x00, 255 ); ++ wpsielen = 0; ++ ++ // WPS Section ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Device Password ID ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); ++ } ++ else ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); ++ } ++ wpsielen += 2; ++ ++ // Commented by Kurt 20120113 ++ // If some device wants to do p2p handshake without sending prov_disc_req ++ // We have to get peer_req_cm from here. ++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) ++ { ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ } ++ else ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ } ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20100908 ++ // According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes ++ // 1. Status ++ // 2. P2P Capability ++ // 3. Group Owner Intent ++ // 4. Configuration Timeout ++ // 5. Operating Channel ++ // 6. Intended P2P Interface Address ++ // 7. Channel List ++ // 8. Device Info ++ // 9. Group ID ( Only GO ) ++ ++ ++ // ToDo: ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = result; ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ // Commented by Albert 2011/03/08 ++ // According to the P2P specification ++ // if the sending device will be client, the P2P Capability should be reserved of group negotation response frame ++ p2pie[ p2pielen++ ] = 0; ++ } ++ else ++ { ++ // Be group owner or meet the error case ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ } ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; ++ } ++ ++ // Group Owner Intent ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ if ( pwdinfo->peer_intent & 0x01 ) ++ { ++ // Peer's tie breaker bit is 1, our tie breaker bit should be 0 ++ p2pie[ p2pielen++ ] = ( pwdinfo->intent << 1 ); ++ } ++ else ++ { ++ // Peer's tie breaker bit is 0, our tie breaker bit should be 1 ++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) ); ++ } ++ ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ if ( pwdinfo->operating_channel <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ // Intended P2P Interface Address ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Country String(3) ++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) ++ // + number of channels in all classes ++ len_channellist_attr = 3 ++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes ++ + get_reg_classes_full_count(pmlmeext->channel_list); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ } ++#else ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ ++ #endif ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ // Operating Class ++ if ( pbuddy_mlmeext->cur_channel > 14 ) ++ { ++ if ( pbuddy_mlmeext->cur_channel >= 149 ) ++ { ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ ++ // Number of Channels ++ // Just support 1 channel and this channel is AP's channel ++ p2pie[ p2pielen++ ] = 1; ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; ++ } ++ else ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#else // CONFIG_CONCURRENT_MODE ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Group ID Attribute ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // p2P Device Address ++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ p2pielen += pwdinfo->nego_ssidlen; ++ ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_GO_confirm(_adapter *padapter, u8* raddr, u8 result) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_CONF; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 wpsielen = 0, p2pielen = 0; ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); ++ ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110306 ++ // According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes ++ // 1. Status ++ // 2. P2P Capability ++ // 3. Operating Channel ++ // 4. Channel List ++ // 5. Group ID ( if this WiFi is GO ) ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = result; ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; ++ } ++ ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ if ( pwdinfo->peer_operating_ch <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ ++ p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch; ++ } ++ else ++ { ++ if ( pwdinfo->operating_channel <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel ++ } ++ ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ *(u16*) ( p2pie + p2pielen ) = 6; ++ p2pielen += 2; ++ ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Value: ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ if ( pwdinfo->peer_operating_ch <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ p2pie[ p2pielen++ ] = 1; ++ p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch; ++ } ++ else ++ { ++ if ( pwdinfo->operating_channel <= 14 ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ else ++ { ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = 1; ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel ++ } ++ ++ if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Group ID Attribute ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // p2P Device Address ++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ p2pielen += pwdinfo->nego_ssidlen; ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_invitation_request(_adapter *padapter, u8* raddr ) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_INVIT_REQ; ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0, i; ++ u8 dialogToken = 3; ++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; ++ u16 len_channellist_attr = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101011 ++ // According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes ++ // 1. Configuration Timeout ++ // 2. Invitation Flags ++ // 3. Operating Channel ( Only GO ) ++ // 4. P2P Group BSSID ( Should be included if I am the GO ) ++ // 5. Channel List ++ // 6. P2P Group ID ++ // 7. P2P Device Info ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ // Invitation Flags ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INVITATION_FLAGS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = P2P_INVITATION_FLAGS_PERSISTENT; ++ ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ if ( pwdinfo->invitereq_info.operating_ch <= 14 ) ++ p2pie[ p2pielen++ ] = 0x51; ++ else if ( ( pwdinfo->invitereq_info.operating_ch >= 36 ) && ( pwdinfo->invitereq_info.operating_ch <= 48 ) ) ++ p2pie[ p2pielen++ ] = 0x73; ++ else ++ p2pie[ p2pielen++ ] = 0x7c; ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->invitereq_info.operating_ch; // operating channel number ++ ++ if ( _rtw_memcmp( myid( &padapter->eeprompriv ), pwdinfo->invitereq_info.go_bssid, ETH_ALEN ) ) ++ { ++ // P2P Group BSSID ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address for GO ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ } ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ ++ // Length: ++ // Country String(3) ++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) ++ // + number of channels in all classes ++ len_channellist_attr = 3 ++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes ++ + get_reg_classes_full_count(pmlmeext->channel_list); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ } ++#else ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ ++ #endif ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ // Operating Class ++ if ( pbuddy_mlmeext->cur_channel > 14 ) ++ { ++ if ( pbuddy_mlmeext->cur_channel >= 149 ) ++ { ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ ++ // Number of Channels ++ // Just support 1 channel and this channel is AP's channel ++ p2pie[ p2pielen++ ] = 1; ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; ++ } ++ else ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#else // CONFIG_CONCURRENT_MODE ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ ++ // P2P Group ID ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 6 + pwdinfo->invitereq_info.ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address for GO ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen ); ++ p2pielen += pwdinfo->invitereq_info.ssidlen; ++ ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 status_code) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_INVIT_RESP; ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0, i; ++ u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; ++ u16 len_channellist_attr = 0; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101005 ++ // According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes ++ // 1. Status ++ // 2. Configuration Timeout ++ // 3. Operating Channel ( Only GO ) ++ // 4. P2P Group BSSID ( Only GO ) ++ // 5. Channel List ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ // When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. ++ // Sent the event receiving the P2P Invitation Req frame to DMP UI. ++ // DMP had to compare the MAC address to find out the profile. ++ // So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. ++ // If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req ++ // to NB to rebuild the persistent group. ++ p2pie[ p2pielen++ ] = status_code; ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ if( status_code == P2P_STATUS_SUCCESS ) ++ { ++ if( rtw_p2p_chk_role( pwdinfo, P2P_ROLE_GO ) ) ++ { ++ // The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO ++ // In this case, the P2P Invitation response frame should carry the two more P2P attributes. ++ // First one is operating channel attribute. ++ // Second one is P2P Group BSSID attribute. ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ ++ // P2P Group BSSID ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address for GO ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ } ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ // Country String(3) ++ // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) ++ // + number of channels in all classes ++ len_channellist_attr = 3 ++ + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes ++ + get_reg_classes_full_count(pmlmeext->channel_list); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ } ++#else ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); ++ ++#endif ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ // Operating Class ++ if ( pbuddy_mlmeext->cur_channel > 14 ) ++ { ++ if ( pbuddy_mlmeext->cur_channel >= 149 ) ++ { ++ p2pie[ p2pielen++ ] = 0x7c; ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x73; ++ } ++ } ++ else ++ { ++ p2pie[ p2pielen++ ] = 0x51; ++ } ++ ++ // Number of Channels ++ // Just support 1 channel and this channel is AP's channel ++ p2pie[ p2pielen++ ] = 1; ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; ++ } ++ else ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#else // CONFIG_CONCURRENT_MODE ++ { ++ int i, j; ++ for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { ++ // Operating Class ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; ++ ++ // Number of Channels ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; ++ ++ // Channel List ++ for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { ++ p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; ++ } ++ } ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_provision_request(_adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr ) ++{ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = 1; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_REQ; ++ u8 wpsie[ 100 ] = { 0x00 }; ++ u8 wpsielen = 0; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, pssid, ussidlen, pdev_raddr ); ++ ++ pframe += p2pielen; ++ pattrib->pktlen += p2pielen; ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++ ++u8 is_matched_in_profilelist( u8* peermacaddr, struct profile_info* profileinfo ) ++{ ++ u8 i, match_result = 0; ++ ++ DBG_871X( "[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]); ++ ++ for( i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++ ) ++ { ++ DBG_871X( "[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]); ++ if ( _rtw_memcmp( peermacaddr, profileinfo->peermac, ETH_ALEN ) ) ++ { ++ match_result = 1; ++ DBG_871X( "[%s] Match!\n", __FUNCTION__ ); ++ break; ++ } ++ } ++ ++ return (match_result ); ++} ++ ++void issue_probersp_p2p(_adapter *padapter, unsigned char *da) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u16 beacon_interval = 100; ++ u16 capInfo = 0; ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 wpsie[255] = { 0x00 }; ++ u32 wpsielen = 0, p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#ifdef CONFIG_INTEL_WIDI ++ u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 }; ++#endif //CONFIG_INTEL_WIDI ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ // Use the device address for BSSID field. ++ _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ // ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) ++ capInfo |= cap_ShortPremble; ++ capInfo |= cap_ShortSlot; ++ ++ _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ // Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if( pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL ) ++ { ++ //WPS IE ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); ++ pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len; ++ pframe += pmlmepriv->wps_probe_resp_ie_len; ++ ++ //P2P IE ++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); ++ pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len; ++ pframe += pmlmepriv->p2p_probe_resp_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ ++ // Todo: WPS IE ++ // Noted by Albert 20100907 ++ // According to the WPS specification, all the WPS attribute is presented by Big Endian. ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++#ifdef CONFIG_INTEL_WIDI ++ // Commented by Kurt ++ // Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext. ++ if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE ++ || pmlmepriv->num_p2p_sdt != 0 ) ++ { ++ //Sec dev type ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SEC_DEV_TYPE_LIST ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); ++ wpsielen += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_DISPLAYS ); ++ wpsielen += 2; ++ ++ // OUI ++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( INTEL_DEV_TYPE_OUI ); ++ wpsielen += 4; ++ ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_WIDI_CONSUMER_SINK ); ++ wpsielen += 2; ++ ++ if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE ) ++ { ++ // Vendor Extension ++ _rtw_memcpy( wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN ); ++ wpsielen += L2SDTA_SERVICE_VE_LEN; ++ } ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++ // WiFi Simple Config State ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SIMPLE_CONF_STATE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; // Not Configured. ++ ++ // Response Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_RESP_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X; ++ ++ // UUID-E ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 ); ++ wpsielen += 2; ++ ++ // Value: ++ if (pwdinfo->external_uuid == 0) { ++ _rtw_memset( wpsie + wpsielen, 0x0, 16 ); ++ _rtw_memcpy( wpsie + wpsielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ } else { ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 ); ++ } ++ wpsielen += 0x10; ++ ++ // Manufacturer ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MANUFACTURER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0007 ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "Realtek", 7 ); ++ wpsielen += 7; ++ ++ // Model Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0006 ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "8192CU", 6 ); ++ wpsielen += 6; ++ ++ // Model Number ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NUMBER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[ wpsielen++ ] = 0x31; // character 1 ++ ++ // Serial Number ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SERIAL_NUMBER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( ETH_ALEN ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "123456" , ETH_ALEN ); ++ wpsielen += ETH_ALEN; ++ ++ // Primary Device Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); ++ wpsielen += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ wpsielen += 2; ++ ++ // OUI ++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ wpsielen += 2; ++ ++ // Device Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ wpsielen += 2; ++ ++ // Value: ++ if (pwdinfo->device_name_len) ++ { ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ wpsielen += pwdinfo->device_name_len; ++ } ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ wpsielen += 2; ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe); ++ pframe += p2pielen; ++ pattrib->pktlen += p2pielen; ++ } ++ ++#ifdef CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable ) ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 0); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else if (pmlmepriv->wfd_probe_resp_ie != NULL && pmlmepriv->wfd_probe_resp_ie_len>0) ++ { ++ //WFD IE ++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, pmlmepriv->wfd_probe_resp_ie_len); ++ pattrib->pktlen += pmlmepriv->wfd_probe_resp_ie_len; ++ pframe += pmlmepriv->wfd_probe_resp_ie_len; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) ++{ ++ int ret = _FAIL; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ unsigned char bssrate[NumRates]; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 wpsie[255] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u16 wpsielen = 0, p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if (da) { ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); ++ } else { ++ if ( ( pwdinfo->p2p_info.scan_op_ch_only ) || ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ) ++ { ++ // This two flags will be set when this is only the P2P client mode. ++ _rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); ++ } ++ else ++ { ++ // broadcast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); ++ } ++ } ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_PROBEREQ); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); ++ } ++ // Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if( pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL ) ++ { ++ //WPS IE ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; ++ pframe += pmlmepriv->wps_probe_req_ie_len; ++ ++ //P2P IE ++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len; ++ pframe += pmlmepriv->p2p_probe_req_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ ++ // WPS IE ++ // Noted by Albert 20110221 ++ // According to the WPS specification, all the WPS attribute is presented by Big Endian. ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ if( pmlmepriv->wps_probe_req_ie == NULL ) ++ { ++ // UUID-E ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 ); ++ wpsielen += 2; ++ ++ // Value: ++ if (pwdinfo->external_uuid == 0) { ++ _rtw_memset( wpsie + wpsielen, 0x0, 16 ); ++ _rtw_memcpy( wpsie + wpsielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ } else { ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 ); ++ } ++ wpsielen += 0x10; ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ wpsielen += 2; ++ } ++ ++ // Device Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ wpsielen += pwdinfo->device_name_len; ++ ++ // Primary Device Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); ++ wpsielen += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ wpsielen += 2; ++ ++ // OUI ++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ wpsielen += 2; ++ ++ // Device Password ID ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); // Registrar-specified ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110221 ++ // According to the P2P Specification, the probe request frame should contain 5 P2P attributes ++ // 1. P2P Capability ++ // 2. P2P Device ID if this probe request wants to find the specific P2P device ++ // 3. Listen Channel ++ // 4. Extended Listen Timing ++ // 5. Operating Channel if this WiFi is working as the group owner now ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; ++ else ++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; ++ ++ // Listen Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listen channel ++ ++ ++ // Extended Listen Timing ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Operating Channel (if this WiFi is working as the group owner now) ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'X'; ++ p2pie[ p2pielen++ ] = 'X'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++ if( pmlmepriv->wps_probe_req_ie != NULL ) ++ { ++ //WPS IE ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; ++ pframe += pmlmepriv->wps_probe_req_ie_len; ++ } ++ } ++ ++#ifdef CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable ) ++#endif ++ { ++ wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else if (pmlmepriv->wfd_probe_req_ie != NULL && pmlmepriv->wfd_probe_req_ie_len>0) ++ { ++ //WFD IE ++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_req_ie, pmlmepriv->wfd_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->wfd_probe_req_ie_len; ++ pframe += pmlmepriv->wfd_probe_req_ie_len; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); ++ ++ if (wait_ack) { ++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); ++ } else { ++ dump_mgntframe(padapter, pmgntframe); ++ ret = _SUCCESS; ++ } ++ ++exit: ++ return ret; ++} ++ ++inline void issue_probereq_p2p(_adapter *adapter, u8 *da) ++{ ++ _issue_probereq_p2p(adapter, da, _FALSE); ++} ++ ++int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) ++{ ++ int ret; ++ int i = 0; ++ u32 start = rtw_get_current_time(); ++ ++ do ++ { ++ ret = _issue_probereq_p2p(adapter, da, wait_ms>0?_TRUE:_FALSE); ++ ++ i++; ++ ++ if (adapter->bDriverStopped || adapter->bSurpriseRemoved) ++ break; ++ ++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL) ++ rtw_msleep_os(wait_ms); ++ ++ }while((iu.hdr.adapter; ++ struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); ++ u8 *frame = recv_frame->u.hdr.rx_data; ++ u16 seq_ctrl = ( (recv_frame->u.hdr.attrib.seq_num&0xffff) << 4) | ++ (recv_frame->u.hdr.attrib.frag_num & 0xf); ++ ++ if (GetRetry(frame)) { ++ if (token >= 0) { ++ if ((seq_ctrl == mlmeext->action_public_rxseq) ++ && (token == mlmeext->action_public_dialog_token)) ++ { ++ DBG_871X(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n", ++ FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token); ++ return _FAIL; ++ } ++ } else { ++ if (seq_ctrl == mlmeext->action_public_rxseq) { ++ DBG_871X(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x\n", ++ FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq); ++ return _FAIL; ++ } ++ } ++ } ++ ++ mlmeext->action_public_rxseq = seq_ctrl; ++ ++ if (token >= 0) ++ mlmeext->action_public_dialog_token = token; ++ ++ return _SUCCESS; ++} ++ ++unsigned int on_action_public_p2p(union recv_frame *precv_frame) ++{ ++ _adapter *padapter = precv_frame->u.hdr.adapter; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ u8 *frame_body; ++ u8 dialogToken=0; ++#ifdef CONFIG_P2P ++ u8 *p2p_ie; ++ u32 p2p_ielen, wps_ielen; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 result = P2P_STATUS_SUCCESS; ++ u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++ u8 *merged_p2pie = NULL; ++ u32 merged_p2p_ielen = 0; ++#endif //CONFIG_P2P ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ dialogToken = frame_body[7]; ++ ++ if (rtw_action_public_decache(precv_frame, dialogToken) == _FAIL) ++ return _FAIL; ++ ++#ifdef CONFIG_P2P ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) ++ { ++ rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ // Do nothing if the driver doesn't enable the P2P function. ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ return _SUCCESS; ++ ++ len -= sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ switch( frame_body[ 6 ] )//OUI Subtype ++ { ++ case P2P_GO_NEGO_REQ: ++ { ++ DBG_871X( "[%s] Got GO Nego Req Frame\n", __FUNCTION__); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) ++ { ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ } ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) ++ { ++ // Commented by Albert 20110526 ++ // In this case, this means the previous nego fail doesn't be reset yet. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ // Restore the previous p2p state ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ DBG_871X( "[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ // Commented by Kurt 20110902 ++ //Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ ++ // Commented by Kurt 20120113 ++ // Get peer_dev_addr here if peer doesn't issue prov_disc frame. ++ if( _rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN) ); ++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); ++ ++ result = process_p2p_group_negotation_req( pwdinfo, frame_body, len ); ++ issue_p2p_GO_response( padapter, GetAddr2Ptr(pframe), frame_body, len, result ); ++#ifdef CONFIG_INTEL_WIDI ++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) ) ++ { ++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; ++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); ++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL); ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++ // Commented by Albert 20110718 ++ // No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. ++#ifdef CONFIG_CONCURRENT_MODE ++ // Commented by Albert 20120107 ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); ++#else // CONFIG_CONCURRENT_MODE ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); ++#endif // CONFIG_CONCURRENT_MODE ++ break; ++ } ++ case P2P_GO_NEGO_RESP: ++ { ++ DBG_871X( "[%s] Got GO Nego Resp Frame\n", __FUNCTION__); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ // Commented by Albert 20110425 ++ // The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ pwdinfo->nego_req_info.benable = _FALSE; ++ result = process_p2p_group_negotation_resp( pwdinfo, frame_body, len); ++ issue_p2p_GO_confirm( pwdinfo->padapter, GetAddr2Ptr(pframe), result); ++ if ( P2P_STATUS_SUCCESS == result ) ++ { ++ if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT ) ++ { ++ pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch; ++ #ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1; ++ pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6; ++ pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11; ++ #endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.scan_op_ch_only = 1; ++ _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH ); ++ } ++ } ++ ++ // Reset the dialog token for group negotiation frames. ++ pwdinfo->negotiation_dialog_token = 1; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__); ++ } ++ ++ break; ++ } ++ case P2P_GO_NEGO_CONF: ++ { ++ DBG_871X( "[%s] Got GO Nego Confirm Frame\n", __FUNCTION__); ++ result = process_p2p_group_negotation_confirm( pwdinfo, frame_body, len); ++ if ( P2P_STATUS_SUCCESS == result ) ++ { ++ if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT ) ++ { ++ pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch; ++ #ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1; ++ pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6; ++ pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11; ++ #endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.scan_op_ch_only = 1; ++ _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH ); ++ } ++ } ++ break; ++ } ++ case P2P_INVIT_REQ: ++ { ++ // Added by Albert 2010/10/05 ++ // Received the P2P Invite Request frame. ++ ++ DBG_871X( "[%s] Got invite request frame!\n", __FUNCTION__ ); ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ // Parse the necessary information from the P2P Invitation Request frame. ++ // For example: The MAC address of sending this P2P Invitation Request frame. ++ u32 attr_contentlen = 0; ++ u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ struct group_id_info group_id; ++ u8 invitation_flag = 0; ++ ++ ++ merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_); ++ ++ merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2); // 2 is for EID and Length ++ if (merged_p2pie == NULL) ++ { ++ DBG_871X( "[%s] Malloc p2p ie fail\n", __FUNCTION__); ++ goto exit; ++ } ++ _rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen); ++ ++ merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie); ++ ++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ ++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen); ++ // Commented by Albert 20120510 ++ // Copy to the pwdinfo->p2p_peer_interface_addr. ++ // So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. ++ // #> iwpriv wlan0 p2p_get peer_ifa ++ // After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. ++ ++ if ( attr_contentlen ) ++ { ++ DBG_871X( "[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], ++ pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3], ++ pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5] ); ++ } ++ ++ if ( invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT ) ++ { ++ // Re-invoke the persistent group. ++ ++ _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) ); ++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ if ( _rtw_memcmp( group_id.go_device_addr, myid( &padapter->eeprompriv ), ETH_ALEN ) ) ++ { ++ // The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_GO ); ++ status_code = P2P_STATUS_SUCCESS; ++ } ++ else ++ { ++ // The p2p device sending this p2p invitation request wants to be the persistent GO. ++ if ( is_matched_in_profilelist( pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[ 0 ] ) ) ++ { ++ u8 operatingch_info[5] = { 0x00 }; ++ ++ if ( rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) ++ { ++ if( rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4] ) ) ++ { ++ // The operating channel is acceptable for this device. ++ pwdinfo->rx_invitereq_info.operation_ch[0]= operatingch_info[4]; ++ #ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.operation_ch[1]= 1; //Check whether GO is operating in channel 1; ++ pwdinfo->rx_invitereq_info.operation_ch[2]= 6; //Check whether GO is operating in channel 6; ++ pwdinfo->rx_invitereq_info.operation_ch[3]= 11; //Check whether GO is operating in channel 11; ++ #endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 1; ++ _set_timer( &pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); ++ status_code = P2P_STATUS_SUCCESS; ++ } ++ else ++ { ++ // The operating channel isn't supported by this device. ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_DEVICE ); ++ status_code = P2P_STATUS_FAIL_NO_COMMON_CH; ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); ++ } ++ } ++ else ++ { ++ // Commented by Albert 20121130 ++ // Intel will use the different P2P IE to store the operating channel information ++ // Workaround for Intel WiDi 3.5 ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); ++ status_code = P2P_STATUS_SUCCESS; ++ } ++ } ++ else ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); ++ #ifdef CONFIG_INTEL_WIDI ++ _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); ++ #endif //CONFIG_INTEL_WIDI ++ ++ status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; ++ } ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ ); ++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ } ++ else ++ { ++ // Received the invitation to join a P2P group. ++ ++ _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) ); ++ rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ if ( _rtw_memcmp( group_id.go_device_addr, myid( &padapter->eeprompriv ), ETH_ALEN ) ) ++ { ++ // In this case, the GO can't be myself. ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); ++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ else ++ { ++ // The p2p device sending this p2p invitation request wants to join an existing P2P group ++ // Commented by Albert 2012/06/28 ++ // In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. ++ // The peer device address should be the destination address for the provisioning discovery request. ++ // Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. ++ // The peer interface address should be the address for WPS mac address ++ _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN ); ++ rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN ); ++ status_code = P2P_STATUS_SUCCESS; ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ ); ++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__ ); ++ status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ ++ DBG_871X( "[%s] status_code = %d\n", __FUNCTION__, status_code ); ++ ++ pwdinfo->inviteresp_info.token = frame_body[ 7 ]; ++ issue_p2p_invitation_response( padapter, GetAddr2Ptr(pframe), pwdinfo->inviteresp_info.token, status_code ); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); ++ } ++#ifdef CONFIG_INTEL_WIDI ++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) ) ++ { ++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; ++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); ++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL); ++ } ++#endif //CONFIG_INTEL_WIDI ++ break; ++ } ++ case P2P_INVIT_RESP: ++ { ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ ++ DBG_871X( "[%s] Got invite response frame!\n", __FUNCTION__ ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ pwdinfo->invitereq_info.benable = _FALSE; ++ ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ if ( _rtw_memcmp( pwdinfo->invitereq_info.go_bssid, myid( &padapter->eeprompriv ), ETH_ALEN )) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO ); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_OK ); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); ++ } ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); ++ } ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); ++ } ++ ++ if ( rtw_p2p_chk_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ) ) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); ++ } ++ break; ++ } ++ case P2P_DEVDISC_REQ: ++ ++ process_p2p_devdisc_req(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_DEVDISC_RESP: ++ ++ process_p2p_devdisc_resp(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_PROVISION_DISC_REQ: ++ DBG_871X( "[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__ ); ++ process_p2p_provdisc_req(pwdinfo, pframe, len); ++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); ++ ++ //20110902 Kurt ++ //Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++#ifdef CONFIG_INTEL_WIDI ++ if( (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) && (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_WFD_CONNECTION) ) ++ { ++ padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; ++ _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); ++ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL); ++ } ++#endif //CONFIG_INTEL_WIDI ++ break; ++ ++ case P2P_PROVISION_DISC_RESP: ++ // Commented by Albert 20110707 ++ // Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? ++ DBG_871X( "[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__ ); ++ // Commented by Albert 20110426 ++ // The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP); ++ process_p2p_provdisc_resp(pwdinfo, pframe); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++ break; ++ ++ } ++ } ++#endif //CONFIG_P2P ++ ++exit: ++ ++#ifdef CONFIG_P2P ++ if(merged_p2pie) ++ { ++ rtw_mfree(merged_p2pie, merged_p2p_ielen + 2); ++ } ++#endif ++ return _SUCCESS; ++} ++ ++unsigned int on_action_public_vendor(union recv_frame *precv_frame) ++{ ++ unsigned int ret = _FAIL; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint frame_len = precv_frame->u.hdr.len; ++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { ++ ret = on_action_public_p2p(precv_frame); ++ } ++ ++ return ret; ++} ++ ++unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) ++{ ++ unsigned int ret = _FAIL; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint frame_len = precv_frame->u.hdr.len; ++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ u8 token; ++ _adapter *adapter = precv_frame->u.hdr.adapter; ++ int cnt = 0; ++ char msg[64]; ++ ++ token = frame_body[2]; ++ ++ if (rtw_action_public_decache(precv_frame, token) == _FAIL) ++ goto exit; ++ ++ #ifdef CONFIG_IOCTL_CFG80211 ++ cnt += sprintf((msg+cnt), "%s(token:%u)", action_public_str(action), token); ++ rtw_cfg80211_rx_action(adapter, pframe, frame_len, msg); ++ #endif ++ ++ ret = _SUCCESS; ++ ++exit: ++ return ret; ++} ++ ++unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int ret = _FAIL; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint frame_len = precv_frame->u.hdr.len; ++ u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ u8 category, action; ++ ++ /* check RA matches or not */ ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN)) ++ goto exit; ++ ++ category = frame_body[0]; ++ if(category != RTW_WLAN_CATEGORY_PUBLIC) ++ goto exit; ++ ++ action = frame_body[1]; ++ switch (action) { ++ case ACT_PUBLIC_VENDOR: ++ ret = on_action_public_vendor(precv_frame); ++ break; ++ default: ++ ret = on_action_public_default(precv_frame, action); ++ break; ++ } ++ ++exit: ++ return ret; ++} ++ ++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++#ifdef CONFIG_IEEE80211W ++unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned short tid; ++ //Baron ++ ++ DBG_871X("OnAction_sa_query\n"); ++ ++ switch (pframe[WLAN_HDR_A3_LEN+1]) ++ { ++ case 0: //SA Query req ++ _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN+2], sizeof(unsigned short)); ++ DBG_871X("OnAction_sa_query request,action=%d, tid=%04x\n", pframe[WLAN_HDR_A3_LEN+1], tid); ++ issue_action_SA_Query(padapter, GetAddr2Ptr(pframe), 1, tid); ++ break; ++ ++ case 1: //SA Query rsp ++ _cancel_timer_ex(&pmlmeext->sa_query_timer); ++ DBG_871X("OnAction_sa_query response,action=%d, tid=%04x, cahcel timer\n", pframe[WLAN_HDR_A3_LEN+1], pframe[WLAN_HDR_A3_LEN+2]); ++ break; ++ default: ++ break; ++ } ++ if(0) ++ { ++ int pp; ++ printk("pattrib->pktlen = %d =>", pattrib->pkt_len); ++ for(pp=0;pp< pattrib->pkt_len; pp++) ++ printk(" %02x ", pframe[pp]); ++ printk("\n"); ++ } ++ ++ return _SUCCESS; ++} ++#endif //CONFIG_IEEE80211W ++ ++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_P2P ++ u8 *frame_body; ++ u8 category, OUI_Subtype, dialogToken=0; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check RA matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode ++ return _SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ if(category != RTW_WLAN_CATEGORY_P2P) ++ return _SUCCESS; ++ ++ if ( cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ) != P2POUI ) ++ return _SUCCESS; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ rtw_cfg80211_rx_action_p2p(padapter, pframe, len); ++ return _SUCCESS; ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len -= sizeof(struct rtw_ieee80211_hdr_3addr); ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++ switch(OUI_Subtype) ++ { ++ case P2P_NOTICE_OF_ABSENCE: ++ ++ break; ++ ++ case P2P_PRESENCE_REQUEST: ++ ++ process_p2p_presence_req(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_PRESENCE_RESPONSE: ++ ++ break; ++ ++ case P2P_GO_DISC_REQUEST: ++ ++ break; ++ ++ default: ++ break; ++ ++ } ++ } ++#endif //CONFIG_P2P ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int i; ++ unsigned char category; ++ struct action_handler *ptable; ++ unsigned char *frame_body; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ ++ for(i = 0; i < sizeof(OnAction_tbl)/sizeof(struct action_handler); i++) ++ { ++ ptable = &OnAction_tbl[i]; ++ ++ if(category == ptable->num) ++ ptable->func(padapter, precv_frame); ++ ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ ++ //DBG_871X("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); ++ return _SUCCESS; ++} ++ ++struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once) ++{ ++ struct xmit_frame *pmgntframe; ++ struct xmit_buf *pxmitbuf; ++ ++ if (once) ++ pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv); ++ else ++ pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv); ++ ++ if (pmgntframe == NULL) { ++ DBG_871X(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once); ++ goto exit; ++ } ++ ++ if ((pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv)) == NULL) { ++ DBG_871X(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter)); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ pmgntframe = NULL; ++ goto exit; ++ } ++ ++ pmgntframe->frame_tag = MGNT_FRAMETAG; ++ pmgntframe->pxmitbuf = pxmitbuf; ++ pmgntframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pmgntframe; ++ ++exit: ++ return pmgntframe; ++ ++} ++ ++inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) ++{ ++ return _alloc_mgtxmitframe(pxmitpriv, _FALSE); ++} ++ ++inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv) ++{ ++ return _alloc_mgtxmitframe(pxmitpriv, _TRUE); ++} ++ ++ ++/**************************************************************************** ++ ++Following are some TX fuctions for WiFi MLME ++ ++*****************************************************************************/ ++ ++void update_mgnt_tx_rate(_adapter *padapter, u8 rate) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ pmlmeext->tx_rate = rate; ++ DBG_871X("%s(): rate = %x\n",__FUNCTION__, rate); ++} ++ ++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); ++ ++ pattrib->hdrlen = 24; ++ pattrib->nr_frags = 1; ++ pattrib->priority = 7; ++ pattrib->mac_id = 0; ++ pattrib->qsel = 0x12; ++ ++ pattrib->pktlen = 0; ++ ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ pattrib->raid = 6;//b mode ++ else ++ pattrib->raid = 5;//a/g mode ++ ++ pattrib->encrypt = _NO_PRIVACY_; ++ pattrib->bswenc = _FALSE; ++ ++ pattrib->qos_en = _FALSE; ++ pattrib->ht_en = _FALSE; ++ pattrib->bwmode = HT_CHANNEL_WIDTH_20; ++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pattrib->sgi = _FALSE; ++ ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ ++ pattrib->retry_ctrl = _TRUE; ++ ++} ++ ++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++ if(padapter->bSurpriseRemoved == _TRUE || ++ padapter->bDriverStopped == _TRUE) ++ { ++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); ++ return; ++ } ++ ++ rtw_hal_mgnt_xmit(padapter, pmgntframe); ++} ++ ++s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) ++{ ++ s32 ret = _FAIL; ++ _irqL irqL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf; ++ struct submit_ctx sctx; ++ ++ if(padapter->bSurpriseRemoved == _TRUE || ++ padapter->bDriverStopped == _TRUE) ++ { ++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); ++ return ret; ++ } ++ ++ rtw_sctx_init(&sctx, timeout_ms); ++ pxmitbuf->sctx = &sctx; ++ ++ ret = rtw_hal_mgnt_xmit(padapter, pmgntframe); ++ ++ if (ret == _SUCCESS) ++ ret = rtw_sctx_wait(&sctx); ++ ++ _enter_critical(&pxmitpriv->lock_sctx, &irqL); ++ pxmitbuf->sctx = NULL; ++ _exit_critical(&pxmitpriv->lock_sctx, &irqL); ++ ++ return ret; ++} ++ ++s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++#ifdef CONFIG_XMIT_ACK ++ s32 ret = _FAIL; ++ u32 timeout_ms = 500;// 500ms ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ #ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->pbuddy_adapter && !padapter->isprimary) ++ pxmitpriv = &(padapter->pbuddy_adapter->xmitpriv); ++ #endif ++ ++ if(padapter->bSurpriseRemoved == _TRUE || ++ padapter->bDriverStopped == _TRUE) ++ { ++ rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); ++ return -1; ++ } ++ ++ _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); ++ pxmitpriv->ack_tx = _TRUE; ++ ++ pmgntframe->ack_report = 1; ++ if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) { ++ ret = rtw_ack_tx_wait(pxmitpriv, timeout_ms); ++ } ++ ++ pxmitpriv->ack_tx = _FALSE; ++ _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); ++ ++ return ret; ++#else //!CONFIG_XMIT_ACK ++ dump_mgntframe(padapter, pmgntframe); ++ rtw_msleep_os(50); ++ return _SUCCESS; ++#endif //!CONFIG_XMIT_ACK ++} ++ ++int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) ++{ ++ u8 *ssid_ie; ++ sint ssid_len_ori; ++ int len_diff = 0; ++ ++ ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); ++ ++ //DBG_871X("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); ++ ++ if(ssid_ie && ssid_len_ori>0) ++ { ++ switch(hidden_ssid_mode) ++ { ++ case 1: ++ { ++ u8 *next_ie = ssid_ie + 2 + ssid_len_ori; ++ u32 remain_len = 0; ++ ++ remain_len = ies_len -(next_ie-ies); ++ ++ ssid_ie[1] = 0; ++ _rtw_memcpy(ssid_ie+2, next_ie, remain_len); ++ len_diff -= ssid_len_ori; ++ ++ break; ++ } ++ case 2: ++ _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return len_diff; ++} ++ ++void issue_beacon(_adapter *padapter, int timeout_ms) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned int rate_len; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); ++ return; ++ } ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->qsel = 0x10; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //DBG_871X("ie len=%d\n", cur_network->IELength); ++#ifdef CONFIG_P2P ++ // for P2P : Primary Device Type & Device Name ++ u32 wpsielen=0, insert_len=0; ++ u8 *wpsie=NULL; ++ wpsie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen>0) ++ { ++ uint wps_offset, remainder_ielen; ++ u8 *premainder_ie, *pframe_wscie; ++ ++ wps_offset = (uint)(wpsie - cur_network->IEs); ++ ++ premainder_ie = wpsie + wpsielen; ++ ++ remainder_ielen = cur_network->IELength - wps_offset - wpsielen; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len>0) ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset); ++ pframe += wps_offset; ++ pattrib->pktlen += wps_offset; ++ ++ _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); ++ pframe += pmlmepriv->wps_beacon_ie_len; ++ pattrib->pktlen += pmlmepriv->wps_beacon_ie_len; ++ ++ //copy remainder_ie to pframe ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ } ++ else ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pattrib->pktlen += cur_network->IELength; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ pframe_wscie = pframe + wps_offset; ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset+wpsielen); ++ pframe += (wps_offset + wpsielen); ++ pattrib->pktlen += (wps_offset + wpsielen); ++ ++ //now pframe is end of wsc ie, insert Primary Device Type & Device Name ++ // Primary Device Type ++ // Type: ++ *(u16*) ( pframe + insert_len) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ insert_len += 2; ++ ++ // Length: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( 0x0008 ); ++ insert_len += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ insert_len += 2; ++ ++ // OUI ++ *(u32*) ( pframe + insert_len ) = cpu_to_be32( WPSOUI ); ++ insert_len += 4; ++ ++ // Sub Category ID ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ insert_len += 2; ++ ++ ++ // Device Name ++ // Type: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ insert_len += 2; ++ ++ // Length: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( pwdinfo->device_name_len ); ++ insert_len += 2; ++ ++ // Value: ++ _rtw_memcpy( pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len ); ++ insert_len += pwdinfo->device_name_len; ++ ++ ++ //update wsc ie length ++ *(pframe_wscie+1) = (wpsielen -2) + insert_len; ++ ++ //pframe move to end ++ pframe+=insert_len; ++ pattrib->pktlen += insert_len; ++ ++ //copy remainder_ie to pframe ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ } ++ } ++ else ++#endif //CONFIG_P2P ++ { ++ int len_diff; ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ len_diff = update_hidden_ssid( ++ pframe+_BEACON_IE_OFFSET_ ++ , cur_network->IELength-_BEACON_IE_OFFSET_ ++ , pmlmeinfo->hidden_ssid_mode ++ ); ++ pframe += (cur_network->IELength+len_diff); ++ pattrib->pktlen += (cur_network->IELength+len_diff); ++ } ++ ++ { ++ u8 *wps_ie; ++ uint wps_ielen; ++ u8 sr = 0; ++ wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr+TXDESC_OFFSET+sizeof (struct rtw_ieee80211_hdr_3addr)+_BEACON_IE_OFFSET_, ++ pattrib->pktlen-sizeof (struct rtw_ieee80211_hdr_3addr)-_BEACON_IE_OFFSET_, NULL, &wps_ielen); ++ if (wps_ie && wps_ielen>0) { ++ rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); ++ } ++ if (sr != 0) ++ set_fwstate(pmlmepriv, WIFI_UNDER_WPS); ++ else ++ _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); ++ } ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ u32 len; ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ len = pmlmepriv->p2p_beacon_ie_len; ++ if(pmlmepriv->p2p_beacon_ie && len>0) ++ _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_beacon_p2p_ie(pwdinfo, pframe); ++ } ++ ++ pframe += len; ++ pattrib->pktlen += len; ++#ifdef CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(_TRUE == pwdinfo->wfd_info->wfd_enable) ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_beacon_wfd_ie( pwdinfo, pframe ); ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else ++ { ++ len = 0; ++ if(pmlmepriv->wfd_beacon_ie && pmlmepriv->wfd_beacon_ie_len>0) ++ { ++ len = pmlmepriv->wfd_beacon_ie_len; ++ _rtw_memcpy(pframe, pmlmepriv->wfd_beacon_ie, len); ++ } ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ pframe += len; ++ pattrib->pktlen += len; ++#endif //CONFIG_WFD ++ } ++#endif //CONFIG_P2P ++ ++ goto _issue_bcn; ++ ++ } ++ ++ //below for ad-hoc mode ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); ++ ++ //if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u8 erpinfo=0; ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); ++ ++ //ERP IE ++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); ++ } ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++_issue_bcn: ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ pmlmepriv->update_bcn = _FALSE; ++ ++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ ++ if ((pattrib->pktlen + TXDESC_SIZE) > 512) ++ { ++ DBG_871X("beacon frame too large\n"); ++ return; ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ //DBG_871X("issue bcn_sz=%d\n", pattrib->last_txcmdsz); ++ if(timeout_ms > 0) ++ dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms); ++ else ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac, *bssid; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ u8 *pwps_ie; ++ uint wps_ielen; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ unsigned int rate_len; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#endif //CONFIG_P2P ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); ++ return; ++ } ++ ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ bssid = cur_network->MacAddress; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ ++ if(cur_network->IELength>MAX_IE_SZ) ++ return; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ pwps_ie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen); ++ ++ //inerset & update wps_probe_resp_ie ++ if((pmlmepriv->wps_probe_resp_ie!=NULL) && pwps_ie && (wps_ielen>0)) ++ { ++ uint wps_offset, remainder_ielen; ++ u8 *premainder_ie; ++ ++ wps_offset = (uint)(pwps_ie - cur_network->IEs); ++ ++ premainder_ie = pwps_ie + wps_ielen; ++ ++ remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; ++ ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset); ++ pframe += wps_offset; ++ pattrib->pktlen += wps_offset; ++ ++ wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];//to get ie data len ++ if((wps_offset+wps_ielen+2)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen+2); ++ pframe += wps_ielen+2; ++ pattrib->pktlen += wps_ielen+2; ++ } ++ ++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ } ++ } ++ else ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pattrib->pktlen += cur_network->IELength; ++ } ++ ++ /* retrieve SSID IE from cur_network->Ssid */ ++ { ++ u8 *ssid_ie; ++ sint ssid_ielen; ++ sint ssid_ielen_diff; ++ u8 buf[MAX_IE_SZ]; ++ u8 *ies = pmgntframe->buf_addr+TXDESC_OFFSET+sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ ssid_ie = rtw_get_ie(ies+_FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, ++ (pframe-ies)-_FIXED_IE_LENGTH_); ++ ++ ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; ++ ++ if (ssid_ie && cur_network->Ssid.SsidLength) { ++ uint remainder_ielen; ++ u8 *remainder_ie; ++ remainder_ie = ssid_ie+2; ++ remainder_ielen = (pframe-remainder_ie); ++ ++ DBG_871X_LEVEL(_drv_warning_, FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter)); ++ if (remainder_ielen > MAX_IE_SZ) { ++ remainder_ielen = MAX_IE_SZ; ++ } ++ ++ _rtw_memcpy(buf, remainder_ie, remainder_ielen); ++ _rtw_memcpy(remainder_ie+ssid_ielen_diff, buf, remainder_ielen); ++ *(ssid_ie+1) = cur_network->Ssid.SsidLength; ++ _rtw_memcpy(ssid_ie+2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); ++ ++ pframe += ssid_ielen_diff; ++ pattrib->pktlen += ssid_ielen_diff; ++ } ++ } ++ } ++ else ++#endif ++ { ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //below for ad-hoc mode ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); ++ ++ // DS parameter set ++ pframe =rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u8 erpinfo=0; ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); ++ ++ //ERP IE ++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); ++ } ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++ } ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) /*&& is_valid_p2p_probereq*/) ++ { ++ u32 len; ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ //if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() ++ len = pmlmepriv->p2p_go_probe_resp_ie_len; ++ if(pmlmepriv->p2p_go_probe_resp_ie && len>0) ++ _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_probe_resp_p2p_ie(pwdinfo, pframe); ++ } ++ ++ pframe += len; ++ pattrib->pktlen += len; ++ ++#ifdef CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(_TRUE == pwdinfo->wfd_info->wfd_enable) ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_probe_resp_wfd_ie(pwdinfo, pframe, 0); ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else ++ { ++ len = 0; ++ if(pmlmepriv->wfd_probe_resp_ie && pmlmepriv->wfd_probe_resp_ie_len>0) ++ { ++ len = pmlmepriv->wfd_probe_resp_ie_len; ++ _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, len); ++ } ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ pframe += len; ++ pattrib->pktlen += len; ++#endif //CONFIG_WFD ++ ++ } ++#endif //CONFIG_P2P ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, int wait_ack) ++{ ++ int ret = _FAIL; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ unsigned char bssrate[NumRates]; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_notice_,("+issue_probereq\n")); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if (da) ++ { ++ // unicast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); ++ } ++ else ++ { ++ // broadcast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_PROBEREQ); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if(pssid) ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); ++ else ++ pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); ++ ++ get_rate_set(padapter, bssrate, &bssrate_len); ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++#if 0 ++ //add wps_ie for wps2.0 ++ if(pmlmepriv->probereq_wpsie_len>0 && pmlmepriv->probereq_wpsie_lenprobereq_wpsie, pmlmepriv->probereq_wpsie_len); ++ pframe += pmlmepriv->probereq_wpsie_len; ++ pattrib->pktlen += pmlmepriv->probereq_wpsie_len; ++ //pmlmepriv->probereq_wpsie_len = 0 ;//reset to zero ++ } ++#else ++ //add wps_ie for wps2.0 ++ if(pmlmepriv->wps_probe_req_ie_len>0 && pmlmepriv->wps_probe_req_ie) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); ++ pframe += pmlmepriv->wps_probe_req_ie_len; ++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; ++ //pmlmepriv->wps_probe_req_ie_len = 0 ;//reset to zero ++ } ++#endif ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_notice_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); ++ ++ if (wait_ack) { ++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); ++ } else { ++ dump_mgntframe(padapter, pmgntframe); ++ ret = _SUCCESS; ++ } ++ ++exit: ++ return ret; ++} ++ ++inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) ++{ ++ _issue_probereq(padapter, pssid, da, _FALSE); ++} ++ ++int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, ++ int try_cnt, int wait_ms) ++{ ++ int ret; ++ int i = 0; ++ u32 start = rtw_get_current_time(); ++ ++ do ++ { ++ ret = _issue_probereq(padapter, pssid, da, wait_ms>0?_TRUE:_FALSE); ++ ++ i++; ++ ++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved) ++ break; ++ ++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL) ++ rtw_msleep_os(wait_ms); ++ ++ }while((ixmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_AUTH); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ ++ if(psta)// for AP mode ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ ++ _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ ++ // setting auth algo number ++ val16 = (u16)psta->authalg; ++ ++ if(status != _STATS_SUCCESSFUL_) ++ val16 = 0; ++ ++ if (val16) { ++ val16 = cpu_to_le16(val16); ++ use_shared_key = 1; ++ } ++ ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting auth seq number ++ val16 =(u16)psta->auth_seq; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting status code... ++ val16 = status; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // added challenging text... ++ if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); ++ } ++#endif ++ } ++ else ++ { ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); ++ ++ // setting auth algo number ++ val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)? 1: 0;// 0:OPEN System, 1:Shared key ++ if (val16) { ++ val16 = cpu_to_le16(val16); ++ use_shared_key = 1; ++ } ++ //DBG_871X("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); ++ ++ //setting IV for auth seq #3 ++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ //DBG_871X("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); ++ val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30)); ++ val32 = cpu_to_le32(val32); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); ++ ++ pattrib->iv_len = 4; ++ } ++ ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting auth seq number ++ val16 = pmlmeinfo->auth_seq; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ ++ // setting status code... ++ val16 = status; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // then checking to see if sending challenging text... ++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); ++ ++ SetPrivacy(fctrl); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->encrypt = _WEP40_; ++ ++ pattrib->icv_len = 4; ++ ++ pattrib->pktlen += pattrib->icv_len; ++ ++ } ++ ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ rtw_wep_encrypt(padapter, (u8 *)pmgntframe); ++ DBG_871X("%s\n", __FUNCTION__); ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++ ++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) ++{ ++#ifdef CONFIG_AP_MODE ++ struct xmit_frame *pmgntframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct pkt_attrib *pattrib; ++ unsigned char *pbuf, *pframe; ++ unsigned short val; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); ++ u8 *ie = pnetwork->IEs; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); ++ _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) ++ SetFrameSubType(pwlanhdr, pkt_type); ++ else ++ return; ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen += pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ //capability ++ val = *(unsigned short *)rtw_get_capability_from_ie(ie); ++ ++ pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); ++ ++ status = cpu_to_le16(status); ++ pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&status, &(pattrib->pktlen)); ++ ++ val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); ++ pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); ++ ++ if (pstat->bssratelen <= 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen-8), pstat->bssrateset+8, &(pattrib->pktlen)); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) ++ { ++ uint ie_len=0; ++ ++ //FILL HT CAP INFO IE ++ //p = hostapd_eid_ht_capabilities_info(hapd, p); ++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if(pbuf && ie_len>0) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ } ++ ++ //FILL HT ADD INFO IE ++ //p = hostapd_eid_ht_operation(hapd, p); ++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if(pbuf && ie_len>0) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ } ++ ++ } ++#endif ++ ++ //FILL WMM IE ++ if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) ++ { ++ uint ie_len=0; ++ unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ ++ for (pbuf = ie + _BEACON_IE_OFFSET_; ;pbuf+= (ie_len + 2)) ++ { ++ pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if(pbuf && _rtw_memcmp(pbuf+2, WMM_PARA_IE, 6)) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ ++ break; ++ } ++ ++ if ((pbuf == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ } ++ ++ } ++ ++ ++ if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) ++ { ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); ++ } ++ ++ //add WPS IE ie for wps 2.0 ++ if(pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len>0) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); ++ ++ pframe += pmlmepriv->wps_assoc_resp_ie_len; ++ pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; ++ } ++ ++#ifdef CONFIG_P2P ++ if( padapter->wdinfo.driver_interface == DRIVER_WEXT ) ++ { ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) ++ { ++ u32 len; ++ ++ len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code); ++ ++ pframe += len; ++ pattrib->pktlen += len; ++ } ++ } ++#ifdef CONFIG_WFD ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ++#ifdef CONFIG_IOCTL_CFG80211 ++ && (_TRUE == pwdinfo->wfd_info->wfd_enable) ++#endif //CONFIG_IOCTL_CFG80211 ++ ) ++ { ++ wfdielen = build_assoc_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++#endif //CONFIG_WFD ++#endif //CONFIG_P2P ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++#endif ++} ++ ++void issue_assocreq(_adapter *padapter) ++{ ++ int ret = _FAIL; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe, *p; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned short val16; ++ unsigned int i, j, ie_len, index=0; ++ unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates]; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0, sta_bssrate_len = 0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u16 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_DFS ++ u16 cap; ++#endif //CONFIG_DFS ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ goto exit; ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ASSOCREQ); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //caps ++ ++#ifdef CONFIG_DFS ++ _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ cap |= BIT(8); ++ _rtw_memcpy(pframe, &cap, 2); ++#else ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++#endif //CONFIG_DFS ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //listen interval ++ //todo: listen interval for power saving ++ val16 = cpu_to_le16(3); ++ _rtw_memcpy(pframe ,(unsigned char *)&val16, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); ++ ++ //supported rate & extended supported rate ++ ++#if 1 // Check if the AP's supported rates are also supported by STA. ++ get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); ++ //DBG_871X("sta_bssrate_len=%d\n", sta_bssrate_len); ++ ++ if(pmlmeext->cur_channel == 14)// for JAPAN, channel 14 can only uses B Mode(CCK) ++ { ++ sta_bssrate_len = 4; ++ } ++ ++ ++ //for (i = 0; i < sta_bssrate_len; i++) { ++ // DBG_871X("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); ++ //} ++ ++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { ++ if (pmlmeinfo->network.SupportedRates[i] == 0) break; ++ DBG_871X("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); ++ } ++ ++ ++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { ++ if (pmlmeinfo->network.SupportedRates[i] == 0) break; ++ ++ ++ // Check if the AP's supported rates are also supported by STA. ++ for (j=0; j < sta_bssrate_len; j++) { ++ // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP ++ if ( (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK) ++ == (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)) { ++ //DBG_871X("match i = %d, j=%d\n", i, j); ++ break; ++ } else { ++ //DBG_871X("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); ++ } ++ } ++ ++ if (j == sta_bssrate_len) { ++ // the rate is not supported by STA ++ DBG_871X("%s(): the rate[%d]=%02X is not supported by STA!\n",__FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); ++ } else { ++ // the rate is supported by STA ++ bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; ++ } ++ } ++ ++ bssrate_len = index; ++ DBG_871X("bssrate_len = %d\n", bssrate_len); ++ ++#else // Check if the AP's supported rates are also supported by STA. ++#if 0 ++ get_rate_set(padapter, bssrate, &bssrate_len); ++#else ++ for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { ++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) break; ++ ++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP ++ break; ++ ++ bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len]; ++ } ++#endif ++#endif // Check if the AP's supported rates are also supported by STA. ++ ++ if (bssrate_len == 0) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; //don't connect to AP if no joint supported rate ++ } ++ ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //RSN ++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _RSN_IE_2_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if (p != NULL) ++ { ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, ie_len, (p + 2), &(pattrib->pktlen)); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ //HT caps ++ if(padapter->mlmepriv.htpriv.ht_option==_TRUE) ++ { ++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_CAPABILITY_IE_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if ((p != NULL) && (!(is_ap_in_tkip(padapter)))) ++ { ++ _rtw_memcpy(&(pmlmeinfo->HT_caps), (p + 2), sizeof(struct HT_caps_element)); ++ ++ //to disable 40M Hz support while gd_bw_40MHz_en = 0 ++ if (pregpriv->cbw40_enable == 0) ++ { ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info &= (~(BIT(6) | BIT(1))); ++ } ++ else ++ { ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= BIT(1); ++ } ++ ++ //todo: disable SM power save mode ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= 0x000c; ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ //switch (pregpriv->rf_config) ++ switch(rf_type) ++ { ++ case RF_1T1R: ++ ++ if(pregpriv->rx_stbc) ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream ++ ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ++ if((pregpriv->rx_stbc == 0x3) ||//enable for 2.4/5 GHz ++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_24N) && (pregpriv->rx_stbc == 0x1)) || //enable for 2.4GHz ++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_5N) && (pregpriv->rx_stbc == 0x2)) || //enable for 5GHz ++ (pregpriv->wifi_spec==1)) ++ { ++ DBG_871X("declare supporting RX STBC\n"); ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0200);//RX STBC two spatial stream ++ } ++ #ifdef CONFIG_DISABLE_MCS13TO15 ++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && (pregpriv->wifi_spec!=1)) ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R_MCS13TO15_OFF, 16); ++ else ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R, 16); ++ #else //CONFIG_DISABLE_MCS13TO15 ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_2R, 16); ++ #endif //CONFIG_DISABLE_MCS13TO15 ++ break; ++ } ++#ifdef RTL8192C_RECONFIG_TO_1T1R ++ { ++ if(pregpriv->rx_stbc) ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream ++ ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16); ++ } ++#endif ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); ++ ++#ifdef CONFIG_BT_COEXIST ++ if (BT_1Ant(padapter) == _TRUE) ++ { ++ // set to 8K ++ pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para &= (u8)~IEEE80211_HT_CAP_AMPDU_FACTOR; ++// pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para |= MAX_AMPDU_FACTOR_8K ++ } ++#endif ++ ++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ie_len , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); ++ ++ } ++ } ++#endif ++ ++ //vendor specific IE, such as WPA, WMM, WPS ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) || ++ (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || ++ (_rtw_memcmp(pIE->data, WPS_OUI, 4))) ++ { ++ if(!padapter->registrypriv.wifi_spec) ++ { ++ //Commented by Kurt 20110629 ++ //In some older APs, WPS handshake ++ //would be fail if we append vender extensions informations to AP ++ if(_rtw_memcmp(pIE->data, WPS_OUI, 4)){ ++ pIE->Length=14; ++ } ++ } ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, pIE->Length, pIE->data, &(pattrib->pktlen)); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) ++ { ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); ++ } ++ ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib); ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len>0) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len); ++ pframe += pmlmepriv->p2p_assoc_req_ie_len; ++ pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ // Should add the P2P IE in the association request frame. ++ // P2P OUI ++ ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101109 ++ // According to the P2P Specification, the association request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Extended Listen Timing ++ // 3. Device Info ++ // Commented by Albert 20110516 ++ // 4. P2P Interface ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; ++ else ++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; ++ ++ // Extended Listen Timing ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ if ( ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) || ++ ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); ++ } ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ // P2P Interface ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTERFACE; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x000D ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Device Address ++ p2pielen += ETH_ALEN; ++ ++ p2pie[ p2pielen++ ] = 1; // P2P Interface Address Count ++ ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Interface Address List ++ p2pielen += ETH_ALEN; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ //wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe); ++ //pframe += wfdielen; ++ //pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ } ++ } ++ ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( _TRUE == pwdinfo->wfd_info->wfd_enable ) ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else if (pmlmepriv->wfd_assoc_req_ie != NULL && pmlmepriv->wfd_assoc_req_ie_len>0) ++ { ++ //WFD IE ++ _rtw_memcpy(pframe, pmlmepriv->wfd_assoc_req_ie, pmlmepriv->wfd_assoc_req_ie_len); ++ pattrib->pktlen += pmlmepriv->wfd_assoc_req_ie_len; ++ pframe += pmlmepriv->wfd_assoc_req_ie_len; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++ ret = _SUCCESS; ++ ++exit: ++ if (ret == _SUCCESS) ++ rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen); ++ else ++ rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); ++ ++ return; ++} ++ ++//when wait_ack is ture, this function shoule be called at process context ++static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) ++{ ++ int ret = _FAIL; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv; ++ struct mlme_ext_priv *pmlmeext; ++ struct mlme_ext_info *pmlmeinfo; ++ ++ //DBG_871X("%s:%d\n", __FUNCTION__, power_mode); ++ ++ if(!padapter) ++ goto exit; ++ ++ pxmitpriv = &(padapter->xmitpriv); ++ pmlmeext = &(padapter->mlmeextpriv); ++ pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ SetFrDs(fctrl); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ SetToDs(fctrl); ++ } ++ ++ if (power_mode) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ if(wait_ack) ++ { ++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); ++ } ++ else ++ { ++ dump_mgntframe(padapter, pmgntframe); ++ ret = _SUCCESS; ++ } ++ ++exit: ++ return ret; ++} ++ ++ ++//when wait_ms >0 , this function shoule be called at process context ++//da == NULL for station mode ++int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) ++{ ++ int ret; ++ int i = 0; ++ u32 start = rtw_get_current_time(); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ /* da == NULL, assum it's null data for sta to ap*/ ++ if (da == NULL) ++ da = get_my_bssid(&(pmlmeinfo->network)); ++ ++ do ++ { ++ ret = _issue_nulldata(padapter, da, power_mode, wait_ms>0?_TRUE:_FALSE); ++ ++ i++; ++ ++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved) ++ break; ++ ++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL) ++ rtw_msleep_os(wait_ms); ++ ++ }while((ixmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ pattrib->hdrlen +=2; ++ pattrib->qos_en = _TRUE; ++ pattrib->eosp = 1; ++ pattrib->ack_policy = 0; ++ pattrib->mdata = 0; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ SetFrDs(fctrl); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ SetToDs(fctrl); ++ } ++ ++ if(pattrib->mdata) ++ SetMData(fctrl); ++ ++ qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); ++ ++ SetPriority(qc, tid); ++ ++ SetEOSP(qc, pattrib->eosp); ++ ++ SetAckpolicy(qc, pattrib->ack_policy); ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ if(wait_ack) ++ { ++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); ++ } ++ else ++ { ++ dump_mgntframe(padapter, pmgntframe); ++ ret = _SUCCESS; ++ } ++ ++exit: ++ return ret; ++} ++ ++//when wait_ms >0 , this function shoule be called at process context ++//da == NULL for station mode ++int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms) ++{ ++ int ret; ++ int i = 0; ++ u32 start = rtw_get_current_time(); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ /* da == NULL, assum it's null data for sta to ap*/ ++ if (da == NULL) ++ da = get_my_bssid(&(pmlmeinfo->network)); ++ ++ do ++ { ++ ret = _issue_qos_nulldata(padapter, da, tid, wait_ms>0?_TRUE:_FALSE); ++ ++ i++; ++ ++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved) ++ break; ++ ++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL) ++ rtw_msleep_os(wait_ms); ++ ++ }while((ixmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int ret = _FAIL; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ //DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); ++ ++#ifdef CONFIG_P2P ++ if ( !( rtw_p2p_chk_state( pwdinfo, P2P_STATE_NONE ) ) && ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ) ++ { ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); ++ _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); ++ } ++#endif //CONFIG_P2P ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_DEAUTH); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ reason = cpu_to_le16(reason); ++ pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ ++ if(wait_ack) ++ { ++ ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); ++ } ++ else ++ { ++ dump_mgntframe(padapter, pmgntframe); ++ ret = _SUCCESS; ++ } ++ ++exit: ++ return ret; ++} ++ ++int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) ++{ ++ DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); ++ return _issue_deauth(padapter, da, reason, _FALSE); ++} ++ ++int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, ++ int wait_ms) ++{ ++ int ret; ++ int i = 0; ++ u32 start = rtw_get_current_time(); ++ ++ do ++ { ++ ret = _issue_deauth(padapter, da, reason, wait_ms>0?_TRUE:_FALSE); ++ ++ i++; ++ ++ if (padapter->bDriverStopped || padapter->bSurpriseRemoved) ++ break; ++ ++ if(i < try_cnt && wait_ms > 0 && ret==_FAIL) ++ rtw_msleep_os(wait_ms); ++ ++ }while((ixmitpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ DBG_871X(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n", ++ FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ return; ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */ ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); /* TA */ ++ _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */ ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ /* category, action */ ++ { ++ u8 category, action; ++ category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT; ++ action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH; ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ } ++ ++ pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0); ++ pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen), ++ hal_ch_offset_to_secondary_ch_offset(ch_offset)); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++#ifdef CONFIG_IEEE80211W ++void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid) ++{ ++ u8 category = RTW_WLAN_CATEGORY_SA_QUERY; ++ u16 reason_code; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ u8 *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s: alloc_mgtxmitframe fail\n", __FUNCTION__); ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if(raddr) ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ else ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen); ++ pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen); ++ ++ switch (action) ++ { ++ case 0: //SA Query req ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen); ++ pmlmeext->sa_query_seq++; ++ //send sa query request to AP, AP should reply sa query response in 1 second ++ set_sa_query_timer(pmlmeext, 1000); ++ break; ++ ++ case 1: //SA Query rsp ++ tid = cpu_to_le16(tid); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen); ++ break; ++ default: ++ break; ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++} ++#endif //CONFIG_IEEE80211W ++ ++void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status) ++{ ++ u8 category = RTW_WLAN_CATEGORY_BACK; ++ u16 start_seq; ++ u16 BA_para_set; ++ u16 reason_code; ++ u16 BA_timeout_value; ++ u16 BA_starting_seqctrl; ++ HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ u8 *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++#ifdef CONFIG_BT_COEXIST ++ u8 tendaAPMac[] = {0xC8, 0x3A, 0x35}; ++#endif ++ ++#ifdef CONFIG_80211N_HT ++ DBG_871X("%s, category=%d, action=%d, status=%d\n", __FUNCTION__, category, action, status); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ //_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ ++ status = cpu_to_le16(status); ++ ++ ++ if (category == 3) ++ { ++ switch (action) ++ { ++ case 0: //ADDBA req ++ do { ++ pmlmeinfo->dialogToken++; ++ } while (pmlmeinfo->dialogToken == 0); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); ++ ++#ifdef CONFIG_BT_COEXIST ++ if ((BT_1Ant(padapter) == _TRUE) && ++ ((pmlmeinfo->assoc_AP_vendor != broadcomAP) || ++ (_rtw_memcmp(raddr, tendaAPMac, 3) == _FALSE))) ++ { ++ // A-MSDU NOT Supported ++ BA_para_set = 0; ++ // immediate Block Ack ++ BA_para_set |= (1 << 1) & IEEE80211_ADDBA_PARAM_POLICY_MASK; ++ // TID ++ BA_para_set |= (status << 2) & IEEE80211_ADDBA_PARAM_TID_MASK; ++ // max buffer size is 8 MSDU ++ BA_para_set |= (8 << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; ++ } ++ else ++#endif ++ { ++ #if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI) ++ BA_para_set = (0x0802 | ((status & 0xf) << 2)); //immediate ack & 16 buffer size ++ #else ++ BA_para_set = (0x1002 | ((status & 0xf) << 2)); //immediate ack & 64 buffer size ++ #endif ++ } ++ //sys_mib.BA_para_set = 0x0802; //immediate ack & 32 buffer size ++ BA_para_set = cpu_to_le16(BA_para_set); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ ++ //BA_timeout_value = 0xffff;//max: 65535 TUs(~ 65 ms) ++ BA_timeout_value = 5000;//~ 5ms ++ BA_timeout_value = cpu_to_le16(BA_timeout_value); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); ++ ++ //if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ if ((psta = rtw_get_stainfo(pstapriv, raddr)) != NULL) ++ { ++ start_seq = (psta->sta_xmitpriv.txseq_tid[status & 0x07]&0xfff) + 1; ++ ++ DBG_871X("BA_starting_seqctrl = %d for TID=%d\n", start_seq, status & 0x07); ++ ++ psta->BA_starting_seqctrl[status & 0x07] = start_seq; ++ ++ BA_starting_seqctrl = start_seq << 4; ++ } ++ ++ BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); ++ break; ++ ++ case 1: //ADDBA rsp ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); ++ /* ++ //BA_para_set = cpu_to_le16((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ #if defined(CONFIG_RTL8188E )&& defined (CONFIG_SDIO_HCI) ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x0800); //32buffer size ++ #else ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ #endif ++ */ ++ rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); ++ if(MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor) ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ else if(MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor) ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x0800); //32 buffer size ++ else if(MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor) ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x0400); //16 buffer size ++ else if(MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor) ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x0200); //8 buffer size ++ else ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ ++#ifdef CONFIG_BT_COEXIST ++ if ((BT_1Ant(padapter) == _TRUE) && ++ ((pmlmeinfo->assoc_AP_vendor != broadcomAP) || ++ (_rtw_memcmp(raddr, tendaAPMac, 3) == _FALSE))) ++ { ++ // max buffer size is 8 MSDU ++ BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; ++ BA_para_set |= (8 << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; ++ } ++#endif ++ ++ if(pregpriv->ampdu_amsdu==0)//disabled ++ BA_para_set = cpu_to_le16(BA_para_set & ~BIT(0)); ++ else if(pregpriv->ampdu_amsdu==1)//enabled ++ BA_para_set = cpu_to_le16(BA_para_set | BIT(0)); ++ else //auto ++ BA_para_set = cpu_to_le16(BA_para_set); ++ ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen)); ++ break; ++ case 2://DELBA ++ BA_para_set = (status & 0x1F) << 3; ++ BA_para_set = cpu_to_le16(BA_para_set); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ ++ reason_code = 37;//Requested from peer STA as it does not want to use the mechanism ++ reason_code = cpu_to_le16(reason_code); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(reason_code)), &(pattrib->pktlen)); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++#endif //CONFIG_80211N_HT ++} ++ ++static void issue_action_BSSCoexistPacket(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ unsigned char category, action; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct wlan_network *pnetwork = NULL; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ u8 InfoContent[16] = {0}; ++ u8 ICS[8][15]; ++#ifdef CONFIG_80211N_HT ++ if((pmlmepriv->num_FortyMHzIntolerant==0) || (pmlmepriv->num_sta_no_ht==0)) ++ return; ++ ++ if(_TRUE == pmlmeinfo->bwmode_updated) ++ return; ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ++ category = RTW_WLAN_CATEGORY_PUBLIC; ++ action = ACT_PUBLIC_BSSCOEXIST; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ ++ ++ // ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ { ++ u8 iedata=0; ++ ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ } ++ ++ ++ // ++ _rtw_memset(ICS, 0, sizeof(ICS)); ++ if(pmlmepriv->num_sta_no_ht>0) ++ { ++ int i; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ int len; ++ u8 *p; ++ WLAN_BSSID_EX *pbss_network; ++ ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ plist = get_next(plist); ++ ++ pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; ++ ++ p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); ++ if((p==NULL) || (len==0))//non-HT ++ { ++ if((pbss_network->Configuration.DSConfig<=0) || (pbss_network->Configuration.DSConfig>14)) ++ continue; ++ ++ ICS[0][pbss_network->Configuration.DSConfig]=1; ++ ++ if(ICS[0][0] == 0) ++ ICS[0][0] = 1; ++ } ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ ++ for(i= 0;i<8;i++) ++ { ++ if(ICS[i][0] == 1) ++ { ++ int j, k = 0; ++ ++ InfoContent[k] = i; ++ //SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); ++ k++; ++ ++ for(j=1;j<=14;j++) ++ { ++ if(ICS[i][j]==1) ++ { ++ if(k<16) ++ { ++ InfoContent[k] = j; //channel number ++ //SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); ++ k++; ++ } ++ } ++ } ++ ++ pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); ++ ++ } ++ ++ } ++ ++ ++ } ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++#endif //CONFIG_80211N_HT ++} ++ ++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta = NULL; ++ //struct recv_reorder_ctrl *preorder_ctrl; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u16 tid; ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ return _SUCCESS; ++ ++ psta = rtw_get_stainfo(pstapriv, addr); ++ if(psta==NULL) ++ return _SUCCESS; ++ ++ //DBG_871X("%s:%s\n", __FUNCTION__, (initiator==0)?"RX_DIR":"TX_DIR"); ++ ++ if(initiator==0) // recipient ++ { ++ for(tid = 0;tidrecvreorder_ctrl[tid].enable == _TRUE) ++ { ++ DBG_871X("rx agg disable tid(%d)\n",tid); ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F)); ++ psta->recvreorder_ctrl[tid].enable = _FALSE; ++ psta->recvreorder_ctrl[tid].indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ psta->recvreorder_ctrl[tid].indicate_seq); ++ #endif ++ } ++ } ++ } ++ else if(initiator == 1)// originator ++ { ++#ifdef CONFIG_80211N_HT ++ //DBG_871X("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap); ++ for(tid = 0;tidhtpriv.agg_enable_bitmap & BIT(tid)) ++ { ++ DBG_871X("tx agg disable tid(%d)\n",tid); ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F) ); ++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid); ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); ++ ++ } ++ } ++#endif //CONFIG_80211N_HT ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int send_beacon(_adapter *padapter) ++{ ++ u8 bxmitok = _FALSE; ++ int issue=0; ++ int poll = 0; ++//#ifdef CONFIG_CONCURRENT_MODE ++ //struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ //struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //_adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++//#endif ++ ++#ifdef CONFIG_PCI_HCI ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ issue_beacon(padapter, 0); ++ ++ return _SUCCESS; ++ ++#endif ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ u32 start = rtw_get_current_time(); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); ++ do{ ++ issue_beacon(padapter, 100); ++ issue++; ++ do { ++ rtw_yield_os(); ++ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); ++ poll++; ++ }while((poll%10)!=0 && _FALSE == bxmitok && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ ++ }while(_FALSE == bxmitok && issue<100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped) ++ { ++ return _FAIL; ++ } ++ ++ ++ if(_FALSE == bxmitok) ++ { ++ DBG_871X("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); ++ return _FAIL; ++ } ++ else ++ { ++ u32 passing_time = rtw_get_passing_time_ms(start); ++ ++ if(passing_time > 100 || issue > 3) ++ DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); ++ //else ++ // DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); ++ ++ return _SUCCESS; ++ } ++ ++#endif ++ ++} ++ ++/**************************************************************************** ++ ++Following are some utitity fuctions for WiFi MLME ++ ++*****************************************************************************/ ++ ++BOOLEAN IsLegal5GChannel( ++ IN PADAPTER Adapter, ++ IN u8 channel) ++{ ++ ++ int i=0; ++ u8 Channel_5G[45] = {36,38,40,42,44,46,48,50,52,54,56,58, ++ 60,62,64,100,102,104,106,108,110,112,114,116,118,120,122, ++ 124,126,128,130,132,134,136,138,140,149,151,153,155,157,159, ++ 161,163,165}; ++ for(i=0;imlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 initialgain = 0; ++ ++#ifdef CONFIG_P2P ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ u8 stay_buddy_ch = 0; ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++#endif //CONFIG_CONCURRENT_MODE ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ static unsigned char prev_survey_channel = 0; ++ static unsigned int p2p_scan_count = 0; ++ ++ if ( ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) || ( pwdinfo->p2p_info.scan_op_ch_only ) ) ++ { ++ if ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ++ { ++ survey_channel = pwdinfo->rx_invitereq_info.operation_ch[pmlmeext->sitesurvey_res.channel_idx]; ++ } ++ else ++ { ++ survey_channel = pwdinfo->p2p_info.operation_ch[pmlmeext->sitesurvey_res.channel_idx]; ++ } ++ ScanType = SCAN_ACTIVE; ++ } ++ else if(rtw_p2p_findphase_ex_is_social(pwdinfo)) ++ { ++ // Commented by Albert 2011/06/03 ++ // The driver is in the find phase, it should go through the social channel. ++ int ch_set_idx; ++ survey_channel = pwdinfo->social_chan[pmlmeext->sitesurvey_res.channel_idx]; ++ ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, survey_channel); ++ if (ch_set_idx >= 0) ++ ScanType = pmlmeext->channel_set[ch_set_idx].ScanType; ++ else ++ ScanType = SCAN_ACTIVE; ++ } ++ else ++#endif //CONFIG_P2P ++ { ++ struct rtw_ieee80211_channel *ch; ++ if (pmlmeext->sitesurvey_res.channel_idx < pmlmeext->sitesurvey_res.ch_num) { ++ ch = &pmlmeext->sitesurvey_res.ch[pmlmeext->sitesurvey_res.channel_idx]; ++ survey_channel = ch->hw_value; ++ ScanType = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; ++ } ++ } ++ ++ if (0){ ++#ifdef CONFIG_P2P ++ DBG_871X(FUNC_ADPT_FMT" ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n" ++ , FUNC_ADPT_ARG(padapter) ++ , survey_channel ++ , pwdinfo->find_phase_state_exchange_cnt, pmlmeext->sitesurvey_res.channel_idx ++ , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) ++ , ScanType?'A':'P', pmlmeext->sitesurvey_res.scan_mode?'A':'P' ++ , pmlmeext->sitesurvey_res.ssid[0].SsidLength?'S':' ' ++ ); ++#endif ++ #ifdef DBG_FIXED_CHAN ++ DBG_871X(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); ++ #endif ++ } ++ ++ if(survey_channel != 0) ++ { ++ //PAUSE 4-AC Queue when site_survey ++ //rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++ //val8 |= 0x0f; ++ //rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++#ifdef CONFIG_CONCURRENT_MODE ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE) ++ { ++ if( pmlmeinfo->scan_cnt == RTW_SCAN_NUM_OF_CH ) ++ { ++ pmlmeinfo->scan_cnt = 0; ++ survey_channel = pbuddy_mlmeext->cur_channel; ++ stay_buddy_ch = 1; ++ } ++ else ++ { ++ if( pmlmeinfo->scan_cnt == 0 ) ++ stay_buddy_ch = 2; ++ pmlmeinfo->scan_cnt++; ++ } ++ } ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++#endif //CONFIG_CONCURRENT_MODE ++ if(pmlmeext->sitesurvey_res.channel_idx == 0) ++ { ++#ifdef DBG_FIXED_CHAN ++ if(pmlmeext->fixed_chan !=0xff) ++ set_channel_bwmode(padapter, pmlmeext->fixed_chan, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ else ++#endif ++ set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ { ++#ifdef DBG_FIXED_CHAN ++ if(pmlmeext->fixed_chan!=0xff) ++ SelectChannel(padapter, pmlmeext->fixed_chan); ++ else ++#endif ++ SelectChannel(padapter, survey_channel); ++ } ++ ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ if( stay_buddy_ch == 1 ) ++ { ++ val8 = 0; //survey done ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ if(check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(padapter, _FW_LINKED)) ++ { ++ update_beacon(padapter->pbuddy_adapter, 0, NULL, _TRUE); ++ } ++ } ++ else if( stay_buddy_ch == 2 ) ++ { ++ val8 = 1; //under site survey ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ } ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ ++ if(ScanType == SCAN_ACTIVE) //obey the channel plan setting... ++ { ++ #ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || ++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) ++ ) ++ { ++ issue_probereq_p2p(padapter, NULL); ++ issue_probereq_p2p(padapter, NULL); ++ issue_probereq_p2p(padapter, NULL); ++ } ++ else ++ #endif //CONFIG_P2P ++ { ++ int i; ++ for(i=0;isitesurvey_res.ssid[i].SsidLength) { ++ //todo: to issue two probe req??? ++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); ++ //rtw_msleep_os(SURVEY_TO>>1); ++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); ++ } ++ } ++ ++ if(pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { ++ //todo: to issue two probe req??? ++ issue_probereq(padapter, NULL, NULL); ++ //rtw_msleep_os(SURVEY_TO>>1); ++ issue_probereq(padapter, NULL, NULL); ++ } ++ } ++ } ++#ifdef CONFIG_ATMEL_RC_PATCH ++ #ifdef CONFIG_P2P ++ if( !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) ++ ) ++ #endif//CONFIG_P2P ++ { ++ if(ScanType == SCAN_ACTIVE){ ++ if( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE){ ++ if(survey_channel == pmlmeext->cur_channel ) ++ set_survey_timer(pmlmeext, 200); ++ else ++ set_survey_timer(pmlmeext, 20); ++ } ++ else{ ++ set_survey_timer(pmlmeext, 40); ++ } ++ } ++ else{//SCAN_PASSIVE ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time); ++ } ++ } ++ else ++#endif //CONFIG_ATMEL_RC_PATCH ++ { ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ if( stay_buddy_ch == 1 ) ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time * RTW_STAY_AP_CH_MILLISECOND ); ++ else ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time); ++ } ++ } ++ else ++ { ++ ++ // channel number is 0 or this channel is not valid. ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 cur_channel; ++ u8 cur_bwmode; ++ u8 cur_ch_offset; ++ ++ if (rtw_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) ++ { ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" back to linked union - ch:%u, bw:%u, offset:%u\n", ++ FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); ++ } ++ #ifdef CONFIG_IOCTL_CFG80211 ++ else if(padapter->pbuddy_adapter ++ && pbuddy_adapter->wdinfo.driver_interface == DRIVER_CFG80211 ++ && wdev_to_priv(pbuddy_adapter->rtw_wdev)->p2p_enabled ++ && rtw_p2p_chk_state(&pbuddy_adapter->wdinfo, P2P_STATE_LISTEN) ++ ) ++ { ++ cur_channel = pbuddy_adapter->wdinfo.listen_channel; ++ cur_bwmode = pbuddy_mlmeext->cur_bwmode; ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ } ++ #endif ++ else ++ { ++ cur_channel = pmlmeext->cur_channel; ++ cur_bwmode = pmlmeext->cur_bwmode; ++ cur_ch_offset = pmlmeext->cur_ch_offset; ++ } ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) ++ { ++ if( ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) || ( pwdinfo->p2p_info.scan_op_ch_only ) ) ++ { ++ // Set the find_phase_state_exchange_cnt to P2P_FINDPHASE_EX_CNT. ++ // This will let the following flow to run the scanning end. ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); ++ } ++ #ifdef CONFIG_DBG_P2P ++ DBG_871X( "[%s] find phase exchange cnt = %d\n", __FUNCTION__, pwdinfo->find_phase_state_exchange_cnt ); ++ #endif ++ } ++ ++ if(rtw_p2p_findphase_ex_is_needed(pwdinfo)) ++ { ++ // Set the P2P State to the listen state of find phase and set the current channel to the listen channel ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ ++ initialgain = 0xff; //restore RX GAIN ++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ //turn on dynamic functions ++ Restore_DM_Func_Flag(padapter); ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE); ++ ++ _set_timer( &pwdinfo->find_phase_timer, ( u32 ) ( ( u32 ) ( pwdinfo->listen_dwell ) * 100 ) ); ++ } ++ else ++#endif //CONFIG_P2P ++ { ++ ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ pmlmeinfo->scan_cnt = 0; ++#endif //CONFIG_DMP_STA_NODE_SCAN_UNDER_AP_MODE ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ // 20100721:Interrupt scan operation here. ++ // For SW antenna diversity before link, it needs to switch to another antenna and scan again. ++ // It compares the scan result and select beter one to do connection. ++ if(rtw_hal_antdiv_before_linked(padapter)) ++ { ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ pmlmeext->sitesurvey_res.channel_idx = -1; ++ pmlmeext->chan_scan_time = SURVEY_TO /2; ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time); ++ return; ++ } ++#endif ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) ++ { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if( pwdinfo->driver_interface == DRIVER_WEXT ) ++ { ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _set_timer( &pwdinfo->ap_p2p_switch_timer, 500 ); ++ } ++ } ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ #else ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ #endif ++ } ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); ++#endif //CONFIG_P2P ++ ++ pmlmeext->sitesurvey_res.state = SCAN_COMPLETE; ++ ++ //switch back to the original channel ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++#else ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_set_channel_bwmode_survey_done(padapter); ++#else ++ if( pwdinfo->driver_interface == DRIVER_WEXT ) ++ { ++ if( rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ) ++ { ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ else if( pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++#endif //CONFIG_DUALMAC_CONCURRENT ++#endif //CONFIG_CONCURRENT_MODE ++ } ++ ++ //flush 4-AC Queue after site_survey ++ //val8 = 0; ++ //rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++ ++ //config MSR ++ Set_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ initialgain = 0xff; //restore RX GAIN ++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ //turn on dynamic functions ++ Restore_DM_Func_Flag(padapter); ++ //Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); ++ ++ if (is_client_associated_to_ap(padapter) == _TRUE) ++ { ++ issue_nulldata(padapter, NULL, 0, 3, 500); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE) ++ { ++ DBG_871X("adapter is surveydone(buddy_adapter is linked), issue nulldata(pwrbit=0)\n"); ++ ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 0, 3, 500); ++ } ++#endif ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ else if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE) ++ { ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 0, 3, 500); ++ } ++#endif ++ ++ val8 = 0; //survey done ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ report_surveydone_event(padapter); ++ ++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_RTL8723A) ++ if ((BT_1Ant(padapter) == _TRUE) && (BT_GetBtState(padapter) > BT_INFO_STATE_NO_CONNECTION)) ++ { ++ pmlmeext->chan_scan_time = SURVEY_TO * 2; ++ } ++ else ++ { ++ pmlmeext->chan_scan_time = SURVEY_TO; ++ } ++#else ++ pmlmeext->chan_scan_time = SURVEY_TO; ++#endif ++ ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ ++ issue_action_BSSCoexistPacket(padapter); ++ issue_action_BSSCoexistPacket(padapter); ++ issue_action_BSSCoexistPacket(padapter); ++ ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(padapter, _FW_LINKED)) ++ { ++ ++ DBG_871X("survey done, current CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ DBG_871X("restart pbuddy_adapter's beacon\n"); ++ ++ update_beacon(padapter->pbuddy_adapter, 0, NULL, _TRUE); ++ } ++#endif ++ ++ } ++ ++ return; ++ ++} ++ ++//collect bss info from Beacon and Probe request/response frames. ++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) ++{ ++ int i; ++ u32 len; ++ u8 *p; ++ u16 val16, subtype; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ u32 packet_len = precv_frame->u.hdr.len; ++ u8 ie_offset; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ if (len > MAX_IE_SZ) ++ { ++ //DBG_871X("IE too long for survey event\n"); ++ return _FAIL; ++ } ++ ++ _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); ++ ++ subtype = GetFrameSubType(pframe); ++ ++ if(subtype==WIFI_BEACON) { ++ bssid->Reserved[0] = 1; ++ ie_offset = _BEACON_IE_OFFSET_; ++ } else { ++ // FIXME : more type ++ if (subtype == WIFI_PROBERSP) { ++ ie_offset = _PROBERSP_IE_OFFSET_; ++ bssid->Reserved[0] = 3; ++ } else if (subtype == WIFI_PROBEREQ) { ++ ie_offset = _PROBEREQ_IE_OFFSET_; ++ bssid->Reserved[0] = 2; ++ } else { ++ bssid->Reserved[0] = 0; ++ ie_offset = _FIXED_IE_LENGTH_; ++ } ++ } ++ ++ bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; ++ ++ //below is to copy the information element ++ bssid->IELength = len; ++ _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); ++ ++ //get the signal strength ++ //bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; // 0-100 index. ++ bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; // in dBM.raw data ++ bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;//in percentage ++ bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;//in percentage ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //rtw_hal_get_hwreg(padapter, HW_VAR_CURRENT_ANTENNA, (u8 *)(&bssid->PhyInfo.Optimum_antenna)); ++ rtw_hal_get_def_var(padapter, HAL_DEF_CURRENT_ANTENNA, &bssid->PhyInfo.Optimum_antenna); ++#endif ++ ++ // checking SSID ++ if ((p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset)) == NULL) ++ { ++ DBG_871X("marc: cannot find SSID for survey event\n"); ++ return _FAIL; ++ } ++ ++ if (*(p + 1)) ++ { ++ if (len > NDIS_802_11_LENGTH_SSID) ++ { ++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); ++ return _FAIL; ++ } ++ _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); ++ bssid->Ssid.SsidLength = *(p + 1); ++ } ++ else ++ { ++ bssid->Ssid.SsidLength = 0; ++ } ++ ++ _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); ++ ++ //checking rate info... ++ i = 0; ++ p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); ++ if (p != NULL) ++ { ++ if (len > NDIS_802_11_LENGTH_RATES_EX) ++ { ++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); ++ return _FAIL; ++ } ++ _rtw_memcpy(bssid->SupportedRates, (p + 2), len); ++ i = len; ++ } ++ ++ p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); ++ if (p != NULL) ++ { ++ if (len > (NDIS_802_11_LENGTH_RATES_EX-i)) ++ { ++ DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); ++ return _FAIL; ++ } ++ _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); ++ } ++ ++ //todo: ++#if 0 ++ if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B) ++ { ++ bssid->NetworkTypeInUse = Ndis802_11DS; ++ } ++ else ++#endif ++ { ++ bssid->NetworkTypeInUse = Ndis802_11OFDM24; ++ } ++ ++ if (bssid->IELength < 12) ++ return _FAIL; ++ ++#ifdef CONFIG_P2P ++ if (subtype == WIFI_PROBEREQ) { ++ u8 *p2p_ie; ++ u32 p2p_ielen; ++ // Set Listion Channel ++ if ((p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen))) { ++ u32 attr_contentlen = 0; ++ u8 listen_ch[5] = { 0x00 }; ++ ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen); ++ bssid->Configuration.DSConfig = listen_ch[4]; ++ } ++ else { // use current channel ++ bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); ++ DBG_871X("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig); ++ } ++ ++ // FIXME ++ bssid->InfrastructureMode = Ndis802_11Infrastructure; ++ _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); ++ bssid->Privacy = 1; ++ return _SUCCESS; ++ } ++#endif //CONFIG_P2P ++ ++ // Checking for DSConfig ++ p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset); ++ ++ bssid->Configuration.DSConfig = 0; ++ bssid->Configuration.Length = 0; ++ ++ if (p) ++ { ++ bssid->Configuration.DSConfig = *(p + 2); ++ } ++ else ++ {// In 5G, some ap do not have DSSET IE ++ // checking HT info for channel ++ p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset); ++ if(p) ++ { ++ struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); ++ bssid->Configuration.DSConfig = HT_info->primary_channel; ++ } ++ else ++ { // use current channel ++ bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); ++ } ++ } ++ ++ _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); ++ bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); ++ ++ val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); ++ ++ if (val16 & BIT(0)) ++ { ++ bssid->InfrastructureMode = Ndis802_11Infrastructure; ++ _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); ++ } ++ else ++ { ++ bssid->InfrastructureMode = Ndis802_11IBSS; ++ _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); ++ } ++ ++ if (val16 & BIT(4)) ++ bssid->Privacy = 1; ++ else ++ bssid->Privacy = 0; ++ ++ bssid->Configuration.ATIMWindow = 0; ++ ++ //20/40 BSS Coexistence check ++ if((pregistrypriv->wifi_spec==1) && (_FALSE == pmlmeinfo->bwmode_updated)) ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_80211N_HT ++ p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset); ++ if(p && len>0) ++ { ++ struct HT_caps_element *pHT_caps; ++ pHT_caps = (struct HT_caps_element *)(p + 2); ++ ++ if(pHT_caps->u.HT_cap_element.HT_caps_info&BIT(14)) ++ { ++ pmlmepriv->num_FortyMHzIntolerant++; ++ } ++ } ++ else ++ { ++ pmlmepriv->num_sta_no_ht++; ++ } ++#endif //CONFIG_80211N_HT ++ ++ } ++ ++#ifdef CONFIG_INTEL_WIDI ++ //process_intel_widi_query_or_tigger(padapter, bssid); ++ if(process_intel_widi_query_or_tigger(padapter, bssid)) ++ { ++ return _FAIL; ++ } ++#endif // CONFIG_INTEL_WIDI ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1 ++ if(strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n" ++ , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig ++ , rtw_get_oper_ch(padapter) ++ , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi ++ ); ++ } ++ #endif ++ ++ // mark bss info receving from nearby channel as SignalQuality 101 ++ if(bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) ++ { ++ bssid->PhyInfo.SignalQuality= 101; ++ } ++ ++ return _SUCCESS; ++} ++ ++void start_create_ibss(_adapter* padapter) ++{ ++ unsigned short caps; ++ u8 val8; ++ u8 join_type; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; ++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); ++ ++ //update wireless mode ++ update_wireless_mode(padapter); ++ ++ //udpate capability ++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); ++ update_capinfo(padapter, caps); ++ if(caps&cap_IBSS)//adhoc master ++ { ++ //set_opmode_cmd(padapter, adhoc);//removed ++ ++ val8 = 0xcf; ++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //switch channel ++ //SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ ++ beacon_timing_control(padapter); ++ ++ //set msr to WIFI_FW_ADHOC_STATE ++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; ++ Set_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ //issue beacon ++ if(send_beacon(padapter)==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing beacon frame fail....\n")); ++ ++ report_join_res(padapter, -1); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ } ++ else ++ { ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); ++ join_type = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ report_join_res(padapter, 1); ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ rtw_indicate_connect(padapter); ++ } ++ } ++ else ++ { ++ DBG_871X("start_create_ibss, invalid cap:%x\n", caps); ++ return; ++ } ++ //update bc/mc sta_info ++ update_bmc_sta(padapter); ++ ++} ++ ++void start_clnt_join(_adapter* padapter) ++{ ++ unsigned short caps; ++ u8 val8; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ int beacon_timeout; ++ ++ //update wireless mode ++ update_wireless_mode(padapter); ++ ++ //udpate capability ++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); ++ update_capinfo(padapter, caps); ++ if (caps&cap_ESS) ++ { ++ Set_MSR(padapter, WIFI_FW_STATION_STATE); ++ ++ val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) ++ { ++ //Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. ++ val8 = 0x4c; ++ } ++#endif ++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ #ifdef CONFIG_DEAUTH_BEFORE_CONNECT ++ // Because of AP's not receiving deauth before ++ // AP may: 1)not response auth or 2)deauth us after link is complete ++ // issue deauth before issuing auth to deal with the situation ++ ++ // Commented by Albert 2012/07/21 ++ // For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. ++ { ++ #ifdef CONFIG_P2P ++ _queue *queue = &(padapter->mlmepriv.scanned_queue); ++ _list *head = get_list_head(queue); ++ _list *pos = get_next(head); ++ struct wlan_network *scanned = NULL; ++ u8 ie_offset = 0; ++ _irqL irqL; ++ bool has_p2p_ie = _FALSE; ++ ++ _enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); ++ ++ for (pos = get_next(head);!rtw_end_of_queue_search(head, pos); pos = get_next(pos)) { ++ ++ scanned = LIST_CONTAINOR(pos, struct wlan_network, list); ++ if(scanned==NULL) ++ rtw_warn_on(1); ++ ++ if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE ++ && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ++ ) { ++ ie_offset = (scanned->network.Reserved[0] == 2? 0:12); ++ if (rtw_get_p2p_ie(scanned->network.IEs+ie_offset, scanned->network.IELength-ie_offset, NULL, NULL)) ++ has_p2p_ie = _TRUE; ++ break; ++ } ++ } ++ ++ _exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); ++ ++ if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE) ++ #endif /* CONFIG_P2P */ ++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 5, 100); ++ } ++ #endif /* CONFIG_DEAUTH_BEFORE_CONNECT */ ++ ++ //here wait for receiving the beacon to start auth ++ //and enable a timer ++ beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval); ++ set_link_timer(pmlmeext, beacon_timeout); ++ _set_timer( &padapter->mlmepriv.assoc_timer, ++ (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO*REASSOC_LIMIT) +beacon_timeout); ++ ++ pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; ++ ++ {//only for STA mode ++ u16 media_status; ++ u8 mac_id = 0; ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(PRIMARY_ADAPTER == padapter->adapter_type) ++ mac_id=0; ++ else ++ mac_id=2; ++ #endif ++ media_status = (mac_id<<8)|1; // MACID|OPMODE:1 connect ++ rtw_hal_set_hwreg(padapter,HW_VAR_H2C_MEDIA_STATUS_RPT,(u8 *)&media_status); ++ } ++ } ++ else if (caps&cap_IBSS) //adhoc client ++ { ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if(dc_handle_join_request(padapter) == _FAIL) ++ { ++ DBG_871X("dc_handle_join_request for Ad-hoc fail !!!\n"); ++ return; ++ } ++#endif ++ ++ Set_MSR(padapter, WIFI_FW_ADHOC_STATE); ++ ++ val8 = 0xcf; ++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ beacon_timing_control(padapter); ++ ++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; ++ ++ report_join_res(padapter, 1); ++ } ++ else ++ { ++ //DBG_871X("marc: invalid cap:%x\n", caps); ++ return; ++ } ++ ++} ++ ++void start_clnt_auth(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); ++ pmlmeinfo->state |= WIFI_FW_AUTH_STATE; ++ ++ pmlmeinfo->auth_seq = 1; ++ pmlmeinfo->reauth_count = 0; ++ pmlmeinfo->reassoc_count = 0; ++ pmlmeinfo->link_count = 0; ++ pmlmeext->retry = 0; ++ ++ ++ DBG_871X_LEVEL(_drv_always_, "start auth\n"); ++ issue_auth(padapter, NULL, 0); ++ ++ set_link_timer(pmlmeext, REAUTH_TO); ++ ++} ++ ++ ++void start_clnt_assoc(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); ++ pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); ++ ++ issue_assocreq(padapter); ++ ++ set_link_timer(pmlmeext, REASSOC_TO); ++} ++ ++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //check A3 ++ if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_del_sta_event(padapter, MacAddr, reason); ++ ++ } ++ else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -2); ++ } ++ } ++ ++ return _SUCCESS; ++} ++ ++#ifdef CONFIG_80211D ++static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) ++{ ++ struct registry_priv *pregistrypriv; ++ struct mlme_ext_priv *pmlmeext; ++ RT_CHANNEL_INFO *chplan_new; ++ u8 channel; ++ u8 i; ++ ++ ++ pregistrypriv = &padapter->registrypriv; ++ pmlmeext = &padapter->mlmeextpriv; ++ ++ // Adjust channel plan by AP Country IE ++ if (pregistrypriv->enable80211d && ++ (!pmlmeext->update_channel_plan_by_ap_done)) ++ { ++ u8 *ie, *p; ++ u32 len; ++ RT_CHANNEL_PLAN chplan_ap; ++ RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM]; ++ u8 country[4]; ++ u8 fcn; // first channel number ++ u8 noc; // number of channel ++ u8 j, k; ++ ++ ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if (!ie) return; ++ if (len < 6) return; ++ ++ ie += 2; ++ p = ie; ++ ie += len; ++ ++ _rtw_memset(country, 0, 4); ++ _rtw_memcpy(country, p, 3); ++ p += 3; ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ++ ("%s: 802.11d country=%s\n", __FUNCTION__, country)); ++ ++ i = 0; ++ while ((ie - p) >= 3) ++ { ++ fcn = *(p++); ++ noc = *(p++); ++ p++; ++ ++ for (j = 0; j < noc; j++) ++ { ++ if (fcn <= 14) channel = fcn + j; // 2.4 GHz ++ else channel = fcn + j*4; // 5 GHz ++ ++ chplan_ap.Channel[i++] = channel; ++ } ++ } ++ chplan_ap.Len = i; ++ ++#ifdef CONFIG_DEBUG_RTL871X ++#ifdef PLATFORM_LINUX ++ i = 0; ++ DBG_871X("%s: AP[%s] channel plan {", __func__, bssid->Ssid.Ssid); ++ while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) ++ { ++ DBG_8192C("%02d,", chplan_ap.Channel[i]); ++ i++; ++ } ++ DBG_871X("}\n"); ++#endif ++#endif ++ ++ _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta)); ++#ifdef CONFIG_DEBUG_RTL871X ++#ifdef PLATFORM_LINUX ++ i = 0; ++ DBG_871X("%s: STA channel plan {", __func__); ++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) ++ { ++ DBG_871X("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType==SCAN_PASSIVE?'p':'a'); ++ i++; ++ } ++ DBG_871X("}\n"); ++#endif ++#endif ++ ++ _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set)); ++ chplan_new = pmlmeext->channel_set; ++ ++ i = j = k = 0; ++ if (pregistrypriv->wireless_mode & WIRELESS_11G) ++ { ++ do { ++ if ((i == MAX_CHANNEL_NUM) || ++ (chplan_sta[i].ChannelNum == 0) || ++ (chplan_sta[i].ChannelNum > 14)) ++ break; ++ ++ if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14)) ++ break; ++ ++ if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ i++; ++ j++; ++ k++; ++ } ++ else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++// chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ chplan_new[k].ScanType = SCAN_PASSIVE; ++ i++; ++ k++; ++ } ++ else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ j++; ++ k++; ++ } ++ } while (1); ++ ++ // change AP not support channel to Passive scan ++ while ((i < MAX_CHANNEL_NUM) && ++ (chplan_sta[i].ChannelNum != 0) && ++ (chplan_sta[i].ChannelNum <= 14)) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++// chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ chplan_new[k].ScanType = SCAN_PASSIVE; ++ i++; ++ k++; ++ } ++ ++ // add channel AP supported ++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ j++; ++ k++; ++ } ++ } ++ else ++ { ++ // keep original STA 2.4G channel plan ++ while ((i < MAX_CHANNEL_NUM) && ++ (chplan_sta[i].ChannelNum != 0) && ++ (chplan_sta[i].ChannelNum <= 14)) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++ chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ i++; ++ k++; ++ } ++ ++ // skip AP 2.4G channel plan ++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) ++ { ++ j++; ++ } ++ } ++ ++ if (pregistrypriv->wireless_mode & WIRELESS_11A) ++ { ++ do { ++ if ((i == MAX_CHANNEL_NUM) || ++ (chplan_sta[i].ChannelNum == 0)) ++ break; ++ ++ if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0)) ++ break; ++ ++ if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ i++; ++ j++; ++ k++; ++ } ++ else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++// chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ chplan_new[k].ScanType = SCAN_PASSIVE; ++ i++; ++ k++; ++ } ++ else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ j++; ++ k++; ++ } ++ } while (1); ++ ++ // change AP not support channel to Passive scan ++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++// chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ chplan_new[k].ScanType = SCAN_PASSIVE; ++ i++; ++ k++; ++ } ++ ++ // add channel AP supported ++ while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) ++ { ++ chplan_new[k].ChannelNum = chplan_ap.Channel[j]; ++ chplan_new[k].ScanType = SCAN_ACTIVE; ++ j++; ++ k++; ++ } ++ } ++ else ++ { ++ // keep original STA 5G channel plan ++ while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) ++ { ++ chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; ++ chplan_new[k].ScanType = chplan_sta[i].ScanType; ++ i++; ++ k++; ++ } ++ } ++ ++ pmlmeext->update_channel_plan_by_ap_done = 1; ++ ++#ifdef CONFIG_DEBUG_RTL871X ++#ifdef PLATFORM_LINUX ++ k = 0; ++ DBG_871X("%s: new STA channel plan {", __func__); ++ while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) ++ { ++ DBG_871X("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType==SCAN_PASSIVE?'p':'c'); ++ k++; ++ } ++ DBG_871X("}\n"); ++#endif ++#endif ++ ++#if 0 ++ // recover the right channel index ++ channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ k = 0; ++ while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) ++ { ++ if (chplan_new[k].ChannelNum == channel) { ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ++ ("%s: change mlme_ext sitesurvey channel index from %d to %d\n", ++ __FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k)); ++ pmlmeext->sitesurvey_res.channel_idx = k; ++ break; ++ } ++ k++; ++ } ++#endif ++ } ++ ++ // If channel is used by AP, set channel scan type to active ++ channel = bssid->Configuration.DSConfig; ++ chplan_new = pmlmeext->channel_set; ++ i = 0; ++ while ((i < MAX_CHANNEL_NUM) && (chplan_new[i].ChannelNum != 0)) ++ { ++ if (chplan_new[i].ChannelNum == channel) ++ { ++ if (chplan_new[i].ScanType == SCAN_PASSIVE) ++ { ++ //5G Bnad 2, 3 (DFS) doesn't change to active scan ++ if(channel >= 52 && channel <= 144) ++ break; ++ ++ chplan_new[i].ScanType = SCAN_ACTIVE; ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ++ ("%s: change channel %d scan type from passive to active\n", ++ __FUNCTION__, channel)); ++ } ++ break; ++ } ++ i++; ++ } ++} ++#endif ++ ++/**************************************************************************** ++ ++Following are the functions to report events ++ ++*****************************************************************************/ ++ ++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct survey_event *psurvey_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext; ++ struct cmd_priv *pcmdpriv; ++ //u8 *pframe = precv_frame->u.hdr.rx_data; ++ //uint len = precv_frame->u.hdr.len; ++ ++ if(!padapter) ++ return; ++ ++ pmlmeext = &padapter->mlmeextpriv; ++ pcmdpriv = &padapter->cmdpriv; ++ ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct survey_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ psurvey_evt = (struct survey_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ ++ if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *)pevtcmd, cmdsz); ++ return; ++ } ++ ++#ifdef CONFIG_80211D ++ process_80211d(padapter, &psurvey_evt->bss); ++#endif ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ pmlmeext->sitesurvey_res.bss_cnt++; ++ ++ return; ++ ++} ++ ++void report_surveydone_event(_adapter *padapter) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct surveydone_event *psurveydone_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct surveydone_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ psurveydone_evt = (struct surveydone_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; ++ ++ DBG_871X("survey done event(%x)\n", psurveydone_evt->bss_cnt); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++ ++} ++ ++void report_join_res(_adapter *padapter, int res) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct joinbss_event *pjoinbss_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct joinbss_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ pjoinbss_evt = (struct joinbss_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); ++ pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res; ++ ++ DBG_871X("report_join_res(%d)\n", res); ++ ++ ++ rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network); ++ ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++ ++} ++ ++void report_del_sta_event(_adapter *padapter, unsigned char* MacAddr, unsigned short reason) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct sta_info *psta; ++ int mac_id; ++ struct stadel_event *pdel_sta_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct stadel_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ pdel_sta_evt = (struct stadel_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); ++ _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd),(unsigned char *)(&reason),2); ++ ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); ++ if(psta) ++ mac_id = (int)psta->mac_id; ++ else ++ mac_id = (-1); ++ ++ pdel_sta_evt->mac_id = mac_id; ++ ++ DBG_871X("report_del_sta_event: delete STA, mac_id=%d\n", mac_id); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++} ++ ++void report_add_sta_event(_adapter *padapter, unsigned char* MacAddr, int cam_idx) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct stassoc_event *padd_sta_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct stassoc_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ padd_sta_evt = (struct stassoc_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); ++ padd_sta_evt->cam_id = cam_idx; ++ ++ DBG_871X("report_add_sta_event: add STA\n"); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++} ++ ++ ++/**************************************************************************** ++ ++Following are the event callback functions ++ ++*****************************************************************************/ ++ ++//for sta/adhoc mode ++void update_sta_info(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //ERP ++ VCS_update(padapter, psta); ++ ++#ifdef CONFIG_80211N_HT ++ //HT ++ if(pmlmepriv->htpriv.ht_option) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ ++ psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; ++ ++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps))) ++ psta->htpriv.sgi = _TRUE; ++ ++ psta->qos_option = _TRUE; ++ ++ } ++ else ++#endif //CONFIG_80211N_HT ++ { ++#ifdef CONFIG_80211N_HT ++ psta->htpriv.ht_option = _FALSE; ++ ++ psta->htpriv.ampdu_enable = _FALSE; ++ ++ psta->htpriv.sgi = _FALSE; ++#endif //CONFIG_80211N_HT ++ psta->qos_option = _FALSE; ++ ++ } ++#ifdef CONFIG_80211N_HT ++ psta->htpriv.bwmode = pmlmeext->cur_bwmode; ++ psta->htpriv.ch_offset = pmlmeext->cur_ch_offset; ++ ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++#endif //CONFIG_80211N_HT ++ ++ //QoS ++ if(pmlmepriv->qospriv.qos_option) ++ psta->qos_option = _TRUE; ++ ++ ++ psta->state = _FW_LINKED; ++ ++} ++ ++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) ++{ ++ struct sta_info *psta, *psta_bmc; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 join_type; ++ u16 media_status; ++ ++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); ++ ++ if(join_res < 0) ++ { ++ join_type = 1; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); ++ ++ //restore to initial setting. ++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); ++ ++ if (psta){//only for STA mode ++ media_status = (psta->mac_id<<8)|0; // MACID|OPMODE:1 connect ++ rtw_hal_set_hwreg(padapter,HW_VAR_H2C_MEDIA_STATUS_RPT,(u8 *)&media_status); ++ } ++ ++ goto exit_mlmeext_joinbss_event_callback; ++ } ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ //for bc/mc ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(psta_bmc) ++ { ++ pmlmeinfo->FW_sta_info[psta_bmc->mac_id].psta = psta_bmc; ++ update_bmc_sta_support_rate(padapter, psta_bmc->mac_id); ++ Update_RA_Entry(padapter, psta_bmc); ++ } ++ //update bc/mc sta_info ++ update_bmc_sta(padapter); ++ } ++ ++ ++ //turn on dynamic functions ++ Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); ++ ++ // update IOT-releated issue ++ update_IOT_info(padapter); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates); ++ ++ //BCN interval ++ rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval)); ++ ++ //udpate capability ++ update_capinfo(padapter, pmlmeinfo->capability); ++ ++ //WMM, Update EDCA param ++ WMMOnAssocRsp(padapter); ++ ++ //HT ++ HTOnAssocRsp(padapter); ++ ++#ifndef CONFIG_CONCURRENT_MODE ++ // Call set_channel_bwmode when the CONFIG_CONCURRENT_MODE doesn't be defined. ++ //Set cur_channel&cur_bwmode&cur_ch_offset ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++#endif ++ ++ ++ if (psta) //only for infra. mode ++ { ++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta; ++ ++ //DBG_871X("set_sta_rate\n"); ++ ++ psta->wireless_mode = pmlmeext->cur_wireless_mode; ++ ++ //set per sta rate after updating HT cap. ++ set_sta_rate(padapter, psta); ++ ++ rtw_sta_media_status_rpt(padapter, psta, 1); ++ } ++ ++ join_type = 2; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ // correcting TSF ++ correct_TSF(padapter, pmlmeext); ++ ++ //set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++ ++#ifdef CONFIG_LPS ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0); ++#endif ++ ++exit_mlmeext_joinbss_event_callback: ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_handle_join_done(padapter, join_res); ++#endif ++#ifdef CONFIG_CONCURRENT_MODE ++ concurrent_chk_joinbss_done(padapter, join_res); ++#endif ++ ++ DBG_871X("=>%s\n", __FUNCTION__); ++ ++} ++ ++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 join_type; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ if(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)//adhoc master or sta_count>1 ++ { ++ //nothing to do ++ } ++ else//adhoc client ++ { ++ //update TSF Value ++ //update_TSF(pmlmeext, pframe, len); ++ ++ // correcting TSF ++ correct_TSF(padapter, pmlmeext); ++ ++ //start beacon ++ if(send_beacon(padapter)==_FAIL) ++ { ++ pmlmeinfo->FW_sta_info[psta->mac_id].status = 0; ++ ++ pmlmeinfo->state ^= WIFI_FW_ADHOC_STATE; ++ ++ return; ++ } ++ ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ } ++ ++ join_type = 2; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ } ++ ++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta; ++ ++ //rate radaptive ++ Update_RA_Entry(padapter, psta); ++ ++ //update adhoc sta_info ++ update_sta_info(padapter, psta); ++ ++} ++ ++void mlmeext_sta_del_event_callback(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) ++ { ++ //set_opmode_cmd(padapter, infra_client_with_mlme); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); ++ ++ //restore to initial setting. ++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_set_channel_bwmode_disconnect(padapter); ++#else ++#ifdef CONFIG_CONCURRENT_MODE ++ if((check_buddy_fwstate(padapter, _FW_LINKED)) != _TRUE) ++ { ++#endif //CONFIG_CONCURRENT_MODE ++ ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ } ++#endif //CONFIG_CONCURRENT_MODE ++#endif //CONFIG_DUALMAC_CONCURRENT ++ ++ flush_all_cam_entry(padapter); ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ //set MSR to no link state -> infra. mode ++ Set_MSR(padapter, _HW_STATE_STATION_); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ } ++ ++} ++ ++/**************************************************************************** ++ ++Following are the functions for the timer handlers ++ ++*****************************************************************************/ ++void _linked_rx_signal_strehgth_display(_adapter *padapter); ++void _linked_rx_signal_strehgth_display(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 mac_id; ++ int UndecoratedSmoothedPWDB; ++ #if 0 ++ DBG_871X("============ linked status check ===================\n"); ++ DBG_871X("pathA Rx SNRdb:%d, pathB Rx SNRdb:%d\n",padapter->recvpriv.RxSNRdB[0], padapter->recvpriv.RxSNRdB[1]); ++ DBG_871X("pathA Rx PWDB:%d\n",padapter->recvpriv.rxpwdb); ++ rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); ++ DBG_871X("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB); ++ DBG_871X("Rx RSSI:%d\n",padapter->recvpriv.rssi); ++ DBG_871X("Rx Signal_strength:%d\n",padapter->recvpriv.signal_strength); ++ DBG_871X("Rx Signal_qual:%d \n",padapter->recvpriv.signal_qual); ++ if ( check_fwstate( &padapter->mlmepriv, _FW_LINKED ) ) ++ { ++ DBG_871X("bw mode: %d, channel: %d\n", padapter->mlmeextpriv.cur_bwmode, padapter->mlmeextpriv.cur_channel ); ++ DBG_871X("received bytes = %d\n", (u32) (padapter->recvpriv.rx_bytes - padapter->recvpriv.last_rx_bytes ) ); ++ } ++ DBG_871X("============ linked status check ===================\n"); ++ #endif ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ mac_id=0; ++ } ++ else if((pmlmeinfo->state&0x03) == _HW_STATE_AP_) ++ { ++ mac_id=2; ++ } ++ ++ rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP,&mac_id); ++ #if 0 ++ DBG_871X("============ RX GAIN / FALSE ALARM ===================\n"); ++ DBG_871X(" DIG PATH-A(0x%02x), PATH-B(0x%02x)\n",rtw_read8(padapter,0xc50),rtw_read8(padapter,0xc58)); ++ DBG_871X(" OFDM -Alarm DA2(0x%04x),DA4(0x%04x),DA6(0x%04x),DA8(0x%04x)\n", ++ rtw_read16(padapter,0xDA2),rtw_read16(padapter,0xDA4),rtw_read16(padapter,0xDA6),rtw_read16(padapter,0xDA8)); ++ ++ DBG_871X(" CCK -Alarm A5B(0x%02x),A5C(0x%02x)\n",rtw_read8(padapter,0xA5B),rtw_read8(padapter,0xA5C)); ++ #endif ++ ++ ++ //rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); ++ //DBG_871X("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB); ++ ++} ++ ++u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) ++{ ++ u8 ret = _FALSE; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" ++ /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ ++ ", retry:%u\n" ++ , FUNC_ADPT_ARG(padapter) ++ , STA_RX_PKTS_DIFF_ARG(psta) ++ , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts ++ , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts ++ /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts ++ , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts ++ , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts ++ , pmlmeinfo->bcn_interval*/ ++ , pmlmeext->retry ++ ); ++ ++ DBG_871X(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) ++ , padapter->xmitpriv.tx_pkts ++ , pmlmeinfo->link_count ++ ); ++ #endif ++ ++ if((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)) ++ && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) ++ && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta) ++ ) ++ { ++ ret = _FALSE; ++ } ++ else ++ { ++ ret = _TRUE; ++ } ++ ++ sta_update_last_rx_pkts(psta); ++ ++ return ret; ++} ++ ++void linked_status_chk(_adapter *padapter) ++{ ++ u32 i; ++ struct sta_info *psta; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(padapter->bRxRSSIDisplay) ++ _linked_rx_signal_strehgth_display(padapter); ++ ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ rtw_hal_sreset_linked_status_check(padapter); ++ #endif ++ ++ if (is_client_associated_to_ap(padapter)) ++ { ++ //linked infrastructure client mode ++ ++ int tx_chk = _SUCCESS, rx_chk = _SUCCESS; ++ int rx_chk_limit; ++ ++ #if defined(DBG_ROAMING_TEST) ++ rx_chk_limit = 1; ++ #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) ++ rx_chk_limit = 4; ++ #else ++ rx_chk_limit = 8; ++ #endif ++ ++ // Marked by Kurt 20130715 ++ // For WiDi 3.5 and latered on, they don't ask WiDi sink to do roaming, so we could not check rx limit that strictly. ++ // todo: To check why we under miracast session, rx_chk would be _FALSE ++ //#ifdef CONFIG_INTEL_WIDI ++ //if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE) ++ // rx_chk_limit = 1; ++ //#endif ++ ++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ { ++ bool is_p2p_enable = _FALSE; ++ #ifdef CONFIG_P2P ++ is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE); ++ #endif ++ ++ if (chk_ap_is_alive(padapter, psta) == _FALSE) ++ rx_chk = _FAIL; ++ ++ if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) ++ tx_chk = _FAIL; ++ ++ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)) { ++ u8 backup_oper_channel=0; ++ ++ /* switch to correct channel of current network before issue keep-alive frames */ ++ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { ++ backup_oper_channel = rtw_get_oper_ch(padapter); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ } ++ ++ if (rx_chk != _SUCCESS) ++ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 3, 1); ++ ++ if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == 0xf) || rx_chk != _SUCCESS) { ++ tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1); ++ /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ ++ if (tx_chk == _SUCCESS && !is_p2p_enable) ++ rx_chk = _SUCCESS; ++ } ++ ++ /* back to the original operation channel */ ++ if(backup_oper_channel>0) ++ SelectChannel(padapter, backup_oper_channel); ++ ++ } ++ else ++ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ ++ { ++ if (rx_chk != _SUCCESS) { ++ if (pmlmeext->retry == 0) { ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); ++ #endif ++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress); ++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress); ++ issue_probereq(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress); ++ } ++ } ++ ++ if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == 0xf) { ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("%s issue_nulldata 0\n", __FUNCTION__); ++ #endif ++ tx_chk = issue_nulldata(padapter, NULL, 0, 1, 0); ++ } ++ } ++ ++ if (rx_chk == _FAIL) { ++ pmlmeext->retry++; ++ if (pmlmeext->retry > rx_chk_limit) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" disconnect or roaming\n", ++ FUNC_ADPT_ARG(padapter)); ++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress ++ , WLAN_REASON_EXPIRATION_CHK); ++ return; ++ } ++ } else { ++ pmlmeext->retry = 0; ++ } ++ ++ if (tx_chk == _FAIL) { ++ pmlmeinfo->link_count &= 0xf; ++ } else { ++ pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; ++ pmlmeinfo->link_count = 0; ++ } ++ ++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) ++ } ++ else if (is_client_associated_to_ibss(padapter)) ++ { ++ //linked IBSS mode ++ //for each assoc list entry to check the rx pkt counter ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ psta = pmlmeinfo->FW_sta_info[i].psta; ++ ++ if(NULL==psta) continue; ++ ++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == sta_rx_pkts(psta)) ++ { ++ ++ if(pmlmeinfo->FW_sta_info[i].retry<3) ++ { ++ pmlmeinfo->FW_sta_info[i].retry++; ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].retry = 0; ++ pmlmeinfo->FW_sta_info[i].status = 0; ++ report_del_sta_event(padapter, psta->hwaddr ++ , 65535// indicate disconnect caused by no rx ++ ); ++ } ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].retry = 0; ++ pmlmeinfo->FW_sta_info[i].rx_pkt = (u32)sta_rx_pkts(psta); ++ } ++ } ++ } ++ ++ //set_link_timer(pmlmeext, DISCONNECT_TO); ++ ++ } ++ ++} ++ ++void survey_timer_hdl(_adapter *padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct sitesurvey_parm *psurveyPara; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif ++ ++ //DBG_871X("marc: survey timer\n"); ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_lock(NULL); ++ if (callout_pending(&padapter->mlmeextpriv.survey_timer.callout)) { ++ /* callout was reset */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ if (!callout_active(&padapter->mlmeextpriv.survey_timer.callout)) { ++ /* callout was stopped */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ callout_deactivate(&padapter->mlmeextpriv.survey_timer.callout); ++ ++ ++#endif ++ ++ //issue rtw_sitesurvey_cmd ++ if (pmlmeext->sitesurvey_res.state > SCAN_START) ++ { ++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ if( padapter->mlmeextpriv.mlmext_info.scan_cnt != RTW_SCAN_NUM_OF_CH ) ++#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ pmlmeext->sitesurvey_res.channel_idx++; ++ } ++ ++ if(pmlmeext->scan_abort == _TRUE) ++ { ++ #ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); ++ pmlmeext->sitesurvey_res.channel_idx = 3; ++ DBG_871X("%s idx:%d, cnt:%u\n", __FUNCTION__ ++ , pmlmeext->sitesurvey_res.channel_idx ++ , pwdinfo->find_phase_state_exchange_cnt ++ ); ++ } ++ else ++ #endif ++ { ++ pmlmeext->sitesurvey_res.channel_idx = pmlmeext->sitesurvey_res.ch_num; ++ DBG_871X("%s idx:%d\n", __FUNCTION__ ++ , pmlmeext->sitesurvey_res.channel_idx ++ ); ++ } ++ ++ pmlmeext->scan_abort = _FALSE;//reset ++ } ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ goto exit_survey_timer_hdl; ++ } ++ ++ if ((psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ goto exit_survey_timer_hdl; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); ++ rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ ++ ++exit_survey_timer_hdl: ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_unlock(NULL); ++#endif ++ ++ return; ++} ++ ++void link_timer_hdl(_adapter *padapter) ++{ ++ //static unsigned int rx_pkt = 0; ++ //static u64 tx_cnt = 0; ++ //struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_lock(NULL); ++ if (callout_pending(&padapter->mlmeextpriv.survey_timer.callout)) { ++ /* callout was reset */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ if (!callout_active(&padapter->mlmeextpriv.survey_timer.callout)) { ++ /* callout was stopped */ ++ //mtx_unlock(&sc->sc_mtx); ++ rtw_mtx_unlock(NULL); ++ return; ++ } ++ callout_deactivate(&padapter->mlmeextpriv.survey_timer.callout); ++ ++ ++#endif ++ ++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) ++ { ++ DBG_871X("link_timer_hdl:no beacon while connecting\n"); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -3); ++ } ++ else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) ++ { ++ //re-auth timer ++ if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) ++ { ++ //if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) ++ //{ ++ pmlmeinfo->state = 0; ++ report_join_res(padapter, -1); ++ return; ++ //} ++ //else ++ //{ ++ // pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; ++ // pmlmeinfo->reauth_count = 0; ++ //} ++ } ++ ++ DBG_871X("link_timer_hdl: auth timeout and try again\n"); ++ pmlmeinfo->auth_seq = 1; ++ issue_auth(padapter, NULL, 0); ++ set_link_timer(pmlmeext, REAUTH_TO); ++ } ++ else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) ++ { ++ //re-assoc timer ++ if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -2); ++ return; ++ } ++ ++ DBG_871X("link_timer_hdl: assoc timeout and try again\n"); ++ issue_assocreq(padapter); ++ set_link_timer(pmlmeext, REASSOC_TO); ++ } ++#if 0 ++ else if (is_client_associated_to_ap(padapter)) ++ { ++ //linked infrastructure client mode ++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ { ++ /*to monitor whether the AP is alive or not*/ ++ if (rx_pkt == psta->sta_stats.rx_pkts) ++ { ++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress); ++ return; ++ } ++ else ++ { ++ rx_pkt = psta->sta_stats.rx_pkts; ++ set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++ ++ //update the EDCA paramter according to the Tx/RX mode ++ update_EDCA_param(padapter); ++ ++ /*to send the AP a nulldata if no frame is xmitted in order to keep alive*/ ++ if (pmlmeinfo->link_count++ == 0) ++ { ++ tx_cnt = pxmitpriv->tx_pkts; ++ } ++ else if ((pmlmeinfo->link_count & 0xf) == 0) ++ { ++ if (tx_cnt == pxmitpriv->tx_pkts) ++ { ++ issue_nulldata(padapter, NULL, 0, 0, 0); ++ } ++ ++ tx_cnt = pxmitpriv->tx_pkts; ++ } ++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) ++ } ++ else if (is_client_associated_to_ibss(padapter)) ++ { ++ //linked IBSS mode ++ //for each assoc list entry to check the rx pkt counter ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ psta = pmlmeinfo->FW_sta_info[i].psta; ++ ++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == psta->sta_stats.rx_pkts) ++ { ++ pmlmeinfo->FW_sta_info[i].status = 0; ++ report_del_sta_event(padapter, psta->hwaddr); ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].rx_pkt = psta->sta_stats.rx_pkts; ++ } ++ } ++ } ++ ++ set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++ rtw_mtx_unlock(NULL); ++#endif ++ ++ return; ++} ++ ++void addba_timer_hdl(struct sta_info *psta) ++{ ++#ifdef CONFIG_80211N_HT ++ struct ht_priv *phtpriv; ++ ++ if(!psta) ++ return; ++ ++ phtpriv = &psta->htpriv; ++ ++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) ++ { ++ if(phtpriv->candidate_tid_bitmap) ++ phtpriv->candidate_tid_bitmap=0x0; ++ ++ } ++#endif //CONFIG_80211N_HT ++} ++ ++#ifdef CONFIG_IEEE80211W ++void sa_query_timer_hdl(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv * pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ //disconnect ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ rtw_disassoc_cmd(padapter, 0, _TRUE); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ DBG_871X("SA query timeout disconnect\n"); ++} ++#endif //CONFIG_IEEE80211W ++ ++u8 NULL_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ return H2C_SUCCESS; ++} ++ ++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ u8 type; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; ++ ++ if(psetop->mode == Ndis802_11APMode) ++ { ++ pmlmeinfo->state = WIFI_FW_AP_STATE; ++ type = _HW_STATE_AP_; ++#ifdef CONFIG_NATIVEAP_MLME ++ //start_ap_mode(padapter); ++#endif ++ } ++ else if(psetop->mode == Ndis802_11Infrastructure) ++ { ++ pmlmeinfo->state &= ~(BIT(0)|BIT(1));// clear state ++ pmlmeinfo->state |= WIFI_FW_STATION_STATE;//set to STATION_STATE ++ type = _HW_STATE_STATION_; ++ } ++ else if(psetop->mode == Ndis802_11IBSS) ++ { ++ type = _HW_STATE_ADHOC_; ++ } ++ else ++ { ++ type = _HW_STATE_NOLINK_; ++ } ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); ++ //Set_NETYPE0_MSR(padapter, type); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 createbss_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; ++ //u32 initialgain; ++ ++ ++ if(pparm->network.InfrastructureMode == Ndis802_11APMode) ++ { ++#ifdef CONFIG_AP_MODE ++ ++ if(pmlmeinfo->state == WIFI_FW_AP_STATE) ++ { ++ //todo: ++ return H2C_SUCCESS; ++ } ++#endif ++ } ++ ++ //below is for ad-hoc master ++ if(pparm->network.InfrastructureMode == Ndis802_11IBSS) ++ { ++ rtw_joinbss_reset(padapter); ++ ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmlmeinfo->ERP_enable = 0; ++ pmlmeinfo->WMM_enable = 0; ++ pmlmeinfo->HT_enable = 0; ++ pmlmeinfo->HT_caps_enable = 0; ++ pmlmeinfo->HT_info_enable = 0; ++ pmlmeinfo->agg_enable_bitmap = 0; ++ pmlmeinfo->candidate_tid_bitmap = 0; ++ ++ //disable dynamic functions, such as high power, DIG ++ Save_DM_Func_Flag(padapter); ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under linking, need to write the BB registers ++ //initialgain = 0x1E; ++ //rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ //cancel link timer ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //clear CAM ++ flush_all_cam_entry(padapter); ++ ++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); ++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; ++ ++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength ++ return H2C_PARAMETERS_ERROR; ++ ++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); ++ ++ start_create_ibss(padapter); ++ ++ } ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ u8 join_type; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; ++#endif //CONFIG_ANTENNA_DIVERSITY ++ u32 i; ++ //u32 initialgain; ++ //u32 acparm; ++ u8 ch, bw, offset; ++ ++ //check already connecting to AP or not ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ if (pmlmeinfo->state & WIFI_FW_STATION_STATE) ++ { ++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 5, 100); ++ } ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ //clear CAM ++ flush_all_cam_entry(padapter); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //set MSR to nolink -> infra. mode ++ //Set_MSR(padapter, _HW_STATE_NOLINK_); ++ Set_MSR(padapter, _HW_STATE_STATION_); ++ ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ } ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE); ++#endif ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_clear_all_cam_entry(padapter); ++#endif ++ ++ rtw_joinbss_reset(padapter); ++ ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmlmeinfo->ERP_enable = 0; ++ pmlmeinfo->WMM_enable = 0; ++ pmlmeinfo->HT_enable = 0; ++ pmlmeinfo->HT_caps_enable = 0; ++ pmlmeinfo->HT_info_enable = 0; ++ pmlmeinfo->agg_enable_bitmap = 0; ++ pmlmeinfo->candidate_tid_bitmap = 0; ++ pmlmeinfo->bwmode_updated = _FALSE; ++ //pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; ++ ++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); ++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; ++ ++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength ++ return H2C_PARAMETERS_ERROR; ++ ++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); ++ ++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; ++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); ++ ++ //Check AP vendor to move rtw_joinbss_cmd() ++ //pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); ++ ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_://Get WMM IE. ++ if ( _rtw_memcmp(pIE->data, WMM_OUI, 4) ) ++ { ++ pmlmeinfo->WMM_enable = 1; ++ } ++ break; ++ ++ case _HT_CAPABILITY_IE_: //Get HT Cap IE. ++ pmlmeinfo->HT_caps_enable = 1; ++ break; ++ ++ case _HT_EXTRA_INFO_IE_: //Get HT Info IE. ++#ifdef CONFIG_80211N_HT ++ pmlmeinfo->HT_info_enable = 1; ++ ++ //spec case only for cisco's ap because cisco's ap issue assoc rsp using mcs rate @40MHz or @20MHz ++//#if !defined(CONFIG_CONCURRENT_MODE) && !defined(CONFIG_DUALMAC_CONCURRENT) ++// if(pmlmeinfo->assoc_AP_vendor == ciscoAP) ++//#endif ++ { ++ struct HT_info_element *pht_info = (struct HT_info_element *)(pIE->data); ++ ++ if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode according to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch (pht_info->infos[0] & 0x3) ++ { ++ case 1: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ DBG_871X("set ch/bw before connected\n"); ++ } ++ } ++#endif //CONFIG_80211N_HT ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++#if 0 ++ if (padapter->registrypriv.wifi_spec) { ++ // for WiFi test, follow WMM test plan spec ++ acparm = 0x002F431C; // VO ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E541C; // VI ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ acparm = 0x0000A525; // BE ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A549; // BK ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ ++ // for WiFi test, mixed mode with intel STA under bg mode throughput issue ++ if (padapter->mlmepriv.htpriv.ht_option == _FALSE){ ++ acparm = 0x00004320; ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ } ++ } ++ else { ++ acparm = 0x002F3217; // VO ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E4317; // VI ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ acparm = 0x00105320; // BE ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A444; // BK ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ } ++#endif ++ ++ /* check channel, bandwidth, offset and switch */ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if(dc_handle_join_request(padapter, &ch, &bw, &offset) == _FAIL) { ++ DBG_871X("dc_handle_join_request fail !!!\n"); ++ return H2C_SUCCESS; ++ } ++#else //NON CONFIG_DUALMAC_CONCURRENT ++ if(rtw_chk_start_clnt_join(padapter, &ch, &bw, &offset) == _FAIL) { ++ report_join_res(padapter, (-4)); ++ return H2C_SUCCESS; ++ } ++#endif ++ ++ //disable dynamic functions, such as high power, DIG ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under linking, need to write the BB registers ++ //initialgain = 0x1E; ++ //rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); ++ join_type = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ set_channel_bwmode(padapter, ch, offset, bw); ++ ++ //cancel link timer ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ start_clnt_join(padapter); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct disconnect_parm *param = (struct disconnect_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ u8 val8; ++ ++ if (is_client_associated_to_ap(padapter)) ++ { ++ issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms/100, 100); ++ } ++ ++ //set_opmode_cmd(padapter, infra_client_with_mlme); ++ ++ //pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); ++ ++ //restore to initial setting. ++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //Stop BCN ++ val8 = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); ++ } ++ ++ ++ //set MSR to no link state -> infra. mode ++ Set_MSR(padapter, _HW_STATE_STATION_); ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ dc_set_channel_bwmode_disconnect(padapter); ++#else ++#ifdef CONFIG_CONCURRENT_MODE ++ if((check_buddy_fwstate(padapter, _FW_LINKED)) != _TRUE) ++ { ++#endif //CONFIG_CONCURRENT_MODE ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++#ifdef CONFIG_CONCURRENT_MODE ++ } ++#endif //CONFIG_CONCURRENT_MODE ++#endif //CONFIG_DUALMAC_CONCURRENT ++ ++ flush_all_cam_entry(padapter); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ rtw_free_uc_swdec_pending_queue(padapter); ++ ++ return H2C_SUCCESS; ++} ++ ++int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, ++ u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num) ++{ ++ int i, j; ++ int scan_ch_num = 0; ++ int set_idx; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ /* clear out first */ ++ _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel)*out_num); ++ ++ /* acquire channels from in */ ++ j = 0; ++ for (i=0;ichannel_set, in[i].hw_value)) >=0 ++ ) ++ { ++ _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); ++ ++ if(pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE) ++ out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; ++ ++ j++; ++ } ++ if(j>=out_num) ++ break; ++ } ++ ++ /* if out is empty, use channel_set as default */ ++ if(j == 0) { ++ for (i=0;imax_chan_nums;i++) { ++ out[i].hw_value = pmlmeext->channel_set[i].ChannelNum; ++ ++ if(pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE) ++ out[i].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; ++ ++ j++; ++ } ++ } ++ ++ if (padapter->setband == GHZ_24) { // 2.4G ++ for (i=0; i < j ; i++) { ++ if (out[i].hw_value > 35) ++ _rtw_memset(&out[i], 0 , sizeof(struct rtw_ieee80211_channel)); ++ else ++ scan_ch_num++; ++ } ++ j = scan_ch_num; ++ } else if (padapter->setband == GHZ_50) { // 5G ++ for (i=0; i < j ; i++) { ++ if (out[i].hw_value > 35) { ++ _rtw_memcpy(&out[scan_ch_num++], &out[i], sizeof(struct rtw_ieee80211_channel)); ++ } ++ } ++ j = scan_ch_num; ++ } else ++ {} ++ ++ return j; ++} ++ ++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; ++ u8 bdelayscan = _FALSE; ++ u8 val8; ++ u32 initialgain; ++ u32 i; ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_DISABLE) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ //for first time sitesurvey_cmd ++ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); ++#endif //CONFIG_CONCURRENT_MODE ++ ++ pmlmeext->sitesurvey_res.state = SCAN_START; ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ ++ for(i=0;issid[i].SsidLength) { ++ _rtw_memcpy(pmlmeext->sitesurvey_res.ssid[i].Ssid, pparm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); ++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= pparm->ssid[i].SsidLength; ++ } else { ++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= 0; ++ } ++ } ++ ++ pmlmeext->sitesurvey_res.ch_num = rtw_scan_ch_decision(padapter ++ , pmlmeext->sitesurvey_res.ch, RTW_CHANNEL_SCAN_AMOUNT ++ , pparm->ch, pparm->ch_num ++ ); ++ ++ pmlmeext->sitesurvey_res.scan_mode = pparm->scan_mode; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ bdelayscan = dc_handle_site_survey(padapter); ++#endif ++ ++ //issue null data if associating to the AP ++ if (is_client_associated_to_ap(padapter) == _TRUE) ++ { ++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL; ++ ++ /* switch to correct channel of current network before issue keep-alive frames */ ++ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ } ++ ++ issue_nulldata(padapter, NULL, 1, 3, 500); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE) ++ { ++ DBG_871X("adapter is scanning(buddy_adapter is linked), issue nulldata(pwrbit=1)\n"); ++ ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); ++ } ++#endif ++ bdelayscan = _TRUE; ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ else if(is_client_associated_to_ap(padapter->pbuddy_adapter) == _TRUE) ++ { ++ #ifdef CONFIG_TDLS ++ if(padapter->pbuddy_adapter->wdinfo.wfd_tdls_enable == 1) ++ { ++ issue_tunneled_probe_req(padapter->pbuddy_adapter); ++ } ++ #endif //CONFIG_TDLS ++ ++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL; ++ ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); ++ ++ bdelayscan = _TRUE; ++ } ++#endif ++ if(bdelayscan) ++ { ++ //delay 50ms to protect nulldata(1). ++ set_survey_timer(pmlmeext, 50); ++ return H2C_SUCCESS; ++ } ++ } ++ ++ if ((pmlmeext->sitesurvey_res.state == SCAN_START) || (pmlmeext->sitesurvey_res.state == SCAN_TXNULL)) ++ { ++#ifdef CONFIG_FIND_BEST_CHANNEL ++#if 0 ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ pmlmeext->channel_set[i].rx_count = 0; ++ } ++#endif ++#endif /* CONFIG_FIND_BEST_CHANNEL */ ++ ++ //disable dynamic functions, such as high power, DIG ++ Save_DM_Func_Flag(padapter); ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under scaning, need to write the BB registers ++#ifdef CONFIG_P2P ++#ifdef CONFIG_IOCTL_CFG80211 ++ if((wdev_to_priv(padapter->rtw_wdev))->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ initialgain = 0x30; ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ if ( !rtw_p2p_chk_state( pwdinfo, P2P_STATE_NONE ) ) ++ initialgain = 0x28; ++ else ++#endif //CONFIG_P2P ++ initialgain = 0x1e; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ //set MSR to no link state ++ Set_MSR(padapter, _HW_STATE_NOLINK_); ++ ++ val8 = 1; //under site survey ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ pmlmeext->sitesurvey_res.state = SCAN_PROCESS; ++ } ++ ++ site_survey(padapter); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct setauth_parm *pparm = (struct setauth_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (pparm->mode < 4) ++ { ++ pmlmeinfo->auth_algo = pparm->mode; ++ } ++ ++ return H2C_SUCCESS; ++} ++ ++u8 setkey_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ unsigned short ctrl; ++ struct setkey_parm *pparm = (struct setkey_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ //main tx key for wep. ++ if(pparm->set_tx) ++ pmlmeinfo->key_index = pparm->keyid; ++ ++ //write cam ++ ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; ++ ++ DBG_871X_LEVEL(_drv_always_, "set group key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) " ++ "keyid:%d\n", pparm->algorithm, pparm->keyid); ++ write_cam(padapter, pparm->keyid, ctrl, null_sta, pparm->key); ++ ++ //allow multicast packets to driver ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_ON_RCR_AM, null_addr); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ u16 ctrl=0; ++ u8 cam_id;//cam_entry ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++#endif //CONFIG_TDLS ++ ++ //cam_entry: ++ //0~3 for default key ++ ++ //for concurrent mode (ap+sta): ++ //default key is disable, using sw encrypt/decrypt ++ //cam_entry = 4 //for sta mode (macid=0) ++ //cam_entry(macid+3) = 5 ~ N//for ap mode (aid=1~N, macid=2 ~N) ++ ++ //for concurrent mode (sta+sta): ++ //default key is disable, using sw encrypt/decrypt ++ //cam_entry = 4 //mapping to macid=0 ++ //cam_entry = 5 //mapping to macid=2 ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++ ++ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); ++ ++ if(psta && psta->mac_id==2) ++ { ++ cam_id = 5; ++ } ++ else ++ { ++ cam_id = 4; ++ } ++/* ++ if(padapter->iface_type > PRIMARY_IFACE) ++ { ++ cam_id = 5; ++ } ++ else ++ { ++ cam_id = 4; ++ } ++*/ ++ } ++#else ++ cam_id = 4; ++#endif ++ ++ DBG_871X_LEVEL(_drv_always_, "set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) camid:%d\n", ++ pparm->algorithm, cam_id); ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(pparm->algorithm == _NO_PRIVACY_) // clear cam entry ++ { ++ clear_cam_entry(padapter, pparm->id); ++ return H2C_SUCCESS_RSP; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, pparm->addr); ++ if(psta) ++ { ++ ctrl = (BIT(15) | ((pparm->algorithm) << 2)); ++ ++ DBG_871X("r871x_set_stakey_hdl(): enc_algorithm=%d\n", pparm->algorithm); ++ ++ if((psta->mac_id<1) || (psta->mac_id>(NUM_STA-4))) ++ { ++ DBG_871X("r871x_set_stakey_hdl():set_stakey failed, mac_id(aid)=%d\n", psta->mac_id); ++ return H2C_REJECTED; ++ } ++ ++ cam_id = (psta->mac_id + 3);//0~3 for default key, cmd_id=macid + 3, macid=aid+1; ++ ++ DBG_871X("Write CAM, mac_addr=%x:%x:%x:%x:%x:%x, cam_entry=%d\n", pparm->addr[0], ++ pparm->addr[1], pparm->addr[2], pparm->addr[3], pparm->addr[4], ++ pparm->addr[5], cam_id); ++ ++ write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); ++ ++ return H2C_SUCCESS_RSP; ++ ++ } ++ else ++ { ++ DBG_871X("r871x_set_stakey_hdl(): sta has been free\n"); ++ return H2C_REJECTED; ++ } ++ ++ } ++ ++ //below for sta mode ++ ++ if(pparm->algorithm == _NO_PRIVACY_) // clear cam entry ++ { ++ clear_cam_entry(padapter, pparm->id); ++ return H2C_SUCCESS; ++ } ++ ++ ctrl = BIT(15) | ((pparm->algorithm) << 2); ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->clear_cam!=0){ ++ clear_cam_entry(padapter, ptdlsinfo->clear_cam); ++ ptdlsinfo->clear_cam=0; ++ ++ return H2C_SUCCESS; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, pparm->addr);//Get TDLS Peer STA ++ if( psta->tdls_sta_state&TDLS_LINKED_STATE ){ ++ write_cam(padapter, psta->mac_id, ctrl, pparm->addr, pparm->key); ++ } ++ else ++#endif //CONFIG_TDLS ++ write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); ++ ++ pmlmeinfo->enc_algo = pparm->algorithm; ++ ++ return H2C_SUCCESS; ++} ++ ++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); ++ ++ if(!psta) ++ return H2C_SUCCESS; ++ ++#ifdef CONFIG_80211N_HT ++ if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || ++ ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pmlmeinfo->ADDBA_retry_count = 0; ++ //pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); ++ //psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); ++ issue_action_BA(padapter, pparm->addr, RTW_WLAN_ACTION_ADDBA_REQ, (u16)pparm->tid); ++ //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); ++ _set_timer(&psta->addba_retry_timer, ADDBA_TO); ++ } ++#ifdef CONFIG_TDLS ++ else if((psta->tdls_sta_state & TDLS_LINKED_STATE)&& ++ (psta->htpriv.ht_option==_TRUE) && ++ (psta->htpriv.ampdu_enable==_TRUE) ) ++ { ++ issue_action_BA(padapter, pparm->addr, RTW_WLAN_ACTION_ADDBA_REQ, (u16)pparm->tid); ++ //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); ++ _set_timer(&psta->addba_retry_timer, ADDBA_TO); ++ } ++#endif //CONFIG ++ else ++ { ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); ++ } ++#endif //CONFIG_80211N_HT ++ return H2C_SUCCESS; ++} ++ ++u8 set_tx_beacon_cmd(_adapter* padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct Tx_Beacon_param *ptxBeacon_parm; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 res = _SUCCESS; ++ int len_diff = 0; ++ ++_func_enter_; ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ res= _FAIL; ++ goto exit; ++ } ++ ++ if ((ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); ++ ++ len_diff = update_hidden_ssid( ++ ptxBeacon_parm->network.IEs+_BEACON_IE_OFFSET_ ++ , ptxBeacon_parm->network.IELength-_BEACON_IE_OFFSET_ ++ , pmlmeinfo->hidden_ssid_mode ++ ); ++ ptxBeacon_parm->network.IELength += len_diff; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++ ++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ u8 evt_code, evt_seq; ++ u16 evt_sz; ++ uint *peventbuf; ++ void (*event_callback)(_adapter *dev, u8 *pbuf); ++ struct evt_priv *pevt_priv = &(padapter->evtpriv); ++ ++ peventbuf = (uint*)pbuf; ++ evt_sz = (u16)(*peventbuf&0xffff); ++ evt_seq = (u8)((*peventbuf>>24)&0x7f); ++ evt_code = (u8)((*peventbuf>>16)&0xff); ++ ++ ++ #ifdef CHECK_EVENT_SEQ ++ // checking event sequence... ++ if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f) ) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f))); ++ ++ pevt_priv->event_seq = (evt_seq+1)&0x7f; ++ ++ goto _abort_event_; ++ } ++ #endif ++ ++ // checking if event code is valid ++ if (evt_code >= MAX_C2HEVT) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent Code(%d) mismatch!\n", evt_code)); ++ goto _abort_event_; ++ } ++ ++ // checking if event size match the event parm size ++ if ((wlanevents[evt_code].parmsize != 0) && ++ (wlanevents[evt_code].parmsize != evt_sz)) ++ { ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n", ++ evt_code, wlanevents[evt_code].parmsize, evt_sz)); ++ goto _abort_event_; ++ ++ } ++ ++ ATOMIC_INC(&pevt_priv->event_seq); ++ ++ peventbuf += 2; ++ ++ if(peventbuf) ++ { ++ event_callback = wlanevents[evt_code].event_callback; ++ event_callback(padapter, (u8*)peventbuf); ++ ++ pevt_priv->evt_done_cnt++; ++ } ++ ++ ++_abort_event_: ++ ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ return H2C_SUCCESS; ++} ++ ++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ if(send_beacon(padapter)==_FAIL) ++ { ++ DBG_871X("issue_beacon, fail!\n"); ++ return H2C_PARAMETERS_ERROR; ++ } ++#ifdef CONFIG_AP_MODE ++ else //tx bc/mc frames after update TIM ++ { ++ _irqL irqL; ++ struct sta_info *psta_bmc; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //for BC/MC Frames ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(!psta_bmc) ++ return H2C_SUCCESS; ++ ++ if((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len>0)) ++ { ++#ifndef CONFIG_PCI_HCI ++ rtw_msleep_os(10);// 10ms, ATIM(HIQ) Windows ++#endif ++ //_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta_bmc->sleepq_len--; ++ if(psta_bmc->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ pxmitframe->attrib.triggered=1; ++ ++ pxmitframe->attrib.qsel = 0x11;//HIQ ++ ++#if 0 ++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++#endif ++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ //pstapriv->tim_bitmap &= ~BIT(0); ++ ++ } ++ ++ //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++//#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ rtw_chk_hi_queue_cmd(padapter); ++#endif ++ ++ } ++ ++ } ++#endif ++ ++ return H2C_SUCCESS; ++ ++} ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++void dc_SelectChannel(_adapter *padapter, unsigned char channel) ++{ ++ PADAPTER ptarget_adapter; ++ ++ if( (padapter->pbuddy_adapter != NULL) && ++ (padapter->DualMacConcurrent == _TRUE) && ++ (padapter->adapter_type == SECONDARY_ADAPTER)) ++ { ++ // only mac0 could control BB&RF ++ ptarget_adapter = padapter->pbuddy_adapter; ++ } ++ else ++ { ++ ptarget_adapter = padapter; ++ } ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setch_mutex), NULL); ++ ++ rtw_hal_set_chan(ptarget_adapter, channel); ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setch_mutex), NULL); ++} ++ ++void dc_SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset) ++{ ++ PADAPTER ptarget_adapter; ++ ++ if( (padapter->pbuddy_adapter != NULL) && ++ (padapter->DualMacConcurrent == _TRUE) && ++ (padapter->adapter_type == SECONDARY_ADAPTER)) ++ { ++ // only mac0 could control BB&RF ++ ptarget_adapter = padapter->pbuddy_adapter; ++ } ++ else ++ { ++ ptarget_adapter = padapter; ++ } ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setbw_mutex), NULL); ++ ++ rtw_hal_set_bwmode(ptarget_adapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset); ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(ptarget_adapter)->setbw_mutex), NULL); ++} ++ ++static void dc_change_band(_adapter *padapter, WLAN_BSSID_EX *pnetwork) ++{ ++ u8 network_type,rate_len, total_rate_len,remainder_rate_len; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 erpinfo=0x4; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if(pmlmeext->cur_channel >= 36) ++ { ++ network_type = WIRELESS_11A; ++ total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; ++ DBG_871X("%s(): change to 5G Band\n",__FUNCTION__); ++ rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); ++ } ++ else ++ { ++ network_type = WIRELESS_11BG; ++ total_rate_len = IEEE80211_CCK_RATE_LEN+IEEE80211_NUM_OFDM_RATESLEN; ++ DBG_871X("%s(): change to 2.4G Band\n",__FUNCTION__); ++ rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); ++ } ++ ++ rtw_set_supported_rate(pnetwork->SupportedRates, network_type); ++ ++ UpdateBrateTbl(padapter, pnetwork->SupportedRates); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); ++ ++ if(total_rate_len > 8) ++ { ++ rate_len = 8; ++ remainder_rate_len = total_rate_len - 8; ++ } ++ else ++ { ++ rate_len = total_rate_len; ++ remainder_rate_len = 0; ++ } ++ ++ rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len); ++ ++ if(remainder_rate_len) ++ { ++ rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates+8), remainder_rate_len); ++ } ++ else ++ { ++ rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_); ++ } ++} ++ ++void dc_set_channel_bwmode_disconnect(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ if((check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) != _TRUE) ++ { ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ } ++ else ++ { ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++} ++ ++u8 dc_handle_join_request(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = NULL; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ u8 ret = _SUCCESS; ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ ++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel || ++ pmlmeext->cur_bwmode != pbuddy_mlmeext->cur_bwmode || ++ pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset) ++ { ++ if((check_fwstate(pbuddy_mlmepriv, WIFI_AP_STATE)) == _TRUE) ++ { ++ //issue deauth to all stas if if2 is at ap mode ++ rtw_sta_flush(pbuddy_adapter); ++ ++ //rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); ++ rtw_hal_set_hwreg(pbuddy_adapter, HW_VAR_CHECK_TXBUF, 0); ++ } ++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE) ++ { ++ if(pmlmeext->cur_channel == pbuddy_mlmeext->cur_channel) ++ { ++ // HT_CHANNEL_WIDTH_40 or HT_CHANNEL_WIDTH_20 but channel offset is different ++ if((pmlmeext->cur_bwmode == pbuddy_mlmeext->cur_bwmode) && ++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset) ) ++ { ++ report_join_res(padapter, -4); ++ ret = _FAIL; ++ } ++ } ++ else ++ { ++ report_join_res(padapter, -4); ++ ret = _FAIL; ++ } ++ } ++ } ++ else if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE) ++ { ++ issue_nulldata(pbuddy_adapter, NULL, 1, 0, 0); ++ } ++ } ++ ++ if (!ch || !bw || !offset) { ++ rtw_warn_on(1); ++ ret = _FAIL; ++ } ++ ++ if (ret == _SUCCESS) { ++ *ch = pmlmeext->cur_channel; ++ *bw = pmlmeext->cur_bwmode; ++ *offset = pmlmeext->cur_ch_offset; ++ } ++ ++exit: ++ return ret; ++} ++ ++void dc_handle_join_done(_adapter *padapter, u8 join_res) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ struct mlme_ext_priv *pbuddy_mlmeext = NULL; ++ struct mlme_ext_info *pbuddy_mlmeinfo = NULL; ++ WLAN_BSSID_EX *pbuddy_network_mlmeext = NULL; ++ u8 change_band = _FALSE; ++ ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info); ++ pbuddy_network_mlmeext = &(pbuddy_mlmeinfo->network); ++ ++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) ++ { ++ //restart and update beacon ++ DBG_871X("after join, current adapter, CH=%d, BW=%d, offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ ++ if(join_res >= 0) ++ { ++ u8 *p; ++ int ie_len; ++ struct HT_info_element *pht_info=NULL; ++ ++ if((pbuddy_mlmeext->cur_channel <= 14 && pmlmeext->cur_channel >= 36) || ++ (pbuddy_mlmeext->cur_channel >= 36 && pmlmeext->cur_channel <= 14)) ++ { ++ change_band = _TRUE; ++ } ++ ++ //sync channel/bwmode/ch_offset with another adapter ++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel; ++ ++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); //no secondary channel is present ++ } ++ ++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ pbuddy_mlmeext->cur_ch_offset = pmlmeext->cur_ch_offset; ++ ++ //to update cur_ch_offset value in beacon ++ if( pht_info ) ++ { ++ switch(pmlmeext->cur_ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ pht_info->infos[0] |= 0x1; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ pht_info->infos[0] |= 0x3; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ default: ++ break; ++ } ++ } ++ } ++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) ++ { ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ if(pmlmeext->cur_channel>0 && pmlmeext->cur_channel<5) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x1; ++ ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ } ++ ++ if(pmlmeext->cur_channel>7 && pmlmeext->cur_channel<(14+1)) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x3; ++ ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ } ++ ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ } ++ } ++ ++ // to update channel value in beacon ++ pbuddy_network_mlmeext->Configuration.DSConfig = pmlmeext->cur_channel; ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if(p && ie_len>0) ++ *(p + 2) = pmlmeext->cur_channel; ++ ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ pht_info->primary_channel = pmlmeext->cur_channel; ++ } ++ ++ // update mlmepriv's cur_network ++ _rtw_memcpy(&pbuddy_mlmepriv->cur_network.network, pbuddy_network_mlmeext, pbuddy_network_mlmeext->Length); ++ } ++ else ++ { ++ // switch back to original channel/bwmode/ch_offset; ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ } ++ ++ DBG_871X("after join, another adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ ++ if(change_band == _TRUE) ++ dc_change_band(pbuddy_adapter, pbuddy_network_mlmeext); ++ ++ DBG_871X("update pbuddy_adapter's beacon\n"); ++ ++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE); ++ } ++ else if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE) ++ { ++ if((pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) && ++ (pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20)) ++ { ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ } ++ ++ issue_nulldata(pbuddy_adapter, NULL, 0, 0, 0); ++ } ++ } ++} ++ ++sint dc_check_fwstate(_adapter *padapter, sint fw_state) ++{ ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ ++ if(padapter->pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ ++ return check_fwstate(pbuddy_mlmepriv, fw_state); ++ } ++ ++ return _FALSE; ++} ++ ++u8 dc_handle_site_survey(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ ++ // only mac0 can do scan request, help issue nulldata(1) for mac1 ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE) ++ { ++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL; ++ ++ issue_nulldata(pbuddy_adapter, NULL, 1, 2, 0); ++ ++ return _TRUE; ++ } ++ } ++ ++ return _FALSE; ++} ++ ++void dc_report_survey_event(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ if(padapter->pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ report_survey_event(padapter->pbuddy_adapter, precv_frame); ++ } ++} ++ ++void dc_set_channel_bwmode_survey_done(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ struct mlme_ext_priv *pbuddy_mlmeext = NULL; ++ struct mlme_ext_info *pbuddy_mlmeinfo = NULL; ++ u8 cur_channel; ++ u8 cur_bwmode; ++ u8 cur_ch_offset; ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info); ++ ++ if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED) && ++ (pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)) ++ { ++ cur_channel = pmlmeext->cur_channel; ++ cur_bwmode = pmlmeext->cur_bwmode; ++ cur_ch_offset = pmlmeext->cur_ch_offset; ++ } ++ else ++ { ++ cur_channel = pbuddy_mlmeext->cur_channel; ++ cur_bwmode = pbuddy_mlmeext->cur_bwmode; ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ } ++ } ++ else ++ { ++ cur_channel = pmlmeext->cur_channel; ++ cur_bwmode = pmlmeext->cur_bwmode; ++ cur_ch_offset = pmlmeext->cur_ch_offset; ++ } ++ ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ ++ if (is_client_associated_to_ap(pbuddy_adapter) == _TRUE) ++ { ++ //issue null data ++ issue_nulldata(pbuddy_adapter, NULL, 0, 0, 0); ++ } ++ ++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) ++ { ++ ++ DBG_871X("survey done, current CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ DBG_871X("restart pbuddy_adapter's beacon\n"); ++ ++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE); ++ } ++ } ++ else ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++} ++ ++void dc_set_ap_channel_bandwidth(_adapter *padapter, u8 channel, u8 channel_offset, u8 bwmode) ++{ ++ u8 *p; ++ u8 val8, cur_channel, cur_bwmode, cur_ch_offset, change_band; ++ int ie_len; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct HT_info_element *pht_info=NULL; ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ struct mlme_ext_priv *pbuddy_mlmeext = NULL; ++ ++ DBG_871X("dualmac_concurrent_ap_set_channel_bwmode ==>\n"); ++ ++ cur_channel = channel; ++ cur_bwmode = bwmode; ++ cur_ch_offset = channel_offset; ++ change_band = _FALSE; ++ ++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ } ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ if(!check_fwstate(pbuddy_mlmepriv, _FW_LINKED|_FW_UNDER_LINKING|_FW_UNDER_SURVEY)) ++ { ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ } ++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED)==_TRUE) ++ { ++ //To sync cur_channel/cur_bwmode/cur_ch_offset with another adapter ++ DBG_871X("Another iface is at linked state, sync cur_channel/cur_bwmode/cur_ch_offset\n"); ++ DBG_871X("Another adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ DBG_871X("Current adapter, CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ cur_channel = pbuddy_mlmeext->cur_channel; ++ if(cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ if(pht_info) ++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); ++ ++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ ++ //to update cur_ch_offset value in beacon ++ if(pht_info) ++ { ++ switch(cur_ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ pht_info->infos[0] |= 0x1; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ pht_info->infos[0] |= 0x3; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ default: ++ break; ++ } ++ } ++ } ++ else if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) ++ { ++ cur_bwmode = HT_CHANNEL_WIDTH_20; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ if(cur_channel>0 && cur_channel<5) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x1; ++ ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ } ++ ++ if(cur_channel>7 && cur_channel<(14+1)) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= 0x3; ++ ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ } ++ ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ } ++ } ++ ++ // to update channel value in beacon ++ pnetwork->Configuration.DSConfig = cur_channel; ++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if(p && ie_len>0) ++ *(p + 2) = cur_channel; ++ ++ if(pht_info) ++ pht_info->primary_channel = cur_channel; ++ } ++ } ++ else ++ { ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ } ++ ++ DBG_871X("CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ if((channel <= 14 && cur_channel >= 36) || ++ (channel >= 36 && cur_channel <= 14)) ++ { ++ change_band = _TRUE; ++ } ++ ++ pmlmeext->cur_channel = cur_channel; ++ pmlmeext->cur_bwmode = cur_bwmode; ++ pmlmeext->cur_ch_offset = cur_ch_offset; ++ ++ if(change_band == _TRUE) ++ dc_change_band(padapter, pnetwork); ++ ++ DBG_871X("dualmac_concurrent_ap_set_channel_bwmode <==\n"); ++} ++ ++void dc_resume_xmit(_adapter *padapter) ++{ ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ DBG_871X("dc_resume_xmit, resume pbuddy_adapter Tx\n"); ++ rtw_os_xmit_schedule(pbuddy_adapter); ++ } ++} ++ ++u8 dc_check_xmit(_adapter *padapter) ++{ ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++ ++ if(pbuddy_adapter != NULL && ++ padapter->DualMacConcurrent == _TRUE) ++ { ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ if (check_fwstate(pbuddy_mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_871X("dc_check_xmit pbuddy_adapter is under survey or under linking\n"); ++ return _FALSE; ++ } ++ } ++ ++ return _TRUE; ++} ++#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state) ++{ ++ PADAPTER pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext; ++ struct mlme_ext_info *pbuddy_mlmeinfo; ++ ++ if(padapter == NULL) ++ return _FALSE; ++ ++ pbuddy_adapter = padapter->pbuddy_adapter; ++ ++ if(pbuddy_adapter == NULL) ++ return _FALSE; ++ ++ ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info); ++ ++ if((pbuddy_mlmeinfo->state&0x03) == state) ++ return _TRUE; ++ ++ return _FALSE; ++ ++} ++ ++void concurrent_chk_joinbss_done(_adapter *padapter, int join_res) ++{ ++ struct mlme_ext_priv *pmlmeext; ++ struct mlme_ext_info *pmlmeinfo; ++ PADAPTER pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext; ++ struct mlme_ext_info *pbuddy_mlmeinfo; ++ WLAN_BSSID_EX *pbuddy_network_mlmeext; ++ ++ pmlmeext = &padapter->mlmeextpriv; ++ pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(!rtw_buddy_adapter_up(padapter)) ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ return; ++ } ++ ++ pbuddy_adapter = padapter->pbuddy_adapter; ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info); ++ pbuddy_network_mlmeext = &(pbuddy_mlmeinfo->network); ++ ++ if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && ++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) ++ { ++ //restart and update beacon ++ ++ DBG_871X("after join,primary adapter, CH=%d, BW=%d, offset=%d\n" ++ , pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ ++ ++ if(join_res >= 0) ++ { ++ u8 *p; ++ int ie_len; ++ struct HT_info_element *pht_info=NULL; ++ ++ //sync channel/bwmode/ch_offset with primary adapter ++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel; ++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ pht_info->infos[0] &= ~(BIT(0)|BIT(1)); //no secondary channel is present ++ } ++ ++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ { ++ pbuddy_mlmeext->cur_ch_offset = pmlmeext->cur_ch_offset; ++ ++ //to update cur_ch_offset value in beacon ++ if( pht_info ) ++ { ++ switch(pmlmeext->cur_ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ pht_info->infos[0] |= 0x1; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ pht_info->infos[0] |= 0x3; ++ break; ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ default: ++ break; ++ } ++ ++ } ++ ++ } ++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) ++ { ++ if(pmlmeext->cur_channel>=1 && pmlmeext->cur_channel<=4) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE; ++ ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ } ++ else if(pmlmeext->cur_channel>=5 && pmlmeext->cur_channel<=14) ++ { ++ if(pht_info) ++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW; ++ ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ } ++ else ++ { ++ switch(pmlmeext->cur_channel) ++ { ++ case 36: ++ case 44: ++ case 52: ++ case 60: ++ case 100: ++ case 108: ++ case 116: ++ case 124: ++ case 132: ++ case 149: ++ case 157: ++ { ++ if(pht_info) ++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE; ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ } ++ case 40: ++ case 48: ++ case 56: ++ case 64: ++ case 104: ++ case 112: ++ case 120: ++ case 128: ++ case 136: ++ case 153: ++ case 161: ++ { ++ if(pht_info) ++ pht_info->infos[0] |= HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW; ++ ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ } ++ default: ++ if(pht_info) ++ pht_info->infos[0] &= ~HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW; ++ pbuddy_mlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pbuddy_mlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ ++ } ++ ++ } ++ ++ } ++ ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ } ++ else ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ ++ ++ // to update channel value in beacon ++ pbuddy_network_mlmeext->Configuration.DSConfig = pmlmeext->cur_channel; ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if(p && ie_len>0) ++ *(p + 2) = pmlmeext->cur_channel; ++ ++ p = rtw_get_ie((pbuddy_network_mlmeext->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pbuddy_network_mlmeext->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ pht_info = (struct HT_info_element *)(p+2); ++ pht_info->primary_channel = pmlmeext->cur_channel; ++ } ++ ++ } ++ else ++ { ++ // switch back to original channel/bwmode/ch_offset; ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ } ++ ++ DBG_871X("after join, second adapter, CH=%d, BW=%d, offset=%d\n", pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ ++ DBG_871X("update pbuddy_adapter's beacon\n"); ++ ++ update_beacon(pbuddy_adapter, 0, NULL, _TRUE); ++ ++ } ++ else if(((pbuddy_mlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) && ++ check_fwstate(pbuddy_mlmepriv, _FW_LINKED)) ++ { ++ if(join_res >= 0) ++ { ++ pbuddy_mlmeext->cur_channel = pmlmeext->cur_channel; ++ if(pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ else if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ else ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ { ++ // switch back to original channel/bwmode/ch_offset; ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ } ++ } ++ else ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ ++} ++#endif //CONFIG_CONCURRENT_MODE ++ ++int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ unsigned char cur_ch = pmlmeext->cur_channel; ++ unsigned char cur_bw = pmlmeext->cur_bwmode; ++ unsigned char cur_ch_offset = pmlmeext->cur_ch_offset; ++ bool chbw_allow = _TRUE; ++ bool connect_allow = _TRUE; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext; ++ struct mlme_ext_info *pbuddy_pmlmeinfo; ++ struct mlme_priv *pbuddy_mlmepriv; ++ ++ if (!rtw_buddy_adapter_up(padapter)) { ++ goto exit; ++ } ++ ++ pbuddy_adapter = padapter->pbuddy_adapter; ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ pbuddy_pmlmeinfo = &(pbuddy_mlmeext->mlmext_info); ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ ++ if((pbuddy_pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)//for AP MODE ++ { ++ DBG_871X("start_clnt_join: "ADPT_FMT"(ch=%d, bw=%d, ch_offset=%d)" ++ ", "ADPT_FMT" AP mode(ch=%d, bw=%d, ch_offset=%d)\n", ++ ADPT_ARG(padapter), pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset, ++ ADPT_ARG(pbuddy_adapter), pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ ++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel) ++ { ++ chbw_allow = _FALSE; ++ } ++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) && ++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) && ++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset)) ++ { ++ chbw_allow = _FALSE; ++ } ++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) && ++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)) ++ { ++ cur_ch = pmlmeext->cur_channel; ++ cur_bw = pbuddy_mlmeext->cur_bwmode; ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ } ++ ++ DBG_871X("start_clnt_join: connect_allow:%d, chbw_allow:%d\n", connect_allow, chbw_allow); ++ if (chbw_allow == _FALSE) { ++ #ifdef CONFIG_SPCT_CH_SWITCH ++ if (1) { ++ rtw_ap_inform_ch_switch(pbuddy_adapter, pmlmeext->cur_channel , pmlmeext->cur_ch_offset); ++ } else ++ #endif ++ { ++ //issue deauth to all stas if if2 is at ap mode ++ rtw_sta_flush(pbuddy_adapter); ++ } ++ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); ++ } ++ } ++ else if(check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE && ++ check_fwstate(pbuddy_mlmepriv, WIFI_STATION_STATE) == _TRUE) //for Client Mode/p2p client ++ { ++ DBG_871X("start_clnt_join: "ADPT_FMT"(ch=%d, bw=%d, ch_offset=%d)" ++ ", "ADPT_FMT" STA mode(ch=%d, bw=%d, ch_offset=%d)\n", ++ ADPT_ARG(padapter), pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset, ++ ADPT_ARG(pbuddy_adapter), pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_bwmode, pbuddy_mlmeext->cur_ch_offset); ++ ++ if(pmlmeext->cur_channel != pbuddy_mlmeext->cur_channel) ++ { ++ chbw_allow = _FALSE; ++ } ++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_20) && ++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40)) ++ { ++ cur_bw = HT_CHANNEL_WIDTH_40; ++ cur_ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ } ++ else if((pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) && ++ (pbuddy_mlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40) && ++ (pmlmeext->cur_ch_offset != pbuddy_mlmeext->cur_ch_offset)) ++ { ++ chbw_allow = _FALSE; ++ } ++ ++ connect_allow = chbw_allow; ++ ++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) ++ /* wlan0-sta mode has higher priority than p2p0-p2p client */ ++ if (!rtw_p2p_chk_state(&(pbuddy_adapter->wdinfo), P2P_STATE_NONE) ++ && pbuddy_adapter->wdinfo.driver_interface == DRIVER_CFG80211) ++ { ++ connect_allow = _TRUE; ++ } ++ #endif /* CONFIG_P2P && CONFIG_IOCTL_CFG80211 */ ++ ++ DBG_871X("start_clnt_join: connect_allow:%d, chbw_allow:%d\n", connect_allow, chbw_allow); ++ if (connect_allow == _TRUE && chbw_allow == _FALSE) { ++ /* disconnect buddy's connection */ ++ rtw_disassoc_cmd(pbuddy_adapter, 500, _FALSE); ++ rtw_indicate_disconnect(pbuddy_adapter); ++ rtw_free_assoc_resources(pbuddy_adapter, 1); ++ } ++ } ++ ++exit: ++#endif /* CONFIG_CONCURRENT_MODE */ ++ ++ if (!ch || !bw || !offset) { ++ rtw_warn_on(1); ++ connect_allow = _FALSE; ++ } ++ ++ if (connect_allow == _TRUE) { ++ DBG_871X("start_join_set_ch_bw: ch=%d, bwmode=%d, ch_offset=%d\n", cur_ch, cur_bw, cur_ch_offset); ++ *ch = cur_ch; ++ *bw = cur_bw; ++ *offset = cur_ch_offset; ++ } ++ ++ return connect_allow == _TRUE ? _SUCCESS : _FAIL; ++} ++ ++/* Find union about ch, bw, ch_offset of all linked interfaces */ ++int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) ++{ ++ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); ++ _adapter *iface; ++ struct mlme_ext_priv *mlmeext; ++ int i; ++ u8 ch_ret = 0; ++ u8 bw_ret = HT_CHANNEL_WIDTH_20; ++ u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ int num = 0; ++ ++ if (ch) *ch = 0; ++ if (bw) *bw = HT_CHANNEL_WIDTH_20; ++ if (offset) *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ for (i = 0; iiface_nums; i++) { ++ iface = dvobj->padapters[i]; ++ mlmeext = &iface->mlmeextpriv; ++ ++ if (!check_fwstate(&iface->mlmepriv, _FW_LINKED)) ++ continue; ++ ++ if (num == 0) { ++ ch_ret = mlmeext->cur_channel; ++ bw_ret = mlmeext->cur_bwmode; ++ offset_ret = mlmeext->cur_ch_offset; ++ num++; ++ continue; ++ } ++ ++ if (ch_ret != mlmeext->cur_channel) { ++ num = 0; ++ break; ++ } ++ ++ if (bw_ret < mlmeext->cur_bwmode) { ++ bw_ret = mlmeext->cur_bwmode; ++ offset_ret = mlmeext->cur_ch_offset; ++ } else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) { ++ num = 0; ++ break; ++ } ++ ++ num++; ++ } ++ ++ if (num) { ++ if (ch) *ch = ch_ret; ++ if (bw) *bw = bw_ret; ++ if (offset) *offset = offset_ret; ++ } ++ ++ return num; ++} ++ ++u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ struct set_ch_parm *set_ch_parm; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ set_ch_parm = (struct set_ch_parm *)pbuf; ++ ++ DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", ++ FUNC_NDEV_ARG(padapter->pnetdev), ++ set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset); ++ ++ pmlmeext->cur_channel = set_ch_parm->ch; ++ pmlmeext->cur_ch_offset = set_ch_parm->ch_offset; ++ pmlmeext->cur_bwmode = set_ch_parm->bw; ++ ++ set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct SetChannelPlan_param *setChannelPlan_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ setChannelPlan_param = (struct SetChannelPlan_param *)pbuf; ++ ++ pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); ++ init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct LedBlink_param *ledBlink_param; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ ledBlink_param = (struct LedBlink_param *)pbuf; ++ ++ #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD ++ BlinkHandler(ledBlink_param->pLed); ++ #endif ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++#ifdef CONFIG_DFS ++ struct SetChannelSwitch_param *setChannelSwitch_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 new_ch_no; ++ u8 gval8 = 0x00, sval8 = 0xff; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ setChannelSwitch_param = (struct SetChannelSwitch_param *)pbuf; ++ new_ch_no = setChannelSwitch_param->new_ch_no; ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8); ++ ++ DBG_871X("DFS detected! Swiching channel to %d!\n", new_ch_no); ++ SelectChannel(padapter, new_ch_no); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); ++ ++ rtw_free_network_queue(padapter, _TRUE); ++ rtw_indicate_disconnect(padapter); ++ ++ if ( ((new_ch_no >= 52) && (new_ch_no <= 64)) ||((new_ch_no >= 100) && (new_ch_no <= 140)) ) { ++ DBG_871X("Switched to DFS band (ch %02x) again!!\n", new_ch_no); ++ } ++ ++ return H2C_SUCCESS; ++#else ++ return H2C_REJECTED; ++#endif //CONFIG_DFS ++ ++} ++ ++// TDLS_WRCR : write RCR DATA BIT ++// TDLS_SD_PTI : issue peer traffic indication ++// TDLS_CS_OFF : go back to the channel linked with AP, terminating channel switch procedure ++// TDLS_INIT_CH_SEN : init channel sensing, receive all data and mgnt frame ++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel ++// TDLS_OFF_CH : first time set channel to off channel ++// TDLS_BASE_CH : go back tp the channel linked with AP when set base channel as target channel ++// TDLS_P_OFF_CH : periodically go to off channel ++// TDLS_P_BASE_CH : periodically go back to base channel ++// TDLS_RS_RCR : restore RCR ++// TDLS_CKALV_PH1 : check alive timer phase1 ++// TDLS_CKALV_PH2 : check alive timer phase2 ++// TDLS_FREE_STA : free tdls sta ++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++#ifdef CONFIG_TDLS ++ _irqL irqL; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct TDLSoption_param *TDLSoption; ++ struct sta_info *ptdls_sta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 survey_channel, i, min, option; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ TDLSoption = (struct TDLSoption_param *)pbuf; ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), TDLSoption->addr ); ++ option = TDLSoption->option; ++ ++ if( ptdls_sta == NULL ) ++ { ++ if( option != TDLS_RS_RCR ) ++ return H2C_REJECTED; ++ } ++ ++ //_enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ DBG_871X("[%s] option:%d\n", __FUNCTION__, option); ++ ++ switch(option){ ++ case TDLS_WRCR: ++ //As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 ++ //such we can receive all kinds of data frames. ++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0); ++ DBG_871X("TDLS with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr)); ++ ++ pmlmeinfo->FW_sta_info[ptdls_sta->mac_id].psta = ptdls_sta; ++ //set TDLS sta rate. ++ set_sta_rate(padapter, ptdls_sta); ++ break; ++ case TDLS_SD_PTI: ++ issue_tdls_peer_traffic_indication(padapter, ptdls_sta); ++ break; ++ case TDLS_CS_OFF: ++ _cancel_timer_ex(&ptdls_sta->base_ch_timer); ++ _cancel_timer_ex(&ptdls_sta->off_ch_timer); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE | ++ TDLS_PEER_AT_OFF_STATE | ++ TDLS_AT_OFF_CH_STATE); ++ DBG_871X("go back to base channel\n "); ++ issue_nulldata(padapter, NULL, 0, 0, 0); ++ break; ++ case TDLS_INIT_CH_SEN: ++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_INIT_CH_SEN, 0); ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ ptdls_sta->option = TDLS_DONE_CH_SEN; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN); ++ break; ++ case TDLS_DONE_CH_SEN: ++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ if(survey_channel){ ++ SelectChannel(padapter, survey_channel); ++ ptdlsinfo->cur_channel = survey_channel; ++ pmlmeext->sitesurvey_res.channel_idx++; ++ _set_timer(&ptdls_sta->option_timer, SURVEY_TO); ++ }else{ ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_DONE_CH_SEN, 0); ++ ++ if(ptdlsinfo->ch_sensing==1){ ++ ptdlsinfo->ch_sensing=0; ++ ptdlsinfo->cur_channel=1; ++ min=ptdlsinfo->collect_pkt_num[0]; ++ for(i=1; i ptdlsinfo->collect_pkt_num[i]){ ++ ptdlsinfo->cur_channel=i+1; ++ min=ptdlsinfo->collect_pkt_num[i]; ++ } ++ ptdlsinfo->collect_pkt_num[i]=0; ++ } ++ ptdlsinfo->collect_pkt_num[0]=0; ++ ptdlsinfo->candidate_ch=ptdlsinfo->cur_channel; ++ DBG_871X("TDLS channel sensing done, candidate channel: %02x\n", ptdlsinfo->candidate_ch); ++ ptdlsinfo->cur_channel=0; ++ ++ } ++ ++ if(ptdls_sta->tdls_sta_state & TDLS_PEER_SLEEP_STATE){ ++ ptdls_sta->tdls_sta_state |= TDLS_APSD_CHSW_STATE; ++ }else{ ++ //send null data with pwrbit==1 before send ch_switching_req to peer STA. ++ issue_nulldata(padapter, NULL, 1, 0, 0); ++ ++ ptdls_sta->tdls_sta_state |= TDLS_CH_SW_INITIATOR_STATE; ++ ++ issue_tdls_ch_switch_req(padapter, ptdls_sta->hwaddr); ++ DBG_871X("issue tdls ch switch req\n"); ++ } ++ } ++ break; ++ case TDLS_OFF_CH: ++ issue_nulldata(padapter, NULL, 1, 0, 0); ++ SelectChannel(padapter, ptdls_sta->off_ch); ++ ++ DBG_871X("change channel to tar ch:%02x\n", ptdls_sta->off_ch); ++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE; ++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE); ++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); ++ break; ++ case TDLS_BASE_CH: ++ _cancel_timer_ex(&ptdls_sta->base_ch_timer); ++ _cancel_timer_ex(&ptdls_sta->off_ch_timer); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE | ++ TDLS_PEER_AT_OFF_STATE | ++ TDLS_AT_OFF_CH_STATE); ++ DBG_871X("go back to base channel\n "); ++ issue_nulldata(padapter, NULL, 0, 0, 0); ++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); ++ break; ++ case TDLS_P_OFF_CH: ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ issue_nulldata(padapter, NULL, 0, 0, 0); ++ DBG_871X("change channel to base ch:%02x\n", pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE| TDLS_AT_OFF_CH_STATE); ++ _set_timer(&ptdls_sta->off_ch_timer, TDLS_STAY_TIME); ++ break; ++ case TDLS_P_BASE_CH: ++ issue_nulldata(ptdls_sta->padapter, NULL, 1, 0, 0); ++ SelectChannel(padapter, ptdls_sta->off_ch); ++ DBG_871X("change channel to off ch:%02x\n", ptdls_sta->off_ch); ++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE; ++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE){ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0); ++ } ++ _set_timer(&ptdls_sta->base_ch_timer, TDLS_STAY_TIME); ++ break; ++ case TDLS_RS_RCR: ++ rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0); ++ DBG_871X("wirte REG_RCR, set bit6 on\n"); ++ break; ++ case TDLS_CKALV_PH1: ++ _set_timer(&ptdls_sta->alive_timer2, TDLS_ALIVE_TIMER_PH2); ++ break; ++ case TDLS_CKALV_PH2: ++ _set_timer(&ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++ break; ++ case TDLS_FREE_STA: ++ free_tdls_sta(padapter, ptdls_sta); ++ break; ++ ++ } ++ ++ //_exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ++ return H2C_SUCCESS; ++#else ++ return H2C_REJECTED; ++#endif //CONFIG_TDLS ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp.c +new file mode 100644 +index 00000000..75f0da1a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp.c +@@ -0,0 +1,1620 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MP_C_ ++ ++#include ++ ++#ifdef PLATFORM_FREEBSD ++#include /* for RFHIGHPID */ ++#endif ++ ++#ifdef CONFIG_RTL8712 ++#include ++#endif ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#include "rtw_bt_mp.h" ++#endif ++#ifdef CONFIG_RTL8188E ++#include "../hal/OUTSRC/odm_precomp.h" ++#include "rtl8188e_hal.h" ++#endif ++ ++ ++#ifdef CONFIG_MP_INCLUDED ++ ++u32 read_macreg(_adapter *padapter, u32 addr, u32 sz) ++{ ++ u32 val = 0; ++ ++ switch(sz) ++ { ++ case 1: ++ val = rtw_read8(padapter, addr); ++ break; ++ case 2: ++ val = rtw_read16(padapter, addr); ++ break; ++ case 4: ++ val = rtw_read32(padapter, addr); ++ break; ++ default: ++ val = 0xffffffff; ++ break; ++ } ++ ++ return val; ++ ++} ++ ++void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz) ++{ ++ switch(sz) ++ { ++ case 1: ++ rtw_write8(padapter, addr, (u8)val); ++ break; ++ case 2: ++ rtw_write16(padapter, addr, (u16)val); ++ break; ++ case 4: ++ rtw_write32(padapter, addr, val); ++ break; ++ default: ++ break; ++ } ++ ++} ++ ++u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask) ++{ ++ return rtw_hal_read_bbreg(padapter, addr, bitmask); ++} ++ ++void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val) ++{ ++ rtw_hal_write_bbreg(padapter, addr, bitmask, val); ++} ++ ++u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask) ++{ ++ return rtw_hal_read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask); ++} ++ ++void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val) ++{ ++ rtw_hal_write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask, val); ++} ++ ++u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr) ++{ ++ return _read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask); ++} ++ ++void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val) ++{ ++ _write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask, val); ++} ++ ++static void _init_mp_priv_(struct mp_priv *pmp_priv) ++{ ++ WLAN_BSSID_EX *pnetwork; ++ ++ _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv)); ++ ++ pmp_priv->mode = MP_OFF; ++ ++ pmp_priv->channel = 1; ++ pmp_priv->bandwidth = HT_CHANNEL_WIDTH_20; ++ pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmp_priv->rateidx = MPT_RATE_1M; ++ pmp_priv->txpoweridx = 0x2A; ++ ++ pmp_priv->antenna_tx = ANTENNA_A; ++ pmp_priv->antenna_rx = ANTENNA_AB; ++ ++ pmp_priv->check_mp_pkt = 0; ++ ++ pmp_priv->tx_pktcount = 0; ++ ++ pmp_priv->rx_pktcount = 0; ++ pmp_priv->rx_crcerrpktcount = 0; ++ ++ pmp_priv->network_macaddr[0] = 0x00; ++ pmp_priv->network_macaddr[1] = 0xE0; ++ pmp_priv->network_macaddr[2] = 0x4C; ++ pmp_priv->network_macaddr[3] = 0x87; ++ pmp_priv->network_macaddr[4] = 0x66; ++ pmp_priv->network_macaddr[5] = 0x55; ++ ++ pnetwork = &pmp_priv->mp_network.network; ++ _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); ++ ++ pnetwork->Ssid.SsidLength = 8; ++ _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength); ++} ++ ++#ifdef PLATFORM_WINDOWS ++/* ++void mp_wi_callback( ++ IN NDIS_WORK_ITEM* pwk_item, ++ IN PVOID cntx ++ ) ++{ ++ _adapter* padapter =(_adapter *)cntx; ++ struct mp_priv *pmppriv=&padapter->mppriv; ++ struct mp_wi_cntx *pmp_wi_cntx=&pmppriv->wi_cntx; ++ ++ // Execute specified action. ++ if(pmp_wi_cntx->curractfunc != NULL) ++ { ++ LARGE_INTEGER cur_time; ++ ULONGLONG start_time, end_time; ++ NdisGetCurrentSystemTime(&cur_time); // driver version ++ start_time = cur_time.QuadPart/10; // The return value is in microsecond ++ ++ pmp_wi_cntx->curractfunc(padapter); ++ ++ NdisGetCurrentSystemTime(&cur_time); // driver version ++ end_time = cur_time.QuadPart/10; // The return value is in microsecond ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("WorkItemActType: %d, time spent: %I64d us\n", ++ pmp_wi_cntx->param.act_type, (end_time-start_time))); ++ } ++ ++ NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock)); ++ pmp_wi_cntx->bmp_wi_progress= _FALSE; ++ NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock)); ++ ++ if (pmp_wi_cntx->bmpdrv_unload) ++ { ++ NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt)); ++ } ++ ++} ++*/ ++ ++static int init_mp_priv_by_os(struct mp_priv *pmp_priv) ++{ ++ struct mp_wi_cntx *pmp_wi_cntx; ++ ++ if (pmp_priv == NULL) return _FAIL; ++ ++ pmp_priv->rx_testcnt = 0; ++ pmp_priv->rx_testcnt1 = 0; ++ pmp_priv->rx_testcnt2 = 0; ++ ++ pmp_priv->tx_testcnt = 0; ++ pmp_priv->tx_testcnt1 = 0; ++ ++ pmp_wi_cntx = &pmp_priv->wi_cntx ++ pmp_wi_cntx->bmpdrv_unload = _FALSE; ++ pmp_wi_cntx->bmp_wi_progress = _FALSE; ++ pmp_wi_cntx->curractfunc = NULL; ++ ++ return _SUCCESS; ++} ++#endif ++ ++#ifdef PLATFORM_LINUX ++static int init_mp_priv_by_os(struct mp_priv *pmp_priv) ++{ ++ int i, res; ++ struct mp_xmit_frame *pmp_xmitframe; ++ ++ if (pmp_priv == NULL) return _FAIL; ++ ++ _rtw_init_queue(&pmp_priv->free_mp_xmitqueue); ++ ++ pmp_priv->pallocated_mp_xmitframe_buf = NULL; ++ pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4); ++ if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { ++ res = _FAIL; ++ goto _exit_init_mp_priv; ++ } ++ ++ pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR) (pmp_priv->pallocated_mp_xmitframe_buf) & 3); ++ ++ pmp_xmitframe = (struct mp_xmit_frame*)pmp_priv->pmp_xmtframe_buf; ++ ++ for (i = 0; i < NR_MP_XMITFRAME; i++) ++ { ++ _rtw_init_listhead(&pmp_xmitframe->list); ++ rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue); ++ ++ pmp_xmitframe->pkt = NULL; ++ pmp_xmitframe->frame_tag = MP_FRAMETAG; ++ pmp_xmitframe->padapter = pmp_priv->papdater; ++ ++ pmp_xmitframe++; ++ } ++ ++ pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; ++ ++ res = _SUCCESS; ++ ++_exit_init_mp_priv: ++ ++ return res; ++} ++#endif ++ ++static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) ++{ ++ struct pkt_attrib *pattrib; ++ struct tx_desc *desc; ++ ++ // init xmitframe attribute ++ pattrib = &pmptx->attrib; ++ _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); ++ desc = &pmptx->desc; ++ _rtw_memset(desc, 0, TXDESC_SIZE); ++ ++ pattrib->ether_type = 0x8712; ++ //_rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN); ++// _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); ++// pattrib->pctrl = 0; ++// pattrib->dhcp_pkt = 0; ++// pattrib->pktlen = 0; ++ pattrib->ack_policy = 0; ++// pattrib->pkt_hdrlen = ETH_HLEN; ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA; ++ pattrib->priority = 0; ++ pattrib->qsel = pattrib->priority; ++// do_queue_select(padapter, pattrib); ++ pattrib->nr_frags = 1; ++ pattrib->encrypt = 0; ++ pattrib->bswenc = _FALSE; ++ pattrib->qos_en = _FALSE; ++} ++ ++s32 init_mp_priv(PADAPTER padapter) ++{ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ ++ _init_mp_priv_(pmppriv); ++ pmppriv->papdater = padapter; ++ ++ pmppriv->tx.stop = 1; ++ mp_init_xmit_attrib(&pmppriv->tx, padapter); ++ ++ switch (padapter->registrypriv.rf_config) { ++ case RF_1T1R: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_A; ++ break; ++ case RF_1T2R: ++ default: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T4R: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_ABCD; ++ break; ++ } ++ ++ return _SUCCESS; ++} ++ ++void free_mp_priv(struct mp_priv *pmp_priv) ++{ ++ if (pmp_priv->pallocated_mp_xmitframe_buf) { ++ rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0); ++ pmp_priv->pallocated_mp_xmitframe_buf = NULL; ++ } ++ pmp_priv->pmp_xmtframe_buf = NULL; ++} ++ ++#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8723A) ++#define PHY_IQCalibrate(a,b) rtl8192c_PHY_IQCalibrate(a,b) ++#define PHY_LCCalibrate(a) rtl8192c_PHY_LCCalibrate(a) ++//#define dm_CheckTXPowerTracking(a) rtl8192c_odm_CheckTXPowerTracking(a) ++#define PHY_SetRFPathSwitch(a,b) rtl8192c_PHY_SetRFPathSwitch(a,b) ++#endif ++ ++#ifdef CONFIG_RTL8192D ++#define PHY_IQCalibrate(a,b) rtl8192d_PHY_IQCalibrate(a) ++#define PHY_LCCalibrate(a) rtl8192d_PHY_LCCalibrate(a) ++//#define dm_CheckTXPowerTracking(a) rtl8192d_odm_CheckTXPowerTracking(a) ++#define PHY_SetRFPathSwitch(a,b) rtl8192d_PHY_SetRFPathSwitch(a,b) ++#endif ++ ++#ifdef CONFIG_RTL8188E ++#define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8188E(a,b) ++#define PHY_LCCalibrate(a) PHY_LCCalibrate_8188E(a) ++#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8188E(a,b) ++#endif ++ ++s32 ++MPT_InitializeAdapter( ++ IN PADAPTER pAdapter, ++ IN u8 Channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ s32 rtStatus = _SUCCESS; ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ u32 ledsetting; ++ struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; ++ ++ //------------------------------------------------------------------------- ++ // HW Initialization for 8190 MPT. ++ //------------------------------------------------------------------------- ++ //------------------------------------------------------------------------- ++ // SW Initialization for 8190 MP. ++ //------------------------------------------------------------------------- ++ pMptCtx->bMptDrvUnload = _FALSE; ++ pMptCtx->bMassProdTest = _FALSE; ++ pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db ++ pMptCtx->h2cReqNum = 0x0; ++ /* Init mpt event. */ ++#if 0 // for Windows ++ NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) ); ++ NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) ); ++ ++ PlatformInitializeWorkItem( ++ Adapter, ++ &(pMptCtx->MptWorkItem), ++ (RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback, ++ (PVOID)Adapter, ++ "MptWorkItem"); ++#endif ++ //init for BT MP ++#ifdef CONFIG_RTL8723A ++ pMptCtx->bMPh2c_timeout = _FALSE; ++ pMptCtx->MptH2cRspEvent = _FALSE; ++ pMptCtx->MptBtC2hEvent = _FALSE; ++ ++ _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0); ++ _init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter ); ++ ++ //before the reset bt patch command,set the wifi page 0's IO to BT mac reboot. ++#endif ++ ++ pMptCtx->bMptWorkItemInProgress = _FALSE; ++ pMptCtx->CurrMptAct = NULL; ++ //------------------------------------------------------------------------- ++ ++#if 1 ++ // Don't accept any packets ++ rtw_write32(pAdapter, REG_RCR, 0); ++#else ++ // Accept CRC error and destination address ++ //pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP); ++ //rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); ++ rtw_write32(pAdapter, REG_RCR, 0x70000101); ++#endif ++ ++#if 0 ++ // If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP. ++ if (pHalData->AutoloadFailFlag == TRUE) ++ { ++ pHalData->RF_Type = RF_2T2R; ++ } ++#endif ++ ++ //ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); ++ //rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); ++ ++ if(IS_HARDWARE_TYPE_8192DU(pAdapter)) ++ { ++ rtw_write32(pAdapter, REG_LEDCFG0, 0x8888); ++ } ++ else ++ { ++ //rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); ++ ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); ++ ++ #if defined (CONFIG_RTL8192C) || defined( CONFIG_RTL8192D ) ++ rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); ++ #endif ++ } ++ ++ PHY_IQCalibrate(pAdapter, _FALSE); ++ dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter ++ PHY_LCCalibrate(pAdapter); ++ ++#ifdef CONFIG_PCI_HCI ++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main ++#else ++ ++#ifdef CONFIG_RTL8192C ++ if (pHalData->BoardType == BOARD_MINICARD) ++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main ++#endif ++ ++#endif ++ ++ pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); ++ pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); ++ pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); ++#ifdef CONFIG_RTL8188E ++ pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); ++ pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); ++#endif ++ //set ant to wifi side in mp mode ++#ifdef CONFIG_RTL8723A ++ rtl8723a_InitAntenna_Selection(pAdapter); ++#endif //CONFIG_RTL8723A ++ ++ //set ant to wifi side in mp mode ++ rtw_write16(pAdapter, 0x870, 0x300); ++ rtw_write16(pAdapter, 0x860, 0x110); ++ ++ if (pAdapter->registrypriv.mp_mode == 1) ++ pmlmepriv->fw_state = WIFI_MP_STATE; ++ ++ return rtStatus; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: MPT_DeInitAdapter() ++ * ++ * Overview: Extra DeInitialization for Mass Production Test. ++ * ++ * Input: PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/08/2007 MHC Create Version 0. ++ * 05/18/2007 MHC Add normal driver MPHalt code. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++MPT_DeInitAdapter( ++ IN PADAPTER pAdapter ++ ) ++{ ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ ++ pMptCtx->bMptDrvUnload = _TRUE; ++ #ifdef CONFIG_RTL8723A ++ _rtw_free_sema(&(pMptCtx->MPh2c_Sema)); ++ _cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer); ++ ++ rtw_write32(pAdapter, 0xcc, (rtw_read32(pAdapter, 0xcc)& 0xFFFFFFFD)| 0x00000002); ++ rtw_write32(pAdapter, 0x6b, (rtw_read32(pAdapter, 0x6b)& 0xFFFFFFFB)); ++ rtw_msleep_os(500); ++ rtw_write32(pAdapter, 0x6b, (rtw_read32(pAdapter, 0x6b)& 0xFFFFFFFB)| 0x00000004); ++ rtw_write32(pAdapter, 0xcc, (rtw_read32(pAdapter, 0xcc)& 0xFFFFFFFD)); ++ rtw_msleep_os(1000); ++ ++ DBG_871X("_rtw_mp_xmit_priv reinit for normal mode\n"); ++ _rtw_mp_xmit_priv(&pAdapter->xmitpriv); ++ #endif ++#if 0 // for Windows ++ PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) ); ++ ++ while(pMptCtx->bMptWorkItemInProgress) ++ { ++ if(NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50)) ++ { ++ break; ++ } ++ } ++ NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) ); ++#endif ++ ++} ++ ++static u8 mpt_ProStartTest(PADAPTER padapter) ++{ ++ PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx; ++ ++ pMptCtx->bMassProdTest = _TRUE; ++ pMptCtx->bStartContTx = _FALSE; ++ pMptCtx->bCckContTx = _FALSE; ++ pMptCtx->bOfdmContTx = _FALSE; ++ pMptCtx->bSingleCarrier = _FALSE; ++ pMptCtx->bCarrierSuppression = _FALSE; ++ pMptCtx->bSingleTone = _FALSE; ++ ++ return _SUCCESS; ++} ++ ++/* ++ * General use ++ */ ++s32 SetPowerTracking(PADAPTER padapter, u8 enable) ++{ ++ ++ Hal_SetPowerTracking( padapter, enable ); ++ return 0; ++} ++ ++void GetPowerTracking(PADAPTER padapter, u8 *enable) ++{ ++ Hal_GetPowerTracking( padapter, enable ); ++} ++ ++static void disable_dm(PADAPTER padapter) ++{ ++#ifndef CONFIG_RTL8723A ++ u8 v8; ++#endif ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ //3 1. disable firmware dynamic mechanism ++ // disable Power Training, Rate Adaptive ++#ifdef CONFIG_RTL8723A ++ SetBcnCtrlReg(padapter, 0, EN_BCN_FUNCTION); ++#else ++ v8 = rtw_read8(padapter, REG_BCN_CTRL); ++ v8 &= ~EN_BCN_FUNCTION; ++ rtw_write8(padapter, REG_BCN_CTRL, v8); ++#endif ++ ++ //3 2. disable driver dynamic mechanism ++ // disable Dynamic Initial Gain ++ // disable High Power ++ // disable Power Tracking ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ // enable APK, LCK and IQK but disable power tracking ++#ifndef CONFIG_RTL8188E ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; ++#endif ++ Switch_DM_Func(padapter, DYNAMIC_RF_CALIBRATION, _TRUE); ++} ++ ++ ++void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ //Switch_DM_Func(padapter, DYNAMIC_RF_CALIBRATION, bstart); ++ if (bstart==1){ ++ DBG_871X("in MPT_PwrCtlDM start \n"); ++ Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK, _TRUE); ++ pdmpriv->InitODMFlag |= ODM_RF_TX_PWR_TRACK ; ++ pdmpriv->InitODMFlag |= ODM_RF_CALIBRATION ; ++ pdmpriv->TxPowerTrackControl = _TRUE; ++#ifndef CONFIG_RTL8188E ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; ++#endif ++ }else{ ++ DBG_871X("in MPT_PwrCtlDM stop \n"); ++ disable_dm(padapter); ++ pdmpriv->TxPowerTrackControl = _FALSE; ++ #ifndef CONFIG_RTL8188E ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; ++ #endif ++ ++ } ++ ++} ++ ++ ++//This function initializes the DUT to the MP test mode ++s32 mp_start_test(PADAPTER padapter) ++{ ++ WLAN_BSSID_EX bssid; ++ struct sta_info *psta; ++ u32 length; ++ u8 val8; ++ ++ _irqL irqL; ++ s32 res = _SUCCESS; ++ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ ++ padapter->registrypriv.mp_mode = 1; ++ pmppriv->bSetTxPower=0; //for manually set tx power ++ ++ //3 disable dynamic mechanism ++ disable_dm(padapter); ++ //3 0. update mp_priv ++ ++ if (padapter->registrypriv.rf_config == RF_819X_MAX_TYPE) { ++// switch (phal->rf_type) { ++ switch (GET_RF_TYPE(padapter)) { ++ case RF_1T1R: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_A; ++ break; ++ case RF_1T2R: ++ default: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T4R: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_ABCD; ++ break; ++ } ++ } ++ ++ mpt_ProStartTest(padapter); ++ ++ //3 1. initialize a new WLAN_BSSID_EX ++// _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX)); ++ _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN); ++ bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc"); ++ _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_adhoc", bssid.Ssid.SsidLength); ++ bssid.InfrastructureMode = Ndis802_11IBSS; ++ bssid.NetworkTypeInUse = Ndis802_11DS; ++ bssid.IELength = 0; ++ ++ length = get_WLAN_BSSID_EX_sz(&bssid); ++ if (length % 4) ++ bssid.Length = ((length >> 2) + 1) << 2; //round up to multiple of 4 bytes. ++ else ++ bssid.Length = length; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ goto end_of_mp_start_test; ++ ++ //init mp_start_test status ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ rtw_disassoc_cmd(padapter, 500, _TRUE); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ pmppriv->prev_fw_state = get_fwstate(pmlmepriv); ++ if (padapter->registrypriv.mp_mode == 1) ++ pmlmepriv->fw_state = WIFI_MP_STATE; ++#if 0 ++ if (pmppriv->mode == _LOOPBOOK_MODE_) { ++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc ++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in Lookback mode\n")); ++ } else { ++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in normal mode\n")); ++ } ++#endif ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ //3 2. create a new psta for mp driver ++ //clear psta in the cur_network, if any ++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); ++ if (psta) rtw_free_stainfo(padapter, psta); ++ ++ psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress); ++ if (psta == NULL) { ++ RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n")); ++ pmlmepriv->fw_state = pmppriv->prev_fw_state; ++ res = _FAIL; ++ goto end_of_mp_start_test; ++ } ++ ++ //3 3. join psudo AdHoc ++ tgt_network->join_res = 1; ++ tgt_network->aid = psta->aid = 1; ++ _rtw_memcpy(&tgt_network->network, &bssid, length); ++ ++ rtw_indicate_connect(padapter); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++end_of_mp_start_test: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (res == _SUCCESS) ++ { ++ // set MSR to WIFI_FW_ADHOC_STATE ++#if !defined (CONFIG_RTL8712) ++ val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102 ++ val8 |= WIFI_FW_ADHOC_STATE; ++ rtw_write8(padapter, MSR, val8); // Link in ad hoc network ++#endif ++ ++#if defined (CONFIG_RTL8712) ++ rtw_write8(padapter, MSR, 1); // Link in ad hoc network ++ rtw_write8(padapter, RCR, 0); // RCR : disable all pkt, 0x10250048 ++ rtw_write8(padapter, RCR+2, 0x57); // RCR disable Check BSSID, 0x1025004a ++ ++ // disable RX filter map , mgt frames will put in RX FIFO 0 ++ rtw_write16(padapter, RXFLTMAP0, 0x0); // 0x10250116 ++ ++ val8 = rtw_read8(padapter, EE_9346CR); // 0x1025000A ++ if (!(val8 & _9356SEL))//boot from EFUSE ++ efuse_change_max_size(padapter); ++#endif ++ } ++ ++ return res; ++} ++//------------------------------------------------------------------------------ ++//This function change the DUT from the MP test mode into normal mode ++void mp_stop_test(PADAPTER padapter) ++{ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ struct sta_info *psta; ++ ++ _irqL irqL; ++ ++ if(pmppriv->mode==MP_ON) ++ { ++ pmppriv->bSetTxPower=0; ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE) ++ goto end_of_mp_stop_test; ++ ++ //3 1. disconnect psudo AdHoc ++ rtw_indicate_disconnect(padapter); ++ ++ //3 2. clear psta used in mp test mode. ++// rtw_free_assoc_resources(padapter, 1); ++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); ++ if (psta) rtw_free_stainfo(padapter, psta); ++ ++ //3 3. return to normal state (default:station mode) ++ pmlmepriv->fw_state = pmppriv->prev_fw_state; // WIFI_STATION_STATE; ++ ++ //flush the cur_network ++ _rtw_memset(tgt_network, 0, sizeof(struct wlan_network)); ++ ++ _clr_fwstate_(pmlmepriv, WIFI_MP_STATE); ++ ++end_of_mp_stop_test: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ } ++} ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++#if 0 ++//#ifdef CONFIG_USB_HCI ++static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID) ++{ ++ u8 eRFPath; ++ u32 rfReg0x26; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu ++ rfReg0x26 = 0xf400; ++ } ++ else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu ++ if ((4 == Channel) || (8 == Channel) || (12 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu ++ ++ if (HT_CHANNEL_WIDTH_20 == BandWidthID) { ++ if ((4 == Channel) || (8 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ else{ ++ if ((4 == Channel) || (8 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ } ++ ++// RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26)); ++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { ++ write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26); ++ } ++} ++#endif ++/*----------------------------------------------------------------------------- ++ * Function: mpt_SwitchRfSetting ++ * ++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. ++ * ++ * Input: IN PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. ++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++static void mpt_SwitchRfSetting(PADAPTER pAdapter) ++{ ++ Hal_mpt_SwitchRfSetting(pAdapter); ++ } ++ ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) ++{ ++ Hal_MPT_CCKTxPowerAdjust(Adapter,bInCH14); ++} ++ ++static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) ++{ ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter,beven); ++ } ++ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++ ++/* ++ * SetChannel ++ * Description ++ * Use H2C command to change channel, ++ * not only modify rf register, but also other setting need to be done. ++ */ ++void SetChannel(PADAPTER pAdapter) ++{ ++ Hal_SetChannel(pAdapter); ++ ++} ++ ++/* ++ * Notice ++ * Switch bandwitdth may change center frequency(channel) ++ */ ++void SetBandwidth(PADAPTER pAdapter) ++{ ++ Hal_SetBandwidth(pAdapter); ++ ++} ++ ++static void SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ Hal_SetCCKTxPower(pAdapter,TxPower); ++} ++ ++static void SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ Hal_SetOFDMTxPower(pAdapter,TxPower); ++ } ++ ++ ++void SetAntenna(PADAPTER pAdapter) ++ { ++ Hal_SetAntenna(pAdapter); ++} ++ ++void SetAntennaPathPower(PADAPTER pAdapter) ++{ ++ Hal_SetAntennaPathPower(pAdapter); ++} ++ ++void SetTxPower(PADAPTER pAdapter) ++{ ++ Hal_SetTxPower(pAdapter); ++ } ++ ++void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) ++{ ++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; ++ ++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); ++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); ++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); ++ ++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); ++ write_bbreg(pAdapter, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); ++} ++ ++void SetDataRate(PADAPTER pAdapter) ++{ ++ Hal_SetDataRate(pAdapter); ++} ++ ++void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter ,BOOLEAN bMain) ++{ ++ ++ PHY_SetRFPathSwitch(pAdapter,bMain); ++ ++} ++ ++#if defined (CONFIG_RTL8712) ++/*------------------------------Define structure----------------------------*/ ++typedef struct _R_ANTENNA_SELECT_OFDM { ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK { ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++#endif ++ ++s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) ++{ ++ return Hal_SetThermalMeter( pAdapter, target_ther); ++} ++ ++static void TriggerRFThermalMeter(PADAPTER pAdapter) ++{ ++ Hal_TriggerRFThermalMeter(pAdapter); ++} ++ ++static u8 ReadRFThermalMeter(PADAPTER pAdapter) ++{ ++ return Hal_ReadRFThermalMeter(pAdapter); ++} ++ ++void GetThermalMeter(PADAPTER pAdapter, u8 *value) ++{ ++ Hal_GetThermalMeter(pAdapter,value); ++} ++ ++void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetSingleCarrierTx(pAdapter,bStart); ++} ++ ++void SetSingleToneTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetSingleToneTx(pAdapter,bStart); ++} ++ ++void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetCarrierSuppressionTx(pAdapter, bStart); ++} ++ ++void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetCCKContinuousTx(pAdapter,bStart); ++} ++ ++void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetOFDMContinuousTx( pAdapter, bStart); ++}/* mpt_StartOfdmContTx */ ++ ++void SetContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ PhySetTxPowerLevel(pAdapter); ++ Hal_SetContinuousTx(pAdapter,bStart); ++} ++ ++ ++void PhySetTxPowerLevel(PADAPTER pAdapter) ++{ ++ struct mp_priv *pmp_priv = &pAdapter->mppriv; ++ ++ if (pmp_priv->bSetTxPower==0) // for NO manually set power index ++ { ++#ifdef CONFIG_RTL8188E ++ PHY_SetTxPowerLevel8188E(pAdapter,pmp_priv->channel); ++#elif defined(CONFIG_RTL8192D) ++ PHY_SetTxPowerLevel8192D(pAdapter,pmp_priv->channel); ++#else ++ PHY_SetTxPowerLevel8192C(pAdapter,pmp_priv->channel); ++#endif ++ } ++} ++ ++//------------------------------------------------------------------------------ ++static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe) ++{ ++ rtw_hal_mgnt_xmit(padapter, pmpframe); ++} ++ ++static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) ++{ ++ struct xmit_frame *pmpframe; ++ struct xmit_buf *pxmitbuf; ++ ++ if ((pmpframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL) ++ { ++ return NULL; ++ } ++ ++ if ((pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) ++ { ++ rtw_free_xmitframe(pxmitpriv, pmpframe); ++ return NULL; ++ } ++ ++ pmpframe->frame_tag = MP_FRAMETAG; ++ ++ pmpframe->pxmitbuf = pxmitbuf; ++ ++ pmpframe->buf_addr = pxmitbuf->pbuf; ++ ++ pxmitbuf->priv_data = pmpframe; ++ ++ return pmpframe; ++ ++} ++ ++static thread_return mp_xmit_packet_thread(thread_context context) ++{ ++ struct xmit_frame *pxmitframe; ++ struct mp_tx *pmptx; ++ struct mp_priv *pmp_priv; ++ struct xmit_priv *pxmitpriv; ++ PADAPTER padapter; ++ ++ pmp_priv = (struct mp_priv *)context; ++ pmptx = &pmp_priv->tx; ++ padapter = pmp_priv->papdater; ++ pxmitpriv = &(padapter->xmitpriv); ++ ++ thread_enter("RTW_MP_THREAD"); ++ ++ //DBG_871X("%s:pkTx Start\n", __func__); ++ while (1) { ++ pxmitframe = alloc_mp_xmitframe(pxmitpriv); ++ if (pxmitframe == NULL) { ++ if (pmptx->stop || ++ padapter->bSurpriseRemoved || ++ padapter->bDriverStopped) { ++ goto exit; ++ } ++ else { ++ rtw_msleep_os(1); ++ continue; ++ } ++ } ++ ++ _rtw_memcpy((u8 *)(pxmitframe->buf_addr+TXDESC_OFFSET), pmptx->buf, pmptx->write_size); ++ _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib)); ++ ++ dump_mpframe(padapter, pxmitframe); ++ ++ pmptx->sended++; ++ pmp_priv->tx_pktcount++; ++ ++ if (pmptx->stop || ++ padapter->bSurpriseRemoved || ++ padapter->bDriverStopped) ++ goto exit; ++ if ((pmptx->count != 0) && ++ (pmptx->count == pmptx->sended)) ++ goto exit; ++ ++ flush_signals_thread(); ++ } ++ ++exit: ++ //DBG_871X("%s:pkTx Exit\n", __func__); ++ rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size); ++ pmptx->pallocated_buf = NULL; ++ pmptx->stop = 1; ++ ++ thread_exit(); ++} ++ ++void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc) ++{ ++ struct mp_priv *pmp_priv = &padapter->mppriv; ++ _rtw_memcpy(ptxdesc, &(pmp_priv->tx.desc), TXDESC_SIZE); ++} ++ ++void SetPacketTx(PADAPTER padapter) ++{ ++ u8 *ptr, *pkt_start, *pkt_end; ++ u32 pkt_size,offset; ++ struct tx_desc *desc; ++ struct rtw_ieee80211_hdr *hdr; ++ u8 payload; ++ s32 bmcast; ++ struct pkt_attrib *pattrib; ++ struct mp_priv *pmp_priv; ++ ++ ++ pmp_priv = &padapter->mppriv; ++ if (pmp_priv->tx.stop) return; ++ pmp_priv->tx.sended = 0; ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx_pktcount = 0; ++ ++ //3 1. update_attrib() ++ pattrib = &pmp_priv->tx.attrib; ++ _rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ bmcast = IS_MCAST(pattrib->ra); ++ if (bmcast) { ++ pattrib->mac_id = 1; ++ pattrib->psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ pattrib->mac_id = 0; ++ pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ } ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; ++ ++ //3 2. allocate xmit buffer ++ pkt_size = pattrib->last_txcmdsz; ++ ++ if (pmp_priv->tx.pallocated_buf) ++ rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size); ++ pmp_priv->tx.write_size = pkt_size; ++ pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ; ++ pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size); ++ if (pmp_priv->tx.pallocated_buf == NULL) { ++ DBG_871X("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size); ++ return; ++ } ++ pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ); ++ ptr = pmp_priv->tx.buf; ++ ++ desc = &(pmp_priv->tx.desc); ++ _rtw_memset(desc, 0, TXDESC_SIZE); ++ pkt_start = ptr; ++ pkt_end = pkt_start + pkt_size; ++ ++ //3 3. init TX descriptor ++ // offset 0 ++#if defined(CONFIG_RTL8188E) && !defined(CONFIG_RTL8188E_SDIO) ++ desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size ++ desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc ++ if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet ++ ++ desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000); ++#endif ++ // offset 4 ++ #ifndef CONFIG_RTL8188E ++ desc->txdw1 |= cpu_to_le32(BK); // don't aggregate(AMPDU) ++ desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x1F); //CAM_ID(MAC_ID) ++ #else ++ desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); //CAM_ID(MAC_ID) ++ #endif ++ desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID ++ ++ #ifdef CONFIG_RTL8188E ++ desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); // Rate Adaptive ID ++ #else ++ desc->txdw1 |= cpu_to_le32((pattrib->raid << Rate_ID_SHT) & 0x000F0000); // Rate Adaptive ID ++ ++ #endif ++ // offset 8 ++ // desc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK ++ // offset 12 ++ ++ desc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0x0fff0000); ++// desc->txdw3 |= cpu_to_le32((pattrib->seqnum & 0xFFF) << SEQ_SHT); ++ //desc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0xffff0000); ++ ++ // offset 16 ++ //desc->txdw4 |= cpu_to_le32(QoS) ++ #ifdef CONFIG_RTL8188E ++ desc->txdw4 |= cpu_to_le32(HW_SSN); ++ #else ++ desc->txdw4 |= cpu_to_le32(HW_SEQ_EN); ++ #endif ++ desc->txdw4 |= cpu_to_le32(USERATE); ++ desc->txdw4 |= cpu_to_le32(DISDATAFB); ++ ++ if( pmp_priv->preamble ){ ++ if (pmp_priv->rateidx <= MPT_RATE_54M) ++ desc->txdw4 |= cpu_to_le32(DATA_SHORT); // CCK Short Preamble ++ } ++ if (pmp_priv->bandwidth == HT_CHANNEL_WIDTH_40) ++ desc->txdw4 |= cpu_to_le32(DATA_BW); ++ ++ // offset 20 ++ desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F); ++ ++ if( pmp_priv->preamble ){ ++ if (pmp_priv->rateidx > MPT_RATE_54M) ++ desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval ++ } ++ #ifdef CONFIG_RTL8188E ++ desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); // retry limit enable ++ desc->txdw5 |= cpu_to_le32(0x00180000); // DATA/RTS Rate Fallback Limit ++ #else ++ desc->txdw5 |= cpu_to_le32(0x0001FF00); // DATA/RTS Rate Fallback Limit ++ #endif ++ ++ //3 4. make wlan header, make_wlanhdr() ++ hdr = (struct rtw_ieee80211_hdr *)pkt_start; ++ SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); ++ _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA ++ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA ++ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID ++ ++ //3 5. make payload ++ ptr = pkt_start + pattrib->hdrlen; ++ ++ switch (pmp_priv->tx.payload) { ++ case 0: ++ payload = 0x00; ++ break; ++ case 1: ++ payload = 0x5a; ++ break; ++ case 2: ++ payload = 0xa5; ++ break; ++ case 3: ++ payload = 0xff; ++ break; ++ default: ++ payload = 0x00; ++ break; ++ } ++ ++ _rtw_memset(ptr, payload, pkt_end - ptr); ++ ++ //3 6. start thread ++#ifdef PLATFORM_LINUX ++ pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); ++ if (IS_ERR(pmp_priv->tx.PktTxThread)) ++ DBG_871X("Create PktTx Thread Fail !!!!!\n"); ++#endif ++#ifdef PLATFORM_FREEBSD ++{ ++ struct proc *p; ++ struct thread *td; ++ pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv, ++ &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread"); ++ ++ if (pmp_priv->tx.PktTxThread < 0) ++ DBG_871X("Create PktTx Thread Fail !!!!!\n"); ++} ++#endif ++} ++ ++void SetPacketRx(PADAPTER pAdapter, u8 bStartRx) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if(bStartRx) ++ { ++ // Accept CRC error and destination address ++#if 1 ++//ndef CONFIG_RTL8723A ++ //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; ++ ++ //pHalData->ReceiveConfig |= ACRC32; ++ ++ pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | AMF | ADF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; ++ ++ pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP); ++ ++ rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); ++ ++ // Accept all data frames ++ rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF); ++#else ++ rtw_write32(pAdapter, REG_RCR, 0x70000101); ++#endif ++ } ++ else ++ { ++ rtw_write32(pAdapter, REG_RCR, 0); ++ } ++} ++ ++void ResetPhyRxPktCount(PADAPTER pAdapter) ++{ ++ u32 i, phyrx_set = 0; ++ ++ for (i = 0; i <= 0xF; i++) { ++ phyrx_set = 0; ++ phyrx_set |= _RXERR_RPT_SEL(i); //select ++ phyrx_set |= RXERR_RPT_RST; // set counter to zero ++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); ++ } ++} ++ ++static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit) ++{ ++ //selection ++ u32 phyrx_set = 0, count = 0; ++ ++ phyrx_set = _RXERR_RPT_SEL(selbit & 0xF); ++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); ++ ++ //Read packet count ++ count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK; ++ ++ return count; ++} ++ ++u32 GetPhyRxPktReceived(PADAPTER pAdapter) ++{ ++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; ++ ++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK); ++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK); ++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK); ++ ++ return OFDM_cnt + CCK_cnt + HT_cnt; ++} ++ ++u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter) ++{ ++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; ++ ++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL); ++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL); ++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL); ++ ++ return OFDM_cnt + CCK_cnt + HT_cnt; ++} ++ ++//reg 0x808[9:0]: FFT data x ++//reg 0x808[22]: 0 --> 1 to get 1 FFT data y ++//reg 0x8B4[15:0]: FFT data y report ++static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) ++{ ++ int psd_val; ++ ++ ++ psd_val = rtw_read32(pAdapter, 0x808); ++ psd_val &= 0xFFBFFC00; ++ psd_val |= point; ++ ++ rtw_write32(pAdapter, 0x808, psd_val); ++ rtw_mdelay_os(1); ++ psd_val |= 0x00400000; ++ ++ rtw_write32(pAdapter, 0x808, psd_val); ++ rtw_mdelay_os(1); ++ psd_val = rtw_read32(pAdapter, 0x8B4); ++ ++ psd_val &= 0x0000FFFF; ++ ++ return psd_val; ++} ++ ++/* ++ * pts start_point_min stop_point_max ++ * 128 64 64 + 128 = 192 ++ * 256 128 128 + 256 = 384 ++ * 512 256 256 + 512 = 768 ++ * 1024 512 512 + 1024 = 1536 ++ * ++ */ ++u32 mp_query_psd(PADAPTER pAdapter, u8 *data) ++{ ++ u32 i, psd_pts=0, psd_start=0, psd_stop=0; ++ u32 psd_data=0; ++ ++ ++#ifdef PLATFORM_LINUX ++ if (!netif_running(pAdapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n")); ++ return 0; ++ } ++#endif ++ ++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n")); ++ return 0; ++ } ++ ++ if (strlen(data) == 0) { //default value ++ psd_pts = 128; ++ psd_start = 64; ++ psd_stop = 128; ++ } else { ++ sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); ++ } ++ ++ _rtw_memset(data, '\0', sizeof(data)); ++ ++ i = psd_start; ++ while (i < psd_stop) ++ { ++ if (i >= psd_pts) { ++ psd_data = rtw_GetPSDData(pAdapter, i-psd_pts); ++ } else { ++ psd_data = rtw_GetPSDData(pAdapter, i); ++ } ++ sprintf(data, "%s%x ", data, psd_data); ++ i++; ++ } ++ ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(100); ++ #else ++ rtw_mdelay_os(100); ++ #endif ++ ++ return strlen(data)+1; ++} ++ ++ ++ ++void _rtw_mp_xmit_priv (struct xmit_priv *pxmitpriv) ++{ ++ int i,res; ++ _adapter *padapter = pxmitpriv->adapter; ++ struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; ++ ++ u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; ++ u32 num_xmit_extbuf = NR_XMIT_EXTBUFF; ++ if(padapter->registrypriv.mp_mode ==0) ++ { ++ max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; ++ num_xmit_extbuf = NR_XMIT_EXTBUFF; ++ } ++ else ++ { ++ #ifdef CONFIG_RTL8723A_SDIO ++ max_xmit_extbuf_size = 20000; ++ num_xmit_extbuf = 1; ++ #else ++ max_xmit_extbuf_size = 6000; ++ num_xmit_extbuf = 8; ++ #endif ++ } ++ ++ pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; ++ for(i=0; ipallocated_xmit_extbuf) { ++ rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4); ++ } ++ ++ if(padapter->registrypriv.mp_mode ==0) ++ { ++ #ifdef CONFIG_RTL8723A_SDIO ++ max_xmit_extbuf_size = 20000; ++ num_xmit_extbuf = 1; ++ #else ++ max_xmit_extbuf_size = 6000; ++ num_xmit_extbuf = 8; ++ #endif ++ } ++ else ++ { ++ max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; ++ num_xmit_extbuf = NR_XMIT_EXTBUFF; ++ } ++ ++ // Init xmit extension buff ++ _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); ++ ++ pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4); ++ ++ if (pxmitpriv->pallocated_xmit_extbuf == NULL){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); ++ ++ pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; ++ ++ for (i = 0; i < num_xmit_extbuf; i++) ++ { ++ _rtw_init_listhead(&pxmitbuf->list); ++ ++ pxmitbuf->priv_data = NULL; ++ pxmitbuf->padapter = padapter; ++ pxmitbuf->ext_tag = _TRUE; ++ ++/* ++ pxmitbuf->pallocated_buf = rtw_zmalloc(max_xmit_extbuf_size); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), 4); ++*/ ++ ++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,max_xmit_extbuf_size + XMITBUF_ALIGN_SZ)) == _FAIL) { ++ res= _FAIL; ++ goto exit; ++ } ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->phead = pxmitbuf->pbuf; ++ pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size; ++ pxmitbuf->len = 0; ++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; ++#endif ++ ++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); ++ #ifdef DBG_XMIT_BUF_EXT ++ pxmitbuf->no=i; ++ #endif ++ pxmitbuf++; ++ ++ } ++ ++ pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf; ++ ++exit: ++ ; ++} ++ ++ ++void Hal_ProSetCrystalCap (PADAPTER pAdapter , u32 CrystalCapVal) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ CrystalCapVal = CrystalCapVal & 0x3F; ++ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, REG_AFE_XTAL_CTRL, 0xF0, CrystalCapVal & 0x0F); ++ PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, 0xF0000000, (CrystalCapVal & 0xF0) >> 4); ++ } ++ else if(IS_HARDWARE_TYPE_8188E(pAdapter)) ++ { ++ // write 0x24[16:11] = 0x24[22:17] = CrystalCap ++ PHY_SetBBReg(pAdapter, REG_AFE_XTAL_CTRL, 0x7FF800, (CrystalCapVal | (CrystalCapVal << 6))); ++ } ++ else ++ { ++ DBG_871X(" not as 88E and 92D Hal_ProSetCrystalCap 0x2c !!!!!\n"); ++ PHY_SetBBReg(pAdapter, 0x2c, 0xFFF000, (CrystalCapVal | (CrystalCapVal << 6))); ++ } ++} ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp_ioctl.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp_ioctl.c +new file mode 100644 +index 00000000..95570d1e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_mp_ioctl.c +@@ -0,0 +1,2954 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MP_IOCTL_C_ ++ ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++ ++ ++//**************** oid_rtl_seg_81_85 section start **************** ++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ Adapter->registrypriv.wireless_mode = *(u8*)poid_par_priv->information_buf; ++ } else if (poid_par_priv->type_of_oid == QUERY_OID) { ++ *(u8*)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode)); ++ } else { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_87_80 section start **************** ++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ struct bb_reg_param *pbbreg; ++ u16 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); ++ ++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff ++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; ++ ++ value = pbbreg->value; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n", ++ offset, value)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ write_bbreg(Adapter, offset, 0xFFFFFFFF, value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ struct bb_reg_param *pbbreg; ++ u16 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); ++ ++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff ++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ value = read_bbreg(Adapter, offset, 0xFFFFFFFF); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ pbbreg->value = value; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n", ++ offset, value)); ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ struct rf_reg_param *pbbreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); ++ ++ if (pbbreg->path >= MAX_RF_PATH_NUMS) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->offset > 0xFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->value > 0xFFFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ path = (u8)pbbreg->path; ++ offset = (u8)pbbreg->offset; ++ value = pbbreg->value; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", ++ path, offset, value)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ write_rfreg(Adapter, path, offset, value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ struct rf_reg_param *pbbreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); ++ ++ if (pbbreg->path >= MAX_RF_PATH_NUMS) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->offset > 0xFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ path = (u8)pbbreg->path; ++ offset = (u8)pbbreg->offset; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ value = read_rfreg(Adapter, path, offset); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ pbbreg->value = value; ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", ++ path, offset, value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_87_00 section end**************** ++//------------------------------------------------------------------------------ ++ ++//**************** oid_rtl_seg_81_80_00 section start **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 ratevalue;//4 ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_set_data_rate_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ ratevalue = *((u32*)poid_par_priv->information_buf);//4 ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue)); ++ if (ratevalue >= MPT_RATE_LAST) ++ return NDIS_STATUS_INVALID_DATA; ++ ++ Adapter->mppriv.rateidx = ratevalue; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetDataRate(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 mode; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n")); ++ ++ if (Adapter->registrypriv.mp_mode == 0) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ //IQCalibrateBcut(Adapter); ++ ++ mode = *((u32*)poid_par_priv->information_buf); ++ Adapter->mppriv.mode = mode;// 1 for loopback ++ ++ if (mp_start_test(Adapter) == _FAIL) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ goto exit; ++ } ++ ++exit: ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ mp_stop_test(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n")); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 Channel; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n")); ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) { ++ *((u32*)poid_par_priv->information_buf) = Adapter->mppriv.channel; ++ return NDIS_STATUS_SUCCESS; ++ } ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Channel = *((u32*)poid_par_priv->information_buf); ++ RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel)); ++ if (Channel > 14) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ Adapter->mppriv.channel = Channel; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetChannel(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u16 bandwidth; ++ u16 channel_offset; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_set_bandwidth_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ bandwidth = *((u32*)poid_par_priv->information_buf);//4 ++ channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ if (bandwidth != HT_CHANNEL_WIDTH_40) ++ bandwidth = HT_CHANNEL_WIDTH_20; ++ padapter->mppriv.bandwidth = (u8)bandwidth; ++ padapter->mppriv.prime_channel_offset = (u8)channel_offset; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetBandwidth(padapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n", ++ bandwidth, channel_offset)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 antenna; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n")); ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) ++ { ++ antenna = *(u32*)poid_par_priv->information_buf; ++ ++ Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16); ++ Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF); ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n", ++ Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetAntenna(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ } else { ++ antenna = (Adapter->mppriv.antenna_tx << 16)|Adapter->mppriv.antenna_rx; ++ *(u32*)poid_par_priv->information_buf = antenna; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 tx_pwr_idx; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ tx_pwr_idx = *((u32*)poid_par_priv->information_buf); ++ if (tx_pwr_idx > MAX_TX_PWR_INDEX_N_MODE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n", ++ Adapter->mppriv.txpoweridx)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetTxPower(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++//**************** oid_rtl_seg_81_80_20 section start **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid !=QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.tx_pktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n")); ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d \n",Adapter->mppriv.rx_pktcount)); ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n")); ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d \n",Adapter->mppriv.rx_crcerrpktcount)); ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++ ++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n")); ++ Adapter->mppriv.tx_pktcount = 0; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ Adapter->mppriv.rx_pktcount = 0; ++ Adapter->mppriv.rx_crcerrpktcount = 0; ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ResetPhyRxPktCount(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(ULONG)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktReceived(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG*)poid_par_priv->information_buf)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ ++ if (poid_par_priv->information_buf_len != sizeof(ULONG)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktCRC32Error(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG*)poid_par_priv->information_buf)); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_80_20 section end **************** ++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetContinuousTx(Adapter,(u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_871X("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetSingleCarrierTx(Adapter, (u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_871X("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetCarrierSuppressionTx(Adapter, (u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_871X("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetSingleToneTx(Adapter,(u8)bStartTest); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ return 0; ++} ++ ++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_80_00 section end **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ PNDIS_802_11_SSID pssid; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = (u32)sizeof(NDIS_802_11_SSID); ++ *poid_par_priv->bytes_rw = 0; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pssid = (PNDIS_802_11_SSID)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (mp_start_joinbss(Adapter, pssid) == _FAIL) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pRW_Reg RegRWStruct; ++ u32 offset, width; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_pro_read_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; ++ offset = RegRWStruct->offset; ++ width = RegRWStruct->width; ++ ++ if (offset > 0xFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ switch (width) { ++ case 1: ++ RegRWStruct->value = rtw_read8(Adapter, offset); ++ break; ++ case 2: ++ RegRWStruct->value = rtw_read16(Adapter, offset); ++ break; ++ default: ++ width = 4; ++ RegRWStruct->value = rtw_read32(Adapter, offset); ++ break; ++ } ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n", ++ offset, RegRWStruct->value)); ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = width; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pRW_Reg RegRWStruct; ++ u32 offset, width, value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_pro_write_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; ++ offset = RegRWStruct->offset; ++ width = RegRWStruct->width; ++ value = RegRWStruct->value; ++ ++ if (offset > 0xFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ if (value > 0xFF) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ rtw_write8(padapter, offset, (u8)value); ++ break; ++ case 2: ++ if (value > 0xFFFF) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ rtw_write16(padapter, offset, (u16)value); ++ break; ++ case 4: ++ rtw_write32(padapter, offset, value); ++ break; ++ default: ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n", ++ offset, width, value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pBurst_RW_Reg pBstRwReg; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ rtw_read_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n")); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pBurst_RW_Reg pBstRwReg; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n")); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ ++ TX_CMD_Desc *TxCmd_Info; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n")); ++ ++ TxCmd_Info=(TX_CMD_Desc*)poid_par_priv->information_buf; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset)); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0])); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1])); ++ RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2])); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3])); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ rtw_write32(Adapter, TxCmd_Info->offset + 0, (unsigned int)TxCmd_Info->TxCMD.value[0]); ++ rtw_write32(Adapter, TxCmd_Info->offset + 4, (unsigned int)TxCmd_Info->TxCMD.value[1]); ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pEEPROM_RWParam pEEPROM; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ pEEPROM->value = eeprom_read16(padapter, (u16)(pEEPROM->offset >> 1)); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n", ++ pEEPROM->offset, pEEPROM->value)); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ pEEPROM_RWParam pEEPROM; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ eeprom_write16(padapter, (u16)(pEEPROM->offset >> 1), pEEPROM->value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct mp_wiparam *pwi_param; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct mp_wiparam)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (Adapter->mppriv.workparam.bcompleted == _FALSE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pwi_param = (struct mp_wiparam *)poid_par_priv->information_buf; ++ ++ _rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam)); ++ Adapter->mppriv.act_in_progress = _FALSE; ++// RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(uint)*2) { ++ RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len)); ++ return NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ if (*(uint*)poid_par_priv->information_buf == 1)//init==1 ++ Adapter->mppriv.rx_pktloss = 0; ++ ++ *((uint*)poid_par_priv->information_buf+1) = Adapter->mppriv.rx_pktloss; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#endif ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++#ifdef CONFIG_SDIO_HCI ++ _irqlevel_changed_(&oldirql, LOWER); ++{ ++ u32 *plmem = (u32*)poid_par_priv->information_buf+2; ++ _attrib_read = pintfhdl->io_ops._attrib_read; ++ _attrib_read(pintfhdl, *((u32*)poid_par_priv->information_buf), ++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++} ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#endif ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++#ifdef CONFIG_SDIO_HCI ++ _irqlevel_changed_(&oldirql, LOWER); ++{ ++ u32 *plmem = (u32*)poid_par_priv->information_buf + 2; ++ _attrib_write = pintfhdl->io_ops._attrib_write; ++ _attrib_write(pintfhdl, *(u32*)poid_par_priv->information_buf, ++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); ++} ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setrfintfs_cmd(Adapter, *(unsigned char*)poid_par_priv->information_buf) == _FAIL) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _rtw_memcpy(poid_par_priv->information_buf, (unsigned char*)&Adapter->mppriv.rxstat, sizeof(struct recv_stat)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ PCFG_DBG_MSG_STRUCT pdbg_msg; ++ ++_func_enter_; ++ ++// RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n")); ++ ++#if 0//#ifdef CONFIG_DEBUG_RTL871X ++ ++ pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf); ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n", ++ pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32)); ++ ++ GlobalDebugLevel = pdbg_msg->DebugLevel; ++ GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32; ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===> Set level :0x%08x, component:0x%016x\n", ++ GlobalDebugLevel, (u32)GlobalDebugComponents)); ++ } else { ++ pdbg_msg->DebugLevel = GlobalDebugLevel; ++ pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32); ++ pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n", ++ (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32)); ++ } ++ ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setdatarate_cmd(Adapter, poid_par_priv->information_buf) !=_SUCCESS) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ u8 thermal = 0; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ GetThermalMeter(Adapter, &thermal); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *(u32*)poid_par_priv->information_buf = (u32)thermal; ++ *poid_par_priv->bytes_rw = sizeof(u32); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (Adapter->mppriv.act_in_progress == _TRUE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ //init workparam ++ Adapter->mppriv.act_in_progress = _TRUE; ++ Adapter->mppriv.workparam.bcompleted = _FALSE; ++ Adapter->mppriv.workparam.act_type = MPT_READ_TSSI; ++ Adapter->mppriv.workparam.io_offset = 0; ++ Adapter->mppriv.workparam.io_value = 0xFFFFFFFF; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (!rtw_gettssi_cmd(Adapter,0, (u8*)&Adapter->mppriv.workparam.io_value)) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ ++_func_enter_; ++ ++// if (poid_par_priv->type_of_oid != SET_OID) ++// return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ u8 enable; ++ ++ enable = *(u8*)poid_par_priv->information_buf; ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable)); ++ ++ SetPowerTracking(Adapter, enable); ++ } else { ++ GetPowerTracking(Adapter, (u8*)poid_par_priv->information_buf); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u32 ratevalue; ++ u8 datarates[NumRates]; ++ int i; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ ratevalue = *((u32*)poid_par_priv->information_buf); ++ ++ for (i = 0; i < NumRates; i++) { ++ if (ratevalue == mpdatarate[i]) ++ datarates[i] = mpdatarate[i]; ++ else ++ datarates[i] = 0xff; ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i])); ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setbasicrate_cmd(padapter, datarates) != _SUCCESS) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < 8) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ *poid_par_priv->bytes_rw = 8; ++ _rtw_memcpy(poid_par_priv->information_buf, &(adapter_to_pwrctl(Adapter)->pwr_mode), 8); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n", ++ adapter_to_pwrctl(Adapter)->pwr_mode, adapter_to_pwrctl(Adapter)->smart_ps)); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ uint pwr_mode, smart_ps; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_rw = 0; ++ *poid_par_priv->bytes_needed = 8; ++ ++ if (poid_par_priv->information_buf_len < 8) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pwr_mode = *(uint *)(poid_par_priv->information_buf); ++ smart_ps = *(uint *)((int)poid_par_priv->information_buf + 4); ++ ++ *poid_par_priv->bytes_rw = 8; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct setratable_parm *prate_table; ++ u8 res; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = sizeof(struct setratable_parm); ++ if (poid_par_priv->information_buf_len < sizeof(struct setratable_parm)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ prate_table = (struct setratable_parm*)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ res = rtw_setrttbl_cmd(Adapter, prate_table); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ if (res == _FAIL) ++ status = NDIS_STATUS_FAILURE; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ #if 0 ++ struct mp_wi_cntx *pmp_wi_cntx=&(Adapter->mppriv.wi_cntx); ++ u8 res=_SUCCESS; ++ DEBUG_INFO(("===> Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); ++ ++ if(pmp_wi_cntx->bmp_wi_progress ==_TRUE){ ++ DEBUG_ERR(("\n mp workitem is progressing, not allow to set another workitem right now!!!\n")); ++ Status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ else{ ++ pmp_wi_cntx->bmp_wi_progress=_TRUE; ++ pmp_wi_cntx->param.bcompleted=_FALSE; ++ pmp_wi_cntx->param.act_type=MPT_GET_RATE_TABLE; ++ pmp_wi_cntx->param.io_offset=0x0; ++ pmp_wi_cntx->param.bytes_cnt=sizeof(struct getratable_rsp); ++ pmp_wi_cntx->param.io_value=0xffffffff; ++ ++ res=rtw_getrttbl_cmd(Adapter,(struct getratable_rsp *)pmp_wi_cntx->param.data); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ if(res != _SUCCESS) ++ { ++ Status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ } ++ DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); ++ #endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++//**************** oid_rtl_seg_87_12_00 section start **************** ++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct security_priv *psecuritypriv = &Adapter->securitypriv; ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ ENCRY_CTRL_STATE encry_mode; ++ ++ ++ *poid_par_priv->bytes_needed = sizeof(u8); ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) ++ { ++ encry_mode = *((u8*)poid_par_priv->information_buf); ++ switch (encry_mode) ++ { ++ case HW_CONTROL: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_FALSE; ++ Adapter->registrypriv.software_encrypt=_FALSE; ++ #else ++ psecuritypriv->sw_decrypt = _FALSE; ++ psecuritypriv->sw_encrypt = _FALSE; ++ #endif ++ break; ++ case SW_CONTROL: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_TRUE; ++ Adapter->registrypriv.software_encrypt=_TRUE; ++ #else ++ psecuritypriv->sw_decrypt = _TRUE; ++ psecuritypriv->sw_encrypt = _TRUE; ++ #endif ++ break; ++ case HW_ENCRY_SW_DECRY: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_TRUE; ++ Adapter->registrypriv.software_encrypt=_FALSE; ++ #else ++ psecuritypriv->sw_decrypt = _TRUE; ++ psecuritypriv->sw_encrypt = _FALSE; ++ #endif ++ break; ++ case SW_ENCRY_HW_DECRY: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_FALSE; ++ Adapter->registrypriv.software_encrypt=_TRUE; ++ #else ++ psecuritypriv->sw_decrypt = _FALSE; ++ psecuritypriv->sw_encrypt = _TRUE; ++ #endif ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, ++ ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n", ++ encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt)); ++ } ++ else { ++ #if 0 ++ if (Adapter->registrypriv.software_encrypt == _FALSE) { ++ if (Adapter->registrypriv.software_decrypt == _FALSE) ++ encry_mode = HW_CONTROL; ++ else ++ encry_mode = HW_ENCRY_SW_DECRY; ++ } ++ else { ++ if (Adapter->registrypriv.software_decrypt == _FALSE) ++ encry_mode = SW_ENCRY_HW_DECRY; ++ else ++ encry_mode = SW_CONTROL; ++ } ++ #else ++ ++ if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _FALSE)) ++ encry_mode = HW_CONTROL; ++ else if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _TRUE)) ++ encry_mode = HW_ENCRY_SW_DECRY; ++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _FALSE)) ++ encry_mode = SW_ENCRY_HW_DECRY; ++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _TRUE)) ++ encry_mode = SW_CONTROL; ++ ++ #endif ++ ++ *(u8*)poid_par_priv->information_buf = encry_mode; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n", ++ encry_mode)); ++ } ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct sta_info *psta = NULL; ++ UCHAR *macaddr; ++ ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = ETH_ALEN; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ macaddr = (UCHAR *) poid_par_priv->information_buf ; ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, ++ ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); ++ ++ if (psta == NULL) { // the sta have been in sta_info_queue => do nothing ++ psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr); ++ ++ if (psta == NULL) { ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } else { //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY) ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ++ ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue \n")); ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct sta_info *psta = NULL; ++ UCHAR *macaddr; ++ ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = ETH_ALEN; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ macaddr = (UCHAR *) poid_par_priv->information_buf ; ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, ++ ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); ++ ++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); ++ if (psta != NULL) { ++ _enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); ++ rtw_free_stainfo(Adapter, psta); ++ _exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); ++ } ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++#if 0 ++#include ++static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) ++{ ++#ifdef CONFIG_SDIO_HCI ++ ++ if (offset == 1) { ++ u16 tmp_blk_num; ++ tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM); ++ RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x dvobj.rxblknum=0x%x\n", tmp_blk_num, adapter_to_dvobj(padapter)->rxblknum)); ++ if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) { ++ RT_TRACE(_module_mp_,_drv_err_, ("Query Information, mp_query_drv_var call recv rx\n")); ++ // sd_recv_rxfifo(padapter); ++ } ++ } ++ ++#if 0 ++ if(offset <=100){ //For setting data rate and query data rate ++ if(offset==100){ //For query data rate ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); ++ var=padapter->registrypriv.tx_rate; ++ ++ } ++ else if(offset<0x1d){ //For setting data rate ++ padapter->registrypriv.tx_rate=offset; ++ var=padapter->registrypriv.tx_rate; ++ padapter->registrypriv.use_rate=_TRUE; ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); ++ } ++ else{ //not use the data rate ++ padapter->registrypriv.use_rate=_FALSE; ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n",offset)); ++ } ++ } ++ else if (offset<=110){ //for setting debug level ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n",offset)); ++ if(offset==110){ //For query data rate ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x \n",offset,padapter->registrypriv.dbg_level)); ++ padapter->registrypriv.dbg_level=GlobalDebugLevel; ++ var=padapter->registrypriv.dbg_level; ++ } ++ else if(offset<110 && offset>100){ ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x \n",offset,offset-100)); ++ padapter->registrypriv.dbg_level=GlobalDebugLevel=offset-100; ++ var=padapter->registrypriv.dbg_level; ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ ++ } ++ } ++ else if(offset >110 &&offset <116){ ++ if(115==offset){ ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); ++ } ++ else { ++ switch(offset){ ++ case 111: ++ adapter_to_dvobj(padapter)->tx_block_mode=1; ++ adapter_to_dvobj(padapter)->rx_block_mode=1; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); ++ break; ++ case 112: ++ adapter_to_dvobj(padapter)->tx_block_mode=1; ++ adapter_to_dvobj(padapter)->rx_block_mode=0; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); ++ break; ++ case 113: ++ adapter_to_dvobj(padapter)->tx_block_mode=0; ++ adapter_to_dvobj(padapter)->rx_block_mode=1; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); ++ break; ++ case 114: ++ adapter_to_dvobj(padapter)->tx_block_mode=0; ++ adapter_to_dvobj(padapter)->rx_block_mode=0; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); ++ break; ++ default : ++ break; ++ ++ } ++ ++ } ++ ++ } ++ else if(offset>=127){ ++ u64 prnt_dbg_comp; ++ u8 chg_idx; ++ u64 tmp_dbg_comp; ++ chg_idx=offset-0x80; ++ tmp_dbg_comp=BIT(chg_idx); ++ prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; ++ RT_TRACE(_module_mp_, _drv_emerg_, (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n",offset,offset,prnt_dbg_comp,GlobalDebugComponents,padapter->registrypriv.dbg_component)); ++ if(offset==127){ ++ // prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; ++ var=(u32)(padapter->registrypriv.dbg_component); ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) \n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ ++ } ++ else{ ++ RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_,("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx));// ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp) ++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ ++ if(GlobalDebugComponents&tmp_dbg_comp){ ++ //this bit is already set, now clear it ++ GlobalDebugComponents=GlobalDebugComponents&(~tmp_dbg_comp); ++ } ++ else{ ++ //this bit is not set, now set it. ++ GlobalDebugComponents =GlobalDebugComponents|tmp_dbg_comp; ++ } ++ RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,prnt_dbg_comp)); ++ RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ var=(u32)(GlobalDebugComponents); ++ //GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ ++ } ++ } ++ else{ ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n",offset)); ++ } ++#endif ++#endif ++ ++ return var; ++} ++#endif ++ ++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ DR_VARIABLE_STRUCT *pdrv_var; ++ ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = sizeof(DR_VARIABLE_STRUCT); ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n")); ++ ++ pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ pdrv_var->variable = mp_query_drv_var(Adapter, pdrv_var->offset, pdrv_var->variable); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n", ++ pdrv_var->offset, pdrv_var->variable)); ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n")); ++ ++ if (poid_par_priv->information_buf_len < sizeof (UCHAR)) { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ *poid_par_priv->bytes_needed = sizeof(UCHAR); ++ return status; ++ } ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf; ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n",\ ++ Adapter->mppriv.rx_with_status)); ++ ++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); ++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ ++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); ++ ++ } ++ else { ++ *(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n", \ ++ Adapter->mppriv.rx_with_status)); ++ ++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); ++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ ++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); ++ } ++#endif ++ ++ return NDIS_STATUS_SUCCESS; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ PEFUSE_ACCESS_STRUCT pefuse; ++ u8 *data; ++ u16 addr = 0, cnts = 0, max_available_size = 0; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(EFUSE_ACCESS_STRUCT)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; ++ addr = pefuse->start_addr; ++ cnts = pefuse->cnts; ++ data = pefuse->data; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_read_efuse_hd: buf_len=%d addr=%d cnts=%d\n", ++ poid_par_priv->information_buf_len, addr, cnts)); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n")); ++ return NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n")); ++ status = NDIS_STATUS_FAILURE; ++ } else ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ PEFUSE_ACCESS_STRUCT pefuse; ++ u8 *data; ++ u16 addr = 0, cnts = 0, max_available_size = 0; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; ++ addr = pefuse->start_addr; ++ cnts = pefuse->cnts; ++ data = pefuse->data; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_write_efuse_hdl: buf_len=%d addr=0x%04x cnts=%d\n", ++ poid_par_priv->information_buf_len, addr, cnts)); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error")); ++ return NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (rtw_efuse_access(Adapter, _TRUE, addr, cnts, data) == _FAIL) ++ status = NDIS_STATUS_FAILURE; ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ PPGPKT_STRUCT ppgpkt; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++// RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n")); ++ ++ *poid_par_priv->bytes_rw = 0; ++ ++ if (poid_par_priv->information_buf_len < sizeof(PGPKT_STRUCT)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ ppgpkt = (PPGPKT_STRUCT)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ { ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n",\ ++ ppgpkt->offset)); ++ ++ Efuse_PowerSwitch(Adapter, _FALSE, _TRUE); ++ if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE) ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ else ++ status = NDIS_STATUS_FAILURE; ++ Efuse_PowerSwitch(Adapter, _FALSE, _FALSE); ++ } else { ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n",\ ++ ppgpkt->offset, ppgpkt->word_en)); ++ ++ Efuse_PowerSwitch(Adapter, _TRUE, _TRUE); ++ if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE) ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ else ++ status = NDIS_STATUS_FAILURE; ++ Efuse_PowerSwitch(Adapter, _TRUE, _FALSE); ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u16 size; ++ u8 ret; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf = size; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } else ++ status = NDIS_STATUS_FAILURE; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ *(u32*)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n", ++ *(int*)poid_par_priv->information_buf, status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ status = oid_rt_pro_read_efuse_hdl(poid_par_priv); ++ else ++ status = oid_rt_pro_write_efuse_hdl(poid_par_priv); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u8 *data; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ u16 mapLen=0; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n")); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ *poid_par_priv->bytes_rw = 0; ++ ++ if (poid_par_priv->information_buf_len < mapLen) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ data = (u8*)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_efuse_map_hdl: READ\n")); ++ ++ if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS) ++ *poid_par_priv->bytes_rw = mapLen; ++ else { ++ RT_TRACE(_module_mp_, _drv_err_, ++ ("oid_rt_pro_efuse_map_hdl: READ fail\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } else { ++ // SET_OID ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_efuse_map_hdl: WRITE\n")); ++ ++ if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS) ++ *poid_par_priv->bytes_rw = mapLen; ++ else { ++ RT_TRACE(_module_mp_, _drv_err_, ++ ("oid_rt_pro_efuse_map_hdl: WRITE fail\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ ++ u32 crystal_cap = 0; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf);//4 ++ if (crystal_cap > 0xf) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Adapter->mppriv.curr_crystalcap = crystal_cap; ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ SetCrystalCap(Adapter); ++ _irqlevel_changed_(&oldirql,RAISE); ++ ++_func_exit_; ++ ++#endif ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u8 rx_pkt_type; ++// u32 rcr_val32; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++// PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ rx_pkt_type = *((u8*)poid_par_priv->information_buf);//4 ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n",rx_pkt_type )); ++#if 0 ++ _irqlevel_changed_(&oldirql, LOWER); ++#if 0 ++ rcr_val8 = rtw_read8(Adapter, 0x10250048);//RCR ++ rcr_val8 &= ~(RCR_AB|RCR_AM|RCR_APM|RCR_AAP); ++ ++ if(rx_pkt_type == RX_PKT_BROADCAST){ ++ rcr_val8 |= (RCR_AB | RCR_ACRC32 ); ++ } ++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){ ++ rcr_val8 |= (RCR_AAP| RCR_AM |RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){ ++ rcr_val8 |= (RCR_APM|RCR_ACRC32); ++ } ++ else{ ++ rcr_val8 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ } ++ rtw_write8(padapter, 0x10250048,rcr_val8); ++#else ++ rcr_val32 = rtw_read32(padapter, RCR);//RCR = 0x10250048 ++ rcr_val32 &= ~(RCR_CBSSID|RCR_AB|RCR_AM|RCR_APM|RCR_AAP); ++#if 0 ++ if(rx_pkt_type == RX_PKT_BROADCAST){ ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){ ++ //rcr_val32 |= (RCR_CBSSID|RCR_AAP|RCR_AM|RCR_ACRC32); ++ rcr_val32 |= (RCR_CBSSID|RCR_APM|RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){ ++ rcr_val32 |= (RCR_APM|RCR_ACRC32); ++ //rcr_val32 |= (RCR_AAP|RCR_ACRC32); ++ } ++ else{ ++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ } ++#else ++ switch (rx_pkt_type) ++ { ++ case RX_PKT_BROADCAST : ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ break; ++ case RX_PKT_DEST_ADDR : ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ break; ++ case RX_PKT_PHY_MATCH: ++ rcr_val32 |= (RCR_APM|RCR_ACRC32); ++ break; ++ default: ++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ break; ++ } ++ ++ if (rx_pkt_type == RX_PKT_DEST_ADDR) { ++ padapter->mppriv.check_mp_pkt = 1; ++ } else { ++ padapter->mppriv.check_mp_pkt = 0; ++ } ++#endif ++ rtw_write32(padapter, RCR, rcr_val32); ++ ++#endif ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ u32 txagc; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ txagc = *(u32*)poid_par_priv->information_buf; ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetTxAGCOffset(Adapter, txagc); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct mp_priv *pmppriv = &Adapter->mppriv; ++ u32 type; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf; ++ ++ if (_LOOPBOOK_MODE_ == type) { ++ pmppriv->mode = type; ++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc ++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv))); ++ } else if (_2MAC_MODE_ == type){ ++ pmppriv->mode = type; ++ _clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE); ++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv))); ++ } else ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PMP_XMIT_PARM pparm; ++ PADAPTER padapter; ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__)); ++ ++ pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf; ++ padapter = (PADAPTER)poid_par_priv->adapter_context; ++ pmp_priv = &padapter->mppriv; ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) { ++ pparm->enable = !pmp_priv->tx.stop; ++ pparm->count = pmp_priv->tx.sended; ++ } else { ++ if (pparm->enable == 0) { ++ pmp_priv->tx.stop = 1; ++ } else if (pmp_priv->tx.stop == 1) { ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = pparm->count; ++ pmp_priv->tx.payload = pparm->payload_type; ++ pattrib = &pmp_priv->tx.attrib; ++ pattrib->pktlen = pparm->length; ++ _rtw_memcpy(pattrib->dst, pparm->da, ETH_ALEN); ++ SetPacketTx(padapter); ++ } else ++ return NDIS_STATUS_FAILURE; ++ } ++ ++ return NDIS_STATUS_SUCCESS; ++} ++ ++#if 0 ++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ unsigned char *pframe, *pmp_pkt; ++ struct ethhdr *pethhdr; ++ struct pkt_attrib *pattrib; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ int llc_sz, payload_len; ++ struct mp_xmit_frame *pxframe= NULL; ++ struct mp_xmit_packet *pmp_xmitpkt = (struct mp_xmit_packet*)param; ++ u8 addr3[] = {0x02, 0xE0, 0x4C, 0x87, 0x66, 0x55}; ++ ++// DBG_871X("+mp_ioctl_xmit_packet_hdl\n"); ++ ++ pxframe = alloc_mp_xmitframe(&padapter->mppriv); ++ if (pxframe == NULL) ++ { ++ DEBUG_ERR(("Can't alloc pmpframe %d:%s\n", __LINE__, __FILE__)); ++ return -1; ++ } ++ ++ //mp_xmit_pkt ++ payload_len = pmp_xmitpkt->len - 14; ++ pmp_pkt = (unsigned char*)pmp_xmitpkt->mem; ++ pethhdr = (struct ethhdr *)pmp_pkt; ++ ++ //DBG_871X("payload_len=%d, pkt_mem=0x%x\n", pmp_xmitpkt->len, (void*)pmp_xmitpkt->mem); ++ ++ //DBG_871X("pxframe=0x%x\n", (void*)pxframe); ++ //DBG_871X("pxframe->mem=0x%x\n", (void*)pxframe->mem); ++ ++ //update attribute ++ pattrib = &pxframe->attrib; ++ memset((u8 *)(pattrib), 0, sizeof (struct pkt_attrib)); ++ pattrib->pktlen = pmp_xmitpkt->len; ++ pattrib->ether_type = ntohs(pethhdr->h_proto); ++ pattrib->hdrlen = 24; ++ pattrib->nr_frags = 1; ++ pattrib->priority = 0; ++#ifndef CONFIG_MP_LINUX ++ if(IS_MCAST(pethhdr->h_dest)) ++ pattrib->mac_id = 4; ++ else ++ pattrib->mac_id = 5; ++#else ++ pattrib->mac_id = 5; ++#endif ++ ++ // ++ memset(pxframe->mem, 0 , WLANHDR_OFFSET); ++ pframe = (u8 *)(pxframe->mem) + WLANHDR_OFFSET; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ SetFrameSubType(pframe, WIFI_DATA); ++ ++ _rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr3, addr3, ETH_ALEN); ++ ++ pwlanhdr->seq_ctl = 0; ++ pframe += pattrib->hdrlen; ++ ++ llc_sz= rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ ++ _rtw_memcpy(pframe, (void*)(pmp_pkt+14), payload_len); ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + llc_sz + payload_len; ++ ++ DEBUG_INFO(("issuing mp_xmit_frame, tx_len=%d, ether_type=0x%x\n", pattrib->last_txcmdsz, pattrib->ether_type)); ++ xmit_mp_frame(padapter, pxframe); ++ ++ return _SUCCESS; ++} ++#endif ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#ifdef PLATFORM_OS_XP ++ _irqL oldirql; ++#endif ++ u8 bpwrup; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#ifdef PLATFORM_LINUX ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++#endif ++#endif ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("\n ===> Setoid_rt_set_power_down_hdl.\n")); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ bpwrup = *(u8 *)poid_par_priv->information_buf; ++ //CALL the power_down function ++#ifdef PLATFORM_LINUX ++#if defined(CONFIG_RTL8712) //Linux MP insmod unknown symbol ++ dev_power_down(padapter,bpwrup); ++#endif ++#endif ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ //DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. ++ // Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++//#ifdef PLATFORM_OS_XP ++// _irqL oldirql; ++//#endif ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if (poid_par_priv->information_buf_len < sizeof(u32)) { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("\n ===> oid_rt_get_power_mode_hdl.\n")); ++ ++// _irqlevel_changed_(&oldirql, LOWER); ++ *(int*)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++// _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_odm.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_odm.c +new file mode 100644 +index 00000000..b7176266 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_odm.c +@@ -0,0 +1,217 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2013 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++ ++const char *odm_comp_str[] = { ++ "ODM_COMP_DIG", ++ "ODM_COMP_RA_MASK", ++ "ODM_COMP_DYNAMIC_TXPWR", ++ "ODM_COMP_FA_CNT", ++ "ODM_COMP_RSSI_MONITOR", ++ "ODM_COMP_CCK_PD", ++ "ODM_COMP_ANT_DIV", ++ "ODM_COMP_PWR_SAVE", ++ "ODM_COMP_PWR_TRAIN", ++ "ODM_COMP_RATE_ADAPTIVE", ++ "ODM_COMP_PATH_DIV", ++ "ODM_COMP_PSD", ++ "ODM_COMP_DYNAMIC_PRICCA", ++ "ODM_COMP_RXHP", ++ NULL, ++ NULL, ++ "ODM_COMP_EDCA_TURBO", ++ "ODM_COMP_EARLY_MODE", ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ "ODM_COMP_TX_PWR_TRACK", ++ "ODM_COMP_RX_GAIN_TRACK", ++ "ODM_COMP_CALIBRATION", ++ NULL, ++ NULL, ++ NULL, ++ "ODM_COMP_COMMON", ++ "ODM_COMP_INIT", ++}; ++ ++#define RTW_ODM_COMP_MAX 32 ++ ++const char *odm_ability_str[] = { ++ "ODM_BB_DIG", ++ "ODM_BB_RA_MASK", ++ "ODM_BB_DYNAMIC_TXPWR", ++ "ODM_BB_FA_CNT", ++ "ODM_BB_RSSI_MONITOR", ++ "ODM_BB_CCK_PD ", ++ "ODM_BB_ANT_DIV", ++ "ODM_BB_PWR_SAVE", ++ "ODM_BB_PWR_TRAIN", ++ "ODM_BB_RATE_ADAPTIVE", ++ "ODM_BB_PATH_DIV", ++ "ODM_BB_PSD", ++ "ODM_BB_RXHP", ++ "ODM_BB_ADAPTIVITY", ++ "ODM_BB_DYNAMIC_ATC", ++ NULL, ++ "ODM_MAC_EDCA_TURBO", ++ "ODM_MAC_EARLY_MODE", ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ "ODM_RF_TX_PWR_TRACK", ++ "ODM_RF_RX_GAIN_TRACK", ++ "ODM_RF_CALIBRATION", ++}; ++ ++#define RTW_ODM_ABILITY_MAX 27 ++ ++const char *odm_dbg_level_str[] = { ++ NULL, ++ "ODM_DBG_OFF", ++ "ODM_DBG_SERIOUS", ++ "ODM_DBG_WARNING", ++ "ODM_DBG_LOUD", ++ "ODM_DBG_TRACE ", ++}; ++ ++#define RTW_ODM_DBG_LEVEL_NUM 6 ++ ++int _rtw_odm_dbg_comp_msg(_adapter *adapter, char *buf, int len) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); ++ DM_ODM_T *odm = &pHalData->odmpriv; ++ int cnt = 0; ++ u64 dbg_comp; ++ int i; ++ ++ rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp); ++ cnt += snprintf(buf+cnt, len-cnt, "odm.DebugComponents = 0x%016llx \n", dbg_comp); ++ for (i=0;iodmpriv; ++ int cnt = 0; ++ u32 dbg_level; ++ int i; ++ ++ rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level); ++ cnt += snprintf(buf+cnt, len-cnt, "odm.DebugDebugLevel = %u\n", dbg_level); ++ for (i=0;iodmpriv; ++ ++ return snprintf(buf, len, ++ "%10s %16s %8s %10s %11s %14s\n" ++ "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n", ++ "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound", ++ (u8)odm->TH_L2H_ini, ++ odm->TH_EDCCA_HL_diff, ++ odm->IGI_Base, ++ odm->ForceEDCCA, ++ odm->AdapEn_RSSI, ++ odm->IGI_LowerBound ++ ); ++} ++ ++void rtw_odm_adaptivity_parm_msg(_adapter *adapter) ++{ ++ char buf[256] = {0}; ++ ++ _rtw_odm_dbg_comp_msg(adapter, buf, 256); ++ DBG_871X_LEVEL(_drv_always_, "\n%s", buf); ++} ++ ++void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, ++ s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); ++ DM_ODM_T *odm = &pHalData->odmpriv; ++ ++ odm->TH_L2H_ini = TH_L2H_ini; ++ odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff; ++ odm->IGI_Base = IGI_Base; ++ odm->ForceEDCCA = ForceEDCCA; ++ odm->AdapEn_RSSI = AdapEn_RSSI; ++ odm->IGI_LowerBound = IGI_LowerBound; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_p2p.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_p2p.c +new file mode 100644 +index 00000000..b9b205ab +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_p2p.c +@@ -0,0 +1,5312 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_P2P_C_ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_P2P ++ ++int rtw_p2p_is_channel_list_ok( u8 desired_ch, u8* ch_list, u8 ch_cnt ) ++{ ++ int found = 0, i = 0; ++ ++ for( i = 0; i < ch_cnt; i++ ) ++ { ++ if ( ch_list[ i ] == desired_ch ) ++ { ++ found = 1; ++ break; ++ } ++ } ++ return( found ); ++} ++ ++int is_any_client_associated(_adapter *padapter) ++{ ++ return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE; ++} ++ ++static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ u32 len=0; ++ u16 attr_len = 0; ++ u8 tmplen, *pdata_attr, *pstart, *pcur; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = pwdinfo->padapter; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); ++ ++ pstart = pdata_attr; ++ pcur = pdata_attr; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //look up sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ ++ if(psta->is_p2p_device) ++ { ++ tmplen = 0; ++ ++ pcur++; ++ ++ //P2P device address ++ _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN); ++ pcur += ETH_ALEN; ++ ++ //P2P interface address ++ _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); ++ pcur += ETH_ALEN; ++ ++ *pcur = psta->dev_cap; ++ pcur++; ++ ++ //*(u16*)(pcur) = cpu_to_be16(psta->config_methods); ++ RTW_PUT_BE16(pcur, psta->config_methods); ++ pcur += 2; ++ ++ _rtw_memcpy(pcur, psta->primary_dev_type, 8); ++ pcur += 8; ++ ++ *pcur = psta->num_of_secdev_type; ++ pcur++; ++ ++ _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type*8); ++ pcur += psta->num_of_secdev_type*8; ++ ++ if(psta->dev_name_len>0) ++ { ++ //*(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME); ++ pcur += 2; ++ ++ //*(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); ++ RTW_PUT_BE16(pcur, psta->dev_name_len); ++ pcur += 2; ++ ++ _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len); ++ pcur += psta->dev_name_len; ++ } ++ ++ ++ tmplen = (u8)(pcur-pstart); ++ ++ *pstart = (tmplen-1); ++ ++ attr_len += tmplen; ++ ++ //pstart += tmplen; ++ pstart = pcur; ++ ++ } ++ ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ if(attr_len>0) ++ { ++ len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr); ++ } ++ ++ rtw_mfree(pdata_attr, MAX_P2P_IE_LEN); ++ ++ return len; ++ ++} ++ ++static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_DISC_REQUEST; ++ u8 dialogToken=0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ //there is no IE in this P2P action frame ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_DEVDISC_RESP; ++ u8 p2pie[8] = { 0x00 }; ++ u32 p2pielen = 0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P public action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //Build P2P IE ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // P2P_ATTR_STATUS ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8* raddr, u8* frame_body, u16 config_method) ++{ ++ _adapter *padapter = pwdinfo->padapter; ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = frame_body[7]; // The Dialog Token of provisioning discovery request frame. ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_RESP; ++ u8 wpsie[ 100 ] = { 0x00 }; ++ u8 wpsielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ wpsielen = 0; ++ // WPS OUI ++ //*(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(wpsie, WPSOUI); ++ wpsielen += 4; ++ ++#if 0 ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++#endif ++ ++ // Config Method ++ // Type: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD); ++ wpsielen += 2; ++ ++ // Length: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ RTW_PUT_BE16(wpsie + wpsielen, 0x0002); ++ wpsielen += 2; ++ ++ // Value: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); ++ RTW_PUT_BE16(wpsie + wpsielen, config_method); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PRESENCE_RESPONSE; ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u8 noa_attr_content[32] = { 0x00 }; ++ u32 p2pielen = 0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //Add P2P IE header ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ //Add Status attribute in P2P IE ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); ++ ++ //Add NoA attribute in P2P IE ++ noa_attr_content[0] = 0x1;//index ++ noa_attr_content[1] = 0x0;//CTWindow and OppPS Parameters ++ ++ //todo: Notice of Absence Descriptor(s) ++ ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content); ++ ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen)); ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u16 capability=0; ++ u32 len=0, p2pielen = 0; ++ ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ ++ // According to the P2P Specification, the beacon frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. P2P Device ID ++ // 3. Notice of Absence ( NOA ) ++ ++ // P2P Capability ATTR ++ // Type: ++ // Length: ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ // Group Capability Bitmap, 1 byte ++ capability = P2P_DEVCAP_INVITATION_PROC|P2P_DEVCAP_CLIENT_DISCOVERABILITY; ++ capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8); ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ capability |= (P2P_GRPCAP_GROUP_FORMATION<<8); ++ ++ capability = cpu_to_le16(capability); ++ ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8*)&capability); ++ ++ ++ // P2P Device ID ATTR ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr); ++ ++ ++ // Notice of Absence ATTR ++ // Type: ++ // Length: ++ // Value: ++ ++ //go_add_noa_attr(pwdinfo); ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++#ifdef CONFIG_WFD ++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the beacon frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ ++ if ( P2P_ROLE_GO == pwdinfo->role ) ++ { ++ if ( is_any_client_associated( pwdinfo->padapter ) ) ++ { ++ // WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD ); ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ } ++ ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ } ++ ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ ++ if ( 1 == pwdinfo->wfd_tdls_enable ) ++ { ++ // WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | ++ WFD_DEVINFO_SESSION_AVAIL | ++ WFD_DEVINFO_WSD | ++ WFD_DEVINFO_PC_TDLS ); ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | ++ WFD_DEVINFO_SESSION_AVAIL | ++ WFD_DEVINFO_WSD ); ++ } ++ ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe response frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ // 4. WFD Session Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ ++ if ( _TRUE == pwdinfo->session_available ) ++ { ++ if ( P2P_ROLE_GO == pwdinfo->role ) ++ { ++ if ( is_any_client_associated( pwdinfo->padapter ) ) ++ { ++ if ( pwdinfo->wfd_tdls_enable ) ++ { ++ // TDLS mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ else ++ { ++ // WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ } ++ else ++ { ++ if ( pwdinfo->wfd_tdls_enable ) ++ { ++ // available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ else ++ { ++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ } ++ } ++ else ++ { ++ if ( pwdinfo->wfd_tdls_enable ) ++ { ++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ else ++ { ++ ++ // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ } ++ } ++ else ++ { ++ if ( pwdinfo->wfd_tdls_enable ) ++ { ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD |WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ else ++ { ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); ++ } ++ ++ } ++ ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ // WFD Session Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000); ++ wfdielen += 2; ++ ++ // Todo: to add the list of WFD device info descriptor in WFD group. ++ ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++#ifdef CONFIG_TDLS ++ if ( ( tunneled == 0 ) && ( padapter->pbuddy_adapter->wdinfo.wfd_tdls_enable == 1 ) ) ++ { ++ // Alternative MAC Address ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ALTER_MAC; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, ETH_ALEN ); ++ wfdielen += 2; ++ ++ // Value: ++ // Alternative MAC Address ++ _rtw_memcpy( wfdie + wfdielen, &padapter->pbuddy_adapter->eeprompriv.mac_addr[ 0 ], ETH_ALEN ); ++ // This mac address is used to make the WFD session when TDLS is enable. ++ ++ wfdielen += ETH_ALEN; ++ } ++#endif // CONFIG_TDLS ++#endif // CONFIG_CONCURRENT_MODE ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = NULL; ++ struct mlme_priv *pmlmepriv = NULL; ++ struct wifi_display_info *pwfd_info = NULL; ++ ++ // WFD OUI ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ return 0; ++ } ++ ++ padapter = pwdinfo->padapter; ++ pmlmepriv = &padapter->mlmepriv; ++ pwfd_info = padapter->wdinfo.wfd_info; ++ ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ if ( P2P_ROLE_GO == pwdinfo->role ) ++ { ++ // WFD Session Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000); ++ wfdielen += 2; ++ ++ // Todo: to add the list of WFD device info descriptor in WFD group. ++ ++ } ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ if ( P2P_ROLE_GO == pwdinfo->role ) ++ { ++ // WFD Session Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000); ++ wfdielen += 2; ++ ++ // Todo: to add the list of WFD device info descriptor in WFD group. ++ ++ } ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD ); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0007); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ // MAC Addr. ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++ ++#endif //CONFIG_WFD ++ ++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++#ifdef CONFIG_INTEL_WIDI ++ struct mlme_priv *pmlmepriv = &(pwdinfo->padapter->mlmepriv); ++ u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 }; ++ u8 widi_version = 0, i = 0; ++ ++ if( _rtw_memcmp( pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN ) == _FALSE ) ++ { ++ widi_version = 35; ++ } ++ else if( pmlmepriv->num_p2p_sdt != 0 ) ++ { ++ widi_version = 40; ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20100907 ++ // According to the P2P Specification, the probe response frame should contain 5 P2P attributes ++ // 1. P2P Capability ++ // 2. Extended Listen Timing ++ // 3. Notice of Absence ( NOA ) ( Only GO needs this ) ++ // 4. Device Info ++ // 5. Group Info ( Only GO need this ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ p2pie[ p2pielen ] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ p2pie[ p2pielen ] |= P2P_GRPCAP_GROUP_FORMATION; ++ ++ p2pielen++; ++ } ++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) ) ++ { ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; ++ else ++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; ++ } ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0004); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); ++ p2pielen += 2; ++ ++ // Availability Interval ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); ++ p2pielen += 2; ++ ++ ++ // Notice of Absence ATTR ++ // Type: ++ // Length: ++ // Value: ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ //go_add_noa_attr(pwdinfo); ++ } ++ ++ // Device Info ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++#ifdef CONFIG_INTEL_WIDI ++ if( widi_version == 35 ) ++ { ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 + pwdinfo->device_name_len); ++ } ++ else if( widi_version == 40 ) ++ { ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 * pmlmepriv->num_p2p_sdt + pwdinfo->device_name_len); ++ } ++ else ++#endif //CONFIG_INTEL_WIDI ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm); ++ p2pielen += 2; ++ ++#ifdef CONFIG_INTEL_WIDI ++ if( widi_version == 40 ) ++ { ++ // Primary Device Type ++ // Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_cid ); ++ p2pielen += 2; ++ ++ // OUI ++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_scid); ++ p2pielen += 2; ++ } ++ else ++#endif //CONFIG_INTEL_WIDI ++ { ++ // Primary Device Type ++ // Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); ++ p2pielen += 2; ++ ++ // OUI ++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); ++ p2pielen += 2; ++ } ++ ++ // Number of Secondary Device Types ++#ifdef CONFIG_INTEL_WIDI ++ if( widi_version == 35 ) ++ { ++ p2pie[ p2pielen++ ] = 0x01; ++ ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_DISPLAYS); ++ p2pielen += 2; ++ ++ RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI); ++ p2pielen += 4; ++ ++ RTW_PUT_BE16(p2pie + p2pielen, P2P_SCID_WIDI_CONSUMER_SINK); ++ p2pielen += 2; ++ } ++ else if( widi_version == 40 ) ++ { ++ p2pie[ p2pielen++ ] = pmlmepriv->num_p2p_sdt; ++ for( ; i < pmlmepriv->num_p2p_sdt; i++ ) ++ { ++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_cid[i]); ++ p2pielen += 2; ++ ++ RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI); ++ p2pielen += 4; ++ ++ RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_scid[i]); ++ p2pielen += 2; ++ } ++ } ++ else ++#endif //CONFIG_INTEL_WIDI ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); ++ p2pielen += 2; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ // Group Info ATTR ++ // Type: ++ // Length: ++ // Value: ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen); ++ } ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110301 ++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Device Info ++ // 3. Group ID ( When joining an operating P2P Group ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; ++ ++ // Group Capability Bitmap, 1 byte ++ if ( pwdinfo->persistent_supported ) ++ p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; ++ else ++ p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; ++ ++ ++ // Device Info ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) ++ { ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC); ++ } ++ else ++ { ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY); ++ } ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); ++ p2pielen += 2; ++ ++ // OUI ++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); ++ p2pielen += 2; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ // Added by Albert 2011/05/19 ++ // In this case, the pdev_raddr is the device address of the group owner. ++ ++ // P2P Group ID ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); ++ RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pdev_raddr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ _rtw_memcpy( p2pie + p2pielen, pssid, ussidlen ); ++ p2pielen += ussidlen; ++ ++ } ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++ ++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // According to the P2P Specification, the Association response frame should contain 2 P2P attributes ++ // 1. Status ++ // 2. Extended Listen Timing (optional) ++ ++ ++ // Status ATTR ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code); ++ ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ // Length: ++ // Value: ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u32 len=0; ++ ++ return len; ++} ++ ++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *p; ++ u32 ret=_FALSE; ++ u8 *p2pie; ++ u32 p2pielen = 0; ++ int ssid_len=0, rate_cnt = 0; ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ if ( rate_cnt <= 4 ) ++ { ++ int i, g_rate =0; ++ ++ for( i = 0; i < rate_cnt; i++ ) ++ { ++ if ( ( ( *( p + 2 + i ) & 0xff ) != 0x02 ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x04 ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x0B ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x16 ) ) ++ { ++ g_rate = 1; ++ } ++ } ++ ++ if ( g_rate == 0 ) ++ { ++ // There is no OFDM rate included in SupportedRates IE of this probe request frame ++ // The driver should response this probe request. ++ return ret; ++ } ++ } ++ else ++ { ++ // rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. ++ // We should proceed the following check for this probe request. ++ } ++ ++ // Added comments by Albert 20100906 ++ // There are several items we should check here. ++ // 1. This probe request frame must contain the P2P IE. (Done) ++ // 2. This probe request frame must contain the wildcard SSID. (Done) ++ // 3. Wildcard BSSID. (Todo) ++ // 4. Destination Address. ( Done in mgt_dispatcher function ) ++ // 5. Requested Device Type in WSC IE. (Todo) ++ // 6. Device ID attribute in P2P IE. (Todo) ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ ssid_len &= 0xff; // Just last 1 byte is valid for ssid len of the probe request ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if((p2pie=rtw_get_p2p_ie( pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen))) ++ { ++ if ( (p != NULL) && _rtw_memcmp( ( void * ) ( p+2 ), ( void * ) pwdinfo->p2p_wildcard_ssid , 7 )) ++ { ++ //todo: ++ //Check Requested Device Type attributes in WSC IE. ++ //Check Device ID attribute in P2P IE ++ ++ ret = _TRUE; ++ } ++ else if ( (p != NULL) && ( ssid_len == 0 ) ) ++ { ++ ret = _TRUE; ++ } ++ } ++ else ++ { ++ //non -p2p device ++ } ++ ++ } ++ ++ ++ return ret; ++ ++} ++ ++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta) ++{ ++ u8 status_code = P2P_STATUS_SUCCESS; ++ u8 *pbuf, *pattr_content=NULL; ++ u32 attr_contentlen = 0; ++ u16 cap_attr=0; ++ unsigned short frame_type, ie_offset=0; ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ ++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ return P2P_STATUS_FAIL_REQUEST_UNABLE; ++ ++ frame_type = GetFrameSubType(pframe); ++ if (frame_type == WIFI_ASSOCREQ) ++ { ++ ie_offset = _ASOCREQ_IE_OFFSET_; ++ } ++ else // WIFI_REASSOCREQ ++ { ++ ie_offset = _REASOCREQ_IE_OFFSET_; ++ } ++ ++ ies = pframe + WLAN_HDR_A3_LEN + ie_offset; ++ ies_len = len - WLAN_HDR_A3_LEN - ie_offset; ++ ++ p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); ++ ++ if ( !p2p_ie ) ++ { ++ DBG_8192C( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); ++ status_code = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ else ++ { ++ DBG_8192C( "[%s] P2P IE Found!!\n", __FUNCTION__ ); ++ } ++ ++ while ( p2p_ie ) ++ { ++ //Check P2P Capability ATTR ++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); ++ cap_attr = le16_to_cpu(cap_attr); ++ psta->dev_cap = cap_attr&0xff; ++ } ++ ++ //Check Extended Listen Timing ATTR ++ ++ ++ //Check P2P Device Info ATTR ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint*)&attr_contentlen)) ++ { ++ DBG_8192C( "[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__ ); ++ pattr_content = pbuf = rtw_zmalloc(attr_contentlen); ++ if(pattr_content) ++ { ++ u8 num_of_secdev_type; ++ u16 dev_name_len; ++ ++ ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint*)&attr_contentlen); ++ ++ _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address ++ ++ pattr_content += ETH_ALEN; ++ ++ _rtw_memcpy(&psta->config_methods, pattr_content, 2);//Config Methods ++ psta->config_methods = be16_to_cpu(psta->config_methods); ++ ++ pattr_content += 2; ++ ++ _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); ++ ++ pattr_content += 8; ++ ++ num_of_secdev_type = *pattr_content; ++ pattr_content += 1; ++ ++ if(num_of_secdev_type==0) ++ { ++ psta->num_of_secdev_type = 0; ++ } ++ else ++ { ++ u32 len; ++ ++ psta->num_of_secdev_type = num_of_secdev_type; ++ ++ len = (sizeof(psta->secdev_types_list)<(num_of_secdev_type*8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type*8); ++ ++ _rtw_memcpy(psta->secdev_types_list, pattr_content, len); ++ ++ pattr_content += (num_of_secdev_type*8); ++ } ++ ++ ++ //dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); ++ psta->dev_name_len=0; ++ if(WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16*)pattr_content)) ++ { ++ dev_name_len = be16_to_cpu(*(u16*)(pattr_content+2)); ++ ++ psta->dev_name_len = (sizeof(psta->dev_name)dev_name):dev_name_len; ++ ++ _rtw_memcpy(psta->dev_name, pattr_content+4, psta->dev_name_len); ++ } ++ ++ rtw_mfree(pbuf, attr_contentlen); ++ ++ } ++ ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ return status_code; ++ ++} ++ ++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *frame_body; ++ u8 status, dialogToken; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = pwdinfo->padapter; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *p2p_ie; ++ u32 p2p_ielen = 0; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ dialogToken = frame_body[7]; ++ status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; ++ ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ u8 groupid[ 38 ] = { 0x00 }; ++ u8 dev_addr[ETH_ALEN] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) ++ { ++ if(_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) && ++ _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid+ETH_ALEN, pwdinfo->p2p_group_ssid_len)) ++ { ++ attr_contentlen=0; ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) ++ { ++ _irqL irqL; ++ _list *phead, *plist; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //look up sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ if(psta->is_p2p_device && (psta->dev_cap&P2P_DEVCAP_CLIENT_DISCOVERABILITY) && ++ _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) ++ { ++ ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ //issue GO Discoverability Request ++ issue_group_disc_req(pwdinfo, psta->hwaddr); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ status = P2P_STATUS_SUCCESS; ++ ++ break; ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ ++ } ++ ++ } ++ ++ ++ //issue Device Discoverability Response ++ issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); ++ ++ ++ return (status==P2P_STATUS_SUCCESS) ? _TRUE:_FALSE; ++ ++} ++ ++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ return _TRUE; ++} ++ ++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 *frame_body; ++ u8 *wpsie; ++ uint wps_ielen = 0, attr_contentlen = 0; ++ u16 uconfig_method = 0; ++ ++ ++ frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ if ( (wpsie=rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) ++ { ++ if ( rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , ( u8* ) &uconfig_method, &attr_contentlen) ) ++ { ++ uconfig_method = be16_to_cpu( uconfig_method ); ++ switch( uconfig_method ) ++ { ++ case WPS_CM_DISPLYA: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ break; ++ } ++ case WPS_CM_LABEL: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3 ); ++ break; ++ } ++ case WPS_CM_PUSH_BUTTON: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ break; ++ } ++ case WPS_CM_KEYPAD: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ break; ++ } ++ } ++ issue_p2p_provision_resp( pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method); ++ } ++ } ++ DBG_871X( "[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); ++ return _TRUE; ++ ++} ++ ++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe) ++{ ++ ++ return _TRUE; ++} ++ ++u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list) ++{ ++ u8 i = 0, j = 0; ++ u8 temp = 0; ++ u8 ch_no = 0; ++ ch_content += 3; ++ ch_cnt -= 3; ++ ++ while( ch_cnt > 0) ++ { ++ ch_content += 1; ++ ch_cnt -= 1; ++ temp = *ch_content; ++ for( i = 0 ; i < temp ; i++, j++ ) ++ { ++ peer_ch_list[j] = *( ch_content + 1 + i ); ++ } ++ ch_content += (temp + 1); ++ ch_cnt -= (temp + 1); ++ ch_no += temp ; ++ } ++ ++ return ch_no; ++} ++ ++u8 rtw_p2p_check_peer_oper_ch(struct mlme_ext_priv *pmlmeext, u8 ch) ++{ ++ u8 i = 0; ++ ++ for( i = 0; i < pmlmeext->max_chan_nums; i++ ) ++ { ++ if ( pmlmeext->channel_set[ i ].ChannelNum == ch ) ++ { ++ return _SUCCESS; ++ } ++ } ++ ++ return _FAIL; ++} ++ ++u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) ++{ ++ int i = 0, j = 0, temp = 0; ++ u8 ch_no = 0; ++ ++ for( i = 0; i < peer_ch_num; i++ ) ++ { ++ for( j = temp; j < pmlmeext->max_chan_nums; j++ ) ++ { ++ if( *( peer_ch_list + i ) == pmlmeext->channel_set[ j ].ChannelNum ) ++ { ++ ch_list_inclusioned[ ch_no++ ] = *( peer_ch_list + i ); ++ temp = j; ++ break; ++ } ++ } ++ } ++ ++ return ch_no; ++} ++ ++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ _adapter *padapter = pwdinfo->padapter; ++ u8 result = P2P_STATUS_SUCCESS; ++ u32 p2p_ielen = 0, wps_ielen = 0; ++ u8 * ies; ++ u32 ies_len; ++ u8 *p2p_ie; ++ u8 *wpsie; ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++#endif // CONFIG_TDLS ++#endif // CONFIG_WFD ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = pwdinfo->padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif ++ ++ if ( (wpsie=rtw_get_wps_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) ++ { ++ // Commented by Kurt 20120113 ++ // If some device wants to do p2p handshake without sending prov_disc_req ++ // We have to get peer_req_cm from here. ++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) ++ { ++ rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ } ++ else ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ } ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ return( result ); ++ } ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO ) ++ { ++ result = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY); ++ return( result ); ++ } ++ ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ if ( !p2p_ie ) ++ { ++ DBG_871X( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ ++ while ( p2p_ie ) ++ { ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ u8 ch_content[100] = { 0x00 }; ++ uint ch_cnt = 0; ++ u8 peer_ch_list[100] = { 0x00 }; ++ u8 peer_ch_num = 0; ++ u8 ch_list_inclusioned[100] = { 0x00 }; ++ u8 ch_num_inclusioned = 0; ++ u16 cap_attr; ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); ++ ++ //Check P2P Capability ATTR ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) ) ++ { ++ cap_attr = le16_to_cpu(cap_attr); ++ ++#if defined(CONFIG_WFD) && defined(CONFIG_TDLS) ++ if(!(cap_attr & P2P_GRPCAP_INTRABSS) ) ++ ptdlsinfo->ap_prohibited = _TRUE; ++#endif //defined(CONFIG_WFD) && defined(CONFIG_TDLS) ++ } ++ ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) ++ { ++ DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); ++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. ++ ++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ // Try to match the tie breaker value ++ if ( pwdinfo->intent == P2P_MAX_INTENT ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; ++ } ++ else ++ { ++ if ( attr_content & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ } ++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ // Store the group id information. ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ } ++ } ++ ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) ++ { ++ if ( attr_contentlen != ETH_ALEN ) ++ { ++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); ++ } ++ } ++ ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt) ) ++ { ++ peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); ++ ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); ++ ++ if( ch_num_inclusioned == 0) ++ { ++ DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_NO_COMMON_CH; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel, ++ ch_list_inclusioned, ch_num_inclusioned) ) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_NO_COMMON_CH; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; ++ attr_contentlen = 0; ++ ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) ++ { ++ peer_operating_ch = operatingch_info[4]; ++ } ++ ++ if ( rtw_p2p_is_channel_list_ok( peer_operating_ch, ++ ch_list_inclusioned, ch_num_inclusioned) ) ++ { ++ /** ++ * Change our operating channel as peer's for compatibility. ++ */ ++ pwdinfo->operating_channel = peer_operating_ch; ++ DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); ++ } ++ else ++ { ++ // Take first channel of ch_list_inclusioned as operating channel ++ pwdinfo->operating_channel = ch_list_inclusioned[0]; ++ DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); ++ } ++ } ++ ++ } ++ } ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++ ++#ifdef CONFIG_WFD ++ // Added by Albert 20110823 ++ // Try to get the TCP port information when receiving the negotiation request. ++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_871X( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_871X( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ } ++ } ++#endif // CONFIG_WFD ++ ++ return( result ); ++} ++ ++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ _adapter *padapter = pwdinfo->padapter; ++ u8 result = P2P_STATUS_SUCCESS; ++ u32 p2p_ielen, wps_ielen; ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++#endif // CONFIG_TDLS ++#endif // CONFIG_WFD ++ ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ // Be able to know which one is the P2P GO and which one is P2P client. ++ ++ if ( rtw_get_wps_ie( ies, ies_len, NULL, &wps_ielen) ) ++ { ++ ++ } ++ else ++ { ++ DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ if ( !p2p_ie ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ } ++ else ++ { ++ ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ u8 operatingch_info[5] = { 0x00 }; ++ uint ch_cnt = 0; ++ u8 ch_content[100] = { 0x00 }; ++ u8 groupid[ 38 ]; ++ u16 cap_attr; ++ u8 peer_ch_list[100] = { 0x00 }; ++ u8 peer_ch_num = 0; ++ u8 ch_list_inclusioned[100] = { 0x00 }; ++ u8 ch_num_inclusioned = 0; ++ ++ while ( p2p_ie ) // Found the P2P IE. ++ { ++ ++ //Check P2P Capability ATTR ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) ) ++ { ++ cap_attr = le16_to_cpu(cap_attr); ++#ifdef CONFIG_TDLS ++ if(!(cap_attr & P2P_GRPCAP_INTRABSS) ) ++ ptdlsinfo->ap_prohibited = _TRUE; ++#endif // CONFIG_TDLS ++ } ++ ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ // Do nothing. ++ } ++ else ++ { ++ if ( P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content ) { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY); ++ } else { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ result = attr_content; ++ break; ++ } ++ } ++ ++ // Try to get the peer's interface address ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) ++ { ++ if ( attr_contentlen != ETH_ALEN ) ++ { ++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); ++ } ++ } ++ ++ // Try to get the peer's intent and tie breaker value. ++ attr_content = 0x00; ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) ++ { ++ DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); ++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. ++ ++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ // Try to match the tie breaker value ++ if ( pwdinfo->intent == P2P_MAX_INTENT ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ else ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ if ( attr_content & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ } ++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ // Store the group id information. ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ ++ } ++ } ++ ++ // Try to get the operation channel information ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) ++ { ++ DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); ++ pwdinfo->peer_operating_ch = operatingch_info[4]; ++ } ++ ++ // Try to get the channel list information ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len ) ) ++ { ++ DBG_871X( "[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len ); ++ ++ peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); ++ ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); ++ ++ if( ch_num_inclusioned == 0) ++ { ++ DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_NO_COMMON_CH; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel, ++ ch_list_inclusioned, ch_num_inclusioned) ) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_NO_COMMON_CH; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; ++ attr_contentlen = 0; ++ ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) ++ { ++ peer_operating_ch = operatingch_info[4]; ++ } ++ ++ if ( rtw_p2p_is_channel_list_ok( peer_operating_ch, ++ ch_list_inclusioned, ch_num_inclusioned) ) ++ { ++ /** ++ * Change our operating channel as peer's for compatibility. ++ */ ++ pwdinfo->operating_channel = peer_operating_ch; ++ DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); ++ } ++ else ++ { ++ // Take first channel of ch_list_inclusioned as operating channel ++ pwdinfo->operating_channel = ch_list_inclusioned[0]; ++ DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); ++ } ++ } ++ ++ } ++ } ++ ++ } ++ else ++ { ++ DBG_871X( "[%s] channel list attribute not found!\n", __FUNCTION__); ++ } ++ ++ // Try to get the group id information if peer is GO ++ attr_contentlen = 0; ++ _rtw_memset( groupid, 0x00, 38 ); ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) ++ { ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++ ++ } ++ ++#ifdef CONFIG_WFD ++ // Added by Albert 20111122 ++ // Try to get the TCP port information when receiving the negotiation response. ++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ } ++ } ++#endif // CONFIG_WFD ++ ++ return( result ); ++ ++} ++ ++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ u8 result = P2P_STATUS_SUCCESS; ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ while ( p2p_ie ) // Found the P2P IE. ++ { ++ u8 attr_content = 0x00, operatingch_info[5] = { 0x00 }; ++ u8 groupid[ 38 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ pwdinfo->negotiation_dialog_token = 1; ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ result = attr_content; ++ ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ u8 bcancelled = 0; ++ ++ _cancel_timer( &pwdinfo->restore_p2p_state_timer, &bcancelled ); ++ ++ // Commented by Albert 20100911 ++ // Todo: Need to handle the case which both Intents are the same. ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ if ( ( pwdinfo->intent ) > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else if ( ( pwdinfo->intent ) < ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ // Have to compare the Tie Breaker ++ if ( pwdinfo->peer_intent & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(pwdinfo->padapter , _FW_LINKED ) ) ++ { ++ // Switch back to the AP channel soon. ++ _set_timer( &pwdinfo->ap_p2p_switch_timer, 100 ); ++ } ++#endif ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ } ++ ++ // Try to get the group id information ++ attr_contentlen = 0; ++ _rtw_memset( groupid, 0x00, 38 ); ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) ++ { ++ DBG_871X( "[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]) ); ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); ++ } ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) ++ { ++ DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); ++ pwdinfo->peer_operating_ch = operatingch_info[4]; ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ return( result ); ++} ++ ++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *frame_body; ++ u8 dialogToken=0; ++ u8 status = P2P_STATUS_SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ dialogToken = frame_body[6]; ++ ++ //todo: check NoA attribute ++ ++ issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); ++ ++ return _TRUE; ++} ++ ++void find_phase_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid; ++ _irqL irqL; ++ u8 _status = 0; ++ ++_func_enter_; ++ ++ _rtw_memset((unsigned char*)&ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); ++ ssid.SsidLength = P2P_WILDCARD_SSID_LEN; ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++_func_exit_; ++} ++ ++void p2p_concurrent_handler( _adapter* padapter ); ++ ++void restore_p2p_state_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) ++ { ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); ++ } ++ } ++#endif ++ ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ p2p_concurrent_handler( padapter ); ++#else ++ // In the P2P client mode, the driver should not switch back to its listen channel ++ // because this P2P client should stay at the operating channel of P2P GO. ++ set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++#endif ++ } ++_func_exit_; ++} ++ ++void pre_tx_invitereq_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ u8 val8 = 1; ++_func_enter_; ++ ++ set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++_func_exit_; ++} ++ ++void pre_tx_provdisc_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ u8 val8 = 1; ++_func_enter_; ++ ++ set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++_func_exit_; ++} ++ ++void pre_tx_negoreq_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ u8 val8 = 1; ++_func_enter_; ++ ++ set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_CONCURRENT_MODE ++void p2p_concurrent_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ //_adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ //struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ //struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ u8 val8; ++_func_enter_; ++ ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel; ++ ++ if( pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ DBG_871X("%s, switch ch back to buddy's cur_channel=%d\n", __func__, pbuddy_mlmeext->cur_channel); ++ ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); ++ } ++ else if( pwdinfo->driver_interface == DRIVER_WEXT ) ++ { ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ // Now, the driver stays on the AP's channel. ++ // If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. ++ if ( pwdinfo->ext_listen_period > 0 ) ++ { ++ DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period ); ++ ++ if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel ) ++ { ++ // Will switch to listen channel so that need to send the NULL data with PW bit to AP. ++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ val8 = 1; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ // Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. ++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period ); ++ } ++ } ++ else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) || ++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) || ++ ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE ) || ++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ) ) ++ { ++ // Now, the driver is in the listen state of P2P mode. ++ DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval ); ++ ++ // Commented by Albert 2012/11/01 ++ // If the AP's channel is the same as the listen channel, we should still be in the listen state ++ // Other P2P device is still able to find this device out even this device is in the AP's channel. ++ // So, configure this device to be able to receive the probe request frame and set it to listen state. ++ if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel ) ++ { ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ val8 = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); ++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); ++ } ++ ++ // Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. ++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval ); ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) ++ { ++ // The driver had finished the P2P handshake successfully. ++ val8 = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ val8 = 1; ++ set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) ++ { ++ val8 = 1; ++ set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) && pwdinfo->invitereq_info.benable == _TRUE) ++ { ++ /* ++ val8 = 1; ++ set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p(padapter, NULL); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ */ ++ } ++ } ++ } ++ else ++ { ++ set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++_func_exit_; ++} ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++static void ro_ch_handler(_adapter *padapter) ++{ ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ u8 ch, bw, offset; ++_func_enter_; ++ ++ if (rtw_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" back to linked union - ch:%u, bw:%u, offset:%u\n", ++ FUNC_ADPT_ARG(padapter), ch, bw, offset); ++ } ++ else if (wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && pwdinfo->listen_channel) { ++ ch = pwdinfo->listen_channel; ++ bw = HT_CHANNEL_WIDTH_20; ++ offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n", ++ FUNC_ADPT_ARG(padapter), ch, bw, offset); ++ } ++ else { ++ ch = pcfg80211_wdinfo->restore_channel; ++ bw = HT_CHANNEL_WIDTH_20; ++ offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ if (0) ++ DBG_871X(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n", ++ FUNC_ADPT_ARG(padapter), ch, bw, offset); ++ } ++ ++ set_channel_bwmode(padapter, ch, offset, bw); ++ ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ ++ pcfg80211_wdinfo->is_ro_ch = _FALSE; ++ ++ DBG_871X("cfg80211_remain_on_channel_expired\n"); ++ ++ rtw_cfg80211_remain_on_channel_expired(padapter, ++ pcfg80211_wdinfo->remain_on_ch_cookie, ++ &pcfg80211_wdinfo->remain_on_ch_channel, ++ pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL); ++ ++_func_exit_; ++} ++ ++static void ro_ch_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev); ++ ++ //printk("%s \n", __FUNCTION__); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); ++#endif ++ ++ p2p_protocol_wk_cmd( adapter, P2P_RO_CH_WK); ++} ++ ++static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) ++{ ++ u8 *ies, *p2p_ie; ++ u32 ies_len, p2p_ielen; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ while ( p2p_ie ) { ++ u32 attr_contentlen = 0; ++ u8 *pattr = NULL; ++ ++ //Check P2P_ATTR_OPERATING_CH ++ attr_contentlen = 0; ++ pattr = NULL; ++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) ++ { ++ *(pattr+4) = ch; ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++} ++ ++static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) ++{ ++ u8 *ies, *p2p_ie; ++ u32 ies_len, p2p_ielen; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ while (p2p_ie) { ++ u32 attr_contentlen = 0; ++ u8 *pattr = NULL; ++ ++ //Check P2P_ATTR_CH_LIST ++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) { ++ int i; ++ u32 num_of_ch; ++ u8 *pattr_temp = pattr + 3 ; ++ ++ attr_contentlen -= 3; ++ ++ while (attr_contentlen>0) { ++ num_of_ch = *(pattr_temp+1); ++ ++ for(i=0; ipbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ u8 buddy_ch = pbuddy_mlmeext->cur_channel; ++ ++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ while (p2p_ie) { ++ u32 attr_contentlen = 0; ++ u8 *pattr = NULL; ++ ++ //Check P2P_ATTR_CH_LIST ++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) { ++ int i; ++ u32 num_of_ch; ++ u8 *pattr_temp = pattr + 3 ; ++ ++ attr_contentlen -= 3; ++ ++ while (attr_contentlen>0) { ++ num_of_ch = *(pattr_temp+1); ++ ++ for(i=0; ipbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ u8 buddy_ch = pbuddy_mlmeext->cur_channel; ++ ++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ while (p2p_ie) { ++ u32 attr_contentlen = 0; ++ u8 *pattr = NULL; ++ ++ //Check P2P_ATTR_OPERATING_CH ++ attr_contentlen = 0; ++ pattr = NULL; ++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) { ++ if (*(pattr+4) == buddy_ch) { ++ DBG_871X(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), buddy_ch); ++ fit = _TRUE; ++ break; ++ } ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++#endif ++ return fit; ++} ++ ++static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 *ies, *p2p_ie; ++ u32 ies_len, p2p_ielen; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ while ( p2p_ie ) ++ { ++ u32 attr_contentlen = 0; ++ u8 *pattr = NULL; ++ ++ //Check P2P_ATTR_CH_LIST ++ if((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) ++ { ++ int i; ++ u32 num_of_ch; ++ u8 *pattr_temp = pattr + 3 ; ++ ++ attr_contentlen -= 3; ++ ++ while(attr_contentlen>0) ++ { ++ num_of_ch = *(pattr_temp+1); ++ ++ for(i=0; icur_channel;//forcing to the same channel ++ ++ pattr_temp += (2+num_of_ch); ++ attr_contentlen -= (2+num_of_ch); ++ } ++ } ++ ++ //Check P2P_ATTR_OPERATING_CH ++ attr_contentlen = 0; ++ pattr = NULL; ++ if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) ++ { ++ *(pattr+4) = pbuddy_mlmeext->cur_channel;//forcing to the same channel ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++#endif ++} ++ ++#ifdef CONFIG_WFD ++void rtw_append_wfd_ie(_adapter *padapter, u8 *buf, u32* len) ++{ ++ unsigned char *frame_body; ++ u8 category, action, OUI_Subtype, dialogToken=0; ++ u32 wfdielen = 0; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ category = frame_body[0]; ++ ++ if(category == RTW_WLAN_CATEGORY_PUBLIC) ++ { ++ action = frame_body[1]; ++ if (action == ACT_PUBLIC_VENDOR ++ && _rtw_memcmp(frame_body+2, P2P_OUI, 4) == _TRUE ++ ) ++ { ++ OUI_Subtype = frame_body[6]; ++ dialogToken = frame_body[7]; ++ switch( OUI_Subtype )//OUI Subtype ++ { ++ case P2P_GO_NEGO_REQ: ++ { ++ wfdielen = build_nego_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_GO_NEGO_RESP: ++ { ++ wfdielen = build_nego_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_GO_NEGO_CONF: ++ { ++ wfdielen = build_nego_confirm_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_INVIT_REQ: ++ { ++ wfdielen = build_invitation_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_INVIT_RESP: ++ { ++ wfdielen = build_invitation_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_DEVDISC_REQ: ++ break; ++ case P2P_DEVDISC_RESP: ++ ++ break; ++ case P2P_PROVISION_DISC_REQ: ++ { ++ wfdielen = build_provdisc_req_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ case P2P_PROVISION_DISC_RESP: ++ { ++ wfdielen = build_provdisc_resp_wfd_ie( &padapter->wdinfo, buf + ( *len ) ); ++ (*len) += wfdielen; ++ break; ++ } ++ default: ++ ++ break; ++ } ++ ++ } ++ ++ } ++ else if(category == RTW_WLAN_CATEGORY_P2P) ++ { ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); ++#endif ++ ++ switch(OUI_Subtype) ++ { ++ case P2P_NOTICE_OF_ABSENCE: ++ ++ break; ++ case P2P_PRESENCE_REQUEST: ++ ++ break; ++ case P2P_PRESENCE_RESPONSE: ++ ++ break; ++ case P2P_GO_DISC_REQUEST: ++ ++ break; ++ default: ++ ++ break; ++ } ++ ++ } ++ else ++ { ++ DBG_871X("%s, action frame category=%d\n", __func__, category); ++ //is_p2p_frame = (-1); ++ } ++ ++ return; ++} ++#endif ++ ++u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len) ++{ ++ uint attr_contentlen = 0; ++ u8 *pattr = NULL; ++ int w_sz = 0; ++ u8 ch_cnt = 0; ++ u8 ch_list[40]; ++ bool continuous = _FALSE; ++ ++ if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen))!=NULL) { ++ int i, j; ++ u32 num_of_ch; ++ u8 *pattr_temp = pattr + 3 ; ++ ++ attr_contentlen -= 3; ++ ++ _rtw_memset(ch_list, 0, 40); ++ ++ while (attr_contentlen>0) { ++ num_of_ch = *(pattr_temp+1); ++ ++ for(i=0; i=ch_cnt) ++ ch_list[ch_cnt++] = *(pattr_temp+2+i); ++ ++ } ++ ++ pattr_temp += (2+num_of_ch); ++ attr_contentlen -= (2+num_of_ch); ++ } ++ ++ for (j=0;j>1 == resp >>1) ++ return req&0x01 ? _TRUE : _FALSE; ++ else if (req>>1 > resp>>1) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) ++{ ++ int is_p2p_frame = (-1); ++ unsigned char *frame_body; ++ u8 category, action, OUI_Subtype, dialogToken=0; ++ u8 *p2p_ie = NULL; ++ uint p2p_ielen = 0; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ int status = -1; ++ u8 ch_list_buf[128] = {'\0'}; ++ int op_ch = -1; ++ int listen_ch = -1; ++ u8 intent = 0; ++ ++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ category = frame_body[0]; ++ //just for check ++ if(category == RTW_WLAN_CATEGORY_PUBLIC) ++ { ++ action = frame_body[1]; ++ if (action == ACT_PUBLIC_VENDOR ++ && _rtw_memcmp(frame_body+2, P2P_OUI, 4) == _TRUE ++ ) ++ { ++ OUI_Subtype = frame_body[6]; ++ dialogToken = frame_body[7]; ++ is_p2p_frame = OUI_Subtype; ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ #endif ++ ++ p2p_ie = rtw_get_p2p_ie( ++ (u8 *)buf+sizeof(struct rtw_ieee80211_hdr_3addr)+_PUBLIC_ACTION_IE_OFFSET_, ++ len-sizeof(struct rtw_ieee80211_hdr_3addr)-_PUBLIC_ACTION_IE_OFFSET_, ++ NULL, &p2p_ielen); ++ ++ switch( OUI_Subtype )//OUI Subtype ++ { ++ u8 *cont; ++ uint cont_len; ++ case P2P_GO_NEGO_REQ: ++ { ++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; ++ ++ if (tx) { ++ #ifdef CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2 ++ if(pwdev_priv->provdisc_req_issued == _FALSE) ++ rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); ++ #endif //CONFIG_DRV_ISSUE_PROV_REQ ++ ++ //pwdev_priv->provdisc_req_issued = _FALSE; ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ #endif ++ } ++ ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) ++ op_ch = *(cont+4); ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len))) ++ listen_ch = *(cont+4); ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len))) ++ intent = *cont; ++ ++ if (nego_info->token != dialogToken) ++ rtw_wdev_nego_info_init(nego_info); ++ ++ _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); ++ nego_info->active = tx ? 1 : 0; ++ nego_info->token = dialogToken; ++ nego_info->req_op_ch = op_ch; ++ nego_info->req_listen_ch = listen_ch; ++ nego_info->req_intent = intent; ++ nego_info->state = 0; ++ ++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); ++ DBG_871X("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s\n", ++ (tx==_TRUE)?"Tx":"Rx", dialogToken, (intent>>1), intent&0x1 ? "+" : "-", listen_ch, op_ch, ch_list_buf); ++ ++ if (!tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if((check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) ++ { ++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); ++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); ++ } ++ #endif ++ } ++ ++ break; ++ } ++ case P2P_GO_NEGO_RESP: ++ { ++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; ++ ++ if (tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ #endif ++ } ++ ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) ++ op_ch = *(cont+4); ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len))) ++ intent = *cont; ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) ++ status = *cont; ++ ++ if (nego_info->token == dialogToken && nego_info->state == 0 ++ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE ++ ) { ++ nego_info->status = (status==-1) ? 0xff : status; ++ nego_info->rsp_op_ch= op_ch; ++ nego_info->rsp_intent = intent; ++ nego_info->state = 1; ++ if (status != 0) ++ nego_info->token = 0; /* init */ ++ } ++ ++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); ++ DBG_871X("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\n", ++ (tx==_TRUE)?"Tx":"Rx", dialogToken, (intent>>1), intent&0x1 ? "+" : "-", status, op_ch, ch_list_buf); ++ ++ if (!tx) { ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ #ifdef CONFIG_CONCURRENT_MODE ++ if((check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) ++ { ++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); ++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); ++ } ++ #endif ++ } ++ ++ break; ++ } ++ case P2P_GO_NEGO_CONF: ++ { ++ struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; ++ bool is_go = _FALSE; ++ ++ if (tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ #endif ++ } ++ ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) ++ op_ch = *(cont+4); ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) ++ status = *cont; ++ ++ if (nego_info->token == dialogToken && nego_info->state == 1 ++ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE ++ ) { ++ nego_info->status = (status==-1) ? 0xff : status; ++ nego_info->conf_op_ch = (op_ch==-1) ? 0 : op_ch; ++ nego_info->state = 2; ++ ++ if (status == 0) { ++ if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) && tx) ++ is_go = _TRUE; ++ } ++ ++ nego_info->token = 0; /* init */ ++ } ++ ++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); ++ DBG_871X("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", ++ (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf); ++ ++ if (!tx) { ++ } ++ ++ break; ++ } ++ case P2P_INVIT_REQ: ++ { ++ struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info; ++ int flags = -1; ++ ++ if (tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ #endif ++ } ++ ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len))) ++ flags = *cont; ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) ++ op_ch = *(cont+4); ++ ++ if (invit_info->token != dialogToken) ++ rtw_wdev_invit_info_init(invit_info); ++ ++ _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); ++ invit_info->active = tx ? 1 : 0; ++ invit_info->token = dialogToken; ++ invit_info->flags = (flags==-1) ? 0x0 : flags; ++ invit_info->req_op_ch= op_ch; ++ invit_info->state = 0; ++ ++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); ++ DBG_871X("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\n", ++ (tx==_TRUE)?"Tx":"Rx", dialogToken, flags, op_ch, ch_list_buf); ++ ++ if (!tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) { ++ if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { ++ DBG_871X(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch); ++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); ++ } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { ++ DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); ++ rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); ++ } ++ } ++ #endif ++ } ++ ++ break; ++ } ++ case P2P_INVIT_RESP: ++ { ++ struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info; ++ ++ if (tx) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) ++ || check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ #endif ++ } ++ ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) ++ { ++#ifdef CONFIG_P2P_INVITE_IOT ++ if(tx && *cont==7) ++ { ++ DBG_871X("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n"); ++ *cont = 8; //unknow group status ++ } ++#endif //CONFIG_P2P_INVITE_IOT ++ status = *cont; ++ } ++ if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) ++ op_ch = *(cont+4); ++ ++ if (invit_info->token == dialogToken && invit_info->state == 0 ++ && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE ++ ) { ++ invit_info->status = (status==-1) ? 0xff : status; ++ invit_info->rsp_op_ch= op_ch; ++ invit_info->state = 1; ++ invit_info->token = 0; /* init */ ++ } ++ ++ dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); ++ DBG_871X("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", ++ (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf); ++ ++ if (!tx) { ++ } ++ ++ break; ++ } ++ case P2P_DEVDISC_REQ: ++ DBG_871X("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_DEVDISC_RESP: ++ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len); ++ DBG_871X("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken, cont?*cont:-1); ++ break; ++ case P2P_PROVISION_DISC_REQ: ++ { ++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ u8 *p2p_ie; ++ uint p2p_ielen = 0; ++ uint contentlen = 0; ++ ++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ ++ //if(tx) ++ { ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ ++ if( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen))) ++ { ++ ++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) ++ { ++ pwdev_priv->provdisc_req_issued = _FALSE;//case: p2p_client join p2p GO ++ } ++ else ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("provdisc_req_issued is _TRUE\n"); ++ #endif //CONFIG_DEBUG_CFG80211 ++ pwdev_priv->provdisc_req_issued = _TRUE;//case: p2p_devices connection before Nego req. ++ } ++ ++ } ++ } ++ } ++ break; ++ case P2P_PROVISION_DISC_RESP: ++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ default: ++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", OUI_Subtype, dialogToken); ++ break; ++ } ++ ++ } ++ ++ } ++ else if(category == RTW_WLAN_CATEGORY_P2P) ++ { ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); ++ #endif ++ ++ is_p2p_frame = OUI_Subtype; ++ ++ switch(OUI_Subtype) ++ { ++ case P2P_NOTICE_OF_ABSENCE: ++ DBG_871X("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_PRESENCE_REQUEST: ++ DBG_871X("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_PRESENCE_RESPONSE: ++ DBG_871X("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_GO_DISC_REQUEST: ++ DBG_871X("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ default: ++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", OUI_Subtype, dialogToken); ++ break; ++ } ++ ++ } ++ else ++ { ++ DBG_871X("RTW_%s:action frame category=%d\n", (tx==_TRUE)?"TX":"RX", category); ++ } ++ ++ return is_p2p_frame; ++} ++ ++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter) ++{ ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ ++ _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info) ); ++ ++ _init_timer( &pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter ); ++} ++#endif //CONFIG_IOCTL_CFG80211 ++ ++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) ++{ ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++_func_enter_; ++ ++ switch(intCmdType) ++ { ++ case P2P_FIND_PHASE_WK: ++ { ++ find_phase_handler( padapter ); ++ break; ++ } ++ case P2P_RESTORE_STATE_WK: ++ { ++ restore_p2p_state_handler( padapter ); ++ break; ++ } ++ case P2P_PRE_TX_PROVDISC_PROCESS_WK: ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ p2p_concurrent_handler( padapter ); ++ } ++ else ++ { ++ pre_tx_provdisc_handler( padapter ); ++ } ++#else ++ pre_tx_provdisc_handler( padapter ); ++#endif ++ break; ++ } ++ case P2P_PRE_TX_INVITEREQ_PROCESS_WK: ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ p2p_concurrent_handler( padapter ); ++ } ++ else ++ { ++ pre_tx_invitereq_handler( padapter ); ++ } ++#else ++ pre_tx_invitereq_handler( padapter ); ++#endif ++ break; ++ } ++ case P2P_PRE_TX_NEGOREQ_PROCESS_WK: ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ p2p_concurrent_handler( padapter ); ++ } ++ else ++ { ++ pre_tx_negoreq_handler( padapter ); ++ } ++#else ++ pre_tx_negoreq_handler( padapter ); ++#endif ++ break; ++ } ++#ifdef CONFIG_P2P ++#ifdef CONFIG_CONCURRENT_MODE ++ case P2P_AP_P2P_CH_SWITCH_PROCESS_WK: ++ { ++ p2p_concurrent_handler( padapter ); ++ break; ++ } ++#endif ++#endif ++#ifdef CONFIG_IOCTL_CFG80211 ++ case P2P_RO_CH_WK: ++ { ++ ro_ch_handler( padapter ); ++ break; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ } ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_P2P_PS ++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) ++{ ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ u8 noa_attr[MAX_P2P_IE_LEN] = { 0x00 };// NoA length should be n*(13) + 2 ++ u32 attr_contentlen = 0; ++ ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 find_p2p = _FALSE, find_p2p_ps = _FALSE; ++ u8 noa_offset, noa_num, noa_index; ++ ++_func_enter_; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ return; ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->iface_type != IFACE_PORT0) ++ return; ++#endif ++ if(IELength <= _BEACON_IE_OFFSET_) ++ return; ++ ++ ies = IEs + _BEACON_IE_OFFSET_; ++ ies_len = IELength - _BEACON_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen); ++ ++ while(p2p_ie) ++ { ++ find_p2p = _TRUE; ++ // Get Notice of Absence IE. ++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen)) ++ { ++ find_p2p_ps = _TRUE; ++ noa_index = noa_attr[0]; ++ ++ if( (pwdinfo->p2p_ps_mode == P2P_PS_NONE) || ++ (noa_index != pwdinfo->noa_index) )// if index change, driver should reconfigure related setting. ++ { ++ pwdinfo->noa_index = noa_index; ++ pwdinfo->opp_ps = noa_attr[1] >> 7; ++ pwdinfo->ctwindow = noa_attr[1] & 0x7F; ++ ++ noa_offset = 2; ++ noa_num = 0; ++ // NoA length should be n*(13) + 2 ++ if(attr_contentlen > 2) ++ { ++ while(noa_offset < attr_contentlen) ++ { ++ //_rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); ++ pwdinfo->noa_count[noa_num] = noa_attr[noa_offset]; ++ noa_offset += 1; ++ ++ _rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ _rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ _rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ noa_num++; ++ } ++ } ++ pwdinfo->noa_num = noa_num; ++ ++ if( pwdinfo->opp_ps == 1 ) ++ { ++ pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW; ++ // driver should wait LPS for entering CTWindow ++ if(adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); ++ } ++ } ++ else if( pwdinfo->noa_num > 0 ) ++ { ++ pwdinfo->p2p_ps_mode = P2P_PS_NOA; ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); ++ } ++ else if( pwdinfo->p2p_ps_mode > P2P_PS_NONE) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++ } ++ } ++ ++ break; // find target, just break. ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ if(find_p2p == _TRUE) ++ { ++ if( (pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE) ) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++ } ++ } ++ ++_func_exit_; ++} ++ ++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++_func_enter_; ++ ++ // Pre action for p2p state ++ switch(p2p_ps_state) ++ { ++ case P2P_PS_DISABLE: ++ pwdinfo->p2p_ps_state = p2p_ps_state; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); ++ ++ pwdinfo->noa_index = 0; ++ pwdinfo->ctwindow = 0; ++ pwdinfo->opp_ps = 0; ++ pwdinfo->noa_num = 0; ++ pwdinfo->p2p_ps_mode = P2P_PS_NONE; ++ if(pwrpriv->bFwCurrentInPSMode == _TRUE) ++ { ++ if(pwrpriv->smart_ps == 0) ++ { ++ pwrpriv->smart_ps = 2; ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); ++ } ++ } ++ break; ++ case P2P_PS_ENABLE: ++ if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { ++ pwdinfo->p2p_ps_state = p2p_ps_state; ++ ++ if( pwdinfo->ctwindow > 0 ) ++ { ++ if(pwrpriv->smart_ps != 0) ++ { ++ pwrpriv->smart_ps = 0; ++ DBG_871X("%s(): Enter CTW, change SmartPS\n", __FUNCTION__); ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); ++ } ++ } ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); ++ } ++ break; ++ case P2P_PS_SCAN: ++ case P2P_PS_SCAN_DONE: ++ case P2P_PS_ALLSTASLEEP: ++ if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { ++ pwdinfo->p2p_ps_state = p2p_ps_state; ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); ++ } ++ break; ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) ++#ifdef CONFIG_CONCURRENT_MODE ++ || (padapter->iface_type != IFACE_PORT0) ++#endif ++ ) ++ { ++ return res; ++ } ++ ++ if(enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID; ++ pdrvextra_cmd_parm->type_size = p2p_ps_state; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else ++ { ++ p2p_ps_wk_hdl(padapter, p2p_ps_state); ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++#endif // CONFIG_P2P_PS ++ ++static void reset_ch_sitesurvey_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ // Reset the operation channel information ++ pwdinfo->rx_invitereq_info.operation_ch[0] = 0; ++#ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.operation_ch[1] = 0; ++ pwdinfo->rx_invitereq_info.operation_ch[2] = 0; ++ pwdinfo->rx_invitereq_info.operation_ch[3] = 0; ++#endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; ++} ++ ++static void reset_ch_sitesurvey_timer_process2 (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ // Reset the operation channel information ++ pwdinfo->p2p_info.operation_ch[0] = 0; ++#ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.operation_ch[1] = 0; ++ pwdinfo->p2p_info.operation_ch[2] = 0; ++ pwdinfo->p2p_info.operation_ch[3] = 0; ++#endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.scan_op_ch_only = 0; ++} ++ ++static void restore_p2p_state_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ p2p_protocol_wk_cmd( adapter, P2P_RESTORE_STATE_WK ); ++} ++ ++static void pre_tx_scan_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *) FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 _status = 0; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) // the provision discovery request frame is trigger to send or not ++ { ++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK ); ++ //issue_probereq_p2p(adapter, NULL); ++ //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ } ++ } ++ else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ if ( _TRUE == pwdinfo->nego_req_info.benable ) ++ { ++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK ); ++ } ++ } ++ else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) ) ++ { ++ if ( _TRUE == pwdinfo->invitereq_info.benable ) ++ { ++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK ); ++ } ++ } ++ else ++ { ++ DBG_8192C( "[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++static void find_phase_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ adapter->wdinfo.find_phase_state_exchange_cnt++; ++ ++ p2p_protocol_wk_cmd( adapter, P2P_FIND_PHASE_WK ); ++} ++ ++#ifdef CONFIG_CONCURRENT_MODE ++void ap_p2p_switch_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev); ++#endif ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); ++#endif ++ ++ p2p_protocol_wk_cmd( adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK ); ++} ++#endif ++ ++void reset_global_wifidirect_info( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo; ++ ++ pwdinfo = &padapter->wdinfo; ++ pwdinfo->persistent_supported = 0; ++ pwdinfo->session_available = _TRUE; ++ pwdinfo->wfd_tdls_enable = 0; ++ pwdinfo->wfd_tdls_weaksec = 0; ++} ++ ++#ifdef CONFIG_WFD ++int rtw_init_wifi_display_info(_adapter* padapter) ++{ ++ int res = _SUCCESS; ++ struct wifi_display_info *pwfd_info = &padapter->wfd_info; ++ ++ // Used in P2P and TDLS ++ pwfd_info->rtsp_ctrlport = 554; ++ pwfd_info->peer_rtsp_ctrlport = 0; // Reset to 0 ++ pwfd_info->wfd_enable = _FALSE; ++ pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; ++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY; ++ ++ // Used in P2P ++ pwfd_info->peer_session_avail = _TRUE; ++ pwfd_info->wfd_pc = _FALSE; ++ ++ // Used in TDLS ++ _rtw_memset( pwfd_info->ip_address, 0x00, 4 ); ++ _rtw_memset( pwfd_info->peer_ip_address, 0x00, 4 ); ++ return res; ++ ++} ++#endif //CONFIG_WFD ++ ++void rtw_init_wifidirect_timers(_adapter* padapter) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ ++ _init_timer( &pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter ); ++ _init_timer( &pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter ); ++ _init_timer( &pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter ); ++ _init_timer( &pwdinfo->reset_ch_sitesurvey, padapter->pnetdev, reset_ch_sitesurvey_timer_process, padapter ); ++ _init_timer( &pwdinfo->reset_ch_sitesurvey2, padapter->pnetdev, reset_ch_sitesurvey_timer_process2, padapter ); ++#ifdef CONFIG_CONCURRENT_MODE ++ _init_timer( &pwdinfo->ap_p2p_switch_timer, padapter->pnetdev, ap_p2p_switch_timer_process, padapter ); ++#endif ++} ++ ++void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr) ++{ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ ++ /*init device&interface address */ ++ if (dev_addr) { ++ _rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN); ++ } ++ if (iface_addr) { ++ _rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN); ++ } ++#endif ++} ++ ++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role) ++{ ++ struct wifidirect_info *pwdinfo; ++#ifdef CONFIG_WFD ++ struct wifi_display_info *pwfd_info = &padapter->wfd_info; ++#endif ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext; ++#endif ++ ++ pwdinfo = &padapter->wdinfo; ++ ++ pwdinfo->padapter = padapter; ++ ++ // 1, 6, 11 are the social channel defined in the WiFi Direct specification. ++ pwdinfo->social_chan[0] = 1; ++ pwdinfo->social_chan[1] = 6; ++ pwdinfo->social_chan[2] = 11; ++ pwdinfo->social_chan[3] = 0; // channel 0 for scanning ending in site survey function. ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (pbuddy_adapter) { ++ pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ } ++ ++ if ( ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE ) && ++ ( ( pbuddy_mlmeext->cur_channel == 1) || ( pbuddy_mlmeext->cur_channel == 6 ) || ( pbuddy_mlmeext->cur_channel == 11 ) ) ++ ) ++ { ++ // Use the AP's channel as the listen channel ++ // This will avoid the channel switch between AP's channel and listen channel. ++ pwdinfo->listen_channel = pbuddy_mlmeext->cur_channel; ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ // Use the channel 11 as the listen channel ++ pwdinfo->listen_channel = 11; ++ } ++ ++ if (role == P2P_ROLE_DEVICE) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ #ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE ) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); ++ } ++ else ++ #endif ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ } ++ pwdinfo->intent = 1; ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN); ++ } ++ else if (role == P2P_ROLE_CLIENT) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 1; ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ } ++ else if (role == P2P_ROLE_GO) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 15; ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ } ++ ++// Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) ++ pwdinfo->support_rate[0] = 0x8c; // 6(B) ++ pwdinfo->support_rate[1] = 0x92; // 9(B) ++ pwdinfo->support_rate[2] = 0x18; // 12 ++ pwdinfo->support_rate[3] = 0x24; // 18 ++ pwdinfo->support_rate[4] = 0x30; // 24 ++ pwdinfo->support_rate[5] = 0x48; // 36 ++ pwdinfo->support_rate[6] = 0x60; // 48 ++ pwdinfo->support_rate[7] = 0x6c; // 54 ++ ++ _rtw_memcpy( ( void* ) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7 ); ++ ++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); ++ pwdinfo->device_name_len = 0; ++ ++ _rtw_memset( &pwdinfo->invitereq_info, 0x00, sizeof( struct tx_invite_req_info ) ); ++ pwdinfo->invitereq_info.token = 3; // Token used for P2P invitation request frame. ++ ++ _rtw_memset( &pwdinfo->inviteresp_info, 0x00, sizeof( struct tx_invite_resp_info ) ); ++ pwdinfo->inviteresp_info.token = 0; ++ ++ pwdinfo->profileindex = 0; ++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); ++ ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); ++ ++ pwdinfo->listen_dwell = ( u8 ) (( rtw_get_current_time() % 3 ) + 1); ++ //DBG_8192C( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); ++ ++ _rtw_memset( &pwdinfo->tx_prov_disc_info, 0x00, sizeof( struct tx_provdisc_req_info ) ); ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE; ++ ++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); ++ ++ pwdinfo->device_password_id_for_nego = WPS_DPID_PBC; ++ pwdinfo->negotiation_dialog_token = 1; ++ ++ _rtw_memset( pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN ); ++ pwdinfo->nego_ssidlen = 0; ++ ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++#ifdef CONFIG_WFD ++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC; ++ pwdinfo->wfd_info = pwfd_info; ++#else ++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD; ++#endif //CONFIG_WFD ++ pwdinfo->channel_list_attr_len = 0; ++ _rtw_memset( pwdinfo->channel_list_attr, 0x00, 100 ); ++ ++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4 ); ++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3 ); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++#ifdef CONFIG_CONCURRENT_MODE ++#ifdef CONFIG_IOCTL_CFG80211 ++ pwdinfo->ext_listen_interval = 1000; //The interval to be available with legacy AP during p2p0-find/scan ++ pwdinfo->ext_listen_period = 3000; //The time period to be available for P2P during nego ++#else //!CONFIG_IOCTL_CFG80211 ++ //pwdinfo->ext_listen_interval = 3000; ++ //pwdinfo->ext_listen_period = 400; ++ pwdinfo->ext_listen_interval = 1000; ++ pwdinfo->ext_listen_period = 1000; ++#endif //!CONFIG_IOCTL_CFG80211 ++#endif ++ ++// Commented by Kurt 20130319 ++// For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. ++#ifdef CONFIG_IOCTL_CFG80211 ++ pwdinfo->driver_interface = DRIVER_CFG80211; ++#else ++ pwdinfo->driver_interface = DRIVER_WEXT; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ pwdinfo->wfd_tdls_enable = 0; ++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); ++ _rtw_memset( pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN ); ++ ++ pwdinfo->rx_invitereq_info.operation_ch[0] = 0; ++ pwdinfo->rx_invitereq_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function ++#ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.operation_ch[2] = 0; ++ pwdinfo->rx_invitereq_info.operation_ch[3] = 0; ++ pwdinfo->rx_invitereq_info.operation_ch[4] = 0; ++#endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; ++ pwdinfo->p2p_info.operation_ch[0] = 0; ++ pwdinfo->p2p_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function ++#ifdef P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.operation_ch[2] = 0; ++ pwdinfo->p2p_info.operation_ch[3] = 0; ++ pwdinfo->p2p_info.operation_ch[4] = 0; ++#endif //P2P_OP_CHECK_SOCIAL_CH ++ pwdinfo->p2p_info.scan_op_ch_only = 0; ++} ++ ++#ifdef CONFIG_DBG_P2P ++ ++/** ++ * rtw_p2p_role_txt - Get the p2p role name as a text string ++ * @role: P2P role ++ * Returns: The state name as a printable text string ++ */ ++const char * rtw_p2p_role_txt(enum P2P_ROLE role) ++{ ++ switch (role) { ++ case P2P_ROLE_DISABLE: ++ return "P2P_ROLE_DISABLE"; ++ case P2P_ROLE_DEVICE: ++ return "P2P_ROLE_DEVICE"; ++ case P2P_ROLE_CLIENT: ++ return "P2P_ROLE_CLIENT"; ++ case P2P_ROLE_GO: ++ return "P2P_ROLE_GO"; ++ default: ++ return "UNKNOWN"; ++ } ++} ++ ++/** ++ * rtw_p2p_state_txt - Get the p2p state name as a text string ++ * @state: P2P state ++ * Returns: The state name as a printable text string ++ */ ++const char * rtw_p2p_state_txt(enum P2P_STATE state) ++{ ++ switch (state) { ++ case P2P_STATE_NONE: ++ return "P2P_STATE_NONE"; ++ case P2P_STATE_IDLE: ++ return "P2P_STATE_IDLE"; ++ case P2P_STATE_LISTEN: ++ return "P2P_STATE_LISTEN"; ++ case P2P_STATE_SCAN: ++ return "P2P_STATE_SCAN"; ++ case P2P_STATE_FIND_PHASE_LISTEN: ++ return "P2P_STATE_FIND_PHASE_LISTEN"; ++ case P2P_STATE_FIND_PHASE_SEARCH: ++ return "P2P_STATE_FIND_PHASE_SEARCH"; ++ case P2P_STATE_TX_PROVISION_DIS_REQ: ++ return "P2P_STATE_TX_PROVISION_DIS_REQ"; ++ case P2P_STATE_RX_PROVISION_DIS_RSP: ++ return "P2P_STATE_RX_PROVISION_DIS_RSP"; ++ case P2P_STATE_RX_PROVISION_DIS_REQ: ++ return "P2P_STATE_RX_PROVISION_DIS_REQ"; ++ case P2P_STATE_GONEGO_ING: ++ return "P2P_STATE_GONEGO_ING"; ++ case P2P_STATE_GONEGO_OK: ++ return "P2P_STATE_GONEGO_OK"; ++ case P2P_STATE_GONEGO_FAIL: ++ return "P2P_STATE_GONEGO_FAIL"; ++ case P2P_STATE_RECV_INVITE_REQ_MATCH: ++ return "P2P_STATE_RECV_INVITE_REQ_MATCH"; ++ case P2P_STATE_PROVISIONING_ING: ++ return "P2P_STATE_PROVISIONING_ING"; ++ case P2P_STATE_PROVISIONING_DONE: ++ return "P2P_STATE_PROVISIONING_DONE"; ++ case P2P_STATE_TX_INVITE_REQ: ++ return "P2P_STATE_TX_INVITE_REQ"; ++ case P2P_STATE_RX_INVITE_RESP_OK: ++ return "P2P_STATE_RX_INVITE_RESP_OK"; ++ case P2P_STATE_RECV_INVITE_REQ_DISMATCH: ++ return "P2P_STATE_RECV_INVITE_REQ_DISMATCH"; ++ case P2P_STATE_RECV_INVITE_REQ_GO: ++ return "P2P_STATE_RECV_INVITE_REQ_GO"; ++ case P2P_STATE_RECV_INVITE_REQ_JOIN: ++ return "P2P_STATE_RECV_INVITE_REQ_JOIN"; ++ case P2P_STATE_RX_INVITE_RESP_FAIL: ++ return "P2P_STATE_RX_INVITE_RESP_FAIL"; ++ case P2P_STATE_RX_INFOR_NOREADY: ++ return "P2P_STATE_RX_INFOR_NOREADY"; ++ case P2P_STATE_TX_INFOR_NOREADY: ++ return "P2P_STATE_TX_INFOR_NOREADY"; ++ default: ++ return "UNKNOWN"; ++ } ++} ++ ++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) ++{ ++ if(!_rtw_p2p_chk_state(wdinfo, state)) { ++ enum P2P_STATE old_state = _rtw_p2p_state(wdinfo); ++ _rtw_p2p_set_state(wdinfo, state); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line ++ , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line ++ , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) ++ ); ++ } ++} ++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) ++{ ++ if(_rtw_p2p_pre_state(wdinfo) != state) { ++ enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo); ++ _rtw_p2p_set_pre_state(wdinfo, state); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line ++ , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line ++ , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) ++ ); ++ } ++} ++#if 0 ++void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line) ++{ ++ if(wdinfo->pre_p2p_state != -1) { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line ++ , p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state] ++ ); ++ _rtw_p2p_restore_state(wdinfo); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line ++ , p2p_state_str[wdinfo->p2p_state] ++ ); ++ } ++} ++#endif ++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line) ++{ ++ if(wdinfo->role != role) { ++ enum P2P_ROLE old_role = wdinfo->role; ++ _rtw_p2p_set_role(wdinfo, role); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line ++ , rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role) ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line ++ , rtw_p2p_role_txt(wdinfo->role) ++ ); ++ } ++} ++#endif //CONFIG_DBG_P2P ++ ++ ++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) ++{ ++ int ret = _SUCCESS; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT|| role == P2P_ROLE_GO) ++ { ++ u8 channel, ch_offset; ++ u16 bwmode; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ // Commented by Albert 2011/12/30 ++ // The driver just supports 1 P2P group operation. ++ // So, this function will do nothing if the buddy adapter had enabled the P2P function. ++ if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) ++ { ++ // The buddy adapter had enabled the P2P function. ++ return ret; ++ } ++#endif //CONFIG_CONCURRENT_MODE ++ ++ //leave IPS/Autosuspend ++ if (_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ // Added by Albert 2011/03/22 ++ // In the P2P mode, the driver should not support the b mode. ++ // So, the Tx packet shouldn't use the CCK rate ++ update_tx_basic_rate(padapter, WIRELESS_11AGN); ++ ++ //Enable P2P function ++ init_wifidirect_info(padapter, role); ++ ++ rtw_hal_set_odm_var(padapter,HAL_ODM_P2P_STATE,NULL,_TRUE); ++ #ifdef CONFIG_WFD ++ rtw_hal_set_odm_var(padapter,HAL_ODM_WIFI_DISPLAY_STATE,NULL,_TRUE); ++ #endif ++ ++ } ++ else if (role == P2P_ROLE_DISABLE) ++ { ++#ifdef CONFIG_INTEL_WIDI ++ if( padapter->mlmepriv.p2p_reject_disable == _TRUE ) ++ return ret; ++#endif //CONFIG_INTEL_WIDI ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _FALSE; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ if (_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //Disable P2P function ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey); ++ _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey2); ++ reset_ch_sitesurvey_timer_process( padapter ); ++ reset_ch_sitesurvey_timer_process2( padapter ); ++ #ifdef CONFIG_CONCURRENT_MODE ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer); ++ #endif ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); ++ _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info)); ++ } ++ ++ rtw_hal_set_odm_var(padapter,HAL_ODM_P2P_STATE,NULL,_FALSE); ++ #ifdef CONFIG_WFD ++ rtw_hal_set_odm_var(padapter,HAL_ODM_WIFI_DISPLAY_STATE,NULL,_FALSE); ++ #endif ++ ++ //Restore to initial setting. ++ update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); ++ ++#ifdef CONFIG_INTEL_WIDI ++ rtw_reset_widi_info(padapter); ++#endif //CONFIG_INTEL_WIDI ++ ++ //For WiDi purpose. ++#ifdef CONFIG_IOCTL_CFG80211 ++ pwdinfo->driver_interface = DRIVER_CFG80211; ++#else ++ pwdinfo->driver_interface = DRIVER_WEXT; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ } ++ ++exit: ++ return ret; ++} ++ ++#endif //CONFIG_P2P ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_pwrctrl.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_pwrctrl.c +new file mode 100644 +index 00000000..3ccfbfec +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_pwrctrl.c +@@ -0,0 +1,1926 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_PWRCTRL_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_BT_COEXIST ++#include ++#endif ++ ++#ifdef CONFIG_IPS ++void _ips_enter(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ ++ if (padapter->hw_init_completed == _FALSE) { ++ DBG_871X("%s: hw_init_completed: %d\n", ++ __func__, padapter->hw_init_completed); ++ return; ++ } ++ ++ pwrpriv->bips_processing = _TRUE; ++ ++ // syn ips_mode with request ++ pwrpriv->ips_mode = pwrpriv->ips_mode_req; ++ ++ pwrpriv->ips_enter_cnts++; ++ DBG_871X("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts); ++#ifdef CONFIG_BT_COEXIST ++ BTDM_TurnOffBtCoexistBeforeEnterIPS(padapter); ++#endif ++ if(rf_off == pwrpriv->change_rfpwrstate ) ++ { ++ pwrpriv->bpower_saving = _TRUE; ++ DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n"); ++ ++ if(pwrpriv->ips_mode == IPS_LEVEL_2) ++ pwrpriv->bkeepfwalive = _TRUE; ++ ++ rtw_ips_pwr_down(padapter); ++ pwrpriv->rf_pwrstate = rf_off; ++ } ++ pwrpriv->bips_processing = _FALSE; ++ ++} ++ ++void ips_enter(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ _ips_enter(padapter); ++ _exit_pwrlock(&pwrpriv->lock); ++} ++ ++int _ips_leave(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ int result = _SUCCESS; ++ ++ if((pwrpriv->rf_pwrstate == rf_off) &&(!pwrpriv->bips_processing)) ++ { ++ pwrpriv->bips_processing = _TRUE; ++ pwrpriv->change_rfpwrstate = rf_on; ++ pwrpriv->ips_leave_cnts++; ++ DBG_871X("==>ips_leave cnts:%d\n",pwrpriv->ips_leave_cnts); ++ ++ if ((result = rtw_ips_pwr_up(padapter)) == _SUCCESS) { ++ pwrpriv->rf_pwrstate = rf_on; ++ } ++ DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n"); ++ ++ DBG_871X("==> ips_leave.....LED(0x%08x)...\n",rtw_read32(padapter,0x4c)); ++ pwrpriv->bips_processing = _FALSE; ++ ++ pwrpriv->bkeepfwalive = _FALSE; ++ pwrpriv->bpower_saving = _FALSE; ++ } ++ ++ return result; ++} ++ ++int ips_leave(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ int ret; ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ret = _ips_leave(padapter); ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ return ret; ++} ++#endif /* CONFIG_IPS */ ++ ++#ifdef CONFIG_AUTOSUSPEND ++extern void autosuspend_enter(_adapter* padapter); ++extern int autoresume_enter(_adapter* padapter); ++#endif ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++int rtw_hw_suspend(_adapter *padapter ); ++int rtw_hw_resume(_adapter *padapter); ++#endif ++ ++bool rtw_pwr_unassociated_idle(_adapter *adapter) ++{ ++ _adapter *buddy = adapter->pbuddy_adapter; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct xmit_priv *pxmit_priv = &adapter->xmitpriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(adapter->wdinfo); ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo; ++#endif ++#endif ++ ++ bool ret = _FALSE; ++ ++ if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) { ++ //DBG_871X("%s ips_deny_time\n", __func__); ++ goto exit; ++ } ++ ++ if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) ++ || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) ++ || check_fwstate(pmlmepriv, WIFI_AP_STATE) ++ || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) ++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS) ++ || pcfg80211_wdinfo->is_ro_ch ++ #elif defined(CONFIG_P2P) ++ || !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) ++ #endif ++ ) { ++ goto exit; ++ } ++ ++ /* consider buddy, if exist */ ++ if (buddy) { ++ struct mlme_priv *b_pmlmepriv = &(buddy->mlmepriv); ++ #ifdef CONFIG_P2P ++ struct wifidirect_info *b_pwdinfo = &(buddy->wdinfo); ++ #ifdef CONFIG_IOCTL_CFG80211 ++ struct cfg80211_wifidirect_info *b_pcfg80211_wdinfo = &buddy->cfg80211_wdinfo; ++ #endif ++ #endif ++ ++ if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) ++ || check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) ++ || check_fwstate(b_pmlmepriv, WIFI_AP_STATE) ++ || check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) ++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS) ++ || b_pcfg80211_wdinfo->is_ro_ch ++ #elif defined(CONFIG_P2P) ++ || !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE) ++ #endif ++ ) { ++ goto exit; ++ } ++ } ++ ++#if (MP_DRIVER == 1) ++ if (adapter->registrypriv.mp_mode == 1) ++ goto exit; ++#endif ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if(adapter->proximity.proxim_on==_TRUE){ ++ return; ++ } ++#endif ++ ++ if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF || ++ pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) { ++ DBG_871X_LEVEL(_drv_always_, "There are some pkts to transmit\n"); ++ DBG_871X_LEVEL(_drv_info_, "free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n", ++ pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt); ++ goto exit; ++ } ++ ++ ret = _TRUE; ++ ++exit: ++ return ret; ++} ++ ++#if defined (PLATFORM_LINUX)||defined (PLATFORM_FREEBSD) ++void rtw_ps_processor(_adapter*padapter) ++{ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#endif //CONFIG_P2P ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ rt_rf_power_state rfpwrstate; ++#endif //SUPPORT_HW_RFOFF_DETECTED ++ ++ pwrpriv->ps_processing = _TRUE; ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ if(pwrpriv->bips_processing == _TRUE) ++ goto exit; ++ ++ //DBG_871X("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca)); ++ if(pwrpriv->bHWPwrPindetect) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ if(padapter->registrypriv.usbss_enable) ++ { ++ if(pwrpriv->rf_pwrstate == rf_on) ++ { ++ if(padapter->net_closed == _TRUE) ++ pwrpriv->ps_flag = _TRUE; ++ ++ rfpwrstate = RfOnOffDetect(padapter); ++ DBG_871X("@@@@- #1 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); ++ if(rfpwrstate!= pwrpriv->rf_pwrstate) ++ { ++ if(rfpwrstate == rf_off) ++ { ++ pwrpriv->change_rfpwrstate = rf_off; ++ ++ pwrpriv->bkeepfwalive = _TRUE; ++ pwrpriv->brfoffbyhw = _TRUE; ++ ++ autosuspend_enter(padapter); ++ } ++ } ++ } ++ } ++ else ++ #endif //CONFIG_AUTOSUSPEND ++ { ++ rfpwrstate = RfOnOffDetect(padapter); ++ DBG_871X("@@@@- #2 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); ++ ++ if(rfpwrstate!= pwrpriv->rf_pwrstate) ++ { ++ if(rfpwrstate == rf_off) ++ { ++ pwrpriv->change_rfpwrstate = rf_off; ++ pwrpriv->brfoffbyhw = _TRUE; ++ padapter->bCardDisableWOHSM = _TRUE; ++ rtw_hw_suspend(padapter ); ++ } ++ else ++ { ++ pwrpriv->change_rfpwrstate = rf_on; ++ rtw_hw_resume(padapter ); ++ } ++ DBG_871X("current rf_pwrstate(%s)\n",(pwrpriv->rf_pwrstate == rf_off)?"rf_off":"rf_on"); ++ } ++ } ++ pwrpriv->pwr_state_check_cnts ++; ++ } ++#endif //SUPPORT_HW_RFOFF_DETECTED ++ ++ if (pwrpriv->ips_mode_req == IPS_NONE) ++ goto exit; ++ ++ if (rtw_pwr_unassociated_idle(padapter) == _FALSE) ++ goto exit; ++ ++ if((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts%4)==0)) ++ { ++ DBG_871X("==>%s .fw_state(%x)\n",__FUNCTION__,get_fwstate(pmlmepriv)); ++ #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ #else ++ pwrpriv->change_rfpwrstate = rf_off; ++ #endif ++ #ifdef CONFIG_AUTOSUSPEND ++ if(padapter->registrypriv.usbss_enable) ++ { ++ if(pwrpriv->bHWPwrPindetect) ++ pwrpriv->bkeepfwalive = _TRUE; ++ ++ if(padapter->net_closed == _TRUE) ++ pwrpriv->ps_flag = _TRUE; ++ ++ #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ if (_TRUE==pwrpriv->bInternalAutoSuspend) { ++ DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x)\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend); ++ } else { ++ pwrpriv->change_rfpwrstate = rf_off; ++ padapter->bCardDisableWOHSM = _TRUE; ++ DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x) call autosuspend_enter\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend); ++ autosuspend_enter(padapter); ++ } ++ #else ++ padapter->bCardDisableWOHSM = _TRUE; ++ autosuspend_enter(padapter); ++ #endif //if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ } ++ else if(pwrpriv->bHWPwrPindetect) ++ { ++ } ++ else ++ #endif //CONFIG_AUTOSUSPEND ++ { ++ #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ pwrpriv->change_rfpwrstate = rf_off; ++ #endif //defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ ++ #ifdef CONFIG_IPS ++ ips_enter(padapter); ++ #endif ++ } ++ } ++exit: ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ pwrpriv->ps_processing = _FALSE; ++ return; ++} ++ ++void pwr_state_check_handler(void *FunctionContext); ++void pwr_state_check_handler(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ rtw_ps_cmd(padapter); ++} ++#endif ++ ++ ++ ++#ifdef CONFIG_LPS ++/* ++ * ++ * Parameters ++ * padapter ++ * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 ++ * ++ */ ++void rtw_set_rpwm(PADAPTER padapter, u8 pslv) ++{ ++ u8 rpwm; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++ u8 cpwm_orig = 0; ++ u8 cpwm_now = 0; ++ u32 cpwm_polling_start_time = 0; ++ u8 pollingRes = _FAIL; ++#endif ++ ++_func_enter_; ++ ++ pslv = PS_STATE(pslv); ++ ++ ++ if (_TRUE == pwrpriv->btcoex_rfon) ++ { ++ if (pslv < PS_STATE_S4) ++ pslv = PS_STATE_S3; ++ } ++ ++#ifdef CONFIG_LPS_RPWM_TIMER ++ if (pwrpriv->brpwmtimeout == _TRUE) ++ { ++ DBG_871X("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv); ++ } ++ else ++#endif // CONFIG_LPS_RPWM_TIMER ++ { ++ if ( (pwrpriv->rpwm == pslv) ++#ifdef CONFIG_LPS_LCLK ++#ifndef CONFIG_RTL8723A ++ || ((pwrpriv->rpwm >= PS_STATE_S2)&&(pslv >= PS_STATE_S2)) ++#endif ++#endif ++ ) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_, ++ ("%s: Already set rpwm[0x%02X], new=0x%02X!\n", __FUNCTION__, pwrpriv->rpwm, pslv)); ++ return; ++ } ++ } ++ ++ if ((padapter->bSurpriseRemoved == _TRUE) || ++ (padapter->hw_init_completed == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ++ ("%s: SurpriseRemoved(%d) hw_init_completed(%d)\n", ++ __FUNCTION__, padapter->bSurpriseRemoved, padapter->hw_init_completed)); ++ ++ pwrpriv->cpwm = PS_STATE_S4; ++ ++ return; ++ } ++ ++ if (padapter->bDriverStopped == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ++ ("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv)); ++ ++ if (pslv < PS_STATE_S2) { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ++ ("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __FUNCTION__, pslv)); ++ return; ++ } ++ } ++ ++ rpwm = pslv | pwrpriv->tog; ++#ifdef CONFIG_LPS_LCLK ++ // only when from PS_STATE S0/S1 to S2 and higher needs ACK ++ if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2)) ++ rpwm |= PS_ACK; ++#endif ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm)); ++ ++ pwrpriv->rpwm = pslv; ++ ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++ if (rpwm & PS_ACK) ++ { ++ //cpwm_orig = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1); ++ rtw_hal_get_hwreg(padapter, HW_VAR_GET_CPWM, (u8 *)(&cpwm_orig)); ++ } ++#endif ++ ++#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING) ++ if (rpwm & PS_ACK) ++ _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_RPWM_WAIT_MS); ++#endif // CONFIG_LPS_RPWM_TIMER && !CONFIG_DETECT_CPWM_BY_POLLING ++ rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); ++ ++ pwrpriv->tog += 0x80; ++ ++#ifdef CONFIG_LPS_LCLK ++ // No LPS 32K, No Ack ++ if (!(rpwm & PS_ACK)) ++#endif ++ { ++ pwrpriv->cpwm = pslv; ++ } ++ ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++ if (rpwm & PS_ACK) ++ { ++ cpwm_polling_start_time = rtw_get_current_time(); ++ ++ //polling cpwm ++ do{ ++ rtw_mdelay_os(1); ++ ++ //cpwm_now = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1); ++ rtw_hal_get_hwreg(padapter, HW_VAR_GET_CPWM, (u8 *)(&cpwm_now)); ++ if ((cpwm_orig ^ cpwm_now) & 0x80) ++ { ++#ifdef CONFIG_LPS_LCLK ++ #ifdef CONFIG_RTL8723A ++ pwrpriv->cpwm = PS_STATE(cpwm_now); ++ #else // !CONFIG_RTL8723A ++ pwrpriv->cpwm = PS_STATE_S4; ++ #endif // !CONFIG_RTL8723A ++ pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; ++#endif ++ pollingRes = _SUCCESS; ++ break; ++ } ++ }while (rtw_get_passing_time_ms(cpwm_polling_start_time) < LPS_RPWM_WAIT_MS); ++ ++ if (pollingRes == _FAIL) ++ { ++#ifdef CONFIG_LPS_RPWM_TIMER ++ _set_timer(&pwrpriv->pwr_rpwm_timer, 1); ++#endif ++ DBG_871X("%s polling cpwm timeout!!!!!!!!!!\n", __FUNCTION__); ++ } ++ } ++#endif ++ ++_func_exit_; ++} ++ ++u8 PS_RDY_CHECK(_adapter * padapter); ++u8 PS_RDY_CHECK(_adapter * padapter) ++{ ++ u32 curr_time, delta_time; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_WOWLAN ++ if(_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode) ++ return _TRUE; ++ else if (_TRUE == pwrpriv->bInSuspend) ++ return _FALSE; ++#else ++ if(_TRUE == pwrpriv->bInSuspend ) ++ return _FALSE; ++#endif ++ ++ curr_time = rtw_get_current_time(); ++ delta_time = curr_time -pwrpriv->DelayLPSLastTimeStamp; ++ ++ if(delta_time < LPS_DELAY_TIME) ++ { ++ return _FALSE; ++ } ++ ++ if ((check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) || ++ (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ) ++ return _FALSE; ++ ++ if( (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE) ) ++ { ++ DBG_871X("Group handshake still in progress !!!\n"); ++ return _FALSE; ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if (!rtw_cfg80211_pwr_mgmt(padapter)) ++ return _FALSE; ++#endif ++ ++ return _TRUE; ++} ++ ++void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#endif //CONFIG_P2P ++#ifdef CONFIG_TDLS ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ _irqL irqL; ++ int i, j; ++ _list *plist, *phead; ++ struct sta_info *ptdls_sta; ++#endif //CONFIG_TDLS ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("%s: PowerMode=%d Smart_PS=%d\n", ++ __FUNCTION__, ps_mode, smart_ps)); ++ ++ if(ps_mode > PM_Card_Disable) { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("ps_mode:%d error\n", ps_mode)); ++ return; ++ } ++ ++ if (pwrpriv->pwr_mode == ps_mode) ++ { ++ if (PS_MODE_ACTIVE == ps_mode) return; ++ ++ if ((pwrpriv->smart_ps == smart_ps) && ++ (pwrpriv->bcn_ant_mode == bcn_ant_mode)) ++ { ++ return; ++ } ++ } ++ ++#ifdef CONFIG_LPS_LCLK ++ _enter_pwrlock(&pwrpriv->lock); ++#endif ++ ++ //if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ if(ps_mode == PS_MODE_ACTIVE) ++ { ++#ifdef CONFIG_P2P_PS ++ if(pwdinfo->opp_ps == 0) ++#endif //CONFIG_P2P_PS ++ { ++ DBG_871X("rtw_set_ps_mode: Leave 802.11 power save\n"); ++ ++#ifdef CONFIG_TDLS ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE ) ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0); ++ plist = get_next(plist); ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++#endif //CONFIG_TDLS ++ ++ pwrpriv->pwr_mode = ps_mode; ++ rtw_set_rpwm(padapter, PS_STATE_S4); ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_mode == _TRUE) ++ { ++ u32 start_time, delay_ms; ++ u8 val8; ++ delay_ms = 20; ++ start_time = rtw_get_current_time(); ++ do { ++ rtw_hal_get_hwreg(padapter, HW_VAR_SYS_CLKR, &val8); ++ if (!(val8 & BIT(4))){ //0x08 bit4 =1 --> in 32k, bit4 = 0 --> leave 32k ++ pwrpriv->cpwm = PS_STATE_S4; ++ break; ++ } ++ if (rtw_get_passing_time_ms(start_time) > delay_ms) ++ { ++ DBG_871X("%s: Wait for FW 32K leave more than %u ms!!!\n", __FUNCTION__, delay_ms); ++ break; ++ } ++ rtw_usleep_os(100); ++ } while (1); ++ } ++#endif ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); ++ pwrpriv->bFwCurrentInPSMode = _FALSE; ++ } ++ } ++ else ++ { ++ if (PS_RDY_CHECK(padapter) ++#ifdef CONFIG_BT_COEXIST ++ || (BT_1Ant(padapter) == _TRUE) ++#endif ++ ) ++ { ++ DBG_871X("%s: Enter 802.11 power save\n", __FUNCTION__); ++ ++#ifdef CONFIG_TDLS ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE ) ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 1); ++ plist = get_next(plist); ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++#endif //CONFIG_TDLS ++ ++ pwrpriv->bFwCurrentInPSMode = _TRUE; ++ pwrpriv->pwr_mode = ps_mode; ++ pwrpriv->smart_ps = smart_ps; ++ pwrpriv->bcn_ant_mode = bcn_ant_mode; ++ rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); ++ ++#ifdef CONFIG_P2P_PS ++ // Set CTWindow after LPS ++ if(pwdinfo->opp_ps == 1) ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0); ++#endif //CONFIG_P2P_PS ++ ++#ifdef CONFIG_LPS_LCLK ++ DBG_871X("%s: alives: %d\n", __FUNCTION__, pwrpriv->alives); ++ if (pwrpriv->alives == 0) ++ rtw_set_rpwm(padapter, PS_STATE_S0); ++#else ++ rtw_set_rpwm(padapter, PS_STATE_S2); ++#endif ++ } ++ } ++ ++#ifdef CONFIG_LPS_LCLK ++ _exit_pwrlock(&pwrpriv->lock); ++#endif ++ ++_func_exit_; ++} ++ ++/* ++ * Return: ++ * 0: Leave OK ++ * -1: Timeout ++ * -2: Other error ++ */ ++s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms) ++{ ++ u32 start_time; ++ u8 bAwake = _FALSE; ++ s32 err = 0; ++ ++ ++ start_time = rtw_get_current_time(); ++ while (1) ++ { ++ rtw_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, &bAwake); ++ if (_TRUE == bAwake) ++ break; ++ ++ if (_TRUE == padapter->bSurpriseRemoved) ++ { ++ err = -2; ++ DBG_871X("%s: device surprise removed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ if (rtw_get_passing_time_ms(start_time) > delay_ms) ++ { ++ err = -1; ++ DBG_871X("%s: Wait for FW LPS leave more than %u ms!!!\n", __FUNCTION__, delay_ms); ++ break; ++ } ++ rtw_usleep_os(100); ++ } ++ ++ return err; ++} ++ ++// ++// Description: ++// Enter the leisure power save mode. ++// ++void LPS_Enter(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _adapter *buddy = padapter->pbuddy_adapter; ++ ++_func_enter_; ++ ++// DBG_871X("+LeisurePSEnter\n"); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->iface_type != IFACE_PORT0) ++ return; /* Skip power saving for concurrent mode port 1*/ ++ ++ /* consider buddy, if exist */ ++ if (buddy) { ++ struct mlme_priv *b_pmlmepriv = &(buddy->mlmepriv); ++ #ifdef CONFIG_P2P ++ struct wifidirect_info *b_pwdinfo = &(buddy->wdinfo); ++ #ifdef CONFIG_IOCTL_CFG80211 ++ struct cfg80211_wifidirect_info *b_pcfg80211_wdinfo = &buddy->cfg80211_wdinfo; ++ #endif ++ #endif ++ ++ if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) ++ || check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) ++ || check_fwstate(b_pmlmepriv, WIFI_AP_STATE) ++ || check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) ++ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P_IPS) ++ || b_pcfg80211_wdinfo->is_ro_ch ++ #elif defined(CONFIG_P2P) ++ || !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE) ++ #endif ++ || rtw_is_scan_deny(buddy) ++ ) { ++ return; ++ } ++ } ++#endif ++ ++ if (PS_RDY_CHECK(padapter) == _FALSE) ++ return; ++ ++ if (_TRUE == pwrpriv->bLeisurePs) ++ { ++ // Idle for a while if we connect to AP a while ago. ++ if(pwrpriv->LpsIdleCount >= 2) // 4 Sec ++ { ++ if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ { ++ pwrpriv->bpower_saving = _TRUE; ++ DBG_871X("%s smart_ps:%d\n", __func__, pwrpriv->smart_ps); ++ //For Tenda W311R IOT issue ++ rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, pwrpriv->smart_ps, 0x40); ++ } ++ } ++ else ++ pwrpriv->LpsIdleCount++; ++ } ++ ++// DBG_871X("-LeisurePSEnter\n"); ++ ++_func_exit_; ++} ++ ++// ++// Description: ++// Leave the leisure power save mode. ++// ++void LPS_Leave(PADAPTER padapter) ++{ ++#define LPS_LEAVE_TIMEOUT_MS 100 ++ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ u32 start_time; ++ u8 bAwake = _FALSE; ++ ++_func_enter_; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->iface_type != IFACE_PORT0) ++ return; /* Skip power saving for concurrent mode port 1*/ ++#endif ++ ++// DBG_871X("+LeisurePSLeave\n"); ++ ++ if (pwrpriv->bLeisurePs) ++ { ++ if(pwrpriv->pwr_mode != PS_MODE_ACTIVE) ++ { ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0x40); ++ ++ if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS); ++ } ++ } ++ ++ pwrpriv->bpower_saving = _FALSE; ++ ++// DBG_871X("-LeisurePSLeave\n"); ++ ++_func_exit_; ++} ++#endif ++ ++// ++// Description: Leave all power save mode: LPS, FwLPS, IPS if needed. ++// Move code to function by tynli. 2010.03.26. ++// ++void LeaveAllPowerSaveMode(IN PADAPTER Adapter) ++{ ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ u8 enqueue = 0; ++ ++_func_enter_; ++ ++ //DBG_871X("%s.....\n",__FUNCTION__); ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { //connect ++#ifdef CONFIG_LPS_LCLK ++ enqueue = 1; ++#endif ++ ++#ifdef CONFIG_P2P_PS ++ p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue); ++#endif //CONFIG_P2P_PS ++ ++#ifdef CONFIG_LPS ++ rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue); ++#endif ++ ++#ifdef CONFIG_LPS_LCLK ++ LPS_Leave_check(Adapter); ++#endif ++ } ++ else ++ { ++ if(adapter_to_pwrctl(Adapter)->rf_pwrstate== rf_off) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ if(Adapter->registrypriv.usbss_enable) ++ { ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;//autosuspend disabled by the user ++ #endif ++ } ++ else ++ #endif ++ { ++#if defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E) ++ #ifdef CONFIG_IPS ++ if(_FALSE == ips_leave(Adapter)) ++ { ++ DBG_871X("======> ips_leave fail.............\n"); ++ } ++ #endif ++#endif //CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E ++ } ++ } ++ } ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_LPS_LCLK ++void LPS_Leave_check( ++ PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrpriv; ++ u32 start_time; ++ u8 bReady; ++ ++_func_enter_; ++ ++ pwrpriv = adapter_to_pwrctl(padapter); ++ ++ bReady = _FALSE; ++ start_time = rtw_get_current_time(); ++ ++ rtw_yield_os(); ++ ++ while(1) ++ { ++ _enter_pwrlock(&pwrpriv->lock); ++ ++ if ((padapter->bSurpriseRemoved == _TRUE) ++ || (padapter->hw_init_completed == _FALSE) ++#ifdef CONFIG_USB_HCI ++ || (padapter->bDriverStopped== _TRUE) ++#endif ++ || (pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ ) ++ { ++ bReady = _TRUE; ++ } ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ if(_TRUE == bReady) ++ break; ++ ++ if(rtw_get_passing_time_ms(start_time)>100) ++ { ++ DBG_871X("Wait for cpwm event than 100 ms!!!\n"); ++ break; ++ } ++ rtw_msleep_os(1); ++ } ++ ++_func_exit_; ++} ++ ++/* ++ * Caller:ISR handler... ++ * ++ * This will be called when CPWM interrupt is up. ++ * ++ * using to update cpwn of drv; and drv willl make a decision to up or down pwr level ++ */ ++void cpwm_int_hdl( ++ PADAPTER padapter, ++ struct reportpwrstate_parm *preportpwrstate) ++{ ++ struct pwrctrl_priv *pwrpriv; ++ ++_func_enter_; ++ ++ pwrpriv = adapter_to_pwrctl(padapter); ++#if 0 ++ if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ++ ("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n", ++ pwrpriv->cpwm_tog, preportpwrstate->state)); ++ goto exit; ++ } ++#endif ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ++#ifdef CONFIG_LPS_RPWM_TIMER ++ if (pwrpriv->rpwm < PS_STATE_S2) ++ { ++ DBG_871X("%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); ++ _exit_pwrlock(&pwrpriv->lock); ++ goto exit; ++ } ++#endif // CONFIG_LPS_RPWM_TIMER ++ ++ pwrpriv->cpwm = PS_STATE(preportpwrstate->state); ++ pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE; ++ ++ if (pwrpriv->cpwm >= PS_STATE_S2) ++ { ++ if (pwrpriv->alives & CMD_ALIVE) ++ _rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema); ++ ++ if (pwrpriv->alives & XMIT_ALIVE) ++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema); ++ } ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ ++exit: ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("cpwm_int_hdl: cpwm=0x%02x\n", pwrpriv->cpwm)); ++ ++_func_exit_; ++} ++ ++static void cpwm_event_callback(struct work_struct *work) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event); ++ struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); ++ _adapter *adapter = dvobj->if1; ++ struct reportpwrstate_parm report; ++ ++ //DBG_871X("%s\n",__FUNCTION__); ++ ++ report.state = PS_STATE_S2; ++ cpwm_int_hdl(adapter, &report); ++} ++ ++#ifdef CONFIG_LPS_RPWM_TIMER ++static void rpwmtimeout_workitem_callback(struct work_struct *work) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *dvobj; ++ struct pwrctrl_priv *pwrpriv; ++ ++ ++ pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi); ++ dvobj = pwrctl_to_dvobj(pwrpriv); ++ padapter = dvobj->if1; ++// DBG_871X("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) ++ { ++ DBG_871X("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); ++ goto exit; ++ } ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ if (rtw_read8(padapter, 0x100) != 0xEA) ++ { ++#if 1 ++ struct reportpwrstate_parm report; ++ ++ report.state = PS_STATE_S2; ++ DBG_871X("\n%s: FW already leave 32K!\n\n", __func__); ++ cpwm_int_hdl(padapter, &report); ++#else ++ DBG_871X("\n%s: FW already leave 32K!\n\n", __func__); ++ cpwm_event_callback(&pwrpriv->cpwm_event); ++#endif ++ return; ++ } ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ++ if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) ++ { ++ DBG_871X("%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm); ++ goto exit; ++ } ++ pwrpriv->brpwmtimeout = _TRUE; ++ rtw_set_rpwm(padapter, pwrpriv->rpwm); ++ pwrpriv->brpwmtimeout = _FALSE; ++ ++exit: ++ _exit_pwrlock(&pwrpriv->lock); ++} ++ ++/* ++ * This function is a timer handler, can't do any IO in it. ++ */ ++static void pwr_rpwm_timeout_handler(void *FunctionContext) ++{ ++ PADAPTER padapter; ++ struct pwrctrl_priv *pwrpriv; ++ ++ ++ padapter = (PADAPTER)FunctionContext; ++ pwrpriv = adapter_to_pwrctl(padapter); ++// DBG_871X("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); ++ ++ if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) ++ { ++ DBG_871X("+%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm); ++ return; ++ } ++ ++ _set_workitem(&pwrpriv->rpwmtimeoutwi); ++} ++#endif // CONFIG_LPS_RPWM_TIMER ++ ++__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag) ++{ ++ pwrctrl->alives |= tag; ++} ++ ++__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag) ++{ ++ pwrctrl->alives &= ~tag; ++} ++ ++/* ++ * Caller: rtw_xmit_thread ++ * ++ * Check if the fw_pwrstate is okay for xmit. ++ * If not (cpwm is less than S3), then the sub-routine ++ * will raise the cpwm to be greater than or equal to S3. ++ * ++ * Calling Context: Passive ++ * ++ * Return Value: ++ * _SUCCESS rtw_xmit_thread can write fifo/txcmd afterwards. ++ * _FAIL rtw_xmit_thread can not do anything. ++ */ ++s32 rtw_register_tx_alive(PADAPTER padapter) ++{ ++ s32 res; ++ struct pwrctrl_priv *pwrctrl; ++ u8 pslv; ++ ++_func_enter_; ++ ++ res = _SUCCESS; ++ pwrctrl = adapter_to_pwrctl(padapter); ++#ifdef CONFIG_BT_COEXIST ++ if (_TRUE == adapter_to_pwrctl(padapter)->btcoex_rfon) ++ pslv = PS_STATE_S3; ++ else ++#endif ++ { ++ pslv = PS_STATE_S2; ++ } ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, XMIT_ALIVE); ++ ++ if (pwrctrl->bFwCurrentInPSMode == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_register_tx_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if (pwrctrl->cpwm < pslv) ++ { ++ if (pwrctrl->cpwm < PS_STATE_S2) ++ res = _FAIL; ++ if (pwrctrl->rpwm < pslv) ++ rtw_set_rpwm(padapter, pslv); ++ } ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++ if (_FAIL == res) ++ { ++ if (pwrctrl->cpwm >= PS_STATE_S2) ++ res = _SUCCESS; ++ } ++#endif // CONFIG_DETECT_CPWM_BY_POLLING ++ ++_func_exit_; ++ ++ return res; ++} ++ ++/* ++ * Caller: rtw_cmd_thread ++ * ++ * Check if the fw_pwrstate is okay for issuing cmd. ++ * If not (cpwm should be is less than S2), then the sub-routine ++ * will raise the cpwm to be greater than or equal to S2. ++ * ++ * Calling Context: Passive ++ * ++ * Return Value: ++ * _SUCCESS rtw_cmd_thread can issue cmds to firmware afterwards. ++ * _FAIL rtw_cmd_thread can not do anything. ++ */ ++s32 rtw_register_cmd_alive(PADAPTER padapter) ++{ ++ s32 res; ++ struct pwrctrl_priv *pwrctrl; ++ u8 pslv; ++ ++_func_enter_; ++ ++ res = _SUCCESS; ++ pwrctrl = adapter_to_pwrctl(padapter); ++#ifdef CONFIG_BT_COEXIST ++ if (_TRUE == adapter_to_pwrctl(padapter)->btcoex_rfon) ++ pslv = PS_STATE_S3; ++ else ++#endif ++ { ++ pslv = PS_STATE_S2; ++ } ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, CMD_ALIVE); ++ ++ if (pwrctrl->bFwCurrentInPSMode == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, ++ ("rtw_register_cmd_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if (pwrctrl->cpwm < pslv) ++ { ++ if (pwrctrl->cpwm < PS_STATE_S2) ++ res = _FAIL; ++ if (pwrctrl->rpwm < pslv) ++ rtw_set_rpwm(padapter, pslv); ++ } ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++ if (_FAIL == res) ++ { ++ if (pwrctrl->cpwm >= PS_STATE_S2) ++ res = _SUCCESS; ++ } ++#endif // CONFIG_DETECT_CPWM_BY_POLLING ++ ++_func_exit_; ++ ++ return res; ++} ++ ++/* ++ * Caller: rx_isr ++ * ++ * Calling Context: Dispatch/ISR ++ * ++ * Return Value: ++ * _SUCCESS ++ * _FAIL ++ */ ++s32 rtw_register_rx_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, RECV_ALIVE); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_register_rx_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++/* ++ * Caller: evt_isr or evt_thread ++ * ++ * Calling Context: Dispatch/ISR or Passive ++ * ++ * Return Value: ++ * _SUCCESS ++ * _FAIL ++ */ ++s32 rtw_register_evt_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, EVT_ALIVE); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_register_evt_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++/* ++ * Caller: ISR ++ * ++ * If ISR's txdone, ++ * No more pkts for TX, ++ * Then driver shall call this fun. to power down firmware again. ++ */ ++void rtw_unregister_tx_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, XMIT_ALIVE); ++ ++ if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) && ++ (pwrctrl->bFwCurrentInPSMode == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("%s: cpwm=0x%02x alives=0x%08x\n", ++ __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if ((pwrctrl->alives == 0) && ++ (pwrctrl->cpwm > PS_STATE_S0)) ++ { ++ rtw_set_rpwm(padapter, PS_STATE_S0); ++ } ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++} ++ ++/* ++ * Caller: ISR ++ * ++ * If all commands have been done, ++ * and no more command to do, ++ * then driver shall call this fun. to power down firmware again. ++ */ ++void rtw_unregister_cmd_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, CMD_ALIVE); ++ ++ if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) && ++ (pwrctrl->bFwCurrentInPSMode == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, ++ ("%s: cpwm=0x%02x alives=0x%08x\n", ++ __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if ((pwrctrl->alives == 0) && ++ (pwrctrl->cpwm > PS_STATE_S0)) ++ { ++ rtw_set_rpwm(padapter, PS_STATE_S0); ++ } ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++} ++ ++/* ++ * Caller: ISR ++ */ ++void rtw_unregister_rx_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, RECV_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_unregister_rx_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++} ++ ++void rtw_unregister_evt_alive(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrl; ++ ++_func_enter_; ++ ++ pwrctrl = adapter_to_pwrctl(padapter); ++ ++ unregister_task_alive(pwrctrl, EVT_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ++ ("rtw_unregister_evt_alive: cpwm=0x%02x alives=0x%08x\n", ++ pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++} ++#endif /* CONFIG_LPS_LCLK */ ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++static void resume_workitem_callback(struct work_struct *work); ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++void rtw_init_pwrctrl_priv(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++#if defined(CONFIG_CONCURRENT_MODE) ++ if (padapter->adapter_type != PRIMARY_ADAPTER) ++ return; ++#endif ++ ++_func_enter_; ++ ++#ifdef PLATFORM_WINDOWS ++ pwrctrlpriv->pnp_current_pwr_state=NdisDeviceStateD0; ++#endif ++ ++ _init_pwrlock(&pwrctrlpriv->lock); ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ pwrctrlpriv->ips_enter_cnts=0; ++ pwrctrlpriv->ips_leave_cnts=0; ++ pwrctrlpriv->bips_processing = _FALSE; ++ ++ pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; ++ pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; ++ ++ pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; ++ pwrctrlpriv->pwr_state_check_cnts = 0; ++ pwrctrlpriv->bInternalAutoSuspend = _FALSE; ++ pwrctrlpriv->bInSuspend = _FALSE; ++ pwrctrlpriv->bkeepfwalive = _FALSE; ++ ++#ifdef CONFIG_AUTOSUSPEND ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ pwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ?1000:2000; ++#endif ++#endif ++ ++ pwrctrlpriv->LpsIdleCount = 0; ++ //pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; ++ if (padapter->registrypriv.mp_mode == 1) ++ pwrctrlpriv->power_mgnt =PS_MODE_ACTIVE ; ++ else ++ pwrctrlpriv->power_mgnt =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; ++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; ++ ++ pwrctrlpriv->bFwCurrentInPSMode = _FALSE; ++ ++ pwrctrlpriv->rpwm = 0; ++ pwrctrlpriv->cpwm = PS_STATE_S4; ++ ++ pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE; ++ pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps; ++ pwrctrlpriv->bcn_ant_mode = 0; ++ ++ pwrctrlpriv->tog = 0x80; ++ ++ pwrctrlpriv->btcoex_rfon = _FALSE; ++ ++#ifdef CONFIG_LPS_LCLK ++ rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm)); ++ ++ _init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL); ++ ++#ifdef CONFIG_LPS_RPWM_TIMER ++ pwrctrlpriv->brpwmtimeout = _FALSE; ++ _init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL); ++ _init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter->pnetdev, pwr_rpwm_timeout_handler, padapter); ++#endif // CONFIG_LPS_RPWM_TIMER ++#endif // CONFIG_LPS_LCLK ++ ++#ifdef PLATFORM_LINUX ++ _init_timer(&(pwrctrlpriv->pwr_state_check_timer), padapter->pnetdev, pwr_state_check_handler, (u8 *)padapter); ++#endif ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL); ++ pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue"); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ pwrctrlpriv->early_suspend.suspend = NULL; ++ rtw_register_early_suspend(pwrctrlpriv); ++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER ++ ++ ++_func_exit_; ++ ++} ++ ++ ++void rtw_free_pwrctrl_priv(PADAPTER adapter) ++{ ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); ++ ++#if defined(CONFIG_CONCURRENT_MODE) ++ if (adapter->adapter_type != PRIMARY_ADAPTER) ++ return; ++#endif ++ ++_func_enter_; ++ ++ //_rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); ++ ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ if (pwrctrlpriv->rtw_workqueue) { ++ flush_workqueue(pwrctrlpriv->rtw_workqueue); ++ destroy_workqueue(pwrctrlpriv->rtw_workqueue); ++ } ++ #endif ++ ++ ++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(pwrctrlpriv); ++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER ++ ++ _free_pwrlock(&pwrctrlpriv->lock); ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++extern int rtw_resume_process(_adapter *padapter); ++#endif ++static void resume_workitem_callback(struct work_struct *work) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work); ++ struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); ++ _adapter *adapter = dvobj->if1; ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ rtw_resume_process(adapter); ++ #endif ++ ++} ++ ++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv) ++{ ++ // accquire system's suspend lock preventing from falliing asleep while resume in workqueue ++ rtw_lock_suspend(); ++ ++ #if 1 ++ queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work); ++ #else ++ _set_workitem(&pwrpriv->resume_work); ++ #endif ++} ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv) ++{ ++ return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE; ++} ++ ++inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv) ++{ ++ return (pwrpriv->do_late_resume) ? _TRUE : _FALSE; ++} ++ ++inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable) ++{ ++ pwrpriv->do_late_resume = enable; ++} ++#endif ++ ++#ifdef CONFIG_HAS_EARLYSUSPEND ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++extern int rtw_resume_process(_adapter *padapter); ++#endif ++static void rtw_early_suspend(struct early_suspend *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++} ++ ++static void rtw_late_resume(struct early_suspend *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); ++ _adapter *adapter = dvobj->if1; ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ if(pwrpriv->do_late_resume) { ++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++ rtw_resume_process(adapter); ++ #endif ++ } ++} ++ ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit ++ pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; ++ pwrpriv->early_suspend.suspend = rtw_early_suspend; ++ pwrpriv->early_suspend.resume = rtw_late_resume; ++ register_early_suspend(&pwrpriv->early_suspend); ++} ++ ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++ ++ if (pwrpriv->early_suspend.suspend) ++ unregister_early_suspend(&pwrpriv->early_suspend); ++ ++ pwrpriv->early_suspend.suspend = NULL; ++ pwrpriv->early_suspend.resume = NULL; ++} ++#endif //CONFIG_HAS_EARLYSUSPEND ++ ++#ifdef CONFIG_ANDROID_POWER ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++extern int rtw_resume_process(PADAPTER padapter); ++#endif ++static void rtw_early_suspend(android_early_suspend_t *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++} ++ ++static void rtw_late_resume(android_early_suspend_t *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); ++ _adapter *adapter = dvobj->if1; ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ if(pwrpriv->do_late_resume) { ++ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++ rtw_resume_process(adapter); ++ #endif ++ } ++} ++ ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit ++ pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; ++ pwrpriv->early_suspend.suspend = rtw_early_suspend; ++ pwrpriv->early_suspend.resume = rtw_late_resume; ++ android_register_early_suspend(&pwrpriv->early_suspend); ++} ++ ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++ ++ if (pwrpriv->early_suspend.suspend) ++ android_unregister_early_suspend(&pwrpriv->early_suspend); ++ ++ pwrpriv->early_suspend.suspend = NULL; ++ pwrpriv->early_suspend.resume = NULL; ++} ++#endif //CONFIG_ANDROID_POWER ++ ++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val) ++{ ++ u8 bResult = _TRUE; ++ rtw_hal_intf_ps_func(padapter,efunc_id,val); ++ ++ return bResult; ++} ++ ++ ++inline void rtw_set_ips_deny(_adapter *padapter, u32 ms) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms); ++} ++ ++/* ++* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend ++* @adapter: pointer to _adapter structure ++* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup ++* Return _SUCCESS or _FAIL ++*/ ++ ++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int ret = _SUCCESS; ++ u32 start = rtw_get_current_time(); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->pbuddy_adapter) ++ LeaveAllPowerSaveMode(padapter->pbuddy_adapter); ++ ++ if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){ ++ padapter = padapter->pbuddy_adapter; ++ pmlmepriv = &padapter->mlmepriv; ++ } ++#endif ++ ++ if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) ++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); ++ ++ ++ if (pwrpriv->ps_processing) { ++ DBG_871X("%s wait ps_processing...\n", __func__); ++ while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000) ++ rtw_msleep_os(10); ++ if (pwrpriv->ps_processing) ++ DBG_871X("%s wait ps_processing timeout\n", __func__); ++ else ++ DBG_871X("%s wait ps_processing done\n", __func__); ++ } ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ if (rtw_hal_sreset_inprogress(padapter)) { ++ DBG_871X("%s wait sreset_inprogress...\n", __func__); ++ while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000) ++ rtw_msleep_os(10); ++ if (rtw_hal_sreset_inprogress(padapter)) ++ DBG_871X("%s wait sreset_inprogress timeout\n", __func__); ++ else ++ DBG_871X("%s wait sreset_inprogress done\n", __func__); ++ } ++#endif ++ ++ if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) { ++ DBG_871X("%s wait bInSuspend...\n", __func__); ++ while (pwrpriv->bInSuspend ++ && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv)) ++ || (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv))) ++ ) { ++ rtw_msleep_os(10); ++ } ++ if (pwrpriv->bInSuspend) ++ DBG_871X("%s wait bInSuspend timeout\n", __func__); ++ else ++ DBG_871X("%s wait bInSuspend done\n", __func__); ++ } ++ ++ //System suspend is not allowed to wakeup ++ if((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend )){ ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //block??? ++ if((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //I think this should be check in IPS, LPS, autosuspend functions... ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ if(_TRUE==pwrpriv->bInternalAutoSuspend){ ++ if(0==pwrpriv->autopm_cnt){ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ if (usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf) < 0) ++ { ++ DBG_871X( "can't get autopm: \n"); ++ } ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_disable(adapter_to_dvobj(padapter)->pusbintf); ++ #else ++ usb_autoresume_device(adapter_to_dvobj(padapter)->pusbdev, 1); ++ #endif ++ pwrpriv->autopm_cnt++; ++ } ++#endif //#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ ret = _SUCCESS; ++ goto exit; ++#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ } ++#endif //#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) ++ } ++ ++ if(rf_off == pwrpriv->rf_pwrstate ) ++ { ++#ifdef CONFIG_USB_HCI ++#ifdef CONFIG_AUTOSUSPEND ++ if(pwrpriv->brfoffbyhw==_TRUE) ++ { ++ DBG_8192C("hw still in rf_off state ...........\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ else if(padapter->registrypriv.usbss_enable) ++ { ++ DBG_8192C("%s call autoresume_enter....\n",__FUNCTION__); ++ if(_FAIL == autoresume_enter(padapter)) ++ { ++ DBG_8192C("======> autoresume fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ } ++ else ++#endif ++#endif ++ { ++#ifdef CONFIG_IPS ++ DBG_8192C("%s call ips_leave....\n",__FUNCTION__); ++ if(_FAIL == ips_leave(padapter)) ++ { ++ DBG_8192C("======> ips_leave fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++#endif ++ } ++ } ++ ++ //TODO: the following checking need to be merged... ++ if(padapter->bDriverStopped ++ || !padapter->bup ++ || !padapter->hw_init_completed ++ ){ ++ DBG_8192C("%s: bDriverStopped=%d, bup=%d, hw_init_completed=%u\n" ++ , caller ++ , padapter->bDriverStopped ++ , padapter->bup ++ , padapter->hw_init_completed); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++exit: ++ if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) ++ pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); ++ return ret; ++ ++} ++ ++int rtw_pm_set_lps(_adapter *padapter, u8 mode) ++{ ++ int ret = 0; ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++ if ( mode < PS_MODE_NUM ) ++ { ++ if(pwrctrlpriv->power_mgnt !=mode) ++ { ++ if(PS_MODE_ACTIVE == mode) ++ { ++ LeaveAllPowerSaveMode(padapter); ++ } ++ else ++ { ++ pwrctrlpriv->LpsIdleCount = 2; ++ } ++ pwrctrlpriv->power_mgnt = mode; ++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; ++ } ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++int rtw_pm_set_ips(_adapter *padapter, u8 mode) ++{ ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++ if( mode == IPS_NORMAL || mode == IPS_LEVEL_2 ) { ++ rtw_ips_mode_req(pwrctrlpriv, mode); ++ DBG_871X("%s %s\n", __FUNCTION__, mode == IPS_NORMAL?"IPS_NORMAL":"IPS_LEVEL_2"); ++ return 0; ++ } ++ else if(mode ==IPS_NONE){ ++ rtw_ips_mode_req(pwrctrlpriv, mode); ++ DBG_871X("%s %s\n", __FUNCTION__, "IPS_NONE"); ++ if((padapter->bSurpriseRemoved ==0)&&(_FAIL == rtw_pwr_wakeup(padapter)) ) ++ return -EFAULT; ++ } ++ else { ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_recv.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_recv.c +new file mode 100644 +index 00000000..322ee4ea +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_recv.c +@@ -0,0 +1,4403 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_RECV_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS); ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ ++void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) ++{ ++ ++ ++_func_enter_; ++ ++ _rtw_memset((u8 *)psta_recvpriv, 0, sizeof (struct sta_recv_priv)); ++ ++ _rtw_spinlock_init(&psta_recvpriv->lock); ++ ++ //for(i=0; iblk_strms[i]); ++ ++ _rtw_init_queue(&psta_recvpriv->defrag_q); ++ ++_func_exit_; ++ ++} ++ ++sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) ++{ ++ sint i; ++ ++ union recv_frame *precvframe; ++ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); ++ ++ _rtw_spinlock_init(&precvpriv->lock); ++ ++ _rtw_init_queue(&precvpriv->free_recv_queue); ++ _rtw_init_queue(&precvpriv->recv_pending_queue); ++ _rtw_init_queue(&precvpriv->uc_swdec_pending_queue); ++ ++ precvpriv->adapter = padapter; ++ ++ precvpriv->free_recvframe_cnt = NR_RECVFRAME; ++ ++ rtw_os_recv_resource_init(precvpriv, padapter); ++ ++ precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ ++ if(precvpriv->pallocated_frame_buf==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ //_rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ ++ precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ); ++ //precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - ++ // ((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); ++ ++ precvframe = (union recv_frame*) precvpriv->precv_frame_buf; ++ ++ ++ for(i=0; i < NR_RECVFRAME ; i++) ++ { ++ _rtw_init_listhead(&(precvframe->u.list)); ++ ++ rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue)); ++ ++ res = rtw_os_recv_resource_alloc(padapter, precvframe); ++ ++ precvframe->u.hdr.len = 0; ++ ++ precvframe->u.hdr.adapter =padapter; ++ precvframe++; ++ ++ } ++ ++#ifdef CONFIG_USB_HCI ++ ++ precvpriv->rx_pending_cnt=1; ++ ++ _rtw_init_sema(&precvpriv->allrxreturnevt, 0); ++ ++#endif ++ ++ res = rtw_hal_init_recv_priv(padapter); ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ #ifdef PLATFORM_LINUX ++ _init_timer(&precvpriv->signal_stat_timer, padapter->pnetdev, RTW_TIMER_HDL_NAME(signal_stat), padapter); ++ #elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS) ++ _init_timer(&precvpriv->signal_stat_timer, padapter->hndis_adapter, RTW_TIMER_HDL_NAME(signal_stat), padapter); ++ #endif ++ ++ precvpriv->signal_stat_sampling_interval = 1000; //ms ++ //precvpriv->signal_stat_converging_constant = 5000; //ms ++ ++ rtw_set_signal_stat_timer(precvpriv); ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv); ++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) ++{ ++ _rtw_spinlock_free(&precvpriv->lock); ++#ifdef CONFIG_RECV_THREAD_MODE ++ _rtw_free_sema(&precvpriv->recv_sema); ++ _rtw_free_sema(&precvpriv->terminate_recvthread_sema); ++#endif ++ ++ _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); ++ _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock); ++ ++ _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock); ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ _rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++} ++ ++void _rtw_free_recv_priv (struct recv_priv *precvpriv) ++{ ++ _adapter *padapter = precvpriv->adapter; ++ ++_func_enter_; ++ ++ rtw_free_uc_swdec_pending_queue(padapter); ++ ++ rtw_mfree_recv_priv_lock(precvpriv); ++ ++ rtw_os_recv_resource_free(precvpriv); ++ ++ if(precvpriv->pallocated_frame_buf) { ++ rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ } ++ ++ rtw_hal_free_recv_priv(padapter); ++ ++_func_exit_; ++ ++} ++ ++union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue) ++{ ++ ++ union recv_frame *precvframe; ++ _list *plist, *phead; ++ _adapter *padapter; ++ struct recv_priv *precvpriv; ++_func_enter_; ++ ++ if(_rtw_queue_empty(pfree_recv_queue) == _TRUE) ++ { ++ precvframe = NULL; ++ } ++ else ++ { ++ phead = get_list_head(pfree_recv_queue); ++ ++ plist = get_next(phead); ++ ++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ rtw_list_delete(&precvframe->u.hdr.list); ++ padapter=precvframe->u.hdr.adapter; ++ if(padapter !=NULL){ ++ precvpriv=&padapter->recvpriv; ++ if(pfree_recv_queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt--; ++ } ++ } ++ ++_func_exit_; ++ ++ return precvframe; ++ ++} ++ ++union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue) ++{ ++ _irqL irqL; ++ union recv_frame *precvframe; ++ ++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++ precvframe = _rtw_alloc_recvframe(pfree_recv_queue); ++ ++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++ return precvframe; ++} ++ ++void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv) ++{ ++ /* Perry: This can be removed */ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ ++ precvframe->u.hdr.len=0; ++} ++ ++int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) ++{ ++ _irqL irqL; ++ _adapter *padapter=precvframe->u.hdr.adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++_func_enter_; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->adapter_type > PRIMARY_ADAPTER) ++ { ++ padapter = padapter->pbuddy_adapter;//get primary_padapter ++ precvpriv = &padapter->recvpriv; ++ pfree_recv_queue = &precvpriv->free_recv_queue; ++ precvframe->u.hdr.adapter = padapter; ++ } ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ rtw_os_read_port(padapter, precvframe->u.hdr.precvbuf); ++#endif ++ ++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) ++ ++ if(precvframe->u.hdr.pkt) ++ { ++#ifdef CONFIG_BSD_RX_USE_MBUF ++ m_freem(precvframe->u.hdr.pkt); ++#else // CONFIG_BSD_RX_USE_MBUF ++ rtw_skb_free(precvframe->u.hdr.pkt);//free skb by driver ++#endif // CONFIG_BSD_RX_USE_MBUF ++ precvframe->u.hdr.pkt = NULL; ++ } ++ ++#endif //defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) ++ ++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++ rtw_list_delete(&(precvframe->u.hdr.list)); ++ ++ precvframe->u.hdr.len = 0; ++ ++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue)); ++ ++ if(padapter !=NULL){ ++ if(pfree_recv_queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt++; ++ } ++ ++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++ ++ ++ ++sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) ++{ ++ ++ _adapter *padapter=precvframe->u.hdr.adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++_func_enter_; ++ ++ //_rtw_init_listhead(&(precvframe->u.hdr.list)); ++ rtw_list_delete(&(precvframe->u.hdr.list)); ++ ++ ++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue)); ++ ++ if (padapter != NULL) { ++ if (queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt++; ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) ++{ ++ sint ret; ++ _irqL irqL; ++ ++ //_spinlock(&pfree_recv_queue->lock); ++ _enter_critical_bh(&queue->lock, &irqL); ++ ret = _rtw_enqueue_recvframe(precvframe, queue); ++ //_rtw_spinunlock(&pfree_recv_queue->lock); ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ return ret; ++} ++ ++/* ++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) ++{ ++ return rtw_free_recvframe(precvframe, queue); ++} ++*/ ++ ++ ++ ++ ++/* ++caller : defrag ; recvframe_chk_defrag in recv_thread (passive) ++pframequeue: defrag_queue : will be accessed in recv_thread (passive) ++ ++using spinlock to protect ++ ++*/ ++ ++void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) ++{ ++ union recv_frame *precvframe; ++ _list *plist, *phead; ++ ++_func_enter_; ++ _rtw_spinlock(&pframequeue->lock); ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ plist = get_next(plist); ++ ++ //rtw_list_delete(&precvframe->u.hdr.list); // will do this in rtw_free_recvframe() ++ ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ } ++ ++ _rtw_spinunlock(&pframequeue->lock); ++ ++_func_exit_; ++ ++} ++ ++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter) ++{ ++ u32 cnt = 0; ++ union recv_frame *pending_frame; ++ while((pending_frame=rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) { ++ rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue); ++ cnt++; ++ } ++ ++ if (cnt) ++ DBG_871X(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt); ++ ++ return cnt; ++} ++ ++ ++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_delete(&precvbuf->list); ++ rtw_list_insert_head(&precvbuf->list, get_list_head(queue)); ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ return _SUCCESS; ++} ++ ++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue) ++{ ++ _irqL irqL; ++#ifdef CONFIG_SDIO_HCI ++ _enter_critical_bh(&queue->lock, &irqL); ++#else ++ _enter_critical_ex(&queue->lock, &irqL); ++#endif/*#ifdef CONFIG_SDIO_HCI*/ ++ ++ rtw_list_delete(&precvbuf->list); ++ ++ rtw_list_insert_tail(&precvbuf->list, get_list_head(queue)); ++#ifdef CONFIG_SDIO_HCI ++ _exit_critical_bh(&queue->lock, &irqL); ++#else ++ _exit_critical_ex(&queue->lock, &irqL); ++#endif/*#ifdef CONFIG_SDIO_HCI*/ ++ return _SUCCESS; ++ ++} ++ ++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue) ++{ ++ _irqL irqL; ++ struct recv_buf *precvbuf; ++ _list *plist, *phead; ++ ++#ifdef CONFIG_SDIO_HCI ++ _enter_critical_bh(&queue->lock, &irqL); ++#else ++ _enter_critical_ex(&queue->lock, &irqL); ++#endif/*#ifdef CONFIG_SDIO_HCI*/ ++ ++ if(_rtw_queue_empty(queue) == _TRUE) ++ { ++ precvbuf = NULL; ++ } ++ else ++ { ++ phead = get_list_head(queue); ++ ++ plist = get_next(phead); ++ ++ precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list); ++ ++ rtw_list_delete(&precvbuf->list); ++ ++ } ++ ++#ifdef CONFIG_SDIO_HCI ++ _exit_critical_bh(&queue->lock, &irqL); ++#else ++ _exit_critical_ex(&queue->lock, &irqL); ++#endif/*#ifdef CONFIG_SDIO_HCI*/ ++ ++ return precvbuf; ++ ++} ++ ++sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe); ++sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe){ ++ ++ sint i,res=_SUCCESS; ++ u32 datalen; ++ u8 miccode[8]; ++ u8 bmic_err=_FALSE,brpt_micerror = _TRUE; ++ u8 *pframe, *payload,*pframemic; ++ u8 *mickey; ++ //u8 *iv,rxdata_key_idx=0; ++ struct sta_info *stainfo; ++ struct rx_pkt_attrib *prxattrib=&precvframe->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&adapter->securitypriv; ++ ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++_func_enter_; ++ ++ stainfo=rtw_get_stainfo(&adapter->stapriv ,&prxattrib->ta[0]); ++ ++ if(prxattrib->encrypt ==_TKIP_) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n")); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2],prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5])); ++ ++ //calculate mic code ++ if(stainfo!= NULL) ++ { ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ //mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; ++ //iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; ++ //rxdata_key_idx =( ((iv[3])>>6)&0x3) ; ++ mickey=&psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0]; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic: bcmc key \n")); ++ //DBG_871X("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", ++ // psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); ++ ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n")); ++ DBG_871X("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"); ++ goto exit; ++ } ++ } ++ else{ ++ mickey=&stainfo->dot11tkiprxmickey.skey[0]; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic: unicast key \n")); ++ } ++ ++ datalen=precvframe->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len-prxattrib->icv_len-8;//icv_len included the mic code ++ pframe=precvframe->u.hdr.rx_data; ++ payload=pframe+prxattrib->hdrlen+prxattrib->iv_len; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n",prxattrib->iv_len,prxattrib->icv_len)); ++ ++ //rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data ++ ++ rtw_seccalctkipmic(mickey,pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data ++ ++ pframemic=payload+datalen; ++ ++ bmic_err=_FALSE; ++ ++ for(i=0;i<8;i++){ ++ if(miccode[i] != *(pframemic+i)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ",i,miccode[i],i,*(pframemic+i))); ++ bmic_err=_TRUE; ++ } ++ } ++ ++ ++ if(bmic_err==_TRUE){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ *(pframemic-8),*(pframemic-7),*(pframemic-6),*(pframemic-5),*(pframemic-4),*(pframemic-3),*(pframemic-2),*(pframemic-1))); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ *(pframemic-16),*(pframemic-15),*(pframemic-14),*(pframemic-13),*(pframemic-12),*(pframemic-11),*(pframemic-10),*(pframemic-9))); ++ ++ { ++ uint i; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet (len=%d)======\n",precvframe->u.hdr.len)); ++ for(i=0;iu.hdr.len;i=i+8){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x", ++ *(precvframe->u.hdr.rx_data+i),*(precvframe->u.hdr.rx_data+i+1), ++ *(precvframe->u.hdr.rx_data+i+2),*(precvframe->u.hdr.rx_data+i+3), ++ *(precvframe->u.hdr.rx_data+i+4),*(precvframe->u.hdr.rx_data+i+5), ++ *(precvframe->u.hdr.rx_data+i+6),*(precvframe->u.hdr.rx_data+i+7))); ++ } ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet end [len=%d]======\n",precvframe->u.hdr.len)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n hrdlen=%d, \n",prxattrib->hdrlen)); ++ } ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ", ++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2], ++ prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5],psecuritypriv->binstallGrpkey)); ++ ++ // double check key_index for some timing issue , ++ // cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue ++ if((IS_MCAST(prxattrib->ra)==_TRUE) && (prxattrib->key_index != pmlmeinfo->key_index )) ++ brpt_micerror = _FALSE; ++ ++ if((prxattrib->bdecrypted ==_TRUE)&& (brpt_micerror == _TRUE)) ++ { ++ rtw_handle_tkip_mic_err(adapter,(u8)IS_MCAST(prxattrib->ra)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); ++ DBG_871X(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); ++ DBG_871X(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); ++ } ++ ++ res=_FAIL; ++ ++ } ++ else{ ++ //mic checked ok ++ if((psecuritypriv->bcheck_grpkey ==_FALSE)&&(IS_MCAST(prxattrib->ra)==_TRUE)){ ++ psecuritypriv->bcheck_grpkey =_TRUE; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->bcheck_grpkey =_TRUE")); ++ } ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n")); ++ } ++ ++ recvframe_pull_tail(precvframe, 8); ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++//decrypt and set the ivlen,icvlen of the recv_frame ++union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame); ++union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame) ++{ ++ ++ struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ union recv_frame *return_packet=precv_frame; ++ u32 res=_SUCCESS; ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n",prxattrib->bdecrypted,prxattrib->encrypt)); ++ ++ if(prxattrib->encrypt>0) ++ { ++ u8 *iv = precv_frame->u.hdr.rx_data+prxattrib->hdrlen; ++ prxattrib->key_index = ( ((iv[3])>>6)&0x3) ; ++ ++ if(prxattrib->key_index > WEP_KEYS) ++ { ++ DBG_871X("prxattrib->key_index(%d) > WEP_KEYS \n", prxattrib->key_index); ++ ++ switch(prxattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case _TKIP_: ++ case _AES_: ++ default: ++ prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid; ++ break; ++ } ++ } ++ } ++ ++ if((prxattrib->encrypt>0) && ((prxattrib->bdecrypted==0) ||(psecuritypriv->sw_decrypt==_TRUE))) ++ { ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(!IS_MCAST(prxattrib->ra))//bc/mc packets use sw decryption for concurrent mode ++#endif ++ psecuritypriv->hw_decrypted=_FALSE; ++ ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ ++ switch(prxattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ rtw_wep_decrypt(padapter, (u8 *)precv_frame); ++ break; ++ case _TKIP_: ++ res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame); ++ break; ++ case _AES_: ++ res = rtw_aes_decrypt(padapter, (u8 * )precv_frame); ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ rtw_sms4_decrypt(padapter, (u8 * )precv_frame); ++ break; ++#endif ++ default: ++ break; ++ } ++ } ++ else if(prxattrib->bdecrypted==1 ++ && prxattrib->encrypt >0 ++ && (psecuritypriv->busetkipkey==1 || prxattrib->encrypt !=_TKIP_ ) ++ ) ++ { ++#if 0 ++ if((prxstat->icv==1)&&(prxattrib->encrypt!=_AES_)) ++ { ++ psecuritypriv->hw_decrypted=_FALSE; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->hw_decrypted=_FALSE")); ++ ++ rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue); ++ ++ return_packet=NULL; ++ ++ } ++ else ++#endif ++ { ++ psecuritypriv->hw_decrypted=_TRUE; ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ ++ } ++ } ++ else { ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, psecuritypriv->hw_decrypted:%d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ } ++ ++ if(res == _FAIL) ++ { ++ rtw_free_recvframe(return_packet,&padapter->recvpriv.free_recv_queue); ++ return_packet = NULL; ++ ++ } ++ else{ ++ prxattrib->bdecrypted = _TRUE; ++ } ++ //recvframe_chkmic(adapter, precv_frame); //move to recvframme_defrag function ++ ++_func_exit_; ++ ++ return return_packet; ++ ++} ++//###set the security information in the recv_frame ++union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame); ++union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame) ++{ ++ u8 *psta_addr, *ptr; ++ uint auth_alg; ++ struct recv_frame_hdr *pfhdr; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv ; ++ union recv_frame *prtnframe; ++ u16 ether_type=0; ++ u16 eapol_type = 0x888e;//for Funia BD's WPA issue ++ struct rx_pkt_attrib *pattrib; ++ ++_func_enter_; ++ ++ pstapriv = &adapter->stapriv; ++ ++ auth_alg = adapter->securitypriv.dot11AuthAlgrthm; ++ ++ ptr = get_recvframe_data(precv_frame); ++ pfhdr = &precv_frame->u.hdr; ++ pattrib = &pfhdr->attrib; ++ psta_addr = pattrib->ta; ++ ++ prtnframe = NULL; ++ ++ psta = rtw_get_stainfo(pstapriv, psta_addr); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:adapter->securitypriv.dot11AuthAlgrthm=%d\n",adapter->securitypriv.dot11AuthAlgrthm)); ++ ++ if(auth_alg==2) ++ { ++ if ((psta!=NULL) && (psta->ieee8021x_blocked)) ++ { ++ //blocked ++ //only accept EAPOL frame ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==1\n")); ++ ++ prtnframe=precv_frame; ++ ++ //get ether_type ++ ptr=ptr+pfhdr->attrib.hdrlen+pfhdr->attrib.iv_len+LLC_HEADER_SIZE; ++ _rtw_memcpy(ðer_type,ptr, 2); ++ ether_type= ntohs((unsigned short )ether_type); ++ ++ if (ether_type == eapol_type) { ++ prtnframe=precv_frame; ++ } ++ else { ++ //free this frame ++ rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue); ++ prtnframe=NULL; ++ } ++ } ++ else ++ { ++ //allowed ++ //check decryption status, and decrypt the frame if needed ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==0\n")); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:precv_frame->hdr.attrib.privacy=%x\n",precv_frame->u.hdr.attrib.privacy)); ++ ++ if (pattrib->bdecrypted == 0) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted)); ++ } ++ ++ prtnframe=precv_frame; ++ //check is the EAPOL frame or not (Rekey) ++ if(ether_type == eapol_type){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("########portctrl:ether_type == 0x888e\n")); ++ //check Rekey ++ ++ prtnframe=precv_frame; ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:ether_type=0x%04x\n", ether_type)); ++ } ++ } ++ } ++ else ++ { ++ prtnframe=precv_frame; ++ } ++ ++_func_exit_; ++ ++ return prtnframe; ++ ++} ++ ++sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache); ++sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) ++{ ++ sint tid = precv_frame->u.hdr.attrib.priority; ++ ++ u16 seq_ctrl = ( (precv_frame->u.hdr.attrib.seq_num&0xffff) << 4) | ++ (precv_frame->u.hdr.attrib.frag_num & 0xf); ++ ++_func_enter_; ++ ++ if(tid>15) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid)); ++ ++ return _FAIL; ++ } ++ ++ if(1)//if(bretry) ++ { ++ if(seq_ctrl == prxcache->tid_rxseq[tid]) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid])); ++ ++ return _FAIL; ++ } ++ } ++ ++ prxcache->tid_rxseq[tid] = seq_ctrl; ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame); ++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ unsigned char pwrbit; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL; ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ ++ pwrbit = GetPwrMgt(ptr); ++ ++ if(psta) ++ { ++ if(pwrbit) ++ { ++ if(!(psta->state & WIFI_SLEEP_STATE)) ++ { ++ //psta->state |= WIFI_SLEEP_STATE; ++ //pstapriv->sta_dz_bitmap |= BIT(psta->aid); ++ ++ stop_sta_xmit(padapter, psta); ++ ++ //DBG_871X("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); ++ } ++ } ++ else ++ { ++ if(psta->state & WIFI_SLEEP_STATE) ++ { ++ //psta->state ^= WIFI_SLEEP_STATE; ++ //pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); ++ ++ wakeup_sta_to_xmit(padapter, psta); ++ ++ //DBG_871X("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); ++ } ++ } ++ ++ } ++ ++#endif ++} ++ ++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); ++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL; ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ ++ if(!psta) return; ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE ) ) ++ { ++#endif //CONFIG_TDLS ++ ++ if(!psta->qos_option) ++ return; ++ ++ if(!(psta->qos_info&0xf)) ++ return; ++ ++#ifdef CONFIG_TDLS ++ } ++#endif //CONFIG_TDLS ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ { ++ u8 wmmps_ac=0; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ if(wmmps_ac) ++ { ++ if(psta->sleepq_ac_len>0) ++ { ++ //process received triggered frame ++ xmit_delivery_enabled_frames(padapter, psta); ++ } ++ else ++ { ++ //issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) ++ issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0); ++ } ++ } ++ ++ } ++ ++ ++#endif ++ ++} ++ ++#ifdef CONFIG_TDLS ++sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ sint ret = _SUCCESS; ++ u8 *paction = get_recvframe_data(precv_frame); ++ u8 category_field = 1; ++#ifdef CONFIG_WFD ++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a }; ++#endif //CONFIG_WFD ++ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); ++ ++ //point to action field ++ paction+=pattrib->hdrlen ++ + pattrib->iv_len ++ + SNAP_SIZE ++ + ETH_TYPE_LEN ++ + PAYLOAD_TYPE_LEN ++ + category_field; ++ ++ if(ptdlsinfo->enable == 0) ++ { ++ DBG_871X("recv tdls frame, " ++ "but tdls haven't enabled\n"); ++ ret = _FAIL; ++ return ret; ++ } ++ ++ switch(*paction){ ++ case TDLS_SETUP_REQUEST: ++ DBG_871X("recv tdls setup request frame\n"); ++ ret=On_TDLS_Setup_Req(adapter, precv_frame); ++ break; ++ case TDLS_SETUP_RESPONSE: ++ DBG_871X("recv tdls setup response frame\n"); ++ ret=On_TDLS_Setup_Rsp(adapter, precv_frame); ++ break; ++ case TDLS_SETUP_CONFIRM: ++ DBG_871X("recv tdls setup confirm frame\n"); ++ ret=On_TDLS_Setup_Cfm(adapter, precv_frame); ++ break; ++ case TDLS_TEARDOWN: ++ DBG_871X("recv tdls teardown, free sta_info\n"); ++ ret=On_TDLS_Teardown(adapter, precv_frame); ++ break; ++ case TDLS_DISCOVERY_REQUEST: ++ DBG_871X("recv tdls discovery request frame\n"); ++ ret=On_TDLS_Dis_Req(adapter, precv_frame); ++ break; ++ case TDLS_PEER_TRAFFIC_RESPONSE: ++ DBG_871X("recv tdls peer traffic response frame\n"); ++ ret=On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ DBG_871X("recv tdls channel switch request frame\n"); ++ ret=On_TDLS_Ch_Switch_Req(adapter, precv_frame); ++ break; ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ DBG_871X("recv tdls channel switch response frame\n"); ++ ret=On_TDLS_Ch_Switch_Rsp(adapter, precv_frame); ++ break; ++#ifdef CONFIG_WFD ++ case 0x50: //First byte of WFA OUI ++ if( _rtw_memcmp(WFA_OUI, (paction), 3) ) ++ { ++ if( *(paction + 3) == 0x04) //Probe request frame ++ { ++ //WFDTDLS: for sigma test, do not setup direct link automatically ++ ptdlsinfo->dev_discovered = 1; ++ DBG_871X("recv tunneled probe request frame\n"); ++ issue_tunneled_probe_rsp(adapter, precv_frame); ++ } ++ if( *(paction + 3) == 0x05) //Probe response frame ++ { ++ //WFDTDLS: for sigma test, do not setup direct link automatically ++ ptdlsinfo->dev_discovered = 1; ++ DBG_871X("recv tunneled probe response frame\n"); ++ } ++ } ++ break; ++#endif //CONFIG_WFD ++ default: ++ DBG_871X("receive TDLS frame but not supported\n"); ++ ret=_FAIL; ++ break; ++ } ++ ++exit: ++ return ret; ++ ++} ++#endif ++ ++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta); ++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta) ++{ ++ int sz; ++ struct sta_info *psta = NULL; ++ struct stainfo_stats *pstats = NULL; ++ struct rx_pkt_attrib *pattrib = & prframe->u.hdr.attrib; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ sz = get_recvframe_len(prframe); ++ precvpriv->rx_bytes += sz; ++ ++ padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++; ++ ++ if( (!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst))){ ++ padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++; ++ } ++ ++ if(sta) ++ psta = sta; ++ else ++ psta = prframe->u.hdr.psta; ++ ++ if(psta) ++ { ++ pstats = &psta->sta_stats; ++ ++ pstats->rx_data_pkts++; ++ pstats->rx_bytes += sz; ++ } ++ ++} ++ ++sint sta2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ++); ++sint sta2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ++) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ sint ret = _SUCCESS; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 *mybssid = get_bssid(pmlmepriv); ++ u8 *myhwaddr = myid(&adapter->eeprompriv); ++ u8 * sta_addr = NULL; ++ sint bmcast = IS_MCAST(pattrib->dst); ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta=NULL; ++ u8 *psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ //frame body located after [+2]: ether-type, [+1]: payload type ++ u8 *pframe_body = psnap_type+2+1; ++#endif ++ ++_func_enter_; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if( (!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast) ){ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->src; ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++#ifdef CONFIG_TDLS ++ ++ //direct link data transfer ++ if(ptdlsinfo->setup_state == TDLS_LINKED_STATE){ ++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); ++ if(ptdls_sta==NULL) ++ { ++ ret=_FAIL; ++ goto exit; ++ } ++ else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE) ++ { ++ ++ //drop QoS-SubType Data, including QoS NULL, excluding QoS-Data ++ if( (GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE )== WIFI_QOS_DATA_TYPE) ++ { ++ if(GetFrameSubType(ptr)&(BIT(4)|BIT(5)|BIT(6))) ++ { ++ DBG_871X("drop QoS-Sybtype Data\n"); ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ ret= _FAIL; ++ goto exit; ++ } ++ // da should be for me ++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast)) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ // check BSSID ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //process UAPSD tdls sta ++ process_pwrbit_data(adapter, precv_frame); ++ ++ // if NULL-frame, check pwrbit ++ if ((GetFrameSubType(ptr)) == WIFI_DATA_NULL) ++ { ++ //NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA ++ if(GetPwrMgt(ptr)) ++ { ++ DBG_871X("TDLS: recv peer null frame with pwr bit 1\n"); ++ ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; ++ // it would be triggered when we are off channel and receiving NULL DATA ++ // we can confirm that peer STA is at off channel ++ } ++ else if(ptdls_sta->tdls_sta_state&TDLS_CH_SWITCH_ON_STATE) ++ { ++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE) ++ { ++ issue_nulldata_to_TDLS_peer_STA(adapter, ptdls_sta, 0); ++ ptdls_sta->tdls_sta_state |= TDLS_PEER_AT_OFF_STATE; ++ On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); ++ } ++ } ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ //receive some of all TDLS management frames, process it at ON_TDLS ++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2))){ ++ ret= OnTDLS(adapter, precv_frame); ++ goto exit; ++ } ++ ++ } ++ ++ sta_addr = pattrib->src; ++ ++ } ++ else ++#endif //CONFIG_TDLS ++ { ++ // For Station mode, sa and bssid should always be BSSID, and DA is my mac-address ++ if(!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN) ) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("bssid != TA under STATION_MODE; drop pkt\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->bssid; ++ } ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ if (bmcast) ++ { ++ // For AP mode, if DA == MCAST, then BSSID should be also MCAST ++ if (!IS_MCAST(pattrib->bssid)){ ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ else // not mc-frame ++ { ++ // For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID ++ if(!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->src; ++ } ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ sta_addr = mybssid; ++ } ++ else ++ { ++ ret = _FAIL; ++ } ++ ++ ++ ++ if(bmcast) ++ *psta = rtw_get_bcmc_stainfo(adapter); ++ else ++ *psta = rtw_get_stainfo(pstapriv, sta_addr); // get ap_info ++ ++#ifdef CONFIG_TDLS ++ if(ptdls_sta != NULL) ++ *psta = ptdls_sta; ++#endif //CONFIG_TDLS ++ ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under sta2sta_data_frame ; drop pkt\n")); ++#ifdef CONFIG_MP_INCLUDED ++ if (adapter->registrypriv.mp_mode == 1) ++ { ++ if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ adapter->mppriv.rx_pktloss++; ++ } ++#endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++exit: ++_func_exit_; ++ return ret; ++ ++} ++ ++sint ap2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ); ++sint ap2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ sint ret = _SUCCESS; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 *mybssid = get_bssid(pmlmepriv); ++ u8 *myhwaddr = myid(&adapter->eeprompriv); ++ sint bmcast = IS_MCAST(pattrib->dst); ++ ++_func_enter_; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ++ || check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE ) ++ ) ++ { ++ ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n", ++ __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // da should be for me ++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_, ++ (" ap2sta_data_frame: compare DA fail; DA="MAC_FMT"\n", MAC_ARG(pattrib->dst))); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst)); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ ++ // check BSSID ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_, ++ (" ap2sta_data_frame: compare BSSID fail ; BSSID="MAC_FMT"\n", MAC_ARG(pattrib->bssid))); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("mybssid="MAC_FMT"\n", MAC_ARG(mybssid))); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n", ++ __FUNCTION__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); ++ DBG_871X( "this adapter = %d, buddy adapter = %d\n", adapter->adapter_type, adapter->pbuddy_adapter->adapter_type ); ++ #endif ++ ++ if(!bmcast) ++ { ++ DBG_871X("issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid)); ++ issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); ++ } ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if(bmcast) ++ *psta = rtw_get_bcmc_stainfo(adapter); ++ else ++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get ap_info ++ ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ap2sta: can't get psta under STATION_MODE ; drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { ++ //} ++ ++ if (GetFrameSubType(ptr) & BIT(6)) { ++ /* No data, will not indicate to upper layer, temporily count it here */ ++ count_rx_stats(adapter, precv_frame, *psta); ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && ++ (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ) ++ { ++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ // ++ _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); ++ ++ ++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under MP_MODE ; drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ /* Special case */ ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ else ++ { ++ if(_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)&& (!bmcast)) ++ { ++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info ++ if (*psta == NULL) ++ { ++ DBG_871X("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid)); ++ ++ issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); ++ } ++ } ++ ++ ret = _FAIL; ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ #endif ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++sint sta2ap_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ); ++sint sta2ap_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ unsigned char *mybssid = get_bssid(pmlmepriv); ++ sint ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ //For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR ++ if(!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ *psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ if (*psta == NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under AP_MODE; drop pkt\n")); ++ DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); ++ ++ issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); ++ ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ ++ process_pwrbit_data(adapter, precv_frame); ++ ++ if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { ++ process_wmmps_data(adapter, precv_frame); ++ } ++ ++ if (GetFrameSubType(ptr) & BIT(6)) { ++ /* No data, will not indicate to upper layer, temporily count it here */ ++ count_rx_stats(adapter, precv_frame, *psta); ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ } ++ else { ++ u8 *myhwaddr = myid(&adapter->eeprompriv); ++ if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) { ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); ++ issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); ++ ret = RTW_RX_HANDLED; ++ goto exit; ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame); ++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ //uint len = precv_frame->u.hdr.len; ++ ++ //DBG_871X("+validate_recv_ctrl_frame\n"); ++ ++ if (GetFrameType(pframe) != WIFI_CTRL_TYPE) ++ { ++ return _FAIL; ++ } ++ ++ //receive the frames that ra(a1) is my address ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN)) ++ { ++ return _FAIL; ++ } ++ ++ //only handle ps-poll ++ if(GetFrameSubType(pframe) == WIFI_PSPOLL) ++ { ++ u16 aid; ++ u8 wmmps_ac=0; ++ struct sta_info *psta=NULL; ++ ++ aid = GetAid(pframe); ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ ++ if((psta==NULL) || (psta->aid!=aid)) ++ { ++ return _FAIL; ++ } ++ ++ //for rx pkt statistics ++ psta->sta_stats.rx_ctrl_pkts++; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(0); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(0); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(0); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(0); ++ break; ++ } ++ ++ if(wmmps_ac) ++ return _FAIL; ++ ++ if(psta->state & WIFI_STA_ALIVE_CHK_STATE) ++ { ++ DBG_871X("%s alive check-rx ps-poll\n", __func__); ++ psta->expire_to = pstapriv->expire_to; ++ psta->state ^= WIFI_STA_ALIVE_CHK_STATE; ++ } ++ ++ if((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid))) ++ { ++ _irqL irqL; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta->sleepq_len--; ++ ++ if(psta->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ pxmitframe->attrib.triggered = 1; ++ ++ //DBG_871X("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++#if 0 ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++#endif ++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ if(psta->sleepq_len==0) ++ { ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); ++ ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ } ++ else ++ { ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ //DBG_871X("no buffered packets to xmit\n"); ++ if(pstapriv->tim_bitmap&BIT(psta->aid)) ++ { ++ if(psta->sleepq_len==0) ++ { ++ DBG_871X("no buffered packets to xmit\n"); ++ ++ //issue nulldata with More data bit = 0 to indicate we have no buffered packets ++ issue_nulldata(padapter, psta->hwaddr, 0, 0, 0); ++ } ++ else ++ { ++ DBG_871X("error!psta->sleepq_len=%d\n", psta->sleepq_len); ++ psta->sleepq_len=0; ++ } ++ ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++#endif ++ ++ return _FAIL; ++ ++} ++ ++union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); ++sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame); ++sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) ++{ ++ //struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n")); ++ ++#if 0 ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ mgt_dispatcher(padapter, precv_frame); ++#else ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++#endif ++ } ++ else ++ { ++ mgt_dispatcher(padapter, precv_frame); ++ } ++#endif ++ ++ precv_frame = recvframe_chk_defrag(padapter, precv_frame); ++ if (precv_frame == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,("%s: fragment packet\n",__FUNCTION__)); ++ return _SUCCESS; ++ } ++ ++ { ++ //for rx pkt statistics ++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data)); ++ if (psta) { ++ psta->sta_stats.rx_mgnt_pkts++; ++ if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_BEACON) ++ psta->sta_stats.rx_beacon_pkts++; ++ else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) ++ psta->sta_stats.rx_probereq_pkts++; ++ else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { ++ if (_rtw_memcmp(padapter->eeprompriv.mac_addr, GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) ++ psta->sta_stats.rx_probersp_pkts++; ++ else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) ++ || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) ++ psta->sta_stats.rx_probersp_bm_pkts++; ++ else ++ psta->sta_stats.rx_probersp_uo_pkts++; ++ } ++ } ++ } ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if(padapter->proximity.proxim_on==_TRUE) ++ { ++ struct rx_pkt_attrib * pattrib=&precv_frame->u.hdr.attrib; ++ struct recv_stat* prxstat=( struct recv_stat * ) precv_frame->u.hdr.rx_head ; ++ u8 * pda,*psa,*pbssid,*ptr; ++ ptr=precv_frame->u.hdr.rx_data; ++ pda = get_da(ptr); ++ psa = get_sa(ptr); ++ pbssid = get_hdr_bssid(ptr); ++ ++ ++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); ++ ++ switch(pattrib->to_fr_ds) ++ { ++ case 0: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ break; ++ ++ case 1: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); ++ break; ++ ++ case 2: ++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ break; ++ ++ case 3: ++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); ++ break; ++ ++ default: ++ break; ++ ++ } ++ pattrib->priority=0; ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; ++ ++ padapter->proximity.proxim_rx(padapter,precv_frame); ++ } ++#endif ++ mgt_dispatcher(padapter, precv_frame); ++ ++ return _SUCCESS; ++ ++} ++ ++sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame); ++sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ u8 bretry; ++ u8 *psa, *pda, *pbssid; ++ struct sta_info *psta = NULL; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ sint ret = _SUCCESS; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++#endif //CONFIG_TDLS ++ ++_func_enter_; ++ ++ bretry = GetRetry(ptr); ++ pda = get_da(ptr); ++ psa = get_sa(ptr); ++ pbssid = get_hdr_bssid(ptr); ++ ++ if(pbssid == NULL){ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s pbssid == NULL\n", __func__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); ++ ++ switch(pattrib->to_fr_ds) ++ { ++ case 0: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ ret = sta2sta_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 1: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); ++ ret = ap2sta_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 2: ++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ ret = sta2ap_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 3: ++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); ++ ret =_FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); ++ break; ++ ++ default: ++ ret =_FAIL; ++ break; ++ ++ } ++ ++ if(ret ==_FAIL){ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret); ++ #endif ++ goto exit; ++ } else if (ret == RTW_RX_HANDLED) { ++ goto exit; ++ } ++ ++ ++ if(psta==NULL){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" after to_fr_ds_chk; psta==NULL \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //psta->rssi = prxcmd->rssi; ++ //psta->signal_quality= prxcmd->sq; ++ precv_frame->u.hdr.psta = psta; ++ ++ ++ pattrib->amsdu=0; ++ pattrib->ack_policy = 0; ++ //parsing QC field ++ if(pattrib->qos == 1) ++ { ++ pattrib->priority = GetPriority((ptr + 24)); ++ pattrib->ack_policy = GetAckpolicy((ptr + 24)); ++ pattrib->amsdu = GetAMsdu((ptr + 24)); ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 32 : 26; ++ ++ if(pattrib->priority!=0 && pattrib->priority!=3) ++ { ++ adapter->recvpriv.bIsAnyNonBEPkts = _TRUE; ++ } ++ } ++ else ++ { ++ pattrib->priority=0; ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; ++ } ++ ++ ++ if(pattrib->order)//HT-CTRL 11n ++ { ++ pattrib->hdrlen += 4; ++ } ++ ++ precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; ++ ++ // decache, drop duplicate recv packets ++ if(recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decache : drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++#if 0 ++ if(psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ if(psta->dot118021XPrivacy==_AES_) ++ pattrib->encrypt=psta->dot118021XPrivacy; ++ } ++#endif //CONFIG_TDLS ++ ++ if(pattrib->privacy){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0],IS_MCAST(pattrib->ra))); ++ ++#ifdef CONFIG_TDLS ++ if((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy==_AES_)) ++ { ++ pattrib->encrypt=psta->dot118021XPrivacy; ++ } ++ else ++#endif //CONFIG_TDLS ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra)); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n pattrib->encrypt=%d\n",pattrib->encrypt)); ++ ++ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); ++ } ++ else ++ { ++ pattrib->encrypt = 0; ++ pattrib->iv_len = pattrib->icv_len = 0; ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++#ifdef CONFIG_IEEE80211W ++static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ u8 type; ++ u8 subtype; ++ ++ type = GetFrameType(ptr); ++ subtype = GetFrameSubType(ptr); //bit(7)~bit(2) ++ ++ //only support station mode ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ++ && adapter->securitypriv.binstallBIPkey == _TRUE) ++ { ++ //unicast management frame decrypt ++ if(pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) && ++ (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) ++ { ++ u8 *ppp, *mgmt_DATA; ++ u32 data_len=0; ++ ppp = GetAddr2Ptr(ptr); ++ ++ pattrib->bdecrypted = 0; ++ pattrib->encrypt = _AES_; ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ //set iv and icv length ++ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); ++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); ++ //actual management data frame body ++ data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; ++ mgmt_DATA = rtw_zmalloc(data_len); ++ if(mgmt_DATA == NULL) ++ { ++ DBG_871X("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__); ++ goto validate_80211w_fail; ++ } ++ /*//dump the packet content before decrypt ++ { ++ int pp; ++ printk("pattrib->pktlen = %d =>", pattrib->pkt_len); ++ for(pp=0;pp< pattrib->pkt_len; pp++) ++ printk(" %02x ", ptr[pp]); ++ printk("\n"); ++ }*/ ++ ++ precv_frame = decryptor(adapter, precv_frame); ++ //save actual management data frame body ++ _rtw_memcpy(mgmt_DATA, ptr+pattrib->hdrlen+pattrib->iv_len, data_len); ++ //overwrite the iv field ++ _rtw_memcpy(ptr+pattrib->hdrlen, mgmt_DATA, data_len); ++ //remove the iv and icv length ++ pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; ++ rtw_mfree(mgmt_DATA, data_len); ++ /*//print packet content after decryption ++ { ++ int pp; ++ printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); ++ for(pp=0;pp< pattrib->pkt_len; pp++) ++ printk(" %02x ", ptr[pp]); ++ printk("\n"); ++ }*/ ++ if(!precv_frame) ++ { ++ DBG_871X("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__); ++ goto validate_80211w_fail; ++ } ++ } ++ else if(IS_MCAST(GetAddr1Ptr(ptr)) && ++ (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)) ++ { ++ sint BIP_ret = _SUCCESS; ++ //verify BIP MME IE of broadcast/multicast de-auth/disassoc packet ++ BIP_ret = rtw_BIP_verify(adapter, (u8 * )precv_frame); ++ if(BIP_ret == _FAIL) ++ { ++ //DBG_871X("802.11w BIP verify fail\n"); ++ goto validate_80211w_fail; ++ } ++ else if(BIP_ret == RTW_RX_HANDLED) ++ { ++ //DBG_871X("802.11w recv none protected packet\n"); ++ //issue sa query request ++ issue_action_SA_Query(adapter, NULL, 0, 0); ++ goto validate_80211w_fail; ++ } ++ }//802.11w protect ++ else ++ { ++ if(subtype == WIFI_ACTION) ++ { ++ //according 802.11-2012 standard, these five types are not robust types ++ if( ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC && ++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT && ++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM && ++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED && ++ ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P) ++ { ++ DBG_871X("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]); ++ goto validate_80211w_fail; ++ } ++ } ++ else if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) ++ { ++ DBG_871X("802.11w recv none protected packet\n"); ++ //issue sa query request ++ issue_action_SA_Query(adapter, NULL, 0, 0); ++ goto validate_80211w_fail; ++ } ++ } ++ } ++ return _SUCCESS; ++ ++validate_80211w_fail: ++ return _FAIL; ++ ++} ++#endif //CONFIG_IEEE80211W ++ ++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame); ++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ //shall check frame subtype, to / from ds, da, bssid ++ ++ //then call check if rx seq/frag. duplicated. ++ ++ u8 type; ++ u8 subtype; ++ sint retval = _SUCCESS; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ u8 ver =(unsigned char) (*ptr)&0x3 ; ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++#endif ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++#endif //CONFIG_TDLS ++#ifdef CONFIG_WAPI_SUPPORT ++ PRT_WAPI_T pWapiInfo = &adapter->wapiInfo; ++ struct recv_frame_hdr *phdr = &precv_frame->u.hdr; ++ u8 wai_pkt = 0; ++ u16 sc; ++ u8 external_len = 0; ++#endif ++ ++_func_enter_; ++ ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { ++ int ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter)); ++ if (ch_set_idx >= 0) ++ pmlmeext->channel_set[ch_set_idx].rx_count++; ++ } ++#endif ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->ch_sensing==1 && ptdlsinfo->cur_channel !=0){ ++ ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel-1]++; ++ } ++#endif //CONFIG_TDLS ++ ++#ifdef RTK_DMP_PLATFORM ++ if ( 0 ) ++ { ++ DBG_871X("++\n"); ++ { ++ int i; ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ ++ } ++ DBG_871X("--\n"); ++ } ++#endif //RTK_DMP_PLATFORM ++ ++ //add version chk ++ if(ver!=0){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! (ver!=0)\n")); ++ retval= _FAIL; ++ goto exit; ++ } ++ ++ type = GetFrameType(ptr); ++ subtype = GetFrameSubType(ptr); //bit(7)~bit(2) ++ ++ pattrib->to_fr_ds = get_tofr_ds(ptr); ++ ++ pattrib->frag_num = GetFragNum(ptr); ++ pattrib->seq_num = GetSequence(ptr); ++ ++ pattrib->pw_save = GetPwrMgt(ptr); ++ pattrib->mfrag = GetMFrag(ptr); ++ pattrib->mdata = GetMData(ptr); ++ pattrib->privacy = GetPrivacy(ptr); ++ pattrib->order = GetOrder(ptr); ++#ifdef CONFIG_WAPI_SUPPORT ++ sc = (pattrib->seq_num<<4) | pattrib->frag_num; ++#endif ++ ++#if 1 //Dump rx packets ++{ ++ u8 bDumpRxPkt; ++ rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); ++ if(bDumpRxPkt ==1){//dump all rx packets ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++ } ++ else if(bDumpRxPkt ==2){ ++ if(type== WIFI_MGT_TYPE){ ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++ } ++ } ++ else if(bDumpRxPkt ==3){ ++ if(type== WIFI_DATA_TYPE){ ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++ } ++ } ++} ++#endif ++ switch (type) ++ { ++ case WIFI_MGT_TYPE: //mgnt ++#ifdef CONFIG_IEEE80211W ++ if(validate_80211w_mgmt(adapter, precv_frame) == _FAIL) ++ { ++ retval = _FAIL; ++ break; ++ } ++#endif //CONFIG_IEEE80211W ++ ++ retval = validate_recv_mgnt_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_mgnt_frame fail\n")); ++ } ++ retval = _FAIL; // only data frame return _SUCCESS ++ break; ++ case WIFI_CTRL_TYPE: //ctrl ++ retval = validate_recv_ctrl_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_ctrl_frame fail\n")); ++ } ++ retval = _FAIL; // only data frame return _SUCCESS ++ break; ++ case WIFI_DATA_TYPE: //data ++#ifdef CONFIG_WAPI_SUPPORT ++ if(pattrib->qos) ++ external_len = 2; ++ else ++ external_len= 0; ++ ++ wai_pkt = rtw_wapi_is_wai_packet(adapter,ptr); ++ ++ phdr->bIsWaiPacket = wai_pkt; ++ ++ if(wai_pkt !=0){ ++ if(sc != adapter->wapiInfo.wapiSeqnumAndFragNum) ++ { ++ adapter->wapiInfo.wapiSeqnumAndFragNum = sc; ++ } ++ else ++ { ++ retval = _FAIL; ++ break; ++ } ++ } ++ else{ ++ ++ if(rtw_wapi_drop_for_key_absent(adapter,GetAddr2Ptr(ptr))){ ++ retval=_FAIL; ++ WAPI_TRACE(WAPI_RX,"drop for key absent for rx \n"); ++ break; ++ } ++ } ++ ++#endif ++ ++ rtw_led_control(adapter, LED_CTL_RX); ++ pattrib->qos = (subtype & BIT(7))? 1:0; ++ retval = validate_recv_data_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n")); ++ precvpriv->rx_drop++; ++ } ++ break; ++ default: ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! type=0x%x\n", type)); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); ++ #endif ++ retval = _FAIL; ++ break; ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return retval; ++} ++ ++ ++//remove the wlanhdr and add the eth_hdr ++#if 1 ++ ++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe); ++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) ++{ ++ sint rmv_len; ++ u16 eth_type, len; ++ u8 bsnaphdr; ++ u8 *psnap_type; ++ struct ieee80211_snap_hdr *psnap; ++ ++ sint ret=_SUCCESS; ++ _adapter *adapter =precvframe->u.hdr.adapter; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ u8 *ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field ++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; ++ ++_func_enter_; ++ ++ if(pattrib->encrypt){ ++ recvframe_pull_tail(precvframe, pattrib->icv_len); ++ } ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); ++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ /* convert hdr + possible LLC headers into Ethernet header */ ++ //eth_type = (psnap_type[0] << 8) | psnap_type[1]; ++ if((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && ++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && ++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2)==_FALSE) )|| ++ //eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || ++ _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)){ ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ ++ bsnaphdr = _TRUE; ++ } ++ else { ++ /* Leave Ethernet header part of hdr and full payload */ ++ bsnaphdr = _FALSE; ++ } ++ ++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); ++ len = precvframe->u.hdr.len - rmv_len; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); ++ ++ _rtw_memcpy(ð_type, ptr+rmv_len, 2); ++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type ++ pattrib->eth_type = eth_type; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) ++ { ++ ptr += rmv_len ; ++ *ptr = 0x87; ++ *(ptr+1) = 0x12; ++ ++ eth_type = 0x8712; ++ // append rx status for mp test packets ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24); ++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24); ++ ptr+=24; ++ } ++ else { ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+ (bsnaphdr?2:0))); ++ } ++ ++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); ++ ++ if(!bsnaphdr) { ++ len = htons(len); ++ _rtw_memcpy(ptr+12, &len, 2); ++ } ++ ++_func_exit_; ++ return ret; ++ ++} ++ ++#else ++ ++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) ++{ ++ sint rmv_len; ++ u16 eth_type; ++ u8 bsnaphdr; ++ u8 *psnap_type; ++ struct ieee80211_snap_hdr *psnap; ++ ++ sint ret=_SUCCESS; ++ _adapter *adapter =precvframe->u.hdr.adapter; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ u8* ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field ++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; ++ struct _vlan *pvlan = NULL; ++ ++_func_enter_; ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); ++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03) ++ { ++ if (_rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN)) ++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042; ++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) && ++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) ) ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; ++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; ++ else { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ } else ++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; ++ ++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len)); ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ptr += rmv_len ; ++ *ptr = 0x87; ++ *(ptr+1) = 0x12; ++ ++ //back to original pointer ++ ptr -= rmv_len; ++ } ++ ++ ptr += rmv_len ; ++ ++ _rtw_memcpy(ð_type, ptr, 2); ++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type ++ ptr +=2; ++ ++ if(pattrib->encrypt){ ++ recvframe_pull_tail(precvframe, pattrib->icv_len); ++ } ++ ++ if(eth_type == 0x8100) //vlan ++ { ++ pvlan = (struct _vlan *) ptr; ++ ++ //eth_type = get_vlan_encap_proto(pvlan); ++ //eth_type = pvlan->h_vlan_encapsulated_proto;//? ++ rmv_len += 4; ++ ptr+=4; ++ } ++ ++ if(eth_type==0x0800)//ip ++ { ++ //struct iphdr* piphdr = (struct iphdr*) ptr; ++ //__u8 tos = (unsigned char)(pattrib->priority & 0xff); ++ ++ //piphdr->tos = tos; ++ ++ //if (piphdr->protocol == 0x06) ++ //{ ++ // RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len)); ++ //} ++ } ++ else if(eth_type==0x8712)// append rx status for mp test packets ++ { ++ //ptr -= 16; ++ //_rtw_memcpy(ptr, get_rxmem(precvframe), 16); ++ } ++ else ++ { ++#ifdef PLATFORM_OS_XP ++ NDIS_PACKET_8021Q_INFO VlanPriInfo; ++ UINT32 UserPriority = precvframe->u.hdr.attrib.priority; ++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 ); ++ ++ VlanPriInfo.Value = // Get current value. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo); ++ ++ VlanPriInfo.TagHeader.UserPriority = UserPriority; ++ VlanPriInfo.TagHeader.VlanId = VlanID ; ++ ++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero. ++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value; ++#endif ++ } ++ ++ if(eth_type==0x8712)// append rx status for mp test packets ++ { ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24); ++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24); ++ ptr+=24; ++ } ++ else ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)); ++ ++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); ++ ++ eth_type = htons((unsigned short)eth_type) ; ++ _rtw_memcpy(ptr+12, ð_type, 2); ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif ++ ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++#ifdef PLATFORM_LINUX ++static void recvframe_expand_pkt( ++ PADAPTER padapter, ++ union recv_frame *prframe) ++{ ++ struct recv_frame_hdr *pfhdr; ++ _pkt *ppkt; ++ u8 shift_sz; ++ u32 alloc_sz; ++ ++ ++ pfhdr = &prframe->u.hdr; ++ ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ if (pfhdr->attrib.qos) ++ shift_sz = 6; ++ else ++ shift_sz = 0; ++ ++ // for first fragment packet, need to allocate ++ // (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet ++ // 8 is for skb->data 8 bytes alignment. ++// alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); ++ alloc_sz = 1664; // round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment ++ ++ //3 1. alloc new skb ++ // prepare extra space for 4 bytes alignment ++ ppkt = rtw_skb_alloc(alloc_sz); ++ ++ if (!ppkt) return; // no way to expand ++ ++ //3 2. Prepare new skb to replace & release old skb ++ // force ppkt->data at 8-byte alignment address ++ skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7)); ++ // force ip_hdr at 8-byte alignment address according to shift_sz ++ skb_reserve(ppkt, shift_sz); ++ ++ // copy data to new pkt ++ _rtw_memcpy(skb_put(ppkt, pfhdr->len), pfhdr->rx_data, pfhdr->len); ++ ++ rtw_skb_free(pfhdr->pkt); ++ ++ // attach new pkt to recvframe ++ pfhdr->pkt = ppkt; ++ pfhdr->rx_head = ppkt->head; ++ pfhdr->rx_data = ppkt->data; ++ pfhdr->rx_tail = skb_tail_pointer(ppkt); ++ pfhdr->rx_end = skb_end_pointer(ppkt); ++} ++#else ++#warning "recvframe_expand_pkt not implement, defrag may crash system" ++#endif ++#endif ++ ++//perform defrag ++union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q); ++union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q) ++{ ++ _list *plist, *phead; ++ u8 *data,wlanhdr_offset; ++ u8 curfragnum; ++ struct recv_frame_hdr *pfhdr,*pnfhdr; ++ union recv_frame* prframe, *pnextrframe; ++ _queue *pfree_recv_queue; ++ ++_func_enter_; ++ ++ curfragnum=0; ++ pfree_recv_queue=&adapter->recvpriv.free_recv_queue; ++ ++ phead = get_list_head(defrag_q); ++ plist = get_next(phead); ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pfhdr=&prframe->u.hdr; ++ rtw_list_delete(&(prframe->u.list)); ++ ++ if(curfragnum!=pfhdr->attrib.frag_num) ++ { ++ //the first fragment number must be 0 ++ //free the whole queue ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ ++ return NULL; ++ } ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++#ifndef CONFIG_SDIO_RX_COPY ++ recvframe_expand_pkt(adapter, prframe); ++#endif ++#endif ++ ++ curfragnum++; ++ ++ plist= get_list_head(defrag_q); ++ ++ plist = get_next(plist); ++ ++ data=get_recvframe_data(prframe); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u); ++ pnfhdr=&pnextrframe->u.hdr; ++ ++ ++ //check the fragment sequence (2nd ~n fragment frame) ++ ++ if(curfragnum!=pnfhdr->attrib.frag_num) ++ { ++ //the fragment number must be increasing (after decache) ++ //release the defrag_q & prframe ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ return NULL; ++ } ++ ++ curfragnum++; ++ ++ //copy the 2nd~n fragment frame's payload to the first fragment ++ //get the 2nd~last fragment frame's payload ++ ++ wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len; ++ ++ recvframe_pull(pnextrframe, wlanhdr_offset); ++ ++ //append to first fragment frame's tail (if privacy frame, pull the ICV) ++ recvframe_pull_tail(prframe, pfhdr->attrib.icv_len); ++ ++ //memcpy ++ _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len); ++ ++ recvframe_put(prframe, pnfhdr->len); ++ ++ pfhdr->attrib.icv_len=pnfhdr->attrib.icv_len; ++ plist = get_next(plist); ++ ++ }; ++ ++ //free the defrag_q queue and return the prframe ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Performance defrag!!!!!\n")); ++ ++_func_exit_; ++ ++ return prframe; ++} ++ ++//check if need to defrag, if needed queue the frame to defrag_q ++union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame) ++{ ++ u8 ismfrag; ++ u8 fragnum; ++ u8 *psta_addr; ++ struct recv_frame_hdr *pfhdr; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv; ++ _list *phead; ++ union recv_frame *prtnframe = NULL; ++ _queue *pfree_recv_queue, *pdefrag_q; ++ ++_func_enter_; ++ ++ pstapriv = &padapter->stapriv; ++ ++ pfhdr = &precv_frame->u.hdr; ++ ++ pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ ++ //need to define struct of wlan header frame ctrl ++ ismfrag = pfhdr->attrib.mfrag; ++ fragnum = pfhdr->attrib.frag_num; ++ ++ psta_addr = pfhdr->attrib.ta; ++ psta = rtw_get_stainfo(pstapriv, psta_addr); ++ if (psta == NULL) ++ { ++ u8 type = GetFrameType(pfhdr->rx_data); ++ if (type != WIFI_DATA_TYPE) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ pdefrag_q = &psta->sta_recvpriv.defrag_q; ++ } else ++ pdefrag_q = NULL; ++ } ++ else ++ pdefrag_q = &psta->sta_recvpriv.defrag_q; ++ ++ if ((ismfrag==0) && (fragnum==0)) ++ { ++ prtnframe = precv_frame;//isn't a fragment frame ++ } ++ ++ if (ismfrag==1) ++ { ++ //0~(n-1) fragment frame ++ //enqueue to defraf_g ++ if(pdefrag_q != NULL) ++ { ++ if(fragnum==0) ++ { ++ //the first fragment ++ if(_rtw_queue_empty(pdefrag_q) == _FALSE) ++ { ++ //free current defrag_q ++ rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue); ++ } ++ } ++ ++ ++ //Then enqueue the 0~(n-1) fragment into the defrag_q ++ ++ //_rtw_spinlock(&pdefrag_q->lock); ++ phead = get_list_head(pdefrag_q); ++ rtw_list_insert_tail(&pfhdr->list, phead); ++ //_rtw_spinunlock(&pdefrag_q->lock); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); ++ ++ prtnframe=NULL; ++ ++ } ++ else ++ { ++ //can't find this ta's defrag_queue, so free this recv_frame ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ prtnframe=NULL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); ++ } ++ ++ } ++ ++ if((ismfrag==0)&&(fragnum!=0)) ++ { ++ //the last fragment frame ++ //enqueue the last fragment ++ if(pdefrag_q != NULL) ++ { ++ //_rtw_spinlock(&pdefrag_q->lock); ++ phead = get_list_head(pdefrag_q); ++ rtw_list_insert_tail(&pfhdr->list,phead); ++ //_rtw_spinunlock(&pdefrag_q->lock); ++ ++ //call recvframe_defrag to defrag ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); ++ precv_frame = recvframe_defrag(padapter, pdefrag_q); ++ prtnframe=precv_frame; ++ ++ } ++ else ++ { ++ //can't find this ta's defrag_queue, so free this recv_frame ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ prtnframe=NULL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); ++ } ++ ++ } ++ ++ ++ if((prtnframe!=NULL)&&(prtnframe->u.hdr.attrib.privacy)) ++ { ++ //after defrag we must check tkip mic code ++ if(recvframe_chkmic(padapter, prtnframe)==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic(padapter, prtnframe)==_FAIL\n")); ++ rtw_free_recvframe(prtnframe,pfree_recv_queue); ++ prtnframe=NULL; ++ } ++ } ++ ++_func_exit_; ++ ++ return prtnframe; ++ ++} ++ ++#define ENDIAN_FREE 1 ++ ++int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe); ++int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) ++{ ++#if defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) //for amsdu TP improvement,Creator: Thomas ++ int a_len, padding_len; ++ u16 eth_type, nSubframe_Length; ++ u8 nr_subframes, i; ++ unsigned char *pdata; ++ struct rx_pkt_attrib *pattrib; ++#ifndef PLATFORM_FREEBSD ++ unsigned char *data_ptr; ++ _pkt *sub_skb,*subframes[MAX_SUBFRAME_COUNT]; ++#endif //PLATFORM_FREEBSD ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); ++ int ret = _SUCCESS; ++#ifdef PLATFORM_FREEBSD ++ struct mbuf *sub_m=NULL, *subframes[MAX_SUBFRAME_COUNT]; ++ u8 *ptr,offset; ++#endif //PLATFORM_FREEBSD ++ nr_subframes = 0; ++ ++ pattrib = &prframe->u.hdr.attrib; ++ ++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); ++ ++ if(prframe->u.hdr.attrib.iv_len >0) ++ { ++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); ++ } ++ ++ a_len = prframe->u.hdr.len; ++ ++ pdata = prframe->u.hdr.rx_data; ++ ++ while(a_len > ETH_HLEN) { ++ ++ /* Offset 12 denote 2 mac address */ ++#ifdef ENDIAN_FREE ++ //nSubframe_Length = ntohs(*((u16*)(pdata + 12))); ++ nSubframe_Length = RTW_GET_BE16(pdata + 12); ++#else // ENDIAN_FREE ++ nSubframe_Length = *((u16*)(pdata + 12)); ++ //==m==>change the length order ++ nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8); ++ //ntohs(nSubframe_Length); ++#endif // ENDIAN_FREE ++ ++ if( a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length) ) { ++ DBG_871X("nRemain_Length is %d and nSubframe_Length is : %d\n",a_len,nSubframe_Length); ++ goto exit; ++ } ++ ++#ifndef PLATFORM_FREEBSD ++ /* move the data point to data content */ ++ pdata += ETH_HLEN; ++ a_len -= ETH_HLEN; ++ ++ /* Allocate new skb for releasing to upper layer */ ++#ifdef CONFIG_SKB_COPY ++ sub_skb = rtw_skb_alloc(nSubframe_Length + 12); ++ if(sub_skb) ++ { ++ skb_reserve(sub_skb, 12); ++ data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); ++ _rtw_memcpy(data_ptr, pdata, nSubframe_Length); ++ } ++ else ++#endif // CONFIG_SKB_COPY ++ { ++ sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); ++ if(sub_skb) ++ { ++ sub_skb->data = pdata; ++ sub_skb->len = nSubframe_Length; ++ skb_set_tail_pointer(sub_skb, nSubframe_Length); ++ } ++ else ++ { ++ DBG_871X("rtw_skb_clone() Fail!!! , nr_subframes = %d\n",nr_subframes); ++ break; ++ } ++ } ++ ++#else // PLATFORM_FREEBSD ++ ++ //PLATFORM_FREEBSD ++ //Allocate a mbuff, ++ //sub_m =m_devget(pdata, nSubframe_Length+12, 12, padapter->pifp,NULL); ++ sub_m =m_devget(pdata, nSubframe_Length+ETH_HLEN, ETHER_ALIGN, padapter->pifp,NULL); ++ ++ pdata += ETH_HLEN; ++ a_len -= ETH_HLEN; ++#endif // PLATFORM_FREEBSD ++ ++#ifndef PLATFORM_FREEBSD ++ //sub_skb->dev = padapter->pnetdev; ++ subframes[nr_subframes++] = sub_skb; ++#else //PLATFORM_FREEBSD ++ //PLATFORM_FREEBSD ++ subframes[nr_subframes++] = sub_m; ++#endif //PLATFORM_FREEBSD ++ ++ if(nr_subframes >= MAX_SUBFRAME_COUNT) { ++ DBG_871X("ParseSubframe(): Too many Subframes! Packets dropped!\n"); ++ break; ++ } ++ ++ pdata += nSubframe_Length; ++ a_len -= nSubframe_Length; ++ if(a_len != 0) { ++ padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4-1)); ++ if(padding_len == 4) { ++ padding_len = 0; ++ } ++ ++ if(a_len < padding_len) { ++ goto exit; ++ } ++ pdata += padding_len; ++ a_len -= padding_len; ++ } ++ } ++ ++ for(i=0; idata[6]); ++ eth_type = RTW_GET_BE16(&sub_skb->data[6]); ++#else // ENDIAN_FREE ++ eth_type = (sub_skb->data[6] << 8) | sub_skb->data[7]; ++#endif // ENDIAN_FREE ++ if (sub_skb->len >= 8 && ++ ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && ++ eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || ++ _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE) )) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ ++ skb_pull(sub_skb, SNAP_SIZE); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); ++ } else { ++ u16 len; ++ /* Leave Ethernet header part of hdr and full payload */ ++ len = htons(sub_skb->len); ++ _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); ++ } ++ ++ /* Indicat the packets to upper layer */ ++ if (sub_skb) { ++ //memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); ++ ++#ifdef CONFIG_BR_EXT ++ // Insert NAT2.5 RX here! ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ void *br_port = NULL; ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ ++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); ++ if (nat25_handle_frame(padapter, sub_skb) == -1) { ++ //priv->ext_stats.rx_data_drops++; ++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); ++ //return FAIL; ++ ++#if 1 ++ // bypass this frame to upper layer!! ++#else ++ rtw_skb_free(sub_skb); ++ continue; ++#endif ++ } ++ } ++#endif // CONFIG_BR_EXT ++ ++ sub_skb->protocol = eth_type_trans(sub_skb, padapter->pnetdev); ++ sub_skb->dev = padapter->pnetdev; ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { ++ sub_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ sub_skb->ip_summed = CHECKSUM_NONE; ++ } ++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ ++ sub_skb->ip_summed = CHECKSUM_NONE; ++#endif //CONFIG_TCP_CSUM_OFFLOAD_RX ++ ++ rtw_netif_rx(padapter->pnetdev, sub_skb); ++ } ++#else //PLATFORM_FREEBSD ++ ++ //PLATFORM_FREEBSD ++ sub_m = subframes[i]; ++ ptr=mtod(sub_m, u8 *); ++ offset=ETH_HLEN; ++ /* convert hdr + possible LLC headers into Ethernet header */ ++#ifdef ENDIAN_FREE ++ eth_type = ntohs(*(u16*)&ptr[offset+6]); ++#else // ENDIAN_FREE ++ eth_type = ( ptr[offset+6] << 8) | ptr[offset+7]; ++#endif // ENDIAN_FREE ++ if (sub_m->m_pkthdr.len >= ETH_HLEN+8 && ++ ((_rtw_memcmp(ptr+ETH_HLEN, rtw_rfc1042_header, SNAP_SIZE) && ++ eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || ++ _rtw_memcmp(ptr+ETH_HLEN, rtw_bridge_tunnel_header, SNAP_SIZE) )) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ ++ offset+=SNAP_SIZE; ++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->src, ETH_ALEN); ++ offset-=ETH_ALEN; ++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->dst, ETH_ALEN); ++ offset-=ETH_ALEN; ++ } else { ++ u16 len; ++ /* Leave Ethernet header part of hdr and full payload */ ++ len = htons(sub_m->m_pkthdr.len-offset); ++ _rtw_memcpy(&ptr[offset- 2], &len, 2); ++ offset-=2; ++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->src, ETH_ALEN); ++ offset-=ETH_ALEN; ++ _rtw_memcpy(&ptr[offset-ETH_ALEN], pattrib->dst, ETH_ALEN); ++ offset-=ETH_ALEN; ++ } ++ ++ m_adj(sub_m,offset); ++ ++ /* Indicat the packets to upper layer */ ++ if (sub_m) { ++ ++#if 0 ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { ++ sub_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ sub_skb->ip_summed = CHECKSUM_NONE; ++ } ++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ ++ sub_skb->ip_summed = CHECKSUM_NONE; ++#endif //CONFIG_TCP_CSUM_OFFLOAD_RX ++#endif //0 ++ ++ if ( ((u32)(mtod(sub_m, caddr_t) + 14) % 4) != 0) ++ printf("%s()-%d: mtod(sub_m) = %p\n", __FUNCTION__, __LINE__, mtod(sub_m, caddr_t)); ++#ifdef CONFIG_RX_INDICATE_QUEUE ++ IF_ENQUEUE(&precvpriv->rx_indicate_queue, sub_m); ++ if (_IF_QLEN(&precvpriv->rx_indicate_queue) <= 1) { ++ taskqueue_enqueue(taskqueue_thread, &precvpriv->rx_indicate_tasklet); ++ } ++#else // CONFIG_RX_INDICATE_QUEUE ++ (*padapter->pifp->if_input)(padapter->pifp, sub_m); ++#endif // CONFIG_RX_INDICATE_QUEUE ++ } ++ ++#endif //PLATFORM_FREEBSD ++ } ++ ++exit: ++ ++ prframe->u.hdr.len=0; ++ rtw_free_recvframe(prframe, pfree_recv_queue);//free this recv_frame ++ ++ return ret; ++#else // || defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) ++#ifdef PLATFORM_WINDOWS ++ _irqL irql; ++#endif //PLATFORM_WINDOWS ++ unsigned char *ptr, *pdata, *pbuf, *psnap_type; ++ union recv_frame *pnrframe, *pnrframe_new; ++ int a_len, mv_len, padding_len; ++ u16 eth_type, type_len; ++ u8 bsnaphdr; ++ struct ieee80211_snap_hdr *psnap; ++ struct _vlan *pvlan; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); ++ int ret = _SUCCESS; ++#ifdef PLATFORM_WINDOWS ++ struct recv_buf *precvbuf = prframe->u.hdr.precvbuf; ++#endif //PLATFORM_WINDOWS ++ a_len = prframe->u.hdr.len - prframe->u.hdr.attrib.hdrlen; ++ ++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); ++ ++ if(prframe->u.hdr.attrib.iv_len >0) ++ { ++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); ++ } ++ ++ pdata = prframe->u.hdr.rx_data; ++ ++ prframe->u.hdr.len=0; ++ ++ pnrframe = prframe; ++ ++ ++ do{ ++ ++ mv_len=0; ++ pnrframe->u.hdr.rx_data = pnrframe->u.hdr.rx_tail = pdata; ++ ptr = pdata; ++ ++ ++ _rtw_memcpy(pnrframe->u.hdr.attrib.dst, ptr, ETH_ALEN); ++ ptr+=ETH_ALEN; ++ _rtw_memcpy(pnrframe->u.hdr.attrib.src, ptr, ETH_ALEN); ++ ptr+=ETH_ALEN; ++ ++ _rtw_memcpy(&type_len, ptr, 2); ++ type_len= ntohs((unsigned short )type_len); ++ ptr +=2; ++ mv_len += ETH_HLEN; ++ ++ recvframe_put(pnrframe, type_len+ETH_HLEN);//update tail; ++ ++ if(pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8) ++ { ++ //panic("pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8\n"); ++ ++ rtw_free_recvframe(pnrframe, pfree_recv_queue); ++ ++ goto exit; ++ } ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr); ++ psnap_type=ptr+SNAP_SIZE; ++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03) ++ { ++ if ( _rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN)) ++ { ++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042; ++ } ++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) && ++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) ) ++ { ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; ++ } ++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) ++ { ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n")); ++ ++ //KeBugCheckEx(0x87123333, 0xe0, 0x4c, 0x87, 0xdd); ++ ++ //panic("0x87123333, 0xe0, 0x4c, 0x87, 0xdd\n"); ++ ++ rtw_free_recvframe(pnrframe, pfree_recv_queue); ++ ++ goto exit; ++ } ++ ++ } ++ else ++ { ++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; ++ } ++ ++ ptr += (bsnaphdr?SNAP_SIZE:0); ++ _rtw_memcpy(ð_type, ptr, 2); ++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type ++ ++ mv_len+= 2+(bsnaphdr?SNAP_SIZE:0); ++ ptr += 2;//now move to iphdr; ++ ++ pvlan = NULL; ++ if(eth_type == 0x8100) //vlan ++ { ++ pvlan = (struct _vlan *)ptr; ++ ptr+=4; ++ mv_len+=4; ++ } ++ ++ if(eth_type==0x0800)//ip ++ { ++ struct iphdr* piphdr = (struct iphdr*)ptr; ++ ++ ++ if (piphdr->protocol == 0x06) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", pnrframe->u.hdr.len)); ++ } ++ } ++#ifdef PLATFORM_OS_XP ++ else ++ { ++ NDIS_PACKET_8021Q_INFO VlanPriInfo; ++ UINT32 UserPriority = pnrframe->u.hdr.attrib.priority; ++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 ); ++ ++ VlanPriInfo.Value = // Get current value. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo); ++ ++ VlanPriInfo.TagHeader.UserPriority = UserPriority; ++ VlanPriInfo.TagHeader.VlanId = VlanID; ++ ++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero. ++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value; ++ ++ } ++#endif //PLATFORM_OS_XP ++ ++ pbuf = recvframe_pull(pnrframe, (mv_len-sizeof(struct ethhdr))); ++ ++ _rtw_memcpy(pbuf, pnrframe->u.hdr.attrib.dst, ETH_ALEN); ++ _rtw_memcpy(pbuf+ETH_ALEN, pnrframe->u.hdr.attrib.src, ETH_ALEN); ++ ++ eth_type = htons((unsigned short)eth_type) ; ++ _rtw_memcpy(pbuf+12, ð_type, 2); ++ ++ padding_len = (4) - ((type_len + ETH_HLEN)&(4-1)); ++ ++ a_len -= (type_len + ETH_HLEN + padding_len) ; ++ ++ ++#if 0 ++ ++ if(a_len > ETH_HLEN) ++ { ++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue); ++ if(pnrframe_new) ++ { ++ _pkt *pskb_copy; ++ unsigned int copy_len = pnrframe->u.hdr.len; ++ ++ _rtw_init_listhead(&pnrframe_new->u.hdr.list); ++ ++ pskb_copy = rtw_skb_alloc(copy_len+64); ++ ++ if(pskb_copy==NULL) ++ { ++ DBG_871X("amsdu_to_msdu:can not all(ocate memory for skb copy\n"); ++ } ++ ++ pnrframe_new->u.hdr.pkt = pskb_copy; ++ ++ _rtw_memcpy(pskb_copy->data, pnrframe->u.hdr.rx_data, copy_len); ++ ++ pnrframe_new->u.hdr.rx_data = pnrframe->u.hdr.rx_data; ++ pnrframe_new->u.hdr.rx_tail = pnrframe->u.hdr.rx_data + copy_len; ++ ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe_new);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe_new, pfree_recv_queue);//free this recv_frame ++ } ++ ++ } ++ else ++ { ++ DBG_871X("amsdu_to_msdu:can not allocate memory for pnrframe_new\n"); ++ } ++ ++ } ++ else ++ { ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame ++ } ++ ++ pnrframe = NULL; ++ ++ } ++ ++#else // 0 ++ ++ //padding_len = (4) - ((type_len + ETH_HLEN)&(4-1)); ++ ++ //a_len -= (type_len + ETH_HLEN + padding_len) ; ++ ++ pnrframe_new = NULL; ++ ++ ++ if(a_len > ETH_HLEN) ++ { ++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue); ++ ++ if(pnrframe_new) ++ { ++ ++ ++ //pnrframe_new->u.hdr.precvbuf = precvbuf;//precvbuf is assigned before call rtw_init_recvframe() ++ //rtw_init_recvframe(pnrframe_new, precvpriv); ++ { ++#ifdef PLATFORM_LINUX ++ _pkt *pskb = pnrframe->u.hdr.pkt; ++#endif //PLATFORM_LINUX ++ _rtw_init_listhead(&pnrframe_new->u.hdr.list); ++ ++ pnrframe_new->u.hdr.len=0; ++ ++#ifdef PLATFORM_LINUX ++ if(pskb) ++ { ++ pnrframe_new->u.hdr.pkt = rtw_skb_clone(pskb); ++ } ++#endif //PLATFORM_LINUX ++ ++ } ++ ++ pdata += (type_len + ETH_HLEN + padding_len); ++ pnrframe_new->u.hdr.rx_head = pnrframe_new->u.hdr.rx_data = pnrframe_new->u.hdr.rx_tail = pdata; ++ pnrframe_new->u.hdr.rx_end = pdata + a_len + padding_len;// ++ ++#ifdef PLATFORM_WINDOWS ++ pnrframe_new->u.hdr.precvbuf=precvbuf; ++ _enter_critical_bh(&precvbuf->recvbuf_lock, &irql); ++ precvbuf->ref_cnt++; ++ _exit_critical_bh(&precvbuf->recvbuf_lock, &irql); ++#endif //PLATFORM_WINDOWS ++ ++ } ++ else ++ { ++ //panic("pnrframe_new=%x\n", pnrframe_new); ++ } ++ } ++ ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE) ) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame ++ } ++ ++ ++ pnrframe = NULL; ++ if(pnrframe_new) ++ { ++ pnrframe = pnrframe_new; ++ } ++ ++ ++#endif // end defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD) ++ ++ }while(pnrframe); ++ ++exit: ++ ++ return ret; ++#endif ++} ++ ++int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num); ++int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) ++{ ++ u8 wsize = preorder_ctrl->wsize_b; ++ u16 wend = (preorder_ctrl->indicate_seq + wsize -1) & 0xFFF;//% 4096; ++ ++ // Rx Reorder initialize condition. ++ if (preorder_ctrl->indicate_seq == 0xFFFF) ++ { ++ preorder_ctrl->indicate_seq = seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ ++ //DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); ++ } ++ ++ //DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ // Drop out the packet which SeqNum is smaller than WinStart ++ if( SN_LESS(seq_num, preorder_ctrl->indicate_seq) ) ++ { ++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); ++ //DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ ++ ++ return _FALSE; ++ } ++ ++ // ++ // Sliding window manipulation. Conditions includes: ++ // 1. Incoming SeqNum is equal to WinStart =>Window shift 1 ++ // 2. Incoming SeqNum is larger than the WinEnd => Window shift N ++ // ++ if( SN_EQUAL(seq_num, preorder_ctrl->indicate_seq) ) ++ { ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ } ++ else if(SN_LESS(wend, seq_num)) ++ { ++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); ++ //DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ // boundary situation, when seq_num cross 0xFFF ++ if(seq_num >= (wsize - 1)) ++ preorder_ctrl->indicate_seq = seq_num + 1 -wsize; ++ else ++ preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; ++ ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ } ++ ++ //DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ return _TRUE; ++} ++ ++int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe); ++int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) ++{ ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ _list *phead, *plist; ++ union recv_frame *pnextrframe; ++ struct rx_pkt_attrib *pnextattrib; ++ ++ //DbgPrint("+enqueue_reorder_recvframe()\n"); ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pnextattrib = &pnextrframe->u.hdr.attrib; ++ ++ if(SN_LESS(pnextattrib->seq_num, pattrib->seq_num)) ++ { ++ plist = get_next(plist); ++ } ++ else if( SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) ++ { ++ //Duplicate entry is found!! Do not insert current entry. ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); ++ ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ return _FALSE; ++ } ++ else ++ { ++ break; ++ } ++ ++ //DbgPrint("enqueue_reorder_recvframe():while\n"); ++ ++ } ++ ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ rtw_list_insert_tail(&(prframe->u.hdr.list), plist); ++ ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); ++ return _TRUE; ++ ++} ++ ++int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced); ++int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) ++{ ++ //_irqL irql; ++ //u8 bcancelled; ++ _list *phead, *plist; ++ union recv_frame *prframe; ++ struct rx_pkt_attrib *pattrib; ++ //u8 index = 0; ++ int bPktInBuf = _FALSE; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ //DbgPrint("+recv_indicatepkts_in_order\n"); ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++#if 0 ++ // Check if there is any other indication thread running. ++ if(pTS->RxIndicateState == RXTS_INDICATE_PROCESSING) ++ return; ++#endif ++ ++ // Handling some condition for forced indicate case. ++ if(bforced==_TRUE) ++ { ++ if(rtw_is_list_empty(phead)) ++ { ++ // _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ return _TRUE; ++ } ++ ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pattrib = &prframe->u.hdr.attrib; ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ } ++ ++ // Prepare indication list and indication. ++ // Check if there is any packet need indicate. ++ while(!rtw_is_list_empty(phead)) ++ { ++ ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pattrib = &prframe->u.hdr.attrib; ++ ++ if(!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ++ ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n", ++ preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu)); ++ ++#if 0 ++ // This protect buffer from overflow. ++ if(index >= REORDER_WIN_SIZE) ++ { ++ RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!! \n")); ++ bPktInBuf = TRUE; ++ break; ++ } ++#endif ++ ++ plist = get_next(plist); ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ if(SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) ++ { ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ } ++ ++#if 0 ++ index++; ++ if(index==1) ++ { ++ //Cancel previous pending timer. ++ //PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); ++ if(bforced!=_TRUE) ++ { ++ //DBG_871X("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n"); ++ _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled); ++ } ++ } ++#endif ++ ++ //Set this as a lock to make sure that only one thread is indicating packet. ++ //pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; ++ ++ // Indicate packets ++ //RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!! \n")); ++ ++ ++ //indicate this recv_frame ++ //DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); ++ if(!pattrib->amsdu) ++ { ++ //DBG_871X("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); ++ ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ ++ rtw_recv_indicatepkt(padapter, prframe);//indicate this recv_frame ++ ++ } ++ } ++ else if(pattrib->amsdu==1) ++ { ++ if(amsdu_to_msdu(padapter, prframe)!=_SUCCESS) ++ { ++ rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); ++ } ++ } ++ else ++ { ++ //error condition; ++ } ++ ++ ++ //Update local variables. ++ bPktInBuf = _FALSE; ++ ++ } ++ else ++ { ++ bPktInBuf = _TRUE; ++ break; ++ } ++ ++ //DbgPrint("recv_indicatepkts_in_order():while\n"); ++ ++ } ++ ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++/* ++ //Release the indication lock and set to new indication step. ++ if(bPktInBuf) ++ { ++ // Set new pending timer. ++ //pTS->RxIndicateState = RXTS_INDICATE_REORDER; ++ //PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); ++ //DBG_871X("_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME)\n"); ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ } ++ else ++ { ++ //pTS->RxIndicateState = RXTS_INDICATE_IDLE; ++ } ++*/ ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ //return _TRUE; ++ return bPktInBuf; ++ ++} ++ ++int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe); ++int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) ++{ ++ _irqL irql; ++ int retval = _SUCCESS; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ if(!pattrib->amsdu) ++ { ++ //s1. ++ wlanhdr_to_ethhdr(prframe); ++ ++ //if ((pattrib->qos!=1) /*|| pattrib->priority!=0 || IS_MCAST(pattrib->ra)*/ ++ // || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) ++ if (pattrib->qos!=1) ++ { ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n" )); ++ ++ rtw_recv_indicatepkt(padapter, prframe); ++ return _SUCCESS; ++ ++ } ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__); ++ #endif ++ ++ return _FAIL; ++ ++ } ++ ++ if (preorder_ctrl->enable == _FALSE) ++ { ++ //indicate this recv_frame ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ rtw_recv_indicatepkt(padapter, prframe); ++ ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ return _SUCCESS; ++ } ++ ++#ifndef CONFIG_RECV_REORDERING_CTRL ++ //indicate this recv_frame ++ rtw_recv_indicatepkt(padapter, prframe); ++ return _SUCCESS; ++#endif ++ ++ } ++ else if(pattrib->amsdu==1) //temp filter -> means didn't support A-MSDUs in a A-MPDU ++ { ++ if (preorder_ctrl->enable == _FALSE) ++ { ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ retval = amsdu_to_msdu(padapter, prframe); ++ ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ if(retval != _SUCCESS){ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); ++ #endif ++ } ++ ++ return retval; ++ } ++ } ++ else ++ { ++ ++ } ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ++ ("recv_indicatepkt_reorder: indicate=%d seq=%d\n", ++ preorder_ctrl->indicate_seq, pattrib->seq_num)); ++ ++ //s2. check if winstart_b(indicate_seq) needs to been updated ++ if(!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) ++ { ++ //pHTInfo->RxReorderDropCounter++; ++ //ReturnRFDList(Adapter, pRfd); ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n")); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //return _FAIL; ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__); ++ #endif ++#if 0 ++ rtw_recv_indicatepkt(padapter, prframe); ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ goto _success_exit; ++#else ++ goto _err_exit; ++#endif ++ } ++ ++ ++ //s3. Insert all packet into Reorder Queue to maintain its ordering. ++ if(!enqueue_reorder_recvframe(preorder_ctrl, prframe)) ++ { ++ //DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //return _FAIL; ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__); ++ #endif ++ goto _err_exit; ++ } ++ ++ ++ //s4. ++ // Indication process. ++ // After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets ++ // with the SeqNum smaller than latest WinStart and buffer other packets. ++ // ++ // For Rx Reorder condition: ++ // 1. All packets with SeqNum smaller than WinStart => Indicate ++ // 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. ++ // ++ ++ //recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); ++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE)==_TRUE) ++ { ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ } ++ else ++ { ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ++ } ++ ++ ++_success_exit: ++ ++ return _SUCCESS; ++ ++_err_exit: ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ return _FAIL; ++} ++ ++ ++void rtw_reordering_ctrl_timeout_handler(void *pcontext) ++{ ++ _irqL irql; ++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; ++ _adapter *padapter = preorder_ctrl->padapter; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ ++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved) ++ { ++ return; ++ } ++ ++ //DBG_871X("+rtw_reordering_ctrl_timeout_handler()=>\n"); ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE)==_TRUE) ++ { ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ } ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++} ++ ++int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe); ++int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) ++{ ++ int retval = _SUCCESS; ++ //struct recv_priv *precvpriv = &padapter->recvpriv; ++ //struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_TDLS ++ struct sta_info *psta = prframe->u.hdr.psta; ++#endif //CONFIG_TDLS ++ ++#ifdef CONFIG_80211N_HT ++ ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++#ifdef CONFIG_TDLS ++ if( (phtpriv->ht_option==_TRUE) || ++ ((psta->tdls_sta_state & TDLS_LINKED_STATE) && ++ (psta->htpriv.ht_option==_TRUE) && ++ (psta->htpriv.ampdu_enable==_TRUE))) //B/G/N Mode ++#else ++ if(phtpriv->ht_option==_TRUE) //B/G/N Mode ++#endif //CONFIG_TDLS ++ { ++ //prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; ++ ++ if(recv_indicatepkt_reorder(padapter, prframe)!=_SUCCESS)// including perform A-MPDU Rx Ordering Buffer Control ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__); ++ #endif ++ ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ retval = _FAIL; ++ return retval; ++ } ++ } ++ } ++ else //B/G mode ++#endif ++ { ++ retval=wlanhdr_to_ethhdr (prframe); ++ if(retval != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); ++ #endif ++ return retval; ++ } ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ //indicate this recv_frame ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n" )); ++ rtw_recv_indicatepkt(padapter, prframe); ++ ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n" )); ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ retval = _FAIL; ++ return retval; ++ } ++ ++ } ++ ++ return retval; ++ ++} ++ ++int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) ++{ ++ int ret = _SUCCESS; ++ struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ ++ ++#ifdef CONFIG_MP_INCLUDED ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#endif //CONFIG_MP_INCLUDED ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ { ++ if (pattrib->crc_err == 1) ++ { ++ padapter->mppriv.rx_crcerrpktcount++; ++ } ++ else ++ { ++ padapter->mppriv.rx_pktcount++; ++ } ++ if (check_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE) == _FALSE) { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt \n")); ++ ret = _FAIL; ++ rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame ++ goto exit; ++ } ++ } ++#endif ++ ++ //check the frame crtl field and decache ++ ret = validate_recv_frame(padapter, rframe); ++ if (ret != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); ++ rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame ++ goto exit; ++ } ++ ++exit: ++ return ret; ++} ++ ++int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) ++{ ++ int ret = _SUCCESS; ++ union recv_frame *orig_prframe = prframe; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ ++ ++#ifdef CONFIG_TDLS ++ u8 *psnap_type, *pcategory; ++ struct sta_info *ptdls_sta = NULL; ++#endif //CONFIG_TDLS ++ ++ ++ // DATA FRAME ++ rtw_led_control(padapter, LED_CTL_RX); ++ ++ prframe = decryptor(padapter, prframe); ++ if (prframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decryptor: drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); ++ #endif ++ ret = _FAIL; ++ goto _recv_data_drop; ++ } ++ ++#if 0 ++ if ( padapter->adapter_type == PRIMARY_ADAPTER ) ++ { ++ DBG_871X("+++\n"); ++ { ++ int i; ++ u8 *ptr = get_recvframe_data(prframe); ++ for(i=0; i<140;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ ++ } ++ DBG_871X("---\n"); ++ } ++#endif ++ ++#ifdef CONFIG_TDLS ++ //check TDLS frame ++ psnap_type = get_recvframe_data(orig_prframe); ++ psnap_type+=pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; ++ ++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) && ++ ((*pcategory==RTW_WLAN_CATEGORY_TDLS) || (*pcategory==RTW_WLAN_CATEGORY_P2P))){ ++ ret = OnTDLS(padapter, prframe); //all of functions will return _FAIL ++ goto _exit_recv_func; ++ } ++#endif //CONFIG_TDLS ++ ++ prframe = recvframe_chk_defrag(padapter, prframe); ++ if(prframe==NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chk_defrag: drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); ++ #endif ++ goto _recv_data_drop; ++ } ++ ++ prframe=portctrl(padapter, prframe); ++ if (prframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("portctrl: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); ++ #endif ++ ret = _FAIL; ++ goto _recv_data_drop; ++ } ++ ++#ifdef CONFIG_TDLS ++ if(padapter->tdlsinfo.setup_state == TDLS_LINKED_STATE) ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src); ++ count_rx_stats(padapter, prframe, ptdls_sta); ++#else ++ count_rx_stats(padapter, prframe, NULL); ++#endif //CONFIG_TDLS ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_update_info(padapter, prframe); ++#endif ++ ++#ifdef CONFIG_80211N_HT ++ ret = process_recv_indicatepkts(padapter, prframe); ++ if (ret != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recv_func: process_recv_indicatepkts fail! \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _recv_data_drop; ++ } ++#else // CONFIG_80211N_HT ++ if (!pattrib->amsdu) ++ { ++ ret = wlanhdr_to_ethhdr (prframe); ++ if (ret != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _recv_data_drop; ++ } ++ ++ if ((padapter->bDriverStopped == _FALSE) && (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n" )); ++ //indicate this recv_frame ++ ret = rtw_recv_indicatepkt(padapter, prframe); ++ if (ret != _SUCCESS) ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); ++ #endif ++ goto _recv_data_drop; ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n" )); ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", __FUNCTION__, ++ padapter->bDriverStopped, padapter->bSurpriseRemoved); ++ #endif ++ ret = _FAIL; ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue); //free this recv_frame ++ } ++ ++ } ++ else if(pattrib->amsdu==1) ++ { ++ ++ ret = amsdu_to_msdu(padapter, prframe); ++ if(ret != _SUCCESS) ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue); ++ goto _recv_data_drop; ++ } ++ } ++ else ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__); ++ #endif ++ goto _recv_data_drop; ++ } ++#endif // CONFIG_80211N_HT ++ ++_exit_recv_func: ++ return ret; ++ ++_recv_data_drop: ++ precvpriv->rx_drop++; ++ return ret; ++} ++ ++ ++int recv_func(_adapter *padapter, union recv_frame *rframe); ++int recv_func(_adapter *padapter, union recv_frame *rframe) ++{ ++ int ret; ++ struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib; ++ struct recv_priv *recvpriv = &padapter->recvpriv; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ ++ /* check if need to handle uc_swdec_pending_queue*/ ++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) ++ { ++ union recv_frame *pending_frame; ++ int cnt = 0; ++ ++ while((pending_frame=rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) { ++ cnt++; ++ recv_func_posthandle(padapter, pending_frame); ++ } ++ ++ if (cnt) ++ DBG_871X(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n", ++ FUNC_ADPT_ARG(padapter), cnt); ++ } ++ ++ ret = recv_func_prehandle(padapter, rframe); ++ ++ if(ret == _SUCCESS) { ++ ++ /* check if need to enqueue into uc_swdec_pending_queue*/ ++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && ++ !IS_MCAST(prxattrib->ra) && prxattrib->encrypt>0 && ++ (prxattrib->bdecrypted == 0 ||psecuritypriv->sw_decrypt == _TRUE) && ++ psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK && ++ !psecuritypriv->busetkipkey) ++ { ++ rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue); ++ //DBG_871X("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); ++ ++ if (recvpriv->free_recvframe_cnt < NR_RECVFRAME/4) { ++ /* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */ ++ rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue); ++ if (rframe) ++ goto do_posthandle; ++ } ++ goto exit; ++ } ++ ++do_posthandle: ++ ret = recv_func_posthandle(padapter, rframe); ++ } ++ ++exit: ++ return ret; ++} ++ ++ ++s32 rtw_recv_entry(union recv_frame *precvframe) ++{ ++ _adapter *padapter; ++ struct recv_priv *precvpriv; ++ s32 ret=_SUCCESS; ++ ++_func_enter_; ++ ++// RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n")); ++ ++ padapter = precvframe->u.hdr.adapter; ++ ++ precvpriv = &padapter->recvpriv; ++ ++ ++ if ((ret = recv_func(padapter, precvframe)) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("rtw_recv_entry: recv_func return fail!!!\n")); ++ goto _recv_entry_drop; ++ } ++ ++ ++ precvpriv->rx_pkts++; ++ ++_func_exit_; ++ ++ return ret; ++ ++_recv_entry_drop: ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ padapter->mppriv.rx_pktloss = precvpriv->rx_drop; ++#endif ++ ++ //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n")); ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS){ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct recv_priv *recvpriv = &adapter->recvpriv; ++ ++ u32 tmp_s, tmp_q; ++ u8 avg_signal_strength = 0; ++ u8 avg_signal_qual = 0; ++ u32 num_signal_strength = 0; ++ u32 num_signal_qual = 0; ++ u8 _alpha = 3; // this value is based on converging_constant = 5000 and sampling_interval = 1000 ++ ++ if(adapter->recvpriv.is_signal_dbg) { ++ //update the user specific value, signal_strength_dbg, to signal_strength, rssi ++ adapter->recvpriv.signal_strength= adapter->recvpriv.signal_strength_dbg; ++ adapter->recvpriv.rssi=(s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg); ++ } else { ++ ++ if(recvpriv->signal_strength_data.update_req == 0) {// update_req is clear, means we got rx ++ avg_signal_strength = recvpriv->signal_strength_data.avg_val; ++ num_signal_strength = recvpriv->signal_strength_data.total_num; ++ // after avg_vals are accquired, we can re-stat the signal values ++ recvpriv->signal_strength_data.update_req = 1; ++ } ++ ++ if(recvpriv->signal_qual_data.update_req == 0) {// update_req is clear, means we got rx ++ avg_signal_qual = recvpriv->signal_qual_data.avg_val; ++ num_signal_qual = recvpriv->signal_qual_data.total_num; ++ // after avg_vals are accquired, we can re-stat the signal values ++ recvpriv->signal_qual_data.update_req = 1; ++ } ++ ++ if (num_signal_strength == 0) { ++ if (rtw_get_on_cur_ch_time(adapter) == 0 ++ || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval ++#ifdef CONFIG_BT_COEXIST ++ || ((BTDM_IsBtDisabled(adapter) == _FALSE) && (BT_IsBtInquiryPage(adapter) == _TRUE)) ++#endif ++ ) { ++ goto set_timer; ++ } ++ } ++ ++ if(check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE ++ || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE ++ ) { ++ goto set_timer; ++ } ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(adapter, _FW_UNDER_SURVEY) == _TRUE) ++ goto set_timer; ++ #endif ++ ++ //update value of signal_strength, rssi, signal_qual ++ tmp_s = (avg_signal_strength+(_alpha-1)*recvpriv->signal_strength); ++ if(tmp_s %_alpha) ++ tmp_s = tmp_s/_alpha + 1; ++ else ++ tmp_s = tmp_s/_alpha; ++ if(tmp_s>100) ++ tmp_s = 100; ++ ++ tmp_q = (avg_signal_qual+(_alpha-1)*recvpriv->signal_qual); ++ if(tmp_q %_alpha) ++ tmp_q = tmp_q/_alpha + 1; ++ else ++ tmp_q = tmp_q/_alpha; ++ if(tmp_q>100) ++ tmp_q = 100; ++ ++ recvpriv->signal_strength = tmp_s; ++ recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s); ++ recvpriv->signal_qual = tmp_q; ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 ++ DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" ++ ", num_signal_strength:%u, num_signal_qual:%u" ++ ", on_cur_ch_ms:%d" ++ "\n" ++ , FUNC_ADPT_ARG(adapter) ++ , recvpriv->signal_strength ++ , recvpriv->rssi ++ , recvpriv->signal_qual ++ , num_signal_strength, num_signal_qual ++ , rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0 ++ ); ++ #endif ++ } ++ ++set_timer: ++ rtw_set_signal_stat_timer(recvpriv); ++ ++} ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_rf.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_rf.c +new file mode 100644 +index 00000000..7ae86351 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_rf.c +@@ -0,0 +1,95 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_RF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct ch_freq { ++ u32 channel; ++ u32 frequency; ++}; ++ ++struct ch_freq ch_freq_map[] = { ++ {1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432}, ++ {6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457}, ++ {11, 2462},{12, 2467},{13, 2472},{14, 2484}, ++ /* UNII */ ++ {36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260}, ++ {56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765}, ++ {157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845}, ++ {171, 5855},{173, 5865}, ++ /* HiperLAN2 */ ++ {100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580}, ++ {120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680}, ++ {140, 5700}, ++ /* Japan MMAC */ ++ {34, 5170},{38, 5190},{42, 5210},{46, 5230}, ++ /* Japan */ ++ {184, 4920},{188, 4940},{192, 4960},{196, 4980}, ++ {208, 5040},/* Japan, means J08 */ ++ {212, 5060},/* Japan, means J12 */ ++ {216, 5080},/* Japan, means J16 */ ++}; ++ ++int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq)); ++ ++u32 rtw_ch2freq(u32 channel) ++{ ++ u8 i; ++ u32 freq = 0; ++ ++ for (i = 0; i < ch_freq_map_num; i++) ++ { ++ if (channel == ch_freq_map[i].channel) ++ { ++ freq = ch_freq_map[i].frequency; ++ break; ++ } ++ } ++ if (i == ch_freq_map_num) ++ freq = 2412; ++ ++ return freq; ++} ++ ++u32 rtw_freq2ch(u32 freq) ++{ ++ u8 i; ++ u32 ch = 0; ++ ++ for (i = 0; i < ch_freq_map_num; i++) ++ { ++ if (freq == ch_freq_map[i].frequency) ++ { ++ ch = ch_freq_map[i].channel; ++ break; ++ } ++ } ++ if (i == ch_freq_map_num) ++ ch = 1; ++ ++ return ch; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_security.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_security.c +new file mode 100644 +index 00000000..66df244e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_security.c +@@ -0,0 +1,3159 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_SECURITY_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++//=====WEP related===== ++ ++#define CRC32_POLY 0x04c11db7 ++ ++struct arc4context ++{ ++ u32 x; ++ u32 y; ++ u8 state[256]; ++}; ++ ++ ++static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len) ++{ ++ u32 t, u; ++ u32 keyindex; ++ u32 stateindex; ++ u8 * state; ++ u32 counter; ++_func_enter_; ++ state = parc4ctx->state; ++ parc4ctx->x = 0; ++ parc4ctx->y = 0; ++ for (counter = 0; counter < 256; counter++) ++ state[counter] = (u8)counter; ++ keyindex = 0; ++ stateindex = 0; ++ for (counter = 0; counter < 256; counter++) ++ { ++ t = state[counter]; ++ stateindex = (stateindex + key[keyindex] + t) & 0xff; ++ u = state[stateindex]; ++ state[stateindex] = (u8)t; ++ state[counter] = (u8)u; ++ if (++keyindex >= key_len) ++ keyindex = 0; ++ } ++_func_exit_; ++} ++static u32 arcfour_byte( struct arc4context *parc4ctx) ++{ ++ u32 x; ++ u32 y; ++ u32 sx, sy; ++ u8 * state; ++_func_enter_; ++ state = parc4ctx->state; ++ x = (parc4ctx->x + 1) & 0xff; ++ sx = state[x]; ++ y = (sx + parc4ctx->y) & 0xff; ++ sy = state[y]; ++ parc4ctx->x = x; ++ parc4ctx->y = y; ++ state[y] = (u8)sx; ++ state[x] = (u8)sy; ++_func_exit_; ++ return state[(sx + sy) & 0xff]; ++} ++ ++ ++static void arcfour_encrypt( struct arc4context *parc4ctx, ++ u8 * dest, ++ u8 * src, ++ u32 len) ++{ ++ u32 i; ++_func_enter_; ++ for (i = 0; i < len; i++) ++ dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx); ++_func_exit_; ++} ++ ++static sint bcrc32initialized = 0; ++static u32 crc32_table[256]; ++ ++ ++static u8 crc32_reverseBit( u8 data) ++{ ++ return( (u8)((data<<7)&0x80) | ((data<<5)&0x40) | ((data<<3)&0x20) | ((data<<1)&0x10) | ((data>>1)&0x08) | ((data>>3)&0x04) | ((data>>5)&0x02) | ((data>>7)&0x01) ); ++} ++ ++static void crc32_init(void) ++{ ++_func_enter_; ++ if (bcrc32initialized == 1) ++ goto exit; ++ else{ ++ sint i, j; ++ u32 c; ++ u8 *p=(u8 *)&c, *p1; ++ u8 k; ++ ++ c = 0x12340000; ++ ++ for (i = 0; i < 256; ++i) ++ { ++ k = crc32_reverseBit((u8)i); ++ for (c = ((u32)k) << 24, j = 8; j > 0; --j){ ++ c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1); ++ } ++ p1 = (u8 *)&crc32_table[i]; ++ ++ p1[0] = crc32_reverseBit(p[3]); ++ p1[1] = crc32_reverseBit(p[2]); ++ p1[2] = crc32_reverseBit(p[1]); ++ p1[3] = crc32_reverseBit(p[0]); ++ } ++ bcrc32initialized= 1; ++ } ++exit: ++_func_exit_; ++} ++ ++static u32 getcrc32(u8 *buf, sint len) ++{ ++ u8 *p; ++ u32 crc; ++_func_enter_; ++ if (bcrc32initialized == 0) crc32_init(); ++ ++ crc = 0xffffffff; /* preload shift register, per CRC-32 spec */ ++ ++ for (p = buf; len > 0; ++p, --len) ++ { ++ crc = crc32_table[ (crc ^ *p) & 0xff] ^ (crc >> 8); ++ } ++_func_exit_; ++ return ~crc; /* transmit complement, per CRC-32 spec */ ++} ++ ++ ++/* ++ Need to consider the fragment situation ++*/ ++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ // exclude ICV ++ ++ unsigned char crc[4]; ++ struct arc4context mycontext; ++ ++ sint curfragnum,length; ++ u32 keylength; ++ ++ u8 *pframe, *payload,*iv; //,*wepkey ++ u8 wepkey[16]; ++ u8 hw_hdr_offset=0; ++ struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ ++_func_enter_; ++ ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ hw_hdr_offset = TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ #ifdef CONFIG_TX_EARLY_MODE ++ hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; ++ #else ++ hw_hdr_offset = TXDESC_OFFSET; ++ #endif ++#endif ++ ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; ++ ++ //start to encrypt each fragment ++ if((pattrib->encrypt==_WEP40_)||(pattrib->encrypt==_WEP104_)) ++ { ++ keylength=psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++) ++ { ++ iv=pframe+pattrib->hdrlen; ++ _rtw_memcpy(&wepkey[0], iv, 3); ++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); ++ payload=pframe+pattrib->iv_len+pattrib->hdrlen; ++ ++ if((curfragnum+1)==pattrib->nr_frags) ++ { //the last fragment ++ ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length)); ++ ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ } ++ else ++ { ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length)); ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8 *)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ ++ } ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) ++{ ++ // exclude ICV ++ u8 crc[4]; ++ struct arc4context mycontext; ++ sint length; ++ u32 keylength; ++ u8 *pframe, *payload,*iv,wepkey[16]; ++ u8 keyindex; ++ struct rx_pkt_attrib *prxattrib = &(((union recv_frame*)precvframe)->u.hdr.attrib); ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ ++_func_enter_; ++ ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ ++ //start to decrypt recvframe ++ if((prxattrib->encrypt==_WEP40_)||(prxattrib->encrypt==_WEP104_)) ++ { ++ iv=pframe+prxattrib->hdrlen; ++ //keyindex=(iv[3]&0x3); ++ keyindex = prxattrib->key_index; ++ keylength=psecuritypriv->dot11DefKeylen[keyindex]; ++ _rtw_memcpy(&wepkey[0], iv, 3); ++ //_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); ++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0],keylength); ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ ++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; ++ ++ //decrypt payload include icv ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ ++ //calculate icv and compare the icv ++ *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4)); ++ ++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", ++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); ++ } ++ ++ } ++ ++_func_exit_; ++ ++ return; ++ ++} ++ ++//3 =====TKIP related===== ++ ++static u32 secmicgetuint32( u8 * p ) ++// Convert from Byte[] to Us4Byte32 in a portable way ++{ ++ s32 i; ++ u32 res = 0; ++_func_enter_; ++ for( i=0; i<4; i++ ) ++ { ++ res |= ((u32)(*p++)) << (8*i); ++ } ++_func_exit_; ++ return res; ++} ++ ++static void secmicputuint32( u8 * p, u32 val ) ++// Convert from Us4Byte32 to Byte[] in a portable way ++{ ++ long i; ++_func_enter_; ++ for( i=0; i<4; i++ ) ++ { ++ *p++ = (u8) (val & 0xff); ++ val >>= 8; ++ } ++_func_exit_; ++} ++ ++static void secmicclear(struct mic_data *pmicdata) ++{ ++// Reset the state to the empty message. ++_func_enter_; ++ pmicdata->L = pmicdata->K0; ++ pmicdata->R = pmicdata->K1; ++ pmicdata->nBytesInM = 0; ++ pmicdata->M = 0; ++_func_exit_; ++} ++ ++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ) ++{ ++ // Set the key ++_func_enter_; ++ pmicdata->K0 = secmicgetuint32( key ); ++ pmicdata->K1 = secmicgetuint32( key + 4 ); ++ // and reset the message ++ secmicclear(pmicdata); ++_func_exit_; ++} ++ ++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ) ++{ ++_func_enter_; ++ // Append the byte to our word-sized buffer ++ pmicdata->M |= ((unsigned long)b) << (8*pmicdata->nBytesInM); ++ pmicdata->nBytesInM++; ++ // Process the word if it is full. ++ if( pmicdata->nBytesInM >= 4 ) ++ { ++ pmicdata->L ^= pmicdata->M; ++ pmicdata->R ^= ROL32( pmicdata->L, 17 ); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ROL32( pmicdata->L, 3 ); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ROR32( pmicdata->L, 2 ); ++ pmicdata->L += pmicdata->R; ++ // Clear the buffer ++ pmicdata->M = 0; ++ pmicdata->nBytesInM = 0; ++ } ++_func_exit_; ++} ++ ++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes ) ++{ ++_func_enter_; ++ // This is simple ++ while( nbytes > 0 ) ++ { ++ rtw_secmicappendbyte(pmicdata, *src++ ); ++ nbytes--; ++ } ++_func_exit_; ++} ++ ++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ) ++{ ++_func_enter_; ++ // Append the minimum padding ++ rtw_secmicappendbyte(pmicdata, 0x5a ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ // and then zeroes until the length is a multiple of 4 ++ while( pmicdata->nBytesInM != 0 ) ++ { ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ } ++ // The appendByte function has already computed the result. ++ secmicputuint32( dst, pmicdata->L ); ++ secmicputuint32( dst+4, pmicdata->R ); ++ // Reset to the empty message. ++ secmicclear(pmicdata); ++_func_exit_; ++} ++ ++ ++void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri) ++{ ++ ++ struct mic_data micdata; ++ u8 priority[4]={0x0,0x0,0x0,0x0}; ++_func_enter_; ++ rtw_secmicsetkey(&micdata, key); ++ priority[0]=pri; ++ ++ /* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */ ++ if(header[1]&1){ //ToDS==1 ++ rtw_secmicappend(&micdata, &header[16], 6); //DA ++ if(header[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &header[24], 6); ++ else ++ rtw_secmicappend(&micdata, &header[10], 6); ++ } ++ else{ //ToDS==0 ++ rtw_secmicappend(&micdata, &header[4], 6); //DA ++ if(header[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &header[16], 6); ++ else ++ rtw_secmicappend(&micdata, &header[10], 6); ++ ++ } ++ rtw_secmicappend(&micdata, &priority[0], 4); ++ ++ ++ rtw_secmicappend(&micdata, data, data_len); ++ ++ rtw_secgetmic(&micdata,mic_code); ++_func_exit_; ++} ++ ++ ++ ++ ++/* macros for extraction/creation of unsigned char/unsigned short values */ ++#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15)) ++#define Lo8(v16) ((u8)( (v16) & 0x00FF)) ++#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF)) ++#define Lo16(v32) ((u16)( (v32) & 0xFFFF)) ++#define Hi16(v32) ((u16)(((v32) >>16) & 0xFFFF)) ++#define Mk16(hi,lo) ((lo) ^ (((u16)(hi)) << 8)) ++ ++/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */ ++#define TK16(N) Mk16(tk[2*(N)+1],tk[2*(N)]) ++ ++/* S-box lookup: 16 bits --> 16 bits */ ++#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)]) ++ ++/* fixed algorithm "parameters" */ ++#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */ ++#define TA_SIZE 6 /* 48-bit transmitter address */ ++#define TK_SIZE 16 /* 128-bit temporal key */ ++#define P1K_SIZE 10 /* 80-bit Phase1 key */ ++#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */ ++ ++ ++/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */ ++static const unsigned short Sbox1[2][256]= /* Sbox for hash (can be in ROM) */ ++{ { ++ 0xC6A5,0xF884,0xEE99,0xF68D,0xFF0D,0xD6BD,0xDEB1,0x9154, ++ 0x6050,0x0203,0xCEA9,0x567D,0xE719,0xB562,0x4DE6,0xEC9A, ++ 0x8F45,0x1F9D,0x8940,0xFA87,0xEF15,0xB2EB,0x8EC9,0xFB0B, ++ 0x41EC,0xB367,0x5FFD,0x45EA,0x23BF,0x53F7,0xE496,0x9B5B, ++ 0x75C2,0xE11C,0x3DAE,0x4C6A,0x6C5A,0x7E41,0xF502,0x834F, ++ 0x685C,0x51F4,0xD134,0xF908,0xE293,0xAB73,0x6253,0x2A3F, ++ 0x080C,0x9552,0x4665,0x9D5E,0x3028,0x37A1,0x0A0F,0x2FB5, ++ 0x0E09,0x2436,0x1B9B,0xDF3D,0xCD26,0x4E69,0x7FCD,0xEA9F, ++ 0x121B,0x1D9E,0x5874,0x342E,0x362D,0xDCB2,0xB4EE,0x5BFB, ++ 0xA4F6,0x764D,0xB761,0x7DCE,0x527B,0xDD3E,0x5E71,0x1397, ++ 0xA6F5,0xB968,0x0000,0xC12C,0x4060,0xE31F,0x79C8,0xB6ED, ++ 0xD4BE,0x8D46,0x67D9,0x724B,0x94DE,0x98D4,0xB0E8,0x854A, ++ 0xBB6B,0xC52A,0x4FE5,0xED16,0x86C5,0x9AD7,0x6655,0x1194, ++ 0x8ACF,0xE910,0x0406,0xFE81,0xA0F0,0x7844,0x25BA,0x4BE3, ++ 0xA2F3,0x5DFE,0x80C0,0x058A,0x3FAD,0x21BC,0x7048,0xF104, ++ 0x63DF,0x77C1,0xAF75,0x4263,0x2030,0xE51A,0xFD0E,0xBF6D, ++ 0x814C,0x1814,0x2635,0xC32F,0xBEE1,0x35A2,0x88CC,0x2E39, ++ 0x9357,0x55F2,0xFC82,0x7A47,0xC8AC,0xBAE7,0x322B,0xE695, ++ 0xC0A0,0x1998,0x9ED1,0xA37F,0x4466,0x547E,0x3BAB,0x0B83, ++ 0x8CCA,0xC729,0x6BD3,0x283C,0xA779,0xBCE2,0x161D,0xAD76, ++ 0xDB3B,0x6456,0x744E,0x141E,0x92DB,0x0C0A,0x486C,0xB8E4, ++ 0x9F5D,0xBD6E,0x43EF,0xC4A6,0x39A8,0x31A4,0xD337,0xF28B, ++ 0xD532,0x8B43,0x6E59,0xDAB7,0x018C,0xB164,0x9CD2,0x49E0, ++ 0xD8B4,0xACFA,0xF307,0xCF25,0xCAAF,0xF48E,0x47E9,0x1018, ++ 0x6FD5,0xF088,0x4A6F,0x5C72,0x3824,0x57F1,0x73C7,0x9751, ++ 0xCB23,0xA17C,0xE89C,0x3E21,0x96DD,0x61DC,0x0D86,0x0F85, ++ 0xE090,0x7C42,0x71C4,0xCCAA,0x90D8,0x0605,0xF701,0x1C12, ++ 0xC2A3,0x6A5F,0xAEF9,0x69D0,0x1791,0x9958,0x3A27,0x27B9, ++ 0xD938,0xEB13,0x2BB3,0x2233,0xD2BB,0xA970,0x0789,0x33A7, ++ 0x2DB6,0x3C22,0x1592,0xC920,0x8749,0xAAFF,0x5078,0xA57A, ++ 0x038F,0x59F8,0x0980,0x1A17,0x65DA,0xD731,0x84C6,0xD0B8, ++ 0x82C3,0x29B0,0x5A77,0x1E11,0x7BCB,0xA8FC,0x6DD6,0x2C3A, ++ }, ++ ++ ++ { /* second half of table is unsigned char-reversed version of first! */ ++ 0xA5C6,0x84F8,0x99EE,0x8DF6,0x0DFF,0xBDD6,0xB1DE,0x5491, ++ 0x5060,0x0302,0xA9CE,0x7D56,0x19E7,0x62B5,0xE64D,0x9AEC, ++ 0x458F,0x9D1F,0x4089,0x87FA,0x15EF,0xEBB2,0xC98E,0x0BFB, ++ 0xEC41,0x67B3,0xFD5F,0xEA45,0xBF23,0xF753,0x96E4,0x5B9B, ++ 0xC275,0x1CE1,0xAE3D,0x6A4C,0x5A6C,0x417E,0x02F5,0x4F83, ++ 0x5C68,0xF451,0x34D1,0x08F9,0x93E2,0x73AB,0x5362,0x3F2A, ++ 0x0C08,0x5295,0x6546,0x5E9D,0x2830,0xA137,0x0F0A,0xB52F, ++ 0x090E,0x3624,0x9B1B,0x3DDF,0x26CD,0x694E,0xCD7F,0x9FEA, ++ 0x1B12,0x9E1D,0x7458,0x2E34,0x2D36,0xB2DC,0xEEB4,0xFB5B, ++ 0xF6A4,0x4D76,0x61B7,0xCE7D,0x7B52,0x3EDD,0x715E,0x9713, ++ 0xF5A6,0x68B9,0x0000,0x2CC1,0x6040,0x1FE3,0xC879,0xEDB6, ++ 0xBED4,0x468D,0xD967,0x4B72,0xDE94,0xD498,0xE8B0,0x4A85, ++ 0x6BBB,0x2AC5,0xE54F,0x16ED,0xC586,0xD79A,0x5566,0x9411, ++ 0xCF8A,0x10E9,0x0604,0x81FE,0xF0A0,0x4478,0xBA25,0xE34B, ++ 0xF3A2,0xFE5D,0xC080,0x8A05,0xAD3F,0xBC21,0x4870,0x04F1, ++ 0xDF63,0xC177,0x75AF,0x6342,0x3020,0x1AE5,0x0EFD,0x6DBF, ++ 0x4C81,0x1418,0x3526,0x2FC3,0xE1BE,0xA235,0xCC88,0x392E, ++ 0x5793,0xF255,0x82FC,0x477A,0xACC8,0xE7BA,0x2B32,0x95E6, ++ 0xA0C0,0x9819,0xD19E,0x7FA3,0x6644,0x7E54,0xAB3B,0x830B, ++ 0xCA8C,0x29C7,0xD36B,0x3C28,0x79A7,0xE2BC,0x1D16,0x76AD, ++ 0x3BDB,0x5664,0x4E74,0x1E14,0xDB92,0x0A0C,0x6C48,0xE4B8, ++ 0x5D9F,0x6EBD,0xEF43,0xA6C4,0xA839,0xA431,0x37D3,0x8BF2, ++ 0x32D5,0x438B,0x596E,0xB7DA,0x8C01,0x64B1,0xD29C,0xE049, ++ 0xB4D8,0xFAAC,0x07F3,0x25CF,0xAFCA,0x8EF4,0xE947,0x1810, ++ 0xD56F,0x88F0,0x6F4A,0x725C,0x2438,0xF157,0xC773,0x5197, ++ 0x23CB,0x7CA1,0x9CE8,0x213E,0xDD96,0xDC61,0x860D,0x850F, ++ 0x90E0,0x427C,0xC471,0xAACC,0xD890,0x0506,0x01F7,0x121C, ++ 0xA3C2,0x5F6A,0xF9AE,0xD069,0x9117,0x5899,0x273A,0xB927, ++ 0x38D9,0x13EB,0xB32B,0x3322,0xBBD2,0x70A9,0x8907,0xA733, ++ 0xB62D,0x223C,0x9215,0x20C9,0x4987,0xFFAA,0x7850,0x7AA5, ++ 0x8F03,0xF859,0x8009,0x171A,0xDA65,0x31D7,0xC684,0xB8D0, ++ 0xC382,0xB029,0x775A,0x111E,0xCB7B,0xFCA8,0xD66D,0x3A2C, ++ } ++}; ++ ++ /* ++********************************************************************** ++* Routine: Phase 1 -- generate P1K, given TA, TK, IV32 ++* ++* Inputs: ++* tk[] = temporal key [128 bits] ++* ta[] = transmitter's MAC address [ 48 bits] ++* iv32 = upper 32 bits of IV [ 32 bits] ++* Output: ++* p1k[] = Phase 1 key [ 80 bits] ++* ++* Note: ++* This function only needs to be called every 2**16 packets, ++* although in theory it could be called every packet. ++* ++********************************************************************** ++*/ ++static void phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32) ++{ ++ sint i; ++_func_enter_; ++ /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */ ++ p1k[0] = Lo16(iv32); ++ p1k[1] = Hi16(iv32); ++ p1k[2] = Mk16(ta[1],ta[0]); /* use TA[] as little-endian */ ++ p1k[3] = Mk16(ta[3],ta[2]); ++ p1k[4] = Mk16(ta[5],ta[4]); ++ ++ /* Now compute an unbalanced Feistel cipher with 80-bit block */ ++ /* size on the 80-bit block P1K[], using the 128-bit key TK[] */ ++ for (i=0; i < PHASE1_LOOP_CNT ;i++) ++ { /* Each add operation here is mod 2**16 */ ++ p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0)); ++ p1k[1] += _S_(p1k[0] ^ TK16((i&1)+2)); ++ p1k[2] += _S_(p1k[1] ^ TK16((i&1)+4)); ++ p1k[3] += _S_(p1k[2] ^ TK16((i&1)+6)); ++ p1k[4] += _S_(p1k[3] ^ TK16((i&1)+0)); ++ p1k[4] += (unsigned short)i; /* avoid "slide attacks" */ ++ } ++_func_exit_; ++} ++ ++ ++/* ++********************************************************************** ++* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16 ++* ++* Inputs: ++* tk[] = Temporal key [128 bits] ++* p1k[] = Phase 1 output key [ 80 bits] ++* iv16 = low 16 bits of IV counter [ 16 bits] ++* Output: ++* rc4key[] = the key used to encrypt the packet [128 bits] ++* ++* Note: ++* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique ++* across all packets using the same key TK value. Then, for a ++* given value of TK[], this TKIP48 construction guarantees that ++* the final RC4KEY value is unique across all packets. ++* ++* Suggested implementation optimization: if PPK[] is "overlaid" ++* appropriately on RC4KEY[], there is no need for the final ++* for loop below that copies the PPK[] result into RC4KEY[]. ++* ++********************************************************************** ++*/ ++static void phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16) ++{ ++ sint i; ++ u16 PPK[6]; /* temporary key for mixing */ ++_func_enter_; ++ /* Note: all adds in the PPK[] equations below are mod 2**16 */ ++ for (i=0;i<5;i++) PPK[i]=p1k[i]; /* first, copy P1K to PPK */ ++ PPK[5] = p1k[4] +iv16; /* next, add in IV16 */ ++ ++ /* Bijective non-linear mixing of the 96 bits of PPK[0..5] */ ++ PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */ ++ PPK[1] += _S_(PPK[0] ^ TK16(1)); ++ PPK[2] += _S_(PPK[1] ^ TK16(2)); ++ PPK[3] += _S_(PPK[2] ^ TK16(3)); ++ PPK[4] += _S_(PPK[3] ^ TK16(4)); ++ PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */ ++ ++ /* Final sweep: bijective, "linear". Rotates kill LSB correlations */ ++ PPK[0] += RotR1(PPK[5] ^ TK16(6)); ++ PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */ ++ PPK[2] += RotR1(PPK[1]); ++ PPK[3] += RotR1(PPK[2]); ++ PPK[4] += RotR1(PPK[3]); ++ PPK[5] += RotR1(PPK[4]); ++ /* Note: At this point, for a given key TK[0..15], the 96-bit output */ ++ /* value PPK[0..5] is guaranteed to be unique, as a function */ ++ /* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */ ++ /* is now a keyed permutation of {TA,IV32,IV16}. */ ++ ++ /* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */ ++ rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */ ++ rc4key[1] =(Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */ ++ rc4key[2] = Lo8(iv16); ++ rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1); ++ ++ ++ /* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */ ++ for (i=0;i<6;i++) ++ { ++ rc4key[4+2*i] = Lo8(PPK[i]); ++ rc4key[5+2*i] = Hi8(PPK[i]); ++ } ++_func_exit_; ++} ++ ++ ++//The hlen isn't include the IV ++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ // exclude ICV ++ u16 pnl; ++ u32 pnh; ++ u8 rc4key[16]; ++ u8 ttkey[16]; ++ u8 crc[4]; ++ u8 hw_hdr_offset = 0; ++ struct arc4context mycontext; ++ sint curfragnum,length; ++ u32 prwskeylen; ++ ++ u8 *pframe, *payload,*iv,*prwskey; ++ union pn48 dot11txpn; ++ struct sta_info *stainfo; ++ struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ u32 res=_SUCCESS; ++_func_enter_; ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return _FAIL; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ hw_hdr_offset = TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ #ifdef CONFIG_TX_EARLY_MODE ++ hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; ++ #else ++ hw_hdr_offset = TXDESC_OFFSET; ++ #endif ++#endif ++ ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; ++ //4 start to encrypt each fragment ++ if(pattrib->encrypt==_TKIP_){ ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); ++ } ++ ++ if (stainfo!=NULL){ ++ ++ if(!(stainfo->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); ++ return _FAIL; ++ } ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(pattrib->ra)) ++ { ++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ } ++ ++ prwskeylen=16; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ iv=pframe+pattrib->hdrlen; ++ payload=pframe+pattrib->iv_len+pattrib->hdrlen; ++ ++ GET_TKIP_PN(iv, dot11txpn); ++ ++ pnl=(u16)(dot11txpn.val); ++ pnh=(u32)(dot11txpn.val>>16); ++ ++ phase1((u16 *)&ttkey[0],prwskey,&pattrib->ta[0],pnh); ++ ++ phase2(&rc4key[0],prwskey,(u16 *)&ttkey[0],pnl); ++ ++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ RT_TRACE(_module_rtl871x_security_c_,_drv_info_,("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len,pattrib->icv_len)); ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ ++ ++ arcfour_init(&mycontext, rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ ++ arcfour_init(&mycontext,rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8 *)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n")); ++ DBG_871X("%s, psta==NUL\n", __func__); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++ return res; ++ ++} ++ ++ ++//The hlen isn't include the IV ++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) ++{ // exclude ICV ++ u16 pnl; ++ u32 pnh; ++ u8 rc4key[16]; ++ u8 ttkey[16]; ++ u8 crc[4]; ++ struct arc4context mycontext; ++ sint length; ++ u32 prwskeylen; ++ ++ u8 *pframe, *payload,*iv,*prwskey; ++ union pn48 dot11txpn; ++ struct sta_info *stainfo; ++ struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++// struct recv_priv *precvpriv=&padapter->recvpriv; ++ u32 res=_SUCCESS; ++ ++_func_enter_; ++ ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ ++ //4 start to decrypt recvframe ++ if(prxattrib->encrypt==_TKIP_){ ++ ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); ++ if (stainfo!=NULL){ ++ ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ static u32 start = 0; ++ static u32 no_gkey_bc_cnt = 0; ++ static u32 no_gkey_mc_cnt = 0; ++ ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ ++ if (start == 0) ++ start = rtw_get_current_time(); ++ ++ if (is_broadcast_mac_addr(prxattrib->ra)) ++ no_gkey_bc_cnt++; ++ else ++ no_gkey_mc_cnt++; ++ ++ if (rtw_get_passing_time_ms(start) > 1000) { ++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", ++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); ++ } ++ start = rtw_get_current_time(); ++ no_gkey_bc_cnt = 0; ++ no_gkey_mc_cnt = 0; ++ } ++ goto exit; ++ } ++ ++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", ++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); ++ } ++ start = 0; ++ no_gkey_bc_cnt = 0; ++ no_gkey_mc_cnt = 0; ++ ++ //DBG_871X("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); ++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; ++ prwskeylen=16; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo!=NULL!!!\n")); ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ prwskeylen=16; ++ } ++ ++ iv=pframe+prxattrib->hdrlen; ++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ ++ GET_TKIP_PN(iv, dot11txpn); ++ ++ pnl=(u16)(dot11txpn.val); ++ pnh=(u32)(dot11txpn.val>>16); ++ ++ phase1((u16 *)&ttkey[0],prwskey,&prxattrib->ta[0],pnh); ++ phase2(&rc4key[0],prwskey,(unsigned short *)&ttkey[0],pnl); ++ ++ //4 decrypt payload include icv ++ ++ arcfour_init(&mycontext, rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ ++ *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4)); ++ ++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", ++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); ++ res=_FAIL; ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++exit: ++ return res; ++ ++} ++ ++ ++//3 =====AES related===== ++ ++ ++ ++#define MAX_MSG_SIZE 2048 ++/*****************************/ ++/******** SBOX Table *********/ ++/*****************************/ ++ ++ static u8 sbox_table[256] = ++ { ++ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, ++ 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, ++ 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, ++ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, ++ 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, ++ 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, ++ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, ++ 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, ++ 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, ++ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, ++ 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, ++ 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, ++ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, ++ 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, ++ 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, ++ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, ++ 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, ++ 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, ++ 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, ++ 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, ++ 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, ++ 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, ++ 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, ++ 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, ++ 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, ++ 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, ++ 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, ++ 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, ++ 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, ++ 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, ++ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, ++ 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 ++ }; ++ ++/*****************************/ ++/**** Function Prototypes ****/ ++/*****************************/ ++ ++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out); ++static void construct_mic_iv( ++ u8 *mic_header1, ++ sint qc_exists, ++ sint a4_exists, ++ u8 *mpdu, ++ uint payload_length, ++ u8 * pn_vector, ++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use ++static void construct_mic_header1( ++ u8 *mic_header1, ++ sint header_length, ++ u8 *mpdu, ++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use ++static void construct_mic_header2( ++ u8 *mic_header2, ++ u8 *mpdu, ++ sint a4_exists, ++ sint qc_exists); ++static void construct_ctr_preload( ++ u8 *ctr_preload, ++ sint a4_exists, ++ sint qc_exists, ++ u8 *mpdu, ++ u8 *pn_vector, ++ sint c, ++ uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use ++static void xor_128(u8 *a, u8 *b, u8 *out); ++static void xor_32(u8 *a, u8 *b, u8 *out); ++static u8 sbox(u8 a); ++static void next_key(u8 *key, sint round); ++static void byte_sub(u8 *in, u8 *out); ++static void shift_row(u8 *in, u8 *out); ++static void mix_column(u8 *in, u8 *out); ++#ifndef PLATFORM_FREEBSD ++static void add_round_key( u8 *shiftrow_in, ++ u8 *mcol_in, ++ u8 *block_in, ++ sint round, ++ u8 *out); ++#endif //PLATFORM_FREEBSD ++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); ++ ++ ++/****************************************/ ++/* aes128k128d() */ ++/* Performs a 128 bit AES encrypt with */ ++/* 128 bit data. */ ++/****************************************/ ++static void xor_128(u8 *a, u8 *b, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0;i<16; i++) ++ { ++ out[i] = a[i] ^ b[i]; ++ } ++_func_exit_; ++} ++ ++ ++static void xor_32(u8 *a, u8 *b, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0;i<4; i++) ++ { ++ out[i] = a[i] ^ b[i]; ++ } ++_func_exit_; ++} ++ ++ ++static u8 sbox(u8 a) ++{ ++ return sbox_table[(sint)a]; ++} ++ ++ ++static void next_key(u8 *key, sint round) ++{ ++ u8 rcon; ++ u8 sbox_key[4]; ++ u8 rcon_table[12] = ++ { ++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, ++ 0x1b, 0x36, 0x36, 0x36 ++ }; ++_func_enter_; ++ sbox_key[0] = sbox(key[13]); ++ sbox_key[1] = sbox(key[14]); ++ sbox_key[2] = sbox(key[15]); ++ sbox_key[3] = sbox(key[12]); ++ ++ rcon = rcon_table[round]; ++ ++ xor_32(&key[0], sbox_key, &key[0]); ++ key[0] = key[0] ^ rcon; ++ ++ xor_32(&key[4], &key[0], &key[4]); ++ xor_32(&key[8], &key[4], &key[8]); ++ xor_32(&key[12], &key[8], &key[12]); ++_func_exit_; ++} ++ ++ ++static void byte_sub(u8 *in, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0; i< 16; i++) ++ { ++ out[i] = sbox(in[i]); ++ } ++_func_exit_; ++} ++ ++ ++static void shift_row(u8 *in, u8 *out) ++{ ++_func_enter_; ++ out[0] = in[0]; ++ out[1] = in[5]; ++ out[2] = in[10]; ++ out[3] = in[15]; ++ out[4] = in[4]; ++ out[5] = in[9]; ++ out[6] = in[14]; ++ out[7] = in[3]; ++ out[8] = in[8]; ++ out[9] = in[13]; ++ out[10] = in[2]; ++ out[11] = in[7]; ++ out[12] = in[12]; ++ out[13] = in[1]; ++ out[14] = in[6]; ++ out[15] = in[11]; ++_func_exit_; ++} ++ ++ ++static void mix_column(u8 *in, u8 *out) ++{ ++ sint i; ++ u8 add1b[4]; ++ u8 add1bf7[4]; ++ u8 rotl[4]; ++ u8 swap_halfs[4]; ++ u8 andf7[4]; ++ u8 rotr[4]; ++ u8 temp[4]; ++ u8 tempb[4]; ++_func_enter_; ++ for (i=0 ; i<4; i++) ++ { ++ if ((in[i] & 0x80)== 0x80) ++ add1b[i] = 0x1b; ++ else ++ add1b[i] = 0x00; ++ } ++ ++ swap_halfs[0] = in[2]; /* Swap halfs */ ++ swap_halfs[1] = in[3]; ++ swap_halfs[2] = in[0]; ++ swap_halfs[3] = in[1]; ++ ++ rotl[0] = in[3]; /* Rotate left 8 bits */ ++ rotl[1] = in[0]; ++ rotl[2] = in[1]; ++ rotl[3] = in[2]; ++ ++ andf7[0] = in[0] & 0x7f; ++ andf7[1] = in[1] & 0x7f; ++ andf7[2] = in[2] & 0x7f; ++ andf7[3] = in[3] & 0x7f; ++ ++ for (i = 3; i>0; i--) /* logical shift left 1 bit */ ++ { ++ andf7[i] = andf7[i] << 1; ++ if ((andf7[i-1] & 0x80) == 0x80) ++ { ++ andf7[i] = (andf7[i] | 0x01); ++ } ++ } ++ andf7[0] = andf7[0] << 1; ++ andf7[0] = andf7[0] & 0xfe; ++ ++ xor_32(add1b, andf7, add1bf7); ++ ++ xor_32(in, add1bf7, rotr); ++ ++ temp[0] = rotr[0]; /* Rotate right 8 bits */ ++ rotr[0] = rotr[1]; ++ rotr[1] = rotr[2]; ++ rotr[2] = rotr[3]; ++ rotr[3] = temp[0]; ++ ++ xor_32(add1bf7, rotr, temp); ++ xor_32(swap_halfs, rotl,tempb); ++ xor_32(temp, tempb, out); ++_func_exit_; ++} ++ ++ ++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) ++{ ++ sint round; ++ sint i; ++ u8 intermediatea[16]; ++ u8 intermediateb[16]; ++ u8 round_key[16]; ++_func_enter_; ++ for(i=0; i<16; i++) round_key[i] = key[i]; ++ ++ for (round = 0; round < 11; round++) ++ { ++ if (round == 0) ++ { ++ xor_128(round_key, data, ciphertext); ++ next_key(round_key, round); ++ } ++ else if (round == 10) ++ { ++ byte_sub(ciphertext, intermediatea); ++ shift_row(intermediatea, intermediateb); ++ xor_128(intermediateb, round_key, ciphertext); ++ } ++ else /* 1 - 9 */ ++ { ++ byte_sub(ciphertext, intermediatea); ++ shift_row(intermediatea, intermediateb); ++ mix_column(&intermediateb[0], &intermediatea[0]); ++ mix_column(&intermediateb[4], &intermediatea[4]); ++ mix_column(&intermediateb[8], &intermediatea[8]); ++ mix_column(&intermediateb[12], &intermediatea[12]); ++ xor_128(intermediatea, round_key, ciphertext); ++ next_key(round_key, round); ++ } ++ } ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_iv() */ ++/* Builds the MIC IV from header fields and PN */ ++/* Baron think the function is construct CCM */ ++/* nonce */ ++/************************************************/ ++static void construct_mic_iv( ++ u8 *mic_iv, ++ sint qc_exists, ++ sint a4_exists, ++ u8 *mpdu, ++ uint payload_length, ++ u8 *pn_vector, ++ uint frtype// add for CONFIG_IEEE80211W, none 11w also can use ++ ) ++{ ++ sint i; ++_func_enter_; ++ mic_iv[0] = 0x59; ++ if (qc_exists && a4_exists) mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */ ++ if (qc_exists && !a4_exists) mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ ++ if (!qc_exists) mic_iv[1] = 0x00; ++#ifdef CONFIG_IEEE80211W ++ //802.11w management frame should set management bit(4) ++ if(frtype == WIFI_MGT_TYPE) ++ mic_iv[1] |= BIT(4); ++#endif //CONFIG_IEEE80211W ++ for (i = 2; i < 8; i++) ++ mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ ++ #ifdef CONSISTENT_PN_ORDER ++ for (i = 8; i < 14; i++) ++ mic_iv[i] = pn_vector[i - 8]; /* mic_iv[8:13] = PN[0:5] */ ++ #else ++ for (i = 8; i < 14; i++) ++ mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */ ++ #endif ++ mic_iv[14] = (unsigned char) (payload_length / 256); ++ mic_iv[15] = (unsigned char) (payload_length % 256); ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header1() */ ++/* Builds the first MIC header block from */ ++/* header fields. */ ++/* Build AAD SC,A1,A2 */ ++/************************************************/ ++static void construct_mic_header1( ++ u8 *mic_header1, ++ sint header_length, ++ u8 *mpdu, ++ uint frtype// add for CONFIG_IEEE80211W, none 11w also can use ++ ) ++{ ++_func_enter_; ++ mic_header1[0] = (u8)((header_length - 2) / 256); ++ mic_header1[1] = (u8)((header_length - 2) % 256); ++#ifdef CONFIG_IEEE80211W ++ //802.11w management frame don't AND subtype bits 4,5,6 of frame control field ++ if(frtype == WIFI_MGT_TYPE) ++ mic_header1[2] = mpdu[0]; /* Mute CF poll & CF ack bits */ ++ else ++#endif //CONFIG_IEEE80211W ++ mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ ++ ++ mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ ++ mic_header1[4] = mpdu[4]; /* A1 */ ++ mic_header1[5] = mpdu[5]; ++ mic_header1[6] = mpdu[6]; ++ mic_header1[7] = mpdu[7]; ++ mic_header1[8] = mpdu[8]; ++ mic_header1[9] = mpdu[9]; ++ mic_header1[10] = mpdu[10]; /* A2 */ ++ mic_header1[11] = mpdu[11]; ++ mic_header1[12] = mpdu[12]; ++ mic_header1[13] = mpdu[13]; ++ mic_header1[14] = mpdu[14]; ++ mic_header1[15] = mpdu[15]; ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header2() */ ++/* Builds the last MIC header block from */ ++/* header fields. */ ++/************************************************/ ++static void construct_mic_header2( ++ u8 *mic_header2, ++ u8 *mpdu, ++ sint a4_exists, ++ sint qc_exists ++ ) ++{ ++ sint i; ++_func_enter_; ++ for (i = 0; i<16; i++) mic_header2[i]=0x00; ++ ++ mic_header2[0] = mpdu[16]; /* A3 */ ++ mic_header2[1] = mpdu[17]; ++ mic_header2[2] = mpdu[18]; ++ mic_header2[3] = mpdu[19]; ++ mic_header2[4] = mpdu[20]; ++ mic_header2[5] = mpdu[21]; ++ ++ //mic_header2[6] = mpdu[22] & 0xf0; /* SC */ ++ mic_header2[6] = 0x00; ++ mic_header2[7] = 0x00; /* mpdu[23]; */ ++ ++ ++ if (!qc_exists && a4_exists) ++ { ++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ ++ ++ } ++ ++ if (qc_exists && !a4_exists) ++ { ++ mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */ ++ mic_header2[9] = mpdu[25] & 0x00; ++ } ++ ++ if (qc_exists && a4_exists) ++ { ++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ ++ ++ mic_header2[14] = mpdu[30] & 0x0f; ++ mic_header2[15] = mpdu[31] & 0x00; ++ } ++ ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header2() */ ++/* Builds the last MIC header block from */ ++/* header fields. */ ++/* Baron think the function is construct CCM */ ++/* nonce */ ++/************************************************/ ++static void construct_ctr_preload( ++ u8 *ctr_preload, ++ sint a4_exists, ++ sint qc_exists, ++ u8 *mpdu, ++ u8 *pn_vector, ++ sint c, ++ uint frtype // add for CONFIG_IEEE80211W, none 11w also can use ++ ) ++{ ++ sint i = 0; ++_func_enter_; ++ for (i=0; i<16; i++) ctr_preload[i] = 0x00; ++ i = 0; ++ ++ ctr_preload[0] = 0x01; /* flag */ ++ if (qc_exists && a4_exists) ++ ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ ++ if (qc_exists && !a4_exists) ++ ctr_preload[1] = mpdu[24] & 0x0f; ++#ifdef CONFIG_IEEE80211W ++ //802.11w management frame should set management bit(4) ++ if(frtype == WIFI_MGT_TYPE) ++ ctr_preload[1] |= BIT(4); ++#endif //CONFIG_IEEE80211W ++ for (i = 2; i < 8; i++) ++ ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ ++ #ifdef CONSISTENT_PN_ORDER ++ for (i = 8; i < 14; i++) ++ ctr_preload[i] = pn_vector[i - 8]; /* ctr_preload[8:13] = PN[0:5] */ ++ #else ++ for (i = 8; i < 14; i++) ++ ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */ ++ #endif ++ ctr_preload[14] = (unsigned char) (c / 256); /* Ctr */ ++ ctr_preload[15] = (unsigned char) (c % 256); ++_func_exit_; ++} ++ ++ ++/************************************/ ++/* bitwise_xor() */ ++/* A 128 bit, bitwise exclusive or */ ++/************************************/ ++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0; i<16; i++) ++ { ++ out[i] = ina[i] ^ inb[i]; ++ } ++_func_exit_; ++} ++ ++ ++static sint aes_cipher(u8 *key, uint hdrlen, ++ u8 *pframe, uint plen) ++{ ++// /*static*/ unsigned char message[MAX_MSG_SIZE]; ++ uint qc_exists, a4_exists, i, j, payload_remainder, ++ num_blocks, payload_index; ++ ++ u8 pn_vector[6]; ++ u8 mic_iv[16]; ++ u8 mic_header1[16]; ++ u8 mic_header2[16]; ++ u8 ctr_preload[16]; ++ ++ /* Intermediate Buffers */ ++ u8 chain_buffer[16]; ++ u8 aes_out[16]; ++ u8 padded_buffer[16]; ++ u8 mic[8]; ++// uint offset = 0; ++ uint frtype = GetFrameType(pframe); ++ uint frsubtype = GetFrameSubType(pframe); ++ ++_func_enter_; ++ frsubtype=frsubtype>>4; ++ ++ ++ _rtw_memset((void *)mic_iv, 0, 16); ++ _rtw_memset((void *)mic_header1, 0, 16); ++ _rtw_memset((void *)mic_header2, 0, 16); ++ _rtw_memset((void *)ctr_preload, 0, 16); ++ _rtw_memset((void *)chain_buffer, 0, 16); ++ _rtw_memset((void *)aes_out, 0, 16); ++ _rtw_memset((void *)padded_buffer, 0, 16); ++ ++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) ++ a4_exists = 0; ++ else ++ a4_exists = 1; ++ ++ if ( ++ ((frtype|frsubtype) == WIFI_DATA_CFACK) || ++ ((frtype|frsubtype) == WIFI_DATA_CFPOLL)|| ++ ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL)) ++ { ++ qc_exists = 1; ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ } ++ // add for CONFIG_IEEE80211W, none 11w also can use ++ else if ((frtype == WIFI_DATA) && ++ ((frsubtype == 0x08) || ++ (frsubtype == 0x09)|| ++ (frsubtype == 0x0a)|| ++ (frsubtype == 0x0b))) ++ { ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ qc_exists = 1; ++ } ++ else ++ qc_exists = 0; ++ ++ pn_vector[0]=pframe[hdrlen]; ++ pn_vector[1]=pframe[hdrlen+1]; ++ pn_vector[2]=pframe[hdrlen+4]; ++ pn_vector[3]=pframe[hdrlen+5]; ++ pn_vector[4]=pframe[hdrlen+6]; ++ pn_vector[5]=pframe[hdrlen+7]; ++ ++ construct_mic_iv( ++ mic_iv, ++ qc_exists, ++ a4_exists, ++ pframe, //message, ++ plen, ++ pn_vector, ++ frtype // add for CONFIG_IEEE80211W, none 11w also can use ++ ); ++ ++ construct_mic_header1( ++ mic_header1, ++ hdrlen, ++ pframe, //message ++ frtype // add for CONFIG_IEEE80211W, none 11w also can use ++ ); ++ construct_mic_header2( ++ mic_header2, ++ pframe, //message, ++ a4_exists, ++ qc_exists ++ ); ++ ++ ++ payload_remainder = plen % 16; ++ num_blocks = plen / 16; ++ ++ /* Find start of payload */ ++ payload_index = (hdrlen + 8); ++ ++ /* Calculate MIC */ ++ aes128k128d(key, mic_iv, aes_out); ++ bitwise_xor(aes_out, mic_header1, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ bitwise_xor(aes_out, mic_header2, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ for (i = 0; i < num_blocks; i++) ++ { ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ ++ payload_index += 16; ++ aes128k128d(key, chain_buffer, aes_out); ++ } ++ ++ /* Add on the final payload block if it needs padding */ ++ if (payload_remainder > 0) ++ { ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index++];//padded_buffer[j] = message[payload_index++]; ++ } ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ } ++ ++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; ++ ++ /* Insert MIC into payload */ ++ for (j = 0; j < 8; j++) ++ pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; ++ ++ payload_index = hdrlen + 8; ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, //message, ++ pn_vector, ++ i+1, ++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, //message, ++ pn_vector, ++ num_blocks+1, ++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index+j];//padded_buffer[j] = message[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; jattrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ ++// uint offset = 0; ++ u32 res=_SUCCESS; ++_func_enter_; ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return _FAIL; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ hw_hdr_offset = TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ #ifdef CONFIG_TX_EARLY_MODE ++ hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; ++ #else ++ hw_hdr_offset = TXDESC_OFFSET; ++ #endif ++#endif ++ ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; ++ ++ //4 start to encrypt each fragment ++ if((pattrib->encrypt==_AES_)){ ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); ++ } ++ ++ if (stainfo!=NULL){ ++ ++ if(!(stainfo->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); ++ return _FAIL; ++ } ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(pattrib->ra)) ++ { ++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ } ++ ++#ifdef CONFIG_TDLS //swencryption ++ { ++ struct sta_info *ptdls_sta; ++ ptdls_sta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->dst[0] ); ++ if((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) ) ++ { ++ DBG_871X("[%s] for tdls link\n", __FUNCTION__); ++ prwskey=&ptdls_sta->tpk.tk[0]; ++ } ++ } ++#endif //CONFIG_TDLS ++ ++ prwskeylen=16; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ ++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ ++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length); ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ ++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length); ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8*)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); ++ DBG_871X("%s, psta==NUL\n", __func__); ++ res=_FAIL; ++ } ++ ++ } ++ ++ ++ ++_func_exit_; ++ return res; ++} ++ ++static sint aes_decipher(u8 *key, uint hdrlen, ++ u8 *pframe, uint plen) ++{ ++ static u8 message[MAX_MSG_SIZE]; ++ uint qc_exists, a4_exists, i, j, payload_remainder, ++ num_blocks, payload_index; ++ sint res = _SUCCESS; ++ u8 pn_vector[6]; ++ u8 mic_iv[16]; ++ u8 mic_header1[16]; ++ u8 mic_header2[16]; ++ u8 ctr_preload[16]; ++ ++ /* Intermediate Buffers */ ++ u8 chain_buffer[16]; ++ u8 aes_out[16]; ++ u8 padded_buffer[16]; ++ u8 mic[8]; ++ ++ ++// uint offset = 0; ++ uint frtype = GetFrameType(pframe); ++ uint frsubtype = GetFrameSubType(pframe); ++_func_enter_; ++ frsubtype=frsubtype>>4; ++ ++ ++ _rtw_memset((void *)mic_iv, 0, 16); ++ _rtw_memset((void *)mic_header1, 0, 16); ++ _rtw_memset((void *)mic_header2, 0, 16); ++ _rtw_memset((void *)ctr_preload, 0, 16); ++ _rtw_memset((void *)chain_buffer, 0, 16); ++ _rtw_memset((void *)aes_out, 0, 16); ++ _rtw_memset((void *)padded_buffer, 0, 16); ++ ++ //start to decrypt the payload ++ ++ num_blocks = (plen-8) / 16; //(plen including LLC, payload_length and mic ) ++ ++ payload_remainder = (plen-8) % 16; ++ ++ pn_vector[0] = pframe[hdrlen]; ++ pn_vector[1] = pframe[hdrlen+1]; ++ pn_vector[2] = pframe[hdrlen+4]; ++ pn_vector[3] = pframe[hdrlen+5]; ++ pn_vector[4] = pframe[hdrlen+6]; ++ pn_vector[5] = pframe[hdrlen+7]; ++ ++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) ++ a4_exists = 0; ++ else ++ a4_exists = 1; ++ ++ if ( ++ ((frtype|frsubtype) == WIFI_DATA_CFACK) || ++ ((frtype|frsubtype) == WIFI_DATA_CFPOLL)|| ++ ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL)) ++ { ++ qc_exists = 1; ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ }//only for data packet . add for CONFIG_IEEE80211W, none 11w also can use ++ else if ((frtype == WIFI_DATA) && ++ ((frsubtype == 0x08) || ++ (frsubtype == 0x09)|| ++ (frsubtype == 0x0a)|| ++ (frsubtype == 0x0b))) ++ { ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ qc_exists = 1; ++ } ++ else ++ qc_exists = 0; ++ ++ ++ // now, decrypt pframe with hdrlen offset and plen long ++ ++ payload_index = hdrlen + 8; // 8 is for extiv ++ ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, ++ pn_vector, ++ i+1, ++ frtype ++ ); ++ ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer); ++ ++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, ++ pn_vector, ++ num_blocks+1, ++ frtype // add for CONFIG_IEEE80211W, none 11w also can use ++ ); ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; j 0) ++ { ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = message[payload_index++]; ++ } ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ } ++ ++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; ++ ++ /* Insert MIC into payload */ ++ for (j = 0; j < 8; j++) ++ message[payload_index+j] = mic[j]; ++ ++ payload_index = hdrlen + 8; ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ message, ++ pn_vector, ++ i+1, ++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ message, ++ pn_vector, ++ num_blocks+1, ++ frtype); // add for CONFIG_IEEE80211W, none 11w also can use ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = message[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; ju.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++// struct recv_priv *precvpriv=&padapter->recvpriv; ++ u32 res=_SUCCESS; ++_func_enter_; ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ //4 start to encrypt each fragment ++ if((prxattrib->encrypt==_AES_)){ ++ ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); ++ if (stainfo!=NULL){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_decrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ static u32 start = 0; ++ static u32 no_gkey_bc_cnt = 0; ++ static u32 no_gkey_mc_cnt = 0; ++ ++ //in concurrent we should use sw descrypt in group key, so we remove this message ++ //DBG_871X("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); ++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ ++ if (start == 0) ++ start = rtw_get_current_time(); ++ ++ if (is_broadcast_mac_addr(prxattrib->ra)) ++ no_gkey_bc_cnt++; ++ else ++ no_gkey_mc_cnt++; ++ ++ if (rtw_get_passing_time_ms(start) > 1000) { ++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", ++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); ++ } ++ start = rtw_get_current_time(); ++ no_gkey_bc_cnt = 0; ++ no_gkey_mc_cnt = 0; ++ } ++ ++ goto exit; ++ } ++ ++ if (no_gkey_bc_cnt || no_gkey_mc_cnt) { ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", ++ FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); ++ } ++ start = 0; ++ no_gkey_bc_cnt = 0; ++ no_gkey_mc_cnt = 0; ++ ++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; ++ if(psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) ++ { ++ DBG_871X("not match packet_index=%d, install_index=%d \n" ++ , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); ++ res=_FAIL; ++ goto exit; ++ } ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ } ++ ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ /*// add for CONFIG_IEEE80211W, debug ++ if(0) ++ printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d \n" ++ , length, prxattrib->hdrlen, prxattrib->pkt_len); ++ if(0) ++ { ++ int no; ++ //test print PSK ++ printk("PSK key below:\n"); ++ for(no=0;no<16;no++) ++ printk(" %02x ", prwskey[no]); ++ printk("\n"); ++ } ++ if(0) ++ { ++ int no; ++ //test print PSK ++ printk("frame:\n"); ++ for(no=0;nopkt_len;no++) ++ printk(" %02x ", pframe[no]); ++ printk("\n"); ++ }*/ ++ ++ res= aes_decipher(prwskey,prxattrib->hdrlen,pframe, length); ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++exit: ++ return res; ++} ++ ++#ifdef CONFIG_IEEE80211W ++u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe) ++{ ++ struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; ++ u8 *pframe; ++ u8 *BIP_AAD, *p; ++ u32 res=_FAIL; ++ uint len, ori_len; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u8 mic[16]; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ori_len = pattrib->pkt_len-WLAN_HDR_A3_LEN+BIP_AAD_SIZE; ++ BIP_AAD = rtw_zmalloc(ori_len); ++ ++ if(BIP_AAD == NULL) ++ { ++ DBG_871X("BIP AAD allocate fail\n"); ++ return _FAIL; ++ } ++ //PKT start ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ //mapping to wlan header ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ //save the frame body + MME ++ _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, pframe+WLAN_HDR_A3_LEN, pattrib->pkt_len-WLAN_HDR_A3_LEN); ++ //find MME IE pointer ++ p = rtw_get_ie(BIP_AAD+BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len-WLAN_HDR_A3_LEN); ++ //Baron ++ if(p) ++ { ++ u16 keyid=0; ++ u64 temp_ipn=0; ++ //save packet number ++ _rtw_memcpy(&temp_ipn, p+4, 6); ++ temp_ipn = le64_to_cpu(temp_ipn); ++ //BIP packet number should bigger than previous BIP packet ++ if(temp_ipn <= pmlmeext->mgnt_80211w_IPN_rx) ++ { ++ DBG_871X("replay BIP packet\n"); ++ goto BIP_exit; ++ } ++ //copy key index ++ _rtw_memcpy(&keyid, p+2, 2); ++ keyid = le16_to_cpu(keyid); ++ if(keyid != padapter->securitypriv.dot11wBIPKeyid) ++ { ++ DBG_871X("BIP key index error!\n"); ++ goto BIP_exit; ++ } ++ //clear the MIC field of MME to zero ++ _rtw_memset(p+2+len-8, 0, 8); ++ ++ //conscruct AAD, copy frame control field ++ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); ++ ClearRetry(BIP_AAD); ++ ClearPwrMgt(BIP_AAD); ++ ClearMData(BIP_AAD); ++ //conscruct AAD, copy address 1 to address 3 ++ _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18); ++ ++ if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey ++ , BIP_AAD, ori_len, mic)) ++ goto BIP_exit; ++ ++ /*//management packet content ++ { ++ int pp; ++ DBG_871X("pkt: "); ++ for(pp=0;pp< pattrib->pkt_len; pp++) ++ printk(" %02x ", pframe[pp]); ++ DBG_871X("\n"); ++ //BIP AAD + management frame body + MME(MIC is zero) ++ DBG_871X("AAD+PKT: "); ++ for(pp=0;pp< ori_len; pp++) ++ DBG_871X(" %02x ", BIP_AAD[pp]); ++ DBG_871X("\n"); ++ //show the MIC result ++ DBG_871X("mic: "); ++ for(pp=0;pp<16; pp++) ++ DBG_871X(" %02x ", mic[pp]); ++ DBG_871X("\n"); ++ } ++ */ ++ //MIC field should be last 8 bytes of packet (packet without FCS) ++ if(_rtw_memcmp(mic, pframe+pattrib->pkt_len-8, 8)) ++ { ++ pmlmeext->mgnt_80211w_IPN_rx = temp_ipn; ++ res=_SUCCESS; ++ } ++ else ++ DBG_871X("BIP MIC error!\n"); ++ ++ } ++ else ++ res = RTW_RX_HANDLED; ++BIP_exit: ++ ++ rtw_mfree(BIP_AAD, ori_len); ++ return res; ++} ++#endif //CONFIG_IEEE80211W ++ ++#ifndef PLATFORM_FREEBSD ++/* compress 512-bits */ ++static int sha256_compress(struct sha256_state *md, unsigned char *buf) ++{ ++ u32 S[8], W[64], t0, t1; ++ u32 t; ++ int i; ++ ++ /* copy state into S */ ++ for (i = 0; i < 8; i++) { ++ S[i] = md->state[i]; ++ } ++ ++ /* copy the state into 512-bits into W[0..15] */ ++ for (i = 0; i < 16; i++) ++ W[i] = WPA_GET_BE32(buf + (4 * i)); ++ ++ /* fill W[16..63] */ ++ for (i = 16; i < 64; i++) { ++ W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) + ++ W[i - 16]; ++ } ++ ++ /* Compress */ ++#define RND(a,b,c,d,e,f,g,h,i) \ ++ t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \ ++ t1 = Sigma0(a) + Maj(a, b, c); \ ++ d += t0; \ ++ h = t0 + t1; ++ ++ for (i = 0; i < 64; ++i) { ++ RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i); ++ t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; ++ S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; ++ } ++ ++ /* feedback */ ++ for (i = 0; i < 8; i++) { ++ md->state[i] = md->state[i] + S[i]; ++ } ++ return 0; ++} ++ ++/* Initialize the hash state */ ++static void sha256_init(struct sha256_state *md) ++{ ++ md->curlen = 0; ++ md->length = 0; ++ md->state[0] = 0x6A09E667UL; ++ md->state[1] = 0xBB67AE85UL; ++ md->state[2] = 0x3C6EF372UL; ++ md->state[3] = 0xA54FF53AUL; ++ md->state[4] = 0x510E527FUL; ++ md->state[5] = 0x9B05688CUL; ++ md->state[6] = 0x1F83D9ABUL; ++ md->state[7] = 0x5BE0CD19UL; ++} ++ ++/** ++ Process a block of memory though the hash ++ @param md The hash state ++ @param in The data to hash ++ @param inlen The length of the data (octets) ++ @return CRYPT_OK if successful ++*/ ++static int sha256_process(struct sha256_state *md, unsigned char *in, ++ unsigned long inlen) ++{ ++ unsigned long n; ++#define block_size 64 ++ ++ if (md->curlen > sizeof(md->buf)) ++ return -1; ++ ++ while (inlen > 0) { ++ if (md->curlen == 0 && inlen >= block_size) { ++ if (sha256_compress(md, (unsigned char *) in) < 0) ++ return -1; ++ md->length += block_size * 8; ++ in += block_size; ++ inlen -= block_size; ++ } else { ++ n = MIN(inlen, (block_size - md->curlen)); ++ _rtw_memcpy(md->buf + md->curlen, in, n); ++ md->curlen += n; ++ in += n; ++ inlen -= n; ++ if (md->curlen == block_size) { ++ if (sha256_compress(md, md->buf) < 0) ++ return -1; ++ md->length += 8 * block_size; ++ md->curlen = 0; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ Terminate the hash to get the digest ++ @param md The hash state ++ @param out [out] The destination of the hash (32 bytes) ++ @return CRYPT_OK if successful ++*/ ++static int sha256_done(struct sha256_state *md, unsigned char *out) ++{ ++ int i; ++ ++ if (md->curlen >= sizeof(md->buf)) ++ return -1; ++ ++ /* increase the length of the message */ ++ md->length += md->curlen * 8; ++ ++ /* append the '1' bit */ ++ md->buf[md->curlen++] = (unsigned char) 0x80; ++ ++ /* if the length is currently above 56 bytes we append zeros ++ * then compress. Then we can fall back to padding zeros and length ++ * encoding like normal. ++ */ ++ if (md->curlen > 56) { ++ while (md->curlen < 64) { ++ md->buf[md->curlen++] = (unsigned char) 0; ++ } ++ sha256_compress(md, md->buf); ++ md->curlen = 0; ++ } ++ ++ /* pad upto 56 bytes of zeroes */ ++ while (md->curlen < 56) { ++ md->buf[md->curlen++] = (unsigned char) 0; ++ } ++ ++ /* store length */ ++ WPA_PUT_BE64(md->buf + 56, md->length); ++ sha256_compress(md, md->buf); ++ ++ /* copy output */ ++ for (i = 0; i < 8; i++) ++ WPA_PUT_BE32(out + (4 * i), md->state[i]); ++ ++ return 0; ++} ++ ++/** ++ * sha256_vector - SHA256 hash for data vector ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for the hash ++ * Returns: 0 on success, -1 of failure ++ */ ++static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len, ++ u8 *mac) ++{ ++ struct sha256_state ctx; ++ size_t i; ++ ++ sha256_init(&ctx); ++ for (i = 0; i < num_elem; i++) ++ if (sha256_process(&ctx, addr[i], len[i])) ++ return -1; ++ if (sha256_done(&ctx, mac)) ++ return -1; ++ return 0; ++} ++ ++static u8 os_strlen(const char *s) ++{ ++ const char *p = s; ++ while (*p) ++ p++; ++ return p - s; ++} ++ ++static int os_memcmp(void *s1, void *s2, u8 n) ++{ ++ unsigned char *p1 = s1, *p2 = s2; ++ ++ if (n == 0) ++ return 0; ++ ++ while (*p1 == *p2) { ++ p1++; ++ p2++; ++ n--; ++ if (n == 0) ++ return 0; ++ } ++ ++ return *p1 - *p2; ++} ++ ++/** ++ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) ++ * @key: Key for HMAC operations ++ * @key_len: Length of the key in bytes ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for the hash (32 bytes) ++ */ ++static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, ++ u8 *addr[], size_t *len, u8 *mac) ++{ ++ unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */ ++ unsigned char tk[32]; ++ u8 *_addr[6]; ++ size_t _len[6], i; ++ ++ if (num_elem > 5) { ++ /* ++ * Fixed limit on the number of fragments to avoid having to ++ * allocate memory (which could fail). ++ */ ++ return; ++ } ++ ++ /* if key is longer than 64 bytes reset it to key = SHA256(key) */ ++ if (key_len > 64) { ++ sha256_vector(1, &key, &key_len, tk); ++ key = tk; ++ key_len = 32; ++ } ++ ++ /* the HMAC_SHA256 transform looks like: ++ * ++ * SHA256(K XOR opad, SHA256(K XOR ipad, text)) ++ * ++ * where K is an n byte key ++ * ipad is the byte 0x36 repeated 64 times ++ * opad is the byte 0x5c repeated 64 times ++ * and text is the data being protected */ ++ ++ /* start out by storing key in ipad */ ++ _rtw_memset(k_pad, 0, sizeof(k_pad)); ++ _rtw_memcpy(k_pad, key, key_len); ++ /* XOR key with ipad values */ ++ for (i = 0; i < 64; i++) ++ k_pad[i] ^= 0x36; ++ ++ /* perform inner SHA256 */ ++ _addr[0] = k_pad; ++ _len[0] = 64; ++ for (i = 0; i < num_elem; i++) { ++ _addr[i + 1] = addr[i]; ++ _len[i + 1] = len[i]; ++ } ++ sha256_vector(1 + num_elem, _addr, _len, mac); ++ ++ _rtw_memset(k_pad, 0, sizeof(k_pad)); ++ _rtw_memcpy(k_pad, key, key_len); ++ /* XOR key with opad values */ ++ for (i = 0; i < 64; i++) ++ k_pad[i] ^= 0x5c; ++ ++ /* perform outer SHA256 */ ++ _addr[0] = k_pad; ++ _len[0] = 64; ++ _addr[1] = mac; ++ _len[1] = 32; ++ sha256_vector(2, _addr, _len, mac); ++} ++#endif //PLATFORM_FREEBSD ++/** ++ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) ++ * @key: Key for PRF ++ * @key_len: Length of the key in bytes ++ * @label: A unique label for each purpose of the PRF ++ * @data: Extra data to bind into the key ++ * @data_len: Length of the data ++ * @buf: Buffer for the generated pseudo-random key ++ * @buf_len: Number of bytes of key to generate ++ * ++ * This function is used to derive new, cryptographically separate keys from a ++ * given key. ++ */ ++#ifndef PLATFORM_FREEBSD //Baron ++static void sha256_prf(u8 *key, size_t key_len, char *label, ++ u8 *data, size_t data_len, u8 *buf, size_t buf_len) ++{ ++ u16 counter = 1; ++ size_t pos, plen; ++ u8 hash[SHA256_MAC_LEN]; ++ u8 *addr[4]; ++ size_t len[4]; ++ u8 counter_le[2], length_le[2]; ++ ++ addr[0] = counter_le; ++ len[0] = 2; ++ addr[1] = (u8 *) label; ++ len[1] = os_strlen(label); ++ addr[2] = data; ++ len[2] = data_len; ++ addr[3] = length_le; ++ len[3] = sizeof(length_le); ++ ++ WPA_PUT_LE16(length_le, buf_len * 8); ++ pos = 0; ++ while (pos < buf_len) { ++ plen = buf_len - pos; ++ WPA_PUT_LE16(counter_le, counter); ++ if (plen >= SHA256_MAC_LEN) { ++ hmac_sha256_vector(key, key_len, 4, addr, len, ++ &buf[pos]); ++ pos += SHA256_MAC_LEN; ++ } else { ++ hmac_sha256_vector(key, key_len, 4, addr, len, hash); ++ _rtw_memcpy(&buf[pos], hash, plen); ++ break; ++ } ++ counter++; ++ } ++} ++#endif //PLATFORM_FREEBSD Baron ++ ++/* AES tables*/ ++const u32 Te0[256] = { ++ 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, ++ 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, ++ 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, ++ 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU, ++ 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, ++ 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, ++ 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, ++ 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU, ++ 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU, ++ 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, ++ 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, ++ 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU, ++ 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU, ++ 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U, ++ 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, ++ 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, ++ 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, ++ 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU, ++ 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU, ++ 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, ++ 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, ++ 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, ++ 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU, ++ 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU, ++ 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, ++ 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, ++ 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, ++ 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U, ++ 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU, ++ 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, ++ 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, ++ 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, ++ 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU, ++ 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U, ++ 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, ++ 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, ++ 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, ++ 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U, ++ 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU, ++ 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, ++ 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, ++ 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, ++ 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U, ++ 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU, ++ 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, ++ 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, ++ 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, ++ 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U, ++ 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U, ++ 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, ++ 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, ++ 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, ++ 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU, ++ 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U, ++ 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, ++ 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, ++ 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U, ++ 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U, ++ 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U, ++ 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, ++ 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, ++ 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, ++ 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U, ++ 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU, ++}; ++const u32 Td0[256] = { ++ 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, ++ 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, ++ 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, ++ 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU, ++ 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, ++ 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, ++ 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU, ++ 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U, ++ 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU, ++ 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, ++ 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, ++ 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, ++ 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U, ++ 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU, ++ 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, ++ 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, ++ 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, ++ 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU, ++ 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U, ++ 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, ++ 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, ++ 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU, ++ 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U, ++ 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU, ++ 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, ++ 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, ++ 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U, ++ 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU, ++ 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU, ++ 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, ++ 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, ++ 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, ++ 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU, ++ 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U, ++ 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, ++ 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, ++ 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, ++ 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U, ++ 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U, ++ 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, ++ 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, ++ 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, ++ 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U, ++ 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U, ++ 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, ++ 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, ++ 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, ++ 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U, ++ 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U, ++ 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, ++ 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, ++ 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, ++ 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU, ++ 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU, ++ 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, ++ 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, ++ 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, ++ 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU, ++ 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU, ++ 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, ++ 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, ++ 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U, ++ 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U, ++ 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U, ++}; ++const u8 Td4s[256] = { ++ 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, ++ 0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, ++ 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U, ++ 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, ++ 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, ++ 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, ++ 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, ++ 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, ++ 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, ++ 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, ++ 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, ++ 0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, ++ 0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, ++ 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U, ++ 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, ++ 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, ++ 0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, ++ 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U, ++ 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, ++ 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, ++ 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, ++ 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, ++ 0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, ++ 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, ++ 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, ++ 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, ++ 0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, ++ 0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU, ++ 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U, ++ 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, ++ 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, ++ 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, ++}; ++const u8 rcons[] = { ++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36 ++ /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ ++}; ++ ++/** ++ * Expand the cipher key into the encryption key schedule. ++ * ++ * @return the number of rounds for the given cipher key size. ++ */ ++#ifndef PLATFORM_FREEBSD //Baron ++static void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[]) ++{ ++ int i; ++ u32 temp; ++ ++ rk[0] = GETU32(cipherKey ); ++ rk[1] = GETU32(cipherKey + 4); ++ rk[2] = GETU32(cipherKey + 8); ++ rk[3] = GETU32(cipherKey + 12); ++ for (i = 0; i < 10; i++) { ++ temp = rk[3]; ++ rk[4] = rk[0] ^ ++ TE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^ ++ RCON(i); ++ rk[5] = rk[1] ^ rk[4]; ++ rk[6] = rk[2] ^ rk[5]; ++ rk[7] = rk[3] ^ rk[6]; ++ rk += 4; ++ } ++} ++ ++static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16]) ++{ ++ u32 s0, s1, s2, s3, t0, t1, t2, t3; ++ int Nr = 10; ++#ifndef FULL_UNROLL ++ int r; ++#endif /* ?FULL_UNROLL */ ++ ++ /* ++ * map byte array block to cipher state ++ * and add initial round key: ++ */ ++ s0 = GETU32(pt ) ^ rk[0]; ++ s1 = GETU32(pt + 4) ^ rk[1]; ++ s2 = GETU32(pt + 8) ^ rk[2]; ++ s3 = GETU32(pt + 12) ^ rk[3]; ++ ++#define ROUND(i,d,s) \ ++d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \ ++d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \ ++d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \ ++d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3] ++ ++#ifdef FULL_UNROLL ++ ++ ROUND(1,t,s); ++ ROUND(2,s,t); ++ ROUND(3,t,s); ++ ROUND(4,s,t); ++ ROUND(5,t,s); ++ ROUND(6,s,t); ++ ROUND(7,t,s); ++ ROUND(8,s,t); ++ ROUND(9,t,s); ++ ++ rk += Nr << 2; ++ ++#else /* !FULL_UNROLL */ ++ ++ /* Nr - 1 full rounds: */ ++ r = Nr >> 1; ++ for (;;) { ++ ROUND(1,t,s); ++ rk += 8; ++ if (--r == 0) ++ break; ++ ROUND(0,s,t); ++ } ++ ++#endif /* ?FULL_UNROLL */ ++ ++#undef ROUND ++ ++ /* ++ * apply last round and ++ * map cipher state to byte array block: ++ */ ++ s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0]; ++ PUTU32(ct , s0); ++ s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1]; ++ PUTU32(ct + 4, s1); ++ s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2]; ++ PUTU32(ct + 8, s2); ++ s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3]; ++ PUTU32(ct + 12, s3); ++} ++ ++static void * aes_encrypt_init(u8 *key, size_t len) ++{ ++ u32 *rk; ++ if (len != 16) ++ return NULL; ++ rk = (u32*)rtw_malloc(AES_PRIV_SIZE); ++ if (rk == NULL) ++ return NULL; ++ rijndaelKeySetupEnc(rk, key); ++ return rk; ++} ++ ++static void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt) ++{ ++ rijndaelEncrypt(ctx, plain, crypt); ++} ++ ++ ++static void gf_mulx(u8 *pad) ++{ ++ int i, carry; ++ ++ carry = pad[0] & 0x80; ++ for (i = 0; i < AES_BLOCK_SIZE - 1; i++) ++ pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7); ++ pad[AES_BLOCK_SIZE - 1] <<= 1; ++ if (carry) ++ pad[AES_BLOCK_SIZE - 1] ^= 0x87; ++} ++ ++static void aes_encrypt_deinit(void *ctx) ++{ ++ _rtw_memset(ctx, 0, AES_PRIV_SIZE); ++ rtw_mfree(ctx, AES_PRIV_SIZE); ++} ++ ++ ++/** ++ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128 ++ * @key: 128-bit key for the hash operation ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) ++ * Returns: 0 on success, -1 on failure ++ * ++ * This is a mode for using block cipher (AES in this case) for authentication. ++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication ++ * (SP) 800-38B. ++ */ ++static int omac1_aes_128_vector(u8 *key, size_t num_elem, ++ u8 *addr[], size_t *len, u8 *mac) ++{ ++ void *ctx; ++ u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE]; ++ u8 *pos, *end; ++ size_t i, e, left, total_len; ++ ++ ctx = aes_encrypt_init(key, 16); ++ if (ctx == NULL) ++ return -1; ++ _rtw_memset(cbc, 0, AES_BLOCK_SIZE); ++ ++ total_len = 0; ++ for (e = 0; e < num_elem; e++) ++ total_len += len[e]; ++ left = total_len; ++ ++ e = 0; ++ pos = addr[0]; ++ end = pos + len[0]; ++ ++ while (left >= AES_BLOCK_SIZE) { ++ for (i = 0; i < AES_BLOCK_SIZE; i++) { ++ cbc[i] ^= *pos++; ++ if (pos >= end) { ++ e++; ++ pos = addr[e]; ++ end = pos + len[e]; ++ } ++ } ++ if (left > AES_BLOCK_SIZE) ++ aes_128_encrypt(ctx, cbc, cbc); ++ left -= AES_BLOCK_SIZE; ++ } ++ ++ _rtw_memset(pad, 0, AES_BLOCK_SIZE); ++ aes_128_encrypt(ctx, pad, pad); ++ gf_mulx(pad); ++ ++ if (left || total_len == 0) { ++ for (i = 0; i < left; i++) { ++ cbc[i] ^= *pos++; ++ if (pos >= end) { ++ e++; ++ pos = addr[e]; ++ end = pos + len[e]; ++ } ++ } ++ cbc[left] ^= 0x80; ++ gf_mulx(pad); ++ } ++ ++ for (i = 0; i < AES_BLOCK_SIZE; i++) ++ pad[i] ^= cbc[i]; ++ aes_128_encrypt(ctx, pad, mac); ++ aes_encrypt_deinit(ctx); ++ return 0; ++} ++ ++ ++/** ++ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC) ++ * @key: 128-bit key for the hash operation ++ * @data: Data buffer for which a MAC is determined ++ * @data_len: Length of data buffer in bytes ++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) ++ * Returns: 0 on success, -1 on failure ++ * ++ * This is a mode for using block cipher (AES in this case) for authentication. ++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication ++ * (SP) 800-38B. ++ */ //modify for CONFIG_IEEE80211W ++int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac) ++{ ++ return omac1_aes_128_vector(key, 1, &data, &data_len, mac); ++} ++#endif //PLATFORM_FREEBSD Baron ++ ++#ifdef CONFIG_TDLS ++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 *SNonce = psta->SNonce; ++ u8 *ANonce = psta->ANonce; ++ ++ u8 key_input[SHA256_MAC_LEN]; ++ u8 *nonce[2]; ++ size_t len[2]; ++ u8 data[3 * ETH_ALEN]; ++ ++ /* IEEE Std 802.11z-2010 8.5.9.1: ++ * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce)) ++ */ ++ len[0] = 32; ++ len[1] = 32; ++ if (os_memcmp(SNonce, ANonce, 32) < 0) { ++ nonce[0] = SNonce; ++ nonce[1] = ANonce; ++ } else { ++ nonce[0] = ANonce; ++ nonce[1] = SNonce; ++ } ++ ++ sha256_vector(2, nonce, len, key_input); ++ ++ /* ++ * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, "TDLS PMK", ++ * min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY) ++ * TODO: is N_KEY really included in KDF Context and if so, in which ++ * presentation format (little endian 16-bit?) is it used? It gets ++ * added by the KDF anyway.. ++ */ ++ ++ if (os_memcmp(myid(&(padapter->eeprompriv)), psta->hwaddr, ETH_ALEN) < 0) { ++ _rtw_memcpy(data, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN); ++ } else { ++ _rtw_memcpy(data, psta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(data + ETH_ALEN, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ } ++ _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN); ++ ++ sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk)); ++ ++ ++} ++ ++/** ++ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC ++ * @kck: TPK-KCK ++ * @lnkid: Pointer to the beginning of Link Identifier IE ++ * @rsnie: Pointer to the beginning of RSN IE used for handshake ++ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake ++ * @ftie: Pointer to the beginning of FT IE ++ * @mic: Pointer for writing MIC ++ * ++ * Calculate MIC for TDLS frame. ++ */ ++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, ++ u8 *mic) ++{ ++ u8 *buf, *pos; ++ struct wpa_tdls_ftie *_ftie; ++ struct wpa_tdls_lnkid *_lnkid; ++ int ret; ++ int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] + ++ 2 + timeoutie[1] + 2 + ftie[1]; ++ buf = rtw_zmalloc(len); ++ if (!buf) { ++ DBG_871X("TDLS: No memory for MIC calculation\n"); ++ return -1; ++ } ++ ++ pos = buf; ++ _lnkid = (struct wpa_tdls_lnkid *) lnkid; ++ /* 1) TDLS initiator STA MAC address */ ++ _rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 2) TDLS responder STA MAC address */ ++ _rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 3) Transaction Sequence number */ ++ *pos++ = trans_seq; ++ /* 4) Link Identifier IE */ ++ _rtw_memcpy(pos, lnkid, 2 + lnkid[1]); ++ pos += 2 + lnkid[1]; ++ /* 5) RSN IE */ ++ _rtw_memcpy(pos, rsnie, 2 + rsnie[1]); ++ pos += 2 + rsnie[1]; ++ /* 6) Timeout Interval IE */ ++ _rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]); ++ pos += 2 + timeoutie[1]; ++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */ ++ _rtw_memcpy(pos, ftie, 2 + ftie[1]); ++ _ftie = (struct wpa_tdls_ftie *) pos; ++ _rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN); ++ pos += 2 + ftie[1]; ++ ++ ret = omac1_aes_128(kck, buf, pos - buf, mic); ++ rtw_mfree(buf, len); ++ return ret; ++ ++} ++ ++int tdls_verify_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie) ++{ ++ u8 *buf, *pos; ++ int len; ++ u8 mic[16]; ++ int ret; ++ u8 *rx_ftie, *tmp_ftie; ++ ++ if (lnkid == NULL || rsnie == NULL || ++ timeoutie == NULL || ftie == NULL){ ++ return 0; ++ } ++ ++ len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie+1) + 2 + *(timeoutie+1) + 2 + *(ftie+1); ++ ++ buf = rtw_zmalloc(len); ++ if (buf == NULL) ++ return 0; ++ ++ pos = buf; ++ /* 1) TDLS initiator STA MAC address */ ++ _rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 2) TDLS responder STA MAC address */ ++ _rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 3) Transaction Sequence number */ ++ *pos++ = trans_seq; ++ /* 4) Link Identifier IE */ ++ _rtw_memcpy(pos, lnkid, 2 + 18); ++ pos += 2 + 18; ++ /* 5) RSN IE */ ++ _rtw_memcpy(pos, rsnie, 2 + *(rsnie+1)); ++ pos += 2 + *(rsnie+1); ++ /* 6) Timeout Interval IE */ ++ _rtw_memcpy(pos, timeoutie, 2 + *(timeoutie+1)); ++ pos += 2 + *(timeoutie+1); ++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */ ++ _rtw_memcpy(pos, ftie, 2 + *(ftie+1)); ++ pos += 2; ++ tmp_ftie = (u8 *) (pos+2); ++ _rtw_memset(tmp_ftie, 0, 16); ++ pos += *(ftie+1); ++ ++ ret = omac1_aes_128(kck, buf, pos - buf, mic); ++ rtw_mfree(buf, len); ++ if (ret) ++ return 0; ++ rx_ftie = ftie+4; ++ ++ if (os_memcmp(mic, rx_ftie, 16) == 0) { ++ //Valid MIC ++ return 1; ++ } ++ ++ //Invalid MIC ++ DBG_871X( "[%s] Invalid MIC\n", __FUNCTION__); ++ return 0; ++ ++} ++#endif //CONFIG_TDLS ++ ++#ifdef PLATFORM_WINDOWS ++void rtw_use_tkipkey_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ) ++#endif ++#ifdef PLATFORM_LINUX ++void rtw_use_tkipkey_handler(void *FunctionContext) ++#endif ++#ifdef PLATFORM_FREEBSD ++void rtw_use_tkipkey_handler(void *FunctionContext) ++#endif ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler ^^^\n")); ++ ++/* ++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %d)(padapter->bSurpriseRemoved %d)^^^\n",padapter->bDriverStopped,padapter->bSurpriseRemoved)); ++ ++ return; ++ } ++ */ ++ ++ padapter->securitypriv.busetkipkey=_TRUE; ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n",padapter->securitypriv.busetkipkey)); ++ ++_func_exit_; ++ ++} ++ ++/* Restore HW wep key setting according to key_mask */ ++void rtw_sec_restore_wep_key(_adapter *adapter) ++{ ++ struct security_priv* securitypriv=&(adapter->securitypriv); ++ sint keyid; ++ ++ if((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) ||(_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) { ++ for(keyid=0;keyid<4;keyid++){ ++ if(securitypriv->key_mask & BIT(keyid)){ ++ if(keyid == securitypriv->dot11PrivacyKeyIndex) ++ rtw_set_key(adapter,securitypriv, keyid, 1, _TRUE); ++ else ++ rtw_set_key(adapter,securitypriv, keyid, 0, _TRUE); ++ } ++ } ++ } ++} ++ ++u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller) ++{ ++ struct security_priv* securitypriv=&(adapter->securitypriv); ++ u8 status = _SUCCESS; ++ ++ if (securitypriv->btkip_countermeasure == _TRUE) { ++ u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time); ++ if (passing_ms > 60*1000) { ++ DBG_871X_LEVEL(_drv_always_, "%s("ADPT_FMT") countermeasure time:%ds > 60s \n", ++ caller, ADPT_ARG(adapter), passing_ms/1000); ++ securitypriv->btkip_countermeasure = _FALSE; ++ securitypriv->btkip_countermeasure_time = 0; ++ } else { ++ DBG_871X_LEVEL(_drv_always_, "%s("ADPT_FMT") countermeasure time:%ds < 60s \n", ++ caller, ADPT_ARG(adapter), passing_ms/1000); ++ status = _FAIL; ++ } ++ } ++ ++ return status; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sreset.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sreset.c +new file mode 100644 +index 00000000..bc34827b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sreset.c +@@ -0,0 +1,356 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++ ++void sreset_init_value(_adapter *padapter) ++{ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ _rtw_mutex_init(&psrtpriv->silentreset_mutex); ++ psrtpriv->silent_reset_inprogress = _FALSE; ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ psrtpriv->last_tx_time =0; ++ psrtpriv->last_tx_complete_time =0; ++#endif ++} ++void sreset_reset_value(_adapter *padapter) ++{ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ //psrtpriv->silent_reset_inprogress = _FALSE; ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ psrtpriv->last_tx_time =0; ++ psrtpriv->last_tx_complete_time =0; ++#endif ++} ++ ++u8 sreset_get_wifi_status(_adapter *padapter) ++{ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ u8 status = WIFI_STATUS_SUCCESS; ++ u32 val32 = 0; ++ _irqL irqL; ++ if(psrtpriv->silent_reset_inprogress == _TRUE) ++ { ++ return status; ++ } ++ val32 =rtw_read32(padapter,REG_TXDMA_STATUS); ++ if(val32==0xeaeaeaea){ ++ psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST; ++ } ++ else if(val32!=0){ ++ DBG_8192C("txdmastatu(%x)\n",val32); ++ psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR; ++ } ++ ++ if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status) ++ { ++ DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status); ++ status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL))); ++ } ++ DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status); ++ ++ //status restore ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ ++ return status; ++#else ++ return WIFI_STATUS_SUCCESS; ++#endif ++} ++ ++void sreset_set_wifi_error_status(_adapter *padapter, u32 status) ++{ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = status; ++#endif ++} ++ ++void sreset_set_trigger_point(_adapter *padapter, s32 tgp) ++{ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.dbg_trigger_point = tgp; ++#endif ++} ++ ++bool sreset_inprogress(_adapter *padapter) ++{ ++#if defined(DBG_CONFIG_ERROR_RESET) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ return pHalData->srestpriv.silent_reset_inprogress; ++#else ++ return _FALSE; ++#endif ++} ++ ++void sreset_restore_security_station(_adapter *padapter) ++{ ++ u8 EntryId = 0; ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; ++ ++ { ++ u8 val8; ++ ++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) { ++ val8 = 0xcc; ++ #ifdef CONFIG_WAPI_SUPPORT ++ } else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) { ++ //Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. ++ val8 = 0x4c; ++ #endif ++ } else { ++ val8 = 0xcf; ++ } ++ rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ } ++ ++ #if 0 ++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) || ++ ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ )) ++ { ++ ++ for(EntryId=0; EntryId<4; EntryId++) ++ { ++ if(EntryId == psecuritypriv->dot11PrivacyKeyIndex) ++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE); ++ else ++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE); ++ } ++ ++ } ++ else ++ #endif ++ if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ } ++ else ++ { ++ //pairwise key ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE,_FALSE); ++ //group key ++ rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE); ++ } ++ } ++} ++ ++void sreset_restore_network_station(_adapter *padapter) ++{ ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ #if 0 ++ { ++ //======================================================= ++ // reset related register of Beacon control ++ ++ //set MSR to nolink ++ Set_MSR(padapter, _HW_STATE_NOLINK_); ++ // reject all data frame ++ rtw_write16(padapter, REG_RXFLTMAP2,0x00); ++ //reset TSF ++ rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); ++ ++ // disable update TSF ++ SetBcnCtrlReg(padapter, BIT(4), 0); ++ ++ //======================================================= ++ } ++ #endif ++ ++ rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE); ++ ++ { ++ u8 threshold; ++ #ifdef CONFIG_USB_HCI ++ // TH=1 => means that invalidate usb rx aggregation ++ // TH=0 => means that validate usb rx aggregation, use init value. ++ if(mlmepriv->htpriv.ht_option) { ++ if(padapter->registrypriv.wifi_spec==1) ++ threshold = 1; ++ else ++ threshold = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } else { ++ threshold = 1; ++ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } ++ #endif ++ } ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ //disable dynamic functions, such as high power, DIG ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); ++ ++ { ++ u8 join_type = 0; ++ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ } ++ ++ Set_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ mlmeext_joinbss_event_callback(padapter, 1); ++ //restore Sequence No. ++ rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn); ++ ++ sreset_restore_security_station(padapter); ++} ++ ++ ++void sreset_restore_network_status(_adapter *padapter) ++{ ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ sreset_restore_network_station(padapter); ++ } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ rtw_ap_restore_network(padapter); ++ } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } else { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } ++} ++ ++void sreset_stop_adapter(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ if (padapter == NULL) ++ return; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++ if (!rtw_netif_queue_stopped(padapter->pnetdev)) ++ rtw_netif_stop_queue(padapter->pnetdev); ++ ++ rtw_cancel_all_timer(padapter); ++ ++ /* TODO: OS and HCI independent */ ++ #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) ++ tasklet_kill(&pxmitpriv->xmit_tasklet); ++ #endif ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_scan_abort(padapter); ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ { ++ rtw_set_roaming(padapter, 0); ++ _rtw_join_timeout_handler(padapter); ++ } ++ ++} ++ ++void sreset_start_adapter(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ if (padapter == NULL) ++ return; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) { ++ sreset_restore_network_status(padapter); ++ } ++ ++ /* TODO: OS and HCI independent */ ++ #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ #endif ++ ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ ++ if (rtw_netif_queue_stopped(padapter->pnetdev)) ++ rtw_netif_wake_queue(padapter->pnetdev); ++ ++} ++ ++void sreset_reset(_adapter *padapter) ++{ ++#ifdef DBG_CONFIG_ERROR_RESET ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ u32 start = rtw_get_current_time(); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ++ psrtpriv->silent_reset_inprogress = _TRUE; ++ pwrpriv->change_rfpwrstate = rf_off; ++ ++ sreset_stop_adapter(padapter); ++ #ifdef CONFIG_CONCURRENT_MODE ++ sreset_stop_adapter(padapter->pbuddy_adapter); ++ #endif ++ ++ #ifdef CONFIG_IPS ++ _ips_enter(padapter); ++ _ips_leave(padapter); ++ #endif ++ ++ sreset_start_adapter(padapter); ++ #ifdef CONFIG_CONCURRENT_MODE ++ sreset_start_adapter(padapter->pbuddy_adapter); ++ #endif ++ ++ psrtpriv->silent_reset_inprogress = _FALSE; ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); ++#endif ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sta_mgt.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sta_mgt.c +new file mode 100644 +index 00000000..084b5002 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_sta_mgt.c +@@ -0,0 +1,870 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_STA_MGT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++ ++void _rtw_init_stainfo(struct sta_info *psta); ++void _rtw_init_stainfo(struct sta_info *psta) ++{ ++ ++_func_enter_; ++ ++ _rtw_memset((u8 *)psta, 0, sizeof (struct sta_info)); ++ ++ _rtw_spinlock_init(&psta->lock); ++ _rtw_init_listhead(&psta->list); ++ _rtw_init_listhead(&psta->hash_list); ++ //_rtw_init_listhead(&psta->asoc_list); ++ //_rtw_init_listhead(&psta->sleep_list); ++ //_rtw_init_listhead(&psta->wakeup_list); ++ ++ _rtw_init_queue(&psta->sleep_q); ++ psta->sleepq_len = 0; ++ ++ _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); ++ _rtw_init_sta_recv_priv(&psta->sta_recvpriv); ++ ++#ifdef CONFIG_AP_MODE ++ ++ _rtw_init_listhead(&psta->asoc_list); ++ ++ _rtw_init_listhead(&psta->auth_list); ++ ++ psta->expire_to = 0; ++ ++ psta->flags = 0; ++ ++ psta->capability = 0; ++ ++ psta->bpairwise_key_installed = _FALSE; ++ ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ psta->nonerp_set = 0; ++ psta->no_short_slot_time_set = 0; ++ psta->no_short_preamble_set = 0; ++ psta->no_ht_gf_set = 0; ++ psta->no_ht_set = 0; ++ psta->ht_20mhz_set = 0; ++#endif ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++ psta->keep_alive_trycnt = 0; ++ ++#endif // CONFIG_AP_MODE ++ ++#ifdef DBG_TRX_STA_PKTS ++ psta->tx_be_cnt = 0; ++ psta->tx_bk_cnt = 0; ++ psta->tx_vi_cnt = 0; ++ psta->tx_vo_cnt = 0; ++ ++ psta->rx_be_cnt = 0; ++ psta->rx_bk_cnt = 0; ++ psta->rx_vi_cnt = 0; ++ psta->rx_vo_cnt = 0; ++#endif ++_func_exit_; ++ ++} ++ ++u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) ++{ ++ struct sta_info *psta; ++ s32 i; ++ ++_func_enter_; ++ ++ pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4); ++ ++ if(!pstapriv->pallocated_stainfo_buf) ++ return _FAIL; ++ ++ pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - ++ ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3); ++ ++ _rtw_init_queue(&pstapriv->free_sta_queue); ++ ++ _rtw_spinlock_init(&pstapriv->sta_hash_lock); ++ ++ //_rtw_init_queue(&pstapriv->asoc_q); ++ pstapriv->asoc_sta_count = 0; ++ _rtw_init_queue(&pstapriv->sleep_q); ++ _rtw_init_queue(&pstapriv->wakeup_q); ++ ++ psta = (struct sta_info *)(pstapriv->pstainfo_buf); ++ ++ ++ for(i = 0; i < NUM_STA; i++) ++ { ++ _rtw_init_stainfo(psta); ++ ++ _rtw_init_listhead(&(pstapriv->sta_hash[i])); ++ ++ rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue)); ++ ++ psta++; ++ } ++ ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++ pstapriv->sta_dz_bitmap = 0; ++ pstapriv->tim_bitmap = 0; ++ ++ _rtw_init_listhead(&pstapriv->asoc_list); ++ _rtw_init_listhead(&pstapriv->auth_list); ++ _rtw_spinlock_init(&pstapriv->asoc_list_lock); ++ _rtw_spinlock_init(&pstapriv->auth_list_lock); ++ pstapriv->asoc_list_cnt = 0; ++ pstapriv->auth_list_cnt = 0; ++ ++ pstapriv->auth_to = 3; // 3*2 = 6 sec ++ pstapriv->assoc_to = 3; ++ //pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic. ++ //pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic. ++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++ pstapriv->expire_to = 3; // 3*2 = 6 sec ++#else ++ pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic. ++#endif ++#ifdef CONFIG_ATMEL_RC_PATCH ++ _rtw_memset( pstapriv->atmel_rc_pattern, 0, ETH_ALEN); ++#endif ++ pstapriv->max_num_sta = NUM_STA; ++ ++#endif ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta) ++{ ++ int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info); ++ ++ if (!stainfo_offset_valid(offset)) ++ DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset); ++ ++ return offset; ++} ++ ++inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset) ++{ ++ if (!stainfo_offset_valid(offset)) ++ DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset); ++ ++ return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info)); ++} ++ ++void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv); ++void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) ++{ ++_func_enter_; ++ ++ _rtw_spinlock_free(&psta_xmitpriv->lock); ++ ++ _rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); ++_func_exit_; ++} ++ ++static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) ++{ ++_func_enter_; ++ ++ _rtw_spinlock_free(&psta_recvpriv->lock); ++ ++ _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock)); ++ ++_func_exit_; ++ ++} ++ ++void rtw_mfree_stainfo(struct sta_info *psta); ++void rtw_mfree_stainfo(struct sta_info *psta) ++{ ++_func_enter_; ++ ++ if(&psta->lock != NULL) ++ _rtw_spinlock_free(&psta->lock); ++ ++ _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); ++ _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv); ++ ++_func_exit_; ++} ++ ++ ++// this function is used to free the memory of lock || sema for all stainfos ++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv ); ++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv ) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct sta_info *psta = NULL; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ phead = get_list_head(&pstapriv->free_sta_queue); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info ,list); ++ plist = get_next(plist); ++ ++ rtw_mfree_stainfo(psta); ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++_func_exit_; ++ ++} ++ ++void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv); ++void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv) ++{ ++#ifdef CONFIG_AP_MODE ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++#endif ++ ++ rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock ++ ++ _rtw_spinlock_free(&pstapriv->free_sta_queue.lock); ++ ++ _rtw_spinlock_free(&pstapriv->sta_hash_lock); ++ _rtw_spinlock_free(&pstapriv->wakeup_q.lock); ++ _rtw_spinlock_free(&pstapriv->sleep_q.lock); ++ ++#ifdef CONFIG_AP_MODE ++ _rtw_spinlock_free(&pstapriv->asoc_list_lock); ++ _rtw_spinlock_free(&pstapriv->auth_list_lock); ++ _rtw_spinlock_free(&pacl_list->acl_node_q.lock); ++#endif ++ ++} ++ ++u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sta_info *psta = NULL; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ int index; ++ ++_func_enter_; ++ if(pstapriv){ ++ ++ /* delete all reordering_ctrl_timer */ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ for(index = 0; index < NUM_STA; index++) ++ { ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ int i; ++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); ++ plist = get_next(plist); ++ ++ for(i=0; i < 16 ; i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ++ } ++ } ++ } ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ /*===============================*/ ++ ++ rtw_mfree_sta_priv_lock(pstapriv); ++ ++ if(pstapriv->pallocated_stainfo_buf) { ++ rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4); ++ } ++ } ++ ++_func_exit_; ++ return _SUCCESS; ++} ++ ++ ++//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) ++struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) ++{ ++ _irqL irqL, irqL2; ++ uint tmp_aid; ++ s32 index; ++ _list *phash_list; ++ struct sta_info *psta; ++ _queue *pfree_sta_queue; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ int i = 0; ++ u16 wRxSeqInitialValue = 0xffff; ++ ++_func_enter_; ++ ++ pfree_sta_queue = &pstapriv->free_sta_queue; ++ ++ //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++ if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) ++ { ++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ psta = NULL; ++ } ++ else ++ { ++ psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list); ++ ++ rtw_list_delete(&(psta->list)); ++ ++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ ++ tmp_aid = psta->aid; ++ ++ _rtw_init_stainfo(psta); ++ ++ psta->padapter = pstapriv->padapter; ++ ++ _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); ++ ++ index = wifi_mac_hash(hwaddr); ++ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index)); ++ ++ if(index >= NUM_STA){ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA")); ++ psta= NULL; ++ goto exit; ++ } ++ phash_list = &(pstapriv->sta_hash[index]); ++ ++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++ rtw_list_insert_tail(&psta->hash_list, phash_list); ++ ++ pstapriv->asoc_sta_count ++ ; ++ ++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++// Commented by Albert 2009/08/13 ++// For the SMC router, the sequence number of first packet of WPS handshake will be 0. ++// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. ++// So, we initialize the tid_rxseq variable as the 0xffff. ++ ++ for( i = 0; i < 16; i++ ) ++ { ++ _rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 ); ++ } ++ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n", ++ pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5])); ++ ++ init_addba_retry_timer(pstapriv->padapter, psta); ++ ++#ifdef CONFIG_TDLS ++ psta->padapter = pstapriv->padapter; ++ init_TPK_timer(pstapriv->padapter, psta); ++ init_ch_switch_timer(pstapriv->padapter, psta); ++ init_base_ch_timer(pstapriv->padapter, psta); ++ init_off_ch_timer(pstapriv->padapter, psta); ++ init_handshake_timer(pstapriv->padapter, psta); ++ init_tdls_alive_timer(pstapriv->padapter, psta); ++#endif //CONFIG_TDLS ++ ++ //for A-MPDU Rx reordering buffer control ++ for(i=0; i < 16 ; i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ ++ preorder_ctrl->padapter = pstapriv->padapter; ++ ++ preorder_ctrl->enable = _FALSE; ++ ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ //preorder_ctrl->wsize_b = (NR_RECVBUFF-2); ++ preorder_ctrl->wsize_b = 64;//64; ++ ++ _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue); ++ ++ rtw_init_recv_timer(preorder_ctrl); ++ } ++ ++ ++ //init for DM ++ psta->rssi_stat.UndecoratedSmoothedPWDB = (-1); ++ psta->rssi_stat.UndecoratedSmoothedCCK = (-1); ++#ifdef CONFIG_ATMEL_RC_PATCH ++ psta->flag_atmel_rc = 0; ++#endif ++ /* init for the sequence number of received management frame */ ++ psta->RxMgmtFrameSeqNum = 0xffff; ++ } ++ ++exit: ++ ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++_func_exit_; ++ ++ return psta; ++ ++ ++} ++ ++ ++// using pstapriv->sta_hash_lock to protect ++u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) ++{ ++ int i; ++ _irqL irqL0; ++ _queue *pfree_sta_queue; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_xmit_priv *pstaxmitpriv; ++ struct xmit_priv *pxmitpriv= &padapter->xmitpriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct hw_xmit *phwxmit; ++ ++ ++_func_enter_; ++ ++ if (psta == NULL) ++ goto exit; ++ ++ ++ _enter_critical_bh(&psta->lock, &irqL0); ++ psta->state &= ~_FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL0); ++ ++ pfree_sta_queue = &pstapriv->free_sta_queue; ++ ++ ++ pstaxmitpriv = &psta->sta_xmitpriv; ++ ++ //rtw_list_delete(&psta->sleep_list); ++ ++ //rtw_list_delete(&psta->wakeup_list); ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); ++ psta->sleepq_len = 0; ++ ++ //vo ++ //_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); ++ phwxmit = pxmitpriv->hwxmits; ++ phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt; ++ pstaxmitpriv->vo_q.qcnt = 0; ++ //_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); ++ ++ //vi ++ //_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); ++ phwxmit = pxmitpriv->hwxmits+1; ++ phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt; ++ pstaxmitpriv->vi_q.qcnt = 0; ++ //_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); ++ ++ //be ++ //_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ phwxmit = pxmitpriv->hwxmits+2; ++ phwxmit->accnt -= pstaxmitpriv->be_q.qcnt; ++ pstaxmitpriv->be_q.qcnt = 0; ++ //_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); ++ ++ //bk ++ //_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); ++ phwxmit = pxmitpriv->hwxmits+3; ++ phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt; ++ pstaxmitpriv->bk_q.qcnt = 0; ++ //_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ rtw_list_delete(&psta->hash_list); ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5])); ++ pstapriv->asoc_sta_count --; ++ ++ ++ // re-init sta_info; 20061114 // will be init in alloc_stainfo ++ //_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); ++ //_rtw_init_sta_recv_priv(&psta->sta_recvpriv); ++ ++ _cancel_timer_ex(&psta->addba_retry_timer); ++ ++#ifdef CONFIG_TDLS ++ _cancel_timer_ex(&psta->TPK_timer); ++ _cancel_timer_ex(&psta->option_timer); ++ _cancel_timer_ex(&psta->base_ch_timer); ++ _cancel_timer_ex(&psta->off_ch_timer); ++ _cancel_timer_ex(&psta->alive_timer1); ++ _cancel_timer_ex(&psta->alive_timer2); ++#endif //CONFIG_TDLS ++ ++ //for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer ++ for(i=0; i < 16 ; i++) ++ { ++ _irqL irqL; ++ _list *phead, *plist; ++ union recv_frame *prframe; ++ _queue *ppending_recvframe_queue; ++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ ++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ++ ++ ++ ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL); ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++ while(!rtw_is_list_empty(phead)) ++ { ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ plist = get_next(plist); ++ ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ } ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL); ++ ++ } ++ ++ if (!(psta->state & WIFI_AP_STATE)) ++ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); ++ ++#ifdef CONFIG_AP_MODE ++ ++/* ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0); ++ rtw_list_delete(&psta->asoc_list); ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0); ++*/ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0); ++ if (!rtw_is_list_empty(&psta->auth_list)) { ++ rtw_list_delete(&psta->auth_list); ++ pstapriv->auth_list_cnt--; ++ } ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0); ++ ++ psta->expire_to = 0; ++#ifdef CONFIG_ATMEL_RC_PATCH ++ psta->flag_atmel_rc = 0; ++#endif ++ psta->sleepq_ac_len = 0; ++ psta->qos_info = 0; ++ ++ psta->max_sp_len = 0; ++ psta->uapsd_bk = 0; ++ psta->uapsd_be = 0; ++ psta->uapsd_vi = 0; ++ psta->uapsd_vo = 0; ++ ++ psta->has_legacy_ac = 0; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ ++ pstapriv->sta_dz_bitmap &=~BIT(psta->aid); ++ pstapriv->tim_bitmap &=~BIT(psta->aid); ++ ++ //rtw_indicate_sta_disassoc_event(padapter, psta); ++ ++ if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta)) ++ { ++ pstapriv->sta_aid[psta->aid - 1] = NULL; ++ psta->aid = 0; ++ } ++ ++#endif // CONFIG_NATIVEAP_MLME ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++#endif // CONFIG_AP_MODE ++ ++ _rtw_spinlock_free(&psta->lock); ++ ++ //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); ++ rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); ++ //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++// free all stainfo which in sta_hash[all] ++void rtw_free_all_stainfo(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ s32 index; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter); ++ ++_func_enter_; ++ ++ if(pstapriv->asoc_sta_count==1) ++ goto exit; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(index=0; index< NUM_STA; index++) ++ { ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); ++ ++ plist = get_next(plist); ++ ++ if(pbcmc_stainfo!=psta) ++ rtw_free_stainfo(padapter , psta); ++ ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++/* any station allocated can be searched by hash list */ ++struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) ++{ ++ ++ _irqL irqL; ++ ++ _list *plist, *phead; ++ ++ struct sta_info *psta = NULL; ++ ++ u32 index; ++ ++ u8 *addr; ++ ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++_func_enter_; ++ ++ if(hwaddr==NULL) ++ return NULL; ++ ++ if(IS_MCAST(hwaddr)) ++ { ++ addr = bc_addr; ++ } ++ else ++ { ++ addr = hwaddr; ++ } ++ ++ index = wifi_mac_hash(addr); ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE) ++ { // if found the matched address ++ break; ++ } ++ psta=NULL; ++ plist = get_next(plist); ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++_func_exit_; ++ return psta; ++ ++} ++ ++u32 rtw_init_bcmc_stainfo(_adapter* padapter) ++{ ++ ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ u32 res=_SUCCESS; ++ NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ //_queue *pstapending = &padapter->xmitpriv.bm_pending; ++ ++_func_enter_; ++ ++ psta = rtw_alloc_stainfo(pstapriv, bcast_addr); ++ ++ if(psta==NULL){ ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail")); ++ goto exit; ++ } ++ ++ // default broadcast & multicast use macid 1 ++ psta->mac_id = 1; ++ ++ ptxservq= &(psta->sta_xmitpriv.be_q); ++ ++/* ++ _enter_critical(&pstapending->lock, &irqL0); ++ ++ if (rtw_is_list_empty(&ptxservq->tx_pending)) ++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending)); ++ ++ _exit_critical(&pstapending->lock, &irqL0); ++*/ ++ ++exit: ++_func_exit_; ++ return _SUCCESS; ++ ++} ++ ++ ++struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter) ++{ ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++_func_enter_; ++ psta = rtw_get_stainfo(pstapriv, bc_addr); ++_func_exit_; ++ return psta; ++ ++} ++ ++u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr) ++{ ++ u8 res = _TRUE; ++#ifdef CONFIG_AP_MODE ++ _irqL irqL; ++ _list *plist, *phead; ++ struct rtw_wlan_acl_node *paclnode; ++ u8 match = _FALSE; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; ++ _queue *pacl_node_q =&pacl_list->acl_node_q; ++ ++ _enter_critical_bh(&(pacl_node_q->lock), &irqL); ++ phead = get_list_head(pacl_node_q); ++ plist = get_next(phead); ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN)) ++ { ++ if(paclnode->valid == _TRUE) ++ { ++ match = _TRUE; ++ break; ++ } ++ } ++ } ++ _exit_critical_bh(&(pacl_node_q->lock), &irqL); ++ ++ ++ if(pacl_list->mode == 1)//accept unless in deny list ++ { ++ res = (match == _TRUE) ? _FALSE:_TRUE; ++ } ++ else if(pacl_list->mode == 2)//deny unless in accept list ++ { ++ res = (match == _TRUE) ? _TRUE:_FALSE; ++ } ++ else ++ { ++ res = _TRUE; ++ } ++ ++#endif ++ ++ return res; ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_tdls.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_tdls.c +new file mode 100644 +index 00000000..f7ca24aa +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_tdls.c +@@ -0,0 +1,2941 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_TDLS_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_TDLS ++extern unsigned char MCS_rate_2R[16]; ++extern unsigned char MCS_rate_1R[16]; ++extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); ++extern s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++void rtw_reset_tdls_info(_adapter* padapter) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ ptdlsinfo->ap_prohibited = _FALSE; ++ ptdlsinfo->setup_state = TDLS_STATE_NONE; ++ ptdlsinfo->sta_cnt = 0; ++ ptdlsinfo->sta_maximum = _FALSE; ++ ptdlsinfo->macid_index= 6; ++ ptdlsinfo->clear_cam= 0; ++ ptdlsinfo->ch_sensing = 0; ++ ptdlsinfo->cur_channel = 0; ++ ptdlsinfo->candidate_ch = 1; //when inplement channel switching, default candidate channel is 1 ++ ptdlsinfo->watchdog_count = 0; ++ ptdlsinfo->dev_discovered = 0; ++ ++#ifdef CONFIG_WFD ++ ptdlsinfo->wfd_info = &padapter->wfd_info; ++#endif //CONFIG_WFD ++} ++ ++int rtw_init_tdls_info(_adapter* padapter) ++{ ++ int res = _SUCCESS; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ ptdlsinfo->enable = 1; ++ rtw_reset_tdls_info(padapter); ++ ++ _rtw_spinlock_init(&ptdlsinfo->cmd_lock); ++ _rtw_spinlock_init(&ptdlsinfo->hdl_lock); ++ ++ return res; ++ ++} ++ ++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo) ++{ ++ _rtw_spinlock_free(&ptdlsinfo->cmd_lock); ++ _rtw_spinlock_free(&ptdlsinfo->hdl_lock); ++ ++ _rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info) ); ++ ++} ++ ++void issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, struct sta_info *ptdls_sta, unsigned int power_mode) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++// SetToDs(fctrl); ++ if (power_mode) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr1, ptdls_sta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(pwlanhdr, pattrib->seqnum); ++ ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ ++ s32 res=_SUCCESS; ++ sint bmcast; ++ ++ bmcast = IS_MCAST(pattrib->ra); ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ if (psta == NULL) { ++ res =_FAIL; ++ goto exit; ++ } ++ ++ pattrib->mac_id = psta->mac_id; ++ ++ pattrib->psta = psta; ++ ++ pattrib->ack_policy = 0; ++ // get ether_hdr_len ++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag ++ ++ if (pqospriv->qos_option && psta->qos_option) { ++ pattrib->priority = 1; //tdls management frame should be AC_BK ++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; ++ pattrib->subtype = WIFI_QOS_DATA_TYPE; ++ } else { ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA_TYPE; ++ pattrib->priority = 0; ++ } ++ ++ if (psta->ieee8021x_blocked == _TRUE) ++ { ++ pattrib->encrypt = 0; ++ } ++ else ++ { ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); ++ ++ switch(psecuritypriv->dot11AuthAlgrthm) ++ { ++ case dot11AuthAlgrthm_Open: ++ case dot11AuthAlgrthm_Shared: ++ case dot11AuthAlgrthm_Auto: ++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case dot11AuthAlgrthm_8021X: ++ pattrib->key_idx = 0; ++ break; ++ default: ++ pattrib->key_idx = 0; ++ break; ++ } ++ } ++ ++ switch (pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ pattrib->iv_len = 4; ++ pattrib->icv_len = 4; ++ break; ++ case _TKIP_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 4; ++ if(padapter->securitypriv.busetkipkey==_FAIL) ++ { ++ res =_FAIL; ++ goto exit; ++ } ++ break; ++ case _AES_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 8; ++ break; ++ default: ++ pattrib->iv_len = 0; ++ pattrib->icv_len = 0; ++ break; ++ } ++ ++ if (pattrib->encrypt && ++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) ++ { ++ pattrib->bswenc = _TRUE; ++ } else { ++ pattrib->bswenc = _FALSE; ++ } ++ ++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi ++ pattrib->qos_en = psta->qos_option; ++ pattrib->ht_en = psta->htpriv.ht_option; ++ pattrib->raid = psta->raid; ++ pattrib->bwmode = psta->htpriv.bwmode; ++ pattrib->ch_offset = psta->htpriv.ch_offset; ++ pattrib->sgi= psta->htpriv.sgi; ++ pattrib->ampdu_en = _FALSE; ++ ++ //if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ //{ ++ // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ // pattrib->ampdu_en = _TRUE; ++ //} ++ ++exit: ++ ++ return res; ++} ++ ++void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ _irqL irqL; ++ ++ //free peer sta_info ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if(ptdlsinfo->sta_cnt != 0) ++ ptdlsinfo->sta_cnt--; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt < (NUM_STA - 2) ) // -2: AP + BC/MC sta ++ { ++ ptdlsinfo->sta_maximum = _FALSE; ++ _rtw_memset( &ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record) ); ++ } ++ //ready to clear cam ++ if(ptdls_sta->mac_id!=0){ ++ ptdlsinfo->clear_cam=ptdls_sta->mac_id; ++ rtw_setstakey_cmd(padapter, (u8 *)ptdls_sta, _TRUE, _TRUE); ++ } ++ ++ if(ptdlsinfo->sta_cnt==0){ ++ rtw_tdls_cmd(padapter, myid(&(padapter->eeprompriv)), TDLS_RS_RCR); ++ ptdlsinfo->setup_state=TDLS_STATE_NONE; ++ } ++ else ++ DBG_871X("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); ++ ++ rtw_free_stainfo(padapter, ptdls_sta); ++ ++} ++ ++// cam entry will be the same as mac_id ++void rtw_tdls_set_mac_id(struct tdls_info *ptdlsinfo, struct sta_info *ptdls_sta) ++{ ++ if(ptdls_sta->mac_id==0) ++ { ++ ptdls_sta->mac_id = ptdlsinfo->macid_index; ++ if( (++ptdlsinfo->macid_index) > (NUM_STA -2) ) ++ ptdlsinfo->macid_index= TDLS_INI_MACID_ENTRY; ++ } ++} ++ ++//TDLS encryption(if needed) will always be CCMP ++void rtw_tdls_set_key(_adapter *adapter, struct rx_pkt_attrib *prx_pkt_attrib, struct sta_info *ptdls_sta) ++{ ++ if(prx_pkt_attrib->encrypt) ++ { ++ ptdls_sta->dot118021XPrivacy=_AES_; ++ rtw_setstakey_cmd(adapter, (u8*)ptdls_sta, _TRUE, _TRUE); ++ } ++} ++ ++void rtw_tdls_process_ht_cap(_adapter *adapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) ++{ ++ /* save HT capabilities in the sta object */ ++ _rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap) ) ++ { ++ ptdls_sta->flags |= WLAN_STA_HT; ++ ++ ptdls_sta->flags |= WLAN_STA_WME; ++ ++ _rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ } else ++ ptdls_sta->flags &= ~WLAN_STA_HT; ++ ++ if(ptdls_sta->flags & WLAN_STA_HT) ++ { ++ if(adapter->registrypriv.ht_enable == _TRUE) ++ { ++ ptdls_sta->htpriv.ht_option = _TRUE; ++ } ++ else ++ { ++ ptdls_sta->htpriv.ht_option = _FALSE; ++ ptdls_sta->stat_code = _STATS_FAILURE_; ++ } ++ } ++ ++ //HT related cap ++ if(ptdls_sta->htpriv.ht_option) ++ { ++ //check if sta supports rx ampdu ++ if(adapter->registrypriv.ampdu_enable==1) ++ ptdls_sta->htpriv.ampdu_enable = _TRUE; ++ ++ //check if sta support s Short GI ++ if(ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ++ { ++ ptdls_sta->htpriv.sgi = _TRUE; ++ } ++ ++ // bwmode would still followed AP's setting ++ if(ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) ++ { ++ ptdls_sta->htpriv.bwmode = adapter->mlmeextpriv.cur_bwmode; ++ ptdls_sta->htpriv.ch_offset = adapter->mlmeextpriv.cur_ch_offset; ++ } ++ } ++} ++ ++u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) ++{ ++ struct rtw_ieee80211_ht_cap ht_capie; ++ u8 rf_type; ++ ++ //HT capabilities ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 |IEEE80211_HT_CAP_SM_PS | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC |IEEE80211_HT_CAP_DSSSCCK40; ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ if(max_recvbuf_sz-rx_packet_offset>(8191-256)) ++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ } ++ ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ switch(rf_type) ++ { ++ case RF_1T1R: ++ ht_capie.cap_info |= 0x0100;//RX STBC One spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ht_capie.cap_info|= 0x0200;//RX STBC two spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_2R, 16); ++ break; ++ } ++ ++ return(rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, &(pattrib->pktlen))); ++} ++ ++u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib) ++{ ++ u8 sup_ch[ 30 * 2 ] = { 0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel ++ do{ ++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14 ) ++ { ++ sup_ch[0] = 1; //First channel number ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; //Number of channel ++ } ++ else ++ { ++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; ++ sup_ch[idx_5g++] = 1; ++ } ++ ++ sup_ch_idx++; ++ } ++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 ); ++ return(rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g, sup_ch, &(pattrib->pktlen))); ++} ++ ++#ifdef CONFIG_WFD ++void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length) ++{ ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++ u32 wfd_offset = 0; ++ // Try to get the TCP port information when receiving the negotiation response. ++ // ++ ++ wfd_offset = 0; ++ wfd_offset = rtw_get_wfd_ie( ptr + wfd_offset, length - wfd_offset, wfd_ie, &wfd_ielen ); ++ while( wfd_offset ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ int i; ++ ++ DBG_871X( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_871X( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport ); ++ } ++ ++ _rtw_memset( attr_content, 0x00, 10); ++ attr_contentlen = 0; ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ _rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, ( attr_content + 1 ), 4); ++ DBG_871X( "[%s] Peer IP = %02u.%02u.%02u.%02u \n", __FUNCTION__, ++ ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1], ++ ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3] ++ ); ++ } ++ wfd_offset = rtw_get_wfd_ie( ptr + wfd_offset, length - wfd_offset, wfd_ie, &wfd_ielen ); ++ } ++} ++ ++void issue_tunneled_probe_req(_adapter *padapter) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TUNNELED_PROBE_REQ) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TUNNELED_PROBE_RSP) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++#endif //CONFIG_WFD ++ ++void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta= NULL; ++ _irqL irqL; ++ static u8 dialogtoken = 0; ++ u32 timeout_interval= TPK_RESEND_COUNT * 1000; //retry timer should set at least 301 sec, using TPK_count counting 301 times. ++ ++ if(ptdlsinfo->ap_prohibited == _TRUE) ++ goto exit; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ //init peer sta_info ++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta==NULL) ++ { ++ ptdls_sta = rtw_alloc_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta) ++ { ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if(!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) ++ ptdlsinfo->sta_cnt++; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt == (NUM_STA - 2) ) // -2: AP + BC/MC sta ++ { ++ ptdlsinfo->sta_maximum = _TRUE; ++ } ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ } ++ ++ if(ptdls_sta){ ++ ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE; ++ //for tdls; ptdls_sta->aid is used to fill dialogtoken ++ ptdls_sta->dialog = dialogtoken; ++ dialogtoken = (dialogtoken+1)%256; ++ ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; ++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME ); ++ } ++ ++ pattrib->qsel=pattrib->priority; ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_REQUEST) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_teardown(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta=NULL; ++ _irqL irqL; ++ ++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta==NULL){ ++ DBG_871X("issue tdls teardown unsuccessful\n"); ++ return; ++ }else{ ++ ptdls_sta->tdls_sta_state=TDLS_STATE_NONE; ++ } ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_TEARDOWN) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){ ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ ++ if( ptdls_sta->timer_flag == 1 ) ++ { ++ _enter_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 2; ++ _exit_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL); ++ } ++ else ++ rtw_tdls_cmd(padapter, mac_addr, TDLS_FREE_STA ); ++ ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_dis_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ if(mac_addr == NULL) ++ _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN); ++ else ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_DISCOVERY_REQUEST) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ DBG_871X("issue tdls dis req\n"); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_setup_rsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib; ++ _irqL irqL; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_RESPONSE) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++ ++} ++ ++void issue_tdls_setup_cfm(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_info *ptdls_sta=NULL; ++ _irqL irqL; ++ ++ struct rx_pkt_attrib *rx_pkt_pattrib = & precv_frame->u.hdr.attrib; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_CONFIRM) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++ ++} ++ ++//TDLS Discovery Response frame is a management action frame ++void issue_tdls_dis_rsp(_adapter *padapter, union recv_frame *precv_frame, u8 dialog) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ // unicast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr3, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, dialog); ++ ++ pattrib->nr_frags = 1; ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++void issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ static u8 dialogtoken=0; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ //for tdls; pattrib->nr_frags is used to fill dialogtoken ++ ptdls_sta->dialog = dialogtoken; ++ dialogtoken = (dialogtoken+1)%256; ++ //PTI frame's priority should be AC_VO ++ pattrib->priority = 7; ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_PEER_TRAFFIC_INDICATION) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_ch_switch_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ pattrib->qsel=pattrib->priority; ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_REQUEST) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_ch_switch_rsp(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ _irqL irqL; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ pattrib->qsel=pattrib->priority; ++/* ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ return _FALSE; ++ } ++*/ ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_RESPONSE) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(adapter->stapriv), get_bssid(&(adapter->mlmepriv))); ++ struct recv_priv *precvpriv = &(adapter->recvpriv); ++ u8 *ptr = precv_frame->u.hdr.rx_data, *psa; ++ struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); ++ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); ++ u8 empty_addr[ETH_ALEN] = { 0x00 }; ++ int UndecoratedSmoothedPWDB; ++ ++ ++ //WFDTDLS: for sigma test, not to setup direct link automatically ++ ptdlsinfo->dev_discovered = 1; ++ ++#ifdef CONFIG_TDLS_AUTOSETUP ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(&(adapter->stapriv), psa); ++ ++ if(ptdls_sta != NULL) ++ { ++ ptdls_sta->tdls_sta_state |= TDLS_ALIVE_STATE; ++ ++ //Record the tdls sta with lowest signal strength ++ if( (ptdlsinfo->sta_maximum == _TRUE) && (ptdls_sta->alive_count >= 1) ) ++ { ++ if( _rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN) ) ++ { ++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); ++ ptdlsinfo->ss_record.RxPWDBAll = pattrib->RxPWDBAll; ++ } ++ else ++ { ++ if( ptdlsinfo->ss_record.RxPWDBAll < pattrib->RxPWDBAll ) ++ { ++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); ++ ptdlsinfo->ss_record.RxPWDBAll = pattrib->RxPWDBAll; ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ if( ptdlsinfo->sta_maximum == _TRUE) ++ { ++ if( _rtw_memcmp( ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN ) ) ++ { ++ //All traffics are busy, do not set up another direct link. ++ return _FAIL; ++ } ++ else ++ { ++ if( pattrib->RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll ) ++ { ++ issue_tdls_teardown(adapter, ptdlsinfo->ss_record.macaddr); ++ } ++ else ++ { ++ return _FAIL; ++ } ++ } ++ } ++ ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); ++ ++ if( pattrib->RxPWDBAll + TDLS_SIGNAL_THRESH >= UndecoratedSmoothedPWDB); ++ { ++ DBG_871X("pattrib->RxPWDBAll=%d, pdmpriv->UndecoratedSmoothedPWDB=%d\n", pattrib->RxPWDBAll, UndecoratedSmoothedPWDB); ++ issue_tdls_setup_req(adapter, psa); ++ } ++ } ++#endif //CONFIG_TDLS_AUTOSETUP ++ ++ return _SUCCESS; ++} ++ ++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ u8 *psa, *pmyid; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *prsnie, *ppairwise_cipher; ++ u8 i, k, pairwise_count; ++ u8 ccmp_have=0, rsnie_have=0; ++ u16 j; ++ u8 SNonce[32]; ++ u32 *timeout_interval; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE = 5; ++ unsigned char supportRate[16]; ++ int supportRateNum = 0; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ pmyid=myid(&(adapter->eeprompriv)); ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -ETH_TYPE_LEN ++ -PAYLOAD_TYPE_LEN ++ -FIXED_IE; ++ ++ if(ptdlsinfo->ap_prohibited == _TRUE) ++ { ++ goto exit; ++ } ++ ++ if(ptdls_sta==NULL){ ++ ptdls_sta = rtw_alloc_stainfo(pstapriv, psa); ++ }else{ ++ if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE){ ++ //If the direct link is already set up ++ //Process as re-setup after tear down ++ DBG_871X("re-setup a direct link\n"); ++ } ++ //already receiving TDLS setup request ++ else if(ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE){ ++ DBG_871X("receive duplicated TDLS setup request frame in handshaking\n"); ++ goto exit; ++ } ++ //When receiving and sending setup_req to the same link at the same time, STA with higher MAC_addr would be initiator ++ //following is to check out MAC_addr ++ else if(ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE){ ++ DBG_871X("receive setup_req after sending setup_req\n"); ++ for (i=0;i<6;i++){ ++ if(*(pmyid+i)==*(psa+i)){ ++ } ++ else if(*(pmyid+i)>*(psa+i)){ ++ goto exit; ++ }else if(*(pmyid+i)<*(psa+i)){ ++ ptdls_sta->tdls_sta_state=TDLS_INITIATOR_STATE; ++ break; ++ } ++ } ++ } ++ } ++ ++ if(ptdls_sta) ++ { ++ ptdls_sta->dialog = *(ptr+2); //copy dialog token ++ ptdls_sta->stat_code = 0; ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _SUPPORTEDRATES_IE_: ++ _rtw_memcpy(supportRate, pIE->data, pIE->Length); ++ supportRateNum = pIE->Length; ++ break; ++ case _COUNTRY_IE_: ++ break; ++ case _EXT_SUPPORTEDRATES_IE_: ++ if(supportRateNum<=sizeof(supportRate)) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length); ++ supportRateNum += pIE->Length; ++ } ++ break; ++ case _SUPPORTED_CH_IE_: ++ break; ++ case _RSN_IE_2_: ++ rsnie_have=1; ++ if(prx_pkt_attrib->encrypt){ ++ prsnie=(u8*)pIE; ++ //check whether initiator STA has CCMP pairwise_cipher. ++ ppairwise_cipher=prsnie+10; ++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 1); ++ for(k=0;kstat_code=72; ++ } ++ } ++ break; ++ case _EXT_CAP_IE_: ++ break; ++ case _VENDOR_SPECIFIC_IE_: ++ break; ++ case _FTIE_: ++ if(prx_pkt_attrib->encrypt) ++ _rtw_memcpy(SNonce, (ptr+j+52), 32); ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ if(prx_pkt_attrib->encrypt) ++ timeout_interval = (u32 *)(ptr+j+3); ++ break; ++ case _RIC_Descriptor_IE_: ++ break; ++ case _HT_CAPABILITY_IE_: ++ rtw_tdls_process_ht_cap(adapter, ptdls_sta, pIE->data, pIE->Length); ++ break; ++ case EID_BSSCoexistence: ++ break; ++ case _LINK_ID_IE_: ++ if(_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE) ++ { ++ //not in the same BSS ++ ptdls_sta->stat_code=7; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //update station supportRate ++ ptdls_sta->bssratelen = supportRateNum; ++ _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); ++ ++ //check status code ++ //if responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject ++ if(ptdls_sta->stat_code == 0 ) ++ { ++ if(rsnie_have && (prx_pkt_attrib->encrypt==0)){ ++ //security disabled ++ ptdls_sta->stat_code = 5; ++ }else if(rsnie_have==0 && (prx_pkt_attrib->encrypt)){ ++ //request haven't RSNIE ++ ptdls_sta->stat_code = 38; ++ } ++ ++#ifdef CONFIG_WFD ++ //WFD test plan version 0.18.2 test item 5.1.5 ++ //SoUT does not use TDLS if AP uses weak security ++ if ( adapter->wdinfo.wfd_tdls_enable ) ++ { ++ if(rsnie_have && (prx_pkt_attrib->encrypt != _AES_)) ++ { ++ ptdls_sta->stat_code = 5; ++ } ++ } ++#endif //CONFIG_WFD ++ } ++ ++ ptdls_sta->tdls_sta_state|= TDLS_INITIATOR_STATE; ++ if(prx_pkt_attrib->encrypt){ ++ _rtw_memcpy(ptdls_sta->SNonce, SNonce, 32); ++ _rtw_memcpy(&(ptdls_sta->TDLS_PeerKey_Lifetime), timeout_interval, 4); ++ } ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if(!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) ++ ptdlsinfo->sta_cnt++; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt == (NUM_STA - 2) ) // -2: AP + BC/MC sta ++ { ++ ptdlsinfo->sta_maximum = _TRUE; ++ } ++ ++#ifdef CONFIG_WFD ++ rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length - FIXED_IE); ++#endif // CONFIG_WFD ++ ++ } ++ else ++ { ++ goto exit; ++ } ++ ++ issue_tdls_setup_rsp(adapter, precv_frame); ++ ++ if(ptdls_sta->stat_code==0) ++ { ++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); ++ } ++ else //status code!=0 ; setup unsuccess ++ { ++ free_tdls_sta(adapter, ptdls_sta); ++ } ++ ++exit: ++ ++ return _FAIL; ++} ++ ++sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ u16 stat_code; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =7; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher; ++ u16 pairwise_count, j, k; ++ u8 verify_ccmp=0; ++ unsigned char supportRate[16]; ++ int supportRateNum = 0; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ if ( NULL == ptdls_sta ) ++ { ++ return _FAIL; ++ } ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0) ++ { ++ DBG_871X( "[%s] status_code = %d, free_tdls_sta\n", __FUNCTION__, stat_code ); ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ stat_code = 0; ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _SUPPORTEDRATES_IE_: ++ _rtw_memcpy(supportRate, pIE->data, pIE->Length); ++ supportRateNum = pIE->Length; ++ break; ++ case _COUNTRY_IE_: ++ break; ++ case _EXT_SUPPORTEDRATES_IE_: ++ if(supportRateNum<=sizeof(supportRate)) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length); ++ supportRateNum += pIE->Length; ++ } ++ break; ++ case _SUPPORTED_CH_IE_: ++ break; ++ case _RSN_IE_2_: ++ prsnie=(u8*)pIE; ++ //check whether responder STA has CCMP pairwise_cipher. ++ ppairwise_cipher=prsnie+10; ++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 2); ++ for(k=0;kANonce, (ptr+j+20), 32); ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ ptimeout_ie=(u8*)pIE; ++ break; ++ case _RIC_Descriptor_IE_: ++ break; ++ case _HT_CAPABILITY_IE_: ++ rtw_tdls_process_ht_cap(adapter, ptdls_sta, pIE->data, pIE->Length); ++ break; ++ case EID_BSSCoexistence: ++ break; ++ case _LINK_ID_IE_: ++ plinkid_ie=(u8*)pIE; ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //update station supportRate ++ ptdls_sta->bssratelen = supportRateNum; ++ _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); ++ ++#ifdef CONFIG_WFD ++ rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length - FIXED_IE); ++#endif // CONFIG_WFD ++ ++ if(stat_code != 0) ++ { ++ ptdls_sta->stat_code = stat_code; ++ } ++ else ++ { ++ if(prx_pkt_attrib->encrypt) ++ { ++ if(verify_ccmp==1) ++ { ++ wpa_tdls_generate_tpk(adapter, ptdls_sta); ++ ptdls_sta->stat_code=0; ++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie)==0) //0: Invalid, 1: valid ++ { ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ } ++ else ++ { ++ ptdls_sta->stat_code=72; //invalide contents of RSNIE ++ } ++ ++ }else{ ++ ptdls_sta->stat_code=0; ++ } ++ } ++ ++ DBG_871X("issue_tdls_setup_cfm\n"); ++ issue_tdls_setup_cfm(adapter, precv_frame); ++ ++ if(ptdls_sta->stat_code==0) ++ { ++ ptdlsinfo->setup_state = TDLS_LINKED_STATE; ++ ++ if( ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE ) ++ { ++ ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; ++ _cancel_timer_ex( &ptdls_sta->handshake_timer); ++#ifdef CONFIG_TDLS_AUTOCHECKALIVE ++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++#endif //CONFIG_TDLS_AUTOSETUP ++ } ++ ++ rtw_tdls_set_mac_id(ptdlsinfo, ptdls_sta); ++ rtw_tdls_set_key(adapter, prx_pkt_attrib, ptdls_sta); ++ ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR); ++ ++ } ++ else //status code!=0 ; setup unsuccessful ++ { ++ free_tdls_sta(adapter, ptdls_sta); ++ } ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ u16 stat_code; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =5; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher; ++ u16 j, pairwise_count; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -ETH_TYPE_LEN ++ -PAYLOAD_TYPE_LEN ++ -FIXED_IE; ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0){ ++ DBG_871X( "[%s] stat_code = %d\n, free_tdls_sta", __FUNCTION__, stat_code ); ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ if(prx_pkt_attrib->encrypt){ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _RSN_IE_2_: ++ prsnie=(u8*)pIE; ++ break; ++ case _VENDOR_SPECIFIC_IE_: ++ break; ++ case _FTIE_: ++ pftie=(u8*)pIE; ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ ptimeout_ie=(u8*)pIE; ++ break; ++ case _HT_EXTRA_INFO_IE_: ++ break; ++ case _LINK_ID_IE_: ++ plinkid_ie=(u8*)pIE; ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //verify mic in FTIE MIC field ++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie)==0){ //0: Invalid, 1: Valid ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ } ++ ++ ptdlsinfo->setup_state = TDLS_LINKED_STATE; ++ if( ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE ) ++ { ++ ptdls_sta->tdls_sta_state|=TDLS_LINKED_STATE; ++ _cancel_timer_ex( &ptdls_sta->handshake_timer); ++#ifdef CONFIG_TDLS_AUTOCHECKALIVE ++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++#endif //CONFIG_TDLS_AUTOCHECKALIVE ++ } ++ ++ rtw_tdls_set_mac_id(ptdlsinfo, ptdls_sta); ++ rtw_tdls_set_key(adapter, prx_pkt_attrib, ptdls_sta); ++ ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR); ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct sta_info *psta_ap; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE = 3, *dst, *pdialog = NULL; ++ u16 j; ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE + 1; ++ pdialog=ptr+2; ++ ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _LINK_ID_IE_: ++ psta_ap = rtw_get_stainfo(pstapriv, pIE->data); ++ if(psta_ap == NULL) ++ { ++ goto exit; ++ } ++ dst = pIE->data + 12; ++ if( (MacAddr_isBcst(dst) == _FALSE) && (_rtw_memcmp(myid(&(adapter->eeprompriv)), dst, 6) == _FALSE) ) ++ { ++ goto exit; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //check frame contents ++ ++ issue_tdls_dis_rsp(adapter, precv_frame, *(pdialog) ); ++ ++exit: ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ u8 *psa; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct sta_info *ptdls_sta= NULL; ++ _irqL irqL; ++ ++ psa = get_sa(ptr); ++ ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ if(ptdls_sta!=NULL){ ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){ ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ free_tdls_sta(adapter, ptdls_sta); ++ } ++ ++ return _FAIL; ++ ++} ++ ++u8 TDLS_check_ch_state(uint state){ ++ if( (state & TDLS_CH_SWITCH_ON_STATE) && ++ (state & TDLS_AT_OFF_CH_STATE) && ++ (state & TDLS_PEER_AT_OFF_STATE) ){ ++ ++ if(state & TDLS_PEER_SLEEP_STATE) ++ return 2; //U-APSD + ch. switch ++ else ++ return 1; //ch. switch ++ }else ++ return 0; ++} ++ ++//we process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here ++sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ //get peer sta infomation ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); ++ u8 wmmps_ac=0, state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); ++ int i; ++ ++ ptdls_sta->sta_stats.rx_data_pkts++; ++ ++ //receive peer traffic response frame, sleeping STA wakes up ++ //ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_SLEEP_STATE); ++ process_wmmps_data( adapter, precv_frame); ++ ++ // if noticed peer STA wakes up by receiving peer traffic response ++ // and we want to do channel swtiching, then we will transmit channel switch request first ++ if(ptdls_sta->tdls_sta_state & TDLS_APSD_CHSW_STATE){ ++ issue_tdls_ch_switch_req(adapter, pattrib->src); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_APSD_CHSW_STATE); ++ return _FAIL; ++ } ++ ++ //check 4-AC queue bit ++ if(ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk) ++ wmmps_ac=1; ++ ++ //if it's a direct link and have buffered frame ++ if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE){ ++ if(wmmps_ac && state) ++ { ++ _irqL irqL; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ ++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&ptdls_sta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ //transmit buffered frames ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ xmitframe_plist = get_next(xmitframe_plist); ++ rtw_list_delete(&pxmitframe->list); ++ ++ ptdls_sta->sleepq_len--; ++ if(ptdls_sta->sleepq_len>0){ ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ }else{ ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ //pxmitframe->attrib.triggered = 1; //maybe doesn't need in TDLS ++ if(adapter->HalFunc.hal_xmit(adapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(adapter, pxmitframe); ++ } ++ ++ } ++ ++ if(ptdls_sta->sleepq_len==0) ++ { ++ DBG_871X("no buffered packets for tdls to xmit\n"); ++ //on U-APSD + CH. switch state, when there is no buffered date to xmit, ++ // we should go back to base channel ++ if(state==2){ ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ }else if(ptdls_sta->tdls_sta_state&TDLS_SW_OFF_STATE){ ++ ptdls_sta->tdls_sta_state &= ~(TDLS_SW_OFF_STATE); ++ ptdlsinfo->candidate_ch= pmlmeext->cur_channel; ++ issue_tdls_ch_switch_req(adapter, pattrib->src); ++ DBG_871X("issue tdls ch switch req back to base channel\n"); ++ } ++ ++ } ++ else ++ { ++ DBG_871X("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len); ++ ptdls_sta->sleepq_len=0; ++ } ++ ++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ } ++ ++ } ++ ++ return _FAIL; ++} ++ ++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =3; ++ u16 j; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -ETH_TYPE_LEN ++ -PAYLOAD_TYPE_LEN ++ -FIXED_IE; ++ ++ ptdls_sta->off_ch = *(ptr+2); ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _COUNTRY_IE_: ++ break; ++ case _CH_SWTICH_ANNOUNCE_: ++ break; ++ case _LINK_ID_IE_: ++ break; ++ case _CH_SWITCH_TIMING_: ++ _rtw_memcpy(&ptdls_sta->ch_switch_time, pIE->data, 2); ++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, pIE->data+2, 2); ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //todo: check status ++ ptdls_sta->stat_code=0; ++ ptdls_sta->tdls_sta_state |= TDLS_CH_SWITCH_ON_STATE; ++ ++ issue_nulldata(adapter, NULL, 1, 0, 0); ++ ++ issue_tdls_ch_switch_rsp(adapter, psa); ++ ++ DBG_871X("issue tdls channel switch response\n"); ++ ++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE) && ptdls_sta->off_ch==pmlmeext->cur_channel){ ++ DBG_871X("back to base channel %x\n", pmlmeext->cur_channel); ++ ptdls_sta->option=7; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_BASE_CH); ++ }else{ ++ ptdls_sta->option=6; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ } ++ return _FAIL; ++} ++ ++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =4; ++ u16 stat_code, j, switch_time, switch_timeout; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ //if channel switch is running and receiving Unsolicited TDLS Channel Switch Response, ++ //it will go back to base channel and terminate this channel switch procedure ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE ){ ++ if(pmlmeext->cur_channel==ptdls_sta->off_ch){ ++ DBG_871X("back to base channel %x\n", pmlmeext->cur_channel); ++ ptdls_sta->option=7; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ }else{ ++ DBG_871X("receive unsolicited channel switch response \n"); ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ return _FAIL; ++ } ++ ++ //avoiding duplicated or unconditional ch. switch. rsp ++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SW_INITIATOR_STATE) != TDLS_CH_SW_INITIATOR_STATE) ++ return _FAIL; ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -ETH_TYPE_LEN ++ -PAYLOAD_TYPE_LEN ++ -FIXED_IE; ++ ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0){ ++ return _FAIL; ++ } ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _LINK_ID_IE_: ++ break; ++ case _CH_SWITCH_TIMING_: ++ _rtw_memcpy(&switch_time, pIE->data, 2); ++ if(switch_time > ptdls_sta->ch_switch_time) ++ _rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2); ++ ++ _rtw_memcpy(&switch_timeout, pIE->data+2, 2); ++ if(switch_timeout > ptdls_sta->ch_switch_timeout) ++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2); ++ ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SW_INITIATOR_STATE); ++ ptdls_sta->tdls_sta_state |=TDLS_CH_SWITCH_ON_STATE; ++ ++ //goto set_channel_workitem_callback() ++ ptdls_sta->option=6; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ ++ return _FAIL; ++} ++ ++#ifdef CONFIG_WFD ++void wfd_ie_tdls(_adapter * padapter, u8 *pframe, u32 *pktlen ) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info; ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 wfdielen = 0; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL ++ | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate( pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ // Local IP Address ATTR ++ wfdie[ wfdielen++ ] = WFD_ATTR_LOCAL_IP_ADDR; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0005); ++ wfdielen += 2; ++ ++ // Version: ++ // 0x01: Version1;IPv4 ++ wfdie[ wfdielen++ ] = 0x01; ++ ++ // IPv4 Address ++ _rtw_memcpy( wfdie + wfdielen, pwfd_info->ip_address, 4 ); ++ wfdielen += 4; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen); ++ ++} ++#endif //CONFIG_WFD ++ ++void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); ++ ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_TDLS; ++ u8 action = TDLS_SETUP_REQUEST; ++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; //Use NDIS_802_11_LENGTH_RATES_EX in order to call func.rtw_set_supported_rate ++ int bssrate_len = 0, i = 0 ; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ u8 *p; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 iedata=0; ++ u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ u32 time; ++ ++ //SNonce ++ if(pattrib->encrypt){ ++ for(i=0;i<8;i++){ ++ time=rtw_get_current_time(); ++ _rtw_memcpy(&ptdls_sta->SNonce[4*i], (u8 *)&time, 4); ++ } ++ } ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //country(optional) ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); ++ ++ // SRC IE ++ pframe = rtw_set_ie( pframe, _SRC_IE_, 16, TDLS_SRC, &(pattrib->pktlen)); ++ ++ //RSNIE ++ if(pattrib->encrypt) ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ ++ //extended capabilities ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ //QoS capability(WMM_IE) ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen)); ++ ++ ++ if(pattrib->encrypt){ ++ //FTIE ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++#ifdef CONFIG_WFD ++ wfd_ie_tdls( padapter, pframe, &(pattrib->pktlen) ); ++#endif //CONFIG_WFD ++ ++} ++ ++void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *ptdls_sta; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_SETUP_RESPONSE; ++ unsigned char bssrate[NDIS_802_11_LENGTH_RATES_EX]; ++ int bssrate_len = 0; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ unsigned char *p; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 iedata=0; ++ u8 timeout_itvl[5]; //setup response timeout interval will copy from request ++ u8 ANonce[32]; //maybe it can put in ontdls_req ++ u8 k; //for random ANonce ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic; ++ u32 time; ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); ++ ++ if(ptdls_sta == NULL ) ++ { ++ DBG_871X("[%s] %d\n", __FUNCTION__, __LINE__); ++ return; ++ } ++ ++ if(pattrib->encrypt){ ++ for(k=0;k<8;k++){ ++ time=rtw_get_current_time(); ++ _rtw_memcpy(&ptdls_sta->ANonce[4*k], (u8*)&time, 4); ++ } ++ } ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ if(ptdls_sta->stat_code!=0) //invalid setup request ++ { ++ DBG_871X("ptdls_sta->stat_code:%04x \n", ptdls_sta->stat_code); ++ return; ++ } ++ ++ //dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt ) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //country(optional) ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); ++ ++ // SRC IE ++ pframe = rtw_set_ie(pframe, _SRC_IE_ , 16, TDLS_SRC, &(pattrib->pktlen)); ++ ++ //RSNIE ++ if(pattrib->encrypt){ ++ prsnie = pframe; ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ } ++ ++ //extended capabilities ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ //QoS capability(WMM_IE) ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen)); ++ ++ if(pattrib->encrypt){ ++ wpa_tdls_generate_tpk(padapter, ptdls_sta); ++ ++ //FTIE ++ pftie = pframe; ++ pftie_mic = pframe+4; ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32); ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ ptimeout_ie = pframe; ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ plinkid_ie = pframe; ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //fill FTIE mic ++ if(pattrib->encrypt) ++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); ++ ++#ifdef CONFIG_WFD ++ wfd_ie_tdls( padapter, pframe, &(pattrib->pktlen) ); ++#endif //CONFIG_WFD ++ ++} ++ ++void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); ++ ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_SETUP_CONFIRM; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ unsigned char *p; ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status code, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ if(ptdls_sta->stat_code!=0) //invalid setup request ++ return; ++ ++ //RSNIE ++ if(pattrib->encrypt){ ++ prsnie = pframe; ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ } ++ ++ //EDCA param set; WMM param ele. ++ if(pattrib->encrypt){ ++ //FTIE ++ pftie = pframe; ++ pftie_mic = pframe+4; ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32); ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ ptimeout_ie = pframe; ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ ptdls_sta->TPK_count=0; ++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //HT operation; todo ++ //Link identifier ++ plinkid_ie = pframe; ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //fill FTIE mic ++ if(pattrib->encrypt) ++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); ++ ++} ++ ++void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_TEARDOWN; ++ u8 link_id_addr[18] = {0}; ++ ++ struct sta_info *ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ //Link identifier ++ if(ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE){ ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ }else if(ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE){ ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ } ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_TDLS; ++ u8 action = TDLS_DISCOVERY_REQUEST; ++ u8 link_id_addr[18] = {0}; ++ static u8 dialogtoken=0; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen)); ++ dialogtoken = (dialogtoken+1)%256; ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++ u8 category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = TDLS_DISCOVERY_RESPONSE; ++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; ++ int bssrate_len = 0; ++ u8 more_supportedrates = 0; ++ u8 *p; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 iedata=0; ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ u32 timeout_interval= TPK_RESEND_COUNT * 1000; ++ ++ //category, action, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); ++ ++ //RSNIE ++ if(pattrib->encrypt) ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ ++ //extended capability ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ if(pattrib->encrypt){ ++ //FTIE ++ _rtw_memset(pframe, 0, 84); //All fields shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, &timeout_interval, 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ pframe = rtw_tdls_set_ht_cap(padapter, pframe, pattrib); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_PEER_TRAFFIC_INDICATION; ++ ++ u8 link_id_addr[18] = {0}; ++ u8 AC_queue=0; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //PTI control ++ //PU buffer status ++ if(ptdls_sta->uapsd_bk&BIT(1)) ++ AC_queue=BIT(0); ++ if(ptdls_sta->uapsd_be&BIT(1)) ++ AC_queue=BIT(1); ++ if(ptdls_sta->uapsd_vi&BIT(1)) ++ AC_queue=BIT(2); ++ if(ptdls_sta->uapsd_vo&BIT(1)) ++ AC_queue=BIT(3); ++ pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_CHANNEL_SWITCH_REQUEST; ++ u8 link_id_addr[18] = {0}; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ u8 ch_switch_timing[4] = {0}; ++ u16 switch_time= CH_SWITCH_TIME, switch_timeout=CH_SWITCH_TIMEOUT; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, target_ch ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdlsinfo->candidate_ch), &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //ch switch timing ++ _rtw_memcpy(ch_switch_timing, &switch_time, 2); ++ _rtw_memcpy(ch_switch_timing+2, &switch_timeout, 2); ++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen)); ++ ++ //update ch switch attrib to sta_info ++ ptdls_sta->off_ch=ptdlsinfo->candidate_ch; ++ ptdls_sta->ch_switch_time=switch_time; ++ ptdls_sta->ch_switch_timeout=switch_timeout; ++ ++} ++ ++void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_CHANNEL_SWITCH_RESPONSE; ++ u8 link_id_addr[18] = {0}; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 ch_switch_timing[4] = {0}; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status_code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //ch switch timing ++ _rtw_memcpy(ch_switch_timing, &ptdls_sta->ch_switch_time, 2); ++ _rtw_memcpy(ch_switch_timing+2, &ptdls_sta->ch_switch_timeout, 2); ++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen)); ++ ++} ++ ++#ifdef CONFIG_WFD ++void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo; ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_P2P; ++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a}; ++ u8 probe_req = 4; ++ u8 wfdielen = 0; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, OUI, frame_body_type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen)); ++ ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++ else if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) ++ { ++ wfdielen = build_probe_req_wfd_ie(pbuddy_wdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++ ++} ++ ++void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo; ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_P2P; ++ u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a}; ++ u8 probe_rsp = 5; ++ u8 wfdielen = 0; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, OUI, frame_body_type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen)); ++ ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++ else if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) ++ { ++ wfdielen = build_probe_resp_wfd_ie(pbuddy_wdinfo, pframe, 1); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++ } ++ ++} ++#endif //CONFIG_WFD ++ ++void _TPK_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ ++ ptdls_sta->TPK_count++; ++ //TPK_timer set 1000 as default ++ //retry timer should set at least 301 sec. ++ if(ptdls_sta->TPK_count==TPK_RESEND_COUNT){ ++ ptdls_sta->TPK_count=0; ++ issue_tdls_setup_req(ptdls_sta->padapter, ptdls_sta->hwaddr); ++ } ++ ++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT); ++} ++ ++void init_TPK_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ ++ _init_timer(&psta->TPK_timer, padapter->pnetdev, _TPK_timer_hdl, psta); ++} ++ ++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel ++// TDLS_OFF_CH: first time set channel to off channel ++// TDLS_BASE_CH: when go back to the channel linked with AP, send null data to peer STA as an indication ++void _ch_switch_timer_hdl(void *FunctionContext) ++{ ++ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ ++ if( ptdls_sta->option == TDLS_DONE_CH_SEN ){ ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN); ++ }else if( ptdls_sta->option == TDLS_OFF_CH ){ ++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0); ++ _set_timer(&ptdls_sta->base_ch_timer, 500); ++ }else if( ptdls_sta->option == TDLS_BASE_CH){ ++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0); ++ } ++} ++ ++void init_ch_switch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->option_timer, padapter->pnetdev, _ch_switch_timer_hdl, psta); ++} ++ ++void _base_ch_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_OFF_CH); ++} ++ ++void init_base_ch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->base_ch_timer, padapter->pnetdev, _base_ch_timer_hdl, psta); ++} ++ ++void _off_ch_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_BASE_CH ); ++} ++ ++void init_off_ch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->off_ch_timer, padapter->pnetdev, _off_ch_timer_hdl, psta); ++} ++ ++void _tdls_handshake_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ ++ if(ptdls_sta != NULL) ++ { ++ if( !(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) ) ++ { ++ DBG_871X("tdls handshake time out\n"); ++ free_tdls_sta(ptdls_sta->padapter, ptdls_sta); ++ } ++ } ++} ++ ++void init_handshake_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta); ++} ++ ++//Check tdls peer sta alive. ++void _tdls_alive_timer_phase1_hdl(void *FunctionContext) ++{ ++ _irqL irqL; ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ptdls_sta->timer_flag = 1; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ++ ptdls_sta->tdls_sta_state &= (~TDLS_ALIVE_STATE); ++ ++ DBG_871X("issue_tdls_dis_req to check alive\n"); ++ issue_tdls_dis_req( padapter, ptdls_sta->hwaddr); ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH1); ++ sta_update_last_rx_pkts(ptdls_sta); ++ ++ if ( ptdls_sta->timer_flag == 2 ) ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA); ++ else ++ { ++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ptdls_sta->timer_flag = 0; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ } ++ ++} ++ ++void _tdls_alive_timer_phase2_hdl(void *FunctionContext) ++{ ++ _irqL irqL; ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 1; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ++ if( (ptdls_sta->tdls_sta_state & TDLS_ALIVE_STATE) && ++ (sta_last_rx_pkts(ptdls_sta) + 3 <= sta_rx_pkts(ptdls_sta)) ) ++ { ++ DBG_871X("TDLS STA ALIVE, ptdls_sta->sta_stats.last_rx_pkts:%llu, ptdls_sta->sta_stats.rx_pkts:%llu\n", ++ sta_last_rx_pkts(ptdls_sta), sta_rx_pkts(ptdls_sta)); ++ ++ ptdls_sta->alive_count = 0; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2); ++ } ++ else ++ { ++ if( !(ptdls_sta->tdls_sta_state & TDLS_ALIVE_STATE) ) ++ DBG_871X("TDLS STA TOO FAR\n"); ++ if( !(sta_last_rx_pkts(ptdls_sta) + 3 <= sta_rx_pkts(ptdls_sta))) ++ DBG_871X("TDLS LINK WITH LOW TRAFFIC, ptdls_sta->sta_stats.last_rx_pkts:%llu, ptdls_sta->sta_stats.rx_pkts:%llu\n", ++ sta_last_rx_pkts(ptdls_sta), sta_rx_pkts(ptdls_sta)); ++ ++ ptdls_sta->alive_count++; ++ if( ptdls_sta->alive_count == TDLS_ALIVE_COUNT ) ++ { ++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_TOOFAR_; ++ issue_tdls_teardown(padapter, ptdls_sta->hwaddr); ++ } ++ else ++ { ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2); ++ } ++ } ++ ++ if ( ptdls_sta->timer_flag == 2 ) ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA); ++ else ++ { ++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 0; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++} ++ ++} ++ ++void init_tdls_alive_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->alive_timer1, padapter->pnetdev, _tdls_alive_timer_phase1_hdl, psta); ++ _init_timer(&psta->alive_timer2, padapter->pnetdev, _tdls_alive_timer_phase2_hdl, psta); ++} ++ ++int update_sgi_tdls(_adapter *padapter, struct sta_info *psta) ++{ ++ struct ht_priv *psta_ht = NULL; ++ psta_ht = &psta->htpriv; ++ ++ if(psta_ht->ht_option) ++ { ++ return psta_ht->sgi; ++ } ++ else ++ return _FALSE; ++} ++ ++u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta) ++{ ++ int i; ++ u8 rf_type, id; ++ unsigned char sta_band = 0; ++ unsigned char limit; ++ unsigned int tx_ra_bitmap=0; ++ struct ht_priv *psta_ht = NULL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ ++ psta_ht = &psta->htpriv; ++ //b/g mode ra_bitmap ++ for (i=0; ibssrateset); i++) ++ { ++ if (psta->bssrateset[i]) ++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); ++ } ++ ++ //n mode ra_bitmap ++ if(psta_ht->ht_option) ++ { ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if(rf_type == RF_2T2R) ++ limit=16;// 2R ++ else ++ limit=8;// 1R ++ ++ for (i=0; iht_cap.supp_mcs_set[i/8] & BIT(i%8)) ++ tx_ra_bitmap |= BIT(i+12); ++ } ++ } ++ ++ if ( pcur_network->Configuration.DSConfig > 14 ) { ++ // 5G band ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_5N | WIRELESS_11A; ++ else ++ sta_band |= WIRELESS_11A; ++ } else { ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B; ++ else if (tx_ra_bitmap & 0xff0) ++ sta_band |= WIRELESS_11G |WIRELESS_11B; ++ else ++ sta_band |= WIRELESS_11B; ++ } ++ ++ id = networktype_to_raid(sta_band); ++ tx_ra_bitmap |= ((id<<28)&0xf0000000); ++ return tx_ra_bitmap; ++} ++ ++#endif //CONFIG_TDLS ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi.c +new file mode 100644 +index 00000000..6c6268c0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi.c +@@ -0,0 +1,1326 @@ ++#ifdef CONFIG_WAPI_SUPPORT ++ ++#include ++#include ++#include ++#include ++ ++ ++u32 wapi_debug_component = ++// WAPI_INIT | ++// WAPI_API | ++// WAPI_TX | ++// WAPI_RX | ++ WAPI_ERR ; //always open err flags on ++ ++void WapiFreeAllStaInfo(_adapter *padapter) ++{ ++ PRT_WAPI_T pWapiInfo; ++ PRT_WAPI_STA_INFO pWapiStaInfo; ++ PRT_WAPI_BKID pWapiBkid; ++ ++ WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); ++ pWapiInfo = &padapter->wapiInfo; ++ ++ //Pust to Idle List ++ rtw_wapi_return_all_sta_info(padapter); ++ ++ //Sta Info List ++ while(!list_empty(&(pWapiInfo->wapiSTAIdleList))) ++ { ++ pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list); ++ list_del_init(&pWapiStaInfo->list); ++ } ++ ++ //BKID List ++ while(!list_empty(&(pWapiInfo->wapiBKIDIdleList))) ++ { ++ pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list); ++ list_del_init(&pWapiBkid->list); ++ } ++ WAPI_TRACE(WAPI_INIT, "<=========== %s\n", __FUNCTION__); ++ return; ++} ++ ++void WapiSetIE(_adapter *padapter) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ //PRT_WAPI_BKID pWapiBkid; ++ u16 protocolVer = 1; ++ u16 akmCnt = 1; ++ u16 suiteCnt = 1; ++ u16 capability = 0; ++ u8 OUI[3]; ++ ++ OUI[0] = 0x00; ++ OUI[1] = 0x14; ++ OUI[2] = 0x72; ++ ++ pWapiInfo->wapiIELength = 0; ++//protocol version ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &protocolVer, 2); ++ pWapiInfo->wapiIELength +=2; ++//akm ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &akmCnt, 2); ++ pWapiInfo->wapiIELength +=2; ++ ++ if(pWapiInfo->bWapiPSK){ ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); ++ pWapiInfo->wapiIELength +=3; ++ pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2; ++ pWapiInfo->wapiIELength +=1; ++ }else{ ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); ++ pWapiInfo->wapiIELength +=3; ++ pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; ++ pWapiInfo->wapiIELength +=1; ++ } ++ ++//usk ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &suiteCnt, 2); ++ pWapiInfo->wapiIELength +=2; ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); ++ pWapiInfo->wapiIELength +=3; ++ pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; ++ pWapiInfo->wapiIELength +=1; ++ ++//msk ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); ++ pWapiInfo->wapiIELength +=3; ++ pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; ++ pWapiInfo->wapiIELength +=1; ++ ++//Capbility ++ memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &capability, 2); ++ pWapiInfo->wapiIELength +=2; ++} ++ ++ ++/* PN1 > PN2, return 1, ++ * else return 0. ++ */ ++u32 WapiComparePN(u8 *PN1, u8 *PN2) ++{ ++ char i; ++ ++ if ((NULL == PN1) || (NULL == PN2)) ++ return 1; ++ ++ // overflow case ++ if ((PN2[15] - PN1[15]) & 0x80) ++ return 1; ++ ++ for (i=16; i>0; i--) ++ { ++ if(PN1[i-1] == PN2[i-1]) ++ continue; ++ else if(PN1[i-1] > PN2[i-1]) ++ return 1; ++ else ++ return 0; ++ } ++ ++ return 0; ++} ++ ++u8 ++WapiGetEntryForCamWrite(_adapter *padapter,u8 *pMacAddr,u8 KID,BOOLEAN IsMsk) ++{ ++ PRT_WAPI_T pWapiInfo=NULL; ++ //PRT_WAPI_CAM_ENTRY pEntry=NULL; ++ u8 i=0; ++ u8 ret = 0xff; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ pWapiInfo = &padapter->wapiInfo; ++ ++ //exist? ++ for(i=0;iwapiCamEntry[i].IsUsed ++ && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE) ++ && pWapiInfo->wapiCamEntry[i].keyidx == KID ++ && pWapiInfo->wapiCamEntry[i].type == IsMsk) ++ { ++ ret = pWapiInfo->wapiCamEntry[i].entry_idx; //cover it ++ break; ++ } ++ } ++ ++ if(i == WAPI_CAM_ENTRY_NUM) //not found ++ { ++ for(i=0;iwapiCamEntry[i].IsUsed == 0) ++ { ++ pWapiInfo->wapiCamEntry[i].IsUsed = 1; ++ pWapiInfo->wapiCamEntry[i].type = IsMsk; ++ pWapiInfo->wapiCamEntry[i].keyidx = KID; ++ _rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr,ETH_ALEN); ++ ret = pWapiInfo->wapiCamEntry[i].entry_idx; ++ break; ++ } ++ } ++ } ++ ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++ return ret; ++ ++/* ++ if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)){ ++ RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); ++ return 0; ++ } ++ ++ pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList); ++ RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list); ++ ++ RT_TRACE(COMP_SEC,DBG_LOUD,("<====WapiGetCamEntry(),Get Entry Idx:%d.but we just return 4 for test\n",pEntry->entry_idx)); ++ ++ return pEntry->entry_idx;*/ ++} ++ ++u8 WapiGetEntryForCamClear(_adapter *padapter,u8 *pPeerMac,u8 keyid,u8 IsMsk) ++{ ++ PRT_WAPI_T pWapiInfo=NULL; ++ u8 i=0; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ pWapiInfo = &padapter->wapiInfo; ++ ++ for(i=0;iwapiCamEntry[i].IsUsed ++ && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE) ++ && pWapiInfo->wapiCamEntry[i].keyidx == keyid ++ && pWapiInfo->wapiCamEntry[i].type == IsMsk) ++ { ++ pWapiInfo->wapiCamEntry[i].IsUsed = 0; ++ pWapiInfo->wapiCamEntry[i].keyidx = 2; ++ _rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr,0,ETH_ALEN); ++ ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++ return pWapiInfo->wapiCamEntry[i].entry_idx; ++ } ++ } ++ ++ WAPI_TRACE(WAPI_API,"<====WapiGetReturnCamEntry(), No this cam entry.\n"); ++ return 0xff; ++/* ++ if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)){ ++ RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); ++ return FALSE; ++ } ++ ++ pList = &pWapiInfo->wapiCamUsedList; ++ while(pList->Flink != &pWapiInfo->wapiCamUsedList) ++ { ++ pEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink; ++ if(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0 ++ && keyid == pEntry->keyidx) ++ { ++ RTRemoveEntryList(pList); ++ RTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList); ++ return pEntry->entry_idx; ++ } ++ pList = pList->Flink; ++ } ++ ++ return 0; ++*/ ++} ++ ++void ++WapiResetAllCamEntry(_adapter *padapter) ++{ ++ PRT_WAPI_T pWapiInfo; ++ int i; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ pWapiInfo = &padapter->wapiInfo; ++ ++ for (i=0;iwapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN); ++ pWapiInfo->wapiCamEntry[i].IsUsed = 0; ++ pWapiInfo->wapiCamEntry[i].keyidx = 2; //invalid ++ pWapiInfo->wapiCamEntry[i].entry_idx = 4+i*2; ++ } ++ ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++ ++ return; ++} ++ ++u8 WapiWriteOneCamEntry( ++ _adapter *padapter, ++ u8 *pMacAddr, ++ u8 KeyId, ++ u8 EntryId, ++ u8 EncAlg, ++ u8 bGroupKey, ++ u8 *pKey ++) ++{ ++ u8 retVal = 0; ++ u16 usConfig = 0; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ if(EntryId >= 32) ++ { ++ WAPI_TRACE(WAPI_ERR, "<=== CamAddOneEntry(): ulKeyId exceed!\n"); ++ return retVal; ++ } ++ ++ usConfig=usConfig|(0x01<<15)|((u16)(EncAlg)<<2)|(KeyId); ++ ++ if(EncAlg == _SMS4_ ) ++ { ++ if(bGroupKey == 1) ++ usConfig |= (0x01<<6); ++ if((EntryId % 2)==1) // ==0 sec key; == 1mic key ++ usConfig |= (0x01<<5); ++ } ++ ++ write_cam(padapter, EntryId, usConfig, pMacAddr, pKey); ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ return 1; ++} ++ ++void rtw_wapi_init(_adapter *padapter) ++{ ++ PRT_WAPI_T pWapiInfo; ++ int i; ++ ++ WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); ++ RT_ASSERT_RET(padapter); ++ ++ if (!padapter->WapiSupport) ++ { ++ WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ pWapiInfo = &padapter->wapiInfo; ++ pWapiInfo->bWapiEnable = false; ++ ++ //Init BKID List ++ INIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList); ++ INIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList); ++ for(i=0;iwapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList); ++ } ++ ++ //Init STA List ++ INIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList); ++ INIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList); ++ for(i=0;iwapiSta[i].list, &pWapiInfo->wapiSTAIdleList); ++ } ++ ++ for (i=0;iwapiCamEntry[i].IsUsed = 0; ++ pWapiInfo->wapiCamEntry[i].keyidx = 2; //invalid ++ pWapiInfo->wapiCamEntry[i].entry_idx = 4+i*2; ++ } ++ ++ WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_free(_adapter *padapter) ++{ ++ WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); ++ RT_ASSERT_RET(padapter); ++ ++ if (!padapter->WapiSupport) ++ { ++ WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ WapiFreeAllStaInfo(padapter); ++ ++ WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_disable_tx(_adapter *padapter) ++{ ++ WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); ++ RT_ASSERT_RET(padapter); ++ ++ if (!padapter->WapiSupport) ++ { ++ WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ padapter->wapiInfo.wapiTxMsk.bTxEnable = false; ++ padapter->wapiInfo.wapiTxMsk.bSet = false; ++ ++ WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); ++} ++ ++u8 rtw_wapi_is_wai_packet(_adapter* padapter,u8 *pkt_data) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ u8 WaiPkt = 0, *pTaddr, bFind = false; ++ u8 Offset_TypeWAI = 0 ; // (mac header len + llc length) ++ ++ WAPI_TRACE(WAPI_TX|WAPI_RX, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ Offset_TypeWAI = 24 + 6 ; ++ ++ //YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. ++ if ((pkt_data[1]&0x40) !=0) ++ { ++ DBG_871X("data is privacy \n"); ++ return 0; ++ } ++ ++ pTaddr = GetAddr2Ptr(pkt_data); ++ if(list_empty(&pWapiInfo->wapiSTAUsedList)){ ++ bFind = false; ++ }else{ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ ++ if (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) { ++ bFind = true; ++ break; ++ } ++ } ++ } ++ ++ WAPI_TRACE(WAPI_TX|WAPI_RX, "%s: bFind=%d pTaddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(pTaddr)); ++ ++ if (pkt_data[0] == WIFI_QOS_DATA_TYPE) ++ { ++ Offset_TypeWAI += 2; ++ } ++ ++ // 88b4? ++ if( (pkt_data[Offset_TypeWAI]==0x88) && (pkt_data[Offset_TypeWAI+1]==0xb4) ){ ++ WaiPkt = pkt_data[Offset_TypeWAI+5]; ++ ++ psecuritypriv->hw_decrypted = _TRUE; ++ }else{ ++ WAPI_TRACE(WAPI_TX|WAPI_RX, "%s(): non wai packet\n",__FUNCTION__); ++ } ++ ++ WAPI_TRACE(WAPI_TX|WAPI_RX, "%s(): Recvd WAI frame. IsWAIPkt(%d)\n",__FUNCTION__, WaiPkt); ++ ++ return WaiPkt; ++} ++ ++ ++void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ struct recv_frame_hdr *precv_hdr; ++ u8 *ptr; ++ u8 *pTA; ++ u8 *pRecvPN; ++ ++ ++ WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ precv_hdr = &precv_frame->u.hdr; ++ ptr = precv_hdr->rx_data; ++ ++ if (precv_hdr->attrib.qos == 1) ++ { ++ precv_hdr->UserPriority = GetTid(ptr); ++ } ++ else ++ { ++ precv_hdr->UserPriority = 0; ++ } ++ ++ pTA = GetAddr2Ptr(ptr); ++ _rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6); ++ pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2; ++ _rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16); ++ ++ WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__); ++} ++ ++/**************************************************************************** ++TRUE-----------------Drop ++FALSE---------------- handle ++add to support WAPI to N-mode ++*****************************************************************************/ ++u8 rtw_wapi_check_for_drop( ++ _adapter *padapter, ++ union recv_frame *precv_frame ++) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ u8 *pLastRecvPN = NULL; ++ u8 bFind = false; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ u8 bDrop = false; ++ struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr; ++ u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ int i; ++ ++ WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return false; ++ } ++ ++ if(precv_hdr->bIsWaiPacket !=0) ++ { ++ if(precv_hdr->bIsWaiPacket== 0x8) ++ { ++ ++ DBG_871X("rtw_wapi_check_for_drop: dump packet \n"); ++ for(i=0;i<50;i++) ++ { ++ DBG_871X("%02X ",ptr[i]); ++ if((i+1) %8 ==0) ++ DBG_871X("\n"); ++ } ++ DBG_871X("\n rtw_wapi_check_for_drop: dump packet \n"); ++ ++ for(i=0;i<16;i++) ++ { ++ if(ptr[i+27] !=0) ++ break; ++ } ++ ++ if(i== 16) ++ { ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: drop with zero BKID \n"); ++ return true; ++ } ++ else ++ { ++ return false; ++ } ++ } ++ else ++ return false; ++ } ++ ++ if(list_empty(&pWapiInfo->wapiSTAUsedList)){ ++ bFind = false; ++ }else{ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) { ++ bFind = true; ++ break; ++ } ++ } ++ } ++ WAPI_TRACE(WAPI_RX, "%s: bFind=%d prxb->WapiSrcAddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr)); ++ ++ if(bFind) ++ { ++ if(IS_MCAST(precv_hdr->attrib.ra)) ++ { ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: multicast case \n"); ++ pLastRecvPN = pWapiSta->lastRxMulticastPN; ++ } ++ else ++ { ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: unicast case \n"); ++ switch(precv_hdr->UserPriority) ++ { ++ case 0: ++ case 3: ++ pLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue; ++ break; ++ case 1: ++ case 2: ++ pLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue; ++ break; ++ case 4: ++ case 5: ++ pLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue; ++ break; ++ case 6: ++ case 7: ++ pLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue; ++ break; ++ default: ++ WAPI_TRACE(WAPI_ERR,"%s: Unknown TID \n",__FUNCTION__); ++ break; ++ } ++ } ++ ++ if(!WapiComparePN(precv_hdr->WapiTempPN,pLastRecvPN)) ++ { ++ WAPI_TRACE(WAPI_RX,"%s: Equal PN!!\n",__FUNCTION__); ++ if(IS_MCAST(precv_hdr->attrib.ra)) ++ _rtw_memcpy(pLastRecvPN,WapiAEMultiCastPNInitialValueSrc,16); ++ else ++ _rtw_memcpy(pLastRecvPN,WapiAEPNInitialValueSrc,16); ++ bDrop = true; ++ } ++ else ++ { ++ _rtw_memcpy(pLastRecvPN,precv_hdr->WapiTempPN,16); ++ } ++ } ++ ++ WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__); ++ return bDrop; ++} ++ ++void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ u8 WapiIELength = 0; ++ ++ WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ WapiSetIE(padapter); ++ WapiIELength = pWapiInfo->wapiIELength; ++ pframe[0] = _WAPI_IE_; ++ pframe[1] = WapiIELength; ++ _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); ++ pframe += WapiIELength+2; ++ pattrib->pktlen += WapiIELength+2; ++ ++ WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ u8 WapiIELength = 0; ++ WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ WapiSetIE(padapter); ++ WapiIELength = pWapiInfo->wapiIELength; ++ pframe[0] = _WAPI_IE_; ++ pframe[1] = WapiIELength; ++ _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); ++ pframe += WapiIELength+2; ++ pattrib->pktlen += WapiIELength+2; ++ ++ WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) ++{ ++ PRT_WAPI_BKID pWapiBKID; ++ u16 bkidNum; ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ u8 WapiIELength = 0; ++ ++ WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); ++ return; ++ } ++ ++ WapiSetIE(padapter); ++ WapiIELength = pWapiInfo->wapiIELength; ++ bkidNum = 0; ++ if(!list_empty(&(pWapiInfo->wapiBKIDStoreList))){ ++ list_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) { ++ bkidNum ++; ++ _rtw_memcpy(pWapiInfo->wapiIE+WapiIELength+2, pWapiBKID->bkid,16); ++ WapiIELength += 16; ++ } ++ } ++ _rtw_memcpy(pWapiInfo->wapiIE+WapiIELength, &bkidNum, 2); ++ WapiIELength += 2; ++ ++ pframe[0] = _WAPI_IE_; ++ pframe[1] = WapiIELength; ++ _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); ++ pframe += WapiIELength+2; ++ pattrib->pktlen += WapiIELength+2; ++ WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); ++ PRT_WAPI_STA_INFO pWapiSta; ++ u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ //u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ ++ WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ pWapiSta =(PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list); ++ list_del_init(&pWapiSta->list); ++ list_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList); ++ _rtw_memcpy(pWapiSta->PeerMacAddr,padapter->mlmeextpriv.mlmext_info.network.MacAddress,6); ++ _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); ++ ++ //For chenk PN error with Qos Data after s3: add by ylb 20111114 ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); ++ ++ WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); ++} ++ ++ ++void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr) ++{ ++ PRT_WAPI_T pWapiInfo; ++ PRT_WAPI_STA_INFO pWapiStaInfo = NULL; ++ PRT_WAPI_BKID pWapiBkid = NULL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ pWapiInfo = &padapter->wapiInfo; ++ ++ WAPI_TRACE(WAPI_API, "==========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ while(!list_empty(&(pWapiInfo->wapiBKIDStoreList))) ++ { ++ pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); ++ list_del_init(&pWapiBkid->list); ++ _rtw_memset(pWapiBkid->bkid,0,16); ++ list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList); ++ } ++ } ++ ++ ++ WAPI_TRACE(WAPI_API, " %s: after clear bkid \n", __FUNCTION__); ++ ++ ++ //Remove STA info ++ if(list_empty(&(pWapiInfo->wapiSTAUsedList))){ ++ WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is null \n", __FUNCTION__); ++ return; ++ }else{ ++ ++ WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is not null \n", __FUNCTION__); ++#if 0 ++ pWapiStaInfo=(PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next),RT_WAPI_STA_INFO,list); ++ ++ list_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) { ++ ++ DBG_871X("MAC Addr %02x-%02x-%02x-%02x-%02x-%02x \n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); ++ ++ ++ DBG_871X("peer Addr %02x-%02x-%02x-%02x-%02x-%02x \n",pWapiStaInfo->PeerMacAddr[0],pWapiStaInfo->PeerMacAddr[1],pWapiStaInfo->PeerMacAddr[2],pWapiStaInfo->PeerMacAddr[3],pWapiStaInfo->PeerMacAddr[4],pWapiStaInfo->PeerMacAddr[5]); ++ ++ if(pWapiStaInfo == NULL) ++ { ++ WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo == NULL Case \n", __FUNCTION__); ++ return; ++ } ++ ++ if(pWapiStaInfo->PeerMacAddr == NULL) ++ { ++ WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo->PeerMacAddr == NULL Case \n", __FUNCTION__); ++ return; ++ } ++ ++ if(MacAddr == NULL) ++ { ++ WAPI_TRACE(WAPI_API, " %s: MacAddr == NULL Case \n", __FUNCTION__); ++ return; ++ } ++ ++ if (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) { ++ pWapiStaInfo->bAuthenticateInProgress = false; ++ pWapiStaInfo->bSetkeyOk = false; ++ _rtw_memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); ++ list_del_init(&pWapiStaInfo->list); ++ list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); ++ break; ++ } ++ ++ } ++#endif ++ ++ while(!list_empty(&(pWapiInfo->wapiSTAUsedList))) ++ { ++ pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list); ++ ++ DBG_871X("peer Addr %02x-%02x-%02x-%02x-%02x-%02x \n",pWapiStaInfo->PeerMacAddr[0],pWapiStaInfo->PeerMacAddr[1],pWapiStaInfo->PeerMacAddr[2],pWapiStaInfo->PeerMacAddr[3],pWapiStaInfo->PeerMacAddr[4],pWapiStaInfo->PeerMacAddr[5]); ++ ++ list_del_init(&pWapiStaInfo->list); ++ memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); ++ pWapiStaInfo->bSetkeyOk = 0; ++ list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); ++ } ++ ++ } ++ ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++ return; ++} ++ ++void rtw_wapi_return_all_sta_info(_adapter *padapter) ++{ ++ PRT_WAPI_T pWapiInfo; ++ PRT_WAPI_STA_INFO pWapiStaInfo; ++ PRT_WAPI_BKID pWapiBkid; ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ pWapiInfo = &padapter->wapiInfo; ++ ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ //Sta Info List ++ while(!list_empty(&(pWapiInfo->wapiSTAUsedList))) ++ { ++ pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list); ++ list_del_init(&pWapiStaInfo->list); ++ memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); ++ pWapiStaInfo->bSetkeyOk = 0; ++ list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); ++ } ++ ++ //BKID List ++ while(!list_empty(&(pWapiInfo->wapiBKIDStoreList))) ++ { ++ pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); ++ list_del_init(&pWapiBkid->list); ++ memset(pWapiBkid->bkid,0,16); ++ list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList); ++ } ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr) ++{ ++ u8 UcIndex = 0; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0); ++ if(UcIndex != 0xff){ ++ //CAM_mark_invalid(Adapter, UcIndex); ++ CAM_empty_entry(padapter, UcIndex); ++ } ++ ++ UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0); ++ if(UcIndex != 0xff){ ++ //CAM_mark_invalid(Adapter, UcIndex); ++ CAM_empty_entry(padapter, UcIndex); ++ } ++ ++ UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1); ++ if(UcIndex != 0xff){ ++ //CAM_mark_invalid(Adapter, UcIndex); ++ CAM_empty_entry(padapter, UcIndex); ++ } ++ ++ UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1); ++ if(UcIndex != 0xff){ ++ //CAM_mark_invalid(padapter, UcIndex); ++ CAM_empty_entry(padapter, UcIndex); ++ } ++ ++ WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_clear_all_cam_entry(_adapter *padapter) ++{ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ invalidate_cam_all(padapter); // is this ok? ++ WapiResetAllCamEntry(padapter); ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++} ++ ++void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey) ++{ ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ u8 *pMacAddr = pWapiSta->PeerMacAddr; ++ u32 EntryId = 0; ++ BOOLEAN IsPairWise = false ; ++ u8 EncAlgo; ++ ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_API, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); ++ return; ++ } ++ ++ EncAlgo = _SMS4_; ++ ++ //For Tx bc/mc pkt,use defualt key entry ++ if(bUseDefaultKey) ++ { ++ // when WAPI update key, keyid will be 0 or 1 by turns. ++ if (pWapiKey->keyId == 0) ++ EntryId = 0; ++ else ++ EntryId = 2; ++ } ++ else ++ { ++ // tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr ++ EntryId = WapiGetEntryForCamWrite(padapter,pMacAddr,pWapiKey->keyId,bGroupKey); ++ } ++ ++ if(EntryId == 0xff){ ++ WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n"); ++ return; ++ } ++ ++ //EntryId is also used to diff Sec key and Mic key ++ //Sec Key ++ WapiWriteOneCamEntry(padapter, ++ pMacAddr, ++ pWapiKey->keyId, //keyid ++ EntryId, //entry ++ EncAlgo, //type ++ bGroupKey, //pairwise or group key ++ pWapiKey->dataKey); ++ //MIC key ++ WapiWriteOneCamEntry(padapter, ++ pMacAddr, ++ pWapiKey->keyId, //keyid ++ EntryId+1, //entry ++ EncAlgo, //type ++ bGroupKey, //pairwise or group key ++ pWapiKey->micKey); ++ ++ WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n",pWapiKey->keyId,EntryId,!bGroupKey); ++ WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); ++ ++} ++ ++#if 0 ++//YJ,test,091013 ++void wapi_test_set_key(struct _adapter *padapter, u8* buf) ++{ /*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/ ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ PRT_WAPI_BKID pWapiBkid; ++ PRT_WAPI_STA_INFO pWapiSta; ++ u8 data[43]; ++ bool bTxEnable; ++ bool bUpdate; ++ bool bAuthenticator; ++ u8 PeerAddr[6]; ++ u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ ++ WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__); ++ ++ if (!padapter->WapiSupport){ ++ return; ++ } ++ ++ copy_from_user(data, buf, 43); ++ bTxEnable = data[1]; ++ bAuthenticator = data[2]; ++ bUpdate = data[3]; ++ memcpy(PeerAddr,data+4,6); ++ ++ if(data[0] == 0x3){ ++ if(!list_empty(&(pWapiInfo->wapiBKIDIdleList))){ ++ pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list); ++ list_del_init(&pWapiBkid->list); ++ memcpy(pWapiBkid->bkid, data+10, 16); ++ WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16); ++ list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList); ++ } ++ }else{ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(!memcmp(pWapiSta->PeerMacAddr,PeerAddr,6)){ ++ pWapiSta->bAuthenticatorInUpdata = false; ++ switch(data[0]){ ++ case 1: //usk ++ if(bAuthenticator){ //authenticator ++ memcpy(pWapiSta->lastTxUnicastPN,WapiAEPNInitialValueSrc,16); ++ if(!bUpdate) { //first ++ WAPI_TRACE(WAPI_INIT,"AE fisrt set usk \n"); ++ pWapiSta->wapiUsk.bSet = true; ++ memcpy(pWapiSta->wapiUsk.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiUsk.micKey,data+26,16); ++ pWapiSta->wapiUsk.keyId = *(data+42); ++ pWapiSta->wapiUsk.bTxEnable = true; ++ WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16); ++ WAPI_DATA(WAPI_INIT, "SetKey - AE USK Mic Key", pWapiSta->wapiUsk.micKey, 16); ++ } ++ else //update ++ { ++ WAPI_TRACE(WAPI_INIT, "AE update usk \n"); ++ pWapiSta->wapiUskUpdate.bSet = true; ++ pWapiSta->bAuthenticatorInUpdata = true; ++ memcpy(pWapiSta->wapiUskUpdate.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiUskUpdate.micKey,data+26,16); ++ memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ pWapiSta->wapiUskUpdate.keyId = *(data+42); ++ pWapiSta->wapiUskUpdate.bTxEnable = true; ++ } ++ } ++ else{ ++ if(!bUpdate){ ++ WAPI_TRACE(WAPI_INIT,"ASUE fisrt set usk \n"); ++ if(bTxEnable){ ++ pWapiSta->wapiUsk.bTxEnable = true; ++ memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ }else{ ++ pWapiSta->wapiUsk.bSet = true; ++ memcpy(pWapiSta->wapiUsk.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiUsk.micKey,data+26,16); ++ pWapiSta->wapiUsk.keyId = *(data+42); ++ pWapiSta->wapiUsk.bTxEnable = false; ++ } ++ }else{ ++ WAPI_TRACE(WAPI_INIT,"ASUE update usk \n"); ++ if(bTxEnable){ ++ pWapiSta->wapiUskUpdate.bTxEnable = true; ++ if(pWapiSta->wapiUskUpdate.bSet){ ++ memcpy(pWapiSta->wapiUsk.dataKey,pWapiSta->wapiUskUpdate.dataKey,16); ++ memcpy(pWapiSta->wapiUsk.micKey,pWapiSta->wapiUskUpdate.micKey,16); ++ pWapiSta->wapiUsk.keyId=pWapiSta->wapiUskUpdate.keyId; ++ memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiASUEPNInitialValueSrc,16); ++ memcpy(pWapiSta->lastRxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ pWapiSta->wapiUskUpdate.bTxEnable = false; ++ pWapiSta->wapiUskUpdate.bSet = false; ++ } ++ memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ }else{ ++ pWapiSta->wapiUskUpdate.bSet = true; ++ memcpy(pWapiSta->wapiUskUpdate.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiUskUpdate.micKey,data+26,16); ++ pWapiSta->wapiUskUpdate.keyId = *(data+42); ++ pWapiSta->wapiUskUpdate.bTxEnable = false; ++ } ++ } ++ } ++ break; ++ case 2: //msk ++ if(bAuthenticator){ //authenticator ++ pWapiInfo->wapiTxMsk.bSet = true; ++ memcpy(pWapiInfo->wapiTxMsk.dataKey,data+10,16); ++ memcpy(pWapiInfo->wapiTxMsk.micKey,data+26,16); ++ pWapiInfo->wapiTxMsk.keyId = *(data+42); ++ pWapiInfo->wapiTxMsk.bTxEnable = true; ++ memcpy(pWapiInfo->lastTxMulticastPN,WapiAEMultiCastPNInitialValueSrc,16); ++ ++ if(!bUpdate){ //first ++ WAPI_TRACE(WAPI_INIT, "AE fisrt set msk \n"); ++ if(!pWapiSta->bSetkeyOk) ++ pWapiSta->bSetkeyOk = true; ++ pWapiInfo->bFirstAuthentiateInProgress= false; ++ }else{ //update ++ WAPI_TRACE(WAPI_INIT,"AE update msk \n"); ++ } ++ ++ WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Data Key", pWapiInfo->wapiTxMsk.dataKey, 16); ++ WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Mic Key", pWapiInfo->wapiTxMsk.micKey, 16); ++ } ++ else{ ++ if(!bUpdate){ ++ WAPI_TRACE(WAPI_INIT,"ASUE fisrt set msk \n"); ++ pWapiSta->wapiMsk.bSet = true; ++ memcpy(pWapiSta->wapiMsk.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiMsk.micKey,data+26,16); ++ pWapiSta->wapiMsk.keyId = *(data+42); ++ pWapiSta->wapiMsk.bTxEnable = false; ++ if(!pWapiSta->bSetkeyOk) ++ pWapiSta->bSetkeyOk = true; ++ pWapiInfo->bFirstAuthentiateInProgress= false; ++ WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Data Key", pWapiSta->wapiMsk.dataKey, 16); ++ WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Mic Key", pWapiSta->wapiMsk.micKey, 16); ++ }else{ ++ WAPI_TRACE(WAPI_INIT,"ASUE update msk \n"); ++ pWapiSta->wapiMskUpdate.bSet = true; ++ memcpy(pWapiSta->wapiMskUpdate.dataKey,data+10,16); ++ memcpy(pWapiSta->wapiMskUpdate.micKey,data+26,16); ++ pWapiSta->wapiMskUpdate.keyId = *(data+42); ++ pWapiSta->wapiMskUpdate.bTxEnable = false; ++ } ++ } ++ break; ++ default: ++ WAPI_TRACE(WAPI_ERR,"Unknown Flag \n"); ++ break; ++ } ++ } ++ } ++ } ++ WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__); ++} ++ ++ ++void wapi_test_init(struct _adapter *padapter) ++{ ++ u8 keybuf[100]; ++ u8 mac_addr[6]={0x00,0xe0,0x4c,0x72,0x04,0x70}; ++ u8 UskDataKey[16]={0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f}; ++ u8 UskMicKey[16]={0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f}; ++ u8 UskId = 0; ++ u8 MskDataKey[16]={0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f}; ++ u8 MskMicKey[16]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f}; ++ u8 MskId = 0; ++ ++ WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__); ++ ++ //Enable Wapi ++ WAPI_TRACE(WAPI_INIT, "%s: Enable wapi!!!!\n", __FUNCTION__); ++ padapter->wapiInfo.bWapiEnable = true; ++ padapter->pairwise_key_type = KEY_TYPE_SMS4; ++ ieee->group_key_type = KEY_TYPE_SMS4; ++ padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; ++ padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; ++ ++ //set usk ++ WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__); ++ memset(keybuf,0,100); ++ keybuf[0] = 1; //set usk ++ keybuf[1] = 1; //enable tx ++ keybuf[2] = 1; //AE ++ keybuf[3] = 0; //not update ++ ++ memcpy(keybuf+4,mac_addr,6); ++ memcpy(keybuf+10,UskDataKey,16); ++ memcpy(keybuf+26,UskMicKey,16); ++ keybuf[42]=UskId; ++ wapi_test_set_key(padapter, keybuf); ++ ++ memset(keybuf,0,100); ++ keybuf[0] = 1; //set usk ++ keybuf[1] = 1; //enable tx ++ keybuf[2] = 0; //AE ++ keybuf[3] = 0; //not update ++ ++ memcpy(keybuf+4,mac_addr,6); ++ memcpy(keybuf+10,UskDataKey,16); ++ memcpy(keybuf+26,UskMicKey,16); ++ keybuf[42]=UskId; ++ wapi_test_set_key(padapter, keybuf); ++ ++ //set msk ++ WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__); ++ memset(keybuf,0,100); ++ keybuf[0] = 2; //set msk ++ keybuf[1] = 1; //Enable TX ++ keybuf[2] = 1; //AE ++ keybuf[3] = 0; //not update ++ memcpy(keybuf+4,mac_addr,6); ++ memcpy(keybuf+10,MskDataKey,16); ++ memcpy(keybuf+26,MskMicKey,16); ++ keybuf[42] = MskId; ++ wapi_test_set_key(padapter, keybuf); ++ ++ memset(keybuf,0,100); ++ keybuf[0] = 2; //set msk ++ keybuf[1] = 1; //Enable TX ++ keybuf[2] = 0; //AE ++ keybuf[3] = 0; //not update ++ memcpy(keybuf+4,mac_addr,6); ++ memcpy(keybuf+10,MskDataKey,16); ++ memcpy(keybuf+26,MskMicKey,16); ++ keybuf[42] = MskId; ++ wapi_test_set_key(padapter, keybuf); ++ WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__); ++} ++#endif ++ ++void rtw_wapi_get_iv(_adapter *padapter,u8 *pRA, u8*IV) ++{ ++ PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL; ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ bool bPNOverflow = false; ++ bool bFindMatchPeer = false; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ ++ pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV; ++ ++ WAPI_DATA(WAPI_RX,"wapi_get_iv: pra",pRA,6); ++ ++ if(IS_MCAST(pRA)){ ++ if(!pWapiInfo->wapiTxMsk.bTxEnable){ ++ WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); ++ return; ++ } ++ ++ if(pWapiInfo->wapiTxMsk.keyId <= 1){ ++ pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; ++ pWapiExt->Reserved = 0; ++ bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); ++ memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); ++ } ++ } ++ else ++ { ++ if(list_empty(&pWapiInfo->wapiSTAUsedList)){ ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_get_iv: list is empty \n"); ++ _rtw_memset(IV,10,18); ++ return; ++ } ++ else{ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ ++ WAPI_DATA(WAPI_RX,"rtw_wapi_get_iv: peermacaddr ",pWapiSta->PeerMacAddr,6); ++ if (_rtw_memcmp((u8*)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) { ++ bFindMatchPeer = true; ++ break; ++ } ++ } ++ ++ WAPI_TRACE(WAPI_RX,"bFindMatchPeer: %d \n",bFindMatchPeer); ++ WAPI_DATA(WAPI_RX,"Addr",pRA,6); ++ ++ if (bFindMatchPeer){ ++ if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) ++ return; ++ ++ if (pWapiSta->wapiUsk.keyId <= 1){ ++ if(pWapiSta->wapiUskUpdate.bTxEnable) ++ pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId; ++ else ++ pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId; ++ ++ pWapiExt->Reserved = 0; ++ bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2); ++ _rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); ++ ++ } ++ } ++ } ++ ++ } ++ ++} ++ ++bool rtw_wapi_drop_for_key_absent(_adapter *padapter,u8 *pRA) ++{ ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ bool bFindMatchPeer = false; ++ bool bDrop = false; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ WAPI_DATA(WAPI_RX,"rtw_wapi_drop_for_key_absent: ra ",pRA,6); ++ ++ if(psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) ++ { ++ if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) ++ return true; ++ ++ if(IS_MCAST(pRA)){ ++ if(!pWapiInfo->wapiTxMsk.bTxEnable){ ++ bDrop = true; ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: multicast key is absent \n"); ++ return bDrop; ++ } ++ } ++ else{ ++ if(!list_empty(&pWapiInfo->wapiSTAUsedList)){ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ ++ WAPI_DATA(WAPI_RX,"rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr ",pWapiSta->PeerMacAddr,6); ++ if (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE){ ++ bFindMatchPeer = true; ++ break; ++ } ++ } ++ if (bFindMatchPeer) { ++ if (!pWapiSta->wapiUsk.bTxEnable){ ++ bDrop = true; ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: unicast key is absent \n"); ++ return bDrop; ++ } ++ } ++ else{ ++ bDrop = true; ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: no peer find \n"); ++ return bDrop; ++ } ++ ++ } ++ else{ ++ bDrop = true; ++ WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: no sta exist \n"); ++ return bDrop; ++ } ++ } ++ } ++ else ++ { ++ return bDrop; ++ } ++ ++ return bDrop; ++} ++ ++#endif +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi_sms4.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi_sms4.c +new file mode 100644 +index 00000000..6126ed9a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wapi_sms4.c +@@ -0,0 +1,923 @@ ++#ifdef CONFIG_WAPI_SUPPORT ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CONFIG_WAPI_SW_SMS4 ++ ++#define WAPI_LITTLE_ENDIAN ++//#define BIG_ENDIAN ++#define ENCRYPT 0 ++#define DECRYPT 1 ++ ++ ++/********************************************************** ++ **********************************************************/ ++const u8 Sbox[256] = { ++0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05, ++0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99, ++0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62, ++0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x94,0xfa,0x75,0x8f,0x3f,0xa6, ++0x47,0x07,0xa7,0xfc,0xf3,0x73,0x17,0xba,0x83,0x59,0x3c,0x19,0xe6,0x85,0x4f,0xa8, ++0x68,0x6b,0x81,0xb2,0x71,0x64,0xda,0x8b,0xf8,0xeb,0x0f,0x4b,0x70,0x56,0x9d,0x35, ++0x1e,0x24,0x0e,0x5e,0x63,0x58,0xd1,0xa2,0x25,0x22,0x7c,0x3b,0x01,0x21,0x78,0x87, ++0xd4,0x00,0x46,0x57,0x9f,0xd3,0x27,0x52,0x4c,0x36,0x02,0xe7,0xa0,0xc4,0xc8,0x9e, ++0xea,0xbf,0x8a,0xd2,0x40,0xc7,0x38,0xb5,0xa3,0xf7,0xf2,0xce,0xf9,0x61,0x15,0xa1, ++0xe0,0xae,0x5d,0xa4,0x9b,0x34,0x1a,0x55,0xad,0x93,0x32,0x30,0xf5,0x8c,0xb1,0xe3, ++0x1d,0xf6,0xe2,0x2e,0x82,0x66,0xca,0x60,0xc0,0x29,0x23,0xab,0x0d,0x53,0x4e,0x6f, ++0xd5,0xdb,0x37,0x45,0xde,0xfd,0x8e,0x2f,0x03,0xff,0x6a,0x72,0x6d,0x6c,0x5b,0x51, ++0x8d,0x1b,0xaf,0x92,0xbb,0xdd,0xbc,0x7f,0x11,0xd9,0x5c,0x41,0x1f,0x10,0x5a,0xd8, ++0x0a,0xc1,0x31,0x88,0xa5,0xcd,0x7b,0xbd,0x2d,0x74,0xd0,0x12,0xb8,0xe5,0xb4,0xb0, ++0x89,0x69,0x97,0x4a,0x0c,0x96,0x77,0x7e,0x65,0xb9,0xf1,0x09,0xc5,0x6e,0xc6,0x84, ++0x18,0xf0,0x7d,0xec,0x3a,0xdc,0x4d,0x20,0x79,0xee,0x5f,0x3e,0xd7,0xcb,0x39,0x48 ++}; ++ ++const u32 CK[32] = { ++ 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, ++ 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, ++ 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, ++ 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, ++ 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, ++ 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, ++ 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, ++ 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 }; ++ ++#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y)))) ++ ++#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \ ++ Sbox[(_A) >> 16 & 0xFF] << 16 | \ ++ Sbox[(_A) >> 8 & 0xFF] << 8 | \ ++ Sbox[(_A) & 0xFF]) ++ ++#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24)) ++#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23)) ++ ++static void ++xor_block(void *dst, void *src1, void *src2) ++/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */ ++{ ++ ((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0]; ++ ((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1]; ++ ((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2]; ++ ((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3]; ++} ++ ++ ++void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk) ++{ ++ u32 r, mid, x0, x1, x2, x3, *p; ++ p = (u32 *)Input; ++ x0 = p[0]; ++ x1 = p[1]; ++ x2 = p[2]; ++ x3 = p[3]; ++#ifdef WAPI_LITTLE_ENDIAN ++ x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); ++ x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); ++ x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); ++ x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); ++#endif ++ for (r = 0; r < 32; r += 4) ++ { ++ mid = x1 ^ x2 ^ x3 ^ rk[r + 0]; ++ mid = ByteSub(mid); ++ x0 ^= L1(mid); ++ mid = x2 ^ x3 ^ x0 ^ rk[r + 1]; ++ mid = ByteSub(mid); ++ x1 ^= L1(mid); ++ mid = x3 ^ x0 ^ x1 ^ rk[r + 2]; ++ mid = ByteSub(mid); ++ x2 ^= L1(mid); ++ mid = x0 ^ x1 ^ x2 ^ rk[r + 3]; ++ mid = ByteSub(mid); ++ x3 ^= L1(mid); ++ } ++#ifdef WAPI_LITTLE_ENDIAN ++ x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); ++ x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); ++ x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); ++ x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); ++#endif ++ p = (u32 *)Output; ++ p[0] = x3; ++ p[1] = x2; ++ p[2] = x1; ++ p[3] = x0; ++} ++ ++ ++ ++void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag) ++{ ++ u32 r, mid, x0, x1, x2, x3, *p; ++ ++ p = (u32 *)Key; ++ x0 = p[0]; ++ x1 = p[1]; ++ x2 = p[2]; ++ x3 = p[3]; ++#ifdef WAPI_LITTLE_ENDIAN ++ x0 = Rotl(x0, 16); x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); ++ x1 = Rotl(x1, 16); x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); ++ x2 = Rotl(x2, 16); x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); ++ x3 = Rotl(x3, 16); x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); ++#endif ++ ++ x0 ^= 0xa3b1bac6; ++ x1 ^= 0x56aa3350; ++ x2 ^= 0x677d9197; ++ x3 ^= 0xb27022dc; ++ for (r = 0; r < 32; r += 4) ++ { ++ mid = x1 ^ x2 ^ x3 ^ CK[r + 0]; ++ mid = ByteSub(mid); ++ rk[r + 0] = x0 ^= L2(mid); ++ mid = x2 ^ x3 ^ x0 ^ CK[r + 1]; ++ mid = ByteSub(mid); ++ rk[r + 1] = x1 ^= L2(mid); ++ mid = x3 ^ x0 ^ x1 ^ CK[r + 2]; ++ mid = ByteSub(mid); ++ rk[r + 2] = x2 ^= L2(mid); ++ mid = x0 ^ x1 ^ x2 ^ CK[r + 3]; ++ mid = ByteSub(mid); ++ rk[r + 3] = x3 ^= L2(mid); ++ } ++ if (CryptFlag == DECRYPT) ++ { ++ for (r = 0; r < 16; r++) ++ mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid; ++ } ++} ++ ++ ++void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength, ++ u8 *Output, u16 *OutputLength, u32 CryptFlag) ++{ ++ u32 blockNum,i,j, rk[32]; ++ u16 remainder; ++ u8 blockIn[16],blockOut[16], tempIV[16], k; ++ ++ *OutputLength = 0; ++ remainder = InputLength & 0x0F; ++ blockNum = InputLength >> 4; ++ if(remainder !=0) ++ blockNum++; ++ else ++ remainder = 16; ++ ++ for(k=0;k<16;k++) ++ tempIV[k] = IV[15-k]; ++ ++ memcpy(blockIn, tempIV, 16); ++ ++ SMS4KeyExt((u8 *)Key, rk,CryptFlag); ++ ++ for(i=0; i> 4; ++ ++ for(k=0;k<16;k++) ++ tempIV[k] = IV[15-k]; ++ ++ memcpy(BlockIn, tempIV, 16); ++ ++ SMS4KeyExt((u8 *)Key, rk, ENCRYPT); ++ ++ SMS4Crypt((u8 *)BlockIn, BlockOut, rk); ++ ++ for(i=0; i> 4; ++ ++ for(i=0; i%s\n", __FUNCTION__); ++ ++ header = (struct ieee80211_hdr_3addr_qos *)pHeader; ++ memset(TempBuf, 0, 34); ++ memcpy(TempBuf, pHeader, 2); //FrameCtrl ++ pTemp = (u16*)TempBuf; ++ *pTemp &= 0xc78f; //bit4,5,6,11,12,13 ++ ++ memcpy((TempBuf+2), (pHeader+4), 12); //Addr1, Addr2 ++ memcpy((TempBuf+14), (pHeader+22), 2); // SeqCtrl ++ pTemp = (u16*)(TempBuf + 14); ++ *pTemp &= 0x000f; ++ ++ memcpy((TempBuf+16), (pHeader+16), 6); //Addr3 ++ ++ fc = le16_to_cpu(header->frame_ctl); ++ ++ ++ ++ if (GetFrDs((u16*)&fc) && GetToDs((u16 *)&fc)) ++ { ++ memcpy((TempBuf+22), (pHeader+24), 6); ++ QosOffset = 30; ++ }else{ ++ memset((TempBuf+22), 0, 6); ++ QosOffset = 24; ++ } ++ ++ if((fc & 0x0088) == 0x0088){ ++ memcpy((TempBuf+28), (pHeader+QosOffset), 2); ++ TempLen += 2; ++ //IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; ++ IV = pHeader + QosOffset + 2 + 2; ++ }else{ ++ IV = pHeader + QosOffset + 2; ++ //IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; ++ } ++ ++ TempBuf[TempLen-1] = (u8)(DataLen & 0xff); ++ TempBuf[TempLen-2] = (u8)((DataLen & 0xff00)>>8); ++ TempBuf[TempLen-4] = KeyIdx; ++ ++ WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16); ++ WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16); ++ WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen); ++ WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen); ++ ++ WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen, ++ pData, DataLen, MicBuffer, &MicLen); ++ ++ if (MicLen != 16) ++ WAPI_TRACE(WAPI_ERR,"%s: MIC Length Error!!\n",__FUNCTION__); ++ ++ WAPI_TRACE(WAPI_TX|WAPI_RX, "<=========%s\n", __FUNCTION__); ++#endif ++} ++ ++/* AddCount: 1 or 2. ++ * If overflow, return 1, ++ * else return 0. ++ */ ++u8 WapiIncreasePN(u8 *PN, u8 AddCount) ++{ ++ u8 i; ++ ++ if (NULL == PN) ++ return 1; ++ //YJ,test,091102 ++ /* ++ if(AddCount == 2){ ++ DBG_8192C("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]); ++ if(PN[0] == 0x48){ ++ PN[0] += AddCount; ++ return 1; ++ }else{ ++ PN[0] += AddCount; ++ return 0; ++ } ++ } ++ */ ++ //YJ,test,091102,end ++ ++ for (i=0; i<16; i++) ++ { ++ if (PN[i] + AddCount <= 0xff) ++ { ++ PN[i] += AddCount; ++ return 0; ++ } ++ else ++ { ++ PN[i] += AddCount; ++ AddCount = 1; ++ } ++ } ++ return 1; ++} ++ ++ ++void WapiGetLastRxUnicastPNForQoSData( ++ u8 UserPriority, ++ PRT_WAPI_STA_INFO pWapiStaInfo, ++ u8 *PNOut ++) ++{ ++ WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); ++ switch(UserPriority) ++ { ++ case 0: ++ case 3: ++ memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBEQueue,16); ++ break; ++ case 1: ++ case 2: ++ memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBKQueue,16); ++ break; ++ case 4: ++ case 5: ++ memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVIQueue,16); ++ break; ++ case 6: ++ case 7: ++ memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVOQueue,16); ++ break; ++ default: ++ WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__); ++ break; ++ } ++ WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__); ++} ++ ++ ++void WapiSetLastRxUnicastPNForQoSData( ++ u8 UserPriority, ++ u8 *PNIn, ++ PRT_WAPI_STA_INFO pWapiStaInfo ++) ++{ ++ WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); ++ switch(UserPriority) ++ { ++ case 0: ++ case 3: ++ memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue,PNIn,16); ++ break; ++ case 1: ++ case 2: ++ memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue,PNIn,16); ++ break; ++ case 4: ++ case 5: ++ memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue,PNIn,16); ++ break; ++ case 6: ++ case 7: ++ memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue,PNIn,16); ++ break; ++ default: ++ WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__); ++ break; ++ } ++ WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__); ++} ++ ++ ++/**************************************************************************** ++ FALSE not RX-Reorder ++ TRUE do RX Reorder ++add to support WAPI to N-mode ++*****************************************************************************/ ++u8 WapiCheckPnInSwDecrypt( ++ _adapter *padapter, ++ struct sk_buff *pskb ++) ++{ ++ u8 ret = false; ++ ++#if 0 ++ struct ieee80211_hdr_3addr_qos *header; ++ u16 fc; ++ u8 *pDaddr, *pTaddr, *pRaddr; ++ ++ header = (struct ieee80211_hdr_3addr_qos *)pskb->data; ++ pTaddr = header->addr2; ++ pRaddr = header->addr1; ++ fc = le16_to_cpu(header->frame_ctl); ++ ++ if(GetToDs(&fc)) ++ pDaddr = header->addr3; ++ else ++ pDaddr = header->addr1; ++ ++ if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0) ++ && ! (pDaddr) ++ && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE)) ++ //&& ieee->pHTInfo->bCurrentHTSupport && ++ //ieee->pHTInfo->bCurRxReorderEnable) ++ ret = false; ++ else ++ ret = true; ++#endif ++ WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret); ++ return ret; ++} ++ ++int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe) ++{ ++ struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; ++ u8 * frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET; ++ u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL; ++ u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0; ++ PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL; ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ int ret = 0; ++ ++ WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); ++ ++ return ret; ++#if 0 ++ hdr_len = sMacHdrLng; ++ if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) ++ { ++ hdr_len += 2; ++ } ++ //hdr_len += SNAP_SIZE + sizeof(u16); ++ ++ pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len); ++ memmove(pos, pos+padapter->wapiInfo.extra_prefix_len, hdr_len); ++ ++ pSecHeader = pskb->data + hdr_len; ++ pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader; ++ pRA = pskb->data + 4; ++ ++ WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len); ++ ++ //Address 1 is always receiver's address ++ if( IS_MCAST(pRA) ){ ++ if(!pWapiInfo->wapiTxMsk.bTxEnable){ ++ WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); ++ return -2; ++ } ++ if(pWapiInfo->wapiTxMsk.keyId <= 1){ ++ pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; ++ pWapiExt->Reserved = 0; ++ bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); ++ memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); ++ if (bPNOverflow){ ++ // Update MSK Notification. ++ WAPI_TRACE(WAPI_ERR,"===============>%s():multicast PN overflow\n",__FUNCTION__); ++ rtw_wapi_app_event_handler(padapter,NULL,0,pRA, false, false, true, 0, false); ++ } ++ }else{ ++ WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Multicast KeyIdx!!\n",__FUNCTION__); ++ ret = -3; ++ } ++ } ++ else{ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(!memcmp(pWapiSta->PeerMacAddr,pRA,6)){ ++ bFindMatchPeer = true; ++ break; ++ } ++ } ++ if (bFindMatchPeer){ ++ if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)){ ++ WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); ++ return -4; ++ } ++ if (pWapiSta->wapiUsk.keyId <= 1){ ++ if(pWapiSta->wapiUskUpdate.bTxEnable) ++ pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId; ++ else ++ pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId; ++ ++ pWapiExt->Reserved = 0; ++ bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2); ++ memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); ++ if (bPNOverflow){ ++ // Update USK Notification. ++ WAPI_TRACE(WAPI_ERR,"===============>%s():unicast PN overflow\n",__FUNCTION__); ++ rtw_wapi_app_event_handler(padapter,NULL,0,pWapiSta->PeerMacAddr, false, true, false, 0, false); ++ } ++ }else{ ++ WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Unicast KeyIdx!!\n",__FUNCTION__); ++ ret = -5; ++ } ++ } ++ else{ ++ WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta "MAC_FMT"!!\n",__FUNCTION__, MAC_ARG(pRA)); ++ ret = -6; ++ } ++ } ++ ++ WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len); ++ WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); ++ return ret; ++#endif ++} ++ ++// WAPI SW Enc: must have done Coalesce! ++void SecSWSMS4Encryption( ++ _adapter *padapter, ++ u8 * pxmitframe ++ ) ++{ ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ u8 *pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE; ++ struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; ++ ++ u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL; ++ u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16]; ++ u16 OutputLength; ++ ++ WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); ++ ++ WAPI_TRACE(WAPI_TX,"hdrlen: %d \n",pattrib->hdrlen); ++ ++ return; ++ ++ DataOffset = pattrib->hdrlen + pattrib->iv_len; ++ ++ pRA = pframe + 4; ++ ++ ++ if( IS_MCAST(pRA) ){ ++ KeyIdx = pWapiInfo->wapiTxMsk.keyId; ++ pIV = pWapiInfo->lastTxMulticastPN; ++ pMicKey = pWapiInfo->wapiTxMsk.micKey; ++ pDataKey = pWapiInfo->wapiTxMsk.dataKey; ++ }else{ ++ if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)){ ++ bFindMatchPeer = true; ++ break; ++ } ++ } ++ ++ if (bFindMatchPeer){ ++ if (pWapiSta->wapiUskUpdate.bTxEnable){ ++ KeyIdx = pWapiSta->wapiUskUpdate.keyId; ++ WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx); ++ pIV = pWapiSta->lastTxUnicastPN; ++ pMicKey = pWapiSta->wapiUskUpdate.micKey; ++ pDataKey = pWapiSta->wapiUskUpdate.dataKey; ++ }else{ ++ KeyIdx = pWapiSta->wapiUsk.keyId; ++ WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx); ++ pIV = pWapiSta->lastTxUnicastPN; ++ pMicKey = pWapiSta->wapiUsk.micKey; ++ pDataKey = pWapiSta->wapiUsk.dataKey; ++ } ++ }else{ ++ WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta!!\n",__FUNCTION__); ++ return; ++ } ++ }else{ ++ WAPI_TRACE(WAPI_ERR,"%s: wapiSTAUsedList is empty!!\n",__FUNCTION__); ++ return; ++ } ++ } ++ ++ SecPtr = pframe; ++ SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr+DataOffset), pattrib->pktlen, MicBuffer); ++ ++ WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len); ++ ++ memcpy(pframe+pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen-pattrib->icv_len, ++ (u8 *)MicBuffer, ++ padapter->wapiInfo.extra_postfix_len ++ ); ++ ++ ++ WapiSMS4Encryption(pDataKey, pIV, (SecPtr+DataOffset),pattrib->pktlen+pattrib->icv_len, (SecPtr+DataOffset), &OutputLength); ++ ++ WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption",pframe,pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen); ++ ++ WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); ++} ++ ++u8 SecSWSMS4Decryption( ++ _adapter *padapter, ++ u8 *precv_frame, ++ struct recv_priv *precv_priv ++ ) ++{ ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ struct recv_frame_hdr *precv_hdr; ++ PRT_WAPI_STA_INFO pWapiSta = NULL; ++ u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false; ++ u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16]; ++ u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos; ++ u8 TID = 0; ++ u16 OutputLength, DataLen; ++ u8 bQosData; ++ struct sk_buff * pskb; ++ ++ WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__); ++ ++ return 0; ++ ++ precv_hdr = &((union recv_frame*)precv_frame)->u.hdr; ++ pskb = (struct sk_buff *)(precv_hdr->rx_data); ++ precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb); ++ WAPI_TRACE(WAPI_RX, "=========>%s: check PN %d\n", __FUNCTION__,precv_hdr->bWapiCheckPNInDecrypt); ++ WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len); ++ ++ IVOffset = sMacHdrLng; ++ bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE; ++ if (bQosData){ ++ IVOffset += 2; ++ } ++ ++ //if(GetHTC()) ++ // IVOffset += 4; ++ ++ //IVOffset += SNAP_SIZE + sizeof(u16); ++ ++ DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len; ++ ++ pRA = pskb->data + 4; ++ pTA = pskb->data + 10; ++ KeyIdx = *(pskb->data + IVOffset); ++ pRecvPN = pskb->data + IVOffset + 2; ++ pSecData = pskb->data + DataOffset; ++ DataLen = pskb->len - DataOffset; ++ pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len; ++ TID = GetTid(pskb->data); ++ ++ if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){ ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)){ ++ bFindMatchPeer = true; ++ break; ++ } ++ } ++ } ++ ++ if (!bFindMatchPeer){ ++ WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA)); ++ return false; ++ } ++ ++ if( IS_MCAST(pRA) ){ ++ WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__); ++ if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet){ ++ pLastRxPN = pWapiSta->lastRxMulticastPN; ++ if (!WapiComparePN(pRecvPN, pLastRxPN)){ ++ WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__); ++ WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16); ++ WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16); ++ return false; ++ } ++ ++ memcpy(pLastRxPN, pRecvPN, 16); ++ pMicKey = pWapiSta->wapiMsk.micKey; ++ pDataKey = pWapiSta->wapiMsk.dataKey; ++ }else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet){ ++ WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__); ++ bUseUpdatedKey = true; ++ memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16); ++ pMicKey = pWapiSta->wapiMskUpdate.micKey; ++ pDataKey = pWapiSta->wapiMskUpdate.dataKey; ++ }else{ ++ WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__,KeyIdx); ++ return false; ++ } ++ } ++ else{ ++ WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__); ++ if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet){ ++ WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__); ++ if(precv_hdr->bWapiCheckPNInDecrypt){ ++ if(GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE){ ++ WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS); ++ pLastRxPN = lastRxPNforQoS; ++ }else{ ++ pLastRxPN = pWapiSta->lastRxUnicastPN; ++ } ++ if (!WapiComparePN(pRecvPN, pLastRxPN)){ ++ return false; ++ } ++ if(bQosData){ ++ WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); ++ }else{ ++ memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); ++ } ++ }else{ ++ memcpy(precv_hdr->WapiTempPN,pRecvPN,16); ++ } ++ ++ if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) ++ { ++ if ((pRecvPN[0] & 0x1) == 0){ ++ WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__); ++ return false; ++ } ++ } ++ ++ pMicKey = pWapiSta->wapiUsk.micKey; ++ pDataKey = pWapiSta->wapiUsk.dataKey; ++ } ++ else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet ){ ++ WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__); ++ if(pWapiSta->bAuthenticatorInUpdata) ++ bUseUpdatedKey = true; ++ else ++ bUseUpdatedKey = false; ++ ++ if(bQosData){ ++ WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); ++ }else{ ++ memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); ++ } ++ pMicKey = pWapiSta->wapiUskUpdate.micKey; ++ pDataKey = pWapiSta->wapiUskUpdate.dataKey; ++ }else{ ++ WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId, pWapiSta->wapiUskUpdate.keyId); ++ //dump_buf(pskb->data,pskb->len); ++ return false; ++ } ++ } ++ ++ WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16); ++ WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16); ++ WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength); ++ ++ if (OutputLength != DataLen) ++ WAPI_TRACE(WAPI_ERR, "%s: Output Length Error!!!!\n", __FUNCTION__); ++ ++ WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len); ++ ++ DataLen -= padapter->wapiInfo.extra_postfix_len; ++ ++ SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer); ++ ++ WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN); ++ WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN); ++ ++ if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)){ ++ WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__); ++ if (bUseUpdatedKey){ ++ // delete the old key ++ if ( IS_MCAST(pRA) ){ ++ WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__); ++ pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId; ++ memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16); ++ memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16); ++ pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false; ++ }else{ ++ WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__); ++ pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId; ++ memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); ++ memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); ++ pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false; ++ } ++ } ++ }else{ ++ WAPI_TRACE(WAPI_ERR, "%s: Check MIC Error, Dropped !!!!\n", __FUNCTION__); ++ return false; ++ } ++ ++ pos = pskb->data; ++ memmove(pos+padapter->wapiInfo.extra_prefix_len, pos, IVOffset); ++ skb_pull(pskb, padapter->wapiInfo.extra_prefix_len); ++ ++ WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__); ++ ++ return true; ++} ++ ++u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ ++ ++ u8 *pframe; ++ u32 res = _SUCCESS; ++ ++ WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__); ++ return _FAIL; ++ } ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return _FAIL; ++ ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET; ++ ++ SecSWSMS4Encryption(padapter, pxmitframe); ++ ++ WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); ++ return res; ++} ++ ++u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe) ++{ ++ u8 *pframe; ++ u32 res = _SUCCESS; ++ ++ WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__); ++ ++ if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) ++ { ++ WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__); ++ return _FAIL; ++ } ++ ++ ++ //drop packet when hw decrypt fail ++ //return tempraily ++ return _FAIL; ++ ++ //pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ ++ if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) ++ { ++ WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n",__FUNCTION__); ++ return _FAIL; ++ } ++ ++ WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__); ++ return res; ++} ++ ++#else ++ ++u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ ++ WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__); ++ WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__); ++ return _SUCCESS; ++} ++ ++u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe) ++{ ++ WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__); ++ WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__); ++ return _SUCCESS; ++} ++ ++#endif ++ ++#endif +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wlan_util.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wlan_util.c +new file mode 100644 +index 00000000..8bac6dc5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_wlan_util.c +@@ -0,0 +1,2663 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_WLAN_UTIL_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_WOWLAN ++#include ++#endif ++ ++unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; ++unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74}; ++ ++unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18}; ++unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7}; ++unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5}; ++ ++unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96}; ++unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43}; ++unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43}; ++unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c}; ++unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5}; ++unsigned char EPIGRAM_OUI[] = {0x00, 0x90, 0x4c}; ++ ++unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20}; ++ ++extern unsigned char MCS_rate_2R[16]; ++#ifdef CONFIG_DISABLE_MCS13TO15 ++extern unsigned char MCS_rate_2R_MCS13TO15_OFF[16]; ++#endif //CONFIG_DISABLE_MCS13TO15 ++extern unsigned char MCS_rate_1R[16]; ++extern unsigned char RTW_WPA_OUI[]; ++extern unsigned char WPA_TKIP_CIPHER[4]; ++extern unsigned char RSN_TKIP_CIPHER[4]; ++ ++#define R2T_PHY_DELAY (0) ++ ++//#define WAIT_FOR_BCN_TO_MIN (3000) ++#define WAIT_FOR_BCN_TO_MIN (6000) ++#define WAIT_FOR_BCN_TO_MAX (20000) ++ ++static u8 rtw_basic_rate_cck[4] = { ++ IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK ++}; ++ ++static u8 rtw_basic_rate_ofdm[3] = { ++ IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK ++}; ++ ++static u8 rtw_basic_rate_mix[7] = { ++ IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK ++}; ++ ++ ++int cckrates_included(unsigned char *rate, int ratelen) ++{ ++ int i; ++ ++ for(i = 0; i < ratelen; i++) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ } ++ ++ return _FALSE; ++ ++} ++ ++int cckratesonly_included(unsigned char *rate, int ratelen) ++{ ++ int i; ++ ++ for(i = 0; i < ratelen; i++) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ return _FALSE; ++ } ++ ++ return _TRUE; ++} ++ ++unsigned char networktype_to_raid(unsigned char network_type) ++{ ++ unsigned char raid; ++ ++ switch(network_type) ++ { ++ case WIRELESS_11B: ++ raid = RATR_INX_WIRELESS_B; ++ break; ++ case WIRELESS_11A: ++ case WIRELESS_11G: ++ raid = RATR_INX_WIRELESS_G; ++ break; ++ case WIRELESS_11BG: ++ raid = RATR_INX_WIRELESS_GB; ++ break; ++ case WIRELESS_11_24N: ++ case WIRELESS_11_5N: ++ raid = RATR_INX_WIRELESS_N; ++ break; ++ case WIRELESS_11A_5N: ++ case WIRELESS_11G_24N: ++ raid = RATR_INX_WIRELESS_NG; ++ break; ++ case WIRELESS_11BG_24N: ++ raid = RATR_INX_WIRELESS_NGB; ++ break; ++ default: ++ raid = RATR_INX_WIRELESS_GB; ++ break; ++ ++ } ++ ++ return raid; ++ ++} ++ ++u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) ++{ ++ u8 network_type = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(pmlmeext->cur_channel > 14) ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_5N; ++ } ++ ++ network_type |= WIRELESS_11A; ++ } ++ else ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_24N; ++ } ++ ++ if ((cckratesonly_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11B; ++ } ++ else if((cckrates_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11BG; ++ } ++ else ++ { ++ network_type |= WIRELESS_11G; ++ } ++ } ++ ++ return network_type; ++} ++ ++unsigned char ratetbl_val_2wifirate(unsigned char rate); ++unsigned char ratetbl_val_2wifirate(unsigned char rate) ++{ ++ unsigned char val = 0; ++ ++ switch (rate & 0x7f) ++ { ++ case 0: ++ val = IEEE80211_CCK_RATE_1MB; ++ break; ++ ++ case 1: ++ val = IEEE80211_CCK_RATE_2MB; ++ break; ++ ++ case 2: ++ val = IEEE80211_CCK_RATE_5MB; ++ break; ++ ++ case 3: ++ val = IEEE80211_CCK_RATE_11MB; ++ break; ++ ++ case 4: ++ val = IEEE80211_OFDM_RATE_6MB; ++ break; ++ ++ case 5: ++ val = IEEE80211_OFDM_RATE_9MB; ++ break; ++ ++ case 6: ++ val = IEEE80211_OFDM_RATE_12MB; ++ break; ++ ++ case 7: ++ val = IEEE80211_OFDM_RATE_18MB; ++ break; ++ ++ case 8: ++ val = IEEE80211_OFDM_RATE_24MB; ++ break; ++ ++ case 9: ++ val = IEEE80211_OFDM_RATE_36MB; ++ break; ++ ++ case 10: ++ val = IEEE80211_OFDM_RATE_48MB; ++ break; ++ ++ case 11: ++ val = IEEE80211_OFDM_RATE_54MB; ++ break; ++ ++ } ++ ++ return val; ++ ++} ++ ++int is_basicrate(_adapter *padapter, unsigned char rate); ++int is_basicrate(_adapter *padapter, unsigned char rate) ++{ ++ int i; ++ unsigned char val; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ for(i = 0; i < NumRates; i++) ++ { ++ val = pmlmeext->basicrate[i]; ++ ++ if ((val != 0xff) && (val != 0xfe)) ++ { ++ if (rate == ratetbl_val_2wifirate(val)) ++ { ++ return _TRUE; ++ } ++ } ++ } ++ ++ return _FALSE; ++} ++ ++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset); ++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) ++{ ++ int i; ++ unsigned char rate; ++ unsigned int len = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ for (i = 0; i < NumRates; i++) ++ { ++ rate = pmlmeext->datarate[i]; ++ ++ switch (rate) ++ { ++ case 0xff: ++ return len; ++ ++ case 0xfe: ++ continue; ++ ++ default: ++ rate = ratetbl_val_2wifirate(rate); ++ ++ if (is_basicrate(padapter, rate) == _TRUE) ++ { ++ rate |= IEEE80211_BASIC_RATE_MASK; ++ } ++ ++ rateset[len] = rate; ++ len++; ++ break; ++ } ++ } ++ return len; ++} ++ ++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len) ++{ ++ unsigned char supportedrates[NumRates]; ++ ++ _rtw_memset(supportedrates, 0, NumRates); ++ *bssrate_len = ratetbl2rateset(padapter, supportedrates); ++ _rtw_memcpy(pbssrate, supportedrates, *bssrate_len); ++} ++ ++void UpdateBrateTbl( ++ IN PADAPTER Adapter, ++ IN u8 *mBratesOS ++) ++{ ++ u8 i; ++ u8 rate; ++ ++ // 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. ++ for(i=0;iiface_type == IFACE_PORT1) ++ { ++ Set_NETYPE1_MSR(padapter, type); ++ } ++ else ++#endif ++ { ++ Set_NETYPE0_MSR(padapter, type); ++ } ++} ++ ++inline u8 rtw_get_oper_ch(_adapter *adapter) ++{ ++ return adapter_to_dvobj(adapter)->oper_channel; ++} ++ ++inline void rtw_set_oper_ch(_adapter *adapter, u8 ch) ++{ ++ if (adapter_to_dvobj(adapter)->oper_channel != ch) ++ adapter_to_dvobj(adapter)->on_oper_ch_time = rtw_get_current_time(); ++ ++ adapter_to_dvobj(adapter)->oper_channel = ch; ++} ++ ++inline u8 rtw_get_oper_bw(_adapter *adapter) ++{ ++ return adapter_to_dvobj(adapter)->oper_bwmode; ++} ++ ++inline void rtw_set_oper_bw(_adapter *adapter, u8 bw) ++{ ++ adapter_to_dvobj(adapter)->oper_bwmode = bw; ++} ++ ++inline u8 rtw_get_oper_choffset(_adapter *adapter) ++{ ++ return adapter_to_dvobj(adapter)->oper_ch_offset; ++} ++ ++inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset) ++{ ++ adapter_to_dvobj(adapter)->oper_ch_offset = offset; ++} ++ ++inline u32 rtw_get_on_oper_ch_time(_adapter *adapter) ++{ ++ return adapter_to_dvobj(adapter)->on_oper_ch_time; ++} ++ ++inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) ++{ ++ if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) ++ return adapter_to_dvobj(adapter)->on_oper_ch_time; ++ else ++ return 0; ++} ++ ++void SelectChannel(_adapter *padapter, unsigned char channel) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ //saved channel info ++ rtw_set_oper_ch(padapter, channel); ++ dc_SelectChannel(padapter, channel); ++#else //CONFIG_DUALMAC_CONCURRENT ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); ++ ++ //saved channel info ++ rtw_set_oper_ch(padapter, channel); ++ ++ rtw_hal_set_chan(padapter, channel); ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); ++ ++#endif // CONFIG_DUALMAC_CONCURRENT ++} ++ ++void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ //saved bw info ++ rtw_set_oper_bw(padapter, bwmode); ++ rtw_set_oper_choffset(padapter, channel_offset); ++ dc_SetBWMode(padapter, bwmode, channel_offset); ++#else //CONFIG_DUALMAC_CONCURRENT ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); ++ ++ //saved bw info ++ rtw_set_oper_bw(padapter, bwmode); ++ rtw_set_oper_choffset(padapter, channel_offset); ++ ++ rtw_hal_set_bwmode(padapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset); ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); ++ ++#endif // CONFIG_DUALMAC_CONCURRENT ++} ++ ++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) ++{ ++ u8 center_ch; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if ( padapter->bNotifyChannelChange ) ++ { ++ DBG_871X( "[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode ); ++ } ++ ++ if((bwmode == HT_CHANNEL_WIDTH_20)||(channel_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)) ++ { ++ //SelectChannel(padapter, channel); ++ center_ch = channel; ++ } ++ else ++ { ++ //switch to the proper channel ++ if (channel_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ { ++ //SelectChannel(padapter, channel + 2); ++ center_ch = channel + 2; ++ } ++ else ++ { ++ //SelectChannel(padapter, channel - 2); ++ center_ch = channel - 2; ++ } ++ } ++ ++ //set Channel ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ //saved channel/bw info ++ rtw_set_oper_ch(padapter, channel); ++ rtw_set_oper_bw(padapter, bwmode); ++ rtw_set_oper_choffset(padapter, channel_offset); ++ dc_SelectChannel(padapter, center_ch);// set center channel ++#else //CONFIG_DUALMAC_CONCURRENT ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); ++ ++ //saved channel/bw info ++ rtw_set_oper_ch(padapter, channel); ++ rtw_set_oper_bw(padapter, bwmode); ++ rtw_set_oper_choffset(padapter, channel_offset); ++ ++ rtw_hal_set_chan(padapter, center_ch); // set center channel ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); ++ ++#endif // CONFIG_DUALMAC_CONCURRENT ++ ++ ++ SetBWMode(padapter, bwmode, channel_offset); ++ ++} ++ ++int get_bsstype(unsigned short capability) ++{ ++ if (capability & BIT(0)) ++ { ++ return WIFI_FW_AP_STATE; ++ } ++ else if (capability & BIT(1)) ++ { ++ return WIFI_FW_ADHOC_STATE; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) ++{ ++ return (pnetwork->MacAddress); ++} ++ ++u16 get_beacon_interval(WLAN_BSSID_EX *bss) ++{ ++ unsigned short val; ++ _rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2); ++ ++ return le16_to_cpu(val); ++ ++} ++ ++int is_client_associated_to_ap(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext; ++ struct mlme_ext_info *pmlmeinfo; ++ ++ if(!padapter) ++ return _FAIL; ++ ++ pmlmeext = &padapter->mlmeextpriv; ++ pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++int is_client_associated_to_ibss(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++int is_IBSS_empty(_adapter *padapter) ++{ ++ unsigned int i; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ return _FAIL; ++ } ++ } ++ ++ return _TRUE; ++ ++} ++ ++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval) ++{ ++ if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN) ++ { ++ return WAIT_FOR_BCN_TO_MIN; ++ } ++ else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX) ++ { ++ return WAIT_FOR_BCN_TO_MAX; ++ } ++ else ++ { ++ return ((bcn_interval << 2)); ++ } ++} ++ ++void CAM_empty_entry( ++ PADAPTER Adapter, ++ u8 ucIndex ++) ++{ ++ rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex)); ++} ++ ++void invalidate_cam_all(_adapter *padapter) ++{ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0); ++} ++#if 0 ++static u32 _ReadCAM(_adapter *padapter ,u32 addr) ++{ ++ u32 count = 0, cmd; ++ cmd = CAM_POLLINIG |addr ; ++ rtw_write32(padapter, RWCAM, cmd); ++ ++ do{ ++ if(0 == (rtw_read32(padapter,REG_CAMCMD) & CAM_POLLINIG)){ ++ break; ++ } ++ }while(count++ < 100); ++ ++ return rtw_read32(padapter,REG_CAMREAD); ++} ++#endif ++void read_cam(_adapter *padapter ,u8 entry) ++{ ++ u32 j,count = 0, addr; ++ u32 cam_val[2]; //cam_val[0] is read_val, cam_val[1] is the address ++ addr = entry << 3; ++ ++ DBG_8192C("********* DUMP CAM Entry_#%02d***************\n",entry); ++ for (j = 0; j < 6; j++) ++ { ++ //cmd = _ReadCAM(padapter ,addr+j); ++ //HW_VAR_CAM_READ ++ cam_val[1]=addr+j; ++ rtw_hal_get_hwreg(padapter, HW_VAR_CAM_READ, (u8 *)cam_val); ++ DBG_8192C("offset:0x%02x => 0x%08x \n",addr+j,cam_val[0]); ++ } ++ DBG_8192C("*********************************\n"); ++} ++ ++ ++void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key) ++{ ++ unsigned int i, val, addr; ++ //unsigned int cmd; ++ int j; ++ u32 cam_val[2]; ++ ++ addr = entry << 3; ++ ++ for (j = 5; j >= 0; j--) ++ { ++ switch (j) ++ { ++ case 0: ++ val = (ctrl | (mac[0] << 16) | (mac[1] << 24) ); ++ break; ++ ++ case 1: ++ val = (mac[2] | ( mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); ++ break; ++ ++ default: ++ i = (j - 2) << 2; ++ val = (key[i] | (key[i+1] << 8) | (key[i+2] << 16) | (key[i+3] << 24)); ++ break; ++ ++ } ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)j; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++ ++ //rtw_write32(padapter, WCAMI, val); ++ ++ //cmd = CAM_POLLINIG | CAM_WRITE | (addr + j); ++ //rtw_write32(padapter, RWCAM, cmd); ++ ++ //DBG_871X("%s=> cam write: %x, %x\n",__FUNCTION__, cmd, val); ++ ++ } ++ ++} ++ ++void clear_cam_entry(_adapter *padapter, u8 entry) ++{ ++#if 0 ++ u32 addr, val=0; ++ u32 cam_val[2]; ++ ++ addr = entry << 3; ++ ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)0; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++ ++ ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)1; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++#else ++ ++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00}; ++ ++ write_cam(padapter, entry, 0, null_sta, null_key); ++ ++#endif ++} ++ ++int allocate_fw_sta_entry(_adapter *padapter) ++{ ++ unsigned int mac_id; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ for (mac_id = IBSS_START_MAC_ID; mac_id < NUM_STA; mac_id++) ++ { ++ if (pmlmeinfo->FW_sta_info[mac_id].status == 0) ++ { ++ pmlmeinfo->FW_sta_info[mac_id].status = 1; ++ pmlmeinfo->FW_sta_info[mac_id].retry = 0; ++ break; ++ } ++ } ++ ++ return mac_id; ++} ++ ++void flush_all_cam_entry(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ //if(check_buddy_mlmeinfo_state(padapter, _HW_STATE_NOLINK_)) ++ if(check_buddy_fwstate(padapter, _FW_LINKED) == _FALSE) ++ { ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0); ++ } ++ else ++ { ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++ u8 cam_id;//cam_entry ++ ++ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); ++ if(psta) { ++ if(psta->state & WIFI_AP_STATE) ++ {} //clear cam when ap free per sta_info ++ else { ++ if(psta->mac_id==2) ++ cam_id = 5; ++ else ++ cam_id = 4; ++ } ++ //clear_cam_entry(padapter, cam_id); ++ rtw_clearstakey_cmd(padapter, (u8*)psta, cam_id, _FALSE); ++ } ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ //clear cam when ap free per sta_info ++ } ++ } ++#else //CONFIG_CONCURRENT_MODE ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0); ++ ++#endif //CONFIG_CONCURRENT_MODE ++ ++ _rtw_memset((u8 *)(pmlmeinfo->FW_sta_info), 0, sizeof(pmlmeinfo->FW_sta_info)); ++ ++} ++ ++#if defined(CONFIG_P2P) && defined(CONFIG_WFD) ++int WFD_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo; ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++ ++ ++ pwdinfo = &padapter->wdinfo; ++ if ( rtw_get_wfd_ie( ( u8* ) pIE, pIE->Length, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_871X( "[%s] Found WFD IE\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ return( _TRUE ); ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] NO WFD IE\n", __FUNCTION__ ); ++ ++ } ++ return( _FAIL ); ++} ++#endif ++ ++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ //struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pmlmepriv->qospriv.qos_option==0) ++ { ++ pmlmeinfo->WMM_enable = 0; ++ return _FAIL; ++ } ++ ++ pmlmeinfo->WMM_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); ++ return _TRUE; ++ ++ /*if (pregpriv->wifi_spec == 1) ++ { ++ if (pmlmeinfo->WMM_enable == 1) ++ { ++ //todo: compare the parameter set count & decide wheher to update or not ++ return _FAIL; ++ } ++ else ++ { ++ pmlmeinfo->WMM_enable = 1; ++ _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); ++ return _TRUE; ++ } ++ } ++ else ++ { ++ pmlmeinfo->WMM_enable = 0; ++ return _FAIL; ++ }*/ ++ ++} ++ ++void WMMOnAssocRsp(_adapter *padapter) ++{ ++ u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; ++ u8 acm_mask; ++ u16 TXOP; ++ u32 acParm, i; ++ u32 edca[4], inx[4]; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ if (pmlmeinfo->WMM_enable == 0) ++ { ++ padapter->mlmepriv.acm_mask = 0; ++ return; ++ } ++ ++ acm_mask = 0; ++ ++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B) ++ aSifsTime = 10; ++ else ++ aSifsTime = 16; ++ ++ for (i = 0; i < 4; i++) ++ { ++ ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; ++ ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; ++ ++ //AIFS = AIFSN * slot time + SIFS - r2t phy delay ++ AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; ++ ++ ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); ++ ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; ++ TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); ++ ++ acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); ++ ++ switch (ACI) ++ { ++ case 0x0: ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(1):0); ++ edca[XMIT_BE_QUEUE] = acParm; ++ break; ++ ++ case 0x1: ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); ++ //acm_mask |= (ACM? BIT(0):0); ++ edca[XMIT_BK_QUEUE] = acParm; ++ break; ++ ++ case 0x2: ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(2):0); ++ edca[XMIT_VI_QUEUE] = acParm; ++ break; ++ ++ case 0x3: ++ rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(3):0); ++ edca[XMIT_VO_QUEUE] = acParm; ++ break; ++ } ++ ++ DBG_871X("WMM(%x): %x, %x\n", ACI, ACM, acParm); ++ } ++ ++ if(padapter->registrypriv.acm_method == 1) ++ rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); ++ else ++ padapter->mlmepriv.acm_mask = acm_mask; ++ ++ inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; ++ ++ if(pregpriv->wifi_spec==1) ++ { ++ u32 j, tmp, change_inx; ++ ++ //entry indx: 0->vo, 1->vi, 2->be, 3->bk. ++ for(i=0; i<4; i++) ++ { ++ for(j=i+1; j<4; j++) ++ { ++ //compare CW and AIFS ++ if((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) ++ { ++ change_inx = _TRUE; ++ } ++ else if((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) ++ { ++ //compare TXOP ++ if((edca[j] >> 16) > (edca[i] >> 16)) ++ change_inx = _TRUE; ++ } ++ ++ if(change_inx) ++ { ++ tmp = edca[i]; ++ edca[i] = edca[j]; ++ edca[j] = tmp; ++ ++ tmp = inx[i]; ++ inx[i] = inx[j]; ++ inx[j] = tmp; ++ ++ change_inx = _FALSE; ++ } ++ } ++ } ++ } ++ ++ for(i=0; i<4; i++) { ++ pxmitpriv->wmm_para_seq[i] = inx[i]; ++ DBG_871X("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); ++ } ++ ++ return; ++} ++ ++static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++#ifdef CONFIG_80211N_HT ++ unsigned char new_bwmode; ++ unsigned char new_ch_offset; ++ struct HT_info_element *pHT_info; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ if(!pIE) ++ return; ++ ++ if(phtpriv->ht_option == _FALSE) return; ++ ++ if(pIE->Length > sizeof(struct HT_info_element)) ++ return; ++ ++ pHT_info = (struct HT_info_element *)pIE->data; ++ ++ if((pHT_info->infos[0] & BIT(2)) && pregistrypriv->cbw40_enable ) ++ { ++ new_bwmode = HT_CHANNEL_WIDTH_40; ++ ++ switch (pHT_info->infos[0] & 0x3) ++ { ++ case 1: ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ new_bwmode = HT_CHANNEL_WIDTH_20; ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ } ++ else ++ { ++ new_bwmode = HT_CHANNEL_WIDTH_20; ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ ++ if((new_bwmode!= pmlmeext->cur_bwmode) || (new_ch_offset!=pmlmeext->cur_ch_offset)) ++ { ++ pmlmeinfo->bwmode_updated = _TRUE; ++ ++ pmlmeext->cur_bwmode = new_bwmode; ++ pmlmeext->cur_ch_offset = new_ch_offset; ++ ++ //update HT info also ++ HT_info_handler(padapter, pIE); ++ } ++ else ++ { ++ pmlmeinfo->bwmode_updated = _FALSE; ++ } ++ ++ ++ if(_TRUE == pmlmeinfo->bwmode_updated) ++ { ++ struct sta_info *psta; ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ ++ //update ap's stainfo ++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); ++ if(psta) ++ { ++ struct ht_priv *phtpriv_sta = &psta->htpriv; ++ ++ if(phtpriv_sta->ht_option) ++ { ++ // bwmode ++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode; ++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; ++ } ++ else ++ { ++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20; ++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ } ++ ++ //pmlmeinfo->bwmode_updated = _FALSE;//bwmode_updated done, reset it! ++ ++ } ++#endif //CONFIG_80211N_HT ++} ++ ++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++#ifdef CONFIG_80211N_HT ++ unsigned int i; ++ u8 rf_type; ++ u8 max_AMPDU_len, min_MPDU_spacing; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++ if(pIE==NULL) return; ++ ++ if(phtpriv->ht_option == _FALSE) return; ++ ++ pmlmeinfo->HT_caps_enable = 1; ++ ++ for (i = 0; i < (pIE->Length); i++) ++ { ++ if (i != 2) ++ { ++ // Commented by Albert 2010/07/12 ++ // Got the endian issue here. ++ pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]); ++ } ++ else ++ { ++ //modify from fw by Thomas 2010/11/17 ++ if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) ++ { ++ max_AMPDU_len = (pIE->data[i] & 0x3); ++ } ++ else ++ { ++ max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); ++ } ++ ++ if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) ++ { ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); ++ } ++ else ++ { ++ min_MPDU_spacing = (pIE->data[i] & 0x1c); ++ } ++ ++ pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; ++ } ++ } ++ ++ // Commented by Albert 2010/07/12 ++ // Have to handle the endian issue after copying. ++ // HT_ext_caps didn't be used yet. ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info ); ++ pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps ); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ if((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) ++ { ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ else ++ { ++ #ifdef CONFIG_DISABLE_MCS13TO15 ++ if(pmlmeext->cur_bwmode == HT_CHANNEL_WIDTH_40 && (pregistrypriv->wifi_spec!=1)) ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R_MCS13TO15_OFF[i]; ++ else ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i]; ++ #else ++ pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i]; ++ #endif //CONFIG_DISABLE_MCS13TO15 ++ } ++ #ifdef RTL8192C_RECONFIG_TO_1T1R ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ #endif ++ } ++#endif //CONFIG_80211N_HT ++ return; ++} ++ ++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++#ifdef CONFIG_80211N_HT ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ if(pIE==NULL) return; ++ ++ if(phtpriv->ht_option == _FALSE) return; ++ ++ ++ if(pIE->Length > sizeof(struct HT_info_element)) ++ return; ++ ++ pmlmeinfo->HT_info_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); ++#endif //CONFIG_80211N_HT ++ return; ++} ++ ++void HTOnAssocRsp(_adapter *padapter) ++{ ++ unsigned char max_AMPDU_len; ++ unsigned char min_MPDU_spacing; ++ //struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) ++ { ++ pmlmeinfo->HT_enable = 1; ++ } ++ else ++ { ++ pmlmeinfo->HT_enable = 0; ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ return; ++ } ++ ++ //handle A-MPDU parameter field ++ /* ++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k ++ AMPDU_para [4:2]:Min MPDU Start Spacing ++ */ ++ max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; ++ ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); ++ ++#if 0 //move to rtw_update_ht_cap() ++ if ((pregpriv->cbw40_enable) && ++ (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && ++ (pmlmeinfo->HT_info.infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode accoring to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) ++ { ++ case HT_EXTCHNL_OFFSET_UPPER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case HT_EXTCHNL_OFFSET_LOWER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ } ++#endif ++ ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++#if 0 //move to rtw_update_ht_cap() ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++#endif ++ ++} ++ ++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pIE->Length>1) ++ return; ++ ++ pmlmeinfo->ERP_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); ++} ++ ++void VCS_update(_adapter *padapter, struct sta_info *psta) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ switch (pregpriv->vrtl_carrier_sense)/* 0:off 1:on 2:auto */ ++ { ++ case 0: //off ++ psta->rtsen = 0; ++ psta->cts2self = 0; ++ break; ++ ++ case 1: //on ++ if (pregpriv->vcs_type == 1) /* 1:RTS/CTS 2:CTS to self */ ++ { ++ psta->rtsen = 1; ++ psta->cts2self = 0; ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 1; ++ } ++ break; ++ ++ case 2: //auto ++ default: ++ if ((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) ++ { ++ if (pregpriv->vcs_type == 1) ++ { ++ psta->rtsen = 1; ++ psta->cts2self = 0; ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 1; ++ } ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 0; ++ } ++ break; ++ } ++} ++ ++#ifdef CONFIG_TDLS ++int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len) ++{ ++ u8 tdls_prohibited_bit = 0x40; //bit(38); TDLS_prohibited ++ ++ if(pkt_len < 5) ++ { ++ return _FALSE; ++ } ++ ++ pframe += 4; ++ if( (*pframe) & tdls_prohibited_bit ) ++ return _TRUE; ++ ++ return _FALSE; ++} ++#endif //CONFIG_TDLS ++ ++int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) ++{ ++ unsigned int len; ++ unsigned char *p; ++ unsigned short val16, subtype; ++ struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); ++ //u8 wpa_ie[255],rsn_ie[255]; ++ u16 wpa_len=0,rsn_len=0; ++ u8 encryp_protocol = 0; ++ WLAN_BSSID_EX *bssid; ++ int group_cipher = 0, pairwise_cipher = 0, is_8021x = 0; ++ unsigned char *pbuf; ++ u32 wpa_ielen = 0; ++ u8 *pbssid = GetAddr3Ptr(pframe); ++ u32 hidden_ssid = 0; ++ u8 cur_network_type, network_type=0; ++ struct HT_info_element *pht_info = NULL; ++ struct rtw_ieee80211_ht_cap *pht_cap = NULL; ++ u32 bcn_channel; ++ unsigned short ht_cap_info; ++ unsigned char ht_info_infos_0; ++ ++ if (is_client_associated_to_ap(Adapter) == _FALSE) ++ return _TRUE; ++ ++ len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ if (len > MAX_IE_SZ) { ++ DBG_871X("%s IE too long for survey event\n", __func__); ++ return _FAIL; ++ } ++ ++ if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) { ++ DBG_871X("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT, ++ MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress)); ++ return _TRUE; ++ } ++ ++ bssid = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); ++ ++ subtype = GetFrameSubType(pframe) >> 4; ++ ++ if(subtype==WIFI_BEACON) ++ bssid->Reserved[0] = 1; ++ ++ bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; ++ ++ /* below is to copy the information element */ ++ bssid->IELength = len; ++ _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); ++ ++ /* check bw and channel offset */ ++ /* parsing HT_CAP_IE */ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if(p && len>0) { ++ pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); ++ ht_cap_info = pht_cap->cap_info; ++ } else { ++ ht_cap_info = 0; ++ } ++ /* parsing HT_INFO_IE */ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if(p && len>0) { ++ pht_info = (struct HT_info_element *)(p + 2); ++ ht_info_infos_0 = pht_info->infos[0]; ++ } else { ++ ht_info_infos_0 = 0; ++ } ++ if (ht_cap_info != cur_network->BcnInfo.ht_cap_info || ++ ((ht_info_infos_0&0x03) != (cur_network->BcnInfo.ht_info_infos_0&0x03))) { ++ DBG_871X("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, ++ ht_cap_info, ht_info_infos_0); ++ DBG_871X("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, ++ cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0); ++ DBG_871X("%s bw mode change, disconnect\n", __func__); ++ { ++ //bcn_info_update ++ cur_network->BcnInfo.ht_cap_info = ht_cap_info; ++ cur_network->BcnInfo.ht_info_infos_0 = ht_info_infos_0; ++ //to do : need to check that whether modify related register of BB or not ++ } ++ //goto _mismatch; ++ } ++ ++ /* Checking for channel */ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _DSSET_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if (p) { ++ bcn_channel = *(p + 2); ++ } else {/* In 5G, some ap do not have DSSET IE checking HT info for channel */ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if(pht_info) { ++ bcn_channel = pht_info->primary_channel; ++ } else { /* we don't find channel IE, so don't check it */ ++ DBG_871X("Oops: %s we don't find channel IE, so don't check it \n", __func__); ++ bcn_channel = Adapter->mlmeextpriv.cur_channel; ++ } ++ } ++ if (bcn_channel != Adapter->mlmeextpriv.cur_channel) { ++ DBG_871X("%s beacon channel:%d cur channel:%d disconnect\n", __func__, ++ bcn_channel, Adapter->mlmeextpriv.cur_channel); ++ goto _mismatch; ++ } ++ ++ /* checking SSID */ ++ if ((p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_)) == NULL) { ++ DBG_871X("%s marc: cannot find SSID for survey event\n", __func__); ++ hidden_ssid = _TRUE; ++ } else { ++ hidden_ssid = _FALSE; ++ } ++ ++ if((NULL != p) && (_FALSE == hidden_ssid && (*(p + 1)))) { ++ _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); ++ bssid->Ssid.SsidLength = *(p + 1); ++ } else { ++ bssid->Ssid.SsidLength = 0; ++ bssid->Ssid.Ssid[0] = '\0'; ++ } ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s bssid.Ssid.Ssid:%s bssid.Ssid.SsidLength:%d " ++ "cur_network->network.Ssid.Ssid:%s len:%d\n", __func__, bssid->Ssid.Ssid, ++ bssid->Ssid.SsidLength, cur_network->network.Ssid.Ssid, ++ cur_network->network.Ssid.SsidLength)); ++ ++ if (_rtw_memcmp(bssid->Ssid.Ssid, cur_network->network.Ssid.Ssid, 32) == _FALSE || ++ bssid->Ssid.SsidLength != cur_network->network.Ssid.SsidLength) { ++ if (bssid->Ssid.Ssid[0] != '\0' && bssid->Ssid.SsidLength != 0) { /* not hidden ssid */ ++ DBG_871X("%s(), SSID is not match return FAIL\n", __func__); ++ goto _mismatch; ++ } ++ } ++ ++ /* check encryption info */ ++ val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); ++ ++ if (val16 & BIT(4)) ++ bssid->Privacy = 1; ++ else ++ bssid->Privacy = 0; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, ++ ("%s(): cur_network->network.Privacy is %d, bssid.Privacy is %d\n", ++ __func__, cur_network->network.Privacy,bssid->Privacy)); ++ if (cur_network->network.Privacy != bssid->Privacy) { ++ DBG_871X("%s(), privacy is not match return FAIL\n",__func__); ++ goto _mismatch; ++ } ++ ++ rtw_get_sec_ie(bssid->IEs, bssid->IELength, NULL,&rsn_len,NULL,&wpa_len); ++ ++ if (rsn_len > 0) { ++ encryp_protocol = ENCRYP_PROTOCOL_WPA2; ++ } else if (wpa_len > 0) { ++ encryp_protocol = ENCRYP_PROTOCOL_WPA; ++ } else { ++ if (bssid->Privacy) ++ encryp_protocol = ENCRYP_PROTOCOL_WEP; ++ } ++ ++ if (cur_network->BcnInfo.encryp_protocol != encryp_protocol) { ++ DBG_871X("%s(): enctyp is not match ,return FAIL\n",__func__); ++ goto _mismatch; ++ } ++ ++ if (encryp_protocol == ENCRYP_PROTOCOL_WPA || encryp_protocol == ENCRYP_PROTOCOL_WPA2) { ++ pbuf = rtw_get_wpa_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength-12); ++ if(pbuf && (wpa_ielen>0)) { ++ if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is_8021x)) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, ++ ("%s pnetwork->pairwise_cipher: %d, group_cipher is %d, is_8021x is %d\n", __func__, ++ pairwise_cipher, group_cipher, is_8021x)); ++ } ++ } else { ++ pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength-12); ++ ++ if(pbuf && (wpa_ielen>0)) { ++ if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is_8021x)) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, ++ ("%s pnetwork->pairwise_cipher: %d, pnetwork->group_cipher is %d, is_802x is %d\n", ++ __func__, pairwise_cipher, group_cipher, is_8021x)); ++ } ++ } ++ } ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_, ++ ("%s cur_network->group_cipher is %d: %d\n",__func__, cur_network->BcnInfo.group_cipher, group_cipher)); ++ if (pairwise_cipher != cur_network->BcnInfo.pairwise_cipher || group_cipher != cur_network->BcnInfo.group_cipher) { ++ DBG_871X("%s pairwise_cipher(%x:%x) or group_cipher(%x:%x) is not match ,return FAIL\n",__func__, ++ pairwise_cipher, cur_network->BcnInfo.pairwise_cipher, ++ group_cipher, cur_network->BcnInfo.group_cipher); ++ goto _mismatch; ++ } ++ ++ if (is_8021x != cur_network->BcnInfo.is_8021x) { ++ DBG_871X("%s authentication is not match ,return FAIL\n", __func__); ++ goto _mismatch; ++ } ++ } ++ ++ rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); ++ return _SUCCESS; ++ ++_mismatch: ++ rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); ++ return _FAIL; ++ ++ _func_exit_; ++} ++ ++void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) ++{ ++ unsigned int i; ++ unsigned int len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; //bit(38): TDLS_prohibited ++#endif //CONFIG_TDLS ++ ++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); ++ ++ for (i = 0; i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); ++ ++ switch (pIE->ElementID) ++ { ++#if 0 ++ case _VENDOR_SPECIFIC_IE_: ++ //todo: to update WMM paramter set while receiving beacon ++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM ++ { ++ (WMM_param_handler(padapter, pIE))? WMMOnAssocRsp(padapter): 0; ++ } ++ break; ++#endif ++ ++ case _HT_EXTRA_INFO_IE_: //HT info ++ //HT_info_handler(padapter, pIE); ++ bwmode_update_check(padapter, pIE); ++ break; ++ ++ case _ERPINFO_IE_: ++ ERP_IE_handler(padapter, pIE); ++ VCS_update(padapter, psta); ++ break; ++ ++#ifdef CONFIG_TDLS ++ case _EXT_CAP_IE_: ++ if( check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE ) ++ ptdlsinfo->ap_prohibited = _TRUE; ++ break; ++#endif //CONFIG_TDLS ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++} ++ ++#ifdef CONFIG_DFS ++void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) ++{ ++ unsigned int i; ++ unsigned int len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 new_ch_no = 0; ++ ++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); ++ ++ for (i = 0; i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _CH_SWTICH_ANNOUNCE_: ++ _rtw_memcpy(&new_ch_no, pIE->data+1, 1); ++ rtw_set_csa_cmd(padapter, new_ch_no); ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++} ++#endif //CONFIG_DFS ++ ++unsigned int is_ap_in_tkip(_adapter *padapter) ++{ ++ u32 i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) ++ { ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) ++ { ++ return _TRUE; ++ } ++ break; ++ ++ case _RSN_IE_2_: ++ if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) ++ { ++ return _TRUE; ++ } ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return _FALSE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ ++} ++ ++unsigned int should_forbid_n_rate(_adapter * padapter) ++{ ++ u32 i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ WLAN_BSSID_EX *cur_network = &pmlmepriv->cur_network.network; ++ ++ if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) ++ { ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) && ++ ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) || ++ (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4)))) ++ return _FALSE; ++ break; ++ ++ case _RSN_IE_2_: ++ if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4)) || ++ (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4))) ++ return _FALSE; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return _TRUE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ ++} ++ ++ ++unsigned int is_ap_in_wep(_adapter *padapter) ++{ ++ u32 i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) ++ { ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ++ return _FALSE; ++ break; ++ ++ case _RSN_IE_2_: ++ return _FALSE; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return _TRUE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ ++} ++ ++int wifirate2_ratetbl_inx(unsigned char rate); ++int wifirate2_ratetbl_inx(unsigned char rate) ++{ ++ int inx = 0; ++ rate = rate & 0x7f; ++ ++ switch (rate) ++ { ++ case 54*2: ++ inx = 11; ++ break; ++ ++ case 48*2: ++ inx = 10; ++ break; ++ ++ case 36*2: ++ inx = 9; ++ break; ++ ++ case 24*2: ++ inx = 8; ++ break; ++ ++ case 18*2: ++ inx = 7; ++ break; ++ ++ case 12*2: ++ inx = 6; ++ break; ++ ++ case 9*2: ++ inx = 5; ++ break; ++ ++ case 6*2: ++ inx = 4; ++ break; ++ ++ case 11*2: ++ inx = 3; ++ break; ++ case 11: ++ inx = 2; ++ break; ++ ++ case 2*2: ++ inx = 1; ++ break; ++ ++ case 1*2: ++ inx = 0; ++ break; ++ ++ } ++ return inx; ++} ++ ++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz) ++{ ++ unsigned int i, num_of_rate; ++ unsigned int mask = 0; ++ ++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; ++ ++ for (i = 0; i < num_of_rate; i++) ++ { ++ if ((*(ptn + i)) & 0x80) ++ { ++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); ++ } ++ } ++ return mask; ++} ++ ++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) ++{ ++ unsigned int i, num_of_rate; ++ unsigned int mask = 0; ++ ++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; ++ ++ for (i = 0; i < num_of_rate; i++) ++ { ++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); ++ } ++ ++ return mask; ++} ++ ++unsigned int update_MSC_rate(struct HT_caps_element *pHT_caps) ++{ ++ unsigned int mask = 0; ++ ++ mask = ((pHT_caps->u.HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 20)); ++ ++ return mask; ++} ++ ++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps) ++{ ++ unsigned char bit_offset; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (!(pmlmeinfo->HT_enable)) ++ return _FAIL; ++ ++ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)) ++ return _FAIL; ++ ++ bit_offset = (pmlmeext->cur_bwmode & HT_CHANNEL_WIDTH_40)? 6: 5; ++ ++ if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset)) ++ { ++ return _SUCCESS; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++unsigned char get_highest_rate_idx(u32 mask) ++{ ++ int i; ++ unsigned char rate_idx=0; ++ ++ for(i=27; i>=0; i--) ++ { ++ if(mask & BIT(i)) ++ { ++ rate_idx = i; ++ break; ++ } ++ } ++ ++ return rate_idx; ++} ++ ++unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps); ++unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps) ++{ ++ int i, mcs_rate; ++ ++ mcs_rate = (pHT_caps->u.HT_cap_element.MCS_rate[0] | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 8)); ++ ++ for (i = 15; i >= 0; i--) ++ { ++ if (mcs_rate & (0x1 << i)) ++ { ++ break; ++ } ++ } ++ ++ return i; ++} ++ ++void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) ++{ ++ rtw_hal_update_ra_mask(psta, 0); ++} ++ ++void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta); ++void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta) ++{ ++ Update_RA_Entry(padapter, psta); ++} ++ ++void set_sta_rate(_adapter *padapter, struct sta_info *psta) ++{ ++ //rate adaptive ++ enable_rate_adaptive(padapter, psta); ++} ++ ++// Update RRSR and Rate for USERATE ++void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode) ++{ ++ NDIS_802_11_RATES_EX supported_rates; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++ ++ // Added by Albert 2011/03/22 ++ // In the P2P mode, the driver should not support the b mode. ++ // So, the Tx packet shouldn't use the CCK rate ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++#endif //CONFIG_P2P ++#ifdef CONFIG_INTEL_WIDI ++ if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE) ++ return; ++#endif //CONFIG_INTEL_WIDI ++ ++ _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX); ++ ++ if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B)) { ++ _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4); ++ } else if (wirelessmode & WIRELESS_11B) { ++ _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7); ++ } else { ++ _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3); ++ } ++ ++ if (wirelessmode & WIRELESS_11B) ++ update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); ++ else ++ update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates); ++} ++ ++unsigned char check_assoc_AP(u8 *pframe, uint len) ++{ ++ unsigned int i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 epigram_vendor_flag; ++ u8 ralink_vendor_flag; ++ epigram_vendor_flag = 0; ++ ralink_vendor_flag = 0; ++ ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) ++ { ++ DBG_871X("link to Artheros AP\n"); ++ return HT_IOT_PEER_ATHEROS; ++ } ++ else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) ++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) ++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))) ++ { ++ DBG_871X("link to Broadcom AP\n"); ++ return HT_IOT_PEER_BROADCOM; ++ } ++ else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) ++ { ++ DBG_871X("link to Marvell AP\n"); ++ return HT_IOT_PEER_MARVELL; ++ } ++ else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) ++ { ++ if (!ralink_vendor_flag) { ++ ralink_vendor_flag = 1; ++ } else { ++ DBG_871X("link to Ralink AP\n"); ++ return HT_IOT_PEER_RALINK; ++ } ++ } ++ else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) ++ { ++ DBG_871X("link to Cisco AP\n"); ++ return HT_IOT_PEER_CISCO; ++ } ++ else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) ++ { ++ DBG_871X("link to Realtek 96B\n"); ++ return HT_IOT_PEER_REALTEK; ++ } ++ else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI,3)) ++ { ++ DBG_871X("link to Airgo Cap\n"); ++ return HT_IOT_PEER_AIRGO; ++ } ++ else if (_rtw_memcmp(pIE->data, EPIGRAM_OUI, 3)) ++ { ++ epigram_vendor_flag = 1; ++ if(ralink_vendor_flag) { ++ DBG_871X("link to Tenda W311R AP\n"); ++ return HT_IOT_PEER_TENDA; ++ } else { ++ DBG_871X("Capture EPIGRAM_OUI\n"); ++ } ++ } ++ else ++ { ++ break; ++ } ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ if (ralink_vendor_flag && !epigram_vendor_flag) { ++ DBG_871X("link to Ralink AP\n"); ++ return HT_IOT_PEER_RALINK; ++ } else if (ralink_vendor_flag && epigram_vendor_flag){ ++ DBG_871X("link to Tenda W311R AP\n"); ++ return HT_IOT_PEER_TENDA; ++ } else { ++ DBG_871X("link to new AP\n"); ++ return HT_IOT_PEER_UNKNOWN; ++ } ++} ++ ++void update_IOT_info(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ switch (pmlmeinfo->assoc_AP_vendor) ++ { ++ case HT_IOT_PEER_MARVELL: ++ pmlmeinfo->turboMode_cts2self = 1; ++ pmlmeinfo->turboMode_rtsen = 0; ++ break; ++ ++ case HT_IOT_PEER_RALINK: ++ pmlmeinfo->turboMode_cts2self = 0; ++ pmlmeinfo->turboMode_rtsen = 1; ++ //disable high power ++ Switch_DM_Func(padapter, (~DYNAMIC_BB_DYNAMIC_TXPWR), _FALSE); ++ break; ++ case HT_IOT_PEER_REALTEK: ++ //rtw_write16(padapter, 0x4cc, 0xffff); ++ //rtw_write16(padapter, 0x546, 0x01c0); ++ //disable high power ++ Switch_DM_Func(padapter, (~DYNAMIC_BB_DYNAMIC_TXPWR), _FALSE); ++ break; ++ default: ++ pmlmeinfo->turboMode_cts2self = 0; ++ pmlmeinfo->turboMode_rtsen = 1; ++ break; ++ } ++ ++} ++ ++void update_capinfo(PADAPTER Adapter, u16 updateCap) ++{ ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ BOOLEAN ShortPreamble; ++ ++ // Check preamble mode, 2005.01.06, by rcnjko. ++ // Mark to update preamble value forever, 2008.03.18 by lanhsin ++ //if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) ++ { ++ ++ if(updateCap & cShortPreamble) ++ { // Short Preamble ++ if(pmlmeinfo->preamble_mode != PREAMBLE_SHORT) // PREAMBLE_LONG or PREAMBLE_AUTO ++ { ++ ShortPreamble = _TRUE; ++ pmlmeinfo->preamble_mode = PREAMBLE_SHORT; ++ rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); ++ } ++ } ++ else ++ { // Long Preamble ++ if(pmlmeinfo->preamble_mode != PREAMBLE_LONG) // PREAMBLE_SHORT or PREAMBLE_AUTO ++ { ++ ShortPreamble = _FALSE; ++ pmlmeinfo->preamble_mode = PREAMBLE_LONG; ++ rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); ++ } ++ } ++ } ++ ++ if ( updateCap & cIBSS ) { ++ //Filen: See 802.11-2007 p.91 ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ else ++ { ++ //Filen: See 802.11-2007 p.90 ++ if( pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11_24N)) ++ { ++ if( (updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) ++ { // Short Slot Time ++ if(pmlmeinfo->slotTime != SHORT_SLOT_TIME) ++ { ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ } ++ } ++ else ++ { // Long Slot Time ++ if(pmlmeinfo->slotTime != NON_SHORT_SLOT_TIME) ++ { ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ } ++ } ++ else if( pmlmeext->cur_wireless_mode & (WIRELESS_11A | WIRELESS_11_5N)) ++ { ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ } ++ else ++ { ++ //B Mode ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ } ++ ++ rtw_hal_set_hwreg( Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime ); ++ ++} ++ ++void update_wireless_mode(_adapter *padapter) ++{ ++ int ratelen, network_type = 0; ++ u32 SIFS_Timer; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ unsigned char *rate = cur_network->SupportedRates; ++ ++ ratelen = rtw_get_rateset_len(cur_network->SupportedRates); ++ ++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) ++ { ++ pmlmeinfo->HT_enable = 1; ++ } ++ ++ if(pmlmeext->cur_channel > 14) ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_5N; ++ } ++ ++ network_type |= WIRELESS_11A; ++ } ++ else ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_24N; ++ } ++ ++ if ((cckratesonly_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11B; ++ } ++ else if((cckrates_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11BG; ++ } ++ else ++ { ++ network_type |= WIRELESS_11G; ++ } ++ } ++ ++ pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; ++/* ++ if((pmlmeext->cur_wireless_mode==WIRELESS_11G) || ++ (pmlmeext->cur_wireless_mode==WIRELESS_11BG))//WIRELESS_MODE_G) ++ SIFS_Timer = 0x0a0a;//CCK ++ else ++ SIFS_Timer = 0x0e0e;//pHalData->SifsTime; //OFDM ++*/ ++ ++ SIFS_Timer = 0x0a0a0808; //0x0808 -> for CCK, 0x0a0a -> for OFDM ++ //change this value if having IOT issues. ++ ++ padapter->HalFunc.SetHwRegHandler( padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer); ++ ++ if (pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); ++ else ++ update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); ++} ++ ++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value); ++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value) ++{ ++#if 0 ++ struct cmd_obj *ph2c; ++ struct reg_rw_parm *pwriteMacPara; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ if ((pwriteMacPara = (struct reg_rw_parm*)rtw_malloc(sizeof(struct reg_rw_parm))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ pwriteMacPara->rw = 1; ++ pwriteMacPara->addr = addr; ++ pwriteMacPara->value = value; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG)); ++ rtw_enqueue_cmd(pcmdpriv, ph2c); ++#endif ++} ++ ++void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ { ++ // Only B, B/G, and B/G/N AP could use CCK rate ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), rtw_basic_rate_cck, 4); ++ } ++ else ++ { ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), rtw_basic_rate_ofdm, 4); ++ } ++} ++ ++int update_sta_support_rate(_adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx) ++{ ++ unsigned int ie_len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ int supportRateNum = 0; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _SUPPORTEDRATES_IE_, &ie_len, var_ie_len); ++ if (pIE == NULL) ++ { ++ return _FAIL; ++ } ++ ++ _rtw_memcpy(pmlmeinfo->FW_sta_info[cam_idx].SupportedRates, pIE->data, ie_len); ++ supportRateNum = ie_len; ++ ++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _EXT_SUPPORTEDRATES_IE_, &ie_len, var_ie_len); ++ if (pIE) ++ { ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[cam_idx].SupportedRates + supportRateNum), pIE->data, ie_len); ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) ++{ ++ struct sta_info *psta; ++ u16 tid, start_seq, param; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct ADDBA_request *preq = (struct ADDBA_request*)paddba_req; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ psta = rtw_get_stainfo(pstapriv, addr); ++ ++ if(psta) ++ { ++ start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; ++ ++ param = le16_to_cpu(preq->BA_para_set); ++ tid = (param>>2)&0x0f; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[tid]; ++ ++ #ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ ++ preorder_ctrl->indicate_seq = start_seq; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, start_seq); ++ #endif ++ #else ++ preorder_ctrl->indicate_seq = 0xffff; ++ #endif ++ ++ preorder_ctrl->enable =(pmlmeinfo->bAcceptAddbaReq == _TRUE)? _TRUE :_FALSE; ++ } ++ ++} ++ ++void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) ++{ ++ u8* pIE; ++ u32 *pbuf; ++ ++ pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ pbuf = (u32*)pIE; ++ ++ pmlmeext->TSFValue = le32_to_cpu(*(pbuf+1)); ++ ++ pmlmeext->TSFValue = pmlmeext->TSFValue << 32; ++ ++ pmlmeext->TSFValue |= le32_to_cpu(*pbuf); ++} ++ ++void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext) ++{ ++ rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, 0); ++} ++ ++void beacon_timing_control(_adapter *padapter) ++{ ++ rtw_hal_bcn_related_reg_setting(padapter); ++} ++ ++#if 0 ++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) ++{ ++ unsigned short ATIMWindow; ++ unsigned char *pframe; ++ struct tx_desc *ptxdesc; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned int rate_len, len = 0; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ _rtw_memset(beacon_frame, 0, 256); ++ ++ pframe = beacon_frame + TXDESC_SIZE; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ len = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ len += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ len += 2; ++ ++ // capability info: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ len += 2; ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &len); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len); ++ ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len); ++ ++ //todo: ERP IE ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len); ++ } ++ ++ if ((len + TXDESC_SIZE) > 256) ++ { ++ //DBG_871X("marc: beacon frame too large\n"); ++ return 0; ++ } ++ ++ //fill the tx descriptor ++ ptxdesc = (struct tx_desc *)beacon_frame; ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); //default = 32 bytes for TX Desc ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00); ++ ++ //offset 8 ++ ptxdesc->txdw2 |= cpu_to_le32(BMC); ++ ptxdesc->txdw2 |= cpu_to_le32(BK); ++ ++ //offset 16 ++ ptxdesc->txdw4 = 0x80000000; ++ ++ //offset 20 ++ ptxdesc->txdw5 = 0x00000000; //1M ++ ++ return (len + TXDESC_SIZE); ++} ++#endif ++ ++static _adapter *pbuddy_padapter = NULL; ++ ++int rtw_handle_dualmac(_adapter *adapter, bool init) ++{ ++ int status = _SUCCESS; ++ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); ++ ++ if (init) { ++ #if 0 ++ /* For SMSP on 92DU-VC, driver do not probe another Interface. */ ++ if(dvobj->NumInterfaces == 2 && dvobj->InterfaceNumber != 0 && ++ adapter->registrypriv.mac_phy_mode == 1) { ++ DBG_871X("%s(): Do not init another USB Interface because SMSP\n",__FUNCTION__); ++ status = _FAIL; ++ goto exit; ++ } ++ #endif ++ ++ if (pbuddy_padapter == NULL) { ++ pbuddy_padapter = adapter; ++ DBG_871X("%s(): pbuddy_padapter == NULL, Set pbuddy_padapter\n",__FUNCTION__); ++ } else { ++ adapter->pbuddy_adapter = pbuddy_padapter; ++ pbuddy_padapter->pbuddy_adapter = adapter; ++ // clear global value ++ pbuddy_padapter = NULL; ++ DBG_871X("%s(): pbuddy_padapter exist, Exchange Information\n",__FUNCTION__); ++ } ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if (dvobj->InterfaceNumber == 0) { ++ //set adapter_type/iface type ++ adapter->isprimary = _TRUE; ++ adapter->adapter_type = PRIMARY_ADAPTER; ++ adapter->iface_type = IFACE_PORT0; ++ DBG_871X("%s(): PRIMARY_ADAPTER\n",__FUNCTION__); ++ } else { ++ //set adapter_type/iface type ++ adapter->isprimary = _FALSE; ++ adapter->adapter_type = SECONDARY_ADAPTER; ++ adapter->iface_type = IFACE_PORT1; ++ DBG_871X("%s(): SECONDARY_ADAPTER\n",__FUNCTION__); ++ } ++#endif ++ }else { ++ pbuddy_padapter = NULL; ++ } ++exit: ++ return status; ++} ++#ifdef CONFIG_WOWLAN ++void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct in_device *my_ip_ptr = padapter->pnetdev->ip_ptr; ++ u8 ipaddress[4]; ++ ++ if ( (pmlmeinfo->state & WIFI_FW_LINKING_STATE) ) { ++ if ( my_ip_ptr != NULL ) { ++ struct in_ifaddr *my_ifa_list = my_ip_ptr->ifa_list ; ++ if ( my_ifa_list != NULL ) { ++ ipaddress[0] = my_ifa_list->ifa_address & 0xFF; ++ ipaddress[1] = (my_ifa_list->ifa_address >> 8) & 0xFF; ++ ipaddress[2] = (my_ifa_list->ifa_address >> 16) & 0xFF; ++ ipaddress[3] = my_ifa_list->ifa_address >> 24; ++ DBG_871X("%s: %d.%d.%d.%d ==========\n", __func__, ++ ipaddress[0], ipaddress[1], ipaddress[2], ipaddress[3]); ++ _rtw_memcpy(pcurrentip, ipaddress, 4); ++ } ++ } ++ } ++} ++void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr) ++{ ++ struct sta_info *psta; ++ struct security_priv *psecpriv = &padapter->securitypriv; ++ ++ _rtw_memset(pcur_dot11txpn, 0, 8); ++ if(NULL == StaAddr) ++ return; ++ psta = rtw_get_stainfo(&padapter->stapriv, StaAddr); ++ DBG_871X("%s(): StaAddr: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", ++ __func__, StaAddr[0], StaAddr[1], StaAddr[2], StaAddr[3], StaAddr[4], StaAddr[5]); ++ ++ if(psta) ++ { ++ if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ && psta->dot11txpn.val > 0) ++ psta->dot11txpn.val--; ++ ++ _rtw_memcpy(pcur_dot11txpn, (u8*)&psta->dot11txpn, 8); ++ ++ DBG_871X("%s(): CurrentIV: 0x%016llx\n", __func__, psta->dot11txpn.val); ++ } ++} ++void rtw_set_sec_iv(PADAPTER padapter) ++{ ++ struct sta_info *psta; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct security_priv *psecpriv = &padapter->securitypriv; ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&pmlmeinfo->network)); ++ ++ if(psta) ++ { ++ if (pwrpriv->wowlan_fw_iv > psta->dot11txpn.val) ++ { ++ if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) ++ psta->dot11txpn.val = pwrpriv->wowlan_fw_iv + 2; ++ } else { ++ DBG_871X("%s(): FW IV is smaller than driver\n", __func__); ++ psta->dot11txpn.val += 2; ++ } ++ DBG_871X("%s: dot11txpn: 0x%016llx\n", __func__ ,psta->dot11txpn.val); ++ } ++} ++#endif //CONFIG_WOWLAN +diff --git a/drivers/net/wireless/rtl818x/rtl8189/core/rtw_xmit.c b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_xmit.c +new file mode 100644 +index 00000000..73043534 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/core/rtw_xmit.c +@@ -0,0 +1,4469 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_XMIT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++#include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++ ++static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; ++static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; ++ ++static void _init_txservq(struct tx_servq *ptxservq) ++{ ++_func_enter_; ++ _rtw_init_listhead(&ptxservq->tx_pending); ++ _rtw_init_queue(&ptxservq->sta_pending); ++ ptxservq->qcnt = 0; ++_func_exit_; ++} ++ ++ ++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) ++{ ++ ++_func_enter_; ++ ++ _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof (struct sta_xmit_priv)); ++ ++ _rtw_spinlock_init(&psta_xmitpriv->lock); ++ ++ //for(i = 0 ; i < MAX_NUMBLKS; i++) ++ // _init_txservq(&(psta_xmitpriv->blk_q[i])); ++ ++ _init_txservq(&psta_xmitpriv->be_q); ++ _init_txservq(&psta_xmitpriv->bk_q); ++ _init_txservq(&psta_xmitpriv->vi_q); ++ _init_txservq(&psta_xmitpriv->vo_q); ++ _rtw_init_listhead(&psta_xmitpriv->legacy_dz); ++ _rtw_init_listhead(&psta_xmitpriv->apsd); ++ ++_func_exit_; ++ ++} ++ ++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) ++{ ++ int i; ++ struct xmit_buf *pxmitbuf; ++ struct xmit_frame *pxframe; ++ sint res=_SUCCESS; ++ u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; ++ u32 num_xmit_extbuf = NR_XMIT_EXTBUFF; ++ ++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723A) ++ if (padapter->registrypriv.mp_mode) { ++ max_xmit_extbuf_size = 6000; ++ num_xmit_extbuf = 8; ++ } ++#endif ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); ++ ++ _rtw_spinlock_init(&pxmitpriv->lock); ++ _rtw_spinlock_init(&pxmitpriv->lock_sctx); ++ _rtw_init_sema(&pxmitpriv->xmit_sema, 0); ++ _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0); ++ ++ /* ++ Please insert all the queue initializaiton using _rtw_init_queue below ++ */ ++ ++ pxmitpriv->adapter = padapter; ++ ++ //for(i = 0 ; i < MAX_NUMBLKS; i++) ++ // _rtw_init_queue(&pxmitpriv->blk_strms[i]); ++ ++ _rtw_init_queue(&pxmitpriv->be_pending); ++ _rtw_init_queue(&pxmitpriv->bk_pending); ++ _rtw_init_queue(&pxmitpriv->vi_pending); ++ _rtw_init_queue(&pxmitpriv->vo_pending); ++ _rtw_init_queue(&pxmitpriv->bm_pending); ++ ++ //_rtw_init_queue(&pxmitpriv->legacy_dz_queue); ++ //_rtw_init_queue(&pxmitpriv->apsd_queue); ++ ++ _rtw_init_queue(&pxmitpriv->free_xmit_queue); ++ ++ /* ++ Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, ++ and initialize free_xmit_frame below. ++ Please also apply free_txobj to link_up all the xmit_frames... ++ */ ++ ++ pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4); ++ ++ if (pxmitpriv->pallocated_frame_buf == NULL){ ++ pxmitpriv->pxmit_frame_buf =NULL; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_frame fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4); ++ //pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - ++ // ((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); ++ ++ pxframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; ++ ++ for (i = 0; i < NR_XMITFRAME; i++) ++ { ++ _rtw_init_listhead(&(pxframe->list)); ++ ++ pxframe->padapter = padapter; ++ pxframe->frame_tag = NULL_FRAMETAG; ++ ++ pxframe->pkt = NULL; ++ ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue)); ++ ++ pxframe++; ++ } ++ ++ pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME; ++ ++ pxmitpriv->frag_len = MAX_FRAG_THRESHOLD; ++ ++ ++ //init xmit_buf ++ _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue); ++ _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue); ++ ++ pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); ++ ++ if (pxmitpriv->pallocated_xmitbuf == NULL){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_buf fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4); ++ //pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - ++ // ((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); ++ ++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmitbuf; ++ ++ for (i = 0; i < NR_XMITBUFF; i++) ++ { ++ _rtw_init_listhead(&pxmitbuf->list); ++ ++ pxmitbuf->priv_data = NULL; ++ pxmitbuf->padapter = padapter; ++ pxmitbuf->ext_tag = _FALSE; ++ ++/* ++ pxmitbuf->pallocated_buf = rtw_zmalloc(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++ //pxmitbuf->pbuf = pxmitbuf->pallocated_buf + XMITBUF_ALIGN_SZ -((SIZE_PTR) (pxmitbuf->pallocated_buf) &(XMITBUF_ALIGN_SZ-1)); ++*/ ++ /* Tx buf allocation may fail sometimes, so sleep and retry. */ ++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ))) == _FAIL) { ++ rtw_msleep_os(10); ++ res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ)); ++ if (res == _FAIL) { ++ goto exit; ++ } ++ } ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->phead = pxmitbuf->pbuf; ++ pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ; ++ pxmitbuf->len = 0; ++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; ++#endif ++ ++ pxmitbuf->flags = XMIT_VO_QUEUE; ++ ++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue)); ++ #ifdef DBG_XMIT_BUF ++ pxmitbuf->no=i; ++ #endif ++ ++ pxmitbuf++; ++ ++ } ++ ++ pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF; ++ ++ /* init xframe_ext queue, the same count as extbuf */ ++ _rtw_init_queue(&pxmitpriv->free_xframe_ext_queue); ++ ++ pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_frame) + 4); ++ ++ if (pxmitpriv->xframe_ext_alloc_addr == NULL){ ++ pxmitpriv->xframe_ext = NULL; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xframe_ext fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4); ++ pxframe = (struct xmit_frame*)pxmitpriv->xframe_ext; ++ ++ for (i = 0; i < num_xmit_extbuf; i++) { ++ _rtw_init_listhead(&(pxframe->list)); ++ ++ pxframe->padapter = padapter; ++ pxframe->frame_tag = NULL_FRAMETAG; ++ ++ pxframe->pkt = NULL; ++ ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ pxframe->ext_tag = 1; ++ ++ rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue)); ++ ++ pxframe++; ++ } ++ pxmitpriv->free_xframe_ext_cnt = num_xmit_extbuf; ++ ++ // Init xmit extension buff ++ _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); ++ ++ pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4); ++ ++ if (pxmitpriv->pallocated_xmit_extbuf == NULL){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); ++ ++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmit_extbuf; ++ ++ for (i = 0; i < num_xmit_extbuf; i++) ++ { ++ _rtw_init_listhead(&pxmitbuf->list); ++ ++ pxmitbuf->priv_data = NULL; ++ pxmitbuf->padapter = padapter; ++ pxmitbuf->ext_tag = _TRUE; ++ ++/* ++ pxmitbuf->pallocated_buf = rtw_zmalloc(max_xmit_extbuf_size); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), 4); ++*/ ++ ++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,max_xmit_extbuf_size + XMITBUF_ALIGN_SZ)) == _FAIL) { ++ res= _FAIL; ++ goto exit; ++ } ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->phead = pxmitbuf->pbuf; ++ pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size; ++ pxmitbuf->len = 0; ++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; ++#endif ++ ++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); ++ #ifdef DBG_XMIT_BUF_EXT ++ pxmitbuf->no=i; ++ #endif ++ pxmitbuf++; ++ ++ } ++ ++ pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf; ++ ++ rtw_alloc_hwxmits(padapter); ++ rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); ++ ++ for (i = 0; i < 4; i ++) ++ { ++ pxmitpriv->wmm_para_seq[i] = i; ++ } ++ ++#ifdef CONFIG_USB_HCI ++ pxmitpriv->txirp_cnt=1; ++ ++ _rtw_init_sema(&(pxmitpriv->tx_retevt), 0); ++ ++ //per AC pending irp ++ pxmitpriv->beq_cnt = 0; ++ pxmitpriv->bkq_cnt = 0; ++ pxmitpriv->viq_cnt = 0; ++ pxmitpriv->voq_cnt = 0; ++#endif ++ ++ ++#ifdef CONFIG_XMIT_ACK ++ pxmitpriv->ack_tx = _FALSE; ++ _rtw_mutex_init(&pxmitpriv->ack_tx_mutex); ++ rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0); ++#endif ++ ++ rtw_hal_init_xmit_priv(padapter); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv); ++void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv) ++{ ++ _rtw_spinlock_free(&pxmitpriv->lock); ++ _rtw_free_sema(&pxmitpriv->xmit_sema); ++ _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema); ++ ++ _rtw_spinlock_free(&pxmitpriv->be_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->vi_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->vo_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->bm_pending.lock); ++ ++ //_rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); ++ //_rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); ++ ++ _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock); ++ _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock); ++ _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock); ++} ++ ++ ++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv) ++{ ++ int i; ++ _adapter *padapter = pxmitpriv->adapter; ++ struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; ++ u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; ++ u32 num_xmit_extbuf = NR_XMIT_EXTBUFF; ++ ++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723A) ++ if (padapter->registrypriv.mp_mode) { ++ max_xmit_extbuf_size = 6000; ++ num_xmit_extbuf = 8; ++ } ++#endif ++ ++ _func_enter_; ++ ++ rtw_hal_free_xmit_priv(padapter); ++ ++ rtw_mfree_xmit_priv_lock(pxmitpriv); ++ ++ if(pxmitpriv->pxmit_frame_buf==NULL) ++ goto out; ++ ++ for(i=0; ipallocated_buf) ++ // rtw_mfree(pxmitbuf->pallocated_buf, MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ); ++ ++ pxmitbuf++; ++ } ++ ++ if(pxmitpriv->pallocated_frame_buf) { ++ rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4); ++ } ++ ++ ++ if(pxmitpriv->pallocated_xmitbuf) { ++ rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4); ++ } ++ ++ /* free xframe_ext queue, the same count as extbuf */ ++ if ((pxmitframe = (struct xmit_frame*)pxmitpriv->xframe_ext)) { ++ for (i=0; ixframe_ext_alloc_addr) ++ rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, num_xmit_extbuf * sizeof(struct xmit_frame) + 4); ++ _rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock); ++ ++ // free xmit extension buff ++ _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock); ++ ++ pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; ++ for(i=0; ipallocated_buf) ++ // rtw_mfree(pxmitbuf->pallocated_buf, max_xmit_extbuf_size); ++ ++ pxmitbuf++; ++ } ++ ++ if(pxmitpriv->pallocated_xmit_extbuf) { ++ rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4); ++ } ++ ++ rtw_free_hwxmits(padapter); ++ ++#ifdef CONFIG_XMIT_ACK ++ _rtw_mutex_free(&pxmitpriv->ack_tx_mutex); ++#endif ++ ++out: ++ ++_func_exit_; ++ ++} ++ ++static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ u32 sz; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *psta = pattrib->psta; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pattrib->psta) ++ { ++ psta = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); ++ } ++ ++ if(psta==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return; ++ } ++ ++ if (pattrib->nr_frags != 1) ++ { ++ sz = padapter->xmitpriv.frag_len; ++ } ++ else //no frag ++ { ++ sz = pattrib->last_txcmdsz; ++ } ++ ++ // (1) RTS_Threshold is compared to the MPDU, not MSDU. ++ // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. ++ // Other fragments are protected by previous fragment. ++ // So we only need to check the length of first fragment. ++ if(pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec) ++ { ++ if(sz > padapter->registrypriv.rts_thresh) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ } ++ else ++ { ++ if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ else ++ pattrib->vcs_mode = NONE_VCS; ++ } ++ } ++ else ++ { ++ while (_TRUE) ++ { ++#if 0 //Todo ++ //check IOT action ++ if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) ++ { ++ pattrib->vcs_mode = CTS_TO_SELF; ++ pattrib->rts_rate = MGN_24M; ++ break; ++ } ++ else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE)) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ pattrib->rts_rate = MGN_24M; ++ break; ++ } ++#endif ++ ++ //IOT action ++ if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en==_TRUE) && ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )) ++ { ++ pattrib->vcs_mode = CTS_TO_SELF; ++ break; ++ } ++ ++ ++ //check ERP protection ++ if(psta->rtsen || psta->cts2self) ++ { ++ if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ ++ break; ++ } ++ ++ //check HT op mode ++ if(pattrib->ht_en) ++ { ++ u8 HTOpMode = pmlmeinfo->HT_protection; ++ if((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) || ++ (!pmlmeext->cur_bwmode && HTOpMode == 3) ) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ } ++ ++ //check rts ++ if(sz > padapter->registrypriv.rts_thresh) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ ++ //to do list: check MIMO power save condition. ++ ++ //check AMPDU aggregation for TXOP ++ if(pattrib->ampdu_en==_TRUE) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ ++ pattrib->vcs_mode = NONE_VCS; ++ break; ++ } ++ } ++} ++ ++static void update_attrib_phy_info(struct pkt_attrib *pattrib, struct sta_info *psta) ++{ ++ /*if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ else ++ pattrib->vcs_mode = NONE_VCS;*/ ++ ++ pattrib->mdata = 0; ++ pattrib->eosp = 0; ++ pattrib->triggered=0; ++ ++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi ++ pattrib->qos_en = psta->qos_option; ++ ++ pattrib->raid = psta->raid; ++#ifdef CONFIG_80211N_HT ++ pattrib->ht_en = psta->htpriv.ht_option; ++ pattrib->bwmode = psta->htpriv.bwmode; ++ pattrib->ch_offset = psta->htpriv.ch_offset; ++ pattrib->sgi= psta->htpriv.sgi; ++ pattrib->ampdu_en = _FALSE; ++#endif //CONFIG_80211N_HT ++ //if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ //{ ++ // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ // pattrib->ampdu_en = _TRUE; ++ //} ++ ++ ++ pattrib->retry_ctrl = _FALSE; ++ ++} ++ ++u8 qos_acm(u8 acm_mask, u8 priority) ++{ ++ u8 change_priority = priority; ++ ++ switch (priority) ++ { ++ case 0: ++ case 3: ++ if(acm_mask & BIT(1)) ++ change_priority = 1; ++ break; ++ case 1: ++ case 2: ++ break; ++ case 4: ++ case 5: ++ if(acm_mask & BIT(2)) ++ change_priority = 0; ++ break; ++ case 6: ++ case 7: ++ if(acm_mask & BIT(3)) ++ change_priority = 5; ++ break; ++ default: ++ DBG_871X("qos_acm(): invalid pattrib->priority: %d!!!\n", priority); ++ break; ++ } ++ ++ return change_priority; ++} ++ ++static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib) ++{ ++ struct ethhdr etherhdr; ++ struct iphdr ip_hdr; ++ s32 UserPriority = 0; ++ ++ ++ _rtw_open_pktfile(ppktfile->pkt, ppktfile); ++ _rtw_pktfile_read(ppktfile, (unsigned char*)ðerhdr, ETH_HLEN); ++ ++ // get UserPriority from IP hdr ++ if (pattrib->ether_type == 0x0800) { ++ _rtw_pktfile_read(ppktfile, (u8*)&ip_hdr, sizeof(ip_hdr)); ++// UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; ++ UserPriority = ip_hdr.tos >> 5; ++ } else if (pattrib->ether_type == 0x888e) { ++ // "When priority processing of data frames is supported, ++ // a STA's SME should send EAPOL-Key frames at the highest priority." ++ UserPriority = 7; ++ } ++ ++ pattrib->priority = UserPriority; ++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; ++ pattrib->subtype = WIFI_QOS_DATA_TYPE; ++} ++ ++static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) ++{ ++ uint i; ++ struct pkt_file pktfile; ++ struct sta_info *psta = NULL; ++ struct ethhdr etherhdr; ++ ++ sint bmcast; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ sint res = _SUCCESS; ++ ++ _func_enter_; ++ ++ _rtw_open_pktfile(pkt, &pktfile); ++ i = _rtw_pktfile_read(&pktfile, (u8*)ðerhdr, ETH_HLEN); ++ ++ pattrib->ether_type = ntohs(etherhdr.h_proto); ++ ++ ++ _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); ++ ++ pattrib->pctrl = 0; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN); ++ } ++ ++ pattrib->pktlen = pktfile.pkt_len; ++ ++ if (ETH_P_IP == pattrib->ether_type) ++ { ++ // The following is for DHCP and ARP packet, we use cck1M to tx these packets and let LPS awake some time ++ // to prevent DHCP protocol fail ++ u8 tmp[24]; ++ _rtw_pktfile_read(&pktfile, &tmp[0], 24); ++ pattrib->dhcp_pkt = 0; ++ if (pktfile.pkt_len > 282) {//MINIMUM_DHCP_PACKET_SIZE) { ++ if (ETH_P_IP == pattrib->ether_type) {// IP header ++ if (((tmp[21] == 68) && (tmp[23] == 67)) || ++ ((tmp[21] == 67) && (tmp[23] == 68))) { ++ // 68 : UDP BOOTP client ++ // 67 : UDP BOOTP server ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("======================update_attrib: get DHCP Packet \n")); ++ // Use low rate to send DHCP packet. ++ //if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) ++ //{ ++ // tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m ++ // tcb_desc->bTxDisableRateFallBack = false; ++ //} ++ //else ++ // pTcb->DataRate = Adapter->MgntInfo.LowestBasicRate; ++ //RTPRINT(FDM, WA_IOT, ("DHCP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate)); ++ pattrib->dhcp_pkt = 1; ++ } ++ } ++ } ++ } else if (0x888e == pattrib->ether_type) { ++ DBG_871X_LEVEL(_drv_always_, "send eapol packet\n"); ++ } ++ ++ if ( (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) ++ { ++ rtw_set_scan_deny(padapter, 3000); ++ } ++ ++#ifdef CONFIG_LPS ++ // If EAPOL , ARP , OR DHCP packet, driver must be in active mode. ++#ifdef CONFIG_WAPI_SUPPORT ++ if ( (pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) ++#else ++ if ( (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) ++#endif ++ { ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1); ++ } ++#endif ++ ++ bmcast = IS_MCAST(pattrib->ra); ++ ++ // get sta_info ++ if (bmcast) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ if (psta == NULL) { // if we cannot get psta => drrp the pkt ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra))); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra)); ++ #endif ++ res =_FAIL; ++ goto exit; ++ } ++ else if((check_fwstate(pmlmepriv, WIFI_AP_STATE)==_TRUE)&&(!(psta->state & _FW_LINKED))) ++ { ++ res =_FAIL; ++ goto exit; ++ } ++ } ++ ++ if (psta) ++ { ++ pattrib->mac_id = psta->mac_id; ++ //DBG_8192C("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); ++ pattrib->psta = psta; ++ } ++ else ++ { ++ // if we cannot get psta => drop the pkt ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra))); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra)); ++ #endif ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pattrib->ack_policy = 0; ++ // get ether_hdr_len ++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag ++ ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA_TYPE; ++ pattrib->priority = 0; ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ if(psta->qos_option) ++ set_qos(&pktfile, pattrib); ++ } ++ else ++ { ++ if(pqospriv->qos_option) ++ { ++ set_qos(&pktfile, pattrib); ++ ++ if(pmlmepriv->acm_mask != 0) ++ { ++ pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority); ++ } ++ } ++ } ++ ++ //pattrib->priority = 5; //force to used VI queue, for testing ++ ++ if (psta->ieee8021x_blocked == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n psta->ieee8021x_blocked == _TRUE \n")); ++ ++ pattrib->encrypt = 0; ++ ++ if((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n",pattrib->ether_type)); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__,pattrib->ether_type); ++ #endif ++ res = _FAIL; ++ goto exit; ++ } ++ } ++ else ++ { ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(pattrib->ether_type == 0x88B4) ++ pattrib->encrypt=_NO_PRIVACY_; ++#endif ++ ++ switch(psecuritypriv->dot11AuthAlgrthm) ++ { ++ case dot11AuthAlgrthm_Open: ++ case dot11AuthAlgrthm_Shared: ++ case dot11AuthAlgrthm_Auto: ++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case dot11AuthAlgrthm_8021X: ++ if(bmcast) ++ pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid; ++ else ++ pattrib->key_idx = 0; ++ break; ++ default: ++ pattrib->key_idx = 0; ++ break; ++ } ++ ++ ++ } ++ ++ switch (pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ pattrib->iv_len = 4; ++ pattrib->icv_len = 4; ++ break; ++ ++ case _TKIP_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 4; ++ ++ if(padapter->securitypriv.busetkipkey==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npadapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", padapter->securitypriv.busetkipkey)); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s padapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, padapter->securitypriv.busetkipkey); ++ #endif ++ res =_FAIL; ++ goto exit; ++ } ++ ++ break; ++ case _AES_: ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("pattrib->encrypt=%d (_AES_)\n",pattrib->encrypt)); ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 8; ++ break; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ pattrib->iv_len = 18; ++ pattrib->icv_len = 16; ++ break; ++#endif ++ ++ default: ++ pattrib->iv_len = 0; ++ pattrib->icv_len = 0; ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ++ ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n", ++ pattrib->encrypt, padapter->securitypriv.sw_encrypt)); ++ ++ if (pattrib->encrypt && ++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) ++ { ++ pattrib->bswenc = _TRUE; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_, ++ ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n", ++ pattrib->encrypt, padapter->securitypriv.sw_encrypt)); ++ } else { ++ pattrib->bswenc = _FALSE; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("update_attrib: bswenc=_FALSE\n")); ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if((pattrib->encrypt && bmcast) || (pattrib->encrypt ==_WEP40_) || (pattrib->encrypt ==_WEP104_)) ++ { ++ pattrib->bswenc = _TRUE;//force using sw enc. ++ } ++#endif ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(pattrib->encrypt == _SMS4_) ++ pattrib->bswenc = _FALSE; ++#endif ++ ++ rtw_set_tx_chksum_offload(pkt, pattrib); ++ ++ update_attrib_phy_info(pattrib, psta); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe){ ++ sint curfragnum,length; ++ u8 *pframe, *payload,mic[8]; ++ struct mic_data micdata; ++ struct sta_info *stainfo; ++ struct qos_priv *pqospriv= &(padapter->mlmepriv.qospriv); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ u8 priority[4]={0x0,0x0,0x0,0x0}; ++ u8 hw_hdr_offset = 0; ++ sint bmcst = IS_MCAST(pattrib->ra); ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); ++ } ++ ++ if(stainfo==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return _FAIL; ++ } ++ ++ if(!(stainfo->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); ++ return _FAIL; ++ } ++ ++_func_enter_; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);; ++#else ++ #ifdef CONFIG_TX_EARLY_MODE ++ hw_hdr_offset = TXDESC_OFFSET+ EARLY_MODE_INFO_SIZE; ++ #else ++ hw_hdr_offset = TXDESC_OFFSET; ++ #endif ++#endif ++ ++ if(pattrib->encrypt ==_TKIP_)//if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) ++ { ++ //encode mic code ++ if(stainfo!= NULL){ ++ u8 null_key[16]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; ++ ++ pframe = pxmitframe->buf_addr + hw_hdr_offset; ++ ++ if(bmcst) ++ { ++ if(_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16)==_TRUE){ ++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); ++ //rtw_msleep_os(10); ++ return _FAIL; ++ } ++ //start to calculate the mic code ++ rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); ++ } ++ else ++ { ++ if(_rtw_memcmp(&stainfo->dot11tkiptxmickey.skey[0],null_key, 16)==_TRUE){ ++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); ++ //rtw_msleep_os(10); ++ return _FAIL; ++ } ++ //start to calculate the mic code ++ rtw_secmicsetkey(&micdata, &stainfo->dot11tkiptxmickey.skey[0]); ++ } ++ ++ if(pframe[1]&1){ //ToDS==1 ++ rtw_secmicappend(&micdata, &pframe[16], 6); //DA ++ if(pframe[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &pframe[24], 6); ++ else ++ rtw_secmicappend(&micdata, &pframe[10], 6); ++ } ++ else{ //ToDS==0 ++ rtw_secmicappend(&micdata, &pframe[4], 6); //DA ++ if(pframe[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &pframe[16], 6); ++ else ++ rtw_secmicappend(&micdata, &pframe[10], 6); ++ ++ } ++ ++ //if(pqospriv->qos_option==1) ++ if(pattrib->qos_en) ++ priority[0]=(u8)pxmitframe->attrib.priority; ++ ++ ++ rtw_secmicappend(&micdata, &priority[0], 4); ++ ++ payload=pframe; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ payload=(u8 *)RND4((SIZE_PTR)(payload)); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n", ++ curfragnum,*payload, *(payload+1),*(payload+2),*(payload+3),*(payload+4),*(payload+5),*(payload+6),*(payload+7))); ++ ++ payload=payload+pattrib->hdrlen+pattrib->iv_len; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d",curfragnum,pattrib->hdrlen,pattrib->iv_len)); ++ if((curfragnum+1)==pattrib->nr_frags){ ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); ++ rtw_secmicappend(&micdata, payload,length); ++ payload=payload+length; ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); ++ rtw_secmicappend(&micdata, payload, length); ++ payload=payload+length+pattrib->icv_len; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d length=%d pattrib->icv_len=%d",curfragnum,length,pattrib->icv_len)); ++ } ++ } ++ rtw_secgetmic(&micdata,&(mic[0])); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: before add mic code!!!\n")); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n",pattrib->last_txcmdsz)); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\ ++ mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n", ++ mic[0],mic[1],mic[2],mic[3],mic[4],mic[5],mic[6],mic[7])); ++ //add mic code and add the mic code length in last_txcmdsz ++ ++ _rtw_memcpy(payload, &(mic[0]),8); ++ pattrib->last_txcmdsz+=8; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("\n ========last pkt========\n")); ++ payload=payload-pattrib->last_txcmdsz+8; ++ for(curfragnum=0;curfragnumlast_txcmdsz;curfragnum=curfragnum+8) ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,(" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ", ++ *(payload+curfragnum), *(payload+curfragnum+1), *(payload+curfragnum+2),*(payload+curfragnum+3), ++ *(payload+curfragnum+4),*(payload+curfragnum+5),*(payload+curfragnum+6),*(payload+curfragnum+7))); ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n")); ++ } ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe){ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ //struct security_priv *psecuritypriv=&padapter->securitypriv; ++ ++_func_enter_; ++ ++ //if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) ++ if(pattrib->bswenc) ++ { ++ //DBG_871X("start xmitframe_swencrypt\n"); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_alert_,("### xmitframe_swencrypt\n")); ++ switch(pattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ rtw_wep_encrypt(padapter, (u8 *)pxmitframe); ++ break; ++ case _TKIP_: ++ rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); ++ break; ++ case _AES_: ++ rtw_aes_encrypt(padapter, (u8 * )pxmitframe); ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ rtw_sms4_encrypt(padapter, (u8 * )pxmitframe); ++#endif ++ default: ++ break; ++ } ++ ++ } else { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_notice_,("### xmitframe_hwencrypt\n")); ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) ++{ ++ u16 *qc; ++ ++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv = &pmlmepriv->qospriv; ++ u8 qos_option = _FALSE; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta=NULL, *psta_backup=NULL; ++ u8 direct_link=0; ++#endif //CONFIG_TDLS ++ ++ sint res = _SUCCESS; ++ u16 *fctrl = &pwlanhdr->frame_ctl; ++ ++ struct sta_info *psta; ++ ++ sint bmcst = IS_MCAST(pattrib->ra); ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ if(bmcst) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ } ++ ++ if(psta==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return _FAIL; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return _FAIL; ++ } ++ ++ _rtw_memset(hdr, 0, WLANHDR_OFFSET); ++ ++ SetFrameSubType(fctrl, pattrib->subtype); ++ ++ if (pattrib->subtype & WIFI_DATA_TYPE) ++ { ++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { ++ //to_ds = 1, fr_ds = 0; ++#ifdef CONFIG_TDLS ++ if((ptdlsinfo->setup_state == TDLS_LINKED_STATE)){ ++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ if((ptdls_sta!=NULL)&&(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)&&(pattrib->ether_type!=0x0806)){ ++ //TDLS data transfer, ToDS=0, FrDs=0 ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ direct_link=1; ++ }else{ ++ // 1.Data transfer to AP ++ // 2.Arp pkt will relayed by AP ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ }else ++#endif //CONFIG_TDLS ++ { ++ //Data transfer to AP ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ ++ if (pqospriv->qos_option) ++ qos_option = _TRUE; ++ ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ) { ++ //to_ds = 0, fr_ds = 1; ++ SetFrDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); ++ ++ if(psta->qos_option) ++ qos_option = _TRUE; ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ ++ if(psta->qos_option) ++ qos_option = _TRUE; ++ } ++ else { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv))); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ if(pattrib->mdata) ++ SetMData(fctrl); ++ ++ if (pattrib->encrypt) ++ SetPrivacy(fctrl); ++ ++ if (qos_option) ++ { ++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); ++ ++ if (pattrib->priority) ++ SetPriority(qc, pattrib->priority); ++ ++ SetEOSP(qc, pattrib->eosp); ++ ++ SetAckpolicy(qc, pattrib->ack_policy); ++ } ++ ++ //TODO: fill HT Control Field ++ ++ //Update Seq Num will be handled by f/w ++ { ++ if(psta){ ++#ifdef CONFIG_TDLS ++ if(direct_link==1) ++ { ++ psta_backup = psta; ++ psta = ptdls_sta; ++ } ++#endif //CONFIG_TDLS ++ ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ ++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ ++ SetSeqNum(hdr, pattrib->seqnum); ++ ++#ifdef CONFIG_80211N_HT ++ //check if enable ampdu ++ if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ { ++ if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ pattrib->ampdu_en = _TRUE; ++ } ++ ++ //re-check if enable ampdu by BA_starting_seqctrl ++ if(pattrib->ampdu_en == _TRUE) ++ { ++ u16 tx_seq; ++ ++ tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; ++ ++ //check BA_starting_seqctrl ++ if(SN_LESS(pattrib->seqnum, tx_seq)) ++ { ++ //DBG_871X("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); ++ pattrib->ampdu_en = _FALSE;//AGG BK ++ } ++ else if(SN_EQUAL(pattrib->seqnum, tx_seq)) ++ { ++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq+1)&0xfff; ++ ++ pattrib->ampdu_en = _TRUE;//AGG EN ++ } ++ else ++ { ++ //DBG_871X("tx ampdu over run\n"); ++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum+1)&0xfff; ++ pattrib->ampdu_en = _TRUE;//AGG EN ++ } ++ ++ } ++#endif //CONFIG_80211N_HT ++#ifdef CONFIG_TDLS ++ if(direct_link==1) ++ { ++ if (pattrib->encrypt){ ++ pattrib->encrypt= _AES_; ++ pattrib->iv_len=8; ++ pattrib->icv_len=8; ++ } ++ ++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi ++ //pattrib->qos_en = ptdls_sta->qos_option; ++ ++ pattrib->raid = ptdls_sta->raid; ++#ifdef CONFIG_80211N_HT ++ pattrib->bwmode = ptdls_sta->htpriv.bwmode; ++ pattrib->ht_en = ptdls_sta->htpriv.ht_option; ++ pattrib->ch_offset = ptdls_sta->htpriv.ch_offset; ++ pattrib->sgi= ptdls_sta->htpriv.sgi; ++#endif //CONFIG_80211N_HT ++ pattrib->mac_id = ptdls_sta->mac_id; ++ ++ psta = psta_backup; ++ } ++#endif //CONFIG_TDLS ++ ++ } ++ } ++ ++ } ++ else ++ { ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++s32 rtw_txframes_pending(_adapter *padapter) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)); ++} ++ ++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ int priority = pattrib->priority; ++ ++ if(pattrib->psta) ++ { ++ psta = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); ++ } ++ ++ if(psta==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return 0; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return 0; ++ } ++ ++ switch(priority) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ break; ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ break; ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ break; ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ break; ++ ++ } ++ ++ return ptxservq->qcnt; ++} ++ ++#ifdef CONFIG_TDLS ++ ++int rtw_build_tdls_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 action) ++{ ++ int res=_SUCCESS; ++ ++ switch(action){ ++ case TDLS_SETUP_REQUEST: ++ rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_SETUP_RESPONSE: ++ rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_SETUP_CONFIRM: ++ rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_TEARDOWN: ++ rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_DISCOVERY_REQUEST: ++ rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_PEER_TRAFFIC_INDICATION: ++ rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe); ++ break; ++#ifdef CONFIG_WFD ++ case TUNNELED_PROBE_REQ: ++ rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe); ++ break; ++ case TUNNELED_PROBE_RSP: ++ rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe); ++ break; ++#endif //CONFIG_WFD ++ default: ++ res=_FAIL; ++ break; ++ } ++ ++ return res; ++} ++ ++s32 rtw_make_tdls_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, u8 action) ++{ ++ u16 *qc; ++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv = &pmlmepriv->qospriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL, *ptdls_sta=NULL; ++ u8 tdls_seq=0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; ++ ++ sint res = _SUCCESS; ++ u16 *fctrl = &pwlanhdr->frame_ctl; ++ ++_func_enter_; ++ ++ _rtw_memset(hdr, 0, WLANHDR_OFFSET); ++ ++ SetFrameSubType(fctrl, pattrib->subtype); ++ ++ switch(action){ ++ case TDLS_SETUP_REQUEST: ++ case TDLS_SETUP_RESPONSE: ++ case TDLS_SETUP_CONFIRM: ++ case TDLS_TEARDOWN: //directly to peer STA or via AP ++ case TDLS_PEER_TRAFFIC_INDICATION: ++ case TDLS_PEER_PSM_REQUEST: //directly to peer STA or via AP ++ case TUNNELED_PROBE_REQ: ++ case TUNNELED_PROBE_RSP: ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ case TDLS_PEER_PSM_RESPONSE: ++ case TDLS_PEER_TRAFFIC_RESPONSE: ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ tdls_seq=1; ++ break; ++ case TDLS_DISCOVERY_REQUEST: //unicast: directly to peer sta, Bcast: via AP ++ if(_rtw_memcmp(pattrib->dst, baddr, ETH_ALEN) ) ++ { ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ else ++ { ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ tdls_seq=1; ++ } ++ break; ++ } ++ ++ if (pattrib->encrypt) ++ SetPrivacy(fctrl); ++ ++ if (pqospriv->qos_option) ++ { ++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); ++ if (pattrib->priority) ++ SetPriority(qc, pattrib->priority); ++ SetAckpolicy(qc, pattrib->ack_policy); ++ } ++ ++ psta = pattrib->psta; ++ ++ // 1. update seq_num per link by sta_info ++ // 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len ++ if(tdls_seq==1){ ++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); ++ if(ptdls_sta){ ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(hdr, pattrib->seqnum); ++ ++ if (pattrib->encrypt){ ++ pattrib->encrypt= _AES_; ++ pattrib->iv_len=8; ++ pattrib->icv_len=8; ++ } ++ }else{ ++ res=_FAIL; ++ goto exit; ++ } ++ }else if(psta){ ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(hdr, pattrib->seqnum); ++ } ++ ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++s32 rtw_xmit_tdls_coalesce(_adapter * padapter, struct xmit_frame * pxmitframe, u8 action) ++{ ++ s32 llc_sz; ++ ++ u8 *pframe, *mem_start; ++ ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 *pbuf_start; ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ s32 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ if(bmcst) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ } ++ ++ if(psta==NULL) ++ return _FAIL; ++ ++ if (pxmitframe->buf_addr == NULL) ++ return _FAIL; ++ ++ pbuf_start = pxmitframe->buf_addr; ++ mem_start = pbuf_start + TXDESC_OFFSET; ++ ++ if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, action) == _FAIL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pframe = mem_start; ++ pframe += pattrib->hdrlen; ++ ++ //adding icv, if necessary... ++ if (pattrib->iv_len) ++ { ++ if (psta != NULL) ++ { ++ switch(pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ break; ++ case _TKIP_: ++ if(bmcst) ++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ case _AES_: ++ if(bmcst) ++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ AES_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ } ++ } ++ ++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); ++ pframe += pattrib->iv_len; ++ ++ } ++ ++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ ++ //pattrib->pktlen will be counted in rtw_build_tdls_ies ++ pattrib->pktlen = 0; ++ ++ rtw_build_tdls_ies(padapter, pxmitframe, pframe, action); ++ ++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { ++ pframe += pattrib->pktlen; ++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); ++ pframe += pattrib->icv_len; ++ } ++ ++ pattrib->nr_frags = 1; ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen; ++ ++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) ++ { ++ goto exit; ++ } ++ ++ xmitframe_swencrypt(padapter, pxmitframe); ++ ++ update_attrib_vcs_info(padapter, pxmitframe); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++#endif //CONFIG_TDLS ++ ++/* ++ * Calculate wlan 802.11 packet MAX size from pkt_attrib ++ * This function doesn't consider fragment case ++ */ ++u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) ++{ ++ u32 len = 0; ++ ++ len = pattrib->hdrlen + pattrib->iv_len; // WLAN Header and IV ++ len += SNAP_SIZE + sizeof(u16); // LLC ++ len += pattrib->pktlen; ++ if (pattrib->encrypt == _TKIP_) len += 8; // MIC ++ len += ((pattrib->bswenc) ? pattrib->icv_len : 0); // ICV ++ ++ return len; ++} ++ ++/* ++ ++This sub-routine will perform all the following: ++ ++1. remove 802.3 header. ++2. create wlan_header, based on the info in pxmitframe ++3. append sta's iv/ext-iv ++4. append LLC ++5. move frag chunk from pframe to pxmitframe->mem ++6. apply sw-encrypt, if necessary. ++ ++*/ ++s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) ++{ ++ struct pkt_file pktfile; ++ ++ s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; ++ ++ SIZE_PTR addr; ++ ++ u8 *pframe, *mem_start; ++ u8 hw_hdr_offset; ++ ++ struct sta_info *psta; ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ //struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ u8 *pbuf_start; ++ ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ s32 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) ++ { ++ psta = pattrib->psta; ++ } else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ { ++ ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return _FAIL; ++ } ++ ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return _FAIL; ++ } ++ ++ if (pxmitframe->buf_addr == NULL){ ++ DBG_8192C("==> %s buf_addr==NULL \n",__FUNCTION__); ++ return _FAIL; ++ } ++ ++ pbuf_start = pxmitframe->buf_addr; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ #ifdef CONFIG_TX_EARLY_MODE //for SDIO && Tx Agg ++ hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; ++ #else ++ hw_hdr_offset = TXDESC_OFFSET; ++ #endif ++#endif ++ ++ mem_start = pbuf_start + hw_hdr_offset; ++ ++ if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); ++ DBG_8192C("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ _rtw_open_pktfile(pkt, &pktfile); ++ _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); ++ ++ frg_inx = 0; ++ frg_len = pxmitpriv->frag_len - 4;//2346-4 = 2342 ++ ++ while (1) ++ { ++ llc_sz = 0; ++ ++ mpdu_len = frg_len; ++ ++ pframe = mem_start; ++ ++ SetMFrag(mem_start); ++ ++ pframe += pattrib->hdrlen; ++ mpdu_len -= pattrib->hdrlen; ++ ++ //adding icv, if necessary... ++ if (pattrib->iv_len) ++ { ++ //if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) ++ // psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ //else ++ // psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ ++ if (psta != NULL) ++ { ++ switch(pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ break; ++ case _TKIP_: ++ if(bmcst) ++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ case _AES_: ++ if(bmcst) ++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ AES_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ rtw_wapi_get_iv(padapter,pattrib->ra,pattrib->iv); ++ break; ++#endif ++ } ++ } ++ ++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, ++ ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", ++ padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe+1), *(pframe+2), *(pframe+3))); ++ ++ pframe += pattrib->iv_len; ++ ++ mpdu_len -= pattrib->iv_len; ++ } ++ ++ if (frg_inx == 0) { ++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ mpdu_len -= llc_sz; ++ } ++ ++ if ((pattrib->icv_len >0) && (pattrib->bswenc)) { ++ mpdu_len -= pattrib->icv_len; ++ } ++ ++ ++ if (bmcst) { ++ // don't do fragment to broadcat/multicast packets ++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); ++ } else { ++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); ++ } ++ ++ pframe += mem_sz; ++ ++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { ++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); ++ pframe += pattrib->icv_len; ++ } ++ ++ frg_inx++; ++ ++ if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) ++ { ++ pattrib->nr_frags = frg_inx; ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags==1)? llc_sz:0) + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; ++ ++ ClearMFrag(mem_start); ++ ++ break; ++ } else { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("%s: There're still something in packet!\n", __FUNCTION__)); ++ } ++ ++ addr = (SIZE_PTR)(pframe); ++ ++ mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset; ++ _rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen); ++ ++ } ++ ++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); ++ DBG_8192C("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ xmitframe_swencrypt(padapter, pxmitframe); ++ ++ if(bmcst == _FALSE) ++ update_attrib_vcs_info(padapter, pxmitframe); ++ else ++ pattrib->vcs_mode = NONE_VCS; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++#ifdef CONFIG_IEEE80211W ++//broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption ++s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) ++{ ++ struct pkt_file pktfile; ++ s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; ++ SIZE_PTR addr; ++ u8 *pframe, *mem_start = NULL, *tmp_buf=NULL; ++ u8 hw_hdr_offset, subtype ; ++ struct sta_info *psta = NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 *pbuf_start; ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ s32 res = _FAIL; ++ u8 *BIP_AAD; ++ u8 *MGMT_body=NULL; ++ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u8 MME[_MME_IE_LENGTH_]; ++ ++ _irqL irqL; ++ u32 ori_len; ++ mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ tmp_buf = BIP_AAD; ++ ++_func_enter_; ++ ori_len = BIP_AAD_SIZE+pattrib->pktlen; ++ tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); ++ subtype = GetFrameSubType(pframe); //bit(7)~bit(2) ++ ++ if(BIP_AAD == NULL) ++ return _FAIL; ++ ++ _enter_critical_bh(&padapter->security_key_mutex, &irqL); ++ ++ //only support station mode ++ if(!check_fwstate(pmlmepriv, WIFI_STATION_STATE) || !check_fwstate(pmlmepriv, _FW_LINKED)) ++ goto xmitframe_coalesce_success; ++ ++ //IGTK key is not install, it may not support 802.11w ++ if(padapter->securitypriv.binstallBIPkey != _TRUE) ++ { ++ DBG_871X("no instll BIP key\n"); ++ goto xmitframe_coalesce_success; ++ } ++ //station mode doesn't need TX BIP, just ready the code ++ if(bmcst) ++ { ++ int frame_body_len; ++ u8 mic[16]; ++ ++ _rtw_memset(MME, 0, 18); ++ ++ //other types doesn't need the BIP ++ if(GetFrameSubType(pframe) != WIFI_DEAUTH && GetFrameSubType(pframe) != WIFI_DISASSOC) ++ goto xmitframe_coalesce_fail; ++ ++ MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ pframe += pattrib->pktlen; ++ ++ //octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 ++ MME[0]=padapter->securitypriv.dot11wBIPKeyid; ++ //copy packet number ++ _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6); ++ //increase the packet number ++ pmlmeext->mgnt_80211w_IPN++; ++ ++ //add MME IE with MIC all zero, MME string doesn't include element id and length ++ pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ // total frame length - header length ++ frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //conscruct AAD, copy frame control field ++ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); ++ ClearRetry(BIP_AAD); ++ ClearPwrMgt(BIP_AAD); ++ ClearMData(BIP_AAD); ++ //conscruct AAD, copy address 1 to address 3 ++ _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18); ++ //copy management fram body ++ _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, MGMT_body, frame_body_len); ++ /*//dump total packet include MME with zero MIC ++ { ++ int i; ++ printk("Total packet: "); ++ for(i=0; i < BIP_AAD_SIZE+frame_body_len; i++) ++ printk(" %02x ", BIP_AAD[i]); ++ printk("\n"); ++ }*/ ++ //calculate mic ++ if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey ++ , BIP_AAD, BIP_AAD_SIZE+frame_body_len, mic)) ++ goto xmitframe_coalesce_fail; ++ ++ /*//dump calculated mic result ++ { ++ int i; ++ printk("Calculated mic result: "); ++ for(i=0; i<16; i++) ++ printk(" %02x ", mic[i]); ++ printk("\n"); ++ }*/ ++ //copy right BIP mic value, total is 128bits, we use the 0~63 bits ++ _rtw_memcpy(pframe-8, mic, 8); ++ /*/dump all packet after mic ok ++ { ++ int pp; ++ printk("pattrib->pktlen = %d \n", pattrib->pktlen); ++ for(pp=0;pp< pattrib->pktlen; pp++) ++ printk(" %02x ", mem_start[pp]); ++ printk("\n"); ++ }*/ ++ } ++ else //unicast mgmt frame TX ++ { ++ //start to encrypt mgmt frame ++ if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || ++ subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION) ++ { ++ if (pattrib->psta) ++ psta = pattrib->psta; ++ else ++ { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ { ++ ++ DBG_871X("%s, psta==NUL\n", __func__); ++ goto xmitframe_coalesce_fail; ++ } ++ ++ if(!(psta->state & _FW_LINKED) || pxmitframe->buf_addr==NULL) ++ { ++ DBG_871X("%s, not _FW_LINKED or addr null\n", __func__); ++ goto xmitframe_coalesce_fail; ++ } ++ ++ //DBG_871X("%s, action frame category=%d \n", __func__, pframe[WLAN_HDR_A3_LEN]); ++ //according 802.11-2012 standard, these five types are not robust types ++ if(subtype == WIFI_ACTION && ++ (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC || ++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT || ++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM || ++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED || ++ pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P)) ++ goto xmitframe_coalesce_fail; ++ /*//before encrypt dump the management packet content ++ { ++ int i; ++ printk("Management pkt: "); ++ for(i=0; ipktlen; i++) ++ printk(" %02x ", pframe[i]); ++ printk("=======\n"); ++ }*/ ++ ++ //bakeup original management packet ++ _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); ++ //move to data portion ++ pframe += pattrib->hdrlen; ++ ++ //802.11w unicast management packet must be _AES_ ++ pattrib->iv_len = 8; ++ //it's MIC of AES ++ pattrib->icv_len = 8; ++ ++ switch(pattrib->encrypt) ++ { ++ case _AES_: ++ //set AES IV header ++ AES_IV(pattrib->iv, psta->dot11wtxpn, 0); ++ break; ++ default: ++ goto xmitframe_coalesce_fail; ++ } ++ //insert iv header into management frame ++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); ++ pframe += pattrib->iv_len; ++ //copy mgmt data portion after CCMP header ++ _rtw_memcpy(pframe, tmp_buf+pattrib->hdrlen, pattrib->pktlen-pattrib->hdrlen); ++ //move pframe to end of mgmt pkt ++ pframe += pattrib->pktlen-pattrib->hdrlen; ++ //add 8 bytes CCMP IV header to length ++ pattrib->pktlen += pattrib->iv_len; ++ /*//dump management packet include AES IV header ++ { ++ int i; ++ printk("Management pkt + IV: "); ++ //for(i=0; ipktlen; i++) ++ //printk(" %02x ", mem_start[i]); ++ printk("@@@@@@@@@@@@@\n"); ++ }*/ ++ ++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { ++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); ++ pframe += pattrib->icv_len; ++ } ++ //add 8 bytes MIC ++ pattrib->pktlen += pattrib->icv_len; ++ //set final tx command size ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ //set protected bit must be beofre SW encrypt ++ SetPrivacy(mem_start); ++ /*//dump management packet include AES header ++ { ++ int i; ++ printk("prepare to enc Management pkt + IV: "); ++ for(i=0; ipktlen; i++) ++ printk(" %02x ", mem_start[i]); ++ printk("@@@@@@@@@@@@@\n"); ++ }*/ ++ //software encrypt ++ xmitframe_swencrypt(padapter, pxmitframe); ++ } ++ } ++ ++xmitframe_coalesce_success: ++ _exit_critical_bh(&padapter->security_key_mutex, &irqL); ++ rtw_mfree(BIP_AAD, ori_len); ++_func_exit_; ++ return _SUCCESS; ++ ++xmitframe_coalesce_fail: ++ _exit_critical_bh(&padapter->security_key_mutex, &irqL); ++ rtw_mfree(BIP_AAD, ori_len); ++_func_exit_; ++ ++ return _FAIL; ++} ++#endif //CONFIG_IEEE80211W ++ ++/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header ++ * IEEE LLC/SNAP header contains 8 octets ++ * First 3 octets comprise the LLC portion ++ * SNAP portion, 5 octets, is divided into two fields: ++ * Organizationally Unique Identifier(OUI), 3 octets, ++ * type, defined by that organization, 2 octets. ++ */ ++s32 rtw_put_snap(u8 *data, u16 h_proto) ++{ ++ struct ieee80211_snap_hdr *snap; ++ u8 *oui; ++ ++_func_enter_; ++ ++ snap = (struct ieee80211_snap_hdr *)data; ++ snap->dsap = 0xaa; ++ snap->ssap = 0xaa; ++ snap->ctrl = 0x03; ++ ++ if (h_proto == 0x8137 || h_proto == 0x80f3) ++ oui = P802_1H_OUI; ++ else ++ oui = RFC1042_OUI; ++ ++ snap->oui[0] = oui[0]; ++ snap->oui[1] = oui[1]; ++ snap->oui[2] = oui[2]; ++ ++ *(u16 *)(data + SNAP_SIZE) = htons(h_proto); ++ ++_func_exit_; ++ ++ return SNAP_SIZE + sizeof(u16); ++} ++ ++void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) ++{ ++ ++ uint protection; ++ u8 *perp; ++ sint erp_len; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++_func_enter_; ++ ++ switch(pxmitpriv->vcs_setting) ++ { ++ case DISABLE_VCS: ++ pxmitpriv->vcs = NONE_VCS; ++ break; ++ ++ case ENABLE_VCS: ++ break; ++ ++ case AUTO_VCS: ++ default: ++ perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); ++ if(perp == NULL) ++ { ++ pxmitpriv->vcs = NONE_VCS; ++ } ++ else ++ { ++ protection = (*(perp + 2)) & BIT(1); ++ if (protection) ++ { ++ if(pregistrypriv->vcs_type == RTS_CTS) ++ pxmitpriv->vcs = RTS_CTS; ++ else ++ pxmitpriv->vcs = CTS_TO_SELF; ++ } ++ else ++ pxmitpriv->vcs = NONE_VCS; ++ } ++ ++ break; ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz) ++{ ++ struct sta_info *psta = NULL; ++ struct stainfo_stats *pstats = NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ pxmitpriv->tx_bytes += sz; ++#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pxmitframe->agg_num; ++#else ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++; ++#endif ++ ++ psta = pxmitframe->attrib.psta; ++ if (psta) ++ { ++ pstats = &psta->sta_stats; ++#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pstats->tx_pkts += pxmitframe->agg_num; ++#else ++ pstats->tx_pkts++; ++#endif ++ pstats->tx_bytes += sz; ++ } ++ } ++} ++ ++struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) ++{ ++ _irqL irqL; ++ struct xmit_buf *pxmitbuf = NULL; ++ _list *plist, *phead; ++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; ++ ++_func_enter_; ++ ++ _enter_critical(&pfree_queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(pfree_queue) == _TRUE) { ++ pxmitbuf = NULL; ++ } else { ++ ++ phead = get_list_head(pfree_queue); ++ ++ plist = get_next(phead); ++ ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ ++ rtw_list_delete(&(pxmitbuf->list)); ++ } ++ ++ if (pxmitbuf != NULL) ++ { ++ pxmitpriv->free_xmit_extbuf_cnt--; ++ #ifdef DBG_XMIT_BUF_EXT ++ DBG_871X("DBG_XMIT_BUF_EXT ALLOC no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); ++ #endif ++ ++ ++ pxmitbuf->priv_data = NULL; ++ //pxmitbuf->ext_tag = _TRUE; ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->len = 0; ++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; ++#endif ++#ifdef CONFIG_PCI_HCI ++ pxmitbuf->len = 0; ++#endif ++ ++ if (pxmitbuf->sctx) { ++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); ++ } ++ ++ } ++ ++ _exit_critical(&pfree_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pxmitbuf; ++} ++ ++s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ _irqL irqL; ++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; ++ ++_func_enter_; ++ ++ if(pxmitbuf==NULL) ++ { ++ return _FAIL; ++ } ++ ++ _enter_critical(&pfree_queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitbuf->list); ++ ++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); ++ pxmitpriv->free_xmit_extbuf_cnt++; ++ #ifdef DBG_XMIT_BUF_EXT ++ DBG_871X("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmit_extbuf_cnt); ++ #endif ++ ++ _exit_critical(&pfree_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) ++{ ++ _irqL irqL; ++ struct xmit_buf *pxmitbuf = NULL; ++ _list *plist, *phead; ++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; ++ ++_func_enter_; ++ ++ //DBG_871X("+rtw_alloc_xmitbuf\n"); ++ ++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) { ++ pxmitbuf = NULL; ++ } else { ++ ++ phead = get_list_head(pfree_xmitbuf_queue); ++ ++ plist = get_next(phead); ++ ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ ++ rtw_list_delete(&(pxmitbuf->list)); ++ } ++ ++ if (pxmitbuf != NULL) ++ { ++ pxmitpriv->free_xmitbuf_cnt--; ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); ++ #endif ++ //DBG_871X("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); ++ ++ pxmitbuf->priv_data = NULL; ++ //pxmitbuf->ext_tag = _FALSE; ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->len = 0; ++ pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; ++ pxmitbuf->agg_num = 0; ++ pxmitbuf->pg_num = 0; ++#endif ++#ifdef CONFIG_PCI_HCI ++ pxmitbuf->len = 0; ++#endif ++ ++ if (pxmitbuf->sctx) { ++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); ++ } ++ } ++ #ifdef DBG_XMIT_BUF ++ else ++ { ++ DBG_871X("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n"); ++ } ++ #endif ++ ++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pxmitbuf; ++} ++ ++s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ _irqL irqL; ++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; ++ ++_func_enter_; ++ ++ //DBG_871X("+rtw_free_xmitbuf\n"); ++ ++ if(pxmitbuf==NULL) ++ { ++ return _FAIL; ++ } ++ ++ if (pxmitbuf->sctx) { ++ DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE); ++ } ++ ++ if(pxmitbuf->ext_tag) ++ { ++ rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); ++ } ++ else ++ { ++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitbuf->list); ++ ++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); ++ ++ pxmitpriv->free_xmitbuf_cnt++; ++ //DBG_871X("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmitbuf_cnt); ++ #endif ++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++void rtw_init_xmitframe(struct xmit_frame *pxframe) ++{ ++ if (pxframe != NULL)//default value setting ++ { ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); ++ //pxframe->attrib.psta = NULL; ++ ++ pxframe->frame_tag = DATA_FRAMETAG; ++ ++#ifdef CONFIG_USB_HCI ++ pxframe->pkt = NULL; ++ pxframe->pkt_offset = 1;//default use pkt_offset to fill tx desc ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pxframe->agg_num = 1; ++#endif ++ ++#endif //#ifdef CONFIG_USB_HCI ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxframe->pg_num = 1; ++ pxframe->agg_num = 1; ++#endif ++ ++#ifdef CONFIG_XMIT_ACK ++ pxframe->ack_report = 0; ++#endif ++ ++ } ++} ++ ++/* ++Calling context: ++1. OS_TXENTRY ++2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) ++ ++If we turn on USE_RXTHREAD, then, no need for critical section. ++Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... ++ ++Must be very very cautious... ++ ++*/ ++struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)//(_queue *pfree_xmit_queue) ++{ ++ /* ++ Please remember to use all the osdep_service api, ++ and lock/unlock or _enter/_exit critical to protect ++ pfree_xmit_queue ++ */ ++ ++ _irqL irqL; ++ struct xmit_frame *pxframe = NULL; ++ _list *plist, *phead; ++ _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; ++#ifdef PLATFORM_LINUX ++ _adapter *padapter = pxmitpriv->adapter; ++#endif //PLATFORM_LINUX ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt)); ++ pxframe = NULL; ++ } else { ++ phead = get_list_head(pfree_xmit_queue); ++ ++ plist = get_next(phead); ++ ++ pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ rtw_list_delete(&(pxframe->list)); ++ pxmitpriv->free_xmitframe_cnt--; ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); ++ } ++ ++ _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++ rtw_init_xmitframe(pxframe); ++ ++_func_exit_; ++ ++ return pxframe; ++} ++ ++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) ++{ ++ _irqL irqL; ++ struct xmit_frame *pxframe = NULL; ++ _list *plist, *phead; ++ _queue *queue = &pxmitpriv->free_xframe_ext_queue; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(queue) == _TRUE) { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe_ext:%d\n", pxmitpriv->free_xframe_ext_cnt)); ++ pxframe = NULL; ++ } else { ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ rtw_list_delete(&(pxframe->list)); ++ pxmitpriv->free_xframe_ext_cnt--; ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext():free_xmitframe_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ rtw_init_xmitframe(pxframe); ++ ++_func_exit_; ++ ++ return pxframe; ++} ++ ++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv) ++{ ++ struct xmit_frame *pxframe = NULL; ++ u8 *alloc_addr; ++ ++ alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4); ++ ++ if (alloc_addr == NULL) ++ goto exit; ++ ++ pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4); ++ pxframe->alloc_addr = alloc_addr; ++ ++ pxframe->padapter = pxmitpriv->adapter; ++ pxframe->frame_tag = NULL_FRAMETAG; ++ ++ pxframe->pkt = NULL; ++ ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ rtw_init_xmitframe(pxframe); ++ ++ DBG_871X("################## %s ##################\n", __func__); ++ ++exit: ++ return pxframe; ++} ++ ++s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ _queue *queue; ++ _adapter *padapter = pxmitpriv->adapter; ++ _pkt *pndis_pkt = NULL; ++ ++_func_enter_; ++ ++ if (pxmitframe == NULL) { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n")); ++ goto exit; ++ } ++ ++ if (pxmitframe->pkt){ ++ pndis_pkt = pxmitframe->pkt; ++ pxmitframe->pkt = NULL; ++ } ++ ++ if (pxmitframe->alloc_addr) { ++ DBG_871X("################## %s with alloc_addr ##################\n", __func__); ++ rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4); ++ goto check_pkt_complete; ++ } ++ ++ if (pxmitframe->ext_tag == 0) ++ queue = &pxmitpriv->free_xmit_queue; ++ else if(pxmitframe->ext_tag == 1) ++ queue = &pxmitpriv->free_xframe_ext_queue; ++ else ++ {} ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitframe->list); ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); ++ if (pxmitframe->ext_tag == 0) { ++ pxmitpriv->free_xmitframe_cnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); ++ } else if(pxmitframe->ext_tag == 1) { ++ pxmitpriv->free_xframe_ext_cnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xframe_ext_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); ++ } else { ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++check_pkt_complete: ++ ++ if(pndis_pkt) ++ rtw_os_pkt_complete(padapter, pndis_pkt); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct xmit_frame *pxmitframe; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pframequeue->lock), &irqL); ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ ++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ plist = get_next(plist); ++ ++ rtw_free_xmitframe(pxmitpriv,pxmitframe); ++ ++ } ++ _exit_critical_bh(&(pframequeue->lock), &irqL); ++ ++_func_exit_; ++} ++ ++s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ++ ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n")); ++// pxmitframe->pkt = NULL; ++ return _FAIL; ++ } ++ ++ return _SUCCESS; ++} ++ ++static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) ++{ ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ ++ xmitframe_phead = get_list_head(pframe_queue); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++/*#ifdef RTK_DMP_PLATFORM ++#ifdef CONFIG_USB_TX_AGGREGATION ++ if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2)) ++ { ++ pxmitframe = NULL; ++ ++ tasklet_schedule(&pxmitpriv->xmit_tasklet); ++ ++ break; ++ } ++#endif ++#endif*/ ++ rtw_list_delete(&pxmitframe->list); ++ ++ ptxservq->qcnt--; ++ ++ //rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); ++ ++ //ptxservq->qcnt--; ++ ++ break; ++ ++ pxmitframe = NULL; ++ ++ } ++ ++ return pxmitframe; ++} ++ ++struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) ++{ ++ _irqL irqL0; ++ _list *sta_plist, *sta_phead; ++ struct hw_xmit *phwxmit; ++ struct tx_servq *ptxservq = NULL; ++ _queue *pframe_queue = NULL; ++ struct xmit_frame *pxmitframe = NULL; ++ _adapter *padapter = pxmitpriv->adapter; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ int i, inx[4]; ++#ifdef CONFIG_USB_HCI ++// int j, tmp, acirp_cnt[4]; ++#endif ++ ++_func_enter_; ++ ++ inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; ++ ++ if(pregpriv->wifi_spec==1) ++ { ++ int j, tmp, acirp_cnt[4]; ++#if 0 ++ if(flagswmm_para_seq[j]; ++#endif ++ } ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ for(i = 0; i < entry; i++) ++ { ++ phwxmit = phwxmit_i + inx[i]; ++ ++ //_enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ sta_phead = get_list_head(phwxmit->sta_queue); ++ sta_plist = get_next(sta_phead); ++ ++ while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) ++ { ++ ++ ptxservq= LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); ++ ++ pframe_queue = &ptxservq->sta_pending; ++ ++ pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); ++ ++ if(pxmitframe) ++ { ++ phwxmit->accnt--; ++ ++ //Remove sta node when there is no pending packets. ++ if(_rtw_queue_empty(pframe_queue)) //must be done after get_next and before break ++ rtw_list_delete(&ptxservq->tx_pending); ++ ++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ goto exit; ++ } ++ ++ sta_plist = get_next(sta_plist); ++ ++ } ++ ++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ } ++ ++exit: ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++_func_exit_; ++ ++ return pxmitframe; ++} ++ ++#if 1 ++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) ++{ ++ struct tx_servq *ptxservq=NULL; ++ ++_func_enter_; ++ ++ switch (up) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ *(ac) = 3; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ *(ac) = 1; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ *(ac) = 0; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ *(ac) = 2; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); ++ break; ++ ++ } ++ ++_func_exit_; ++ ++ return ptxservq; ++} ++#else ++__inline static struct tx_servq *rtw_get_sta_pending ++ (_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up) ++{ ++ struct tx_servq *ptxservq; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ ++_func_enter_; ++ ++#ifdef CONFIG_RTL8711 ++ ++ if(IS_MCAST(psta->hwaddr)) ++ { ++ ptxservq = &(psta->sta_xmitpriv.be_q); // we will use be_q to queue bc/mc frames in BCMC_stainfo ++ *ppstapending = &padapter->xmitpriv.bm_pending; ++ } ++ else ++#endif ++ { ++ switch (up) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ *ppstapending = &padapter->xmitpriv.bk_pending; ++ (phwxmits+3)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ *ppstapending = &padapter->xmitpriv.vi_pending; ++ (phwxmits+1)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ *ppstapending = &padapter->xmitpriv.vo_pending; ++ (phwxmits+0)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ *ppstapending = &padapter->xmitpriv.be_pending; ++ (phwxmits+2)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); ++ break; ++ ++ } ++ ++ } ++ ++_func_exit_; ++ ++ return ptxservq; ++} ++#endif ++ ++/* ++ * Will enqueue pxmitframe to the proper queue, ++ * and indicate it to xx_pending list..... ++ */ ++s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ //_irqL irqL0; ++ u8 ac_index; ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ sint res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ } ++ ++ if (psta == NULL) { ++ res = _FAIL; ++ DBG_8192C("rtw_xmit_classifier: psta == NULL\n"); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("rtw_xmit_classifier: psta == NULL\n")); ++ goto exit; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return _FAIL; ++ } ++ ++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); ++ ++ //_enter_critical(&pstapending->lock, &irqL0); ++ ++ if (rtw_is_list_empty(&ptxservq->tx_pending)) { ++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); ++ } ++ ++ //_enter_critical(&ptxservq->sta_pending.lock, &irqL1); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); ++ ptxservq->qcnt++; ++ phwxmits[ac_index].accnt++; ++ ++ //_exit_critical(&ptxservq->sta_pending.lock, &irqL1); ++ ++ //_exit_critical(&pstapending->lock, &irqL0); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_alloc_hwxmits(_adapter *padapter) ++{ ++ struct hw_xmit *hwxmits; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; ++ ++ pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry); ++ ++ hwxmits = pxmitpriv->hwxmits; ++ ++ if(pxmitpriv->hwxmit_entry == 5) ++ { ++ //pxmitpriv->bmc_txqueue.head = 0; ++ //hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; ++ hwxmits[0] .sta_queue = &pxmitpriv->bm_pending; ++ ++ //pxmitpriv->vo_txqueue.head = 0; ++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; ++ hwxmits[1] .sta_queue = &pxmitpriv->vo_pending; ++ ++ //pxmitpriv->vi_txqueue.head = 0; ++ //hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; ++ hwxmits[2] .sta_queue = &pxmitpriv->vi_pending; ++ ++ //pxmitpriv->bk_txqueue.head = 0; ++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; ++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; ++ ++ //pxmitpriv->be_txqueue.head = 0; ++ //hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; ++ hwxmits[4] .sta_queue = &pxmitpriv->be_pending; ++ ++ } ++ else if(pxmitpriv->hwxmit_entry == 4) ++ { ++ ++ //pxmitpriv->vo_txqueue.head = 0; ++ //hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; ++ hwxmits[0] .sta_queue = &pxmitpriv->vo_pending; ++ ++ //pxmitpriv->vi_txqueue.head = 0; ++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; ++ hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; ++ ++ //pxmitpriv->be_txqueue.head = 0; ++ //hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; ++ hwxmits[2] .sta_queue = &pxmitpriv->be_pending; ++ ++ //pxmitpriv->bk_txqueue.head = 0; ++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; ++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; ++ } ++ else ++ { ++ ++ ++ } ++ ++ ++} ++ ++void rtw_free_hwxmits(_adapter *padapter) ++{ ++ struct hw_xmit *hwxmits; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ hwxmits = pxmitpriv->hwxmits; ++ if(hwxmits) ++ rtw_mfree((u8 *)hwxmits, (sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry)); ++} ++ ++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) ++{ ++ sint i; ++_func_enter_; ++ for(i = 0; i < entry; i++, phwxmit++) ++ { ++ //_rtw_spinlock_init(&phwxmit->xmit_lock); ++ //_rtw_init_listhead(&phwxmit->pending); ++ //phwxmit->txcmdcnt = 0; ++ phwxmit->accnt = 0; ++ } ++_func_exit_; ++} ++ ++#ifdef CONFIG_BR_EXT ++int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) ++{ ++ struct sk_buff *skb = *pskb; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); ++ int res, is_vlan_tag=0, i, do_nat25=1; ++ unsigned short vlan_hdr=0; ++ void *br_port = NULL; ++ ++ //mac_clone_handle_frame(priv, skb); ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ _enter_critical_bh(&padapter->br_ext_lock, &irqL); ++ if ( !(skb->data[0] & 1) && ++ br_port && ++ memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) != __constant_htons(ETH_P_8021Q) && ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP) && ++ !memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ padapter->scdb_entry->ageing_timer = jiffies; ++ _exit_critical_bh(&padapter->br_ext_lock, &irqL); ++ } ++ else ++ //if (!priv->pmib->ethBrExtInfo.nat25_disable) ++ { ++// if (priv->dev->br_port && ++// !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { ++#if 1 ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ //if SA == br_mac && skb== IP => copy SIP to br_ip ?? why ++ if (!memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && ++ (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP))) ++ memcpy(padapter->br_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); ++ ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP)) { ++ if (memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN)) { ++ void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); ++ ++ if ((padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, ++ skb->data+MACADDRLEN, skb->data+WLAN_ETHHDR_LEN+12)) != NULL) { ++ memcpy(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN); ++ memcpy(padapter->scdb_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); ++ padapter->scdb_entry->ageing_timer = jiffies; ++ do_nat25 = 0; ++ } ++ } ++ else { ++ if (padapter->scdb_entry) { ++ padapter->scdb_entry->ageing_timer = jiffies; ++ do_nat25 = 0; ++ } ++ else { ++ memset(padapter->scdb_mac, 0, MACADDRLEN); ++ memset(padapter->scdb_ip, 0, 4); ++ } ++ } ++ } ++ _exit_critical_bh(&padapter->br_ext_lock, &irqL); ++#endif // 1 ++ if (do_nat25) ++ { ++ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); ++ if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { ++ struct sk_buff *newskb; ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; ++ } ++ ++ newskb = rtw_skb_copy(skb); ++ if (newskb == NULL) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n"); ++ //goto stop_proc; ++ return -1; ++ } ++ rtw_skb_free(skb); ++ ++ *pskb = skb = newskb; ++ if (is_vlan_tag) { ++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ } ++ ++ if (skb_is_nonlinear(skb)) ++ DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ res = skb_linearize(skb, GFP_ATOMIC); ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ res = skb_linearize(skb); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ if (res < 0) { ++ DEBUG_ERR("TX DROP: skb_linearize fail!\n"); ++ //goto free_and_stop; ++ return -1; ++ } ++ ++ res = nat25_db_handle(padapter, skb, NAT25_INSERT); ++ if (res < 0) { ++ if (res == -2) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); ++ //goto free_and_stop; ++ return -1; ++ ++ } ++ // we just print warning message and let it go ++ //DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); ++ //return -1; // return -1 will cause system crash on 2011/08/30! ++ return 0; ++ } ++ } ++ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ ++ dhcp_flag_bcast(padapter, skb); ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; ++ } ++ } ++#if 0 ++ else{ ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ } ++ ++ if(is_vlan_tag){ ++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)){ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ } ++ }else ++ { ++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)){ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ } ++ } ++ } ++#endif // 0 ++ ++ // check if SA is equal to our MAC ++ if (memcmp(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", ++ skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11]); ++ //goto free_and_stop; ++ return -1; ++ } ++ } ++ return 0; ++} ++#endif // CONFIG_BR_EXT ++ ++u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) ++{ ++ u32 addr; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ switch(pattrib->qsel) ++ { ++ case 0: ++ case 3: ++ addr = BE_QUEUE_INX; ++ break; ++ case 1: ++ case 2: ++ addr = BK_QUEUE_INX; ++ break; ++ case 4: ++ case 5: ++ addr = VI_QUEUE_INX; ++ break; ++ case 6: ++ case 7: ++ addr = VO_QUEUE_INX; ++ break; ++ case 0x10: ++ addr = BCN_QUEUE_INX; ++ break; ++ case 0x11://BC/MC in PS (HIQ) ++ addr = HIGH_QUEUE_INX; ++ break; ++ case 0x12: ++ default: ++ addr = MGT_QUEUE_INX; ++ break; ++ ++ } ++ ++ return addr; ++ ++} ++ ++static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ u8 qsel; ++ ++ qsel = pattrib->priority; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("### do_queue_select priority=%d ,qsel = %d\n",pattrib->priority ,qsel)); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++// if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) ++// qsel = 7;// ++#endif ++ ++ pattrib->qsel = qsel; ++} ++ ++/* ++ * The main transmit(tx) entry ++ * ++ * Return ++ * 1 enqueue ++ * 0 success, hardware will handle this xmit frame(packet) ++ * <0 fail ++ */ ++s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) ++{ ++ static u32 start = 0; ++ static u32 drop_cnt = 0; ++#ifdef CONFIG_AP_MODE ++ _irqL irqL0; ++#endif ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_frame *pxmitframe = NULL; ++#ifdef CONFIG_BR_EXT ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ void *br_port = NULL; ++#endif // CONFIG_BR_EXT ++ ++ s32 res; ++ ++ if (start == 0) ++ start = rtw_get_current_time(); ++ ++ pxmitframe = rtw_alloc_xmitframe(pxmitpriv); ++ ++ if (rtw_get_passing_time_ms(start) > 2000) { ++ if (drop_cnt) ++ DBG_871X("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt); ++ start = rtw_get_current_time(); ++ drop_cnt = 0; ++ } ++ ++ if (pxmitframe == NULL) { ++ drop_cnt ++; ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: no more pxmitframe\n")); ++ return -1; ++ } ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ if( br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ res = rtw_br_client_tx(padapter, ppkt); ++ if (res == -1) ++ { ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ return -1; ++ } ++ } ++ ++#endif // CONFIG_BR_EXT ++ ++ res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(pxmitframe->attrib.ether_type != 0x88B4) ++ { ++ if(rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) ++ { ++ WAPI_TRACE(WAPI_RX,"drop for key absend when tx \n"); ++ res = _FAIL; ++ } ++ } ++#endif ++ if (res == _FAIL) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: update attrib fail\n")); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); ++ #endif ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ return -1; ++ } ++ pxmitframe->pkt = *ppkt; ++ ++ rtw_led_control(padapter, LED_CTL_TX); ++ ++ do_queue_select(padapter, &pxmitframe->attrib); ++ ++#ifdef CONFIG_AP_MODE ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) ++ { ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ return 1; ++ } ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++#endif ++ ++ if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) ++ return 1; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_TDLS ++sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ sint ret=_FALSE; ++ ++ _irqL irqL; ++ struct sta_info *ptdls_sta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ int i; ++ ++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); ++ if(ptdls_sta==NULL){ ++ return ret; ++ }else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE){ ++ ++ if(pattrib->triggered==1) ++ { ++ ret = _TRUE; ++ return ret; ++ } ++ ++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ if(ptdls_sta->state&WIFI_SLEEP_STATE) ++ { ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q)); ++ ++ ptdls_sta->sleepq_len++; ++ ptdls_sta->sleepq_ac_len++; ++ ++ //indicate 4-AC queue bit in TDLS peer traffic indication ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ ptdls_sta->uapsd_bk = ptdls_sta->uapsd_bk | BIT(1); ++ break; ++ case 4: ++ case 5: ++ ptdls_sta->uapsd_vi = ptdls_sta->uapsd_vi | BIT(1); ++ break; ++ case 6: ++ case 7: ++ ptdls_sta->uapsd_vo = ptdls_sta->uapsd_vo | BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ ptdls_sta->uapsd_be = ptdls_sta->uapsd_be | BIT(1); ++ break; ++ } ++ ++ if(ptdls_sta->sleepq_len==1) ++ { ++ //transmit TDLS PTI via AP ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_SD_PTI); ++ } ++ ret = _TRUE; ++ ++ } ++ ++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ } ++ ++ return ret; ++ ++} ++#endif //CONFIG_TDLS ++ ++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) ++ ++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ sint ret=_FALSE; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ sint bmcst = IS_MCAST(pattrib->ra); ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ if( ptdlsinfo->setup_state == TDLS_LINKED_STATE ) ++ { ++ ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe); ++ return ret; ++ } ++#endif //CONFIG_TDLS ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) ++ return ret; ++ ++ if(pattrib->psta) ++ { ++ psta = pattrib->psta; ++ } ++ else ++ { ++ DBG_871X("%s, call rtw_get_stainfo()\n", __func__); ++ psta=rtw_get_stainfo(pstapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ { ++ DBG_871X("%s, psta==NUL\n", __func__); ++ return _FALSE; ++ } ++ ++ if(!(psta->state &_FW_LINKED)) ++ { ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ return _FALSE; ++ } ++ ++ if(pattrib->triggered==1) ++ { ++ //DBG_871X("directly xmit pspoll_triggered packet\n"); ++ ++ //pattrib->triggered=0; ++ ++ if(bmcst) ++ pattrib->qsel = 0x11;//HIQ ++ ++ ++ return ret; ++ } ++ ++ ++ if(bmcst) ++ { ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ if(pstapriv->sta_dz_bitmap)//if anyone sta is in ps mode ++ { ++ //pattrib->qsel = 0x11;//HIQ ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); ++ ++ psta->sleepq_len++; ++ ++ pstapriv->tim_bitmap |= BIT(0);// ++ pstapriv->sta_dz_bitmap |= BIT(0); ++ ++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);//tx bc/mc packets after upate bcn ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ ret = _TRUE; ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ return ret; ++ ++ } ++ ++ ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ { ++ u8 wmmps_ac=0; ++ ++ if(pstapriv->sta_dz_bitmap&BIT(psta->aid)) ++ { ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); ++ ++ psta->sleepq_len++; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(0); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(0); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(0); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(0); ++ break; ++ } ++ ++ if(wmmps_ac) ++ psta->sleepq_ac_len++; ++ ++ if(((psta->has_legacy_ac) && (!wmmps_ac)) ||((!psta->has_legacy_ac)&&(wmmps_ac))) ++ { ++ pstapriv->tim_bitmap |= BIT(psta->aid); ++ ++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++ if(psta->sleepq_len==1) ++ { ++ //DBG_871X("sleepq_len==1, update BCNTIM\n"); ++ //upate BCN for TIM IE ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ } ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ //if(psta->sleepq_len > (NR_XMITFRAME>>3)) ++ //{ ++ // wakeup_sta_to_xmit(padapter, psta); ++ //} ++ ++ ret = _TRUE; ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ return ret; ++ ++} ++ ++static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue) ++{ ++ sint ret; ++ _list *plist, *phead; ++ u8 ac_index; ++ struct tx_servq *ptxservq; ++ struct pkt_attrib *pattrib; ++ struct xmit_frame *pxmitframe; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ plist = get_next(plist); ++ ++ ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe); ++ ++ if(_TRUE == ret) ++ { ++ pattrib = &pxmitframe->attrib; ++ ++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); ++ ++ ptxservq->qcnt--; ++ phwxmits[ac_index].accnt--; ++ } ++ else ++ { ++ //DBG_871X("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); ++ } ++ ++ } ++ ++} ++ ++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL0; ++ struct sta_info *psta_bmc; ++ struct sta_xmit_priv *pstaxmitpriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ pstaxmitpriv = &psta->sta_xmitpriv; ++ ++ //for BC/MC Frames ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ psta->state |= WIFI_SLEEP_STATE; ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) ) ++#endif //CONFIG_TDLS ++ pstapriv->sta_dz_bitmap |= BIT(psta->aid); ++ ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) ) ++ { ++ if( psta_bmc != NULL ) ++ { ++#endif //CONFIG_TDLS ++ ++ ++ //for BC/MC Frames ++ pstaxmitpriv = &psta_bmc->sta_xmitpriv; ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ ++ ++#ifdef CONFIG_TDLS ++ } ++ } ++#endif //CONFIG_TDLS ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ ++} ++ ++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ u8 update_mask=0, wmmps_ac=0; ++ struct sta_info *psta_bmc; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ switch(pxmitframe->attrib.priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ psta->sleepq_len--; ++ if(psta->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ if(wmmps_ac) ++ { ++ psta->sleepq_ac_len--; ++ if(psta->sleepq_ac_len>0) ++ { ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ } ++ else ++ { ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ } ++ ++ pxmitframe->attrib.triggered = 1; ++ ++/* ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++*/ ++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ ++ } ++ ++ //for BC/MC Frames ++ if(!psta_bmc) ++ goto _exit; ++ ++ if((pstapriv->sta_dz_bitmap&0xfffe) == 0x0)//no any sta in ps mode ++ { ++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta_bmc->sleepq_len--; ++ if(psta_bmc->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ ++ pxmitframe->attrib.triggered = 1; ++/* ++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++*/ ++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ } ++ ++ if(psta_bmc->sleepq_len==0) ++ { ++ pstapriv->tim_bitmap &= ~BIT(0); ++ pstapriv->sta_dz_bitmap &= ~BIT(0); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_mask |= BIT(1); ++ } ++ ++ } ++ ++ if(psta->sleepq_len==0) ++ { ++#ifdef CONFIG_TDLS ++ if( psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ if(psta->state&WIFI_SLEEP_STATE) ++ psta->state ^= WIFI_SLEEP_STATE; ++ ++ goto _exit; ++ } ++#endif //CONFIG_TDLS ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_mask = BIT(0); ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ psta->state ^= WIFI_SLEEP_STATE; ++ ++ if(psta->state & WIFI_STA_ALIVE_CHK_STATE) ++ { ++ psta->expire_to = pstapriv->expire_to; ++ psta->state ^= WIFI_STA_ALIVE_CHK_STATE; ++ } ++ ++ pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); ++ } ++ ++_exit: ++ ++ //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if(update_mask) ++ { ++ //update_BCNTIM(padapter); ++ //printk("%s => call update_beacon\n",__FUNCTION__); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++} ++ ++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ u8 wmmps_ac=0; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ switch(pxmitframe->attrib.priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ if(!wmmps_ac) ++ continue; ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta->sleepq_len--; ++ psta->sleepq_ac_len--; ++ ++ if(psta->sleepq_ac_len>0) ++ { ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ } ++ else ++ { ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ ++ pxmitframe->attrib.triggered = 1; ++ ++/* ++ if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++*/ ++ rtw_hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ if((psta->sleepq_ac_len==0) && (!psta->has_legacy_ac) && (wmmps_ac)) ++ { ++#ifdef CONFIG_TDLS ++ if(psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ return; ++ } ++#endif //CONFIG_TDLS ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ //update_mask = BIT(0); ++ } ++ ++ } ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++} ++ ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++void enqueue_pending_xmitbuf( ++ struct xmit_priv *pxmitpriv, ++ struct xmit_buf *pxmitbuf) ++{ ++ _irqL irql; ++ _queue *pqueue; ++ _adapter *pri_adapter = pxmitpriv->adapter; ++ ++ pqueue = &pxmitpriv->pending_xmitbuf_queue; ++ ++ _enter_critical_bh(&pqueue->lock, &irql); ++ rtw_list_delete(&pxmitbuf->list); ++ rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue)); ++ _exit_critical_bh(&pqueue->lock, &irql); ++ ++ ++ ++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) ++ if (pri_adapter->adapter_type > PRIMARY_ADAPTER) ++ pri_adapter = pri_adapter->pbuddy_adapter; ++#endif //SDIO_HCI + CONCURRENT ++ _rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema)); ++ ++} ++ ++struct xmit_buf* dequeue_pending_xmitbuf( ++ struct xmit_priv *pxmitpriv) ++{ ++ _irqL irql; ++ struct xmit_buf *pxmitbuf; ++ _queue *pqueue; ++ ++ ++ pxmitbuf = NULL; ++ pqueue = &pxmitpriv->pending_xmitbuf_queue; ++ ++ _enter_critical_bh(&pqueue->lock, &irql); ++ ++ if (_rtw_queue_empty(pqueue) == _FALSE) ++ { ++ _list *plist, *phead; ++ ++ phead = get_list_head(pqueue); ++ plist = get_next(phead); ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ rtw_list_delete(&pxmitbuf->list); ++ } ++ ++ _exit_critical_bh(&pqueue->lock, &irql); ++ ++ return pxmitbuf; ++} ++ ++struct xmit_buf* dequeue_pending_xmitbuf_under_survey( ++ struct xmit_priv *pxmitpriv) ++{ ++ _irqL irql; ++ struct xmit_buf *pxmitbuf; ++#ifdef CONFIG_USB_HCI ++ struct xmit_frame *pxmitframe; ++#endif ++ _queue *pqueue; ++ ++ ++ pxmitbuf = NULL; ++ pqueue = &pxmitpriv->pending_xmitbuf_queue; ++ ++ _enter_critical_bh(&pqueue->lock, &irql); ++ ++ if (_rtw_queue_empty(pqueue) == _FALSE) ++ { ++ _list *plist, *phead; ++ u8 type; ++ ++ phead = get_list_head(pqueue); ++ plist = phead; ++ do { ++ plist = get_next(plist); ++ if (plist == phead) break; ++ ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ ++#ifdef CONFIG_USB_HCI ++ pxmitframe = (struct xmit_frame*)pxmitbuf->priv_data; ++ if(pxmitframe) ++ { ++ type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); ++ } ++ else ++ { ++ DBG_871X("%s, !!!ERROR!!! For USB, TODO ITEM \n", __FUNCTION__); ++ } ++#else ++ type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_OFFSET); ++#endif ++ ++ if ((type == WIFI_PROBEREQ) || ++ (type == WIFI_DATA_NULL) || ++ (type == WIFI_QOS_DATA_NULL)) ++ { ++ rtw_list_delete(&pxmitbuf->list); ++ break; ++ } ++ pxmitbuf = NULL; ++ } while (1); ++ } ++ ++ _exit_critical_bh(&pqueue->lock, &irql); ++ ++ return pxmitbuf; ++} ++ ++sint check_pending_xmitbuf( ++ struct xmit_priv *pxmitpriv) ++{ ++ _queue *pqueue; ++ ++ pqueue = &pxmitpriv->pending_xmitbuf_queue; ++ ++ if(_rtw_queue_empty(pqueue) == _FALSE) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++thread_return rtw_xmit_thread(thread_context context) ++{ ++ s32 err; ++ PADAPTER padapter; ++ ++ ++ err = _SUCCESS; ++ padapter = (PADAPTER)context; ++ ++ thread_enter("RTW_XMIT_THREAD"); ++ ++ do { ++ err = rtw_hal_xmit_thread_handler(padapter); ++ flush_signals_thread(); ++ } while (_SUCCESS == err); ++ ++ _rtw_up_sema(&padapter->xmitpriv.terminate_xmitthread_sema); ++ ++ thread_exit(); ++} ++#endif ++ ++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) ++{ ++ sctx->timeout_ms = timeout_ms; ++ sctx->submit_time= rtw_get_current_time(); ++#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */ ++ init_completion(&sctx->done); ++#endif ++ sctx->status = RTW_SCTX_SUBMITTED; ++} ++ ++int rtw_sctx_wait(struct submit_ctx *sctx) ++{ ++ int ret = _FAIL; ++ unsigned long expire; ++ int status = 0; ++ ++#ifdef PLATFORM_LINUX ++ expire= sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT; ++ if (!wait_for_completion_timeout(&sctx->done, expire)) { ++ /* timeout, do something?? */ ++ status = RTW_SCTX_DONE_TIMEOUT; ++ DBG_871X("%s timeout\n", __func__); ++ } else { ++ status = sctx->status; ++ } ++#endif ++ ++ if (status == RTW_SCTX_DONE_SUCCESS) { ++ ret = _SUCCESS; ++ } ++ ++ return ret; ++} ++ ++bool rtw_sctx_chk_waring_status(int status) ++{ ++ switch(status) { ++ case RTW_SCTX_DONE_UNKNOWN: ++ case RTW_SCTX_DONE_BUF_ALLOC: ++ case RTW_SCTX_DONE_BUF_FREE: ++ ++ case RTW_SCTX_DONE_DRV_STOP: ++ case RTW_SCTX_DONE_DEV_REMOVE: ++ return _TRUE; ++ default: ++ return _FALSE; ++ } ++} ++ ++void rtw_sctx_done_err(struct submit_ctx **sctx, int status) ++{ ++ if (*sctx) { ++ if (rtw_sctx_chk_waring_status(status)) ++ DBG_871X("%s status:%d\n", __func__, status); ++ (*sctx)->status = status; ++ #ifdef PLATFORM_LINUX ++ complete(&((*sctx)->done)); ++ #endif ++ *sctx = NULL; ++ } ++} ++ ++void rtw_sctx_done(struct submit_ctx **sctx) ++{ ++ rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS); ++} ++ ++#ifdef CONFIG_XMIT_ACK ++ ++#ifdef CONFIG_XMIT_ACK_POLLING ++s32 c2h_evt_hdl(_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter); ++ ++/** ++ * rtw_ack_tx_polling - ++ * @pxmitpriv: xmit_priv to address ack_tx_ops ++ * @timeout_ms: timeout msec ++ * ++ * Init ack_tx_ops and then do c2h_evt_hdl() and polling ack_tx_ops repeatedly ++ * till tx report or timeout ++ * Returns: _SUCCESS if TX report ok, _FAIL for others ++ */ ++int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms) ++{ ++ int ret = _FAIL; ++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; ++ _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv); ++ ++ pack_tx_ops->submit_time = rtw_get_current_time(); ++ pack_tx_ops->timeout_ms = timeout_ms; ++ pack_tx_ops->status = RTW_SCTX_SUBMITTED; ++ ++ do { ++ c2h_evt_hdl(adapter, NULL, rtw_hal_c2h_id_filter_ccx(adapter)); ++ if (pack_tx_ops->status != RTW_SCTX_SUBMITTED) ++ break; ++ ++ if (adapter->bDriverStopped) { ++ pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP; ++ break; ++ } ++ if (adapter->bSurpriseRemoved) { ++ pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE; ++ break; ++ } ++ ++ rtw_msleep_os(10); ++ } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms); ++ ++ if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) { ++ pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT; ++ DBG_871X("%s timeout\n", __func__); ++ } ++ ++ if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS) ++ ret = _SUCCESS; ++ ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++s32 c2h_evt_hdl(_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter); ++#endif ++ ++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms) ++{ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv); ++ c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter); ++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; ++ u8 check_c2hcmd; ++ u8 check_ccx; ++ int ret = _FAIL; ++ ++ pack_tx_ops->submit_time = rtw_get_current_time(); ++ pack_tx_ops->timeout_ms = timeout_ms; ++ pack_tx_ops->status = RTW_SCTX_SUBMITTED; ++ ++ do { ++ rtw_msleep_os(10); ++ //check_c2hcmd = rtw_read8(adapter, 0x1AF); ++ //check_ccx = rtw_read8(adapter, 0x1A0); ++ rtw_hal_get_hwreg(adapter, HW_VAR_C2HEVT_CLEAR, (u8 *)(&check_c2hcmd)); ++ rtw_hal_get_hwreg(adapter, HW_VAR_C2HEVT_MSG_NORMAL, (u8 *)(&check_ccx)); ++ ++ ++ if (check_c2hcmd != 0) ++ { ++ if (check_c2hcmd != 0xFF) ++ { ++ c2h_evt_clear(adapter); ++ } ++ else if (ccx_id_filter(check_ccx & 0x0F) == _TRUE) ++ { ++ c2h_evt_hdl(adapter, NULL, ccx_id_filter); ++ if (pack_tx_ops->status != RTW_SCTX_SUBMITTED) ++ break; ++ ++ if (adapter->bDriverStopped) { ++ pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP; ++ break; ++ } ++ if (adapter->bSurpriseRemoved) { ++ pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE; ++ break; ++ } ++ } ++ } ++ } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms); ++ ++ if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) { ++ pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT; ++ DBG_871X("%s timeout\n", __func__); ++ } ++ ++ if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS) ++ ret = _SUCCESS; ++ ++ return ret; ++#else ++#ifdef CONFIG_XMIT_ACK_POLLING ++ return rtw_ack_tx_polling(pxmitpriv, timeout_ms); ++#else ++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; ++ ++ pack_tx_ops->submit_time = rtw_get_current_time(); ++ pack_tx_ops->timeout_ms = timeout_ms; ++ pack_tx_ops->status = RTW_SCTX_SUBMITTED; ++ ++ return rtw_sctx_wait(pack_tx_ops); ++#endif ++#endif ++} ++ ++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status) ++{ ++ struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; ++ ++ if (pxmitpriv->ack_tx) { ++ rtw_sctx_done_err(&pack_tx_ops, status); ++ } else { ++ DBG_871X("%s ack_tx not set\n", __func__); ++ } ++} ++#endif //CONFIG_XMIT_ACK ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/HalPwrSeqCmd.c b/drivers/net/wireless/rtl818x/rtl8189/hal/HalPwrSeqCmd.c +new file mode 100644 +index 00000000..2948242c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/HalPwrSeqCmd.c +@@ -0,0 +1,187 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*++ ++Copyright (c) Realtek Semiconductor Corp. All rights reserved. ++ ++Module Name: ++ HalPwrSeqCmd.c ++ ++Abstract: ++ Implement HW Power sequence configuration CMD handling routine for Realtek devices. ++ ++Major Change History: ++ When Who What ++ ---------- --------------- ------------------------------- ++ 2011-10-26 Lucas Modify to be compatible with SD4-CE driver. ++ 2011-07-07 Roger Create. ++ ++--*/ ++#include ++#ifdef CONFIG_SDIO_HCI ++#include ++#elif defined(CONFIG_GSPI_HCI) ++#include ++#endif ++ ++// ++// Description: ++// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. ++// ++// Assumption: ++// We should follow specific format which was released from HW SD. ++// ++// 2011.07.07, added by Roger. ++// ++u8 HalPwrSeqCmdParsing( ++ PADAPTER padapter, ++ u8 CutVersion, ++ u8 FabVersion, ++ u8 InterfaceType, ++ WLAN_PWR_CFG PwrSeqCmd[]) ++{ ++ WLAN_PWR_CFG PwrCfgCmd = {0}; ++ u8 bPollingBit = _FALSE; ++ u32 AryIdx = 0; ++ u8 value = 0; ++ u32 offset = 0; ++ u32 pollingCount = 0; // polling autoload done. ++ u32 maxPollingCnt = 5000; ++ ++ do { ++ PwrCfgCmd = PwrSeqCmd[AryIdx]; ++ ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ++ ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n", ++ GET_PWR_CFG_OFFSET(PwrCfgCmd), ++ GET_PWR_CFG_CUT_MASK(PwrCfgCmd), ++ GET_PWR_CFG_FAB_MASK(PwrCfgCmd), ++ GET_PWR_CFG_INTF_MASK(PwrCfgCmd), ++ GET_PWR_CFG_BASE(PwrCfgCmd), ++ GET_PWR_CFG_CMD(PwrCfgCmd), ++ GET_PWR_CFG_MASK(PwrCfgCmd), ++ GET_PWR_CFG_VALUE(PwrCfgCmd))); ++ ++ //2 Only Handle the command whose FAB, CUT, and Interface are matched ++ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && ++ (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) && ++ (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) ++ { ++ switch (GET_PWR_CFG_CMD(PwrCfgCmd)) ++ { ++ case PWR_CMD_READ: ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")); ++ break; ++ ++ case PWR_CMD_WRITE: ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")); ++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); ++ ++#ifdef CONFIG_SDIO_HCI ++ // ++ // We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface ++ // 2011.07.07. ++ // ++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) ++ { ++ // Read Back SDIO Local value ++ value = SdioLocalCmd52Read1Byte(padapter, offset); ++ ++ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); ++ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); ++ ++ // Write Back SDIO Local value ++ SdioLocalCmd52Write1Byte(padapter, offset, value); ++ } ++ else ++#endif ++ { ++#ifdef CONFIG_GSPI_HCI ++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) ++ offset = SPI_LOCAL_OFFSET | offset; ++#endif ++ // Read the value from system register ++ value = rtw_read8(padapter, offset); ++ ++ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); ++ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); ++ ++ // Write the value back to sytem register ++ rtw_write8(padapter, offset, value); ++ } ++ break; ++ ++ case PWR_CMD_POLLING: ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")); ++ ++ bPollingBit = _FALSE; ++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); ++#ifdef CONFIG_GSPI_HCI ++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) ++ offset = SPI_LOCAL_OFFSET | offset; ++#endif ++ do { ++#ifdef CONFIG_SDIO_HCI ++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) ++ value = SdioLocalCmd52Read1Byte(padapter, offset); ++ else ++#endif ++ value = rtw_read8(padapter, offset); ++ ++ value &= GET_PWR_CFG_MASK(PwrCfgCmd); ++ if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd))) ++ bPollingBit = _TRUE; ++ else ++ rtw_udelay_os(10); ++ ++ if (pollingCount++ > maxPollingCnt) { ++ DBG_871X("Fail to polling Offset[%#x]\n", offset); ++ return _FALSE; ++ } ++ } while (!bPollingBit); ++ ++ break; ++ ++ case PWR_CMD_DELAY: ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")); ++ if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) ++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)); ++ else ++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000); ++ break; ++ ++ case PWR_CMD_END: ++ // When this command is parsed, end the process ++ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n")); ++ return _TRUE; ++ break; ++ ++ default: ++ RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n")); ++ break; ++ } ++ } ++ ++ AryIdx++;//Add Array Index ++ }while(1); ++ ++ return _TRUE; ++} ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/HalPhyRf.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/HalPhyRf.c +new file mode 100644 +index 00000000..ceed28c7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/HalPhyRf.c +@@ -0,0 +1,1561 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ #include "odm_precomp.h" ++ ++#if(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#include "Mp_Precomp.h" ++ ++VOID ++phy_PathAStandBy( ++ IN PADAPTER pAdapter ++ ) ++{ ++ RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); ++ ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0); ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000); ++} ++ ++//1 7. IQK ++//#define MAX_TOLERANCE 5 ++//#define IQK_DELAY_TIME 1 //ms ++ ++u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++phy_PathA_IQK_8192C( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN configPathB ++ ) ++{ ++ ++ u4Byte regEAC, regE94, regE9C, regEA4; ++ u1Byte result = 0x00; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); ++ ++ //path-A IQK setting ++ RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); ++ if(pAdapter->interfaceIndex == 0) ++ { ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); ++ } ++ ++ PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); ++ ++ PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : ++ IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); ++ ++ //path-B IQK setting ++ if(configPathB) ++ { ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160206); ++ else ++ PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); ++ } ++ ++ //LO calibration setting ++ RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); ++ else ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); ++ ++ //One shot, path A LOK & IQK ++ RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ++ ++ // delay x ms ++ RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); ++ PlatformStallExecution(IQK_DELAY_TIME*1000); ++ ++ // Check failed ++ regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); ++ regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); ++ regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); ++ regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); ++ ++ if(!(regEAC & BIT28) && ++ (((regE94 & 0x03FF0000)>>16) != 0x142) && ++ (((regE9C & 0x03FF0000)>>16) != 0x42) ) ++ result |= 0x01; ++ else //if Tx not OK, ignore Rx ++ return result; ++ ++ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK ++ (((regEA4 & 0x03FF0000)>>16) != 0x132) && ++ (((regEAC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); ++ ++ return result; ++ ++ ++} ++ ++u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++phy_PathB_IQK_8192C( ++ IN PADAPTER pAdapter ++ ) ++{ ++ u4Byte regEAC, regEB4, regEBC, regEC4, regECC; ++ u1Byte result = 0x00; ++ RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); ++ ++ //One shot, path B LOK & IQK ++ RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); ++ PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); ++ ++ // delay x ms ++ RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); ++ PlatformStallExecution(IQK_DELAY_TIME*1000); ++ ++ // Check failed ++ regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); ++ regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); ++ regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); ++ regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); ++ regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); ++ ++ if(!(regEAC & BIT31) && ++ (((regEB4 & 0x03FF0000)>>16) != 0x142) && ++ (((regEBC & 0x03FF0000)>>16) != 0x42)) ++ result |= 0x01; ++ else ++ return result; ++ ++ if(!(regEAC & BIT30) && ++ (((regEC4 & 0x03FF0000)>>16) != 0x132) && ++ (((regECC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); ++ ++ ++ return result; ++ ++} ++ ++VOID ++phy_PathAFillIQKMatrix( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bIQKOK, ++ IN s4Byte result[][8], ++ IN u1Byte final_candidate, ++ IN BOOLEAN bTxOnly ++ ) ++{ ++ u4Byte Oldval_0, X, TX0_A, reg; ++ s4Byte Y, TX0_C; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); ++ ++ if(final_candidate == 0xFF) ++ return; ++ ++ else if(bIQKOK) ++ { ++ Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][0]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX0_A = (X * Oldval_0) >> 8; ++ RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT24, ((X* Oldval_0>>7) & 0x1)); ++ else ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); ++ ++ Y = result[final_candidate][1]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ ++ //path B IQK result + 3 ++ if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType92D == BAND_ON_5G) ++ Y += 3; ++ ++ TX0_C = (Y * Oldval_0) >> 8; ++ RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)/*&&is2T*/) ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT26, ((Y* Oldval_0>>7) & 0x1)); ++ else ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); ++ ++ if(bTxOnly) ++ { ++ RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); ++ return; ++ } ++ ++ reg = result[final_candidate][2]; ++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][3] & 0x3F; ++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][3] >> 6) & 0xF; ++ PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); ++ } ++} ++ ++VOID ++phy_PathBFillIQKMatrix( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bIQKOK, ++ IN s4Byte result[][8], ++ IN u1Byte final_candidate, ++ IN BOOLEAN bTxOnly //do Tx only ++ ) ++{ ++ u4Byte Oldval_1, X, TX1_A, reg; ++ s4Byte Y, TX1_C; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); ++ ++ if(final_candidate == 0xFF) ++ return; ++ ++ else if(bIQKOK) ++ { ++ Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][4]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX1_A = (X * Oldval_1) >> 8; ++ RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT28, ((X* Oldval_1>>7) & 0x1)); ++ else ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); ++ ++ Y = result[final_candidate][5]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ if(pHalData->CurrentBandType92D == BAND_ON_5G) ++ Y += 3; //temp modify for preformance ++ TX1_C = (Y * Oldval_1) >> 8; ++ RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT30, ((Y* Oldval_1>>7) & 0x1)); ++ else ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); ++ ++ if(bTxOnly) ++ return; ++ ++ reg = result[final_candidate][6]; ++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][7] & 0x3F; ++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][7] >> 6) & 0xF; ++ PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); ++ } ++} ++ ++ ++BOOLEAN ++phy_SimularityCompare_92C( ++ IN PADAPTER pAdapter, ++ IN s4Byte result[][8], ++ IN u1Byte c1, ++ IN u1Byte c2 ++ ) ++{ ++ u4Byte i, j, diff, SimularityBitMap, bound = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B ++ BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); ++ ++ if(is2T) ++ bound = 8; ++ else ++ bound = 4; ++ ++ SimularityBitMap = 0; ++ ++ for( i = 0; i < bound; i++ ) ++ { ++ diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); ++ if (diff > MAX_TOLERANCE) ++ { ++ if((i == 2 || i == 6) && !SimularityBitMap) ++ { ++ if(result[c1][i]+result[c1][i+1] == 0) ++ final_candidate[(i/4)] = c2; ++ else if (result[c2][i]+result[c2][i+1] == 0) ++ final_candidate[(i/4)] = c1; ++ else ++ SimularityBitMap = SimularityBitMap|(1< do IQK again ++*/ ++BOOLEAN ++phy_SimularityCompare( ++ IN PADAPTER pAdapter, ++ IN s4Byte result[][8], ++ IN u1Byte c1, ++ IN u1Byte c2 ++ ) ++{ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ return phy_SimularityCompare_92D(pAdapter, result, c1, c2); ++ else ++ return phy_SimularityCompare_92C(pAdapter, result, c1, c2); ++ ++} ++ ++VOID ++phy_IQCalibrate_8192C( ++ IN PADAPTER pAdapter, ++ IN s4Byte result[][8], ++ IN u1Byte t, ++ IN BOOLEAN is2T ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u4Byte i; ++ u1Byte PathAOK, PathBOK; ++ u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth, ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN }; ++ u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, ++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; ++ ++ //since 92C & 92D have the different define in IQK_BB_REG ++ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { ++ rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, ++ rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, ++ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, ++ rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD ++ }; ++ ++ u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal ++ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, ++ rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, ++ rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, ++ rFPGA0_RFMOD, rFPGA0_AnalogParameter4, ++ rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 ++ }; ++ u4Byte retryCount; ++#if MP_DRIVER ++ if (pAdapter->registrypriv.mp_mode == 1) ++ retryCount = 9; ++ else ++#endif ++ retryCount = 2; ++ ++ ++ //Neil Chen--2011--05--19-- ++ //3 Path Div ++ u1Byte rfPathSwitch=0x0; ++ ++ // Note: IQ calibration must be performed after loading ++ // PHY_REG.txt , and radio_a, radio_b.txt ++ ++ u4Byte bbvalue; ++ ++ if(t==0) ++ { ++ bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); ++ RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); ++ ++ RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); ++ ++ // Save ADDA parameters, turn Path A ADDA on ++ phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); ++ phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D); ++ else ++ phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); ++ } ++ ++ phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); ++ ++ ++ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)){ ++ //============================== ++ //3 Path Diversity ++ ////Neil Chen--2011--05--20 ++ rfPathSwitch =(u1Byte) (PHY_QueryBBReg(pAdapter, 0xB30, bMaskDWord)>>27); ++ //rfPathSwitch = (u1Byte) DataB30; ++ rfPathSwitch = rfPathSwitch&(0x01); ++ ++ if(rfPathSwitch) // Path Div On ++ { ++ phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); ++ //DbgPrint("=STEP= change ADDA Path from B to A Path\n"); ++ } ++ else ++ { ++ phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); ++ } ++ //3 end ++ //===================================== ++ ++ PHY_SetBBReg(pAdapter, rPdp_AntA, bMaskDWord, 0x01017038); ++ } ++ ++ if(t==0) ++ { ++ pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); ++ } ++ ++ if(!pHalData->bRfPiEnable){ ++ // Switch BB to PI mode to do IQ Calibration. ++ phy_PIModeSwitch(pAdapter, TRUE); ++ } ++ ++ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); ++ PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xf00000, 0x0f); ++ else ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); ++ } ++ ++ if(is2T) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); ++ } ++ ++ //MAC settings ++ phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); ++ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x0f600000); ++ ++ if(is2T) ++ { ++ PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x0f600000); ++ } ++ } ++ else ++ { ++ //Page B init ++ PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); ++ ++ if(is2T) ++ { ++ PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); ++ } ++ } ++ // IQ calibration setting ++ RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000); ++ PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); ++ PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); ++ ++ for(i = 0 ; i < retryCount ; i++){ ++ PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); ++ if(PathAOK == 0x03){ ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); ++ result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; ++ result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK ++ { ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); ++ ++ result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ } ++ } ++ ++ if(0x00 == PathAOK){ ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); ++ } ++ ++ if(is2T){ ++ phy_PathAStandBy(pAdapter); ++ ++ // Turn Path B ADDA on ++ phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); ++ ++ for(i = 0 ; i < retryCount ; i++){ ++ PathBOK = phy_PathB_IQK_8192C(pAdapter); ++ if(PathBOK == 0x03){ ++ RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); ++ result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; ++ result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK ++ { ++ RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); ++ result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ } ++ } ++ ++ if(0x00 == PathBOK){ ++ RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); ++ } ++ } ++ ++ //Back to BB mode, load original value ++ RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0); ++ ++ if(t!=0) ++ { ++ if(!pHalData->bRfPiEnable){ ++ // Switch back BB to SI mode after finish IQ Calibration. ++ phy_PIModeSwitch(pAdapter, FALSE); ++ } ++ ++ // Reload ADDA power saving parameters ++ phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); ++ ++ // Reload MAC parameters ++ phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); ++ ++ // Reload BB parameters ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ if(is2T) ++ phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D); ++ else ++ phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D -1); ++ } ++ else ++ phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); ++ ++ if(!IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ // Restore RX initial gain ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); ++ if(is2T){ ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); ++ } ++ } ++ //load 0xe30 IQC default value ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ ++ } ++ RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); ++ ++} ++ ++ ++VOID ++phy_LCCalibrate92C( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++ u1Byte tmpReg; ++ u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ //Check continuous TX and Packet TX ++ tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); ++ ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX ++ else // Deal with Packet TX case ++ PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues ++ ++ if((tmpReg&0x70) != 0) ++ { ++ //1. Read original RF mode ++ //Path-A ++ RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); ++ ++ //Path-B ++ if(is2T) ++ RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); ++ ++ //2. Set RF mode = standby mode ++ //Path-A ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); ++ ++ //Path-B ++ if(is2T) ++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); ++ } ++ ++ //3. Read RF reg18 ++ LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); ++ ++ //4. Set LC calibration begin bit15 ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); ++ ++ delay_ms(100); ++ ++ ++ //Restore original situation ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ { ++ //Path-A ++ PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); ++ ++ //Path-B ++ if(is2T) ++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); ++ } ++ else // Deal with Packet TX case ++ { ++ PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); ++ } ++} ++ ++ ++VOID ++phy_LCCalibrate( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++#if SWLCK == 1 ++ phy_LCCalibrate92DSW(pAdapter, is2T); ++#else ++ phy_LCCalibrate92D(pAdapter, is2T); ++#endif ++ } ++ else ++ { ++ phy_LCCalibrate92C(pAdapter, is2T); ++ } ++} ++ ++ ++ ++//Analog Pre-distortion calibration ++#define APK_BB_REG_NUM 8 ++#define APK_CURVE_REG_NUM 4 ++#define PATH_NUM 2 ++ ++VOID ++phy_APCalibrate_8192C( ++ IN PADAPTER pAdapter, ++ IN s1Byte delta, ++ IN BOOLEAN is2T ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ u4Byte regD[PATH_NUM]; ++ u4Byte tmpReg, index, offset, i, apkbound; ++ u1Byte path, pathbound = PATH_NUM; ++ u4Byte BB_backup[APK_BB_REG_NUM]; ++ u4Byte BB_REG[APK_BB_REG_NUM] = { ++ rFPGA1_TxBlock, rOFDM0_TRxPathEnable, ++ rFPGA0_RFMOD, rOFDM0_TRMuxPar, ++ rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, ++ rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; ++ u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x00204000 }; ++ u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x22204000 }; ++ ++ u4Byte AFE_backup[IQK_ADDA_REG_NUM]; ++ u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth, ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN }; ++ ++ u4Byte MAC_backup[IQK_MAC_REG_NUM]; ++ u4Byte MAC_REG[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, ++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; ++ ++ u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, ++ {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} ++ }; ++ ++ u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings ++ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} ++ }; ++ ++ u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, ++ {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} ++ }; ++ ++ u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} ++ }; ++#if 0 ++ u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, ++ {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} ++ }; ++#endif ++ u4Byte AFE_on_off[PATH_NUM] = { ++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on ++ ++ u4Byte APK_offset[PATH_NUM] = { ++ rConfig_AntA, rConfig_AntB}; ++ ++ u4Byte APK_normal_offset[PATH_NUM] = { ++ rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; ++ ++ u4Byte APK_value[PATH_NUM] = { ++ 0x92fc0000, 0x12fc0000}; ++ ++ u4Byte APK_normal_value[PATH_NUM] = { ++ 0x92680000, 0x12680000}; ++ ++ s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} ++ }; ++ ++ u4Byte APK_normal_setting_value_1[13] = { ++ 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, ++ 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, ++ 0x12680000, 0x00880000, 0x00880000 ++ }; ++ ++ u4Byte APK_normal_setting_value_2[16] = { ++ 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, ++ 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, ++ 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, ++ 0x00050006 ++ }; ++ ++ u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a ++// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; ++ ++ s4Byte BB_offset, delta_V, delta_offset; ++ ++#if MP_DRIVER == 1 ++if (pAdapter->registrypriv.mp_mode == 1) ++{ ++ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); ++ ++ pMptCtx->APK_bound[0] = 45; ++ pMptCtx->APK_bound[1] = 52; ++} ++#endif ++ ++ RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); ++ RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); ++ if(!is2T) ++ pathbound = 1; ++ ++ //2 FOR NORMAL CHIP SETTINGS ++ ++// Temporarily do not allow normal driver to do the following settings because these offset ++// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal ++// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the ++// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. ++#if MP_DRIVER != 1 ++ return; ++#endif ++ ++ if (pAdapter->registrypriv.mp_mode != 1) ++ return; ++ ++ //settings adjust for normal chip ++ for(index = 0; index < PATH_NUM; index ++) ++ { ++ APK_offset[index] = APK_normal_offset[index]; ++ APK_value[index] = APK_normal_value[index]; ++ AFE_on_off[index] = 0x6fdb25a4; ++ } ++ ++ for(index = 0; index < APK_BB_REG_NUM; index ++) ++ { ++ for(path = 0; path < pathbound; path++) ++ { ++ APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; ++ APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; ++ } ++ BB_AP_MODE[index] = BB_normal_AP_MODE[index]; ++ } ++ ++ apkbound = 6; ++ ++ //save BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(index == 0) //skip ++ continue; ++ BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); ++ } ++ ++ //save MAC default value ++ phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); ++ ++ //save AFE default value ++ phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ ++ ++ if(path == RF_PATH_A) ++ { ++ //path A APK ++ //load APK setting ++ //path-A ++ offset = rPdp_AntA; ++ for(index = 0; index < 11; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); ++ ++ offset = rConfig_AntA; ++ for(; index < 13; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ++ //path A ++ offset = rPdp_AntA; ++ for(index = 0; index < 16; index++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ } ++ else if(path == RF_PATH_B) ++ { ++ //path B APK ++ //load APK setting ++ //path-B ++ offset = rPdp_AntB; ++ for(index = 0; index < 10; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); ++ ++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); ++ ++ offset = rConfig_AntA; ++ index = 11; ++ for(; index < 13; index ++) //offset 0xb68, 0xb6c ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ++ //path B ++ offset = 0xb60; ++ for(index = 0; index < 16; index++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ } ++ ++ //save RF default value ++ regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); ++ ++ //Path A AFE all on, path B AFE All off or vise versa ++ for(index = 0; index < IQK_ADDA_REG_NUM ; index++) ++ PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); ++ ++ //BB to AP mode ++ if(path == 0) ++ { ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ ++ if(index == 0) //skip ++ continue; ++ else if (index < 5) ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); ++ else if (BB_REG[index] == 0x870) ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); ++ else ++ PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); ++ } ++ ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ } ++ else //path B ++ { ++ PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); ++ ++ } ++ ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); ++ ++ //MAC settings ++ phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); ++ ++ if(path == RF_PATH_A) //Path B to standby mode ++ { ++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); ++ } ++ else //Path A to standby mode ++ { ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); ++ } ++ ++ delta_offset = ((delta+14)/2); ++ if(delta_offset < 0) ++ delta_offset = 0; ++ else if (delta_offset > 12) ++ delta_offset = 12; ++ ++ //AP calibration ++ for(index = 0; index < APK_BB_REG_NUM; index++) ++ { ++ if(index != 1) //only DO PA11+PAD01001, AP RF setting ++ continue; ++ ++ tmpReg = APK_RF_init_value[path][index]; ++#if 1 ++ if(!pHalData->bAPKThermalMeterIgnore) ++ { ++ BB_offset = (tmpReg & 0xF0000) >> 16; ++ ++ if(!(tmpReg & BIT15)) //sign bit 0 ++ { ++ BB_offset = -BB_offset; ++ } ++ ++ delta_V = APK_delta_mapping[index][delta_offset]; ++ ++ BB_offset += delta_V; ++ ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); ++ ++ if(BB_offset < 0) ++ { ++ tmpReg = tmpReg & (~BIT15); ++ BB_offset = -BB_offset; ++ } ++ else ++ { ++ tmpReg = tmpReg | BIT15; ++ } ++ tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); ++ } ++#endif ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) ++ PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); ++ else ++#endif ++ PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); ++ PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); ++ PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); ++ ++ // PA11+PAD01111, one shot ++ i = 0; ++ do ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80000000); ++ { ++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); ++ delay_ms(3); ++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); ++ ++ delay_ms(20); ++ } ++ PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ++ if(path == RF_PATH_A) ++ tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); ++ else ++ tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); ++ RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); ++ ++ ++ i++; ++ } ++ while(tmpReg > apkbound && i < 4); ++ ++ APK_result[path][index] = tmpReg; ++ } ++ } ++ ++ //reload MAC default value ++ phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); ++ ++ //reload BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ ++ if(index == 0) //skip ++ continue; ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); ++ } ++ ++ //reload AFE default value ++ phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++ ++ //reload RF path default value ++ for(path = 0; path < pathbound; path++) ++ { ++ PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); ++ if(path == RF_PATH_B) ++ { ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); ++ } ++ ++ //note no index == 0 ++ if (APK_result[path][1] > 6) ++ APK_result[path][1] = 6; ++ RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); ++ } ++ ++ RTPRINT(FINIT, INIT_IQK, ("\n")); ++ ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); ++ if(path == RF_PATH_A) ++ PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); ++ else ++ PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); ++ ++ if(!IS_HARDWARE_TYPE_8723A(pAdapter)) ++ PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ++ ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); ++ } ++ ++ pHalData->bAPKdone = TRUE; ++ ++ RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); ++} ++ ++ ++VOID ++PHY_IQCalibrate_8192C( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bReCovery ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ s4Byte result[4][8]; //last is final result ++ u1Byte i, final_candidate, Indexforchannel; ++ BOOLEAN bPathAOK, bPathBOK; ++ s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; ++ BOOLEAN is12simular, is13simular, is23simular; ++ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; ++ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { ++ rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, ++ rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, ++ rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, ++ rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, ++ rOFDM0_RxIQExtAnta}; ++ ++ if (ODM_CheckPowerStatus(pAdapter) == FALSE) ++ return; ++ ++#if MP_DRIVER == 1 ++if (pAdapter->registrypriv.mp_mode == 1) ++{ ++ bStartContTx = pAdapter->MptCtx.bStartContTx; ++ bSingleTone = pAdapter->MptCtx.bSingleTone; ++ bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; ++} ++#endif ++ ++ //ignore IQK when continuous Tx ++ if(bStartContTx || bSingleTone || bCarrierSuppression) ++ return; ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ if(pAdapter->bSlaveOfDMSP) ++ return; ++ ++ if(!IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ if(bReCovery) ++ { ++ phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); ++ return; ++ ++ } ++ } ++ RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); ++ ++ for(i = 0; i < 8; i++) ++ { ++ result[0][i] = 0; ++ result[1][i] = 0; ++ result[2][i] = 0; ++ result[3][i] = 0; ++ } ++ final_candidate = 0xff; ++ bPathAOK = FALSE; ++ bPathBOK = FALSE; ++ is12simular = FALSE; ++ is23simular = FALSE; ++ is13simular = FALSE; ++ ++ ++ RTPRINT(FINIT, INIT_IQK, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); ++ AcquireCCKAndRWPageAControl(pAdapter); ++// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); ++ for (i=0; i<3; i++) ++ { ++// if(IS_HARDWARE_TYPE_8192C(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter)) ++ if(!IS_HARDWARE_TYPE_8192D(pAdapter)) ++ { ++ if(IS_92C_SERIAL( pHalData->VersionID)) ++ { ++ phy_IQCalibrate_8192C(pAdapter, result, i, TRUE); ++ } ++ else ++ { ++ // For 88C 1T1R ++ phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); ++ } ++ } ++ else/* if(IS_HARDWARE_TYPE_8192D(pAdapter))*/ ++ { ++ if(pHalData->CurrentBandType92D == BAND_ON_5G) ++ { ++ phy_IQCalibrate_5G_Normal(pAdapter, result, i); ++ } ++ else if(pHalData->CurrentBandType92D == BAND_ON_2_4G) ++ { ++ if(IS_92D_SINGLEPHY(pHalData->VersionID)) ++ phy_IQCalibrate_8192C(pAdapter, result, i, TRUE); ++ else ++ phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); ++ } ++ } ++ ++ if(i == 1) ++ { ++ is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); ++ if(is12simular) ++ { ++ final_candidate = 0; ++ break; ++ } ++ } ++ ++ if(i == 2) ++ { ++ is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); ++ if(is13simular) ++ { ++ final_candidate = 0; ++ break; ++ } ++ ++ is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); ++ if(is23simular) ++ final_candidate = 1; ++ else ++ { ++ for(i = 0; i < 8; i++) ++ RegTmp += result[3][i]; ++ ++ if(RegTmp != 0) ++ final_candidate = 3; ++ else ++ final_candidate = 0xFF; ++ } ++ } ++ } ++// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); ++ ReleaseCCKAndRWPageAControl(pAdapter); ++ ++ for (i=0; i<4; i++) ++ { ++ RegE94 = result[i][0]; ++ RegE9C = result[i][1]; ++ RegEA4 = result[i][2]; ++ RegEAC = result[i][3]; ++ RegEB4 = result[i][4]; ++ RegEBC = result[i][5]; ++ RegEC4 = result[i][6]; ++ RegECC = result[i][7]; ++ RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); ++ } ++ ++ if(final_candidate != 0xff) ++ { ++ pHalData->RegE94 = RegE94 = result[final_candidate][0]; ++ pHalData->RegE9C = RegE9C = result[final_candidate][1]; ++ RegEA4 = result[final_candidate][2]; ++ RegEAC = result[final_candidate][3]; ++ pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; ++ pHalData->RegEBC = RegEBC = result[final_candidate][5]; ++ RegEC4 = result[final_candidate][6]; ++ RegECC = result[final_candidate][7]; ++ RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); ++ RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); ++ bPathAOK = bPathBOK = TRUE; ++ } ++ else ++ { ++ RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value ++ RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value ++ } ++ ++ if((RegE94 != 0)/*&&(RegEA4 != 0)*/) ++ { ++ if(pHalData->CurrentBandType92D == BAND_ON_5G) ++ phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); ++ else ++ phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); ++ ++ } ++ ++ if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) ++ { ++ if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) ++ { ++ if(pHalData->CurrentBandType92D == BAND_ON_5G) ++ phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); ++ else ++ phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); ++ } ++ } ++ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter) && final_candidate != 0xFF) ++ { ++ Indexforchannel = GetRightChnlPlaceforIQK(pHalData->CurrentChannel); ++ ++ for(i = 0; i < IQK_Matrix_REG_NUM; i++) ++ pHalData->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = ++ result[final_candidate][i]; ++ ++ pHalData->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; ++ ++ RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); ++ } ++ ++ if(!IS_HARDWARE_TYPE_8192D(pAdapter)) ++ phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); ++ ++} ++ ++ ++VOID ++PHY_LCCalibrate_8192C( ++ IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; ++ PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; ++ PMGNT_INFO pMgntInfoBuddyAdapter; ++ u4Byte timeout = 2000, timecount = 0; ++ PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; ++ ++#if MP_DRIVER == 1 ++if (pAdapter->registrypriv.mp_mode == 1) ++{ ++ bStartContTx = pAdapter->MptCtx.bStartContTx; ++ bSingleTone = pAdapter->MptCtx.bSingleTone; ++ bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; ++} ++#endif ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ //ignore LCK when continuous Tx ++ if(bStartContTx || bSingleTone || bCarrierSuppression) ++ return; ++ ++ if(BuddyAdapter != NULL && ++ ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType92D == BAND_ON_2_4G) || ++ (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType92D == BAND_ON_5G))) ++ { ++ pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; ++ while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) ++ { ++ delay_ms(50); ++ timecount += 50; ++ } ++ } ++ ++ while(pMgntInfo->bScanInProgress && timecount < timeout) ++ { ++ delay_ms(50); ++ timecount += 50; ++ } ++ ++ pHalData->bLCKInProgress = TRUE; ++ ++ RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, timecount)); ++ ++ //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) ++ if(IS_2T2R(pHalData->VersionID)) ++ { ++ phy_LCCalibrate(pAdapter, TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ phy_LCCalibrate(pAdapter, FALSE); ++ } ++ ++ pHalData->bLCKInProgress = FALSE; ++ ++ RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); ++ ++ ++} ++ ++VOID ++PHY_APCalibrate_8192C( ++ IN PADAPTER pAdapter, ++ IN s1Byte delta ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 ++ return; ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ if(IS_HARDWARE_TYPE_8192D(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter)) ++ return; ++ ++#if FOR_BRAZIL_PRETEST != 1 ++ if(pHalData->bAPKdone) ++#endif ++ return; ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ phy_APCalibrate_8192C(pAdapter, delta, TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ phy_APCalibrate_8192C(pAdapter, delta, FALSE); ++ } ++} ++ ++ ++#endif ++ ++ ++//3============================================================ ++//3 IQ Calibration ++//3============================================================ ++ ++VOID ++ODM_ResetIQKResult( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u1Byte i; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP || DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++ if (!IS_HARDWARE_TYPE_8192D(Adapter)) ++ return; ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM)); ++ //0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc ++ ++ for(i = 0; i < IQK_Matrix_Settings_NUM; i++) ++ { ++ { ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100; ++ ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] = ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0; ++ ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].bIQKDone = FALSE; ++ ++ } ++ } ++ ++} ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) ++{ ++ u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = ++ {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; ++ u1Byte place = chnl; ++ ++ ++ if(chnl > 14) ++ { ++ for(place = 14; place To DO modify ++u4Byte EDCAParam[HT_IOT_PEER_MAX][3] = ++{ // UL DL ++ {0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP ++ {0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP ++ {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 2:unknown AP => realtek_92SE ++ {0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP ++ {0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP ++ {0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP ++ //{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP ++ {0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP ++ //{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP ++ {0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP ++ //{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP ++ {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP ++ {0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP ++// {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP ++}; ++//============================================================ ++// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 ++//============================================================ ++#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL) ++enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG }; ++ ++static const struct ParaRecord rtl_ap_EDCA[] = ++{ ++//ACM,AIFSN, ECWmin, ECWmax, TXOplimit ++ {0, 7, 4, 10, 0}, //BK ++ {0, 3, 4, 6, 0}, //BE ++ {0, 1, 3, 4, 188}, //VI ++ {0, 1, 2, 3, 102}, //VO ++ {0, 1, 3, 4, 94}, //VI_AG ++ {0, 1, 2, 3, 47}, //VO_AG ++}; ++ ++static const struct ParaRecord rtl_sta_EDCA[] = ++{ ++//ACM,AIFSN, ECWmin, ECWmax, TXOplimit ++ {0, 7, 4, 10, 0}, ++ {0, 3, 4, 10, 0}, ++ {0, 2, 3, 4, 188}, ++ {0, 2, 2, 3, 102}, ++ {0, 2, 3, 4, 94}, ++ {0, 2, 2, 3, 47}, ++}; ++#endif ++ ++//============================================================ ++// Global var ++//============================================================ ++u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { ++ 0x7f8001fe, // 0, +6.0dB ++ 0x788001e2, // 1, +5.5dB ++ 0x71c001c7, // 2, +5.0dB ++ 0x6b8001ae, // 3, +4.5dB ++ 0x65400195, // 4, +4.0dB ++ 0x5fc0017f, // 5, +3.5dB ++ 0x5a400169, // 6, +3.0dB ++ 0x55400155, // 7, +2.5dB ++ 0x50800142, // 8, +2.0dB ++ 0x4c000130, // 9, +1.5dB ++ 0x47c0011f, // 10, +1.0dB ++ 0x43c0010f, // 11, +0.5dB ++ 0x40000100, // 12, +0dB ++ 0x3c8000f2, // 13, -0.5dB ++ 0x390000e4, // 14, -1.0dB ++ 0x35c000d7, // 15, -1.5dB ++ 0x32c000cb, // 16, -2.0dB ++ 0x300000c0, // 17, -2.5dB ++ 0x2d4000b5, // 18, -3.0dB ++ 0x2ac000ab, // 19, -3.5dB ++ 0x288000a2, // 20, -4.0dB ++ 0x26000098, // 21, -4.5dB ++ 0x24000090, // 22, -5.0dB ++ 0x22000088, // 23, -5.5dB ++ 0x20000080, // 24, -6.0dB ++ 0x1e400079, // 25, -6.5dB ++ 0x1c800072, // 26, -7.0dB ++ 0x1b00006c, // 27. -7.5dB ++ 0x19800066, // 28, -8.0dB ++ 0x18000060, // 29, -8.5dB ++ 0x16c0005b, // 30, -9.0dB ++ 0x15800056, // 31, -9.5dB ++ 0x14400051, // 32, -10.0dB ++ 0x1300004c, // 33, -10.5dB ++ 0x12000048, // 34, -11.0dB ++ 0x11000044, // 35, -11.5dB ++ 0x10000040, // 36, -12.0dB ++ 0x0f00003c,// 37, -12.5dB ++ 0x0e400039,// 38, -13.0dB ++ 0x0d800036,// 39, -13.5dB ++ 0x0cc00033,// 40, -14.0dB ++ 0x0c000030,// 41, -14.5dB ++ 0x0b40002d,// 42, -15.0dB ++}; ++ ++ ++u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { ++ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB ++ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB ++ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB ++ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB ++ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB ++ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB ++ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB ++ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB ++ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB ++ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB ++ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB ++ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB ++ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB ++ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB ++ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB ++ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB ++ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB ++ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB ++ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB ++ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB ++ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB ++ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB ++ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB ++ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB ++ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB ++ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB ++ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB ++ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB ++ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB ++ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB ++ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB ++ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB ++ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB ++}; ++ ++ ++u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { ++ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB ++ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB ++ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB ++ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB ++ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB ++ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB ++ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB ++ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB ++ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB ++ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB ++ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB ++ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB ++ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB ++ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB ++ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB ++ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB ++ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB ++ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB ++ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB ++ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB ++ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB ++ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB ++ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB ++ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB ++ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB ++ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB ++ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB ++ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB ++ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB ++ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB ++ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB ++ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB ++ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB ++}; ++ ++ ++#ifdef AP_BUILD_WORKAROUND ++ ++unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { ++ /* +6.0dB */ 0x7f8001fe, ++ /* +5.5dB */ 0x788001e2, ++ /* +5.0dB */ 0x71c001c7, ++ /* +4.5dB */ 0x6b8001ae, ++ /* +4.0dB */ 0x65400195, ++ /* +3.5dB */ 0x5fc0017f, ++ /* +3.0dB */ 0x5a400169, ++ /* +2.5dB */ 0x55400155, ++ /* +2.0dB */ 0x50800142, ++ /* +1.5dB */ 0x4c000130, ++ /* +1.0dB */ 0x47c0011f, ++ /* +0.5dB */ 0x43c0010f, ++ /* 0.0dB */ 0x40000100, ++ /* -0.5dB */ 0x3c8000f2, ++ /* -1.0dB */ 0x390000e4, ++ /* -1.5dB */ 0x35c000d7, ++ /* -2.0dB */ 0x32c000cb, ++ /* -2.5dB */ 0x300000c0, ++ /* -3.0dB */ 0x2d4000b5, ++ /* -3.5dB */ 0x2ac000ab, ++ /* -4.0dB */ 0x288000a2, ++ /* -4.5dB */ 0x26000098, ++ /* -5.0dB */ 0x24000090, ++ /* -5.5dB */ 0x22000088, ++ /* -6.0dB */ 0x20000080, ++ /* -6.5dB */ 0x1a00006c, ++ /* -7.0dB */ 0x1c800072, ++ /* -7.5dB */ 0x18000060, ++ /* -8.0dB */ 0x19800066, ++ /* -8.5dB */ 0x15800056, ++ /* -9.0dB */ 0x26c0005b, ++ /* -9.5dB */ 0x14400051, ++ /* -10.0dB */ 0x24400051, ++ /* -10.5dB */ 0x1300004c, ++ /* -11.0dB */ 0x12000048, ++ /* -11.5dB */ 0x11000044, ++ /* -12.0dB */ 0x10000040 ++}; ++#endif ++ ++//============================================================ ++// Local Function predefine. ++//============================================================ ++ ++//START------------COMMON INFO RELATED---------------// ++VOID ++odm_CommonInfoSelfInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_CommonInfoSelfUpdate( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_CmnInfoInit_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_CmnInfoHook_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_CmnInfoUpdate_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ); ++/* ++VOID ++odm_FindMinimumRSSI( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_IsLinked( ++ IN PDM_ODM_T pDM_Odm ++ ); ++*/ ++//END------------COMMON INFO RELATED---------------// ++ ++//START---------------DIG---------------------------// ++VOID ++odm_FalseAlarmCounterStatistics( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DIGInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DIG( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_CCKPacketDetectionThresh( ++ IN PDM_ODM_T pDM_Odm ++ ); ++//END---------------DIG---------------------------// ++ ++//START-------BB POWER SAVE-----------------------// ++VOID ++odm_DynamicBBPowerSavingInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicBBPowerSaving( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_1R_CCA( ++ IN PDM_ODM_T pDM_Odm ++ ); ++VOID ++odm_AdaptivityInit( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++VOID ++odm_Adaptivity( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte IGI ++); ++//END---------BB POWER SAVE-----------------------// ++ ++//START-----------------PSD-----------------------// ++#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++//============================================================ ++// Function predefine. ++//============================================================ ++VOID odm_PathDiversityInit_92C( IN PADAPTER Adapter); ++VOID odm_2TPathDiversityInit_92C( IN PADAPTER Adapter); ++VOID odm_1TPathDiversityInit_92C( IN PADAPTER Adapter); ++BOOLEAN odm_IsConnected_92C(IN PADAPTER Adapter); ++VOID odm_PathDiversityAfterLink_92C( IN PADAPTER Adapter); ++ ++VOID ++odm_CCKTXPathDiversityCallback( ++ PRT_TIMER pTimer ++ ); ++ ++VOID ++odm_CCKTXPathDiversityWorkItemCallback( ++ IN PVOID pContext ++ ); ++ ++VOID ++odm_PathDivChkAntSwitchCallback( ++ PRT_TIMER pTimer ++ ); ++ ++VOID ++odm_PathDivChkAntSwitchWorkitemCallback( ++ IN PVOID pContext ++ ); ++ ++VOID odm_SetRespPath_92C( IN PADAPTER Adapter, IN u1Byte DefaultRespPath); ++VOID odm_OFDMTXPathDiversity_92C( IN PADAPTER Adapter); ++VOID odm_CCKTXPathDiversity_92C( IN PADAPTER Adapter); ++VOID odm_ResetPathDiversity_92C( IN PADAPTER Adapter); ++ ++//Start-------------------- RX High Power------------------------// ++VOID odm_RXHPInit( IN PDM_ODM_T pDM_Odm); ++VOID odm_RXHP( IN PDM_ODM_T pDM_Odm); ++VOID odm_Write_RXHP( IN PDM_ODM_T pDM_Odm); ++ ++VOID odm_PSD_RXHP( IN PDM_ODM_T pDM_Odm); ++VOID odm_PSD_RXHPCallback( PRT_TIMER pTimer); ++VOID odm_PSD_RXHPWorkitemCallback( IN PVOID pContext); ++//End--------------------- RX High Power -----------------------// ++ ++VOID ++odm_PathDivInit( IN PDM_ODM_T pDM_Odm); ++ ++VOID ++odm_SetRespPath_92C( ++ IN PADAPTER Adapter, ++ IN u1Byte DefaultRespPath ++ ); ++ ++#endif ++//END-------------------PSD-----------------------// ++ ++VOID ++odm_RefreshRateAdaptiveMaskMP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_RefreshRateAdaptiveMaskCE( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_RefreshRateAdaptiveMaskAPADSL( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPowerInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPowerRestorePowerIndex( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPowerNIC( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++VOID ++odm_DynamicTxPowerSavePowerIndex( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPowerWritePowerIndex( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Value); ++ ++VOID ++odm_DynamicTxPower_92C( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPower_92D( ++ IN PDM_ODM_T pDM_Odm ++ ); ++#endif ++ ++ ++VOID ++odm_RSSIMonitorInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_RSSIMonitorCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_RSSIMonitorCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ); ++VOID ++odm_RSSIMonitorCheckAP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++ ++VOID ++odm_RSSIMonitorCheck( ++ IN PDM_ODM_T pDM_Odm ++ ); ++VOID ++odm_DynamicTxPower( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_DynamicTxPowerAP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++VOID ++odm_SwAntDivInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_SwAntDivInit_NIC( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_SwAntDivChkAntSwitch( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Step ++ ); ++ ++VOID ++odm_SwAntDivChkAntSwitchNIC( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Step ++ ); ++ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++odm_SwAntDivChkAntSwitchCallback( ++ PRT_TIMER pTimer ++); ++VOID ++odm_SwAntDivChkAntSwitchWorkitemCallback( ++ IN PVOID pContext ++ ); ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); ++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); ++#endif ++ ++ ++ ++VOID ++odm_GlobalAdapterCheck( ++ IN VOID ++ ); ++ ++VOID ++odm_RefreshRateAdaptiveMask( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++ODM_TXPowerTrackingCheck( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_TXPowerTrackingCheckAP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++ ++ ++ ++ ++ ++VOID ++odm_RateAdaptiveMaskInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_TXPowerTrackingThermalMeterInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++VOID ++odm_TXPowerTrackingInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_TXPowerTrackingCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++VOID ++odm_TXPowerTrackingCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++ ++VOID ++ODM_RateAdaptiveStateApInit( ++ IN PADAPTER Adapter , ++ IN PRT_WLAN_STA pEntry ++ ); ++ ++VOID ++odm_TXPowerTrackingCallbackThermalMeter92C( ++ IN PADAPTER Adapter ++ ); ++ ++VOID ++odm_TXPowerTrackingCallbackRXGainThermalMeter92D( ++ IN PADAPTER Adapter ++ ); ++ ++VOID ++odm_TXPowerTrackingCallbackThermalMeter92D( ++ IN PADAPTER Adapter ++ ); ++ ++VOID ++odm_TXPowerTrackingDirectCall92C( ++ IN PADAPTER Adapter ++ ); ++ ++VOID ++odm_TXPowerTrackingThermalMeterCheck( ++ IN PADAPTER Adapter ++ ); ++ ++#endif ++ ++VOID ++odm_EdcaTurboCheck( ++ IN PDM_ODM_T pDM_Odm ++ ); ++VOID ++ODM_EdcaTurboInit( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++VOID ++odm_EdcaTurboCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++//check if edca turbo is disabled ++BOOLEAN ++odm_IsEdcaTurboDisable( ++ IN PDM_ODM_T pDM_Odm ++); ++//choose edca paramter for special IOT case ++VOID ++ODM_EdcaParaSelByIot( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u4Byte *EDCA_BE_UL, ++ OUT u4Byte *EDCA_BE_DL ++ ); ++//check if it is UL or DL ++VOID ++odm_EdcaChooseTrafficIdx( ++ IN PDM_ODM_T pDM_Odm, ++ IN u8Byte cur_tx_bytes, ++ IN u8Byte cur_rx_bytes, ++ IN BOOLEAN bBiasOnRx, ++ OUT BOOLEAN *pbIsCurRDLState ++ ); ++ ++#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) ++VOID ++odm_EdcaTurboCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ); ++#else ++VOID ++odm_IotEngine( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++odm_EdcaParaInit( ++ IN PDM_ODM_T pDM_Odm ++ ); ++#endif ++ ++ ++ ++#define RxDefaultAnt1 0x65a9 ++#define RxDefaultAnt2 0x569a ++ ++VOID ++odm_InitHybridAntDiv( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++BOOLEAN ++odm_StaDefAntSel( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte OFDM_Ant1_Cnt, ++ IN u4Byte OFDM_Ant2_Cnt, ++ IN u4Byte CCK_Ant1_Cnt, ++ IN u4Byte CCK_Ant2_Cnt, ++ OUT u1Byte *pDefAnt ++ ); ++ ++VOID ++odm_SetRxIdleAnt( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Ant, ++ IN BOOLEAN bDualPath ++); ++ ++ ++ ++VOID ++odm_HwAntDiv( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++ ++ ++ ++ ++#if 0 ++//#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&defined(HW_ANT_SWITCH)) ++VOID ++odm_HW_AntennaSwitchInit( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++VOID ++odm_SetRxIdleAnt( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Ant ++); ++ ++VOID ++odm_StaAntSelect( ++ IN PDM_ODM_T pDM_Odm, ++ IN struct stat_info *pstat ++); ++ ++VOID ++odm_HW_IdleAntennaSelect( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++u1Byte ++ODM_Diversity_AntennaSelect( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte *data ++); ++#endif ++ ++ ++//============================================================ ++//3 Export Interface ++//============================================================ ++ ++// ++// 2011/09/21 MH Add to describe different team necessary resource allocate?? ++// ++VOID ++ODM_DMInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++#if (FPGA_TWO_MAC_VERIFICATION == 1) ++ odm_RateAdaptiveMaskInit(pDM_Odm); ++ return; ++#endif ++ ++ //2012.05.03 Luke: For all IC series ++ odm_CommonInfoSelfInit(pDM_Odm); ++ odm_CmnInfoInit_Debug(pDM_Odm); ++ odm_DIGInit(pDM_Odm); ++ odm_AdaptivityInit(pDM_Odm); ++ odm_RateAdaptiveMaskInit(pDM_Odm); ++ ++ if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) ++ { ++ ++ } ++ else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ { ++ #if (RTL8188E_SUPPORT == 1) ++ odm_PrimaryCCA_Init(pDM_Odm); // Gary ++ #endif ++ odm_DynamicBBPowerSavingInit(pDM_Odm); ++ odm_DynamicTxPowerInit(pDM_Odm); ++ odm_TXPowerTrackingInit(pDM_Odm); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ odm_PSDMonitorInit(pDM_Odm); ++ odm_RXHPInit(pDM_Odm); ++ odm_PathDivInit(pDM_Odm); //92D Path Div Init //Neil Chen ++ #endif ++ ODM_EdcaTurboInit(pDM_Odm); ++ #if (RTL8188E_SUPPORT == 1) ++ ODM_RAInfo_Init_all(pDM_Odm); ++ #endif ++ if( ( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV ) || ++ ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV ) || ++ ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV )) ++ { ++ odm_InitHybridAntDiv(pDM_Odm); ++ } ++ else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) ++ { ++ odm_SwAntDivInit(pDM_Odm); ++ } ++ } ++} ++ ++// ++// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. ++// You can not add any dummy function here, be care, you can only use DM structure ++// to perform any new ODM_DM. ++// ++VOID ++ODM_DMWatchdog( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ //2012.05.03 Luke: For all IC series ++ odm_GlobalAdapterCheck(); ++ odm_CmnInfoHook_Debug(pDM_Odm); ++ odm_CmnInfoUpdate_Debug(pDM_Odm); ++ odm_CommonInfoSelfUpdate(pDM_Odm); ++ odm_FalseAlarmCounterStatistics(pDM_Odm); ++ odm_RSSIMonitorCheck(pDM_Odm); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++//#ifdef CONFIG_PLATFORM_SPRD ++ //For CE Platform(SPRD or Tablet) ++ //8723A or 8189ES platform ++ //NeilChen--2012--08--24-- ++ //Fix Leave LPS issue ++ if( (adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode != PS_MODE_ACTIVE) &&// in LPS mode ++ ( ++ (pDM_Odm->SupportICType & (ODM_RTL8723A ) )|| ++ (pDM_Odm->SupportICType & (ODM_RTL8188E) )//&&((pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) ) ++ ++ ) ++ ) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); ++ odm_DIGbyRSSI_LPS(pDM_Odm); ++ } ++ else ++//#endif ++#endif ++ { ++ odm_DIG(pDM_Odm); ++ } ++ ++ ++ odm_CCKPacketDetectionThresh(pDM_Odm); ++ ++ if(*(pDM_Odm->pbPowerSaving)==TRUE) ++ return; ++ ++ odm_Adaptivity(pDM_Odm, pDM_Odm->DM_DigTable.CurIGValue); ++ ++ ++ odm_RefreshRateAdaptiveMask(pDM_Odm); ++ ++ #if (RTL8192D_SUPPORT == 1) ++ ODM_DynamicEarlyMode(pDM_Odm); ++ #endif ++ odm_DynamicBBPowerSaving(pDM_Odm); ++ #if (RTL8188E_SUPPORT == 1) ++ odm_DynamicPrimaryCCA(pDM_Odm); ++ #endif ++ if( ( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV ) || ++ ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV ) || ++ ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV )) ++ { ++ odm_HwAntDiv(pDM_Odm); ++ } ++ else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) ++ { ++ odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK); ++ } ++ ++ if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) ++ { ++ ++ } ++ else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ { ++ ODM_TXPowerTrackingCheck(pDM_Odm); ++ odm_EdcaTurboCheck(pDM_Odm); ++ odm_DynamicTxPower(pDM_Odm); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ odm_RXHP(pDM_Odm); ++ #endif ++ } ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ odm_dtc(pDM_Odm); ++#endif ++} ++ ++ ++// ++// Init /.. Fixed HW value. Only init time. ++// ++VOID ++ODM_CmnInfoInit( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN u4Byte Value ++ ) ++{ ++ //ODM_RT_TRACE(pDM_Odm,); ++ ++ // ++ // This section is used for init value ++ // ++ switch (CmnInfo) ++ { ++ // ++ // Fixed ODM value. ++ // ++ case ODM_CMNINFO_ABILITY: ++ pDM_Odm->SupportAbility = (u4Byte)Value; ++ break; ++ case ODM_CMNINFO_PLATFORM: ++ pDM_Odm->SupportPlatform = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_INTERFACE: ++ pDM_Odm->SupportInterface = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_MP_TEST_CHIP: ++ pDM_Odm->bIsMPChip= (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_IC_TYPE: ++ pDM_Odm->SupportICType = Value; ++ break; ++ ++ case ODM_CMNINFO_CUT_VER: ++ pDM_Odm->CutVersion = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_FAB_VER: ++ pDM_Odm->FabVersion = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_RF_TYPE: ++ pDM_Odm->RFType = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_RF_ANTENNA_TYPE: ++ pDM_Odm->AntDivType= (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_BOARD_TYPE: ++ pDM_Odm->BoardType = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_EXT_LNA: ++ pDM_Odm->ExtLNA = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_EXT_PA: ++ pDM_Odm->ExtPA = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_EXT_TRSW: ++ pDM_Odm->ExtTRSW = (u1Byte)Value; ++ break; ++ case ODM_CMNINFO_PATCH_ID: ++ pDM_Odm->PatchID = (u1Byte)Value; ++ break; ++ case ODM_CMNINFO_BINHCT_TEST: ++ pDM_Odm->bInHctTest = (BOOLEAN)Value; ++ break; ++ case ODM_CMNINFO_BWIFI_TEST: ++ pDM_Odm->bWIFITest = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_SMART_CONCURRENT: ++ pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; ++ break; ++ ++ //To remove the compiler warning, must add an empty default statement to handle the other values. ++ default: ++ //do nothing ++ break; ++ ++ } ++ ++ ++} ++ ++ ++VOID ++ODM_CmnInfoHook( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN PVOID pValue ++ ) ++{ ++ // ++ // Hook call by reference pointer. ++ // ++ switch (CmnInfo) ++ { ++ // ++ // Dynamic call by reference pointer. ++ // ++ case ODM_CMNINFO_MAC_PHY_MODE: ++ pDM_Odm->pMacPhyMode = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_TX_UNI: ++ pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_RX_UNI: ++ pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_WM_MODE: ++ pDM_Odm->pWirelessMode = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_BAND: ++ pDM_Odm->pBandType = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_SEC_CHNL_OFFSET: ++ pDM_Odm->pSecChOffset = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_SEC_MODE: ++ pDM_Odm->pSecurity = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_BW: ++ pDM_Odm->pBandWidth = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_CHNL: ++ pDM_Odm->pChannel = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_DMSP_GET_VALUE: ++ pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_BUDDY_ADAPTOR: ++ pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; ++ break; ++ ++ case ODM_CMNINFO_DMSP_IS_MASTER: ++ pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_SCAN: ++ pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_POWER_SAVING: ++ pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_ONE_PATH_CCA: ++ pDM_Odm->pOnePathCCA = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_DRV_STOP: ++ pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_PNP_IN: ++ pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_INIT_ON: ++ pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; ++ break; ++ ++ case ODM_CMNINFO_ANT_TEST: ++ pDM_Odm->pAntennaTest = (u1Byte *)pValue; ++ break; ++ ++ case ODM_CMNINFO_NET_CLOSED: ++ pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; ++ break; ++ case ODM_CMNINFO_MP_MODE: ++ pDM_Odm->mp_mode = (u1Byte *)pValue; ++ break; ++ ++ //case ODM_CMNINFO_BT_COEXIST: ++ // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; ++ ++ //case ODM_CMNINFO_STA_STATUS: ++ //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; ++ //break; ++ ++ //case ODM_CMNINFO_PHY_STATUS: ++ // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; ++ // break; ++ ++ //case ODM_CMNINFO_MAC_STATUS: ++ // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; ++ // break; ++ //To remove the compiler warning, must add an empty default statement to handle the other values. ++ default: ++ //do nothing ++ break; ++ ++ } ++ ++} ++ ++ ++VOID ++ODM_CmnInfoPtrArrayHook( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN u2Byte Index, ++ IN PVOID pValue ++ ) ++{ ++ // ++ // Hook call by reference pointer. ++ // ++ switch (CmnInfo) ++ { ++ // ++ // Dynamic call by reference pointer. ++ // ++ case ODM_CMNINFO_STA_STATUS: ++ pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; ++ break; ++ //To remove the compiler warning, must add an empty default statement to handle the other values. ++ default: ++ //do nothing ++ break; ++ } ++ ++} ++ ++ ++// ++// Update Band/CHannel/.. The values are dynamic but non-per-packet. ++// ++VOID ++ODM_CmnInfoUpdate( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte CmnInfo, ++ IN u8Byte Value ++ ) ++{ ++ // ++ // This init variable may be changed in run time. ++ // ++ switch (CmnInfo) ++ { ++ case ODM_CMNINFO_ABILITY: ++ pDM_Odm->SupportAbility = (u4Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_RF_TYPE: ++ pDM_Odm->RFType = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_WIFI_DIRECT: ++ pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_WIFI_DISPLAY: ++ pDM_Odm->bWIFI_Display = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_LINK: ++ pDM_Odm->bLinked = (BOOLEAN)Value; ++ break; ++ case ODM_CMNINFO_STATION_STATE: ++ pDM_Odm->bsta_state = (BOOLEAN)Value; ++ break; ++ case ODM_CMNINFO_RSSI_MIN: ++ pDM_Odm->RSSI_Min= (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_DBG_COMP: ++ pDM_Odm->DebugComponents = Value; ++ break; ++ ++ case ODM_CMNINFO_DBG_LEVEL: ++ pDM_Odm->DebugLevel = (u4Byte)Value; ++ break; ++ case ODM_CMNINFO_RA_THRESHOLD_HIGH: ++ pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_RA_THRESHOLD_LOW: ++ pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; ++ break; ++#if(BT_30_SUPPORT == 1) ++ // The following is for BT HS mode and BT coexist mechanism. ++ case ODM_CMNINFO_BT_DISABLED: ++ pDM_Odm->bBtDisabled = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_BT_OPERATION: ++ pDM_Odm->bBtHsOperation = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_BT_DIG: ++ pDM_Odm->btHsDigVal = (u1Byte)Value; ++ break; ++ ++ case ODM_CMNINFO_BT_BUSY: ++ pDM_Odm->bBtBusy = (BOOLEAN)Value; ++ break; ++ ++ case ODM_CMNINFO_BT_DISABLE_EDCA: ++ pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; ++ break; ++#endif ++ ++ } ++ ++ ++} ++ ++VOID ++odm_CommonInfoSelfInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x824, BIT9); ++ pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F); ++#if (DM_ODM_SUPPORT_TYPE != ODM_CE) ++ pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; ++#endif ++ if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D)) ++ { ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++ pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; ++#elif (defined(CONFIG_SW_ANTENNA_DIVERSITY)) ++ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ++#endif ++ } ++ if(pDM_Odm->SupportICType & (ODM_RTL8723A)) ++ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ++ ++ ODM_InitDebugSetting(pDM_Odm); ++} ++ ++VOID ++odm_CommonInfoSelfUpdate( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u1Byte EntryCnt=0; ++ u1Byte i; ++ PSTA_INFO_T pEntry; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ pEntry = pDM_Odm->pODM_StaInfo[0]; ++ if(pMgntInfo->mAssoc) ++ { ++ pEntry->bUsed=TRUE; ++ for (i=0; i<6; i++) ++ pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; ++ } ++ else ++ { ++ pEntry->bUsed=FALSE; ++ for (i=0; i<6; i++) ++ pEntry->MacAddr[i] = 0; ++ } ++#endif ++ ++ ++ if(*(pDM_Odm->pBandWidth) == ODM_BW40M) ++ { ++ if(*(pDM_Odm->pSecChOffset) == 1) ++ pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2; ++ else if(*(pDM_Odm->pSecChOffset) == 2) ++ pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2; ++ } ++ else ++ pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); ++ ++ for (i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pEntry)) ++ EntryCnt++; ++ } ++ if(EntryCnt == 1) ++ pDM_Odm->bOneEntryOnly = TRUE; ++ else ++ pDM_Odm->bOneEntryOnly = FALSE; ++} ++ ++VOID ++odm_CmnInfoInit_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) ); ++ ++} ++ ++VOID ++odm_CmnInfoHook_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) ); ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->pBandType) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) ); ++ if(pDM_Odm->pMacPhyMode) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) ); ++ if(pDM_Odm->pBuddyAdapter) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) ); ++ if(pDM_Odm->pBuddyAdapter) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) ); ++ if(pDM_Odm->pbMasterOfDMSP) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) ); ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) ); ++ ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) ); ++} ++ ++VOID ++odm_CmnInfoUpdate_Debug( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) ); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) ); ++} ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) ++{ ++#if USE_WORKITEM ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ ++ ODM_InitializeWorkItem( pDM_Odm, ++ &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem, ++ (RT_WORKITEM_CALL_BACK)odm_SwAntDivChkAntSwitchWorkitemCallback, ++ (PVOID)pAdapter, ++ "AntennaSwitchWorkitem" ++ ); ++ ++ ODM_InitializeWorkItem( ++ pDM_Odm, ++ &(pDM_Odm->PathDivSwitchWorkitem), ++ (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, ++ (PVOID)pAdapter, ++ "SWAS_WorkItem"); ++ ++ ODM_InitializeWorkItem( ++ pDM_Odm, ++ &(pDM_Odm->CCKPathDiversityWorkitem), ++ (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, ++ (PVOID)pAdapter, ++ "CCKTXPathDiversityWorkItem"); ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++#if (RTL8188E_SUPPORT == 1) ++ ODM_InitializeWorkItem( ++ pDM_Odm, ++ &(pDM_Odm->FastAntTrainingWorkitem), ++ (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, ++ (PVOID)pAdapter, ++ "FastAntTrainingWorkitem"); ++#endif ++#endif ++ ODM_InitializeWorkItem( ++ pDM_Odm, ++ &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem), ++ (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback, ++ (PVOID)pAdapter, ++ "PSDRXHP_WorkItem"); ++#endif ++} ++ ++VOID ++ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) ++{ ++#if USE_WORKITEM ++ ODM_FreeWorkItem( &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem)); ++ ++ ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); ++ ++ ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); ++ ++ ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); ++ ++ ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem)); ++#endif ++ ++} ++#endif ++ ++/* ++VOID ++odm_FindMinimumRSSI( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u4Byte i; ++ u1Byte RSSI_Min = 0xFF; ++ ++ for(i=0; ipODM_StaInfo[i] != NULL) ++ if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) ++ { ++ if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) ++ { ++ RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; ++ } ++ } ++ } ++ ++ pDM_Odm->RSSI_Min = RSSI_Min; ++ ++} ++ ++VOID ++odm_IsLinked( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u4Byte i; ++ BOOLEAN Linked = FALSE; ++ ++ for(i=0; ipODM_StaInfo[i]) ) ++ { ++ Linked = TRUE; ++ break; ++ } ++ ++ } ++ ++ pDM_Odm->bLinked = Linked; ++} ++*/ ++ ++ ++//3============================================================ ++//3 DIG ++//3============================================================ ++/*----------------------------------------------------------------------------- ++ * Function: odm_DIGInit() ++ * ++ * Overview: Set DIG scheme init value. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++ODM_ChangeDynamicInitGainThresh( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte DM_Type, ++ IN u4Byte DM_Value ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ if (DM_Type == DIG_TYPE_THRESH_HIGH) ++ { ++ pDM_DigTable->RssiHighThresh = DM_Value; ++ } ++ else if (DM_Type == DIG_TYPE_THRESH_LOW) ++ { ++ pDM_DigTable->RssiLowThresh = DM_Value; ++ } ++ else if (DM_Type == DIG_TYPE_ENABLE) ++ { ++ pDM_DigTable->Dig_Enable_Flag = TRUE; ++ } ++ else if (DM_Type == DIG_TYPE_DISABLE) ++ { ++ pDM_DigTable->Dig_Enable_Flag = FALSE; ++ } ++ else if (DM_Type == DIG_TYPE_BACKOFF) ++ { ++ if(DM_Value > 30) ++ DM_Value = 30; ++ pDM_DigTable->BackoffVal = (u1Byte)DM_Value; ++ } ++ else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) ++ { ++ if(DM_Value == 0) ++ DM_Value = 0x1; ++ pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; ++ } ++ else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) ++ { ++ if(DM_Value > 0x50) ++ DM_Value = 0x50; ++ pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; ++ } ++} /* DM_ChangeDynamicInitGainThresh */ ++ ++int getIGIForDiff(int value_IGI) ++{ ++ #define ONERCCA_LOW_TH 0x30 ++ #define ONERCCA_LOW_DIFF 8 ++ ++ if (value_IGI < ONERCCA_LOW_TH) { ++ if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) ++ return ONERCCA_LOW_TH; ++ else ++ return value_IGI + ONERCCA_LOW_DIFF; ++ } else { ++ return value_IGI; ++ } ++} ++ ++ ++// Add by Neil Chen to enable edcca to MP Platform ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++VOID ++odm_EnableEDCCA( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ ++ // This should be moved out of OUTSRC ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ // Enable EDCCA. The value is suggested by SD3 Wilson. ++ ++ // ++ // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13. ++ // ++ if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter))) ++ { ++ //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00); ++ ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00); ++ ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD); ++ ++ } ++ else ++ { ++ //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03); ++ ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03); ++ ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00); ++ } ++ ++ //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00); ++} ++ ++VOID ++odm_DisableEDCCA( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ // Disable EDCCA.. ++ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f); ++ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f); ++} ++ ++// ++// Description: According to initial gain value to determine to enable or disable EDCCA. ++// ++// Suggested by SD3 Wilson. Added by tynli. 2011.11.25. ++// ++VOID ++odm_DynamicEDCCA( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u1Byte RegC50, RegC58; ++ BOOLEAN bEDCCAenable = FALSE; ++ ++ RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); ++ RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); ++ ++ ++ if((RegC50 > 0x28 && RegC58 > 0x28) || ++ ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) || ++ (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) ++ { ++ if(!pHalData->bPreEdccaEnable) ++ { ++ odm_EnableEDCCA(pDM_Odm); ++ pHalData->bPreEdccaEnable = TRUE; ++ } ++ ++ } ++ else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) ++ { ++ if(pHalData->bPreEdccaEnable) ++ { ++ odm_DisableEDCCA(pDM_Odm); ++ pHalData->bPreEdccaEnable = FALSE; ++ } ++ } ++} ++ ++ ++#endif // end MP platform support ++ ++VOID ++ODM_Write_DIG( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte CurrentIGI ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n", ++ ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); ++ ++ if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI) ++ { ++ if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) ++ { ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ } ++ else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++ switch(*(pDM_Odm->pOnePathCCA)) ++ { ++ case ODM_CCA_2R: ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ break; ++ case ODM_CCA_1R_A: ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); ++ break; ++ case ODM_CCA_1R_B: ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); ++ break; ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI)); ++ //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; ++ pDM_DigTable->CurIGValue = CurrentIGI; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI)); ++ ++// Add by Neil Chen to enable edcca to MP Platform ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ // Adjust EDCCA. ++ if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ odm_DynamicEDCCA(pDM_Odm); ++#endif ++ ++ ++} ++ ++ ++//Need LPS mode for CE platform --2012--08--24--- ++//8723AS/8189ES ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ ++VOID ++odm_DIGbyRSSI_LPS( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ PADAPTER pAdapter =pDM_Odm->Adapter; ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; ++ ++#if 0 //and 2.3.5 coding rule ++ struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++#endif ++ ++ u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C ++ u1Byte bFwCurrentInPSMode = FALSE; ++ u1Byte CurrentIGI=pDM_Odm->RSSI_Min; ++ ++ if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E))) ++ return; ++ ++ //if((pDM_Odm->SupportInterface==ODM_ITRF_PCIE)||(pDM_Odm->SupportInterface ==ODM_ITRF_USB)) ++ // return; ++ ++ CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; ++#ifdef CONFIG_LPS ++ bFwCurrentInPSMode = adapter_to_pwrctl(pAdapter)->bFwCurrentInPSMode; ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("==>pDM_Odm->RSSI_Min=%d ()\n",pDM_Odm->RSSI_Min)); ++ ++ // Using FW PS mode to make IGI ++ if(bFwCurrentInPSMode) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); ++ //Adjust by FA in LPS MODE ++ if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) ++ CurrentIGI = CurrentIGI+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) ++ CurrentIGI = CurrentIGI+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) ++ CurrentIGI = CurrentIGI-1; ++ } ++ else ++ { ++ CurrentIGI = RSSI_Lower; ++ } ++ ++ //Lower bound checking ++ ++ //RSSI Lower bound check ++ if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) ++ RSSI_Lower =(pDM_Odm->RSSI_Min-10); ++ else ++ RSSI_Lower =DM_DIG_MIN_NIC; ++ ++ //Upper and Lower Bound checking ++ if(CurrentIGI > DM_DIG_MAX_NIC) ++ CurrentIGI=DM_DIG_MAX_NIC; ++ else if(CurrentIGI < RSSI_Lower) ++ CurrentIGI =RSSI_Lower; ++ ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ ++} ++#endif ++ ++VOID ++odm_AdaptivityInit( ++IN PDM_ODM_T pDM_Odm ++) ++{ ++ if(pDM_Odm->SupportICType == ODM_RTL8723B) ++ { ++ pDM_Odm->TH_L2H_ini = 0xf8; // -8 ++ } ++ if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE)) ++ { ++ pDM_Odm->TH_L2H_ini = 0xf0; // -16 ++ } ++ else ++ { ++ pDM_Odm->TH_L2H_ini = 0xf9; // -7 ++ } ++ ++ pDM_Odm->TH_EDCCA_HL_diff = 7; ++ pDM_Odm->IGI_Base = 0x32; ++ pDM_Odm->IGI_target = 0x1c; ++ pDM_Odm->ForceEDCCA = 0; ++ pDM_Odm->AdapEn_RSSI = 20; ++ ++ //Reg524[11]=0 is easily to transmit packets during adaptivity test ++ ++ //ODM_SetBBReg(pDM_Odm, 0x524, BIT11, 1);// stop counting if EDCCA is asserted ++} ++ ++ ++VOID ++odm_Adaptivity( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte IGI ++) ++{ ++ s1Byte TH_L2H_dmc, TH_H2L_dmc; ++ s1Byte TH_L2H, TH_H2L, Diff, IGI_target; ++ u4Byte value32; ++ BOOLEAN EDCCA_State = 0; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN bFwCurrentInPSMode=FALSE; ++ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); ++ ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode)); ++ ++ // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14. ++ if(bFwCurrentInPSMode) ++ return; ++#endif ++ ++ if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n")); ++ // Add by Neil Chen to enable edcca to MP Platform ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ // Adjust EDCCA. ++ if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ odm_DynamicEDCCA(pDM_Odm); ++#endif ++ return; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n")); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n", ++ pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI)); ++ ++ if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) ++ ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable ++ ++ if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) // Band4 doesn't need adaptivity ++ { ++ if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ { ++ ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f); ++ ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f); ++ } ++ else ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f); ++ return; ++ } ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ if(pMgntInfo->IOTPeer == HT_IOT_PEER_BROADCOM) ++ ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0a); ++ else ++ ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0e); ++#endif ++ if(!pDM_Odm->ForceEDCCA) ++ { ++ if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI) ++ EDCCA_State = 1; ++ else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5)) ++ EDCCA_State = 0; ++ } ++ else ++ EDCCA_State = 1; ++ //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G)) ++ //IGI_target = pDM_Odm->IGI_Base; ++ //else ++ { ++ ++ if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20 ++ IGI_target = pDM_Odm->IGI_Base; ++ else if(*pDM_Odm->pBandWidth == ODM_BW40M) ++ IGI_target = pDM_Odm->IGI_Base + 2; ++ else if(*pDM_Odm->pBandWidth == ODM_BW80M) ++ IGI_target = pDM_Odm->IGI_Base + 6; ++ else ++ IGI_target = pDM_Odm->IGI_Base; ++ } ++ ++ pDM_Odm->IGI_target = (u1Byte) IGI_target; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n", ++ (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State)); ++ ++ if(EDCCA_State == 1) ++ { ++ Diff = IGI_target -(s1Byte)IGI; ++ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; ++ if(TH_L2H_dmc > 10) TH_L2H_dmc = 10; ++ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; ++ } ++ else ++ { ++ TH_L2H_dmc = 0x7f; ++ TH_H2L_dmc = 0x7f; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", ++ IGI, TH_L2H_dmc, TH_H2L_dmc)); ++ ++ if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ { ++ ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc); ++ ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc); ++ } ++ else ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc); ++} ++ ++#if 1 ++VOID ++odm_DIGInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ //pDM_DigTable->Dig_Enable_Flag = TRUE; ++ //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; ++ pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); ++ //pDM_DigTable->PreIGValue = 0x0; ++ //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT; ++ //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; ++ pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; ++ pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; ++ pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; ++ pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; ++ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)) ++ { ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; ++ } ++ else ++ { ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; ++ } ++ pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; ++ pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; ++ pDM_DigTable->PreCCK_CCAThres = 0xFF; ++ pDM_DigTable->CurCCK_CCAThres = 0x83; ++ pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; ++ pDM_DigTable->LargeFAHit = 0; ++ pDM_DigTable->Recover_cnt = 0; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; ++ pDM_DigTable->bMediaConnect_0 = FALSE; ++ pDM_DigTable->bMediaConnect_1 = FALSE; ++ ++ //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error ++ pDM_Odm->bDMInitialGainEnable = TRUE; ++ ++ //To Initi BT30 IGI ++ pDM_DigTable->BT30_CurIGI=0x32; ++ ++} ++ ++VOID ++odm_DigForBtHsMode( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ pDIG_T pDM_DigTable=&pDM_Odm->DM_DigTable; ++ u1Byte digForBtHs=0; ++ u1Byte digUpBound=0x5a; ++ ++ if(pDM_Odm->bBtConnectProcess) ++ { ++ if(pDM_Odm->SupportICType&(ODM_RTL8723A)) ++ digForBtHs = 0x28; ++ else ++ digForBtHs = 0x22; ++ } ++ else ++ { ++ // ++ // Decide DIG value by BT HS RSSI. ++ // ++ digForBtHs = pDM_Odm->btHsRssi+4; ++ ++ //DIG Bound ++ if(pDM_Odm->SupportICType&(ODM_RTL8723A)) ++ digUpBound = 0x3e; ++ ++ if(digForBtHs > digUpBound) ++ digForBtHs = digUpBound; ++ if(digForBtHs < 0x1c) ++ digForBtHs = 0x1c; ++ ++ // update Current IGI ++ pDM_DigTable->BT30_CurIGI = digForBtHs; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs)); ++#endif ++} ++ ++VOID ++odm_DIG( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ u1Byte DIG_Dynamic_MIN; ++ u1Byte DIG_MaxOfMin; ++ BOOLEAN FirstConnect, FirstDisConnect; ++ u1Byte dm_dig_max, dm_dig_min, offset; ++ u1Byte CurrentIGI = pDM_DigTable->CurIGValue; ++ u1Byte Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u1Byte) pDM_Odm->TH_L2H_ini -(u1Byte) pDM_Odm->TH_EDCCA_HL_diff; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++// This should be moved out of OUTSRC ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++#if OS_WIN_FROM_WIN7(OS_VERSION) ++ if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n")); ++ return; ++ } ++#endif ++/* ++ if (pDM_Odm->SupportICType==ODM_RTL8723B) ++ return; ++*/ ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtHsOperation) ++ { ++ odm_DigForBtHsMode(pDM_Odm); ++ } ++#endif ++ if(!(pDM_Odm->SupportICType &(ODM_RTL8723A|ODM_RTL8188E))) ++ { ++ if(pRX_HP_Table->RXHP_flag == 1) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n")); ++ return; ++ } ++ } ++#endif ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) ++ { ++ printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); ++ ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); ++ return; ++ } ++#endif ++#endif ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ if (!((priv->up_time > 5) && (priv->up_time % 2)) ) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period \n")); ++ return; ++ } ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); ++ //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) ++ if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) ++ { ++#if 0 ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++ if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1)) ++ CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30; ++ else ++ CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20; ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); ++ return; ++ } ++ ++ if(*(pDM_Odm->pbScanInProcess)) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n")); ++ return; ++ } ++ ++ //add by Neil Chen to avoid PSD is processing ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ if(pDM_Odm->bDMInitialGainEnable == FALSE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n")); ++ return; ++ } ++ } ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) ++ { ++ if(*(pDM_Odm->pbMasterOfDMSP)) ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); ++ } ++ } ++ else ++ { ++ if(*(pDM_Odm->pBandType) == ODM_BAND_5G) ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); ++ } ++ } ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ ++ //1 Boundary Decision ++ if(pDM_Odm->SupportICType & (ODM_RTL8192C) &&(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))) ++ { ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++ ++ dm_dig_max = DM_DIG_MAX_AP_HP; ++ dm_dig_min = DM_DIG_MIN_AP_HP; ++ } ++ else ++ { ++ dm_dig_max = DM_DIG_MAX_NIC_HP; ++ dm_dig_min = DM_DIG_MIN_NIC_HP; ++ } ++ DIG_MaxOfMin = DM_DIG_MAX_AP_HP; ++ } ++ else ++ { ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#ifdef DFS ++ if (!priv->pmib->dot11DFSEntry.disable_DFS && ++ (OPMODE & WIFI_AP_STATE) && ++ (((pDM_Odm->ControlChannel >= 52) && ++ (pDM_Odm->ControlChannel <= 64)) || ++ ((pDM_Odm->ControlChannel >= 100) && ++ (pDM_Odm->ControlChannel <= 140)))) ++ dm_dig_max = 0x24; ++ else ++#endif ++ if (priv->pmib->dot11RFEntry.tx2path) { ++ if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B) ++ dm_dig_max = 0x2A; ++ else ++ dm_dig_max = 0x32; ++ } ++ else ++#endif ++ dm_dig_max = DM_DIG_MAX_AP; ++ dm_dig_min = DM_DIG_MIN_AP; ++ DIG_MaxOfMin = dm_dig_max; ++ } ++ else ++ { ++ if((pDM_Odm->SupportICType >= ODM_RTL8188E) && (pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) ++ dm_dig_max = 0x5A; ++ else ++ dm_dig_max = DM_DIG_MAX_NIC; ++ ++ if(pDM_Odm->SupportICType != ODM_RTL8821) ++ dm_dig_min = DM_DIG_MIN_NIC; ++ else ++ dm_dig_min = 0x1C; ++ ++ DIG_MaxOfMin = DM_DIG_MAX_AP; ++ } ++ } ++ ++ ++ if(pDM_Odm->bLinked) ++ { ++ if(pDM_Odm->SupportICType&(ODM_RTL8723A/*|ODM_RTL8821*/)) ++ { ++ //2 Upper Bound ++ if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC ) ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC ) ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; ++ ++ //BT is Concurrent ++ ++ if(pDM_Odm->bBtLimitedDig) ++ { ++ if(pDM_Odm->RSSI_Min>10) ++ { ++ if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC) ++ DIG_Dynamic_MIN = DM_DIG_MAX_NIC; ++ else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC) ++ DIG_Dynamic_MIN = DM_DIG_MIN_NIC; ++ else ++ DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10; ++ } ++ else ++ DIG_Dynamic_MIN=DM_DIG_MIN_NIC; ++ } ++ else ++ { ++ if((pDM_Odm->RSSI_Min + 20) > dm_dig_max ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_min; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; ++ ++ } ++ } ++ else ++ { ++ if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)){ ++ //2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT ++ if((pDM_Odm->RSSI_Min + 10) > dm_dig_max ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ else if((pDM_Odm->RSSI_Min + 10) < dm_dig_min ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_min; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; ++ } ++ else{ ++ ++ //2 Modify DIG upper bound ++ //2013.03.19 Luke: Modified upper bound for Netgear rental house test ++ if(pDM_Odm->SupportICType != ODM_RTL8821) ++ offset = 20; ++ else ++ offset = 10; ++ ++ if((pDM_Odm->RSSI_Min + offset) > dm_dig_max ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_min; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset; ++ ++ } ++ ++ //2 Modify DIG lower bound ++ /* ++ if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25)) ++ DIG_Dynamic_MIN++; ++ else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min)) ++ DIG_Dynamic_MIN--; ++ */ ++ ++ ++ //1 Lower Bound for 88E AntDiv ++#if (RTL8188E_SUPPORT == 1) ++ if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) ++ { ++ if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) ++ { ++ DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); ++ } ++ } ++ else ++#endif ++ { ++ if(pDM_Odm->SupportICType != ODM_RTL8723B) ++ offset = 0; ++ else ++ offset = 12; ++ ++ if(pDM_Odm->RSSI_Min - offset < dm_dig_min) ++ DIG_Dynamic_MIN = dm_dig_min; ++ else if (pDM_Odm->RSSI_Min - offset > DIG_MaxOfMin) ++ DIG_Dynamic_MIN = DIG_MaxOfMin; ++ else ++ DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - offset; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE, DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min)); ++ } ++ ++ ++ } ++ } ++ else ++ { ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ DIG_Dynamic_MIN = dm_dig_min; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); ++ } ++ ++ //1 Modify DIG lower bound, deal with abnorally large false alarm ++ if(pFalseAlmCnt->Cnt_all > 10000) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); ++ ++ if(pDM_DigTable->LargeFAHit != 3) ++ pDM_DigTable->LargeFAHit++; ++ if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) ++ { ++ pDM_DigTable->ForbiddenIGI = (u1Byte)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; ++ pDM_DigTable->LargeFAHit = 1; ++ } ++ ++ if(pDM_DigTable->LargeFAHit >= 3) ++ { ++ if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max) ++ pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; ++ else ++ pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); ++ pDM_DigTable->Recover_cnt = 3600; //3600=2hr ++ } ++ ++ } ++ else ++ { ++ //Recovery mechanism for IGI lower bound ++ if(pDM_DigTable->Recover_cnt != 0) ++ pDM_DigTable->Recover_cnt --; ++ else ++ { ++ if(pDM_DigTable->LargeFAHit < 3) ++ { ++ if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN) ++ { ++ pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; ++ pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); ++ } ++ else ++ { ++ pDM_DigTable->ForbiddenIGI --; ++ pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); ++ } ++ } ++ else ++ { ++ pDM_DigTable->LargeFAHit = 0; ++ } ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit)); ++ ++ if((pDM_Odm->SupportPlatform&(ODM_MP|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 10) && (pDM_Odm->bsta_state)) ++ pDM_DigTable->rx_gain_range_min = dm_dig_min; ++ ++ if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) ++ pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; ++ ++ //1 Adjust initial gain by false alarm ++ if(pDM_Odm->bLinked) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); ++ if(FirstConnect) ++ { ++ if(pDM_Odm->RSSI_Min <= DIG_MaxOfMin) ++ CurrentIGI = pDM_Odm->RSSI_Min; ++ else ++ CurrentIGI = DIG_MaxOfMin; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); ++ ++ //ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); ++ } ++ else ++ { ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) ++ CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) ++ CurrentIGI = CurrentIGI + 2; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) ++ CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ } ++ else ++ { ++ //FA for Combo IC--NeilChen--2012--09--28 ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ //WLAN and BT ConCurrent ++ if(pDM_Odm->bBtLimitedDig) ++ { ++ if(pFalseAlmCnt->Cnt_all > 0x300) ++ CurrentIGI = CurrentIGI + 4; ++ else if (pFalseAlmCnt->Cnt_all > 0x250) ++ CurrentIGI = CurrentIGI + 2; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ CurrentIGI = CurrentIGI -2; ++ } ++ else //Not Concurrent ++ { ++ if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) ++ CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) ++ CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ } ++ } ++ else ++ { ++ if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) ++ CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) ++ CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ ++ if((pDM_Odm->SupportPlatform&(ODM_MP|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 10) ++ &&(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) ++ { ++ CurrentIGI = pDM_DigTable->rx_gain_range_min; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Beacon is less than 10 and FA is less than 768, IGI GOES TO 0x1E!!!!!!!!!!!!\n")); ++ } ++ } ++ } ++ } ++ } ++ else ++ { ++ //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); ++ if(FirstDisConnect) ++ { ++ CurrentIGI = pDM_DigTable->rx_gain_range_min; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n")); ++ } ++ else ++ { ++ //2012.03.30 LukeLee: enable DIG before link but with very high thresholds ++ if(pFalseAlmCnt->Cnt_all > 10000) ++ CurrentIGI = CurrentIGI + 4; ++ else if (pFalseAlmCnt->Cnt_all > 8000) ++ CurrentIGI = CurrentIGI + 2; ++ else if(pFalseAlmCnt->Cnt_all < 500) ++ CurrentIGI = CurrentIGI - 2; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n")); ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); ++ //1 Check initial gain by upper/lower bound ++ ++ if(CurrentIGI > pDM_DigTable->rx_gain_range_max) ++ CurrentIGI = pDM_DigTable->rx_gain_range_max; ++ if(CurrentIGI < pDM_DigTable->rx_gain_range_min) ++ CurrentIGI = pDM_DigTable->rx_gain_range_min; ++ ++ if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) ++ { ++ if(CurrentIGI > Adap_IGI_Upper) ++ CurrentIGI = Adap_IGI_Upper; ++ ++ if(CurrentIGI > (pDM_Odm->IGI_target + 4)) ++ CurrentIGI = (u1Byte)pDM_Odm->IGI_target + 4; ++ } ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", ++ pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); ++ ++ //2 High power RSSI threshold ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); ++ //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); ++ // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue ++ u8Byte curTxOkCnt=0, curRxOkCnt=0; ++ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ ++ //u8Byte OKCntAll=0; ++ //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; ++ //u8Byte CurByteCnt=0, PreByteCnt=0; ++ ++ curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; ++ curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; ++ lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast; ++ lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast; ++ //----------------------------------------------------------end for LC Mocca issue ++ if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD)) ++ { ++ // High power IGI lower bound ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB)); ++ if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue)); ++ //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; ++ CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; ++ } ++ } ++ if((pDM_Odm->SupportICType & ODM_RTL8723A) && ++ IS_WIRELESS_MODE_G(pAdapter)) ++ { ++ if(pHalData->UndecoratedSmoothedPWDB > 0x28) ++ { ++ if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND) ++ { ++ //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; ++ CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; ++ } ++ } ++ } ++#if 0 ++ if((pDM_Odm->SupportICType & ODM_RTL8723A)&&(pMgntInfo->CustomerID = RT_CID_LENOVO_CHINA)) ++ { ++ OKCntAll = (curTxOkCnt+curRxOkCnt); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", CurrentIGI)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): OKCntAll(%#x)\n", OKCntAll)); ++ //8723AS_VAU ++ if(pDM_Odm->SupportInterface==ODM_ITRF_USB) ++ { ++ if(pHalData->UndecoratedSmoothedPWDB < 12) ++ { ++ if(CurrentIGI > DM_DIG_MIN_NIC) ++ { ++ if(OKCntAll >= 1500000) // >=6Mbps ++ CurrentIGI=0x1B; ++ else if(OKCntAll >= 1000000) //4Mbps ++ CurrentIGI=0x1A; ++ else if(OKCntAll >= 500000) //2Mbps ++ CurrentIGI=0x19; ++ else if(OKCntAll >= 250000) //1Mbps ++ CurrentIGI=0x18; ++ else ++ { ++ CurrentIGI=0x17; //SCAN mode ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Modify---->CurIGValue(%#x)\n", CurrentIGI)); ++ } ++ } ++ } ++#endif ++} ++#endif ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ //sherry delete DualMacSmartConncurrent 20110517 ++ if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) ++ { ++ ODM_Write_DIG_DMSP(pDM_Odm, (u1Byte)CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue); ++ if(*(pDM_Odm->pbMasterOfDMSP)) ++ { ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ else ++ { ++ pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; ++ } ++ } ++ else ++ { ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ if(*(pDM_Odm->pBandType) == ODM_BAND_5G) ++ { ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ else ++ { ++ pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; ++ } ++ } ++ } ++ else ++#endif ++ { ++ #if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtHsOperation) ++ { ++ if(pDM_Odm->bLinked) ++ { ++ if(pDM_DigTable->BT30_CurIGI > (CurrentIGI)) ++ { ++ ODM_Write_DIG(pDM_Odm, CurrentIGI); ++ ++ } ++ else ++ { ++ ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI); ++ } ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ else ++ { ++ if(pDM_Odm->bLinkInProcess) ++ { ++ ODM_Write_DIG(pDM_Odm, 0x1c); ++ } ++ else if(pDM_Odm->bBtConnectProcess) ++ { ++ ODM_Write_DIG(pDM_Odm, 0x28); ++ } ++ else ++ { ++ ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ } ++ } ++ } ++ else // BT is not using ++ #endif ++ { ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ } ++} ++ ++ ++BOOLEAN ++odm_DigAbort( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++// This should be moved out of OUTSRC ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ ++#if OS_WIN_FROM_WIN7(OS_VERSION) ++ if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n")); ++ return TRUE; ++ } ++#endif ++ ++ if(pRX_HP_Table->RXHP_flag == 1) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n")); ++ return TRUE; ++ } ++ ++ return FALSE; ++#else // For Other team any special case for DIG? ++ return FALSE; ++#endif ++ ++ ++} ++ ++ ++#else ++VOID ++odm_DIGInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ //pDM_DigTable->Dig_Enable_Flag = TRUE; ++ //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; ++ pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); ++ //pDM_DigTable->PreIGValue = 0x0; ++ //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT; ++ //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; ++ pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; ++ pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; ++ pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; ++ pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; ++ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) ++ { ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; ++ } ++ else ++ { ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; ++ } ++ pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; ++ pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; ++ pDM_DigTable->PreCCK_CCAThres = 0xFF; ++ pDM_DigTable->CurCCK_CCAThres = 0x83; ++ pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; ++ pDM_DigTable->LargeFAHit = 0; ++ pDM_DigTable->Recover_cnt = 0; ++ pDM_DigTable->DIG_Dynamic_MIN_0 =DM_DIG_MIN_NIC; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; ++ pDM_DigTable->bMediaConnect_0 = FALSE; ++ pDM_DigTable->bMediaConnect_1 = FALSE; ++ ++ //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error ++ pDM_Odm->bDMInitialGainEnable = TRUE; ++ ++} ++ ++ ++VOID ++odm_DIG( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ u1Byte DIG_Dynamic_MIN; ++ u1Byte DIG_MaxOfMin; ++ BOOLEAN FirstConnect, FirstDisConnect; ++ u1Byte dm_dig_max, dm_dig_min; ++ u1Byte CurrentIGI = pDM_DigTable->CurIGValue; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++// This should be moved out of OUTSRC ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++#if OS_WIN_FROM_WIN7(OS_VERSION) ++ if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n")); ++ return; ++ } ++#endif ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtHsOperation) ++ { ++ odm_DigForBtHsMode(pDM_Odm); ++ return; ++ } ++#endif ++ ++ if(pRX_HP_Table->RXHP_flag == 1) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n")); ++ return; ++ } ++#endif //end ODM_MP type ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) ++ { ++ printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); ++ ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); ++ return; ++ } ++#endif ++#endif ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ if (!((priv->up_time > 5) && (priv->up_time % 2)) ) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period \n")); ++ return; ++ } ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); ++ //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) ++ if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) ++ { ++#if 0 ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++ if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1)) ++ CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30; ++ else ++ CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20; ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); ++ return; ++ } ++ ++ if(*(pDM_Odm->pbScanInProcess)) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n")); ++ return; ++ } ++ ++ //add by Neil Chen to avoid PSD is processing ++ if(pDM_Odm->bDMInitialGainEnable == FALSE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n")); ++ return; ++ } ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) ++ { ++ if(*(pDM_Odm->pbMasterOfDMSP)) ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); ++ } ++ } ++ else ++ { ++ if(*(pDM_Odm->pBandType) == ODM_BAND_5G) ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); ++ } ++ } ++ } ++ else ++ { ++ DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; ++ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); ++ FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); ++ } ++ ++ //1 Boundary Decision ++ if((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && ++ ((if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))) || pDM_Odm->ExtLNA)) ++ { ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++ ++ dm_dig_max = DM_DIG_MAX_AP_HP; ++ dm_dig_min = DM_DIG_MIN_AP_HP; ++ } ++ else ++ { ++ dm_dig_max = DM_DIG_MAX_NIC_HP; ++ dm_dig_min = DM_DIG_MIN_NIC_HP; ++ } ++ DIG_MaxOfMin = DM_DIG_MAX_AP_HP; ++ } ++ else ++ { ++ if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) ++ { ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#ifdef DFS ++ if (!priv->pmib->dot11DFSEntry.disable_DFS && ++ (OPMODE & WIFI_AP_STATE) && ++ (((pDM_Odm->ControlChannel >= 52) && ++ (pDM_Odm->ControlChannel <= 64)) || ++ ((pDM_Odm->ControlChannel >= 100) && ++ (pDM_Odm->ControlChannel <= 140)))) ++ dm_dig_max = 0x24; ++ else ++#endif ++ if (priv->pmib->dot11RFEntry.tx2path) { ++ if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B) ++ dm_dig_max = 0x2A; ++ else ++ dm_dig_max = 0x32; ++ } ++ else ++#endif ++ dm_dig_max = DM_DIG_MAX_AP; ++ dm_dig_min = DM_DIG_MIN_AP; ++ DIG_MaxOfMin = dm_dig_max; ++ } ++ else ++ { ++ dm_dig_max = DM_DIG_MAX_NIC; ++ dm_dig_min = DM_DIG_MIN_NIC; ++ DIG_MaxOfMin = DM_DIG_MAX_AP; ++ } ++ } ++ ++ ++ if(pDM_Odm->bLinked) ++ { ++ //2 8723A Series, offset need to be 10 //neil ++ if(pDM_Odm->SupportICType==(ODM_RTL8723A)) ++ { ++ //2 Upper Bound ++ if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC ) ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; ++ else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC ) ++ pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; ++ ++ //2 If BT is Concurrent, need to set Lower Bound ++ ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtBusy) ++ { ++ if(pDM_Odm->RSSI_Min>10) ++ { ++ if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC) ++ DIG_Dynamic_MIN = DM_DIG_MAX_NIC; ++ else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC) ++ DIG_Dynamic_MIN = DM_DIG_MIN_NIC; ++ else ++ DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10; ++ } ++ else ++ DIG_Dynamic_MIN=DM_DIG_MIN_NIC; ++ } ++ else ++#endif ++ { ++ DIG_Dynamic_MIN=DM_DIG_MIN_NIC; ++ } ++ } ++ else ++ { ++ //2 Modify DIG upper bound ++ if((pDM_Odm->RSSI_Min + 20) > dm_dig_max ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min ) ++ pDM_DigTable->rx_gain_range_max = dm_dig_min; ++ else ++ pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; ++ ++ ++ //2 Modify DIG lower bound ++ /* ++ if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25)) ++ DIG_Dynamic_MIN++; ++ else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min)) ++ DIG_Dynamic_MIN--; ++ */ ++ if(pDM_Odm->bOneEntryOnly) ++ { ++ if(pDM_Odm->RSSI_Min < dm_dig_min) ++ DIG_Dynamic_MIN = dm_dig_min; ++ else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) ++ DIG_Dynamic_MIN = DIG_MaxOfMin; ++ else ++ DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE, DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min)); ++ } ++ //1 Lower Bound for 88E AntDiv ++#if (RTL8188E_SUPPORT == 1) ++ else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) ++ { ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ { ++ DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); ++ } ++ } ++#endif ++ else ++ { ++ DIG_Dynamic_MIN=dm_dig_min; ++ } ++ } ++ } ++ else ++ { ++ pDM_DigTable->rx_gain_range_max = dm_dig_max; ++ DIG_Dynamic_MIN = dm_dig_min; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); ++ } ++ ++ //1 Modify DIG lower bound, deal with abnormally large false alarm ++ if(pFalseAlmCnt->Cnt_all > 10000) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); ++ ++ if(pDM_DigTable->LargeFAHit != 3) ++ pDM_DigTable->LargeFAHit++; ++ if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) ++ { ++ pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; ++ pDM_DigTable->LargeFAHit = 1; ++ } ++ ++ if(pDM_DigTable->LargeFAHit >= 3) ++ { ++ if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max) ++ pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; ++ else ++ pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); ++ pDM_DigTable->Recover_cnt = 3600; //3600=2hr ++ } ++ ++ } ++ else ++ { ++ //Recovery mechanism for IGI lower bound ++ if(pDM_DigTable->Recover_cnt != 0) ++ pDM_DigTable->Recover_cnt --; ++ else ++ { ++ if(pDM_DigTable->LargeFAHit < 3) ++ { ++ if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN) ++ { ++ pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; ++ pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); ++ } ++ else ++ { ++ pDM_DigTable->ForbiddenIGI --; ++ pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); ++ } ++ } ++ else ++ { ++ pDM_DigTable->LargeFAHit = 0; ++ } ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit)); ++ ++ //1 Adjust initial gain by false alarm ++ if(pDM_Odm->bLinked) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); ++ if(FirstConnect) ++ { ++ CurrentIGI = pDM_Odm->RSSI_Min; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); ++ } ++ else ++ { ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) ++ CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) ++ CurrentIGI = CurrentIGI + 1; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) ++ CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ } ++ else ++ { ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtBusy) ++ { ++ if(pFalseAlmCnt->Cnt_all > 0x300) ++ CurrentIGI = CurrentIGI + 2; ++ else if (pFalseAlmCnt->Cnt_all > 0x250) ++ CurrentIGI = CurrentIGI + 1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ CurrentIGI = CurrentIGI -1; ++ } ++ else ++#endif ++ { ++ if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) ++ CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) ++ CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ ++ ++ } ++ } ++ } ++ } ++ else ++ { ++ //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); ++ if(FirstDisConnect) ++ { ++ CurrentIGI = pDM_DigTable->rx_gain_range_min; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n")); ++ } ++ else ++ { ++ //2012.03.30 LukeLee: enable DIG before link but with very high thresholds ++ if(pFalseAlmCnt->Cnt_all > 10000) ++ CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; ++ else if (pFalseAlmCnt->Cnt_all > 8000) ++ CurrentIGI = CurrentIGI + 1;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; ++ else if(pFalseAlmCnt->Cnt_all < 500) ++ CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n")); ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); ++ //1 Check initial gain by upper/lower bound ++/* ++ if(pDM_DigTable->CurIGValue > pDM_DigTable->rx_gain_range_max) ++ pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_max; ++ if(pDM_DigTable->CurIGValue < pDM_DigTable->rx_gain_range_min) ++ pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min; ++*/ ++ if(CurrentIGI > pDM_DigTable->rx_gain_range_max) ++ CurrentIGI = pDM_DigTable->rx_gain_range_max; ++ if(CurrentIGI < pDM_DigTable->rx_gain_range_min) ++ CurrentIGI = pDM_DigTable->rx_gain_range_min; ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", ++ pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); ++ ++ //2 High power RSSI threshold ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); ++ ++ // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue ++ u8Byte curTxOkCnt=0, curRxOkCnt=0; ++ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ ++ u8Byte OKCntAll=0; ++ //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; ++ //u8Byte CurByteCnt=0, PreByteCnt=0; ++ ++ curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; ++ curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; ++ lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast; ++ lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast; ++ //----------------------------------------------------------end for LC Mocca issue ++ if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD)) ++ { ++ // High power IGI lower bound ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB)); ++ if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue)); ++ //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; ++ CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; ++ } ++ } ++ if((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter)) ++ { ++ if(pHalData->UndecoratedSmoothedPWDB > 0x28) ++ { ++ if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND) ++ { ++ //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; ++ CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; ++ } ++ } ++ } ++} ++#endif ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ //sherry delete DualMacSmartConncurrent 20110517 ++ if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) ++ { ++ ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue); ++ if(*(pDM_Odm->pbMasterOfDMSP)) ++ { ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ else ++ { ++ pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; ++ } ++ } ++ else ++ { ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ if(*(pDM_Odm->pBandType) == ODM_BAND_5G) ++ { ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ else ++ { ++ pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; ++ } ++ } ++ } ++ else ++#endif ++ { ++ ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); ++ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; ++ pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; ++ } ++ ++} ++#endif ++//3============================================================ ++//3 FASLE ALARM CHECK ++//3============================================================ ++ ++VOID ++odm_FalseAlarmCounterStatistics( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u4Byte ret_value; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) ++ return; ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ if((pDM_Odm->SupportICType == ODM_RTL8192D) && ++ (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&& ////modify by Guo.Mingzhi 2011-12-29 ++ (!(*(pDM_Odm->pbMasterOfDMSP)))) ++ { ++ odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm); ++ return; ++ } ++#endif ++ ++ if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) ++ return; ++ ++// if(pDM_Odm->SupportICType != ODM_RTL8812) ++ if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ++ { ++ ++ //hold ofdm counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter ++ ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); ++ ++ FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + ++ FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + ++ FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; ++ ++#if (RTL8188E_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); ++ } ++#endif ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ odm_GetCCKFalseAlarm_92D(pDM_Odm); ++ } ++ else ++#endif ++ { ++ //hold cck counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); ++ ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); ++ FalseAlmCnt->Cnt_Cck_fail = ret_value; ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); ++ FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; ++ ++ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); ++ FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); ++ } ++ ++ FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + ++ FalseAlmCnt->Cnt_SB_Search_fail + ++ FalseAlmCnt->Cnt_Parity_Fail + ++ FalseAlmCnt->Cnt_Rate_Illegal + ++ FalseAlmCnt->Cnt_Crc8_fail + ++ FalseAlmCnt->Cnt_Mcs_fail + ++ FalseAlmCnt->Cnt_Cck_fail); ++ ++ FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; ++ ++#if (RTL8192C_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192C) ++ odm_ResetFACounter_92C(pDM_Odm); ++#endif ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ odm_ResetFACounter_92D(pDM_Odm); ++#endif ++ ++ if(pDM_Odm->SupportICType >=ODM_RTL8723A) ++ { ++ //reset false alarm counter registers ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); ++ //update ofdm counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter ++ ++ //reset CCK CCA counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); ++ //reset CCK FA counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", ++ FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", ++ FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", ++ FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); ++ } ++ else //FOR ODM_IC_11AC_SERIES ++ { ++ //read OFDM FA counter ++ FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); ++ FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); ++ FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; ++ ++ // reset OFDM FA coutner ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); ++ // reset CCK FA counter ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); ++} ++ ++//3============================================================ ++//3 CCK Packet Detect Threshold ++//3============================================================ ++ ++VOID ++odm_CCKPacketDetectionThresh( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ u1Byte CurCCK_CCAThres; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++//modify by Guo.Mingzhi 2011-12-29 ++ if (pDM_Odm->bDualMacSmartConcurrent == TRUE) ++// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) ++ return; ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtHsOperation) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); ++ ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); ++ return; ++ } ++#endif ++#endif ++ ++ if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) ++ return; ++ ++ if(pDM_Odm->ExtLNA) ++ return; ++ ++ if(pDM_Odm->bLinked) ++ { ++ if(pDM_Odm->RSSI_Min > 25) ++ CurCCK_CCAThres = 0xcd; ++ else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) ++ CurCCK_CCAThres = 0x83; ++ else ++ { ++ if(FalseAlmCnt->Cnt_Cck_fail > 1000) ++ CurCCK_CCAThres = 0x83; ++ else ++ CurCCK_CCAThres = 0x40; ++ } ++ } ++ else ++ { ++ if(FalseAlmCnt->Cnt_Cck_fail > 1000) ++ CurCCK_CCAThres = 0x83; ++ else ++ CurCCK_CCAThres = 0x40; ++ } ++ ++#if (RTL8192D_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres); ++ else ++#endif ++ ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); ++} ++ ++VOID ++ODM_Write_CCK_CCA_Thres( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte CurCCK_CCAThres ++ ) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 ++ { ++ ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); ++ } ++ pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; ++ pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; ++ ++} ++ ++//3============================================================ ++//3 BB Power Save ++//3============================================================ ++VOID ++odm_DynamicBBPowerSavingInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; ++ ++ pDM_PSTable->PreCCAState = CCA_MAX; ++ pDM_PSTable->CurCCAState = CCA_MAX; ++ pDM_PSTable->PreRFState = RF_MAX; ++ pDM_PSTable->CurRFState = RF_MAX; ++ pDM_PSTable->Rssi_val_min = 0; ++ pDM_PSTable->initialize = 0; ++} ++ ++ ++VOID ++odm_DynamicBBPowerSaving( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ ++ if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A)) ++ return; ++ if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) ++ return; ++ if(!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) ++ return; ++ ++ //1 2.Power Saving for 92C ++ if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) ++ { ++ odm_1R_CCA(pDM_Odm); ++ } ++ ++ // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. ++ // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. ++ //1 3.Power Saving for 88C ++ else ++ { ++ ODM_RF_Saving(pDM_Odm, FALSE); ++ } ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++} ++ ++VOID ++odm_1R_CCA( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; ++ ++ if(pDM_Odm->RSSI_Min!= 0xFF) ++ { ++ ++ if(pDM_PSTable->PreCCAState == CCA_2R) ++ { ++ if(pDM_Odm->RSSI_Min >= 35) ++ pDM_PSTable->CurCCAState = CCA_1R; ++ else ++ pDM_PSTable->CurCCAState = CCA_2R; ++ ++ } ++ else{ ++ if(pDM_Odm->RSSI_Min <= 30) ++ pDM_PSTable->CurCCAState = CCA_2R; ++ else ++ pDM_PSTable->CurCCAState = CCA_1R; ++ } ++ } ++ else{ ++ pDM_PSTable->CurCCAState=CCA_MAX; ++ } ++ ++ if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) ++ { ++ if(pDM_PSTable->CurCCAState == CCA_1R) ++ { ++ if( pDM_Odm->RFType ==ODM_2T2R ) ++ { ++ ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); ++ //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); ++ //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 ++ } ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); ++ //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); ++ } ++ pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; ++ } ++ //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA")); ++} ++ ++void ++ODM_RF_Saving( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte bForceInNormal ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE != ODM_AP) ++ pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; ++ u1Byte Rssi_Up_bound = 30 ; ++ u1Byte Rssi_Low_bound = 25; ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV ++ { ++ Rssi_Up_bound = 50 ; ++ Rssi_Low_bound = 45; ++ } ++ #endif ++ if(pDM_PSTable->initialize == 0){ ++ ++ pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; ++ pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; ++ pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; ++ pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; ++ //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); ++ pDM_PSTable->initialize = 1; ++ } ++ ++ if(!bForceInNormal) ++ { ++ if(pDM_Odm->RSSI_Min != 0xFF) ++ { ++ if(pDM_PSTable->PreRFState == RF_Normal) ++ { ++ if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) ++ pDM_PSTable->CurRFState = RF_Save; ++ else ++ pDM_PSTable->CurRFState = RF_Normal; ++ } ++ else{ ++ if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) ++ pDM_PSTable->CurRFState = RF_Normal; ++ else ++ pDM_PSTable->CurRFState = RF_Save; ++ } ++ } ++ else ++ pDM_PSTable->CurRFState=RF_MAX; ++ } ++ else ++ { ++ pDM_PSTable->CurRFState = RF_Normal; ++ } ++ ++ if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) ++ { ++ if(pDM_PSTable->CurRFState == RF_Save) ++ { ++ // 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. ++ // Suggested by SD3 Yu-Nan. 2011.01.20. ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1 ++ } ++ ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 ++ ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 ++ ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 ++ ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 ++ ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 ++ //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save")); ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); ++ ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); ++ ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); ++ ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); ++ ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0 ++ } ++ //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal")); ++ } ++ pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; ++ } ++#endif ++} ++ ++ ++//3============================================================ ++//3 RATR MASK ++//3============================================================ ++//3============================================================ ++//3 Rate Adaptive ++//3============================================================ ++ ++VOID ++odm_RateAdaptiveMaskInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; ++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive; ++ ++ pRA->RATRState = DM_RATR_STA_INIT; ++ if (pMgntInfo->DM_Type == DM_Type_ByDriver) ++ pMgntInfo->bUseRAMask = TRUE; ++ else ++ pMgntInfo->bUseRAMask = FALSE; ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ pOdmRA->Type = DM_Type_ByDriver; ++ if (pOdmRA->Type == DM_Type_ByDriver) ++ pDM_Odm->bUseRAMask = _TRUE; ++ else ++ pDM_Odm->bUseRAMask = _FALSE; ++ ++#endif ++ ++ pOdmRA->RATRState = DM_RATR_STA_INIT; ++ pOdmRA->HighRSSIThresh = 50; ++ pOdmRA->LowRSSIThresh = 20; ++} ++ ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++VOID ++ODM_RateAdaptiveStateApInit( ++ IN PADAPTER Adapter , ++ IN PRT_WLAN_STA pEntry ++ ) ++{ ++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pEntry->RateAdaptive; ++ pRA->RATRState = DM_RATR_STA_INIT; ++} ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++u4Byte ODM_Get_Rate_Bitmap( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte macid, ++ IN u4Byte ra_mask, ++ IN u1Byte rssi_level) ++{ ++ PSTA_INFO_T pEntry; ++ u4Byte rate_bitmap = 0x0fffffff; ++ u1Byte WirelessMode; ++ //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); ++ ++ ++ pEntry = pDM_Odm->pODM_StaInfo[macid]; ++ if(!IS_STA_VALID(pEntry)) ++ return ra_mask; ++ ++ WirelessMode = pEntry->wireless_mode; ++ ++ switch(WirelessMode) ++ { ++ case ODM_WM_B: ++ if(ra_mask & 0x0000000c) //11M or 5.5M enable ++ rate_bitmap = 0x0000000d; ++ else ++ rate_bitmap = 0x0000000f; ++ break; ++ ++ case (ODM_WM_A|ODM_WM_G): ++ if(rssi_level == DM_RATR_STA_HIGH) ++ rate_bitmap = 0x00000f00; ++ else ++ rate_bitmap = 0x00000ff0; ++ break; ++ ++ case (ODM_WM_B|ODM_WM_G): ++ if(rssi_level == DM_RATR_STA_HIGH) ++ rate_bitmap = 0x00000f00; ++ else if(rssi_level == DM_RATR_STA_MIDDLE) ++ rate_bitmap = 0x00000ff0; ++ else ++ rate_bitmap = 0x00000ff5; ++ break; ++ ++ case (ODM_WM_G|ODM_WM_N24G) : ++ case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : ++ case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : ++ { ++ if ( pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R) ++ { ++ if(rssi_level == DM_RATR_STA_HIGH) ++ { ++ rate_bitmap = 0x000f0000; ++ } ++ else if(rssi_level == DM_RATR_STA_MIDDLE) ++ { ++ rate_bitmap = 0x000ff000; ++ } ++ else{ ++ if (*(pDM_Odm->pBandWidth) == ODM_BW40M) ++ rate_bitmap = 0x000ff015; ++ else ++ rate_bitmap = 0x000ff005; ++ } ++ } ++ else ++ { ++ if(rssi_level == DM_RATR_STA_HIGH) ++ { ++ rate_bitmap = 0x0f8f0000; ++ } ++ else if(rssi_level == DM_RATR_STA_MIDDLE) ++ { ++ rate_bitmap = 0x0f8ff000; ++ } ++ else ++ { ++ if (*(pDM_Odm->pBandWidth) == ODM_BW40M) ++ rate_bitmap = 0x0f8ff015; ++ else ++ rate_bitmap = 0x0f8ff005; ++ } ++ } ++ } ++ break; ++ default: ++ //case WIRELESS_11_24N: ++ //case WIRELESS_11_5N: ++ if(pDM_Odm->RFType == RF_1T2R) ++ rate_bitmap = 0x000fffff; ++ else ++ rate_bitmap = 0x0fffffff; ++ break; ++ ++ } ++ ++ //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap)); ++ ++ return rate_bitmap; ++ ++} ++#endif ++ ++/*----------------------------------------------------------------------------- ++ * Function: odm_RefreshRateAdaptiveMask() ++ * ++ * Overview: Update rate table mask according to rssi ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/27/2009 hpfan Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++odm_RefreshRateAdaptiveMask( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) ++ return; ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ odm_RefreshRateAdaptiveMaskMP(pDM_Odm); ++ break; ++ ++ case ODM_CE: ++ odm_RefreshRateAdaptiveMaskCE(pDM_Odm); ++ break; ++ ++ case ODM_AP: ++ case ODM_ADSL: ++ odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); ++ break; ++ } ++ ++} ++ ++VOID ++odm_RefreshRateAdaptiveMaskMP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ PADAPTER pTargetAdapter = NULL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); ++ //PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive; ++ PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; ++ ++ if(pAdapter->bDriverStopped) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); ++ return; ++ } ++ ++ if(!pMgntInfo->bUseRAMask) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); ++ return; ++ } ++ ++ // if default port is connected, update RA table for default port (infrastructure mode only) ++ if(pAdapter->MgntInfo.mAssoc && (!ACTING_AS_AP(pAdapter))) ++ { ++ if( ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pRA->RATRState) ) ++ { ++ ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pRA->RATRState)); ++ pAdapter->HalFunc.UpdateHalRAMaskHandler( ++ pAdapter, ++ FALSE, ++ 0, ++ NULL, ++ NULL, ++ pRA->RATRState, ++ RAMask_Normal); ++ } ++ } ++ ++ // ++ // The following part configure AP/VWifi/IBSS rate adaptive mask. ++ // ++ ++ if(pMgntInfo->mIbss) ++ { ++ // Target: AP/IBSS peer. ++ pTargetAdapter = GetDefaultAdapter(pAdapter); ++ } ++ else ++ { ++ pTargetAdapter = GetFirstAPAdapter(pAdapter); ++ } ++ ++ // if extension port (softap) is started, updaet RA table for more than one clients associate ++ if(pTargetAdapter != NULL) ++ { ++ int i; ++ PRT_WLAN_STA pEntry; ++ PRATE_ADAPTIVE pEntryRA; ++ ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++#if 0 //By YJ,120208 ++ if( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated) ++ { ++ pEntry = pTargetAdapter->MgntInfo.AsocEntry+i; ++ pEntryRA = &pEntry->RateAdaptive; ++ if( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) ) ++ { ++ ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState)); ++ pAdapter->HalFunc.UpdateHalRAMaskHandler( ++ pTargetAdapter, ++ FALSE, ++ pEntry->AID+1, ++ pEntry->MacAddr, ++ pEntry, ++ pEntryRA->RATRState, ++ RAMask_Normal); ++ } ++ } ++#else ++ pEntry = AsocEntry_EnumStation(pTargetAdapter, i); ++ if(NULL != pEntry) ++ { ++ if(pEntry->bAssociated) ++ { ++ pEntryRA = &pEntry->RateAdaptive; ++ if( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) ) ++ { ++ ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState)); ++ pAdapter->HalFunc.UpdateHalRAMaskHandler( ++ pTargetAdapter, ++ FALSE, ++ pEntry->AID+1, ++ pEntry->MacAddr, ++ pEntry, ++ pEntryRA->RATRState, ++ RAMask_Normal); ++ } ++ } ++ } ++#endif ++ } ++ } ++ ++ if(pMgntInfo->bSetTXPowerTrainingByOid) ++ pMgntInfo->bSetTXPowerTrainingByOid = FALSE; ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++} ++ ++ ++VOID ++odm_RefreshRateAdaptiveMaskCE( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ u1Byte i; ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ ++ if(pAdapter->bDriverStopped) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); ++ return; ++ } ++ ++ if(!pDM_Odm->bUseRAMask) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); ++ return; ++ } ++ ++ //printk("==> %s \n",__FUNCTION__); ++ ++ for(i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pstat) ) { ++ if(IS_MCAST( pstat->hwaddr)) //if(psta->mac_id ==1) ++ continue; ++ if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) ) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); ++ //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); ++ rtw_hal_update_ra_mask(pstat, pstat->rssi_level); ++ } ++ ++ } ++ } ++ ++#endif ++} ++ ++VOID ++odm_RefreshRateAdaptiveMaskAPADSL( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ struct rtl8192cd_priv *priv = pDM_Odm->priv; ++ struct stat_info *pstat; ++ ++ if (!priv->pmib->dot11StationConfigEntry.autoRate) ++ return; ++ ++ if (list_empty(&priv->asoc_list)) ++ return; ++ ++ list_for_each_entry(pstat, &priv->asoc_list, asoc_list) { ++ if(ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, FALSE, &pstat->rssi_level) ) { ++ ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level)); ++ ++#ifdef CONFIG_RTL_88E_SUPPORT ++ if (GET_CHIP_VER(priv)==VERSION_8188E) { ++#ifdef TXREPORT ++ add_RATid(priv, pstat); ++#endif ++ } else ++#endif ++ { ++#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) ++ add_update_RATid(priv, pstat); ++#endif ++ } ++ } ++ } ++#endif ++} ++ ++// Return Value: BOOLEAN ++// - TRUE: RATRState is changed. ++BOOLEAN ++ODM_RAStateCheck( ++ IN PDM_ODM_T pDM_Odm, ++ IN s4Byte RSSI, ++ IN BOOLEAN bForceUpdate, ++ OUT pu1Byte pRATRState ++ ) ++{ ++ PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; ++ const u1Byte GoUpGap = 5; ++ u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; ++ u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; ++ u1Byte RATRState; ++ ++ // Threshold Adjustment: ++ // when RSSI state trends to go up one or two levels, make sure RSSI is high enough. ++ // Here GoUpGap is added to solve the boundary's level alternation issue. ++ switch (*pRATRState) ++ { ++ case DM_RATR_STA_INIT: ++ case DM_RATR_STA_HIGH: ++ break; ++ ++ case DM_RATR_STA_MIDDLE: ++ HighRSSIThreshForRA += GoUpGap; ++ break; ++ ++ case DM_RATR_STA_LOW: ++ HighRSSIThreshForRA += GoUpGap; ++ LowRSSIThreshForRA += GoUpGap; ++ break; ++ ++ default: ++ ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState) ); ++ break; ++ } ++ ++ // Decide RATRState by RSSI. ++ if(RSSI > HighRSSIThreshForRA) ++ RATRState = DM_RATR_STA_HIGH; ++ else if(RSSI > LowRSSIThreshForRA) ++ RATRState = DM_RATR_STA_MIDDLE; ++ else ++ RATRState = DM_RATR_STA_LOW; ++ //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI); ++ ++ if( *pRATRState!=RATRState || bForceUpdate) ++ { ++ ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) ); ++ *pRATRState = RATRState; ++ return TRUE; ++ } ++ ++ return FALSE; ++} ++ ++ ++//============================================================ ++ ++//3============================================================ ++//3 Dynamic Tx Power ++//3============================================================ ++ ++VOID ++odm_DynamicTxPowerInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ #if DEV_BUS_TYPE==RT_USB_INTERFACE ++ if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) ++ { ++ odm_DynamicTxPowerSavePowerIndex(pDM_Odm); ++ pMgntInfo->bDynamicTxPowerEnable = TRUE; ++ } ++ else ++ #else ++ //so 92c pci do not need dynamic tx power? vivi check it later ++ if(IS_HARDWARE_TYPE_8192D(Adapter)) ++ pMgntInfo->bDynamicTxPowerEnable = TRUE; ++ else ++ pMgntInfo->bDynamicTxPowerEnable = FALSE; ++ #endif ++ ++ ++ pHalData->LastDTPLvl = TxHighPwrLevel_Normal; ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ pdmpriv->bDynamicTxPowerEnable = _FALSE; ++ ++ #if (RTL8192C_SUPPORT==1) ++ #ifdef CONFIG_USB_HCI ++ ++ #ifdef CONFIG_INTEL_PROXIM ++ if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE)) ++ #else ++ if(pHalData->BoardType == BOARD_USB_High_PA) ++ #endif ++ ++ { ++ //odm_SavePowerIndex(Adapter); ++ odm_DynamicTxPowerSavePowerIndex(pDM_Odm); ++ pdmpriv->bDynamicTxPowerEnable = _TRUE; ++ } ++ else ++ #else ++ pdmpriv->bDynamicTxPowerEnable = _FALSE; ++ #endif ++ #endif ++ ++ pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ++#endif ++ ++} ++ ++VOID ++odm_DynamicTxPowerSavePowerIndex( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u1Byte index; ++ u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ for(index = 0; index< 6; index++) ++ pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ for(index = 0; index< 6; index++) ++ pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]); ++#endif ++} ++ ++VOID ++odm_DynamicTxPowerRestorePowerIndex( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u1Byte index; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ for(index = 0; index< 6; index++) ++ PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); ++#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ for(index = 0; index< 6; index++) ++ rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]); ++#endif ++#endif ++} ++ ++VOID ++odm_DynamicTxPowerWritePowerIndex( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Value) ++{ ++ ++ u1Byte index; ++ u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++ ++ for(index = 0; index< 6; index++) ++ //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); ++ ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); ++ ++} ++ ++ ++VOID ++odm_DynamicTxPower( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ // ++ // For AP/ADSL use prtl8192cd_priv ++ // For CE/NIC use PADAPTER ++ // ++ //PADAPTER pAdapter = pDM_Odm->Adapter; ++// prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) ++ return; ++ ++ // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. ++ if (pDM_Odm->ExtPA == FALSE) ++ return; ++ ++ ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ case ODM_CE: ++ odm_DynamicTxPowerNIC(pDM_Odm); ++ break; ++ case ODM_AP: ++ odm_DynamicTxPowerAP(pDM_Odm); ++ break; ++ ++ case ODM_ADSL: ++ //odm_DIGAP(pDM_Odm); ++ break; ++ } ++ ++ ++} ++ ++ ++VOID ++odm_DynamicTxPowerNIC( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) ++ return; ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8192C) ++ { ++ odm_DynamicTxPower_92C(pDM_Odm); ++ } ++ else if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ odm_DynamicTxPower_92D(pDM_Odm); ++ } ++ else if (pDM_Odm->SupportICType & ODM_RTL8188E) ++ { ++ // Add Later. ++ } ++ else if (pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ // ??? ++ // This part need to be redefined. ++ } ++#endif ++} ++ ++VOID ++odm_DynamicTxPowerAP( ++ IN PDM_ODM_T pDM_Odm ++ ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ s4Byte i; ++ ++ if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) ++ return; ++ ++#ifdef HIGH_POWER_EXT_PA ++ if(pDM_Odm->ExtPA) ++ tx_power_control(priv); ++#endif ++ ++ /* ++ * Check if station is near by to use lower tx power ++ */ ++ ++ if ((priv->up_time % 3) == 0 ) { ++ for(i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pstat) ) { ++ if ((pstat->hp_level == 0) && (pstat->rssi > TX_POWER_NEAR_FIELD_THRESH_AP+4)) ++ pstat->hp_level = 1; ++ else if ((pstat->hp_level == 1) && (pstat->rssi < TX_POWER_NEAR_FIELD_THRESH_AP)) ++ pstat->hp_level = 0; ++ } ++ } ++ } ++ ++#endif ++} ++ ++ ++VOID ++odm_DynamicTxPower_92C( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ s4Byte UndecoratedSmoothedPWDB; ++ ++ ++ // STA not connected and AP not connected ++ if((!pMgntInfo->bMediaConnect) && ++ (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ++ //the LastDTPlvl should reset when disconnect, ++ //otherwise the tx power level wouldn't change when disconnect and connect again. ++ // Maddest 20091220. ++ pHalData->LastDTPLvl=TxHighPwrLevel_Normal; ++ return; ++ } ++ ++#if (INTEL_PROXIMITY_SUPPORT == 1) ++ // Intel set fixed tx power ++ if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0) ++ { ++ switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){ ++ case 1: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); ++ break; ++ case 2: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_70\n")); ++ break; ++ case 3: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_50\n")); ++ break; ++ case 4: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_35\n")); ++ break; ++ case 5: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_15\n")); ++ break; ++ default: ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); ++ break; ++ } ++ } ++ else ++#endif ++ { ++ if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || ++ (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) || ++ pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ } ++ else ++ { ++ if(pMgntInfo->bMediaConnect) // Default port ++ { ++ if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) ++ { ++ UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ } ++ else // associated entry pwdb ++ { ++ UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ ++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && ++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); ++ } ++ } ++ } ++ if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl ) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel)); ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ if( (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) && ++ (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal ++ odm_DynamicTxPowerRestorePowerIndex(pDM_Odm); ++ else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14); ++ else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10); ++ } ++ pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; ++ ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ ++ #if (RTL8192C_SUPPORT==1) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ int UndecoratedSmoothedPWDB; ++ ++ if(!pdmpriv->bDynamicTxPowerEnable) ++ return; ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if(Adapter->proximity.proxim_on== _TRUE){ ++ struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv; ++ // Intel set fixed tx power ++ printk("\n %s Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output); ++ if(prox_priv!=NULL){ ++ if(prox_priv->proxim_modeinfo->power_output> 0) ++ { ++ switch(prox_priv->proxim_modeinfo->power_output) ++ { ++ case 1: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100; ++ printk("TxHighPwrLevel_100\n"); ++ break; ++ case 2: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_70; ++ printk("TxHighPwrLevel_70\n"); ++ break; ++ case 3: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_50; ++ printk("TxHighPwrLevel_50\n"); ++ break; ++ case 4: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_35; ++ printk("TxHighPwrLevel_35\n"); ++ break; ++ case 5: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_15; ++ printk("TxHighPwrLevel_15\n"); ++ break; ++ default: ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100; ++ printk("TxHighPwrLevel_100\n"); ++ break; ++ } ++ } ++ } ++ } ++ else ++#endif ++ { ++ // STA not connected and AP not connected ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && ++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ++ //the LastDTPlvl should reset when disconnect, ++ //otherwise the tx power level wouldn't change when disconnect and connect again. ++ // Maddest 20091220. ++ pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port ++ { ++ #if 0 ++ //todo: AP Mode ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ #else ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ #endif ++ } ++ else // associated entry pwdb ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ ++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && ++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); ++ } ++ } ++ if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) ) ++ { ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal ++ odm_DynamicTxPowerRestorePowerIndex(pDM_Odm); ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14); ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10); ++ } ++ pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl; ++ #endif ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++} ++ ++ ++VOID ++odm_DynamicTxPower_92D( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ s4Byte UndecoratedSmoothedPWDB; ++ ++ PADAPTER BuddyAdapter = Adapter->BuddyAdapter; ++ BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter); ++ u1Byte HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1; ++ ++ ++ // If dynamic high power is disabled. ++ if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || ++ (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) || ++ pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ // STA not connected and AP not connected ++ if((!pMgntInfo->bMediaConnect) && ++ (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ++ //the LastDTPlvl should reset when disconnect, ++ //otherwise the tx power level wouldn't change when disconnect and connect again. ++ // Maddest 20091220. ++ pHalData->LastDTPLvl=TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ if(pMgntInfo->bMediaConnect) // Default port ++ { ++ if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss) ++ { ++ UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ } ++ else // associated entry pwdb ++ { ++ UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ ++ if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType92D == 1){ ++ if(UndecoratedSmoothedPWDB >= 0x33) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB <0x33) && ++ (UndecoratedSmoothedPWDB >= 0x2b) ) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < 0x2b) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n")); ++ } ++ ++ } ++ else ++ ++ { ++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && ++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) ++ { ++ pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); ++ } ++ ++ } ++ ++//sherry delete flag 20110517 ++ if(bGetValueFromBuddyAdapter) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n")); ++ if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n")); ++ HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl; ++ pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP; ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0; ++ Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE; ++ } ++ } ++ ++ if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) ) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel)); ++ if(Adapter->DualMacSmartConcurrent == TRUE) ++ { ++ if(BuddyAdapter == NULL) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n")); ++ if(!Adapter->bSlaveOfDMSP) ++ { ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ } ++ } ++ else ++ { ++ if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n")); ++ if(Adapter->bSlaveOfDMSP) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n")); ++ BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE; ++ BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl; ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n")); ++ if(!bGetValueFromBuddyAdapter) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n")); ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ } ++ } ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n")); ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ } ++ } ++ } ++ else ++ { ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ } ++ ++ } ++ pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++#if (RTL8192D_SUPPORT==1) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++ int UndecoratedSmoothedPWDB; ++ #if (RTL8192D_EASY_SMART_CONCURRENT == 1) ++ PADAPTER BuddyAdapter = Adapter->BuddyAdapter; ++ BOOLEAN bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter); ++ u8 HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1; ++ #endif ++ ++ // If dynamic high power is disabled. ++ if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) || ++ (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ // STA not connected and AP not connected ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && ++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ //the LastDTPlvl should reset when disconnect, ++ //otherwise the tx power level wouldn't change when disconnect and connect again. ++ // Maddest 20091220. ++ pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port ++ { ++ #if 0 ++ //todo: AP Mode ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ #else ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ #endif ++ } ++ else // associated entry pwdb ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++#if TX_POWER_FOR_5G_BAND == 1 ++ if(pHalData->CurrentBandType92D == BAND_ON_5G){ ++ if(UndecoratedSmoothedPWDB >= 0x33) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB <0x33) && ++ (UndecoratedSmoothedPWDB >= 0x2b) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < 0x2b) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n")); ++ } ++ } ++ else ++#endif ++ { ++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && ++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); ++ } ++ } ++#if (RTL8192D_EASY_SMART_CONCURRENT == 1) ++ if(bGetValueFromBuddyAdapter) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n")); ++ if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n")); ++ HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl; ++ pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP; ++ PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); ++ pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0; ++ Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE; ++ } ++ } ++#endif ++ ++ if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) ) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel)); ++#if (RTL8192D_EASY_SMART_CONCURRENT == 1) ++ if(BuddyAdapter == NULL) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n")); ++ if(!Adapter->bSlaveOfDMSP) ++ { ++ PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); ++ } ++ } ++ else ++ { ++ if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n")); ++ if(Adapter->bSlaveOfDMSP) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n")); ++ BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE; ++ BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl; ++ } ++ else ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n")); ++ if(!bGetValueFromBuddyAdapter) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n")); ++ PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); ++ } ++ } ++ } ++ else ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n")); ++ PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); ++ } ++ } ++#else ++ PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); ++#endif ++ } ++ pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl; ++#endif ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++} ++ ++ ++//3============================================================ ++//3 RSSI Monitor ++//3============================================================ ++ ++VOID ++odm_RSSIMonitorInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++} ++ ++VOID ++odm_RSSIMonitorCheck( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ // ++ // For AP/ADSL use prtl8192cd_priv ++ // For CE/NIC use PADAPTER ++ // ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) ++ return; ++ ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ odm_RSSIMonitorCheckMP(pDM_Odm); ++ break; ++ ++ case ODM_CE: ++ odm_RSSIMonitorCheckCE(pDM_Odm); ++ break; ++ ++ case ODM_AP: ++ odm_RSSIMonitorCheckAP(pDM_Odm); ++ break; ++ ++ case ODM_ADSL: ++ //odm_DIGAP(pDM_Odm); ++ break; ++ } ++ ++} // odm_RSSIMonitorCheck ++ ++ ++VOID ++odm_RSSIMonitorCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PRT_WLAN_STA pEntry; ++ u1Byte i; ++ s4Byte tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; ++ ++ RTPRINT(FDM, DM_PWDB, ("pHalData->UndecoratedSmoothedPWDB = 0x%x( %d)\n", ++ pHalData->UndecoratedSmoothedPWDB, ++ pHalData->UndecoratedSmoothedPWDB)); ++ ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ { ++ pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); ++ } ++ else ++ { ++ pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); ++ } ++ ++ if(pEntry!=NULL) ++ { ++ if(pEntry->bAssociated) ++ { ++ RTPRINT_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); ++ RTPRINT(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", ++ pEntry->rssi_stat.UndecoratedSmoothedPWDB, ++ pEntry->rssi_stat.UndecoratedSmoothedPWDB)); ++ if(pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) ++ tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; ++ if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) ++ tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; ++ } ++ } ++ else ++ { ++ break; ++ } ++ } ++ ++ if(tmpEntryMaxPWDB != 0) // If associated entry is found ++ { ++ pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; ++ RTPRINT(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", ++ tmpEntryMaxPWDB, tmpEntryMaxPWDB)); ++ } ++ else ++ { ++ pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; ++ } ++ if(tmpEntryMinPWDB != 0xff) // If associated entry is found ++ { ++ pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; ++ RTPRINT(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", ++ tmpEntryMinPWDB, tmpEntryMinPWDB)); ++ } ++ else ++ { ++ pHalData->EntryMinUndecoratedSmoothedPWDB = 0; ++ } ++ ++ // Indicate Rx signal strength to FW. ++ if(Adapter->MgntInfo.bUseRAMask) ++ { ++ u1Byte H2C_Parameter[3] ={0}; ++ // DbgPrint("RxSS: %lx =%ld\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB); ++ H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); ++ H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 ++ ++ ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter); ++ } ++ else ++ { ++ PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); ++ //DbgPrint("0x4fe write %x %d\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB); ++ } ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++} ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++// ++//sherry move from DUSC to here 20110517 ++// ++static VOID ++FindMinimumRSSI_Dmsp( ++ IN PADAPTER pAdapter ++) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ s32 Rssi_val_min_back_for_mac0; ++ BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter); ++ BOOLEAN bRestoreRssi = _FALSE; ++ PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; ++ ++ if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) ++ { ++ if(BuddyAdapter!= NULL) ++ { ++ if(pHalData->bSlaveOfDMSP) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n")); ++ BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM; ++ } ++ else ++ { ++ if(bGetValueFromBuddyAdapter) ++ { ++ //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n")); ++ bRestoreRssi = _TRUE; ++ Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM; ++ pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP; ++ } ++ } ++ } ++ ++ } ++ ++ if(bRestoreRssi) ++ { ++ bRestoreRssi = _FALSE; ++ pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0; ++ } ++#endif ++} ++ ++static void ++FindMinimumRSSI( ++IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ //1 1.Determine the minimum RSSI ++ ++ if((pDM_Odm->bLinked != _TRUE) && ++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ pdmpriv->MinUndecoratedPWDBForDM = 0; ++ //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n")); ++ } ++ else ++ { ++ pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ } ++ ++ //DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM); ++ //ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM)); ++} ++#endif ++ ++VOID ++odm_RSSIMonitorCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ int i; ++ int tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; ++ u8 sta_cnt=0; ++ u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi ++ ++ if(pDM_Odm->bLinked != _TRUE) ++ return; ++ ++ //if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ #if 1 ++ struct sta_info *psta; ++ ++ for(i=0; ipODM_StaInfo[i])) ++ { ++ if(IS_MCAST( psta->hwaddr)) //if(psta->mac_id ==1) ++ continue; ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) ++ tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) ++ tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ #if 0 ++ DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, ++ psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB); ++ #endif ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) { ++ #if(RTL8192D_SUPPORT==1) ++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8)); ++ #else ++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) ); ++ #endif ++ } ++ } ++ } ++ #else ++ _irqL irqL; ++ _list *plist, *phead; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &Adapter->stapriv; ++ u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) || ++ _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) ++ continue; ++ ++ if(psta->state & WIFI_ASOC_STATE) ++ { ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) ++ tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) ++ tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)){ ++ //printk("%s==> mac_id(%d),rssi(%d)\n",__FUNCTION__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB); ++ #if(RTL8192D_SUPPORT==1) ++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8)); ++ #else ++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) ); ++ #endif ++ } ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ #endif ++ ++ //printk("%s==> sta_cnt(%d)\n",__FUNCTION__,sta_cnt); ++ ++ for(i=0; i< sta_cnt; i++) ++ { ++ if(PWDB_rssi[i] != (0)){ ++ if(pHalData->fw_ractrl == _TRUE)// Report every sta's RSSI to FW ++ { ++ #if(RTL8192D_SUPPORT==1) ++ FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i])); ++ #elif((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1)) ++ rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]); ++ #endif ++ } ++ else{ ++ #if((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1)) ++ ODM_RA_SetRSSI_8188E( ++ &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); ++ #endif ++ } ++ } ++ } ++ } ++ ++ if(tmpEntryMaxPWDB != 0) // If associated entry is found ++ { ++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; ++ } ++ else ++ { ++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; ++ } ++ ++ if(tmpEntryMinPWDB != 0xff) // If associated entry is found ++ { ++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; ++ } ++ else ++ { ++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; ++ } ++ ++ FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM ++ ++ #if(RTL8192D_SUPPORT==1) ++ FindMinimumRSSI_Dmsp(Adapter); ++ #endif ++ pDM_Odm->RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM; ++ //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); ++#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++} ++VOID ++odm_RSSIMonitorCheckAP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++#ifdef CONFIG_RTL_92C_SUPPORT || defined(CONFIG_RTL_92D_SUPPORT) ++ ++ u4Byte i; ++ PSTA_INFO_T pstat; ++ ++ for(i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pstat) ) ++ { ++#ifdef STA_EXT ++ if (REMAP_AID(pstat) < (FW_NUM_STAT - 1)) ++#endif ++ add_update_rssi(pDM_Odm->priv, pstat); ++ ++ } ++ } ++#endif ++#endif ++ ++} ++ ++ ++ ++VOID ++ODM_InitAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, ++ (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer"); ++ ++#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++#if (RTL8188E_SUPPORT == 1) ++ ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, ++ (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); ++#endif ++#endif ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer, ++ (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer"); ++ // ++ //Path Diversity ++ //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. ++ // ++ ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, ++ (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); ++ ++ ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, ++ (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); ++ ++ ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer, ++ (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer"); ++#endif ++} ++ ++VOID ++ODM_CancelAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ // ++ // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in ++ // win7 platform. ++ // ++ HAL_ADAPTER_STS_CHK(pDM_Odm) ++#endif ++ ++ ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++#if (RTL8188E_SUPPORT == 1) ++ ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); ++#endif ++ ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); ++ // ++ //Path Diversity ++ //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. ++ // ++ ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); ++ ++ ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); ++ ++ ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); ++#endif ++} ++ ++ ++VOID ++ODM_ReleaseAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); ++ ++#if (RTL8188E_SUPPORT == 1) ++ ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++ ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer); ++ // ++ //Path Diversity ++ //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. ++ // ++ ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); ++ ++ ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); ++ ++ ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); ++#endif ++} ++ ++ ++ ++//#endif ++//3============================================================ ++//3 Tx Power Tracking ++//3============================================================ ++ ++VOID ++odm_TXPowerTrackingInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ odm_TXPowerTrackingThermalMeterInit(pDM_Odm); ++} ++ ++ ++VOID ++odm_TXPowerTrackingThermalMeterInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ pMgntInfo->bTXPowerTracking = TRUE; ++ pHalData->TXPowercount = 0; ++ pHalData->bTXPowerTrackingInit = FALSE; ++ #if MP_DRIVER != 1 //for mp driver, turn off txpwrtracking as default ++ pHalData->TxPowerTrackControl = TRUE; ++ #endif//#if (MP_DRIVER != 1) ++ ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ #ifdef CONFIG_RTL8188E ++ { ++ pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; ++ pDM_Odm->RFCalibrateInfo.TXPowercount = 0; ++ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; ++ //#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default ++ if ( *(pDM_Odm->mp_mode) != 1) ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; ++ //#endif//#if (MP_DRIVER != 1) ++ MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); ++ } ++ #else ++ { ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ //if(IS_HARDWARE_TYPE_8192C(pHalData)) ++ { ++ pdmpriv->bTXPowerTracking = _TRUE; ++ pdmpriv->TXPowercount = 0; ++ pdmpriv->bTXPowerTrackingInit = _FALSE; ++ //#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default ++ ++ if (*(pDM_Odm->mp_mode) != 1) ++ pdmpriv->TxPowerTrackControl = _TRUE; ++ //#endif//#if (MP_DRIVER != 1) ++ } ++ MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); ++ ++ } ++ #endif//endif (CONFIG_RTL8188E==1) ++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ #ifdef RTL8188E_SUPPORT ++ { ++ pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; ++ pDM_Odm->RFCalibrateInfo.TXPowercount = 0; ++ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; ++ } ++ #endif ++#endif ++ ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = 0; ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = 0; ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; ++ pDM_Odm->RFCalibrateInfo.ThermalValue = 0; ++ pDM_Odm->DefaultOfdmIndex = 12; ++ pDM_Odm->DefaultCckIndex = 12; ++ pDM_Odm->BbSwingIdxOfdmBase = pDM_Odm->DefaultOfdmIndex; ++ pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex; ++ pDM_Odm->BbSwingIdxOfdm = pDM_Odm->DefaultOfdmIndex; ++ pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex; ++ ++ pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->DefaultCckIndex; ++ pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A] = pDM_Odm->DefaultOfdmIndex; ++ pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_B] = pDM_Odm->DefaultOfdmIndex; ++ ++} ++ ++ ++VOID ++ODM_TXPowerTrackingCheck( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ // ++ // For AP/ADSL use prtl8192cd_priv ++ // For CE/NIC use PADAPTER ++ // ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ //if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) ++ //return; ++ ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ odm_TXPowerTrackingCheckMP(pDM_Odm); ++ break; ++ ++ case ODM_CE: ++ odm_TXPowerTrackingCheckCE(pDM_Odm); ++ break; ++ ++ case ODM_AP: ++ odm_TXPowerTrackingCheckAP(pDM_Odm); ++ break; ++ ++ case ODM_ADSL: ++ //odm_DIGAP(pDM_Odm); ++ break; ++ } ++ ++} ++ ++VOID ++odm_TXPowerTrackingCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ #if( (RTL8192C_SUPPORT==1) || (RTL8723A_SUPPORT==1) ) ++ rtl8192c_odm_CheckTXPowerTracking(Adapter); ++ #endif ++ ++ #if (RTL8192D_SUPPORT==1) ++ #if (RTL8192D_EASY_SMART_CONCURRENT == 1) ++ if(!Adapter->bSlaveOfDMSP) ++ #endif ++ rtl8192d_odm_CheckTXPowerTracking(Adapter); ++ #endif ++ #if(RTL8188E_SUPPORT==1) ++ ++ //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) ++ if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) ++ { ++ return; ++ } ++ ++ if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec ++ { ++ //pHalData->TxPowerCheckCnt++; //cosa add for debug ++ //ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); ++ //DBG_8192C("Trigger 92C Thermal Meter!!\n"); ++ ++ pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; ++ return; ++ ++ } ++ else ++ { ++ //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); ++ odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); ++ pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; ++ } ++ #endif ++ ++#endif ++} ++ ++VOID ++odm_TXPowerTrackingCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++ if (ODM_CheckPowerStatus(Adapter) == FALSE) ++ return; ++ ++ if(IS_HARDWARE_TYPE_8723A(Adapter)) ++ return; ++ ++ if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) ++ odm_TXPowerTrackingThermalMeterCheck(Adapter); ++#endif ++ ++} ++ ++ ++VOID ++odm_TXPowerTrackingCheckAP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ if ( (priv->pmib->dot11RFEntry.ther) && ((priv->up_time % priv->pshare->rf_ft_var.tpt_period) == 0)){ ++#ifdef CONFIG_RTL_92D_SUPPORT ++ if (GET_CHIP_VER(priv)==VERSION_8192D){ ++ tx_power_tracking_92D(priv); ++ } else ++#endif ++ { ++#ifdef CONFIG_RTL_92C_SUPPORT ++ tx_power_tracking(priv); ++#endif ++ } ++ } ++#endif ++ ++} ++ ++ ++ ++//antenna mapping info ++// 1: right-side antenna ++// 2/0: left-side antenna ++//PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 ++//PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 ++// We select left antenna as default antenna in initial process, modify it as needed ++// ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++VOID ++odm_TXPowerTrackingThermalMeterCheck( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifndef AP_BUILD_WORKAROUND ++#if (HAL_CODE_BASE==RTL8192_C) ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ static u1Byte TM_Trigger = 0; ++ //u1Byte TxPowerCheckCnt = 5; //10 sec ++ ++ if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) ++ { ++ return; ++ } ++ ++ if(!TM_Trigger) //at least delay 1 sec ++ { ++ if(IS_HARDWARE_TYPE_8192D(Adapter)) ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03); ++ else if(IS_HARDWARE_TYPE_8188E(Adapter)) ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); ++ else ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); ++ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); ++ ++ TM_Trigger = 1; ++ return; ++ } ++ else ++ { ++ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); ++ odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. ++ TM_Trigger = 0; ++ } ++#endif ++#endif ++} ++ ++#endif ++ ++ ++ ++//3============================================================ ++//3 SW Antenna Diversity ++//3============================================================ ++#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) ++VOID ++odm_SwAntDivInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ odm_SwAntDivInit_NIC(pDM_Odm); ++#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) ++ dm_SW_AntennaSwitchInit(pDM_Odm->priv); ++#endif ++} ++#if (RTL8723A_SUPPORT==1) ++// Only for 8723A SW ANT DIV INIT--2012--07--17 ++VOID ++odm_SwAntDivInit_NIC_8723A( ++ IN PDM_ODM_T pDM_Odm) ++{ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ u1Byte btAntNum=BT_GetPGAntNum(Adapter); ++ ++ ++ if(IS_HARDWARE_TYPE_8723A(Adapter)) ++ { ++ pDM_SWAT_Table->ANTA_ON =TRUE; ++ ++ // Set default antenna B status by PG ++ if(btAntNum == Ant_x2) ++ pDM_SWAT_Table->ANTB_ON = TRUE; ++ else if(btAntNum ==Ant_x1) ++ pDM_SWAT_Table->ANTB_ON = FALSE; ++ else ++ pDM_SWAT_Table->ANTB_ON = TRUE; ++ } ++ ++} ++#endif ++VOID ++odm_SwAntDivInit_NIC( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++// Init SW ANT DIV mechanism for 8723AE/AU/AS// Neil Chen--2012--07--17--- ++// CE/AP/ADSL no using SW ANT DIV for 8723A Series IC ++//#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++#if (RTL8723A_SUPPORT==1) ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ odm_SwAntDivInit_NIC_8723A(pDM_Odm); ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n")); ++ pDM_SWAT_Table->RSSI_sum_A = 0; ++ pDM_SWAT_Table->RSSI_cnt_A = 0; ++ pDM_SWAT_Table->RSSI_sum_B = 0; ++ pDM_SWAT_Table->RSSI_cnt_B = 0; ++ pDM_SWAT_Table->CurAntenna = Antenna_A; ++ pDM_SWAT_Table->PreAntenna = Antenna_A; ++ pDM_SWAT_Table->try_flag = 0xff; ++ pDM_SWAT_Table->PreRSSI = 0; ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0; ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ pDM_SWAT_Table->lastTxOkCnt = 0; ++ pDM_SWAT_Table->lastRxOkCnt = 0; ++ pDM_SWAT_Table->TXByteCnt_A = 0; ++ pDM_SWAT_Table->TXByteCnt_B = 0; ++ pDM_SWAT_Table->RXByteCnt_A = 0; ++ pDM_SWAT_Table->RXByteCnt_B = 0; ++ pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; ++ pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860); ++} ++ ++// ++// 20100514 Joseph: ++// Add new function to reset the state of antenna diversity before link. ++// ++VOID ++ODM_SwAntDivResetBeforeLink( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ ++} ++ ++// ++// 20100514 Luke/Joseph: ++// Add new function to reset antenna diversity state after link. ++// ++VOID ++ODM_SwAntDivRestAfterLink( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ pDM_SWAT_Table->RSSI_cnt_A = 0; ++ pDM_SWAT_Table->RSSI_cnt_B = 0; ++ pDM_Odm->RSSI_test = FALSE; ++ pDM_SWAT_Table->try_flag = 0xff; ++ pDM_SWAT_Table->RSSI_Trying = 0; ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++} ++ ++VOID ++ODM_SwAntDivChkPerPktRssi( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte StationID, ++ IN PODM_PHY_INFO_T pPhyInfo ++ ) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ if(!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV))) ++ return; ++ ++ if(StationID == pDM_SWAT_Table->RSSI_target) ++ { ++ //1 RSSI for SW Antenna Switch ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll; ++ pDM_SWAT_Table->RSSI_cnt_A++; ++ } ++ else ++ { ++ pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll; ++ pDM_SWAT_Table->RSSI_cnt_B++; ++ ++ } ++ } ++ ++} ++ ++// ++VOID ++odm_SwAntDivChkAntSwitch( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Step ++ ) ++{ ++ // ++ // For AP/ADSL use prtl8192cd_priv ++ // For CE/NIC use PADAPTER ++ // ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ case ODM_CE: ++ odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step); ++ break; ++ ++ case ODM_AP: ++ case ODM_ADSL: ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP |ODM_ADSL)) ++ if (priv->pshare->rf_ft_var.antSw_enable && (priv->up_time % 4==1)) ++ dm_SW_AntennaSwitch(priv, SWAW_STEP_PEAK); ++#endif ++ break; ++ } ++ ++} ++ ++// ++// 20100514 Luke/Joseph: ++// Add new function for antenna diversity after link. ++// This is the main function of antenna diversity after link. ++// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). ++// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. ++// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. ++// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just ++// listened on the air with the RSSI of original antenna. ++// It chooses the antenna with better RSSI. ++// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting ++// penalty to get next try. ++ ++ ++VOID ++ODM_SetAntenna( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Antenna) ++{ ++ ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna); ++} ++//--------------------------------2012--09--06-- ++//Note: Antenna_Main--> Antenna_A ++// Antenna_Aux---> Antenna_B ++//---------------------------------- ++VOID ++odm_SwAntDivChkAntSwitchNIC( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Step ++ ) ++{ ++#if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1)) ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ s4Byte curRSSI=100, RSSI_A, RSSI_B; ++ u1Byte nextAntenna=Antenna_B; ++ //static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ u8Byte curTxOkCnt, curRxOkCnt; ++ //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; ++ u8Byte CurByteCnt=0, PreByteCnt=0; ++ //static u1Byte TrafficLoad = TRAFFIC_LOW; ++ u1Byte Score_A=0, Score_B=0; ++ u1Byte i; ++ ++ if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) ++ return; ++ ++ if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E)) ++ return; ++ ++ if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) ++ return; ++ ++ if(pDM_Odm->SupportPlatform & ODM_MP) ++ { ++ if(*(pDM_Odm->pAntennaTest)) ++ return; ++ } ++ ++ if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE)) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n")); ++ return; ++ } ++ ++ // Radio off: Status reset to default and return. ++ if(*(pDM_Odm->pbPowerSaving)==TRUE) //pHalData->eRFPowerState==eRfOff ++ { ++ ODM_SwAntDivRestAfterLink(pDM_Odm); ++ return; ++ } ++ ++ ++ // Handling step mismatch condition. ++ // Peak step is not finished at last time. Recover the variable and check again. ++ if( Step != pDM_SWAT_Table->try_flag ) ++ { ++ ODM_SwAntDivRestAfterLink(pDM_Odm); ++ } ++ ++#if (DM_ODM_SUPPORT_TYPE &( ODM_MP| ODM_CE )) ++ ++ if(pDM_SWAT_Table->try_flag == 0xff) ++ { ++ pDM_SWAT_Table->RSSI_target = 0xff; ++ ++ #if(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ { ++ u1Byte index = 0; ++ PSTA_INFO_T pEntry = NULL; ++ ++ ++ for(index=0; indexpODM_StaInfo[index]; ++ if(IS_STA_VALID(pEntry) ) { ++ break; ++ } ++ } ++ if(pEntry == NULL) ++ { ++ ODM_SwAntDivRestAfterLink(pDM_Odm); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); ++ return; ++ } ++ else ++ { ++ pDM_SWAT_Table->RSSI_target = index; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); ++ } ++ } ++ #elif (DM_ODM_SUPPORT_TYPE & ODM_MP) ++ { ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; ++ ++ // Select RSSI checking target ++ if(pMgntInfo->mAssoc && !ACTING_AS_AP(pAdapter)) ++ { ++ // Target: Infrastructure mode AP. ++ //pDM_SWAT_Table->RSSI_target = NULL; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): RSSI_target is DEF AP!\n")); ++ } ++ else ++ { ++ u1Byte index = 0; ++ PSTA_INFO_T pEntry = NULL; ++ PADAPTER pTargetAdapter = NULL; ++ ++ if(pMgntInfo->mIbss ) ++ { ++ // Target: AP/IBSS peer. ++ pTargetAdapter = pAdapter; ++ } ++ else ++ { ++ pTargetAdapter = GetFirstAPAdapter(pAdapter); ++ } ++ ++ if(pTargetAdapter != NULL) ++ { ++ for(index=0; indexbAssociated) ++ break; ++ } ++ ++ } ++ ++ } ++ ++ if(pEntry == NULL) ++ { ++ ODM_SwAntDivRestAfterLink(pDM_Odm); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); ++ return; ++ } ++ else ++ { ++ //pDM_SWAT_Table->RSSI_target = pEntry; ++ pDM_SWAT_Table->RSSI_target = index; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); ++ } ++ }//end if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) ++ ++ } ++ #endif ++ ++ pDM_SWAT_Table->RSSI_cnt_A = 0; ++ pDM_SWAT_Table->RSSI_cnt_B = 0; ++ pDM_SWAT_Table->try_flag = 0; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n")); ++ return; ++ } ++ else ++ { ++#if (DM_ODM_SUPPORT_TYPE &( ODM_MP)) ++ //PADAPTER Adapter = pDM_Odm->Adapter; ++ curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt; ++ curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt; ++ pDM_SWAT_Table->lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast; ++ pDM_SWAT_Table->lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast; ++#else ++ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt; ++ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt; ++ pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); ++ pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); ++#endif ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curTxOkCnt = %lld\n",curTxOkCnt)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curRxOkCnt = %lld\n",curRxOkCnt)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastTxOkCnt = %lld\n",pDM_SWAT_Table->lastTxOkCnt)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastRxOkCnt = %lld\n",pDM_SWAT_Table->lastRxOkCnt)); ++ ++ if(pDM_SWAT_Table->try_flag == 1) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt; ++ pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt; ++ } ++ else ++ { ++ pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt; ++ pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt; ++ } ++ ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->RSSI_Trying--; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying)); ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ { ++ CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B); ++ PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A); ++ ++ if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) ++ //CurByteCnt = PlatformDivision64(CurByteCnt, 9); ++ PreByteCnt = PreByteCnt*9; ++ else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) ++ //CurByteCnt = PlatformDivision64(CurByteCnt, 2); ++ PreByteCnt = PreByteCnt*2; ++ ++ if(pDM_SWAT_Table->RSSI_cnt_A > 0) ++ RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pDM_SWAT_Table->RSSI_cnt_B > 0) ++ RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n", ++ (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B)); ++ } ++ ++ } ++ else ++ { ++ ++ if(pDM_SWAT_Table->RSSI_cnt_A > 0) ++ RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pDM_SWAT_Table->RSSI_cnt_B > 0) ++ RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n", ++ (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B)); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); ++ } ++ ++ //1 Trying State ++ if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) ++ { ++ ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE")); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt)); ++ if(CurByteCnt < PreByteCnt) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ } ++ else ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ } ++ for (i= 0; i<8; i++) ++ { ++ if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) ++ Score_A++; ++ else ++ Score_B++; ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B)); ++ ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B; ++ } ++ else ++ { ++ nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A; ++ } ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B")); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n", ++ //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B"))); ++ ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna")); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n")); ++ } ++ } ++ ++ if(pDM_SWAT_Table->TestMode == RSSI_MODE) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE")); ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna")); ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ } ++ else // current anntena is good ++ { ++ nextAntenna =pDM_SWAT_Table->CurAntenna; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n")); ++ } ++ } ++ pDM_SWAT_Table->try_flag = 0; ++ pDM_Odm->RSSI_test = FALSE; ++ pDM_SWAT_Table->RSSI_sum_A = 0; ++ pDM_SWAT_Table->RSSI_cnt_A = 0; ++ pDM_SWAT_Table->RSSI_sum_B = 0; ++ pDM_SWAT_Table->RSSI_cnt_B = 0; ++ pDM_SWAT_Table->TXByteCnt_A = 0; ++ pDM_SWAT_Table->TXByteCnt_B = 0; ++ pDM_SWAT_Table->RXByteCnt_A = 0; ++ pDM_SWAT_Table->RXByteCnt_B = 0; ++ ++ } ++ ++ //1 Normal State ++ else if(pDM_SWAT_Table->try_flag == 0) ++ { ++ if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) ++ { ++ if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ++ pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH; ++ else ++ pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; ++ } ++ else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) ++ { ++ if ((curTxOkCnt+curRxOkCnt) > 3750000) //if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ++ pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH; ++ else ++ pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; ++ } ++ if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) ++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0; ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt)); ++ ++ //Prepare To Try Antenna ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->try_flag = 1; ++ pDM_Odm->RSSI_test = TRUE; ++ if((curRxOkCnt+curTxOkCnt) > 1000) ++ { ++ pDM_SWAT_Table->RSSI_Trying = 4; ++ pDM_SWAT_Table->TestMode = TP_MODE; ++ } ++ else ++ { ++ pDM_SWAT_Table->RSSI_Trying = 2; ++ pDM_SWAT_Table->TestMode = RSSI_MODE; ++ ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n")); ++ ++ ++ pDM_SWAT_Table->RSSI_sum_A = 0; ++ pDM_SWAT_Table->RSSI_cnt_A = 0; ++ pDM_SWAT_Table->RSSI_sum_B = 0; ++ pDM_SWAT_Table->RSSI_cnt_B = 0; ++ } ++ } ++ ++ //1 4.Change TRX antenna ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n ")); ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ODM_SetAntenna(pDM_Odm,nextAntenna); ++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ { ++ BOOLEAN bEnqueue; ++ bEnqueue = (pDM_Odm->SupportInterface == ODM_ITRF_PCIE)?FALSE :TRUE; ++ rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue); ++ } ++ #endif ++ ++ } ++ ++ //1 5.Reset Statistics ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ pDM_SWAT_Table->CurAntenna = nextAntenna; ++ pDM_SWAT_Table->PreRSSI = curRSSI; ++ ++ //1 6.Set next timer ++ { ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ return; ++ ++ if(pDM_SWAT_Table->RSSI_Trying%2 == 0) ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) ++ { ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 10 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n")); ++ } ++ else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) ++ { ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 50 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n")); ++ } ++ } ++ else ++ { ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n")); ++ } ++ } ++ else ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 90 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms ++ else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 100 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms ++ } ++ else ++ //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms ++ ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms ++ } ++ } ++#endif // #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++#endif // #if (RTL8192C_SUPPORT==1) ++} ++ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++u1Byte ++odm_SwAntDivSelectChkChnl( ++ IN PADAPTER Adapter ++ ) ++{ ++#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) ++ u1Byte index, target_chnl=0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ u1Byte chnl_peer_cnt[14] = {0}; ++ ++ if(Adapter->MgntInfo.tmpNumBssDesc==0) ++ { ++ return 0; ++ } ++ else ++ { ++ // 20100519 Joseph: Select checking channel from current scan list. ++ // We just choose the channel with most APs to be the test scan channel. ++ for(index=0; indexMgntInfo.tmpNumBssDesc; index++) ++ { ++ // Add by hpfan: prevent access invalid channel number ++ // TODO: Verify channel number by channel plan ++ if(Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber == 0 || ++ Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber > 13) ++ continue; ++ ++ chnl_peer_cnt[Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber-1]++; ++ } ++ for(index=0; index<14; index++) ++ { ++ if(chnl_peer_cnt[index]>chnl_peer_cnt[target_chnl]) ++ target_chnl = index; ++ } ++ target_chnl+=1; ++ ODM_RT_TRACE(pDM_Odm,COMP_SWAS, DBG_LOUD, ++ ("odm_SwAntDivSelectChkChnl(): Channel %d is select as test channel.\n", target_chnl)); ++ ++ return target_chnl; ++ } ++#else ++ return 0; ++#endif ++} ++ ++ ++VOID ++odm_SwAntDivConsructChkScanChnl( ++ IN PADAPTER Adapter, ++ IN u1Byte ChkChnl ++ ) ++{ ++ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ PRT_CHANNEL_LIST pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo); ++ u1Byte index; ++ ++ if(ChkChnl==0) ++ { ++ // 20100519 Joseph: Original antenna scanned nothing. ++ // Test antenna shall scan all channel with half period in this condition. ++ RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL); ++ for(index=0; indexChannelLen; index++) ++ pChannelList->ChannelInfo[index].ScanPeriod /= 2; ++ } ++ else ++ { ++ // The using of this CustomizedScanRequest is a trick to rescan the two channels ++ // under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest. ++ CUSTOMIZED_SCAN_REQUEST CustomScanReq; ++ ++ CustomScanReq.bEnabled = TRUE; ++ CustomScanReq.Channels[0] = ChkChnl; ++ CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber; ++ CustomScanReq.nChannels = 2; ++ CustomScanReq.ScanType = SCAN_ACTIVE; ++ CustomScanReq.Duration = DEFAULT_ACTIVE_SCAN_PERIOD; ++ ++ RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL); ++ } ++ ++} ++#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++// ++// 20100514 Luke/Joseph: ++// Callback function for 500ms antenna test trying. ++// ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++odm_SwAntDivChkAntSwitchCallback( ++ PRT_TIMER pTimer ++) ++{ ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; ++ ++ #if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ #if USE_WORKITEM ++ ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem); ++ #else ++ odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); ++ #endif ++#else ++ ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem); ++ #endif ++ ++} ++VOID ++odm_SwAntDivChkAntSwitchWorkitemCallback( ++ IN PVOID pContext ++ ) ++{ ++ ++ PADAPTER pAdapter = (PADAPTER)pContext; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); ++ ++} ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) ++{ ++ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; ++ PADAPTER padapter = pDM_Odm->Adapter; ++ if(padapter->net_closed == _TRUE) ++ return; ++ odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE); ++} ++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) ++{ ++ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; ++ odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE); ++} ++#endif ++ ++#else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) ++ ++VOID odm_SwAntDivInit( IN PDM_ODM_T pDM_Odm ) {} ++VOID ODM_SwAntDivChkPerPktRssi( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte StationID, ++ IN PODM_PHY_INFO_T pPhyInfo ++ ) {} ++VOID odm_SwAntDivChkAntSwitch( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Step ++ ) {} ++VOID ODM_SwAntDivResetBeforeLink( IN PDM_ODM_T pDM_Odm ){} ++VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm ){} ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++u1Byte odm_SwAntDivSelectChkChnl( IN PADAPTER Adapter ){ return 0;} ++VOID ++odm_SwAntDivConsructChkScanChnl( ++ IN PADAPTER Adapter, ++ IN u1Byte ChkChnl ++ ){} ++#endif ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID odm_SwAntDivChkAntSwitchCallback( PRT_TIMER pTimer){} ++VOID odm_SwAntDivChkAntSwitchWorkitemCallback( IN PVOID pContext ){} ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){} ++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){} ++#endif ++ ++#endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++#if((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY))) ++BOOLEAN ++ODM_SwAntDivCheckBeforeLink8192C( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData=NULL; ++ PMGNT_INFO pMgntInfo = NULL; ++ //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ ++ s1Byte Score = 0; ++ PRT_WLAN_BSS pTmpBssDesc; ++ PRT_WLAN_BSS pTestBssDesc; ++ ++ u1Byte target_chnl = 0; ++ u1Byte index; ++ ++return FALSE; ++ if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 ++ { // The ODM structure is not initialized. ++ return FALSE; ++ } ++ // 2012/04/26 MH Prevent no-checked IC to execute antenna diversity. ++ if(pDM_Odm->SupportICType == ODM_RTL8188E && pDM_Odm->SupportInterface != ODM_ITRF_PCIE) ++ return FALSE; ++ pHalData = GET_HAL_DATA(Adapter); ++ pMgntInfo = &Adapter->MgntInfo; ++ ++ // Condition that does not need to use antenna diversity. ++ if(IS_8723_SERIES(pHalData->VersionID) || ++ IS_92C_SERIAL(pHalData->VersionID) || ++ (pHalData->AntDivCfg==0) || ++ pMgntInfo->AntennaTest || ++ Adapter->bInHctTest) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism.\n")); ++ return FALSE; ++ } ++ ++ if(IS_8723_SERIES(pHalData->VersionID) || IS_92C_SERIAL(pHalData->VersionID) ) ++ { ++ if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE)) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism, Antenna A or B is off\n")); ++ return FALSE; ++ } ++ } ++ ++ // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. ++ PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) ++ { ++ PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", ++ pMgntInfo->RFChangeInProgress, ++ pHalData->eRFPowerState)); ++ ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ ++ return FALSE; ++ } ++ else ++ { ++ PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ } ++ ++ //1 Run AntDiv mechanism "Before Link" part. ++ if(pDM_SWAT_Table->SWAS_NoLink_State == 0) ++ { ++ //1 Prepare to do Scan again to check current antenna state. ++ ++ // Set check state to next step. ++ pDM_SWAT_Table->SWAS_NoLink_State = 1; ++ ++ // Copy Current Scan list. ++ Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; ++ PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ if(pDM_FatTable->RxIdleAnt == MAIN_ANT) ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); ++ else ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); ++ } ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ { ++ // Switch Antenna to another one. ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); ++ pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); ++ } ++ // Go back to scan function again. ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Scan one more time\n")); ++ pMgntInfo->ScanStep=0; ++ target_chnl = odm_SwAntDivSelectChkChnl(Adapter); ++ odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl); ++ HTReleaseChnlOpLock(Adapter); ++ PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); ++ ++ return TRUE; ++ } ++ else ++ { ++ //1 ScanComple() is called after antenna swiched. ++ //1 Check scan result and determine which antenna is going ++ //1 to be used. ++ ++ for(index=0; indexMgntInfo.tmpNumBssDesc; index++) ++ { ++ pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); ++ pTestBssDesc = &(pMgntInfo->bssDesc[index]); ++ ++ if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C(): ERROR!! This shall not happen.\n")); ++ continue; ++ } ++ ++ if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score++\n")); ++ RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); ++ ++ Score++; ++ PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); ++ } ++ else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score--\n")); ++ RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); ++ Score--; ++ } ++ ++ } ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ if(pMgntInfo->NumBssDesc!=0 && Score<=0) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); ++ ++ if(pDM_FatTable->RxIdleAnt == MAIN_ANT) ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); ++ else ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ++ } ++ } ++ ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ { ++ if(pMgntInfo->NumBssDesc!=0 && Score<=0) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_A":"Antenna_B")); ++ ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_B":"Antenna_A")); ++ ++ pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); ++ pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); ++ PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); ++ } ++ } ++ // Check state reset to default and wait for next time. ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ ++ return FALSE; ++ } ++#else ++ return FALSE; ++#endif ++ ++return FALSE; ++} ++#else ++BOOLEAN ++ODM_SwAntDivCheckBeforeLink8192C( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ return FALSE; ++ ++} ++#endif //#if((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY))) ++#endif //#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++ ++ ++//3============================================================ ++//3 SW Antenna Diversity ++//3============================================================ ++ ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++VOID ++odm_InitHybridAntDiv_88C_92D( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) ++ struct rtl8192cd_priv *priv=pDM_Odm->priv; ++#endif ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ u1Byte bTxPathSel=0; //0:Path-A 1:Path-B ++ u1Byte i; ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n")); ++ ++ //whether to do antenna diversity or not ++#if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if(priv==NULL) return; ++ if(!priv->pshare->rf_ft_var.antHw_enable) ++ return; ++ ++ #ifdef SW_ANT_SWITCH ++ priv->pshare->rf_ft_var.antSw_enable =0; ++ #endif ++#endif ++ ++ if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) ++ return; ++ ++ ++ bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE; ++ ++ ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1 ++ ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna ++ // check HW setting: ANTSEL pin connection ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ ODM_Write2Byte(pDM_Odm,ODM_REG_RF_PIN_11N, (ODM_Read2Byte(pDM_Odm,0x804)&0xf0ff )| BIT(8) ); // b11-b8=0001,update RFPin setting ++ #endif ++ ++ // only AP support different path selection temperarly ++ if(!bTxPathSel){ //PATH-A ++ ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1); //select TX ANTESEL from path A ++ } ++ else { ++ ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0); //select ANTESEL from path B ++ } ++ ++ //Set OFDM HW RX Antenna Diversity ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold ++ ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1); // Decide final antenna by comparing 2 antennas' pwdb ++ ++ //Set CCK HW RX Antenna Diversity ++ ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample ++ ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 ++ ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0 ++ ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16) ++ ++ ++ //Enable HW Antenna Diversity ++ if(!bTxPathSel) //PATH-A ++ ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1); // Enable Hardware antenna switch ++ else ++ ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1); // Enable Hardware antenna switch ++ ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity ++ ++ pDM_SWAT_Table->CurAntenna=0; //choose left antenna as default antenna ++ pDM_SWAT_Table->PreAntenna=0; ++ for(i=0; iCCK_Ant1_Cnt[i] = 0; ++ pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0; ++ pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0; ++ pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0; ++ pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0; ++ pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0; ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n")); ++} ++ ++ ++VOID ++odm_InitHybridAntDiv( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n")); ++ return; ++ } ++ ++ if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) ++ { ++#if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1)) ++ odm_InitHybridAntDiv_88C_92D(pDM_Odm); ++#endif ++ } ++ else if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++#if (RTL8188E_SUPPORT == 1) ++ ODM_AntennaDiversityInit_88E(pDM_Odm); ++#endif ++ } ++ ++} ++ ++ ++BOOLEAN ++odm_StaDefAntSel( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte OFDM_Ant1_Cnt, ++ IN u4Byte OFDM_Ant2_Cnt, ++ IN u4Byte CCK_Ant1_Cnt, ++ IN u4Byte CCK_Ant2_Cnt, ++ OUT u1Byte *pDefAnt ++ ++ ) ++{ ++#if 1 ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n")); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt)); ++ ++ ++ if(((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n")); ++ return FALSE; ++ } ++ ++ if(OFDM_Ant1_Cnt || OFDM_Ant2_Cnt ) { ++ //if RX OFDM packet number larger than 0 ++ if(OFDM_Ant1_Cnt > OFDM_Ant2_Cnt) ++ (*pDefAnt)=1; ++ else ++ (*pDefAnt)=0; ++ } ++ // else if RX CCK packet number larger than 10 ++ else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 ) ++ { ++ if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt)) ++ (*pDefAnt)=1; ++ else if(CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt)) ++ (*pDefAnt)=0; ++ else if(CCK_Ant1_Cnt > CCK_Ant2_Cnt) ++ (*pDefAnt)=0; ++ else ++ (*pDefAnt)=1; ++ ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2")); ++ ++#endif ++ //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0); ++ //(*pDefAnt)= (u1Byte) antsel; ++ ++ ++ ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n")); ++ ++ return TRUE; ++ ++ ++} ++ ++ ++VOID ++odm_SetRxIdleAnt( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Ant, ++ IN BOOLEAN bDualPath ++) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n")); ++ ++ if(Ant != pDM_SWAT_Table->RxIdleAnt) ++ { ++ //for path-A ++ if(Ant==1) ++ ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); //right-side antenna ++ else ++ ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); //left-side antenna ++ ++ //for path-B ++ if(bDualPath){ ++ if(Ant==0) ++ ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); //right-side antenna ++ else ++ ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); //left-side antenna ++ } ++ } ++ pDM_SWAT_Table->RxIdleAnt = Ant; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a)); ++ ++ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n")); ++ ++ } ++ ++VOID ++ODM_AntselStatistics_88C( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacId, ++ IN u4Byte PWDBAll, ++ IN BOOLEAN isCCKrate ++) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ if(pDM_SWAT_Table->antsel == 1) ++ { ++ if(isCCKrate) ++ pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++; ++ else ++ { ++ pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++; ++ pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll; ++ } ++ } ++ else ++ { ++ if(isCCKrate) ++ pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++; ++ else ++ { ++ pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++; ++ pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll; ++ } ++ } ++ ++} ++ ++ ++ ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++VOID ++ODM_SetTxAntByTxInfo_88C_92D( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ u1Byte antsel; ++ ++ if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) ++ return; ++ ++ if(pDM_SWAT_Table->RxIdleAnt == 1) ++ antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?0:1; ++ else ++ antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?1:0; ++ ++ SET_TX_DESC_ANTSEL_A_92C(pDesc, antsel); ++ //SET_TX_DESC_ANTSEL_B_92C(pDesc, antsel); ++ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId])); ++} ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++VOID ++ODM_SetTxAntByTxInfo_88C_92D( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ ++} ++#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) ++VOID ++ODM_SetTxAntByTxInfo_88C_92D( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ ++} ++#endif ++ ++VOID ++odm_HwAntDiv_92C_92D( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ u4Byte RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2; ++ u1Byte RxIdleAnt, i; ++ BOOLEAN bRet=FALSE; ++ PSTA_INFO_T pEntry; ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ struct rtl8192cd_priv *priv=pDM_Odm->priv; ++ //if test, return ++ if(priv->pshare->rf_ft_var.CurAntenna & 0x80) ++ return; ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n")); ++ ++ if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) //if don't support antenna diveristy ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n")); ++ return; ++ } ++ ++ if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n")); ++ return; ++ } ++ ++#if (DM_ODM_SUPPORT_TYPE&(ODM_MP|ODM_CE)) ++ if(!pDM_Odm->bLinked) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is FALSE\n")); ++ return; ++ } ++#endif ++ ++ for (i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pEntry)) ++ { ++ ++ RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]); ++ RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]); ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d, RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2)); ++ ++ if(RSSI_Ant1 ||RSSI_Ant2) ++ { ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if(pDM_Odm->pODM_StaInfo[i]->expire_to) ++#endif ++ { ++ RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2; ++ if((!RSSI) || ( RSSI < RSSI_Min) ) { ++ pDM_SWAT_Table->TargetSTA = i; ++ RSSI_Min = RSSI; ++ } ++ } ++ } ++ ///STA: found out default antenna ++ bRet=odm_StaDefAntSel(pDM_Odm, ++ pDM_SWAT_Table->OFDM_Ant1_Cnt[i], ++ pDM_SWAT_Table->OFDM_Ant2_Cnt[i], ++ pDM_SWAT_Table->CCK_Ant1_Cnt[i], ++ pDM_SWAT_Table->CCK_Ant2_Cnt[i], ++ &pDM_SWAT_Table->TxAnt[i]); ++ ++ //if Tx antenna selection: successful ++ if(bRet){ ++ pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0; ++ pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0; ++ pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0; ++ pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0; ++ pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0; ++ pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0; ++ } ++ } ++ } ++ ++ //set RX Idle Ant ++ RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA]; ++ odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE); ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++#ifdef TX_SHORTCUT ++ if (!priv->pmib->dot11OperationEntry.disable_txsc) { ++ plist = phead->next; ++ while(plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ if(pstat->expire_to) { ++ for (i=0; itx_sc_ent[i].hwdesc1); ++ pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); ++ if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) ++ pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); ++ pdesc= &(pstat->tx_sc_ent[i].hwdesc2); ++ pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); ++ if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) ++ pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); ++ } ++ } ++ ++ if (plist == plist->next) ++ break; ++ plist = plist->next; ++ }; ++ } ++#endif ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n")); ++ ++} ++ ++VOID ++odm_HwAntDiv( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n")); ++ return; ++ } ++ ++ if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) ++ { ++#if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1)) ++ odm_HwAntDiv_92C_92D(pDM_Odm); ++#endif ++ } ++ else if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++#if (RTL8188E_SUPPORT == 1) ++ ODM_AntennaDiversity_88E(pDM_Odm); ++#endif ++ } ++ ++} ++ ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++#if 0 ++VOID ++odm_HwAntDiv( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ struct rtl8192cd_priv *priv=pDM_Odm->priv; ++ struct stat_info *pstat, *pstat_min=NULL; ++ struct list_head *phead, *plist; ++ int rssi_min= 0xff, i; ++ u1Byte idleAnt=priv->pshare->rf_ft_var.CurAntenna; ++ u1Byte nextAnt; ++ BOOLEAN bRet=FALSE; ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n")); ++ ++ if((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))) ++ return; ++ ++ //if test, return ++ if(priv->pshare->rf_ft_var.CurAntenna & 0x80) ++ return; ++ ++ phead = &priv->asoc_list; ++ plist = phead->next; ++ ////========================= ++ //find mimum rssi sta ++ ////========================= ++ while(plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) { ++ int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1]; ++ if((!pstat_min) || ( rssi < rssi_min) ) { ++ pstat_min = pstat; ++ rssi_min = rssi; ++ } ++ } ++ ///STA: found out default antenna ++ bRet=odm_StaDefAntSel(pDM_Odm, ++ pstat->hwRxAntSel[1], ++ pstat->hwRxAntSel[0], ++ pstat->cckPktCount[1], ++ pstat->cckPktCount[0], ++ &nextAnt ++ ); ++ ++ //if default antenna selection: successful ++ if(bRet){ ++ pstat->CurAntenna = nextAnt; ++ //update rssi ++ for(i=0; i<2; i++) { ++ if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0) ++ pstat->AntRSSI[i] = 0; ++ } ++ if(pstat->AntRSSI[idleAnt]==0) ++ pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1]; ++ // reset variables ++ pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0; ++ pstat->cckPktCount[1]= pstat->cckPktCount[0] =0; ++ } ++ ++ if (plist == plist->next) ++ break; ++ plist = plist->next; ++ ++ }; ++ ////========================= ++ //Choose RX Idle antenna according to minmum rssi ++ ////========================= ++ if(pstat_min) { ++ if(priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna) ++ odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE); ++ priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna; ++ } ++ ++ ++#ifdef TX_SHORTCUT ++ if (!priv->pmib->dot11OperationEntry.disable_txsc) { ++ plist = phead->next; ++ while(plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ if(pstat->expire_to) { ++ for (i=0; itx_sc_ent[i].hwdesc1); ++ pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); ++ if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) ++ pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); ++ pdesc= &(pstat->tx_sc_ent[i].hwdesc2); ++ pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); ++ if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) ++ pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); ++ } ++ } ++ ++ if (plist == plist->next) ++ break; ++ plist = plist->next; ++ }; ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n"); ++} ++#endif ++ ++u1Byte ++ODM_Diversity_AntennaSelect( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte *data ++) ++{ ++ struct rtl8192cd_priv *priv=pDM_Odm->priv; ++ ++ int ant = _atoi(data, 16); ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ODM_Diversity_AntennaSelect==============>\n")); ++ ++ #ifdef PCIE_POWER_SAVING ++ PCIeWakeUp(priv, POWER_DOWN_T0); ++ #endif ++ ++ if (ant==Antenna_B || ant==Antenna_A) ++ { ++ if ( !priv->pshare->rf_ft_var.antSw_select) { ++ ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(8)| BIT(9) ); // ANTSEL A as SW control ++ ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7))); // rx OFDM SW control ++ PHY_SetBBReg(priv, 0x860, 0x300, ant); ++ } else { ++ ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(24)| BIT(25) ); // ANTSEL B as HW control ++ PHY_SetBBReg(priv, 0x864, 0x300, ant); ++ ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7))); // rx OFDM SW control ++ } ++ ++ ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7))); // rx CCK SW control ++ ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc ++ ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); ++ ++ priv->pshare->rf_ft_var.antHw_enable = 0; ++ priv->pshare->rf_ft_var.CurAntenna = (ant%2); ++ ++ #ifdef SW_ANT_SWITCH ++ priv->pshare->rf_ft_var.antSw_enable = 0; ++ priv->pshare->DM_SWAT_Table.CurAntenna = ant; ++ priv->pshare->RSSI_test =0; ++ #endif ++ } ++ else if(ant==0){ ++ ++ if ( !priv->pshare->rf_ft_var.antSw_select) { ++ ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(8)| BIT(9)) ); ++ ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) | BIT(7)); // OFDM HW control ++ } else { ++ ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(24)| BIT(25)) ); ++ ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) | BIT(7)); // OFDM HW control ++ } ++ ++ ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) | BIT(7)); // CCK HW control ++ ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) | BIT(21) ); // by tx desc ++ priv->pshare->rf_ft_var.CurAntenna = 0; ++ ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); ++ priv->pshare->rf_ft_var.antHw_enable = 1; ++#ifdef SW_ANT_SWITCH ++ priv->pshare->rf_ft_var.antSw_enable = 0; ++ priv->pshare->RSSI_test =0; ++#endif ++ } ++#ifdef SW_ANT_SWITCH ++ else if(ant==3) { ++ if(!priv->pshare->rf_ft_var.antSw_enable) { ++ ++ dm_SW_AntennaSwitchInit(priv); ++ ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); ++ priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; ++ priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; ++ } ++ if ( !priv->pshare->rf_ft_var.antSw_select) ++ ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7))); // rx OFDM SW control ++ else ++ ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7))); // rx OFDM SW control ++ ++ ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7))); // rx CCK SW control ++ ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc ++ priv->pshare->rf_ft_var.antHw_enable = 0; ++ priv->pshare->rf_ft_var.antSw_enable = 1; ++ ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============ODM_Diversity_AntennaSelect\n")); ++ ++ return 1; ++} ++#endif ++ ++#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++ ++VOID odm_InitHybridAntDiv( IN PDM_ODM_T pDM_Odm ){} ++VOID odm_HwAntDiv( IN PDM_ODM_T pDM_Odm){} ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++VOID ODM_SetTxAntByTxInfo_88C_92D( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++){} ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++VOID ODM_SetTxAntByTxInfo_88C_92D( IN PDM_ODM_T pDM_Odm){ } ++#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) ++VOID ODM_SetTxAntByTxInfo_88C_92D( IN PDM_ODM_T pDM_Odm){ } ++#endif ++ ++#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++ ++ ++ ++//============================================================ ++//EDCA Turbo ++//============================================================ ++VOID ++ODM_EdcaTurboInit( ++ IN PDM_ODM_T pDM_Odm) ++{ ++ ++#if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) ++ odm_EdcaParaInit(pDM_Odm); ++#elif (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ PADAPTER Adapter = NULL; ++ HAL_DATA_TYPE *pHalData = NULL; ++ ++ if(pDM_Odm->Adapter==NULL) { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); ++ return; ++ } ++ ++ Adapter=pDM_Odm->Adapter; ++ pHalData=GET_HAL_DATA(Adapter); ++ ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; ++ pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; ++ pHalData->bIsAnyNonBEPkts = FALSE; ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; ++ pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; ++ Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; ++ ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); ++ ++ ++} // ODM_InitEdcaTurbo ++ ++VOID ++odm_EdcaTurboCheck( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ // ++ // For AP/ADSL use prtl8192cd_priv ++ // For CE/NIC use PADAPTER ++ // ++ PADAPTER pAdapter = pDM_Odm->Adapter; ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++ // ++ // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate ++ // at the same time. In the stage2/3, we need to prive universal interface and merge all ++ // HW dynamic mechanism. ++ // ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); ++ ++ if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) ++ return; ++ ++ switch (pDM_Odm->SupportPlatform) ++ { ++ case ODM_MP: ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++ odm_EdcaTurboCheckMP(pDM_Odm); ++#endif ++ break; ++ ++ case ODM_CE: ++#if(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ odm_EdcaTurboCheckCE(pDM_Odm); ++#endif ++ break; ++ ++ case ODM_AP: ++ case ODM_ADSL: ++ ++#if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) ++ odm_IotEngine(pDM_Odm); ++#endif ++ break; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); ++ ++} // odm_CheckEdcaTurbo ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ ++ ++VOID ++odm_EdcaTurboCheckCE( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++ u32 trafficIndex; ++ u32 edca_param; ++ u64 cur_tx_bytes = 0; ++ u64 cur_rx_bytes = 0; ++ u8 bbtchange = _FALSE; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); ++ struct recv_priv *precvpriv = &(Adapter->recvpriv); ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++ ++ if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ if (BT_DisableEDCATurbo(Adapter)) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++#endif ++ ++ // Check if the status needs to be changed. ++ if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) ++ { ++ cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; ++ cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; ++ ++ //traffic, TX or RX ++ if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)||(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) ++ { ++ if (cur_tx_bytes > (cur_rx_bytes << 2)) ++ { // Uplink TP is present. ++ trafficIndex = UP_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ } ++ else ++ { ++ if (cur_rx_bytes > (cur_tx_bytes << 2)) ++ { // Downlink TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = UP_LINK; ++ } ++ } ++ ++ if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) ++ { ++ ++#if 0 ++ //adjust EDCA parameter for BE queue ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++#else ++ ++ if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) ++ { ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++ } ++ else ++ { ++ edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; ++ } ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ if(IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ edca_param = 0x60a42b; ++ } ++ else ++ { ++ edca_param = 0x6ea42b; ++ } ++#endif ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); ++ ++ pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; ++ } ++ ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; ++ } ++ else ++ { ++ // ++ // Turn Off EDCA turbo here. ++ // Restore original EDCA according to the declaration of AP. ++ // ++ if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) ++ { ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; ++ } ++ } ++ ++dm_CheckEdcaTurbo_EXIT: ++ // Set variables for next time. ++ precvpriv->bIsAnyNonBEPkts = _FALSE; ++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; ++ precvpriv->last_rx_bytes = precvpriv->rx_bytes; ++#endif ++} ++ ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_MP) ++VOID ++odm_EdcaTurboCheckMP( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++ PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); ++ PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; ++ //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn ++ u8Byte Ext_curTxOkCnt = 0; ++ u8Byte Ext_curRxOkCnt = 0; ++ static u8Byte Ext_lastTxOkCnt = 0; ++ static u8Byte Ext_lastRxOkCnt = 0; ++ //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. ++ u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; ++ ++#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); ++ struct recv_priv *precvpriv = &(Adapter->recvpriv); ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ #ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ #endif ++ u1Byte bbtchange =FALSE; ++#endif ++ // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. ++ u8Byte curTxOkCnt = 0; ++ u8Byte curRxOkCnt = 0; ++ u8Byte lastTxOkCnt = 0; ++ u8Byte lastRxOkCnt = 0; ++ u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; ++ u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; ++ u4Byte EDCA_BE = 0x5ea42b; ++ u4Byte IOTPeer=0; ++ BOOLEAN *pbIsCurRDLState=NULL; ++ BOOLEAN bLastIsCurRDLState=FALSE; ++ BOOLEAN bBiasOnRx=FALSE; ++ BOOLEAN bEdcaTurboOn=FALSE; ++ ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); ++ ++////=============================== ++////list paramter for different platform ++////=============================== ++ bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; ++ pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ // Caculate TX/RX TP: ++ curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; ++ curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; ++ if(pExtAdapter == NULL) ++ pExtAdapter = pDefaultAdapter; ++ ++ Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; ++ Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; ++ GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); ++ //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. ++ if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) ++ { ++ curTxOkCnt = Ext_curTxOkCnt ; ++ curRxOkCnt = Ext_curRxOkCnt ; ++ } ++ // ++ IOTPeer=pMgntInfo->IOTPeer; ++ bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; ++ bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts) && (!pMgntInfo->bDisableFrameBursting))?TRUE:FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx bDisableFrameBursting : 0x%lx \n",pHalData->bIsAnyNonBEPkts,pMgntInfo->bDisableFrameBursting)); ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ // Caculate TX/RX TP: ++ curTxOkCnt = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; ++ curRxOkCnt = precvpriv->rx_bytes - precvpriv->last_rx_bytes; ++ #ifdef CONFIG_BT_COEXIST ++ if(pbtpriv->BT_Coexist) ++ { ++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) ++ bbtchange = TRUE; ++ } ++ #endif ++ IOTPeer=pmlmeinfo->assoc_AP_vendor; ++ bBiasOnRx=((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))?TRUE:FALSE; ++ bEdcaTurboOn=(bbtchange || (!precvpriv->bIsAnyNonBEPkts))?TRUE:FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bbtchange : 0x%lx bIsAnyNonBEPkts : 0x%lx \n",bbtchange,precvpriv->bIsAnyNonBEPkts)); ++#endif ++ ++ ++////=============================== ++////check if edca turbo is disabled ++////=============================== ++ if(odm_IsEdcaTurboDisable(pDM_Odm)) ++ goto dm_CheckEdcaTurbo_EXIT; ++ ++ ++////=============================== ++////remove iot case out ++////=============================== ++ ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); ++ ++ ++////=============================== ++////Check if the status needs to be changed. ++////=============================== ++ if(bEdcaTurboOn) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); ++ if(bBiasOnRx) ++ odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); ++ else ++ odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); ++ ++//modify by Guo.Mingzhi 2011-12-29 ++ EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; ++ ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); ++ ++// if(((*pbIsCurRDLState)!=bLastIsCurRDLState)||(!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) ++// { ++// EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; ++// ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); ++ // } ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); ++ ++ } ++ else ++ { ++ // Turn Off EDCA turbo here. ++ // Restore original EDCA according to the declaration of AP. ++ if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) ++ { ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, pHalData->AcParam_BE); ++#endif ++ ++ pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); ++ ++ } ++ } ++ ++////=============================== ++////Set variables for next time. ++////=============================== ++dm_CheckEdcaTurbo_EXIT: ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ pHalData->bIsAnyNonBEPkts = FALSE; ++ pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; ++ pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; ++ pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; ++ pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; ++#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) ++ precvpriv->bIsAnyNonBEPkts = FALSE; ++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; ++ precvpriv->last_rx_bytes = precvpriv->rx_bytes; ++#endif ++ ++} ++ ++ ++//check if edca turbo is disabled ++BOOLEAN ++odm_IsEdcaTurboDisable( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ u4Byte IOTPeer=pMgntInfo->IOTPeer; ++#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u4Byte IOTPeer=pmlmeinfo->assoc_AP_vendor; ++ u1Byte WirelessMode=0xFF; //invalid value ++ ++ if(pDM_Odm->pWirelessMode!=NULL) ++ WirelessMode=*(pDM_Odm->pWirelessMode); ++ ++#endif ++ ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtDisableEdcaTurbo) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); ++ return TRUE; ++ } ++#endif ++ ++ if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| ++ (pDM_Odm->bWIFITest)|| ++ (IOTPeer>= HT_IOT_PEER_MAX)) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); ++ return TRUE; ++ } ++ ++ ++#if (DM_ODM_SUPPORT_TYPE ==ODM_MP) ++ // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue ++ // 2. User may disable EDCA Turbo mode with OID settings. ++ if((pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) ||pHalData->bForcedDisableTurboEDCA){ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); ++ return TRUE; ++ } ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ //suggested by Jr.Luke: open TXOP for B/G/BG/A mode 2012-0215 ++ if((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)||(WirelessMode==ODM_WM_G)||(WirelessMode=ODM_WM_A)) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)|0x5E0000); ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8192D) { ++ if ((pregpriv->wifi_spec == 1) || (pmlmeext->cur_wireless_mode == WIRELESS_11B)) { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("92D:EdcaTurboDisable\n")); ++ return TRUE; ++ } ++ } ++ else ++ { ++ if((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)){ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("Others:EdcaTurboDisable\n")); ++ return TRUE; ++ } ++ } ++#ifdef CONFIG_BT_COEXIST ++ if (BT_DisableEDCATurbo(Adapter)) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++#endif ++ ++#endif ++ ++ return FALSE; ++ ++ ++} ++ ++//add iot case here: for MP/CE ++VOID ++ODM_EdcaParaSelByIot( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u4Byte *EDCA_BE_UL, ++ OUT u4Byte *EDCA_BE_DL ++ ) ++{ ++ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u4Byte IOTPeer=0; ++ u4Byte ICType=pDM_Odm->SupportICType; ++ u1Byte WirelessMode=0xFF; //invalid value ++ u4Byte RFType=pDM_Odm->RFType; ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_MP) ++ PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); ++ PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ #ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ #endif ++ u1Byte bbtchange =FALSE; ++#endif ++ ++ if(pDM_Odm->pWirelessMode!=NULL) ++ WirelessMode=*(pDM_Odm->pWirelessMode); ++ ++/////////////////////////////////////////////////////////// ++////list paramter for different platform ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ IOTPeer=pMgntInfo->IOTPeer; ++ GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); ++ ++#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) ++ IOTPeer=pmlmeinfo->assoc_AP_vendor; ++ #ifdef CONFIG_BT_COEXIST ++ if(pbtpriv->BT_Coexist) ++ { ++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) ++ bbtchange = TRUE; ++ } ++ #endif ++ ++#endif ++ ++ if(ICType==ODM_RTL8192D) ++ { ++ // Single PHY ++ if(pDM_Odm->RFType==ODM_2T2R) ++ { ++ (*EDCA_BE_UL) = 0x60a42b; //0x5ea42b; ++ (*EDCA_BE_DL) = 0x60a42b; //0x5ea42b; ++ ++ } ++ else ++ { ++ (*EDCA_BE_UL) = 0x6ea42b; ++ (*EDCA_BE_DL) = 0x6ea42b; ++ } ++ ++ } ++////============================ ++/// IOT case for MP ++////============================ ++#if (DM_ODM_SUPPORT_TYPE==ODM_MP) ++ else ++ { ++ ++ if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){ ++ if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) { ++ (*EDCA_BE_UL) = 0x60a42b; ++ (*EDCA_BE_DL) = 0x60a42b; ++ } ++ else ++ { ++ (*EDCA_BE_UL) = 0x6ea42b; ++ (*EDCA_BE_DL) = 0x6ea42b; ++ } ++ } ++ } ++ ++ if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) ++ { ++ (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; ++ (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; ++ } ++ ++ #if (INTEL_PROXIMITY_SUPPORT == 1) ++ if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) ++ { ++ (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; ++ } ++ else ++ #endif ++ { ++ if((!pMgntInfo->bDisableFrameBursting) && ++ (pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) ++ {// To check whether we shall force turn on TXOP configuration. ++ if(!((*EDCA_BE_UL) & 0xffff0000)) ++ (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. ++ if(!((*EDCA_BE_DL) & 0xffff0000)) ++ (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. ++ } ++ ++ //92D txop can't be set to 0x3e for cisco1250 ++ if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) ++ { ++ (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; ++ (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; ++ } ++ //merge from 92s_92c_merge temp brunch v2445 20120215 ++ else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) ++ { ++ (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; ++ } ++ else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) ++ { ++ (*EDCA_BE_DL) = 0xa630; ++ } ++ ++ else if(IOTPeer == HT_IOT_PEER_MARVELL) ++ { ++ (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; ++ (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; ++ } ++ else if(IOTPeer == HT_IOT_PEER_ATHEROS) ++ { ++ // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. ++ (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; ++ } ++ } ++////============================ ++/// IOT case for CE ++////============================ ++#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) ++ ++ if(RFType==ODM_RTL8192D) ++ { ++ if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) ++ { ++ (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK]; ++ (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK]; ++ } ++ else if((IOTPeer == HT_IOT_PEER_AIRGO) && ++ ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)))) ++ (*EDCA_BE_DL)=0x00a630; ++ ++ else if((IOTPeer== HT_IOT_PEER_ATHEROS) && ++ (WirelessMode&ODM_WM_N5G) && ++ (Adapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )) ++ (*EDCA_BE_DL)=0xa42b; ++ ++ } ++ //92C IOT case: ++ else ++ { ++ #ifdef CONFIG_BT_COEXIST ++ if(bbtchange) ++ { ++ (*EDCA_BE_UL) = pbtpriv->BT_EDCA[UP_LINK]; ++ (*EDCA_BE_DL) = pbtpriv->BT_EDCA[DOWN_LINK]; ++ } ++ else ++ #endif ++ { ++ if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) ++ { ++ (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK]; ++ (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK]; ++ } ++ else ++ { ++ (*EDCA_BE_UL)=EDCAParam[HT_IOT_PEER_UNKNOWN][UP_LINK]; ++ (*EDCA_BE_DL)=EDCAParam[HT_IOT_PEER_UNKNOWN][DOWN_LINK]; ++ } ++ } ++ if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){ ++ if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) ++ { ++ (*EDCA_BE_UL) = 0x60a42b; ++ (*EDCA_BE_DL) = 0x60a42b; ++ } ++ else ++ { ++ (*EDCA_BE_UL) = 0x6ea42b; ++ (*EDCA_BE_DL) = 0x6ea42b; ++ } ++ } ++ ++ } ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL))); ++ ++} ++ ++ ++VOID ++odm_EdcaChooseTrafficIdx( ++ IN PDM_ODM_T pDM_Odm, ++ IN u8Byte cur_tx_bytes, ++ IN u8Byte cur_rx_bytes, ++ IN BOOLEAN bBiasOnRx, ++ OUT BOOLEAN *pbIsCurRDLState ++ ) ++{ ++ ++ ++ if(bBiasOnRx) ++ { ++ ++ if(cur_tx_bytes>(cur_rx_bytes*4)) ++ { ++ *pbIsCurRDLState=FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); ++ ++ } ++ else ++ { ++ *pbIsCurRDLState=TRUE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); ++ ++ } ++ } ++ else ++ { ++ if(cur_rx_bytes>(cur_tx_bytes*4)) ++ { ++ *pbIsCurRDLState=TRUE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); ++ ++ } ++ else ++ { ++ *pbIsCurRDLState=FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); ++ } ++ } ++ ++ return ; ++} ++ ++#endif ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) ++ ++void odm_EdcaParaInit( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ int mode=priv->pmib->dot11BssType.net_work_type; ++ ++ static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time; ++ struct ParaRecord EDCA[4]; ++ ++ memset(EDCA, 0, 4*sizeof(struct ParaRecord)); ++ ++ sifs_time = 10; ++ slot_time = 20; ++ ++ if (mode & (ODM_WM_N24G|ODM_WM_N5G)) ++ sifs_time = 16; ++ ++ if (mode & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G|ODM_WM_A)) ++ slot_time = 9; ++ ++ ++#if((defined(RTL_MANUAL_EDCA))&&(DM_ODM_SUPPORT_TYPE==ODM_AP)) ++ if( priv->pmib->dot11QosEntry.ManualEDCA ) { ++ if( OPMODE & WIFI_AP_STATE ) ++ memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord)); ++ else ++ memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord)); ++ ++ #ifdef WIFI_WMM ++ if (QOS_ENABLE) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); ++ else ++ #endif ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); ++ ++ }else ++ #endif //RTL_MANUAL_EDCA ++ { ++ ++ if(OPMODE & WIFI_AP_STATE) ++ { ++ memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord)); ++ ++ if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G)) ++ memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); ++ else ++ memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord)); ++ } ++ else ++ { ++ memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord)); ++ ++ if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G)) ++ memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); ++ else ++ memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord)); ++ } ++ ++ #ifdef WIFI_WMM ++ if (QOS_ENABLE) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); ++ else ++ #endif ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); ++#elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + 2* slot_time)); ++#endif ++ ++ ++ } ++ ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VO_PARAM, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time)); ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time)); ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BK_PARAM, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time)); ++// ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00); ++ ++ priv->pshare->iot_mode_enable = 0; ++#if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (priv->pshare->rf_ft_var.wifi_beq_iot) ++ priv->pshare->iot_mode_VI_exist = 0; ++ ++ #ifdef WMM_VIBE_PRI ++ priv->pshare->iot_mode_BE_exist = 0; ++ #endif ++ ++ #ifdef LOW_TP_TXOP ++ priv->pshare->BE_cwmax_enhance = 0; ++ #endif ++ ++#elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ priv->pshare->iot_mode_BE_exist = 0; ++#endif ++ priv->pshare->iot_mode_VO_exist = 0; ++} ++ ++BOOLEAN ++ODM_ChooseIotMainSTA( ++ IN PDM_ODM_T pDM_Odm, ++ IN PSTA_INFO_T pstat ++ ) ++{ ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ BOOLEAN bhighTP_found_pstat=FALSE; ++ ++ if ((GET_ROOT(priv)->up_time % 2) == 0) { ++ unsigned int tx_2s_avg = 0; ++ unsigned int rx_2s_avg = 0; ++ int i=0, aggReady=0; ++ unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes); ++ ++ pstat->current_tx_bytes += pstat->tx_byte_cnt; ++ pstat->current_rx_bytes += pstat->rx_byte_cnt; ++ ++ if (total_sum != 0) { ++ if (total_sum <= 100) { ++ tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum); ++ rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum); ++ } else { ++ tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100)); ++ rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100)); ++ } ++ ++ } ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ if (pstat->ht_cap_len) { ++ if ((tx_2s_avg + rx_2s_avg) >=25 /*50*/) { ++ ++ priv->pshare->highTP_found_pstat = pstat; ++ bhighTP_found_pstat=TRUE; ++ } ++ } ++#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ for(i=0; i<8; i++) ++ aggReady += (pstat->ADDBA_ready[i]); ++ if (pstat->ht_cap_len && aggReady) ++ { ++ if ((tx_2s_avg + rx_2s_avg >= 25)) { ++ priv->pshare->highTP_found_pstat = pstat; ++ } ++ ++ #ifdef CLIENT_MODE ++ if (OPMODE & WIFI_STATION_STATE) { ++#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) ++ if ((pstat->IOTPeer==HT_IOT_PEER_RALINK) && ((tx_2s_avg + rx_2s_avg) >= 45)) ++#else ++ if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45)) ++#endif ++ priv->pshare->highTP_found_pstat = pstat; ++ } ++ #endif ++ } ++#endif ++ } else { ++ pstat->current_tx_bytes = pstat->tx_byte_cnt; ++ pstat->current_rx_bytes = pstat->rx_byte_cnt; ++ } ++ ++ return bhighTP_found_pstat; ++} ++ ++ ++#ifdef WIFI_WMM ++VOID ++ODM_IotEdcaSwitch( ++ IN PDM_ODM_T pDM_Odm, ++ IN unsigned char enable ++ ) ++{ ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ int mode=priv->pmib->dot11BssType.net_work_type; ++ unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94; ++ unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs; ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (!(!priv->pmib->dot11OperationEntry.wifi_specific || ++ ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ #ifdef CLIENT_MODE ++ || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ #endif ++ )) ++ return; ++#endif ++ ++ if ((mode & (ODM_WM_N24G|ODM_WM_N5G)) && (priv->pshare->ht_sta_num ++ #ifdef WDS ++ || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) ++ #endif ++ )) ++ sifs_time = 16; ++ ++ if (mode & (ODM_WM_N24G|ODM_WM_N5G|ODM_WM_G|ODM_WM_A)) { ++ slot_time = 9; ++ } ++ else ++ { ++ BE_TXOP = 94; ++ VI_TXOP = 188; ++ } ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ if (priv->pshare->iot_mode_VO_exist) { ++ // to separate AC_VI and AC_BE to avoid using the same EDCA settings ++ if (priv->pshare->iot_mode_BE_exist) { ++ vi_cw_max = 5; ++ vi_cw_min = 3; ++ } else { ++ vi_cw_max = 6; ++ vi_cw_min = 4; ++ } ++ } ++ vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); ++ ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); ++ ++ ++#elif (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { ++ if (priv->pshare->iot_mode_VO_exist) { ++ #ifdef WMM_VIBE_PRI ++ if (priv->pshare->iot_mode_BE_exist) ++ { ++ vi_cw_max = 5; ++ vi_cw_min = 3; ++ vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); ++ } ++ else ++ #endif ++ { ++ vi_cw_max = 6; ++ vi_cw_min = 4; ++ vi_aifs = 0x2b; ++ } ++ } ++ else { ++ vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); ++ } ++ ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16) ++ | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); ++ } ++#endif ++ ++ ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (10 << 12) | (4 << 8) | 0x4f); ++ else if(!enable) ++#elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ if(!enable) //if iot is disable ,maintain original BEQ PARAM ++#endif ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8) ++ | (sifs_time + 3 * slot_time)); ++ else ++ { ++ int txop_enlarge; ++ int txop; ++ unsigned int cw_max; ++ unsigned int txop_close; ++ ++ #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)) ++ cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6); ++ txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0); ++ ++ if(priv->pshare->txop_enlarge == 0xe) //if intel case ++ txop = (txop_close ? 0 : (BE_TXOP*2)); ++ else //if other case ++ txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge)); ++ #else ++ cw_max=6; ++ if((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd)) ++ txop=BE_TXOP*2; ++ else ++ txop=BE_TXOP*priv->pshare->txop_enlarge; ++ ++ #endif ++ ++ if (priv->pshare->ht_sta_num ++ #ifdef WDS ++ || ((OPMODE & WIFI_AP_STATE) && (mode & (ODM_WM_N24G|ODM_WM_N5G)) && ++ priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) ++ #endif ++ ) ++ { ++ ++ if (priv->pshare->txop_enlarge == 0xe) { ++ // is intel client, use a different edca value ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f); ++ priv->pshare->txop_enlarge = 2; ++ } ++#if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ #ifndef LOW_TP_TXOP ++ else if (priv->pshare->txop_enlarge == 0xd) { ++ // is intel ralink, use a different edca value ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | (4 << 12) | (3 << 8) | 0x19); ++ priv->pshare->txop_enlarge = 2; ++ } ++ #endif ++#endif ++ else ++ { ++ if (pDM_Odm->RFType==ODM_2T2R) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | ++ (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); ++ else ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | ++ (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); ++ #else ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | ++ (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); ++ ++ #endif ++ } ++ } ++ else ++ { ++ #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); ++ #else ++ #if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP*2 << 16) | (cw_max << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); ++ #else ++ ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP*2 << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); ++ #endif ++ ++ #endif ++ } ++ ++ } ++} ++#endif ++ ++VOID ++odm_IotEngine( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++ struct rtl8192cd_priv *priv=pDM_Odm->priv; ++ PSTA_INFO_T pstat = NULL; ++ u4Byte i; ++ ++#ifdef WIFI_WMM ++ unsigned int switch_turbo = 0; ++#endif ++//////////////////////////////////////////////////////// ++// if EDCA Turbo function is not supported or Manual EDCA Setting ++// then return ++//////////////////////////////////////////////////////// ++ if(!(pDM_Odm->SupportAbility&ODM_MAC_EDCA_TURBO)){ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO NOT SUPPORTED\n")); ++ return; ++ } ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM)) ++ if(priv->pmib->dot11QosEntry.ManualEDCA){ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: MANUAL SETTING\n")); ++ return ; ++ } ++#endif ++ ++#if !(DM_ODM_SUPPORT_TYPE &ODM_AP) ++ ////////////////////////////////////////////////////// ++ //find high TP STA every 2s ++////////////////////////////////////////////////////// ++ if ((GET_ROOT(priv)->up_time % 2) == 0) ++ priv->pshare->highTP_found_pstat==NULL; ++ ++#if 0 ++ phead = &priv->asoc_list; ++ plist = phead->next; ++ while(plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ ++ if(ODM_ChooseIotMainSTA(pDM_Odm, pstat)); //find the correct station ++ break; ++ if (plist == plist->next) //the last plist ++ break; ++ plist = plist->next; ++ }; ++#endif ++ ++ //find highTP STA ++ for(i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pstat) && (ODM_ChooseIotMainSTA(pDM_Odm, pstat))) //find the correct station ++ break; ++ } ++ ++ ////////////////////////////////////////////////////// ++ //if highTP STA is not found, then return ++ ////////////////////////////////////////////////////// ++ if(priv->pshare->highTP_found_pstat==NULL) { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: NO HT STA FOUND\n")); ++ return; ++ } ++#endif ++ ++ pstat=priv->pshare->highTP_found_pstat; ++ ++ ++#ifdef WIFI_WMM ++ if (QOS_ENABLE) { ++ if (!priv->pmib->dot11OperationEntry.wifi_specific ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ ||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ || (priv->pmib->dot11OperationEntry.wifi_specific == 2) ++ #endif ++ ) { ++ if (priv->pshare->iot_mode_enable && ++ ((priv->pshare->phw->VO_pkt_count > 50) || ++ (priv->pshare->phw->VI_pkt_count > 50) || ++ (priv->pshare->phw->BK_pkt_count > 50))) { ++ priv->pshare->iot_mode_enable = 0; ++ switch_turbo++; ++ } else if ((!priv->pshare->iot_mode_enable) && ++ ((priv->pshare->phw->VO_pkt_count < 50) && ++ (priv->pshare->phw->VI_pkt_count < 50) && ++ (priv->pshare->phw->BK_pkt_count < 50))) { ++ priv->pshare->iot_mode_enable++; ++ switch_turbo++; ++ } ++ } ++ ++ ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) ++ #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ if (priv->pmib->dot11OperationEntry.wifi_specific) ++ #endif ++ { ++ if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) { ++ priv->pshare->iot_mode_VO_exist++; ++ switch_turbo++; ++ } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) { ++ priv->pshare->iot_mode_VO_exist = 0; ++ switch_turbo++; ++ } ++#if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI))) ++ if (priv->pshare->iot_mode_VO_exist) { ++ //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count); ++ if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) { ++ priv->pshare->iot_mode_BE_exist++; ++ switch_turbo++; ++ } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) { ++ priv->pshare->iot_mode_BE_exist = 0; ++ switch_turbo++; ++ } ++ } ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (priv->pshare->rf_ft_var.wifi_beq_iot) ++ { ++ if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) { ++ priv->pshare->iot_mode_VI_exist++; ++ switch_turbo++; ++ } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) { ++ priv->pshare->iot_mode_VI_exist = 0; ++ switch_turbo++; ++ } ++ } ++#endif ++ ++ } ++ else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) { ++ if (priv->pshare->txop_enlarge) { ++ priv->pshare->txop_enlarge = 0; ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++ } ++ ++#if(defined(CLIENT_MODE) && (DM_ODM_SUPPORT_TYPE==ODM_AP)) ++ if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ { ++ if (priv->pshare->iot_mode_enable && ++ (((priv->pshare->phw->VO_pkt_count > 50) || ++ (priv->pshare->phw->VI_pkt_count > 50) || ++ (priv->pshare->phw->BK_pkt_count > 50)) || ++ (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3])))) ++ { ++ priv->pshare->iot_mode_enable = 0; ++ switch_turbo++; ++ } ++ else if ((!priv->pshare->iot_mode_enable) && ++ (((priv->pshare->phw->VO_pkt_count < 50) && ++ (priv->pshare->phw->VI_pkt_count < 50) && ++ (priv->pshare->phw->BK_pkt_count < 50)) && ++ (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3])))) ++ { ++ priv->pshare->iot_mode_enable++; ++ switch_turbo++; ++ } ++ } ++#endif ++ ++ priv->pshare->phw->VO_pkt_count = 0; ++ priv->pshare->phw->VI_pkt_count = 0; ++ priv->pshare->phw->BK_pkt_count = 0; ++ ++ #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI))) ++ priv->pshare->phw->BE_pkt_count = 0; ++ #endif ++ ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (priv->pshare->rf_ft_var.wifi_beq_iot) ++ priv->pshare->phw->VI_rx_pkt_count = 0; ++ #endif ++ ++ } ++#endif ++ ++ if ((priv->up_time % 2) == 0) { ++ /* ++ * decide EDCA content for different chip vendor ++ */ ++#ifdef WIFI_WMM ++ #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL) ++ if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2) ++ ++ #elif(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || ++ ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ #ifdef CLIENT_MODE ++ || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ #endif ++ #endif ++ )) ++ ++ { ++ ++ if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) { ++#ifdef LOW_TP_TXOP ++#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) ++ if (pstat->IOTPeer==HT_IOT_PEER_INTEL) ++#else ++ if (pstat->is_intel_sta) ++#endif ++ { ++ if (priv->pshare->txop_enlarge != 0xe) ++ { ++ priv->pshare->txop_enlarge = 0xe; ++ ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++ } ++ else if (priv->pshare->txop_enlarge != 2) ++ { ++ priv->pshare->txop_enlarge = 2; ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++#else ++ if (priv->pshare->txop_enlarge != 2) ++ { ++#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) ++ if (pstat->IOTPeer==HT_IOT_PEER_INTEL) ++#else ++ if (pstat->is_intel_sta) ++#endif ++ priv->pshare->txop_enlarge = 0xe; ++#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) ++ else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) ++#else ++ else if (pstat->is_ralink_sta) ++#endif ++ priv->pshare->txop_enlarge = 0xd; ++ else ++ priv->pshare->txop_enlarge = 2; ++ ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++#endif ++#if 0 ++ if (priv->pshare->txop_enlarge != 2) ++ { ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if (pstat->IOTPeer==HT_IOT_PEER_INTEL) ++ #else ++ if (pstat->is_intel_sta) ++ #endif ++ priv->pshare->txop_enlarge = 0xe; ++ #if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++ else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) ++ priv->pshare->txop_enlarge = 0xd; ++ #endif ++ else ++ priv->pshare->txop_enlarge = 2; ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++#endif ++ } ++ else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) ++ { ++ if (priv->pshare->txop_enlarge) { ++ priv->pshare->txop_enlarge = 0; ++ if (priv->pshare->iot_mode_enable) ++ switch_turbo++; ++ } ++ } ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&( defined LOW_TP_TXOP)) ++ // for Intel IOT, need to enlarge CW MAX from 6 to 10 ++ if (pstat && pstat->is_intel_sta && (((pstat->tx_avarage+pstat->rx_avarage)>>10) < ++ priv->pshare->rf_ft_var.cwmax_enhance_thd)) ++ { ++ if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable) ++ { ++ priv->pshare->BE_cwmax_enhance = 1; ++ switch_turbo++; ++ } ++ } else { ++ if (priv->pshare->BE_cwmax_enhance) { ++ priv->pshare->BE_cwmax_enhance = 0; ++ switch_turbo++; ++ } ++ } ++#endif ++ } ++#endif ++ priv->pshare->current_tx_bytes = 0; ++ priv->pshare->current_rx_bytes = 0; ++ } ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined( SW_TX_QUEUE)) ++ if ((priv->assoc_num > 1) && (AMPDU_ENABLE)) ++ { ++ if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd){ ++ if ((priv->swq_en == 0)){ ++ switch_turbo++; ++ if (priv->pshare->txop_enlarge == 0) ++ priv->pshare->txop_enlarge = 2; ++ priv->swq_en = 1; ++ } ++ else ++ { ++ if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) ++ { ++ priv->pshare->txop_enlarge = 2; ++ switch_turbo--; ++ } ++ } ++ } ++ else if(priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd){ ++ priv->swq_en = 0; ++ } ++ else if ((priv->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) { ++ priv->pshare->txop_enlarge = 2; ++ switch_turbo--; ++ } ++ } ++#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined CONFIG_RTL_819XD)) ++ else if( (priv->assoc_num == 1) && (AMPDU_ENABLE)) { ++ if (pstat) { ++ int en_thd = 14417920>>(priv->up_time % 2); ++ if ((priv->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) ) { //50Mbps ++ priv->swq_en = 1; ++ priv->swqen_keeptime = priv->up_time; ++ } ++ else if ((priv->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps ++ priv->swq_en = 0; ++ priv->swqen_keeptime = 0; ++ } ++ } ++ else { ++ priv->swq_en = 0; ++ priv->swqen_keeptime = 0; ++ } ++ } ++#endif ++#endif ++ ++#ifdef WIFI_WMM ++#ifdef LOW_TP_TXOP ++ if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)) ++ && QOS_ENABLE) { ++ if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) { ++ unsigned int thd_tp; ++ unsigned char under_thd; ++ unsigned int curr_tp; ++ ++ if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G)) ++ { ++ // Determine the upper bound throughput threshold. ++ if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G)) { ++ if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num) ++ thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; ++ else ++ thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n; ++ } ++ else ++ thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; ++ ++ // Determine to close txop. ++ curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); ++ if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low) ++ under_thd = 1; ++ else ++ under_thd = 0; ++ } ++ else ++ { ++ under_thd = 0; ++ } ++ ++ if (switch_turbo) ++ { ++ priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; ++ priv->pshare->rf_ft_var.low_tp_txop_count = 0; ++ } ++ else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) { ++ priv->pshare->rf_ft_var.low_tp_txop_count++; ++ if (priv->pshare->rf_ft_var.low_tp_txop_close) { ++ priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;; ++ } ++ if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay) ++ ++ { ++ priv->pshare->rf_ft_var.low_tp_txop_count = 0; ++ priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; ++ switch_turbo++; ++ } ++ } ++ else ++ { ++ priv->pshare->rf_ft_var.low_tp_txop_count = 0; ++ } ++ } ++ } ++#endif ++ ++ if (switch_turbo) ++ ODM_IotEdcaSwitch( pDM_Odm, priv->pshare->iot_mode_enable ); ++#endif ++} ++#endif ++ ++ ++#if( DM_ODM_SUPPORT_TYPE == ODM_MP) ++// ++// 2011/07/26 MH Add an API for testing IQK fail case. ++// ++BOOLEAN ++ODM_CheckPowerStatus( ++ IN PADAPTER Adapter) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ RT_RF_POWER_STATE rtState; ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ ++ // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. ++ if (pMgntInfo->init_adpt_in_progress == TRUE) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); ++ return TRUE; ++ } ++ ++ // ++ // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. ++ // ++ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); ++ if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", ++ Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); ++ return FALSE; ++ } ++ return TRUE; ++} ++#endif ++ ++// need to ODM CE Platform ++//move to here for ANT detection mechanism using ++ ++#if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++u4Byte ++GetPSDData( ++ IN PDM_ODM_T pDM_Odm, ++ unsigned int point, ++ u1Byte initial_gain_psd) ++{ ++ //unsigned int val, rfval; ++ //int psd_report; ++ u4Byte psd_report; ++ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //Debug Message ++ //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); ++ //DbgPrint("Reg908 = 0x%x\n",val); ++ //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); ++ //rfval = PHY_QueryRFReg(Adapter, RF_PATH_A, 0x00, bRFRegOffsetMask); ++ //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); ++ //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", ++ //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); ++ ++ //Set DCO frequency index, offset=(40MHz/SamplePts)*point ++ ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); ++ ++ //Start PSD calculation, Reg808[22]=0->1 ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); ++ //Need to wait for HW PSD report ++ ODM_StallExecution(30); ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); ++ //Read PSD report, Reg8B4[15:0] ++ psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; ++ ++#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) ++ psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); ++#else ++ psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); ++#endif ++ ++ return psd_report; ++ ++} ++ ++u4Byte ++ConvertTo_dB( ++ u4Byte Value) ++{ ++ u1Byte i; ++ u1Byte j; ++ u4Byte dB; ++ ++ Value = Value & 0xFFFF; ++ ++ for (i=0;i<8;i++) ++ { ++ if (Value <= dB_Invert_Table[i][11]) ++ { ++ break; ++ } ++ } ++ ++ if (i >= 8) ++ { ++ return (96); // maximum 96 dB ++ } ++ ++ for (j=0;j<12;j++) ++ { ++ if (Value <= dB_Invert_Table[i][j]) ++ { ++ break; ++ } ++ } ++ ++ dB = i*12 + j + 1; ++ ++ return (dB); ++} ++ ++#endif ++ ++// ++// LukeLee: ++// PSD function will be moved to FW in future IC, but now is only implemented in MP platform ++// So PSD function will not be incorporated to common ODM ++// ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD ++#define MODE_40M 0 //0:20M, 1:40M ++#define PSD_TH2 3 ++#define PSD_CHMIN 20 // Minimum channel number for BT AFH ++#define SIR_STEP_SIZE 3 ++#define Smooth_Size_1 5 ++#define Smooth_TH_1 3 ++#define Smooth_Size_2 10 ++#define Smooth_TH_2 4 ++#define Smooth_Size_3 20 ++#define Smooth_TH_3 4 ++#define Smooth_Step_Size 5 ++#define Adaptive_SIR 1 ++//#if(RTL8723_FPGA_VERIFICATION == 1) ++//#define PSD_RESCAN 1 ++//#else ++//#define PSD_RESCAN 4 ++//#endif ++#define SCAN_INTERVAL 700 //ms ++#define SYN_Length 5 // for 92D ++ ++#define LNA_Low_Gain_1 0x64 ++#define LNA_Low_Gain_2 0x5A ++#define LNA_Low_Gain_3 0x58 ++ ++#define pw_th_10dB 0x0 ++#define pw_th_16dB 0x3 ++ ++#define FA_RXHP_TH1 5000 ++#define FA_RXHP_TH2 1500 ++#define FA_RXHP_TH3 800 ++#define FA_RXHP_TH4 600 ++#define FA_RXHP_TH5 500 ++ ++#define Idle_Mode 0 ++#define High_TP_Mode 1 ++#define Low_TP_Mode 2 ++ ++ ++VOID ++odm_PSDMonitorInit( ++ IN PDM_ODM_T pDM_Odm) ++{ ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PSD Monitor Setting ++ //Which path in ADC/DAC is turnned on for PSD: both I/Q ++ ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3); ++ //Ageraged number: 8 ++ ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1); ++ pDM_Odm->bPSDinProcess = FALSE; ++ pDM_Odm->bUserAssignLevel = FALSE; ++ ++ //pDM_Odm->bDMInitialGainEnable=TRUE; //change the initialization to DIGinit ++ //Set Debug Port ++ //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803); ++ //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD ++ //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan ++ //PHY_SetBBReg(Adapter, 0xB38, bMaskByte1, 0x32); // PSDDelay ++ //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval ++ ++ //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms ++#endif ++} ++ ++VOID ++PatchDCTone( ++ IN PDM_ODM_T pDM_Odm, ++ pu4Byte PSD_report, ++ u1Byte initial_gain_psd ++) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PADAPTER pAdapter; ++ ++ u4Byte psd_report; ++ ++ //2 Switch to CH11 to patch CH9 and CH13 DC tone ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 11); ++ ++ if(pDM_Odm->SupportICType== ODM_RTL8192D) ++ { ++ if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 11); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, 0xfffff, 0x643BC); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, 0xfffff, 0xFC038); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x77C1A); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, 0xfffff, 0x41289); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, 0xfffff, 0x01840); ++ } ++ else ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, 0xfffff, 0x643BC); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, 0xfffff, 0xFC038); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x77C1A); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, 0xfffff, 0x41289); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, 0xfffff, 0x01840); ++ } ++ } ++ ++ //Ch9 DC tone patch ++ psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); ++ PSD_report[50] = psd_report; ++ //Ch13 DC tone patch ++ psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); ++ PSD_report[70] = psd_report; ++ ++ //2 Switch to CH3 to patch CH1 and CH5 DC tone ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 3); ++ ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8192D) ++ { ++ if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 3); ++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, 0xfffff, 0x643BC); ++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, 0xfffff, 0xFC038); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x07C1A); ++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, 0xfffff, 0x61289); ++ //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, 0xfffff, 0x01C41); ++ } ++ else ++ { ++ //PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, 0xfffff, 0x643BC); ++ //PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, 0xfffff, 0xFC038); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x07C1A); ++ //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, 0xfffff, 0x61289); ++ //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, 0xfffff, 0x01C41); ++ } ++ } ++ ++ //Ch1 DC tone patch ++ psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); ++ PSD_report[10] = psd_report; ++ //Ch5 DC tone patch ++ psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); ++ PSD_report[30] = psd_report; ++ ++} ++ ++ ++VOID ++GoodChannelDecision( ++ PDM_ODM_T pDM_Odm, ++ ps4Byte PSD_report, ++ pu1Byte PSD_bitmap, ++ u1Byte RSSI_BT, ++ pu1Byte PSD_bitmap_memory) ++{ ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ //s4Byte TH1 = SSBT-0x15; // modify TH by Neil Chen ++ s4Byte TH1= RSSI_BT+0x14; ++ s4Byte TH2 = RSSI_BT+85; ++ //u2Byte TH3; ++// s4Byte RegB34; ++ u1Byte bitmap, Smooth_size[3], Smooth_TH[3]; ++ //u1Byte psd_bit; ++ u4Byte i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3]; ++ int start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ; ++ ++// RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF; ++ ++ if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D)) ++ { ++ TH1 = RSSI_BT + 0x14; ++ } ++ ++ Smooth_size[0]=Smooth_Size_1; ++ Smooth_size[1]=Smooth_Size_2; ++ Smooth_size[2]=Smooth_Size_3; ++ Smooth_TH[0]=Smooth_TH_1; ++ Smooth_TH[1]=Smooth_TH_2; ++ Smooth_TH[2]=Smooth_TH_3; ++ Smooth_Interval[0]=16; ++ Smooth_Interval[1]=15; ++ Smooth_Interval[2]=13; ++ good_cnt = 0; ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ //2 Threshold ++ ++ if(RSSI_BT >=41) ++ TH1 = 113; ++ else if(RSSI_BT >=38) // >= -15dBm ++ TH1 = 105; //0x69 ++ else if((RSSI_BT >=33)&(RSSI_BT <38)) ++ TH1 = 99+(RSSI_BT-33); //0x63 ++ else if((RSSI_BT >=26)&(RSSI_BT<33)) ++ TH1 = 99-(33-RSSI_BT)+2; //0x5e ++ else if((RSSI_BT >=24)&(RSSI_BT<26)) ++ TH1 = 88-((RSSI_BT-24)*3); //0x58 ++ else if((RSSI_BT >=18)&(RSSI_BT<24)) ++ TH1 = 77+((RSSI_BT-18)*2); ++ else if((RSSI_BT >=14)&(RSSI_BT<18)) ++ TH1 = 63+((RSSI_BT-14)*2); ++ else if((RSSI_BT >=8)&(RSSI_BT<14)) ++ TH1 = 58+((RSSI_BT-8)*2); ++ else if((RSSI_BT >=3)&(RSSI_BT<8)) ++ TH1 = 52+(RSSI_BT-3); ++ else ++ TH1 = 51; ++ } ++ ++ for (i = 0; i< 10; i++) ++ PSD_bitmap[i] = 0; ++ ++ ++ // Add By Gary ++ for (i=0; i<80; i++) ++ pRX_HP_Table->PSD_bitmap_RXHP[i] = 0; ++ // End ++ ++ ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ TH1 =TH1-SIR_STEP_SIZE; ++ } ++ while (good_cnt < PSD_CHMIN) ++ { ++ good_cnt = 0; ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ if(TH1 ==TH2) ++ break; ++ if((TH1+SIR_STEP_SIZE) < TH2) ++ TH1 += SIR_STEP_SIZE; ++ else ++ TH1 = TH2; ++ } ++ else ++ { ++ if(TH1==(RSSI_BT+0x1E)) ++ break; ++ if((TH1+2) < (RSSI_BT+0x1E)) ++ TH1+=3; ++ else ++ TH1 = RSSI_BT+0x1E; ++ ++ } ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1)); ++ ++ for (i = 0; i< 80; i++) ++ { ++ if(PSD_report[i] < TH1) ++ { ++ byte_idx = i / 8; ++ bit_idx = i -8*byte_idx; ++ bitmap = PSD_bitmap[byte_idx]; ++ PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx); ++ } ++ } ++ ++#if DBG ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: before smoothing\n")); ++ for(n=0;n<10;n++) ++ { ++ //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]); ++ for (i = 0; i<8; i++) ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); ++ } ++#endif ++ ++ //1 Start of smoothing function ++ ++ for (j=0;j<3;j++) ++ { ++ start_byte_idx=0; ++ start_bit_idx=0; ++ for(n=0; n 7 ) ++ { ++ start_byte_idx= start_byte_idx+start_bit_idx/8; ++ start_bit_idx = start_bit_idx%8; ++ } ++ } ++ ++ ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1)); ++ for(n=0;n<10;n++) ++ { ++ for (i = 0; i<8; i++) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); ++ ++ if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1) //----- Add By Gary ++ { ++ pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1; ++ } // ------end by Gary ++ } ++ } ++ ++ } ++ ++ ++ good_cnt = 0; ++ for ( i = 0; i < 10; i++) ++ { ++ for (n = 0; n < 8; n++) ++ if((PSD_bitmap[i]& BIT(n)) != 0) ++ good_cnt++; ++ } ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: good channel cnt = %u",good_cnt)); ++ } ++ ++ //RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1)); ++ for (i = 0; i <10; i++) ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i])); ++/* ++ //Update bitmap memory ++ for(i = 0; i < 80; i++) ++ { ++ byte_idx = i / 8; ++ bit_idx = i -8*byte_idx; ++ psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx; ++ bitmap = PSD_bitmap_memory[i]; ++ PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit; ++ } ++*/ ++} ++ ++ ++ ++VOID ++odm_PSD_Monitor( ++ PDM_ODM_T pDM_Odm ++) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ ++ unsigned int pts, start_point, stop_point, initial_gain ; ++ static u1Byte PSD_bitmap_memory[80], init_memory = 0; ++ static u1Byte psd_cnt=0; ++ static u4Byte PSD_report[80], PSD_report_tmp; ++ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ u1Byte H2C_PSD_DATA[5]={0,0,0,0,0}; ++ static u1Byte H2C_PSD_DATA_last[5] ={0,0,0,0,0}; ++ u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, ++ 0,3,6,10,13,16,19,22,26,29}; ++ u1Byte n, i, channel, BBReset,tone_idx; ++ u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; ++ s4Byte PSD_skip_start, PSD_skip_stop; ++ u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; ++ u4Byte ReScan, Interval, Is40MHz; ++ u8Byte curTxOkCnt, curRxOkCnt; ++ int cur_byte_idx, cur_bit_idx; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ //--------------2G band synthesizer for 92D switch RF channel using----------------- ++ u1Byte group_idx=0; ++ u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0; ++ u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel ++ u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840} ++ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14 ++ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8 ++ //--------------------- Add by Gary for Debug setting ---------------------- ++ s4Byte psd_result = 0; ++ u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF); ++ u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF); ++ //--------------------------------------------------------------------- ++ ++ if(*(pDM_Odm->pbScanInProcess)) ++ { ++ if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) ++ { ++ //pHalData->bPSDactive=FALSE; ++ //ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ) ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 900); //ms ++ //psd_cnt=0; ++ } ++ return; ++ } ++ ++ ReScan = PSD_RESCAN; ++ Interval = SCAN_INTERVAL; ++ ++ ++ //1 Initialization ++ if(init_memory == 0) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Init memory\n")); ++ for(i = 0; i < 80; i++) ++ PSD_bitmap_memory[i] = 0xFF; // channel is always good ++ init_memory = 1; ++ } ++ if(psd_cnt == 0) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); ++ for(i = 0; i < 80; i++) ++ PSD_report[i] = 0; ++ } ++#if 0 //for test only ++ DbgPrint("cosa odm_PSD_Monitor call()\n"); ++ DbgPrint("cosa pHalData->RSSI_BT = %d\n", pHalData->RSSI_BT); ++ DbgPrint("cosa pHalData->bUserAssignLevel = %d\n", pHalData->bUserAssignLevel); ++#if 0 ++ psd_cnt++; ++ if (psd_cnt < ReScan) ++ PlatformSetTimer( Adapter, &pHalData->PSDTimer, Interval); //ms ++ else ++ psd_cnt = 0; ++ return; ++#endif ++#endif ++ //1 Backup Current Settings ++ CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); ++/* ++ if(pDM_Odm->SupportICType==ODM_RTL8192D) ++ { ++ //2 Record Current synthesizer parameters based on current channel ++ if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY)) ++ { ++ SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord); ++ SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord); ++ SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord); ++ SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord); ++ SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord); ++ } ++ else // DualMAC_DualPHY 2G ++ { ++ SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord); ++ SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord); ++ SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord); ++ SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord); ++ SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord); ++ } ++ } ++*/ ++ //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord); ++ RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); ++ ++ //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28; ++ RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; ++ ++ //2??? ++ Is40MHz = pMgntInfo->pHTInfo->bCurBW40MHz; ++ ++ ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); ++ //1 Turn off CCK ++ //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); ++ //1 Turn off TX ++ //Pause TX Queue ++ //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF); ++ ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF); ++ ++ //Force RX to stop TX immediately ++ //PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); ++ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); ++ //1 Turn off RX ++ //Rx AGC off RegC70[0]=0, RegC7C[20]=0 ++ //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0); ++ //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0); ++ ++ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); ++ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); ++ ++ ++ //Turn off CCA ++ //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0); ++ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); ++ ++ //BB Reset ++ //BBReset = PlatformEFIORead1Byte(Adapter, 0x02); ++ BBReset = ODM_Read1Byte(pDM_Odm, 0x02); ++ ++ //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0)); ++ //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0); ++ ++ ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); ++ ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); ++ ++ //1 Leave RX idle low power ++ //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0); ++ ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); ++ //1 Fix initial gain ++ //if (IS_HARDWARE_TYPE_8723AE(Adapter)) ++ //RSSI_BT = pHalData->RSSI_BT; ++ //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary ++ // RSSI_BT = RSSI_BT_new; ++ ++ if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) ++ RSSI_BT=pDM_Odm->RSSI_BT; //need to check C2H to pDM_Odm RSSI BT ++ ++ else if((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D)) ++ RSSI_BT = RSSI_BT_new; ++ ++ ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ //Neil add--2011--10--12 ++ //2 Initial Gain index ++ if(RSSI_BT >=35) // >= -15dBm ++ initial_gain_psd = RSSI_BT*2; ++ else if((RSSI_BT >=33)&(RSSI_BT<35)) ++ initial_gain_psd = RSSI_BT*2+6; ++ else if((RSSI_BT >=24)&(RSSI_BT<33)) ++ initial_gain_psd = 70-(31-RSSI_BT); ++ else if((RSSI_BT >=19)&(RSSI_BT<24)) ++ initial_gain_psd = 64-((24-RSSI_BT)*4); ++ else if((RSSI_BT >=14)&(RSSI_BT<19)) ++ initial_gain_psd = 44-((18-RSSI_BT)*2); ++ else if((RSSI_BT >=8)&(RSSI_BT<14)) ++ initial_gain_psd = 35-(14-RSSI_BT); ++ else ++ initial_gain_psd = 0x1B; ++ } ++ else ++ { ++ if(rssi_ctrl == 1) // just for debug!! ++ initial_gain_psd = RSSI_BT_new ; ++ else ++ { ++ //need to do ++ initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI ++ } ++ } ++ //if(RSSI_BT<0x17) ++ // RSSI_BT +=3; ++ //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT); ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); ++ ++ //initialGainUpper = 0x5E; //Modify by neil chen ++ ++ if(pDM_Odm->bUserAssignLevel) ++ { ++ pDM_Odm->bUserAssignLevel = FALSE; ++ initialGainUpper = 0x7f; ++ } ++ else ++ { ++ initialGainUpper = 0x5E; ++ } ++ ++ /* ++ if (initial_gain_psd < 0x1a) ++ initial_gain_psd = 0x1a; ++ if (initial_gain_psd > initialGainUpper) ++ initial_gain_psd = initialGainUpper; ++ */ ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ SSBT = RSSI_BT * 2 +0x3E; ++ else if((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D)) ++ { ++ RSSI_BT = initial_gain_psd; ++ SSBT = RSSI_BT; ++ } ++ ++ //if(IS_HARDWARE_TYPE_8723AE(Adapter)) ++ // SSBT = RSSI_BT * 2 +0x3E; ++ //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary ++ //{ ++ // RSSI_BT = initial_gain_psd; ++ // SSBT = RSSI_BT; ++ //} ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); ++ ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); ++ //DbgPrint("PSD: SSBT= %d", SSBT); ++ //need to do ++ //pMgntInfo->bDMInitialGainEnable = FALSE; ++ pDM_Odm->bDMInitialGainEnable = FALSE; ++ initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F; ++ ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); ++ //1 Turn off 3-wire ++ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); ++ ++ //pts value = 128, 256, 512, 1024 ++ pts = 128; ++ ++ if(pts == 128) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); ++ start_point = 64; ++ stop_point = 192; ++ } ++ else if(pts == 256) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); ++ start_point = 128; ++ stop_point = 384; ++ } ++ else if(pts == 512) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); ++ start_point = 256; ++ stop_point = 768; ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); ++ start_point = 512; ++ stop_point = 1536; ++ } ++ ++ ++//3 Skip WLAN channels if WLAN busy ++ ++ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; ++ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; ++ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); ++ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); ++ ++ PSD_skip_start=80; ++ PSD_skip_stop = 0; ++ wlan_channel = CurrentChannel & 0x0f; ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtHsOperation) ++ { ++ if(pDM_Odm->bLinked) ++ { ++ if(Is40MHz) ++ { ++ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask ++ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; ++ } ++ else ++ { ++ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask ++ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; ++ } ++ } ++ else ++ { ++ // mask for 40MHz ++ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask ++ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; ++ } ++ if(PSD_skip_start < 0) ++ PSD_skip_start = 0; ++ if(PSD_skip_stop >80) ++ PSD_skip_stop = 80; ++ } ++ else ++#endif ++ { ++ if((curRxOkCnt+curTxOkCnt) > 5) ++ { ++ if(Is40MHz) ++ { ++ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask ++ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; ++ } ++ else ++ { ++ PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask ++ PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; ++ } ++ ++ if(PSD_skip_start < 0) ++ PSD_skip_start = 0; ++ if(PSD_skip_stop >80) ++ PSD_skip_stop = 80; ++ } ++ } ++ } ++ else ++ { ++ if((curRxOkCnt+curTxOkCnt) > 1000) ++ { ++ PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; ++ PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; ++ } ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); ++ ++ for (n=0;n<80;n++) ++ { ++ if((n%20)==0) ++ { ++ channel = (n/20)*4 + 1; ++ /* ++ if(pDM_Odm->SupportICType==ODM_RTL8192D) ++ { ++ switch(channel) ++ { ++ case 1: ++ case 9: ++ group_idx = 0; ++ break; ++ case 5: ++ group_idx = 2; ++ break; ++ case 13: ++ group_idx = 1; ++ break; ++ } ++ ++ if((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)) ++ { ++ for(i = 0; i < SYN_Length; i++) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]); ++ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel); ++ } ++ else // DualMAC_DualPHY 2G ++ { ++ for(i = 0; i < SYN_Length; i++) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); ++ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ } ++ } ++ else */ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ } ++ tone_idx = n%20; ++ if ((n>=PSD_skip_start) && (n PSD_report[n]) ++ PSD_report[n] = PSD_report_tmp; ++ ++ } ++ } ++ ++ PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); ++ ++ //----end ++ //1 Turn on RX ++ //Rx AGC on ++ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); ++ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); ++ //CCK on ++ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); ++ //1 Turn on TX ++ //Resume TX Queue ++ ++ ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00); ++ //Turn on 3-wire ++ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); ++ //1 Restore Current Settings ++ //Resume DIG ++ pDM_Odm->bDMInitialGainEnable = TRUE; ++ ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain); ++ // restore originl center frequency ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); ++ ++ /* ++ if(pDM_Odm->SupportICType==ODM_RTL8192D) ++ { ++ if((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)) ++ { ++ PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel); ++ PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25); ++ PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26); ++ PHY_SetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27); ++ PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B); ++ PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C); ++ } ++ else // DualMAC_DualPHY ++ { ++ PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25); ++ PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26); ++ PHY_SetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27); ++ PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B); ++ PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C); ++ } ++ }*/ ++ //Turn on CCA ++ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); ++ //Restore RX idle low power ++ if(RxIdleLowPwr == TRUE) ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); ++ ++ psd_cnt++; ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); ++ if (psd_cnt < ReScan) ++ ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval); ++ else ++ { ++ psd_cnt = 0; ++ for(i=0;i<80;i++) ++ //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); ++ RT_TRACE( COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); ++ ++ ++ GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); ++ ++ if(pDM_Odm->SupportICType==ODM_RTL8723A) ++ { ++ cur_byte_idx=0; ++ cur_bit_idx=0; ++ ++ //2 Restore H2C PSD Data to Last Data ++ H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0]; ++ H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1]; ++ H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2]; ++ H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3]; ++ H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4]; ++ ++ ++ //2 Translate 80bit channel map to 40bit channel ++ for ( i=0;i<5;i++) ++ { ++ for(n=0;n<8;n++) ++ { ++ cur_byte_idx = i*2 + n/4; ++ cur_bit_idx = (n%4)*2; ++ if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0)) ++ H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n); ++ } ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i])); ++ } ++ ++ //3 To Compare the difference ++ for ( i=0;i<5;i++) ++ { ++ if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i]) ++ { ++ FillH2CCmd(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA); ++ ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n")); ++ break; ++ } ++ else ++ { ++ if(i==5) ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Not need to Update\n")); ++ } ++ } ++ //pHalData->bPSDactive=FALSE; ++ ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 900); ++ ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); ++ } ++ } ++} ++/* ++//Neil for Get BT RSSI ++// Be Triggered by BT C2H CMD ++VOID ++ODM_PSDGetRSSI( ++ IN u1Byte RSSI_BT) ++{ ++ ++ ++} ++ ++*/ ++ ++VOID ++ODM_PSDMonitor( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //if(IS_HARDWARE_TYPE_8723AE(Adapter)) ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) //may need to add other IC type ++ { ++ if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) ++ { ++#if(BT_30_SUPPORT == 1) ++ if(pDM_Odm->bBtDisabled) //need to check upper layer connection ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n")); ++ return; ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n")); ++ //if(pHalData->bPSDactive ==FALSE) ++ //{ ++ pDM_Odm->bPSDinProcess = TRUE; ++ //pHalData->bPSDactive=TRUE; ++ odm_PSD_Monitor(pDM_Odm); ++ pDM_Odm->bPSDinProcess = FALSE; ++ } ++ } ++ ++} ++VOID ++odm_PSDMonitorCallback( ++ PRT_TIMER pTimer ++) ++{ ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ ++#if USE_WORKITEM ++ PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem); ++#else ++ ODM_PSDMonitor(pDM_Odm); ++#endif ++} ++ ++VOID ++odm_PSDMonitorWorkItemCallback( ++ IN PVOID pContext ++ ) ++{ ++ PADAPTER Adapter = (PADAPTER)pContext; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ ++ ODM_PSDMonitor(pDM_Odm); ++} ++ ++ ++ ++ //cosa debug tool need to modify ++ ++VOID ++ODM_PSDDbgControl( ++ IN PADAPTER Adapter, ++ IN u4Byte mode, ++ IN u4Byte btRssi ++ ) ++{ ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi)); ++ if(mode) ++ { ++ pDM_Odm->RSSI_BT = (u1Byte)btRssi; ++ pDM_Odm->bUserAssignLevel = TRUE; ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms ++ } ++ else ++ { ++ ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); ++ } ++#endif ++} ++ ++ ++//#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ ++void odm_RXHPInit( ++ IN PDM_ODM_T pDM_Odm) ++{ ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ u1Byte index; ++ ++ pRX_HP_Table->RXHP_enable = TRUE; ++ pRX_HP_Table->RXHP_flag = 0; ++ pRX_HP_Table->PSD_func_trigger = 0; ++ pRX_HP_Table->Pre_IGI = 0x20; ++ pRX_HP_Table->Cur_IGI = 0x20; ++ pRX_HP_Table->Cur_pw_th = pw_th_10dB; ++ pRX_HP_Table->Pre_pw_th = pw_th_10dB; ++ for(index=0; index<80; index++) ++ pRX_HP_Table->PSD_bitmap_RXHP[index] = 1; ++ ++#if(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ pRX_HP_Table->TP_Mode = Idle_Mode; ++#endif ++#endif ++} ++ ++void odm_RXHP( ++ IN PDM_ODM_T pDM_Odm) ++{ ++#if( DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); ++ ++ u1Byte i, j, sum; ++ u1Byte Is40MHz; ++ s1Byte Intf_diff_idx, MIN_Intf_diff_idx = 16; ++ s4Byte cur_channel; ++ u1Byte ch_map_intf_5M[17] = {0}; ++ static u4Byte FA_TH = 0; ++ static u1Byte psd_intf_flag = 0; ++ static s4Byte curRssi = 0; ++ static s4Byte preRssi = 0; ++ static u1Byte PSDTriggerCnt = 1; ++ ++ u1Byte RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31); // for debug!! ++ ++#if(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ static s8Byte lastTxOkCnt = 0, lastRxOkCnt = 0; ++ s8Byte curTxOkCnt, curRxOkCnt; ++ s8Byte curTPOkCnt; ++ s8Byte TP_Acc3, TP_Acc5; ++ static s8Byte TP_Buff[5] = {0}; ++ static u1Byte pre_state = 0, pre_state_flag = 0; ++ static u1Byte Intf_HighTP_flag = 0, De_counter = 16; ++ static u1Byte TP_Degrade_flag = 0; ++#endif ++ static u1Byte LatchCnt = 0; ++ ++ if((pDM_Odm->SupportICType == ODM_RTL8723A)||(pDM_Odm->SupportICType == ODM_RTL8188E)) ++ return; ++ //AGC RX High Power Mode is only applied on 2G band in 92D!!! ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G) ++ return; ++ } ++ ++ if(!(pDM_Odm->SupportAbility==ODM_BB_RXHP)) ++ return; ++ ++ ++ //RX HP ON/OFF ++ if(RX_HP_enable == 1) ++ pRX_HP_Table->RXHP_enable = FALSE; ++ else ++ pRX_HP_Table->RXHP_enable = TRUE; ++ ++ if(pRX_HP_Table->RXHP_enable == FALSE) ++ { ++ if(pRX_HP_Table->RXHP_flag == 1) ++ { ++ pRX_HP_Table->RXHP_flag = 0; ++ psd_intf_flag = 0; ++ } ++ return; ++ } ++ ++#if(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ //2 Record current TP for USB interface ++ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; ++ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; ++ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); ++ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); ++ ++ curTPOkCnt = curTxOkCnt+curRxOkCnt; ++ TP_Buff[0] = curTPOkCnt; // current TP ++ TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3); ++ TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5); ++ ++ if(TP_Acc5 < 1000) ++ pRX_HP_Table->TP_Mode = Idle_Mode; ++ else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000)) ++ pRX_HP_Table->TP_Mode = Low_TP_Mode; ++ else ++ pRX_HP_Table->TP_Mode = High_TP_Mode; ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode)); ++ // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing. ++ // When LatchCnt = 0, we would Get PSD result. ++ if(TP_Degrade_flag == 1) ++ { ++ LatchCnt--; ++ if(LatchCnt == 0) ++ { ++ TP_Degrade_flag = 0; ++ } ++ } ++ // When PSD function triggered by TP degrade 20%, and Interference Flag = 1 ++ // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down. ++ if(Intf_HighTP_flag == 1) ++ { ++ De_counter--; ++ if(De_counter == 0) ++ { ++ Intf_HighTP_flag = 0; ++ psd_intf_flag = 0; ++ } ++ } ++#endif ++ ++ //2 AGC RX High Power Mode by PSD only applied to STA Mode ++ //3 NOT applied 1. Ad Hoc Mode. ++ //3 NOT applied 2. AP Mode ++ if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter))) ++ { ++ Is40MHz = *(pDM_Odm->pBandWidth); ++ curRssi = pDM_Odm->RSSI_Min; ++ cur_channel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz)); ++ //2 PSD function would be triggered ++ //3 1. Every 4 sec for PCIE ++ //3 2. Before TP Mode (Idle TP<4kbps) for USB ++ //3 3. After TP Mode (High TP) for USB ++ if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0)) // Only RSSI>TH and RX_HP_flag=0 will Do PSD process ++ { ++#if (DEV_BUS_TYPE == RT_USB_INTERFACE) ++ //2 Before TP Mode ==> PSD would be trigger every 4 sec ++ if(pRX_HP_Table->TP_Mode == Idle_Mode) //2.1 less wlan traffic <4kbps ++ { ++#endif ++ if(PSDTriggerCnt == 1) ++ { ++ odm_PSD_RXHP(pDM_Odm); ++ pRX_HP_Table->PSD_func_trigger = 1; ++ PSDTriggerCnt = 0; ++ } ++ else ++ { ++ PSDTriggerCnt++; ++ } ++#if(DEV_BUS_TYPE == RT_USB_INTERFACE) ++ } ++ //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function ++ if(pRX_HP_Table->TP_Mode == High_TP_Mode) ++ { ++ if((pre_state_flag == 0)&&(LatchCnt == 0)) ++ { ++ // TP var < 5% ++ if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3))) ++ { ++ pre_state++; ++ if(pre_state == 3) // hit pre_state condition => consecutive 3 times ++ { ++ pre_state_flag = 1; ++ pre_state = 0; ++ } ++ ++ } ++ else ++ { ++ pre_state = 0; ++ } ++ } ++ //3 If pre_state_flag=1 ==> start to monitor TP degrade 20% ++ if(pre_state_flag == 1) ++ { ++ if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3)) // degrade 20% ++ { ++ odm_PSD_RXHP(pDM_Odm); ++ pRX_HP_Table->PSD_func_trigger = 1; ++ TP_Degrade_flag = 1; ++ LatchCnt = 2; ++ pre_state_flag = 0; ++ } ++ else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2]) ++ { ++ odm_PSD_RXHP(pDM_Odm); ++ pRX_HP_Table->PSD_func_trigger = 1; ++ TP_Degrade_flag = 1; ++ LatchCnt = 2; ++ pre_state_flag = 0; ++ } ++ else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3]) ++ { ++ odm_PSD_RXHP(pDM_Odm); ++ pRX_HP_Table->PSD_func_trigger = 1; ++ TP_Degrade_flag = 1; ++ LatchCnt = 2; ++ pre_state_flag = 0; ++ } ++ } ++ } ++#endif ++} ++ ++#if (DEV_BUS_TYPE == RT_USB_INTERFACE) ++ for (i=0;i<4;i++) ++ { ++ TP_Buff[4-i] = TP_Buff[3-i]; ++ } ++#endif ++ //2 Update PSD bitmap according to PSD report ++ if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0)) ++ { ++ //2 Separate 80M bandwidth into 16 group with smaller 5M BW. ++ for (i = 0 ; i < 16 ; i++) ++ { ++ sum = 0; ++ for(j = 0; j < 5 ; j++) ++ sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j]; ++ ++ if(sum < 5) ++ { ++ ch_map_intf_5M[i] = 1; // interference flag ++ } ++ } ++ //=============just for debug========================= ++ //for(i=0;i<16;i++) ++ //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]); ++ //=============================================== ++ //2 Mask target channel 5M index ++ for(i = 0; i < (4+4*Is40MHz) ; i++) ++ { ++ ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0; ++ } ++ ++ psd_intf_flag = 0; ++ for(i = 0; i < 16; i++) ++ { ++ if(ch_map_intf_5M[i] == 1) ++ { ++ psd_intf_flag = 1; // interference is detected!!! ++ break; ++ } ++ } ++ ++#if (DEV_BUS_TYPE == RT_USB_INTERFACE) ++ if(pRX_HP_Table->TP_Mode!=Idle_Mode) ++ { ++ if(psd_intf_flag == 1) // to avoid psd_intf_flag always 1 ++ { ++ Intf_HighTP_flag = 1; ++ De_counter = 32; // 0x1E -> 0x3E needs 32 times by each IGI step =1 ++ } ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag)); ++ //2 Distance between target channel and interference ++ for(i = 0; i < 16; i++) ++ { ++ if(ch_map_intf_5M[i] == 1) ++ { ++ Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz)); ++ if(Intf_diff_idx < MIN_Intf_diff_idx) ++ MIN_Intf_diff_idx = Intf_diff_idx; // the min difference index between interference and target ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx)); ++ //2 Choose False Alarm Threshold ++ switch (MIN_Intf_diff_idx){ ++ case 0: ++ case 1: ++ case 2: ++ case 3: ++ FA_TH = FA_RXHP_TH1; ++ break; ++ case 4: // CH5 ++ case 5: // CH6 ++ FA_TH = FA_RXHP_TH2; ++ break; ++ case 6: // CH7 ++ case 7: // CH8 ++ FA_TH = FA_RXHP_TH3; ++ break; ++ case 8: // CH9 ++ case 9: //CH10 ++ FA_TH = FA_RXHP_TH4; ++ break; ++ case 10: ++ case 11: ++ case 12: ++ case 13: ++ case 14: ++ case 15: ++ FA_TH = FA_RXHP_TH5; ++ break; ++ } ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH)); ++ pRX_HP_Table->PSD_func_trigger = 0; ++ } ++ //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode ++ if(pRX_HP_Table->RXHP_flag == 1) ++ { ++ if ((curRssi > 80)&&(preRssi < 80)) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; ++ } ++ else if ((curRssi < 80)&&(preRssi > 80)) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; ++ } ++ else if ((curRssi > 72)&&(preRssi < 72)) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; ++ } ++ else if ((curRssi < 72)&&( preRssi > 72)) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; ++ } ++ else if (curRssi < 68) //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode ++ { ++ pRX_HP_Table->Cur_pw_th = pw_th_10dB; ++ pRX_HP_Table->RXHP_flag = 0; // Back to Normal DIG Mode ++ psd_intf_flag = 0; ++ } ++ } ++ else // pRX_HP_Table->RXHP_flag == 0 ++ { ++ //1 Decide whether to enter AGC RX High Power Mode ++ if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) && ++ (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max)) ++ { ++ if (curRssi > 80) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; ++ } ++ else if (curRssi > 72) ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; ++ } ++ else ++ { ++ pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; ++ } ++ pRX_HP_Table->Cur_pw_th = pw_th_16dB; //RegC54[9:8]=2'b11: to enter AGC Flow 3 ++ pRX_HP_Table->First_time_enter = TRUE; ++ pRX_HP_Table->RXHP_flag = 1; // RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode ++ } ++ } ++ preRssi = curRssi; ++ odm_Write_RXHP(pDM_Odm); ++ } ++#endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++#endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) ++} ++ ++void odm_Write_RXHP( ++ IN PDM_ODM_T pDM_Odm) ++{ ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ u4Byte currentIGI; ++ ++ if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI) ++ { ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); ++ } ++ ++ if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th) ++{ ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th); // RegC54[9:8]=2'b11: AGC Flow 3 ++ } ++ ++ if(pRX_HP_Table->RXHP_flag == 0) ++ { ++ pRX_HP_Table->Cur_IGI = 0x20; ++ } ++ else ++ { ++ currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); ++ if(currentIGI<0x50) ++ { ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); ++ } ++ } ++ pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI; ++ pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th; ++ ++} ++ ++VOID ++odm_PSD_RXHP( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ unsigned int pts, start_point, stop_point, initial_gain ; ++ static u1Byte PSD_bitmap_memory[80], init_memory = 0; ++ static u1Byte psd_cnt=0; ++ static u4Byte PSD_report[80], PSD_report_tmp; ++ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, ++ 0,3,6,10,13,16,19,22,26,29}; ++ u1Byte n, i, channel, BBReset,tone_idx; ++ u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; ++ s4Byte PSD_skip_start, PSD_skip_stop; ++ u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; ++ u4Byte ReScan, Interval, Is40MHz; ++ u8Byte curTxOkCnt, curRxOkCnt; ++ //--------------2G band synthesizer for 92D switch RF channel using----------------- ++ u1Byte group_idx=0; ++ u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0; ++ u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel ++ u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840} ++ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14 ++ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8 ++ //--------------------- Add by Gary for Debug setting ---------------------- ++ s4Byte psd_result = 0; ++ u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF); ++ u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF); ++ //--------------------------------------------------------------------- ++ ++ if(pMgntInfo->bScanInProgress) ++ { ++ return; ++ } ++ ++ ReScan = PSD_RESCAN; ++ Interval = SCAN_INTERVAL; ++ ++ ++ //1 Initialization ++ if(init_memory == 0) ++ { ++ RT_TRACE( COMP_PSD, DBG_LOUD,("Init memory\n")); ++ for(i = 0; i < 80; i++) ++ PSD_bitmap_memory[i] = 0xFF; // channel is always good ++ init_memory = 1; ++ } ++ if(psd_cnt == 0) ++ { ++ RT_TRACE(COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); ++ for(i = 0; i < 80; i++) ++ PSD_report[i] = 0; ++ } ++ ++ //1 Backup Current Settings ++ CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ //2 Record Current synthesizer parameters based on current channel ++ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) ++ { ++ SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord); ++ SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord); ++ SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord); ++ SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord); ++ SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord); ++ } ++ else // DualMAC_DualPHY 2G ++ { ++ SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord); ++ SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord); ++ SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord); ++ SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord); ++ SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord); ++ } ++ } ++ RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); ++ RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; ++ Is40MHz = *(pDM_Odm->pBandWidth); ++ ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); ++ //1 Turn off CCK ++ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); ++ //1 Turn off TX ++ //Pause TX Queue ++ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); ++ //Force RX to stop TX immediately ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); ++ //1 Turn off RX ++ //Rx AGC off RegC70[0]=0, RegC7C[20]=0 ++ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); ++ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); ++ //Turn off CCA ++ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); ++ //BB Reset ++ BBReset = ODM_Read1Byte(pDM_Odm, 0x02); ++ ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); ++ ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); ++ //1 Leave RX idle low power ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); ++ //1 Fix initial gain ++ RSSI_BT = RSSI_BT_new; ++ RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); ++ ++ if(rssi_ctrl == 1) // just for debug!! ++ initial_gain_psd = RSSI_BT_new; ++ else ++ initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI ++ ++ RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); ++ ++ initialGainUpper = 0x54; ++ ++ RSSI_BT = initial_gain_psd; ++ //SSBT = RSSI_BT; ++ ++ //RT_TRACE( COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); ++ RT_TRACE( COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); ++ ++ pDM_Odm->bDMInitialGainEnable = FALSE; ++ initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F; ++ ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); ++ //1 Turn off 3-wire ++ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); ++ ++ //pts value = 128, 256, 512, 1024 ++ pts = 128; ++ ++ if(pts == 128) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); ++ start_point = 64; ++ stop_point = 192; ++ } ++ else if(pts == 256) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); ++ start_point = 128; ++ stop_point = 384; ++ } ++ else if(pts == 512) ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); ++ start_point = 256; ++ stop_point = 768; ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); ++ start_point = 512; ++ stop_point = 1536; ++ } ++ ++ ++//3 Skip WLAN channels if WLAN busy ++ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; ++ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; ++ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); ++ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); ++ ++ PSD_skip_start=80; ++ PSD_skip_stop = 0; ++ wlan_channel = CurrentChannel & 0x0f; ++ ++ RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); ++ ++ if((curRxOkCnt+curTxOkCnt) > 1000) ++ { ++ PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; ++ PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; ++ } ++ ++ RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); ++ ++ for (n=0;n<80;n++) ++ { ++ if((n%20)==0) ++ { ++ channel = (n/20)*4 + 1; ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ switch(channel) ++ { ++ case 1: ++ case 9: ++ group_idx = 0; ++ break; ++ case 5: ++ group_idx = 2; ++ break; ++ case 13: ++ group_idx = 1; ++ break; ++ } ++ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) ++ { ++ for(i = 0; i < SYN_Length; i++) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]); ++ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel); ++ } ++ else // DualMAC_DualPHY 2G ++ { ++ for(i = 0; i < SYN_Length; i++) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); ++ ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ } ++ } ++ else ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); ++ } ++ tone_idx = n%20; ++ if ((n>=PSD_skip_start) && (n PSD_report[n]) ++ PSD_report[n] = PSD_report_tmp; ++ ++ } ++ } ++ ++ PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); ++ ++ //----end ++ //1 Turn on RX ++ //Rx AGC on ++ ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); ++ ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); ++ //CCK on ++ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); ++ //1 Turn on TX ++ //Resume TX Queue ++ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); ++ //Turn on 3-wire ++ ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); ++ //1 Restore Current Settings ++ //Resume DIG ++ pDM_Odm->bDMInitialGainEnable= TRUE; ++ ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain); ++ // restore originl center frequency ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); ++ if(pDM_Odm->SupportICType == ODM_RTL8192D) ++ { ++ if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C); ++ } ++ else // DualMAC_DualPHY ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C); ++ } ++ } ++ //Turn on CCA ++ ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); ++ //Restore RX idle low power ++ if(RxIdleLowPwr == TRUE) ++ ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); ++ ++ psd_cnt++; ++ //gPrint("psd cnt=%d\n", psd_cnt); ++ ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); ++ if (psd_cnt < ReScan) ++ { ++ ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval); //ms ++ } ++ else ++ { ++ psd_cnt = 0; ++ for(i=0;i<80;i++) ++ RT_TRACE( COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); ++ //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); ++ ++ GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); ++ ++ } ++ } ++ ++VOID ++odm_PSD_RXHPCallback( ++ PRT_TIMER pTimer ++) ++{ ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ #if USE_WORKITEM ++ ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); ++ #else ++ odm_PSD_RXHP(pDM_Odm); ++ #endif ++#else ++ ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); ++#endif ++ ++ } ++ ++VOID ++odm_PSD_RXHPWorkitemCallback( ++ IN PVOID pContext ++ ) ++{ ++ PADAPTER pAdapter = (PADAPTER)pContext; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ odm_PSD_RXHP(pDM_Odm); ++} ++ ++#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++// ++// 2011/09/22 MH Add for 92D global spin lock utilization. ++// ++VOID ++odm_GlobalAdapterCheck( ++ IN VOID ++ ) ++{ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++ //sherry delete flag 20110517 ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++ ACQUIRE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList); ++#else ++ ACQUIRE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList); ++#endif ++ ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++ RELEASE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList); ++#else ++ RELEASE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList); ++#endif ++ ++#endif ++ ++} // odm_GlobalAdapterCheck ++ ++ ++ ++// ++// 2011/12/02 MH Copy from MP oursrc for temporarily test. ++// ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++odm_OFDMTXPathDiversity_92C( ++ IN PADAPTER Adapter) ++{ ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ PRT_WLAN_STA pEntry; ++ u1Byte i, DefaultRespPath = 0; ++ s4Byte MinRSSI = 0xFF; ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ pDM_PDTable->OFDMTXPath = 0; ++ ++ //1 Default Port ++ if(pMgntInfo->mAssoc) ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n", ++ Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1])); ++ if(Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1]) ++ { ++ pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0); ++ MinRSSI = Adapter->RxStats.RxRSSIPercentage[1]; ++ DefaultRespPath = 0; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n")); ++ } ++ else ++ { ++ pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT0; ++ MinRSSI = Adapter->RxStats.RxRSSIPercentage[0]; ++ DefaultRespPath = 1; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n")); ++ } ++ //RT_TRACE( COMP_SWAS, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath)); ++ } ++ //1 Extension Port ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); ++ else ++ pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); ++ ++ if(pEntry!=NULL) ++ { ++ if(pEntry->bAssociated) ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n", ++ pEntry->AID+1, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1])); ++ ++ if(pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1]) ++ { ++ pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AID+1)); ++ //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AID+1)); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AID+1)); ++ if(pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI) ++ { ++ MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1]; ++ DefaultRespPath = 0; ++ } ++ } ++ else ++ { ++ pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AID+1); ++ //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AID+1)); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AID+1)); ++ if(pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI) ++ { ++ MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0]; ++ DefaultRespPath = 1; ++ } ++ } ++ } ++ } ++ else ++ { ++ break; ++ } ++ } ++ ++ pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath; ++} ++ ++ ++BOOLEAN ++odm_IsConnected_92C( ++ IN PADAPTER Adapter ++) ++{ ++ PRT_WLAN_STA pEntry; ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u4Byte i; ++ BOOLEAN bConnected=FALSE; ++ ++ if(pMgntInfo->mAssoc) ++ { ++ bConnected = TRUE; ++ } ++ else ++ { ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); ++ else ++ pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); ++ ++ if(pEntry!=NULL) ++ { ++ if(pEntry->bAssociated) ++ { ++ bConnected = TRUE; ++ break; ++ } ++ } ++ else ++ { ++ break; ++ } ++ } ++ } ++ return bConnected; ++} ++ ++ ++VOID ++odm_ResetPathDiversity_92C( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ PRT_WLAN_STA pEntry; ++ u4Byte i; ++ ++ pHalData->RSSI_test = FALSE; ++ pDM_PDTable->CCK_Pkt_Cnt = 0; ++ pDM_PDTable->OFDM_Pkt_Cnt = 0; ++ pHalData->CCK_Pkt_Cnt =0; ++ pHalData->OFDM_Pkt_Cnt =0; ++ ++ if(pDM_PDTable->CCKPathDivEnable == TRUE) ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); //RX path = PathAB ++ ++ for(i=0; i<2; i++) ++ { ++ pDM_PDTable->RSSI_CCK_Path_cnt[i]=0; ++ pDM_PDTable->RSSI_CCK_Path[i] = 0; ++ } ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); ++ else ++ pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); ++ ++ if(pEntry!=NULL) ++ { ++ pEntry->rssi_stat.CCK_Pkt_Cnt = 0; ++ pEntry->rssi_stat.OFDM_Pkt_Cnt = 0; ++ for(i=0; i<2; i++) ++ { ++ pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] = 0; ++ pEntry->rssi_stat.RSSI_CCK_Path[i] = 0; ++ } ++ } ++ else ++ break; ++ } ++} ++ ++ ++VOID ++odm_CCKTXPathDiversity_92C( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ PRT_WLAN_STA pEntry; ++ s4Byte MinRSSI = 0xFF; ++ u1Byte i, DefaultRespPath = 0; ++// BOOLEAN bBModePathDiv = FALSE; ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ ++ //1 Default Port ++ if(pMgntInfo->mAssoc) ++ { ++ if(pHalData->OFDM_Pkt_Cnt == 0) ++ { ++ for(i=0; i<2; i++) ++ { ++ if(pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded ++ pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1); ++ else ++ pDM_PDTable->RSSI_CCK_Path[i] = 0; ++ } ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n", ++ pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1])); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n", ++ pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1])); ++ ++ if(pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1]) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); ++ MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; ++ DefaultRespPath = 0; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); ++ } ++ else if(pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1]) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT0; ++ MinRSSI = pDM_PDTable->RSSI_CCK_Path[0]; ++ DefaultRespPath = 1; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n")); ++ } ++ else ++ { ++ if((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI)) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); ++ MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; ++ DefaultRespPath = 0; ++ } ++ else ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n")); ++ } ++ } ++ } ++ else //Follow OFDM decision ++ { ++ pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n", ++ pDM_PDTable->CCKTXPath &BIT0)); ++ } ++ } ++ //1 Extension Port ++ for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); ++ else ++ pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); ++ ++ if(pEntry!=NULL) ++ { ++ if(pEntry->bAssociated) ++ { ++ if(pEntry->rssi_stat.OFDM_Pkt_Cnt == 0) ++ { ++ for(i=0; i<2; i++) ++ { ++ if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] > 1) ++ pEntry->rssi_stat.RSSI_CCK_Path[i] = pEntry->rssi_stat.RSSI_CCK_Path[i] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[i]-1); ++ else ++ pEntry->rssi_stat.RSSI_CCK_Path[i] = 0; ++ } ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n", ++ pEntry->AID+1, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1])); ++ ++ if(pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1]) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1)); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1)); ++ if(pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI) ++ { ++ MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; ++ DefaultRespPath = 0; ++ } ++ } ++ else if(pEntry->rssi_stat.RSSI_CCK_Path[0] rssi_stat.RSSI_CCK_Path[1]) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AID+1); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AID+1)); ++ if(pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI) ++ { ++ MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0]; ++ DefaultRespPath = 1; ++ } ++ } ++ else ++ { ++ if((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)) ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1)); ++ MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; ++ DefaultRespPath = 0; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1)); ++ } ++ else ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AID+1)); ++ } ++ } ++ } ++ else //Follow OFDM decision ++ { ++ pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AID+1)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AID+1)); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n", ++ pEntry->AID+1, (pDM_PDTable->CCKTXPath & BIT(pEntry->AID+1))>>(pEntry->AID+1))); ++ } ++ } ++ } ++ else ++ { ++ break; ++ } ++ } ++ ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI)); ++ ++ if(MinRSSI == 0xFF) ++ DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; ++ ++ pDM_PDTable->CCKDefaultRespPath = DefaultRespPath; ++} ++ ++ ++ ++VOID ++odm_PathDiversityAfterLink_92C( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ u1Byte DefaultRespPath=0; ++ ++ if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff)) ++ { ++ if(pHalData->PathDivCfg == 0) ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("No ODM_TXPathDiversity()\n")); ++ } ++ else ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("2T ODM_TXPathDiversity()\n")); ++ } ++ return; ++ } ++ if(!odm_IsConnected_92C(Adapter)) ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n")); ++ return; ++ } ++ ++ ++ if(pDM_PDTable->TrainingState == 0) ++ { ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n")); ++ odm_OFDMTXPathDiversity_92C(Adapter); ++ ++ if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100)) ++ { ++ //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n")); ++ ++ if(pDM_PDTable->CCK_Pkt_Cnt > 300) ++ pDM_PDTable->Timer = 20; ++ else if(pDM_PDTable->CCK_Pkt_Cnt > 100) ++ pDM_PDTable->Timer = 60; ++ else ++ pDM_PDTable->Timer = 250; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer)); ++ ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // RX path = PathA ++ pDM_PDTable->TrainingState = 1; ++ pHalData->RSSI_test = TRUE; ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms ++ } ++ else ++ { ++ pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath; ++ DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n")); ++ odm_SetRespPath_92C(Adapter, DefaultRespPath); ++ odm_ResetPathDiversity_92C(Adapter); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); ++ } ++ } ++ else if(pDM_PDTable->TrainingState == 1) ++ { ++ //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n")); ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // RX path = PathB ++ pDM_PDTable->TrainingState = 2; ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms ++ } ++ else ++ { ++ //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n")); ++ pDM_PDTable->TrainingState = 0; ++ odm_CCKTXPathDiversity_92C(Adapter); ++ if(pDM_PDTable->OFDM_Pkt_Cnt != 0) ++ { ++ DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n")); ++ } ++ else ++ { ++ DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n")); ++ } ++ odm_SetRespPath_92C(Adapter, DefaultRespPath); ++ odm_ResetPathDiversity_92C(Adapter); ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); ++ } ++ ++} ++ ++ ++ ++VOID ++odm_CCKTXPathDiversityCallback( ++ PRT_TIMER pTimer ++) ++{ ++#if USE_WORKITEM ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++#else ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++#endif ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++#if USE_WORKITEM ++ PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); ++#else ++ odm_PathDiversityAfterLink_92C(Adapter); ++#endif ++#else ++ PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); ++#endif ++ ++} ++ ++ ++VOID ++odm_CCKTXPathDiversityWorkItemCallback( ++ IN PVOID pContext ++ ) ++{ ++ PADAPTER Adapter = (PADAPTER)pContext; ++ ++ odm_CCKTXPathDiversity_92C(Adapter); ++} ++ ++ ++VOID ++ODM_CCKPathDiversityChkPerPktRssi( ++ PADAPTER Adapter, ++ BOOLEAN bIsDefPort, ++ BOOLEAN bMatchBSSID, ++ PRT_WLAN_STA pEntry, ++ PRT_RFD pRfd, ++ pu1Byte pDesc ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN bCount = FALSE; ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ //BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc); ++#if DEV_BUS_TYPE != RT_SDIO_INTERFACE ++ BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc); ++#else //below code would be removed if we have verified SDIO ++ BOOLEAN isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc); ++#endif ++ ++ if((pHalData->PathDivCfg != 1) || (pHalData->RSSI_test == FALSE)) ++ return; ++ ++ if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) ++ bCount = TRUE; ++ else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) ++ bCount = TRUE; ++ ++ if(bCount && isCCKrate) ++ { ++ if(pDM_PDTable->TrainingState == 1 ) ++ { ++ if(pEntry) ++ { ++ if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0) ++ pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; ++ pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++; ++ } ++ else ++ { ++ if(pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0) ++ pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; ++ pDM_PDTable->RSSI_CCK_Path_cnt[0]++; ++ } ++ } ++ else if(pDM_PDTable->TrainingState == 2 ) ++ { ++ if(pEntry) ++ { ++ if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0) ++ pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; ++ pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++; ++ } ++ else ++ { ++ if(pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0) ++ pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; ++ pDM_PDTable->RSSI_CCK_Path_cnt[1]++; ++ } ++ } ++ } ++} ++ ++ ++BOOLEAN ++ODM_PathDiversityBeforeLink92C( ++ //IN PADAPTER Adapter ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE* pHalData = NULL; ++ PMGNT_INFO pMgntInfo = NULL; ++ //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; ++ pPD_T pDM_PDTable = NULL; ++ ++ s1Byte Score = 0; ++ PRT_WLAN_BSS pTmpBssDesc; ++ PRT_WLAN_BSS pTestBssDesc; ++ ++ u1Byte target_chnl = 0; ++ u1Byte index; ++ ++ if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 ++ { // The ODM structure is not initialized. ++ return FALSE; ++ } ++ pHalData = GET_HAL_DATA(Adapter); ++ pMgntInfo = &Adapter->MgntInfo; ++ pDM_PDTable = &Adapter->DM_PDTable; ++ ++ // Condition that does not need to use path diversity. ++ if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest ) ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n")); ++ return FALSE; ++ } ++ ++ // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. ++ PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) ++ { ++ PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", ++ pMgntInfo->RFChangeInProgress, ++ pHalData->eRFPowerState)); ++ ++ //pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ pDM_PDTable->PathDiv_NoLink_State = 0; ++ ++ return FALSE; ++ } ++ else ++ { ++ PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); ++ } ++ ++ //1 Run AntDiv mechanism "Before Link" part. ++ //if(pDM_SWAT_Table->SWAS_NoLink_State == 0) ++ if(pDM_PDTable->PathDiv_NoLink_State == 0) ++ { ++ //1 Prepare to do Scan again to check current antenna state. ++ ++ // Set check state to next step. ++ //pDM_SWAT_Table->SWAS_NoLink_State = 1; ++ pDM_PDTable->PathDiv_NoLink_State = 1; ++ ++ // Copy Current Scan list. ++ Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; ++ PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); ++ ++ // Switch Antenna to another one. ++ if(pDM_PDTable->DefaultRespPath == 0) ++ { ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // TRX path = PathB ++ odm_SetRespPath_92C(Adapter, 1); ++ pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; ++ pDM_PDTable->CCKTXPath = 0xFFFFFFFF; ++ } ++ else ++ { ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // TRX path = PathA ++ odm_SetRespPath_92C(Adapter, 0); ++ pDM_PDTable->OFDMTXPath = 0x0; ++ pDM_PDTable->CCKTXPath = 0x0; ++ } ++#if 0 ++ ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; ++ ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); ++ pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); ++ PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); ++#endif ++ ++ // Go back to scan function again. ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n")); ++ pMgntInfo->ScanStep=0; ++ target_chnl = odm_SwAntDivSelectChkChnl(Adapter); ++ odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl); ++ HTReleaseChnlOpLock(Adapter); ++ PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); ++ ++ return TRUE; ++ } ++ else ++ { ++ //1 ScanComple() is called after antenna swiched. ++ //1 Check scan result and determine which antenna is going ++ //1 to be used. ++ ++ for(index=0; indexMgntInfo.tmpNumBssDesc; index++) ++ { ++ pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); ++ pTestBssDesc = &(pMgntInfo->bssDesc[index]); ++ ++ if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n")); ++ continue; ++ } ++ ++ if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n")); ++ RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); ++ ++ Score++; ++ PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); ++ } ++ else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n")); ++ RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); ++ Score--; ++ } ++ ++ } ++ ++ if(pMgntInfo->NumBssDesc!=0 && Score<=0) ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); ++ ++ //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ } ++ else ++ { ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); ++ ++ if(pDM_PDTable->DefaultRespPath == 0) ++ { ++ pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; ++ pDM_PDTable->CCKTXPath = 0xFFFFFFFF; ++ odm_SetRespPath_92C(Adapter, 1); ++ } ++ else ++ { ++ pDM_PDTable->OFDMTXPath = 0x0; ++ pDM_PDTable->CCKTXPath = 0x0; ++ odm_SetRespPath_92C(Adapter, 0); ++ } ++ PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); // RX path = PathAB ++ ++ //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); ++ //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); ++ } ++ ++ // Check state reset to default and wait for next time. ++ //pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ pDM_PDTable->PathDiv_NoLink_State = 0; ++ ++ return FALSE; ++ } ++#else ++ return FALSE; ++#endif ++ ++} ++ ++ ++//Neil Chen---2011--06--22 ++//----92D Path Diversity----// ++//#ifdef PathDiv92D ++//================================== ++//3 Path Diversity ++//================================== ++// ++// 20100514 Luke/Joseph: ++// Add new function for antenna diversity after link. ++// This is the main function of antenna diversity after link. ++// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). ++// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. ++// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. ++// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just ++// listened on the air with the RSSI of original antenna. ++// It chooses the antenna with better RSSI. ++// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting ++// penalty to get next try. ++// ++// ++// 20100503 Joseph: ++// Add new function SwAntDivCheck8192C(). ++// This is the main function of Antenna diversity function before link. ++// Mainly, it just retains last scan result and scan again. ++// After that, it compares the scan result to see which one gets better RSSI. ++// It selects antenna with better receiving power and returns better scan result. ++// ++ ++ ++// ++// 20100514 Luke/Joseph: ++// This function is used to gather the RSSI information for antenna testing. ++// It selects the RSSI of the peer STA that we want to know. ++// ++VOID ++ODM_PathDivChkPerPktRssi( ++ PADAPTER Adapter, ++ BOOLEAN bIsDefPort, ++ BOOLEAN bMatchBSSID, ++ PRT_WLAN_STA pEntry, ++ PRT_RFD pRfd ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN bCount = FALSE; ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) ++ bCount = TRUE; ++ else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) ++ bCount = TRUE; ++ ++ if(bCount) ++ { ++ //1 RSSI for SW Antenna Switch ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll; ++ pHalData->RSSI_cnt_A++; ++ } ++ else ++ { ++ pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll; ++ pHalData->RSSI_cnt_B++; ++ ++ } ++ } ++} ++ ++ ++ ++// ++// 20100514 Luke/Joseph: ++// Add new function to reset antenna diversity state after link. ++// ++VOID ++ODM_PathDivRestAfterLink( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ PADAPTER Adapter=pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_cnt_B = 0; ++ pHalData->RSSI_test = FALSE; ++ pDM_SWAT_Table->try_flag = 0x0; // NOT 0xff ++ pDM_SWAT_Table->RSSI_Trying = 0; ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ pDM_SWAT_Table->CurAntenna = Antenna_A; ++} ++ ++ ++// ++// 20100514 Luke/Joseph: ++// Callback function for 500ms antenna test trying. ++// ++VOID ++odm_PathDivChkAntSwitchCallback( ++ PRT_TIMER pTimer ++) ++{ ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ ++#if USE_WORKITEM ++ PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); ++#else ++ odm_PathDivChkAntSwitch(pDM_Odm); ++#endif ++#else ++ PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); ++#endif ++ ++//odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE); ++ ++} ++ ++ ++VOID ++odm_PathDivChkAntSwitchWorkitemCallback( ++ IN PVOID pContext ++ ) ++{ ++ PADAPTER pAdapter = (PADAPTER)pContext; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ ++ odm_PathDivChkAntSwitch(pDM_Odm); ++} ++ ++ ++ //MAC0_ACCESS_PHY1 ++ ++// 2011-06-22 Neil Chen & Gary Hsin ++// Refer to Jr.Luke's SW ANT DIV ++// 92D Path Diversity Main function ++// refer to 88C software antenna diversity ++// ++VOID ++odm_PathDivChkAntSwitch( ++ PDM_ODM_T pDM_Odm ++ //PADAPTER Adapter, ++ //u1Byte Step ++) ++{ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ s4Byte curRSSI=100, RSSI_A, RSSI_B; ++ u1Byte nextAntenna=Antenna_B; ++ static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; ++ u8Byte curTxOkCnt, curRxOkCnt; ++ static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; ++ u8Byte CurByteCnt=0, PreByteCnt=0; ++ static u1Byte TrafficLoad = TRAFFIC_LOW; ++ u1Byte Score_A=0, Score_B=0; ++ u1Byte i=0x0; ++ // Neil Chen ++ static u1Byte pathdiv_para=0x0; ++ static u1Byte switchfirsttime=0x00; ++ // u1Byte regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27); ++ u1Byte regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27); ++ ++ ++ //u1Byte reg637 =0x0; ++ static u1Byte fw_value=0x0; ++ u1Byte n=0; ++ static u8Byte lastTxOkCnt_tmp=0, lastRxOkCnt_tmp=0; ++ //u8Byte curTxOkCnt_tmp, curRxOkCnt_tmp; ++ PADAPTER BuddyAdapter = Adapter->BuddyAdapter; // another adapter MAC ++ // Path Diversity //Neil Chen--2011--06--22 ++ ++ //u1Byte PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31); ++ u1Byte PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31); ++ u1Byte PathDiv_Enable = pHalData->bPathDiv_Enable; ++ ++ ++ //DbgPrint("Path Div PG Value:%x \n",PathDiv_Enable); ++ if((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType92D == BAND_ON_2_4G)) ++ { ++ return; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n")); ++ ++ // The first time to switch path excluding 2nd, 3rd, ....etc.... ++ if(switchfirsttime==0) ++ { ++ if(regB33==0) ++ { ++ pDM_SWAT_Table->CurAntenna = Antenna_A; // Default MAC0_5G-->Path A (current antenna) ++ } ++ } ++ ++ // Condition that does not need to use antenna diversity. ++ if(pDM_Odm->SupportICType != ODM_RTL8192D) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n")); ++ return; ++ } ++ ++ // Radio off: Status reset to default and return. ++ if(pHalData->eRFPowerState==eRfOff) ++ { ++ //ODM_SwAntDivRestAfterLink(Adapter); ++ return; ++ } ++ ++ /* ++ // Handling step mismatch condition. ++ // Peak step is not finished at last time. Recover the variable and check again. ++ if( Step != pDM_SWAT_Table->try_flag ) ++ { ++ ODM_SwAntDivRestAfterLink(Adapter); ++ } */ ++ ++ if(pDM_SWAT_Table->try_flag == 0xff) ++ { ++ // Select RSSI checking target ++ if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) ++ { ++ // Target: Infrastructure mode AP. ++ pHalData->RSSI_target = NULL; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n")); ++ } ++ else ++ { ++ u1Byte index = 0; ++ PRT_WLAN_STA pEntry = NULL; ++ PADAPTER pTargetAdapter = NULL; ++ ++ if( pMgntInfo->mIbss || ACTING_AS_AP(Adapter) ) ++ { ++ // Target: AP/IBSS peer. ++ pTargetAdapter = Adapter; ++ } ++ else if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) ++ { ++ // Target: VWIFI peer. ++ pTargetAdapter = GetFirstExtAdapter(Adapter); ++ } ++ ++ if(pTargetAdapter != NULL) ++ { ++ for(index=0; indexbAssociated) ++ break; ++ } ++ } ++ } ++ ++ if(pEntry == NULL) ++ { ++ ODM_PathDivRestAfterLink(pDM_Odm); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); ++ return; ++ } ++ else ++ { ++ pHalData->RSSI_target = pEntry; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); ++ } ++ } ++ ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_cnt_B = 0; ++ pDM_SWAT_Table->try_flag = 0; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n")); ++ return; ++ } ++ else ++ { ++ // 1st step ++ curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; ++ curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; ++ lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; ++ lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; ++ ++ if(pDM_SWAT_Table->try_flag == 1) // Training State ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ TXByteCnt_A += curTxOkCnt; ++ RXByteCnt_A += curRxOkCnt; ++ } ++ else ++ { ++ TXByteCnt_B += curTxOkCnt; ++ RXByteCnt_B += curRxOkCnt; ++ } ++ ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->RSSI_Trying--; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying)); ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ { ++ CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B); ++ PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A); ++ ++ if(TrafficLoad == TRAFFIC_HIGH) ++ { ++ //CurByteCnt = PlatformDivision64(CurByteCnt, 9); ++ PreByteCnt =PreByteCnt*9; ++ } ++ else if(TrafficLoad == TRAFFIC_LOW) ++ { ++ //CurByteCnt = PlatformDivision64(CurByteCnt, 2); ++ PreByteCnt =PreByteCnt*2; ++ } ++ if(pHalData->RSSI_cnt_A > 0) ++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pHalData->RSSI_cnt_B > 0) ++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", ++ (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); ++ } ++ ++ } ++ else // try_flag=0 ++ { ++ ++ if(pHalData->RSSI_cnt_A > 0) ++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pHalData->RSSI_cnt_B > 0) ++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", ++ (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); ++ } ++ ++ //1 Trying State ++ if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) ++ { ++ ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt)); ++ if(CurByteCnt < PreByteCnt) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ } ++ else ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ } ++ for (i= 0; i<8; i++) ++ { ++ if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) ++ Score_A++; ++ else ++ Score_B++; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B)); ++ ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ nextAntenna = (Score_A >= Score_B)?Antenna_A:Antenna_B; ++ } ++ else ++ { ++ nextAntenna = (Score_B >= Score_A)?Antenna_B:Antenna_A; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s \n", ++ (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); ++ ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna")); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n")); ++ } ++ } ++ ++ ++ if(pDM_SWAT_Table->TestMode == RSSI_MODE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE")); ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna ++ { ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Switch back to another antenna")); ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ } ++ else // current anntena is good ++ { ++ nextAntenna =pDM_SWAT_Table->CurAntenna; ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: current anntena is good\n")); ++ } ++ } ++ ++ pDM_SWAT_Table->try_flag = 0; ++ pHalData->RSSI_test = FALSE; ++ pHalData->RSSI_sum_A = 0; ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_sum_B = 0; ++ pHalData->RSSI_cnt_B = 0; ++ TXByteCnt_A = 0; ++ TXByteCnt_B = 0; ++ RXByteCnt_A = 0; ++ RXByteCnt_B = 0; ++ ++ } ++ ++ //1 Normal State ++ else if(pDM_SWAT_Table->try_flag == 0) ++ { ++ if(TrafficLoad == TRAFFIC_HIGH) ++ { ++ if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ++ TrafficLoad = TRAFFIC_HIGH; ++ else ++ TrafficLoad = TRAFFIC_LOW; ++ } ++ else if(TrafficLoad == TRAFFIC_LOW) ++ { ++ if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ++ TrafficLoad = TRAFFIC_HIGH; ++ else ++ TrafficLoad = TRAFFIC_LOW; ++ } ++ if(TrafficLoad == TRAFFIC_HIGH) ++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0; ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt)); ++ ++ //Prepare To Try Antenna ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->try_flag = 1; ++ pHalData->RSSI_test = TRUE; ++ if((curRxOkCnt+curTxOkCnt) > 1000) ++ { ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ pDM_SWAT_Table->RSSI_Trying = 4; ++#else ++ pDM_SWAT_Table->RSSI_Trying = 2; ++#endif ++ pDM_SWAT_Table->TestMode = TP_MODE; ++ } ++ else ++ { ++ pDM_SWAT_Table->RSSI_Trying = 2; ++ pDM_SWAT_Table->TestMode = RSSI_MODE; ++ ++ } ++ ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n")); ++ pHalData->RSSI_sum_A = 0; ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_sum_B = 0; ++ pHalData->RSSI_cnt_B = 0; ++ } // end of try_flag=0 ++ } ++ ++ //1 4.Change TRX antenna ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n ")); ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C ++ if(nextAntenna==Antenna_A) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n ")); ++ pathdiv_para = 0x02; //02 to switchback to RF path A ++ fw_value = 0x03; ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); ++#else ++ ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); ++#endif ++ } ++ else if(nextAntenna==Antenna_B) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n ")); ++ if(switchfirsttime==0) // First Time To Enter Path Diversity ++ { ++ switchfirsttime=0x01; ++ pathdiv_para = 0x00; ++ fw_value=0x00; // to backup RF Path A Releated Registers ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); ++#else ++ ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); ++ //for(u1Byte n=0; n<80,n++) ++ //{ ++ //delay_us(500); ++ ODM_delay_ms(500); ++ odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); ++ ++ fw_value=0x01; // to backup RF Path A Releated Registers ++ ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n ")); ++ } ++ else ++ { ++ pathdiv_para = 0x01; ++ fw_value = 0x02; ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); ++#else ++ ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); ++#endif ++ } ++ } ++ // odm_PathDiversity_8192D(Adapter, pathdiv_para); ++ } ++ ++ //1 5.Reset Statistics ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ pDM_SWAT_Table->CurAntenna = nextAntenna; ++ pDM_SWAT_Table->PreRSSI = curRSSI; ++ //lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; ++ //lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; ++ ++ //1 6.Set next timer ++ ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ return; ++ ++ if(pDM_SWAT_Table->RSSI_Trying%2 == 0) ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(TrafficLoad == TRAFFIC_HIGH) ++ { ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n")); ++#else ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n")); ++#endif ++ } ++ else if(TrafficLoad == TRAFFIC_LOW) ++ { ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n")); ++ } ++ } ++ else // TestMode == RSSI_MODE ++ { ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n")); ++ } ++ } ++ else ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(TrafficLoad == TRAFFIC_HIGH) ++ ++#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n")); ++#else ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms ++#endif ++ else if(TrafficLoad == TRAFFIC_LOW) ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms ++ } ++ else ++ ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms ++ } ++} ++ ++//================================================== ++//3 PathDiv End ++//================================================== ++ ++VOID ++odm_SetRespPath_92C( ++ IN PADAPTER Adapter, ++ IN u1Byte DefaultRespPath ++ ) ++{ ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ ++ RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath)); ++ if(DefaultRespPath != pDM_PDTable->DefaultRespPath) ++ { ++ if(DefaultRespPath == 0) ++ { ++ PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15); ++ } ++ else ++ { ++ PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A); ++ } ++ } ++ pDM_PDTable->DefaultRespPath = DefaultRespPath; ++} ++ ++ ++VOID ++ODM_FillTXPathInTXDESC( ++ IN PADAPTER Adapter, ++ IN PRT_TCB pTcb, ++ IN pu1Byte pDesc ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u4Byte TXPath; ++ pPD_T pDM_PDTable = &Adapter->DM_PDTable; ++ ++ //2011.09.05 Add by Luke Lee for path diversity ++ if(pHalData->PathDivCfg == 1) ++ { ++ TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0; ++ //RT_TRACE( COMP_SWAS, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath)); ++ //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath); ++ if(TXPath == 0) ++ { ++ SET_TX_DESC_TX_ANTL_92C(pDesc,1); ++ SET_TX_DESC_TX_ANT_HT_92C(pDesc,1); ++ } ++ else ++ { ++ SET_TX_DESC_TX_ANTL_92C(pDesc,2); ++ SET_TX_DESC_TX_ANT_HT_92C(pDesc,2); ++ } ++ TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0; ++ if(TXPath == 0) ++ { ++ SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1); ++ } ++ else ++ { ++ SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2); ++ } ++ } ++} ++ ++//Only for MP //Neil Chen--2012--0502-- ++VOID ++odm_PathDivInit( ++IN PDM_ODM_T pDM_Odm) ++{ ++ pPATHDIV_PARA pathIQK = &pDM_Odm->pathIQK; ++ ++ pathIQK->org_2g_RegC14=0x0; ++ pathIQK->org_2g_RegC4C=0x0; ++ pathIQK->org_2g_RegC80=0x0; ++ pathIQK->org_2g_RegC94=0x0; ++ pathIQK->org_2g_RegCA0=0x0; ++ pathIQK->org_5g_RegC14=0x0; ++ pathIQK->org_5g_RegCA0=0x0; ++ pathIQK->org_5g_RegE30=0x0; ++ pathIQK->swt_2g_RegC14=0x0; ++ pathIQK->swt_2g_RegC4C=0x0; ++ pathIQK->swt_2g_RegC80=0x0; ++ pathIQK->swt_2g_RegC94=0x0; ++ pathIQK->swt_2g_RegCA0=0x0; ++ pathIQK->swt_5g_RegC14=0x0; ++ pathIQK->swt_5g_RegCA0=0x0; ++ pathIQK->swt_5g_RegE30=0x0; ++ ++} ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++#if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++ ++ ++// ++// Description: ++// Set Single/Dual Antenna default setting for products that do not do detection in advance. ++// ++// Added by Joseph, 2012.03.22 ++// ++VOID ++ODM_SingleDualAntennaDefaultSetting( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ pDM_SWAT_Table->ANTA_ON=TRUE; ++ pDM_SWAT_Table->ANTB_ON=TRUE; ++} ++ ++ ++//2 8723A ANT DETECT ++ ++ ++VOID ++odm_PHY_SaveAFERegisters( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu4Byte AFEReg, ++ IN pu4Byte AFEBackup, ++ IN u4Byte RegisterNum ++ ) ++{ ++ u4Byte i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); ++ for( i = 0 ; i < RegisterNum ; i++){ ++ AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord); ++ } ++} ++ ++VOID ++odm_PHY_ReloadAFERegisters( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu4Byte AFEReg, ++ IN pu4Byte AFEBackup, ++ IN u4Byte RegiesterNum ++ ) ++{ ++ u4Byte i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); ++ for(i = 0 ; i < RegiesterNum; i++) ++ { ++ ++ ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]); ++ } ++} ++ ++//2 8723A ANT DETECT ++// ++// Description: ++// Implement IQK single tone for RF DPK loopback and BB PSD scanning. ++// This function is cooperated with BB team Neil. ++// ++// Added by Roger, 2011.12.15 ++// ++BOOLEAN ++ODM_SingleDualAntennaDetection( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte mode ++ ) ++{ ++ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ u4Byte CurrentChannel,RfLoopReg; ++ u1Byte n; ++ u4Byte Reg88c, Regc08, Reg874, Regc50; ++ u1Byte initial_gain = 0x5a; ++ u4Byte PSD_report_tmp; ++ u4Byte AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0; ++ BOOLEAN bResult = TRUE; ++ u4Byte AFE_Backup[16]; ++ u4Byte AFE_REG_8723A[16] = { ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN, ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth}; ++ ++ if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))) ++ return bResult; ++ ++ if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) ++ return bResult; ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8192C) ++ { ++ //Which path in ADC/DAC is turnned on for PSD: both I/Q ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3); ++ //Ageraged number: 8 ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1); ++ //pts = 128; ++ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); ++ } ++ ++ //1 Backup Current RF/BB Settings ++ ++ CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); ++ RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); // change to Antenna A ++ // Step 1: USE IQK to transmitter single tone ++ ++ ODM_StallExecution(10); ++ ++ //Store A Path Register 88c, c08, 874, c50 ++ Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); ++ Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); ++ Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); ++ Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); ++ ++ // Store AFE Registers ++ odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); ++ ++ //Set PSD 128 pts ++ ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts ++ ++ // To SET CH1 to do ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); //Channel 1 ++ ++ // AFE all on step ++ ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); ++ ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); ++ ++ // 3 wire Disable ++ ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); ++ ++ //BB IQK Setting ++ ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); ++ ++ //IQK setting tone@ 4.34Mhz ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); ++ ++ ++ //Page B init ++ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); ++ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); ++ ++ //RF loop Setting ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); ++ ++ //IQK Single tone start ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ++ ODM_StallExecution(1000); ++ PSD_report_tmp=0x0; ++ ++ for (n=0;n<2;n++) ++ { ++ PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); ++ if(PSD_report_tmp >AntA_report) ++ AntA_report=PSD_report_tmp; ++ } ++ ++ PSD_report_tmp=0x0; ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); // change to Antenna B ++ ODM_StallExecution(10); ++ ++ ++ for (n=0;n<2;n++) ++ { ++ PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); ++ if(PSD_report_tmp > AntB_report) ++ AntB_report=PSD_report_tmp; ++ } ++ ++ // change to open case ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); // change to Ant A and B all open case ++ ODM_StallExecution(10); ++ ++ for (n=0;n<2;n++) ++ { ++ PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); ++ if(PSD_report_tmp > AntO_report) ++ AntO_report=PSD_report_tmp; ++ } ++ ++ //Close IQK Single Tone function ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ PSD_report_tmp = 0x0; ++ ++ //1 Return to antanna A ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); ++ ++ //Reload AFE Registers ++ odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report)); ++ ++ ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ //2 Test Ant B based on Ant A is ON ++ if(mode==ANTTESTB) ++ { ++ if(AntA_report >= 100) ++ { ++ if(AntB_report > (AntA_report+1)) ++ { ++ pDM_SWAT_Table->ANTB_ON=FALSE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); ++ } ++ else ++ { ++ pDM_SWAT_Table->ANTB_ON=TRUE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n")); ++ } ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); ++ pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default ++ bResult = FALSE; ++ } ++ } ++ //2 Test Ant A and B based on DPDT Open ++ else if(mode==ANTTESTALL) ++ { ++ if((AntO_report >=100)&(AntO_report <118)) ++ { ++ if(AntA_report > (AntO_report+1)) ++ { ++ pDM_SWAT_Table->ANTA_ON=FALSE; ++ //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF")); ++ } ++ else ++ { ++ pDM_SWAT_Table->ANTA_ON=TRUE; ++ //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON")); ++ } ++ ++ if(AntB_report > (AntO_report+2)) ++ { ++ pDM_SWAT_Table->ANTB_ON=FALSE; ++ //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF")); ++ } ++ else ++ { ++ pDM_SWAT_Table->ANTB_ON=TRUE; ++ //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON")); ++ } ++ } ++ } ++ } ++ else if(pDM_Odm->SupportICType == ODM_RTL8192C) ++ { ++ if(AntA_report >= 100) ++ { ++ if(AntB_report > (AntA_report+2)) ++ { ++ pDM_SWAT_Table->ANTA_ON=FALSE; ++ pDM_SWAT_Table->ANTB_ON=TRUE; ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n")); ++ } ++ else if(AntA_report > (AntB_report+2)) ++ { ++ pDM_SWAT_Table->ANTA_ON=TRUE; ++ pDM_SWAT_Table->ANTB_ON=FALSE; ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); ++ } ++ else ++ { ++ pDM_SWAT_Table->ANTA_ON=TRUE; ++ pDM_SWAT_Table->ANTB_ON=TRUE; ++ RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna \n")); ++ } ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); ++ pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default ++ pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default ++ bResult = FALSE; ++ } ++ } ++ return bResult; ++ ++} ++ ++ ++#endif // end odm_CE ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ ++void odm_dtc(PDM_ODM_T pDM_Odm) ++{ ++#ifdef CONFIG_DM_RESP_TXAGC ++ #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ ++ #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ ++ ++ /* RSSI vs TX power step mapping: decade TX power */ ++ static const u8 dtc_table_down[]={ ++ DTC_BASE, ++ (DTC_BASE+5), ++ (DTC_BASE+10), ++ (DTC_BASE+15), ++ (DTC_BASE+20), ++ (DTC_BASE+25) ++ }; ++ ++ /* RSSI vs TX power step mapping: increase TX power */ ++ static const u8 dtc_table_up[]={ ++ DTC_DWN_BASE, ++ (DTC_DWN_BASE-5), ++ (DTC_DWN_BASE-10), ++ (DTC_DWN_BASE-15), ++ (DTC_DWN_BASE-15), ++ (DTC_DWN_BASE-20), ++ (DTC_DWN_BASE-20), ++ (DTC_DWN_BASE-25), ++ (DTC_DWN_BASE-25), ++ (DTC_DWN_BASE-30), ++ (DTC_DWN_BASE-35) ++ }; ++ ++ u8 i; ++ u8 dtc_steps=0; ++ u8 sign; ++ u8 resp_txagc=0; ++ ++ #if 0 ++ /* As DIG is disabled, DTC is also disable */ ++ if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) ++ return; ++ #endif ++ ++ if (DTC_BASE < pDM_Odm->RSSI_Min) { ++ /* need to decade the CTS TX power */ ++ sign = 1; ++ for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) ++ break; ++ else ++ dtc_steps++; ++ } ++ } ++#if 0 ++ else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) ++ { ++ /* needs to increase the CTS TX power */ ++ sign = 0; ++ dtc_steps = 1; ++ for (i=0;iRSSI_Min) || (dtc_steps>=10)) ++ break; ++ else ++ dtc_steps++; ++ } ++ } ++#endif ++ else ++ { ++ sign = 0; ++ dtc_steps = 0; ++ } ++ ++ resp_txagc = dtc_steps | (sign << 4); ++ resp_txagc = resp_txagc | (resp_txagc << 5); ++ ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); ++ ++ DBG_871X("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", ++ __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps); ++#endif /* CONFIG_RESP_TXAGC_ADJUST */ ++} ++ ++#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm.h +new file mode 100644 +index 00000000..f5add651 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm.h +@@ -0,0 +1,2063 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __HALDMOUTSRC_H__ ++#define __HALDMOUTSRC_H__ ++ ++//============================================================ ++// Definition ++//============================================================ ++// ++// 2011/09/22 MH Define all team supprt ability. ++// ++ ++// ++// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. ++// ++//#define DM_ODM_SUPPORT_AP 0 ++//#define DM_ODM_SUPPORT_ADSL 0 ++//#define DM_ODM_SUPPORT_CE 0 ++//#define DM_ODM_SUPPORT_MP 1 ++ ++// ++// 2011/09/28 MH Define ODM SW team support flag. ++// ++ ++ ++ ++// ++// Antenna Switch Relative Definition. ++// ++ ++// ++// 20100503 Joseph: ++// Add new function SwAntDivCheck8192C(). ++// This is the main function of Antenna diversity function before link. ++// Mainly, it just retains last scan result and scan again. ++// After that, it compares the scan result to see which one gets better RSSI. ++// It selects antenna with better receiving power and returns better scan result. ++// ++#define TP_MODE 0 ++#define RSSI_MODE 1 ++#define TRAFFIC_LOW 0 ++#define TRAFFIC_HIGH 1 ++ ++ ++//============================================================ ++//3 Tx Power Tracking ++//3============================================================ ++#define DPK_DELTA_MAPPING_NUM 13 ++#define index_mapping_HP_NUM 15 ++ ++ ++//============================================================ ++//3 PSD Handler ++//3============================================================ ++ ++#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD ++#define MODE_40M 0 //0:20M, 1:40M ++#define PSD_TH2 3 ++#define PSD_CHMIN 20 // Minimum channel number for BT AFH ++#define SIR_STEP_SIZE 3 ++#define Smooth_Size_1 5 ++#define Smooth_TH_1 3 ++#define Smooth_Size_2 10 ++#define Smooth_TH_2 4 ++#define Smooth_Size_3 20 ++#define Smooth_TH_3 4 ++#define Smooth_Step_Size 5 ++#define Adaptive_SIR 1 ++#if(RTL8723_FPGA_VERIFICATION == 1) ++#define PSD_RESCAN 1 ++#else ++#define PSD_RESCAN 4 ++#endif ++#define PSD_SCAN_INTERVAL 700 //ms ++ ++ ++ ++//8723A High Power IGI Setting ++#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 ++#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 ++#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a ++#define DM_DIG_LOW_PWR_THRESHOLD 0x14 ++ ++//ANT Test ++#define ANTTESTALL 0x00 //Ant A or B will be Testing ++#define ANTTESTA 0x01 //Ant A will be Testing ++#define ANTTESTB 0x02 //Ant B will be testing ++ ++// LPS define ++#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps ++#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps ++#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps ++#define RSSI_OFFSET_DIG 0x05; ++ ++//ANT Test ++#define ANTTESTALL 0x00 //Ant A or B will be Testing ++#define ANTTESTA 0x01 //Ant A will be Testing ++#define ANTTESTB 0x02 //Ant B will be testing ++ ++ ++//============================================================ ++// structure and define ++//============================================================ ++ ++// ++// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. ++// We need to remove to other position??? ++// ++#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++typedef struct rtl8192cd_priv { ++ u1Byte temp; ++ ++}rtl8192cd_priv, *prtl8192cd_priv; ++#endif ++ ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++typedef struct _ADAPTER{ ++ u1Byte temp; ++ #ifdef AP_BUILD_WORKAROUND ++ HAL_DATA_TYPE* temp2; ++ prtl8192cd_priv priv; ++ #endif ++}ADAPTER, *PADAPTER; ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ ++typedef struct _WLAN_STA{ ++ u1Byte temp; ++} WLAN_STA, *PRT_WLAN_STA; ++ ++#endif ++ ++typedef struct _Dynamic_Initial_Gain_Threshold_ ++{ ++ u1Byte Dig_Enable_Flag; ++ u1Byte Dig_Ext_Port_Stage; ++ ++ int RssiLowThresh; ++ int RssiHighThresh; ++ ++ u4Byte FALowThresh; ++ u4Byte FAHighThresh; ++ ++ u1Byte CurSTAConnectState; ++ u1Byte PreSTAConnectState; ++ u1Byte CurMultiSTAConnectState; ++ ++ u1Byte PreIGValue; ++ u1Byte CurIGValue; ++ u1Byte BT30_CurIGI; ++ u1Byte BackupIGValue; ++ ++ s1Byte BackoffVal; ++ s1Byte BackoffVal_range_max; ++ s1Byte BackoffVal_range_min; ++ u1Byte rx_gain_range_max; ++ u1Byte rx_gain_range_min; ++ u1Byte Rssi_val_min; ++ ++ u1Byte PreCCK_CCAThres; ++ u1Byte CurCCK_CCAThres; ++ u1Byte PreCCKPDState; ++ u1Byte CurCCKPDState; ++ ++ u1Byte LargeFAHit; ++ u1Byte ForbiddenIGI; ++ u4Byte Recover_cnt; ++ ++ u1Byte DIG_Dynamic_MIN_0; ++ u1Byte DIG_Dynamic_MIN_1; ++ BOOLEAN bMediaConnect_0; ++ BOOLEAN bMediaConnect_1; ++ ++ u4Byte AntDiv_RSSI_max; ++ u4Byte RSSI_max; ++}DIG_T,*pDIG_T; ++ ++typedef struct _Dynamic_Power_Saving_ ++{ ++ u1Byte PreCCAState; ++ u1Byte CurCCAState; ++ ++ u1Byte PreRFState; ++ u1Byte CurRFState; ++ ++ int Rssi_val_min; ++ ++ u1Byte initialize; ++ u4Byte Reg874,RegC70,Reg85C,RegA74; ++ ++}PS_T,*pPS_T; ++ ++typedef struct _FALSE_ALARM_STATISTICS{ ++ u4Byte Cnt_Parity_Fail; ++ u4Byte Cnt_Rate_Illegal; ++ u4Byte Cnt_Crc8_fail; ++ u4Byte Cnt_Mcs_fail; ++ u4Byte Cnt_Ofdm_fail; ++ u4Byte Cnt_Cck_fail; ++ u4Byte Cnt_all; ++ u4Byte Cnt_Fast_Fsync; ++ u4Byte Cnt_SB_Search_fail; ++ u4Byte Cnt_OFDM_CCA; ++ u4Byte Cnt_CCK_CCA; ++ u4Byte Cnt_CCA_all; ++ u4Byte Cnt_BW_USC; //Gary ++ u4Byte Cnt_BW_LSC; //Gary ++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; ++ ++typedef struct _Dynamic_Primary_CCA{ ++ u1Byte PriCCA_flag; ++ u1Byte intf_flag; ++ u1Byte intf_type; ++ u1Byte DupRTS_flag; ++ u1Byte Monitor_flag; ++}Pri_CCA_T, *pPri_CCA_T; ++ ++typedef struct _RX_High_Power_ ++{ ++ u1Byte RXHP_flag; ++ u1Byte PSD_func_trigger; ++ u1Byte PSD_bitmap_RXHP[80]; ++ u1Byte Pre_IGI; ++ u1Byte Cur_IGI; ++ u1Byte Pre_pw_th; ++ u1Byte Cur_pw_th; ++ BOOLEAN First_time_enter; ++ BOOLEAN RXHP_enable; ++ u1Byte TP_Mode; ++ RT_TIMER PSDTimer; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ #if USE_WORKITEM ++ RT_WORK_ITEM PSDTimeWorkitem; ++ #endif ++#endif ++ ++}RXHP_T, *pRXHP_T; ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) ++#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[]. ++#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM ++ ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#define ASSOCIATE_ENTRY_NUM NUM_STAT ++#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1 ++ ++#else ++// ++// 2012/01/12 MH Revise for compatiable with other SW team. ++// 0 is for STA 1-n is for AP clients. ++// ++#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one ++#endif ++ ++//#ifdef CONFIG_ANTENNA_DIVERSITY ++// This indicates two different the steps. ++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. ++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK ++// with original RSSI to determine if it is necessary to switch antenna. ++#define SWAW_STEP_PEAK 0 ++#define SWAW_STEP_DETERMINE 1 ++ ++#define TP_MODE 0 ++#define RSSI_MODE 1 ++#define TRAFFIC_LOW 0 ++#define TRAFFIC_HIGH 1 ++ ++typedef struct _SW_Antenna_Switch_ ++{ ++ u1Byte try_flag; ++ s4Byte PreRSSI; ++ u1Byte CurAntenna; ++ u1Byte PreAntenna; ++ u1Byte RSSI_Trying; ++ u1Byte TestMode; ++ u1Byte bTriggerAntennaSwitch; ++ u1Byte SelectAntennaMap; ++ u1Byte RSSI_target; ++ ++ // Before link Antenna Switch check ++ u1Byte SWAS_NoLink_State; ++ u4Byte SWAS_NoLink_BK_Reg860; ++ BOOLEAN ANTA_ON; //To indicate Ant A is or not ++ BOOLEAN ANTB_ON; //To indicate Ant B is on or not ++ ++ s4Byte RSSI_sum_A; ++ s4Byte RSSI_sum_B; ++ s4Byte RSSI_cnt_A; ++ s4Byte RSSI_cnt_B; ++ ++ u8Byte lastTxOkCnt; ++ u8Byte lastRxOkCnt; ++ u8Byte TXByteCnt_A; ++ u8Byte TXByteCnt_B; ++ u8Byte RXByteCnt_A; ++ u8Byte RXByteCnt_B; ++ u1Byte TrafficLoad; ++ RT_TIMER SwAntennaSwitchTimer; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ #if USE_WORKITEM ++ RT_WORK_ITEM SwAntennaSwitchWorkitem; ++ #endif ++#endif ++/* CE Platform use ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ _timer SwAntennaSwitchTimer; ++ u8Byte lastTxOkCnt; ++ u8Byte lastRxOkCnt; ++ u8Byte TXByteCnt_A; ++ u8Byte TXByteCnt_B; ++ u8Byte RXByteCnt_A; ++ u8Byte RXByteCnt_B; ++ u1Byte DoubleComfirm; ++ u1Byte TrafficLoad; ++ //SW Antenna Switch ++ ++ ++#endif ++*/ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; ++ u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; ++ u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; ++ u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; ++ u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; ++ u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; ++ u1Byte TxAnt[ASSOCIATE_ENTRY_NUM]; ++ u1Byte TargetSTA; ++ u1Byte antsel; ++ u1Byte RxIdleAnt; ++ ++#endif ++ ++}SWAT_T, *pSWAT_T; ++//#endif ++ ++typedef struct _EDCA_TURBO_ ++{ ++ BOOLEAN bCurrentTurboEDCA; ++ BOOLEAN bIsCurRDLState; ++ #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) ++ u4Byte prv_traffic_idx; // edca turbo ++ #endif ++ ++}EDCA_T,*pEDCA_T; ++ ++typedef struct _ODM_RATE_ADAPTIVE ++{ ++ u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver ++ u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH ++ u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW ++ u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW ++ u4Byte LastRATR; // RATR Register Content ++ ++} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; ++ ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++ ++#ifdef ADSL_AP_BUILD_WORKAROUND ++#define MAX_TOLERANCE 5 ++#define IQK_DELAY_TIME 1 //ms ++#endif ++ ++// ++// Indicate different AP vendor for IOT issue. ++// ++typedef enum _HT_IOT_PEER ++{ ++ HT_IOT_PEER_UNKNOWN = 0, ++ HT_IOT_PEER_REALTEK = 1, ++ HT_IOT_PEER_REALTEK_92SE = 2, ++ HT_IOT_PEER_BROADCOM = 3, ++ HT_IOT_PEER_RALINK = 4, ++ HT_IOT_PEER_ATHEROS = 5, ++ HT_IOT_PEER_CISCO = 6, ++ HT_IOT_PEER_MERU = 7, ++ HT_IOT_PEER_MARVELL = 8, ++ HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 ++ HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP ++ HT_IOT_PEER_AIRGO = 11, ++ HT_IOT_PEER_INTEL = 12, ++ HT_IOT_PEER_RTK_APCLIENT = 13, ++ HT_IOT_PEER_REALTEK_81XX = 14, ++ HT_IOT_PEER_REALTEK_WOW = 15, ++ HT_IOT_PEER_MAX = 16 ++}HT_IOT_PEER_E, *PHTIOT_PEER_E; ++#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++ ++ ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM_MAX 10 ++#if (RTL8192D_SUPPORT==1) ++#define IQK_BB_REG_NUM 10 ++#else ++#define IQK_BB_REG_NUM 9 ++#endif ++#define HP_THERMAL_NUM 8 ++ ++#define AVG_THERMAL_NUM 8 ++#define IQK_Matrix_REG_NUM 8 ++#define IQK_Matrix_Settings_NUM 1+24+21 ++ ++#define DM_Type_ByFW 0 ++#define DM_Type_ByDriver 1 ++ ++// ++// Declare for common info ++// ++// Declare for common info ++// ++#define MAX_PATH_NUM_92CS 2 ++ ++typedef struct _ODM_Phy_Status_Info_ ++{ ++ u1Byte RxPWDBAll; ++ u1Byte SignalQuality; // in 0-100 index. ++ u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM ++ u1Byte RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ s1Byte RxPower; // in dBm Translate from PWdB ++ s1Byte RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. ++ u1Byte BTRxRSSIPercentage; ++ u1Byte SignalStrength; // in 0-100 index. ++ u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb ++#endif ++ u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR ++}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; ++ ++ ++typedef struct _ODM_Phy_Dbg_Info_ ++{ ++ //ODM Write,debug info ++ s1Byte RxSNRdB[MAX_PATH_NUM_92CS]; ++ u8Byte NumQryPhyStatus; ++ u8Byte NumQryPhyStatusCCK; ++ u8Byte NumQryPhyStatusOFDM; ++ u1Byte NumQryBeaconPkt; ++ //Others ++ s4Byte RxEVM[MAX_PATH_NUM_92CS]; ++ ++}ODM_PHY_DBG_INFO_T; ++ ++ ++typedef struct _ODM_Per_Pkt_Info_ ++{ ++ u1Byte Rate; ++ u1Byte StationID; ++ BOOLEAN bPacketMatchBSSID; ++ BOOLEAN bPacketToSelf; ++ BOOLEAN bPacketBeacon; ++}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; ++ ++typedef struct _ODM_Mac_Status_Info_ ++{ ++ u1Byte test; ++ ++}ODM_MAC_INFO; ++ ++ ++typedef enum tag_Dynamic_ODM_Support_Ability_Type ++{ ++ // BB Team ++ ODM_DIG = 0x00000001, ++ ODM_HIGH_POWER = 0x00000002, ++ ODM_CCK_CCA_TH = 0x00000004, ++ ODM_FA_STATISTICS = 0x00000008, ++ ODM_RAMASK = 0x00000010, ++ ODM_RSSI_MONITOR = 0x00000020, ++ ODM_SW_ANTDIV = 0x00000040, ++ ODM_HW_ANTDIV = 0x00000080, ++ ODM_BB_PWRSV = 0x00000100, ++ ODM_2TPATHDIV = 0x00000200, ++ ODM_1TPATHDIV = 0x00000400, ++ ODM_PSD2AFH = 0x00000800 ++}ODM_Ability_E; ++ ++// ++// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T ++// Please declare below ODM relative info in your STA info structure. ++// ++#if 1 ++typedef struct _ODM_STA_INFO{ ++ // Driver Write ++ BOOLEAN bUsed; // record the sta status link or not? ++ //u1Byte WirelessMode; // ++ u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E ++ ++ // ODM Write ++ //1 PHY_STATUS_INFO ++ u1Byte RSSI_Path[4]; // ++ u1Byte RSSI_Ave; ++ u1Byte RXEVM[4]; ++ u1Byte RXSNR[4]; ++ ++ // ODM Write ++ //1 TX_INFO (may changed by IC) ++ //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. ++#if 0 ++ u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit ++ u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit ++ u1Byte ANTSEL_C; //only in Jagar: 4bit ++ u1Byte ANTSEL_D; //only in Jagar: 4bit ++ u1Byte TX_ANTL; //not in Jagar: 2bit ++ u1Byte TX_ANT_HT; //not in Jagar: 2bit ++ u1Byte TX_ANT_CCK; //not in Jagar: 2bit ++ u1Byte TXAGC_A; //not in Jagar: 4bit ++ u1Byte TXAGC_B; //not in Jagar: 4bit ++ u1Byte TXPWR_OFFSET; //only in Jagar: 3bit ++ u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK ++#endif ++ ++ // ++ // Please use compile flag to disabe the strcutrue for other IC except 88E. ++ // Move To lower layer. ++ // ++ // ODM Write Wilson will handle this part(said by Luke.Lee) ++ //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. ++#if 0 ++ //1 For 88E RA (don't redefine the naming) ++ u1Byte rate_id; ++ u1Byte rate_SGI; ++ u1Byte rssi_sta_ra; ++ u1Byte SGI_enable; ++ u1Byte Decision_rate; ++ u1Byte Pre_rate; ++ u1Byte Active; ++ ++ // Driver write Wilson handle. ++ //1 TX_RPT (don't redefine the naming) ++ u2Byte RTY[4]; // ??? ++ u2Byte TOTAL; // ??? ++ u2Byte DROP; // ??? ++ // ++ // Please use compile flag to disabe the strcutrue for other IC except 88E. ++ // ++#endif ++ ++}ODM_STA_INFO_T, *PODM_STA_INFO_T; ++#endif ++ ++// ++// 2011/10/20 MH Define Common info enum for all team. ++// ++typedef enum _ODM_Common_Info_Definition ++{ ++//-------------REMOVED CASE-----------// ++ //ODM_CMNINFO_CCK_HP, ++ //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? ++ //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E ++ //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E ++//-------------REMOVED CASE-----------// ++ ++ // ++ // Fixed value: ++ // ++ ++ //-----------HOOK BEFORE REG INIT-----------// ++ ODM_CMNINFO_PLATFORM = 0, ++ ODM_CMNINFO_ABILITY, // ODM_ABILITY_E ++ ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E ++ ODM_CMNINFO_MP_TEST_CHIP, ++ ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E ++ ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E ++ ODM_CMNINFO_FAB_VER, // ODM_FAB_E ++ ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? ++ ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E ++ ODM_CMNINFO_EXT_LNA, // TRUE ++ ODM_CMNINFO_EXT_PA, ++ ODM_CMNINFO_EXT_TRSW, ++ ODM_CMNINFO_PATCH_ID, //CUSTOMER ID ++ ODM_CMNINFO_BINHCT_TEST, ++ ODM_CMNINFO_BWIFI_TEST, ++ ODM_CMNINFO_SMART_CONCURRENT, ++ //-----------HOOK BEFORE REG INIT-----------// ++ ++ ++ // ++ // Dynamic value: ++ // ++//--------- POINTER REFERENCE-----------// ++ ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E ++ ODM_CMNINFO_TX_UNI, ++ ODM_CMNINFO_RX_UNI, ++ ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E ++ ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E ++ ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E ++ ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E ++ ODM_CMNINFO_BW, // ODM_BW_E ++ ODM_CMNINFO_CHNL, ++ ++ ODM_CMNINFO_DMSP_GET_VALUE, ++ ODM_CMNINFO_BUDDY_ADAPTOR, ++ ODM_CMNINFO_DMSP_IS_MASTER, ++ ODM_CMNINFO_SCAN, ++ ODM_CMNINFO_POWER_SAVING, ++ ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E ++ ODM_CMNINFO_DRV_STOP, ++ ODM_CMNINFO_PNP_IN, ++ ODM_CMNINFO_INIT_ON, ++ ODM_CMNINFO_ANT_TEST, ++ ODM_CMNINFO_NET_CLOSED, ++ ODM_CMNINFO_MP_MODE, ++//--------- POINTER REFERENCE-----------// ++ ++//------------CALL BY VALUE-------------// ++ ODM_CMNINFO_WIFI_DIRECT, ++ ODM_CMNINFO_WIFI_DISPLAY, ++ ODM_CMNINFO_LINK, ++ ODM_CMNINFO_RSSI_MIN, ++ ODM_CMNINFO_DBG_COMP, // u8Byte ++ ODM_CMNINFO_DBG_LEVEL, // u4Byte ++ ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte ++ ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte ++ ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte ++ ODM_CMNINFO_BT_DISABLED, ++ ODM_CMNINFO_BT_OPERATION, ++ ODM_CMNINFO_BT_DIG, ++ ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil ++ ODM_CMNINFO_BT_DISABLE_EDCA, ++ ODM_CMNINFO_STATION_STATE, ++//------------CALL BY VALUE-------------// ++ ++ // ++ // Dynamic ptr array hook itms. ++ // ++ ODM_CMNINFO_STA_STATUS, ++ ODM_CMNINFO_PHY_STATUS, ++ ODM_CMNINFO_MAC_STATUS, ++ ++ ODM_CMNINFO_MAX, ++ ++ ++}ODM_CMNINFO_E; ++ ++// ++// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY ++// ++typedef enum _ODM_Support_Ability_Definition ++{ ++ // ++ // BB ODM section BIT 0-15 ++ // ++ ODM_BB_DIG = BIT0, ++ ODM_BB_RA_MASK = BIT1, ++ ODM_BB_DYNAMIC_TXPWR = BIT2, ++ ODM_BB_FA_CNT = BIT3, ++ ODM_BB_RSSI_MONITOR = BIT4, ++ ODM_BB_CCK_PD = BIT5, ++ ODM_BB_ANT_DIV = BIT6, ++ ODM_BB_PWR_SAVE = BIT7, ++ ODM_BB_PWR_TRAIN = BIT8, ++ ODM_BB_RATE_ADAPTIVE = BIT9, ++ ODM_BB_PATH_DIV = BIT10, ++ ODM_BB_PSD = BIT11, ++ ODM_BB_RXHP = BIT12, ++ ODM_BB_ADAPTIVITY = BIT13, ++ ODM_BB_DYNAMIC_ATC = BIT14, ++ ++ // ++ // MAC DM section BIT 16-23 ++ // ++ ODM_MAC_EDCA_TURBO = BIT16, ++ ODM_MAC_EARLY_MODE = BIT17, ++ ++ // ++ // RF ODM section BIT 24-31 ++ // ++ ODM_RF_TX_PWR_TRACK = BIT24, ++ ODM_RF_RX_GAIN_TRACK = BIT25, ++ ODM_RF_CALIBRATION = BIT26, ++ ++}ODM_ABILITY_E; ++ ++// ODM_CMNINFO_INTERFACE ++typedef enum tag_ODM_Support_Interface_Definition ++{ ++ ODM_ITRF_PCIE = 0x1, ++ ODM_ITRF_USB = 0x2, ++ ODM_ITRF_SDIO = 0x4, ++ ODM_ITRF_ALL = 0x7, ++}ODM_INTERFACE_E; ++ ++// ODM_CMNINFO_IC_TYPE ++typedef enum tag_ODM_Support_IC_Type_Definition ++{ ++ ODM_RTL8192S = BIT0, ++ ODM_RTL8192C = BIT1, ++ ODM_RTL8192D = BIT2, ++ ODM_RTL8723A = BIT3, ++ ODM_RTL8188E = BIT4, ++ ODM_RTL8812 = BIT5, ++ ODM_RTL8821 = BIT6, ++ ODM_RTL8192E = BIT7, ++ ODM_RTL8723B = BIT8, ++ ODM_RTL8813A = BIT9, ++ ODM_RTL8881A = BIT10 ++}ODM_IC_TYPE_E; ++ ++#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) ++#define ODM_IC_11AC_SERIES (ODM_RTL8812) ++ ++//ODM_CMNINFO_CUT_VER ++typedef enum tag_ODM_Cut_Version_Definition ++{ ++ ODM_CUT_A = 1, ++ ODM_CUT_B = 2, ++ ODM_CUT_C = 3, ++ ODM_CUT_D = 4, ++ ODM_CUT_E = 5, ++ ODM_CUT_F = 6, ++ ODM_CUT_TEST = 7, ++}ODM_CUT_VERSION_E; ++ ++// ODM_CMNINFO_FAB_VER ++typedef enum tag_ODM_Fab_Version_Definition ++{ ++ ODM_TSMC = 0, ++ ODM_UMC = 1, ++}ODM_FAB_E; ++ ++// ODM_CMNINFO_RF_TYPE ++// ++// For example 1T2R (A+AB = BIT0|BIT4|BIT5) ++// ++typedef enum tag_ODM_RF_Path_Bit_Definition ++{ ++ ODM_RF_TX_A = BIT0, ++ ODM_RF_TX_B = BIT1, ++ ODM_RF_TX_C = BIT2, ++ ODM_RF_TX_D = BIT3, ++ ODM_RF_RX_A = BIT4, ++ ODM_RF_RX_B = BIT5, ++ ODM_RF_RX_C = BIT6, ++ ODM_RF_RX_D = BIT7, ++}ODM_RF_PATH_E; ++ ++ ++typedef enum tag_ODM_RF_Type_Definition ++{ ++ ODM_1T1R = 0, ++ ODM_1T2R = 1, ++ ODM_2T2R = 2, ++ ODM_2T3R = 3, ++ ODM_2T4R = 4, ++ ODM_3T3R = 5, ++ ODM_3T4R = 6, ++ ODM_4T4R = 7, ++}ODM_RF_TYPE_E; ++ ++ ++// ++// ODM Dynamic common info value definition ++// ++ ++//typedef enum _MACPHY_MODE_8192D{ ++// SINGLEMAC_SINGLEPHY, ++// DUALMAC_DUALPHY, ++// DUALMAC_SINGLEPHY, ++//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; ++// Above is the original define in MP driver. Please use the same define. THX. ++typedef enum tag_ODM_MAC_PHY_Mode_Definition ++{ ++ ODM_SMSP = 0, ++ ODM_DMSP = 1, ++ ODM_DMDP = 2, ++}ODM_MAC_PHY_MODE_E; ++ ++ ++typedef enum tag_BT_Coexist_Definition ++{ ++ ODM_BT_BUSY = 1, ++ ODM_BT_ON = 2, ++ ODM_BT_OFF = 3, ++ ODM_BT_NONE = 4, ++}ODM_BT_COEXIST_E; ++ ++// ODM_CMNINFO_OP_MODE ++typedef enum tag_Operation_Mode_Definition ++{ ++ ODM_NO_LINK = BIT0, ++ ODM_LINK = BIT1, ++ ODM_SCAN = BIT2, ++ ODM_POWERSAVE = BIT3, ++ ODM_AP_MODE = BIT4, ++ ODM_CLIENT_MODE = BIT5, ++ ODM_AD_HOC = BIT6, ++ ODM_WIFI_DIRECT = BIT7, ++ ODM_WIFI_DISPLAY = BIT8, ++}ODM_OPERATION_MODE_E; ++ ++// ODM_CMNINFO_WM_MODE ++typedef enum tag_Wireless_Mode_Definition ++{ ++ ODM_WM_UNKNOW = 0x0, ++ ODM_WM_B = BIT0, ++ ODM_WM_G = BIT1, ++ ODM_WM_A = BIT2, ++ ODM_WM_N24G = BIT3, ++ ODM_WM_N5G = BIT4, ++ ODM_WM_AUTO = BIT5, ++ ODM_WM_AC = BIT6, ++}ODM_WIRELESS_MODE_E; ++ ++// ODM_CMNINFO_BAND ++typedef enum tag_Band_Type_Definition ++{ ++ ODM_BAND_2_4G = BIT0, ++ ODM_BAND_5G = BIT1, ++ ++}ODM_BAND_TYPE_E; ++ ++// ODM_CMNINFO_SEC_CHNL_OFFSET ++typedef enum tag_Secondary_Channel_Offset_Definition ++{ ++ ODM_DONT_CARE = 0, ++ ODM_BELOW = 1, ++ ODM_ABOVE = 2 ++}ODM_SEC_CHNL_OFFSET_E; ++ ++// ODM_CMNINFO_SEC_MODE ++typedef enum tag_Security_Definition ++{ ++ ODM_SEC_OPEN = 0, ++ ODM_SEC_WEP40 = 1, ++ ODM_SEC_TKIP = 2, ++ ODM_SEC_RESERVE = 3, ++ ODM_SEC_AESCCMP = 4, ++ ODM_SEC_WEP104 = 5, ++ ODM_WEP_WPA_MIXED = 6, // WEP + WPA ++ ODM_SEC_SMS4 = 7, ++}ODM_SECURITY_E; ++ ++// ODM_CMNINFO_BW ++typedef enum tag_Bandwidth_Definition ++{ ++ ODM_BW20M = 0, ++ ODM_BW40M = 1, ++ ODM_BW80M = 2, ++ ODM_BW160M = 3, ++ ODM_BW10M = 4, ++}ODM_BW_E; ++ ++// ODM_CMNINFO_CHNL ++ ++// ODM_CMNINFO_BOARD_TYPE ++#if 1 ++typedef enum tag_Board_Definition ++{ ++ ODM_BOARD_DEFAULT = 0, // The DEFAULT case. ++ ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. ++ ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card ++ ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT ++ ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA ++ ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA ++ ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW ++ ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA ++ ODM_BOARD_EXT_LNA_5G = BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA ++}ODM_BOARD_TYPE_E; ++#else ++typedef enum tag_Board_Definition ++{ ++ ODM_BOARD_NORMAL = 0, ++ ODM_BOARD_HIGHPWR = 1, ++ ODM_BOARD_MINICARD = 2, ++ ODM_BOARD_SLIM = 3, ++ ODM_BOARD_COMBO = 4, ++ ++}ODM_BOARD_TYPE_E; ++#endif ++ ++ ++ ++// ODM_CMNINFO_ONE_PATH_CCA ++typedef enum tag_CCA_Path ++{ ++ ODM_CCA_2R = 0, ++ ODM_CCA_1R_A = 1, ++ ODM_CCA_1R_B = 2, ++}ODM_CCA_PATH_E; ++ ++ ++typedef struct _ODM_RA_Info_ ++{ ++ u1Byte RateID; ++ u4Byte RateMask; ++ u4Byte RAUseRate; ++ u1Byte RateSGI; ++ u1Byte RssiStaRA; ++ u1Byte PreRssiStaRA; ++ u1Byte SGIEnable; ++ u1Byte DecisionRate; ++ u1Byte PreRate; ++ u1Byte HighestRate; ++ u1Byte LowestRate; ++ u4Byte NscUp; ++ u4Byte NscDown; ++ u2Byte RTY[5]; ++ u4Byte TOTAL; ++ u2Byte DROP;//Retry over or drop ++ u2Byte DROP1;//LifeTime over ++ u1Byte Active; ++ u2Byte RptTime; ++ u1Byte RAWaitingCounter; ++ u1Byte RAPendingCounter; ++#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! ++ u1Byte PTActive; // on or off ++ u1Byte PTTryState; // 0 trying state, 1 for decision state ++ u1Byte PTStage; // 0~6 ++ u1Byte PTStopCount; //Stop PT counter ++ u1Byte PTPreRate; // if rate change do PT ++ u1Byte PTPreRssi; // if RSSI change 5% do PT ++ u1Byte PTModeSS; // decide whitch rate should do PT ++ u1Byte RAstage; // StageRA, decide how many times RA will be done between PT ++ u1Byte PTSmoothFactor; ++#endif ++} ODM_RA_INFO_T,*PODM_RA_INFO_T; ++ ++typedef struct _IQK_MATRIX_REGS_SETTING{ ++ BOOLEAN bIQKDone; ++ s4Byte Value[1][IQK_Matrix_REG_NUM]; ++}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; ++ ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++typedef struct _PathDiv_Parameter_define_ ++{ ++ u4Byte org_5g_RegE30; ++ u4Byte org_5g_RegC14; ++ u4Byte org_5g_RegCA0; ++ u4Byte swt_5g_RegE30; ++ u4Byte swt_5g_RegC14; ++ u4Byte swt_5g_RegCA0; ++ //for 2G IQK information ++ u4Byte org_2g_RegC80; ++ u4Byte org_2g_RegC4C; ++ u4Byte org_2g_RegC94; ++ u4Byte org_2g_RegC14; ++ u4Byte org_2g_RegCA0; ++ ++ u4Byte swt_2g_RegC80; ++ u4Byte swt_2g_RegC4C; ++ u4Byte swt_2g_RegC94; ++ u4Byte swt_2g_RegC14; ++ u4Byte swt_2g_RegCA0; ++}PATHDIV_PARA,*pPATHDIV_PARA; ++#endif ++ ++ ++typedef struct ODM_RF_Calibration_Structure ++{ ++ //for tx power tracking ++ ++ u4Byte RegA24; // for TempCCK ++ s4Byte RegE94; ++ s4Byte RegE9C; ++ s4Byte RegEB4; ++ s4Byte RegEBC; ++ ++ //u1Byte bTXPowerTracking; ++ u1Byte TXPowercount; ++ BOOLEAN bTXPowerTrackingInit; ++ BOOLEAN bTXPowerTracking; ++ u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u1Byte TM_Trigger; ++ u1Byte InternalPA5G[2]; //pathA / pathB ++ ++ u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u1Byte ThermalValue; ++ u1Byte ThermalValue_LCK; ++ u1Byte ThermalValue_IQK; ++ u1Byte ThermalValue_DPK; ++ u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; ++ u1Byte ThermalValue_AVG_index; ++ u1Byte ThermalValue_RxGain; ++ u1Byte ThermalValue_Crystal; ++ u1Byte ThermalValue_DPKstore; ++ u1Byte ThermalValue_DPKtrack; ++ BOOLEAN TxPowerTrackingInProgress; ++ BOOLEAN bDPKenable; ++ ++ BOOLEAN bReloadtxpowerindex; ++ u1Byte bRfPiEnable; ++ u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u1Byte bCCKinCH14; ++ u1Byte CCK_index; ++ u1Byte OFDM_index[2]; ++ BOOLEAN bDoneTxpower; ++ s1Byte PowerIndexOffset; ++ s1Byte DeltaPowerIndex; ++ s1Byte DeltaPowerIndexLast; ++ BOOLEAN bTxPowerChanged; ++ ++ u1Byte ThermalValue_HP[HP_THERMAL_NUM]; ++ u1Byte ThermalValue_HP_index; ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; ++ ++ u1Byte Delta_IQK; ++ u1Byte Delta_LCK; ++ ++ //for IQK ++ u4Byte RegC04; ++ u4Byte Reg874; ++ u4Byte RegC08; ++ u4Byte RegB68; ++ u4Byte RegB6C; ++ u4Byte Reg870; ++ u4Byte Reg860; ++ u4Byte Reg864; ++ ++ BOOLEAN bIQKInitialized; ++ BOOLEAN bLCKInProgress; ++ BOOLEAN bAntennaDetected; ++ u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; ++ u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u4Byte IQK_BB_backup_recover[9]; ++ u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; ++ ++ //for APK ++ u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u1Byte bAPKdone; ++ u1Byte bAPKThermalMeterIgnore; ++ u1Byte bDPdone; ++ u1Byte bDPPathAOK; ++ u1Byte bDPPathBOK; ++}ODM_RF_CAL_T,*PODM_RF_CAL_T; ++// ++// ODM Dynamic common info value definition ++// ++ ++typedef struct _FAST_ANTENNA_TRAINNING_ ++{ ++ u1Byte Bssid[6]; ++ u1Byte antsel_rx_keep_0; ++ u1Byte antsel_rx_keep_1; ++ u1Byte antsel_rx_keep_2; ++ u4Byte antSumRSSI[7]; ++ u4Byte antRSSIcnt[7]; ++ u4Byte antAveRSSI[7]; ++ u1Byte FAT_State; ++ u4Byte TrainIdx; ++ u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; ++ u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; ++ u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; ++ u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; ++ u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; ++ u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; ++ u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; ++ u1Byte RxIdleAnt; ++ BOOLEAN bBecomeLinked; ++ ++}FAT_T,*pFAT_T; ++ ++typedef enum _FAT_STATE ++{ ++ FAT_NORMAL_STATE = 0, ++ FAT_TRAINING_STATE = 1, ++}FAT_STATE_E, *PFAT_STATE_E; ++ ++typedef enum _ANT_DIV_TYPE ++{ ++ NO_ANTDIV = 0xFF, ++ CG_TRX_HW_ANTDIV = 0x01, ++ CGCS_RX_HW_ANTDIV = 0x02, ++ FIXED_HW_ANTDIV = 0x03, ++ CG_TRX_SMART_ANTDIV = 0x04, ++ CGCS_RX_SW_ANTDIV = 0x05, ++ ++}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++// ++// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. ++// ++#if(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#if (RT_PLATFORM != PLATFORM_LINUX) ++typedef ++#endif ++struct DM_Out_Source_Dynamic_Mechanism_Structure ++#else// for AP,ADSL,CE Team ++typedef struct DM_Out_Source_Dynamic_Mechanism_Structure ++#endif ++{ ++ //RT_TIMER FastAntTrainingTimer; ++ // ++ // Add for different team use temporarily ++ // ++ PADAPTER Adapter; // For CE/NIC team ++ prtl8192cd_priv priv; // For AP/ADSL team ++ // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. ++ BOOLEAN odm_ready; ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ rtl8192cd_priv fake_priv; ++#endif ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ // ADSL_AP_BUILD_WORKAROUND ++ ADAPTER fake_adapter; ++#endif ++ ++ u8Byte DebugComponents; ++ u4Byte DebugLevel; ++ ++//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// ++ BOOLEAN bCckHighPower; ++ u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE ++ u1Byte ControlChannel; ++//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// ++ ++//--------REMOVED COMMON INFO----------// ++ //u1Byte PseudoMacPhyMode; ++ //BOOLEAN *BTCoexist; ++ //BOOLEAN PseudoBtCoexist; ++ //u1Byte OPMode; ++ //BOOLEAN bAPMode; ++ //BOOLEAN bClientMode; ++ //BOOLEAN bAdHocMode; ++ //BOOLEAN bSlaveOfDMSP; ++//--------REMOVED COMMON INFO----------// ++ ++ ++//1 COMMON INFORMATION ++ ++ // ++ // Init Value ++ // ++//-----------HOOK BEFORE REG INIT-----------// ++ // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 ++ u1Byte SupportPlatform; ++ // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K ++ u4Byte SupportAbility; ++ // ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 ++ u1Byte SupportInterface; ++ // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... ++ u4Byte SupportICType; ++ // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... ++ u1Byte CutVersion; ++ // Fab Version TSMC/UMC = 0/1 ++ u1Byte FabVersion; ++ // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... ++ u1Byte RFType; ++ // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... ++ u1Byte BoardType; ++ // with external LNA NO/Yes = 0/1 ++ u1Byte ExtLNA; ++ // with external PA NO/Yes = 0/1 ++ u1Byte ExtPA; ++ // with external TRSW NO/Yes = 0/1 ++ u1Byte ExtTRSW; ++ u1Byte PatchID; //Customer ID ++ BOOLEAN bInHctTest; ++ BOOLEAN bWIFITest; ++ ++ BOOLEAN bDualMacSmartConcurrent; ++ u4Byte BK_SupportAbility; ++ u1Byte AntDivType; ++//-----------HOOK BEFORE REG INIT-----------// ++ ++ // ++ // Dynamic Value ++ // ++//--------- POINTER REFERENCE-----------// ++ ++ u1Byte u1Byte_temp; ++ BOOLEAN BOOLEAN_temp; ++ PADAPTER PADAPTER_temp; ++ ++ // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 ++ u1Byte *pMacPhyMode; ++ //TX Unicast byte count ++ u8Byte *pNumTxBytesUnicast; ++ //RX Unicast byte count ++ u8Byte *pNumRxBytesUnicast; ++ // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 ++ u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E ++ // Frequence band 2.4G/5G = 0/1 ++ u1Byte *pBandType; ++ // Secondary channel offset don't_care/below/above = 0/1/2 ++ u1Byte *pSecChOffset; ++ // Security mode Open/WEP/AES/TKIP = 0/1/2/3 ++ u1Byte *pSecurity; ++ // BW info 20M/40M/80M = 0/1/2 ++ u1Byte *pBandWidth; ++ // Central channel location Ch1/Ch2/.... ++ u1Byte *pChannel; //central channel number ++ // Common info for 92D DMSP ++ ++ BOOLEAN *pbGetValueFromOtherMac; ++ PADAPTER *pBuddyAdapter; ++ BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave ++ // Common info for Status ++ BOOLEAN *pbScanInProcess; ++ BOOLEAN *pbPowerSaving; ++ // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. ++ u1Byte *pOnePathCCA; ++ //pMgntInfo->AntennaTest ++ u1Byte *pAntennaTest; ++ BOOLEAN *pbNet_closed; ++//--------- POINTER REFERENCE-----------// ++ // ++//------------CALL BY VALUE-------------// ++ BOOLEAN bLinkInProcess; ++ BOOLEAN bWIFI_Direct; ++ BOOLEAN bWIFI_Display; ++ BOOLEAN bLinked; ++ BOOLEAN bsta_state; ++ u1Byte RSSI_Min; ++ u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1 ++ BOOLEAN bIsMPChip; ++ BOOLEAN bOneEntryOnly; ++ // Common info for BTDM ++ BOOLEAN bBtDisabled; // BT is disabled ++ BOOLEAN bBtConnectProcess; // BT HS is under connection progress. ++ u1Byte btHsRssi; // BT HS mode wifi rssi value. ++ BOOLEAN bBtHsOperation; // BT HS mode is under progress ++ u1Byte btHsDigVal; // use BT rssi to decide the DIG value ++ BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo ++ BOOLEAN bBtLimitedDig; // BT is busy. ++//------------CALL BY VALUE-------------// ++ u1Byte RSSI_A; ++ u1Byte RSSI_B; ++ u8Byte RSSI_TRSW; ++ u8Byte RSSI_TRSW_H; ++ u8Byte RSSI_TRSW_L; ++ u8Byte RSSI_TRSW_iso; ++ ++ u1Byte RxRate; ++ BOOLEAN StopDIG; ++ u1Byte TxRate; ++ u1Byte LinkedInterval; ++ u1Byte preChannel; ++ u4Byte TxagcOffsetValueA; ++ BOOLEAN IsTxagcOffsetPositiveA; ++ u4Byte TxagcOffsetValueB; ++ BOOLEAN IsTxagcOffsetPositiveB; ++ u8Byte lastTxOkCnt; ++ u8Byte lastRxOkCnt; ++ u4Byte BbSwingOffsetA; ++ BOOLEAN IsBbSwingOffsetPositiveA; ++ u4Byte BbSwingOffsetB; ++ BOOLEAN IsBbSwingOffsetPositiveB; ++ s1Byte TH_L2H_ini; ++ s1Byte TH_EDCCA_HL_diff; ++ u4Byte IGI_Base; ++ u4Byte IGI_target; ++ BOOLEAN ForceEDCCA; ++ u1Byte AdapEn_RSSI; ++ u1Byte AntType; ++ u1Byte antdiv_rssi; ++ u1Byte antdiv_period; ++ u4Byte Force_TH_H; ++ u4Byte Force_TH_L; ++ u1Byte IGI_LowerBound; ++ ++ //2 Define STA info. ++ // _ODM_STA_INFO ++ // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? ++ PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; ++ ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ u2Byte CurrminRptTime; ++ ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 ++#endif ++ // ++ // 2012/02/14 MH Add to share 88E ra with other SW team. ++ // We need to colelct all support abilit to a proper area. ++ // ++ BOOLEAN RaSupport88E; ++ ++ // Define ........... ++ ++ // Latest packet phy info (ODM write) ++ ODM_PHY_DBG_INFO_T PhyDbgInfo; ++ //PHY_INFO_88E PhyInfo; ++ ++ // Latest packet phy info (ODM write) ++ ODM_MAC_INFO *pMacInfo; ++ //MAC_INFO_88E MacInfo; ++ ++ // Different Team independt structure?? ++ ++ // ++ //TX_RTP_CMN TX_retrpo; ++ //TX_RTP_88E TX_retrpo; ++ //TX_RTP_8195 TX_retrpo; ++ ++ // ++ //ODM Structure ++ // ++ FAT_T DM_FatTable; ++ DIG_T DM_DigTable; ++ PS_T DM_PSTable; ++ Pri_CCA_T DM_PriCCA; ++ RXHP_T DM_RXHP_Table; ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; ++ //#ifdef CONFIG_ANTENNA_DIVERSITY ++ SWAT_T DM_SWAT_Table; ++ BOOLEAN RSSI_test; ++ //#endif ++ ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++ //Path Div Struct ++ PATHDIV_PARA pathIQK; ++#endif ++ ++ EDCA_T DM_EDCA_Table; ++ u4Byte WMMEDCA_BE; ++ // Copy from SD4 structure ++ // ++ // ================================================== ++ // ++ ++ //common ++ //u1Byte DM_Type; ++ //u1Byte PSD_Report_RXHP[80]; // Add By Gary ++ //u1Byte PSD_func_flag; // Add By Gary ++ //for DIG ++ //u1Byte bDMInitialGainEnable; ++ //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. ++ //for Antenna diversity ++ //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse ++ //PSTA_INFO_T RSSI_target; ++ ++ BOOLEAN *pbDriverStopped; ++ BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; ++ BOOLEAN *pinit_adpt_in_progress; ++ ++ //PSD ++ BOOLEAN bUserAssignLevel; ++ RT_TIMER PSDTimer; ++ u1Byte RSSI_BT; //come from BT ++ BOOLEAN bPSDinProcess; ++ BOOLEAN bDMInitialGainEnable; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u1Byte bUseRAMask; ++ ++ ODM_RATE_ADAPTIVE RateAdaptive; ++ ++ ++ ODM_RF_CAL_T RFCalibrateInfo; ++ ++ // ++ // TX power tracking ++ // ++ u1Byte BbSwingIdxOfdm; ++ u1Byte BbSwingIdxOfdmCurrent; ++ u1Byte BbSwingIdxOfdmBase; ++ BOOLEAN BbSwingFlagOfdm; ++ u1Byte BbSwingIdxCck; ++ u1Byte BbSwingIdxCckCurrent; ++ u1Byte BbSwingIdxCckBase; ++ u1Byte DefaultOfdmIndex; ++ u1Byte DefaultCckIndex; ++ BOOLEAN BbSwingFlagCck; ++ ++ ++ u1Byte *mp_mode; ++ // ++ // ODM system resource. ++ // ++ ++ // ODM relative time. ++ RT_TIMER PathDivSwitchTimer; ++ //2011.09.27 add for Path Diversity ++ RT_TIMER CCKPathDiversityTimer; ++ RT_TIMER FastAntTrainingTimer; ++ ++ // ODM relative workitem. ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ #if USE_WORKITEM ++ RT_WORK_ITEM PathDivSwitchWorkitem; ++ RT_WORK_ITEM CCKPathDiversityWorkitem; ++ RT_WORK_ITEM FastAntTrainingWorkitem; ++ #endif ++#endif ++ ++#if(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ ++#if (RT_PLATFORM != PLATFORM_LINUX) ++} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure ++#else ++}; ++#endif ++ ++#else// for AP,ADSL,CE Team ++} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure ++#endif ++ ++ ++ ++#if 1 //92c-series ++#define ODM_RF_PATH_MAX 2 ++#else //jaguar - series ++#define ODM_RF_PATH_MAX 4 ++#endif ++ ++typedef enum _ODM_RF_RADIO_PATH { ++ ODM_RF_PATH_A = 0, //Radio Path A ++ ODM_RF_PATH_B = 1, //Radio Path B ++ ODM_RF_PATH_C = 2, //Radio Path C ++ ODM_RF_PATH_D = 3, //Radio Path D ++ // ODM_RF_PATH_MAX, //Max RF number 90 support ++} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; ++ ++ typedef enum _ODM_RF_CONTENT{ ++ odm_radioa_txt = 0x1000, ++ odm_radiob_txt = 0x1001, ++ odm_radioc_txt = 0x1002, ++ odm_radiod_txt = 0x1003 ++} ODM_RF_CONTENT; ++ ++typedef enum _ODM_BB_Config_Type{ ++ CONFIG_BB_PHY_REG, ++ CONFIG_BB_AGC_TAB, ++ CONFIG_BB_AGC_TAB_2G, ++ CONFIG_BB_AGC_TAB_5G, ++ CONFIG_BB_PHY_REG_PG, ++} ODM_BB_Config_Type, *PODM_BB_Config_Type; ++ ++// Status code ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++typedef enum _RT_STATUS{ ++ RT_STATUS_SUCCESS, ++ RT_STATUS_FAILURE, ++ RT_STATUS_PENDING, ++ RT_STATUS_RESOURCE, ++ RT_STATUS_INVALID_CONTEXT, ++ RT_STATUS_INVALID_PARAMETER, ++ RT_STATUS_NOT_SUPPORT, ++ RT_STATUS_OS_API_FAILED, ++}RT_STATUS,*PRT_STATUS; ++#endif // end of RT_STATUS definition ++ ++#ifdef REMOVE_PACK ++#pragma pack() ++#endif ++ ++//#include "odm_function.h" ++ ++//3=========================================================== ++//3 DIG ++//3=========================================================== ++ ++typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition ++{ ++ DIG_TYPE_THRESH_HIGH = 0, ++ DIG_TYPE_THRESH_LOW = 1, ++ DIG_TYPE_BACKOFF = 2, ++ DIG_TYPE_RX_GAIN_MIN = 3, ++ DIG_TYPE_RX_GAIN_MAX = 4, ++ DIG_TYPE_ENABLE = 5, ++ DIG_TYPE_DISABLE = 6, ++ DIG_OP_TYPE_MAX ++}DM_DIG_OP_E; ++/* ++typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition ++{ ++ CCK_PD_STAGE_LowRssi = 0, ++ CCK_PD_STAGE_HighRssi = 1, ++ CCK_PD_STAGE_MAX = 3, ++}DM_CCK_PDTH_E; ++ ++typedef enum tag_DIG_EXT_PORT_ALGO_Definition ++{ ++ DIG_EXT_PORT_STAGE_0 = 0, ++ DIG_EXT_PORT_STAGE_1 = 1, ++ DIG_EXT_PORT_STAGE_2 = 2, ++ DIG_EXT_PORT_STAGE_3 = 3, ++ DIG_EXT_PORT_STAGE_MAX = 4, ++}DM_DIG_EXT_PORT_ALG_E; ++ ++typedef enum tag_DIG_Connect_Definition ++{ ++ DIG_STA_DISCONNECT = 0, ++ DIG_STA_CONNECT = 1, ++ DIG_STA_BEFORE_CONNECT = 2, ++ DIG_MultiSTA_DISCONNECT = 3, ++ DIG_MultiSTA_CONNECT = 4, ++ DIG_CONNECT_MAX ++}DM_DIG_CONNECT_E; ++ ++ ++#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} ++ ++#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ ++ DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) ++ ++#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ ++ DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) ++*/ ++ ++#define DM_DIG_THRESH_HIGH 40 ++#define DM_DIG_THRESH_LOW 35 ++ ++#define DM_FALSEALARM_THRESH_LOW 400 ++#define DM_FALSEALARM_THRESH_HIGH 1000 ++ ++#define DM_DIG_MAX_NIC 0x4A ++#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c ++ ++#define DM_DIG_MAX_AP 0x32 ++#define DM_DIG_MIN_AP 0x20 ++ ++#define DM_DIG_MAX_NIC_HP 0x46 ++#define DM_DIG_MIN_NIC_HP 0x2e ++ ++#define DM_DIG_MAX_AP_HP 0x42 ++#define DM_DIG_MIN_AP_HP 0x30 ++ ++//vivi 92c&92d has different definition, 20110504 ++//this is for 92c ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++#define DM_DIG_FA_TH0 0x80//0x20 ++#else ++#define DM_DIG_FA_TH0 0x200//0x20 ++#endif ++#define DM_DIG_FA_TH1 0x300//0x100 ++#define DM_DIG_FA_TH2 0x400//0x200 ++//this is for 92d ++#define DM_DIG_FA_TH0_92D 0x100 ++#define DM_DIG_FA_TH1_92D 0x400 ++#define DM_DIG_FA_TH2_92D 0x600 ++ ++#define DM_DIG_BACKOFF_MAX 12 ++#define DM_DIG_BACKOFF_MIN -4 ++#define DM_DIG_BACKOFF_DEFAULT 10 ++ ++//3=========================================================== ++//3 AGC RX High Power Mode ++//3=========================================================== ++#define LNA_Low_Gain_1 0x64 ++#define LNA_Low_Gain_2 0x5A ++#define LNA_Low_Gain_3 0x58 ++ ++#define FA_RXHP_TH1 5000 ++#define FA_RXHP_TH2 1500 ++#define FA_RXHP_TH3 800 ++#define FA_RXHP_TH4 600 ++#define FA_RXHP_TH5 500 ++ ++//3=========================================================== ++//3 EDCA ++//3=========================================================== ++ ++//3=========================================================== ++//3 Dynamic Tx Power ++//3=========================================================== ++//Dynamic Tx Power Control Threshold ++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 ++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 ++#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F ++ ++#define TxHighPwrLevel_Normal 0 ++#define TxHighPwrLevel_Level1 1 ++#define TxHighPwrLevel_Level2 2 ++#define TxHighPwrLevel_BT1 3 ++#define TxHighPwrLevel_BT2 4 ++#define TxHighPwrLevel_15 5 ++#define TxHighPwrLevel_35 6 ++#define TxHighPwrLevel_50 7 ++#define TxHighPwrLevel_70 8 ++#define TxHighPwrLevel_100 9 ++ ++//3=========================================================== ++//3 Tx Power Tracking ++//3=========================================================== ++#if 0 //mask this, since these have been defined in typdef.h, vivi ++#define OFDM_TABLE_SIZE 37 ++#define OFDM_TABLE_SIZE_92D 43 ++#define CCK_TABLE_SIZE 33 ++#endif ++ ++ ++//3=========================================================== ++//3 Rate Adaptive ++//3=========================================================== ++#define DM_RATR_STA_INIT 0 ++#define DM_RATR_STA_HIGH 1 ++#define DM_RATR_STA_MIDDLE 2 ++#define DM_RATR_STA_LOW 3 ++ ++//3=========================================================== ++//3 BB Power Save ++//3=========================================================== ++ ++ ++typedef enum tag_1R_CCA_Type_Definition ++{ ++ CCA_1R =0, ++ CCA_2R = 1, ++ CCA_MAX = 2, ++}DM_1R_CCA_E; ++ ++typedef enum tag_RF_Type_Definition ++{ ++ RF_Save =0, ++ RF_Normal = 1, ++ RF_MAX = 2, ++}DM_RF_E; ++ ++//3=========================================================== ++//3 Antenna Diversity ++//3=========================================================== ++typedef enum tag_SW_Antenna_Switch_Definition ++{ ++ Antenna_A = 1, ++ Antenna_B = 2, ++ Antenna_MAX = 3, ++}DM_SWAS_E; ++ ++ ++// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. ++#define MAX_ANTENNA_DETECTION_CNT 10 ++ ++// ++// Extern Global Variables. ++// ++#define OFDM_TABLE_SIZE_92C 37 ++#define OFDM_TABLE_SIZE_92D 43 ++#define CCK_TABLE_SIZE 33 ++ ++extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; ++extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; ++extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; ++ ++ ++ ++// ++// check Sta pointer valid or not ++// ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) ++#elif (DM_ODM_SUPPORT_TYPE & ODM_MP) ++#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) ++#else ++#define IS_STA_VALID(pSta) (pSta) ++#endif ++// 20100514 Joseph: Add definition for antenna switching test after link. ++// This indicates two different the steps. ++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. ++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK ++// with original RSSI to determine if it is necessary to switch antenna. ++#define SWAW_STEP_PEAK 0 ++#define SWAW_STEP_DETERMINE 1 ++ ++VOID ODM_Write_DIG(IN PDM_ODM_T pDM_Odm, IN u1Byte CurrentIGI); ++VOID ODM_Write_CCK_CCA_Thres(IN PDM_ODM_T pDM_Odm, IN u1Byte CurCCK_CCAThres); ++ ++VOID ++ODM_SetAntenna( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Antenna); ++ ++ ++#define dm_RF_Saving ODM_RF_Saving ++void ODM_RF_Saving( IN PDM_ODM_T pDM_Odm, ++ IN u1Byte bForceInNormal ); ++ ++#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink ++VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm); ++ ++#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck ++VOID ++ODM_TXPowerTrackingCheck( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++BOOLEAN ++ODM_RAStateCheck( ++ IN PDM_ODM_T pDM_Odm, ++ IN s4Byte RSSI, ++ IN BOOLEAN bForceUpdate, ++ OUT pu1Byte pRATRState ++ ); ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP|ODM_ADSL)) ++//============================================================ ++// function prototype ++//============================================================ ++//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh ++//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, ++// IN INT32 DM_Type, ++// IN INT32 DM_Value); ++VOID ++ODM_ChangeDynamicInitGainThresh( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte DM_Type, ++ IN u4Byte DM_Value ++ ); ++ ++BOOLEAN ++ODM_CheckPowerStatus( ++ IN PADAPTER Adapter ++ ); ++ ++ ++#if (DM_ODM_SUPPORT_TYPE != ODM_ADSL) ++VOID ++ODM_RateAdaptiveStateApInit( ++ IN PADAPTER Adapter , ++ IN PRT_WLAN_STA pEntry ++ ); ++#endif ++#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit ++ ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#ifdef WIFI_WMM ++VOID ++ODM_IotEdcaSwitch( ++ IN PDM_ODM_T pDM_Odm, ++ IN unsigned char enable ++ ); ++#endif ++ ++BOOLEAN ++ODM_ChooseIotMainSTA( ++ IN PDM_ODM_T pDM_Odm, ++ IN PSTA_INFO_T pstat ++ ); ++#endif ++ ++#if(DM_ODM_SUPPORT_TYPE==ODM_AP) ++#ifdef HW_ANT_SWITCH ++u1Byte ++ODM_Diversity_AntennaSelect( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte *data ++); ++#endif ++#endif ++ ++#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink ++VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm); ++ ++//#define SwAntDivCheckBeforeLink8192C ODM_SwAntDivCheckBeforeLink8192C ++#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink8192C ++BOOLEAN ++ODM_SwAntDivCheckBeforeLink8192C( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++#endif ++ ++#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi ++VOID ODM_SwAntDivChkPerPktRssi( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte StationID, ++ IN PODM_PHY_INFO_T pPhyInfo ++ ); ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_MP)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) ++ ++u4Byte ConvertTo_dB(u4Byte Value); ++ ++u4Byte ++GetPSDData( ++ PDM_ODM_T pDM_Odm, ++ unsigned int point, ++ u1Byte initial_gain_psd); ++ ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ ++VOID ++odm_DIGbyRSSI_LPS( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++u4Byte ODM_Get_Rate_Bitmap( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte macid, ++ IN u4Byte ra_mask, ++ IN u1Byte rssi_level); ++#endif ++ ++ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++#define dm_PSDMonitorCallback odm_PSDMonitorCallback ++VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); ++ ++VOID ++odm_PSDMonitorWorkItemCallback( ++ IN PVOID pContext ++ ); ++ ++ ++VOID ++PatchDCTone( ++ IN PDM_ODM_T pDM_Odm, ++ pu4Byte PSD_report, ++ u1Byte initial_gain_psd ++); ++VOID ++ODM_PSDMonitor( ++ IN PDM_ODM_T pDM_Odm ++ ); ++VOID odm_PSD_Monitor(PDM_ODM_T pDM_Odm); ++VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm); ++ ++VOID ++ODM_PSDDbgControl( ++ IN PADAPTER Adapter, ++ IN u4Byte mode, ++ IN u4Byte btRssi ++ ); ++ ++#endif // DM_ODM_SUPPORT_TYPE ++ ++ ++ ++VOID ODM_DMInit( IN PDM_ODM_T pDM_Odm); ++ ++VOID ++ODM_DMWatchdog( ++ IN PDM_ODM_T pDM_Odm // For common use in the future ++ ); ++ ++VOID ++ODM_CmnInfoInit( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN u4Byte Value ++ ); ++ ++VOID ++ODM_CmnInfoHook( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN PVOID pValue ++ ); ++ ++VOID ++ODM_CmnInfoPtrArrayHook( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_CMNINFO_E CmnInfo, ++ IN u2Byte Index, ++ IN PVOID pValue ++ ); ++ ++VOID ++ODM_CmnInfoUpdate( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte CmnInfo, ++ IN u8Byte Value ++ ); ++ ++VOID ++ODM_InitAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++ODM_CancelAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++ODM_ReleaseAllTimers( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++ODM_ResetIQKResult( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); ++VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); ++ ++VOID odm_PathDivChkAntSwitch(PDM_ODM_T pDM_Odm); ++VOID ODM_PathDivRestAfterLink( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++//===========================================// ++// Neil Chen----2011--06--15-- ++ ++//3 Path Diversity ++//=========================================================== ++ ++#define TP_MODE 0 ++#define RSSI_MODE 1 ++#define TRAFFIC_LOW 0 ++#define TRAFFIC_HIGH 1 ++ ++//#define PATHDIV_ENABLE 1 ++ ++//VOID odm_PathDivChkAntSwitch(PADAPTER Adapter,u1Byte Step); ++VOID ODM_PathDivRestAfterLink( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi ++VOID ODM_PathDivChkPerPktRssi(PADAPTER Adapter, ++ BOOLEAN bIsDefPort, ++ BOOLEAN bMatchBSSID, ++ PRT_WLAN_STA pEntry, ++ PRT_RFD pRfd ); ++ ++u8Byte ++PlatformDivision64( ++ IN u8Byte x, ++ IN u8Byte y ++); ++ ++ ++// 20100514 Joseph: Add definition for antenna switching test after link. ++// This indicates two different the steps. ++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. ++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK ++// with original RSSI to determine if it is necessary to switch antenna. ++#define SWAW_STEP_PEAK 0 ++#define SWAW_STEP_DETERMINE 1 ++ ++//==================================================== ++//3 PathDiV End ++//==================================================== ++ ++#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C ++BOOLEAN ++ODM_PathDiversityBeforeLink92C( ++ //IN PADAPTER Adapter ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh ++//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, ++// IN INT32 DM_Type, ++// IN INT32 DM_Value); ++// ++ ++ ++VOID ++ODM_CCKPathDiversityChkPerPktRssi( ++ PADAPTER Adapter, ++ BOOLEAN bIsDefPort, ++ BOOLEAN bMatchBSSID, ++ PRT_WLAN_STA pEntry, ++ PRT_RFD pRfd, ++ pu1Byte pDesc ++ ); ++ ++ ++typedef enum tag_DIG_Connect_Definition ++{ ++ DIG_STA_DISCONNECT = 0, ++ DIG_STA_CONNECT = 1, ++ DIG_STA_BEFORE_CONNECT = 2, ++ DIG_MultiSTA_DISCONNECT = 3, ++ DIG_MultiSTA_CONNECT = 4, ++ DIG_CONNECT_MAX ++}DM_DIG_CONNECT_E; ++ ++ ++VOID ++ODM_FillTXPathInTXDESC( ++ IN PADAPTER Adapter, ++ IN PRT_TCB pTcb, ++ IN pu1Byte pDesc ++); ++ ++ ++#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi ++ ++// ++// 2012/01/12 MH Check afapter status. Temp fix BSOD. ++// ++#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ ++ if (pDM_Odm->Adapter == NULL)\ ++ {\ ++ return;\ ++ }\ ++ ++ ++// ++// For new definition in MP temporarily fro power tracking, ++// ++#define odm_TXPowerTrackingDirectCall(_Adapter) \ ++ IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ ++ IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ ++ IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ ++ odm_TXPowerTrackingCallback_ThermalMeter_8188E(_Adapter) ++ ++VOID ++ODM_SetTxAntByTxInfo_88C_92D( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++ ); ++#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++ODM_AntselStatistics_88C( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacId, ++ IN u4Byte PWDBAll, ++ IN BOOLEAN isCCKrate ++); ++ ++#if( DM_ODM_SUPPORT_TYPE & (ODM_MP |ODM_CE)) ++ ++VOID ++ODM_SingleDualAntennaDefaultSetting( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++BOOLEAN ++ODM_SingleDualAntennaDetection( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte mode ++ ); ++ ++#endif // #if((DM_ODM_SUPPORT_TYPE==ODM_MP)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++void odm_dtc(PDM_ODM_T pDM_Odm); ++#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.c +new file mode 100644 +index 00000000..a11a8154 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.c +@@ -0,0 +1,1198 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++//============================================================ ++// include files ++//============================================================ ++ ++#include "odm_precomp.h" ++ ++#if (RTL8188E_FOR_TEST_CHIP > 1) ++ #define READ_AND_CONFIG(ic, txt) do {\ ++ if (pDM_Odm->bIsMPChip)\ ++ READ_AND_CONFIG_MP(ic,txt);\ ++ else\ ++ READ_AND_CONFIG_TC(ic,txt);\ ++ } while(0) ++#elif (RTL8188E_FOR_TEST_CHIP == 1) ++ #define READ_AND_CONFIG READ_AND_CONFIG_TC ++#else ++ #define READ_AND_CONFIG READ_AND_CONFIG_MP ++#endif ++ ++#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm)) ++#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm)) ++ ++u1Byte ++odm_QueryRxPwrPercentage( ++ IN s1Byte AntPower ++ ) ++{ ++ if ((AntPower <= -100) || (AntPower >= 20)) ++ { ++ return 0; ++ } ++ else if (AntPower >= 0) ++ { ++ return 100; ++ } ++ else ++ { ++ return (100+AntPower); ++ } ++ ++} ++ ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++// ++// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. ++// IF other SW team do not support the feature, remove this section.?? ++// ++s4Byte ++odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( ++ IN OUT PDM_ODM_T pDM_Odm, ++ s4Byte CurrSig ++) ++{ ++ s4Byte RetSig; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) ++ { ++ // Step 1. Scale mapping. ++ // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. ++ // 20100426 Joseph: Modify Signal strength mapping. ++ // This modification makes the RSSI indication similar to Intel solution. ++ // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. ++ if(CurrSig >= 54 && CurrSig <= 100) ++ { ++ RetSig = 100; ++ } ++ else if(CurrSig>=42 && CurrSig <= 53 ) ++ { ++ RetSig = 95; ++ } ++ else if(CurrSig>=36 && CurrSig <= 41 ) ++ { ++ RetSig = 74 + ((CurrSig - 36) *20)/6; ++ } ++ else if(CurrSig>=33 && CurrSig <= 35 ) ++ { ++ RetSig = 65 + ((CurrSig - 33) *8)/2; ++ } ++ else if(CurrSig>=18 && CurrSig <= 32 ) ++ { ++ RetSig = 62 + ((CurrSig - 18) *2)/15; ++ } ++ else if(CurrSig>=15 && CurrSig <= 17 ) ++ { ++ RetSig = 33 + ((CurrSig - 15) *28)/2; ++ } ++ else if(CurrSig>=10 && CurrSig <= 14 ) ++ { ++ RetSig = 39; ++ } ++ else if(CurrSig>=8 && CurrSig <= 9 ) ++ { ++ RetSig = 33; ++ } ++ else if(CurrSig <= 8 ) ++ { ++ RetSig = 19; ++ } ++ } ++#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ return RetSig; ++} ++ ++s4Byte ++odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( ++ IN OUT PDM_ODM_T pDM_Odm, ++ s4Byte CurrSig ++) ++{ ++ s4Byte RetSig; ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) ++ { ++ // Netcore request this modification because 2009.04.13 SU driver use it. ++ if(CurrSig >= 31 && CurrSig <= 100) ++ { ++ RetSig = 100; ++ } ++ else if(CurrSig >= 21 && CurrSig <= 30) ++ { ++ RetSig = 90 + ((CurrSig - 20) / 1); ++ } ++ else if(CurrSig >= 11 && CurrSig <= 20) ++ { ++ RetSig = 80 + ((CurrSig - 10) / 1); ++ } ++ else if(CurrSig >= 7 && CurrSig <= 10) ++ { ++ RetSig = 69 + (CurrSig - 7); ++ } ++ else if(CurrSig == 6) ++ { ++ RetSig = 54; ++ } ++ else if(CurrSig == 5) ++ { ++ RetSig = 45; ++ } ++ else if(CurrSig == 4) ++ { ++ RetSig = 36; ++ } ++ else if(CurrSig == 3) ++ { ++ RetSig = 27; ++ } ++ else if(CurrSig == 2) ++ { ++ RetSig = 18; ++ } ++ else if(CurrSig == 1) ++ { ++ RetSig = 9; ++ } ++ else ++ { ++ RetSig = CurrSig; ++ } ++ } ++#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ return RetSig; ++} ++ ++ ++s4Byte ++odm_SignalScaleMapping_92CSeries( ++ IN OUT PDM_ODM_T pDM_Odm, ++ IN s4Byte CurrSig ++) ++{ ++ s4Byte RetSig; ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++ if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) ++ { ++ // Step 1. Scale mapping. ++ if(CurrSig >= 61 && CurrSig <= 100) ++ { ++ RetSig = 90 + ((CurrSig - 60) / 4); ++ } ++ else if(CurrSig >= 41 && CurrSig <= 60) ++ { ++ RetSig = 78 + ((CurrSig - 40) / 2); ++ } ++ else if(CurrSig >= 31 && CurrSig <= 40) ++ { ++ RetSig = 66 + (CurrSig - 30); ++ } ++ else if(CurrSig >= 21 && CurrSig <= 30) ++ { ++ RetSig = 54 + (CurrSig - 20); ++ } ++ else if(CurrSig >= 5 && CurrSig <= 20) ++ { ++ RetSig = 42 + (((CurrSig - 5) * 2) / 3); ++ } ++ else if(CurrSig == 4) ++ { ++ RetSig = 36; ++ } ++ else if(CurrSig == 3) ++ { ++ RetSig = 27; ++ } ++ else if(CurrSig == 2) ++ { ++ RetSig = 18; ++ } ++ else if(CurrSig == 1) ++ { ++ RetSig = 9; ++ } ++ else ++ { ++ RetSig = CurrSig; ++ } ++ } ++#endif ++ ++#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) ++ if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) ) ++ { ++ if(CurrSig >= 51 && CurrSig <= 100) ++ { ++ RetSig = 100; ++ } ++ else if(CurrSig >= 41 && CurrSig <= 50) ++ { ++ RetSig = 80 + ((CurrSig - 40)*2); ++ } ++ else if(CurrSig >= 31 && CurrSig <= 40) ++ { ++ RetSig = 66 + (CurrSig - 30); ++ } ++ else if(CurrSig >= 21 && CurrSig <= 30) ++ { ++ RetSig = 54 + (CurrSig - 20); ++ } ++ else if(CurrSig >= 10 && CurrSig <= 20) ++ { ++ RetSig = 42 + (((CurrSig - 10) * 2) / 3); ++ } ++ else if(CurrSig >= 5 && CurrSig <= 9) ++ { ++ RetSig = 22 + (((CurrSig - 5) * 3) / 2); ++ } ++ else if(CurrSig >= 1 && CurrSig <= 4) ++ { ++ RetSig = 6 + (((CurrSig - 1) * 3) / 2); ++ } ++ else ++ { ++ RetSig = CurrSig; ++ } ++ } ++#endif ++ return RetSig; ++} ++s4Byte ++odm_SignalScaleMapping( ++ IN OUT PDM_ODM_T pDM_Odm, ++ IN s4Byte CurrSig ++) ++{ ++ if( (pDM_Odm->SupportPlatform == ODM_MP) && ++ (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO ++ (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore ++ { ++ return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); ++ } ++ else if( (pDM_Odm->SupportPlatform == ODM_MP) && ++ (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && ++ (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) ++ { ++ return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); ++ } ++ else{ ++ return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); ++ } ++ ++} ++#endif ++ ++//pMgntInfo->CustomerID == RT_CID_819x_Lenovo ++static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte isCCKrate, ++ IN u1Byte PWDB_ALL, ++ IN u1Byte path, ++ IN u1Byte RSSI ++) ++{ ++ u1Byte SQ; ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++ // mapping to 5 bars for vista signal strength ++ // signal quality in driver will be displayed to signal strength ++ if(isCCKrate){ ++ // in vista. ++ if(PWDB_ALL >= 50) ++ SQ = 100; ++ else if(PWDB_ALL >= 35 && PWDB_ALL < 50) ++ SQ = 80; ++ else if(PWDB_ALL >= 22 && PWDB_ALL < 35) ++ SQ = 60; ++ else if(PWDB_ALL >= 18 && PWDB_ALL < 22) ++ SQ = 40; ++ else ++ SQ = 20; ++ } ++ else{//OFDM rate ++ ++ // mapping to 5 bars for vista signal strength ++ // signal quality in driver will be displayed to signal strength ++ // in vista. ++ if(RSSI >= 50) ++ SQ = 100; ++ else if(RSSI >= 35 && RSSI < 50) ++ SQ = 80; ++ else if(RSSI >= 22 && RSSI < 35) ++ SQ = 60; ++ else if(RSSI >= 18 && RSSI < 22) ++ SQ = 40; ++ else ++ SQ = 20; ++ } ++#endif ++ return SQ; ++} ++ ++static u1Byte ++odm_EVMdbToPercentage( ++ IN s1Byte Value ++ ) ++{ ++ // ++ // -33dB~0dB to 0%~99% ++ // ++ s1Byte ret_val; ++ ++ ret_val = Value; ++ //ret_val /= 2; ++ ++ //ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val)); ++ ++ if(ret_val >= 0) ++ ret_val = 0; ++ if(ret_val <= -33) ++ ret_val = -33; ++ ++ ret_val = 0 - ret_val; ++ ret_val*=3; ++ ++ if(ret_val == 99) ++ ret_val = 100; ++ ++ return(ret_val); ++} ++ ++ ++ ++VOID ++odm_RxPhyStatus92CSeries_Parsing( ++ IN OUT PDM_ODM_T pDM_Odm, ++ OUT PODM_PHY_INFO_T pPhyInfo, ++ IN pu1Byte pPhyStatus, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ) ++{ ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ u1Byte i, Max_spatial_stream; ++ s1Byte rx_pwr[4], rx_pwr_all=0; ++ u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; ++ u1Byte RSSI, total_rssi=0; ++ u1Byte isCCKrate=0; ++ u1Byte rf_rx_num = 0; ++ u1Byte cck_highpwr = 0; ++ u1Byte LNA_idx, VGA_idx; ++ ++ PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; ++ ++ isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE; ++ ++ pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; ++ pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; ++ ++ ++ if(isCCKrate) ++ { ++ u1Byte report; ++ u1Byte cck_agc_rpt; ++ ++ pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; ++ // ++ // (1)Hardware does not provide RSSI for CCK ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) ++ // ++ ++ //if(pHalData->eRFPowerState == eRfOn) ++ cck_highpwr = pDM_Odm->bCckHighPower; ++ //else ++ // cck_highpwr = FALSE; ++ ++ cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; ++ ++ //2011.11.28 LukeLee: 88E use different LNA & VGA gain table ++ //The RSSI formula should be modified according to the gain table ++ //In 88E, cck_highpwr is always set to 1 ++ if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) ++ { ++ LNA_idx = ((cck_agc_rpt & 0xE0) >>5); ++ VGA_idx = (cck_agc_rpt & 0x1F); ++ switch(LNA_idx) ++ { ++ case 7: ++ if(VGA_idx <= 27) ++ rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2 ++ else ++ rx_pwr_all = -100; ++ break; ++ case 6: ++ rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0 ++ break; ++ case 5: ++ rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5 ++ break; ++ case 4: ++ rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4 ++ break; ++ case 3: ++ //rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0 ++ rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0 ++ break; ++ case 2: ++ if(cck_highpwr) ++ rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0 ++ else ++ rx_pwr_all = -6+ 2*(5-VGA_idx); ++ break; ++ case 1: ++ rx_pwr_all = 8-2*VGA_idx; ++ break; ++ case 0: ++ rx_pwr_all = 14-2*VGA_idx; ++ break; ++ default: ++ //DbgPrint("CCK Exception default\n"); ++ break; ++ } ++ rx_pwr_all += 6; ++ PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); ++ if(cck_highpwr == FALSE) ++ { ++ if(PWDB_ALL >= 80) ++ PWDB_ALL = ((PWDB_ALL-80)<<1)+((PWDB_ALL-80)>>1)+80; ++ else if((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) ++ PWDB_ALL += 3; ++ if(PWDB_ALL>100) ++ PWDB_ALL = 100; ++ } ++ } ++ else ++ { ++ if(!cck_highpwr) ++ { ++ report =( cck_agc_rpt & 0xc0 )>>6; ++ switch(report) ++ { ++ // 03312009 modified by cosa ++ // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion ++ // Note: different RF with the different RNA gain. ++ case 0x3: ++ rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x2: ++ rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x1: ++ rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x0: ++ rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); ++ break; ++ } ++ } ++ else ++ { ++ //report = pDrvInfo->cfosho[0] & 0x60; ++ //report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; ++ ++ report = (cck_agc_rpt & 0x60)>>5; ++ switch(report) ++ { ++ case 0x3: ++ rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x2: ++ rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f)<<1); ++ break; ++ case 0x1: ++ rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x0: ++ rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ } ++ } ++ ++ PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); ++ ++ //Modification for ext-LNA board ++ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) ++ { ++ if((cck_agc_rpt>>7) == 0){ ++ PWDB_ALL = (PWDB_ALL>94)?100:(PWDB_ALL +6); ++ } ++ else ++ { ++ if(PWDB_ALL > 38) ++ PWDB_ALL -= 16; ++ else ++ PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12); ++ } ++ ++ //CCK modification ++ if(PWDB_ALL > 25 && PWDB_ALL <= 60) ++ PWDB_ALL += 6; ++ //else if (PWDB_ALL <= 25) ++ // PWDB_ALL += 8; ++ } ++ else//Modification for int-LNA board ++ { ++ if(PWDB_ALL > 99) ++ PWDB_ALL -= 8; ++ else if(PWDB_ALL > 50 && PWDB_ALL <= 68) ++ PWDB_ALL += 4; ++ } ++ } ++ ++ pPhyInfo->RxPWDBAll = PWDB_ALL; ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; ++ pPhyInfo->RecvSignalPower = rx_pwr_all; ++#endif ++ // ++ // (3) Get Signal Quality (EVM) ++ // ++ if(pPktinfo->bPacketMatchBSSID) ++ { ++ u1Byte SQ,SQ_rpt; ++ ++ if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo ++ SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); ++ } ++ else if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ ++ SQ = 100; ++ } ++ else{ ++ SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; ++ ++ if(SQ_rpt > 64) ++ SQ = 0; ++ else if (SQ_rpt < 20) ++ SQ = 100; ++ else ++ SQ = ((64-SQ_rpt) * 100) / 44; ++ ++ } ++ ++ //DbgPrint("cck SQ = %d\n", SQ); ++ pPhyInfo->SignalQuality = SQ; ++ pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; ++ pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; ++ } ++ } ++ else //is OFDM rate ++ { ++ pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; ++ ++ // ++ // (1)Get RSSI for HT rate ++ // ++ ++ for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) ++ { ++ // 2008/01/30 MH we will judge RF RX path now. ++ if (pDM_Odm->RFPathRxEnable & BIT(i)) ++ rf_rx_num++; ++ //else ++ //continue; ++ ++ rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; ++ ++ #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ pPhyInfo->RxPwr[i] = rx_pwr[i]; ++ #endif ++ ++ /* Translate DBM to percentage. */ ++ RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); ++ total_rssi += RSSI; ++ //RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); ++ ++ //Modification for ext-LNA board ++ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) ++ { ++ if((pPhyStaRpt->path_agc[i].trsw) == 1) ++ RSSI = (RSSI>94)?100:(RSSI +6); ++ else ++ RSSI = (RSSI<=16)?(RSSI>>3):(RSSI -16); ++ ++ if((RSSI <= 34) && (RSSI >=4)) ++ RSSI -= 4; ++ } ++ ++ pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; ++ ++ #if (DM_ODM_SUPPORT_TYPE & (/*ODM_MP|*/ODM_CE|ODM_AP|ODM_ADSL)) ++ //Get Rx snr value in DB ++ pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); ++ #endif ++ ++ /* Record Signal Strength for next packet */ ++ if(pPktinfo->bPacketMatchBSSID) ++ { ++ if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)) ++ { ++ if(i==ODM_RF_PATH_A) ++ pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); ++ ++ } ++ ++ } ++ } ++ ++ ++ // ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) ++ // ++ rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; ++ //RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL)); ++ ++ PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); ++ //RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n",PWDB_ALL)); ++ ++ pPhyInfo->RxPWDBAll = PWDB_ALL; ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); ++ #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; ++ pPhyInfo->RxPower = rx_pwr_all; ++ pPhyInfo->RecvSignalPower = rx_pwr_all; ++ #endif ++ ++ if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){ ++ //do nothing ++ } ++ else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo ++ // ++ // (3)EVM of HT rate ++ // ++ if(pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15) ++ Max_spatial_stream = 2; //both spatial stream make sense ++ else ++ Max_spatial_stream = 1; //only spatial stream 1 makes sense ++ ++ for(i=0; i>= 1" because the compilor of free build environment ++ // fill most significant bit to "zero" when doing shifting operation which may change a negative ++ // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. ++ EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm ++ ++ //RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", ++ //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); ++ ++ if(pPktinfo->bPacketMatchBSSID) ++ { ++ if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only ++ { ++ pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); ++ } ++ pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); ++ } ++ } ++ } ++ ++ } ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ //UI BSS List signal strength(in percentage), make it good looking, from 0~100. ++ //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). ++ if(isCCKrate) ++ { ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ ++ pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));//PWDB_ALL; ++#else ++ pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL; ++#endif ++ } ++ else ++ { ++ if (rf_rx_num != 0) ++ { ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ ++ pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));//PWDB_ALL; ++#else ++ pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num)); ++#endif ++ } ++ } ++#endif ++ ++ //For 92C/92D HW (Hybrid) Antenna Diversity ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++ pDM_SWAT_Table->antsel = pPhyStaRpt->ant_sel; ++ //For 88E HW Antenna Diversity ++ pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; ++ pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; ++ pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; ++#endif ++} ++ ++VOID ++odm_Init_RSSIForDM( ++ IN OUT PDM_ODM_T pDM_Odm ++ ) ++{ ++ ++} ++ ++VOID ++odm_Process_RSSIForDM( ++ IN OUT PDM_ODM_T pDM_Odm, ++ IN PODM_PHY_INFO_T pPhyInfo, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ) ++{ ++ ++ s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave; ++ u1Byte isCCKrate=0; ++ u1Byte RSSI_max, RSSI_min, i; ++ u4Byte OFDM_pkt=0; ++ u4Byte Weighting=0; ++ ++ PSTA_INFO_T pEntry; ++ ++ if(pPktinfo->StationID == 0xFF) ++ return; ++ ++ // 2011/11/17 MH Need to debug ++ //if (pDM_Odm->SupportPlatform == ODM_MP) ++ { ++ ++ } ++ ++ pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; ++ if(!IS_STA_VALID(pEntry) ){ ++ return; ++ } ++ if((!pPktinfo->bPacketMatchBSSID) ) ++ { ++ return; ++ } ++ ++ isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE; ++ if(pPktinfo->bPacketBeacon) ++ pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; ++ ++ pDM_Odm->RxRate = pPktinfo->Rate; ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1)) ++ if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D) ++ { ++ if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) ++ { ++ //if(pPktinfo->bPacketBeacon) ++ //{ ++ // DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate); ++ //} ++ ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate); ++ } ++ } ++#endif ++ //-----------------Smart Antenna Debug Message------------------// ++#if (RTL8188E_SUPPORT == 1) ++ if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ u1Byte antsel_tr_mux; ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ ++ if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) ++ { ++ if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) ++ { ++ if(pPktinfo->bPacketToSelf) //(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) ++ { ++ antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; ++ pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll; ++ pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", ++ //pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); ++ ++ } ++ } ++ } ++ else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) ++ { ++ if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) ++ { ++ antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", ++ // pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); ++ ++ ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); ++ } ++ } ++ ++ } ++#endif ++#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++ //-----------------Smart Antenna Debug Message------------------// ++ ++ UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; ++ UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; ++ UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) ++ { ++ ++ if(!isCCKrate)//ofdm rate ++ { ++ if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){ ++ RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; ++ pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; ++ pDM_Odm->RSSI_B = 0; ++ } ++ else ++ { ++ //DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n", ++ //pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); ++ pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; ++ pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; ++ ++ if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) ++ { ++ RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; ++ RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; ++ } ++ else ++ { ++ RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; ++ RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; ++ } ++ if((RSSI_max -RSSI_min) < 3) ++ RSSI_Ave = RSSI_max; ++ else if((RSSI_max -RSSI_min) < 6) ++ RSSI_Ave = RSSI_max - 1; ++ else if((RSSI_max -RSSI_min) < 10) ++ RSSI_Ave = RSSI_max - 2; ++ else ++ RSSI_Ave = RSSI_max - 3; ++ } ++ ++ //1 Process OFDM RSSI ++ if(UndecoratedSmoothedOFDM <= 0) // initialize ++ { ++ UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; ++ } ++ else ++ { ++ if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) ++ { ++ UndecoratedSmoothedOFDM = ++ ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + ++ (RSSI_Ave)) /(Rx_Smooth_Factor); ++ UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; ++ } ++ else ++ { ++ UndecoratedSmoothedOFDM = ++ ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + ++ (RSSI_Ave)) /(Rx_Smooth_Factor); ++ } ++ } ++ ++ pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; ++ ++ } ++ else ++ { ++ RSSI_Ave = pPhyInfo->RxPWDBAll; ++ pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll; ++ pDM_Odm->RSSI_B = 0xFF; ++ ++ //1 Process CCK RSSI ++ if(UndecoratedSmoothedCCK <= 0) // initialize ++ { ++ UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; ++ } ++ else ++ { ++ if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) ++ { ++ UndecoratedSmoothedCCK = ++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + ++ (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); ++ UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; ++ } ++ else ++ { ++ UndecoratedSmoothedCCK = ++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + ++ (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); ++ } ++ } ++ pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; ++ } ++ ++ //if(pEntry) ++ { ++ //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI ++ if(pEntry->rssi_stat.ValidBit >= 64) ++ pEntry->rssi_stat.ValidBit = 64; ++ else ++ pEntry->rssi_stat.ValidBit++; ++ ++ for(i=0; irssi_stat.ValidBit; i++) ++ OFDM_pkt += (u1Byte)(pEntry->rssi_stat.PacketMap>>i)&BIT0; ++ ++ if(pEntry->rssi_stat.ValidBit == 64) ++ { ++ Weighting = ((OFDM_pkt<<4) > 64)?64:(OFDM_pkt<<4); ++ UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; ++ } ++ else ++ { ++ if(pEntry->rssi_stat.ValidBit != 0) ++ UndecoratedSmoothedPWDB = (OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; ++ else ++ UndecoratedSmoothedPWDB = 0; ++ } ++ ++ pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; ++ pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; ++ pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ ++ //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); ++ //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", ++ // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); ++ ++ } ++ ++ } ++} ++ ++// ++// Endianness before calling this API ++// ++VOID ++ODM_PhyStatusQuery_92CSeries( ++ IN OUT PDM_ODM_T pDM_Odm, ++ OUT PODM_PHY_INFO_T pPhyInfo, ++ IN pu1Byte pPhyStatus, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ) ++{ ++ ++ odm_RxPhyStatus92CSeries_Parsing( ++ pDM_Odm, ++ pPhyInfo, ++ pPhyStatus, ++ pPktinfo); ++ ++ if( pDM_Odm->RSSI_test == TRUE) ++ { ++ // Select the packets to do RSSI checking for antenna switching. ++ if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon ) ++ { ++ /* ++ #if 0//(DM_ODM_SUPPORT_TYPE == ODM_MP) ++ dm_SWAW_RSSI_Check( ++ Adapter, ++ (tmppAdapter!=NULL)?(tmppAdapter==Adapter):TRUE, ++ bPacketMatchBSSID, ++ pEntry, ++ pRfd); ++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ // Select the packets to do RSSI checking for antenna switching. ++ //odm_SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll); ++ #endif ++ */ ++ ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo); ++ } ++ } ++ else ++ { ++ odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo); ++ } ++ ++} ++ ++ ++ ++// ++// Endianness before calling this API ++// ++VOID ++ODM_PhyStatusQuery_JaguarSeries( ++ IN OUT PDM_ODM_T pDM_Odm, ++ OUT PODM_PHY_INFO_T pPhyInfo, ++ IN pu1Byte pPhyStatus, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ) ++{ ++ ++ ++} ++ ++VOID ++ODM_PhyStatusQuery( ++ IN OUT PDM_ODM_T pDM_Odm, ++ OUT PODM_PHY_INFO_T pPhyInfo, ++ IN pu1Byte pPhyStatus, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ) ++{ ++#if 0 // How to jaguar jugar series?? ++ if(pDM_Odm->SupportICType >= ODM_RTL8195 ) ++ { ++ ODM_PhyStatusQuery_JaguarSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); ++ } ++ else ++#endif ++ { ++ ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); ++ } ++} ++ ++// For future use. ++VOID ++ODM_MacStatusQuery( ++ IN OUT PDM_ODM_T pDM_Odm, ++ IN pu1Byte pMacStatus, ++ IN u1Byte MacID, ++ IN BOOLEAN bPacketMatchBSSID, ++ IN BOOLEAN bPacketToSelf, ++ IN BOOLEAN bPacketBeacon ++ ) ++{ ++ // 2011/10/19 Driver team will handle in the future. ++ ++} ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP)) ++ ++HAL_STATUS ++ODM_ConfigRFWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E Content, ++ IN ODM_RF_RADIO_PATH_E eRFPath ++ ) ++{ ++ //RT_STATUS rtStatus = RT_STATUS_SUCCESS; ++ ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); ++#if (RTL8723A_SUPPORT == 1) ++ if (pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ if(eRFPath == ODM_RF_PATH_A) ++ READ_AND_CONFIG_MP(8723A,_RadioA_1T_); ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n")); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n")); ++ } ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); ++ //rtStatus = RT_STATUS_SUCCESS; ++#endif ++#if (RTL8188E_SUPPORT == 1) ++ if (pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) ++ READ_AND_CONFIG(8188E,_RadioA_1T_ICUT_); ++ else ++ READ_AND_CONFIG(8188E,_RadioA_1T_); ++ ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); ++ } ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); ++ //rtStatus = RT_STATUS_SUCCESS; ++#endif ++ return HAL_STATUS_SUCCESS; ++} ++ ++ ++HAL_STATUS ++ODM_ConfigBBWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_BB_Config_Type ConfigType ++ ) ++{ ++#if (RTL8723A_SUPPORT == 1) ++ if(pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ ++ if(ConfigType == CONFIG_BB_PHY_REG) ++ { ++ READ_AND_CONFIG_MP(8723A,_PHY_REG_1T_); ++ } ++ else if(ConfigType == CONFIG_BB_AGC_TAB) ++ { ++ READ_AND_CONFIG_MP(8723A,_AGC_TAB_1T_); ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n")); ++ } ++#endif ++ ++#if (RTL8188E_SUPPORT == 1) ++ if(pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ ++ if(ConfigType == CONFIG_BB_PHY_REG) ++ { ++ if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) ++ READ_AND_CONFIG(8188E,_PHY_REG_1T_ICUT_); ++ else ++ READ_AND_CONFIG(8188E,_PHY_REG_1T_); ++ } ++ else if(ConfigType == CONFIG_BB_AGC_TAB) ++ { ++ if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) ++ READ_AND_CONFIG(8188E,_AGC_TAB_1T_ICUT_); ++ else ++ READ_AND_CONFIG(8188E,_AGC_TAB_1T_); ++ } ++ else if(ConfigType == CONFIG_BB_PHY_REG_PG) ++ { ++ READ_AND_CONFIG(8188E,_PHY_REG_PG_); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); ++ } ++ } ++#endif ++ ++ return HAL_STATUS_SUCCESS; ++} ++ ++HAL_STATUS ++ODM_ConfigMACWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u1Byte result = HAL_STATUS_SUCCESS; ++#if (RTL8723A_SUPPORT == 1) ++ if (pDM_Odm->SupportICType == ODM_RTL8723A) ++ { ++ READ_AND_CONFIG_MP(8723A,_MAC_REG_); ++ } ++#endif ++#if (RTL8188E_SUPPORT == 1) ++ if (pDM_Odm->SupportICType == ODM_RTL8188E) ++ { ++ if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) ++ READ_AND_CONFIG(8188E,_MAC_REG_ICUT_); ++ else ++ result =READ_AND_CONFIG(8188E,_MAC_REG_); ++ } ++#endif ++ ++ return result; ++} ++ ++ ++#endif // end of (#if DM_ODM_SUPPORT_TYPE) ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.h +new file mode 100644 +index 00000000..9b53a8aa +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_HWConfig.h +@@ -0,0 +1,195 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __HALHWOUTSRC_H__ ++#define __HALHWOUTSRC_H__ ++ ++//============================================================ ++// Definition ++//============================================================ ++// ++//----------------------------------------------------------- ++// CCK Rates, TxHT = 0 ++#define DESC92C_RATE1M 0x00 ++#define DESC92C_RATE2M 0x01 ++#define DESC92C_RATE5_5M 0x02 ++#define DESC92C_RATE11M 0x03 ++ ++// OFDM Rates, TxHT = 0 ++#define DESC92C_RATE6M 0x04 ++#define DESC92C_RATE9M 0x05 ++#define DESC92C_RATE12M 0x06 ++#define DESC92C_RATE18M 0x07 ++#define DESC92C_RATE24M 0x08 ++#define DESC92C_RATE36M 0x09 ++#define DESC92C_RATE48M 0x0a ++#define DESC92C_RATE54M 0x0b ++ ++// MCS Rates, TxHT = 1 ++#define DESC92C_RATEMCS0 0x0c ++#define DESC92C_RATEMCS1 0x0d ++#define DESC92C_RATEMCS2 0x0e ++#define DESC92C_RATEMCS3 0x0f ++#define DESC92C_RATEMCS4 0x10 ++#define DESC92C_RATEMCS5 0x11 ++#define DESC92C_RATEMCS6 0x12 ++#define DESC92C_RATEMCS7 0x13 ++#define DESC92C_RATEMCS8 0x14 ++#define DESC92C_RATEMCS9 0x15 ++#define DESC92C_RATEMCS10 0x16 ++#define DESC92C_RATEMCS11 0x17 ++#define DESC92C_RATEMCS12 0x18 ++#define DESC92C_RATEMCS13 0x19 ++#define DESC92C_RATEMCS14 0x1a ++#define DESC92C_RATEMCS15 0x1b ++#define DESC92C_RATEMCS15_SG 0x1c ++#define DESC92C_RATEMCS32 0x20 ++ ++ ++//============================================================ ++// structure and define ++//============================================================ ++ ++typedef struct _Phy_Rx_AGC_Info ++{ ++ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) ++ u1Byte gain:7,trsw:1; ++ #else ++ u1Byte trsw:1,gain:7; ++ #endif ++} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T; ++ ++typedef struct _Phy_Status_Rpt_8192cd ++{ ++ PHY_RX_AGC_INFO_T path_agc[2]; ++ u1Byte ch_corr[2]; ++ u1Byte cck_sig_qual_ofdm_pwdb_all; ++ u1Byte cck_agc_rpt_ofdm_cfosho_a; ++ u1Byte cck_rpt_b_ofdm_cfosho_b; ++ u1Byte rsvd_1;//ch_corr_msb; ++ u1Byte noise_power_db_msb; ++ u1Byte path_cfotail[2]; ++ u1Byte pcts_mask[2]; ++ s1Byte stream_rxevm[2]; ++ u1Byte path_rxsnr[2]; ++ u1Byte noise_power_db_lsb; ++ u1Byte rsvd_2[3]; ++ u1Byte stream_csi[2]; ++ u1Byte stream_target_csi[2]; ++ s1Byte sig_evm; ++ u1Byte rsvd_3; ++ ++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) ++ u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; ++ u1Byte sgi_en:1; ++ u1Byte rxsc:2; ++ u1Byte idle_long:1; ++ u1Byte r_ant_train_en:1; ++ u1Byte ant_sel_b:1; ++ u1Byte ant_sel:1; ++#else // _BIG_ENDIAN_ ++ u1Byte ant_sel:1; ++ u1Byte ant_sel_b:1; ++ u1Byte r_ant_train_en:1; ++ u1Byte idle_long:1; ++ u1Byte rxsc:2; ++ u1Byte sgi_en:1; ++ u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; ++#endif ++} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T; ++ ++ ++typedef struct _Phy_Status_Rpt_8195 ++{ ++ PHY_RX_AGC_INFO_T path_agc[2]; ++ u1Byte ch_num[2]; ++ u1Byte cck_sig_qual_ofdm_pwdb_all; ++ u1Byte cck_agc_rpt_ofdm_cfosho_a; ++ u1Byte cck_bb_pwr_ofdm_cfosho_b; ++ u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition) ++ u1Byte rsvd_1; ++ u1Byte path_cfotail[2]; ++ u1Byte pcts_mask[2]; ++ s1Byte stream_rxevm[2]; ++ u1Byte path_rxsnr[2]; ++ u1Byte rsvd_2[2]; ++ u1Byte stream_snr[2]; ++ u1Byte stream_csi[2]; ++ u1Byte rsvd_3[2]; ++ s1Byte sig_evm; ++ u1Byte rsvd_4; ++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) ++ u1Byte antidx_anta:3; ++ u1Byte antidx_antb:3; ++ u1Byte rsvd_5:2; ++#else // _BIG_ENDIAN_ ++ u1Byte rsvd_5:2; ++ u1Byte antidx_antb:3; ++ u1Byte antidx_anta:3; ++#endif ++} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T; ++ ++ ++VOID ++odm_Init_RSSIForDM( ++ IN OUT PDM_ODM_T pDM_Odm ++ ); ++ ++VOID ++ODM_PhyStatusQuery( ++ IN OUT PDM_ODM_T pDM_Odm, ++ OUT PODM_PHY_INFO_T pPhyInfo, ++ IN pu1Byte pPhyStatus, ++ IN PODM_PACKET_INFO_T pPktinfo ++ ); ++ ++VOID ++ODM_MacStatusQuery( ++ IN OUT PDM_ODM_T pDM_Odm, ++ IN pu1Byte pMacStatus, ++ IN u1Byte MacID, ++ IN BOOLEAN bPacketMatchBSSID, ++ IN BOOLEAN bPacketToSelf, ++ IN BOOLEAN bPacketBeacon ++ ); ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP)) ++HAL_STATUS ++ODM_ConfigRFWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E Content, ++ IN ODM_RF_RADIO_PATH_E eRFPath ++ ); ++ ++HAL_STATUS ++ODM_ConfigBBWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_BB_Config_Type ConfigType ++ ); ++ ++HAL_STATUS ++ODM_ConfigMACWithHeaderFile( ++ IN PDM_ODM_T pDM_Odm ++ ); ++#endif ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11AC.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11AC.h +new file mode 100644 +index 00000000..b2a318a9 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11AC.h +@@ -0,0 +1,55 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __ODM_REGDEFINE11AC_H__ ++#define __ODM_REGDEFINE11AC_H__ ++ ++//2 RF REG LIST ++ ++ ++ ++//2 BB REG LIST ++//PAGE 8 ++//PAGE 9 ++#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 ++//PAGE A ++#define ODM_REG_CCK_CCA_11AC 0xA0A ++#define ODM_REG_CCK_FA_RST_11AC 0xA2C ++#define ODM_REG_CCK_FA_11AC 0xA5C ++//PAGE C ++#define ODM_REG_IGI_A_11AC 0xC50 ++//PAGE E ++#define ODM_REG_IGI_B_11AC 0xE50 ++//PAGE F ++#define ODM_REG_OFDM_FA_11AC 0xF48 ++ ++ ++//2 MAC REG LIST ++ ++ ++ ++ ++//DIG Related ++#define ODM_BIT_IGI_11AC 0xFFFFFFFF ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11N.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11N.h +new file mode 100644 +index 00000000..841b1b42 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_RegDefine11N.h +@@ -0,0 +1,172 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __ODM_REGDEFINE11N_H__ ++#define __ODM_REGDEFINE11N_H__ ++ ++ ++//2 RF REG LIST ++#define ODM_REG_RF_MODE_11N 0x00 ++#define ODM_REG_RF_0B_11N 0x0B ++#define ODM_REG_CHNBW_11N 0x18 ++#define ODM_REG_T_METER_11N 0x24 ++#define ODM_REG_RF_25_11N 0x25 ++#define ODM_REG_RF_26_11N 0x26 ++#define ODM_REG_RF_27_11N 0x27 ++#define ODM_REG_RF_2B_11N 0x2B ++#define ODM_REG_RF_2C_11N 0x2C ++#define ODM_REG_RXRF_A3_11N 0x3C ++#define ODM_REG_T_METER_92D_11N 0x42 ++#define ODM_REG_T_METER_88E_11N 0x42 ++ ++ ++ ++//2 BB REG LIST ++//PAGE 8 ++#define ODM_REG_BB_CTRL_11N 0x800 ++#define ODM_REG_RF_PIN_11N 0x804 ++#define ODM_REG_PSD_CTRL_11N 0x808 ++#define ODM_REG_TX_ANT_CTRL_11N 0x80C ++#define ODM_REG_BB_PWR_SAV5_11N 0x818 ++#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 ++#define ODM_REG_RX_DEFUALT_A_11N 0x858 ++#define ODM_REG_RX_DEFUALT_B_11N 0x85A ++#define ODM_REG_BB_PWR_SAV3_11N 0x85C ++#define ODM_REG_ANTSEL_CTRL_11N 0x860 ++#define ODM_REG_RX_ANT_CTRL_11N 0x864 ++#define ODM_REG_PIN_CTRL_11N 0x870 ++#define ODM_REG_BB_PWR_SAV1_11N 0x874 ++#define ODM_REG_ANTSEL_PATH_11N 0x878 ++#define ODM_REG_BB_3WIRE_11N 0x88C ++#define ODM_REG_SC_CNT_11N 0x8C4 ++#define ODM_REG_PSD_DATA_11N 0x8B4 ++//PAGE 9 ++#define ODM_REG_ANT_MAPPING1_11N 0x914 ++#define ODM_REG_ANT_MAPPING2_11N 0x918 ++//PAGE A ++#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 ++#define ODM_REG_CCK_CCA_11N 0xA0A ++#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C ++#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 ++#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 ++#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 ++#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 ++#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 ++#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 ++#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 ++#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 ++#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 ++#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 ++#define ODM_REG_CCK_FA_RST_11N 0xA2C ++#define ODM_REG_CCK_FA_MSB_11N 0xA58 ++#define ODM_REG_CCK_FA_LSB_11N 0xA5C ++#define ODM_REG_CCK_CCA_CNT_11N 0xA60 ++#define ODM_REG_BB_PWR_SAV4_11N 0xA74 ++//PAGE B ++#define ODM_REG_LNA_SWITCH_11N 0xB2C ++#define ODM_REG_PATH_SWITCH_11N 0xB30 ++#define ODM_REG_RSSI_CTRL_11N 0xB38 ++#define ODM_REG_CONFIG_ANTA_11N 0xB68 ++#define ODM_REG_RSSI_BT_11N 0xB9C ++//PAGE C ++#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 ++#define ODM_REG_RX_PATH_11N 0xC04 ++#define ODM_REG_TRMUX_11N 0xC08 ++#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C ++#define ODM_REG_RXIQI_MATRIX_11N 0xC14 ++#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C ++#define ODM_REG_IGI_A_11N 0xC50 ++#define ODM_REG_ANTDIV_PARA2_11N 0xC54 ++#define ODM_REG_IGI_B_11N 0xC58 ++#define ODM_REG_ANTDIV_PARA3_11N 0xC5C ++#define ODM_REG_BB_PWR_SAV2_11N 0xC70 ++#define ODM_REG_RX_OFF_11N 0xC7C ++#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 ++#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 ++#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 ++#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C ++#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 ++#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 ++#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 ++//PAGE D ++#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 ++#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 ++#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 ++#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 ++//PAGE E ++#define ODM_REG_TXAGC_A_6_18_11N 0xE00 ++#define ODM_REG_TXAGC_A_24_54_11N 0xE04 ++#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 ++#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 ++#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 ++#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 ++#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C ++#define ODM_REG_FPGA0_IQK_11N 0xE28 ++#define ODM_REG_TXIQK_TONE_A_11N 0xE30 ++#define ODM_REG_RXIQK_TONE_A_11N 0xE34 ++#define ODM_REG_TXIQK_PI_A_11N 0xE38 ++#define ODM_REG_RXIQK_PI_A_11N 0xE3C ++#define ODM_REG_TXIQK_11N 0xE40 ++#define ODM_REG_RXIQK_11N 0xE44 ++#define ODM_REG_IQK_AGC_PTS_11N 0xE48 ++#define ODM_REG_IQK_AGC_RSP_11N 0xE4C ++#define ODM_REG_BLUETOOTH_11N 0xE6C ++#define ODM_REG_RX_WAIT_CCA_11N 0xE70 ++#define ODM_REG_TX_CCK_RFON_11N 0xE74 ++#define ODM_REG_TX_CCK_BBON_11N 0xE78 ++#define ODM_REG_OFDM_RFON_11N 0xE7C ++#define ODM_REG_OFDM_BBON_11N 0xE80 ++#define ODM_REG_TX2RX_11N 0xE84 ++#define ODM_REG_TX2TX_11N 0xE88 ++#define ODM_REG_RX_CCK_11N 0xE8C ++#define ODM_REG_RX_OFDM_11N 0xED0 ++#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 ++#define ODM_REG_RX2RX_11N 0xED8 ++#define ODM_REG_STANDBY_11N 0xEDC ++#define ODM_REG_SLEEP_11N 0xEE0 ++#define ODM_REG_PMPD_ANAEN_11N 0xEEC ++ ++ ++ ++ ++ ++ ++ ++//2 MAC REG LIST ++#define ODM_REG_BB_RST_11N 0x02 ++#define ODM_REG_ANTSEL_PIN_11N 0x4C ++#define ODM_REG_EARLY_MODE_11N 0x4D0 ++#define ODM_REG_RSSI_MONITOR_11N 0x4FE ++#define ODM_REG_EDCA_VO_11N 0x500 ++#define ODM_REG_EDCA_VI_11N 0x504 ++#define ODM_REG_EDCA_BE_11N 0x508 ++#define ODM_REG_EDCA_BK_11N 0x50C ++#define ODM_REG_TXPAUSE_11N 0x522 ++#define ODM_REG_RESP_TX_11N 0x6D8 ++#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 ++#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 ++ ++ ++//DIG Related ++#define ODM_BIT_IGI_11N 0x0000007F ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.c +new file mode 100644 +index 00000000..7db60cf5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.c +@@ -0,0 +1,627 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++//============================================================ ++// include files ++//============================================================ ++ ++#include "odm_precomp.h" ++ ++VOID ++ODM_InitDebugSetting( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++pDM_Odm->DebugLevel = ODM_DBG_TRACE; ++ ++pDM_Odm->DebugComponents = ++\ ++#if DBG ++//BB Functions ++// ODM_COMP_DIG | ++// ODM_COMP_RA_MASK | ++// ODM_COMP_DYNAMIC_TXPWR | ++// ODM_COMP_FA_CNT | ++// ODM_COMP_RSSI_MONITOR | ++// ODM_COMP_CCK_PD | ++// ODM_COMP_ANT_DIV | ++// ODM_COMP_PWR_SAVE | ++// ODM_COMP_PWR_TRAIN | ++// ODM_COMP_RATE_ADAPTIVE | ++// ODM_COMP_PATH_DIV | ++// ODM_COMP_DYNAMIC_PRICCA | ++// ODM_COMP_RXHP | ++ ++//MAC Functions ++// ODM_COMP_EDCA_TURBO | ++// ODM_COMP_EARLY_MODE | ++//RF Functions ++// ODM_COMP_TX_PWR_TRACK | ++// ODM_COMP_RX_GAIN_TRACK | ++// ODM_COMP_CALIBRATION | ++//Common ++// ODM_COMP_COMMON | ++// ODM_COMP_INIT | ++#endif ++ 0; ++} ++ ++#if 0 ++/*------------------Declare variable----------------------- ++// Define debug flag array for common debug print macro. */ ++u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX]; ++ ++/* Define debug print header for every service module. */ ++ODM_DBGP_HEAD_T ODM_DBGP_Head; ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: DBGP_Flag_Init ++ * ++ * Overview: Refresh all debug print control flag content to zero. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 10/20/2006 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern void ODM_DBGP_Flag_Init(void) ++{ ++ u1Byte i; ++ ++ for (i = 0; i < ODM_DBGP_TYPE_MAX; i++) ++ { ++ ODM_DBGP_Type[i] = 0; ++ } ++ ++#ifndef ADSL_AP_BUILD_WORKAROUND ++#if DBG ++ // 2010/06/02 MH Free build driver can not out any debug message!!! ++ // Init Debug flag enable condition ++ ++ ODM_DBGP_Type[FINIT] = \ ++// INIT_EEPROM | ++// INIT_TxPower | ++// INIT_IQK | ++// INIT_RF | ++ 0; ++ ++ ODM_DBGP_Type[FDM] = \ ++// WA_IOT | ++// DM_PWDB | ++// DM_Monitor | ++// DM_DIG | ++// DM_EDCA_Turbo | ++// DM_BT30 | ++ 0; ++ ++ ODM_DBGP_Type[FIOCTL] = \ ++// IOCTL_IRP | ++// IOCTL_IRP_DETAIL | ++// IOCTL_IRP_STATISTICS | ++// IOCTL_IRP_HANDLE | ++// IOCTL_BT_HCICMD | ++// IOCTL_BT_HCICMD_DETAIL | ++// IOCTL_BT_HCICMD_EXT | ++// IOCTL_BT_EVENT | ++// IOCTL_BT_EVENT_DETAIL | ++// IOCTL_BT_EVENT_PERIODICAL | ++// IOCTL_BT_TX_ACLDATA | ++// IOCTL_BT_TX_ACLDATA_DETAIL | ++// IOCTL_BT_RX_ACLDATA | ++// IOCTL_BT_RX_ACLDATA_DETAIL | ++// IOCTL_BT_TP | ++// IOCTL_STATE | ++// IOCTL_BT_LOGO | ++// IOCTL_CALLBACK_FUN | ++// IOCTL_PARSE_BT_PKT | ++ 0; ++ ++ ODM_DBGP_Type[FBT] = \ ++// BT_TRACE | ++ 0; ++ ++ ODM_DBGP_Type[FEEPROM] = \ ++// EEPROM_W | ++// EFUSE_PG | ++// EFUSE_READ_ALL | ++// EFUSE_ANALYSIS | ++// EFUSE_PG_DETAIL | ++ 0; ++ ++ ODM_DBGP_Type[FDBG_CTRL] = \ ++// DBG_CTRL_TRACE | ++// DBG_CTRL_INBAND_NOISE | ++ 0; ++ ++ // 2011/07/20 MH Add for short cut ++ ODM_DBGP_Type[FSHORT_CUT] = \ ++// SHCUT_TX | ++// SHCUT_RX | ++ 0; ++ ++#endif ++#endif ++ /* Define debug header of every service module. */ ++ //ODM_DBGP_Head.pMANS = "\n\r[MANS] "; ++ //ODM_DBGP_Head.pRTOS = "\n\r[RTOS] "; ++ //ODM_DBGP_Head.pALM = "\n\r[ALM] "; ++ //ODM_DBGP_Head.pPEM = "\n\r[PEM] "; ++ //ODM_DBGP_Head.pCMPK = "\n\r[CMPK] "; ++ //ODM_DBGP_Head.pRAPD = "\n\r[RAPD] "; ++ //ODM_DBGP_Head.pTXPB = "\n\r[TXPB] "; ++ //ODM_DBGP_Head.pQUMG = "\n\r[QUMG] "; ++ ++} /* DBGP_Flag_Init */ ++ ++#endif ++ ++ ++#if 0 ++u4Byte GlobalDebugLevel = DBG_LOUD; ++// ++// 2009/06/22 MH Allow Fre build to print none debug info at init time. ++// ++#if DBG ++u8Byte GlobalDebugComponents = \ ++// COMP_TRACE | ++// COMP_DBG | ++// COMP_INIT | ++// COMP_OID_QUERY | ++// COMP_OID_SET | ++// COMP_RECV | ++// COMP_SEND | ++// COMP_IO | ++// COMP_POWER | ++// COMP_MLME | ++// COMP_SCAN | ++// COMP_SYSTEM | ++// COMP_SEC | ++// COMP_AP | ++// COMP_TURBO | ++// COMP_QOS | ++// COMP_AUTHENTICATOR | ++// COMP_BEACON | ++// COMP_ANTENNA | ++// COMP_RATE | ++// COMP_EVENTS | ++// COMP_FPGA | ++// COMP_RM | ++// COMP_MP | ++// COMP_RXDESC | ++// COMP_CKIP | ++// COMP_DIG | ++// COMP_TXAGC | ++// COMP_HIPWR | ++// COMP_HALDM | ++// COMP_RSNA | ++// COMP_INDIC | ++// COMP_LED | ++// COMP_RF | ++// COMP_DUALMACSWITCH | ++// COMP_EASY_CONCURRENT | ++ ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ ++// COMP_HT | ++// COMP_POWER_TRACKING | ++// COMP_RX_REORDER | ++// COMP_AMSDU | ++// COMP_WPS | ++// COMP_RATR | ++// COMP_RESET | ++// COMP_CMD | ++// COMP_EFUSE | ++// COMP_MESH_INTERWORKING | ++// COMP_CCX | ++// COMP_IOCTL | ++// COMP_GP | ++// COMP_TXAGG | ++// COMP_BB_POWERSAVING | ++// COMP_SWAS | ++// COMP_P2P | ++// COMP_MUX | ++// COMP_FUNC | ++// COMP_TDLS | ++// COMP_OMNIPEEK | ++// COMP_PSD | ++ 0; ++ ++ ++#else ++#define FuncEntry ++#define FuncExit ++u8Byte GlobalDebugComponents = 0; ++#endif ++ ++#if (RT_PLATFORM==PLATFORM_LINUX) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) ++EXPORT_SYMBOL(GlobalDebugComponents); ++EXPORT_SYMBOL(GlobalDebugLevel); ++#endif ++#endif ++ ++/*------------------Declare variable----------------------- ++// Define debug flag array for common debug print macro. */ ++u4Byte DBGP_Type[DBGP_TYPE_MAX]; ++ ++/* Define debug print header for every service module. */ ++DBGP_HEAD_T DBGP_Head; ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: DBGP_Flag_Init ++ * ++ * Overview: Refresh all debug print control flag content to zero. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 10/20/2006 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern void DBGP_Flag_Init(void) ++{ ++ u1Byte i; ++ ++ for (i = 0; i < DBGP_TYPE_MAX; i++) ++ { ++ DBGP_Type[i] = 0; ++ } ++ ++#if DBG ++ // 2010/06/02 MH Free build driver can not out any debug message!!! ++ // Init Debug flag enable condition ++ ++ DBGP_Type[FINIT] = \ ++// INIT_EEPROM | ++// INIT_TxPower | ++// INIT_IQK | ++// INIT_RF | ++ 0; ++ ++ DBGP_Type[FDM] = \ ++// WA_IOT | ++// DM_PWDB | ++// DM_Monitor | ++// DM_DIG | ++// DM_EDCA_Turbo | ++// DM_BT30 | ++ 0; ++ ++ DBGP_Type[FIOCTL] = \ ++// IOCTL_IRP | ++// IOCTL_IRP_DETAIL | ++// IOCTL_IRP_STATISTICS | ++// IOCTL_IRP_HANDLE | ++// IOCTL_BT_HCICMD | ++// IOCTL_BT_HCICMD_DETAIL | ++// IOCTL_BT_HCICMD_EXT | ++// IOCTL_BT_EVENT | ++// IOCTL_BT_EVENT_DETAIL | ++// IOCTL_BT_EVENT_PERIODICAL | ++// IOCTL_BT_TX_ACLDATA | ++// IOCTL_BT_TX_ACLDATA_DETAIL | ++// IOCTL_BT_RX_ACLDATA | ++// IOCTL_BT_RX_ACLDATA_DETAIL | ++// IOCTL_BT_TP | ++// IOCTL_STATE | ++// IOCTL_BT_LOGO | ++// IOCTL_CALLBACK_FUN | ++// IOCTL_PARSE_BT_PKT | ++ 0; ++ ++ DBGP_Type[FBT] = \ ++// BT_TRACE | ++ 0; ++ ++ DBGP_Type[FEEPROM] = \ ++// EEPROM_W | ++// EFUSE_PG | ++// EFUSE_READ_ALL | ++// EFUSE_ANALYSIS | ++// EFUSE_PG_DETAIL | ++ 0; ++ ++ DBGP_Type[FDBG_CTRL] = \ ++// DBG_CTRL_TRACE | ++// DBG_CTRL_INBAND_NOISE | ++ 0; ++ ++ // 2011/07/20 MH Add for short cut ++ DBGP_Type[FSHORT_CUT] = \ ++// SHCUT_TX | ++// SHCUT_RX | ++ 0; ++ ++#endif ++ /* Define debug header of every service module. */ ++ DBGP_Head.pMANS = "\n\r[MANS] "; ++ DBGP_Head.pRTOS = "\n\r[RTOS] "; ++ DBGP_Head.pALM = "\n\r[ALM] "; ++ DBGP_Head.pPEM = "\n\r[PEM] "; ++ DBGP_Head.pCMPK = "\n\r[CMPK] "; ++ DBGP_Head.pRAPD = "\n\r[RAPD] "; ++ DBGP_Head.pTXPB = "\n\r[TXPB] "; ++ DBGP_Head.pQUMG = "\n\r[QUMG] "; ++ ++} /* DBGP_Flag_Init */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: DBG_PrintAllFlag ++ * ++ * Overview: Print All debug flag ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern void DBG_PrintAllFlag(void) ++{ ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n")); ++} // DBG_PrintAllFlag ++ ++ ++extern void DBG_PrintAllComp(void) ++{ ++ u1Byte i; ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n")); ++ ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents)); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP =")); ++ for (i = 0; i < 64; i++) ++ { ++ if (GlobalDebugComponents & ((u8Byte)0x1 << i) ) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i)); ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n")); ++ ++} // DBG_PrintAllComp ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: DBG_PrintFlagEvent ++ * ++ * Overview: Print dedicated debug flag event ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern void DBG_PrintFlagEvent(u1Byte DbgFlag) ++{ ++ switch(DbgFlag) ++ { ++ case FQoS: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n")); ++ break; ++ ++ case FTX: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n")); ++ break; ++ ++ case FRX: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n")); ++ break; ++ ++ case FSEC: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n")); ++ break; ++ ++ case FMGNT: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n")); ++ break; ++ ++ case FMLME: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n")); ++ break; ++ ++ case FRESOURCE: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n")); ++ break; ++ ++ case FBEACON: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n")); ++ break; ++ ++ case FISR: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n")); ++ break; ++ ++ case FPHY: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n")); ++ break; ++ ++ case FMP: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n")); ++ break; ++ ++ case FEEPROM: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n")); ++ break; ++ ++ case FPWR: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n")); ++ break; ++ ++ case FDM: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n")); ++ break; ++ ++ case FDBG_CTRL: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n")); ++ break; ++ ++ case FC2H: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n")); ++ break; ++ ++ case FBT: ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n")); ++ ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n")); ++ break; ++ ++ default: ++ break; ++ } ++ ++} // DBG_PrintFlagEvent ++ ++ ++extern void DBG_DumpMem(const u1Byte DbgComp, ++ const u1Byte DbgLevel, ++ pu1Byte pMem, ++ u2Byte Len) ++{ ++ u2Byte i; ++ ++ for (i=0;i<((Len>>3) + 1);i++) ++ { ++ ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n", ++ *(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)), ++ *(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7)))); ++ ++ } ++} ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.h +new file mode 100644 +index 00000000..f8670c9a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_debug.h +@@ -0,0 +1,905 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __ODM_DBG_H__ ++#define __ODM_DBG_H__ ++ ++ ++//----------------------------------------------------------------------------- ++// Define the debug levels ++// ++// 1. DBG_TRACE and DBG_LOUD are used for normal cases. ++// So that, they can help SW engineer to develope or trace states changed ++// and also help HW enginner to trace every operation to and from HW, ++// e.g IO, Tx, Rx. ++// ++// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, ++// which help us to debug SW or HW. ++// ++//----------------------------------------------------------------------------- ++// ++// Never used in a call to ODM_RT_TRACE()! ++// ++#define ODM_DBG_OFF 1 ++ ++// ++// Fatal bug. ++// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, ++// resource allocation failed, unexpected HW behavior, HW BUG and so on. ++// ++#define ODM_DBG_SERIOUS 2 ++ ++// ++// Abnormal, rare, or unexpeted cases. ++// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. ++// ++#define ODM_DBG_WARNING 3 ++ ++// ++// Normal case with useful information about current SW or HW state. ++// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, ++// SW protocol state change, dynamic mechanism state change and so on. ++// ++#define ODM_DBG_LOUD 4 ++ ++// ++// Normal case with detail execution flow or information. ++// ++#define ODM_DBG_TRACE 5 ++ ++//----------------------------------------------------------------------------- ++// Define the tracing components ++// ++//----------------------------------------------------------------------------- ++//BB Functions ++#define ODM_COMP_DIG BIT0 ++#define ODM_COMP_RA_MASK BIT1 ++#define ODM_COMP_DYNAMIC_TXPWR BIT2 ++#define ODM_COMP_FA_CNT BIT3 ++#define ODM_COMP_RSSI_MONITOR BIT4 ++#define ODM_COMP_CCK_PD BIT5 ++#define ODM_COMP_ANT_DIV BIT6 ++#define ODM_COMP_PWR_SAVE BIT7 ++#define ODM_COMP_PWR_TRAIN BIT8 ++#define ODM_COMP_RATE_ADAPTIVE BIT9 ++#define ODM_COMP_PATH_DIV BIT10 ++#define ODM_COMP_PSD BIT11 ++#define ODM_COMP_DYNAMIC_PRICCA BIT12 ++#define ODM_COMP_RXHP BIT13 ++//MAC Functions ++#define ODM_COMP_EDCA_TURBO BIT16 ++#define ODM_COMP_EARLY_MODE BIT17 ++//RF Functions ++#define ODM_COMP_TX_PWR_TRACK BIT24 ++#define ODM_COMP_RX_GAIN_TRACK BIT25 ++#define ODM_COMP_CALIBRATION BIT26 ++//Common Functions ++#define ODM_COMP_COMMON BIT30 ++#define ODM_COMP_INIT BIT31 ++ ++/*------------------------Export Marco Definition---------------------------*/ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++#define RT_PRINTK DbgPrint ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ #define DbgPrint printk ++ #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); ++#else ++ #define DbgPrint panic_printk ++#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); ++#endif ++ ++#ifndef ASSERT ++ #define ASSERT(expr) ++#endif ++ ++#if DBG ++#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ ++ if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ ++ { \ ++ if(pDM_Odm->SupportICType == ODM_RTL8192C) \ ++ DbgPrint("[ODM-92C] "); \ ++ else if(pDM_Odm->SupportICType == ODM_RTL8192D) \ ++ DbgPrint("[ODM-92D] "); \ ++ else if(pDM_Odm->SupportICType == ODM_RTL8723A) \ ++ DbgPrint("[ODM-8723A] "); \ ++ else if(pDM_Odm->SupportICType == ODM_RTL8188E) \ ++ DbgPrint("[ODM-8188E] "); \ ++ else if(pDM_Odm->SupportICType == ODM_RTL8812) \ ++ DbgPrint("[ODM-8812] "); \ ++ else if(pDM_Odm->SupportICType == ODM_RTL8821) \ ++ DbgPrint("[ODM-8821] "); \ ++ RT_PRINTK fmt; \ ++ } ++ ++#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ ++ if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ ++ { \ ++ RT_PRINTK fmt; \ ++ } ++ ++#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ ++ if(!(expr)) { \ ++ DbgPrint( "Assertion failed! %s at ......\n", #expr); \ ++ DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ ++ RT_PRINTK fmt; \ ++ ASSERT(FALSE); \ ++ } ++#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } ++#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } ++#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } ++ ++#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ ++ if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ ++ { \ ++ int __i; \ ++ pu1Byte __ptr = (pu1Byte)ptr; \ ++ DbgPrint("[ODM] "); \ ++ DbgPrint(title_str); \ ++ DbgPrint(" "); \ ++ for( __i=0; __i<6; __i++ ) \ ++ DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ ++ DbgPrint("\n"); \ ++ } ++#else ++#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) ++#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) ++#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) ++#define ODM_dbg_enter() ++#define ODM_dbg_exit() ++#define ODM_dbg_trace(str) ++#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) ++#endif ++ ++ ++VOID ++ODM_InitDebugSetting( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++ ++ ++#if 0 ++#if DBG ++#define DbgPrint printk ++ ++#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ ++ { \ ++ char *szTitle = _TitleString; \ ++ pu1Byte pbtHexData = _HexData; \ ++ u4Byte u4bHexDataLen = _HexDataLen; \ ++ u4Byte __i; \ ++ DbgPrint("%s", szTitle); \ ++ for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. ++ ++#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ ++ if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \ ++ { \ ++ int __i; \ ++ u1Byte buffer[MAX_STR_LEN]; \ ++ int length = (_Len\n", _Len, buffer); \ ++ } ++ ++#else // of #if DBG ++#define DbgPrint(...) ++#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) ++#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) ++#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) ++#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) ++#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) ++#endif // of #if DBG ++ ++#endif ++ ++ ++#if 0 ++/* Define debug print header for every service module.*/ ++typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure ++{ ++ const char *pMANS; ++ const char *pRTOS; ++ const char *pALM; ++ const char *pPEM; ++ const char *pCMPK; ++ const char *pRAPD; ++ const char *pTXPB; ++ const char *pQUMG; ++}ODM_DBGP_HEAD_T; ++ ++ ++/* Define different debug flag for dedicated service modules in debug flag array. */ ++// Each module has independt 32 bit debug flag you cnn define the flag as yout require. ++typedef enum tag_ODM_DBGP_Flag_Type_Definition ++{ ++ ODM_FTX = 0, ++ ODM_FRX , ++ ODM_FPHY , ++ ODM_FPWR , ++ ODM_FDM , ++ ODM_FC2H , ++ ODM_FBT , ++ ODM_DBGP_TYPE_MAX ++}ODM_DBGP_FLAG_E; ++ ++ ++// Define TX relative debug bit --> FTX ++#define ODM_TX_DESC BIT0 ++#define ODM_TX_DESC_TID BIT1 ++#define ODM_TX_PATH BIT2 ++ ++// Define RX relative debug bit --> FRX ++#define ODM_RX_DATA BIT0 ++#define ODM_RX_PHY_STS BIT1 ++#define ODM_RX_PHY_SS BIT2 ++#define ODM_RX_PHY_SQ BIT3 ++#define ODM_RX_PHY_ASTS BIT4 ++#define ODM_RX_ERR_LEN BIT5 ++#define ODM_RX_DEFRAG BIT6 ++#define ODM_RX_ERR_RATE BIT7 ++#define ODM_RX_PATH BIT8 ++#define ODM_RX_BEACON BIT9 ++ ++// Define PHY-BB/RF/MAC check module bit --> FPHY ++#define ODM_PHY_BBR BIT0 ++#define ODM_PHY_BBW BIT1 ++#define ODM_PHY_RFR BIT2 ++#define ODM_PHY_RFW BIT3 ++#define ODM_PHY_MACR BIT4 ++#define ODM_PHY_MACW BIT5 ++#define ODM_PHY_ALLR BIT6 ++#define ODM_PHY_ALLW BIT7 ++#define ODM_PHY_TXPWR BIT8 ++#define ODM_PHY_PWRDIFF BIT9 ++#define ODM_PHY_SICR BIT10 ++#define ODM_PHY_SICW BIT11 ++ ++ ++ ++ ++extern u4Byte ODM_GlobalDebugLevel; ++ ++ ++#if DBG ++extern u8Byte ODM_GlobalDebugComponents; ++#endif ++#endif ++#if 0 ++ ++//----------------------------------------------------------------------------- ++// Define the debug levels ++// ++// 1. DBG_TRACE and DBG_LOUD are used for normal cases. ++// So that, they can help SW engineer to develope or trace states changed ++// and also help HW enginner to trace every operation to and from HW, ++// e.g IO, Tx, Rx. ++// ++// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, ++// which help us to debug SW or HW. ++// ++//----------------------------------------------------------------------------- ++// ++// Never used in a call to ODM_RT_TRACE(pDM_Odm,)! ++// ++#define DBG_OFF 0 ++ ++// ++// Deprecated! Don't use it! ++// TODO: fix related debug message! ++// ++//#define DBG_SEC 1 ++ ++// ++// Fatal bug. ++// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, ++// resource allocation failed, unexpected HW behavior, HW BUG and so on. ++// ++#define DBG_SERIOUS 2 ++ ++// ++// Abnormal, rare, or unexpeted cases. ++// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. ++// ++#define DBG_WARNING 3 ++ ++// ++// Normal case with useful information about current SW or HW state. ++// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, ++// SW protocol state change, dynamic mechanism state change and so on. ++// ++#define DBG_LOUD 4 ++ ++// ++// Normal case with detail execution flow or information. ++// ++#define DBG_TRACE 5 ++ ++ ++ ++//----------------------------------------------------------------------------- ++// Define the tracing components ++// ++//----------------------------------------------------------------------------- ++#define COMP_TRACE BIT0 // For function call tracing. ++#define COMP_DBG BIT1 // Only for temporary debug message. ++#define COMP_INIT BIT2 // during driver initialization / halt / reset. ++#define COMP_OID_QUERY BIT3 // Query OID. ++#define COMP_OID_SET BIT4 // Set OID. ++#define COMP_RECV BIT5 // Reveive part data path. ++#define COMP_SEND BIT6 // Send part path. ++#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02. ++#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related. ++#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS. ++#define COMP_SCAN BIT10 // For site survey. ++#define COMP_SYSTEM BIT11 // For general platform function. ++#define COMP_SEC BIT12 // For Security. ++#define COMP_AP BIT13 // For AP mode related. ++#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21. ++#define COMP_QOS BIT15 // For QoS. ++#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30. ++#define COMP_BEACON BIT17 // For Beacon related, by rcnjko. ++#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko. ++#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling ++#define COMP_EVENTS BIT20 // Event handling ++#define COMP_FPGA BIT21 // For FPGA verfication ++#define COMP_RM BIT22 // For Radio Measurement. ++#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13 ++#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. ++#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14. ++#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko. ++#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko. ++#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko. ++#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko. ++#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW. ++#define COMP_INDIC BIT31 // For link indication ++#define COMP_LED BIT32 // For LED. ++#define COMP_RF BIT33 // For RF. ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> ++//1!!!!!!!!!!!!!!!!!!!!!!!!!!! ++ ++#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11 ++#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING ++#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder ++#define COMP_AMSDU BIT37 // For A-MSDU Debugging ++#define COMP_WPS BIT38 //WPS Debug Message ++#define COMP_RATR BIT39 ++#define COMP_RESET BIT40 ++// For debug command to print on dbgview!! ++#define COMP_CMD BIT41 ++#define COMP_EFUSE BIT42 ++#define COMP_MESH_INTERWORKING BIT43 ++#define COMP_CCX BIT44 //CCX Debug Flag ++#define COMP_IOCTL BIT45 // IO Control ++#define COMP_GP BIT46 // For generic parser. ++#define COMP_TXAGG BIT47 ++#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer ++#define COMP_TEST BIT49 ++#define COMP_BB_POWERSAVING BIT50 ++#define COMP_SWAS BIT51 // For SW Antenna Switch ++#define COMP_P2P BIT52 ++#define COMP_MUX BIT53 ++#define COMP_FUNC BIT54 ++#define COMP_TDLS BIT55 ++#define COMP_OMNIPEEK BIT56 ++#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug ++#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug ++#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH ++ ++#define COMP_DFS BIT62 ++ ++#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components ++// For debug print flag to use ++/*------------------------------Define structure----------------------------*/ ++/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ ++ ++/* Defnie structure to store different debug flag variable. Every debug flag ++ is a UINT32 integer and you can assign 32 different events. */ ++typedef struct tag_DBGP_Debug_Flag_Structure ++{ ++ u4Byte Mans; /* Main Scheduler module. */ ++ u4Byte Rtos; /* RTOS module. */ ++ u4Byte Alarm; /* Alarm module. */ ++ u4Byte Pm; /* Performance monitor module. */ ++}DBGP_FLAG_T; ++ ++/* Define debug print header for every service module.*/ ++typedef struct tag_DBGP_Service_Module_Header_Name_Structure ++{ ++ const char *pMANS; ++ const char *pRTOS; ++ const char *pALM; ++ const char *pPEM; ++ const char *pCMPK; ++ const char *pRAPD; ++ const char *pTXPB; ++ const char *pQUMG; ++}DBGP_HEAD_T; ++ ++ ++/* Define different debug flag for dedicated service modules in debug flag array. */ ++// Each module has independt 32 bit debug flag you cnn define the flag as yout require. ++typedef enum tag_DBGP_Flag_Type_Definition ++{ ++ FQoS = 0, ++ FTX = 1, ++ FRX = 2, ++ FSEC = 3, ++ FMGNT = 4, ++ FMLME = 5, ++ FRESOURCE = 6, ++ FBEACON = 7, ++ FISR = 8, ++ FPHY = 9, ++ FMP = 10, ++ FEEPROM = 11, ++ FPWR = 12, ++ FDM = 13, ++ FDBG_CTRL = 14, ++ FC2H = 15, ++ FBT = 16, ++ FINIT = 17, ++ FIOCTL = 18, ++ FSHORT_CUT = 19, ++ DBGP_TYPE_MAX ++}DBGP_FLAG_E; ++ ++ ++// Define Qos Relative debug flag bit --> FQoS ++#define QoS_INIT BIT0 ++#define QoS_VISTA BIT1 ++ ++// Define TX relative debug bit --> FTX ++#define TX_DESC BIT0 ++#define TX_DESC_TID BIT1 ++#define TX_PATH BIT2 ++ ++// Define RX relative debug bit --> FRX ++#define RX_DATA BIT0 ++#define RX_PHY_STS BIT1 ++#define RX_PHY_SS BIT2 ++#define RX_PHY_SQ BIT3 ++#define RX_PHY_ASTS BIT4 ++#define RX_ERR_LEN BIT5 ++#define RX_DEFRAG BIT6 ++#define RX_ERR_RATE BIT7 ++#define RX_PATH BIT8 ++#define RX_BEACON BIT9 ++ ++// Define Security relative debug bit --> FSEC ++ ++// Define MGNT relative debug bit --> FMGNT ++ ++// Define MLME relative debug bit --> FMLME ++#define MEDIA_STS BIT0 ++#define LINK_STS BIT1 ++ ++// Define OS resource check module bit --> FRESOURCE ++#define OS_CHK BIT0 ++ ++// Define beacon content check module bit --> FBEACON ++#define BCN_SHOW BIT0 ++#define BCN_PEER BIT1 ++ ++// Define ISR/IMR check module bit --> FISR ++#define ISR_CHK BIT0 ++ ++// Define PHY-BB/RF/MAC check module bit --> FPHY ++#define PHY_BBR BIT0 ++#define PHY_BBW BIT1 ++#define PHY_RFR BIT2 ++#define PHY_RFW BIT3 ++#define PHY_MACR BIT4 ++#define PHY_MACW BIT5 ++#define PHY_ALLR BIT6 ++#define PHY_ALLW BIT7 ++#define PHY_TXPWR BIT8 ++#define PHY_PWRDIFF BIT9 ++#define PHY_SICR BIT10 ++#define PHY_SICW BIT11 ++ ++// Define MPT driver check module bit --> FMP ++#define MP_RX BIT0 ++#define MP_SWICH_CH BIT1 ++ ++// Define EEPROM and EFUSE check module bit --> FEEPROM ++#define EEPROM_W BIT0 ++#define EFUSE_PG BIT1 ++#define EFUSE_READ_ALL BIT2 ++#define EFUSE_ANALYSIS BIT3 ++#define EFUSE_PG_DETAIL BIT4 ++ ++// Define power save check module bit --> FPWR ++#define LPS BIT0 ++#define IPS BIT1 ++#define PWRSW BIT2 ++#define PWRHW BIT3 ++#define PWRHAL BIT4 ++ ++// Define Dynamic Mechanism check module bit --> FDM ++#define WA_IOT BIT0 ++#define DM_PWDB BIT1 ++#define DM_Monitor BIT2 ++#define DM_DIG BIT3 ++#define DM_EDCA_Turbo BIT4 ++#define DM_BT30 BIT5 ++ ++// Define Dbg Control module bit --> FDBG_CTRL ++#define DBG_CTRL_TRACE BIT0 ++#define DBG_CTRL_INBAND_NOISE BIT1 ++ ++// Define FW C2H Cmd check module bit --> FC2H ++#define C2H_Summary BIT0 ++#define C2H_PacketData BIT1 ++#define C2H_ContentData BIT2 ++// Define BT Cmd check module bit --> FBT ++#define BT_TRACE BIT0 ++#define BT_RFPoll BIT1 ++ ++// Define init check for module bit --> FINIT ++#define INIT_EEPROM BIT0 ++#define INIT_TxPower BIT1 ++#define INIT_IQK BIT2 ++#define INIT_RF BIT3 ++ ++// Define IOCTL Cmd check module bit --> FIOCTL ++// section 1 : IRP related ++#define IOCTL_IRP BIT0 ++#define IOCTL_IRP_DETAIL BIT1 ++#define IOCTL_IRP_STATISTICS BIT2 ++#define IOCTL_IRP_HANDLE BIT3 ++// section 2 : HCI command/event ++#define IOCTL_BT_HCICMD BIT8 ++#define IOCTL_BT_HCICMD_DETAIL BIT9 ++#define IOCTL_BT_HCICMD_EXT BIT10 ++#define IOCTL_BT_EVENT BIT11 ++#define IOCTL_BT_EVENT_DETAIL BIT12 ++#define IOCTL_BT_EVENT_PERIODICAL BIT13 ++// section 3 : BT tx/rx data and throughput ++#define IOCTL_BT_TX_ACLDATA BIT16 ++#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17 ++#define IOCTL_BT_RX_ACLDATA BIT18 ++#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19 ++#define IOCTL_BT_TP BIT20 ++// section 4 : BT connection state machine. ++#define IOCTL_STATE BIT21 ++#define IOCTL_BT_LOGO BIT22 ++// section 5 : BT function trace ++#define IOCTL_CALLBACK_FUN BIT24 ++#define IOCTL_PARSE_BT_PKT BIT25 ++#define IOCTL_BT_TX_PKT BIT26 ++#define IOCTL_BT_FLAG_MON BIT27 ++ ++// ++// Define init check for module bit --> FSHORT_CUT ++// 2011/07/20 MH Add for short but definition. ++// ++#define SHCUT_TX BIT0 ++#define SHCUT_RX BIT1 ++ ++ ++/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args); ++ ++#if DBG ++#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \ ++ if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ ++ { \ ++ RT_PRINTK fmt; \ ++ } ++ ++#define RT_TRACE_F(comp, level, fmt) \ ++ if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ ++ { \ ++ RT_PRINTK fmt; \ ++ } ++ ++#define RT_ASSERT(expr,fmt) \ ++ if(!(expr)) { \ ++ printk( "Assertion failed! %s at ......\n", #expr); \ ++ printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ ++ } ++#define dbg_enter() { printk("==> %s\n", __FUNCTION__); } ++#define dbg_exit() { printk("<== %s\n", __FUNCTION__); } ++#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); } ++#else ++#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) ++#define RT_TRACE_F(comp, level, fmt) ++#define RT_ASSERT(expr, fmt) ++#define dbg_enter() ++#define dbg_exit() ++#define dbg_trace(str) ++#endif ++ ++#if DBG ++#define DbgPrint printk ++ ++#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ ++ { \ ++ char *szTitle = _TitleString; \ ++ pu1Byte pbtHexData = _HexData; \ ++ u4Byte u4bHexDataLen = _HexDataLen; \ ++ u4Byte __i; \ ++ DbgPrint("%s", szTitle); \ ++ for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. ++ ++#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ ++ if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ ++ { \ ++ int __i; \ ++ u1Byte buffer[MAX_STR_LEN]; \ ++ int length = (_Len\n", _Len, buffer); \ ++ } ++ ++#else // of #if DBG ++#define DbgPrint(...) ++#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) ++#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) ++#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) ++#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) ++#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) ++#endif // of #if DBG ++ ++ ++ ++#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++ ++#define DEBUG_PRINT 1 ++ ++// Please add new OS's print API by yourself ++ ++//#if (RT_PLATFORM==PLATFORM_WINDOWS) ++#if (DEBUG_PRINT == 1) && DBG ++#define RTPRINT(dbgtype, dbgflag, printstr)\ ++{\ ++ if (DBGP_Type[dbgtype] & dbgflag)\ ++ {\ ++ DbgPrint printstr;\ ++ }\ ++} ++ ++#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\ ++{\ ++ if (DBGP_Type[dbgtype] & dbgflag)\ ++ {\ ++ int __i; \ ++ pu1Byte ptr = (pu1Byte)_Ptr; \ ++ DbgPrint printstr; \ ++ DbgPrint(" "); \ ++ for( __i=0; __i<6; __i++ ) \ ++ DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \ ++ DbgPrint("\n"); \ ++ }\ ++} ++ ++#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\ ++{\ ++ if (DBGP_Type[dbgtype] & dbgflag)\ ++ {\ ++ int __i; \ ++ pu1Byte ptr = (pu1Byte)_HexData; \ ++ DbgPrint(_TitleString); \ ++ for( __i=0; __i<(int)_HexDataLen; __i++ ) \ ++ { \ ++ DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\ ++ if (((__i + 1) % 16) == 0) DbgPrint("\n");\ ++ } \ ++ DbgPrint("\n"); \ ++ }\ ++} ++#define FuncEntry FunctionIn(COMP_FUNC) ++#define FuncExit FunctionOut(COMP_FUNC) ++ ++#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__)) ++#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__)) ++ ++ ++#else ++ ++#define DBGP(dbgtype, dbgflag, printstr) ++#define RTPRINT(dbgtype, dbgflag, printstr) ++#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr) ++#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen) ++#define FuncEntry ++#define FuncExit ++#define FunctionIn(_comp) ++#define FunctionOut(_comp) ++#endif ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++extern u4Byte DBGP_Type[DBGP_TYPE_MAX]; ++extern DBGP_HEAD_T DBGP_Head; ++ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++extern void DBGP_Flag_Init(void); ++extern void DBG_PrintAllFlag(void); ++extern void DBG_PrintAllComp(void); ++extern void DBG_PrintFlagEvent(u1Byte DbgFlag); ++extern void DBG_DumpMem(const u1Byte DbgComp, ++ const u1Byte DbgLevel, ++ pu1Byte pMem, ++ u2Byte Len); ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++extern u4Byte GlobalDebugLevel; ++extern u8Byte GlobalDebugComponents; ++ ++ ++#endif ++ ++ ++#endif // __ODM_DBG_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.c +new file mode 100644 +index 00000000..7f6dd58b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.c +@@ -0,0 +1,666 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++//============================================================ ++// include files ++//============================================================ ++ ++#include "odm_precomp.h" ++// ++// ODM IO Relative API. ++// ++ ++u1Byte ++ODM_Read1Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ return RTL_R8(RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return rtw_read8(Adapter,RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PlatformEFIORead1Byte(Adapter, RegAddr); ++#endif ++ ++} ++ ++ ++u2Byte ++ODM_Read2Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ return RTL_R16(RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return rtw_read16(Adapter,RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PlatformEFIORead2Byte(Adapter, RegAddr); ++#endif ++ ++} ++ ++ ++u4Byte ++ODM_Read4Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ return RTL_R32(RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return rtw_read32(Adapter,RegAddr); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PlatformEFIORead4Byte(Adapter, RegAddr); ++#endif ++ ++} ++ ++ ++VOID ++ODM_Write1Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u1Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ RTL_W8(RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ rtw_write8(Adapter,RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); ++#endif ++ ++} ++ ++ ++VOID ++ODM_Write2Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u2Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ RTL_W16(RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ rtw_write16(Adapter,RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); ++#endif ++ ++} ++ ++ ++VOID ++ODM_Write4Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ RTL_W32(RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ rtw_write32(Adapter,RegAddr, Data); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); ++#endif ++ ++} ++ ++ ++VOID ++ODM_SetMACReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); ++#endif ++} ++ ++ ++u4Byte ++ODM_GetMACReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PHY_QueryBBReg(Adapter, RegAddr, BitMask); ++#endif ++} ++ ++ ++VOID ++ODM_SetBBReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); ++#endif ++} ++ ++ ++u4Byte ++ODM_GetBBReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PHY_QueryBBReg(Adapter, RegAddr, BitMask); ++#endif ++} ++ ++ ++VOID ++ODM_SetRFReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E eRFPath, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); ++#endif ++} ++ ++ ++u4Byte ++ODM_GetRFReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E eRFPath, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); ++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); ++#endif ++} ++ ++ ++ ++ ++// ++// ODM Memory relative API. ++// ++VOID ++ODM_AllocateMemory( ++ IN PDM_ODM_T pDM_Odm, ++ OUT PVOID *pPtr, ++ IN u4Byte length ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ *pPtr = kmalloc(length, GFP_ATOMIC); ++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) ++ *pPtr = rtw_zvmalloc(length); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformAllocateMemory(Adapter, pPtr, length); ++#endif ++} ++ ++// length could be ignored, used to detect memory leakage. ++VOID ++ODM_FreeMemory( ++ IN PDM_ODM_T pDM_Odm, ++ OUT PVOID pPtr, ++ IN u4Byte length ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ kfree(pPtr); ++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) ++ rtw_vmfree(pPtr, length); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ //PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformFreeMemory(pPtr, length); ++#endif ++} ++s4Byte ODM_CompareMemory( ++ IN PDM_ODM_T pDM_Odm, ++ IN PVOID pBuf1, ++ IN PVOID pBuf2, ++ IN u4Byte length ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ return memcmp(pBuf1,pBuf2,length); ++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) ++ return _rtw_memcmp(pBuf1,pBuf2,length); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ return PlatformCompareMemory(pBuf1,pBuf2,length); ++#endif ++} ++ ++ ++ ++// ++// ODM MISC relative API. ++// ++VOID ++ODM_AcquireSpinLock( ++ IN PDM_ODM_T pDM_Odm, ++ IN RT_SPINLOCK_TYPE type ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformAcquireSpinLock(Adapter, type); ++#endif ++} ++VOID ++ODM_ReleaseSpinLock( ++ IN PDM_ODM_T pDM_Odm, ++ IN RT_SPINLOCK_TYPE type ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformReleaseSpinLock(Adapter, type); ++#endif ++} ++ ++// ++// Work item relative API. FOr MP driver only~! ++// ++VOID ++ODM_InitializeWorkItem( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_WORK_ITEM pRtWorkItem, ++ IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, ++ IN PVOID pContext, ++ IN const char* szID ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); ++#endif ++} ++ ++ ++VOID ++ODM_StartWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformStartWorkItem(pRtWorkItem); ++#endif ++} ++ ++ ++VOID ++ODM_StopWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformStopWorkItem(pRtWorkItem); ++#endif ++} ++ ++ ++VOID ++ODM_FreeWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformFreeWorkItem(pRtWorkItem); ++#endif ++} ++ ++ ++VOID ++ODM_ScheduleWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformScheduleWorkItem(pRtWorkItem); ++#endif ++} ++ ++ ++VOID ++ODM_IsWorkItemScheduled( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformIsWorkItemScheduled(pRtWorkItem); ++#endif ++} ++ ++ ++ ++// ++// ODM Timer relative API. ++// ++VOID ++ODM_StallExecution( ++ IN u4Byte usDelay ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ rtw_udelay_os(usDelay); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformStallExecution(usDelay); ++#endif ++} ++ ++VOID ++ODM_delay_ms(IN u4Byte ms) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ delay_ms(ms); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ rtw_mdelay_os(ms); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ delay_ms(ms); ++#endif ++} ++ ++VOID ++ODM_delay_us(IN u4Byte us) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ delay_us(us); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ rtw_udelay_os(us); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PlatformStallExecution(us); ++#endif ++} ++ ++VOID ++ODM_sleep_ms(IN u4Byte ms) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ rtw_msleep_os(ms); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#endif ++} ++ ++VOID ++ODM_sleep_us(IN u4Byte us) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ rtw_usleep_os(us); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#endif ++} ++ ++VOID ++ODM_SetTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer, ++ IN u4Byte msDelay ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ mod_timer(pTimer, jiffies + (msDelay+9)/10); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ _set_timer(pTimer,msDelay ); //ms ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformSetTimer(Adapter, pTimer, msDelay); ++#endif ++ ++} ++ ++VOID ++ODM_InitializeTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer, ++ IN RT_TIMER_CALL_BACK CallBackFunc, ++ IN PVOID pContext, ++ IN const char* szID ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ pTimer->function = CallBackFunc; ++ pTimer->data = (unsigned long)pDM_Odm; ++ init_timer(pTimer); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); ++#endif ++} ++ ++ ++VOID ++ODM_CancelTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ del_timer_sync(pTimer); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ _cancel_timer_ex(pTimer); ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PlatformCancelTimer(Adapter, pTimer); ++#endif ++} ++ ++ ++VOID ++ODM_ReleaseTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++ // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. ++ // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. ++ if (pTimer == 0) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); ++ return; ++ } ++ ++ PlatformReleaseTimer(Adapter, pTimer); ++#endif ++} ++ ++ ++// ++// ODM FW relative API. ++// ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++VOID ++ODM_FillH2CCmd( ++ IN PADAPTER Adapter, ++ IN u1Byte ElementID, ++ IN u4Byte CmdLen, ++ IN pu1Byte pCmdBuffer ++) ++{ ++ if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) ++ { ++ switch(ElementID) ++ { ++ case ODM_H2C_RSSI_REPORT: ++ FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer); ++ default: ++ break; ++ } ++ ++ } ++ else if(IS_HARDWARE_TYPE_8188E(Adapter)) ++ { ++ switch(ElementID) ++ { ++ case ODM_H2C_PSD_RESULT: ++ FillH2CCmd88E(Adapter, H2C_88E_PSD_RESULT, CmdLen, pCmdBuffer); ++ default: ++ break; ++ } ++ } ++ else ++ { ++ switch(ElementID) ++ { ++ case ODM_H2C_RSSI_REPORT: ++ FillH2CCmd92C(Adapter, H2C_RSSI_REPORT, CmdLen, pCmdBuffer); ++ case ODM_H2C_PSD_RESULT: ++ FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, CmdLen, pCmdBuffer); ++ default: ++ break; ++ } ++ } ++} ++#else ++u4Byte ++ODM_FillH2CCmd( ++ IN pu1Byte pH2CBuffer, ++ IN u4Byte H2CBufferLen, ++ IN u4Byte CmdNum, ++ IN pu4Byte pElementID, ++ IN pu4Byte pCmdLen, ++ IN pu1Byte* pCmbBuffer, ++ IN pu1Byte CmdStartSeq ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) ++ ++#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) ++ //FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq); ++ return FALSE; ++#endif ++ ++ return TRUE; ++} ++#endif ++ ++ ++ ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.h +new file mode 100644 +index 00000000..a5e86801 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_interface.h +@@ -0,0 +1,374 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __ODM_INTERFACE_H__ ++#define __ODM_INTERFACE_H__ ++ ++ ++ ++// ++// =========== Constant/Structure/Enum/... Define ++// ++ ++ ++ ++// ++// =========== Macro Define ++// ++ ++#define _reg_all(_name) ODM_##_name ++#define _reg_ic(_name, _ic) ODM_##_name##_ic ++#define _bit_all(_name) BIT_##_name ++#define _bit_ic(_name, _ic) BIT_##_name##_ic ++ ++// _cat: implemented by Token-Pasting Operator. ++#if 0 ++#define _cat(_name, _ic_type, _func) \ ++ ( \ ++ _func##_all(_name) \ ++ ) ++#endif ++ ++/*=================================== ++ ++#define ODM_REG_DIG_11N 0xC50 ++#define ODM_REG_DIG_11AC 0xDDD ++ ++ODM_REG(DIG,_pDM_Odm) ++=====================================*/ ++ ++#define _reg_11N(_name) ODM_REG_##_name##_11N ++#define _reg_11AC(_name) ODM_REG_##_name##_11AC ++#define _bit_11N(_name) ODM_BIT_##_name##_11N ++#define _bit_11AC(_name) ODM_BIT_##_name##_11AC ++ ++#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES. ++#define _cat(_name, _ic_type, _func) \ ++ ( \ ++ ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ ++ _func##_11AC(_name) \ ++ ) ++#endif ++#if 0 // only sample code ++#define _cat(_name, _ic_type, _func) \ ++ ( \ ++ ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \ ++ ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \ ++ ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \ ++ ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \ ++ ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ ++ _func##_ic(_name, _8195) \ ++ ) ++#endif ++ ++// _name: name of register or bit. ++// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" ++// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. ++#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) ++#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) ++ ++typedef enum _ODM_H2C_CMD ++{ ++ ODM_H2C_RSSI_REPORT = 0, ++ ODM_H2C_PSD_RESULT=1, ++ ODM_H2C_PathDiv = 2, ++ ODM_MAX_H2CCMD ++}ODM_H2C_CMD; ++ ++ ++// ++// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. ++// Suggest HW team to use thread instead of workitem. Windows also support the feature. ++// ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++typedef void *PRT_WORK_ITEM ; ++typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; ++typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); ++ ++#if 0 ++typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; ++ ++typedef struct _RT_WORK_ITEM ++{ ++ ++ RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. ++ PVOID Adapter; // Pointer to Adapter object. ++ PVOID pContext; // Parameter to passed to CallBackFunc(). ++ RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. ++ u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. ++ PVOID pPlatformExt; // Pointer to platform-dependent extension. ++ BOOLEAN bFree; ++ char szID[36]; // An identity string of this workitem. ++}RT_WORK_ITEM, *PRT_WORK_ITEM; ++ ++#endif ++ ++ ++#endif ++ ++// ++// =========== Extern Variable ??? It should be forbidden. ++// ++ ++ ++// ++// =========== EXtern Function Prototype ++// ++ ++ ++u1Byte ++ODM_Read1Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ); ++ ++u2Byte ++ODM_Read2Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ); ++ ++u4Byte ++ODM_Read4Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr ++ ); ++ ++VOID ++ODM_Write1Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u1Byte Data ++ ); ++ ++VOID ++ODM_Write2Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u2Byte Data ++ ); ++ ++VOID ++ODM_Write4Byte( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte Data ++ ); ++ ++VOID ++ODM_SetMACReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ); ++ ++u4Byte ++ODM_GetMACReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ); ++ ++VOID ++ODM_SetBBReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ); ++ ++u4Byte ++ODM_GetBBReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ); ++ ++VOID ++ODM_SetRFReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E eRFPath, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask, ++ IN u4Byte Data ++ ); ++ ++u4Byte ++ODM_GetRFReg( ++ IN PDM_ODM_T pDM_Odm, ++ IN ODM_RF_RADIO_PATH_E eRFPath, ++ IN u4Byte RegAddr, ++ IN u4Byte BitMask ++ ); ++ ++ ++// ++// Memory Relative Function. ++// ++VOID ++ODM_AllocateMemory( ++ IN PDM_ODM_T pDM_Odm, ++ OUT PVOID *pPtr, ++ IN u4Byte length ++ ); ++VOID ++ODM_FreeMemory( ++ IN PDM_ODM_T pDM_Odm, ++ OUT PVOID pPtr, ++ IN u4Byte length ++ ); ++ ++s4Byte ODM_CompareMemory( ++ IN PDM_ODM_T pDM_Odm, ++ IN PVOID pBuf1, ++ IN PVOID pBuf2, ++ IN u4Byte length ++ ); ++ ++// ++// ODM MISC-spin lock relative API. ++// ++VOID ++ODM_AcquireSpinLock( ++ IN PDM_ODM_T pDM_Odm, ++ IN RT_SPINLOCK_TYPE type ++ ); ++ ++VOID ++ODM_ReleaseSpinLock( ++ IN PDM_ODM_T pDM_Odm, ++ IN RT_SPINLOCK_TYPE type ++ ); ++ ++ ++// ++// ODM MISC-workitem relative API. ++// ++VOID ++ODM_InitializeWorkItem( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_WORK_ITEM pRtWorkItem, ++ IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, ++ IN PVOID pContext, ++ IN const char* szID ++ ); ++ ++VOID ++ODM_StartWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ); ++ ++VOID ++ODM_StopWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ); ++ ++VOID ++ODM_FreeWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ); ++ ++VOID ++ODM_ScheduleWorkItem( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ); ++ ++VOID ++ODM_IsWorkItemScheduled( ++ IN PRT_WORK_ITEM pRtWorkItem ++ ); ++ ++// ++// ODM Timer relative API. ++// ++VOID ++ODM_StallExecution( ++ IN u4Byte usDelay ++ ); ++ ++VOID ++ODM_delay_ms(IN u4Byte ms); ++ ++ ++VOID ++ODM_delay_us(IN u4Byte us); ++ ++VOID ++ODM_sleep_ms(IN u4Byte ms); ++ ++VOID ++ODM_sleep_us(IN u4Byte us); ++ ++VOID ++ODM_SetTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer, ++ IN u4Byte msDelay ++ ); ++ ++VOID ++ODM_InitializeTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer, ++ IN RT_TIMER_CALL_BACK CallBackFunc, ++ IN PVOID pContext, ++ IN const char* szID ++ ); ++ ++VOID ++ODM_CancelTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer ++ ); ++ ++VOID ++ODM_ReleaseTimer( ++ IN PDM_ODM_T pDM_Odm, ++ IN PRT_TIMER pTimer ++ ); ++ ++ ++// ++// ODM FW relative API. ++// ++#if (DM_ODM_SUPPORT_TYPE & ODM_MP) ++VOID ++ODM_FillH2CCmd( ++ IN PADAPTER Adapter, ++ IN u1Byte ElementID, ++ IN u4Byte CmdLen, ++ IN pu1Byte pCmdBuffer ++); ++#else ++u4Byte ++ODM_FillH2CCmd( ++ IN pu1Byte pH2CBuffer, ++ IN u4Byte H2CBufferLen, ++ IN u4Byte CmdNum, ++ IN pu4Byte pElementID, ++ IN pu4Byte pCmdLen, ++ IN pu1Byte* pCmbBuffer, ++ IN pu1Byte CmdStartSeq ++ ); ++#endif ++#endif // __ODM_INTERFACE_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_precomp.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_precomp.h +new file mode 100644 +index 00000000..f40a1277 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_precomp.h +@@ -0,0 +1,222 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __ODM_PRECOMP_H__ ++#define __ODM_PRECOMP_H__ ++ ++#include "odm_types.h" ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. ++ ++#else ++ ++#define TEST_FALG___ 1 ++ ++#endif ++ ++//2 Config Flags and Structs - defined by each ODM Type ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ #include "../8192cd_cfg.h" ++ #include "../odm_inc.h" ++ ++ #include "../8192cd.h" ++ #include "../8192cd_util.h" ++ #ifdef _BIG_ENDIAN_ ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG ++ #else ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE ++ #endif ++ ++ #ifdef AP_BUILD_WORKAROUND ++ #include "../8192cd_headers.h" ++ #include "../8192cd_debug.h" ++ #endif ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) ++ // Flags ++ #include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags. ++ #include "../odm_inc.h" // OUTSRC needs some extra flags. ++ // Data Structure ++ #include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0. ++ #include "../8192cd.h" // OUTSRC needs basic ADSL struct definition. ++ #include "../8192cd_util.h" // OUTSRC needs basic I/O function. ++ #ifdef _BIG_ENDIAN_ ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG ++ #else ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE ++ #endif ++ ++ #ifdef ADSL_AP_BUILD_WORKAROUND ++ // NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14. ++ #include "../8192cd_headers.h" ++ #include "../8192cd_debug.h" ++ #endif ++ ++#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) ++ #include ++ #include ++ #include ++ #include ++ #include ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ #include "Mp_Precomp.h" ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE ++#endif ++ ++ ++//2 Hardware Parameter Files ++ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++#if (RTL8192C_SUPPORT==1) ++ #include "rtl8192c/Hal8192CEFWImg_AP.h" ++ #include "rtl8192c/Hal8192CEPHYImg_AP.h" ++ #include "rtl8192c/Hal8192CEMACImg_AP.h" ++#endif ++#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) ++ #include "rtl8192c/Hal8192CEFWImg_ADSL.h" ++ #include "rtl8192c/Hal8192CEPHYImg_ADSL.h" ++ #include "rtl8192c/Hal8192CEMACImg_ADSL.h" ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ #if(RTL8192CE_SUPPORT ==1) ++ #include "rtl8192c/Hal8192CEFWImg_CE.h" ++ #include "rtl8192c/Hal8192CEPHYImg_CE.h" ++ #include "rtl8192c/Hal8192CEMACImg_CE.h" ++ #elif(RTL8192CU_SUPPORT ==1) ++ #include "rtl8192c/Hal8192CUFWImg_CE.h" ++ #include "rtl8192c/Hal8192CUPHYImg_CE.h" ++ #include "rtl8192c/Hal8192CUMACImg_CE.h" ++ #elif(RTL8192DE_SUPPORT ==1) ++ #include "rtl8192d/Hal8192DEFWImg_CE.h" ++ #include "rtl8192d/Hal8192DEPHYImg_CE.h" ++ #include "rtl8192d/Hal8192DEMACImg_CE.h" ++ #elif(RTL8192DU_SUPPORT ==1) ++ #include "rtl8192d/Hal8192DUFWImg_CE.h" ++ #include "rtl8192d/Hal8192DUPHYImg_CE.h" ++ #include "rtl8192d/Hal8192DUMACImg_CE.h" ++ #elif(RTL8723AS_SUPPORT==1) ++ #include "rtl8723a/Hal8723SHWImg_CE.h" ++ #elif(RTL8723AU_SUPPORT==1) ++ #include "rtl8723a/Hal8723UHWImg_CE.h" ++ #elif(RTL8188E_SUPPORT==1) ++ #include "rtl8188e/Hal8188EFWImg_CE.h" ++ #endif ++#elif (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ++#endif ++ ++ ++//2 OutSrc Header Files ++ ++#include "odm.h" ++#include "odm_HWConfig.h" ++#include "odm_debug.h" ++#include "odm_RegDefine11AC.h" ++#include "odm_RegDefine11N.h" ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++#if (RTL8192C_SUPPORT==1) ++ #include "rtl8192c/HalDMOutSrc8192C_AP.h" ++#endif ++#if (RTL8188E_SUPPORT==1) ++ #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training ++#endif ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) ++ #include "rtl8192c/HalDMOutSrc8192C_ADSL.h" ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ #include "HalPhyRf.h" ++ #if (RTL8192C_SUPPORT==1) ++ #ifdef CONFIG_INTEL_PROXIM ++ #include "../proxim/intel_proxim.h" ++ #endif ++ #include "rtl8192c/HalDMOutSrc8192C_CE.h" ++ #include ++ #elif (RTL8192D_SUPPORT==1) ++ #include "rtl8192d/HalDMOutSrc8192D_CE.h" ++ #include "rtl8192d_hal.h" ++ #elif (RTL8723A_SUPPORT==1) ++ #include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking ++ #include "rtl8723a_hal.h" ++ #elif (RTL8188E_SUPPORT==1) ++ #include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking ++ #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training ++ #include "rtl8188e_hal.h" ++ #endif ++ ++#endif ++ ++#include "odm_interface.h" ++#include "odm_reg.h" ++ ++#if (RTL8192C_SUPPORT==1) ++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) ++#include "rtl8192c/Hal8192CHWImg_MAC.h" ++#include "rtl8192c/Hal8192CHWImg_RF.h" ++#include "rtl8192c/Hal8192CHWImg_BB.h" ++#include "rtl8192c/Hal8192CHWImg_FW.h" ++#endif ++#include "rtl8192c/odm_RTL8192C.h" ++#endif ++#if (RTL8192D_SUPPORT==1) ++#include "rtl8192d/odm_RTL8192D.h" ++#endif ++ ++#if (RTL8723A_SUPPORT==1) ++#include "rtl8723a/HalHWImg8723A_MAC.h" ++#include "rtl8723a/HalHWImg8723A_RF.h" ++#include "rtl8723a/HalHWImg8723A_BB.h" ++#include "rtl8723a/HalHWImg8723A_FW.h" ++#include "rtl8723a/odm_RegConfig8723A.h" ++#endif ++ ++#if (RTL8188E_SUPPORT==1) ++#include "rtl8188e/HalHWImg8188E_MAC.h" ++#include "rtl8188e/HalHWImg8188E_RF.h" ++#include "rtl8188e/HalHWImg8188E_BB.h" ++#include "rtl8188e/Hal8188EReg.h" ++ ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++#include "rtl8188e/HalPhyRf_8188e.h" ++#endif ++ ++#if (RTL8188E_FOR_TEST_CHIP >= 1) ++#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h" ++#include "rtl8188e/HalHWImg8188E_TestChip_RF.h" ++#include "rtl8188e/HalHWImg8188E_TestChip_BB.h" ++#endif ++ ++#ifdef CONFIG_WOWLAN ++#if (RTL8188E_SUPPORT==1) ++#include "rtl8188e/HalHWImg8188E_FW.h" ++#endif ++#endif //CONFIG_WOWLAN ++ ++#include "rtl8188e/odm_RegConfig8188E.h" ++#include "rtl8188e/odm_RTL8188E.h" ++#endif ++ ++#endif // __ODM_PRECOMP_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_reg.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_reg.h +new file mode 100644 +index 00000000..361ac79c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_reg.h +@@ -0,0 +1,120 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++//============================================================ ++// File Name: odm_reg.h ++// ++// Description: ++// ++// This file is for general register definition. ++// ++// ++//============================================================ ++#ifndef __HAL_ODM_REG_H__ ++#define __HAL_ODM_REG_H__ ++ ++// ++// Register Definition ++// ++ ++//MAC REG ++#define ODM_BB_RESET 0x002 ++#define ODM_DUMMY 0x4fe ++#define ODM_EDCA_VO_PARAM 0x500 ++#define ODM_EDCA_VI_PARAM 0x504 ++#define ODM_EDCA_BE_PARAM 0x508 ++#define ODM_EDCA_BK_PARAM 0x50C ++#define ODM_TXPAUSE 0x522 ++ ++//BB REG ++#define ODM_FPGA_PHY0_PAGE8 0x800 ++#define ODM_PSD_SETTING 0x808 ++#define ODM_AFE_SETTING 0x818 ++#define ODM_TXAGC_B_6_18 0x830 ++#define ODM_TXAGC_B_24_54 0x834 ++#define ODM_TXAGC_B_MCS32_5 0x838 ++#define ODM_TXAGC_B_MCS0_MCS3 0x83c ++#define ODM_TXAGC_B_MCS4_MCS7 0x848 ++#define ODM_TXAGC_B_MCS8_MCS11 0x84c ++#define ODM_ANALOG_REGISTER 0x85c ++#define ODM_RF_INTERFACE_OUTPUT 0x860 ++#define ODM_TXAGC_B_MCS12_MCS15 0x868 ++#define ODM_TXAGC_B_11_A_2_11 0x86c ++#define ODM_AD_DA_LSB_MASK 0x874 ++#define ODM_ENABLE_3_WIRE 0x88c ++#define ODM_PSD_REPORT 0x8b4 ++#define ODM_R_ANT_SELECT 0x90c ++#define ODM_CCK_ANT_SELECT 0xa07 ++#define ODM_CCK_PD_THRESH 0xa0a ++#define ODM_CCK_RF_REG1 0xa11 ++#define ODM_CCK_MATCH_FILTER 0xa20 ++#define ODM_CCK_RAKE_MAC 0xa2e ++#define ODM_CCK_CNT_RESET 0xa2d ++#define ODM_CCK_TX_DIVERSITY 0xa2f ++#define ODM_CCK_FA_CNT_MSB 0xa5b ++#define ODM_CCK_FA_CNT_LSB 0xa5c ++#define ODM_CCK_NEW_FUNCTION 0xa75 ++#define ODM_OFDM_PHY0_PAGE_C 0xc00 ++#define ODM_OFDM_RX_ANT 0xc04 ++#define ODM_R_A_RXIQI 0xc14 ++#define ODM_R_A_AGC_CORE1 0xc50 ++#define ODM_R_A_AGC_CORE2 0xc54 ++#define ODM_R_B_AGC_CORE1 0xc58 ++#define ODM_R_AGC_PAR 0xc70 ++#define ODM_R_HTSTF_AGC_PAR 0xc7c ++#define ODM_TX_PWR_TRAINING_A 0xc90 ++#define ODM_TX_PWR_TRAINING_B 0xc98 ++#define ODM_OFDM_FA_CNT1 0xcf0 ++#define ODM_OFDM_PHY0_PAGE_D 0xd00 ++#define ODM_OFDM_FA_CNT2 0xda0 ++#define ODM_OFDM_FA_CNT3 0xda4 ++#define ODM_OFDM_FA_CNT4 0xda8 ++#define ODM_TXAGC_A_6_18 0xe00 ++#define ODM_TXAGC_A_24_54 0xe04 ++#define ODM_TXAGC_A_1_MCS32 0xe08 ++#define ODM_TXAGC_A_MCS0_MCS3 0xe10 ++#define ODM_TXAGC_A_MCS4_MCS7 0xe14 ++#define ODM_TXAGC_A_MCS8_MCS11 0xe18 ++#define ODM_TXAGC_A_MCS12_MCS15 0xe1c ++ ++//RF REG ++#define ODM_GAIN_SETTING 0x00 ++#define ODM_CHANNEL 0x18 ++ ++//Ant Detect Reg ++#define ODM_DPDT 0x300 ++ ++//PSD Init ++#define ODM_PSDREG 0x808 ++ ++//92D Path Div ++#define PATHDIV_REG 0xB30 ++#define PATHDIV_TRI 0xBA0 ++ ++ ++// ++// Bitmap Definition ++// ++ ++#define BIT_FA_RESET BIT0 ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_types.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_types.h +new file mode 100644 +index 00000000..b243d74d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/odm_types.h +@@ -0,0 +1,252 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __ODM_TYPES_H__ ++#define __ODM_TYPES_H__ ++ ++// ++// Define Different SW team support ++// ++#define ODM_AP 0x01 //BIT0 ++#define ODM_ADSL 0x02 //BIT1 ++#define ODM_CE 0x04 //BIT2 ++#define ODM_MP 0x08 //BIT3 ++ ++#define DM_ODM_SUPPORT_TYPE ODM_CE ++ ++// Deifne HW endian support ++#define ODM_ENDIAN_BIG 0 ++#define ODM_ENDIAN_LITTLE 1 ++ ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++#define RT_PCI_INTERFACE 1 ++#define RT_USB_INTERFACE 2 ++#define RT_SDIO_INTERFACE 3 ++#endif ++ ++typedef enum _HAL_STATUS{ ++ HAL_STATUS_SUCCESS, ++ HAL_STATUS_FAILURE, ++ /*RT_STATUS_PENDING, ++ RT_STATUS_RESOURCE, ++ RT_STATUS_INVALID_CONTEXT, ++ RT_STATUS_INVALID_PARAMETER, ++ RT_STATUS_NOT_SUPPORT, ++ RT_STATUS_OS_API_FAILED,*/ ++}HAL_STATUS,*PHAL_STATUS; ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++typedef enum _RT_SPINLOCK_TYPE{ ++ RT_TEMP =1, ++}RT_SPINLOCK_TYPE; ++#elif( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL)) ++ ++#define VISTA_USB_RX_REVISE 0 ++ ++// ++// Declare for ODM spin lock defintion temporarily fro compile pass. ++// ++typedef enum _RT_SPINLOCK_TYPE{ ++ RT_TX_SPINLOCK = 1, ++ RT_RX_SPINLOCK = 2, ++ RT_RM_SPINLOCK = 3, ++ RT_CAM_SPINLOCK = 4, ++ RT_SCAN_SPINLOCK = 5, ++ RT_LOG_SPINLOCK = 7, ++ RT_BW_SPINLOCK = 8, ++ RT_CHNLOP_SPINLOCK = 9, ++ RT_RF_OPERATE_SPINLOCK = 10, ++ RT_INITIAL_SPINLOCK = 11, ++ RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. ++#if VISTA_USB_RX_REVISE ++ RT_USBRX_CONTEXT_SPINLOCK = 13, ++ RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR ++#endif ++ //Shall we define Ndis 6.2 SpinLock Here ? ++ RT_PORT_SPINLOCK=16, ++ RT_VNIC_SPINLOCK=17, ++ RT_HVL_SPINLOCK=18, ++ RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. ++ ++ RT_BTData_SPINLOCK=25, ++ ++ RT_WAPI_OPTION_SPINLOCK=26, ++ RT_WAPI_RX_SPINLOCK=27, ++ ++ // add for 92D CCK control issue ++ RT_CCK_PAGEA_SPINLOCK = 28, ++ RT_BUFFER_SPINLOCK = 29, ++ RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, ++ RT_GEN_TEMP_BUF_SPINLOCK = 31, ++ RT_AWB_SPINLOCK = 32, ++ RT_FW_PS_SPINLOCK = 33, ++ RT_HW_TIMER_SPIN_LOCK = 34, ++ RT_MPT_WI_SPINLOCK = 35 ++}RT_SPINLOCK_TYPE; ++ ++#endif ++ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ #define STA_INFO_T RT_WLAN_STA ++ #define PSTA_INFO_T PRT_WLAN_STA ++ ++// typedef unsigned long u4Byte,*pu4Byte; ++ #define CONFIG_HW_ANTENNA_DIVERSITY ++#define CONFIG_SW_ANTENNA_DIVERSITY ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ ++ // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. ++ #define ADSL_AP_BUILD_WORKAROUND ++ #define AP_BUILD_WORKAROUND ++ // ++ ++ #ifdef AP_BUILD_WORKAROUND ++ #include "../typedef.h" ++ #else ++ typedef void VOID,*PVOID; ++ typedef unsigned char BOOLEAN,*PBOOLEAN; ++ typedef unsigned char u1Byte,*pu1Byte; ++ typedef unsigned short u2Byte,*pu2Byte; ++ typedef unsigned int u4Byte,*pu4Byte; ++ typedef unsigned long long u8Byte,*pu8Byte; ++ typedef char s1Byte,*ps1Byte; ++ typedef short s2Byte,*ps2Byte; ++ typedef long s4Byte,*ps4Byte; ++ typedef long long s8Byte,*ps8Byte; ++ #endif ++ ++ typedef struct rtl8192cd_priv *prtl8192cd_priv; ++ typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; ++ typedef struct timer_list RT_TIMER, *PRT_TIMER; ++ typedef void * RT_TIMER_CALL_BACK; ++ ++ #define DEV_BUS_TYPE RT_PCI_INTERFACE ++ ++ #define _TRUE 1 ++ #define _FALSE 0 ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) ++ ++ // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. ++ #define ADSL_AP_BUILD_WORKAROUND ++ #define ADSL_BUILD_WORKAROUND ++ // ++ ++ typedef unsigned char BOOLEAN,*PBOOLEAN; ++ typedef unsigned char u1Byte,*pu1Byte; ++ typedef unsigned short u2Byte,*pu2Byte; ++ typedef unsigned int u4Byte,*pu4Byte; ++ typedef unsigned long long u8Byte,*pu8Byte; ++ typedef char s1Byte,*ps1Byte; ++ typedef short s2Byte,*ps2Byte; ++ typedef long s4Byte,*ps4Byte; ++ typedef long long s8Byte,*ps8Byte; ++ ++ typedef struct rtl8192cd_priv *prtl8192cd_priv; ++ typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; ++ typedef struct timer_list RT_TIMER, *PRT_TIMER; ++ typedef void * RT_TIMER_CALL_BACK; ++ ++ #define DEV_BUS_TYPE RT_PCI_INTERFACE ++ ++ #define _TRUE 1 ++ #define _FALSE 0 ++ ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ #include ++ ++#if 0 ++ typedef u8 u1Byte, *pu1Byte; ++ typedef u16 u2Byte,*pu2Byte; ++ typedef u32 u4Byte,*pu4Byte; ++ typedef u64 u8Byte,*pu8Byte; ++ typedef s8 s1Byte,*ps1Byte; ++ typedef s16 s2Byte,*ps2Byte; ++ typedef s32 s4Byte,*ps4Byte; ++ typedef s64 s8Byte,*ps8Byte; ++#else ++ #define u1Byte u8 ++ #define pu1Byte u8* ++ ++ #define u2Byte u16 ++ #define pu2Byte u16* ++ ++ #define u4Byte u32 ++ #define pu4Byte u32* ++ ++ #define u8Byte u64 ++ #define pu8Byte u64* ++ ++ #define s1Byte s8 ++ #define ps1Byte s8* ++ ++ #define s2Byte s16 ++ #define ps2Byte s16* ++ ++ #define s4Byte s32 ++ #define ps4Byte s32* ++ ++ #define s8Byte s64 ++ #define ps8Byte s64* ++ ++#endif ++ #ifdef CONFIG_USB_HCI ++ #define DEV_BUS_TYPE RT_USB_INTERFACE ++ #elif defined(CONFIG_PCI_HCI) ++ #define DEV_BUS_TYPE RT_PCI_INTERFACE ++ #elif defined(CONFIG_SDIO_HCI) ++ #define DEV_BUS_TYPE RT_SDIO_INTERFACE ++ #elif defined(CONFIG_GSPI_HCI) ++ #define DEV_BUS_TYPE RT_SDIO_INTERFACE ++ #endif ++ ++ ++ #if defined(CONFIG_LITTLE_ENDIAN) ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE ++ #elif defined (CONFIG_BIG_ENDIAN) ++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG ++ #endif ++ ++ typedef struct timer_list RT_TIMER, *PRT_TIMER; ++ typedef void * RT_TIMER_CALL_BACK; ++ #define STA_INFO_T struct sta_info ++ #define PSTA_INFO_T struct sta_info * ++ ++ ++ ++ #define TRUE _TRUE ++ #define FALSE _FALSE ++ ++ ++ #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) ++ #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) ++ #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) ++ ++ //define useless flag to avoid compile warning ++ #define USE_WORKITEM 0 ++ #define FOR_BRAZIL_PRETEST 0 ++ #define BT_30_SUPPORT 0 ++ #define FPGA_TWO_MAC_VERIFICATION 0 ++#endif ++ ++ ++#endif // __ODM_TYPES_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c +new file mode 100644 +index 00000000..815a357b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c +@@ -0,0 +1,892 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++#include "../odm_precomp.h" ++ ++const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength] = { ++0xE1, 0x88, 0x10, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x30, 0x36, 0x00, 0x00, ++0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x02, 0x45, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0xC1, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0xA1, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x56, 0xF7, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x42, 0x04, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, ++0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, ++0xEC, 0x24, 0x89, 0xF8, 0xE6, 0xBC, 0x03, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, ++0x40, 0xCE, 0x79, 0x04, 0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, ++0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, ++0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, 0x04, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, ++0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x88, 0x25, 0x0C, 0xF8, ++0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, ++0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, ++0x0C, 0x24, 0x89, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, ++0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x88, ++0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, ++0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, ++0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x88, 0xA6, ++0x81, 0x74, 0x03, 0x60, 0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x04, 0xE4, 0x78, 0x80, ++0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x45, 0xDE, 0x74, 0x01, 0x93, ++0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, ++0x8C, 0xD2, 0xAF, 0x22, 0x03, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, ++0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, ++0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, 0x88, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, ++0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, ++0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, ++0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x88, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, ++0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, ++0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x88, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, ++0x04, 0x90, 0x45, 0xDE, 0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, ++0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, ++0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x88, 0x2F, ++0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x42, 0x4D, 0x50, 0x2E, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xBF, 0x03, ++0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74, 0x88, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C, ++0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19, 0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5, ++0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01, ++0x0F, 0x74, 0x88, 0x2F, 0xF8, 0xA6, 0x01, 0x08, 0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC, ++0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8, 0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5, ++0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, ++0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6, 0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4, ++0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30, 0xE2, 0x01, 0x0F, 0x02, 0x42, 0x4C, 0x8F, 0xF0, ++0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80, 0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08, ++0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50, 0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6, ++0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30, ++0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC, ++0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x42, 0x4D, 0x7F, 0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF, ++0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF, 0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, ++0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xEF, ++0x5B, 0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, ++0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, ++0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xE2, 0xFC, 0x08, 0xE2, 0xFD, 0x08, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, ++0x22, 0xE2, 0xFB, 0x08, 0xE2, 0xF9, 0x08, 0xE2, 0xFA, 0x08, 0xE2, 0xCB, 0xF8, 0x22, 0xEC, 0xF2, ++0x08, 0xED, 0xF2, 0x08, 0xEE, 0xF2, 0x08, 0xEF, 0xF2, 0x22, 0xA4, 0x25, 0x82, 0xF5, 0x82, 0xE5, ++0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, ++0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, ++0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, ++0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0x02, 0x45, ++0x8C, 0x02, 0x42, 0xDD, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01, ++0xF2, 0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, ++0x33, 0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, ++0xDF, 0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90, 0x45, 0xD1, 0xE4, ++0x7E, 0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, ++0x93, 0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93, ++0xA3, 0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, ++0xCA, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, ++0xBE, 0x00, 0x41, 0x82, 0x09, 0x00, 0x41, 0x82, 0x0A, 0x00, 0x41, 0x82, 0x17, 0x00, 0x59, 0xE2, ++0x5C, 0x24, 0x5E, 0x5D, 0x5F, 0xA1, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, ++0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, ++0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xE6, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD1, 0x35, 0x74, ++0xE6, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, ++0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, ++0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x00, 0x54, 0xE0, 0x55, 0x35, 0xF5, 0x39, 0xA3, 0xE0, 0x55, ++0x36, 0xF5, 0x3A, 0xA3, 0xE0, 0x55, 0x37, 0xF5, 0x3B, 0xA3, 0xE0, 0x55, 0x38, 0xF5, 0x3C, 0xAD, ++0x39, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0xAD, 0x3A, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0xAD, 0x3B, 0x7F, ++0x56, 0x12, 0x32, 0x1E, 0xAD, 0x3C, 0x7F, 0x57, 0x12, 0x32, 0x1E, 0x53, 0x91, 0xEF, 0x22, 0xC0, ++0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, ++0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, ++0x6F, 0xF0, 0x74, 0x46, 0xA3, 0xF0, 0x12, 0x6C, 0x78, 0xE5, 0x41, 0x30, 0xE4, 0x04, 0x7F, 0x02, ++0x91, 0x27, 0xE5, 0x41, 0x30, 0xE6, 0x03, 0x12, 0x6C, 0xD5, 0xE5, 0x43, 0x30, 0xE0, 0x03, 0x12, ++0x51, 0xC2, 0xE5, 0x43, 0x30, 0xE1, 0x03, 0x12, 0x4D, 0x0C, 0xE5, 0x43, 0x30, 0xE2, 0x03, 0x12, ++0x4C, 0xC1, 0xE5, 0x43, 0x30, 0xE3, 0x03, 0x12, 0x6C, 0xE2, 0xE5, 0x43, 0x30, 0xE4, 0x03, 0x12, ++0x6D, 0x04, 0xE5, 0x43, 0x30, 0xE5, 0x03, 0x12, 0x6D, 0x33, 0xE5, 0x43, 0x30, 0xE6, 0x02, 0xF1, ++0x0F, 0xE5, 0x44, 0x30, 0xE1, 0x03, 0x12, 0x51, 0x7F, 0x74, 0x6F, 0x04, 0x90, 0x01, 0xC4, 0xF0, ++0x74, 0x46, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, ++0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, ++0x80, 0xDE, 0xE0, 0xB4, 0x01, 0x13, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x0D, 0x90, 0x81, 0x2B, 0xE0, ++0x54, 0xFE, 0xF0, 0x54, 0x07, 0x70, 0x02, 0xF1, 0x2A, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x90, 0x81, ++0x29, 0x30, 0xE0, 0x05, 0xE0, 0xFF, 0x02, 0x74, 0x8F, 0xE0, 0xFF, 0x7D, 0x01, 0xD3, 0x10, 0xAF, ++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, 0x13, 0xED, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x90, 0x82, 0x14, ++0xF0, 0x90, 0x81, 0x24, 0xE0, 0xFE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x03, 0x02, 0x48, ++0xA0, 0xEE, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x03, 0x02, 0x48, 0xA0, 0x90, 0x82, ++0x14, 0xE0, 0xFE, 0x6F, 0x70, 0x03, 0x02, 0x48, 0xA0, 0xEF, 0x70, 0x03, 0x02, 0x48, 0x17, 0x24, ++0xFE, 0x70, 0x03, 0x02, 0x48, 0x50, 0x24, 0xFE, 0x60, 0x51, 0x24, 0xFC, 0x70, 0x03, 0x02, 0x48, ++0x8B, 0x24, 0xFC, 0x60, 0x03, 0x02, 0x48, 0xA0, 0xEE, 0xB4, 0x0E, 0x03, 0x12, 0x49, 0x5E, 0x90, ++0x82, 0x14, 0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x49, 0x93, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, ++0x03, 0x12, 0x49, 0x34, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x04, 0x0F, 0x90, 0x82, 0x13, 0xE0, 0xFF, ++0x60, 0x05, 0x12, 0x73, 0x75, 0x80, 0x03, 0x12, 0x66, 0x26, 0x90, 0x82, 0x14, 0xE0, 0x64, 0x08, ++0x60, 0x03, 0x02, 0x48, 0xA0, 0x12, 0x73, 0xD3, 0x02, 0x48, 0xA0, 0x90, 0x82, 0x14, 0xE0, 0x70, ++0x05, 0x7F, 0x01, 0x12, 0x49, 0x93, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x49, 0x34, ++0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x09, 0x12, 0x48, 0xA5, 0xBF, 0x01, 0x03, 0x12, 0x49, 0x5E, ++0x90, 0x82, 0x14, 0xE0, 0x64, 0x0C, 0x60, 0x02, 0x01, 0xA0, 0x11, 0xA5, 0xEF, 0x64, 0x01, 0x60, ++0x02, 0x01, 0xA0, 0x11, 0xFA, 0x01, 0xA0, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x07, 0x11, 0xA5, ++0xBF, 0x01, 0x02, 0x31, 0x5E, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, 0x02, 0x31, 0x34, 0x90, 0x82, ++0x14, 0xE0, 0xB4, 0x0C, 0x07, 0x11, 0xA5, 0xBF, 0x01, 0x02, 0x11, 0xFA, 0x90, 0x82, 0x14, 0xE0, ++0x64, 0x04, 0x70, 0x5C, 0x12, 0x72, 0xF5, 0xEF, 0x64, 0x01, 0x70, 0x54, 0x31, 0xBE, 0x80, 0x50, ++0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x07, 0x11, 0xA5, 0xBF, 0x01, 0x02, 0x31, 0x5E, 0x90, 0x82, ++0x14, 0xE0, 0xB4, 0x06, 0x02, 0x31, 0x34, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0C, 0x07, 0x11, 0xA5, ++0xBF, 0x01, 0x02, 0x11, 0xFA, 0x90, 0x82, 0x14, 0xE0, 0x70, 0x04, 0x7F, 0x01, 0x31, 0x93, 0x90, ++0x82, 0x14, 0xE0, 0xB4, 0x04, 0x1A, 0x12, 0x73, 0xBB, 0x80, 0x15, 0x90, 0x82, 0x14, 0xE0, 0xB4, ++0x0C, 0x0E, 0x90, 0x81, 0x25, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x02, 0x31, 0xB1, ++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD1, 0xAB, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, ++0x01, 0xF0, 0x80, 0x3D, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, ++0x08, 0x90, 0x01, 0xB8, 0x74, 0x02, 0xF0, 0x80, 0x28, 0xEF, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x08, ++0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x19, 0x90, 0x81, 0x29, 0xE0, 0xD3, 0x94, 0x04, 0x40, ++0x08, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, ++0x22, 0x90, 0x01, 0xB9, 0x74, 0x02, 0xF0, 0x7F, 0x00, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, ++0x70, 0x31, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x7F, ++0x01, 0xF1, 0x0D, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x2A, ++0x74, 0x0E, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, ++0xB8, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x25, 0xE0, 0x90, 0x06, 0x04, 0x20, 0xE0, 0x0C, 0xE0, 0x44, ++0x40, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, 0x80, 0x0E, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x81, ++0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, 0x81, ++0x25, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x08, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x80, 0x1E, 0x90, ++0x06, 0x04, 0xE0, 0x44, 0x40, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, ++0x90, 0x05, 0x27, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x23, 0x74, 0x04, 0xF0, 0x90, 0x05, 0x22, ++0xE4, 0xF0, 0x22, 0x90, 0x82, 0x15, 0xEF, 0xF0, 0x12, 0x54, 0x65, 0x90, 0x82, 0x15, 0xE0, 0x60, ++0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, 0x90, 0x81, 0x23, 0xF0, ++0x22, 0x31, 0xE3, 0x90, 0x81, 0x2A, 0x74, 0x08, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x05, ++0x22, 0x74, 0xFF, 0xF0, 0xF1, 0x3A, 0x90, 0x01, 0x37, 0x74, 0x02, 0xF0, 0xFD, 0x7F, 0x03, 0x51, ++0x57, 0x31, 0xE3, 0xE4, 0x90, 0x81, 0x2A, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x05, 0x22, ++0x74, 0xFF, 0xF0, 0xF1, 0x3A, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, 0xF0, 0x00, 0xC0, 0x7F, ++0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x14, ++0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, ++0x00, 0xE4, 0xFD, 0xFF, 0x12, 0x55, 0x1C, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x44, ++0x80, 0xFC, 0x90, 0x82, 0x05, 0x12, 0x20, 0xCE, 0x90, 0x82, 0x05, 0x12, 0x44, 0xD9, 0x90, 0x85, ++0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x01, 0x00, 0x74, 0x3F, ++0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0x22, 0x90, 0x01, ++0x34, 0x74, 0x40, 0xF0, 0xFD, 0xE4, 0xFF, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0x4D, 0xFE, 0xF6, 0x74, ++0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, ++0xC3, 0xC0, 0xD0, 0xE4, 0x90, 0x81, 0xCB, 0xF0, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, ++0x81, 0x1F, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, ++0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x81, ++0x1F, 0xF0, 0xEE, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, ++0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x90, 0x81, 0x1F, 0xF0, 0xEE, 0x54, 0x20, 0xFE, ++0xEF, 0x54, 0xDF, 0x4E, 0xF0, 0x12, 0x1F, 0xA4, 0xC3, 0x13, 0x20, 0xE0, 0x02, 0x61, 0x5E, 0x90, ++0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x6D, 0x90, 0x81, 0xCB, 0x74, 0x21, 0xF0, 0xEF, 0x13, 0x13, ++0x54, 0x3F, 0x30, 0xE0, 0x0B, 0x51, 0x4E, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x08, 0xF0, 0x80, 0x0C, ++0xE4, 0x90, 0x81, 0x20, 0xF0, 0xA3, 0xF0, 0x7D, 0x40, 0xFF, 0x91, 0x26, 0x90, 0x81, 0x1F, 0xE0, ++0xFD, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x12, 0xF0, ++0xED, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x14, 0xF0, 0x90, 0x81, ++0x1F, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x80, 0xF0, ++0x90, 0x81, 0xCB, 0xE0, 0x90, 0x05, 0x27, 0xF0, 0x90, 0x81, 0x22, 0xE0, 0x60, 0x02, 0x81, 0x17, ++0x7F, 0x01, 0x80, 0x15, 0x90, 0x81, 0xCB, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x27, 0xF0, 0x90, 0x81, ++0x22, 0xE0, 0x64, 0x04, 0x60, 0x02, 0x81, 0x17, 0xFF, 0x12, 0x53, 0x0E, 0x81, 0x17, 0x90, 0x81, ++0x1F, 0xE0, 0xFF, 0x20, 0xE0, 0x02, 0x61, 0xE7, 0x90, 0x81, 0xCB, 0x74, 0x31, 0xF0, 0xEF, 0x13, ++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0B, 0x51, 0x4E, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x08, 0xF0, 0x80, ++0x06, 0x7D, 0x40, 0xE4, 0xFF, 0x91, 0x26, 0x90, 0x81, 0x1F, 0xE0, 0xFD, 0x13, 0x13, 0x13, 0x54, ++0x1F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x02, 0xF0, 0xED, 0xC4, 0x54, 0x0F, 0x30, ++0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x81, 0xCB, 0xE0, 0x90, 0x05, 0x27, ++0xF0, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x70, 0x1D, 0xFD, 0x7F, 0x04, 0x12, 0x47, 0x3D, 0x12, ++0x51, 0x73, 0xBF, 0x01, 0x09, 0x90, 0x81, 0x29, 0xE0, 0xFF, 0x7D, 0x01, 0x80, 0x03, 0xE4, 0xFD, ++0xFF, 0x12, 0x47, 0x3D, 0x80, 0x41, 0x90, 0x81, 0x2A, 0xE0, 0x90, 0x81, 0x23, 0xF0, 0x90, 0x05, ++0x27, 0xE0, 0x44, 0x40, 0xF0, 0x80, 0x30, 0x90, 0x81, 0xCB, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x27, ++0xF0, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x06, 0x7D, 0x01, 0x7F, 0x04, 0x80, 0x0B, 0x90, 0x81, ++0x23, 0xE0, 0xB4, 0x08, 0x07, 0x7D, 0x01, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0xD1, 0x34, 0x90, 0x81, ++0x29, 0x12, 0x47, 0x39, 0x12, 0x5A, 0xA7, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x7D, 0x02, 0x7F, 0x02, ++0x91, 0x26, 0x7D, 0x01, 0x7F, 0x02, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, ++0xF6, 0x74, 0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xEF, 0x70, ++0x37, 0x7D, 0x78, 0x7F, 0x02, 0x91, 0x26, 0x7D, 0x02, 0x7F, 0x03, 0x91, 0x26, 0x7D, 0xC8, 0x7F, ++0x02, 0x12, 0x71, 0x8F, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x7D, ++0x01, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, ++0x90, 0x06, 0x0A, 0xE0, 0x54, 0xF8, 0xF0, 0x22, 0x90, 0x01, 0x36, 0x74, 0x78, 0xF0, 0xA3, 0x74, ++0x02, 0xF0, 0x7D, 0x78, 0xFF, 0x51, 0x57, 0x7D, 0x02, 0x7F, 0x03, 0x51, 0x57, 0x90, 0x06, 0x0A, ++0xE0, 0x44, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x80, 0xDE, ++0xE0, 0xB4, 0x01, 0x15, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, ++0xE2, 0x0E, 0x7D, 0x01, 0x7F, 0x04, 0x02, 0x47, 0x3D, 0x90, 0x81, 0x25, 0xE0, 0x44, 0x04, 0xF0, ++0x22, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x08, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x60, ++0x3A, 0x90, 0x81, 0x27, 0xE0, 0x70, 0x04, 0xEF, 0x30, 0xE0, 0x0A, 0x90, 0x81, 0x2A, 0xE0, 0x64, ++0x02, 0x60, 0x28, 0xB1, 0x83, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, ++0x14, 0x90, 0x81, 0x2D, 0xE0, 0xFF, 0xA3, 0xE0, 0x6F, 0x70, 0x0A, 0xF1, 0xCD, 0x91, 0x1C, 0x90, ++0x81, 0x2E, 0xE0, 0x14, 0xF0, 0x90, 0x01, 0xE6, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x1F, 0xE0, ++0x30, 0xE0, 0x06, 0x90, 0x81, 0x21, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x45, 0x90, ++0x81, 0x25, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x12, 0x90, 0x01, 0x3B, 0xE0, ++0x30, 0xE4, 0x0B, 0x91, 0x1C, 0x90, 0x81, 0x2D, 0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, 0x90, 0x82, ++0x0B, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0xC3, 0x90, 0x82, 0x0C, 0xE0, 0x94, 0x80, 0x90, ++0x82, 0x0B, 0xE0, 0x64, 0x80, 0x94, 0x80, 0x40, 0x0B, 0x90, 0x01, 0x98, 0xE0, 0x54, 0xFE, 0xF0, ++0xE0, 0x44, 0x01, 0xF0, 0x12, 0x75, 0xF8, 0xD1, 0xD6, 0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x0C, ++0xE4, 0xF5, 0x1D, 0xA3, 0xF1, 0xFB, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x01, 0xBE, 0xE0, ++0x04, 0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x60, 0x02, 0xC1, 0x23, 0x90, 0x81, 0x27, ++0xE0, 0x70, 0x02, 0xC1, 0x23, 0x90, 0x81, 0x26, 0xE0, 0xC4, 0x54, 0x0F, 0x64, 0x01, 0x70, 0x22, ++0x90, 0x06, 0xAB, 0xE0, 0x90, 0x81, 0x2E, 0xF0, 0x90, 0x06, 0xAA, 0xE0, 0x90, 0x81, 0x2D, 0xF0, ++0xA3, 0xE0, 0xFF, 0x70, 0x08, 0x90, 0x81, 0x2D, 0xE0, 0xFE, 0xFF, 0x80, 0x00, 0x90, 0x81, 0x2E, ++0xEF, 0xF0, 0x90, 0x81, 0x25, 0xE0, 0x44, 0x04, 0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, 0x81, ++0x32, 0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, ++0x02, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x26, 0xE0, ++0xFF, 0xC4, 0x54, 0x0F, 0x24, 0xFD, 0x50, 0x02, 0x80, 0x0F, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, ++0x05, 0x12, 0x6D, 0xF2, 0x80, 0x03, 0x12, 0x6E, 0xC9, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x13, ++0x54, 0x1F, 0x30, 0xE0, 0x0E, 0x90, 0x81, 0x2D, 0xE0, 0xFF, 0xA3, 0xE0, 0xB5, 0x07, 0x04, 0xF1, ++0xCD, 0x91, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x07, 0x90, 0x81, 0x25, 0xE0, ++0x44, 0x04, 0xF0, 0x22, 0xD1, 0xAB, 0xEF, 0x70, 0x02, 0xD1, 0x3C, 0x22, 0x90, 0x81, 0x27, 0xE0, ++0x64, 0x01, 0x70, 0x66, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x60, 0x51, 0x90, 0x81, 0x2A, 0xE0, ++0x70, 0x03, 0xFF, 0x31, 0x93, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, 0x60, 0x03, 0x12, 0x66, 0x26, ++0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0xD1, 0xAB, 0xEF, 0x64, 0x01, ++0x60, 0x38, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, ++0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x12, 0x50, 0x05, 0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x90, ++0x06, 0x92, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0x90, 0x81, 0x2A, ++0xE0, 0x70, 0x07, 0x7D, 0x01, 0x7F, 0x04, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x04, 0x1A, 0xE0, 0xF4, ++0x60, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x04, 0x1B, 0xE0, 0x54, 0x07, 0x64, 0x07, 0x7F, 0x01, 0x60, ++0x02, 0x7F, 0x00, 0x22, 0x12, 0x50, 0x60, 0x90, 0x81, 0x2D, 0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, ++0x7D, 0x02, 0x7F, 0x02, 0x51, 0x57, 0x90, 0x81, 0x42, 0xE0, 0x30, 0xE0, 0x2D, 0x90, 0x80, 0xDE, ++0xE0, 0xB4, 0x01, 0x26, 0x90, 0x82, 0x17, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x0A, 0x0B, 0x90, 0x81, ++0x44, 0xE0, 0x04, 0xF0, 0xE4, 0x90, 0x82, 0x17, 0xF0, 0x90, 0x81, 0x44, 0xE0, 0xFF, 0x90, 0x81, ++0x43, 0xE0, 0xB5, 0x07, 0x05, 0xE4, 0xA3, 0xF0, 0xF1, 0x0B, 0x22, 0xE4, 0xFF, 0x8F, 0x53, 0x90, ++0x04, 0x1D, 0xE0, 0x60, 0x19, 0x90, 0x05, 0x22, 0xE0, 0xF5, 0x56, 0x74, 0xFF, 0xF0, 0xF1, 0x3A, ++0xBF, 0x01, 0x03, 0x12, 0x74, 0xFB, 0x90, 0x05, 0x22, 0xE5, 0x56, 0xF0, 0x80, 0x03, 0x12, 0x74, ++0xFB, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x7F, 0x01, 0x22, 0xE4, 0x90, 0x82, 0x0F, 0xF0, 0xA3, ++0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0, 0x70, 0x07, 0xA3, ++0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x82, 0x10, 0xE0, 0x94, 0xE8, 0x90, 0x82, 0x0F, ++0xE0, 0x94, 0x03, 0x40, 0x0A, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20, 0xF0, 0x7F, 0x00, 0x22, 0x7F, ++0x32, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x0F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, ++0x80, 0xBF, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0x3F, 0xF0, ++0xEF, 0x60, 0x1D, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x10, ++0xF0, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0x22, ++0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xEF, 0xF0, 0x74, 0x1F, ++0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x40, 0xF0, 0x22, 0xEF, 0x14, 0x90, ++0x05, 0x73, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0, 0xFD, 0x7F, 0x03, 0x74, 0x45, 0x2F, 0xF8, ++0xE6, 0x4D, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, ++0x22, 0xE0, 0x44, 0x02, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x39, 0xE0, 0xF5, 0x1E, 0xE4, 0xFB, ++0xFD, 0x7F, 0x54, 0x7E, 0x01, 0x8E, 0x19, 0x8F, 0x1A, 0xE5, 0x1E, 0x54, 0x07, 0xC4, 0x33, 0x54, ++0xE0, 0x85, 0x19, 0x83, 0x85, 0x1A, 0x82, 0xF0, 0xE5, 0x1D, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, ++0xFF, 0xE5, 0x1E, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0xA3, 0xF0, 0xEB, 0x54, 0x07, 0xC4, 0x33, ++0x54, 0xE0, 0xFF, 0xE5, 0x1D, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0x85, 0x1A, 0x82, 0x85, 0x19, ++0x83, 0xA3, 0xA3, 0xF0, 0xBD, 0x01, 0x0C, 0x85, 0x1A, 0x82, 0x8E, 0x83, 0xA3, 0xA3, 0xA3, 0x74, ++0x03, 0xF0, 0x22, 0x85, 0x1A, 0x82, 0x85, 0x19, 0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x01, 0xF0, 0x22, ++0xE4, 0x90, 0x81, 0x4D, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x58, 0x90, 0x80, 0xDE, 0xE0, 0x64, ++0x01, 0x70, 0x50, 0x90, 0x81, 0x4D, 0x04, 0xF0, 0xE4, 0x90, 0x81, 0x2E, 0xF0, 0x90, 0x81, 0x1F, ++0xE0, 0x30, 0xE0, 0x15, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x05, 0xE4, 0x90, 0x81, 0x4D, 0xF0, ++0x31, 0x73, 0xEF, 0x70, 0x04, 0x90, 0x81, 0x4D, 0xF0, 0x90, 0x81, 0x4D, 0xE0, 0x60, 0x24, 0x90, ++0x81, 0x2B, 0xE0, 0x44, 0x10, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x2F, 0x12, 0x4F, 0xFB, 0x90, ++0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, 0xE2, 0x07, 0x7D, 0x01, 0x7F, 0x04, ++0x12, 0x47, 0x3D, 0x22, 0xE4, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x70, 0x02, 0x21, ++0x72, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x60, 0x02, 0x21, 0x72, 0x90, 0x81, 0x26, 0xE0, 0xFF, ++0xC4, 0x54, 0x0F, 0x60, 0x22, 0x24, 0xFE, 0x60, 0x03, 0x04, 0x70, 0x21, 0x90, 0x81, 0x2E, 0xE0, ++0x14, 0xF0, 0xE0, 0xFF, 0x60, 0x06, 0x90, 0x81, 0x30, 0xE0, 0x60, 0x11, 0xEF, 0x70, 0x08, 0x90, ++0x81, 0x2D, 0xE0, 0xA3, 0xF0, 0x80, 0x00, 0x90, 0x81, 0x4C, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x1F, ++0xE0, 0x30, 0xE0, 0x15, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x05, 0xE4, 0x90, 0x81, 0x4C, 0xF0, ++0x31, 0x73, 0xEF, 0x70, 0x04, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x81, 0x4C, 0xE0, 0x60, 0x43, 0x90, ++0x81, 0x2B, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x81, 0x30, 0xE0, 0x60, 0x03, 0xB4, 0x01, 0x09, 0xE4, ++0xF5, 0x1D, 0x90, 0x81, 0x30, 0xE0, 0x80, 0x0D, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x30, 0xE0, 0x75, ++0xF0, 0x03, 0xA4, 0x24, 0xFE, 0xFF, 0x90, 0x81, 0x2F, 0xE0, 0x2F, 0x12, 0x4F, 0xFC, 0x90, 0x01, ++0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, 0xE2, 0x07, 0x7D, 0x01, 0x7F, 0x04, 0x12, ++0x47, 0x3D, 0x22, 0x90, 0x05, 0x43, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22, 0x90, ++0x81, 0x27, 0xE0, 0x70, 0x07, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x11, 0x90, 0x81, 0x1F, 0xE0, ++0x30, 0xE0, 0x07, 0x31, 0x73, 0xBF, 0x01, 0x05, 0x41, 0x5B, 0x12, 0x4E, 0x3C, 0x22, 0xD3, 0x10, ++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x1E, 0xE0, 0xB4, 0x01, 0x04, 0x7F, 0x04, 0x80, 0x0B, ++0x31, 0x73, 0xBF, 0x01, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x02, 0x71, 0x0E, 0xD0, 0xD0, 0x92, ++0xAF, 0x22, 0x90, 0x81, 0x4B, 0xE0, 0x60, 0x0F, 0xE4, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x02, ++0xF0, 0x90, 0x05, 0xFC, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x10, 0xA3, 0x74, ++0x01, 0xF0, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x02, 0x31, 0x9E, 0x11, 0xC4, ++0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x07, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, ++0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x3D, 0x90, 0x81, 0x23, 0xE0, 0x7E, 0x00, 0xB4, 0x02, 0x02, ++0x7E, 0x01, 0x90, 0x81, 0x22, 0xE0, 0x7D, 0x00, 0xB4, 0x04, 0x02, 0x7D, 0x01, 0xED, 0x4E, 0x70, ++0x23, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x02, 0x21, 0x9E, 0x51, 0x45, 0x90, 0x81, 0x23, 0xE0, 0xB4, ++0x08, 0x06, 0xE4, 0xFD, 0x7F, 0x0C, 0x80, 0x09, 0x90, 0x81, 0x23, 0xE0, 0x70, 0x06, 0xFD, 0x7F, ++0x04, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x81, 0x1E, 0xE0, 0xB4, 0x01, 0x0F, 0x90, 0x81, 0x23, 0xE0, ++0x64, 0x02, 0x60, 0x07, 0x7D, 0x01, 0x7F, 0x02, 0x12, 0x47, 0x3D, 0x90, 0x81, 0x27, 0xE0, 0x64, ++0x02, 0x60, 0x14, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x60, 0x0C, 0x12, 0x4E, 0xAB, 0xEF, 0x70, ++0x06, 0xFD, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x3F, ++0x90, 0x81, 0x23, 0xE0, 0x7E, 0x00, 0xB4, 0x02, 0x02, 0x7E, 0x01, 0x90, 0x81, 0x22, 0xE0, 0x7D, ++0x00, 0xB4, 0x04, 0x02, 0x7D, 0x01, 0xED, 0x4E, 0x70, 0x25, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x02, ++0x21, 0x9E, 0x12, 0x74, 0xAC, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x0C, 0x06, 0xE4, 0xFD, 0x7F, 0x08, ++0x80, 0x0A, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x04, 0x06, 0xE4, 0xFD, 0xFF, 0x12, 0x47, 0x3D, 0x22, ++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x12, 0x1F, 0xA4, ++0xFF, 0x90, 0x81, 0x1E, 0xF0, 0xBF, 0x01, 0x12, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x90, 0x00, ++0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x21, 0x80, 0x1D, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, ++0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x0F, 0x90, 0x81, 0x1F, 0xE0, 0x20, 0xE0, ++0x06, 0xE4, 0xFF, 0x71, 0x0E, 0x80, 0x02, 0x31, 0x9E, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, ++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x22, 0xE0, 0x90, 0x82, 0x16, 0xF0, 0x6F, 0x70, 0x02, ++0x81, 0x04, 0xEF, 0x14, 0x60, 0x3E, 0x14, 0x60, 0x62, 0x14, 0x70, 0x02, 0x61, 0xB8, 0x14, 0x70, ++0x02, 0x61, 0xDF, 0x24, 0x04, 0x60, 0x02, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, ++0x04, 0x91, 0x41, 0x81, 0x04, 0xEF, 0xB4, 0x02, 0x04, 0x91, 0x50, 0x81, 0x04, 0x90, 0x82, 0x16, ++0xE0, 0xFF, 0xB4, 0x03, 0x04, 0x91, 0x54, 0x81, 0x04, 0xEF, 0x64, 0x01, 0x60, 0x02, 0x81, 0x04, ++0x91, 0x43, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, 0x04, 0x91, 0xF3, 0x81, 0x04, ++0xEF, 0xB4, 0x02, 0x04, 0x91, 0x58, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x03, 0x04, ++0x91, 0xE8, 0x81, 0x04, 0xEF, 0x70, 0x7D, 0x91, 0x2B, 0x80, 0x79, 0x90, 0x82, 0x16, 0xE0, 0xB4, ++0x04, 0x05, 0x12, 0x74, 0x60, 0x80, 0x6D, 0x90, 0x82, 0x16, 0xE0, 0xB4, 0x01, 0x04, 0x91, 0x21, ++0x80, 0x62, 0x90, 0x82, 0x16, 0xE0, 0xB4, 0x03, 0x05, 0x12, 0x74, 0x71, 0x80, 0x56, 0x90, 0x82, ++0x16, 0xE0, 0x70, 0x50, 0x91, 0x1F, 0x80, 0x4C, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, 0x05, ++0x12, 0x74, 0x4C, 0x80, 0x3F, 0xEF, 0xB4, 0x01, 0x04, 0x91, 0x34, 0x80, 0x37, 0xEF, 0xB4, 0x02, ++0x04, 0x91, 0xDF, 0x80, 0x2F, 0x90, 0x82, 0x16, 0xE0, 0x70, 0x29, 0x91, 0x32, 0x80, 0x25, 0x90, ++0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x03, 0x05, 0x12, 0x74, 0x7B, 0x80, 0x18, 0xEF, 0xB4, 0x01, 0x04, ++0x91, 0x0B, 0x80, 0x10, 0xEF, 0xB4, 0x02, 0x04, 0xB1, 0x06, 0x80, 0x08, 0x90, 0x82, 0x16, 0xE0, ++0x70, 0x02, 0x91, 0x09, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x91, 0x2B, 0x90, 0x05, 0x22, 0x74, 0x6F, ++0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0x91, ++0x2B, 0x12, 0x49, 0xDD, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x81, 0x22, 0x74, 0x01, ++0xF0, 0x22, 0x91, 0x2B, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, ++0x22, 0x91, 0xF3, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0x90, 0x81, 0x22, 0xF0, 0x22, ++0x91, 0x58, 0x80, 0xEF, 0x91, 0xE8, 0x80, 0xEB, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, ++0x81, 0x22, 0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x01, 0x01, 0xE0, ++0x44, 0x02, 0xF0, 0x90, 0x01, 0x00, 0x74, 0xFF, 0xF0, 0x90, 0x06, 0xB7, 0x74, 0x09, 0xF0, 0x90, ++0x06, 0xB4, 0x74, 0x86, 0xF0, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x54, 0x7F, 0xFC, ++0x90, 0x82, 0x01, 0x12, 0x20, 0xCE, 0x90, 0x82, 0x01, 0x12, 0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, ++0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, ++0xC0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, ++0x00, 0xC0, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xF9, 0x12, 0x20, ++0xDA, 0x00, 0x03, 0x3E, 0x60, 0xE4, 0xFD, 0xFF, 0xB1, 0x1C, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x91, ++0x65, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, 0x22, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x22, ++0x04, 0xF0, 0x22, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, ++0x81, 0x22, 0x74, 0x01, 0xF0, 0x22, 0x91, 0x65, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x90, 0x05, ++0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, ++0xC3, 0xC0, 0xD0, 0xC0, 0x07, 0xC0, 0x05, 0x90, 0x81, 0xF9, 0x12, 0x44, 0xD9, 0x90, 0x81, 0xE5, ++0x12, 0x20, 0xCE, 0xD0, 0x05, 0xD0, 0x07, 0x12, 0x60, 0xF5, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, ++0x81, 0xC8, 0x12, 0x45, 0x1F, 0xEF, 0x12, 0x45, 0x28, 0x55, 0x71, 0x00, 0x55, 0x7A, 0x01, 0x55, ++0x83, 0x02, 0x55, 0x8B, 0x03, 0x55, 0x94, 0x04, 0x55, 0x9C, 0x20, 0x55, 0xA4, 0x21, 0x55, 0xAD, ++0x23, 0x55, 0xB5, 0x24, 0x55, 0xBE, 0x25, 0x55, 0xC7, 0x26, 0x55, 0xCF, 0xC0, 0x00, 0x00, 0x55, ++0xD8, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6A, 0xB0, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, ++0x02, 0x65, 0x81, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x41, 0xC0, 0x90, 0x81, 0xC8, 0x12, 0x45, ++0x16, 0x02, 0x75, 0xD8, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x80, 0x44, 0x90, 0x81, 0xC8, 0x12, ++0x45, 0x16, 0xC1, 0x4B, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6A, 0xF8, 0x90, 0x81, 0xC8, ++0x12, 0x45, 0x16, 0xE1, 0xE1, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x4A, 0x6C, 0x90, 0x81, ++0xC8, 0x12, 0x45, 0x16, 0x02, 0x6B, 0x3E, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x80, 0x3E, 0x90, ++0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6B, 0x4E, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x22, ++0x12, 0x5A, 0x4B, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x45, 0xE0, 0x54, 0xFE, ++0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x14, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, ++0x46, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x47, 0xF0, 0x22, 0x12, 0x1F, 0xA4, ++0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0x90, 0x00, 0x01, 0x12, ++0x1F, 0xBD, 0xFE, 0x90, 0x05, 0x54, 0xE0, 0xC3, 0x9E, 0x90, 0x81, 0x40, 0xF0, 0xEF, 0x20, 0xE0, ++0x07, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0x01, 0x90, 0x01, ++0xBC, 0xF0, 0x90, 0x81, 0x40, 0xE0, 0x90, 0x01, 0xBD, 0xF0, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, ++0x7F, 0x90, 0x81, 0x27, 0xF0, 0xEF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0xA3, 0xF0, 0x90, 0x00, ++0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x54, 0xF0, 0xC4, 0x54, 0x0F, 0xFE, 0x90, 0x81, 0x26, 0xE0, 0x54, ++0xF0, 0x4E, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x54, 0x01, 0x25, 0xE0, 0xFE, 0x90, 0x81, ++0x24, 0xE0, 0x54, 0xFD, 0x4E, 0xF0, 0xEF, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0x90, 0x81, 0x26, ++0xE0, 0x54, 0x0F, 0x4F, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x29, 0xF0, 0xD1, ++0xC6, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x90, ++0x01, 0xBA, 0xF0, 0x90, 0x81, 0x29, 0xE0, 0x90, 0x01, 0xBB, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, ++0x0F, 0x90, 0x01, 0xBE, 0xF0, 0x22, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x12, 0x72, 0xB3, 0x90, ++0x81, 0x27, 0xE0, 0xFF, 0x12, 0x4C, 0x3E, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x19, 0x90, 0x81, 0xCB, ++0x12, 0x45, 0x16, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x54, 0x0F, 0xFF, 0x90, 0x00, 0x02, 0x12, ++0x1F, 0xBD, 0xFD, 0x12, 0x72, 0xC4, 0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, ++0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, ++0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xF7, 0xF0, 0x74, 0x56, 0xA3, 0xF0, 0x12, 0x6C, ++0xA5, 0xE5, 0x49, 0x30, 0xE1, 0x03, 0x12, 0x6F, 0x79, 0xE5, 0x49, 0x30, 0xE2, 0x02, 0xF1, 0xA5, ++0xE5, 0x49, 0x30, 0xE3, 0x03, 0x12, 0x6F, 0x8D, 0xE5, 0x4A, 0x30, 0xE0, 0x03, 0x12, 0x6F, 0xC9, ++0xE5, 0x4A, 0x30, 0xE4, 0x03, 0x12, 0x70, 0x22, 0xE5, 0x4B, 0x30, 0xE1, 0x02, 0x51, 0x78, 0xE5, ++0x4B, 0x30, 0xE0, 0x02, 0x31, 0xFF, 0xE5, 0x4B, 0x30, 0xE3, 0x02, 0xF1, 0xE0, 0xE5, 0x4C, 0x30, ++0xE1, 0x05, 0x7F, 0x03, 0x12, 0x44, 0x27, 0xE5, 0x4C, 0x30, 0xE4, 0x03, 0x12, 0x4E, 0xC4, 0xE5, ++0x4C, 0x30, 0xE5, 0x03, 0x12, 0x70, 0x38, 0xE5, 0x4C, 0x30, 0xE6, 0x03, 0x12, 0x70, 0xCE, 0x74, ++0xF7, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x56, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, ++0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, ++0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x34, 0x90, 0x06, 0x92, 0xE0, 0x30, ++0xE0, 0x23, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, ++0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x11, 0x05, 0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x90, 0x06, ++0x92, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x12, 0x47, 0x2A, 0x22, ++0x22, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x31, 0xF0, 0x22, 0x90, 0x01, 0xC8, 0xE4, 0xF0, 0xA3, 0xF0, ++0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x51, 0x7F, 0xFF, 0xFE, 0x12, 0x2B, 0x27, 0xBF, 0x01, ++0x09, 0x90, 0x81, 0x51, 0xE0, 0x64, 0x03, 0x60, 0x03, 0x22, 0x01, 0xAB, 0xE4, 0x90, 0x81, 0x56, ++0xF0, 0x90, 0x81, 0x56, 0xE0, 0xFF, 0xC3, 0x94, 0x02, 0x40, 0x02, 0x01, 0xE6, 0xC3, 0x74, 0xFE, ++0x9F, 0xFF, 0xE4, 0x94, 0x00, 0xFE, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x52, 0x12, 0x2B, 0x27, 0xEF, ++0x64, 0x01, 0x70, 0x77, 0x90, 0x81, 0x52, 0xE0, 0xFF, 0x54, 0xC0, 0xFE, 0x60, 0x05, 0xEF, 0x54, ++0x0C, 0x70, 0x16, 0x90, 0x81, 0x52, 0xE0, 0xFF, 0x54, 0x30, 0x60, 0x67, 0xEF, 0x54, 0x03, 0x60, ++0x62, 0x90, 0x81, 0x53, 0x74, 0x01, 0xF0, 0x80, 0x05, 0xE4, 0x90, 0x81, 0x53, 0xF0, 0x90, 0x81, ++0x53, 0xE0, 0x90, 0x81, 0x52, 0x70, 0x16, 0xE0, 0xFF, 0xEE, 0x13, 0x13, 0x54, 0x3F, 0x90, 0x81, ++0x54, 0xF0, 0xEF, 0x54, 0x0C, 0x13, 0x13, 0x54, 0x3F, 0xA3, 0xF0, 0x80, 0x0D, 0xE0, 0xFE, 0x54, ++0x30, 0x90, 0x81, 0x54, 0xF0, 0xEE, 0x54, 0x03, 0xA3, 0xF0, 0x90, 0x81, 0x54, 0xE0, 0x64, 0x30, ++0x70, 0x54, 0xA3, 0xE0, 0x64, 0x02, 0x70, 0x4E, 0x90, 0x00, 0xF5, 0xE0, 0x54, 0x40, 0x90, 0x81, ++0x57, 0xF0, 0xE0, 0x70, 0x41, 0xA3, 0x74, 0x02, 0xF0, 0x80, 0x10, 0x90, 0x81, 0x58, 0x74, 0x01, ++0xF0, 0x80, 0x08, 0x90, 0x81, 0x56, 0xE0, 0x04, 0xF0, 0x01, 0x11, 0x90, 0x01, 0xC4, 0x74, 0xE9, ++0xF0, 0x74, 0x57, 0xA3, 0xF0, 0x90, 0x81, 0x58, 0xE0, 0x90, 0x01, 0xC8, 0xF0, 0x90, 0x81, 0x52, ++0xE0, 0x90, 0x01, 0xC9, 0xF0, 0x90, 0x81, 0x53, 0xE0, 0x90, 0x01, 0xCA, 0xF0, 0xE4, 0xFD, 0x7F, ++0x1F, 0x12, 0x32, 0x1E, 0x80, 0xD5, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x20, 0xE7, 0x09, 0xE0, 0x7F, ++0x01, 0x20, 0xE6, 0x0C, 0x7F, 0x02, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x30, 0xE6, 0x02, 0x7F, 0x03, ++0x22, 0x11, 0xE7, 0x90, 0x80, 0x3C, 0xEF, 0xF0, 0x31, 0x13, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0, ++0x02, 0x2D, 0xA7, 0x31, 0x81, 0x31, 0xB1, 0x31, 0x40, 0x31, 0x5F, 0xE4, 0xF5, 0x35, 0xF5, 0x36, ++0xF5, 0x37, 0xF5, 0x38, 0xAD, 0x35, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xAD, 0x36, 0x7F, 0x51, 0x12, ++0x32, 0x1E, 0xAD, 0x37, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xAD, 0x38, 0x7F, 0x53, 0x02, 0x32, 0x1E, ++0x75, 0x3D, 0x10, 0xE4, 0xF5, 0x3E, 0x75, 0x3F, 0x07, 0x75, 0x40, 0x02, 0x90, 0x01, 0x30, 0xE5, ++0x3D, 0xF0, 0xA3, 0xE5, 0x3E, 0xF0, 0xA3, 0xE5, 0x3F, 0xF0, 0xA3, 0xE5, 0x40, 0xF0, 0x22, 0x75, ++0x45, 0x0E, 0x75, 0x46, 0x01, 0x43, 0x46, 0x10, 0x75, 0x47, 0x03, 0x75, 0x48, 0x62, 0x90, 0x01, ++0x38, 0xE5, 0x45, 0xF0, 0xA3, 0xE5, 0x46, 0xF0, 0xA3, 0xE5, 0x47, 0xF0, 0xA3, 0xE5, 0x48, 0xF0, ++0x22, 0x90, 0x01, 0x30, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x38, 0xF0, ++0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x51, ++0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x53, 0x02, 0x32, ++0x1E, 0x90, 0x01, 0x34, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x3C, ++0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, ++0x55, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x56, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x57, 0x02, ++0x32, 0x1E, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x80, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x90, 0xFD, ++0x00, 0xE0, 0x54, 0xBF, 0xF0, 0x12, 0x57, 0xE9, 0x51, 0x77, 0x12, 0x32, 0x77, 0x51, 0xC9, 0x51, ++0x5E, 0x7F, 0x01, 0x12, 0x43, 0x15, 0x90, 0x81, 0x41, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x43, 0x15, ++0x90, 0x81, 0x41, 0xE0, 0x04, 0xF0, 0x7F, 0x03, 0x12, 0x43, 0x15, 0x90, 0x81, 0x41, 0xE0, 0x04, ++0xF0, 0x31, 0x01, 0x51, 0x3F, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x40, 0xFD, 0x7F, 0x80, 0x12, 0x32, ++0x1E, 0x75, 0x20, 0xFF, 0x51, 0x68, 0x51, 0xF9, 0x51, 0x7F, 0xE4, 0xFF, 0x02, 0x43, 0x9E, 0x51, ++0x62, 0x51, 0x6F, 0x51, 0xA7, 0x71, 0x4F, 0x51, 0x8A, 0x51, 0x95, 0x90, 0x81, 0x45, 0xE0, 0x54, ++0xFE, 0xF0, 0xA3, 0x74, 0x03, 0xF0, 0xA3, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0xE4, 0xF5, ++0x4D, 0x22, 0xE4, 0x90, 0x80, 0xDE, 0xF0, 0x22, 0x75, 0xE8, 0x03, 0x75, 0xA8, 0x84, 0x22, 0xE4, ++0x90, 0x80, 0xD8, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x01, 0x94, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, ++0x01, 0xE4, 0x74, 0x0B, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, ++0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x42, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, ++0x74, 0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0xFD, ++0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0xE4, 0xA3, 0xF0, ++0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0x74, 0x0C, 0xF0, 0x22, 0x90, 0x01, 0x01, 0xE0, 0x44, 0x04, 0xF0, ++0x90, 0x01, 0x9C, 0x74, 0x7E, 0xF0, 0xA3, 0x74, 0x92, 0xF0, 0xA3, 0x74, 0xA0, 0xF0, 0xA3, 0x74, ++0x24, 0xF0, 0x90, 0x01, 0x9B, 0x74, 0x49, 0xF0, 0x90, 0x01, 0x9A, 0x74, 0xE0, 0xF0, 0x90, 0x01, ++0x99, 0xE4, 0xF0, 0x90, 0x01, 0x98, 0x04, 0xF0, 0x22, 0xE4, 0x90, 0x81, 0x51, 0xF0, 0xA3, 0xF0, ++0x90, 0x01, 0x98, 0xE0, 0x7F, 0x00, 0x30, 0xE4, 0x02, 0x7F, 0x01, 0xEF, 0x64, 0x01, 0x60, 0x3E, ++0xC3, 0x90, 0x81, 0x52, 0xE0, 0x94, 0x88, 0x90, 0x81, 0x51, 0xE0, 0x94, 0x13, 0x40, 0x08, 0x90, ++0x01, 0xC1, 0xE0, 0x44, 0x10, 0xF0, 0x22, 0x90, 0x81, 0x51, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, ++0xA9, 0x7F, 0x14, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0xD3, 0x90, 0x81, 0x52, 0xE0, 0x94, 0x32, 0x90, ++0x81, 0x51, 0xE0, 0x94, 0x00, 0x40, 0xB9, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE3, 0xB2, 0x22, 0xE4, ++0x90, 0x81, 0x27, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0xF0, 0x54, 0xF0, 0xF0, ++0x90, 0x81, 0x24, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x2D, ++0x74, 0x01, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFB, 0xF0, 0xA3, 0xE0, 0x54, 0xFB, ++0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, 0x81, 0x2F, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xE4, ++0xF0, 0xA3, 0x74, 0x02, 0xF0, 0xE4, 0x90, 0x81, 0x2B, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFE, ++0xF0, 0x90, 0x81, 0x29, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xDF, 0xF0, 0x90, 0x81, ++0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0xE0, ++0x54, 0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x90, 0x81, 0x34, 0x12, 0x20, 0xDA, 0x00, ++0x00, 0x00, 0x00, 0x90, 0x80, 0x3C, 0xE0, 0xB4, 0x01, 0x08, 0x90, 0x81, 0x31, 0x74, 0x99, 0xF0, ++0x80, 0x12, 0x90, 0x80, 0x3C, 0xE0, 0x90, 0x81, 0x31, 0xB4, 0x03, 0x05, 0x74, 0x90, 0xF0, 0x80, ++0x03, 0x74, 0x40, 0xF0, 0x90, 0x81, 0x38, 0x74, 0x01, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xE0, ++0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, ++0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xBF, 0xF0, ++0xE4, 0xA3, 0xF0, 0x22, 0xE4, 0x90, 0x81, 0x59, 0xF0, 0x90, 0x81, 0x59, 0xE0, 0x64, 0x01, 0xF0, ++0x24, 0x24, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x5C, 0xA3, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0xFF, 0x90, ++0x81, 0x29, 0xE0, 0x6F, 0x60, 0x03, 0x12, 0x47, 0x2A, 0xD1, 0x08, 0xBF, 0x01, 0x02, 0x91, 0x5F, ++0xB1, 0xF2, 0x12, 0x32, 0x9E, 0xBF, 0x01, 0x02, 0xB1, 0x67, 0x12, 0x42, 0x4D, 0x80, 0xCA, 0xD3, ++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x24, 0xE0, 0x30, 0xE0, 0x24, 0x90, 0x81, 0x1F, ++0xE0, 0xFF, 0x30, 0xE0, 0x1A, 0xC3, 0x13, 0x30, 0xE0, 0x07, 0xB1, 0xFB, 0xBF, 0x01, 0x12, 0x80, ++0x0A, 0x90, 0x81, 0x23, 0xE0, 0xFF, 0x60, 0x03, 0xB4, 0x08, 0x06, 0x91, 0x96, 0x80, 0x02, 0x91, ++0xA6, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xB1, 0x22, 0x91, ++0xBA, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0x2A, 0xE0, 0x70, 0x0D, 0xD1, 0x2F, 0xBF, 0x01, ++0x08, 0x91, 0x96, 0x90, 0x01, 0xE5, 0xE0, 0x04, 0xF0, 0x22, 0xB1, 0xF3, 0x90, 0x00, 0x08, 0xE0, ++0x54, 0xEF, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, 0xE4, 0xFF, 0x8F, 0x50, 0xE4, 0x90, 0x81, 0x5A, ++0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x09, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0xEF, 0x65, ++0x50, 0x60, 0x3E, 0xC3, 0x90, 0x81, 0x5B, 0xE0, 0x94, 0x88, 0x90, 0x81, 0x5A, 0xE0, 0x94, 0x13, ++0x40, 0x08, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x10, 0xF0, 0x22, 0x90, 0x81, 0x5A, 0xE4, 0x75, 0xF0, ++0x01, 0x12, 0x44, 0xA9, 0x7F, 0x14, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0xD3, 0x90, 0x81, 0x5B, 0xE0, ++0x94, 0x32, 0x90, 0x81, 0x5A, 0xE0, 0x94, 0x00, 0x40, 0xB9, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE0, ++0xB2, 0x22, 0x90, 0x81, 0x31, 0xE0, 0xFD, 0x7F, 0x93, 0x12, 0x32, 0x1E, 0x90, 0x81, 0x28, 0xE0, ++0x60, 0x12, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x05, 0x74, 0x10, 0xF0, 0x80, 0x06, 0x90, 0x01, ++0x2F, 0x74, 0x90, 0xF0, 0x90, 0x00, 0x08, 0xE0, 0x44, 0x10, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, ++0x7F, 0x01, 0x91, 0xCA, 0x90, 0x00, 0x90, 0xE0, 0x44, 0x01, 0xFD, 0x7F, 0x90, 0x12, 0x32, 0x1E, ++0x7F, 0x14, 0x7E, 0x00, 0x02, 0x32, 0xAA, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x2D, ++0xA7, 0xE4, 0xF5, 0x52, 0x12, 0x32, 0x9E, 0xEF, 0x60, 0x73, 0x63, 0x52, 0x01, 0xE5, 0x52, 0x24, ++0x67, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x5D, 0xA3, 0xF0, 0x90, 0x00, 0x88, 0xE0, 0xF5, 0x50, 0xF5, ++0x51, 0x54, 0x0F, 0x60, 0xDF, 0xE5, 0x50, 0x30, 0xE0, 0x0B, 0x20, 0xE4, 0x03, 0x12, 0x29, 0xC5, ++0x53, 0x51, 0xEE, 0x80, 0x3F, 0xE5, 0x50, 0x30, 0xE1, 0x16, 0x20, 0xE5, 0x0E, 0x12, 0x11, 0xBD, ++0xEF, 0x70, 0x03, 0x43, 0x51, 0x20, 0x90, 0x01, 0x06, 0xE4, 0xF0, 0x53, 0x51, 0xFD, 0x80, 0x24, ++0xE5, 0x50, 0x30, 0xE2, 0x0B, 0x20, 0xE6, 0x03, 0x12, 0x67, 0x06, 0x53, 0x51, 0xFB, 0x80, 0x14, ++0xE5, 0x50, 0x30, 0xE3, 0x0F, 0x20, 0xE7, 0x09, 0x12, 0x61, 0x6E, 0xEF, 0x70, 0x03, 0x43, 0x51, ++0x80, 0x53, 0x51, 0xF7, 0xAD, 0x51, 0x7F, 0x88, 0x12, 0x32, 0x1E, 0x80, 0x87, 0xD0, 0xD0, 0x92, ++0xAF, 0x22, 0x22, 0x90, 0x00, 0x90, 0xE0, 0x20, 0xE0, 0xF9, 0x22, 0x90, 0x81, 0x22, 0xE0, 0x64, ++0x02, 0x7F, 0x01, 0x60, 0x02, 0x7F, 0x00, 0x22, 0x7F, 0x02, 0x90, 0x81, 0x41, 0xE0, 0xFE, 0xEF, ++0xC3, 0x9E, 0x50, 0x18, 0xEF, 0x25, 0xE0, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, ++0xB8, 0x74, 0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, 0x0F, 0x80, 0xDE, 0x7F, 0x01, 0x22, 0x90, ++0x02, 0x87, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x01, 0xF0, 0x80, 0x17, 0x90, 0x02, 0x86, ++0xE0, 0x20, 0xE1, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, ++0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x08, 0xF0, 0x7F, 0x00, 0x22, 0xE4, 0xFB, 0xFA, ++0xFD, 0x7F, 0x01, 0x12, 0x44, 0x4E, 0x90, 0x81, 0xBD, 0xEF, 0xF0, 0x60, 0xF0, 0xD1, 0x71, 0x80, ++0xEC, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0x90, 0x81, ++0xBE, 0xF0, 0x90, 0x81, 0xBE, 0xE0, 0xFD, 0x70, 0x02, 0xE1, 0x9C, 0x90, 0x82, 0x09, 0xE0, 0xFF, ++0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, ++0xFF, 0xEF, 0x5D, 0x70, 0x02, 0xE1, 0x95, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, ++0xD0, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xBF, 0xF0, 0x75, 0x13, 0x01, 0x75, 0x14, 0x81, 0x75, ++0x15, 0xBF, 0x75, 0x16, 0x01, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xC0, 0x12, 0x2B, 0xED, 0x90, 0x82, ++0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD1, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC1, 0xF0, ++0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD2, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, ++0xC2, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD3, 0x12, 0x45, 0x0A, 0xE0, ++0x90, 0x81, 0xC3, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF0, 0x12, 0x45, ++0x0A, 0xE0, 0x90, 0x81, 0xC4, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF1, ++0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC5, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, ++0x01, 0xF2, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC6, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, ++0x04, 0x90, 0x01, 0xF3, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC7, 0xF0, 0x90, 0x81, 0xBE, 0xE0, ++0xFF, 0x90, 0x82, 0x09, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, ++0xFC, 0xF4, 0x5F, 0x90, 0x81, 0xBE, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, ++0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x90, 0x01, 0xCC, 0xF0, 0x90, 0x81, 0xC0, 0xE0, 0xFF, ++0x7B, 0x01, 0x7A, 0x81, 0x79, 0xC1, 0x12, 0x55, 0x3F, 0x90, 0x82, 0x09, 0xE0, 0x04, 0xF0, 0xE0, ++0x54, 0x03, 0xF0, 0xC1, 0x82, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x44, 0x4E, 0x90, 0x81, 0xD0, 0xEF, 0xF0, 0x60, ++0xF0, 0x12, 0x6C, 0x19, 0x80, 0xEB, 0x90, 0x81, 0xD4, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0x12, ++0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x90, 0x81, 0xE2, 0xF0, 0x7F, 0x24, 0x7E, 0x08, 0x12, ++0x2D, 0x5C, 0x90, 0x81, 0xDA, 0x12, 0x20, 0xCE, 0x90, 0x81, 0xD4, 0xE0, 0xFB, 0x70, 0x08, 0x90, ++0x81, 0xDA, 0x12, 0x44, 0xD9, 0x80, 0x16, 0xEB, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, ++0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2D, 0x5C, 0x90, 0x81, 0xDE, ++0x12, 0x20, 0xCE, 0x90, 0x81, 0xD5, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x17, 0x12, 0x20, ++0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0xDE, 0x12, 0x44, 0xD9, 0xED, ++0x54, 0x7F, 0xFD, 0xEC, 0x54, 0x80, 0xFC, 0x12, 0x44, 0xCC, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x81, ++0xDE, 0x12, 0x20, 0xCE, 0x90, 0x81, 0xDA, 0x12, 0x44, 0xD9, 0xEC, 0x54, 0x7F, 0xFC, 0x90, 0x85, ++0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xD4, 0xE0, 0x75, ++0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, ++0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0xDE, 0x12, 0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, 0x20, ++0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xDA, 0x12, 0x44, 0xD9, 0xEC, 0x44, ++0x80, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, ++0x81, 0xD4, 0xE0, 0x70, 0x04, 0x7F, 0x20, 0x80, 0x09, 0x90, 0x81, 0xD4, 0xE0, 0xB4, 0x01, 0x16, ++0x7F, 0x28, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x78, 0x08, 0x12, 0x20, 0xA8, 0xEF, 0x54, 0x01, 0xFF, ++0xE4, 0x90, 0x81, 0xE2, 0xEF, 0xF0, 0x90, 0x81, 0xE2, 0xE0, 0x90, 0x81, 0xD4, 0x60, 0x0E, 0xE0, ++0x75, 0xF0, 0x08, 0xA4, 0x24, 0x66, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0x80, 0x0C, 0xE0, 0x75, 0xF0, ++0x08, 0xA4, 0x24, 0x64, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, ++0x12, 0x2D, 0x5C, 0xED, 0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x90, 0x81, 0xD6, 0x12, 0x20, 0xCE, 0x90, ++0x81, 0xD6, 0x02, 0x44, 0xD9, 0x90, 0x81, 0xE3, 0xEF, 0xF0, 0xAB, 0x05, 0x90, 0x81, 0xE9, 0x12, ++0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x03, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x14, 0x12, 0x20, ++0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0xE5, 0x12, 0x44, 0xD9, 0xED, ++0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x12, 0x44, 0xCC, 0xEC, 0x54, 0x0F, 0xFC, 0x90, 0x81, 0xE9, 0x12, ++0x20, 0xCE, 0x90, 0x81, 0xE3, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x60, 0xF5, 0x82, 0xE4, 0x34, ++0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0xE9, 0x12, ++0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x02, 0x2E, 0xA2, 0xD3, ++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x5F, 0xB6, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x78, 0x10, ++0x74, 0x01, 0xF2, 0x90, 0x02, 0x09, 0xE0, 0x78, 0x00, 0xF2, 0x08, 0x74, 0x20, 0xF2, 0x18, 0xE2, ++0xFF, 0x30, 0xE0, 0x05, 0x08, 0xE2, 0x24, 0x80, 0xF2, 0xEF, 0xC3, 0x13, 0x90, 0xFD, 0x10, 0xF0, ++0x78, 0x01, 0xE2, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x78, 0x03, 0xF2, ++0x64, 0x04, 0x60, 0x0D, 0xE2, 0xFF, 0x64, 0x08, 0x60, 0x07, 0xEF, 0x64, 0x0C, 0x60, 0x02, 0x61, ++0xDE, 0xE4, 0x78, 0x02, 0xF2, 0x78, 0x03, 0xE2, 0xFF, 0x18, 0xE2, 0xC3, 0x9F, 0x50, 0x2D, 0xE2, ++0xFD, 0x18, 0xE2, 0x2D, 0x90, 0x81, 0x5A, 0xF0, 0xE0, 0xFF, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, ++0xFC, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x04, 0x2D, 0xF8, 0xEE, 0xF2, 0xEF, 0xB4, 0xFF, 0x06, 0x90, ++0xFD, 0x10, 0xE0, 0x04, 0xF0, 0x78, 0x02, 0xE2, 0x04, 0xF2, 0x80, 0xC9, 0x78, 0x04, 0xE2, 0x78, ++0x12, 0xF2, 0xFF, 0x78, 0x05, 0xE2, 0x78, 0x11, 0xF2, 0x78, 0x06, 0xE2, 0x78, 0x13, 0xF2, 0x78, ++0x07, 0xE2, 0x78, 0x14, 0xF2, 0x78, 0x08, 0xE2, 0x78, 0x33, 0xF2, 0x78, 0x09, 0xE2, 0x78, 0x34, ++0xF2, 0x78, 0x0A, 0xE2, 0x78, 0x35, 0xF2, 0x78, 0x0B, 0xE2, 0x78, 0x36, 0xF2, 0x78, 0x0C, 0xE2, ++0x78, 0x37, 0xF2, 0x78, 0x0D, 0xE2, 0x78, 0x38, 0xF2, 0x78, 0x0E, 0xE2, 0x78, 0x39, 0xF2, 0x78, ++0x0F, 0xE2, 0x78, 0x3A, 0xF2, 0xE4, 0x78, 0x15, 0xF2, 0xEF, 0x24, 0xF8, 0x60, 0x75, 0x24, 0xFC, ++0x60, 0x6C, 0x24, 0x08, 0x60, 0x02, 0x61, 0xC0, 0x78, 0x11, 0xE2, 0xB4, 0x01, 0x05, 0x12, 0x29, ++0xC5, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x02, 0x05, 0x12, 0x11, 0xBD, 0x61, 0xC5, 0x78, 0x11, ++0xE2, 0xB4, 0x03, 0x04, 0xF1, 0x06, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x10, 0x17, 0x78, 0x14, ++0xE2, 0xFE, 0x18, 0xE2, 0xFD, 0xED, 0xFF, 0x78, 0x16, 0xEE, 0xF2, 0xFE, 0x08, 0xEF, 0xF2, 0xFF, ++0x12, 0x32, 0xAA, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x11, 0x17, 0x78, 0x14, 0xE2, 0xFE, 0x18, ++0xE2, 0xFD, 0xED, 0xFF, 0x78, 0x16, 0xEE, 0xF2, 0xFE, 0x08, 0xEF, 0xF2, 0xFF, 0x12, 0x32, 0x06, ++0x61, 0xC5, 0x78, 0x11, 0xE2, 0xF4, 0x60, 0x02, 0x61, 0xC5, 0x18, 0xF2, 0x61, 0xC5, 0x78, 0x15, ++0x74, 0x01, 0xF2, 0x78, 0x11, 0xE2, 0x64, 0x07, 0x60, 0x02, 0x61, 0xAA, 0x78, 0x34, 0xE2, 0xFF, ++0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xC0, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, ++0x07, 0x78, 0x33, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0xC0, 0x04, ++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x78, 0x35, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, ++0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x18, ++0x12, 0x44, 0xFE, 0x78, 0x15, 0xE2, 0x70, 0x02, 0x61, 0x93, 0x18, 0xE2, 0xFF, 0x18, 0xE2, 0xFD, ++0x31, 0x5F, 0x78, 0x1C, 0x12, 0x44, 0xFE, 0x78, 0x38, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, ++0x08, 0x12, 0x20, 0xBB, 0xC0, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x78, 0x37, 0xE2, 0xFF, ++0xE4, 0xFC, 0xFD, 0xFE, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, ++0x07, 0x78, 0x39, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, 0xBB, 0xD0, 0x03, ++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x20, 0x12, 0x44, 0xFE, 0x78, 0x20, ++0x12, 0x44, 0xE5, 0x12, 0x20, 0x9B, 0x78, 0x1C, 0x12, 0x44, 0xF1, 0x12, 0x44, 0xBF, 0xC0, 0x04, ++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x78, 0x18, 0x12, 0x44, 0xE5, 0x78, 0x20, 0x12, 0x44, 0xF1, ++0x12, 0x44, 0xBF, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x18, ++0x12, 0x44, 0xFE, 0x78, 0x18, 0x12, 0x44, 0xE5, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xCE, 0x78, 0x13, ++0xE2, 0xFD, 0x08, 0xE2, 0xFF, 0x12, 0x55, 0x1C, 0x80, 0x1B, 0x78, 0x13, 0xE2, 0xFF, 0x08, 0xE2, ++0xFD, 0x78, 0x11, 0xE2, 0xFB, 0x78, 0x15, 0xE2, 0x90, 0x81, 0xBC, 0xF0, 0x71, 0xE1, 0x80, 0x05, ++0x78, 0x10, 0x74, 0x02, 0xF2, 0x78, 0x10, 0xE2, 0xFF, 0xC3, 0x94, 0x02, 0x50, 0x10, 0xEF, 0x60, ++0x0A, 0x78, 0x02, 0xE2, 0xFF, 0x18, 0xE2, 0x2F, 0xF2, 0x21, 0x90, 0x7F, 0x01, 0x22, 0x7F, 0x00, ++0x22, 0xAC, 0x07, 0xED, 0xAD, 0x04, 0x78, 0x24, 0xF2, 0xED, 0x08, 0xF2, 0xEB, 0xB4, 0x04, 0x07, ++0x78, 0x27, 0x74, 0x01, 0xF2, 0x80, 0x0E, 0xEB, 0x78, 0x27, 0xB4, 0x05, 0x05, 0x74, 0x02, 0xF2, ++0x80, 0x03, 0x74, 0x04, 0xF2, 0xD3, 0x78, 0x25, 0xE2, 0x94, 0xFF, 0x18, 0xE2, 0x94, 0x00, 0x50, ++0x63, 0xE4, 0x78, 0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x40, 0x02, ++0xA1, 0x7F, 0x74, 0x33, 0x2E, 0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2D, ++0x74, 0x37, 0x2E, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xEE, 0xFF, 0x78, 0x25, 0xE2, 0x2F, 0xFF, 0x18, ++0xE2, 0x34, 0x00, 0x8F, 0x82, 0xF5, 0x83, 0xE0, 0x78, 0x29, 0xF2, 0x78, 0x32, 0xE2, 0xFF, 0xF4, ++0xFE, 0x78, 0x29, 0xE2, 0x5E, 0xFE, 0x18, 0xE2, 0xFD, 0xEF, 0x5D, 0x4E, 0xF2, 0x78, 0x24, 0x08, ++0xE2, 0xFF, 0x08, 0xE2, 0x2F, 0xFF, 0x78, 0x28, 0xE2, 0xFD, 0x12, 0x32, 0x1E, 0x78, 0x26, 0xE2, ++0x04, 0xF2, 0x80, 0xA1, 0xD3, 0x78, 0x25, 0xE2, 0x94, 0xFF, 0x18, 0xE2, 0x94, 0x07, 0x50, 0x69, ++0xE4, 0x78, 0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x40, 0x02, 0xA1, ++0x7F, 0x74, 0x33, 0x2E, 0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2D, 0x78, ++0x26, 0xE2, 0xFF, 0xFD, 0x18, 0xE2, 0x2D, 0xFD, 0x18, 0xE2, 0x34, 0x00, 0x8D, 0x82, 0xF5, 0x83, ++0xE0, 0x78, 0x29, 0xF2, 0x74, 0x37, 0x2F, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xE2, 0xFF, 0xF4, 0xFE, ++0x78, 0x29, 0xE2, 0x5E, 0xFE, 0x18, 0xE2, 0xFD, 0xEF, 0x5D, 0x4E, 0xF2, 0x78, 0x28, 0xE2, 0xFF, ++0x78, 0x26, 0xE2, 0xFD, 0x18, 0xE2, 0x2D, 0xFD, 0x18, 0xE2, 0x34, 0x00, 0x8D, 0x82, 0xF5, 0x83, ++0xEF, 0xF0, 0x78, 0x26, 0xE2, 0x04, 0xF2, 0x80, 0x9B, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x0F, 0x78, ++0x24, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, 0x12, 0x2D, 0x5C, 0x78, 0x2E, 0x12, 0x44, 0xFE, 0xE4, 0x78, ++0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x50, 0x5D, 0x74, 0x33, 0x2E, ++0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2B, 0x78, 0x2E, 0x12, 0x44, 0xE5, ++0x78, 0x26, 0xE2, 0xFB, 0x75, 0xF0, 0x08, 0xA4, 0xF9, 0xF8, 0x12, 0x20, 0xA8, 0x78, 0x29, 0xEF, ++0xF2, 0x74, 0x37, 0x2B, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xE2, 0xFE, 0xF4, 0x5F, 0xFF, 0x78, 0x28, ++0xE2, 0xFD, 0xEE, 0x5D, 0x4F, 0xF2, 0x78, 0x28, 0xE2, 0xFF, 0x78, 0x26, 0xE2, 0xFD, 0xC3, 0x74, ++0x03, 0x9D, 0xFD, 0xE4, 0x94, 0x00, 0xFC, 0x7B, 0xFE, 0x74, 0x2A, 0x2D, 0xF9, 0x74, 0x80, 0x3C, ++0xFA, 0xEF, 0x12, 0x1F, 0xEA, 0xE2, 0x04, 0xF2, 0x80, 0x98, 0x78, 0x2A, 0x12, 0x44, 0xE5, 0x90, ++0x85, 0xBB, 0x12, 0x20, 0xCE, 0x78, 0x24, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, 0x12, 0x2E, 0xA2, 0x22, ++0x22, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xFE, 0x12, ++0x1F, 0xA4, 0xFD, 0xC3, 0x13, 0x30, 0xE0, 0x12, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x90, 0x00, ++0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0xCF, 0xF0, 0x80, 0x05, 0x90, 0x81, 0xCF, 0xEF, 0xF0, 0x90, ++0x81, 0xCE, 0xEE, 0xF0, 0x90, 0x81, 0xCF, 0xE0, 0xFE, 0x90, 0x81, 0xCE, 0xE0, 0xFF, 0xD3, 0x9E, ++0x50, 0x38, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x12, 0x1F, 0xA4, 0x54, 0x01, 0xFE, 0x74, 0xDE, ++0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xEE, 0xF0, 0x74, 0xDE, 0x2F, 0xF5, 0x82, 0xE4, ++0x34, 0x80, 0xF5, 0x83, 0xE0, 0x70, 0x04, 0xD1, 0x25, 0x80, 0x07, 0x90, 0x81, 0xCE, 0xE0, 0xFF, ++0xB1, 0x80, 0x90, 0x81, 0xCE, 0xE0, 0x04, 0xF0, 0x80, 0xBA, 0x90, 0x80, 0xDE, 0xE0, 0x70, 0x24, ++0x90, 0x81, 0x2A, 0xE0, 0x70, 0x04, 0xFF, 0x12, 0x49, 0x93, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, ++0x60, 0x02, 0xD1, 0x26, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xBF, ++0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x05, 0x22, ++0xE4, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x22, 0x90, 0x81, 0xED, 0xEF, 0xF0, 0xA3, 0xED, ++0xF0, 0xAD, 0x03, 0xAC, 0x02, 0xE4, 0x90, 0x81, 0xF5, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0xC4, 0x74, ++0x39, 0xF0, 0x74, 0x66, 0xA3, 0xF0, 0xEC, 0x54, 0x3F, 0xFC, 0x90, 0x01, 0x40, 0xED, 0xF0, 0xAE, ++0x04, 0xEE, 0xA3, 0xF0, 0x90, 0x81, 0xED, 0xE0, 0x24, 0x81, 0x60, 0x34, 0x24, 0xDA, 0x60, 0x1C, ++0x24, 0x3C, 0x70, 0x41, 0x90, 0x81, 0xEE, 0xE0, 0xC4, 0x33, 0x33, 0x33, 0x54, 0x80, 0x90, 0x81, ++0xF2, 0xF0, 0xA3, 0x74, 0x69, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x80, 0x2C, 0x90, 0x81, 0xEE, 0xE0, ++0x54, 0x01, 0x90, 0x81, 0xF2, 0xF0, 0xA3, 0x74, 0xA5, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x80, 0x18, ++0x90, 0x81, 0xEE, 0xE0, 0xC4, 0x54, 0x10, 0x90, 0x81, 0xF2, 0xF0, 0xA3, 0x74, 0x7F, 0xF0, 0xA3, ++0x74, 0x10, 0xF0, 0x80, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x81, 0xF3, 0xE0, 0x90, 0x01, 0x06, 0xF0, ++0x90, 0x81, 0xF2, 0xE0, 0x60, 0x0E, 0x90, 0x01, 0x42, 0xF0, 0x90, 0x81, 0xF1, 0xE0, 0x90, 0x01, ++0x43, 0xF0, 0x80, 0x0D, 0x90, 0x01, 0x43, 0xE4, 0xF0, 0x90, 0x81, 0xF2, 0xE0, 0x90, 0x01, 0x42, ++0xF0, 0x90, 0x81, 0xF4, 0xE0, 0xFF, 0x90, 0x01, 0x42, 0xE0, 0x5F, 0xFF, 0x90, 0x81, 0xF2, 0xE0, ++0x6F, 0x60, 0xEE, 0x74, 0x39, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x66, 0xA3, 0xF0, 0x90, 0x01, ++0x43, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0xE4, 0x90, 0x81, 0x6A, 0xF0, 0x90, 0x87, 0x5F, 0xE0, 0x90, ++0x81, 0x69, 0xF0, 0xE4, 0x90, 0x81, 0x76, 0xF0, 0x90, 0x81, 0x66, 0xF0, 0x90, 0x81, 0x66, 0xE0, ++0xFF, 0xC3, 0x94, 0x40, 0x50, 0x15, 0x74, 0x79, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, ++0x74, 0xFF, 0xF0, 0x90, 0x81, 0x66, 0xE0, 0x04, 0xF0, 0x80, 0xE1, 0xE4, 0x90, 0x81, 0x66, 0xF0, ++0x90, 0x81, 0x69, 0xE0, 0xFF, 0x90, 0x81, 0x66, 0xE0, 0xFE, 0xC3, 0x9F, 0x40, 0x03, 0x02, 0x68, ++0x12, 0x74, 0xDF, 0x2E, 0xF9, 0xE4, 0x34, 0x86, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, ++0x16, 0x0A, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x5B, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x5C, 0xE0, 0xFF, ++0x12, 0x2F, 0x27, 0xEF, 0x04, 0x90, 0x81, 0x76, 0xF0, 0x90, 0x81, 0x5B, 0xE0, 0xFF, 0xA3, 0xE0, ++0xFD, 0x12, 0x31, 0xEA, 0xEF, 0x24, 0xC8, 0x90, 0x81, 0x78, 0xF0, 0x75, 0xF0, 0x08, 0xA4, 0xF0, ++0x90, 0x81, 0x5C, 0xE0, 0x54, 0x0F, 0x90, 0x81, 0x77, 0xF0, 0xE4, 0x90, 0x81, 0x65, 0xF0, 0x90, ++0x81, 0x67, 0xF0, 0x90, 0x81, 0x67, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x57, 0x90, 0x81, 0x77, ++0xE0, 0xFE, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x13, 0xD8, 0xFC, 0x20, 0xE0, 0x3E, 0x90, 0x81, ++0x67, 0xE0, 0x25, 0xE0, 0xFF, 0x90, 0x81, 0x78, 0xE0, 0x2F, 0x24, 0x79, 0xF9, 0xE4, 0x34, 0x81, ++0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x01, 0x90, 0x81, 0x65, 0xE0, 0x75, 0xF0, 0x02, 0xA4, 0x24, ++0x5D, 0xF9, 0x74, 0x81, 0x35, 0xF0, 0x8B, 0x13, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x02, 0xD0, ++0x01, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x65, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x67, 0xE0, ++0x04, 0xF0, 0x80, 0x9F, 0x90, 0x81, 0x76, 0xE0, 0xFF, 0x90, 0x81, 0x66, 0xE0, 0x2F, 0xF0, 0x02, ++0x67, 0x40, 0xE4, 0x90, 0x81, 0x6A, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0xC3, 0x94, 0x40, 0x40, 0x02, ++0x41, 0xAF, 0xE0, 0xFF, 0x24, 0x79, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x90, 0x81, ++0x6C, 0xF0, 0xE0, 0xFE, 0x54, 0xF0, 0xC4, 0x54, 0x0F, 0xFD, 0x90, 0x81, 0x6B, 0xF0, 0xEE, 0x54, ++0x0F, 0xFE, 0xA3, 0xF0, 0x74, 0x7A, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x90, ++0x81, 0x6D, 0xF0, 0xFC, 0xEE, 0xFE, 0xEC, 0xFB, 0xEB, 0xFF, 0x90, 0x81, 0x72, 0xEE, 0xF0, 0xA3, ++0xEF, 0xF0, 0xED, 0x12, 0x45, 0x28, 0x68, 0x8B, 0x00, 0x68, 0xC2, 0x01, 0x69, 0x73, 0x02, 0x6A, ++0xA0, 0x03, 0x69, 0x8E, 0x04, 0x69, 0xAF, 0x05, 0x69, 0xAF, 0x06, 0x69, 0xAF, 0x07, 0x69, 0xAF, ++0x08, 0x6A, 0x33, 0x09, 0x6A, 0x69, 0x0A, 0x00, 0x00, 0x6A, 0xAF, 0x90, 0x81, 0x6A, 0xE0, 0xFD, ++0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x7B, 0x2D, 0xF5, 0x82, ++0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD, 0xED, 0xFF, 0x90, 0x81, 0x74, 0xEE, 0xF0, 0xFC, 0xA3, ++0xEF, 0xF0, 0x90, 0x81, 0x6D, 0xE0, 0xFF, 0x12, 0x2F, 0x96, 0x90, 0x81, 0x68, 0x74, 0x02, 0xF0, ++0x41, 0xA0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, ++0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, ++0xAB, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, ++0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, ++0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7D, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFF, 0xE4, ++0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, ++0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, ++0x7E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x18, ++0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x90, 0x81, ++0x6E, 0x12, 0x20, 0xCE, 0x90, 0x81, 0x6E, 0x12, 0x44, 0xD9, 0x90, 0x85, 0x96, 0x12, 0x20, 0xCE, ++0x90, 0x81, 0x72, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2E, 0xE4, 0x90, 0x81, 0x68, 0x74, 0x04, ++0xF0, 0x41, 0xA0, 0x90, 0x81, 0x6D, 0xE0, 0xFD, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, ++0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFB, 0xE4, 0xFF, 0x12, 0x30, 0xC7, 0x80, 0x19, 0x90, 0x81, ++0x6D, 0xE0, 0xFD, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, ++0xE0, 0xFB, 0xE4, 0xFF, 0x12, 0x30, 0x6A, 0x90, 0x81, 0x68, 0x74, 0x01, 0xF0, 0x41, 0xA0, 0x90, ++0x81, 0x68, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, ++0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, ++0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, ++0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, ++0x06, 0xC0, 0x07, 0x90, 0x81, 0x6C, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, ++0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x90, 0x81, 0x6E, 0x12, ++0x20, 0xCE, 0x90, 0x81, 0x6B, 0xE0, 0x24, 0xFB, 0xFF, 0xC0, 0x07, 0x90, 0x81, 0x6E, 0x12, 0x44, ++0xD9, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xCE, 0x90, 0x81, 0x6D, 0xE0, 0xFD, 0xD0, 0x07, 0x12, 0x55, ++0x1C, 0x80, 0x6D, 0x90, 0x81, 0x68, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF9, ++0xE4, 0x34, 0x81, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x01, 0x7B, 0xFE, 0x7A, ++0x80, 0x79, 0x33, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x6D, 0xE0, 0xFF, 0x90, 0x81, 0x6C, 0xE0, 0xFD, ++0xE4, 0x90, 0x81, 0xBC, 0xF0, 0x7B, 0x04, 0x80, 0x34, 0x90, 0x81, 0x68, 0x74, 0x04, 0xF0, 0x90, ++0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF9, 0xE4, 0x34, 0x81, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, ++0x75, 0x16, 0x04, 0x7B, 0xFE, 0x7A, 0x80, 0x79, 0x33, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x6D, 0xE0, ++0xFF, 0x90, 0x81, 0x6C, 0xE0, 0xFD, 0xE4, 0x90, 0x81, 0xBC, 0xF0, 0x7B, 0x06, 0x12, 0x63, 0xE1, ++0x90, 0x81, 0x68, 0xE0, 0x24, 0x02, 0xFF, 0x90, 0x81, 0x6A, 0xE0, 0x2F, 0xF0, 0x01, 0x17, 0x22, ++0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x80, 0x3D, ++0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x3E, 0xF0, 0x90, 0x00, ++0x02, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x3F, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, ++0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x40, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, ++0x05, 0xED, 0x2F, 0x90, 0x80, 0x41, 0xF0, 0x22, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0x30, ++0xE0, 0x26, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x38, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, ++0x81, 0x39, 0xF0, 0xEF, 0x54, 0xFE, 0xFF, 0xA3, 0xE0, 0x54, 0x01, 0x4F, 0xF0, 0x90, 0x00, 0x03, ++0x12, 0x1F, 0xBD, 0x90, 0x81, 0x3B, 0xF0, 0x22, 0x90, 0x81, 0x38, 0x74, 0x01, 0xF0, 0xA3, 0x74, ++0x05, 0xF0, 0xA3, 0xE0, 0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0x22, 0x12, 0x1F, ++0xA4, 0x90, 0x81, 0x3E, 0xF0, 0x90, 0x81, 0x3E, 0xE0, 0x90, 0x01, 0xE7, 0xF0, 0x22, 0x12, 0x1F, ++0xA4, 0x90, 0x81, 0x4A, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x4B, 0xF0, 0x22, ++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xFD, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, ++0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0xFD, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0xE0, ++0x60, 0x2D, 0xC3, 0x90, 0x82, 0x00, 0xE0, 0x94, 0xE8, 0x90, 0x81, 0xFF, 0xE0, 0x94, 0x03, 0x40, ++0x0B, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x80, 0xF0, 0x7F, 0x00, 0x80, 0x15, 0x90, 0x81, 0xFF, 0xE4, ++0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0x7F, 0x0A, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x80, 0xC5, 0x7F, ++0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xD1, ++0x12, 0x45, 0x1F, 0x90, 0x82, 0x0A, 0xE0, 0xFF, 0x04, 0xF0, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, ++0xFC, 0x7F, 0xAF, 0x7E, 0x01, 0x71, 0x60, 0xEF, 0x60, 0x3A, 0x90, 0x81, 0xD1, 0x12, 0x45, 0x16, ++0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x90, 0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xF5, 0x16, ++0x7B, 0x01, 0x7A, 0x01, 0x79, 0xA0, 0x12, 0x2B, 0xED, 0x90, 0x81, 0xD1, 0x12, 0x45, 0x16, 0x90, ++0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x90, 0x01, 0xAE, 0xF0, 0xA3, 0x74, 0xFF, 0xF0, 0x90, 0x01, 0xCB, ++0xE0, 0x64, 0x80, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, ++0xE4, 0xFF, 0x90, 0x80, 0xD9, 0xE0, 0xFE, 0x90, 0x80, 0xD8, 0xE0, 0xFD, 0xB5, 0x06, 0x04, 0x7E, ++0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x64, 0x01, 0x60, 0x32, 0x90, 0x01, 0xAF, 0xE0, 0x70, 0x13, ++0xED, 0x75, 0xF0, 0x0F, 0xA4, 0x24, 0x42, 0xF9, 0x74, 0x80, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0x71, ++0xB6, 0x7F, 0x01, 0xEF, 0x60, 0x16, 0x90, 0x80, 0xD8, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, ++0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0xD8, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0x8F, 0x0D, 0x22, 0x8F, 0x0E, 0x22, 0x22, 0x90, 0x01, 0x34, 0xE0, 0x55, 0x3D, 0xF5, 0x41, ++0xA3, 0xE0, 0x55, 0x3E, 0xF5, 0x42, 0xA3, 0xE0, 0x55, 0x3F, 0xF5, 0x43, 0xA3, 0xE0, 0x55, 0x40, ++0xF5, 0x44, 0x90, 0x01, 0x34, 0xE5, 0x41, 0xF0, 0xA3, 0xE5, 0x42, 0xF0, 0xA3, 0xE5, 0x43, 0xF0, ++0xA3, 0xE5, 0x44, 0xF0, 0x22, 0x90, 0x01, 0x3C, 0xE0, 0x55, 0x45, 0xF5, 0x49, 0xA3, 0xE0, 0x55, ++0x46, 0xF5, 0x4A, 0xA3, 0xE0, 0x55, 0x47, 0xF5, 0x4B, 0xA3, 0xE0, 0x55, 0x48, 0xF5, 0x4C, 0x90, ++0x01, 0x3C, 0xE5, 0x49, 0xF0, 0xA3, 0xE5, 0x4A, 0xF0, 0xA3, 0xE5, 0x4B, 0xF0, 0xA3, 0xE5, 0x4C, ++0xF0, 0x53, 0x91, 0xDF, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x05, 0xE4, 0xA3, 0xF0, 0xA3, ++0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x19, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x13, ++0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0x12, 0x4F, 0xF4, 0x90, 0x01, 0x57, ++0x74, 0x05, 0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x26, 0x90, 0x81, 0x27, 0xE0, ++0x60, 0x20, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, ++0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x03, 0x12, ++0x47, 0x2A, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0xB4, 0x01, 0x14, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x0E, ++0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x02, 0x80, 0x03, 0xD1, 0x7F, 0x22, 0x90, ++0x04, 0x1D, 0xE0, 0x70, 0x13, 0x90, 0x80, 0x3E, 0xE0, 0xFF, 0xE4, 0xFD, 0xB1, 0x69, 0x8E, 0x4E, ++0x8F, 0x4F, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, ++0x90, 0x82, 0x0E, 0xED, 0xF0, 0x90, 0x82, 0x0D, 0xEF, 0xF0, 0xE4, 0xFD, 0xFC, 0xF1, 0x37, 0x7C, ++0x00, 0xAD, 0x07, 0x90, 0x82, 0x0D, 0xE0, 0x90, 0x04, 0x25, 0xF0, 0x90, 0x82, 0x0E, 0xE0, 0x60, ++0x0E, 0x74, 0x0F, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0xAF, ++0x05, 0x74, 0x08, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x09, 0x2F, ++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF0, 0xF0, 0x74, 0x21, 0x2D, 0xF5, 0x82, ++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF7, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xD0, 0xD0, 0x92, ++0xAF, 0x22, 0x8F, 0x4E, 0xF1, 0x4B, 0xBF, 0x01, 0x18, 0x90, 0x80, 0x40, 0xE0, 0xFF, 0x7D, 0x01, ++0xB1, 0x69, 0xAD, 0x07, 0xAC, 0x06, 0xAF, 0x4E, 0x12, 0x4F, 0x82, 0x90, 0x04, 0x1F, 0x74, 0x20, ++0xF0, 0x22, 0x90, 0x06, 0xA9, 0xE0, 0x90, 0x81, 0x4C, 0xF0, 0xE0, 0xFD, 0x54, 0xC0, 0x70, 0x09, ++0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x80, 0x72, 0xED, 0x30, 0xE6, 0x4B, 0x90, 0x81, 0x27, ++0xE0, 0x64, 0x02, 0x70, 0x2A, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0xC3, 0x13, 0x20, 0xE0, 0x09, 0x90, ++0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x28, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x01, ++0x70, 0x2D, 0x90, 0x81, 0x2B, 0xE0, 0x44, 0x04, 0xF0, 0x7F, 0x01, 0xB1, 0xD2, 0x80, 0x20, 0x90, ++0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x04, ++0xB1, 0x4F, 0x80, 0x0B, 0xD1, 0x7F, 0x80, 0x07, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x90, ++0x81, 0x4C, 0xE0, 0x90, 0x81, 0x2B, 0x30, 0xE7, 0x11, 0x12, 0x4F, 0xF1, 0x90, 0x01, 0x57, 0x74, ++0x05, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x90, ++0x01, 0x5F, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x08, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, ++0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x5C, 0x7E, 0x01, 0x12, 0x50, ++0x05, 0x90, 0x01, 0x5F, 0x74, 0x05, 0xF0, 0x90, 0x06, 0x92, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, ++0xE0, 0x44, 0x10, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, 0x60, 0x0C, 0xE4, 0xFD, 0x7F, 0x0C, ++0x12, 0x47, 0x3D, 0xE4, 0xFF, 0x12, 0x4F, 0x0D, 0x22, 0xE4, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x06, ++0xA9, 0xE0, 0x90, 0x81, 0x4C, 0xF0, 0xE0, 0x54, 0xC0, 0x70, 0x0D, 0x90, 0x81, 0x2B, 0xE0, 0x54, ++0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x02, 0x47, 0x2A, 0x90, 0x81, 0x4C, 0xE0, 0x30, 0xE6, 0x21, 0x90, ++0x81, 0x27, 0xE0, 0x64, 0x01, 0x70, 0x20, 0x90, 0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, ++0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x04, 0xB1, 0x4F, 0x80, 0x0B, 0xD1, 0x7F, 0x80, 0x07, ++0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x81, 0x4C, 0xE0, 0x90, 0x81, 0x2B, 0x30, 0xE7, ++0x11, 0x12, 0x4F, 0xF1, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x04, ++0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0xE4, 0xFE, 0xEF, 0xC3, 0x13, 0xFD, 0xEF, 0x30, 0xE0, ++0x02, 0x7E, 0x80, 0x90, 0xFD, 0x10, 0xED, 0xF0, 0xAF, 0x06, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, ++0xC0, 0xD0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x1A, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x90, 0x60, 0x07, ++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE1, 0xE4, 0x7F, 0x00, ++0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x03, 0x12, ++0x73, 0xE1, 0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x03, 0x12, 0x49, 0xDD, 0x22, 0x90, 0x81, 0x27, ++0xE0, 0x60, 0x35, 0x90, 0x06, 0x92, 0xE0, 0x30, 0xE1, 0x24, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, ++0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x5C, 0x7E, 0x01, 0x12, 0x50, ++0x05, 0x90, 0x01, 0x5F, 0x74, 0x05, 0xF0, 0x90, 0x06, 0x92, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x81, ++0x24, 0xE0, 0x54, 0xEF, 0xF0, 0x12, 0x47, 0x2A, 0x22, 0x12, 0x71, 0x48, 0x90, 0x81, 0x4D, 0xEF, ++0xF0, 0x90, 0x81, 0x24, 0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x04, 0xE0, 0x54, 0xFE, ++0xF0, 0x90, 0x81, 0x4D, 0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x04, 0xE4, ++0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, 0x74, 0x80, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x30, 0xE0, 0x1A, ++0x90, 0x81, 0x32, 0xE4, 0xF0, 0xA3, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xA3, 0xE0, 0x90, 0x05, ++0x58, 0xF0, 0x90, 0x04, 0xEC, 0xE0, 0x54, 0xDD, 0xF0, 0x22, 0x90, 0x04, 0xEC, 0xE0, 0x44, 0x22, ++0xF0, 0x22, 0x90, 0x81, 0x4A, 0xE0, 0x60, 0x0F, 0xE4, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x01, ++0xF0, 0x90, 0x05, 0xFD, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0xC4, 0x13, 0x13, ++0x54, 0x03, 0x30, 0xE0, 0x27, 0xEF, 0x54, 0xBF, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x25, ++0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x10, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x01, 0xB9, ++0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x12, 0x47, 0x2A, 0xE4, 0xFF, 0x90, 0x81, ++0x45, 0xE0, 0x30, 0xE0, 0x48, 0x90, 0x81, 0x49, 0xE0, 0xFD, 0x60, 0x41, 0x74, 0x01, 0x7E, 0x00, ++0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x04, 0xE0, ++0xE0, 0xFB, 0xEF, 0x5B, 0x60, 0x06, 0xE4, 0x90, 0x81, 0x49, 0xF0, 0x22, 0x90, 0x81, 0x47, 0xE0, ++0xD3, 0x9D, 0x50, 0x10, 0x90, 0x01, 0xC7, 0x74, 0x10, 0xF0, 0x11, 0xBE, 0x90, 0x81, 0x45, 0xE0, ++0x54, 0xFE, 0xF0, 0x22, 0x12, 0x4F, 0x0B, 0x90, 0x81, 0x49, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x80, ++0x3C, 0xE0, 0x64, 0x02, 0x60, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x81, ++0x24, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x2C, 0xEF, 0x54, 0x7F, 0xF0, ++0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x25, 0x30, 0xE1, 0x06, 0xE0, 0x44, 0x02, 0xF0, 0x80, 0x0F, ++0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x04, 0xF0, 0x90, ++0x81, 0x27, 0xE0, 0x60, 0x03, 0x12, 0x47, 0x2A, 0x7F, 0x01, 0x01, 0x6E, 0xC3, 0xEE, 0x94, 0x01, ++0x40, 0x0A, 0x0D, 0xED, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xC3, 0xEE, 0x94, ++0x01, 0x40, 0x24, 0x90, 0xFD, 0x11, 0xE0, 0x6D, 0x70, 0x1A, 0x90, 0x01, 0x17, 0xE0, 0xB5, 0x05, ++0x0D, 0x90, 0x01, 0xE4, 0x74, 0x77, 0xF0, 0x90, 0xFD, 0x11, 0xE4, 0xF0, 0x80, 0x06, 0xED, 0x04, ++0x90, 0xFD, 0x11, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xE4, 0x90, 0x81, 0x4E, 0xF0, 0xA3, 0xF0, 0xA3, ++0xF0, 0x90, 0x00, 0x83, 0xE0, 0x90, 0x81, 0x4E, 0xF0, 0x90, 0x00, 0x83, 0xE0, 0xFE, 0x90, 0x81, ++0x4E, 0xE0, 0xFF, 0xB5, 0x06, 0x01, 0x22, 0xC3, 0x90, 0x81, 0x50, 0xE0, 0x94, 0x64, 0x90, 0x81, ++0x4F, 0xE0, 0x94, 0x00, 0x40, 0x0D, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x4E, ++0xE0, 0xFF, 0x22, 0x90, 0x81, 0x4F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0x80, 0xC2, 0x74, ++0x45, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, ++0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, ++0x12, 0xED, 0xF0, 0x90, 0x82, 0x11, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x70, 0xE0, 0xFF, 0x74, ++0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x47, 0xE0, ++0x5F, 0xFD, 0x7F, 0x47, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, ++0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x46, 0xE0, 0x4F, 0xFD, 0x7F, 0x46, ++0x12, 0x32, 0x1E, 0x90, 0x82, 0x12, 0xE0, 0x60, 0x18, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, ++0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x4F, 0x80, ++0x17, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, ++0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x5F, 0xFD, 0x7F, 0x45, 0x80, 0x7E, 0x90, 0x82, 0x11, ++0xE0, 0x24, 0xF8, 0xF0, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, ++0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x5F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, ++0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, ++0xFF, 0x90, 0x00, 0x43, 0xE0, 0x4F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x12, 0xE0, ++0x60, 0x1D, 0x90, 0x82, 0x11, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, ++0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x4F, 0xFD, 0x7F, 0x42, 0x80, 0x1C, 0x90, ++0x82, 0x11, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, ++0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x5F, 0xFD, 0x7F, 0x42, 0x12, 0x32, 0x1E, 0xD0, 0xD0, ++0x92, 0xAF, 0x22, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFB, 0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, ++0x81, 0x2B, 0xF0, 0x22, 0xEF, 0x24, 0xFE, 0x60, 0x0C, 0x04, 0x70, 0x28, 0x90, 0x81, 0x2D, 0x74, ++0x01, 0xF0, 0xA3, 0xF0, 0x22, 0xED, 0x70, 0x0A, 0x90, 0x81, 0x3B, 0xE0, 0x90, 0x81, 0x2D, 0xF0, ++0x80, 0x05, 0x90, 0x81, 0x2D, 0xED, 0xF0, 0x90, 0x81, 0x2D, 0xE0, 0xA3, 0xF0, 0x90, 0x81, 0x25, ++0xE0, 0x44, 0x08, 0xF0, 0x22, 0x12, 0x4E, 0xAB, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, ++0x74, 0x01, 0xF0, 0x80, 0x67, 0x90, 0x81, 0x2B, 0xE0, 0xFF, 0x54, 0x03, 0x60, 0x08, 0x90, 0x01, ++0xB8, 0x74, 0x02, 0xF0, 0x80, 0x56, 0x90, 0x81, 0x29, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50, 0x08, ++0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x44, 0xEF, 0x30, 0xE2, 0x08, 0x90, 0x01, 0xB8, 0x74, ++0x08, 0xF0, 0x80, 0x38, 0x90, 0x81, 0x2B, 0xE0, 0x30, 0xE4, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x10, ++0xF0, 0x80, 0x29, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x20, 0xE0, 0x08, 0x90, 0x01, ++0xB8, 0x74, 0x20, 0xF0, 0x80, 0x16, 0x90, 0x81, 0x3E, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, ++0x80, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, ++0x04, 0xF0, 0x7F, 0x00, 0x22, 0xEF, 0x60, 0x42, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x3A, ++0x90, 0x81, 0x25, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x05, 0x22, 0x74, 0x0F, 0xF0, 0x90, 0x06, 0x04, ++0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0xFF, 0x12, 0x4F, 0x0D, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x24, 0xE0, ++0x44, 0x40, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x06, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x01, ++0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F, ++0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x02, 0xF0, 0x90, 0x81, ++0x23, 0xF0, 0x22, 0x12, 0x54, 0x65, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x23, 0xF0, ++0x22, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x11, 0xEF, 0x54, 0xFB, ++0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x42, 0x80, 0x3D, 0x90, 0x81, ++0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x30, 0xE0, 0xFF, ++0xB4, 0x01, 0x02, 0x80, 0x04, 0xEF, 0xB4, 0x02, 0x06, 0x90, 0x05, 0x58, 0xE0, 0x04, 0xF0, 0x90, ++0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0F, 0x90, 0x80, 0xDE, 0xE0, ++0xB4, 0x01, 0x0B, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x47, 0x2A, 0x22, 0x22, ++0x90, 0x05, 0x2B, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x05, 0x22, 0x74, ++0xFF, 0xF0, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, 0x22, ++0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x12, 0x49, 0xDD, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, ++0x22, 0x12, 0x49, 0xE3, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F, ++0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0xAE, ++0x07, 0x12, 0x51, 0x73, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x60, 0x0A, 0xAF, ++0x06, 0x7D, 0x01, 0x12, 0x47, 0x3D, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x90, 0x01, 0x57, 0xE0, ++0x60, 0x48, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, ++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0C, 0xEF, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, ++0xF0, 0x22, 0x90, 0x81, 0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90, ++0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0E, 0x90, 0x80, 0xDE, 0xE0, ++0xB4, 0x01, 0x07, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x90, 0x80, 0x3F, 0xE0, 0xFF, ++0x7D, 0x01, 0x12, 0x6D, 0x69, 0x8E, 0x54, 0x8F, 0x55, 0xAD, 0x55, 0xAC, 0x54, 0xAF, 0x53, 0x12, ++0x4F, 0x82, 0xAF, 0x55, 0xAE, 0x54, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F, 0xFD, 0xAC, 0x07, 0x74, ++0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, 0xF0, 0x74, 0x11, 0x2C, ++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, 0x07, 0x74, 0x16, 0x2C, ++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, 0x15, 0x2C, 0xF5, 0x82, ++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, 0x06, 0x2C, 0xF5, 0x82, ++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53, 0xE4, 0xF0, 0x90, 0x04, ++0x52, 0xF0, 0x90, 0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74, 0xFD, 0xF0, 0x74, 0x14, ++0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, 0xFD, 0x74, 0x14, 0x2F, ++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0xAB, 0x07, 0xAA, 0x06, 0xED, 0x2B, ++0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90, 0x80, 0xDB, 0xE0, 0x9B, 0x90, 0x80, 0xDA, 0xE0, 0x9A, 0x50, ++0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0xDA, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0xEB, 0x9F, ++0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x74, 0x00, 0x2F, 0xF5, 0x82, ++0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, ++0x81, 0x42, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x0A, 0x90, 0x00, 0x01, ++0x12, 0x1F, 0xBD, 0x90, 0x81, 0x43, 0xF0, 0x22, 0x90, 0x81, 0x45, 0xE0, 0x30, 0xE0, 0x2D, 0x90, ++0x81, 0x48, 0xE0, 0x04, 0xF0, 0xE0, 0xFF, 0x90, 0x81, 0x46, 0xE0, 0xB5, 0x07, 0x1E, 0x90, 0x06, ++0x92, 0xE0, 0x54, 0x1C, 0x70, 0x0B, 0x12, 0x4F, 0x0B, 0x90, 0x81, 0x49, 0xE0, 0x04, 0xF0, 0x80, ++0x06, 0x90, 0x06, 0x92, 0x74, 0x1C, 0xF0, 0xE4, 0x90, 0x81, 0x48, 0xF0, 0x22, 0x00, 0xBB, 0x8E, ++}; +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h +new file mode 100644 +index 00000000..2328ec3c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h +@@ -0,0 +1,29 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++#ifndef __INC_HAL8188E_FW_IMG_H ++#define __INC_HAL8188E_FW_IMG_H ++ ++//V10(1641) ++#define Rtl8188EFWImgArrayLength 13904 ++ ++extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength]; ++ ++#endif //__INC_HAL8188E_FW_IMG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c +new file mode 100644 +index 00000000..972f45ee +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c +@@ -0,0 +1,1108 @@ ++/*++ ++Copyright (c) Realtek Semiconductor Corp. All rights reserved. ++ ++Module Name: ++ RateAdaptive.c ++ ++Abstract: ++ Implement Rate Adaptive functions for common operations. ++ ++Major Change History: ++ When Who What ++ ---------- --------------- ------------------------------- ++ 2011-08-12 Page Create. ++ ++--*/ ++#include "../odm_precomp.h" ++ ++//#if( DM_ODM_SUPPORT_TYPE == ODM_MP) ++//#include "Mp_Precomp.h" ++//#endif ++ ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++// Rate adaptive parameters ++ ++ ++static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 ++ {6,5,4,3,0,4},//86 , idx=1 ++ {6,5,4,2,0,4},//81 , idx=2 ++ {8,7,6,4,0,6},//75 , idx=3 ++ {10,9,8,6,0,8},//71 , idx=4 ++ {10,9,8,4,0,8},//66 , idx=5 ++ {10,9,8,2,0,8},//62 , idx=6 ++ {10,9,8,0,0,8},//59 , idx=7 ++ {18,17,16,8,0,16},//53 , idx=8 ++ {26,25,24,16,0,24},//50 , idx=9 ++ {34,33,32,24,0,32},//47 , idx=0x0a ++ //{34,33,32,16,0,32},//43 , idx=0x0b ++ //{34,33,32,8,0,32},//40 , idx=0x0c ++ //{34,33,28,8,0,32},//37 , idx=0x0d ++ //{34,33,20,8,0,32},//32 , idx=0x0e ++ //{34,32,24,8,0,32},//26 , idx=0x0f ++ //{49,48,32,16,0,48},//20 , idx=0x10 ++ //{49,48,24,0,0,48},//17 , idx=0x11 ++ //{49,47,16,16,0,48},//15 , idx=0x12 ++ //{49,44,16,16,0,48},//12 , idx=0x13 ++ //{49,40,16,0,0,48},//9 , idx=0x14 ++ {34,31,28,20,0,32},//43 , idx=0x0b ++ {34,31,27,18,0,32},//40 , idx=0x0c ++ {34,31,26,16,0,32},//37 , idx=0x0d ++ {34,30,22,16,0,32},//32 , idx=0x0e ++ {34,30,24,16,0,32},//26 , idx=0x0f ++ {49,46,40,16,0,48},//20 , idx=0x10 ++ {49,45,32,0,0,48},//17 , idx=0x11 ++ {49,45,22,18,0,48},//15 , idx=0x12 ++ {49,40,24,16,0,48},//12 , idx=0x13 ++ {49,32,18,12,0,48},//9 , idx=0x14 ++ {49,22,18,14,0,48},//6 , idx=0x15 ++ {49,16,16,0,0,48}};//3 //3, idx=0x16 ++ ++static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up ++ ++static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; ++ ++#if 0 ++static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH ++ 4,4,4,4,6,0x0a,0x0b,0x0d, ++ 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 ++ {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH ++ 4,4,4,4,6,0x0a,0x0b,0x0d, ++ 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 ++ {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH ++ 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, ++ 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; ++ ++static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, ++ 0,0,0,0,0,0x24,0x26,0x2a, ++ 0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f, ++ 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; ++#else ++ ++// wilson modify ++static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH ++ 4,4,4,4,6,0x0a,0x0b,0x0d, ++ 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 ++ {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SSTH ++ 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, ++ 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; ++ ++static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, ++ 0,0,0,0,0,0x24,0x26,0x2a, ++ 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, ++ 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; ++ ++#endif ++ ++/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, ++ 0,0,0,0,0,0x24,0x26,0x2a, ++ 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, ++ 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ ++static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, ++ 24,36,48,72,96,144,192,216, ++ 60,80,100,160,240,400,560,640, ++ 300,320,480,720,1000,1200,1600,2000}; ++static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, ++ 12,18,24,36,48,72,96,108, ++ 30,40,50,80,120,200,280,320, ++ 150,160,240,360,500,600,800,1000}; ++static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2, ++ 2,2,3,3,4,4,5,7, ++ 4,4,7,10,10,12,12,18, ++ 5,7,7,8,11,18,36,60}; // 0329 // 1207 ++#if 0 ++static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, ++ 30,30,25,25,20,15,15,10, ++ 30,25,25,20,15,10,10,10, ++ 30,25,25,20,15,10,10,10}; ++#endif ++ ++static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1, ++ 1,2,3,4,5,6,7,8, ++ 1,2,3,4,5,6,7,8, ++ 5,6,7,8,9,10,11,12}; ++ ++ ++static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode ++ 0x0f8ff010, // 1: 40M GN mode ++ 0x0f8ff005, // 2: BN mode/ 40M BGN mode ++ 0x0f8ff000, // 3: N mode ++ 0x00000ff5, // 4: BG mode ++ 0x00000ff0, // 5: G mode ++ 0x0000000d, // 6: B mode ++ 0, // 7: ++ 0, // 8: ++ 0, // 9: ++ 0, // 10: ++ 0, // 11: ++ 0, // 12: ++ 0, // 13: ++ 0, // 14: ++ 0, // 15: ++ ++ }; ++static u1Byte PendingForRateUpFail[5]={2,10,24,40,60}; ++static u2Byte DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms ++ ++// End Rate adaptive parameters ++ ++static void ++odm_SetTxRPTTiming_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN PODM_RA_INFO_T pRaInfo, ++ IN u1Byte extend ++ ) ++{ ++ u1Byte idx = 0; ++ ++ for(idx=0; idx<5; idx++) ++ if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) ++ break; ++ ++ if (extend==0) // back to default timing ++ idx=0; //200ms ++ else if (extend==1) {// increase the timing ++ idx+=1; ++ if (idx>5) ++ idx=5; ++ } ++ else if (extend==2) {// decrease the timing ++ if(idx!=0) ++ idx-=1; ++ } ++ pRaInfo->RptTime=DynamicTxRPTTiming[idx]; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime)); ++} ++ ++static int ++odm_RateDown_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ ++ u1Byte RateID, LowestRate, HighestRate; ++ u1Byte i; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); ++ if(NULL == pRaInfo) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); ++ return -1; ++ } ++ RateID = pRaInfo->PreRate; ++ LowestRate = pRaInfo->LowestRate; ++ HighestRate = pRaInfo->HighestRate; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", ++ RateID, LowestRate, HighestRate, pRaInfo->RateSGI)); ++ if (RateID > HighestRate) ++ { ++ RateID=HighestRate; ++ } ++ else if(pRaInfo->RateSGI) ++ { ++ pRaInfo->RateSGI=0; ++ } ++ else if (RateID > LowestRate) ++ { ++ if (RateID > 0) ++ { ++ for (i=RateID-1; i>LowestRate;i--) ++ { ++ if (pRaInfo->RAUseRate & BIT(i)) ++ { ++ RateID=i; ++ goto RateDownFinish; ++ ++ } ++ } ++ } ++ } ++ else if (RateID <= LowestRate) ++ { ++ RateID = LowestRate; ++ } ++RateDownFinish: ++ if (pRaInfo->RAWaitingCounter==1){ ++ pRaInfo->RAWaitingCounter+=1; ++ pRaInfo->RAPendingCounter+=1; ++ } ++ else if(pRaInfo->RAWaitingCounter==0){ ++ } ++ else{ ++ pRaInfo->RAWaitingCounter=0; ++ pRaInfo->RAPendingCounter=0; ++ } ++ ++ if(pRaInfo->RAPendingCounter>=4) ++ pRaInfo->RAPendingCounter=4; ++ ++ pRaInfo->DecisionRate=RateID; ++ odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 2); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, RPT Timing default\n")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDown_8188E() \n")); ++ return 0; ++} ++ ++static int ++odm_RateUp_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ ++ u1Byte RateID, HighestRate; ++ u1Byte i; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n")); ++ if(NULL == pRaInfo) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); ++ return -1; ++ } ++ RateID = pRaInfo->PreRate; ++ HighestRate = pRaInfo->HighestRate; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" RateID=%d HighestRate=%d\n", ++ RateID, HighestRate)); ++ if (pRaInfo->RAWaitingCounter==1){ ++ pRaInfo->RAWaitingCounter=0; ++ pRaInfo->RAPendingCounter=0; ++ } ++ else if (pRaInfo->RAWaitingCounter>1){ ++ pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; ++ goto RateUpfinish; ++ } ++ odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E():Decrease RPT Timing\n")); ++ ++ if (RateID < HighestRate) ++ { ++ for (i=RateID+1; i<=HighestRate; i++) ++ { ++ if (pRaInfo->RAUseRate & BIT(i)) ++ { ++ RateID=i; ++ goto RateUpfinish; ++ } ++ } ++ } ++ else if(RateID == HighestRate) ++ { ++ if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) ++ pRaInfo->RateSGI = 1; ++ else if((pRaInfo->SGIEnable) !=1 ) ++ pRaInfo->RateSGI = 0; ++ } ++ else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) ++ { ++ RateID = HighestRate; ++ ++ } ++RateUpfinish: ++ //if(pRaInfo->RAWaitingCounter==10) ++ if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) ++ pRaInfo->RAWaitingCounter=0; ++ else ++ pRaInfo->RAWaitingCounter++; ++ ++ pRaInfo->DecisionRate=RateID; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateUp_8188E() \n")); ++ return 0; ++} ++ ++static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){ ++ u1Byte RateID; ++ RateID=pRaInfo->DecisionRate; ++ pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; ++ pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; ++} ++ ++static void ++odm_RateDecision_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ ++ u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; ++ //u4Byte pool_retry; ++ static u1Byte DynamicTxRPTTimingCounter=0; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); ++ ++ if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits ++ { ++ if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ ++ pRaInfo->RAWaitingCounter=0; ++ pRaInfo->RAPendingCounter=0; ++ } ++ // Start RA decision ++ if (pRaInfo->PreRate > pRaInfo->HighestRate) ++ RateID = pRaInfo->HighestRate; ++ else ++ RateID = pRaInfo->PreRate; ++ if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) ++ RtyPtID=0; ++ else ++ RtyPtID=1; ++ PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" NscDown init is %d\n", pRaInfo->NscDown)); ++ //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; ++ pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; ++ pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; ++ pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; ++ pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; ++ pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" NscDown is %d, total*penalty[5] is %d\n", ++ pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); ++ if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) ++ pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; ++ else ++ pRaInfo->NscDown=0; ++ ++ // rate up ++ PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" NscUp init is %d\n", pRaInfo->NscUp)); ++ pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; ++ pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; ++ pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; ++ pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; ++ pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ ("NscUp is %d, total*up[5] is %d\n", ++ pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); ++ if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) ++ pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; ++ else ++ pRaInfo->NscUp = 0; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE|ODM_COMP_INIT, ODM_DBG_LOUD, ++ (" RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d SGI=%d\n", ++ pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); ++ if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) ++ odm_RateDown_8188E(pDM_Odm,pRaInfo); ++ //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) ++ odm_RateUp_8188E(pDM_Odm,pRaInfo); ++ ++ if(pRaInfo->DecisionRate > pRaInfo->HighestRate) ++ pRaInfo->DecisionRate = pRaInfo->HighestRate; ++ ++ if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) ++ DynamicTxRPTTimingCounter+=1; ++ else ++ DynamicTxRPTTimingCounter=0; ++ ++ if (DynamicTxRPTTimingCounter>=4) { ++ odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 1); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<=====Rate don't change 4 times, Extend RPT Timing\n")); ++ DynamicTxRPTTimingCounter=0; ++ } ++ ++ pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 ++ ++ odm_ResetRaCounter_8188E( pRaInfo); ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDecision_8188E() \n")); ++} ++ ++static int ++odm_ARFBRefresh_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ // Wilson 2011/10/26 ++ u4Byte MaskFromReg; ++ s1Byte i; ++ ++ switch(pRaInfo->RateID){ ++ case RATR_INX_WIRELESS_NGB: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; ++ break; ++ case RATR_INX_WIRELESS_NG: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; ++ break; ++ case RATR_INX_WIRELESS_NB: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; ++ break; ++ case RATR_INX_WIRELESS_N: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; ++ break; ++ case RATR_INX_WIRELESS_GB: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; ++ break; ++ case RATR_INX_WIRELESS_G: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; ++ break; ++ case RATR_INX_WIRELESS_B: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; ++ break; ++ case 12: ++ MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR0); ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; ++ break; ++ case 13: ++ MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR1); ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; ++ break; ++ case 14: ++ MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR2); ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; ++ break; ++ case 15: ++ MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR3); ++ pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; ++ break; ++ ++ default: ++ pRaInfo->RAUseRate=(pRaInfo->RateMask); ++ break; ++ } ++ // Highest rate ++ if (pRaInfo->RAUseRate){ ++ for (i=RATESIZE;i>=0;i--) ++ { ++ if((pRaInfo->RAUseRate)&BIT(i)){ ++ pRaInfo->HighestRate=i; ++ break; ++ } ++ } ++ } ++ else{ ++ pRaInfo->HighestRate=0; ++ } ++ // Lowest rate ++ if (pRaInfo->RAUseRate){ ++ for (i=0;iRAUseRate)&BIT(i)) ++ { ++ pRaInfo->LowestRate=i; ++ break; ++ } ++ } ++ } ++ else{ ++ pRaInfo->LowestRate=0; ++ } ++ ++#if POWER_TRAINING_ACTIVE == 1 ++ if (pRaInfo->HighestRate >0x13) ++ pRaInfo->PTModeSS=3; ++ else if(pRaInfo->HighestRate >0x0b) ++ pRaInfo->PTModeSS=2; ++ else if(pRaInfo->HighestRate >0x0b) ++ pRaInfo->PTModeSS=1; ++ else ++ pRaInfo->PTModeSS=0; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ ("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS)); ++ ++#endif ++ ++ if(pRaInfo->DecisionRate > pRaInfo->HighestRate) ++ pRaInfo->DecisionRate = pRaInfo->HighestRate; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ ("ODM_ARFBRefresh_8188E(): RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d,DecisionRate=%d \n", ++ pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate,pRaInfo->DecisionRate)); ++ return 0; ++} ++ ++#if POWER_TRAINING_ACTIVE == 1 ++static void ++odm_PTTryState_8188E( ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ ++ pRaInfo->PTTryState=0; ++ switch (pRaInfo->PTModeSS) ++ { ++ case 3: ++ if (pRaInfo->DecisionRate>=0x19) ++ pRaInfo->PTTryState=1; ++ break; ++ case 2: ++ if (pRaInfo->DecisionRate>=0x11) ++ pRaInfo->PTTryState=1; ++ break; ++ case 1: ++ if (pRaInfo->DecisionRate>=0x0a) ++ pRaInfo->PTTryState=1; ++ break; ++ case 0: ++ if (pRaInfo->DecisionRate>=0x03) ++ pRaInfo->PTTryState=1; ++ break; ++ default: ++ pRaInfo->PTTryState=0; ++ } ++ ++ if (pRaInfo->RssiStaRA<48) ++ { ++ pRaInfo->PTStage=0; ++ } ++ else if (pRaInfo->PTTryState==1) ++ { ++ if ((pRaInfo->PTStopCount>=10)||(pRaInfo->PTPreRssi>pRaInfo->RssiStaRA+5) ++ ||(pRaInfo->PTPreRssiRssiStaRA-5)||(pRaInfo->DecisionRate!=pRaInfo->PTPreRate)) ++ { ++ if (pRaInfo->PTStage==0) ++ pRaInfo->PTStage=1; ++ else if(pRaInfo->PTStage==1) ++ pRaInfo->PTStage=3; ++ else ++ pRaInfo->PTStage=5; ++ ++ pRaInfo->PTPreRssi=pRaInfo->RssiStaRA; ++ pRaInfo->PTStopCount=0; ++ ++ } ++ else{ ++ pRaInfo->RAstage=0; ++ pRaInfo->PTStopCount++; ++ } ++ } ++ else{ ++ pRaInfo->PTStage=0; ++ pRaInfo->RAstage=0; ++ } ++ pRaInfo->PTPreRate=pRaInfo->DecisionRate; ++} ++ ++static void ++odm_PTDecision_8188E( ++ IN PODM_RA_INFO_T pRaInfo ++ ) ++{ ++ u1Byte stage_BUF; ++ u1Byte j; ++ u1Byte temp_stage; ++ u4Byte numsc; ++ u4Byte num_total; ++ u1Byte stage_id; ++ ++ stage_BUF=pRaInfo->PTStage; ++ numsc = 0; ++ num_total= pRaInfo->TOTAL* PT_PENALTY[5]; ++ for(j=0;j<=4;j++) ++ { ++ numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; ++ if(numsc>num_total) ++ break; ++ } ++ ++ j=j>>1; ++ temp_stage= (pRaInfo->PTStage +1)>>1; ++ if (temp_stage>j) ++ stage_id=temp_stage-j; ++ else ++ stage_id=0; ++ ++ pRaInfo->PTSmoothFactor=(pRaInfo->PTSmoothFactor>>1) + (pRaInfo->PTSmoothFactor>>2) + stage_id*16+2; ++ if (pRaInfo->PTSmoothFactor>192) ++ pRaInfo->PTSmoothFactor=192; ++ stage_id =pRaInfo->PTSmoothFactor>>6; ++ temp_stage=stage_id*2; ++ if (temp_stage!=0) ++ temp_stage-=1; ++ if (pRaInfo->DROP>3) ++ temp_stage=0; ++ pRaInfo->PTStage=temp_stage; ++ ++} ++#endif ++ ++static VOID ++odm_RATxRPTTimerSetting( ++ IN PDM_ODM_T pDM_Odm, ++ IN u2Byte minRptTime ++) ++{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n")); ++ ++ ++ if(pDM_Odm->CurrminRptTime != minRptTime){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ (" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime)); ++ #if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP)) ++ ODM_RA_Set_TxRPT_Time(pDM_Odm,minRptTime); ++ #else ++ rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime); ++ #endif ++ pDM_Odm->CurrminRptTime = minRptTime; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" <=====odm_RATxRPTTimerSetting()\n")); ++} ++ ++ ++VOID ++ODM_RASupport_Init( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); ++ ++ // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! ++ if (pDM_Odm->SupportICType == ODM_RTL8188E) ++ pDM_Odm->RaSupport88E = TRUE; ++ ++} ++ ++ ++ ++int ++ODM_RAInfo_Init( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; ++ #if 1 ++ u1Byte WirelessMode=0xFF; //invalid value ++ u1Byte max_rate_idx = 0x13; //MCS7 ++ if(pDM_Odm->pWirelessMode!=NULL){ ++ WirelessMode=*(pDM_Odm->pWirelessMode); ++ } ++ ++ if(WirelessMode != 0xFF ){ ++ if(WirelessMode & ODM_WM_N24G) ++ max_rate_idx = 0x13; ++ else if(WirelessMode & ODM_WM_G) ++ max_rate_idx = 0x0b; ++ else if(WirelessMode & ODM_WM_B) ++ max_rate_idx = 0x03; ++ } ++ ++ //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", ++ WirelessMode,max_rate_idx)); ++ ++ pRaInfo->DecisionRate = max_rate_idx; ++ pRaInfo->PreRate = max_rate_idx; ++ pRaInfo->HighestRate=max_rate_idx; ++ #else ++ pRaInfo->DecisionRate = 0x13; ++ pRaInfo->PreRate = 0x13; ++ pRaInfo->HighestRate= 0x13; ++ #endif ++ pRaInfo->LowestRate=0; ++ pRaInfo->RateID=0; ++ pRaInfo->RateMask=0xffffffff; ++ pRaInfo->RssiStaRA=0; ++ pRaInfo->PreRssiStaRA=0; ++ pRaInfo->SGIEnable=0; ++ pRaInfo->RAUseRate=0xffffffff; ++ pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; ++ pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; ++ pRaInfo->RateSGI=0; ++ pRaInfo->Active=1; //Active is not used at present. by page, 110819 ++ pRaInfo->RptTime = 0x927c; ++ pRaInfo->DROP=0; ++ pRaInfo->DROP1=0; ++ pRaInfo->RTY[0]=0; ++ pRaInfo->RTY[1]=0; ++ pRaInfo->RTY[2]=0; ++ pRaInfo->RTY[3]=0; ++ pRaInfo->RTY[4]=0; ++ pRaInfo->TOTAL=0; ++ pRaInfo->RAWaitingCounter=0; ++ pRaInfo->RAPendingCounter=0; ++#if POWER_TRAINING_ACTIVE == 1 ++ pRaInfo->PTActive=1; // Active when this STA is use ++ pRaInfo->PTTryState=0; ++ pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS ++ pRaInfo->PTSmoothFactor=192; ++ pRaInfo->PTStopCount=0; ++ pRaInfo->PTPreRate=0; ++ pRaInfo->PTPreRssi=0; ++ pRaInfo->PTModeSS=0; ++ pRaInfo->RAstage=0; ++#endif ++ return 0; ++} ++ ++int ++ODM_RAInfo_Init_all( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u1Byte MacID = 0; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n")); ++ pDM_Odm->CurrminRptTime = 0; ++ ++ for(MacID=0; MacID= ASSOCIATE_ENTRY_NUM)) ++ return 0; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ ("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI)); ++ return pDM_Odm->RAInfo[MacID].RateSGI; ++} ++ ++u1Byte ++ODM_RA_GetDecisionRate_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ u1Byte DecisionRate = 0; ++ ++ if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) ++ return 0; ++ DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" MacID=%d DecisionRate=0x%x\n", MacID, DecisionRate)); ++ return DecisionRate; ++} ++ ++u1Byte ++ODM_RA_GetHwPwrStatus_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ u1Byte PTStage = 5; ++ if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) ++ return 0; ++ PTStage = (pDM_Odm->RAInfo[MacID].PTStage); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ ("MacID=%d PTStage=0x%x\n", MacID, PTStage)); ++ return PTStage; ++} ++ ++VOID ++ODM_RA_UpdateRateInfo_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte RateID, ++ IN u4Byte RateMask, ++ IN u1Byte SGIEnable ++ ) ++{ ++ PODM_RA_INFO_T pRaInfo = NULL; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ ("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n", ++ MacID, RateID, RateMask, SGIEnable)); ++ if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) ++ return; ++ ++ pRaInfo = &(pDM_Odm->RAInfo[MacID]); ++ pRaInfo->RateID = RateID; ++ pRaInfo->RateMask = RateMask; ++ pRaInfo->SGIEnable = SGIEnable; ++ odm_ARFBRefresh_8188E(pDM_Odm, pRaInfo); ++} ++ ++VOID ++ODM_RA_SetRSSI_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte Rssi ++ ) ++{ ++ PODM_RA_INFO_T pRaInfo = NULL; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ++ (" MacID=%d Rssi=%d\n", MacID, Rssi)); ++ if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) ++ return; ++ ++ pRaInfo = &(pDM_Odm->RAInfo[MacID]); ++ pRaInfo->RssiStaRA = Rssi; ++} ++ ++VOID ++ODM_RA_Set_TxRPT_Time( ++ IN PDM_ODM_T pDM_Odm, ++ IN u2Byte minRptTime ++ ) ++{ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) ++ if (minRptTime != 0xffff) ++#endif ++ ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); ++} ++ ++ ++VOID ++ODM_RA_TxRPT2Handle_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte TxRPT_Buf, ++ IN u2Byte TxRPT_Len, ++ IN u4Byte MacIDValidEntry0, ++ IN u4Byte MacIDValidEntry1 ++ ) ++{ ++ PODM_RA_INFO_T pRAInfo = NULL; ++ u1Byte MacId = 0; ++ pu1Byte pBuffer = NULL; ++ u4Byte valid = 0, ItemNum = 0; ++ u2Byte minRptTime = 0x927c; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n", ++ MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len)); ++ ++ ItemNum = TxRPT_Len >> 3; ++ pBuffer = TxRPT_Buf; ++ ++ do ++ { ++ if(MacId >= ASSOCIATE_ENTRY_NUM) ++ valid = 0; ++ else if(MacId >= 32) ++ valid = (1<<(MacId-32)) & MacIDValidEntry1; ++ else ++ valid = (1<RAInfo[MacId]); ++ if(valid) ++ { ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ pRAInfo->RTY[0] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer); ++ pRAInfo->RTY[1] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_1(pBuffer); ++ pRAInfo->RTY[2] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_2(pBuffer); ++ pRAInfo->RTY[3] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_3(pBuffer); ++ pRAInfo->RTY[4] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_4(pBuffer); ++ pRAInfo->DROP = (u2Byte)GET_TX_REPORT_TYPE1_DROP_0(pBuffer); ++ pRAInfo->DROP1= (u2Byte)GET_TX_REPORT_TYPE1_DROP_1(pBuffer); ++#else ++ pRAInfo->RTY[0] = (unsigned short)(pBuffer[1] << 8 | pBuffer[0]); ++ pRAInfo->RTY[1] = pBuffer[2]; ++ pRAInfo->RTY[2] = pBuffer[3]; ++ pRAInfo->RTY[3] = pBuffer[4]; ++ pRAInfo->RTY[4] = pBuffer[5]; ++ pRAInfo->DROP = pBuffer[6]; ++ pRAInfo->DROP1= pBuffer[7]; ++#endif ++ pRAInfo->TOTAL = pRAInfo->RTY[0] + \ ++ pRAInfo->RTY[1] + \ ++ pRAInfo->RTY[2] + \ ++ pRAInfo->RTY[3] + \ ++ pRAInfo->RTY[4] + \ ++ pRAInfo->DROP; ++ if(pRAInfo->TOTAL != 0) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ++ ("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", ++ MacId, ++ pRAInfo->TOTAL, ++ pRAInfo->RTY[0], ++ pRAInfo->RTY[1], ++ pRAInfo->RTY[2], ++ pRAInfo->RTY[3], ++ pRAInfo->RTY[4], ++ pRAInfo->DROP, ++ MacIDValidEntry0 , ++ MacIDValidEntry1)); ++#if POWER_TRAINING_ACTIVE == 1 ++ if (pRAInfo->PTActive){ ++ if(pRAInfo->RAstage<5){ ++ odm_RateDecision_8188E(pDM_Odm,pRAInfo); ++ } ++ else if(pRAInfo->RAstage==5){ // Power training try state ++ odm_PTTryState_8188E(pRAInfo); ++ } ++ else {// RAstage==6 ++ odm_PTDecision_8188E(pRAInfo); ++ } ++ ++ // Stage_RA counter ++ if (pRAInfo->RAstage<=5) ++ pRAInfo->RAstage++; ++ else ++ pRAInfo->RAstage=0; ++ } ++ else{ ++ odm_RateDecision_8188E(pDM_Odm,pRAInfo); ++ } ++#else ++ odm_RateDecision_8188E(pDM_Odm, pRAInfo); ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ extern void RTL8188E_SetStationTxRateInfo(PDM_ODM_T, PODM_RA_INFO_T, int); ++ RTL8188E_SetStationTxRateInfo(pDM_Odm, pRAInfo, MacId); ++#ifdef DETECT_STA_EXISTANCE ++ void RTL8188E_DetectSTAExistance(PDM_ODM_T pDM_Odm, PODM_RA_INFO_T pRAInfo, int MacID); ++ RTL8188E_DetectSTAExistance(pDM_Odm, pRAInfo, MacId); ++#endif ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ++ ("macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x RateID=%d SGI=%d\n", ++ MacId, ++ pRAInfo->RTY[0], ++ pRAInfo->RTY[1], ++ pRAInfo->RTY[2], ++ pRAInfo->RTY[3], ++ pRAInfo->RTY[4], ++ pRAInfo->DROP, ++ MacIDValidEntry0, ++ pRAInfo->DecisionRate, ++ pRAInfo->RateSGI)); ++ } ++ else ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n")); ++ } ++ ++ if(minRptTime > pRAInfo->RptTime) ++ minRptTime = pRAInfo->RptTime; ++ ++ pBuffer += TX_RPT2_ITEM_SIZE; ++ MacId++; ++ }while(MacId < ItemNum); ++ ++ odm_RATxRPTTimerSetting(pDM_Odm,minRptTime); ++ ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<===== ODM_RA_TxRPT2Handle_8188E()\n")); ++} ++ ++#else ++ ++static VOID ++odm_RATxRPTTimerSetting( ++ IN PDM_ODM_T pDM_Odm, ++ IN u2Byte minRptTime ++) ++{ ++ return; ++} ++ ++ ++VOID ++ODM_RASupport_Init( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ return; ++} ++ ++int ++ODM_RAInfo_Init( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ return 0; ++} ++ ++int ++ODM_RAInfo_Init_all( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ return 0; ++} ++ ++u1Byte ++ODM_RA_GetShortGI_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ return 0; ++} ++ ++u1Byte ++ODM_RA_GetDecisionRate_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ return 0; ++} ++u1Byte ++ODM_RA_GetHwPwrStatus_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ) ++{ ++ return 0; ++} ++ ++VOID ++ODM_RA_UpdateRateInfo_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte RateID, ++ IN u4Byte RateMask, ++ IN u1Byte SGIEnable ++ ) ++{ ++ return; ++} ++ ++VOID ++ODM_RA_SetRSSI_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte Rssi ++ ) ++{ ++ return; ++} ++ ++VOID ++ODM_RA_Set_TxRPT_Time( ++ IN PDM_ODM_T pDM_Odm, ++ IN u2Byte minRptTime ++ ) ++{ ++ return; ++} ++ ++VOID ++ODM_RA_TxRPT2Handle_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte TxRPT_Buf, ++ IN u2Byte TxRPT_Len, ++ IN u4Byte MacIDValidEntry0, ++ IN u4Byte MacIDValidEntry1 ++ ) ++{ ++ return; ++} ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h +new file mode 100644 +index 00000000..e7c1e125 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h +@@ -0,0 +1,108 @@ ++#ifndef __INC_RA_H ++#define __INC_RA_H ++/*++ ++Copyright (c) Realtek Semiconductor Corp. All rights reserved. ++ ++Module Name: ++ RateAdaptive.h ++ ++Abstract: ++ Prototype of RA and related data structure. ++ ++Major Change History: ++ When Who What ++ ---------- --------------- ------------------------------- ++ 2011-08-12 Page Create. ++--*/ ++ ++// Rate adaptive define ++#define PERENTRY 23 ++#define RETRYSIZE 5 ++#define RATESIZE 28 ++#define TX_RPT2_ITEM_SIZE 8 ++ ++#if (DM_ODM_SUPPORT_TYPE != ODM_MP) ++// ++// TX report 2 format in Rx desc ++// ++#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) ++#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) ++#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) ++ ++#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) ++#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) ++#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) ++#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) ++#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) ++#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) ++#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) ++#endif ++ ++// End rate adaptive define ++ ++VOID ++ODM_RASupport_Init( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++int ++ODM_RAInfo_Init_all( ++ IN PDM_ODM_T pDM_Odm ++ ); ++ ++int ++ODM_RAInfo_Init( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ); ++ ++u1Byte ++ODM_RA_GetShortGI_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ); ++ ++u1Byte ++ODM_RA_GetDecisionRate_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ); ++ ++u1Byte ++ODM_RA_GetHwPwrStatus_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID ++ ); ++VOID ++ODM_RA_UpdateRateInfo_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte RateID, ++ IN u4Byte RateMask, ++ IN u1Byte SGIEnable ++ ); ++ ++VOID ++ODM_RA_SetRSSI_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte MacID, ++ IN u1Byte Rssi ++ ); ++ ++VOID ++ODM_RA_TxRPT2Handle_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte TxRPT_Buf, ++ IN u2Byte TxRPT_Len, ++ IN u4Byte MacIDValidEntry0, ++ IN u4Byte MacIDValidEntry1 ++ ); ++ ++ ++VOID ++ODM_RA_Set_TxRPT_Time( ++ IN PDM_ODM_T pDM_Odm, ++ IN u2Byte minRptTime ++ ); ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EReg.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EReg.h +new file mode 100644 +index 00000000..a5086c9b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/Hal8188EReg.h +@@ -0,0 +1,47 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++//============================================================ ++// File Name: Hal8188EReg.h ++// ++// Description: ++// ++// This file is for RTL8188E register definition. ++// ++// ++//============================================================ ++#ifndef __HAL_8188E_REG_H__ ++#define __HAL_8188E_REG_H__ ++ ++// ++// Register Definition ++// ++#define TRX_ANTDIV_PATH 0x860 ++#define RX_ANTDIV_PATH 0xb2c ++#define ODM_R_A_AGC_CORE1_8188E 0xc50 ++ ++ ++// ++// Bitmap Definition ++// ++#define BIT_FA_RESET_8188E BIT0 ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c +new file mode 100644 +index 00000000..0b218744 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c +@@ -0,0 +1,1448 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#include "../odm_precomp.h" ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++#include ++#endif ++ ++#if (RTL8188E_SUPPORT == 1) ++static BOOLEAN ++CheckCondition( ++ const u4Byte Condition, ++ const u4Byte Hex ++ ) ++{ ++ u4Byte _board = (Hex & 0x000000FF); ++ u4Byte _interface = (Hex & 0x0000FF00) >> 8; ++ u4Byte _platform = (Hex & 0x00FF0000) >> 16; ++ u4Byte cond = Condition; ++ ++ if ( Condition == 0xCDCDCDCD ) ++ return TRUE; ++ ++ cond = Condition & 0x000000FF; ++ if ( (_board != cond) && (cond != 0xFF) ) ++ return FALSE; ++ ++ cond = Condition & 0x0000FF00; ++ cond = cond >> 8; ++ if ( ((_interface & cond) == 0) && (cond != 0x07) ) ++ return FALSE; ++ ++ cond = Condition & 0x00FF0000; ++ cond = cond >> 16; ++ if ( ((_platform & cond) == 0) && (cond != 0x0F) ) ++ return FALSE; ++ return TRUE; ++} ++ ++ ++/****************************************************************************** ++* AGC_TAB_1T.TXT ++******************************************************************************/ ++ ++u4Byte Array_AGC_TAB_1T_8188E[] = { ++0xFF0F0718, 0xABCD, ++ 0xC78, 0xF7000001, ++ 0xC78, 0xF6010001, ++ 0xC78, 0xF5020001, ++ 0xC78, 0xF4030001, ++ 0xC78, 0xF3040001, ++ 0xC78, 0xF2050001, ++ 0xC78, 0xF1060001, ++ 0xC78, 0xF0070001, ++ 0xC78, 0xEF080001, ++ 0xC78, 0xEE090001, ++ 0xC78, 0xED0A0001, ++ 0xC78, 0xEC0B0001, ++ 0xC78, 0xEB0C0001, ++ 0xC78, 0xEA0D0001, ++ 0xC78, 0xE90E0001, ++ 0xC78, 0xE80F0001, ++ 0xC78, 0xE7100001, ++ 0xC78, 0xE6110001, ++ 0xC78, 0xE5120001, ++ 0xC78, 0xE4130001, ++ 0xC78, 0xE3140001, ++ 0xC78, 0xE2150001, ++ 0xC78, 0xE1160001, ++ 0xC78, 0x89170001, ++ 0xC78, 0x88180001, ++ 0xC78, 0x87190001, ++ 0xC78, 0x861A0001, ++ 0xC78, 0x851B0001, ++ 0xC78, 0x841C0001, ++ 0xC78, 0x831D0001, ++ 0xC78, 0x821E0001, ++ 0xC78, 0x811F0001, ++ 0xC78, 0x6B200001, ++ 0xC78, 0x6A210001, ++ 0xC78, 0x69220001, ++ 0xC78, 0x68230001, ++ 0xC78, 0x67240001, ++ 0xC78, 0x66250001, ++ 0xC78, 0x65260001, ++ 0xC78, 0x64270001, ++ 0xC78, 0x63280001, ++ 0xC78, 0x62290001, ++ 0xC78, 0x612A0001, ++ 0xC78, 0x462B0001, ++ 0xC78, 0x452C0001, ++ 0xC78, 0x442D0001, ++ 0xC78, 0x432E0001, ++ 0xC78, 0x422F0001, ++ 0xC78, 0x41300001, ++ 0xC78, 0x40310001, ++ 0xC78, 0x40320001, ++ 0xC78, 0x40330001, ++ 0xC78, 0x40340001, ++ 0xC78, 0x40350001, ++ 0xC78, 0x40360001, ++ 0xC78, 0x40370001, ++ 0xC78, 0x40380001, ++ 0xC78, 0x40390001, ++ 0xC78, 0x403A0001, ++ 0xC78, 0x403B0001, ++ 0xC78, 0x403C0001, ++ 0xC78, 0x403D0001, ++ 0xC78, 0x403E0001, ++ 0xC78, 0x403F0001, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xC78, 0xFB000001, ++ 0xC78, 0xFB010001, ++ 0xC78, 0xFB020001, ++ 0xC78, 0xFB030001, ++ 0xC78, 0xFB040001, ++ 0xC78, 0xFB050001, ++ 0xC78, 0xFA060001, ++ 0xC78, 0xF9070001, ++ 0xC78, 0xF8080001, ++ 0xC78, 0xF7090001, ++ 0xC78, 0xF60A0001, ++ 0xC78, 0xF50B0001, ++ 0xC78, 0xF40C0001, ++ 0xC78, 0xF30D0001, ++ 0xC78, 0xF20E0001, ++ 0xC78, 0xF10F0001, ++ 0xC78, 0xF0100001, ++ 0xC78, 0xEF110001, ++ 0xC78, 0xEE120001, ++ 0xC78, 0xED130001, ++ 0xC78, 0xEC140001, ++ 0xC78, 0xEB150001, ++ 0xC78, 0xEA160001, ++ 0xC78, 0xE9170001, ++ 0xC78, 0xE8180001, ++ 0xC78, 0xE7190001, ++ 0xC78, 0xE61A0001, ++ 0xC78, 0xE51B0001, ++ 0xC78, 0xE41C0001, ++ 0xC78, 0xE31D0001, ++ 0xC78, 0xE21E0001, ++ 0xC78, 0xE11F0001, ++ 0xC78, 0x8A200001, ++ 0xC78, 0x89210001, ++ 0xC78, 0x88220001, ++ 0xC78, 0x87230001, ++ 0xC78, 0x86240001, ++ 0xC78, 0x85250001, ++ 0xC78, 0x84260001, ++ 0xC78, 0x83270001, ++ 0xC78, 0x82280001, ++ 0xC78, 0x6B290001, ++ 0xC78, 0x6A2A0001, ++ 0xC78, 0x692B0001, ++ 0xC78, 0x682C0001, ++ 0xC78, 0x672D0001, ++ 0xC78, 0x662E0001, ++ 0xC78, 0x652F0001, ++ 0xC78, 0x64300001, ++ 0xC78, 0x63310001, ++ 0xC78, 0x62320001, ++ 0xC78, 0x61330001, ++ 0xC78, 0x46340001, ++ 0xC78, 0x45350001, ++ 0xC78, 0x44360001, ++ 0xC78, 0x43370001, ++ 0xC78, 0x42380001, ++ 0xC78, 0x41390001, ++ 0xC78, 0x403A0001, ++ 0xC78, 0x403B0001, ++ 0xC78, 0x403C0001, ++ 0xC78, 0x403D0001, ++ 0xC78, 0x403E0001, ++ 0xC78, 0x403F0001, ++ 0xFF0F0718, 0xDEAD, ++ 0xFF0F0718, 0xABCD, ++ 0xC78, 0xFB400001, ++ 0xC78, 0xFA410001, ++ 0xC78, 0xF9420001, ++ 0xC78, 0xF8430001, ++ 0xC78, 0xF7440001, ++ 0xC78, 0xF6450001, ++ 0xC78, 0xF5460001, ++ 0xC78, 0xF4470001, ++ 0xC78, 0xF3480001, ++ 0xC78, 0xF2490001, ++ 0xC78, 0xF14A0001, ++ 0xC78, 0xF04B0001, ++ 0xC78, 0xEF4C0001, ++ 0xC78, 0xEE4D0001, ++ 0xC78, 0xED4E0001, ++ 0xC78, 0xEC4F0001, ++ 0xC78, 0xEB500001, ++ 0xC78, 0xEA510001, ++ 0xC78, 0xE9520001, ++ 0xC78, 0xE8530001, ++ 0xC78, 0xE7540001, ++ 0xC78, 0xE6550001, ++ 0xC78, 0xE5560001, ++ 0xC78, 0xE4570001, ++ 0xC78, 0xE3580001, ++ 0xC78, 0xE2590001, ++ 0xC78, 0xC35A0001, ++ 0xC78, 0xC25B0001, ++ 0xC78, 0xC15C0001, ++ 0xC78, 0x8B5D0001, ++ 0xC78, 0x8A5E0001, ++ 0xC78, 0x895F0001, ++ 0xC78, 0x88600001, ++ 0xC78, 0x87610001, ++ 0xC78, 0x86620001, ++ 0xC78, 0x85630001, ++ 0xC78, 0x84640001, ++ 0xC78, 0x67650001, ++ 0xC78, 0x66660001, ++ 0xC78, 0x65670001, ++ 0xC78, 0x64680001, ++ 0xC78, 0x63690001, ++ 0xC78, 0x626A0001, ++ 0xC78, 0x616B0001, ++ 0xC78, 0x606C0001, ++ 0xC78, 0x466D0001, ++ 0xC78, 0x456E0001, ++ 0xC78, 0x446F0001, ++ 0xC78, 0x43700001, ++ 0xC78, 0x42710001, ++ 0xC78, 0x41720001, ++ 0xC78, 0x40730001, ++ 0xC78, 0x40740001, ++ 0xC78, 0x40750001, ++ 0xC78, 0x40760001, ++ 0xC78, 0x40770001, ++ 0xC78, 0x40780001, ++ 0xC78, 0x40790001, ++ 0xC78, 0x407A0001, ++ 0xC78, 0x407B0001, ++ 0xC78, 0x407C0001, ++ 0xC78, 0x407D0001, ++ 0xC78, 0x407E0001, ++ 0xC78, 0x407F0001, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xC78, 0xFB400001, ++ 0xC78, 0xFB410001, ++ 0xC78, 0xFB420001, ++ 0xC78, 0xFB430001, ++ 0xC78, 0xFB440001, ++ 0xC78, 0xFB450001, ++ 0xC78, 0xFB460001, ++ 0xC78, 0xFB470001, ++ 0xC78, 0xFB480001, ++ 0xC78, 0xFA490001, ++ 0xC78, 0xF94A0001, ++ 0xC78, 0xF84B0001, ++ 0xC78, 0xF74C0001, ++ 0xC78, 0xF64D0001, ++ 0xC78, 0xF54E0001, ++ 0xC78, 0xF44F0001, ++ 0xC78, 0xF3500001, ++ 0xC78, 0xF2510001, ++ 0xC78, 0xF1520001, ++ 0xC78, 0xF0530001, ++ 0xC78, 0xEF540001, ++ 0xC78, 0xEE550001, ++ 0xC78, 0xED560001, ++ 0xC78, 0xEC570001, ++ 0xC78, 0xEB580001, ++ 0xC78, 0xEA590001, ++ 0xC78, 0xE95A0001, ++ 0xC78, 0xE85B0001, ++ 0xC78, 0xE75C0001, ++ 0xC78, 0xE65D0001, ++ 0xC78, 0xE55E0001, ++ 0xC78, 0xE45F0001, ++ 0xC78, 0xE3600001, ++ 0xC78, 0xE2610001, ++ 0xC78, 0xC3620001, ++ 0xC78, 0xC2630001, ++ 0xC78, 0xC1640001, ++ 0xC78, 0x8B650001, ++ 0xC78, 0x8A660001, ++ 0xC78, 0x89670001, ++ 0xC78, 0x88680001, ++ 0xC78, 0x87690001, ++ 0xC78, 0x866A0001, ++ 0xC78, 0x856B0001, ++ 0xC78, 0x846C0001, ++ 0xC78, 0x676D0001, ++ 0xC78, 0x666E0001, ++ 0xC78, 0x656F0001, ++ 0xC78, 0x64700001, ++ 0xC78, 0x63710001, ++ 0xC78, 0x62720001, ++ 0xC78, 0x61730001, ++ 0xC78, 0x60740001, ++ 0xC78, 0x46750001, ++ 0xC78, 0x45760001, ++ 0xC78, 0x44770001, ++ 0xC78, 0x43780001, ++ 0xC78, 0x42790001, ++ 0xC78, 0x417A0001, ++ 0xC78, 0x407B0001, ++ 0xC78, 0x407C0001, ++ 0xC78, 0x407D0001, ++ 0xC78, 0x407E0001, ++ 0xC78, 0x407F0001, ++ 0xFF0F0718, 0xDEAD, ++ 0xC50, 0x69553422, ++ 0xC50, 0x69553420, ++ ++}; ++ ++HAL_STATUS ++ODM_ReadAndConfig_AGC_TAB_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte interfaceValue = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u4Byte); ++ pu4Byte Array = Array_AGC_TAB_1T_8188E; ++ BOOLEAN biol = FALSE; ++#ifdef CONFIG_IOL_IOREG_CFG ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ struct xmit_frame *pxmit_frame; ++ u8 bndy_cnt=1; ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ HAL_STATUS rst =HAL_STATUS_SUCCESS; ++ ++ hex += board; ++ hex += interfaceValue << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++#ifdef CONFIG_IOL_IOREG_CFG ++ biol = rtw_IOL_applied(Adapter); ++ ++ if(biol){ ++ if((pxmit_frame= rtw_IOL_accquire_xmit_frame(Adapter)) == NULL){ ++ printk("rtw_IOL_accquire_xmit_frame failed\n"); ++ return HAL_STATUS_FAILURE; ++ } ++ } ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ } ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while ( v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while ( v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ } ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++#ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); ++ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ printk("~~~ %s Success !!! \n",__FUNCTION__); ++ { ++ //dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ ++ } ++ else{ ++ printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ { ++ //dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ ++ rst = HAL_STATUS_FAILURE; ++ } ++ } ++#endif //#ifdef CONFIG_IOL_IOREG_CFG ++ return rst; ++} ++ ++/****************************************************************************** ++* AGC_TAB_1T_ICUT.TXT ++******************************************************************************/ ++ ++u4Byte Array_MP_8188E_AGC_TAB_1T_ICUT[] = { ++ 0xC78, 0xFB000001, ++ 0xC78, 0xFB010001, ++ 0xC78, 0xFB020001, ++ 0xC78, 0xFB030001, ++ 0xC78, 0xFB040001, ++ 0xC78, 0xFA050001, ++ 0xC78, 0xF9060001, ++ 0xC78, 0xF8070001, ++ 0xC78, 0xF7080001, ++ 0xC78, 0xF6090001, ++ 0xC78, 0xF50A0001, ++ 0xC78, 0xF40B0001, ++ 0xC78, 0xF30C0001, ++ 0xC78, 0xF20D0001, ++ 0xC78, 0xF10E0001, ++ 0xC78, 0xF00F0001, ++ 0xC78, 0xEF100001, ++ 0xC78, 0xEE110001, ++ 0xC78, 0xED120001, ++ 0xC78, 0xEC130001, ++ 0xC78, 0xEB140001, ++ 0xC78, 0xEA150001, ++ 0xC78, 0xE9160001, ++ 0xC78, 0xE8170001, ++ 0xC78, 0xE7180001, ++ 0xC78, 0xE6190001, ++ 0xC78, 0xE51A0001, ++ 0xC78, 0xE41B0001, ++ 0xC78, 0xC71C0001, ++ 0xC78, 0xC61D0001, ++ 0xC78, 0xC51E0001, ++ 0xC78, 0xC41F0001, ++ 0xC78, 0xC3200001, ++ 0xC78, 0xC2210001, ++ 0xC78, 0x88220001, ++ 0xC78, 0x87230001, ++ 0xC78, 0x86240001, ++ 0xC78, 0x85250001, ++ 0xC78, 0x84260001, ++ 0xC78, 0x83270001, ++ 0xC78, 0x82280001, ++ 0xC78, 0x81290001, ++ 0xC78, 0x242A0001, ++ 0xC78, 0x232B0001, ++ 0xC78, 0x222C0001, ++ 0xC78, 0x672D0001, ++ 0xC78, 0x662E0001, ++ 0xC78, 0x652F0001, ++ 0xC78, 0x64300001, ++ 0xC78, 0x63310001, ++ 0xC78, 0x62320001, ++ 0xC78, 0x61330001, ++ 0xC78, 0x60340001, ++ 0xC78, 0x4A350001, ++ 0xC78, 0x49360001, ++ 0xC78, 0x48370001, ++ 0xC78, 0x47380001, ++ 0xC78, 0x46390001, ++ 0xC78, 0x453A0001, ++ 0xC78, 0x443B0001, ++ 0xC78, 0x433C0001, ++ 0xC78, 0x423D0001, ++ 0xC78, 0x413E0001, ++ 0xC78, 0x403F0001, ++ 0xC78, 0xFB400001, ++ 0xC78, 0xFB410001, ++ 0xC78, 0xFB420001, ++ 0xC78, 0xFB430001, ++ 0xC78, 0xFB440001, ++ 0xC78, 0xFB450001, ++ 0xC78, 0xFB460001, ++ 0xC78, 0xFB470001, ++ 0xC78, 0xFA480001, ++ 0xC78, 0xF9490001, ++ 0xC78, 0xF84A0001, ++ 0xC78, 0xF74B0001, ++ 0xC78, 0xF64C0001, ++ 0xC78, 0xF54D0001, ++ 0xC78, 0xF44E0001, ++ 0xC78, 0xF34F0001, ++ 0xC78, 0xF2500001, ++ 0xC78, 0xF1510001, ++ 0xC78, 0xF0520001, ++ 0xC78, 0xEF530001, ++ 0xC78, 0xEE540001, ++ 0xC78, 0xED550001, ++ 0xC78, 0xEC560001, ++ 0xC78, 0xEB570001, ++ 0xC78, 0xEA580001, ++ 0xC78, 0xE9590001, ++ 0xC78, 0xE85A0001, ++ 0xC78, 0xE75B0001, ++ 0xC78, 0xE65C0001, ++ 0xC78, 0xE55D0001, ++ 0xC78, 0xC65E0001, ++ 0xC78, 0xC55F0001, ++ 0xC78, 0xC4600001, ++ 0xC78, 0xC3610001, ++ 0xC78, 0xC2620001, ++ 0xC78, 0xC1630001, ++ 0xC78, 0xC0640001, ++ 0xC78, 0xA3650001, ++ 0xC78, 0xA2660001, ++ 0xC78, 0xA1670001, ++ 0xC78, 0x88680001, ++ 0xC78, 0x87690001, ++ 0xC78, 0x866A0001, ++ 0xC78, 0x856B0001, ++ 0xC78, 0x846C0001, ++ 0xC78, 0x836D0001, ++ 0xC78, 0x826E0001, ++ 0xC78, 0x666F0001, ++ 0xC78, 0x65700001, ++ 0xC78, 0x64710001, ++ 0xC78, 0x63720001, ++ 0xC78, 0x62730001, ++ 0xC78, 0x61740001, ++ 0xC78, 0x48750001, ++ 0xC78, 0x47760001, ++ 0xC78, 0x46770001, ++ 0xC78, 0x45780001, ++ 0xC78, 0x44790001, ++ 0xC78, 0x437A0001, ++ 0xC78, 0x427B0001, ++ 0xC78, 0x417C0001, ++ 0xC78, 0x407D0001, ++ 0xC78, 0x407E0001, ++ 0xC78, 0x407F0001, ++ 0xC50, 0x69553422, ++ 0xC50, 0x69553420, ++ ++}; ++ ++void ++ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte _interface = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u4Byte); ++ pu4Byte Array = Array_MP_8188E_AGC_TAB_1T_ICUT; ++ ++ ++ hex += board; ++ hex += _interface << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_AGC_TAB_1T_ICUT, hex = 0x%X\n", hex)); ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++ ++} ++ ++/****************************************************************************** ++* PHY_REG_1T.TXT ++******************************************************************************/ ++ ++u4Byte Array_PHY_REG_1T_8188E[] = { ++ 0x800, 0x80040000, ++ 0x804, 0x00000003, ++ 0x808, 0x0000FC00, ++ 0x80C, 0x0000000A, ++ 0x810, 0x10001331, ++ 0x814, 0x020C3D10, ++ 0x818, 0x02200385, ++ 0x81C, 0x00000000, ++ 0x820, 0x01000100, ++ 0x824, 0x00390204, ++ 0x828, 0x00000000, ++ 0x82C, 0x00000000, ++ 0x830, 0x00000000, ++ 0x834, 0x00000000, ++ 0x838, 0x00000000, ++ 0x83C, 0x00000000, ++ 0x840, 0x00010000, ++ 0x844, 0x00000000, ++ 0x848, 0x00000000, ++ 0x84C, 0x00000000, ++ 0x850, 0x00000000, ++ 0x854, 0x00000000, ++ 0x858, 0x569A11A9, ++ 0x85C, 0x01000014, ++ 0x860, 0x66F60110, ++ 0x864, 0x061F0649, ++ 0x868, 0x00000000, ++ 0x86C, 0x27272700, ++ 0xFF0F0718, 0xABCD, ++ 0x870, 0x07000300, ++ 0xCDCDCDCD, 0xCDCD, ++ 0x870, 0x07000760, ++ 0xFF0F0718, 0xDEAD, ++ 0x874, 0x25004000, ++ 0x878, 0x00000808, ++ 0x87C, 0x00000000, ++ 0x880, 0xB0000C1C, ++ 0x884, 0x00000001, ++ 0x888, 0x00000000, ++ 0x88C, 0xCCC000C0, ++ 0x890, 0x00000800, ++ 0x894, 0xFFFFFFFE, ++ 0x898, 0x40302010, ++ 0x89C, 0x00706050, ++ 0x900, 0x00000000, ++ 0x904, 0x00000023, ++ 0x908, 0x00000000, ++ 0x90C, 0x81121111, ++ 0x910, 0x00000002, ++ 0x914, 0x00000201, ++ 0xA00, 0x00D047C8, ++ 0xA04, 0x80FF000C, ++ 0xA08, 0x8C838300, ++ 0xA0C, 0x2E7F120F, ++ 0xA10, 0x9500BB78, ++ 0xA14, 0x1114D028, ++ 0xA18, 0x00881117, ++ 0xA1C, 0x89140F00, ++ 0xFF0F0718, 0xABCD, ++ 0xA20, 0x13130000, ++ 0xA24, 0x060A0D10, ++ 0xA28, 0x00000103, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xA20, 0x1A1B0000, ++ 0xA24, 0x090E1317, ++ 0xA28, 0x00000204, ++ 0xFF0F0718, 0xDEAD, ++ 0xA2C, 0x00D30000, ++ 0xA70, 0x101FBF00, ++ 0xA74, 0x00000007, ++ 0xA78, 0x00000900, ++ 0xA7C, 0x225B0606, ++ 0xA80, 0x218075B1, ++ 0xFF0F0718, 0xABCD, ++ 0xB2C, 0x00000000, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xB2C, 0x80000000, ++ 0xFF0F0718, 0xDEAD, ++ 0xC00, 0x48071D40, ++ 0xC04, 0x03A05611, ++ 0xC08, 0x000000E4, ++ 0xC0C, 0x6C6C6C6C, ++ 0xC10, 0x08800000, ++ 0xC14, 0x40000100, ++ 0xC18, 0x08800000, ++ 0xC1C, 0x40000100, ++ 0xC20, 0x00000000, ++ 0xC24, 0x00000000, ++ 0xC28, 0x00000000, ++ 0xC2C, 0x00000000, ++ 0xC30, 0x69E9AC47, ++ 0xC34, 0x469652AF, ++ 0xC38, 0x49795994, ++ 0xC3C, 0x0A97971C, ++ 0xC40, 0x1F7C403F, ++ 0xC44, 0x000100B7, ++ 0xC48, 0xEC020107, ++ 0xC4C, 0x007F037F, ++ 0xC50, 0x69553420, ++ 0xC54, 0x43BC0094, ++ 0xC58, 0x00013169, ++ 0xC5C, 0x00250492, ++ 0xC60, 0x00000000, ++ 0xC64, 0x7112848B, ++ 0xC68, 0x47C00BFF, ++ 0xC6C, 0x00000036, ++ 0xC70, 0x2C7F000D, ++ 0xC74, 0x020610DB, ++ 0xC78, 0x0000001F, ++ 0xC7C, 0x00B91612, ++ 0xFF0F0718, 0xABCD, ++ 0xC80, 0x2D4000B5, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xC80, 0x390000E4, ++ 0xFF0F0718, 0xDEAD, ++ 0xC84, 0x20F60000, ++ 0xC88, 0x40000100, ++ 0xC8C, 0x20200000, ++ 0xC90, 0x00091521, ++ 0xC94, 0x00000000, ++ 0xC98, 0x00121820, ++ 0xC9C, 0x00007F7F, ++ 0xCA0, 0x00000000, ++ 0xCA4, 0x000300A0, ++ 0xCA8, 0x00000000, ++ 0xCAC, 0x00000000, ++ 0xCB0, 0x00000000, ++ 0xCB4, 0x00000000, ++ 0xCB8, 0x00000000, ++ 0xCBC, 0x28000000, ++ 0xCC0, 0x00000000, ++ 0xCC4, 0x00000000, ++ 0xCC8, 0x00000000, ++ 0xCCC, 0x00000000, ++ 0xCD0, 0x00000000, ++ 0xCD4, 0x00000000, ++ 0xCD8, 0x64B22427, ++ 0xCDC, 0x00766932, ++ 0xCE0, 0x00222222, ++ 0xCE4, 0x00000000, ++ 0xCE8, 0x37644302, ++ 0xCEC, 0x2F97D40C, ++ 0xD00, 0x00000740, ++ 0xD04, 0x00020401, ++ 0xD08, 0x0000907F, ++ 0xD0C, 0x20010201, ++ 0xD10, 0xA0633333, ++ 0xD14, 0x3333BC43, ++ 0xD18, 0x7A8F5B6F, ++ 0xD2C, 0xCC979975, ++ 0xD30, 0x00000000, ++ 0xD34, 0x80608000, ++ 0xD38, 0x00000000, ++ 0xD3C, 0x00127353, ++ 0xD40, 0x00000000, ++ 0xD44, 0x00000000, ++ 0xD48, 0x00000000, ++ 0xD4C, 0x00000000, ++ 0xD50, 0x6437140A, ++ 0xD54, 0x00000000, ++ 0xD58, 0x00000282, ++ 0xD5C, 0x30032064, ++ 0xD60, 0x4653DE68, ++ 0xD64, 0x04518A3C, ++ 0xD68, 0x00002101, ++ 0xD6C, 0x2A201C16, ++ 0xD70, 0x1812362E, ++ 0xD74, 0x322C2220, ++ 0xD78, 0x000E3C24, ++ 0xE00, 0x2D2D2D2D, ++ 0xE04, 0x2D2D2D2D, ++ 0xE08, 0x0390272D, ++ 0xE10, 0x2D2D2D2D, ++ 0xE14, 0x2D2D2D2D, ++ 0xE18, 0x2D2D2D2D, ++ 0xE1C, 0x2D2D2D2D, ++ 0xE28, 0x00000000, ++ 0xE30, 0x1000DC1F, ++ 0xE34, 0x10008C1F, ++ 0xE38, 0x02140102, ++ 0xE3C, 0x681604C2, ++ 0xE40, 0x01007C00, ++ 0xE44, 0x01004800, ++ 0xE48, 0xFB000000, ++ 0xE4C, 0x000028D1, ++ 0xE50, 0x1000DC1F, ++ 0xE54, 0x10008C1F, ++ 0xE58, 0x02140102, ++ 0xE5C, 0x28160D05, ++ 0xE60, 0x00000008, ++ 0xE68, 0x001B25A4, ++ 0xE6C, 0x00C00014, ++ 0xE70, 0x00C00014, ++ 0xE74, 0x01000014, ++ 0xE78, 0x01000014, ++ 0xE7C, 0x01000014, ++ 0xE80, 0x01000014, ++ 0xE84, 0x00C00014, ++ 0xE88, 0x01000014, ++ 0xE8C, 0x00C00014, ++ 0xED0, 0x00C00014, ++ 0xED4, 0x00C00014, ++ 0xED8, 0x00C00014, ++ 0xEDC, 0x00000014, ++ 0xEE0, 0x00000014, ++ 0xFF0F0718, 0xABCD, ++ 0xEE8, 0x32555448, ++ 0xCDCDCDCD, 0xCDCD, ++ 0xEE8, 0x21555448, ++ 0xFF0F0718, 0xDEAD, ++ 0xEEC, 0x01C00014, ++ 0xF14, 0x00000003, ++ 0xF4C, 0x00000000, ++ 0xF00, 0x00000300, ++}; ++ ++ ++HAL_STATUS ++ODM_ReadAndConfig_PHY_REG_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte interfaceValue = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u4Byte); ++ pu4Byte Array = Array_PHY_REG_1T_8188E; ++ BOOLEAN biol = FALSE; ++#ifdef CONFIG_IOL_IOREG_CFG ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ struct xmit_frame *pxmit_frame; ++ u8 bndy_cnt=1; ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ struct cmd_cmp cmpdata[ArrayLen]; ++ u4Byte cmpdata_idx=0; ++ #endif ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ HAL_STATUS rst =HAL_STATUS_SUCCESS; ++ hex += board; ++ hex += interfaceValue << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++#ifdef CONFIG_IOL_IOREG_CFG ++ biol = rtw_IOL_applied(Adapter); ++ ++ if(biol){ ++ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ { ++ printk("rtw_IOL_accquire_xmit_frame failed\n"); ++ return HAL_STATUS_FAILURE; ++ } ++ } ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ ++ ++ if (v1 == 0xfe){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfd){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xfc){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); ++ } ++ else if (v1 == 0xfb){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfa){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); ++ } ++ else if (v1 == 0xf9){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); ++ } ++ else{ ++ if (v1 == 0xa24) ++ pDM_Odm->RFCalibrateInfo.RegA24 = v2; ++ ++ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ } ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ } ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ if (v1 == 0xfe){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfd){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xfc){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); ++ } ++ else if (v1 == 0xfb){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfa){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xf9){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); ++ } ++ else{ ++ if (v1 == 0xa24) ++ pDM_Odm->RFCalibrateInfo.RegA24 = v2; ++ ++ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ } ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ } ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++#ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); ++ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ printk("~~~ %s IOL_exec_cmds Success !!! \n",__FUNCTION__); ++ { ++ u4Byte idx; ++ u4Byte cdata; ++ printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx); ++ printk("### %s data compared !!###\n",__FUNCTION__); ++ for(idx=0;idx< cmpdata_idx;idx++) ++ { ++ cdata = ODM_Read4Byte(pDM_Odm, cmpdata[idx].addr); ++ if(cdata != cmpdata[idx].value){ ++ printk(" addr:0x%04x, data:(0x%02x : 0x%02x) \n", ++ cmpdata[idx].addr,cmpdata[idx].value,cdata); ++ rst = HAL_STATUS_FAILURE; ++ } ++ } ++ printk("### %s data compared !!###\n",__FUNCTION__); ++ //if(rst == HAL_STATUS_FAILURE) ++ {//dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ ++ } ++ else{ ++ rst = HAL_STATUS_FAILURE; ++ printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ { ++ //dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ } ++ } ++#endif //#ifdef CONFIG_IOL_IOREG_CFG ++ return rst; ++} ++/****************************************************************************** ++* PHY_REG_1T_ICUT.TXT ++******************************************************************************/ ++ ++u4Byte Array_MP_8188E_PHY_REG_1T_ICUT[] = { ++ 0x800, 0x80040000, ++ 0x804, 0x00000003, ++ 0x808, 0x0000FC00, ++ 0x80C, 0x0000000A, ++ 0x810, 0x10001331, ++ 0x814, 0x020C3D10, ++ 0x818, 0x02200385, ++ 0x81C, 0x00000000, ++ 0x820, 0x01000100, ++ 0x824, 0x00390204, ++ 0x828, 0x00000000, ++ 0x82C, 0x00000000, ++ 0x830, 0x00000000, ++ 0x834, 0x00000000, ++ 0x838, 0x00000000, ++ 0x83C, 0x00000000, ++ 0x840, 0x00010000, ++ 0x844, 0x00000000, ++ 0x848, 0x00000000, ++ 0x84C, 0x00000000, ++ 0x850, 0x00000000, ++ 0x854, 0x00000000, ++ 0x858, 0x569A11A9, ++ 0x85C, 0x01000014, ++ 0x860, 0x66F60110, ++ 0x864, 0x061F0649, ++ 0x868, 0x00000000, ++ 0x86C, 0x27272700, ++ 0x870, 0x07000760, ++ 0x874, 0x25004000, ++ 0x878, 0x00000808, ++ 0x87C, 0x00000000, ++ 0x880, 0xB0000C1C, ++ 0x884, 0x00000001, ++ 0x888, 0x00000000, ++ 0x88C, 0xCCC000C0, ++ 0x890, 0x00000800, ++ 0x894, 0xFFFFFFFE, ++ 0x898, 0x40302010, ++ 0x89C, 0x00706050, ++ 0x900, 0x00000000, ++ 0x904, 0x00000023, ++ 0x908, 0x00000000, ++ 0x90C, 0x81121111, ++ 0x910, 0x00000002, ++ 0x914, 0x00000201, ++ 0xA00, 0x00D047C8, ++ 0xA04, 0x80FF000C, ++ 0xA08, 0x8C838300, ++ 0xA0C, 0x2E7F120F, ++ 0xA10, 0x9500BB78, ++ 0xA14, 0x1114D028, ++ 0xA18, 0x00881117, ++ 0xA1C, 0x89140F00, ++ 0xA20, 0x1A1B0000, ++ 0xA24, 0x090E1317, ++ 0xA28, 0x00000204, ++ 0xA2C, 0x00D30000, ++ 0xA70, 0x101FBF00, ++ 0xA74, 0x00000007, ++ 0xA78, 0x00000900, ++ 0xA7C, 0x225B0606, ++ 0xA80, 0x218075B1, ++ 0xB2C, 0x80000000, ++ 0xC00, 0x48071D40, ++ 0xC04, 0x03A05611, ++ 0xC08, 0x000000E4, ++ 0xC0C, 0x6C6C6C6C, ++ 0xC10, 0x08800000, ++ 0xC14, 0x40000100, ++ 0xC18, 0x08800000, ++ 0xC1C, 0x40000100, ++ 0xC20, 0x00000000, ++ 0xC24, 0x00000000, ++ 0xC28, 0x00000000, ++ 0xC2C, 0x00000000, ++ 0xC30, 0x69E9AC47, ++ 0xC34, 0x469652AF, ++ 0xC38, 0x49795994, ++ 0xC3C, 0x0A97971C, ++ 0xC40, 0x1F7C403F, ++ 0xC44, 0x000100B7, ++ 0xC48, 0xEC020107, ++ 0xC4C, 0x007F037F, ++ 0xC50, 0x69553420, ++ 0xC54, 0x43BC0094, ++ 0xC58, 0x00013159, ++ 0xC5C, 0x00250492, ++ 0xC60, 0x00000000, ++ 0xC64, 0x7112848B, ++ 0xC68, 0x47C00BFF, ++ 0xC6C, 0x00000036, ++ 0xC70, 0x2C7F000D, ++ 0xC74, 0x028610DB, ++ 0xC78, 0x0000001F, ++ 0xC7C, 0x00B91612, ++ 0xC80, 0x390000E4, ++ 0xC84, 0x20F60000, ++ 0xC88, 0x40000100, ++ 0xC8C, 0x20200000, ++ 0xC90, 0x00091521, ++ 0xC94, 0x00000000, ++ 0xC98, 0x00121820, ++ 0xC9C, 0x00007F7F, ++ 0xCA0, 0x00000000, ++ 0xCA4, 0x000300A0, ++ 0xCA8, 0xFFFF0000, ++ 0xCAC, 0x00000000, ++ 0xCB0, 0x00000000, ++ 0xCB4, 0x00000000, ++ 0xCB8, 0x00000000, ++ 0xCBC, 0x28000000, ++ 0xCC0, 0x00000000, ++ 0xCC4, 0x00000000, ++ 0xCC8, 0x00000000, ++ 0xCCC, 0x00000000, ++ 0xCD0, 0x00000000, ++ 0xCD4, 0x00000000, ++ 0xCD8, 0x64B22427, ++ 0xCDC, 0x00766932, ++ 0xCE0, 0x00222222, ++ 0xCE4, 0x00000000, ++ 0xCE8, 0x37644302, ++ 0xCEC, 0x2F97D40C, ++ 0xD00, 0x00000740, ++ 0xD04, 0x00020401, ++ 0xD08, 0x0000907F, ++ 0xD0C, 0x20010201, ++ 0xD10, 0xA0633333, ++ 0xD14, 0x3333BC43, ++ 0xD18, 0x7A8F5B6F, ++ 0xD2C, 0xCC979975, ++ 0xD30, 0x00000000, ++ 0xD34, 0x80608000, ++ 0xD38, 0x00000000, ++ 0xD3C, 0x00127353, ++ 0xD40, 0x00000000, ++ 0xD44, 0x00000000, ++ 0xD48, 0x00000000, ++ 0xD4C, 0x00000000, ++ 0xD50, 0x6437140A, ++ 0xD54, 0x00000000, ++ 0xD58, 0x00000282, ++ 0xD5C, 0x30032064, ++ 0xD60, 0x4653DE68, ++ 0xD64, 0x04518A3C, ++ 0xD68, 0x00002101, ++ 0xD6C, 0x2A201C16, ++ 0xD70, 0x1812362E, ++ 0xD74, 0x322C2220, ++ 0xD78, 0x000E3C24, ++ 0xE00, 0x2D2D2D2D, ++ 0xE04, 0x2D2D2D2D, ++ 0xE08, 0x0390272D, ++ 0xE10, 0x2D2D2D2D, ++ 0xE14, 0x2D2D2D2D, ++ 0xE18, 0x2D2D2D2D, ++ 0xE1C, 0x2D2D2D2D, ++ 0xE28, 0x00000000, ++ 0xE30, 0x1000DC1F, ++ 0xE34, 0x10008C1F, ++ 0xE38, 0x02140102, ++ 0xE3C, 0x681604C2, ++ 0xE40, 0x01007C00, ++ 0xE44, 0x01004800, ++ 0xE48, 0xFB000000, ++ 0xE4C, 0x000028D1, ++ 0xE50, 0x1000DC1F, ++ 0xE54, 0x10008C1F, ++ 0xE58, 0x02140102, ++ 0xE5C, 0x28160D05, ++ 0xE60, 0x00000008, ++ 0xE68, 0x001B25A4, ++ 0xE6C, 0x00C00014, ++ 0xE70, 0x00C00014, ++ 0xE74, 0x01000014, ++ 0xE78, 0x01000014, ++ 0xE7C, 0x01000014, ++ 0xE80, 0x01000014, ++ 0xE84, 0x00C00014, ++ 0xE88, 0x01000014, ++ 0xE8C, 0x00C00014, ++ 0xED0, 0x00C00014, ++ 0xED4, 0x00C00014, ++ 0xED8, 0x00C00014, ++ 0xEDC, 0x00000014, ++ 0xEE0, 0x00000014, ++ 0xEEC, 0x01C00014, ++ 0xF14, 0x00000003, ++ 0xF4C, 0x00000000, ++ 0xF00, 0x00000300, ++ ++}; ++ ++void ++ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte _interface = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG_1T_ICUT)/sizeof(u4Byte); ++ pu4Byte Array = Array_MP_8188E_PHY_REG_1T_ICUT; ++ ++ ++ hex += board; ++ hex += _interface << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG_1T_ICUT, hex = 0x%X\n", hex)); ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++ ++} ++ ++ ++/****************************************************************************** ++* PHY_REG_PG.TXT ++******************************************************************************/ ++ ++u4Byte Array_PHY_REG_PG_8188E[] = { ++ 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00004000, ++ 0, 0, 0, 0x0000086c, 0xffffff00, 0x34363800, ++ 0, 0, 0, 0x00000e00, 0xffffffff, 0x42444646, ++ 0, 0, 0, 0x00000e04, 0xffffffff, 0x30343840, ++ 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, ++ 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 ++ ++}; ++ ++void ++ODM_ReadAndConfig_PHY_REG_PG_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte interfaceValue = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u4Byte); ++ pu4Byte Array = Array_PHY_REG_PG_8188E; ++ BOOLEAN biol = FALSE; ++ ++ hex += board; ++ hex += interfaceValue << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ for (i = 0; i < ArrayLen; i += 6 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ u4Byte v3 = Array[i+2]; ++ u4Byte v4 = Array[i+3]; ++ u4Byte v5 = Array[i+4]; ++ u4Byte v6 = Array[i+5]; ++ ++ // this line is a line of pure_body ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ ++ odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3); ++ ++ continue; ++ } ++ else ++ { // this line is the start of branch ++ if ( !CheckCondition(Array[i], hex) ) ++ { // don't need the hw_body ++ i += 2; // skip the pair of expression ++ v1 = Array[i]; ++ v2 = Array[i+1]; ++ v3 = Array[i+2]; ++ while (v2 != 0xDEAD) ++ { ++ i += 3; ++ v1 = Array[i]; ++ v2 = Array[i+1]; ++ v3 = Array[i+1]; ++ } ++ } ++ } ++ } ++ ++} ++ ++ ++ ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h +new file mode 100644 +index 00000000..8fbf9b55 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h +@@ -0,0 +1,71 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#if (RTL8188E_SUPPORT == 1) ++#ifndef __INC_BB_8188E_HW_IMG_H ++#define __INC_BB_8188E_HW_IMG_H ++ ++//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); ++ ++/****************************************************************************** ++* AGC_TAB_1T.TXT ++******************************************************************************/ ++ ++HAL_STATUS ++ODM_ReadAndConfig_AGC_TAB_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++); ++/****************************************************************************** ++* AGC_TAB_1T_ICUT.TXT ++******************************************************************************/ ++ ++void ++ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip ++ IN PDM_ODM_T pDM_Odm ++); ++/****************************************************************************** ++* PHY_REG_1T.TXT ++******************************************************************************/ ++ ++HAL_STATUS ++ODM_ReadAndConfig_PHY_REG_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++); ++/****************************************************************************** ++* PHY_REG_1T_ICUT.TXT ++******************************************************************************/ ++ ++void ++ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip ++ IN PDM_ODM_T pDM_Odm ++); ++ ++/****************************************************************************** ++* PHY_REG_PG.TXT ++******************************************************************************/ ++ ++void ++ODM_ReadAndConfig_PHY_REG_PG_8188E( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++#endif ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c +new file mode 100644 +index 00000000..9b3134b5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c +@@ -0,0 +1,1034 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++#if 0 ++#include "Mp_Precomp.h" ++#endif ++#include "../odm_precomp.h" ++ ++#if (RTL8188E_SUPPORT == 1) ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) ++ ++ ++u1Byte Array_8188E_FW_AP[] = { ++ ++}; ++u4Byte ArrayLength_8188E_FW_AP = 0; ++ ++ ++void ++ODM_ReadFirmware_8188E_FW_AP( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++) ++{ ++ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_AP, ArrayLength_8188E_FW_AP); ++ *pFirmwareSize = ArrayLength_8188E_FW_AP; ++} ++ ++ ++#else ++ ++#if 0 ++u1Byte Array_8188E_FW_NIC[] = { ++ ++}; ++u4Byte ArrayLength_8188E_FW_NIC = 0; ++ ++ ++void ++ODM_ReadFirmware_8188E_FW_NIC( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++) ++{ ++ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_NIC, ArrayLength_8188E_FW_NIC); ++ *pFirmwareSize = ArrayLength_8188E_FW_NIC; ++} ++#endif ++ ++const u8 Array_8188E_FW_WoWLAN[] = { ++0xE1, 0x88, 0x30, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x06, 0x27, 0x15, 0x23, 0xC8, 0x3A, 0x00, 0x00, ++0x6E, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x02, 0x46, 0xD5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0xE1, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0xE1, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4F, 0xE9, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++0xE7, 0x09, 0xF6, 0x08, 0xDF, 0xFA, 0x80, 0x46, 0xE7, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x3E, ++0x88, 0x82, 0x8C, 0x83, 0xE7, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x32, 0xE3, 0x09, 0xF6, 0x08, ++0xDF, 0xFA, 0x80, 0x78, 0xE3, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x70, 0x88, 0x82, 0x8C, 0x83, ++0xE3, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x64, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF6, 0x08, ++0xDF, 0xFA, 0x80, 0x58, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x4C, ++0x80, 0xD2, 0x80, 0xFA, 0x80, 0xC6, 0x80, 0xD4, 0x80, 0x69, 0x80, 0xF2, 0x80, 0x33, 0x80, 0x10, ++0x80, 0xA6, 0x80, 0xEA, 0x80, 0x9A, 0x80, 0xA8, 0x80, 0xDA, 0x80, 0xE2, 0x80, 0xCA, 0x80, 0x33, ++0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, ++0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, ++0x0D, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF6, 0x08, 0xDF, 0xF9, 0xEC, 0xFA, 0xA9, 0xF0, ++0xED, 0xFB, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, ++0xC5, 0x83, 0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xEA, 0xDE, ++0xE8, 0x80, 0xDB, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF2, 0x08, 0xDF, 0xF9, 0x80, 0xCC, ++0x88, 0xF0, 0xEF, 0x60, 0x01, 0x0E, 0x4E, 0x60, 0xC3, 0x88, 0xF0, 0xED, 0x24, 0x02, 0xB4, 0x04, ++0x00, 0x50, 0xB9, 0xF5, 0x82, 0xEB, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0xAF, 0x23, 0x23, 0x45, ++0x82, 0x23, 0x90, 0x41, 0x50, 0x73, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, 0xC5, 0xF0, 0xF8, ++0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xEF, 0x5B, 0xFF, 0xEE, ++0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, ++0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, ++0xFF, 0x22, 0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0x22, 0xA4, 0x25, ++0x82, 0xF5, 0x82, 0xE5, 0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, ++0xE0, 0xF9, 0x22, 0xEB, 0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, ++0xF8, 0xE4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, ++0x93, 0xF5, 0x82, 0x88, 0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, ++0x80, 0xDF, 0xE3, 0xF5, 0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x6B, 0xDF, 0xF5, 0x80, 0x67, 0xE3, ++0xF5, 0xF0, 0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x5E, 0xDF, 0xF5, 0x80, 0x5A, 0x87, 0xF0, 0x09, 0xE6, ++0x08, 0xB5, 0xF0, 0x52, 0xDF, 0xF6, 0x80, 0x4E, 0x87, 0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x46, ++0xDF, 0xF6, 0x80, 0x42, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE0, 0xA3, 0xB5, 0xF0, 0x36, ++0xDF, 0xF6, 0x80, 0x32, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE4, 0x93, 0xA3, 0xB5, 0xF0, ++0x25, 0xDF, 0xF5, 0x80, 0x21, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09, 0xE0, 0xA3, 0xB5, ++0xF0, 0x14, 0xDF, 0xF5, 0x80, 0x10, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09, 0xE4, 0x93, ++0xA3, 0xB5, 0xF0, 0x02, 0xDF, 0xF4, 0x02, 0x43, 0xB1, 0x80, 0x87, 0x80, 0xE9, 0x80, 0x90, 0x80, ++0xD4, 0x80, 0x3E, 0x80, 0x15, 0x80, 0x6E, 0x80, 0x7E, 0x80, 0x9D, 0x80, 0xB7, 0x80, 0x8D, 0x80, ++0xA3, 0x80, 0x51, 0x80, 0x74, 0x80, 0x3C, 0x02, 0x43, 0xBD, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, ++0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE4, 0x93, 0xA3, ++0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x76, 0xDF, 0xE3, 0xDE, 0xE1, 0x80, ++0x70, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xE2, 0x08, 0xB5, 0xF0, 0x62, 0xDF, ++0xF4, 0x80, 0x5E, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE6, 0x08, 0xB5, 0xF0, 0x51, ++0xDF, 0xF5, 0x80, 0x4D, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE2, 0x08, 0xB5, 0xF0, ++0x40, 0xDF, 0xF5, 0x80, 0x3C, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xE6, 0x08, ++0xB5, 0xF0, 0x2E, 0xDF, 0xF4, 0x80, 0x2A, 0x80, 0x02, 0x80, 0x57, 0x89, 0x82, 0x8A, 0x83, 0xEC, ++0xFA, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE0, 0xA3, ++0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x06, 0xDF, 0xE4, 0xDE, 0xE2, 0x80, ++0x00, 0x7F, 0xFF, 0xB5, 0xF0, 0x02, 0x0F, 0x22, 0x40, 0x02, 0x7F, 0x01, 0x22, 0x89, 0x82, 0x8A, ++0x83, 0xEC, 0xFA, 0xE0, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE0, ++0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0xD5, 0xDF, 0xE5, 0xDE, 0xE3, ++0x80, 0xCF, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, ++0xCC, 0xC5, 0x83, 0xCC, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, ++0xF0, 0xAF, 0xDF, 0xE4, 0xDE, 0xE2, 0x80, 0xA9, 0x88, 0xF0, 0xEF, 0x60, 0x01, 0x0E, 0x4E, 0x60, ++0xAB, 0xED, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0x98, 0xF5, 0x82, 0xEB, 0x24, 0x02, 0xB4, 0x04, ++0x00, 0x50, 0x8E, 0x23, 0x23, 0x45, 0x82, 0x23, 0x90, 0x42, 0xF9, 0x73, 0xC2, 0xAF, 0x80, 0xFE, ++0x32, 0x12, 0x44, 0x30, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, 0xC2, 0x8C, 0xE5, 0x8A, ++0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, 0xEC, 0x24, 0x87, 0xF8, ++0xE6, 0xBC, 0x02, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, 0x40, 0xCE, 0x79, 0x03, ++0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, 0x03, 0x44, 0x18, 0xF6, ++0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, 0x23, 0x24, 0x81, 0xF8, ++0x0F, 0x08, 0x08, 0xBF, 0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, 0xE4, 0xF2, 0x00, 0xE5, ++0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x86, 0x25, 0x0C, 0xF8, 0xE6, 0xFD, 0xA6, 0x81, ++0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, 0x6D, 0x60, 0xE0, 0x08, ++0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, 0x0C, 0x24, 0x87, 0xF8, ++0xE6, 0xAE, 0x0C, 0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, 0xF8, 0xE5, 0x81, 0x6D, ++0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x86, 0xC8, 0xF6, 0x15, 0x0C, ++0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, 0xE6, 0x30, 0xE0, 0x03, ++0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, 0x08, 0x54, 0xF4, 0x54, ++0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x86, 0xA6, 0x81, 0x74, 0x02, 0x60, ++0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80, 0xF6, 0x08, 0xF6, 0x08, ++0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x47, 0x69, 0x74, 0x01, 0x93, 0xC0, 0xE0, 0xE4, 0x93, ++0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, 0x8C, 0xD2, 0xAF, 0x22, ++0x02, 0xEF, 0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, 0x2F, 0x2F, 0xF8, 0xE6, ++0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, 0x0C, 0xEE, 0xC3, 0x9F, ++0x50, 0x21, 0x0E, 0x74, 0x86, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, 0xBE, 0x02, 0x02, 0x74, ++0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, 0x09, 0x80, 0xF3, 0x16, ++0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, 0xEE, 0xD3, 0x9F, 0x40, ++0x22, 0x74, 0x86, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, 0xA9, 0x81, 0x18, 0x06, ++0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, 0xF7, 0x19, 0x80, 0xF3, ++0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x86, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, 0x04, 0x90, 0x47, 0x69, ++0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x02, 0x40, 0x03, ++0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x54, ++0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x86, 0x2F, 0xF8, 0xE6, 0xF5, 0x81, ++0x02, 0x44, 0x79, 0x50, 0x2E, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xBF, 0x02, 0x02, 0x74, 0xFF, 0xFD, ++0x18, 0xE6, 0xF9, 0x74, 0x86, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C, 0x60, 0x08, 0xA8, 0x05, ++0xE7, 0xF6, 0x1D, 0x19, 0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5, 0x0C, 0xB5, 0x07, 0xE3, ++0x7F, 0x00, 0x22, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01, 0x0F, 0x74, 0x86, 0x2F, ++0xF8, 0xA6, 0x01, 0x08, 0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC, 0x81, 0xED, 0x6C, 0x60, ++0x08, 0x0D, 0x09, 0xA8, 0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5, 0x07, 0xDE, 0x89, 0x81, ++0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, ++0xF8, 0xC2, 0xAF, 0xE6, 0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4, 0xD2, 0xE2, 0xC6, 0xD2, ++0xAF, 0x7F, 0x00, 0x30, 0xE2, 0x01, 0x0F, 0x02, 0x44, 0x78, 0x8F, 0xF0, 0xE4, 0xFF, 0xFE, 0xE5, ++0x0C, 0x23, 0x24, 0x80, 0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08, 0xE6, 0x60, 0x0B, 0x2D, ++0xF6, 0x60, 0x30, 0x50, 0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6, 0x60, 0x25, 0x7E, 0x02, ++0x08, 0x30, 0xF0, 0x10, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30, 0xE2, 0x0C, 0xD2, 0xAF, ++0x7F, 0x04, 0x80, 0x12, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC, 0x4E, 0xF6, 0xD2, 0xAF, ++0x02, 0x44, 0x79, 0x7F, 0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF, 0x56, 0xC6, 0xD2, 0xAF, ++0x54, 0x80, 0x4F, 0xFF, 0x22, 0x02, 0x47, 0x13, 0x02, 0x45, 0x09, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, ++0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, 0x93, 0xA3, ++0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, ++0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, ++0x20, 0x40, 0x80, 0x90, 0x47, 0x58, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, 0x54, 0x3F, ++0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, 0x93, 0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, ++0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93, 0xA3, 0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, ++0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, ++0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, 0xBE, 0x00, 0x41, 0x83, 0x23, 0x00, 0x41, 0x83, 0x24, ++0x00, 0x41, 0x83, 0x37, 0x00, 0x41, 0x83, 0x38, 0x00, 0x59, 0x22, 0x5F, 0xE0, 0x63, 0x3F, 0xC0, ++0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, ++0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, ++0x6F, 0xF0, 0x74, 0x47, 0xA3, 0xF0, 0xF1, 0xBE, 0x74, 0x6F, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, ++0x47, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, ++0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x00, ++0x54, 0xE0, 0x55, 0x35, 0xF5, 0x39, 0xA3, 0xE0, 0x55, 0x36, 0xF5, 0x3A, 0xA3, 0xE0, 0x55, 0x37, ++0xF5, 0x3B, 0xA3, 0xE0, 0x55, 0x38, 0xF5, 0x3C, 0xAD, 0x39, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0xAD, ++0x3A, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0xAD, 0x3B, 0x7F, 0x56, 0x12, 0x32, 0x1E, 0xAD, 0x3C, 0x7F, ++0x57, 0x12, 0x32, 0x1E, 0x53, 0x91, 0xEF, 0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, ++0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, ++0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xF8, 0xF0, 0x74, 0x47, 0xA3, 0xF0, 0x12, ++0x6E, 0x11, 0xE5, 0x41, 0x30, 0xE3, 0x02, 0x71, 0x8D, 0xE5, 0x41, 0x30, 0xE4, 0x02, 0x71, 0x66, ++0xE5, 0x43, 0x30, 0xE0, 0x02, 0x11, 0x90, 0xE5, 0x43, 0x30, 0xE1, 0x03, 0x12, 0x5B, 0x66, 0xE5, ++0x43, 0x30, 0xE2, 0x03, 0x12, 0x5A, 0xAD, 0xE5, 0x43, 0x30, 0xE3, 0x02, 0xF1, 0x53, 0xE5, 0x43, ++0x30, 0xE4, 0x02, 0xF1, 0x97, 0xE5, 0x43, 0x30, 0xE5, 0x02, 0x91, 0x36, 0xE5, 0x43, 0x30, 0xE6, ++0x02, 0xF1, 0x38, 0xE5, 0x44, 0x30, 0xE1, 0x02, 0x71, 0x7A, 0x74, 0xF8, 0x04, 0x90, 0x01, 0xC4, ++0xF0, 0x74, 0x47, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, ++0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, ++0xE4, 0xFF, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x77, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x6F, ++0x90, 0x81, 0x3A, 0xE0, 0xC4, 0x54, 0x0F, 0x60, 0x24, 0x24, 0xFE, 0x60, 0x03, 0x04, 0x70, 0x1F, ++0x90, 0x81, 0x42, 0xE0, 0x14, 0xF0, 0xE0, 0xFE, 0x60, 0x06, 0x90, 0x81, 0x44, 0xE0, 0x60, 0x0F, ++0xEE, 0x70, 0x06, 0x90, 0x81, 0x41, 0xE0, 0xA3, 0xF0, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x01, 0xEF, ++0x60, 0x3D, 0x90, 0x81, 0x3F, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x81, 0x44, 0xE0, 0x60, 0x03, 0xB4, ++0x01, 0x09, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x44, 0xE0, 0x80, 0x0D, 0xE4, 0xF5, 0x1D, 0x90, 0x81, ++0x44, 0xE0, 0x75, 0xF0, 0x03, 0xA4, 0x24, 0xFE, 0xFF, 0x90, 0x81, 0x43, 0xE0, 0x2F, 0xD1, 0xD4, ++0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x3E, 0xE0, 0x20, 0xE2, 0x02, 0x31, 0x10, 0x22, ++0x7D, 0x01, 0x7F, 0x04, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, 0x36, 0xED, 0xF0, ++0x90, 0x81, 0x38, 0xE0, 0xFE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x02, 0x41, 0x5D, 0xEE, ++0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x02, 0x41, 0x5D, 0x90, 0x81, 0x3E, 0xE0, 0xFE, ++0x6F, 0x70, 0x02, 0x41, 0x5D, 0xEF, 0x70, 0x02, 0x21, 0xD4, 0x24, 0xFE, 0x70, 0x02, 0x41, 0x0E, ++0x24, 0xFE, 0x60, 0x48, 0x24, 0xFC, 0x70, 0x02, 0x41, 0x48, 0x24, 0xFC, 0x60, 0x02, 0x41, 0x5D, ++0xEE, 0xB4, 0x0E, 0x02, 0x51, 0xCE, 0x90, 0x81, 0x3E, 0xE0, 0x70, 0x04, 0x7F, 0x01, 0x51, 0xF6, ++0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x06, 0x02, 0x51, 0xA8, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x04, 0x0E, ++0x90, 0x83, 0x36, 0xE0, 0xFF, 0x60, 0x05, 0x12, 0x72, 0x2D, 0x80, 0x02, 0xF1, 0xD6, 0x90, 0x81, ++0x3E, 0xE0, 0x64, 0x08, 0x60, 0x02, 0x41, 0x5D, 0x71, 0x99, 0x41, 0x5D, 0x90, 0x81, 0x3E, 0xE0, ++0x70, 0x04, 0x7F, 0x01, 0x51, 0xF6, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x06, 0x02, 0x51, 0xA8, 0x90, ++0x81, 0x3E, 0xE0, 0xB4, 0x0E, 0x07, 0x51, 0x62, 0xBF, 0x01, 0x02, 0x51, 0xCE, 0x90, 0x81, 0x3E, ++0xE0, 0x64, 0x0C, 0x60, 0x02, 0x41, 0x5D, 0x51, 0x62, 0xEF, 0x64, 0x01, 0x60, 0x02, 0x41, 0x5D, ++0x71, 0x0F, 0x41, 0x5D, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x0E, 0x07, 0x51, 0x62, 0xBF, 0x01, 0x02, ++0x51, 0xCE, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x06, 0x02, 0x51, 0xA8, 0x90, 0x81, 0x3E, 0xE0, 0xB4, ++0x0C, 0x07, 0x51, 0x62, 0xBF, 0x01, 0x02, 0x71, 0x0F, 0x90, 0x81, 0x3E, 0xE0, 0x64, 0x04, 0x70, ++0x5C, 0x12, 0x71, 0x7D, 0xEF, 0x64, 0x01, 0x70, 0x54, 0x12, 0x50, 0xD7, 0x80, 0x4F, 0x90, 0x81, ++0x3E, 0xE0, 0xB4, 0x0E, 0x07, 0x51, 0x62, 0xBF, 0x01, 0x02, 0x51, 0xCE, 0x90, 0x81, 0x3E, 0xE0, ++0xB4, 0x06, 0x02, 0x51, 0xA8, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x0C, 0x07, 0x51, 0x62, 0xBF, 0x01, ++0x02, 0x71, 0x0F, 0x90, 0x81, 0x3E, 0xE0, 0x70, 0x04, 0x7F, 0x01, 0x51, 0xF6, 0x90, 0x81, 0x3E, ++0xE0, 0xB4, 0x04, 0x19, 0xF1, 0xC9, 0x80, 0x15, 0x90, 0x81, 0x3E, 0xE0, 0xB4, 0x0C, 0x0E, 0x90, ++0x81, 0x39, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x02, 0x71, 0x83, 0xD0, 0xD0, 0x92, ++0xAF, 0x22, 0x12, 0x71, 0x64, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x01, 0xF0, ++0x80, 0x2D, 0x90, 0x81, 0x38, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x08, 0x90, 0x01, ++0xB8, 0x74, 0x02, 0xF0, 0x80, 0x19, 0x90, 0x81, 0x3D, 0xE0, 0xD3, 0x94, 0x04, 0x40, 0x08, 0x90, ++0x01, 0xB8, 0x74, 0x08, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, ++0x01, 0xB9, 0x74, 0x02, 0xF0, 0x7F, 0x00, 0x22, 0x90, 0x81, 0x39, 0xE0, 0x90, 0x06, 0x04, 0x20, ++0xE0, 0x0C, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x04, 0xF0, 0x80, 0x0A, 0xE0, 0x54, ++0x7F, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x0C, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, 0x81, ++0x39, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x08, 0x90, 0x81, 0x3E, 0x74, 0x0C, 0xF0, 0x80, 0x11, 0x90, ++0x06, 0x04, 0xE0, 0x44, 0x40, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x04, 0xF0, ++0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, 0x83, 0x35, 0xEF, 0xF0, 0x71, 0xA7, 0x90, 0x83, 0x35, ++0xE0, 0x60, 0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x04, 0xF0, 0x22, 0x90, ++0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x2D, 0x90, 0x81, 0x39, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x05, ++0x22, 0x74, 0x6F, 0xF0, 0x7F, 0x01, 0x91, 0x52, 0xBF, 0x01, 0x0E, 0x90, 0x81, 0x38, 0xE0, 0x44, ++0x80, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x0E, 0xF0, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, ++0x01, 0xB8, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x3B, 0xE0, 0x64, 0x01, 0x70, 0x18, 0x90, 0x81, 0x3A, ++0xE0, 0x54, 0x0F, 0x60, 0x08, 0xE4, 0xFD, 0x7F, 0x0C, 0x31, 0x14, 0x81, 0x8E, 0x90, 0x81, 0x3E, ++0xE0, 0x70, 0x02, 0x31, 0x10, 0x22, 0x12, 0x6B, 0x60, 0x7F, 0x02, 0x8F, 0x1F, 0x7F, 0x02, 0x12, ++0x46, 0x53, 0x90, 0x80, 0x01, 0xE0, 0x45, 0x1F, 0xF0, 0x22, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x02, ++0x71, 0x45, 0x22, 0x12, 0x5C, 0xFE, 0x90, 0x81, 0x3E, 0x74, 0x08, 0xF0, 0x22, 0x90, 0x81, 0x53, ++0xE0, 0x30, 0xE0, 0x04, 0x7F, 0x10, 0x71, 0x6B, 0x22, 0x71, 0xA7, 0x90, 0x05, 0x22, 0xE4, 0xF0, ++0x90, 0x81, 0x3E, 0x74, 0x0C, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x01, ++0x01, 0xE0, 0x44, 0x02, 0xF0, 0x90, 0x01, 0x00, 0x74, 0xFF, 0xF0, 0x90, 0x06, 0xB7, 0x74, 0x09, ++0xF0, 0x90, 0x06, 0xB4, 0x74, 0x86, 0xF0, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x54, ++0x7F, 0xFC, 0x90, 0x83, 0x11, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x11, 0x12, 0x42, 0x26, 0x90, 0x85, ++0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, ++0xDA, 0xCC, 0xC0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, ++0x20, 0xDA, 0x00, 0xC0, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, 0x90, 0x83, 0x03, ++0x12, 0x20, 0xDA, 0x00, 0x03, 0x3E, 0x60, 0xE4, 0xFD, 0xFF, 0xF1, 0x74, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0x91, 0x8E, 0x90, 0x81, 0x3E, 0xE0, 0x64, 0x0C, 0x60, 0x0A, 0xE4, 0xFD, 0x7F, 0x0C, 0x31, ++0x14, 0xE4, 0xFF, 0x91, 0x52, 0x22, 0x90, 0x80, 0xF7, 0xE0, 0xB4, 0x01, 0x14, 0x90, 0x81, 0x3B, ++0xE0, 0x60, 0x0E, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x02, 0xC1, 0xB2, 0x91, ++0x21, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x8F, 0x4E, 0x90, 0x04, 0x1D, 0xE0, 0x60, ++0x1E, 0x90, 0x05, 0x22, 0xE0, 0xF5, 0x51, 0x74, 0xFF, 0xF0, 0x12, 0x6F, 0xBF, 0xBF, 0x01, 0x07, ++0xAF, 0x4E, 0x12, 0x73, 0x0F, 0xB1, 0x1A, 0x90, 0x05, 0x22, 0xE5, 0x51, 0xF0, 0x80, 0x02, 0xB1, ++0x1A, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, ++0x38, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x05, 0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, ++0x06, 0x92, 0x74, 0x02, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, ++0x4E, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0xD1, ++0xDD, 0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0x74, ++0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0x3F, 0xF0, 0xEF, 0x60, 0x1D, ++0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x10, 0xF0, 0x74, 0x1F, ++0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0x22, 0x74, 0x21, 0x2D, ++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xEF, 0xF0, 0x74, 0x1F, 0x2D, 0xF5, 0x82, ++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x40, 0xF0, 0x22, 0x90, 0x80, 0x08, 0xE0, 0xFF, 0x7D, ++0x01, 0xB1, 0xB7, 0x8E, 0x4F, 0x8F, 0x50, 0xAD, 0x50, 0xAC, 0x4F, 0xAF, 0x4E, 0x91, 0xCF, 0xAF, ++0x50, 0xAE, 0x4F, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F, 0xFD, 0xAC, 0x07, 0x74, 0x11, 0x2C, 0xF5, ++0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, 0xF0, 0x74, 0x11, 0x2C, 0xF5, 0x82, 0xE4, ++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, 0x07, 0x74, 0x16, 0x2C, 0xF5, 0x82, 0xE4, ++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, 0x15, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, ++0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, 0x06, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, ++0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53, 0xE4, 0xF0, 0x90, 0x04, 0x52, 0xF0, 0x90, ++0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74, 0xFD, 0xF0, 0x74, 0x14, 0x2C, 0xF5, 0x82, ++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, 0xFD, 0x74, 0x14, 0x2F, 0xF5, 0x82, 0xE4, ++0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, ++0x28, 0xED, 0xF0, 0x90, 0x83, 0x27, 0xEF, 0xF0, 0xE4, 0xFD, 0xFC, 0x12, 0x5E, 0x61, 0x7C, 0x00, ++0xAD, 0x07, 0x90, 0x83, 0x27, 0xE0, 0x90, 0x04, 0x25, 0xF0, 0x90, 0x83, 0x28, 0xE0, 0x60, 0x0E, ++0x74, 0x0F, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0xAF, 0x05, ++0x74, 0x08, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x09, 0x2F, 0xF5, ++0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF0, 0xF0, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, ++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF7, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x12, 0x90, 0x06, 0x92, 0xE0, 0x30, 0xE1, 0x02, 0x81, 0x8E, ++0x90, 0x81, 0x38, 0xE0, 0x54, 0xF7, 0xF0, 0xD1, 0x3A, 0x22, 0x90, 0x81, 0x3D, 0xE0, 0xFF, 0x7D, ++0x01, 0x21, 0x14, 0xE4, 0x90, 0x82, 0x71, 0xF0, 0x90, 0x06, 0xA9, 0xE0, 0x90, 0x82, 0x71, 0xF0, ++0xE0, 0x54, 0xC0, 0x70, 0x0C, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x80, ++0xD9, 0x90, 0x82, 0x71, 0xE0, 0x30, 0xE6, 0x21, 0x90, 0x81, 0x3B, 0xE0, 0x64, 0x01, 0x70, 0x20, ++0x90, 0x81, 0x3F, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, ++0x04, 0xD1, 0xB2, 0x80, 0x0B, 0x91, 0x21, 0x80, 0x07, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, 0xF0, ++0x90, 0x82, 0x71, 0xE0, 0x90, 0x81, 0x3F, 0x30, 0xE7, 0x13, 0xE0, 0x44, 0x02, 0xD1, 0xCC, 0x90, ++0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0xE0, 0x54, 0xFD, ++0xF0, 0x22, 0x90, 0x04, 0x1D, 0xE0, 0x70, 0x13, 0x90, 0x80, 0x07, 0xE0, 0xFF, 0xE4, 0xFD, 0xB1, ++0xB7, 0x8E, 0x0D, 0x8F, 0x0E, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x22, 0xF0, 0xE4, 0xF5, 0x1D, ++0x90, 0x81, 0x4D, 0xE0, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x54, 0x7E, 0x01, 0x8E, 0x19, 0x8F, ++0x1A, 0xE5, 0x1E, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0x85, 0x19, 0x83, 0x85, 0x1A, 0x82, 0xF0, ++0xE5, 0x1D, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0xFF, 0xE5, 0x1E, 0x13, 0x13, 0x13, 0x54, 0x1F, ++0x4F, 0xA3, 0xF0, 0xEB, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0xFF, 0xE5, 0x1D, 0x13, 0x13, 0x13, ++0x54, 0x1F, 0x4F, 0x85, 0x1A, 0x82, 0x85, 0x19, 0x83, 0xA3, 0xA3, 0xF0, 0xBD, 0x01, 0x0C, 0x85, ++0x1A, 0x82, 0x8E, 0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x03, 0xF0, 0x22, 0x85, 0x1A, 0x82, 0x85, 0x19, ++0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x80, 0xF7, 0xE0, 0xB4, 0x01, 0x13, 0x90, ++0x81, 0x3B, 0xE0, 0x60, 0x0D, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0x07, 0x70, 0x02, ++0xD1, 0x3A, 0x22, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x18, 0x90, 0x81, 0x3B, 0xE0, 0x60, ++0x12, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xD1, 0xCC, 0x90, 0x01, 0x57, ++0x74, 0x05, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xC0, 0x07, 0xC0, 0x05, 0x90, ++0x83, 0x03, 0x12, 0x42, 0x26, 0x90, 0x82, 0xF1, 0x12, 0x20, 0xCE, 0xD0, 0x05, 0xD0, 0x07, 0x12, ++0x69, 0x1D, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x25, 0x90, ++0x81, 0x3B, 0xE0, 0x60, 0x1F, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, ++0x90, 0x81, 0x38, 0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, ++0x70, 0x02, 0xD1, 0x3A, 0x22, 0xE4, 0xFF, 0x81, 0x52, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x90, ++0x81, 0x3E, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x05, 0x22, ++0xE4, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x0C, 0xF0, 0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, ++0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, ++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xE9, 0xF0, 0x74, 0x4F, 0xA3, 0xF0, ++0x12, 0x6E, 0x3E, 0xE5, 0x49, 0x30, 0xE1, 0x02, 0x11, 0x70, 0xE5, 0x49, 0x30, 0xE2, 0x03, 0x12, ++0x4E, 0x21, 0xE5, 0x4A, 0x30, 0xE0, 0x03, 0x12, 0x6E, 0x7D, 0xE5, 0x4C, 0x30, 0xE1, 0x05, 0x7F, ++0x04, 0x12, 0x4B, 0x6B, 0xE5, 0x4C, 0x30, 0xE4, 0x02, 0x11, 0x7A, 0xE5, 0x4C, 0x30, 0xE5, 0x02, ++0x11, 0xF4, 0xE5, 0x4C, 0x30, 0xE6, 0x03, 0x12, 0x6F, 0x1C, 0x74, 0xE9, 0x04, 0x90, 0x01, 0xC4, ++0xF0, 0x74, 0x4F, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, ++0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, ++0x90, 0x81, 0x3B, 0xE0, 0x60, 0x03, 0x12, 0x72, 0xB1, 0x22, 0x12, 0x72, 0x7B, 0x90, 0x81, 0x41, ++0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, 0x7D, 0x02, 0x7F, 0x02, 0x11, 0xC2, 0x90, 0x82, 0x65, 0xE0, ++0x30, 0xE0, 0x2E, 0x90, 0x80, 0xF7, 0xE0, 0xB4, 0x01, 0x27, 0x90, 0x83, 0x37, 0xE0, 0x04, 0xF0, ++0xE0, 0xB4, 0x0A, 0x0B, 0x90, 0x82, 0x67, 0xE0, 0x04, 0xF0, 0xE4, 0x90, 0x83, 0x37, 0xF0, 0x90, ++0x82, 0x67, 0xE0, 0xFF, 0x90, 0x82, 0x66, 0xE0, 0xB5, 0x07, 0x06, 0xE4, 0xA3, 0xF0, 0x12, 0x4F, ++0xC5, 0x22, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0x4D, 0xFE, 0xF6, 0x74, 0x30, 0x2F, 0xF5, 0x82, 0xE4, ++0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x12, 0x6F, 0xBF, ++0x90, 0x01, 0x37, 0x74, 0x02, 0xF0, 0xFD, 0x7F, 0x03, 0x11, 0xC2, 0x12, 0x5D, 0x04, 0xE4, 0x90, ++0x81, 0x3E, 0xF0, 0x22, 0x90, 0x81, 0x38, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, ++0x27, 0xEF, 0x54, 0xBF, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x39, 0x30, 0xE0, 0x06, 0xE0, ++0x44, 0x01, 0xF0, 0x80, 0x10, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, ++0x01, 0xB8, 0x74, 0x04, 0xF0, 0x12, 0x4E, 0x3A, 0xE4, 0xFF, 0x90, 0x82, 0x68, 0xE0, 0x30, 0xE0, ++0x48, 0x90, 0x82, 0x6C, 0xE0, 0xFD, 0x60, 0x41, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07, 0x08, 0x80, ++0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x04, 0xE0, 0xE0, 0xFB, 0xEF, 0x5B, ++0x60, 0x06, 0xE4, 0x90, 0x82, 0x6C, 0xF0, 0x22, 0x90, 0x82, 0x6A, 0xE0, 0xD3, 0x9D, 0x50, 0x10, ++0x90, 0x01, 0xC7, 0x74, 0x10, 0xF0, 0x31, 0x7A, 0x90, 0x82, 0x68, 0xE0, 0x54, 0xFE, 0xF0, 0x22, ++0x12, 0x4F, 0xC5, 0x90, 0x82, 0x6C, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x80, 0x05, 0xE0, 0xB4, 0x02, ++0x16, 0x90, 0x81, 0x55, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x0F, 0x90, ++0x01, 0x4D, 0xE0, 0x64, 0x80, 0xF0, 0x22, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x82, ++0x6F, 0xE0, 0x75, 0xF0, 0x20, 0xA4, 0xFF, 0x90, 0x83, 0x19, 0xE5, 0xF0, 0xF0, 0xA3, 0xEF, 0xF0, ++0x90, 0x82, 0x70, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0xAE, 0xF0, 0x90, 0x83, 0x1B, 0xF0, 0xEE, 0xA3, ++0xF0, 0x90, 0x82, 0x6E, 0xE0, 0xFE, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x77, 0xEE, ++0x54, 0x0F, 0xFF, 0xEE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D, 0x01, ++0x51, 0x47, 0x90, 0x82, 0x6E, 0xE0, 0xFE, 0x54, 0x0F, 0xFF, 0xEE, 0xC4, 0x13, 0x13, 0x54, 0x01, ++0xFD, 0x51, 0x47, 0x90, 0x82, 0x6E, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x22, 0x90, 0x83, ++0x19, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x6E, 0xE0, 0xFE, 0x54, 0x0F, ++0xFF, 0xEE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D, 0x01, 0x51, 0x47, ++0x90, 0x82, 0x6E, 0xE0, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x1C, 0x90, 0x83, 0x1C, 0xE0, 0xF5, 0x1D, ++0x90, 0x83, 0x1B, 0xE0, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x12, 0x4E, 0xDD, ++0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, ++0x2C, 0xED, 0xF0, 0x90, 0x83, 0x2B, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x70, 0xE0, 0xFF, 0x74, ++0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x47, 0xE0, ++0x5F, 0xFD, 0x7F, 0x47, 0x12, 0x32, 0x1E, 0x90, 0x83, 0x2B, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, ++0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x46, 0xE0, 0x4F, 0xFD, 0x7F, 0x46, ++0x12, 0x32, 0x1E, 0x90, 0x83, 0x2C, 0xE0, 0x60, 0x18, 0x90, 0x83, 0x2B, 0xE0, 0xFF, 0x74, 0x01, ++0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x4F, 0x80, ++0x17, 0x90, 0x83, 0x2B, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, ++0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x5F, 0xFD, 0x7F, 0x45, 0x80, 0x7E, 0x90, 0x83, 0x2B, ++0xE0, 0x24, 0xF8, 0xF0, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, ++0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x5F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, ++0x90, 0x83, 0x2B, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, ++0xFF, 0x90, 0x00, 0x43, 0xE0, 0x4F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, 0x90, 0x83, 0x2C, 0xE0, ++0x60, 0x1D, 0x90, 0x83, 0x2B, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, ++0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x4F, 0xFD, 0x7F, 0x42, 0x80, 0x1C, 0x90, ++0x83, 0x2B, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, ++0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x5F, 0xFD, 0x7F, 0x42, 0x12, 0x32, 0x1E, 0xD0, 0xD0, ++0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, 0x82, 0x74, 0x08, 0xF0, ++0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x82, 0x89, 0xF0, 0xA3, 0xF0, 0x90, ++0x01, 0x1F, 0xE0, 0xFE, 0x90, 0x01, 0x1E, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, ++0x82, 0x7B, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x02, 0x82, 0xE0, 0x90, 0x82, 0x81, 0xF0, 0x90, 0x81, ++0x53, 0xE0, 0x20, 0xE0, 0x02, 0xA1, 0xBD, 0x90, 0x81, 0x58, 0xE0, 0x20, 0xE0, 0x07, 0x90, 0x01, ++0x3F, 0xE0, 0x30, 0xE2, 0x17, 0x90, 0x80, 0x05, 0xE0, 0xB4, 0x01, 0x0E, 0x90, 0xFD, 0x01, 0xE0, ++0x20, 0xE6, 0x07, 0x90, 0xFD, 0x00, 0xE0, 0x44, 0x10, 0xF0, 0x31, 0x7A, 0xE4, 0x90, 0x82, 0x80, ++0xF0, 0x90, 0x82, 0x81, 0xE0, 0xFF, 0x90, 0x82, 0x80, 0xE0, 0xC3, 0x9F, 0x40, 0x02, 0xA1, 0xBD, ++0x90, 0x82, 0x7B, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xEC, 0xFF, 0x90, 0xFD, 0x11, 0xF0, 0xAE, 0x05, ++0xAB, 0x06, 0x90, 0x82, 0x84, 0xEF, 0xF0, 0x74, 0x02, 0x2B, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, ++0x83, 0xE0, 0x54, 0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xFF, 0x74, 0x03, 0x2B, 0xF5, 0x82, 0xE4, ++0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x03, 0xFE, 0xEF, 0x24, 0x18, 0x2E, 0x90, 0x82, 0x89, 0xF0, ++0xE0, 0xFF, 0x2B, 0xFA, 0x7E, 0x00, 0x90, 0x82, 0x7B, 0xE0, 0xFC, 0xA3, 0xE0, 0x2F, 0xFF, 0xEE, ++0x3C, 0xA3, 0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x00, 0x2A, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, ++0xE0, 0xFF, 0x54, 0xFC, 0x90, 0x82, 0x7F, 0xF0, 0x74, 0x04, 0x2A, 0xF5, 0x82, 0xE4, 0x34, 0xFB, ++0x12, 0x5E, 0x8E, 0x90, 0x82, 0x83, 0xEF, 0xF0, 0x74, 0x01, 0x2B, 0xF5, 0x82, 0xE4, 0x34, 0xFB, ++0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x00, 0x2B, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x7C, ++0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x54, 0x3F, 0xFE, 0x90, 0x82, 0x85, 0xF0, 0xA3, 0xEF, 0xF0, ++0x90, 0x82, 0x89, 0xE0, 0x2F, 0xFF, 0xEC, 0x3E, 0xFE, 0x12, 0x73, 0x6E, 0x74, 0x0F, 0x2B, 0xF5, ++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFD, 0x90, 0x82, 0x7B, 0xEE, 0x8F, 0xF0, 0x12, 0x41, ++0xF6, 0x90, 0x80, 0xF5, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x82, 0x7B, 0xE0, 0xF8, 0xA3, 0xE0, ++0xD3, 0x9F, 0xE8, 0x9E, 0x40, 0x26, 0x90, 0x82, 0x7B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x80, ++0xF5, 0xE0, 0xF8, 0xA3, 0xE0, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x38, 0xF5, 0x83, 0xC3, 0xEF, 0x95, ++0x82, 0xFF, 0xEE, 0x95, 0x83, 0x90, 0x82, 0x7B, 0xF0, 0xA3, 0xEF, 0xF0, 0xED, 0x30, 0xE7, 0x06, ++0x90, 0x01, 0xC7, 0x74, 0x21, 0xF0, 0xED, 0x30, 0xE6, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x22, 0xF0, ++0xED, 0x30, 0xE5, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x23, 0xF0, 0x90, 0x82, 0x7F, 0xE0, 0x24, 0x40, ++0x60, 0x04, 0x24, 0x20, 0x70, 0x20, 0x90, 0x81, 0x54, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, ++0x01, 0x30, 0xE0, 0x64, 0xAF, 0x02, 0x12, 0x75, 0xD9, 0xEF, 0x60, 0x5C, 0x90, 0x82, 0x7F, 0xE0, ++0xFF, 0x12, 0x75, 0xC2, 0x80, 0x52, 0x90, 0x82, 0x7D, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x82, ++0x83, 0xE0, 0xFD, 0x90, 0x82, 0x82, 0xE0, 0xFB, 0x90, 0x82, 0x84, 0xE0, 0x90, 0x82, 0x8F, 0xF0, ++0xB1, 0xC2, 0x90, 0x81, 0x53, 0xE0, 0xC3, 0x13, 0x30, 0xE0, 0x10, 0x90, 0x82, 0x7D, 0xE0, 0xFE, ++0xA3, 0xE0, 0xFF, 0x90, 0x82, 0x83, 0xE0, 0xFD, 0x12, 0x76, 0x14, 0x90, 0x81, 0x53, 0xE0, 0xFF, ++0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x0F, 0x90, 0x82, 0x7D, 0xE0, 0xFE, 0xA3, 0xE0, ++0xFF, 0x90, 0x82, 0x83, 0xE0, 0xFD, 0xD1, 0x9D, 0x90, 0x81, 0x58, 0xE0, 0x20, 0xE0, 0x07, 0x90, ++0x01, 0x3F, 0xE0, 0x30, 0xE2, 0x02, 0x31, 0x7A, 0x12, 0x75, 0x9C, 0xEF, 0x64, 0x01, 0x70, 0x3D, ++0xF1, 0xD8, 0x90, 0x82, 0x8A, 0xEF, 0xF0, 0x64, 0x01, 0x60, 0x25, 0x90, 0x81, 0x58, 0xE0, 0x44, ++0x01, 0xF0, 0x90, 0x82, 0x8A, 0xE0, 0xFF, 0xB4, 0x02, 0x08, 0x90, 0x01, 0xC7, 0x74, 0x42, 0xF0, ++0x80, 0x0A, 0xEF, 0xB4, 0x04, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x43, 0xF0, 0x31, 0x7A, 0x80, 0x0D, ++0x90, 0x82, 0x7B, 0xF1, 0xC5, 0x90, 0x82, 0x80, 0xE0, 0x04, 0xF0, 0x61, 0xC1, 0xD0, 0xD0, 0x92, ++0xAF, 0x22, 0x90, 0x82, 0x8D, 0xED, 0xF0, 0xA3, 0xEB, 0xF0, 0x90, 0x82, 0x8B, 0xEE, 0xF0, 0xA3, ++0xEF, 0xF0, 0xE4, 0xFD, 0xD1, 0x5F, 0xEF, 0x54, 0x0C, 0x64, 0x08, 0x70, 0x6F, 0x90, 0x82, 0x8B, ++0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x24, 0x06, 0xFD, 0xD1, 0x5F, 0xEF, 0x64, 0x88, 0x70, ++0x5B, 0x90, 0x82, 0x8B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x24, 0x07, 0xFD, 0xD1, 0x5F, ++0xEF, 0x64, 0x8E, 0x70, 0x47, 0x90, 0x82, 0x8B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x82, 0x8E, ++0xE0, 0xFD, 0x90, 0x82, 0x8D, 0xE0, 0x2D, 0x04, 0xFD, 0xD1, 0x5F, 0xEF, 0x64, 0x03, 0x70, 0x2C, ++0x90, 0x82, 0x8B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x82, 0x8E, 0xE0, 0xFD, 0x90, 0x82, 0x8D, ++0xE0, 0x2D, 0x24, 0x06, 0xFD, 0xD1, 0x5F, 0xEF, 0x90, 0x01, 0xC7, 0x30, 0xE3, 0x04, 0x74, 0x01, ++0x80, 0x02, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x58, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xFD, 0x90, 0x82, ++0x8B, 0xE0, 0x34, 0x00, 0xFC, 0x7E, 0x00, 0xED, 0x2F, 0xFF, 0xEE, 0x3C, 0xFE, 0xE4, 0xFD, 0xAB, ++0x07, 0xAA, 0x06, 0xED, 0x2B, 0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90, 0x80, 0xF6, 0xE0, 0x9B, 0x90, ++0x80, 0xF5, 0xE0, 0x9A, 0x50, 0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0xF5, 0xE0, 0x34, ++0x00, 0xFE, 0xC3, 0xEB, 0x9F, 0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, ++0x74, 0x00, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x22, 0x90, 0x82, 0x8B, ++0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x78, 0x8E, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, ++0x7A, 0x40, 0x79, 0xCE, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x41, 0xD0, 0x78, 0x95, 0x7C, 0x82, 0x7D, ++0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, 0xD4, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x41, 0xD0, 0xE4, 0x90, ++0x82, 0x94, 0xF0, 0x90, 0x82, 0x94, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x50, 0x1F, 0x90, 0x82, 0x8C, ++0xE0, 0x24, 0x04, 0xD1, 0x4D, 0x90, 0x82, 0x94, 0xE0, 0x24, 0x8E, 0xF5, 0x82, 0xE4, 0x34, 0x82, ++0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x94, 0xE0, 0x04, 0xF0, 0x80, 0xD7, 0xE4, 0x90, 0x82, 0x94, ++0xF0, 0x90, 0x82, 0x94, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x2E, 0x90, 0x82, 0x8D, 0xE0, 0xFD, ++0x90, 0x82, 0x8C, 0xE0, 0x2D, 0xFD, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCD, 0x24, 0x18, 0xCD, ++0xD1, 0x52, 0x90, 0x82, 0x94, 0xE0, 0x24, 0x95, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xEF, ++0xF0, 0x90, 0x82, 0x94, 0xE0, 0x04, 0xF0, 0x80, 0xC8, 0x78, 0x8E, 0x7C, 0x82, 0x7D, 0x01, 0x7B, ++0x01, 0x7A, 0x81, 0x79, 0x59, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x44, 0x08, 0xEF, 0x70, 0x75, 0x90, ++0x82, 0x8B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xE4, 0xFD, 0xD1, 0x5F, 0xEF, 0x54, 0x0C, 0x64, 0x08, ++0x70, 0x62, 0x90, 0x82, 0x8D, 0xE0, 0xFF, 0x90, 0x82, 0x8C, 0xE0, 0x2F, 0xFF, 0x90, 0x82, 0x8B, ++0xE0, 0x34, 0x00, 0xCF, 0x24, 0x06, 0xCF, 0x34, 0x00, 0xFE, 0xE4, 0xFD, 0xD1, 0x5F, 0xEF, 0x64, ++0x08, 0x70, 0x41, 0x90, 0x82, 0x8D, 0xE0, 0xFF, 0x90, 0x82, 0x8C, 0xE0, 0x2F, 0xFF, 0x90, 0x82, ++0x8B, 0xE0, 0x34, 0x00, 0xCF, 0x24, 0x07, 0xCF, 0x34, 0x00, 0xFE, 0xE4, 0xFD, 0xD1, 0x5F, 0xEF, ++0x70, 0x22, 0x78, 0x95, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x6C, 0xFE, 0x7F, ++0x04, 0x12, 0x44, 0x08, 0xEF, 0x70, 0x0D, 0x90, 0x01, 0xC7, 0x74, 0x22, 0xF0, 0x90, 0x81, 0x58, ++0xE0, 0x44, 0x01, 0xF0, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x02, 0x84, 0xEF, 0xF0, 0xEE, ++0xA3, 0xF0, 0xA3, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE2, 0x03, 0x7F, ++0x04, 0x22, 0x90, 0x02, 0x86, 0xE0, 0x7F, 0x01, 0x20, 0xE1, 0x02, 0x7F, 0x02, 0x22, 0x90, 0x00, ++0xF7, 0xE0, 0x20, 0xE7, 0x09, 0xE0, 0x7F, 0x01, 0x20, 0xE6, 0x0C, 0x7F, 0x02, 0x22, 0x90, 0x00, ++0xF7, 0xE0, 0x30, 0xE6, 0x02, 0x7F, 0x03, 0x22, 0x12, 0x57, 0xEE, 0x90, 0x80, 0x05, 0xEF, 0xF0, ++0x11, 0x1B, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0, 0x02, 0x2D, 0xA7, 0x11, 0x86, 0x11, 0xB6, 0x11, ++0x48, 0x11, 0x67, 0xE4, 0xF5, 0x35, 0xF5, 0x36, 0xF5, 0x37, 0xF5, 0x38, 0xAD, 0x35, 0x7F, 0x50, ++0x12, 0x32, 0x1E, 0xAD, 0x36, 0x7F, 0x51, 0x12, 0x32, 0x1E, 0xAD, 0x37, 0x7F, 0x52, 0x12, 0x32, ++0x1E, 0xAD, 0x38, 0x7F, 0x53, 0x02, 0x32, 0x1E, 0x75, 0x3D, 0x10, 0xE4, 0xF5, 0x3E, 0x75, 0x3F, ++0x07, 0x75, 0x40, 0x02, 0x90, 0x01, 0x30, 0xE5, 0x3D, 0xF0, 0xA3, 0xE5, 0x3E, 0xF0, 0xA3, 0xE5, ++0x3F, 0xF0, 0xA3, 0xE5, 0x40, 0xF0, 0x22, 0x75, 0x45, 0x06, 0x75, 0x46, 0x01, 0x75, 0x47, 0x03, ++0x75, 0x48, 0x62, 0x90, 0x01, 0x38, 0xE5, 0x45, 0xF0, 0xA3, 0xE5, 0x46, 0xF0, 0xA3, 0xE5, 0x47, ++0xF0, 0xA3, 0xE5, 0x48, 0xF0, 0x22, 0x90, 0x01, 0x30, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, ++0xF0, 0x90, 0x01, 0x38, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x50, 0x12, 0x32, ++0x1E, 0xE4, 0xFD, 0x7F, 0x51, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xE4, ++0xFD, 0x7F, 0x53, 0x02, 0x32, 0x1E, 0x90, 0x01, 0x34, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, ++0xA3, 0xF0, 0x90, 0x01, 0x3C, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x54, 0x12, ++0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x56, 0x12, 0x32, 0x1E, ++0x7D, 0xFF, 0x7F, 0x57, 0x02, 0x32, 0x1E, 0x90, 0x01, 0xCF, 0xE0, 0x90, 0x83, 0x34, 0xF0, 0xE0, ++0xFF, 0x30, 0xE0, 0x07, 0x90, 0x01, 0xCF, 0xE0, 0x54, 0xFE, 0xF0, 0xEF, 0x30, 0xE5, 0x22, 0x90, ++0x01, 0xCF, 0xE0, 0x54, 0xDF, 0xF0, 0x90, 0x01, 0x34, 0x74, 0x20, 0xF0, 0xE4, 0xF5, 0xA8, 0xF5, ++0xE8, 0x11, 0x86, 0x90, 0x00, 0x03, 0xE0, 0x54, 0xFB, 0xFD, 0x7F, 0x03, 0x12, 0x32, 0x1E, 0x80, ++0xFE, 0x22, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x80, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x90, 0xFD, ++0x00, 0xE0, 0x54, 0xBF, 0xF0, 0xF1, 0xC5, 0x12, 0x32, 0x77, 0xF1, 0x8C, 0xF1, 0xB9, 0x7F, 0x01, ++0x12, 0x45, 0x41, 0x90, 0x82, 0x64, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x45, 0x41, 0x90, 0x82, 0x64, ++0xE0, 0x04, 0xF0, 0x11, 0x08, 0x31, 0x71, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x40, 0xFD, 0x7F, 0x80, ++0x12, 0x32, 0x1E, 0x75, 0x20, 0xFF, 0xF1, 0xA1, 0xF1, 0xA8, 0xF1, 0xAF, 0xE4, 0xFF, 0x02, 0x45, ++0xCA, 0xF1, 0x8F, 0xF1, 0xD2, 0x12, 0x70, 0x81, 0x31, 0x94, 0x12, 0x73, 0x5C, 0x12, 0x65, 0x97, ++0x90, 0x82, 0x6E, 0xE0, 0x54, 0x7F, 0xF0, 0x54, 0xBF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xF0, 0xF0, ++0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x53, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x81, 0x58, 0xE0, 0x54, ++0xFE, 0xF0, 0xE4, 0x90, 0x81, 0x65, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, ++0xF0, 0xA3, 0xF0, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x20, 0xF0, 0x90, 0x81, 0x54, 0xE0, 0x54, 0xFE, ++0xF0, 0x54, 0xFD, 0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, ++0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0xE0, 0x54, 0x80, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xE0, ++0x54, 0xFE, 0xF0, 0x90, 0x81, 0x55, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x81, 0x57, 0xE0, 0x54, 0xFD, ++0xF0, 0x22, 0xEF, 0x60, 0x57, 0x90, 0x04, 0xEC, 0xE0, 0x54, 0xDD, 0xF0, 0x90, 0x82, 0x57, 0xE0, ++0xFF, 0x60, 0x02, 0x51, 0x6D, 0x90, 0x01, 0xC7, 0xE4, 0xF0, 0x90, 0x01, 0x17, 0xE0, 0xFE, 0x90, ++0x01, 0x16, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x80, 0xF5, 0xF0, 0xA3, 0xEF, ++0xF0, 0x90, 0x06, 0x09, 0xE0, 0x54, 0xFE, 0xF0, 0x91, 0xFE, 0x90, 0x02, 0x86, 0xE0, 0x44, 0x04, ++0xF0, 0x91, 0xC3, 0xF1, 0x8D, 0x12, 0x4B, 0xA7, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x12, 0x78, 0xB3, ++0x90, 0x01, 0x34, 0x74, 0x08, 0xF0, 0xFD, 0xE4, 0xFF, 0x02, 0x50, 0xC2, 0x90, 0x04, 0xEC, 0xE0, ++0x44, 0x22, 0xF0, 0x7D, 0x08, 0xE4, 0xFF, 0x51, 0x95, 0x90, 0x06, 0x90, 0xE0, 0x54, 0xF0, 0xF0, ++0x90, 0x02, 0x86, 0xE0, 0x54, 0xFB, 0xF0, 0x91, 0x70, 0xF1, 0x8E, 0x21, 0x94, 0xD1, 0x61, 0x7E, ++0x00, 0x74, 0x00, 0x2F, 0xF9, 0xE4, 0x34, 0xFC, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, ++0x16, 0x08, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x71, 0x02, 0x2B, 0xED, 0x7D, 0x02, 0x7F, 0x02, 0x51, ++0x95, 0x7D, 0x01, 0x7F, 0x02, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, 0xF6, ++0x74, 0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0x90, 0x82, 0x6D, ++0xE0, 0x04, 0xF0, 0x90, 0x81, 0x3E, 0xE0, 0x64, 0x02, 0x60, 0x28, 0x71, 0xB7, 0x90, 0x81, 0x39, ++0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x14, 0x90, 0x81, 0x41, 0xE0, 0xFF, 0xA3, 0xE0, ++0x6F, 0x70, 0x0A, 0x91, 0x4C, 0x51, 0x8B, 0x90, 0x81, 0x42, 0xE0, 0x14, 0xF0, 0x90, 0x01, 0xE6, ++0xE0, 0x04, 0xF0, 0x22, 0xEF, 0x70, 0x34, 0x7D, 0x78, 0x7F, 0x02, 0x51, 0x95, 0x7D, 0x02, 0x7F, ++0x03, 0x51, 0x95, 0x7D, 0xC8, 0x7F, 0x02, 0x12, 0x70, 0x07, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, ++0x01, 0x3C, 0x74, 0x02, 0xF0, 0x7D, 0x01, 0x7F, 0x0C, 0x12, 0x49, 0x14, 0x90, 0x81, 0x38, 0xE0, ++0x54, 0xF7, 0xF0, 0x90, 0x06, 0x0A, 0xE0, 0x54, 0xF8, 0xF0, 0x22, 0x90, 0x01, 0x36, 0x74, 0x78, ++0xF0, 0xA3, 0x74, 0x02, 0xF0, 0x7D, 0x78, 0xFF, 0x12, 0x50, 0xC2, 0x7D, 0x02, 0x7F, 0x03, 0x12, ++0x50, 0xC2, 0x90, 0x06, 0x0A, 0xE0, 0x44, 0x07, 0xF0, 0x90, 0x81, 0x46, 0xA3, 0xE0, 0x90, 0x05, ++0x58, 0xF0, 0x90, 0x80, 0xF7, 0xE0, 0xB4, 0x01, 0x15, 0x90, 0x81, 0x39, 0xE0, 0x54, 0xFB, 0xF0, ++0x90, 0x81, 0x3E, 0xE0, 0x20, 0xE2, 0x0E, 0x7D, 0x01, 0x7F, 0x04, 0x02, 0x49, 0x14, 0x90, 0x81, ++0x39, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x45, 0x90, 0x81, 0x39, 0xE0, ++0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x12, 0x90, 0x01, 0x3B, 0xE0, 0x30, 0xE4, 0x0B, ++0x51, 0x8B, 0x90, 0x81, 0x41, 0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, 0x90, 0x83, 0x25, 0xE4, 0x75, ++0xF0, 0x01, 0x12, 0x41, 0xF6, 0xC3, 0x90, 0x83, 0x26, 0xE0, 0x94, 0x80, 0x90, 0x83, 0x25, 0xE0, ++0x64, 0x80, 0x94, 0x80, 0x40, 0x0B, 0x90, 0x01, 0x98, 0xE0, 0x54, 0xFE, 0xF0, 0xE0, 0x44, 0x01, ++0xF0, 0x12, 0x78, 0xEB, 0x02, 0x50, 0x8C, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x60, 0x02, 0x81, ++0x4B, 0x90, 0x81, 0x3B, 0xE0, 0x70, 0x02, 0x81, 0x4B, 0x90, 0x81, 0x3A, 0xE0, 0xC4, 0x54, 0x0F, ++0x64, 0x01, 0x70, 0x22, 0x90, 0x06, 0xAB, 0xE0, 0x90, 0x81, 0x42, 0xF0, 0x90, 0x06, 0xAA, 0xE0, ++0x90, 0x81, 0x41, 0xF0, 0xA3, 0xE0, 0xFF, 0x70, 0x08, 0x90, 0x81, 0x41, 0xE0, 0xFE, 0xFF, 0x80, ++0x00, 0x90, 0x81, 0x42, 0xEF, 0xF0, 0x90, 0x81, 0x39, 0xE0, 0x44, 0x04, 0xF0, 0xE4, 0x90, 0x81, ++0x44, 0xF0, 0x90, 0x81, 0x46, 0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x01, 0x57, 0xE4, 0xF0, ++0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xEF, 0xF0, ++0x90, 0x81, 0x3A, 0xE0, 0xFF, 0xC4, 0x54, 0x0F, 0x24, 0xFD, 0x50, 0x02, 0x80, 0x03, 0x12, 0x4E, ++0x43, 0x90, 0x81, 0x39, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x0E, 0x90, 0x81, 0x41, ++0xE0, 0xFF, 0xA3, 0xE0, 0xB5, 0x07, 0x04, 0x91, 0x4C, 0x51, 0x91, 0x22, 0xEF, 0x14, 0x90, 0x05, ++0x73, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0, 0xFD, 0x7F, 0x03, 0x74, 0x45, 0x2F, 0xF8, 0xE6, ++0x4D, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, ++0x31, 0xBA, 0x90, 0x01, 0x3F, 0x74, 0x04, 0xF0, 0x90, 0x80, 0x05, 0xE0, 0xFF, 0xB4, 0x01, 0x07, ++0x90, 0xFD, 0x00, 0xE0, 0x54, 0xEF, 0xF0, 0xEF, 0xB4, 0x01, 0x07, 0x90, 0xFE, 0x10, 0xE0, 0x54, ++0xFB, 0xF0, 0x22, 0x90, 0x82, 0x7E, 0x12, 0x42, 0x53, 0x12, 0x71, 0x53, 0x90, 0x81, 0x3B, 0xE0, ++0xFF, 0x51, 0xE4, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x19, 0x90, 0x82, 0x7E, 0x12, 0x42, 0x4A, 0x90, ++0x00, 0x01, 0x12, 0x1F, 0xBD, 0x54, 0x0F, 0xFF, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFD, 0x12, ++0x71, 0xFC, 0x22, 0x12, 0x57, 0xD8, 0xAD, 0x07, 0xEF, 0x64, 0x01, 0x60, 0x20, 0x90, 0x81, 0x58, ++0xE0, 0x44, 0x01, 0xF0, 0xED, 0xB4, 0x02, 0x08, 0x90, 0x01, 0xC7, 0x74, 0x40, 0xF0, 0x80, 0x0A, ++0xED, 0xB4, 0x04, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x41, 0xF0, 0x02, 0x51, 0x7A, 0x12, 0x73, 0x97, ++0x90, 0x02, 0x87, 0xE0, 0x70, 0xF7, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x02, 0xF0, 0x22, 0x90, 0x05, ++0x22, 0x74, 0xFF, 0xF0, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x6F, 0xBF, 0x90, 0x85, ++0xBB, 0x12, 0x20, 0xDA, 0xCC, 0xF0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, ++0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, ++0x90, 0x83, 0x03, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0xFD, 0xFF, 0x12, 0x4F, 0x74, ++0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x83, 0x15, 0x12, 0x20, ++0xCE, 0x90, 0x83, 0x15, 0x12, 0x42, 0x26, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x7C, 0x7E, ++0x08, 0x12, 0x2E, 0xA2, 0x90, 0x01, 0x00, 0x74, 0x3F, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0, 0x90, ++0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, ++0xC0, 0xD0, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x53, 0xE0, 0x54, 0xFE, 0x4E, ++0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, ++0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x81, 0x53, 0xF0, 0xEE, 0x54, 0x08, 0xFE, ++0xEF, 0x54, 0xF7, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, ++0x4D, 0xFF, 0x90, 0x81, 0x53, 0xF0, 0xEE, 0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0xFF, 0xF0, ++0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x90, 0x81, 0x53, 0xF0, ++0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x4E, 0xF0, 0x90, 0x01, 0x17, 0xE0, 0xFE, 0x90, 0x01, ++0x16, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x80, 0xF5, 0xF0, 0xA3, 0xEF, 0xF0, ++0x90, 0x81, 0x53, 0xE0, 0xC3, 0x13, 0x54, 0x01, 0xFF, 0xD1, 0x2E, 0x90, 0x81, 0x53, 0xE0, 0x13, ++0x13, 0x54, 0x01, 0xFF, 0xF1, 0x95, 0x90, 0x81, 0x53, 0xE0, 0xC4, 0x54, 0x01, 0xFF, 0xF1, 0x9B, ++0x90, 0x81, 0x53, 0xE0, 0x54, 0x01, 0xFF, 0x31, 0xF2, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEF, 0x60, ++0x07, 0x90, 0x82, 0x58, 0xE0, 0xFF, 0xD1, 0x39, 0x22, 0xD1, 0x61, 0x7E, 0x00, 0x90, 0x83, 0x2F, ++0xD1, 0x75, 0x90, 0x83, 0x2F, 0xA3, 0xE0, 0x2F, 0x24, 0x36, 0xF9, 0xE4, 0x34, 0xFC, 0x75, 0x13, ++0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x04, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x6C, 0x02, 0x2B, ++0xED, 0xE4, 0xFE, 0xEF, 0xC3, 0x13, 0xFD, 0xEF, 0x30, 0xE0, 0x02, 0x7E, 0x80, 0x90, 0xFD, 0x10, ++0xED, 0xF0, 0xAF, 0x06, 0x22, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xFE, 0x24, 0x20, 0xF5, 0x82, 0xE4, ++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0xFF, 0x74, 0x24, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, ++0xE0, 0xFD, 0xE4, 0xFE, 0xEF, 0x30, 0xE7, 0x04, 0x7C, 0x02, 0x80, 0x02, 0xE4, 0xFC, 0xAF, 0x05, ++0xF1, 0x4D, 0xAE, 0x07, 0xEC, 0x24, 0x18, 0x2E, 0xFF, 0x22, 0x90, 0x83, 0x0A, 0xED, 0xF0, 0x90, ++0x83, 0x07, 0x12, 0x42, 0x53, 0xE4, 0x90, 0x83, 0x0B, 0xF0, 0xA3, 0xF0, 0x12, 0x1F, 0xA4, 0xFF, ++0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFD, 0xD1, 0x92, 0x90, 0x83, 0x0B, 0xEF, 0xF0, 0x90, 0x83, ++0x07, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xF1, 0x4D, 0x90, 0x83, 0x0C, ++0xEF, 0xF0, 0x90, 0x81, 0x70, 0xE0, 0x24, 0xFE, 0x60, 0x1E, 0x24, 0xFE, 0x60, 0x1A, 0x14, 0x60, ++0x07, 0x14, 0x60, 0x04, 0x24, 0x05, 0x70, 0x54, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x71, 0x90, 0x83, ++0x0A, 0xE0, 0xFD, 0x12, 0x7A, 0x4B, 0x80, 0x16, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x71, 0x90, 0x83, ++0x0A, 0xE0, 0xFD, 0x90, 0x81, 0x70, 0xE0, 0x90, 0x82, 0xE5, 0xF0, 0x12, 0x79, 0x29, 0x90, 0x83, ++0x0C, 0xE0, 0xFF, 0x90, 0x83, 0x07, 0x12, 0x42, 0x4A, 0x90, 0x83, 0x0B, 0xE0, 0x7C, 0x00, 0x29, ++0xF9, 0xEC, 0x3A, 0xFA, 0xC3, 0xE9, 0x9F, 0xF9, 0xEA, 0x94, 0x00, 0xFA, 0x75, 0x13, 0x01, 0x75, ++0x14, 0x81, 0x75, 0x15, 0x71, 0xA3, 0xE0, 0xF5, 0x16, 0x12, 0x2B, 0xED, 0x22, 0xD3, 0x10, 0xAF, ++0x01, 0xC3, 0xC0, 0xD0, 0xEF, 0x20, 0xE0, 0x05, 0x90, 0x82, 0x55, 0x80, 0x03, 0x90, 0x82, 0x56, ++0xE0, 0x90, 0x81, 0x70, 0xF0, 0x90, 0x81, 0x70, 0xE0, 0x14, 0x60, 0x13, 0x14, 0x60, 0x14, 0x24, ++0xFE, 0x60, 0x10, 0x14, 0x60, 0x09, 0x14, 0x60, 0x06, 0x24, 0x06, 0xE4, 0xFE, 0x80, 0x06, 0x7E, ++0x04, 0x80, 0x02, 0x7E, 0x08, 0xAF, 0x06, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x22, 0x22, 0x22, 0xE4, ++0x90, 0x80, 0xF7, 0xF0, 0x22, 0x90, 0x82, 0x7E, 0xEF, 0xF0, 0x22, 0x90, 0x82, 0x7E, 0xEF, 0xF0, ++0x22, 0x75, 0xE8, 0x03, 0x75, 0xA8, 0x84, 0x22, 0x90, 0x01, 0xC7, 0x74, 0x05, 0xF0, 0x22, 0x90, ++0x01, 0xE4, 0x74, 0x0D, 0xF0, 0xA3, 0xE4, 0xF0, 0x22, 0xE4, 0x90, 0x80, 0x01, 0xF0, 0xA3, 0xF0, ++0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x01, 0x94, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x01, 0xC7, 0xE4, ++0xF0, 0x22, 0xE4, 0x90, 0x80, 0xF3, 0xF0, 0xA3, 0xF0, 0x90, 0x80, 0x5B, 0xF0, 0xA3, 0xF0, 0x22, ++0xE4, 0x90, 0x82, 0x76, 0xF0, 0x90, 0x82, 0x76, 0xE0, 0x64, 0x01, 0xF0, 0x24, 0xE0, 0x90, 0x01, ++0xC4, 0xF0, 0x74, 0x5F, 0xA3, 0xF0, 0x90, 0x81, 0x3B, 0xE0, 0x60, 0x0F, 0x90, 0x81, 0x3E, 0xE0, ++0xFF, 0x90, 0x81, 0x3D, 0xE0, 0x6F, 0x60, 0x03, 0x12, 0x4E, 0x3A, 0xC2, 0xAF, 0x51, 0xC6, 0xBF, ++0x01, 0x02, 0x31, 0xDF, 0xD2, 0xAF, 0x11, 0x1D, 0x12, 0x44, 0x79, 0x80, 0xC8, 0xD3, 0x10, 0xAF, ++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x00, 0x8F, 0xE0, 0x20, 0xE6, 0x02, 0x21, 0xAF, 0x90, 0x00, 0x8C, ++0xE0, 0x90, 0x82, 0x77, 0xF0, 0x90, 0x00, 0x8D, 0xE0, 0x90, 0x82, 0x78, 0xF0, 0x90, 0x00, 0x8E, ++0xE0, 0x90, 0x82, 0x79, 0xF0, 0x90, 0x82, 0x78, 0xE0, 0x24, 0xF1, 0x70, 0x02, 0x21, 0x0E, 0x24, ++0x07, 0x60, 0x02, 0x21, 0xA1, 0x90, 0x81, 0x3B, 0xE0, 0xFB, 0xE4, 0xFD, 0xFF, 0x31, 0xB7, 0x90, ++0x81, 0x3A, 0xE0, 0x54, 0x0F, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x3D, 0x31, 0xB4, 0x90, 0x81, ++0x3E, 0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x82, 0x77, 0xE0, 0x24, 0xF7, 0xF5, 0x82, 0xE4, 0x34, ++0x80, 0xF5, 0x83, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0x31, 0xB7, 0x90, 0x81, 0x38, 0xE0, 0x54, 0x01, ++0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x38, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0x7F, ++0x01, 0x31, 0xB7, 0x90, 0x81, 0x38, 0xE0, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0x7F, ++0x01, 0x31, 0xB7, 0x90, 0x80, 0x03, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0x31, 0xB7, 0x90, 0x80, 0x04, ++0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x42, 0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x41, ++0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x3A, 0xE0, 0xC4, 0x54, 0x0F, 0xFB, 0xE4, 0xFD, 0x7F, ++0x03, 0x31, 0xB7, 0x90, 0x81, 0x39, 0xE0, 0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0x7F, 0x03, 0x31, ++0xB7, 0x90, 0x81, 0x39, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0x7F, 0x03, 0x31, 0xB7, ++0x90, 0x81, 0x38, 0xE0, 0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0x7F, 0x03, 0x21, 0x9F, 0x90, 0x81, ++0x53, 0xE0, 0x54, 0x01, 0xFB, 0xE4, 0xFD, 0xFF, 0x31, 0xB7, 0x90, 0x81, 0x54, 0xE0, 0xC4, 0x13, ++0x13, 0x13, 0x54, 0x01, 0xFB, 0x0D, 0xE4, 0xFF, 0x31, 0xB7, 0x90, 0x81, 0x54, 0xE0, 0xC4, 0x54, ++0x01, 0xFB, 0x0D, 0xE4, 0xFF, 0x31, 0xB7, 0x90, 0x81, 0x58, 0xE0, 0x54, 0x01, 0xFB, 0x0D, 0x31, ++0xB7, 0x90, 0x81, 0x65, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0x31, 0xB7, 0x90, 0x81, 0x66, 0xE0, 0xFB, ++0x0D, 0x31, 0xB7, 0x90, 0x81, 0x67, 0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x68, 0xE0, 0xFB, ++0x0D, 0x31, 0xB7, 0x90, 0x81, 0x69, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0x31, 0xB7, 0x90, 0x81, 0x6A, ++0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x81, 0x6B, 0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x82, 0x5A, ++0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x80, 0x07, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0x31, 0xB7, 0x90, ++0x80, 0x08, 0xE0, 0xFB, 0x0D, 0x31, 0xB7, 0x90, 0x82, 0x58, 0x31, 0xB4, 0xE4, 0xFB, 0x0D, 0x31, ++0xB7, 0x90, 0x00, 0x8F, 0xE0, 0x30, 0xE0, 0x07, 0xE4, 0xFD, 0x7F, 0x8D, 0x12, 0x32, 0x1E, 0xD0, ++0xD0, 0x92, 0xAF, 0x22, 0xE0, 0xFB, 0x0D, 0xEF, 0x70, 0x04, 0x74, 0xF0, 0x80, 0x16, 0xEF, 0xB4, ++0x01, 0x04, 0x74, 0xF4, 0x80, 0x0E, 0xEF, 0xB4, 0x02, 0x04, 0x74, 0xF8, 0x80, 0x06, 0xEF, 0xB4, ++0x03, 0x0C, 0x74, 0xFC, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83, 0xEB, 0xF0, 0x22, 0x90, ++0x81, 0x38, 0xE0, 0x30, 0xE0, 0x02, 0x31, 0xE9, 0x22, 0x90, 0x81, 0x3E, 0xE0, 0xFF, 0x60, 0x03, ++0xB4, 0x08, 0x0D, 0x51, 0xED, 0xBF, 0x01, 0x08, 0x51, 0x01, 0x90, 0x01, 0xE5, 0xE0, 0x04, 0xF0, ++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x51, 0x79, 0x51, 0x11, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0x51, 0xBE, 0x90, 0x00, 0x08, 0xE0, 0x54, 0xEF, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, 0xE4, ++0xFF, 0x8F, 0x0F, 0xE4, 0x90, 0x82, 0x77, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x09, 0xE0, 0x7F, 0x00, ++0x30, 0xE7, 0x02, 0x7F, 0x01, 0xEF, 0x65, 0x0F, 0x60, 0x3E, 0xC3, 0x90, 0x82, 0x78, 0xE0, 0x94, ++0x88, 0x90, 0x82, 0x77, 0xE0, 0x94, 0x13, 0x40, 0x08, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x10, 0xF0, ++0x22, 0x90, 0x82, 0x77, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x41, 0xF6, 0x7F, 0x14, 0x7E, 0x00, 0x12, ++0x32, 0xAA, 0xD3, 0x90, 0x82, 0x78, 0xE0, 0x94, 0x32, 0x90, 0x82, 0x77, 0xE0, 0x94, 0x00, 0x40, ++0xB9, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE0, 0xB2, 0x22, 0x90, 0x81, 0x45, 0xE0, 0xFD, 0x7F, 0x93, ++0x12, 0x32, 0x1E, 0x90, 0x81, 0x3C, 0xE0, 0x60, 0x12, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x05, ++0x74, 0x10, 0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, 0x74, 0x90, 0xF0, 0x90, 0x00, 0x08, 0xE0, 0x44, ++0x10, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, 0x7F, 0x01, 0x51, 0x21, 0x90, 0x00, 0x90, 0xE0, 0x44, ++0x01, 0xFD, 0x7F, 0x90, 0x12, 0x32, 0x1E, 0x7F, 0x14, 0x7E, 0x00, 0x02, 0x32, 0xAA, 0x90, 0x00, ++0x90, 0xE0, 0x20, 0xE0, 0xF9, 0x22, 0x7F, 0x02, 0x90, 0x82, 0x64, 0xE0, 0xFE, 0xEF, 0xC3, 0x9E, ++0x50, 0x18, 0xEF, 0x25, 0xE0, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, 0xB8, 0x74, ++0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, 0x0F, 0x80, 0xDE, 0x7F, 0x01, 0x22, 0x90, 0x02, 0x87, ++0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x01, 0xF0, 0x80, 0x3B, 0x90, 0x81, 0x53, 0xE0, 0x30, ++0xE0, 0x0E, 0x90, 0x02, 0x82, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x02, 0xF0, 0x80, 0x26, ++0x90, 0x81, 0x58, 0xE0, 0x30, 0xE0, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x80, 0x17, 0x90, ++0x02, 0x86, 0xE0, 0x20, 0xE1, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x08, 0x90, 0x01, ++0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x08, 0xF0, 0x7F, 0x00, 0x22, 0xE4, ++0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x46, 0x7A, 0x90, 0x82, 0x7A, 0xEF, 0xF0, 0x60, 0xF0, 0x90, ++0x80, 0x01, 0xE0, 0xFF, 0x60, 0xE9, 0xC2, 0xAF, 0x30, 0xE1, 0x05, 0x54, 0xFD, 0xF0, 0x71, 0x8C, ++0xD2, 0xAF, 0xC2, 0xAF, 0x90, 0x80, 0x01, 0xE0, 0xFF, 0x30, 0xE2, 0x05, 0x54, 0xFB, 0xF0, 0xD1, ++0x5B, 0xD2, 0xAF, 0xC2, 0xAF, 0x90, 0x80, 0x01, 0xE0, 0xFF, 0x30, 0xE4, 0x0B, 0x54, 0xEF, 0xF0, ++0xD1, 0x1E, 0xBF, 0x01, 0x03, 0x12, 0x53, 0x53, 0xD2, 0xAF, 0x80, 0xC3, 0xD3, 0x10, 0xAF, 0x01, ++0xC3, 0xC0, 0xD0, 0x90, 0x80, 0x5C, 0xE0, 0xFF, 0x90, 0x80, 0x5B, 0xE0, 0xB5, 0x07, 0x04, 0x7F, ++0x01, 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x70, 0x43, 0x90, 0x80, 0x5B, 0xE0, 0xFE, 0x75, 0xF0, 0x08, ++0x90, 0x80, 0x0B, 0x12, 0x42, 0x3E, 0xE0, 0xFD, 0xEE, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x0C, 0xF9, ++0x74, 0x80, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0xAF, 0x05, 0x71, 0xF0, 0x90, 0x80, 0x5B, 0xE0, 0x04, ++0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0x5B, ++0xF0, 0x12, 0x6B, 0x60, 0x90, 0x80, 0x01, 0xE0, 0x44, 0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, ++0x90, 0x82, 0x7B, 0x12, 0x42, 0x53, 0xEF, 0x12, 0x42, 0x5C, 0x64, 0x2B, 0x00, 0x64, 0x33, 0x01, ++0x64, 0x3B, 0x02, 0x64, 0x43, 0x03, 0x64, 0x4B, 0x04, 0x64, 0x53, 0x13, 0x64, 0x5C, 0x20, 0x64, ++0x65, 0x21, 0x64, 0x6D, 0x23, 0x64, 0x75, 0x25, 0x64, 0x86, 0x80, 0x64, 0x7D, 0x81, 0x64, 0x8F, ++0x82, 0x64, 0x97, 0x83, 0x64, 0x9F, 0x84, 0x00, 0x00, 0x64, 0xA7, 0x90, 0x82, 0x7B, 0x12, 0x42, ++0x4A, 0xC1, 0xDF, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0x81, 0xDB, 0x90, 0x82, 0x7B, 0x12, 0x42, ++0x4A, 0xA1, 0xE6, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0xA1, 0xC6, 0x90, 0x82, 0x7B, 0x12, 0x42, ++0x4A, 0x80, 0x5C, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0x02, 0x6A, 0x66, 0x90, 0x82, 0x7B, 0x12, ++0x42, 0x4A, 0x02, 0x6A, 0xD4, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0xC1, 0x99, 0x90, 0x82, 0x7B, ++0x12, 0x42, 0x4A, 0xA1, 0x7F, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0xA1, 0x87, 0x90, 0x82, 0x7B, ++0x12, 0x42, 0x4A, 0x02, 0x5D, 0x7B, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0x02, 0x74, 0x90, 0x90, ++0x82, 0x7B, 0x12, 0x42, 0x4A, 0xA1, 0xAC, 0x90, 0x82, 0x7B, 0x12, 0x42, 0x4A, 0xE1, 0x27, 0x90, ++0x82, 0x7B, 0x12, 0x42, 0x4A, 0xE1, 0x7C, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xB1, ++0x97, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x82, 0x68, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, ++0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x14, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0x69, 0xF0, ++0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0x6A, 0xF0, 0x22, 0x90, 0x82, 0x7E, 0x12, 0x42, ++0x53, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xFE, 0x12, 0x1F, 0xA4, 0xFD, 0xC3, 0x13, 0x30, ++0xE0, 0x12, 0x90, 0x82, 0x7E, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x82, ++0x82, 0xF0, 0x80, 0x05, 0x90, 0x82, 0x82, 0xEF, 0xF0, 0x90, 0x82, 0x81, 0xEE, 0xF0, 0x90, 0x82, ++0x82, 0xE0, 0xFE, 0x90, 0x82, 0x81, 0xE0, 0xFF, 0xD3, 0x9E, 0x50, 0x38, 0x90, 0x82, 0x7E, 0x12, ++0x42, 0x4A, 0x12, 0x1F, 0xA4, 0x54, 0x01, 0xFE, 0x74, 0xF7, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x80, ++0xF5, 0x83, 0xEE, 0xF0, 0x74, 0xF7, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xE0, 0x70, ++0x04, 0xB1, 0x7E, 0x80, 0x07, 0x90, 0x82, 0x81, 0xE0, 0xFF, 0xB1, 0x7D, 0x90, 0x82, 0x81, 0xE0, ++0x04, 0xF0, 0x80, 0xBA, 0x90, 0x80, 0xF7, 0xE0, 0x70, 0x22, 0x90, 0x81, 0x3E, 0xE0, 0x70, 0x04, ++0xFF, 0x12, 0x4A, 0xF6, 0x90, 0x81, 0x3E, 0xE0, 0x64, 0x0C, 0x60, 0x03, 0x12, 0x4F, 0xD6, 0x90, ++0x81, 0x38, 0xE0, 0x54, 0xF7, 0xF0, 0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x22, 0x22, 0x12, ++0x1F, 0xA4, 0x90, 0x81, 0x45, 0xF0, 0x22, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x52, 0xF0, 0x90, 0x81, ++0x52, 0xE0, 0x90, 0x01, 0xE7, 0xF0, 0x22, 0x90, 0x82, 0x68, 0xE0, 0x54, 0xFE, 0xF0, 0xA3, 0x74, ++0x03, 0xF0, 0xA3, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x02, 0x09, 0xE0, ++0x90, 0x82, 0x7E, 0xF0, 0x12, 0x1F, 0xA4, 0x90, 0x82, 0x55, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, ++0xBD, 0x90, 0x82, 0x56, 0xF0, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x82, 0x65, ++0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x0A, 0x90, 0x00, 0x01, 0x12, 0x1F, ++0xBD, 0x90, 0x82, 0x66, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, ++0xFF, 0x90, 0x81, 0x37, 0xF0, 0xBF, 0x01, 0x12, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, ++0x60, 0x17, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x80, 0x0F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, ++0x64, 0x01, 0x60, 0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0x90, ++0x83, 0x2D, 0xF0, 0xA3, 0xF0, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1, 0x2C, 0xC3, 0x90, 0x83, 0x2E, ++0xE0, 0x94, 0xD0, 0x90, 0x83, 0x2D, 0xE0, 0x94, 0x07, 0x40, 0x0A, 0x90, 0x01, 0xC1, 0xE0, 0x44, ++0x04, 0xF0, 0x7F, 0x00, 0x22, 0x90, 0x83, 0x2D, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x41, 0xF6, 0x7F, ++0x0A, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x80, 0xCD, 0x7F, 0x01, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, ++0xC0, 0xD0, 0xE4, 0xFF, 0x90, 0x80, 0xF4, 0xE0, 0xFE, 0x90, 0x80, 0xF3, 0xE0, 0xB5, 0x06, 0x04, ++0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x64, 0x01, 0x60, 0x19, 0xEF, 0x60, 0x16, 0x90, 0x80, ++0xF3, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, ++0x90, 0x80, 0xF3, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, ++0x30, 0xE0, 0x26, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, ++0x90, 0x81, 0x4D, 0xF0, 0xEF, 0x54, 0xFE, 0xFF, 0xA3, 0xE0, 0x54, 0x01, 0x4F, 0xF0, 0x90, 0x00, ++0x03, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x4F, 0xF0, 0x22, 0x90, 0x81, 0x4C, 0x74, 0x01, 0xF0, 0xA3, ++0x74, 0x05, 0xF0, 0xA3, 0xE0, 0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0x22, 0x90, ++0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x80, 0x06, 0xF0, ++0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x07, 0xF0, 0x90, 0x00, 0x02, ++0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x08, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, ++0xFF, 0xED, 0x2F, 0x90, 0x80, 0x09, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, 0x05, ++0xED, 0x2F, 0x90, 0x80, 0x0A, 0xF0, 0x22, 0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, ++0xAF, 0x05, 0xED, 0x2E, 0x90, 0x82, 0x57, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, ++0x2F, 0x90, 0x82, 0x58, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, ++0x59, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, 0x5A, 0xF0, 0x90, ++0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, 0x5B, 0xF0, 0x90, 0x00, 0x05, 0x12, ++0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x82, 0x5C, 0xF0, 0x22, 0x90, 0x02, 0x09, 0xE0, ++0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x82, 0x5D, 0xF0, 0x90, 0x00, 0x01, ++0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, 0x5E, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, ++0xFF, 0xED, 0x2F, 0x90, 0x82, 0x5F, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, ++0x90, 0x82, 0x60, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, 0x61, ++0xF0, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x82, 0x62, 0xF0, 0x90, 0x00, ++0x06, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x82, 0x63, 0xF0, 0x22, 0x90, 0x82, ++0xD2, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x90, ++0x82, 0xE0, 0xF0, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x90, 0x82, 0xD8, 0x12, 0x20, 0xCE, ++0x90, 0x82, 0xD2, 0xE0, 0xFB, 0x70, 0x08, 0x90, 0x82, 0xD8, 0x12, 0x42, 0x26, 0x80, 0x16, 0xEB, ++0x75, 0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, ++0xE0, 0xFF, 0x12, 0x2D, 0x5C, 0x90, 0x82, 0xDC, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xD3, 0xE0, 0xFF, ++0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x17, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, ++0x07, 0x90, 0x82, 0xDC, 0x12, 0x42, 0x26, 0xED, 0x54, 0x7F, 0xFD, 0xEC, 0x54, 0x80, 0xFC, 0x12, ++0x42, 0x19, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x82, 0xDC, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xD8, 0x12, ++0x42, 0x26, 0xEC, 0x54, 0x7F, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, ++0x12, 0x2E, 0xA2, 0x90, 0x82, 0xD2, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, ++0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x82, 0xDC, ++0x12, 0x42, 0x26, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x12, 0x2E, 0xA2, ++0x90, 0x82, 0xD8, 0x12, 0x42, 0x26, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, ++0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x82, 0xD2, 0xE0, 0x70, 0x04, 0x7F, 0x20, 0x80, ++0x09, 0x90, 0x82, 0xD2, 0xE0, 0xB4, 0x01, 0x16, 0x7F, 0x28, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x78, ++0x08, 0x12, 0x20, 0xA8, 0xEF, 0x54, 0x01, 0xFF, 0xE4, 0x90, 0x82, 0xE0, 0xEF, 0xF0, 0x90, 0x82, ++0xE0, 0xE0, 0x90, 0x82, 0xD2, 0x60, 0x0E, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x66, 0xF5, 0x82, ++0xE4, 0x34, 0x87, 0x80, 0x0C, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x64, 0xF5, 0x82, 0xE4, 0x34, ++0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2D, 0x5C, 0xED, 0x54, 0x0F, 0xFD, 0xE4, ++0xFC, 0x90, 0x82, 0xD4, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xD4, 0x02, 0x42, 0x26, 0x90, 0x82, 0xEF, ++0xEF, 0xF0, 0xAB, 0x05, 0x90, 0x82, 0xF5, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x03, ++0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x14, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, ++0x07, 0x90, 0x82, 0xF1, 0x12, 0x42, 0x26, 0xED, 0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x12, 0x42, 0x19, ++0xEC, 0x54, 0x0F, 0xFC, 0x90, 0x82, 0xF5, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xEF, 0xE0, 0x75, 0xF0, ++0x08, 0xA4, 0x24, 0x60, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, ++0xC0, 0x06, 0xC0, 0x07, 0x90, 0x82, 0xF5, 0x12, 0x42, 0x26, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, ++0xD0, 0x07, 0xD0, 0x06, 0x02, 0x2E, 0xA2, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x67, ++0xDE, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x82, 0xAE, 0xEC, 0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x82, ++0xAD, 0xEF, 0xF0, 0xA3, 0xA3, 0xE0, 0xFD, 0x31, 0x87, 0x90, 0x82, 0xB8, 0x12, 0x20, 0xCE, 0x90, ++0x82, 0xB0, 0x12, 0x42, 0x26, 0x12, 0x20, 0x9B, 0x90, 0x82, 0xB8, 0x12, 0x42, 0x32, 0x12, 0x42, ++0x0C, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x82, 0xB0, 0x12, 0x42, 0x26, 0x90, ++0x82, 0xB4, 0x12, 0x42, 0x32, 0x12, 0x42, 0x0C, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, ++0x12, 0x42, 0x19, 0x90, 0x82, 0xBC, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xAE, 0xA3, 0xE0, 0xFD, 0xC0, ++0x05, 0x90, 0x82, 0xBC, 0x12, 0x42, 0x26, 0x90, 0x85, 0x96, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xAD, ++0xE0, 0xFF, 0xD0, 0x05, 0x02, 0x31, 0x4D, 0x90, 0x83, 0x1D, 0x12, 0x42, 0x53, 0xE4, 0xFF, 0x90, ++0x83, 0x1D, 0x12, 0x42, 0x4A, 0x8F, 0x82, 0x75, 0x83, 0x00, 0x12, 0x1F, 0xBD, 0xFE, 0x74, 0xF0, ++0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83, 0xEE, 0xF0, 0x0F, 0xEF, 0xB4, 0x10, 0xE0, 0x22, ++0x90, 0x83, 0x31, 0xEF, 0xF0, 0x7F, 0x02, 0x12, 0x46, 0x53, 0x90, 0x80, 0x01, 0xE0, 0xFF, 0x90, ++0x83, 0x31, 0xE0, 0xFE, 0xEF, 0x4E, 0x90, 0x80, 0x01, 0xF0, 0x22, 0x90, 0x83, 0x32, 0xEF, 0xF0, ++0x7F, 0x02, 0x12, 0x46, 0x53, 0x90, 0x80, 0x02, 0xE0, 0xFF, 0x90, 0x83, 0x32, 0xE0, 0xFE, 0xEF, ++0x4E, 0x90, 0x80, 0x02, 0xF0, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x80, 0xFE, 0x90, 0x82, 0x6E, ++0xE0, 0x54, 0x7F, 0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x40, 0xFF, 0xEE, 0x54, 0xBF, 0x4F, 0xFF, 0xF0, ++0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x20, 0xFD, 0xEF, 0x54, 0xDF, 0x4D, 0xFF, 0x90, 0x82, 0x6E, 0xF0, ++0xEE, 0x54, 0x10, 0xFE, 0xEF, 0x54, 0xEF, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0x54, 0x0F, 0xFE, ++0xEF, 0x54, 0xF0, 0x4E, 0x90, 0x82, 0x6E, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x82, ++0x6F, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0x70, 0xF0, 0x90, 0x82, 0x6E, 0xE0, ++0xFE, 0x54, 0x0F, 0xFF, 0xEE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D, ++0x01, 0x02, 0x52, 0x47, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x7F, 0x90, 0x81, 0x3B, 0xF0, 0xEF, 0xC4, ++0x13, 0x13, 0x13, 0x54, 0x01, 0xA3, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x54, 0xF0, ++0xC4, 0x54, 0x0F, 0xFE, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0xF0, 0x4E, 0xF0, 0x90, 0x00, 0x03, 0x12, ++0x1F, 0xBD, 0x54, 0x01, 0x25, 0xE0, 0xFE, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xFD, 0x4E, 0xF0, 0x90, ++0x81, 0x53, 0xE0, 0x30, 0xE0, 0x09, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0xF0, 0x80, 0x0F, 0xEF, ++0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0x4F, 0xF0, 0x90, 0x00, ++0x04, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x3D, 0xF0, 0x12, 0x5C, 0x93, 0x90, 0x01, 0xB9, 0x74, 0x01, ++0xF0, 0x90, 0x01, 0xB8, 0xF0, 0x90, 0x81, 0x3B, 0xE0, 0x90, 0x01, 0xBA, 0xF0, 0x90, 0x81, 0x3D, ++0xE0, 0x90, 0x01, 0xBB, 0xF0, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0x90, 0x01, 0xBE, 0xF0, 0x22, ++0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0x90, 0x83, 0x33, 0xF0, 0x90, 0x83, 0x33, 0xE0, 0xFD, 0x70, ++0x02, 0x81, 0xED, 0x90, 0x80, 0x5B, 0xE0, 0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09, 0x60, 0x0A, ++0xEF, 0x14, 0xFF, 0x90, 0x80, 0x5C, 0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, ++0xEF, 0x60, 0x08, 0x90, 0x01, 0xC1, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x83, 0x23, 0xE0, 0xFF, ++0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, ++0xFF, 0xEF, 0x5D, 0x70, 0x02, 0x81, 0xE6, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, ++0xD0, 0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x90, 0x80, 0x5C, 0xE0, 0xFE, 0x75, 0xF0, 0x08, 0x90, 0x80, ++0x0B, 0x12, 0x42, 0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD1, ++0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x75, 0xF0, 0x08, 0xEE, 0x90, 0x80, 0x0C, 0x12, 0x42, 0x3E, 0xEF, ++0xF0, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD2, 0x12, 0x42, 0x3E, 0xE0, 0xFF, ++0x75, 0xF0, 0x08, 0xEE, 0x90, 0x80, 0x0D, 0x12, 0x42, 0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x23, 0xE0, ++0x75, 0xF0, 0x04, 0x90, 0x01, 0xD3, 0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x75, 0xF0, 0x08, 0xEE, 0x90, ++0x80, 0x0E, 0x12, 0x42, 0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, ++0xF0, 0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x75, 0xF0, 0x08, 0xEE, 0x90, 0x80, 0x0F, 0x12, 0x42, 0x3E, ++0xEF, 0xF0, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF1, 0x12, 0x42, 0x3E, 0xE0, ++0xFF, 0x75, 0xF0, 0x08, 0xEE, 0x90, 0x80, 0x10, 0x12, 0x42, 0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x23, ++0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF2, 0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x75, 0xF0, 0x08, 0xEE, ++0x90, 0x80, 0x11, 0x12, 0x42, 0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x23, 0xE0, 0x75, 0xF0, 0x04, 0x90, ++0x01, 0xF3, 0x12, 0x42, 0x3E, 0xE0, 0xFF, 0x75, 0xF0, 0x08, 0xEE, 0x90, 0x80, 0x12, 0x12, 0x42, ++0x3E, 0xEF, 0xF0, 0x90, 0x83, 0x33, 0xE0, 0xFF, 0x90, 0x83, 0x23, 0xE0, 0xFE, 0x74, 0x01, 0xA8, ++0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0x90, 0x83, 0x33, 0xF0, 0x90, 0x83, ++0x23, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x90, 0x01, ++0xCC, 0xF0, 0x90, 0x83, 0x23, 0xE0, 0x04, 0xF0, 0xE0, 0x54, 0x03, 0xF0, 0x90, 0x80, 0x5C, 0xE0, ++0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x70, 0x02, 0x61, 0x6A, 0xE4, ++0x90, 0x80, 0x5C, 0xF0, 0x61, 0x6A, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0x22, 0xD3, 0x10, ++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, 0x0D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0xA3, 0xF0, ++0xA3, 0xF0, 0x90, 0x83, 0x0D, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0xE0, 0x60, 0x2D, ++0xC3, 0x90, 0x83, 0x10, 0xE0, 0x94, 0xE8, 0x90, 0x83, 0x0F, 0xE0, 0x94, 0x03, 0x40, 0x0B, 0x90, ++0x01, 0xC0, 0xE0, 0x44, 0x80, 0xF0, 0x7F, 0x00, 0x80, 0x15, 0x90, 0x83, 0x0F, 0xE4, 0x75, 0xF0, ++0x01, 0x12, 0x41, 0xF6, 0x7F, 0x0A, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x80, 0xC5, 0x7F, 0x01, 0xD0, ++0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, 0x20, 0x12, 0x42, ++0x53, 0x90, 0x83, 0x24, 0xE0, 0xFF, 0x04, 0xF0, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, 0xFC, 0x7F, ++0xAF, 0x7E, 0x01, 0x91, 0xEE, 0xEF, 0x60, 0x3A, 0x90, 0x83, 0x20, 0x12, 0x42, 0x4A, 0x8B, 0x13, ++0x8A, 0x14, 0x89, 0x15, 0x90, 0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xF5, 0x16, 0x7B, 0x01, ++0x7A, 0x01, 0x79, 0xA0, 0x12, 0x2B, 0xED, 0x90, 0x83, 0x20, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x0E, ++0x12, 0x1F, 0xBD, 0x90, 0x01, 0xAE, 0xF0, 0xA3, 0x74, 0xFF, 0xF0, 0x90, 0x01, 0xCB, 0xE0, 0x64, ++0x80, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x80, ++0xF3, 0xE0, 0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09, 0x60, 0x0A, 0xEF, 0x14, 0xFF, 0x90, 0x80, ++0xF4, 0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x60, 0x09, 0x90, 0x01, ++0xC1, 0xE0, 0x44, 0x02, 0xF0, 0x80, 0x35, 0xC0, 0x01, 0x90, 0x80, 0xF4, 0xE0, 0x75, 0xF0, 0x0F, ++0xA4, 0x24, 0x5D, 0xF9, 0x74, 0x80, 0x35, 0xF0, 0xA8, 0x01, 0xFC, 0x7D, 0x01, 0xD0, 0x01, 0x7E, ++0x00, 0x7F, 0x0F, 0x12, 0x41, 0xD0, 0x90, 0x80, 0xF4, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, ++0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0xF4, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, ++0x22, 0x90, 0x01, 0x34, 0xE0, 0x55, 0x3D, 0xF5, 0x41, 0xA3, 0xE0, 0x55, 0x3E, 0xF5, 0x42, 0xA3, ++0xE0, 0x55, 0x3F, 0xF5, 0x43, 0xA3, 0xE0, 0x55, 0x40, 0xF5, 0x44, 0x90, 0x01, 0x34, 0xE5, 0x41, ++0xF0, 0xA3, 0xE5, 0x42, 0xF0, 0xA3, 0xE5, 0x43, 0xF0, 0xA3, 0xE5, 0x44, 0xF0, 0x22, 0x90, 0x01, ++0x3C, 0xE0, 0x55, 0x45, 0xF5, 0x49, 0xA3, 0xE0, 0x55, 0x46, 0xF5, 0x4A, 0xA3, 0xE0, 0x55, 0x47, ++0xF5, 0x4B, 0xA3, 0xE0, 0x55, 0x48, 0xF5, 0x4C, 0x90, 0x01, 0x3C, 0xE5, 0x49, 0xF0, 0xA3, 0xE5, ++0x4A, 0xF0, 0xA3, 0xE5, 0x4B, 0xF0, 0xA3, 0xE5, 0x4C, 0xF0, 0x53, 0x91, 0xDF, 0x22, 0x8F, 0x52, ++0x7F, 0x02, 0x12, 0x46, 0x53, 0x90, 0x80, 0x02, 0xE0, 0x45, 0x52, 0xF0, 0x22, 0xD1, 0xD5, 0x90, ++0x82, 0x72, 0xEF, 0xF0, 0x90, 0x81, 0x38, 0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x04, ++0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x82, 0x72, 0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01, 0x2F, 0xE0, 0x30, ++0xE7, 0x04, 0xE4, 0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, 0x74, 0x80, 0xF0, 0x90, 0x81, 0x38, 0xE0, ++0x30, 0xE0, 0x1A, 0x90, 0x81, 0x46, 0xE4, 0xF0, 0xA3, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x46, 0xA3, ++0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x04, 0xEC, 0xE0, 0x54, 0xDD, 0xF0, 0x22, 0x90, 0x04, 0xEC, ++0xE0, 0x44, 0x22, 0xF0, 0x22, 0xE4, 0x90, 0x82, 0x73, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x00, ++0x83, 0xE0, 0x90, 0x82, 0x73, 0xF0, 0x90, 0x00, 0x83, 0xE0, 0xFE, 0x90, 0x82, 0x73, 0xE0, 0xFF, ++0xB5, 0x06, 0x01, 0x22, 0xC3, 0x90, 0x82, 0x75, 0xE0, 0x94, 0x64, 0x90, 0x82, 0x74, 0xE0, 0x94, ++0x00, 0x40, 0x0D, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x82, 0x73, 0xE0, 0xFF, 0x22, ++0x90, 0x82, 0x74, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x41, 0xF6, 0x80, 0xC2, 0x90, 0x81, 0x38, 0xE0, ++0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x2C, 0xEF, 0x54, 0x7F, 0xF0, 0x90, 0x04, ++0xE0, 0xE0, 0x90, 0x81, 0x39, 0x30, 0xE1, 0x06, 0xE0, 0x44, 0x02, 0xF0, 0x80, 0x0F, 0xE0, 0x54, ++0xFD, 0xF0, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x04, 0xF0, 0x90, 0x81, 0x3B, ++0xE0, 0x60, 0x03, 0x12, 0x4E, 0x3A, 0x7F, 0x01, 0x02, 0x51, 0x2A, 0xD3, 0x10, 0xAF, 0x01, 0xC3, ++0xC0, 0xD0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x1A, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x90, 0x60, 0x07, ++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE1, 0xE4, 0x7F, 0x00, ++0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xC3, 0xEE, 0x94, 0x01, 0x40, 0x0A, 0x0D, ++0xED, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xC3, 0xEE, 0x94, 0x01, 0x40, 0x1E, ++0x90, 0xFD, 0x11, 0xE0, 0xB5, 0x05, 0x14, 0x90, 0x01, 0x17, 0xE0, 0xB5, 0x05, 0x07, 0x90, 0xFD, ++0x11, 0xE4, 0xF0, 0x80, 0x06, 0xED, 0x04, 0x90, 0xFD, 0x11, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xE4, ++0x90, 0x83, 0x29, 0xF0, 0xA3, 0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, ++0xA3, 0xE0, 0x70, 0x07, 0xA3, 0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x83, 0x2A, 0xE0, ++0x94, 0xE8, 0x90, 0x83, 0x29, 0xE0, 0x94, 0x03, 0x40, 0x0A, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20, ++0xF0, 0x7F, 0x00, 0x22, 0x7F, 0x32, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x83, 0x29, 0xE4, 0x75, ++0xF0, 0x01, 0x12, 0x41, 0xF6, 0x80, 0xBF, 0x74, 0x45, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, ++0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0x90, ++0x82, 0xC0, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x2D, 0x5C, 0x90, 0x82, 0xCA, 0x12, 0x20, 0xCE, ++0x90, 0x82, 0xC2, 0x12, 0x42, 0x26, 0x12, 0x20, 0x9B, 0x90, 0x82, 0xCA, 0x12, 0x42, 0x32, 0x12, ++0x42, 0x0C, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x82, 0xC2, 0x12, 0x42, 0x26, ++0x90, 0x82, 0xC6, 0x12, 0x42, 0x32, 0x12, 0x42, 0x0C, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, ++0x00, 0x12, 0x42, 0x19, 0x90, 0x82, 0xCE, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xCE, 0x12, 0x42, 0x26, ++0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x90, 0x82, 0xC0, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x02, 0x2E, ++0xA2, 0xE4, 0x90, 0x81, 0x3B, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x3A, 0xE0, 0x54, 0x0F, 0xF0, 0x54, ++0xF0, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x90, 0x81, 0x41, 0x74, ++0x01, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xFB, 0xF0, 0xA3, 0xE0, 0x54, 0xFB, 0xF0, ++0xE4, 0x90, 0x81, 0x44, 0xF0, 0x90, 0x81, 0x43, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x46, 0xE4, 0xF0, ++0xA3, 0x74, 0x02, 0xF0, 0xE4, 0x90, 0x81, 0x3F, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xFE, 0xF0, ++0x90, 0x81, 0x3D, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xDF, 0xF0, 0x90, 0x81, 0x3E, ++0x74, 0x0C, 0xF0, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0xE0, 0x54, ++0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x90, 0x81, 0x48, 0x12, 0x20, 0xDA, 0x00, 0x00, ++0x00, 0x00, 0x90, 0x80, 0x05, 0xE0, 0xB4, 0x01, 0x08, 0x90, 0x81, 0x45, 0x74, 0x99, 0xF0, 0x80, ++0x12, 0x90, 0x80, 0x05, 0xE0, 0x90, 0x81, 0x45, 0xB4, 0x03, 0x05, 0x74, 0x90, 0xF0, 0x80, 0x03, ++0x74, 0x40, 0xF0, 0x90, 0x81, 0x4C, 0x74, 0x01, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xE0, 0x54, ++0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0, ++0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xBF, 0xF0, 0xE4, ++0xA3, 0xF0, 0x22, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xFB, 0xF0, 0xE4, 0x90, 0x81, 0x44, 0xF0, 0x90, ++0x81, 0x3F, 0xF0, 0x22, 0x90, 0x04, 0x1A, 0xE0, 0xF4, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x04, ++0x1B, 0xE0, 0x54, 0x07, 0x64, 0x07, 0x7F, 0x01, 0x60, 0x02, 0x7F, 0x00, 0x22, 0x31, 0x64, 0xEF, ++0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x01, 0xF0, 0x80, 0x67, 0x90, 0x81, 0x3F, 0xE0, ++0xFF, 0x54, 0x03, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x02, 0xF0, 0x80, 0x56, 0x90, 0x81, 0x3D, ++0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x44, 0xEF, ++0x30, 0xE2, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x80, 0x38, 0x90, 0x81, 0x3F, 0xE0, 0x30, ++0xE4, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x10, 0xF0, 0x80, 0x29, 0x90, 0x81, 0x39, 0xE0, 0x13, 0x13, ++0x54, 0x3F, 0x20, 0xE0, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x20, 0xF0, 0x80, 0x16, 0x90, 0x81, 0x52, ++0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x80, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, ++0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x04, 0xF0, 0x7F, 0x00, 0x22, 0xEF, 0x24, 0xFE, 0x60, ++0x0C, 0x04, 0x70, 0x28, 0x90, 0x81, 0x41, 0x74, 0x01, 0xF0, 0xA3, 0xF0, 0x22, 0xED, 0x70, 0x0A, ++0x90, 0x81, 0x4F, 0xE0, 0x90, 0x81, 0x41, 0xF0, 0x80, 0x05, 0x90, 0x81, 0x41, 0xED, 0xF0, 0x90, ++0x81, 0x41, 0xE0, 0xA3, 0xF0, 0x90, 0x81, 0x39, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0xEF, 0x60, 0x3E, ++0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x36, 0x90, 0x81, 0x39, 0xE0, 0x54, 0xFE, 0xF0, 0x90, ++0x05, 0x22, 0x74, 0x0F, 0xF0, 0x90, 0x06, 0x04, 0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0xFF, 0x12, 0x4C, ++0x52, 0xBF, 0x01, 0x0E, 0x90, 0x81, 0x38, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x06, ++0xF0, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x22, 0x90, ++0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x3B, 0xE0, 0x60, ++0x2F, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x70, 0x27, 0x90, 0x81, 0x42, 0xF0, 0x04, 0x60, 0x20, ++0x90, 0x81, 0x3F, 0xE0, 0x44, 0x10, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x43, 0x12, 0x4E, 0xD3, ++0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x3E, 0xE0, 0x20, 0xE2, 0x03, 0x12, 0x49, 0x10, ++0x22, 0x90, 0x81, 0x38, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x11, 0xEF, 0x54, 0xFB, ++0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x42, 0x80, 0x3D, 0x90, 0x81, ++0x44, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x44, 0xE0, 0xFF, ++0xB4, 0x01, 0x02, 0x80, 0x04, 0xEF, 0xB4, 0x02, 0x06, 0x90, 0x05, 0x58, 0xE0, 0x04, 0xF0, 0x90, ++0x81, 0x4C, 0xE0, 0xFF, 0x90, 0x81, 0x44, 0xE0, 0xD3, 0x9F, 0x40, 0x0F, 0x90, 0x80, 0xF7, 0xE0, ++0xB4, 0x01, 0x0B, 0x90, 0x81, 0x39, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x4E, 0x3A, 0x22, 0x90, ++0x80, 0x08, 0xE0, 0xFE, 0x90, 0x04, 0x1C, 0xE0, 0x6E, 0x70, 0x40, 0x90, 0x81, 0x3E, 0xE0, 0xFE, ++0xB4, 0x0E, 0x18, 0xEF, 0x70, 0x35, 0x90, 0x81, 0x38, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x06, 0x04, ++0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x0C, 0xF0, 0x22, 0xEE, 0x64, 0x06, 0x70, 0x1B, ++0xEF, 0x60, 0x18, 0x90, 0x81, 0x38, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x06, 0x04, 0xE0, 0x44, 0x40, ++0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x3E, 0x74, 0x04, 0xF0, 0x22, 0x90, 0x82, 0x65, 0xE0, ++0x54, 0xFE, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0x74, 0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x7D, 0x7F, ++0xEF, 0x5D, 0xC3, 0x60, 0x14, 0x74, 0xFF, 0x9D, 0xFD, 0x74, 0xFF, 0x94, 0x00, 0x5E, 0xFE, 0xED, ++0x5F, 0x24, 0x80, 0xFF, 0xE4, 0x3E, 0xFE, 0x80, 0x0D, 0x74, 0xFF, 0x9D, 0xFD, 0x74, 0xFF, 0x94, ++0x00, 0x5E, 0xFE, 0xED, 0x5F, 0xFF, 0x22, 0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, 0x01, 0x1E, 0xE0, ++0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x82, 0x7E, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x02, ++0x87, 0xE0, 0x90, 0x82, 0x82, 0xF0, 0x90, 0x81, 0x53, 0xE0, 0x20, 0xE0, 0x02, 0x81, 0x8F, 0x90, ++0x82, 0x82, 0xE0, 0xFF, 0xEC, 0xC3, 0x9F, 0x40, 0x02, 0x81, 0x8F, 0x90, 0x82, 0x7E, 0xE0, 0xFA, ++0xA3, 0xE0, 0xFB, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0xAD, 0x07, 0x74, 0x02, 0x2D, 0xF5, ++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xF9, 0x74, ++0x01, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x00, 0x2D, 0xF5, 0x82, ++0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x7A, 0x00, 0x24, 0x00, 0xFF, 0xEA, 0x3E, 0x54, 0x3F, 0x90, ++0x82, 0x80, 0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x03, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, ++0xE0, 0x54, 0x03, 0xFF, 0x7E, 0x00, 0xAD, 0x01, 0xED, 0x24, 0x18, 0xFB, 0xEA, 0x33, 0xCB, 0x2F, ++0xFF, 0xEE, 0x3B, 0x90, 0x82, 0x80, 0x8F, 0xF0, 0x12, 0x41, 0xF6, 0x90, 0x82, 0x80, 0xE0, 0xFE, ++0xA3, 0xE0, 0xFF, 0x71, 0x6E, 0x90, 0x82, 0x80, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x82, 0x7E, ++0xEE, 0x8F, 0xF0, 0x12, 0x41, 0xF6, 0x90, 0x80, 0xF5, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xD3, 0x90, ++0x82, 0x7F, 0xE0, 0x9F, 0x90, 0x82, 0x7E, 0xE0, 0x9E, 0x40, 0x1B, 0x90, 0x80, 0xF6, 0xE0, 0x24, ++0x01, 0xFF, 0x90, 0x80, 0xF5, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x90, 0x82, 0x7F, 0xE0, 0x9F, 0xF0, ++0x90, 0x82, 0x7E, 0xE0, 0x9E, 0xF0, 0x90, 0x82, 0x7E, 0x12, 0x57, 0xC5, 0x0C, 0x61, 0xBF, 0x22, ++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, 0xFC, 0x20, 0xE0, 0x05, 0x12, 0x5C, ++0x70, 0xA1, 0x97, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x54, 0xE0, 0x54, 0xFE, ++0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, ++0xFE, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x81, 0x54, 0xF0, 0xEE, 0x54, 0x08, ++0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x10, 0xFD, 0xEF, 0x54, ++0xEF, 0x4D, 0xFF, 0x90, 0x81, 0x54, 0xF0, 0xEE, 0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0xFF, ++0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x90, 0x81, 0x54, ++0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x4E, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, ++0xFD, 0x54, 0x80, 0xFF, 0x90, 0x81, 0x55, 0xE0, 0x54, 0x7F, 0x4F, 0xF0, 0xEC, 0x13, 0x13, 0x54, ++0x3F, 0x30, 0xE0, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x04, 0xF0, 0x12, 0x1F, 0xA4, 0x13, 0x13, ++0x13, 0x54, 0x1F, 0x30, 0xE0, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x80, 0x05, ++0xE0, 0x64, 0x02, 0x70, 0x44, 0x90, 0x81, 0x55, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, ++0x20, 0xE0, 0x36, 0xED, 0x54, 0x7F, 0xFE, 0xEF, 0x54, 0x80, 0x4E, 0x90, 0x81, 0x55, 0xF0, 0x90, ++0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x56, 0xF0, 0x90, 0x81, 0x54, 0xE0, 0xC4, 0x13, 0x54, ++0x07, 0x30, 0xE0, 0x09, 0xA3, 0xE0, 0x54, 0x7F, 0xFF, 0xE4, 0xFD, 0x80, 0x09, 0x90, 0x81, 0x55, ++0xE0, 0x54, 0x7F, 0xFF, 0x7D, 0x01, 0x12, 0x52, 0x47, 0x90, 0x80, 0x05, 0xE0, 0xB4, 0x01, 0x07, ++0x90, 0xFE, 0x10, 0xE0, 0x44, 0x04, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0x58, 0xE0, ++0xFF, 0x20, 0xE0, 0x07, 0x90, 0x01, 0x3F, 0xE0, 0x30, 0xE2, 0x14, 0xEF, 0x44, 0x01, 0x90, 0x81, ++0x58, 0xF0, 0x90, 0x81, 0x54, 0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x03, 0x7F, 0x00, 0x22, 0x7F, ++0x01, 0x22, 0xEF, 0x90, 0x01, 0xC7, 0xB4, 0xA0, 0x05, 0x74, 0x04, 0xF0, 0x80, 0x03, 0x74, 0x08, ++0xF0, 0x90, 0x81, 0x58, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xE4, 0xFE, 0xEF, 0x2E, 0x24, 0x04, 0xF5, ++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFD, 0x74, 0x8B, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x82, ++0xF5, 0x83, 0xED, 0xF0, 0x0E, 0xEE, 0xB4, 0x06, 0xE2, 0x78, 0x59, 0x7C, 0x81, 0x7D, 0x01, 0x7B, ++0x01, 0x7A, 0x82, 0x79, 0x8B, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x44, 0x08, 0xEF, 0x7F, 0x00, 0x70, ++0x02, 0x7F, 0x01, 0x22, 0x90, 0x82, 0x8B, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x78, ++0x94, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, 0xC0, 0x7E, 0x00, 0x7F, 0x06, 0x12, ++0x41, 0xD0, 0x78, 0x9A, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, 0xC6, 0x7E, 0x00, ++0x7F, 0x04, 0x12, 0x41, 0xD0, 0x78, 0x9E, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, ++0xCA, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x41, 0xD0, 0x90, 0x82, 0x8D, 0xE0, 0xFF, 0x90, 0x82, 0x8C, ++0xE0, 0x2F, 0xFF, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCF, 0x24, 0x06, 0xCF, 0x34, 0x00, 0xFE, ++0xE4, 0xFD, 0x12, 0x56, 0x5F, 0xEF, 0x64, 0x08, 0x60, 0x02, 0xE1, 0xD9, 0x90, 0x82, 0x8D, 0xE0, ++0xFF, 0x90, 0x82, 0x8C, 0xE0, 0x2F, 0xFF, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCF, 0x24, 0x07, ++0xCF, 0x34, 0x00, 0xFE, 0xE4, 0xFD, 0x12, 0x56, 0x5F, 0xEF, 0x64, 0x06, 0x60, 0x02, 0xE1, 0xD9, ++0x90, 0x82, 0xA2, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x50, 0x20, 0x90, 0x82, ++0x8C, 0xE0, 0x24, 0x0A, 0x12, 0x56, 0x4D, 0x90, 0x82, 0xA2, 0xE0, 0x24, 0x8E, 0xF5, 0x82, 0xE4, ++0x34, 0x82, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0x04, 0xF0, 0x80, 0xD6, 0xE4, 0x90, ++0x82, 0xA2, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x50, 0x2F, 0x90, 0x82, 0x8D, ++0xE0, 0xFD, 0x90, 0x82, 0x8C, 0xE0, 0x2D, 0xFD, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCD, 0x24, ++0x10, 0xCD, 0x12, 0x56, 0x52, 0x90, 0x82, 0xA2, 0xE0, 0x24, 0x94, 0xF5, 0x82, 0xE4, 0x34, 0x82, ++0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0x04, 0xF0, 0x80, 0xC7, 0xE4, 0x90, 0x82, 0xA2, ++0xF0, 0x90, 0x82, 0xA2, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x2F, 0x90, 0x82, 0x8D, 0xE0, 0xFD, ++0x90, 0x82, 0x8C, 0xE0, 0x2D, 0xFD, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCD, 0x24, 0x16, 0xCD, ++0x12, 0x56, 0x52, 0x90, 0x82, 0xA2, 0xE0, 0x24, 0x9A, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, ++0xEF, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0x04, 0xF0, 0x80, 0xC7, 0x78, 0x8E, 0x7C, 0x82, 0x7D, 0x01, ++0x7B, 0x01, 0x7A, 0x81, 0x79, 0x5F, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x44, 0x08, 0xEF, 0x70, 0x79, ++0x90, 0x82, 0xA2, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x2F, 0x90, 0x82, ++0x8D, 0xE0, 0xFD, 0x90, 0x82, 0x8C, 0xE0, 0x2D, 0xFD, 0x90, 0x82, 0x8B, 0xE0, 0x34, 0x00, 0xCD, ++0x24, 0x20, 0xCD, 0x12, 0x56, 0x52, 0x90, 0x82, 0xA2, 0xE0, 0x24, 0x9E, 0xF5, 0x82, 0xE4, 0x34, ++0x82, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0xA2, 0xE0, 0x04, 0xF0, 0x80, 0xC7, 0x78, 0x9E, 0x7C, ++0x82, 0x7D, 0x01, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x6C, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x44, 0x08, ++0xEF, 0x90, 0x06, 0x30, 0x70, 0x1D, 0xE0, 0x44, 0x01, 0x54, 0xDF, 0xF0, 0x7B, 0x01, 0x7A, 0x82, ++0x79, 0x94, 0x90, 0x82, 0xA6, 0x12, 0x42, 0x53, 0xE4, 0x90, 0x82, 0xA9, 0xF0, 0x7A, 0x82, 0x79, ++0x9A, 0x80, 0x07, 0xE0, 0x44, 0x21, 0x54, 0xEF, 0xF0, 0x22, 0x90, 0x82, 0xA3, 0x12, 0x42, 0x53, ++0x90, 0x82, 0x58, 0xE0, 0xFF, 0x7D, 0x01, 0x12, 0x4D, 0xB7, 0x90, 0x82, 0xAA, 0x12, 0x5E, 0x75, ++0x90, 0x82, 0xAC, 0xEF, 0xF0, 0x90, 0x82, 0xAA, 0xA3, 0xE0, 0x24, 0x20, 0xF9, 0xE4, 0x34, 0xFC, ++0xFA, 0x7B, 0x01, 0x90, 0x82, 0xA9, 0xE0, 0xFD, 0x12, 0x5E, 0xAA, 0x90, 0x82, 0xAA, 0xA3, 0xE0, ++0x24, 0x30, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, ++0x82, 0xA6, 0x12, 0x42, 0x4A, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x06, 0xD0, 0x01, ++0xD0, 0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x82, 0xAA, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x2F, ++0x24, 0x3A, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, ++0x82, 0xA6, 0x12, 0x42, 0x4A, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x06, 0xD0, 0x01, ++0xD0, 0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x82, 0xAA, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x2F, ++0x24, 0x40, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, ++0x82, 0xA3, 0x12, 0x42, 0x4A, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x04, 0xD0, 0x01, ++0xD0, 0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x06, 0x30, 0xE0, 0x44, 0x10, 0xF0, 0x12, 0x6F, ++0x5B, 0xBF, 0x01, 0x0E, 0x90, 0x82, 0x58, 0xE0, 0x90, 0x04, 0x25, 0xF0, 0x90, 0x04, 0x1F, 0x74, ++0x20, 0xF0, 0x22, 0xE4, 0xFF, 0x74, 0x18, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5, 0x83, 0xE0, ++0xFE, 0x74, 0x5F, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEE, 0xF0, 0x74, 0x10, 0x2F, ++0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x59, 0x2F, 0xF5, 0x82, 0xE4, 0x34, ++0x81, 0xF5, 0x83, 0xEE, 0xF0, 0x0F, 0xEF, 0xB4, 0x06, 0xCB, 0x22, 0x90, 0x82, 0x68, 0xE0, 0x30, ++0xE0, 0x36, 0x90, 0x82, 0x6B, 0xE0, 0x04, 0xF0, 0xE0, 0xFF, 0x90, 0x82, 0x69, 0xE0, 0x6F, 0x70, ++0x27, 0x90, 0x06, 0x92, 0xE0, 0x20, 0xE2, 0x11, 0x90, 0x82, 0x6D, 0xE0, 0x70, 0x0B, 0x12, 0x4F, ++0xC5, 0x90, 0x82, 0x6C, 0xE0, 0x04, 0xF0, 0x80, 0x06, 0x90, 0x06, 0x92, 0x74, 0x04, 0xF0, 0xE4, ++0x90, 0x82, 0x6B, 0xF0, 0x90, 0x82, 0x6D, 0xF0, 0x22, 0x90, 0x82, 0xE1, 0x12, 0x42, 0x53, 0x12, ++0x1F, 0xA4, 0x90, 0x82, 0xE6, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xE7, 0xF0, ++0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xE8, 0xF0, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, ++0x90, 0x82, 0xE9, 0xF0, 0x90, 0x00, 0x06, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xEA, 0xF0, 0x90, 0x00, ++0x07, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xEB, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x82, ++0xEE, 0xF0, 0xED, 0x70, 0x31, 0xFF, 0x74, 0xE6, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, ++0xE0, 0xB4, 0xFF, 0x0E, 0x74, 0xE6, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE4, 0xF0, ++0x80, 0x0F, 0x74, 0xE6, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0x04, 0xF0, 0x80, ++0x05, 0x0F, 0xEF, 0xB4, 0x06, 0xD0, 0x90, 0x82, 0xE5, 0xE0, 0xFF, 0xB4, 0x04, 0x25, 0xA3, 0xE0, ++0xFE, 0x90, 0x82, 0xE1, 0x12, 0x42, 0x4A, 0xEE, 0x12, 0x1F, 0xEA, 0x90, 0x82, 0xE7, 0xE0, 0xFE, ++0x90, 0x82, 0xE1, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x01, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x02, ++0xE4, 0x80, 0x30, 0xEF, 0xB4, 0x02, 0x2F, 0x90, 0x82, 0xE7, 0xE0, 0xFF, 0x90, 0x82, 0xE1, 0x12, ++0x42, 0x4A, 0xEF, 0x12, 0x1F, 0xEA, 0x90, 0x82, 0xE7, 0xE0, 0x44, 0x20, 0x54, 0x7F, 0xFF, 0x90, ++0x82, 0xE1, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xE6, 0xE0, ++0x90, 0x00, 0x02, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xE1, 0x12, 0x42, 0x4A, 0xE9, 0x24, 0x03, 0xF9, ++0xE4, 0x3A, 0xFA, 0x12, 0x1F, 0xA4, 0x44, 0x20, 0x12, 0x1F, 0xEA, 0x90, 0x82, 0xE8, 0xE0, 0xFF, ++0x90, 0x82, 0xE1, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x04, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xE9, ++0xE0, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xEA, 0xE0, 0x90, 0x00, 0x06, 0x12, 0x1F, ++0xFC, 0x90, 0x82, 0xEB, 0xE0, 0x90, 0x00, 0x07, 0x02, 0x1F, 0xFC, 0x90, 0x82, 0xFC, 0xED, 0xF0, ++0x90, 0x82, 0xF9, 0x12, 0x42, 0x53, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x83, 0x00, 0xF0, ++0x90, 0x82, 0xF9, 0x12, 0x42, 0x4A, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x03, 0x7B, ++0x01, 0x7A, 0x82, 0x79, 0xFD, 0x12, 0x2B, 0xED, 0x90, 0x82, 0xFC, 0xE0, 0x70, 0x46, 0xFF, 0x74, ++0xFD, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0xB4, 0xFF, 0x0E, 0x74, 0xFD, 0x2F, ++0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE4, 0xF0, 0x80, 0x0F, 0x74, 0xFD, 0x2F, 0xF5, 0x82, ++0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0x04, 0xF0, 0x80, 0x05, 0x0F, 0xEF, 0xB4, 0x03, 0xD0, 0x75, ++0x13, 0x01, 0x75, 0x14, 0x82, 0x75, 0x15, 0xFD, 0x75, 0x16, 0x03, 0x90, 0x82, 0xF9, 0x12, 0x42, ++0x4A, 0x12, 0x2B, 0xED, 0x22, 0x00, 0xDB, 0x90, ++}; ++#if 0 ++u4Byte ArrayLength_8188E_FW_WoWLAN = 15554; ++ ++ ++void ++ODM_ReadFirmware_8188E_FW_WoWLAN( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++) ++{ ++ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_WoWLAN, ArrayLength_8188E_FW_WoWLAN); ++ *pFirmwareSize = ArrayLength_8188E_FW_WoWLAN; ++} ++ ++#endif ++ ++#endif // end of DM_ODM_SUPPORT_TYPE & (ODM_AP) ++ ++ ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h +new file mode 100644 +index 00000000..b62d5191 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h +@@ -0,0 +1,65 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#if (RTL8188E_SUPPORT == 1) ++#ifndef __INC_FW_8188E_HW_IMG_H ++#define __INC_FW_8188E_HW_IMG_H ++ ++ ++/****************************************************************************** ++* FW_AP.TXT ++******************************************************************************/ ++#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) ++void ++ODM_ReadFirmware_8188E_FW_AP( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++); ++ ++#else ++/****************************************************************************** ++* FW_NIC.TXT ++******************************************************************************/ ++#if 0 ++void ++ODM_ReadFirmware_8188E_FW_NIC( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++); ++#endif ++/****************************************************************************** ++* FW_WoWLAN.TXT ++******************************************************************************/ ++#if 0 ++void ++ODM_ReadFirmware_8188E_FW_WoWLAN( ++ IN PDM_ODM_T pDM_Odm, ++ OUT u1Byte *pFirmware, ++ OUT u4Byte *pFirmwareSize ++); ++#endif ++#define ArrayLength_8188E_FW_WoWLAN 15080 ++extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN]; ++#endif ++ ++#endif ++#endif // end of HWIMG_SUPPORT +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c +new file mode 100644 +index 00000000..5483de97 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c +@@ -0,0 +1,502 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#include "../odm_precomp.h" ++#ifdef CONFIG_IOL_IOREG_CFG ++#include ++#endif ++#if (RTL8188E_SUPPORT == 1) ++static BOOLEAN ++CheckCondition( ++ const u4Byte Condition, ++ const u4Byte Hex ++ ) ++{ ++ u4Byte _board = (Hex & 0x000000FF); ++ u4Byte _interface = (Hex & 0x0000FF00) >> 8; ++ u4Byte _platform = (Hex & 0x00FF0000) >> 16; ++ u4Byte cond = Condition; ++ ++ if ( Condition == 0xCDCDCDCD ) ++ return TRUE; ++ ++ cond = Condition & 0x000000FF; ++ if ( (_board != cond) && (cond != 0xFF) ) ++ return FALSE; ++ ++ cond = Condition & 0x0000FF00; ++ cond = cond >> 8; ++ if ( ((_interface & cond) == 0) && (cond != 0x07) ) ++ return FALSE; ++ ++ cond = Condition & 0x00FF0000; ++ cond = cond >> 16; ++ if ( ((_platform & cond) == 0) && (cond != 0x0F) ) ++ return FALSE; ++ return TRUE; ++} ++ ++ ++/****************************************************************************** ++* MAC_REG.TXT ++******************************************************************************/ ++ ++u4Byte Array_MAC_REG_8188E[] = { ++ 0x026, 0x00000041, ++ 0x027, 0x00000035, ++ 0xFF0F0718, 0xABCD, ++ 0x040, 0x0000000C, ++ 0xCDCDCDCD, 0xCDCD, ++ 0x040, 0x00000000, ++ 0xFF0F0718, 0xDEAD, ++ 0x428, 0x0000000A, ++ 0x429, 0x00000010, ++ 0x430, 0x00000000, ++ 0x431, 0x00000001, ++ 0x432, 0x00000002, ++ 0x433, 0x00000004, ++ 0x434, 0x00000005, ++ 0x435, 0x00000006, ++ 0x436, 0x00000007, ++ 0x437, 0x00000008, ++ 0x438, 0x00000000, ++ 0x439, 0x00000000, ++ 0x43A, 0x00000001, ++ 0x43B, 0x00000002, ++ 0x43C, 0x00000004, ++ 0x43D, 0x00000005, ++ 0x43E, 0x00000006, ++ 0x43F, 0x00000007, ++ 0x440, 0x0000005D, ++ 0x441, 0x00000001, ++ 0x442, 0x00000000, ++ 0x444, 0x00000015, ++ 0x445, 0x000000F0, ++ 0x446, 0x0000000F, ++ 0x447, 0x00000000, ++ 0x458, 0x00000041, ++ 0x459, 0x000000A8, ++ 0x45A, 0x00000072, ++ 0x45B, 0x000000B9, ++ 0x460, 0x00000066, ++ 0x461, 0x00000066, ++ 0x480, 0x00000008, ++ 0x4C8, 0x000000FF, ++ 0x4C9, 0x00000008, ++ 0x4CC, 0x000000FF, ++ 0x4CD, 0x000000FF, ++ 0x4CE, 0x00000001, ++ 0x4D3, 0x00000001, ++ 0x500, 0x00000026, ++ 0x501, 0x000000A2, ++ 0x502, 0x0000002F, ++ 0x503, 0x00000000, ++ 0x504, 0x00000028, ++ 0x505, 0x000000A3, ++ 0x506, 0x0000005E, ++ 0x507, 0x00000000, ++ 0x508, 0x0000002B, ++ 0x509, 0x000000A4, ++ 0x50A, 0x0000005E, ++ 0x50B, 0x00000000, ++ 0x50C, 0x0000004F, ++ 0x50D, 0x000000A4, ++ 0x50E, 0x00000000, ++ 0x50F, 0x00000000, ++ 0x512, 0x0000001C, ++ 0x514, 0x0000000A, ++ 0x516, 0x0000000A, ++ 0x525, 0x0000004F, ++ 0x550, 0x00000010, ++ 0x551, 0x00000010, ++ 0x559, 0x00000002, ++ 0x55D, 0x000000FF, ++ 0x605, 0x00000030, ++ 0x608, 0x0000000E, ++ 0x609, 0x0000002A, ++ 0x620, 0x000000FF, ++ 0x621, 0x000000FF, ++ 0x622, 0x000000FF, ++ 0x623, 0x000000FF, ++ 0x624, 0x000000FF, ++ 0x625, 0x000000FF, ++ 0x626, 0x000000FF, ++ 0x627, 0x000000FF, ++ 0x652, 0x00000020, ++ 0x63C, 0x0000000A, ++ 0x63D, 0x0000000A, ++ 0x63E, 0x0000000E, ++ 0x63F, 0x0000000E, ++ 0x640, 0x00000040, ++ 0x66E, 0x00000005, ++ 0x700, 0x00000021, ++ 0x701, 0x00000043, ++ 0x702, 0x00000065, ++ 0x703, 0x00000087, ++ 0x708, 0x00000021, ++ 0x709, 0x00000043, ++ 0x70A, 0x00000065, ++ 0x70B, 0x00000087, ++}; ++ ++HAL_STATUS ++ODM_ReadAndConfig_MAC_REG_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte interfaceValue = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u4Byte); ++ pu4Byte Array = Array_MAC_REG_8188E; ++ BOOLEAN biol = FALSE; ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ struct xmit_frame *pxmit_frame; ++ u8 bndy_cnt = 1; ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ struct cmd_cmp cmpdata[ArrayLen]; ++ u4Byte cmpdata_idx=0; ++ #endif ++#endif //CONFIG_IOL_IOREG_CFG ++ HAL_STATUS rst =HAL_STATUS_SUCCESS; ++ hex += board; ++ hex += interfaceValue << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++ biol = rtw_IOL_applied(Adapter); ++ ++ if(biol){ ++ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ { ++ printk("rtw_IOL_accquire_xmit_frame failed\n"); ++ return HAL_STATUS_FAILURE; ++ } ++ } ++ ++#endif //CONFIG_IOL_IOREG_CFG ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ ++ if(biol){ ++ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ } ++ else ++ #endif //endif CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); ++ } ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while ( v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while ( v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); ++ } ++ ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); ++ ++ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ printk("~~~ IOL Config MAC Success !!! \n"); ++ //compare writed data ++ { ++ u4Byte idx; ++ u1Byte cdata; ++ // HAL_STATUS_FAILURE; ++ printk(" MAC data compare => array_len:%d \n",cmpdata_idx); ++ for(idx=0;idx< cmpdata_idx;idx++) ++ { ++ cdata = ODM_Read1Byte(pDM_Odm, cmpdata[idx].addr); ++ if(cdata != cmpdata[idx].value){ ++ printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n", ++ cmpdata[idx].addr,cmpdata[idx].value,cdata); ++ //rst = HAL_STATUS_FAILURE; ++ } ++ } ++ ++ ++ //dump data from TX packet buffer ++ //if(rst == HAL_STATUS_FAILURE) ++ { ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ ++ } ++ else{ ++ printk("~~~ MAC IOL_exec_cmds Failed !!! \n"); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ { ++ //dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ rst = HAL_STATUS_FAILURE; ++ } ++ ++ } ++#endif //#ifdef CONFIG_IOL_IOREG_CFG ++ return rst; ++} ++ ++/****************************************************************************** ++* MAC_REG_ICUT.TXT ++******************************************************************************/ ++ ++u4Byte Array_MP_8188E_MAC_REG_ICUT[] = { ++ 0x026, 0x00000041, ++ 0x027, 0x00000035, ++ 0x428, 0x0000000A, ++ 0x429, 0x00000010, ++ 0x430, 0x00000000, ++ 0x431, 0x00000001, ++ 0x432, 0x00000002, ++ 0x433, 0x00000004, ++ 0x434, 0x00000005, ++ 0x435, 0x00000006, ++ 0x436, 0x00000007, ++ 0x437, 0x00000008, ++ 0x438, 0x00000000, ++ 0x439, 0x00000000, ++ 0x43A, 0x00000001, ++ 0x43B, 0x00000002, ++ 0x43C, 0x00000004, ++ 0x43D, 0x00000005, ++ 0x43E, 0x00000006, ++ 0x43F, 0x00000007, ++ 0x440, 0x0000005D, ++ 0x441, 0x00000001, ++ 0x442, 0x00000000, ++ 0x444, 0x00000015, ++ 0x445, 0x000000F0, ++ 0x446, 0x0000000F, ++ 0x447, 0x00000000, ++ 0x458, 0x00000041, ++ 0x459, 0x000000A8, ++ 0x45A, 0x00000072, ++ 0x45B, 0x000000B9, ++ 0x460, 0x00000066, ++ 0x461, 0x00000066, ++ 0x480, 0x00000008, ++ 0x4C8, 0x000000FF, ++ 0x4C9, 0x00000008, ++ 0x4CC, 0x000000FF, ++ 0x4CD, 0x000000FF, ++ 0x4CE, 0x00000001, ++ 0x4D3, 0x00000001, ++ 0x500, 0x00000026, ++ 0x501, 0x000000A2, ++ 0x502, 0x0000002F, ++ 0x503, 0x00000000, ++ 0x504, 0x00000028, ++ 0x505, 0x000000A3, ++ 0x506, 0x0000005E, ++ 0x507, 0x00000000, ++ 0x508, 0x0000002B, ++ 0x509, 0x000000A4, ++ 0x50A, 0x0000005E, ++ 0x50B, 0x00000000, ++ 0x50C, 0x0000004F, ++ 0x50D, 0x000000A4, ++ 0x50E, 0x00000000, ++ 0x50F, 0x00000000, ++ 0x512, 0x0000001C, ++ 0x514, 0x0000000A, ++ 0x516, 0x0000000A, ++ 0x525, 0x0000004F, ++ 0x550, 0x00000010, ++ 0x551, 0x00000010, ++ 0x559, 0x00000002, ++ 0x55D, 0x000000FF, ++ 0x605, 0x00000030, ++ 0x608, 0x0000000E, ++ 0x609, 0x0000002A, ++ 0x620, 0x000000FF, ++ 0x621, 0x000000FF, ++ 0x622, 0x000000FF, ++ 0x623, 0x000000FF, ++ 0x624, 0x000000FF, ++ 0x625, 0x000000FF, ++ 0x626, 0x000000FF, ++ 0x627, 0x000000FF, ++ 0x652, 0x00000020, ++ 0x63C, 0x0000000A, ++ 0x63D, 0x0000000A, ++ 0x63E, 0x0000000E, ++ 0x63F, 0x0000000E, ++ 0x640, 0x00000040, ++ 0x66E, 0x00000005, ++ 0x700, 0x00000021, ++ 0x701, 0x00000043, ++ 0x702, 0x00000065, ++ 0x703, 0x00000087, ++ 0x708, 0x00000021, ++ 0x709, 0x00000043, ++ 0x70A, 0x00000065, ++ 0x70B, 0x00000087, ++ ++}; ++ ++void ++ODM_ReadAndConfig_MAC_REG_ICUT_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte _interface = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_MP_8188E_MAC_REG_ICUT)/sizeof(u4Byte); ++ pu4Byte Array = Array_MP_8188E_MAC_REG_ICUT; ++ ++ ++ hex += board; ++ hex += _interface << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG_ICUT, hex = 0x%X\n", hex)); ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++ ++} ++ ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h +new file mode 100644 +index 00000000..f2c2e475 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h +@@ -0,0 +1,47 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#if (RTL8188E_SUPPORT == 1) ++#ifndef __INC_MAC_8188E_HW_IMG_H ++#define __INC_MAC_8188E_HW_IMG_H ++ ++//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); ++ ++/****************************************************************************** ++* MAC_REG.TXT ++******************************************************************************/ ++ ++HAL_STATUS ++ODM_ReadAndConfig_MAC_REG_8188E( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++/****************************************************************************** ++* MAC_REG_ICUT.TXT ++******************************************************************************/ ++ ++void ++ODM_ReadAndConfig_MAC_REG_ICUT_8188E( // TC: Test Chip, MP: MP Chip ++ IN PDM_ODM_T pDM_Odm ++); ++ ++#endif ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c +new file mode 100644 +index 00000000..3941ec2e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c +@@ -0,0 +1,569 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#include "../odm_precomp.h" ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++#include ++#endif ++ ++#if (RTL8188E_SUPPORT == 1) ++static BOOLEAN ++CheckCondition( ++ const u4Byte Condition, ++ const u4Byte Hex ++ ) ++{ ++ u4Byte _board = (Hex & 0x000000FF); ++ u4Byte _interface = (Hex & 0x0000FF00) >> 8; ++ u4Byte _platform = (Hex & 0x00FF0000) >> 16; ++ u4Byte cond = Condition; ++ ++ if ( Condition == 0xCDCDCDCD ) ++ return TRUE; ++ ++ cond = Condition & 0x000000FF; ++ if ( (_board != cond) && (cond != 0xFF) ) ++ return FALSE; ++ ++ cond = Condition & 0x0000FF00; ++ cond = cond >> 8; ++ if ( ((_interface & cond) == 0) && (cond != 0x07) ) ++ return FALSE; ++ ++ cond = Condition & 0x00FF0000; ++ cond = cond >> 16; ++ if ( ((_platform & cond) == 0) && (cond != 0x0F) ) ++ return FALSE; ++ return TRUE; ++} ++ ++ ++/****************************************************************************** ++* RadioA_1T.TXT ++******************************************************************************/ ++ ++u4Byte Array_RadioA_1T_8188E[] = { ++ 0x000, 0x00030000, ++ 0x008, 0x00084000, ++ 0x018, 0x00000407, ++ 0x019, 0x00000012, ++ 0x01E, 0x00080009, ++ 0x01F, 0x00000880, ++ 0x02F, 0x0001A060, ++ 0x03F, 0x00000000, ++ 0x042, 0x000060C0, ++ 0x057, 0x000D0000, ++ 0x058, 0x000BE180, ++ 0x067, 0x00001552, ++ 0x083, 0x00000000, ++ 0x0B0, 0x000FF8FC, ++ 0x0B1, 0x00054400, ++ 0x0B2, 0x000CCC19, ++ 0x0B4, 0x00043003, ++ 0x0B6, 0x0004953E, ++ 0x0B7, 0x0001C718, ++ 0x0B8, 0x000060FF, ++ 0x0B9, 0x00080001, ++ 0x0BA, 0x00040000, ++ 0x0BB, 0x00000400, ++ 0x0BF, 0x000C0000, ++ 0x0C2, 0x00002400, ++ 0x0C3, 0x00000009, ++ 0x0C4, 0x00040C91, ++ 0x0C5, 0x00099999, ++ 0x0C6, 0x000000A3, ++ 0x0C7, 0x00088820, ++ 0x0C8, 0x00076C06, ++ 0x0C9, 0x00000000, ++ 0x0CA, 0x00080000, ++ 0x0DF, 0x00000180, ++ 0x0EF, 0x000001A0, ++ 0x051, 0x0006B27D, ++ 0xFF0F0400, 0xABCD, ++ 0x052, 0x0007E4DD, ++ 0xCDCDCDCD, 0xCDCD, ++ 0x052, 0x0007E49D, ++ 0xFF0F0400, 0xDEAD, ++ 0x053, 0x00000073, ++ 0x056, 0x00051FF3, ++ 0x035, 0x00000086, ++ 0x035, 0x00000186, ++ 0x035, 0x00000286, ++ 0x036, 0x00001C25, ++ 0x036, 0x00009C25, ++ 0x036, 0x00011C25, ++ 0x036, 0x00019C25, ++ 0x0B6, 0x00048538, ++ 0x018, 0x00000C07, ++ 0x05A, 0x0004BD00, ++ 0x019, 0x000739D0, ++ 0xFF0F0718, 0xABCD, ++ 0x034, 0x0000A093, ++ 0x034, 0x0000908F, ++ 0x034, 0x0000808C, ++ 0x034, 0x0000704F, ++ 0x034, 0x0000604C, ++ 0x034, 0x00005049, ++ 0x034, 0x0000400C, ++ 0x034, 0x00003009, ++ 0x034, 0x00002006, ++ 0x034, 0x00001003, ++ 0x034, 0x00000000, ++ 0xCDCDCDCD, 0xCDCD, ++ 0x034, 0x0000ADF3, ++ 0x034, 0x00009DF0, ++ 0x034, 0x00008DED, ++ 0x034, 0x00007DEA, ++ 0x034, 0x00006DE7, ++ 0x034, 0x000054EE, ++ 0x034, 0x000044EB, ++ 0x034, 0x000034E8, ++ 0x034, 0x0000246B, ++ 0x034, 0x00001468, ++ 0x034, 0x0000006D, ++ 0xFF0F0718, 0xDEAD, ++ 0x000, 0x00030159, ++ 0x084, 0x00068200, ++ 0x086, 0x000000CE, ++ 0x087, 0x00048A00, ++ 0x08E, 0x00065540, ++ 0x08F, 0x00088000, ++ 0x0EF, 0x000020A0, ++ 0x03B, 0x000F02B0, ++ 0x03B, 0x000EF7B0, ++ 0x03B, 0x000D4FB0, ++ 0x03B, 0x000CF060, ++ 0x03B, 0x000B0090, ++ 0x03B, 0x000A0080, ++ 0x03B, 0x00090080, ++ 0x03B, 0x0008F780, ++ 0x03B, 0x000722B0, ++ 0x03B, 0x0006F7B0, ++ 0x03B, 0x00054FB0, ++ 0x03B, 0x0004F060, ++ 0x03B, 0x00030090, ++ 0x03B, 0x00020080, ++ 0x03B, 0x00010080, ++ 0x03B, 0x0000F780, ++ 0x0EF, 0x000000A0, ++ 0x000, 0x00010159, ++ 0x018, 0x0000F407, ++ 0xFFE, 0x00000000, ++ 0xFFE, 0x00000000, ++ 0x01F, 0x00080003, ++ 0xFFE, 0x00000000, ++ 0xFFE, 0x00000000, ++ 0x01E, 0x00000001, ++ 0x01F, 0x00080000, ++ 0x000, 0x00033E60, ++ ++}; ++ ++HAL_STATUS ++ODM_ReadAndConfig_RadioA_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte interfaceValue = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u4Byte); ++ pu4Byte Array = Array_RadioA_1T_8188E; ++ BOOLEAN biol = FALSE; ++#ifdef CONFIG_IOL_IOREG_CFG ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ struct xmit_frame *pxmit_frame; ++ u8 bndy_cnt = 1; ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ struct cmd_cmp cmpdata[ArrayLen]; ++ u4Byte cmpdata_idx=0; ++ #endif ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ HAL_STATUS rst =HAL_STATUS_SUCCESS; ++ ++ hex += board; ++ hex += interfaceValue << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++#ifdef CONFIG_IOL_IOREG_CFG ++ biol = rtw_IOL_applied(Adapter); ++ ++ if(biol){ ++ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ { ++ printk("rtw_IOL_accquire_xmit_frame failed\n"); ++ return HAL_STATUS_FAILURE; ++ } ++ } ++#endif//#ifdef CONFIG_IOL_IOREG_CFG ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ ++ if(v1 == 0xffe) ++ { ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfd){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xfc){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); ++ } ++ else if (v1 == 0xfb){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfa){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xf9){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); ++ } ++ else{ ++ rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ; ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ } ++ ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); ++ } ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) ++ bndy_cnt++; ++ ++ if(v1 == 0xffe) ++ { ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfd){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xfc){ ++ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); ++ } ++ else if (v1 == 0xfb){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); ++ } ++ else if (v1 == 0xfa){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); ++ } ++ else if (v1 == 0xf9){ ++ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); ++ } ++ else{ ++ rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ; ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ cmpdata[cmpdata_idx].addr = v1; ++ cmpdata[cmpdata_idx].value= v2; ++ cmpdata_idx++; ++ #endif ++ ++ } ++ ++ } ++ else ++ #endif //#ifdef CONFIG_IOL_IOREG_CFG ++ { ++ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); ++ } ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++#ifdef CONFIG_IOL_IOREG_CFG ++ if(biol){ ++ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); ++ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) ++ { ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ printk("~~~ %s Success !!! \n",__FUNCTION__); ++ { ++ u4Byte idx; ++ u4Byte cdata; ++ printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx); ++ printk("### %s data compared !!###\n",__FUNCTION__); ++ for(idx=0;idx< cmpdata_idx;idx++) ++ { ++ cdata = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A,cmpdata[idx].addr,bRFRegOffsetMask); ++ if(cdata != cmpdata[idx].value){ ++ printk("addr:0x%04x, data:(0x%02x : 0x%02x) \n", ++ cmpdata[idx].addr,cmpdata[idx].value,cdata); ++ rst = HAL_STATUS_FAILURE; ++ } ++ } ++ printk("### %s data compared !!###\n",__FUNCTION__); ++ //if(rst == HAL_STATUS_FAILURE) ++ {//dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ ++ } ++ else{ ++ rst = HAL_STATUS_FAILURE; ++ printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); ++ #ifdef CONFIG_IOL_IOREG_CFG_DBG ++ { ++ //dump data from TX packet buffer ++ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); ++ } ++ #endif //CONFIG_IOL_IOREG_CFG_DBG ++ } ++ } ++ ++ ++#endif //#ifdef CONFIG_IOL_IOREG_CFG ++ return rst; ++} ++/****************************************************************************** ++* RadioA_1T_ICUT.TXT ++******************************************************************************/ ++ ++u4Byte Array_MP_8188E_RadioA_1T_ICUT[] = { ++ 0x000, 0x00030000, ++ 0x008, 0x00084000, ++ 0x018, 0x00000407, ++ 0x019, 0x00000012, ++ 0x01E, 0x00080009, ++ 0x01F, 0x00000880, ++ 0x02F, 0x0001A060, ++ 0x03F, 0x00000000, ++ 0x042, 0x000060C0, ++ 0x057, 0x000D0000, ++ 0x058, 0x000BE180, ++ 0x067, 0x00001552, ++ 0x083, 0x00000000, ++ 0x0B0, 0x000FF8FC, ++ 0x0B1, 0x00054400, ++ 0x0B2, 0x000CCC19, ++ 0x0B4, 0x00043003, ++ 0x0B6, 0x0004953E, ++ 0x0B7, 0x0001C718, ++ 0x0B8, 0x000060FF, ++ 0x0B9, 0x00080001, ++ 0x0BA, 0x00040000, ++ 0x0BB, 0x00000400, ++ 0x0BF, 0x000C0000, ++ 0x0C2, 0x00002400, ++ 0x0C3, 0x00000009, ++ 0x0C4, 0x00040C91, ++ 0x0C5, 0x00099999, ++ 0x0C6, 0x000000A3, ++ 0x0C7, 0x00088820, ++ 0x0C8, 0x00076C06, ++ 0x0C9, 0x00000000, ++ 0x0CA, 0x00080000, ++ 0x0DF, 0x00000180, ++ 0x0EF, 0x000001A0, ++ 0x051, 0x0006B27D, ++ 0xFF0F0400, 0xABCD, ++ 0x052, 0x0007E4DD, ++ 0xCDCDCDCD, 0xCDCD, ++ 0x052, 0x0007E49D, ++ 0xFF0F0400, 0xDEAD, ++ 0x053, 0x00000073, ++ 0x056, 0x00051FF3, ++ 0x035, 0x00000086, ++ 0x035, 0x00000186, ++ 0x035, 0x00000286, ++ 0x036, 0x00001C25, ++ 0x036, 0x00009C25, ++ 0x036, 0x00011C25, ++ 0x036, 0x00019C25, ++ 0x0B6, 0x00048538, ++ 0x018, 0x00000C07, ++ 0x05A, 0x0004BD00, ++ 0x019, 0x000739D0, ++ 0x034, 0x0000ADF3, ++ 0x034, 0x00009DF0, ++ 0x034, 0x00008DED, ++ 0x034, 0x00007DEA, ++ 0x034, 0x00006DE7, ++ 0x034, 0x000054EE, ++ 0x034, 0x000044EB, ++ 0x034, 0x000034E8, ++ 0x034, 0x0000246B, ++ 0x034, 0x00001468, ++ 0x034, 0x0000006D, ++ 0x000, 0x00030159, ++ 0x084, 0x00068200, ++ 0x086, 0x000000CE, ++ 0x087, 0x00048A00, ++ 0x08E, 0x00065540, ++ 0x08F, 0x00088000, ++ 0x0EF, 0x000020A0, ++ 0x03B, 0x000F02B0, ++ 0x03B, 0x000EF7B0, ++ 0x03B, 0x000D4FB0, ++ 0x03B, 0x000CF060, ++ 0x03B, 0x000B0090, ++ 0x03B, 0x000A0080, ++ 0x03B, 0x00090080, ++ 0x03B, 0x0008F780, ++ 0x03B, 0x000722B0, ++ 0x03B, 0x0006F7B0, ++ 0x03B, 0x00054FB0, ++ 0x03B, 0x0004F060, ++ 0x03B, 0x00030090, ++ 0x03B, 0x00020080, ++ 0x03B, 0x00010080, ++ 0x03B, 0x0000F780, ++ 0x0EF, 0x000000A0, ++ 0x000, 0x00010159, ++ 0x018, 0x0000F407, ++ 0xFFE, 0x00000000, ++ 0xFFE, 0x00000000, ++ 0x01F, 0x00080003, ++ 0xFFE, 0x00000000, ++ 0xFFE, 0x00000000, ++ 0x01E, 0x00000001, ++ 0x01F, 0x00080000, ++ 0x000, 0x00033E60, ++ ++}; ++ ++void ++ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) ++ ++ u4Byte hex = 0; ++ u4Byte i = 0; ++ u2Byte count = 0; ++ pu4Byte ptr_array = NULL; ++ u1Byte platform = pDM_Odm->SupportPlatform; ++ u1Byte _interface = pDM_Odm->SupportInterface; ++ u1Byte board = pDM_Odm->BoardType; ++ u4Byte ArrayLen = sizeof(Array_MP_8188E_RadioA_1T_ICUT)/sizeof(u4Byte); ++ pu4Byte Array = Array_MP_8188E_RadioA_1T_ICUT; ++ ++ ++ hex += board; ++ hex += _interface << 8; ++ hex += platform << 16; ++ hex += 0xFF000000; ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_RadioA_1T_ICUT, hex = 0x%X\n", hex)); ++ ++ for (i = 0; i < ArrayLen; i += 2 ) ++ { ++ u4Byte v1 = Array[i]; ++ u4Byte v2 = Array[i+1]; ++ ++ // This (offset, data) pair meets the condition. ++ if ( v1 < 0xCDCDCDCD ) ++ { ++ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); ++ continue; ++ } ++ else ++ { // This line is the start line of branch. ++ if ( !CheckCondition(Array[i], hex) ) ++ { // Discard the following (offset, data) pairs. ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ i -= 2; // prevent from for-loop += 2 ++ } ++ else // Configure matched pairs and skip to end of if-else. ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ while (v2 != 0xDEAD && ++ v2 != 0xCDEF && ++ v2 != 0xCDCD && i < ArrayLen -2) ++ { ++ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ while (v2 != 0xDEAD && i < ArrayLen -2) ++ { ++ READ_NEXT_PAIR(v1, v2, i); ++ } ++ ++ } ++ } ++ } ++ ++} ++ ++ ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h +new file mode 100644 +index 00000000..46a029fc +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h +@@ -0,0 +1,45 @@ ++/****************************************************************************** ++* ++* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++* ++* This program is free software; you can redistribute it and/or modify it ++* under the terms of version 2 of the GNU General Public License as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++* more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++* ++* ++******************************************************************************/ ++ ++#if (RTL8188E_SUPPORT == 1) ++#ifndef __INC_RF_8188E_HW_IMG_H ++#define __INC_RF_8188E_HW_IMG_H ++ ++//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); ++ ++/****************************************************************************** ++* RadioA_1T.TXT ++******************************************************************************/ ++ ++HAL_STATUS ++ODM_ReadAndConfig_RadioA_1T_8188E( ++ IN PDM_ODM_T pDM_Odm ++); ++/****************************************************************************** ++* RadioA_1T_ICUT.TXT ++******************************************************************************/ ++ ++void ++ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip ++ IN PDM_ODM_T pDM_Odm ++); ++#endif ++#endif // end of HWIMG_SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c +new file mode 100644 +index 00000000..9817b7b6 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c +@@ -0,0 +1,3468 @@ ++ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include "../odm_precomp.h" ++ ++ ++ ++/*---------------------------Define Local Constant---------------------------*/ ++// 2010/04/25 MH Define the max tx power tracking tx agc power. ++#define ODM_TXPWRTRACK_MAX_IDX_88E 6 ++ ++#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ ++ do {\ ++ for(_offset = 0; _offset < _size; _offset++)\ ++ {\ ++ if(_deltaThermal < thermalThreshold[_direction][_offset])\ ++ {\ ++ if(_offset != 0)\ ++ _offset--;\ ++ break;\ ++ }\ ++ } \ ++ if(_offset >= _size)\ ++ _offset = _size-1;\ ++ } while(0) ++ ++//3============================================================ ++//3 Tx Power Tracking ++//3============================================================ ++void setIqkMatrix( ++ PDM_ODM_T pDM_Odm, ++ u1Byte OFDM_index, ++ u1Byte RFPath, ++ s4Byte IqkResult_X, ++ s4Byte IqkResult_Y ++ ) ++{ ++ s4Byte ele_A=0, ele_D, ele_C=0, TempCCk, value32; ++ ++ //printk("%s==> OFDM_index:%d \n",__FUNCTION__,OFDM_index); ++ ++ //if(OFDM_index> OFDM_TABLE_SIZE_92D) ++ //{ ++ //printk("%s==> OFDM_index> 43\n",__FUNCTION__); ++ //} ++ ele_D = (OFDMSwingTable[OFDM_index] & 0xFFC00000)>>22; ++ ++ //new element A = element D x X ++ if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) ++ { ++ if ((IqkResult_X & 0x00000200) != 0) //consider minus ++ IqkResult_X = IqkResult_X | 0xFFFFFC00; ++ ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; ++ ++ //new element C = element D x Y ++ if ((IqkResult_Y & 0x00000200) != 0) ++ IqkResult_Y = IqkResult_Y | 0xFFFFFC00; ++ ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; ++ ++ if (RFPath == RF_PATH_A) ++ switch (RFPath) ++ { ++ case RF_PATH_A: ++ //wirte new elements A, C, D to regC80 and regC94, element B is always 0 ++ value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); ++ ++ value32 = (ele_C&0x000003C0)>>6; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); ++ ++ value32 = ((IqkResult_X * ele_D)>>7)&0x01; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); ++ break; ++ case RF_PATH_B: ++ //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 ++ value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); ++ ++ value32 = (ele_C&0x000003C0)>>6; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); ++ ++ value32 = ((IqkResult_X * ele_D)>>7)&0x01; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); ++ ++ break; ++ default: ++ break; ++ } ++ } ++ else ++ { ++ switch (RFPath) ++ { ++ case RF_PATH_A: ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index]); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); ++ break; ++ ++ case RF_PATH_B: ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index]); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", ++ (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); ++} ++ ++ ++void doIQK( ++ PDM_ODM_T pDM_Odm, ++ u1Byte DeltaThermalIndex, ++ u1Byte ThermalValue, ++ u1Byte Threshold ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#endif ++ ++ ODM_ResetIQKResult(pDM_Odm); ++ ++#if(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++#if USE_WORKITEM ++ PlatformAcquireMutex(&pHalData->mxChnlBwControl); ++#else ++ PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); ++#endif ++#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) ++ PlatformAcquireMutex(&pHalData->mxChnlBwControl); ++#endif ++#endif ++ ++ ++ pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; ++ PHY_IQCalibrate_8188E(Adapter, FALSE); ++ ++ ++#if(DM_ODM_SUPPORT_TYPE & ODM_MP) ++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) ++#if USE_WORKITEM ++ PlatformReleaseMutex(&pHalData->mxChnlBwControl); ++#else ++ PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); ++#endif ++#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) ++ PlatformReleaseMutex(&pHalData->mxChnlBwControl); ++#endif ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: ODM_TxPwrTrackAdjust88E() ++ * ++ * Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc. ++ * No matter OFDM & CCK use the same method. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 04/23/2012 MHC Create Version 0. ++ * 04/23/2012 MHC Adjust TX agc directly not throughput BB digital. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++ODM_TxPwrTrackAdjust88E( ++ PDM_ODM_T pDM_Odm, ++ u1Byte Type, // 0 = OFDM, 1 = CCK ++ pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease) ++ pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust ++ ) ++{ ++ u1Byte pwr_value = 0; ++ // ++ // Tx power tracking BB swing table. ++ // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB ++ // ++ if (Type == 0) // For OFDM afjust ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm)); ++ ++ //printk("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm); ++ if (pDM_Odm->BbSwingIdxOfdm <= pDM_Odm->BbSwingIdxOfdmBase) ++ { ++ *pDirection = 1; ++ pwr_value = (pDM_Odm->BbSwingIdxOfdmBase - pDM_Odm->BbSwingIdxOfdm); ++ } ++ else ++ { ++ *pDirection = 2; ++ pwr_value = (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase); ++ } ++ ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("BbSwingIdxOfdm = %d BbSwingIdxOfdmBase=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase)); ++ //printk("BbSwingIdxOfdm = %d BbSwingIdxOfdmBase=%d pwr_value=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase,pwr_value); ++ ++ } ++ else if (Type == 1) // For CCK adjust. ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase)); ++ ++ //printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase); ++ if (pDM_Odm->BbSwingIdxCck <= pDM_Odm->BbSwingIdxCckBase) ++ { ++ *pDirection = 1; ++ pwr_value = (pDM_Odm->BbSwingIdxCckBase - pDM_Odm->BbSwingIdxCck); ++ } ++ else ++ { ++ *pDirection = 2; ++ pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); ++ } ++ //printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d pwr_value:%d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase,pwr_value); ++ } ++ ++ // ++ // 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking ++ // need to be less than 6 power index for 88E. ++ // ++ if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1) ++ pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; ++ ++ *pOutWriteVal = pwr_value | (pwr_value<<8) | (pwr_value<<16) | (pwr_value<<24); ++ ++} // ODM_TxPwrTrackAdjust88E ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: odm_TxPwrTrackSetPwr88E() ++ * ++ * Overview: 88E change all channel tx power accordign to flag. ++ * OFDM & CCK are all different. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 04/23/2012 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++odm_TxPwrTrackSetPwr88E( ++ PDM_ODM_T pDM_Odm, ++ PWRTRACK_METHOD Method, ++ u1Byte RFPath, ++ u1Byte ChannelMappedIndex ++ ) ++{ ++ if (Method == TXAGC) ++ { ++ u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT]; ++ u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; ++ u1Byte rf = 0; ++ u4Byte pwr = 0, TxAGC = 0; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ //printk("odm_TxPwrTrackSetPwr88E CH=%d, modify TXAGC \n", *(pDM_Odm->pChannel)); ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE )) ++ ++ //#if (MP_DRIVER != 1) ++ if ( *(pDM_Odm->mp_mode) != 1){ ++ PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); ++ } ++ else ++ //#else ++ { ++ pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); ++ pwr += (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); ++ PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); ++ TxAGC = (pwr<<16)|(pwr<<8)|(pwr); ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); ++ DBG_871X("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC); ++ ++ pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); ++ pwr += (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase); ++ TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); ++ PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); ++ DBG_871X("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC); ++ } ++ //#endif ++ ++#endif ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); ++ PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); ++#endif ++ ++ } ++ else if (Method == BBSWING) ++ { ++ //printk("odm_TxPwrTrackSetPwr88E CH=%d, modify BBSWING BbSwingIdxCck:%d \n", *(pDM_Odm->pChannel),pDM_Odm->BbSwingIdxCck); ++ // Adjust BB swing by CCK filter coefficient ++ //if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) ++ if(* (pDM_Odm->pChannel) < 14) ++ { ++ ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][0]); ++ ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][1]); ++ ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][2]); ++ ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][3]); ++ ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][4]); ++ ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][5]); ++ ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][6]); ++ ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][7]); ++ } ++ else ++ { ++ ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][0]); ++ ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][1]); ++ ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][2]); ++ ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][3]); ++ ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][4]); ++ ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][5]); ++ ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][6]); ++ ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][7]); ++ } ++ ++ // Adjust BB swing by OFDM IQ matrix ++ if (RFPath == RF_PATH_A) ++ { ++ setIqkMatrix(pDM_Odm, pDM_Odm->BbSwingIdxOfdm, RF_PATH_A, ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); ++ } ++ /* ++ else if (RFPath == RF_PATH_B) ++ { ++ setIqkMatrix(pDM_Odm, pDM_Odm->BbSwingIdxOfdm[RF_PATH_B], RF_PATH_B, ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); ++ }*/ ++ } ++ else ++ { ++ return; ++ } ++} // odm_TxPwrTrackSetPwr88E ++ ++ ++VOID ++odm_TXPowerTrackingCallback_ThermalMeter_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER Adapter ++#endif ++ ) ++{ ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++#endif ++ ++ u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; ++ u1Byte ThermalValue_AVG_count = 0; ++ u4Byte ThermalValue_AVG = 0; ++ s4Byte ele_A=0, ele_D, TempCCk, X, value32; ++ s4Byte Y, ele_C=0; ++ s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; ++ s1Byte deltaPowerIndex = 0; ++ u4Byte i = 0, j = 0; ++ BOOLEAN is2T = FALSE; ++ BOOLEAN bInteralPA = FALSE; ++ ++ u1Byte OFDM_min_index = 6, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur ++ u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ ++ enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++ ++ //4 0.1 The following TWO tables decide the final index of OFDM/CCK swing table. ++ s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = { ++ // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} ++ {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,-1,-2,-3,-4,-4,-4,-4,-5,-7,-8,-9,-9,-10} ++ }; ++ u1Byte thermalThreshold[2][index_mapping_NUM_88E]={ ++ // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} ++ {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} ++ }; ++ ++ //4 0.1 Initilization ( 7 steps in total ) ++ ++ pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug ++ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; ++ ++#if (MP_DRIVER == 1) ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. ++#endif ++ // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. ++ pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase)); ++ ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E ++ if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) ++ return; ++ ++ //4 3. Initialize ThermalValues of RFCalibrateInfo ++ ++ if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) ++ { ++ pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; ++ pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; ++ } ++ ++ if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); ++ } ++ ++ //4 4. Calculate average thermal meter ++ ++ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; ++ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; ++ if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) ++ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; ++ ++ for(i = 0; i < AVG_THERMAL_NUM_88E; i++) ++ { ++ if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) ++ { ++ ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; ++ ThermalValue_AVG_count++; ++ } ++ } ++ ++ if(ThermalValue_AVG_count) ++ { ++ ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); ++ } ++ ++ //4 5. Calculate delta, delta_LCK, delta_IQK. ++ ++ delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); ++ delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); ++ delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); ++ ++ //4 6. If necessary, do LCK. ++ ++ //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) ++ if ((delta_LCK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. ++ { ++ pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PHY_LCCalibrate_8188E(Adapter); ++#else ++ PHY_LCCalibrate_8188E(pDM_Odm); ++#endif ++ } ++ ++ //3 7. If necessary, move the index of swing table to adjust Tx power. ++ ++ if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) ++ { ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); ++#else ++ delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); ++#endif ++ ++ ++ //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++ if(ThermalValue > pHalData->EEPROMThermalMeter) { ++#else ++ if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { ++#endif ++ CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = -1 * deltaSwingTableIdx[POWER_INC][offset]; ++ ++ } else { ++ ++ CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; ++ pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = -1 * deltaSwingTableIdx[POWER_DEC][offset]; ++ } ++ ++ if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast) ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; ++ else ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast; ++ ++ for(i = 0; i < rf; i++) ++ pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pDM_Odm->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; ++ pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; ++ ++ pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; ++ pDM_Odm->BbSwingIdxOfdm = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A]; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); ++ ++ //4 7.1 Handle boundary conditions of index. ++ ++ ++ for(i = 0; i < rf; i++) ++ { ++ if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) ++ { ++ pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; ++ } ++ else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < OFDM_min_index) ++ { ++ pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_min_index; ++ } ++ } ++ ++ if(pDM_Odm->RFCalibrateInfo.CCK_index > CCK_TABLE_SIZE-1) ++ pDM_Odm->RFCalibrateInfo.CCK_index = CCK_TABLE_SIZE-1; ++ else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) ++ pDM_Odm->RFCalibrateInfo.CCK_index = 0; ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pDM_Odm->BbSwingIdxCckBase)); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pDM_Odm->BbSwingIdxOfdmBase)); ++ ++ if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) ++ { ++ //4 7.2 Configure the Swing Table to adjust Tx Power. ++ ++ pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. ++ // ++ // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital ++ // to increase TX power. Otherwise, EVM will be bad. ++ // ++ // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. ++ if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); ++ } ++ else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ++ ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", ++ pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); ++ } ++ ++ if (ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); ++ odm_TxPwrTrackSetPwr88E(pDM_Odm, TXAGC, 0, 0); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); ++ odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); ++ //if(is2T) ++ // odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); ++ } ++ ++ pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; ++ pDM_Odm->BbSwingIdxOfdmBase = pDM_Odm->BbSwingIdxOfdm; ++ pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; ++ ++ } ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) ++ if ((delta_IQK >= 8)){ // Delta temperature is equal to or larger than 20 centigrade. ++ //printk("delta_IQK(%d) >=8 do_IQK\n",delta_IQK); ++ doIQK(pDM_Odm, delta_IQK, ThermalValue, 8); ++ } ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); ++ ++ pDM_Odm->RFCalibrateInfo.TXPowercount = 0; ++} ++ ++ ++ ++ ++ ++ ++//1 7. IQK ++#define MAX_TOLERANCE 5 ++#define IQK_DELAY_TIME 1 //ms ++ ++u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++phy_PathA_IQK_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN configPathB ++ ) ++{ ++ u4Byte regEAC, regE94, regE9C, regEA4; ++ u1Byte result = 0x00; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); ++ ++ //1 Tx IQK ++ //path-A IQK setting ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); ++ ++ //LO calibration setting ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); ++ ++ //One shot, path A LOK & IQK ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ++ ++ // delay x ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); ++ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); ++ ODM_delay_ms(IQK_DELAY_TIME_88E); ++ ++ // Check failed ++ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); ++ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); ++ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); ++ regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); ++ ++ if(!(regEAC & BIT28) && ++ (((regE94 & 0x03FF0000)>>16) != 0x142) && ++ (((regE9C & 0x03FF0000)>>16) != 0x42) ) ++ result |= 0x01; ++ else //if Tx not OK, ignore Rx ++ return result; ++ ++#if 0 ++ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK ++ (((regEA4 & 0x03FF0000)>>16) != 0x132) && ++ (((regEAC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); ++#endif ++ ++ return result; ++ ++ ++ } ++ ++u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++phy_PathA_RxIQK( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN configPathB ++ ) ++{ ++ u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; ++ u1Byte result = 0x00; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); ++ ++ //1 Get TXIMR setting ++ //modify RXIQK mode table ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); ++ ++ //PA,PAD off ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 ); ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ++ ++ //IQK setting ++ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); ++ ++ //path-A IQK setting ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); ++ ++ //LO calibration setting ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); ++ ++ //One shot, path A LOK & IQK ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ++ ++ // delay x ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); ++ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); ++ ODM_delay_ms(IQK_DELAY_TIME_88E); ++ ++ ++ // Check failed ++ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); ++ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); ++ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); ++ ++ if(!(regEAC & BIT28) && ++ (((regE94 & 0x03FF0000)>>16) != 0x142) && ++ (((regE9C & 0x03FF0000)>>16) != 0x42) ) ++ { ++ result |= 0x01; ++ } ++ else ++ { ++ //reload RF 0xdf ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );//if Tx not OK, ignore Rx ++ return result; ++ } ++ ++ u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); ++ ++ ++ //1 RX IQK ++ //modify RXIQK mode table ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ++ ++ //IQK setting ++ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); ++ ++ //path-A IQK setting ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); ++ ++ //LO calibration setting ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); ++ ++ //One shot, path A LOK & IQK ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ++ ++ // delay x ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); ++ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); ++ ODM_delay_ms(IQK_DELAY_TIME_88E); ++ ++ ++ // Check failed ++ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); ++ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); ++ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); ++ regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); ++ ++ //reload RF 0xdf ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); ++ ++#if 0 ++ if(!(regEAC & BIT28) && ++ (((regE94 & 0x03FF0000)>>16) != 0x142) && ++ (((regE9C & 0x03FF0000)>>16) != 0x42) ) ++ result |= 0x01; ++ else //if Tx not OK, ignore Rx ++ return result; ++#endif ++ ++ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK ++ (((regEA4 & 0x03FF0000)>>16) != 0x132) && ++ (((regEAC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); ++ ++ return result; ++ ++ ++ ++ ++} ++ ++u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++phy_PathB_IQK_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++ ) ++{ ++ u4Byte regEAC, regEB4, regEBC, regEC4, regECC; ++ u1Byte result = 0x00; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); ++ ++ //One shot, path B LOK & IQK ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); ++ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); ++ ++ // delay x ms ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); ++ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); ++ ODM_delay_ms(IQK_DELAY_TIME_88E); ++ ++ // Check failed ++ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); ++ regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); ++ regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); ++ regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); ++ regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); ++ ++ if(!(regEAC & BIT31) && ++ (((regEB4 & 0x03FF0000)>>16) != 0x142) && ++ (((regEBC & 0x03FF0000)>>16) != 0x42)) ++ result |= 0x01; ++ else ++ return result; ++ ++ if(!(regEAC & BIT30) && ++ (((regEC4 & 0x03FF0000)>>16) != 0x132) && ++ (((regECC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); ++ ++ ++ return result; ++ ++} ++ ++VOID ++_PHY_PathAFillIQKMatrix( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN bIQKOK, ++ IN s4Byte result[][8], ++ IN u1Byte final_candidate, ++ IN BOOLEAN bTxOnly ++ ) ++{ ++ u4Byte Oldval_0, X, TX0_A, reg; ++ s4Byte Y, TX0_C; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); ++ ++ if(final_candidate == 0xFF) ++ return; ++ ++ else if(bIQKOK) ++ { ++ Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][0]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX0_A = (X * Oldval_0) >> 8; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); ++ ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); ++ ++ Y = result[final_candidate][1]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ ++ ++ TX0_C = (Y * Oldval_0) >> 8; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); ++ ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); ++ ++ if(bTxOnly) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); ++ return; ++ } ++ ++ reg = result[final_candidate][2]; ++#if (DM_ODM_SUPPORT_TYPE==ODM_AP) ++ if( RTL_ABS(reg ,0x100) >= 16) ++ reg = 0x100; ++#endif ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][3] & 0x3F; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][3] >> 6) & 0xF; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); ++ } ++} ++ ++VOID ++_PHY_PathBFillIQKMatrix( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN bIQKOK, ++ IN s4Byte result[][8], ++ IN u1Byte final_candidate, ++ IN BOOLEAN bTxOnly //do Tx only ++ ) ++{ ++ u4Byte Oldval_1, X, TX1_A, reg; ++ s4Byte Y, TX1_C; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); ++ ++ if(final_candidate == 0xFF) ++ return; ++ ++ else if(bIQKOK) ++ { ++ Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][4]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX1_A = (X * Oldval_1) >> 8; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); ++ ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); ++ ++ Y = result[final_candidate][5]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ ++ TX1_C = (Y * Oldval_1) >> 8; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); ++ ++ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); ++ ++ if(bTxOnly) ++ return; ++ ++ reg = result[final_candidate][6]; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][7] & 0x3F; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][7] >> 6) & 0xF; ++ ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); ++ } ++} ++ ++// ++// 2011/07/26 MH Add an API for testing IQK fail case. ++// ++// MP Already declare in odm.c ++#if !(DM_ODM_SUPPORT_TYPE & ODM_MP) ++BOOLEAN ++ODM_CheckPowerStatus( ++ IN PADAPTER Adapter) ++{ ++/* ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ RT_RF_POWER_STATE rtState; ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ ++ // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. ++ if (pMgntInfo->init_adpt_in_progress == TRUE) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); ++ return TRUE; ++ } ++ ++ // ++ // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. ++ // ++ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); ++ if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) ++ { ++ ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", ++ Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); ++ return FALSE; ++ } ++*/ ++ return TRUE; ++} ++#endif ++ ++VOID ++_PHY_SaveADDARegisters( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte ADDAReg, ++ IN pu4Byte ADDABackup, ++ IN u4Byte RegisterNum ++ ) ++{ ++ u4Byte i; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++ ++ if (ODM_CheckPowerStatus(pAdapter) == FALSE) ++ return; ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); ++ for( i = 0 ; i < RegisterNum ; i++){ ++ ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); ++ } ++} ++ ++ ++VOID ++_PHY_SaveMACRegisters( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte MACReg, ++ IN pu4Byte MACBackup ++ ) ++{ ++ u4Byte i; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); ++ for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); ++ } ++ MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); ++ ++} ++ ++ ++VOID ++_PHY_ReloadADDARegisters( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte ADDAReg, ++ IN pu4Byte ADDABackup, ++ IN u4Byte RegiesterNum ++ ) ++{ ++ u4Byte i; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); ++ for(i = 0 ; i < RegiesterNum; i++) ++ { ++ ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); ++ } ++} ++ ++VOID ++_PHY_ReloadMACRegisters( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte MACReg, ++ IN pu4Byte MACBackup ++ ) ++{ ++ u4Byte i; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); ++ for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); ++ } ++ ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); ++} ++ ++ ++VOID ++_PHY_PathADDAOn( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte ADDAReg, ++ IN BOOLEAN isPathAOn, ++ IN BOOLEAN is2T ++ ) ++{ ++ u4Byte pathOn; ++ u4Byte i; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); ++ ++ pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; ++ if(FALSE == is2T){ ++ pathOn = 0x0bdb25a0; ++ ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); ++ } ++ else{ ++ ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); ++ } ++ ++ for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ ++ ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); ++ } ++ ++} ++ ++VOID ++_PHY_MACSettingCalibration( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte MACReg, ++ IN pu4Byte MACBackup ++ ) ++{ ++ u4Byte i = 0; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); ++ ++ ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); ++ ++ for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); ++ } ++ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); ++ ++} ++ ++VOID ++_PHY_PathAStandBy( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x0); ++ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ++} ++ ++VOID ++_PHY_PIModeSwitch( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN PIMode ++ ) ++{ ++ u4Byte mode; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); ++ ++ mode = PIMode ? 0x01000100 : 0x01000000; ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); ++} ++ ++BOOLEAN ++phy_SimularityCompare_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN s4Byte result[][8], ++ IN u1Byte c1, ++ IN u1Byte c2 ++ ) ++{ ++ u4Byte i, j, diff, SimularityBitMap, bound = 0; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B ++ BOOLEAN bResult = TRUE; ++ BOOLEAN is2T; ++ s4Byte tmp1 = 0,tmp2 = 0; ++ ++ if( (pDM_Odm->RFType ==ODM_2T2R )||(pDM_Odm->RFType ==ODM_2T3R )||(pDM_Odm->RFType ==ODM_2T4R )) ++ is2T = TRUE; ++ else ++ is2T = FALSE; ++ ++ if(is2T) ++ bound = 8; ++ else ++ bound = 4; ++ ++ ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); ++ ++ ++ SimularityBitMap = 0; ++ ++ for( i = 0; i < bound; i++ ) ++ { ++// diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); ++ if((i==1) || (i==3) || (i==5) || (i==7)) ++ { ++ if((result[c1][i]& 0x00000200) != 0) ++ tmp1 = result[c1][i] | 0xFFFFFC00; ++ else ++ tmp1 = result[c1][i]; ++ ++ if((result[c2][i]& 0x00000200) != 0) ++ tmp2 = result[c2][i] | 0xFFFFFC00; ++ else ++ tmp2 = result[c2][i]; ++ } ++ else ++ { ++ tmp1 = result[c1][i]; ++ tmp2 = result[c2][i]; ++ } ++ ++ diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); ++ ++ if (diff > MAX_TOLERANCE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); ++ ++ if((i == 2 || i == 6) && !SimularityBitMap) ++ { ++ if(result[c1][i]+result[c1][i+1] == 0) ++ final_candidate[(i/4)] = c2; ++ else if (result[c2][i]+result[c2][i+1] == 0) ++ final_candidate[(i/4)] = c1; ++ else ++ SimularityBitMap = SimularityBitMap|(1<odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ u4Byte i; ++ u1Byte PathAOK, PathBOK; ++ u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth, ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN }; ++ u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, ++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; ++ ++ //since 92C & 92D have the different define in IQK_BB_REG ++ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { ++ rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, ++ rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, ++ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, ++ rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD ++ }; ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ u4Byte retryCount = 2; ++#else ++#if MP_DRIVER ++ u4Byte retryCount = 9; ++#else ++ u4Byte retryCount = 2; ++#endif ++#endif ++if ( *(pDM_Odm->mp_mode) == 1) ++ retryCount = 9; ++else ++ retryCount = 2; ++ // Note: IQ calibration must be performed after loading ++ // PHY_REG.txt , and radio_a, radio_b.txt ++ ++ //u4Byte bbvalue; ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++#ifdef MP_TEST ++ if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) ++ retryCount = 9; ++#endif ++#endif ++ ++ ++ if(t==0) ++ { ++// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); ++// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); ++ ++ // Save ADDA parameters, turn Path A ADDA on ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); ++ _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); ++#else ++ _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); ++ _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++ _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); ++#endif ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); ++#else ++ _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); ++#endif ++ ++ ++ if(t==0) ++ { ++ pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); ++ } ++ ++ if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ ++ // Switch BB to PI mode to do IQ Calibration. ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_PIModeSwitch(pAdapter, TRUE); ++#else ++ _PHY_PIModeSwitch(pDM_Odm, TRUE); ++#endif ++ } ++ ++ //BB setting ++ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); ++ ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); ++ ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); ++ ++ ++ if(is2T) ++ { ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); ++ } ++ ++ //MAC settings ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++#else ++ _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++#endif ++ ++ ++ //Page B init ++ //AP or IQK ++ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); ++ ++ if(is2T) ++ { ++ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); ++ } ++ ++ // IQ calibration setting ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ++ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); ++ ++ for(i = 0 ; i < retryCount ; i++){ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); ++#else ++ PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); ++#endif ++// if(PathAOK == 0x03){ ++ if(PathAOK == 0x01){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); ++ result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++#if 0 ++ else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK ++ { ++ RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); ++ ++ result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ } ++#endif ++ } ++ ++ for(i = 0 ; i < retryCount ; i++){ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PathAOK = phy_PathA_RxIQK(pAdapter, is2T); ++#else ++ PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); ++#endif ++ if(PathAOK == 0x03){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); ++// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; ++ result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; ++ result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); ++ } ++ } ++ ++ if(0x00 == PathAOK){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); ++ } ++ ++ if(is2T){ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_PathAStandBy(pAdapter); ++ ++ // Turn Path B ADDA on ++ _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); ++#else ++ _PHY_PathAStandBy(pDM_Odm); ++ ++ // Turn Path B ADDA on ++ _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); ++#endif ++ ++ for(i = 0 ; i < retryCount ; i++){ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PathBOK = phy_PathB_IQK_8188E(pAdapter); ++#else ++ PathBOK = phy_PathB_IQK_8188E(pDM_Odm); ++#endif ++ if(PathBOK == 0x03){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); ++ result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; ++ result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); ++ result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; ++ } ++ } ++ ++ if(0x00 == PathBOK){ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); ++ } ++ } ++ ++ //Back to BB mode, load original value ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); ++ ++ if(t!=0) ++ { ++ if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ ++ // Switch back BB to SI mode after finish IQ Calibration. ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_PIModeSwitch(pAdapter, FALSE); ++#else ++ _PHY_PIModeSwitch(pDM_Odm, FALSE); ++#endif ++ } ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ // Reload ADDA power saving parameters ++ _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); ++ ++ // Reload MAC parameters ++ _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++ ++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); ++#else ++ // Reload ADDA power saving parameters ++ _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); ++ ++ // Reload MAC parameters ++ _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); ++ ++ _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); ++#endif ++ ++ ++ // Restore RX initial gain ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); ++ if(is2T){ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); ++ } ++ ++ //load 0xe30 IQC default value ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ ++ ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); ++ ++} ++ ++ ++VOID ++phy_LCCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN is2T ++ ) ++{ ++ u1Byte tmpReg; ++ u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ //Check continuous TX and Packet TX ++ tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); ++ ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX ++ else // Deal with Packet TX case ++ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues ++ ++ if((tmpReg&0x70) != 0) ++ { ++ //1. Read original RF mode ++ //Path-A ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); ++ ++ //Path-B ++ if(is2T) ++ RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); ++#else ++ RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits); ++ ++ //Path-B ++ if(is2T) ++ RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); ++#endif ++ ++ //2. Set RF mode = standby mode ++ //Path-A ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); ++ ++ //Path-B ++ if(is2T) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); ++ } ++ ++ //3. Read RF reg18 ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); ++#else ++ LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits); ++#endif ++ ++ //4. Set LC calibration begin bit15 ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); ++ ++ ODM_sleep_ms(100); ++ ++ ++ //Restore original situation ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ { ++ //Path-A ++ ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); ++ ++ //Path-B ++ if(is2T) ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); ++ } ++ else // Deal with Packet TX case ++ { ++ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); ++ } ++} ++ ++//Analog Pre-distortion calibration ++#define APK_BB_REG_NUM 8 ++#define APK_CURVE_REG_NUM 4 ++#define PATH_NUM 2 ++ ++VOID ++phy_APCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN s1Byte delta, ++ IN BOOLEAN is2T ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ u4Byte regD[PATH_NUM]; ++ u4Byte tmpReg, index, offset, apkbound; ++ u1Byte path, i, pathbound = PATH_NUM; ++ u4Byte BB_backup[APK_BB_REG_NUM]; ++ u4Byte BB_REG[APK_BB_REG_NUM] = { ++ rFPGA1_TxBlock, rOFDM0_TRxPathEnable, ++ rFPGA0_RFMOD, rOFDM0_TRMuxPar, ++ rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, ++ rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; ++ u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x00204000 }; ++ u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x22204000 }; ++ ++ u4Byte AFE_backup[IQK_ADDA_REG_NUM]; ++ u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth, ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN }; ++ ++ u4Byte MAC_backup[IQK_MAC_REG_NUM]; ++ u4Byte MAC_REG[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, ++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; ++ ++ u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, ++ {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} ++ }; ++ ++ u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings ++ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} ++ }; ++ ++ u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, ++ {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} ++ }; ++ ++ u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} ++ }; ++ ++ u4Byte AFE_on_off[PATH_NUM] = { ++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on ++ ++ u4Byte APK_offset[PATH_NUM] = { ++ rConfig_AntA, rConfig_AntB}; ++ ++ u4Byte APK_normal_offset[PATH_NUM] = { ++ rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; ++ ++ u4Byte APK_value[PATH_NUM] = { ++ 0x92fc0000, 0x12fc0000}; ++ ++ u4Byte APK_normal_value[PATH_NUM] = { ++ 0x92680000, 0x12680000}; ++ ++ s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} ++ }; ++ ++ u4Byte APK_normal_setting_value_1[13] = { ++ 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, ++ 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, ++ 0x12680000, 0x00880000, 0x00880000 ++ }; ++ ++ u4Byte APK_normal_setting_value_2[16] = { ++ 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, ++ 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, ++ 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, ++ 0x00050006 ++ }; ++ ++ u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a ++// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; ++ ++ s4Byte BB_offset, delta_V, delta_offset; ++ ++#if MP_DRIVER == 1 ++if ( *(pDM_Odm->mp_mode) == 1) ++{ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); ++#else ++ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); ++#endif ++ pMptCtx->APK_bound[0] = 45; ++ pMptCtx->APK_bound[1] = 52; ++} ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); ++ if(!is2T) ++ pathbound = 1; ++ ++ //2 FOR NORMAL CHIP SETTINGS ++ ++// Temporarily do not allow normal driver to do the following settings because these offset ++// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal ++// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the ++// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. ++//#if MP_DRIVER != 1 ++if (*(pDM_Odm->mp_mode) != 1) ++ return; ++//#endif ++ //settings adjust for normal chip ++ for(index = 0; index < PATH_NUM; index ++) ++ { ++ APK_offset[index] = APK_normal_offset[index]; ++ APK_value[index] = APK_normal_value[index]; ++ AFE_on_off[index] = 0x6fdb25a4; ++ } ++ ++ for(index = 0; index < APK_BB_REG_NUM; index ++) ++ { ++ for(path = 0; path < pathbound; path++) ++ { ++ APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; ++ APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; ++ } ++ BB_AP_MODE[index] = BB_normal_AP_MODE[index]; ++ } ++ ++ apkbound = 6; ++ ++ //save BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(index == 0) //skip ++ continue; ++ BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); ++ } ++ ++ //save MAC default value ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); ++ ++ //save AFE default value ++ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++#else ++ _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); ++ ++ //save AFE default value ++ _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++#endif ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ ++ ++ if(path == RF_PATH_A) ++ { ++ //path A APK ++ //load APK setting ++ //path-A ++ offset = rPdp_AntA; ++ for(index = 0; index < 11; index ++) ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); ++ ++ offset = rConfig_AntA; ++ for(; index < 13; index ++) ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ++ //path A ++ offset = rPdp_AntA; ++ for(index = 0; index < 16; index++) ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ } ++ else if(path == RF_PATH_B) ++ { ++ //path B APK ++ //load APK setting ++ //path-B ++ offset = rPdp_AntB; ++ for(index = 0; index < 10; index ++) ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); ++#else ++ PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); ++#endif ++ ++ offset = rConfig_AntA; ++ index = 11; ++ for(; index < 13; index ++) //offset 0xb68, 0xb6c ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ++ //path B ++ offset = 0xb60; ++ for(index = 0; index < 16; index++) ++ { ++ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); ++ } ++ ++ //save RF default value ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); ++#else ++ regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); ++#endif ++ ++ //Path A AFE all on, path B AFE All off or vise versa ++ for(index = 0; index < IQK_ADDA_REG_NUM ; index++) ++ ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); ++ ++ //BB to AP mode ++ if(path == 0) ++ { ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ ++ if(index == 0) //skip ++ continue; ++ else if (index < 5) ++ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); ++ else if (BB_REG[index] == 0x870) ++ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); ++ else ++ ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); ++ } ++ ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); ++ } ++ else //path B ++ { ++ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); ++ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); ++ ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); ++ ++ //MAC settings ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); ++#else ++ _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); ++#endif ++ ++ if(path == RF_PATH_A) //Path B to standby mode ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); ++ } ++ else //Path A to standby mode ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); ++ } ++ ++ delta_offset = ((delta+14)/2); ++ if(delta_offset < 0) ++ delta_offset = 0; ++ else if (delta_offset > 12) ++ delta_offset = 12; ++ ++ //AP calibration ++ for(index = 0; index < APK_BB_REG_NUM; index++) ++ { ++ if(index != 1) //only DO PA11+PAD01001, AP RF setting ++ continue; ++ ++ tmpReg = APK_RF_init_value[path][index]; ++#if 1 ++ if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) ++ { ++ BB_offset = (tmpReg & 0xF0000) >> 16; ++ ++ if(!(tmpReg & BIT15)) //sign bit 0 ++ { ++ BB_offset = -BB_offset; ++ } ++ ++ delta_V = APK_delta_mapping[index][delta_offset]; ++ ++ BB_offset += delta_V; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); ++ ++ if(BB_offset < 0) ++ { ++ tmpReg = tmpReg & (~BIT15); ++ BB_offset = -BB_offset; ++ } ++ else ++ { ++ tmpReg = tmpReg | BIT15; ++ } ++ tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); ++ } ++#endif ++ ++ ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); ++ ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); ++ ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); ++#else ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); ++ ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); ++ ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); ++#endif ++ ++ // PA11+PAD01111, one shot ++ i = 0; ++ do ++ { ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); ++ { ++ ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); ++ ODM_delay_ms(3); ++ ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); ++ ++ ODM_delay_ms(20); ++ } ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ++ if(path == RF_PATH_A) ++ tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); ++ else ++ tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); ++ ++ ++ i++; ++ } ++ while(tmpReg > apkbound && i < 4); ++ ++ APK_result[path][index] = tmpReg; ++ } ++ } ++ ++ //reload MAC default value ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); ++#else ++ _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); ++#endif ++ ++ //reload BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ ++ if(index == 0) //skip ++ continue; ++ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); ++ } ++ ++ //reload AFE default value ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++#else ++ _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++#endif ++ ++ //reload RF path default value ++ for(path = 0; path < pathbound; path++) ++ { ++ ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); ++ if(path == RF_PATH_B) ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); ++ } ++ ++ //note no index == 0 ++ if (APK_result[path][1] > 6) ++ APK_result[path][1] = 6; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); ++ ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); ++ if(path == RF_PATH_A) ++ ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); ++ else ++ ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ if(!IS_HARDWARE_TYPE_8723A(pAdapter)) ++ ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, ++ ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); ++#endif ++ } ++ ++ pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); ++} ++ ++ ++ ++#define DP_BB_REG_NUM 7 ++#define DP_RF_REG_NUM 1 ++#define DP_RETRY_LIMIT 10 ++#define DP_PATH_NUM 2 ++#define DP_DPK_NUM 3 ++#define DP_DPK_VALUE_NUM 2 ++ ++ ++ ++ ++ ++VOID ++PHY_IQCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN bReCovery ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ ++ #if (MP_DRIVER == 1) ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); ++ #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); ++ #endif ++ #endif//(MP_DRIVER == 1) ++#endif ++ ++ s4Byte result[4][8]; //last is final result ++ u1Byte i, final_candidate, Indexforchannel; ++ u1Byte channelToIQK = 7; ++ BOOLEAN bPathAOK, bPathBOK; ++ s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; ++ BOOLEAN is12simular, is13simular, is23simular; ++ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; ++ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { ++ rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, ++ rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, ++ rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, ++ rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, ++ rOFDM0_RxIQExtAnta}; ++ BOOLEAN is2T; ++ ++ is2T = (pDM_Odm->RFType == ODM_2T2R)?TRUE:FALSE; ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE) ) ++ if (ODM_CheckPowerStatus(pAdapter) == FALSE) ++ return; ++#else ++ prtl8192cd_priv priv = pDM_Odm->priv; ++ ++#ifdef MP_TEST ++ if(priv->pshare->rf_ft_var.mp_specific) ++ { ++ if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) ++ return; ++ } ++#endif ++ ++ if(priv->pshare->IQK_88E_done) ++ bReCovery= 1; ++ priv->pshare->IQK_88E_done = 1; ++ ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) ++ { ++ return; ++ } ++#endif ++ ++#if MP_DRIVER == 1 ++if (*(pDM_Odm->mp_mode) == 1) ++{ ++ bStartContTx = pMptCtx->bStartContTx; ++ bSingleTone = pMptCtx->bSingleTone; ++ bCarrierSuppression = pMptCtx->bCarrierSuppression; ++} ++#endif ++ ++ // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) ++ if(bSingleTone || bCarrierSuppression) ++ return; ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) ++ if(bReCovery) ++#else//for ODM_MP ++ if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 ++#endif ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); ++#else ++ _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); ++#endif ++ return; ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); ++ ++#if 0//Suggested by Edlu,120413 ++ ++ // IQK on channel 7, should switch back when completed. ++ //originChannel = pHalData->CurrentChannel; ++ originChannel = *(pDM_Odm->pChannel); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK); ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK); ++#endif ++ ++#endif ++ ++ for(i = 0; i < 8; i++) ++ { ++ result[0][i] = 0; ++ result[1][i] = 0; ++ result[2][i] = 0; ++ if((i==0) ||(i==2) || (i==4) || (i==6)) ++ result[3][i] = 0x100; ++ else ++ result[3][i] = 0; ++ } ++ final_candidate = 0xff; ++ bPathAOK = FALSE; ++ bPathBOK = FALSE; ++ is12simular = FALSE; ++ is23simular = FALSE; ++ is13simular = FALSE; ++ ++ ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); ++// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); ++ for (i=0; i<3; i++) ++ { ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ phy_IQCalibrate_8188E(pAdapter, result, i, is2T); ++#else ++ phy_IQCalibrate_8188E(pDM_Odm, result, i, is2T); ++#endif ++ ++ ++ if(i == 1) ++ { ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); ++#else ++ is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); ++#endif ++ if(is12simular) ++ { ++ final_candidate = 0; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); ++ break; ++ } ++ } ++ ++ if(i == 2) ++ { ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); ++#else ++ is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); ++#endif ++ if(is13simular) ++ { ++ final_candidate = 0; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); ++ ++ break; ++ } ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); ++#else ++ is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); ++#endif ++ if(is23simular) ++ { ++ final_candidate = 1; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); ++ } ++ else ++ { ++ /* ++ for(i = 0; i < 8; i++) ++ RegTmp += result[3][i]; ++ ++ if(RegTmp != 0) ++ final_candidate = 3; ++ else ++ final_candidate = 0xFF; ++ */ ++ final_candidate = 3; ++ } ++ } ++ } ++// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); ++ ++ for (i=0; i<4; i++) ++ { ++ RegE94 = result[i][0]; ++ RegE9C = result[i][1]; ++ RegEA4 = result[i][2]; ++ RegEAC = result[i][3]; ++ RegEB4 = result[i][4]; ++ RegEBC = result[i][5]; ++ RegEC4 = result[i][6]; ++ RegECC = result[i][7]; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); ++ } ++ ++ if(final_candidate != 0xff) ++ { ++ pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; ++ pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; ++ RegEA4 = result[final_candidate][2]; ++ RegEAC = result[final_candidate][3]; ++ pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; ++ pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; ++ RegEC4 = result[final_candidate][6]; ++ RegECC = result[final_candidate][7]; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); ++ bPathAOK = bPathBOK = TRUE; ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); ++ ++ pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value ++ pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value ++ } ++ ++ if((RegE94 != 0)/*&&(RegEA4 != 0)*/) ++ { ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); ++#else ++ _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); ++#endif ++ } ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ if (is2T) ++ { ++ if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) ++ { ++ _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); ++ } ++ } ++#endif ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); ++#else ++ Indexforchannel = 0; ++#endif ++ ++//To Fix BSOD when final_candidate is 0xff ++//by sherry 20120321 ++ if(final_candidate < 4) ++ { ++ for(i = 0; i < IQK_Matrix_REG_NUM; i++) ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; ++ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; ++ } ++ //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); ++#else ++ _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); ++#endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); ++#if 0 //Suggested by Edlu,120413 ++ ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel); ++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel); ++ #endif ++ ++#endif ++ ++} ++ ++ ++VOID ++PHY_LCCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++ ) ++{ ++ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; ++ u4Byte timeout = 2000, timecount = 0; ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ ++ #if (MP_DRIVER == 1) ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); ++ #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); ++ #endif ++ #endif//(MP_DRIVER == 1) ++#endif ++ ++ ++ ++ ++#if MP_DRIVER == 1 ++if (*(pDM_Odm->mp_mode) == 1) ++{ ++ bStartContTx = pMptCtx->bStartContTx; ++ bSingleTone = pMptCtx->bSingleTone; ++ bCarrierSuppression = pMptCtx->bCarrierSuppression; ++} ++#endif ++ ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) ++ { ++ return; ++ } ++#endif ++ // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) ++ if(bSingleTone || bCarrierSuppression) ++ return; ++ ++ while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) ++ { ++ ODM_delay_ms(50); ++ timecount += 50; ++ } ++ ++ pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; ++ ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ if(pDM_Odm->RFType == ODM_2T2R) ++ { ++ phy_LCCalibrate_8188E(pAdapter, TRUE); ++ } ++ else ++#endif ++ { ++ // For 88C 1T1R ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ phy_LCCalibrate_8188E(pAdapter, FALSE); ++#else ++ phy_LCCalibrate_8188E(pDM_Odm, FALSE); ++#endif ++ } ++ ++ pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); ++ ++} ++ ++VOID ++PHY_APCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN s1Byte delta ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ return; ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) ++ { ++ return; ++ } ++#endif ++ ++#if FOR_BRAZIL_PRETEST != 1 ++ if(pDM_Odm->RFCalibrateInfo.bAPKdone) ++#endif ++ return; ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ if(pDM_Odm->RFType == ODM_2T2R){ ++ phy_APCalibrate_8188E(pAdapter, delta, TRUE); ++ } ++ else ++#endif ++ { ++ // For 88C 1T1R ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ phy_APCalibrate_8188E(pAdapter, delta, FALSE); ++#else ++ phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); ++#endif ++ } ++} ++VOID phy_SetRFPathSwitch_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN bMain, ++ IN BOOLEAN is2T ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #elif (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++ ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ if(!pAdapter->bHWInitReady) ++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ if(pAdapter->hw_init_completed == _FALSE) ++ #endif ++ { ++ u1Byte u1bTmp; ++ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; ++ ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); ++ //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++#endif ++ ++ if(is2T) //92C ++ { ++ if(bMain) ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A ++ else ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT ++ } ++ else //88C ++ { ++ ++ if(bMain) ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main ++ else ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux ++ } ++} ++VOID PHY_SetRFPathSwitch_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN bMain ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ if(pDM_Odm->RFType == ODM_2T2R) ++ { ++ phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); ++ } ++ else ++#endif ++ { ++ // For 88C 1T1R ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); ++#else ++ phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); ++#endif ++ } ++} ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++//digital predistortion ++VOID ++phy_DigitalPredistortion( ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PADAPTER pAdapter, ++#else ++ IN PDM_ODM_T pDM_Odm, ++#endif ++ IN BOOLEAN is2T ++ ) ++{ ++#if ( RT_PLATFORM == PLATFORM_WINDOWS) ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ++ u4Byte tmpReg, tmpReg2, index, i; ++ u1Byte path, pathbound = PATH_NUM; ++ u4Byte AFE_backup[IQK_ADDA_REG_NUM]; ++ u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { ++ rFPGA0_XCD_SwitchControl, rBlue_Tooth, ++ rRx_Wait_CCA, rTx_CCK_RFON, ++ rTx_CCK_BBON, rTx_OFDM_RFON, ++ rTx_OFDM_BBON, rTx_To_Rx, ++ rTx_To_Tx, rRx_CCK, ++ rRx_OFDM, rRx_Wait_RIFS, ++ rRx_TO_Rx, rStandby, ++ rSleep, rPMPD_ANAEN }; ++ ++ u4Byte BB_backup[DP_BB_REG_NUM]; ++ u4Byte BB_REG[DP_BB_REG_NUM] = { ++ rOFDM0_TRxPathEnable, rFPGA0_RFMOD, ++ rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, ++ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, ++ rFPGA0_XB_RFInterfaceOE}; ++ u4Byte BB_settings[DP_BB_REG_NUM] = { ++ 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, ++ 0x0, 0x0, 0x0}; ++ ++ u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; ++ u4Byte RF_REG[DP_RF_REG_NUM] = { ++ RF_TXBIAS_A}; ++ ++ u4Byte MAC_backup[IQK_MAC_REG_NUM]; ++ u4Byte MAC_REG[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, ++ REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; ++ ++ u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { ++ {0x1e1e1e1e, 0x03901e1e}, ++ {0x18181818, 0x03901818}, ++ {0x0e0e0e0e, 0x03900e0e} ++ }; ++ ++ u4Byte AFE_on_off[PATH_NUM] = { ++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on ++ ++ u1Byte RetryCount = 0; ++ ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R"))); ++ ++ //save BB default value ++ for(index=0; index tx_agc 1f ~11 ++ // PA gain = 11 & PAD2 => tx_agc 10~0e ++ // PA gain = 01 => tx_agc 0b~0d ++ // PA gain = 00 => tx_agc 0a~00 ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ++ //do inner loopback DPK 3 times ++ for(i = 0; i < 3; i++) ++ { ++ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 ++ for(index = 0; index < 3; index++) ++ ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); ++ ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); ++ for(index = 0; index < 4; index++) ++ ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); ++ ++ // PAGE_B for Path-A inner loopback DPK setting ++ ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); ++ ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); ++ ++ //----send one shot signal----// ++ // Path A ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); ++ ODM_delay_ms(50); ++ } ++ ++ //PA gain = 11 => tx_agc = 1a ++ for(index = 0; index < 3; index++) ++ ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); ++ ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); ++ for(index = 0; index < 4; index++) ++ ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); ++ ++ //==================================== ++ // PAGE_B for Path-A DPK setting ++ //==================================== ++ // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 ++ ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); ++ ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); ++ ++ //rf_lpbk_setup ++ //1.rf 00:5205a, rf 0d:0e52c ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); ++ ++ //----send one shot signal----// ++ // Path A ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); ++ ODM_delay_ms(50); ++ ++ while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) ++ { ++ //----read back measurement results----// ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); ++ tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); ++ ODM_delay_ms(10); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); ++ tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); ++ ODM_delay_ms(10); ++ ++ tmpReg = (tmpReg & bMaskHWord) >> 16; ++ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; ++ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) ++ { ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); ++ ODM_delay_ms(50); ++ RetryCount++; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); ++ pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; ++ break; ++ } ++ } ++ RetryCount = 0; ++ ++ //DPP path A ++ if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) ++ { ++ // DP settings ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ++ for(i=rPdp_AntA; i<=0xb3c; i+=4) ++ { ++ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); ++ } ++ ++ //pwsf ++ ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); ++ ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); ++ ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); ++ ++ for(i=0xb4c; i<=0xb5c; i+=4) ++ { ++ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); ++ } ++ ++ //TX_AGC boundary ++ ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); ++ } ++ ++ //DPK path B ++ if(is2T) ++ { ++ //Path A to standby mode ++ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); ++ ++ // LUTs => tx_agc ++ // PA gain = 11 & PAD1, => tx_agc 1f ~11 ++ // PA gain = 11 & PAD2, => tx_agc 10 ~0e ++ // PA gain = 01 => tx_agc 0b ~0d ++ // PA gain = 00 => tx_agc 0a ~00 ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ++ //do inner loopback DPK 3 times ++ for(i = 0; i < 3; i++) ++ { ++ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 ++ for(index = 0; index < 4; index++) ++ ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); ++ for(index = 0; index < 2; index++) ++ ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); ++ for(index = 0; index < 2; index++) ++ ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); ++ ++ // PAGE_B for Path-A inner loopback DPK setting ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); ++ ++ //----send one shot signal----// ++ // Path B ++ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); ++ ODM_delay_ms(50); ++ } ++ ++ // PA gain = 11 => tx_agc = 1a ++ for(index = 0; index < 4; index++) ++ ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); ++ for(index = 0; index < 2; index++) ++ ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); ++ for(index = 0; index < 2; index++) ++ ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); ++ ++ // PAGE_B for Path-B DPK setting ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); ++ ++ // RF lpbk switches on ++ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); ++ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); ++ ++ //Path-B RF lpbk ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); ++ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); ++ ++ //----send one shot signal----// ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); ++ ODM_delay_ms(50); ++ ++ while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) ++ { ++ //----read back measurement results----// ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); ++ tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); ++ tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); ++ ++ tmpReg = (tmpReg & bMaskHWord) >> 16; ++ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; ++ ++ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) ++ { ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); ++ ODM_delay_ms(1); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); ++ ODM_delay_ms(50); ++ RetryCount++; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); ++ pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; ++ break; ++ } ++ } ++ ++ //DPP path B ++ if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) ++ { ++ // DP setting ++ // LUT by SRAM ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); ++ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); ++ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); ++ ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); ++ for(i=0xb60; i<=0xb9c; i+=4) ++ { ++ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); ++ } ++ ++ // PWSF ++ ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); ++ ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); ++ ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); ++ ++ for(i=0xbac; i<=0xbbc; i+=4) ++ { ++ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); ++ } ++ ++ // tx_agc boundary ++ ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ++ ++ } ++ else ++ { ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); ++ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); ++ } ++ } ++ ++ //reload BB default value ++ for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); ++#endif ++} ++ ++VOID ++PHY_DigitalPredistortion_8188E( ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PADAPTER pAdapter ++#else ++ IN PDM_ODM_T pDM_Odm ++#endif ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ return; ++ ++ if(pDM_Odm->RFCalibrateInfo.bDPdone) ++ return; ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ if(pDM_Odm->RFType == ODM_2T2R){ ++ phy_DigitalPredistortion(pAdapter, TRUE); ++ } ++ else ++#endif ++ { ++ // For 88C 1T1R ++ phy_DigitalPredistortion(pAdapter, FALSE); ++ } ++} ++ ++ ++ ++//return value TRUE => Main; FALSE => Aux ++ ++BOOLEAN phy_QueryRFPathSwitch_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN BOOLEAN is2T ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ if(!pAdapter->bHWInitReady) ++ { ++ u1Byte u1bTmp; ++ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; ++ ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); ++ //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); ++ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++ if(is2T) // ++ { ++ if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) ++ return TRUE; ++ else ++ return FALSE; ++ } ++ else ++ { ++ if(ODM_GetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9) == 0x02) ++ return TRUE; ++ else ++ return FALSE; ++ } ++} ++ ++ ++ ++//return value TRUE => Main; FALSE => Aux ++BOOLEAN PHY_QueryRFPathSwitch_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++ ) ++{ ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ++ #endif ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; ++ #endif ++#endif ++ ++ ++#if DISABLE_BB_RF ++ return TRUE; ++#endif ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ ++ //if(IS_92C_SERIAL( pHalData->VersionID)){ ++ if(pDM_Odm->RFType == ODM_2T2R){ ++ return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); ++ } ++ else ++#endif ++ { ++ // For 88C 1T1R ++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) ++ return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); ++#else ++ return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); ++#endif ++ } ++} ++#endif +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h +new file mode 100644 +index 00000000..a8f4620b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h +@@ -0,0 +1,141 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __HAL_PHY_RF_8188E_H__ ++#define __HAL_PHY_RF_8188E_H__ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define IQK_DELAY_TIME_88E 10 //ms ++#define index_mapping_NUM_88E 15 ++#define AVG_THERMAL_NUM_88E 4 ++ ++typedef enum _PWRTRACK_CONTROL_METHOD { ++ BBSWING, ++ TXAGC ++} PWRTRACK_METHOD; ++ ++ ++VOID ++ODM_TxPwrTrackAdjust88E( ++ PDM_ODM_T pDM_Odm, ++ u1Byte Type, // 0 = OFDM, 1 = CCK ++ pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease) ++ pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust ++ ); ++ ++ ++VOID ++odm_TXPowerTrackingCallback_ThermalMeter_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER Adapter ++#endif ++ ); ++ ++ ++//1 7. IQK ++ ++void ++PHY_IQCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER Adapter, ++#endif ++ IN BOOLEAN bReCovery); ++ ++ ++// ++// LC calibrate ++// ++void ++PHY_LCCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++); ++ ++// ++// AP calibrate ++// ++void ++PHY_APCalibrate_8188E( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN s1Byte delta); ++void ++PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); ++ ++ ++VOID ++_PHY_SaveADDARegisters( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte ADDAReg, ++ IN pu4Byte ADDABackup, ++ IN u4Byte RegisterNum ++ ); ++ ++VOID ++_PHY_PathADDAOn( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte ADDAReg, ++ IN BOOLEAN isPathAOn, ++ IN BOOLEAN is2T ++ ); ++ ++VOID ++_PHY_MACSettingCalibration( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm, ++#else ++ IN PADAPTER pAdapter, ++#endif ++ IN pu4Byte MACReg, ++ IN pu4Byte MACBackup ++ ); ++ ++ ++VOID ++_PHY_PathAStandBy( ++#if (DM_ODM_SUPPORT_TYPE & ODM_AP) ++ IN PDM_ODM_T pDM_Odm ++#else ++ IN PADAPTER pAdapter ++#endif ++ ); ++ ++ ++#endif // #ifndef __HAL_PHY_RF_8188E_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.c +new file mode 100644 +index 00000000..fb99d0ee +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.c +@@ -0,0 +1,1290 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++//============================================================ ++// include files ++//============================================================ ++ ++#include "../odm_precomp.h" ++ ++#if (RTL8188E_SUPPORT == 1) ++ ++VOID ++ODM_DIG_LowerBound_88E( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ { ++ pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); ++ } ++ //If only one Entry connected ++ ++ ++ ++} ++ ++#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++VOID ++odm_RX_HWAntDivInit( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u4Byte value32; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ #if (MP_DRIVER == 1) ++ if (*(pDM_Odm->mp_mode) == 1) ++ { ++ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ++ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv ++ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS ++ return; ++ } ++ #endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n")); ++ ++ //MAC Setting ++ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); ++ ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output ++ //Pin Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW ++ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch ++ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only ++ //OFDM Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); ++ //CCK Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table ++ ++ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv ++ //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv ++} ++ ++VOID ++odm_TRX_HWAntDivInit( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u4Byte value32; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ++ #if (MP_DRIVER == 1) ++ if (*(pDM_Odm->mp_mode) == 1) ++ { ++ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; ++ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) ++ return; ++ } ++ ++ #endif ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n")); ++ ++ //MAC Setting ++ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); ++ ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output ++ //Pin Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW ++ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch ++ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only ++ //OFDM Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); ++ //CCK Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples ++ //Tx Settings ++ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ++ ++ //antenna mapping table ++ if(!pDM_Odm->bIsMPChip) //testchip ++ { ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 ++ } ++ else //MPchip ++ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001 ++ ++ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv ++ //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv ++} ++ ++VOID ++odm_FastAntTrainingInit( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u4Byte value32, i; ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ u4Byte AntCombination = 2; ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n")); ++ ++#if (MP_DRIVER == 1) ++ if (*(pDM_Odm->mp_mode) == 1) ++ { ++ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); ++ return; ++ } ++#endif ++ ++ for(i=0; i<6; i++) ++ { ++ pDM_FatTable->Bssid[i] = 0; ++ pDM_FatTable->antSumRSSI[i] = 0; ++ pDM_FatTable->antRSSIcnt[i] = 0; ++ pDM_FatTable->antAveRSSI[i] = 0; ++ } ++ pDM_FatTable->TrainIdx = 0; ++ pDM_FatTable->FAT_State = FAT_NORMAL_STATE; ++ ++ //MAC Setting ++ value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); ++ ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output ++ value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); ++ ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match ++ //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); ++ //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet ++ ++ //Match MAC ADDR ++ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); ++ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); ++ ++ ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW ++ ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW ++ ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch ++ ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only ++ ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); ++ ++ //antenna mapping table ++ if(AntCombination == 2) ++ { ++ if(!pDM_Odm->bIsMPChip) //testchip ++ { ++ ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 ++ ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 ++ } ++ else //MPchip ++ { ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); ++ } ++ } ++ else if(AntCombination == 7) ++ { ++ if(!pDM_Odm->bIsMPChip) //testchip ++ { ++ ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 ++ ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); ++ ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 ++ ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 ++ } ++ else //MPchip ++ { ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2); ++ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3); ++ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4); ++ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); ++ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); ++ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7); ++ } ++ } ++ ++ //Default Ant Setting when no fast training ++ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info ++ ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX ++ ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX ++ //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX ++ ++ //Enter Traing state ++ ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 ++ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv ++ //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training ++ //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training ++ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv ++ ++ ++ //SW Control ++ //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); ++ //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); ++ //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); ++ //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); ++ //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); ++ //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); ++} ++ ++VOID ++ODM_AntennaDiversityInit_88E( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++/* ++ //2012.03.27 LukeLee: For temp use, should be removed later ++ //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; ++ //{ ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); ++ //pHalData->AntDivCfg = 1; ++ //} ++*/ ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ return; ++ ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", ++ // pDM_Odm->AntDivType, pHalData->AntDivCfg)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE"))); ++ ++ if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ++ odm_RX_HWAntDivInit(pDM_Odm); ++ else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ odm_TRX_HWAntDivInit(pDM_Odm); ++ else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) ++ odm_FastAntTrainingInit(pDM_Odm); ++} ++ ++ ++VOID ++ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ u4Byte DefaultAnt, OptionalAnt; ++ ++ if(pDM_FatTable->RxIdleAnt != Ant) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); ++ if(Ant == MAIN_ANT) ++ { ++ DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; ++ OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; ++ } ++ else ++ { ++ DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; ++ OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; ++ } ++ ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ { ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX ++ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX ++ ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx ++ ++ } ++ else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ++ { ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX ++ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX ++ } ++ } ++ pDM_FatTable->RxIdleAnt = Ant; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); ++ printk("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); ++} ++ ++ ++VOID ++odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ u1Byte TargetAnt; ++ ++ if(Ant == MAIN_ANT) ++ TargetAnt = MAIN_ANT_CG_TRX; ++ else ++ TargetAnt = AUX_ANT_CG_TRX; ++ ++ pDM_FatTable->antsel_a[MacId] = TargetAnt&BIT0; ++ pDM_FatTable->antsel_b[MacId] = (TargetAnt&BIT1)>>1; ++ pDM_FatTable->antsel_c[MacId] = (TargetAnt&BIT2)>>2; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetAnt=%s\n", ++ (Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", ++ pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); ++} ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++ ) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ ++ if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) ++ { ++ SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); ++ SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); ++ SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", ++ // macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); ++ } ++} ++#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++} ++#endif ++ ++VOID ++ODM_AntselStatistics_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte antsel_tr_mux, ++ IN u4Byte MacId, ++ IN u1Byte RxPWDBAll ++) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ { ++ if(antsel_tr_mux == MAIN_ANT_CG_TRX) ++ { ++ ++ pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; ++ pDM_FatTable->MainAnt_Cnt[MacId]++; ++ } ++ else ++ { ++ pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; ++ pDM_FatTable->AuxAnt_Cnt[MacId]++; ++ ++ } ++ } ++ else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ++ { ++ if(antsel_tr_mux == MAIN_ANT_CGCS_RX) ++ { ++ ++ pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; ++ pDM_FatTable->MainAnt_Cnt[MacId]++; ++ } ++ else ++ { ++ pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; ++ pDM_FatTable->AuxAnt_Cnt[MacId]++; ++ ++ } ++ } ++} ++ ++#define TX_BY_REG 0 ++VOID ++odm_HWAntDiv( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI; ++ u4Byte Main_RSSI, Aux_RSSI; ++ u1Byte RxIdleAnt=0, TargetAnt=7; ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; ++ BOOLEAN bMatchBSSID; ++ BOOLEAN bPktFilterMacth = FALSE; ++ PSTA_INFO_T pEntry; ++ ++ for (i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pEntry)) ++ { ++ //2 Caculate RSSI per Antenna ++ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; ++ Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; ++ TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i])); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i])); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); ++ ++ //2 Select MaxRSSI for DIG ++ LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; ++ if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) ++ AntDivMaxRSSI = LocalMaxRSSI; ++ if(LocalMaxRSSI > MaxRSSI) ++ MaxRSSI = LocalMaxRSSI; ++ ++ //2 Select RX Idle Antenna ++ if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) ++ Main_RSSI = Aux_RSSI; ++ else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) ++ Aux_RSSI = Main_RSSI; ++ ++ LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI; ++ if(LocalMinRSSI < MinRSSI) ++ { ++ MinRSSI = LocalMinRSSI; ++ RxIdleAnt = TargetAnt; ++ } ++#if TX_BY_REG ++ ++#else ++ //2 Select TRX Antenna ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i); ++#endif ++ } ++ pDM_FatTable->MainAnt_Sum[i] = 0; ++ pDM_FatTable->AuxAnt_Sum[i] = 0; ++ pDM_FatTable->MainAnt_Cnt[i] = 0; ++ pDM_FatTable->AuxAnt_Cnt[i] = 0; ++ } ++ ++ //2 Set RX Idle Antenna ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt); ++ ++ pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; ++ pDM_DigTable->RSSI_max = MaxRSSI; ++} ++ ++ ++#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++VOID ++odm_SetNextMACAddrTarget( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ PSTA_INFO_T pEntry; ++ //u1Byte Bssid[6]; ++ u4Byte value32, i; ++ ++ // ++ //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn ++ // ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); ++ if(pDM_Odm->bLinked) ++ { ++ for (i=0; iTrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) ++ pDM_FatTable->TrainIdx = 0; ++ else ++ pDM_FatTable->TrainIdx++; ++ ++ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; ++ if(IS_STA_VALID(pEntry)) ++ { ++ //Match MAC ADDR ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; ++#else ++ value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; ++#endif ++ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; ++#else ++ value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; ++#endif ++ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n",pDM_FatTable->TrainIdx)); ++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", ++ pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0])); ++#else ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", ++ pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0])); ++#endif ++ ++ break; ++ } ++ } ++ ++ } ++ ++#if 0 ++ // ++ //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn ++ // ++ #if( DM_ODM_SUPPORT_TYPE & ODM_MP) ++ { ++ PADAPTER Adapter = pDM_Odm->Adapter; ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ for (i=0; i<6; i++) ++ { ++ Bssid[i] = pMgntInfo->Bssid[i]; ++ //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); ++ } ++ } ++ #endif ++ ++ //odm_SetNextMACAddrTarget(pDM_Odm); ++ ++ //1 Select MAC Address Filter ++ for (i=0; i<6; i++) ++ { ++ if(Bssid[i] != pDM_FatTable->Bssid[i]) ++ { ++ bMatchBSSID = FALSE; ++ break; ++ } ++ } ++ if(bMatchBSSID == FALSE) ++ { ++ //Match MAC ADDR ++ value32 = (Bssid[5]<<8)|Bssid[4]; ++ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); ++ value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; ++ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); ++ } ++ ++ return bMatchBSSID; ++#endif ++ ++} ++ ++VOID ++odm_FastAntTraining( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ u4Byte i, MaxRSSI=0; ++ u1Byte TargetAnt=2; ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ BOOLEAN bPktFilterMacth = FALSE; ++ PSTA_INFO_T pEntry; ++ ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); ++ ++ //1 TRAINING STATE ++ if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n")); ++ //2 Caculate RSSI per Antenna ++ for (i=0; i<7; i++) ++ { ++ if(pDM_FatTable->antRSSIcnt[i] == 0) ++ pDM_FatTable->antAveRSSI[i] = 0; ++ else ++ { ++ pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; ++ bPktFilterMacth = TRUE; ++ } ++ if(pDM_FatTable->antAveRSSI[i] > MaxRSSI) ++ { ++ MaxRSSI = pDM_FatTable->antAveRSSI[i]; ++ TargetAnt = (u1Byte) i; ++ } ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%d] = %d, pDM_FatTable->antRSSIcnt[%d] = %d\n", ++ i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i])); ++ } ++ ++ //2 Select TRX Antenna ++ if(bPktFilterMacth == FALSE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n")); ++ ++ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training ++ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv ++ } ++ else ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%d\n",TargetAnt,MaxRSSI)); ++ ++ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training ++ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv ++ ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT ++ //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX ++ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info ++ ++#if 0 ++ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; ++ ++ if(IS_STA_VALID(pEntry)) ++ { ++ pEntry->antsel_a = TargetAnt&BIT0; ++ pEntry->antsel_b = (TargetAnt&BIT1)>>1; ++ pEntry->antsel_c = (TargetAnt&BIT2)>>2; ++ } ++#else ++ pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0; ++ pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1; ++ pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2; ++#endif ++ ++ ++ if(TargetAnt == 0) ++ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv ++ ++ } ++ ++ //2 Reset Counter ++ for(i=0; i<7; i++) ++ { ++ pDM_FatTable->antSumRSSI[i] = 0; ++ pDM_FatTable->antRSSIcnt[i] = 0; ++ } ++ ++ pDM_FatTable->FAT_State = FAT_NORMAL_STATE; ++ return; ++ } ++ ++ //1 NORMAL STATE ++ if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n")); ++ ++ odm_SetNextMACAddrTarget(pDM_Odm); ++ ++#if 0 ++ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; ++ if(IS_STA_VALID(pEntry)) ++ { ++ pEntry->antsel_a = TargetAnt&BIT0; ++ pEntry->antsel_b = (TargetAnt&BIT1)>>1; ++ pEntry->antsel_c = (TargetAnt&BIT2)>>2; ++ } ++#endif ++ ++ //2 Prepare Training ++ pDM_FatTable->FAT_State = FAT_TRAINING_STATE; ++ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training ++ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n")); ++ ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms ++ ++ } ++ ++} ++ ++VOID ++odm_FastAntTrainingCallback( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) ++ PADAPTER padapter = pDM_Odm->Adapter; ++ if(padapter->net_closed == _TRUE) ++ return; ++ //if(*pDM_Odm->pbNet_closed == TRUE) ++ // return; ++#endif ++ ++#if USE_WORKITEM ++ ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); ++#else ++ odm_FastAntTraining(pDM_Odm); ++#endif ++} ++ ++VOID ++odm_FastAntTrainingWorkItemCallback( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ odm_FastAntTraining(pDM_Odm); ++} ++#endif ++ ++VOID ++ODM_AntennaDiversity_88E( ++ IN PDM_ODM_T pDM_Odm ++) ++{ ++ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; ++ if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))) ++ { ++ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); ++ return; ++ } ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ if(pDM_Odm->bLinked){ ++ if(pDM_Odm->Adapter->registrypriv.force_ant != 0) ++ { ++ u4Byte Main_RSSI, Aux_RSSI; ++ u8 i=0; ++ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; ++ Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i])); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i])); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); ++ pDM_FatTable->MainAnt_Sum[i] = 0; ++ pDM_FatTable->AuxAnt_Sum[i] = 0; ++ pDM_FatTable->MainAnt_Cnt[i] = 0; ++ pDM_FatTable->AuxAnt_Cnt[i] = 0; ++ } ++ if(pDM_Odm->Adapter->registrypriv.force_ant==1){ ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); ++ printk("%s fixed antenna in Main ant\n",__FUNCTION__); ++ return; ++ } ++ else if(pDM_Odm->Adapter->registrypriv.force_ant==2){ ++ ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); ++ printk("%s fixed antenna in AUX ant\n",__FUNCTION__); ++ return; ++ } ++ } ++#endif ++ ++ ++ ++ if(!pDM_Odm->bLinked) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); ++ if(pDM_FatTable->bBecomeLinked == TRUE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); ++ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg ++ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; ++ } ++ return; ++ } ++ else ++ { ++ if(pDM_FatTable->bBecomeLinked ==FALSE) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); ++ //Because HW AntDiv is disabled before Link, we enable HW AntDiv after link ++ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv ++ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv ++ //ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv ++ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ++ { ++#if TX_BY_REG ++ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg ++#else ++ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info ++#endif ++ } ++ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; ++ } ++ } ++ ++ ++ ++ if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) ++ odm_HWAntDiv(pDM_Odm); ++ #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++ else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) ++ odm_FastAntTraining(pDM_Odm); ++ #endif ++} ++ ++ ++/* ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++VOID ++odm_FastAntTrainingCallback( ++ PRT_TIMER pTimer ++) ++{ ++ PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //#if DEV_BUS_TYPE==RT_PCI_INTERFACE ++ //#if USE_WORKITEM ++ //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem); ++ //#else ++ odm_FastAntTraining(&pHalData->DM_OutSrc); ++ //#endif ++ //#else ++ //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem); ++ //#endif ++ ++} ++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) ++VOID odm_FastAntTrainingCallback(void *FunctionContext) ++{ ++ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; ++ PADAPTER padapter = pDM_Odm->Adapter; ++ if(padapter->net_closed == _TRUE) ++ return; ++ odm_FastAntTraining(pDM_Odm); ++} ++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) ++VOID odm_FastAntTrainingCallback(void *FunctionContext) ++{ ++ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; ++ odm_FastAntTraining(pDM_Odm); ++} ++ ++#endif ++*/ ++ ++#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++ ) ++{ ++} ++#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++} ++#endif ++#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) ++//3============================================================ ++//3 Dynamic Primary CCA ++//3============================================================ ++ ++VOID ++odm_PrimaryCCA_Init( ++ IN PDM_ODM_T pDM_Odm) ++{ ++ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); ++ PrimaryCCA->DupRTS_flag = 0; ++ PrimaryCCA->intf_flag = 0; ++ PrimaryCCA->intf_type = 0; ++ PrimaryCCA->Monitor_flag = 0; ++ PrimaryCCA->PriCCA_flag = 0; ++} ++ ++BOOLEAN ++ODM_DynamicPrimaryCCA_DupRTS( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); ++ ++ return PrimaryCCA->DupRTS_flag; ++} ++ ++VOID ++odm_DynamicPrimaryCCA( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ PADAPTER Adapter = pDM_Odm->Adapter; // for NIC ++ prtl8192cd_priv priv = pDM_Odm->priv; // for AP ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP)) ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ PRT_WLAN_STA pEntry; ++#endif ++ ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); ++ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); ++ ++ BOOLEAN Is40MHz; ++ BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW ++ BOOLEAN bConnected = FALSE; // connected or not ++ static u1Byte Client_40MHz_pre = 0; ++ static u8Byte lastTxOkCnt = 0; ++ static u8Byte lastRxOkCnt = 0; ++ static u4Byte Counter = 0; ++ static u1Byte Delay = 1; ++ u8Byte curTxOkCnt; ++ u8Byte curRxOkCnt; ++ u1Byte SecCHOffset; ++ u1Byte i; ++ ++#if((DM_ODM_SUPPORT_TYPE==ODM_ADSL) ||( DM_ODM_SUPPORT_TYPE==ODM_CE)) ++ return; ++#endif ++ ++ if(pDM_Odm->SupportICType != ODM_RTL8188E) ++ return; ++ ++ Is40MHz = *(pDM_Odm->pBandWidth); ++ SecCHOffset = *(pDM_Odm->pSecChOffset); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ if(Is40MHz==1) ++ SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); ++ //3 Check Current WLAN Traffic ++ curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; ++ curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; ++ lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; ++ lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; ++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ //3 Check Current WLAN Traffic ++ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; ++ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; ++ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); ++ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); ++#endif ++ ++ //==================Debug Message==================== ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail)); ++ //================================================ ++ ++#if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode ++#endif ++ { ++ ++ #if (DM_ODM_SUPPORT_TYPE == ODM_MP) ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter))); ++ //3 To get entry's connection and BW infomation status. ++ for(i=0;iHTInfo.bBw40MHz; // client BW ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp)); ++ if(Client_tmp>Client_40MHz) ++ Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High ++ ++ if(pEntry->bAssociated) ++ { ++ bConnected=TRUE; // client is connected or not ++ break; ++ } ++ } ++ else ++ { ++ break; ++ } ++ } ++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) ++ //3 To get entry's connection and BW infomation status. ++ ++ PSTA_INFO_T pstat; ++ ++ for(i=0; ipODM_StaInfo[i]; ++ if(IS_STA_VALID(pstat) ) ++ { ++ Client_tmp = pstat->tx_bw; ++ if(Client_tmp>Client_40MHz) ++ Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High ++ ++ bConnected = TRUE; ++ } ++ } ++#endif ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz)); ++ //1 Monitor whether the interference exists or not ++ if(PrimaryCCA->Monitor_flag == 1) ++ { ++ if(SecCHOffset == 1) // secondary channel is below the primary channel ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500)) ++ { ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ { ++ PrimaryCCA->intf_type = 1; ++ PrimaryCCA->PriCCA_flag = 1; ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF ++ if(PrimaryCCA->DupRTS_flag == 1) ++ PrimaryCCA->DupRTS_flag = 0; ++ } ++ else ++ { ++ PrimaryCCA->intf_type = 2; ++ if(PrimaryCCA->DupRTS_flag == 0) ++ PrimaryCCA->DupRTS_flag = 1; ++ } ++ ++ } ++ else // interferecne disappear ++ { ++ PrimaryCCA->DupRTS_flag = 0; ++ PrimaryCCA->intf_flag = 0; ++ PrimaryCCA->intf_type = 0; ++ } ++ } ++ else if(SecCHOffset == 2) // secondary channel is above the primary channel ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500)) ++ { ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ { ++ PrimaryCCA->intf_type = 1; ++ PrimaryCCA->PriCCA_flag = 1; ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF ++ if(PrimaryCCA->DupRTS_flag == 1) ++ PrimaryCCA->DupRTS_flag = 0; ++ } ++ else ++ { ++ PrimaryCCA->intf_type = 2; ++ if(PrimaryCCA->DupRTS_flag == 0) ++ PrimaryCCA->DupRTS_flag = 1; ++ } ++ ++ } ++ else // interferecne disappear ++ { ++ PrimaryCCA->DupRTS_flag = 0; ++ PrimaryCCA->intf_flag = 0; ++ PrimaryCCA->intf_type = 0; ++ } ++ ++ ++ } ++ PrimaryCCA->Monitor_flag = 0; ++ } ++ ++ //1 Dynamic Primary CCA Main Function ++ if(PrimaryCCA->Monitor_flag == 0) ++ { ++ if(Is40MHz) // if RFBW==40M mode which require to process primary cca ++ { ++ //2 STA is NOT Connected ++ if(!bConnected) ++ { ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n")); ++ ++ if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected ++ { ++ PrimaryCCA->PriCCA_flag = 0; ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); ++ } ++ if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected ++ PrimaryCCA->DupRTS_flag = 0; ++ ++ if(SecCHOffset == 1) // secondary channel is below the primary channel ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) ++ { ++ PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ } ++ else ++ { ++ PrimaryCCA->intf_flag = 0; ++ PrimaryCCA->intf_type = 0; ++ } ++ } ++ else if(SecCHOffset == 2) // secondary channel is above the primary channel ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) ++ { ++ PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ } ++ else ++ { ++ PrimaryCCA->intf_flag = 0; ++ PrimaryCCA->intf_type = 0; ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type)); ++ } ++ //2 STA is Connected ++ else ++ { ++ if(Client_40MHz == 0) //3 // client BW = 20MHz ++ { ++ if(PrimaryCCA->PriCCA_flag == 0) ++ { ++ PrimaryCCA->PriCCA_flag = 1; ++ if(SecCHOffset==1) ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); ++ else if(SecCHOffset==2) ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag)); ++ } ++ else //3 // client BW = 40MHz ++ { ++ if(PrimaryCCA->intf_flag == 1) // interference is detected!! ++ { ++ if(PrimaryCCA->intf_type == 1) ++ { ++ if(PrimaryCCA->PriCCA_flag!=1) ++ { ++ PrimaryCCA->PriCCA_flag = 1; ++ if(SecCHOffset==1) ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); ++ else if(SecCHOffset==2) ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); ++ } ++ } ++ else if(PrimaryCCA->intf_type == 2) ++ { ++ if(PrimaryCCA->DupRTS_flag!=1) ++ PrimaryCCA->DupRTS_flag = 1; ++ } ++ } ++ else // if intf_flag==0 ++ { ++ if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low ++ { ++ if(SecCHOffset == 1) ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) ++ { ++ PrimaryCCA->intf_flag = 1; ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ } ++ } ++ else if(SecCHOffset == 2) ++ { ++ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) ++ { ++ PrimaryCCA->intf_flag = 1; ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ } ++ ++ } ++ } ++ else // TP Traffic is High ++ { ++ if(SecCHOffset == 1) ++ { ++ if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500)) ++ { ++ if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time ++ { ++ PrimaryCCA->intf_flag = 1; ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ Delay = 1; ++ } ++ else ++ Delay = 0; ++ } ++ } ++ else if(SecCHOffset == 2) ++ { ++ if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500)) ++ { ++ if(Delay == 0) // add delay to avoid interference occurring abruptly ++ { ++ PrimaryCCA->intf_flag = 1; ++ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) ++ PrimaryCCA->intf_type = 1; // interference is shift ++ else ++ PrimaryCCA->intf_type = 2; // interference is in-band ++ Delay = 1; ++ } ++ else ++ Delay = 0; ++ } ++ } ++ } ++ } ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag)); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag)); ++ } ++ ++ }// end of connected ++ } ++ } ++ //1 Dynamic Primary CCA Monitor Counter ++ if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1)) ++ { ++ if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag ++ { ++ Client_40MHz_pre = Client_40MHz; ++ return; ++ } ++ Counter++; ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter)); ++ if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time ++ { ++ PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!! ++ if(PrimaryCCA->PriCCA_flag == 1) ++ { ++ PrimaryCCA->PriCCA_flag = 0; ++ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); ++ } ++ Counter = 0; ++ } ++ } ++ } ++ ++ Client_40MHz_pre = Client_40MHz; ++} ++#else //#if (RTL8188E_SUPPORT == 1) ++VOID ++ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant) ++{ ++} ++VOID ++odm_PrimaryCCA_Init( ++ IN PDM_ODM_T pDM_Odm) ++{ ++} ++VOID ++odm_DynamicPrimaryCCA( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++} ++BOOLEAN ++ODM_DynamicPrimaryCCA_DupRTS( ++ IN PDM_ODM_T pDM_Odm ++ ) ++{ ++ return FALSE; ++} ++#endif //#if (RTL8188E_SUPPORT == 1) ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.h +new file mode 100644 +index 00000000..ac0e0067 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RTL8188E.h +@@ -0,0 +1,109 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __ODM_RTL8188E_H__ ++#define __ODM_RTL8188E_H__ ++ ++#define MAIN_ANT 0 ++#define AUX_ANT 1 ++#define MAIN_ANT_CG_TRX 1 ++#define AUX_ANT_CG_TRX 0 ++#define MAIN_ANT_CGCS_RX 0 ++#define AUX_ANT_CGCS_RX 1 ++ ++VOID ++ODM_DIG_LowerBound_88E( ++ IN PDM_ODM_T pDM_Odm ++); ++#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++VOID ++odm_FastAntTrainingInit( ++ IN PDM_ODM_T pDM_Odm ++); ++#endif ++ ++VOID ++ODM_AntennaDiversityInit_88E( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++VOID ++ODM_AntennaDiversity_88E ++( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN pu1Byte pDesc, ++ IN u1Byte macId ++); ++#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) ++VOID ++ODM_SetTxAntByTxInfo_88E( ++ IN PDM_ODM_T pDM_Odm ++); ++#endif ++ ++VOID ++ODM_UpdateRxIdleAnt_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte Ant ++); ++ ++VOID ++ODM_AntselStatistics_88E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u1Byte antsel_tr_mux, ++ IN u4Byte MacId, ++ IN u1Byte RxPWDBAll ++); ++ ++#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE)) ++VOID ++odm_FastAntTraining( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++VOID ++odm_FastAntTrainingCallback( ++ IN PDM_ODM_T pDM_Odm ++); ++ ++VOID ++odm_FastAntTrainingWorkItemCallback( ++ IN PDM_ODM_T pDM_Odm ++); ++#endif ++VOID ++odm_PrimaryCCA_Init( ++ IN PDM_ODM_T pDM_Odm); ++ ++BOOLEAN ++ODM_DynamicPrimaryCCA_DupRTS( ++ IN PDM_ODM_T pDM_Odm); ++ ++VOID ++odm_DynamicPrimaryCCA( ++ IN PDM_ODM_T pDM_Odm); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c +new file mode 100644 +index 00000000..e0e7c8b8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c +@@ -0,0 +1,209 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include "../odm_precomp.h" ++ ++#if (RTL8188E_SUPPORT == 1) ++ ++void ++odm_ConfigRFReg_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data, ++ IN ODM_RF_RADIO_PATH_E RF_PATH, ++ IN u4Byte RegAddr ++ ) ++{ ++ if(Addr == 0xffe) ++ { ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ ODM_sleep_ms(50); ++ #else ++ ODM_delay_ms(50); ++ #endif ++ } ++ else if (Addr == 0xfd) ++ { ++ ODM_delay_ms(5); ++ } ++ else if (Addr == 0xfc) ++ { ++ ODM_delay_ms(1); ++ } ++ else if (Addr == 0xfb) ++ { ++ ODM_delay_us(50); ++ } ++ else if (Addr == 0xfa) ++ { ++ ODM_delay_us(5); ++ } ++ else if (Addr == 0xf9) ++ { ++ ODM_delay_us(1); ++ } ++ else ++ { ++ ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); ++ // Add 1us delay between BB/RF register setting. ++ ODM_delay_us(1); ++ } ++} ++ ++ ++void ++odm_ConfigRF_RadioA_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data ++ ) ++{ ++ u4Byte content = 0x1000; // RF_Content: radioa_txt ++ u4Byte maskforPhySet= (u4Byte)(content&0xE000); ++ ++ odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); ++} ++ ++void ++odm_ConfigRF_RadioB_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data ++ ) ++{ ++ u4Byte content = 0x1001; // RF_Content: radiob_txt ++ u4Byte maskforPhySet= (u4Byte)(content&0xE000); ++ ++ odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); ++ ++} ++ ++void ++odm_ConfigMAC_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u1Byte Data ++ ) ++{ ++ ODM_Write1Byte(pDM_Odm, Addr, Data); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); ++} ++ ++void ++odm_ConfigBB_AGC_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ) ++{ ++ ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); ++ // Add 1us delay between BB/RF register setting. ++ ODM_delay_us(1); ++ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); ++} ++ ++void ++odm_ConfigBB_PHY_REG_PG_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ) ++{ ++ if (Addr == 0xfe){ ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ ODM_sleep_ms(50); ++ #else ++ ODM_delay_ms(50); ++ #endif ++ } ++ else if (Addr == 0xfd){ ++ ODM_delay_ms(5); ++ } ++ else if (Addr == 0xfc){ ++ ODM_delay_ms(1); ++ } ++ else if (Addr == 0xfb){ ++ ODM_delay_us(50); ++ } ++ else if (Addr == 0xfa){ ++ ODM_delay_us(5); ++ } ++ else if (Addr == 0xf9){ ++ ODM_delay_us(1); ++ } ++ else{ ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); ++ ++ #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) ++ storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); ++ #endif ++ } ++ ++} ++ ++void ++odm_ConfigBB_PHY_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ) ++{ ++ if (Addr == 0xfe){ ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ ODM_sleep_ms(50); ++ #else ++ ODM_delay_ms(50); ++ #endif ++ } ++ else if (Addr == 0xfd){ ++ ODM_delay_ms(5); ++ } ++ else if (Addr == 0xfc){ ++ ODM_delay_ms(1); ++ } ++ else if (Addr == 0xfb){ ++ ODM_delay_us(50); ++ } ++ else if (Addr == 0xfa){ ++ ODM_delay_us(5); ++ } ++ else if (Addr == 0xf9){ ++ ODM_delay_us(1); ++ } ++ else{ ++ if (Addr == 0xa24) ++ pDM_Odm->RFCalibrateInfo.RegA24 = Data; ++ ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); ++ ++ // Add 1us delay between BB/RF register setting. ++ ODM_delay_us(1); ++ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); ++ } ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h +new file mode 100644 +index 00000000..211b96de +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h +@@ -0,0 +1,80 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_ODM_REGCONFIG_H_8188E ++#define __INC_ODM_REGCONFIG_H_8188E ++ ++#if (RTL8188E_SUPPORT == 1) ++ ++void ++odm_ConfigRFReg_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data, ++ IN ODM_RF_RADIO_PATH_E RF_PATH, ++ IN u4Byte RegAddr ++ ); ++ ++void ++odm_ConfigRF_RadioA_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data ++ ); ++ ++void ++odm_ConfigRF_RadioB_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Data ++ ); ++ ++void ++odm_ConfigMAC_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u1Byte Data ++ ); ++ ++void ++odm_ConfigBB_AGC_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ); ++ ++void ++odm_ConfigBB_PHY_REG_PG_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ); ++ ++void ++odm_ConfigBB_PHY_8188E( ++ IN PDM_ODM_T pDM_Odm, ++ IN u4Byte Addr, ++ IN u4Byte Bitmask, ++ IN u4Byte Data ++ ); ++#endif ++#endif // end of SUPPORT ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/hal_com.c b/drivers/net/wireless/rtl818x/rtl8189/hal/hal_com.c +new file mode 100644 +index 00000000..9f413a09 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/hal_com.c +@@ -0,0 +1,453 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++ ++#define _HAL_INIT_C_ ++ ++void dump_chip_info(HAL_VERSION ChipVersion) ++{ ++ int cnt = 0; ++ u8 buf[128]; ++ ++ if(IS_81XXC(ChipVersion)){ ++ cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C"); ++ } ++ else if(IS_92D(ChipVersion)){ ++ cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_"); ++ } ++ else if(IS_8723_SERIES(ChipVersion)){ ++ cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_"); ++ } ++ else if(IS_8188E(ChipVersion)){ ++ cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_"); ++ } ++ ++ cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip"); ++ cnt += sprintf((buf+cnt), "%s_", IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC"); ++ if(IS_A_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "A_CUT_"); ++ else if(IS_B_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "B_CUT_"); ++ else if(IS_C_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "C_CUT_"); ++ else if(IS_D_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "D_CUT_"); ++ else if(IS_E_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "E_CUT_"); ++ else if(IS_I_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "I_CUT_"); ++ else if(IS_J_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "J_CUT_"); ++ else if(IS_K_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "K_CUT_"); ++ else cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion); ++ ++ if(IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_"); ++ else if(IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_"); ++ else if(IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_"); ++ else cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType); ++ ++ cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer); ++ ++ DBG_871X("%s", buf); ++} ++ ++ ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++u8 //return the final channel plan decision ++hal_com_get_channel_plan( ++ IN PADAPTER padapter, ++ IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom) ++ IN u8 sw_channel_plan, //channel plan from SW (registry/module param) ++ IN u8 def_channel_plan, //channel plan used when the former two is invalid ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u8 swConfig; ++ u8 chnlPlan; ++ ++ swConfig = _TRUE; ++ if (!AutoLoadFail) ++ { ++ if (!rtw_is_channel_plan_valid(sw_channel_plan)) ++ swConfig = _FALSE; ++ if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ++ swConfig = _FALSE; ++ } ++ ++ if (swConfig == _TRUE) ++ chnlPlan = sw_channel_plan; ++ else ++ chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK); ++ ++ if (!rtw_is_channel_plan_valid(chnlPlan)) ++ chnlPlan = def_channel_plan; ++ ++ return chnlPlan; ++} ++ ++u8 MRateToHwRate(u8 rate) ++{ ++ u8 ret = DESC_RATE1M; ++ ++ switch(rate) ++ { ++ // CCK and OFDM non-HT rates ++ case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break; ++ case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break; ++ case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break; ++ case IEEE80211_CCK_RATE_11MB: ret = DESC_RATE11M; break; ++ case IEEE80211_OFDM_RATE_6MB: ret = DESC_RATE6M; break; ++ case IEEE80211_OFDM_RATE_9MB: ret = DESC_RATE9M; break; ++ case IEEE80211_OFDM_RATE_12MB: ret = DESC_RATE12M; break; ++ case IEEE80211_OFDM_RATE_18MB: ret = DESC_RATE18M; break; ++ case IEEE80211_OFDM_RATE_24MB: ret = DESC_RATE24M; break; ++ case IEEE80211_OFDM_RATE_36MB: ret = DESC_RATE36M; break; ++ case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break; ++ case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break; ++ ++ // HT rates since here ++ //case MGN_MCS0: ret = DESC_RATEMCS0; break; ++ //case MGN_MCS1: ret = DESC_RATEMCS1; break; ++ //case MGN_MCS2: ret = DESC_RATEMCS2; break; ++ //case MGN_MCS3: ret = DESC_RATEMCS3; break; ++ //case MGN_MCS4: ret = DESC_RATEMCS4; break; ++ //case MGN_MCS5: ret = DESC_RATEMCS5; break; ++ //case MGN_MCS6: ret = DESC_RATEMCS6; break; ++ //case MGN_MCS7: ret = DESC_RATEMCS7; break; ++ ++ default: break; ++ } ++ ++ return ret; ++} ++ ++void HalSetBrateCfg( ++ IN PADAPTER Adapter, ++ IN u8 *mBratesOS, ++ OUT u16 *pBrateCfg) ++{ ++ u8 i, is_brate, brate; ++ ++ for(i=0;iQueue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO ++ pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI ++ pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE ++ pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK ++ ++ pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN ++ pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT ++ pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH ++ pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD ++} ++ ++static VOID ++_TwoOutPipeMapping( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bWIFICfg ++ ) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); ++ ++ if(bWIFICfg){ //WMM ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 0, 1, 0, 1, 0, 0, 0, 0, 0 }; ++ //0:H, 1:L ++ ++ pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO ++ pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI ++ pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE ++ pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK ++ ++ pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN ++ pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT ++ pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH ++ pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD ++ ++ } ++ else{//typical setting ++ ++ ++ //BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 1, 1, 0, 0, 0, 0, 0, 0, 0 }; ++ //0:H, 1:L ++ ++ pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO ++ pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI ++ pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE ++ pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK ++ ++ pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN ++ pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT ++ pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH ++ pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD ++ ++ } ++ ++} ++ ++static VOID _ThreeOutPipeMapping( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bWIFICfg ++ ) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); ++ ++ if(bWIFICfg){//for WMM ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 }; ++ //0:H, 1:N, 2:L ++ ++ pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO ++ pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI ++ pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE ++ pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK ++ ++ pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN ++ pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT ++ pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH ++ pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD ++ ++ } ++ else{//typical setting ++ ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 }; ++ //0:H, 1:N, 2:L ++ ++ pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO ++ pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI ++ pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE ++ pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK ++ ++ pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN ++ pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT ++ pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH ++ pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD ++ } ++ ++} ++ ++BOOLEAN ++Hal_MappingOutPipe( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe ++ ) ++{ ++ struct registry_priv *pregistrypriv = &pAdapter->registrypriv; ++ ++ BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE; ++ ++ BOOLEAN result = _TRUE; ++ ++ switch(NumOutPipe) ++ { ++ case 2: ++ _TwoOutPipeMapping(pAdapter, bWIFICfg); ++ break; ++ case 3: ++ _ThreeOutPipeMapping(pAdapter, bWIFICfg); ++ break; ++ case 1: ++ _OneOutPipeMapping(pAdapter); ++ break; ++ default: ++ result = _FALSE; ++ break; ++ } ++ ++ return result; ++ ++} ++ ++void hal_init_macaddr(_adapter *adapter) ++{ ++ rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr); ++#ifdef CONFIG_CONCURRENT_MODE ++ if (adapter->pbuddy_adapter) ++ rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter->pbuddy_adapter->eeprompriv.mac_addr); ++#endif ++} ++ ++/* ++* C2H event format: ++* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID ++* BITS [127:120] [119:16] [15:8] [7:4] [3:0] ++*/ ++ ++void c2h_evt_clear(_adapter *adapter) ++{ ++ rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); ++} ++ ++s32 c2h_evt_read(_adapter *adapter, u8 *buf) ++{ ++ s32 ret = _FAIL; ++ struct c2h_evt_hdr *c2h_evt; ++ int i; ++ u8 trigger; ++ ++ if (buf == NULL) ++ goto exit; ++ ++ trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR); ++ ++ if (trigger == C2H_EVT_HOST_CLOSE) { ++ goto exit; /* Not ready */ ++ } else if (trigger != C2H_EVT_FW_CLOSE) { ++ goto clear_evt; /* Not a valid value */ ++ } ++ ++ c2h_evt = (struct c2h_evt_hdr *)buf; ++ ++ _rtw_memset(c2h_evt, 0, 16); ++ ++ *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); ++ *(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1); ++ ++ RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ", ++ &c2h_evt , sizeof(c2h_evt)); ++ ++ if (0) { ++ DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__ ++ , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); ++ } ++ ++ /* Read the content */ ++ for (i = 0; i < c2h_evt->plen; i++) ++ c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i); ++ ++ RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n", ++ c2h_evt->payload, c2h_evt->plen); ++ ++ ret = _SUCCESS; ++ ++clear_evt: ++ /* ++ * Clear event to notify FW we have read the command. ++ * If this field isn't clear, the FW won't update the next command message. ++ */ ++ c2h_evt_clear(adapter); ++exit: ++ return ret; ++} ++ ++u8 ++SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ u8 bResult = _SUCCESS; ++ ++ switch(variable) { ++ case HW_DEF_FA_CNT_DUMP: ++ if(*((u8*)value)) ++ pDM_Odm->DebugComponents |= (ODM_COMP_DIG |ODM_COMP_FA_CNT); ++ else ++ pDM_Odm->DebugComponents &= ~(ODM_COMP_DIG |ODM_COMP_FA_CNT); ++ break; ++ case HW_DEF_ODM_DBG_FLAG: ++ ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_COMP, *((u8Byte*)value)); ++ break; ++ case HW_DEF_ODM_DBG_LEVEL: ++ ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_LEVEL, *((u4Byte*)value)); ++ break; ++ default: ++ DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); ++ bResult = _FAIL; ++ break; ++ } ++ ++ return bResult; ++} ++ ++u8 ++GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ u8 bResult = _SUCCESS; ++ ++ switch(variable) { ++ case HW_DEF_ODM_DBG_FLAG: ++ *((u8Byte*)value) = pDM_Odm->DebugComponents; ++ break; ++ case HW_DEF_ODM_DBG_LEVEL: ++ *((u4Byte*)value) = pDM_Odm->DebugLevel; ++ break; ++ case HAL_DEF_DBG_DM_FUNC: ++ *((u32*)value) = pHalData->odmpriv.SupportAbility; ++ break; ++ default: ++ DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); ++ bResult = _FAIL; ++ break; ++ } ++ ++ return bResult; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/hal_intf.c b/drivers/net/wireless/rtl818x/rtl8189/hal/hal_intf.c +new file mode 100644 +index 00000000..8b785532 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/hal_intf.c +@@ -0,0 +1,591 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#define _HAL_INTF_C_ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++ #include ++#elif defined(CONFIG_USB_HCI) ++ #include ++#elif defined(CONFIG_GSPI_HCI) ++ #include ++#endif ++ ++void rtw_hal_chip_configure(_adapter *padapter) ++{ ++ if(padapter->HalFunc.intf_chip_configure) ++ padapter->HalFunc.intf_chip_configure(padapter); ++} ++ ++void rtw_hal_read_chip_info(_adapter *padapter) ++{ ++ if(padapter->HalFunc.read_adapter_info) ++ padapter->HalFunc.read_adapter_info(padapter); ++} ++ ++void rtw_hal_read_chip_version(_adapter *padapter) ++{ ++ if(padapter->HalFunc.read_chip_version) ++ padapter->HalFunc.read_chip_version(padapter); ++} ++ ++void rtw_hal_def_value_init(_adapter *padapter) ++{ ++ if (is_primary_adapter(padapter)) ++ if(padapter->HalFunc.init_default_value) ++ padapter->HalFunc.init_default_value(padapter); ++} ++void rtw_hal_free_data(_adapter *padapter) ++{ ++ if (is_primary_adapter(padapter)) ++ if(padapter->HalFunc.free_hal_data) ++ padapter->HalFunc.free_hal_data(padapter); ++} ++void rtw_hal_dm_init(_adapter *padapter) ++{ ++ if (is_primary_adapter(padapter)) ++ if(padapter->HalFunc.dm_init) ++ padapter->HalFunc.dm_init(padapter); ++} ++void rtw_hal_dm_deinit(_adapter *padapter) ++{ ++ // cancel dm timer ++ if (is_primary_adapter(padapter)) ++ if(padapter->HalFunc.dm_deinit) ++ padapter->HalFunc.dm_deinit(padapter); ++} ++void rtw_hal_sw_led_init(_adapter *padapter) ++{ ++ if(padapter->HalFunc.InitSwLeds) ++ padapter->HalFunc.InitSwLeds(padapter); ++} ++ ++void rtw_hal_sw_led_deinit(_adapter *padapter) ++{ ++ if(padapter->HalFunc.DeInitSwLeds) ++ padapter->HalFunc.DeInitSwLeds(padapter); ++} ++ ++u32 rtw_hal_power_on(_adapter *padapter) ++{ ++ if(padapter->HalFunc.hal_power_on) ++ return padapter->HalFunc.hal_power_on(padapter); ++ return _FAIL; ++} ++void rtw_hal_power_off(_adapter *padapter) ++{ ++ if(padapter->HalFunc.hal_power_off) ++ padapter->HalFunc.hal_power_off(padapter); ++} ++ ++ ++uint rtw_hal_init(_adapter *padapter) ++{ ++ uint status = _SUCCESS; ++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); ++ int i; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if(padapter->hw_init_completed == _TRUE) ++ { ++ DBG_871X("rtw_hal_init: hw_init_completed == _TRUE\n"); ++ return status; ++ } ++ ++ // before init mac0, driver must init mac1 first to avoid usb rx error. ++ if((padapter->pbuddy_adapter != NULL) && (padapter->DualMacConcurrent == _TRUE) ++ && (padapter->adapter_type == PRIMARY_ADAPTER)) ++ { ++ if(padapter->pbuddy_adapter->hw_init_completed == _TRUE) ++ { ++ DBG_871X("rtw_hal_init: pbuddy_adapter hw_init_completed == _TRUE\n"); ++ } ++ else ++ { ++ status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter); ++ if(status == _SUCCESS){ ++ padapter->pbuddy_adapter->hw_init_completed = _TRUE; ++ } ++ else{ ++ padapter->pbuddy_adapter->hw_init_completed = _FALSE; ++ RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail(pbuddy_adapter)\n")); ++ DBG_871X("rtw_hal_init: hal__init fail(pbuddy_adapter)\n"); ++ return status; ++ } ++ } ++ } ++#endif ++ ++ status = padapter->HalFunc.hal_init(padapter); ++ ++ if(status == _SUCCESS){ ++ for (i = 0; iiface_nums; i++) { ++ padapter = dvobj->padapters[i]; ++ padapter->hw_init_completed = _TRUE; ++ } ++ ++ if (padapter->registrypriv.notch_filter == 1) ++ rtw_hal_notch_filter(padapter, 1); ++ ++ rtw_hal_reset_security_engine(padapter); ++ rtw_sec_restore_wep_key(padapter); ++ ++ init_hw_mlme_ext(padapter); ++ } ++ else{ ++ for (i = 0; iiface_nums; i++) { ++ padapter = dvobj->padapters[i]; ++ padapter->hw_init_completed = _FALSE; ++ } ++ DBG_871X("rtw_hal_init: hal__init fail\n"); ++ } ++ ++ RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status)); ++ ++ return status; ++ ++} ++ ++uint rtw_hal_deinit(_adapter *padapter) ++{ ++ uint status = _SUCCESS; ++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); ++ int i; ++ ++_func_enter_; ++ if (!is_primary_adapter(padapter)){ ++ DBG_871X(" rtw_hal_deinit: Secondary adapter return l\n"); ++ return status; ++ } ++ ++ status = padapter->HalFunc.hal_deinit(padapter); ++ ++ if(status == _SUCCESS){ ++ for (i = 0; iiface_nums; i++) { ++ padapter = dvobj->padapters[i]; ++ padapter->hw_init_completed = _FALSE; ++ } ++ } ++ else ++ { ++ DBG_871X("\n rtw_hal_deinit: hal_init fail\n"); ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++ ++void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) ++{ ++ if (padapter->HalFunc.SetHwRegHandler) ++ padapter->HalFunc.SetHwRegHandler(padapter, variable, val); ++} ++ ++void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) ++{ ++ if (padapter->HalFunc.GetHwRegHandler) ++ padapter->HalFunc.GetHwRegHandler(padapter, variable, val); ++} ++ ++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) ++{ ++ if(padapter->HalFunc.SetHalDefVarHandler) ++ return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue); ++ return _FAIL; ++} ++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) ++{ ++ if(padapter->HalFunc.GetHalDefVarHandler) ++ return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue); ++ return _FAIL; ++} ++ ++void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet) ++{ ++ if(padapter->HalFunc.SetHalODMVarHandler) ++ padapter->HalFunc.SetHalODMVarHandler(padapter,eVariable,pValue1,bSet); ++} ++void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet) ++{ ++ if(padapter->HalFunc.GetHalODMVarHandler) ++ padapter->HalFunc.GetHalODMVarHandler(padapter,eVariable,pValue1,bSet); ++} ++ ++void rtw_hal_enable_interrupt(_adapter *padapter) ++{ ++ if (!is_primary_adapter(padapter)){ ++ DBG_871X(" rtw_hal_enable_interrupt: Secondary adapter return l\n"); ++ return; ++ } ++ ++ if (padapter->HalFunc.enable_interrupt) ++ padapter->HalFunc.enable_interrupt(padapter); ++ else ++ DBG_871X("%s: HalFunc.enable_interrupt is NULL!\n", __FUNCTION__); ++ ++} ++void rtw_hal_disable_interrupt(_adapter *padapter) ++{ ++ if (!is_primary_adapter(padapter)){ ++ DBG_871X(" rtw_hal_disable_interrupt: Secondary adapter return l\n"); ++ return; ++ } ++ ++ if (padapter->HalFunc.disable_interrupt) ++ padapter->HalFunc.disable_interrupt(padapter); ++ else ++ DBG_871X("%s: HalFunc.disable_interrupt is NULL!\n", __FUNCTION__); ++ ++} ++ ++ ++u32 rtw_hal_inirp_init(_adapter *padapter) ++{ ++ u32 rst = _FAIL; ++ if(padapter->HalFunc.inirp_init) ++ rst = padapter->HalFunc.inirp_init(padapter); ++ else ++ DBG_871X(" %s HalFunc.inirp_init is NULL!!!\n",__FUNCTION__); ++ return rst; ++} ++ ++u32 rtw_hal_inirp_deinit(_adapter *padapter) ++{ ++ ++ if(padapter->HalFunc.inirp_deinit) ++ return padapter->HalFunc.inirp_deinit(padapter); ++ ++ return _FAIL; ++ ++} ++ ++u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val) ++{ ++ if(padapter->HalFunc.interface_ps_func) ++ return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val); ++ return _FAIL; ++} ++ ++s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ if(padapter->HalFunc.hal_xmitframe_enqueue) ++ return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe); ++ ++ return _FALSE; ++} ++ ++s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ if(padapter->HalFunc.hal_xmit) ++ return padapter->HalFunc.hal_xmit(padapter, pxmitframe); ++ ++ return _FALSE; ++} ++ ++s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++ s32 ret = _FAIL; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); ++ ++#ifdef CONFIG_IEEE80211W ++ if(padapter->securitypriv.binstallBIPkey == _TRUE) ++ { ++ if(IS_MCAST(pmgntframe->attrib.ra)) ++ { ++ pmgntframe->attrib.encrypt = _BIP_; ++ //pmgntframe->attrib.bswenc = _TRUE; ++ } ++ else ++ { ++ pmgntframe->attrib.encrypt = _AES_; ++ pmgntframe->attrib.bswenc = _TRUE; ++ } ++ rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe); ++ } ++#endif //CONFIG_IEEE80211W ++ ++ if(padapter->HalFunc.mgnt_xmit) ++ ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe); ++ return ret; ++} ++ ++s32 rtw_hal_init_xmit_priv(_adapter *padapter) ++{ ++ if(padapter->HalFunc.init_xmit_priv != NULL) ++ return padapter->HalFunc.init_xmit_priv(padapter); ++ return _FAIL; ++} ++void rtw_hal_free_xmit_priv(_adapter *padapter) ++{ ++ if(padapter->HalFunc.free_xmit_priv != NULL) ++ padapter->HalFunc.free_xmit_priv(padapter); ++} ++ ++s32 rtw_hal_init_recv_priv(_adapter *padapter) ++{ ++ if(padapter->HalFunc.init_recv_priv) ++ return padapter->HalFunc.init_recv_priv(padapter); ++ ++ return _FAIL; ++} ++void rtw_hal_free_recv_priv(_adapter *padapter) ++{ ++ if(padapter->HalFunc.free_recv_priv) ++ padapter->HalFunc.free_recv_priv(padapter); ++} ++ ++void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level) ++{ ++ _adapter *padapter; ++ struct mlme_priv *pmlmepriv; ++ ++ if(!psta) ++ return; ++ ++ padapter = psta->padapter; ++ ++ pmlmepriv = &(padapter->mlmepriv); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ add_RATid(padapter, psta, rssi_level); ++ } ++ else ++ { ++ if(padapter->HalFunc.UpdateRAMaskHandler) ++ padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level); ++ } ++} ++ ++void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level) ++{ ++ if(padapter->HalFunc.Add_RateATid) ++ padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level); ++} ++ ++/* Start specifical interface thread */ ++void rtw_hal_start_thread(_adapter *padapter) ++{ ++ if(padapter->HalFunc.run_thread) ++ padapter->HalFunc.run_thread(padapter); ++} ++/* Start specifical interface thread */ ++void rtw_hal_stop_thread(_adapter *padapter) ++{ ++ if(padapter->HalFunc.cancel_thread) ++ padapter->HalFunc.cancel_thread(padapter); ++} ++ ++u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask) ++{ ++ u32 data = 0; ++ if(padapter->HalFunc.read_bbreg) ++ data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask); ++ return data; ++} ++void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) ++{ ++ if(padapter->HalFunc.write_bbreg) ++ padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data); ++} ++ ++u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) ++{ ++ u32 data = 0; ++ if( padapter->HalFunc.read_rfreg) ++ data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask); ++ return data; ++} ++void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) ++{ ++ if(padapter->HalFunc.write_rfreg) ++ padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); ++} ++ ++s32 rtw_hal_interrupt_handler(_adapter *padapter) ++{ ++ if(padapter->HalFunc.interrupt_handler) ++ return padapter->HalFunc.interrupt_handler(padapter); ++ return _FAIL; ++} ++ ++void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset) ++{ ++ if(padapter->HalFunc.set_bwmode_handler) ++ padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset); ++} ++ ++void rtw_hal_set_chan(_adapter *padapter, u8 channel) ++{ ++ if(padapter->HalFunc.set_channel_handler) ++ padapter->HalFunc.set_channel_handler(padapter, channel); ++} ++ ++void rtw_hal_dm_watchdog(_adapter *padapter) ++{ ++#if defined(CONFIG_CONCURRENT_MODE) ++ if (padapter->adapter_type != PRIMARY_ADAPTER) ++ return; ++#endif ++ if(padapter->HalFunc.hal_dm_watchdog) ++ padapter->HalFunc.hal_dm_watchdog(padapter); ++} ++ ++void rtw_hal_bcn_related_reg_setting(_adapter *padapter) ++{ ++ if(padapter->HalFunc.SetBeaconRelatedRegistersHandler) ++ padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter); ++} ++ ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++u8 rtw_hal_antdiv_before_linked(_adapter *padapter) ++{ ++ if(padapter->HalFunc.AntDivBeforeLinkHandler) ++ return padapter->HalFunc.AntDivBeforeLinkHandler(padapter); ++ return _FALSE; ++} ++void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src) ++{ ++ if(padapter->HalFunc.AntDivCompareHandler) ++ padapter->HalFunc.AntDivCompareHandler(padapter, dst, src); ++} ++#endif ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) ++{ ++ if(padapter->HalFunc.hostap_mgnt_xmit_entry) ++ return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt); ++ return _FAIL; ++} ++#endif //CONFIG_HOSTAPD_MLME ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++void rtw_hal_sreset_init(_adapter *padapter) ++{ ++ if(padapter->HalFunc.sreset_init_value) ++ padapter->HalFunc.sreset_init_value(padapter); ++} ++void rtw_hal_sreset_reset(_adapter *padapter) ++{ ++ padapter = GET_PRIMARY_ADAPTER(padapter); ++ ++ if(padapter->HalFunc.silentreset) ++ padapter->HalFunc.silentreset(padapter); ++} ++ ++void rtw_hal_sreset_reset_value(_adapter *padapter) ++{ ++ if(padapter->HalFunc.sreset_reset_value) ++ padapter->HalFunc.sreset_reset_value(padapter); ++} ++ ++void rtw_hal_sreset_xmit_status_check(_adapter *padapter) ++{ ++ if (!is_primary_adapter(padapter)) ++ return; ++ ++ if(padapter->HalFunc.sreset_xmit_status_check) ++ padapter->HalFunc.sreset_xmit_status_check(padapter); ++} ++void rtw_hal_sreset_linked_status_check(_adapter *padapter) ++{ ++ if (!is_primary_adapter(padapter)) ++ return; ++ ++ if(padapter->HalFunc.sreset_linked_status_check) ++ padapter->HalFunc.sreset_linked_status_check(padapter); ++} ++u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter) ++{ ++ u8 status = 0; ++ if(padapter->HalFunc.sreset_get_wifi_status) ++ status = padapter->HalFunc.sreset_get_wifi_status(padapter); ++ return status; ++} ++ ++bool rtw_hal_sreset_inprogress(_adapter *padapter) ++{ ++ bool inprogress = _FALSE; ++ ++ padapter = GET_PRIMARY_ADAPTER(padapter); ++ ++ if(padapter->HalFunc.sreset_inprogress) ++ inprogress = padapter->HalFunc.sreset_inprogress(padapter); ++ return inprogress; ++} ++#endif //DBG_CONFIG_ERROR_DETECT ++ ++#ifdef CONFIG_IOL ++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) ++{ ++ if(adapter->HalFunc.IOL_exec_cmds_sync) ++ return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,bndy_cnt); ++ return _FAIL; ++} ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++s32 rtw_hal_xmit_thread_handler(_adapter *padapter) ++{ ++ if(padapter->HalFunc.xmit_thread_handler) ++ return padapter->HalFunc.xmit_thread_handler(padapter); ++ return _FAIL; ++} ++#endif ++ ++void rtw_hal_notch_filter(_adapter *adapter, bool enable) ++{ ++ if(adapter->HalFunc.hal_notch_filter) ++ adapter->HalFunc.hal_notch_filter(adapter,enable); ++} ++ ++void rtw_hal_reset_security_engine(_adapter * adapter) ++{ ++ if(adapter->HalFunc.hal_reset_security_engine) ++ adapter->HalFunc.hal_reset_security_engine(adapter); ++} ++ ++s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt) ++{ ++ s32 ret = _FAIL; ++ if (adapter->HalFunc.c2h_handler) ++ ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt); ++ return ret; ++} ++ ++c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter) ++{ ++ return adapter->HalFunc.c2h_id_filter_ccx; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/Hal8188EPwrSeq.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/Hal8188EPwrSeq.c +new file mode 100644 +index 00000000..c38c25a0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/Hal8188EPwrSeq.c +@@ -0,0 +1,97 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include "Hal8188EPwrSeq.h" ++#include ++ ++/* ++ drivers should parse below arrays and do the corresponding actions ++*/ ++//3 Power on Array ++WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_CARDEMU_TO_ACT ++ RTL8188E_TRANS_END ++}; ++ ++//3Radio off Array ++WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_ACT_TO_CARDEMU ++ RTL8188E_TRANS_END ++}; ++ ++//3Card Disable Array ++WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_ACT_TO_CARDEMU ++ RTL8188E_TRANS_CARDEMU_TO_CARDDIS ++ RTL8188E_TRANS_END ++}; ++ ++//3 Card Enable Array ++WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_CARDDIS_TO_CARDEMU ++ RTL8188E_TRANS_CARDEMU_TO_ACT ++ RTL8188E_TRANS_END ++}; ++ ++//3Suspend Array ++WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_ACT_TO_CARDEMU ++ RTL8188E_TRANS_CARDEMU_TO_SUS ++ RTL8188E_TRANS_END ++}; ++ ++//3 Resume Array ++WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_SUS_TO_CARDEMU ++ RTL8188E_TRANS_CARDEMU_TO_ACT ++ RTL8188E_TRANS_END ++}; ++ ++ ++//3HWPDN Array ++WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ RTL8188E_TRANS_ACT_TO_CARDEMU ++ RTL8188E_TRANS_CARDEMU_TO_PDN ++ RTL8188E_TRANS_END ++}; ++ ++//3 Enter LPS ++WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ //FW behavior ++ RTL8188E_TRANS_ACT_TO_LPS ++ RTL8188E_TRANS_END ++}; ++ ++//3 Leave LPS ++WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= ++{ ++ //FW behavior ++ RTL8188E_TRANS_LPS_TO_ACT ++ RTL8188E_TRANS_END ++}; ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_cmd.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_cmd.c +new file mode 100644 +index 00000000..4decacc3 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_cmd.c +@@ -0,0 +1,1493 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_CMD_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define CONFIG_H2C_EF ++ ++#define RTL88E_MAX_H2C_BOX_NUMS 4 ++#define RTL88E_MAX_CMD_LEN 7 ++#define RTL88E_MESSAGE_BOX_SIZE 4 ++#define RTL88E_EX_MESSAGE_BOX_SIZE 4 ++#define RTL88E_RSVDPAGE_SIZE 1024 ++ ++static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num) ++{ ++ u8 read_down = _FALSE; ++ int retry_cnts = 100; ++ ++ u8 valid; ++ ++ //DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); ++ ++ do{ ++ valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num); ++ if(0 == valid ){ ++ read_down = _TRUE; ++ } ++#ifdef CONFIG_WOWLAN ++ rtw_msleep_os(2); ++#endif ++ }while( (!read_down) && (retry_cnts--)); ++ ++ return read_down; ++ ++} ++ ++ ++/***************************************** ++* H2C Msg format : ++* 0x1DF - 0x1D0 ++*| 31 - 8 | 7-5 4 - 0 | ++*| h2c_msg |Class_ID CMD_ID | ++* ++* Extend 0x1FF - 0x1F0 ++*|31 - 0 | ++*|ext_msg| ++******************************************/ ++static s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) ++{ ++ u8 bcmd_down = _FALSE; ++ s32 retry_cnts = 100; ++ u8 h2c_box_num; ++ u32 msgbox_addr; ++ u32 msgbox_ex_addr; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 cmd_idx,ext_cmd_len; ++ u32 h2c_cmd = 0; ++ u32 h2c_cmd_ex = 0; ++ s32 ret = _FAIL; ++ ++_func_enter_; ++ ++ padapter = GET_PRIMARY_ADAPTER(padapter); ++ pHalData = GET_HAL_DATA(padapter); ++ ++ if(padapter->bFWReady == _FALSE) ++ { ++ DBG_8192C("FillH2CCmd_88E(): return H2C cmd because fw is not ready\n"); ++ return ret; ++ } ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); ++ ++ if (!pCmdBuffer) { ++ goto exit; ++ } ++ if (CmdLen > RTL88E_MAX_CMD_LEN) { ++ goto exit; ++ } ++ if (padapter->bSurpriseRemoved == _TRUE) ++ goto exit; ++ ++ //pay attention to if race condition happened in H2C cmd setting. ++ do{ ++ h2c_box_num = pHalData->LastHMEBoxNum; ++ ++ if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){ ++ DBG_8192C(" fw read cmd failed...\n"); ++ goto exit; ++ } ++ ++ *(u8*)(&h2c_cmd) = ElementID; ++ ++ if(CmdLen<=3) ++ { ++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen ); ++ } ++ else{ ++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer,3); ++ ext_cmd_len = CmdLen-3; ++ _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len ); ++ ++ //Write Ext command ++ msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE); ++ #ifdef CONFIG_H2C_EF ++ for(cmd_idx=0;cmd_idxh2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" ++ // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex); ++ ++ pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS; ++ ++ }while((!bcmd_down) && (retry_cnts--)); ++ ++ ret = _SUCCESS; ++ ++exit: ++ ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ u8 ElementID, CmdLen; ++ u8 *pCmdBuffer; ++ struct cmd_msg_parm *pcmdmsg; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ pcmdmsg = (struct cmd_msg_parm*)pbuf; ++ ElementID = pcmdmsg->eid; ++ CmdLen = pcmdmsg->sz; ++ pCmdBuffer = pcmdmsg->buf; ++ ++ FillH2CCmd_88E(padapter, ElementID, CmdLen, pCmdBuffer); ++ ++ return H2C_SUCCESS; ++} ++/* ++#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) ++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period) ++{ ++ u8 res=_SUCCESS; ++ struct H2C_SS_RFOFF_PARAM param; ++ DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll); ++ param.gpio_period = period;//Polling GPIO_11 period time ++ param.ROFOn = (_TRUE == bfwpoll)?1:0; ++ FillH2CCmd_88E(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(¶m)); ++ return res; ++} ++#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED ++*/ ++u8 rtl8188e_set_rssi_cmd(_adapter*padapter, u8 *param) ++{ ++ u8 res=_SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++_func_enter_; ++ ++ if(pHalData->fw_ractrl == _TRUE){ ++ #if 0 ++ *((u32*) param ) = cpu_to_le32( *((u32*) param ) ); ++ ++ FillH2CCmd_88E(padapter, RSSI_SETTING_EID, 3, param); ++ #endif ++ }else{ ++ DBG_8192C("==>%s fw dont support RA \n",__FUNCTION__); ++ res=_FAIL; ++ } ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtl8188e_set_raid_cmd(_adapter*padapter, u32 mask) ++{ ++ u8 buf[3]; ++ u8 res=_SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++_func_enter_; ++ if(pHalData->fw_ractrl == _TRUE){ ++ _rtw_memset(buf, 0, 3); ++ mask = cpu_to_le32( mask ); ++ _rtw_memcpy(buf, &mask, 3); ++ ++ FillH2CCmd_88E(padapter, H2C_DM_MACID_CFG, 3, buf); ++ }else{ ++ DBG_8192C("==>%s fw dont support RA \n",__FUNCTION__); ++ res=_FAIL; ++ } ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++//bitmap[0:27] = tx_rate_bitmap ++//bitmap[28:31]= Rate Adaptive id ++//arg[0:4] = macid ++//arg[5] = Short GI ++void rtl8188e_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ //struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ u8 macid, init_rate, raid, shortGIrate=_FALSE; ++ ++ macid = arg&0x1f; ++ ++#ifdef CONFIG_ODM_REFRESH_RAMASK ++ raid = (bitmap>>28) & 0x0f; ++ bitmap &=0x0fffffff; ++ ++ if(rssi_level != DM_RATR_STA_INIT) ++ bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level); ++ ++ bitmap |= ((raid<<28)&0xf0000000); ++#endif //CONFIG_ODM_REFRESH_RAMASK ++ ++ ++ init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; ++ ++ shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE; ++ ++ if (shortGIrate==_TRUE) ++ init_rate |= BIT(6); ++ ++ ++ //rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); ++ ++ raid = (bitmap>>28) & 0x0f; ++ ++ bitmap &= 0x0fffffff; ++ ++ DBG_871X("%s=> mac_id:%d , raid:%d , ra_bitmap=0x%x, shortGIrate=0x%02x\n", ++ __FUNCTION__,macid ,raid ,bitmap, shortGIrate); ++ ++ ++#if(RATE_ADAPTIVE_SUPPORT == 1) ++ ODM_RA_UpdateRateInfo_8188E( ++ &(pHalData->odmpriv), ++ macid, ++ raid, ++ bitmap, ++ shortGIrate ++ ); ++#endif ++ ++} ++ ++void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode) ++{ ++ SETPWRMODE_PARM H2CSetPwrMode; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ u8 RLBM = 0; // 0:Min, 1:Max , 2:User define ++_func_enter_; ++ ++ DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __FUNCTION__, ++ Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable); ++ ++ H2CSetPwrMode.AwakeInterval = 2; //DTIM =1 ++ ++ switch(Mode) ++ { ++ case PS_MODE_ACTIVE: ++ H2CSetPwrMode.Mode = 0; ++ break; ++ case PS_MODE_MIN: ++ H2CSetPwrMode.Mode = 1; ++ break; ++ case PS_MODE_MAX: ++ RLBM = 1; ++ H2CSetPwrMode.Mode = 1; ++ break; ++ case PS_MODE_DTIM: ++ RLBM = 2; ++ H2CSetPwrMode.Mode = 1; ++ break; ++ case PS_MODE_UAPSD_WMM: ++ H2CSetPwrMode.Mode = 2; ++ break; ++ default: ++ H2CSetPwrMode.Mode = 0; ++ break; ++ } ++ ++ //H2CSetPwrMode.Mode = Mode; ++ ++ H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f)); ++ ++ H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable; ++ ++ if(Mode > 0) ++ { ++ H2CSetPwrMode.PwrState = 0x00;// AllON(0x0C), RFON(0x04), RFOFF(0x00) ++#ifdef CONFIG_EXT_CLK ++ H2CSetPwrMode.Mode |= BIT(7);//supporting 26M XTAL CLK_Request feature. ++#endif //CONFIG_EXT_CLK ++ } ++ else ++ H2CSetPwrMode.PwrState = 0x0C;// AllON(0x0C), RFON(0x04), RFOFF(0x00) ++ ++ FillH2CCmd_88E(padapter, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); ++ ++ ++_func_exit_; ++} ++ ++void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt ) ++{ ++ u8 opmode,macid; ++ u16 mst_rpt = cpu_to_le16 (mstatus_rpt); ++ u32 reg_macid_no_link = REG_MACID_NO_LINK_0; ++ opmode = (u8) mst_rpt; ++ macid = (u8)(mst_rpt >> 8) ; ++ DBG_871X("### %s: MStatus=%x MACID=%d \n", __FUNCTION__,opmode,macid); ++ FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt); ++ ++ if(macid > 31){ ++ macid = macid-32; ++ reg_macid_no_link = REG_MACID_NO_LINK_1; ++ } ++ ++ //Delete select macid (MACID 0~63) from queue list. ++ if(opmode == 1)// 1:connect ++ { ++ rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid)))); ++ } ++ else//0: disconnect ++ { ++ rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link)|BIT(macid))); ++ } ++ ++ ++ ++} ++ ++void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 rate_len, pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pktlen += 2; ++ ++ // capability info: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pktlen += 2; ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //DBG_871X("ie len=%d\n", cur_network->IELength); ++ pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); ++ _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen); ++ ++ goto _ConstructBeacon; ++ } ++ ++ //below for ad-hoc mode ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); ++ } ++ ++ ++ //todo: ERP IE ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++_ConstructBeacon: ++ ++ if ((pktlen + TXDESC_SIZE) > 512) ++ { ++ DBG_871X("beacon frame too large\n"); ++ return; ++ } ++ ++ *pLength = pktlen; ++ ++ //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); ++ ++} ++ ++void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ // Frame control. ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ SetPwrMgt(fctrl); ++ SetFrameSubType(pframe, WIFI_PSPOLL); ++ ++ // AID. ++ SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); ++ ++ // BSSID. ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ // TA. ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ *pLength = 16; ++} ++ ++void ConstructNullFunctionData( ++ PADAPTER padapter, ++ u8 *pframe, ++ u32 *pLength, ++ u8 *StaAddr, ++ u8 bQoS, ++ u8 AC, ++ u8 bEosp, ++ u8 bForcePowerSave) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 pktlen; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &pmlmepriv->cur_network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; ++ ++ fctrl = &pwlanhdr->frame_ctl; ++ *(fctrl) = 0; ++ if (bForcePowerSave) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ switch(cur_network->network.InfrastructureMode) ++ { ++ case Ndis802_11Infrastructure: ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); ++ break; ++ case Ndis802_11APMode: ++ SetFrDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ break; ++ case Ndis802_11IBSS: ++ default: ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ break; ++ } ++ ++ SetSeqNum(pwlanhdr, 0); ++ ++ if (bQoS == _TRUE) { ++ struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; ++ ++ SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); ++ ++ pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos*)pframe; ++ SetPriority(&pwlanqoshdr->qc, AC); ++ SetEOSP(&pwlanqoshdr->qc, bEosp); ++ ++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); ++ } else { ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ } ++ ++ *pLength = pktlen; ++} ++ ++void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u8 *mac, *bssid; ++ u32 pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ bssid = cur_network->MacAddress; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0); ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pframe += pktlen; ++ ++ if(cur_network->IELength>MAX_IE_SZ) ++ return; ++ ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pktlen += cur_network->IELength; ++ ++ *pLength = pktlen; ++} ++ ++#ifdef CONFIG_WOWLAN ++// ++// Description: ++// Construct the ARP response packet to support ARP offload. ++// ++static void ConstructARPResponse( ++ PADAPTER padapter, ++ u8 *pframe, ++ u32 *pLength, ++ u8 *pIPAddress ++ ) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &pmlmepriv->cur_network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ static u8 ARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06}; ++ ++ u16 *fctrl; ++ u32 pktlen; ++ u8 *pARPRspPkt = pframe; ++ //for TKIP Cal MIC ++ u8 *payload = pframe; ++ u8 EncryptionHeadOverhead = 0; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; ++ ++ fctrl = &pwlanhdr->frame_ctl; ++ *(fctrl) = 0; ++ ++ //------------------------------------------------------------------------- ++ // MAC Header. ++ //------------------------------------------------------------------------- ++ SetFrameType(fctrl, WIFI_DATA); ++ //SetFrameSubType(fctrl, 0); ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0); ++ SetDuration(pwlanhdr, 0); ++ //SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); ++ //SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); ++ //SET_80211_HDR_TO_DS(pARPRspPkt, 1); ++ //SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); ++ //SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); ++ //SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); ++ ++ //SET_80211_HDR_DURATION(pARPRspPkt, 0); ++ //SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); ++ *pLength = 24; ++ ++//YJ,del,120503 ++#if 0 ++ //------------------------------------------------------------------------- ++ // Qos Header: leave space for it if necessary. ++ //------------------------------------------------------------------------- ++ if(pStaQos->CurrentQosMode > QOS_DISABLE) ++ { ++ SET_80211_HDR_QOS_EN(pARPRspPkt, 1); ++ PlatformZeroMemory(&(Buffer[*pLength]), sQoSCtlLng); ++ *pLength += sQoSCtlLng; ++ } ++#endif ++ //------------------------------------------------------------------------- ++ // Security Header: leave space for it if necessary. ++ //------------------------------------------------------------------------- ++ ++ switch (psecuritypriv->dot11PrivacyAlgrthm) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ EncryptionHeadOverhead = 4; ++ break; ++ case _TKIP_: ++ EncryptionHeadOverhead = 8; ++ break; ++ case _AES_: ++ EncryptionHeadOverhead = 8; ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ EncryptionHeadOverhead = 18; ++ break; ++#endif ++ default: ++ EncryptionHeadOverhead = 0; ++ } ++ ++ if(EncryptionHeadOverhead > 0) ++ { ++ _rtw_memset(&(pframe[*pLength]), 0,EncryptionHeadOverhead); ++ *pLength += EncryptionHeadOverhead; ++ //SET_80211_HDR_WEP(pARPRspPkt, 1); //Suggested by CCW. ++ SetPrivacy(fctrl); ++ } ++ ++ //------------------------------------------------------------------------- ++ // Frame Body. ++ //------------------------------------------------------------------------- ++ pARPRspPkt = (u8*)(pframe+ *pLength); ++ // LLC header ++ _rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8); ++ *pLength += 8; ++ ++ // ARP element ++ pARPRspPkt += 8; ++ SET_ARP_PKT_HW(pARPRspPkt, 0x0100); ++ SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); // IP protocol ++ SET_ARP_PKT_HW_ADDR_LEN(pARPRspPkt, 6); ++ SET_ARP_PKT_PROTOCOL_ADDR_LEN(pARPRspPkt, 4); ++ SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); // ARP response ++ SET_ARP_PKT_SENDER_MAC_ADDR(pARPRspPkt, myid(&(padapter->eeprompriv))); ++ SET_ARP_PKT_SENDER_IP_ADDR(pARPRspPkt, pIPAddress); ++#ifdef CONFIG_ARP_KEEP_ALIVE ++ if (rtw_gw_addr_query(padapter)==0) { ++ SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr); ++ SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip); ++ } ++ else ++#endif ++ { ++ SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt, get_my_bssid(&(pmlmeinfo->network))); ++ SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt, pIPAddress); ++ DBG_871X("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); ++ DBG_871X("%s Target IP Addr" IP_FMT "\n", __FUNCTION__, IP_ARG(pIPAddress)); ++ } ++ *pLength += 28; ++ if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ++ { ++ u8 mic[8]; ++ struct mic_data micdata; ++ struct sta_info *psta = NULL; ++ u8 priority[4]={0x0,0x0,0x0,0x0}; ++ u8 null_key[16]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; ++ ++ DBG_871X("%s(): Add MIC\n",__FUNCTION__); ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network))); ++ if (psta != NULL) { ++ if(_rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],null_key, 16)==_TRUE){ ++ DBG_871X("%s(): STA dot11tkiptxmickey==0\n",__FUNCTION__); ++ } ++ //start to calculate the mic code ++ rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]); ++ } ++ ++ rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); //DA ++ ++ rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); //SA ++ ++ priority[0]=0; ++ rtw_secmicappend(&micdata, &priority[0], 4); ++ ++ rtw_secmicappend(&micdata, payload, 36); //payload length = 8 + 28 ++ ++ rtw_secgetmic(&micdata,&(mic[0])); ++ ++ pARPRspPkt += 28; ++ _rtw_memcpy(pARPRspPkt, &(mic[0]),8); ++ ++ *pLength += 8; ++ } ++} ++#endif ++ ++void rtl8188e_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) ++{ ++ u8 u1H2CRsvdPageParm[H2C_8188E_RSVDPAGE_LOC_LEN]={0}; ++ u8 u1H2CAoacRsvdPageParm[H2C_8188E_AOAC_RSVDPAGE_LOC_LEN]={0}; ++ ++ //DBG_871X("8188RsvdPageLoc: PsPoll=%d Null=%d QoSNull=%d\n", ++ // rsvdpageloc->LocPsPoll, rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull); ++ ++ SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll); ++ SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData); ++ SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull); ++ ++ FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, H2C_8188E_RSVDPAGE_LOC_LEN, u1H2CRsvdPageParm); ++ ++#ifdef CONFIG_WOWLAN ++ //DBG_871X("8188E_AOACRsvdPageLoc: RWC=%d ArpRsp=%d\n", rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp); ++ SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo); ++ SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp); ++ ++ FillH2CCmd_88E(padapter, H2C_COM_AOAC_RSVD_PAGE, H2C_8188E_AOAC_RSVDPAGE_LOC_LEN, u1H2CAoacRsvdPageParm); ++#endif ++} ++ ++// To check if reserved page content is destroyed by beacon beacuse beacon is too large. ++// 2010.06.23. Added by tynli. ++VOID ++CheckFwRsvdPageContent( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); ++ u32 MaxBcnPageNum; ++ ++ if(pHalData->FwRsvdPageStartOffset != 0) ++ { ++ /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize); ++ RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset), ++ ("CheckFwRsvdPageContent(): The reserved page content has been"\ ++ "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!", ++ MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/ ++ } ++} ++ ++// ++// Description: Fill the reserved packets that FW will use to RSVD page. ++// Now we just send 4 types packet to rsvd page. ++// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. ++// Input: ++// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, ++// so we need to set the packet length to total lengh. ++// TRUE: At the second time, we should send the first packet (default:beacon) ++// to Hw again and set the lengh in descriptor to the real beacon lengh. ++// 2009.10.15 by tynli. ++static void SetFwRsvdPagePkt(PADAPTER padapter, BOOLEAN bDLFinished) ++{ ++ PHAL_DATA_TYPE pHalData; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv; ++ struct mlme_ext_priv *pmlmeext; ++ struct mlme_ext_info *pmlmeinfo; ++ u32 BeaconLength, ProbeRspLength, PSPollLength; ++ u32 NullDataLength, QosNullLength, BTQosNullLength; ++ u8 *ReservedPagePacket; ++ u8 PageNum, PageNeed, TxDescLen; ++ u16 BufIndex; ++ u32 TotalPacketLen; ++ RSVDPAGE_LOC RsvdPageLoc; ++#ifdef CONFIG_WOWLAN ++ u32 ARPLegnth = 0; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ u8 currentip[4]; ++ u8 cur_dot11txpn[8]; ++#endif ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ReservedPagePacket = (u8*)rtw_zmalloc(RTL88E_RSVDPAGE_SIZE); ++ if (ReservedPagePacket == NULL) { ++ DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); ++ return; ++ } ++ ++ pHalData = GET_HAL_DATA(padapter); ++ pxmitpriv = &padapter->xmitpriv; ++ pmlmeext = &padapter->mlmeextpriv; ++ pmlmeinfo = &pmlmeext->mlmext_info; ++ ++ TxDescLen = TXDESC_SIZE; ++ PageNum = 0; ++ ++ //3 (1) beacon * 2 pages ++ BufIndex = TXDESC_OFFSET; ++ ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength); ++ ++ // When we count the first page size, we need to reserve description size for the RSVD ++ // packet, it will be filled in front of the packet in TXPKTBUF. ++ PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); ++ // To reserved 2 pages for beacon buffer. 2010.06.24. ++ if (PageNeed == 1) ++ PageNeed += 1; ++ PageNum += PageNeed; ++ pHalData->FwRsvdPageStartOffset = PageNum; ++ ++ BufIndex += PageNeed*128; ++ ++ //3 (2) ps-poll *1 page ++ RsvdPageLoc.LocPsPoll = PageNum; ++ ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength); ++ rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE); ++ ++ PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength); ++ PageNum += PageNeed; ++ ++ BufIndex += PageNeed*128; ++ ++ //3 (3) null data * 1 page ++ RsvdPageLoc.LocNullData = PageNum; ++ ConstructNullFunctionData( ++ padapter, ++ &ReservedPagePacket[BufIndex], ++ &NullDataLength, ++ get_my_bssid(&pmlmeinfo->network), ++ _FALSE, 0, 0, _FALSE); ++ rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE); ++ ++ PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength); ++ PageNum += PageNeed; ++ ++ BufIndex += PageNeed*128; ++ ++ //3 (5) Qos null data ++ RsvdPageLoc.LocQosNull = PageNum; ++ ConstructNullFunctionData( ++ padapter, ++ &ReservedPagePacket[BufIndex], ++ &QosNullLength, ++ get_my_bssid(&pmlmeinfo->network), ++ _TRUE, 0, 0, _FALSE); ++ rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE); ++ ++ PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength); ++ PageNum += PageNeed; ++ ++ BufIndex += PageNeed*128; ++ ++#ifdef CONFIG_WOWLAN ++ //3(7) ARP ++ rtw_get_current_ip_address(padapter, currentip); ++ RsvdPageLoc.LocArpRsp = PageNum; ++ ConstructARPResponse( ++ padapter, ++ &ReservedPagePacket[BufIndex], ++ &ARPLegnth, ++ currentip ++ ); ++ rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ARPLegnth, _FALSE, _FALSE); ++ ++ switch (psecuritypriv->dot11PrivacyAlgrthm) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ ReservedPagePacket[BufIndex-TxDescLen+6] |= BIT(6); ++ break; ++ case _AES_: ++ ReservedPagePacket[BufIndex-TxDescLen+6] |= BIT(6)|BIT(7); ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ ReservedPagePacket[BufIndex-TxDescLen+6] |= BIT(7); ++ break; ++#endif ++ default: ++ ; ++ } ++ ++ PageNeed = (u8)PageNum_128(TxDescLen + ARPLegnth); ++ PageNum += PageNeed; ++ ++ BufIndex += PageNeed*128; ++ ++ //3(8) sec IV ++ rtw_get_sec_iv(padapter, cur_dot11txpn, get_my_bssid(&pmlmeinfo->network)); ++ RsvdPageLoc.LocRemoteCtrlInfo = PageNum; ++ _rtw_memcpy(ReservedPagePacket+BufIndex-TxDescLen, cur_dot11txpn, 8); ++ ++ TotalPacketLen = BufIndex-TxDescLen + sizeof (union pn48); //IV len ++#else ++ TotalPacketLen = BufIndex + QosNullLength; ++#endif ++ ++ pmgntframe = alloc_mgtxmitframe(pxmitpriv); ++ if (pmgntframe == NULL) ++ goto exit; ++ ++ // update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->qsel = 0x10; ++ pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET; ++ ++ if (TotalPacketLen < RTL88E_RSVDPAGE_SIZE) ++ _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); ++ else ++ DBG_871X("%s: memory copy fail at Line: %d\n", __FUNCTION__, __LINE__); ++ ++ rtw_hal_mgnt_xmit(padapter, pmgntframe); ++ ++ DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__); ++ rtl8188e_set_FwRsvdPage_cmd(padapter, &RsvdPageLoc); ++ //FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); ++ ++exit: ++ rtw_mfree(ReservedPagePacket, RTL88E_RSVDPAGE_SIZE); ++} ++ ++void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus) ++{ ++ JOINBSSRPT_PARM JoinBssRptParm; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++#ifdef CONFIG_WOWLAN ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct sta_info *psta = NULL; ++#endif ++ BOOLEAN bSendBeacon=_FALSE; ++ BOOLEAN bcn_valid = _FALSE; ++ u8 DLBcnCount=0; ++ u32 poll = 0; ++ ++_func_enter_; ++ ++ DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus); ++ ++ if(mstatus == 1) ++ { ++ // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. ++ // Suggested by filen. Added by tynli. ++ rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid)); ++ // Do not set TSF again here or vWiFi beacon DMA INT will not work. ++ //correct_TSF(padapter, pmlmeext); ++ // Hw sequende enable by dedault. 2010.06.23. by tynli. ++ //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); ++ //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); ++ ++ //Set REG_CR bit 8. DMA beacon by SW. ++ pHalData->RegCR_1 |= BIT0; ++ rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1); ++ ++ // Disable Hw protection for a time which revserd for Hw sending beacon. ++ // Fix download reserved page packet fail that access collision with the protection time. ++ // 2010.05.11. Added by tynli. ++ //SetBcnCtrlReg(padapter, 0, BIT3); ++ //SetBcnCtrlReg(padapter, BIT4, 0); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3))); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)); ++ ++ if(pHalData->RegFwHwTxQCtrl&BIT6) ++ { ++ DBG_871X("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n"); ++ bSendBeacon = _TRUE; ++ } ++ ++ // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6))); ++ pHalData->RegFwHwTxQCtrl &= (~BIT6); ++ ++ // Clear beacon valid check bit. ++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); ++ DLBcnCount = 0; ++ poll = 0; ++ do ++ { ++ // download rsvd page. ++ SetFwRsvdPagePkt(padapter, _FALSE); ++ DLBcnCount++; ++ do ++ { ++ rtw_yield_os(); ++ //rtw_mdelay_os(10); ++ // check rsvd page download OK. ++ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid)); ++ poll++; ++ } while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ ++ }while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ ++ //RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n")); ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped) ++ { ++ } ++ else if(!bcn_valid) ++ DBG_871X("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll); ++ else ++ DBG_871X("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll); ++ // ++ // We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) ++ // becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. ++ // At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return ++ // the beacon TCB in the following code. 2011.11.23. by tynli. ++ // ++ //if(bcn_valid && padapter->bEnterPnpSleep) ++ if(0) ++ { ++ if(bSendBeacon) ++ { ++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); ++ DLBcnCount = 0; ++ poll = 0; ++ do ++ { ++ SetFwRsvdPagePkt(padapter, _TRUE); ++ DLBcnCount++; ++ ++ do ++ { ++ rtw_yield_os(); ++ //rtw_mdelay_os(10); ++ // check rsvd page download OK. ++ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid)); ++ poll++; ++ } while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ }while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); ++ ++ //RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n")); ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped) ++ { ++ } ++ else if(!bcn_valid) ++ DBG_871X("%s: 2 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll); ++ else ++ DBG_871X("%s: 2 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll); ++ } ++ } ++ ++ // Enable Bcn ++ //SetBcnCtrlReg(padapter, BIT3, 0); ++ //SetBcnCtrlReg(padapter, 0, BIT4); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3)); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ // To make sure that if there exists an adapter which would like to send beacon. ++ // If exists, the origianl value of 0x422[6] will be 1, we should check this to ++ // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause ++ // the beacon cannot be sent by HW. ++ // 2010.06.23. Added by tynli. ++ if(bSendBeacon) ++ { ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6)); ++ pHalData->RegFwHwTxQCtrl |= BIT6; ++ } ++ ++ // ++ // Update RSVD page location H2C to Fw. ++ // ++ if(bcn_valid) ++ { ++ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); ++ DBG_871X("Set RSVD page location to Fw.\n"); ++ //FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc); ++ } ++ ++ // Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. ++ //if(!padapter->bEnterPnpSleep) ++ { ++ // Clear CR[8] or beacon packet will not be send to TxBuf anymore. ++ pHalData->RegCR_1 &= (~BIT0); ++ rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1); ++ } ++ } ++#ifdef CONFIG_WOWLAN ++ if (adapter_to_pwrctl(padapter)->wowlan_mode){ ++ JoinBssRptParm.OpMode = mstatus; ++ psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv)); ++ if (psta != NULL) { ++ JoinBssRptParm.MacID = psta->mac_id; ++ } else { ++ JoinBssRptParm.MacID = 0; ++ } ++ FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm); ++ DBG_871X_LEVEL(_drv_info_, "%s opmode:%d MacId:%d\n", __func__, JoinBssRptParm.OpMode, JoinBssRptParm.MacID); ++ } else { ++ DBG_871X_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__); ++ } ++#endif //CONFIG_WOWLAN ++_func_exit_; ++} ++ ++#ifdef CONFIG_P2P_PS ++void rtl8188e_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload; ++ u8 i; ++ ++_func_enter_; ++ ++#if 1 ++ switch(p2p_ps_state) ++ { ++ case P2P_PS_DISABLE: ++ DBG_8192C("P2P_PS_DISABLE \n"); ++ _rtw_memset(p2p_ps_offload, 0 ,1); ++ break; ++ case P2P_PS_ENABLE: ++ DBG_8192C("P2P_PS_ENABLE \n"); ++ // update CTWindow value. ++ if( pwdinfo->ctwindow > 0 ) ++ { ++ p2p_ps_offload->CTWindow_En = 1; ++ rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow); ++ } ++ ++ // hw only support 2 set of NoA ++ for( i=0 ; inoa_num ; i++) ++ { ++ // To control the register setting for which NOA ++ rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4)); ++ if(i == 0) ++ p2p_ps_offload->NoA0_En = 1; ++ else ++ p2p_ps_offload->NoA1_En = 1; ++ ++ // config P2P NoA Descriptor Register ++ //DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); ++ rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); ++ ++ //DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); ++ rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); ++ ++ //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); ++ rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); ++ ++ //DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); ++ rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); ++ } ++ ++ if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) ) ++ { ++ // rst p2p circuit ++ rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4)); ++ ++ p2p_ps_offload->Offload_En = 1; ++ ++ if(pwdinfo->role == P2P_ROLE_GO) ++ { ++ p2p_ps_offload->role= 1; ++ p2p_ps_offload->AllStaSleep = 0; ++ } ++ else ++ { ++ p2p_ps_offload->role= 0; ++ } ++ ++ p2p_ps_offload->discovery = 0; ++ } ++ break; ++ case P2P_PS_SCAN: ++ DBG_8192C("P2P_PS_SCAN \n"); ++ p2p_ps_offload->discovery = 1; ++ break; ++ case P2P_PS_SCAN_DONE: ++ DBG_8192C("P2P_PS_SCAN_DONE \n"); ++ p2p_ps_offload->discovery = 0; ++ pwdinfo->p2p_ps_state = P2P_PS_ENABLE; ++ break; ++ default: ++ break; ++ } ++ ++ FillH2CCmd_88E(padapter, H2C_PS_P2P_OFFLOAD, 1, (u8 *)p2p_ps_offload); ++#endif ++ ++_func_exit_; ++ ++} ++#endif //CONFIG_P2P_PS ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++/* ++ ask FW to Reset sync register at Beacon early interrupt ++*/ ++u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port ) ++{ ++ u8 buf[2]; ++ u8 res=_SUCCESS; ++ ++ s32 ret; ++_func_enter_; ++ if (IFACE_PORT0==reset_port) { ++ buf[0] = 0x1; buf[1] = 0; ++ } else{ ++ buf[0] = 0x0; buf[1] = 0x1; ++ } ++ ++ ret = FillH2CCmd_88E(padapter, H2C_RESET_TSF, 2, buf); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++int reset_tsf(PADAPTER Adapter, u8 reset_port ) ++{ ++ u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; ++ u32 reg_reset_tsf_cnt = (IFACE_PORT0==reset_port) ? ++ REG_FW_RESET_TSF_CNT_0:REG_FW_RESET_TSF_CNT_1; ++ u32 reg_bcncrtl = (IFACE_PORT0==reset_port) ? ++ REG_BCN_CTRL_1:REG_BCN_CTRL; ++ ++ rtw_scan_abort(Adapter->pbuddy_adapter); /* site survey will cause reset_tsf fail */ ++ reset_cnt_after = reset_cnt_before = rtw_read8(Adapter,reg_reset_tsf_cnt); ++ rtl8188e_reset_tsf(Adapter, reset_port); ++ ++ while ((reset_cnt_after == reset_cnt_before ) && (loop_cnt < 10)) { ++ rtw_msleep_os(100); ++ loop_cnt++; ++ reset_cnt_after = rtw_read8(Adapter, reg_reset_tsf_cnt); ++ } ++ ++ return(loop_cnt >= 10) ? _FAIL : _TRUE; ++} ++ ++ ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ ++#ifdef CONFIG_WOWLAN ++#ifdef CONFIG_GPIO_WAKEUP ++void rtl8188es_set_output_gpio(_adapter* padapter, u8 index, u8 outputval) ++{ ++ if ( index <= 7 ) { ++ /* config GPIO mode */ ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index) ); ++ ++ /* config GPIO Sel */ ++ /* 0: input */ ++ /* 1: output */ ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index)); ++ ++ /* set output value */ ++ if ( outputval ) { ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index)); ++ } else { ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index)); ++ } ++ } else { ++ /* 88C Series: */ ++ /* index: 11~8 transform to 3~0 */ ++ /* 8723 Series: */ ++ /* index: 12~8 transform to 4~0 */ ++ index -= 8; ++ ++ /* config GPIO mode */ ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index) ); ++ ++ /* config GPIO Sel */ ++ /* 0: input */ ++ /* 1: output */ ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index)); ++ ++ /* set output value */ ++ if ( outputval ) { ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index)); ++ } else { ++ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index)); ++ } ++ } ++} ++#endif //CONFIG_GPIO_WAKEUP ++ ++void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable) ++{ ++ u8 res=_SUCCESS; ++ u32 test=0; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ SETWOWLAN_PARM pwowlan_parm; ++ SETAOAC_GLOBAL_INFO paoac_global_info_parm; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct security_priv *psecpriv = &padapter->securitypriv; ++#ifdef CONFIG_GPIO_WAKEUP ++ u8 gpio_wake_pin = 7; ++ u8 gpio_high_active = 0; //default low active ++#endif ++ ++_func_enter_; ++ DBG_871X_LEVEL(_drv_always_, "+%s+\n", __func__); ++ ++ pwowlan_parm.mode =0; ++ pwowlan_parm.gpio_index=0; ++ pwowlan_parm.gpio_duration=0; ++ pwowlan_parm.second_mode =0; ++ pwowlan_parm.reserve=0; ++ ++ if(enable){ ++ ++ pwowlan_parm.mode |=FW_WOWLAN_FUN_EN; ++ pwrpriv->wowlan_magic =_TRUE; ++ if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_) ++ pwrpriv->wowlan_unicast =_TRUE; ++ ++ if(pwrpriv->wowlan_pattern ==_TRUE){ ++ pwowlan_parm.mode |= FW_WOWLAN_PATTERN_MATCH; ++ DBG_871X_LEVEL(_drv_info_, "%s 2.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ if(pwrpriv->wowlan_magic ==_TRUE){ ++ pwowlan_parm.mode |=FW_WOWLAN_MAGIC_PKT; ++ DBG_871X_LEVEL(_drv_info_, "%s 3.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ if(pwrpriv->wowlan_unicast ==_TRUE){ ++ pwowlan_parm.mode |=FW_WOWLAN_UNICAST; ++ DBG_871X_LEVEL(_drv_info_, "%s 4.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ ++ pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP; ++ pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP; ++ ++ //DataPinWakeUp ++#ifdef CONFIG_USB_HCI ++ pwowlan_parm.gpio_index=0x0; ++#endif //CONFIG_USB_HCI ++ ++#ifdef CONFIG_SDIO_HCI ++ pwowlan_parm.gpio_index = 0x80; ++#endif //CONFIG_SDIO_HCI ++ ++#ifdef CONFIG_GPIO_WAKEUP ++ pwowlan_parm.gpio_index = gpio_wake_pin; ++ ++ //WOWLAN_GPIO_ACTIVE means GPIO high active ++ //pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; ++ if (gpio_high_active) ++ pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; ++#endif //CONFIG_GPIO_WAKEUP ++ ++ DBG_871X_LEVEL(_drv_info_, "%s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode); ++ DBG_871X_LEVEL(_drv_info_, "%s 6.pwowlan_parm.index=0x%x \n",__FUNCTION__,pwowlan_parm.gpio_index); ++ res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm); ++ ++ rtw_msleep_os(2); ++ ++ //disconnect decision ++ pwowlan_parm.mode =1; ++ pwowlan_parm.gpio_index=0; ++ pwowlan_parm.gpio_duration=0; ++ FillH2CCmd_88E(padapter, H2C_COM_DISCNT_DECISION, 3, (u8 *)&pwowlan_parm); ++ ++ //keep alive period = 10 * 10 BCN interval ++ pwowlan_parm.mode = FW_WOWLAN_KEEP_ALIVE_EN | FW_ADOPT_USER | FW_WOWLAN_KEEP_ALIVE_PKT_TYPE; ++ pwowlan_parm.gpio_index=10; ++ res = FillH2CCmd_88E(padapter, H2C_COM_KEEP_ALIVE, 2, (u8 *)&pwowlan_parm); ++ ++ rtw_msleep_os(2); ++ //Configure STA security information for GTK rekey wakeup event. ++ paoac_global_info_parm.pairwiseEncAlg= ++ padapter->securitypriv.dot11PrivacyAlgrthm; ++ paoac_global_info_parm.groupEncAlg= ++ padapter->securitypriv.dot118021XGrpPrivacy; ++ res = FillH2CCmd_88E(padapter, H2C_COM_AOAC_GLOBAL_INFO, 2, (u8 *)&paoac_global_info_parm); ++ ++ rtw_msleep_os(2); ++ //enable Remote wake ctrl ++ pwowlan_parm.mode = FW_REMOTE_WAKE_CTRL_EN | FW_WOW_FW_UNICAST_EN | FW_ARP_EN; ++ if (psecpriv->dot11PrivacyAlgrthm == _AES_ || psecpriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) ++ { ++ pwowlan_parm.gpio_index=0; ++ } else { ++ pwowlan_parm.gpio_index=1; ++ } ++ pwowlan_parm.gpio_duration=0; ++ ++ res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm); ++ } else { ++ pwrpriv->wowlan_magic =_FALSE; ++#ifdef CONFIG_GPIO_WAKEUP ++ rtl8188es_set_output_gpio(padapter, gpio_wake_pin, !gpio_high_active); ++#endif //CONFIG_GPIO_WAKEUP ++ res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm); ++ rtw_msleep_os(2); ++ res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm); ++ } ++_func_exit_; ++ DBG_871X_LEVEL(_drv_always_, "-%s res:%d-\n", __func__, res); ++ return ; ++} ++#endif //CONFIG_WOWLAN +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_dm.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_dm.c +new file mode 100644 +index 00000000..55cfff96 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_dm.c +@@ -0,0 +1,650 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++#define _RTL8188E_DM_C_ ++ ++//============================================================ ++// include files ++//============================================================ ++#include ++#include ++#include ++#include ++ ++#include ++ ++//============================================================ ++// Global var ++//============================================================ ++ ++ ++static VOID ++dm_CheckProtection( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u1Byte CurRate, RateThreshold; ++ ++ if(pMgntInfo->pHTInfo->bCurBW40MHz) ++ RateThreshold = MGN_MCS1; ++ else ++ RateThreshold = MGN_MCS3; ++ ++ if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold) ++ { ++ pMgntInfo->bDmDisableProtect = TRUE; ++ DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); ++ } ++ else ++ { ++ pMgntInfo->bDmDisableProtect = FALSE; ++ DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); ++ } ++#endif ++} ++ ++static VOID ++dm_CheckStatistics( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ if(!Adapter->MgntInfo.bMediaConnect) ++ return; ++ ++ //2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly. ++ rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) ); ++ ++ // Calculate current Tx Rate(Successful transmited!!) ++ ++ // Calculate current Rx Rate(Successful received!!) ++ ++ //for tx tx retry count ++ rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) ); ++#endif ++} ++ ++static void dm_CheckPbcGPIO(_adapter *padapter) ++{ ++ u8 tmp1byte; ++ u8 bPbcPressed = _FALSE; ++ ++ if(!padapter->registrypriv.hw_wps_pbc) ++ return; ++ ++#ifdef CONFIG_USB_HCI ++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); ++ tmp1byte |= (HAL_8188E_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode ++ ++ tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level ++ ++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); ++ tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode ++ ++ tmp1byte =rtw_read8(padapter, GPIO_IN); ++ ++ if (tmp1byte == 0xff) ++ return ; ++ ++ if (tmp1byte&HAL_8188E_HW_GPIO_WPS_BIT) ++ { ++ bPbcPressed = _TRUE; ++ } ++#else ++ tmp1byte = rtw_read8(padapter, GPIO_IN); ++ //RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte)); ++ ++ if (tmp1byte == 0xff || padapter->init_adpt_in_progress) ++ return ; ++ ++ if((tmp1byte&HAL_8188E_HW_GPIO_WPS_BIT)==0) ++ { ++ bPbcPressed = _TRUE; ++ } ++#endif ++ ++ if( _TRUE == bPbcPressed) ++ { ++ // Here we only set bPbcPressed to true ++ // After trigger PBC, the variable will be set to false ++ DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); ++ ++#ifdef RTK_DMP_PLATFORM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC); ++#endif ++#else ++ ++ if ( padapter->pid[0] == 0 ) ++ { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. ++ return; ++ } ++ ++#ifdef PLATFORM_LINUX ++ rtw_signal_process(padapter->pid[0], SIGUSR1); ++#endif ++#endif ++ } ++} ++ ++#ifdef CONFIG_PCI_HCI ++// ++// Description: ++// Perform interrupt migration dynamically to reduce CPU utilization. ++// ++// Assumption: ++// 1. Do not enable migration under WIFI test. ++// ++// Created by Roger, 2010.03.05. ++// ++VOID ++dm_InterruptMigration( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ BOOLEAN bCurrentIntMt, bCurrentACIntDisable; ++ BOOLEAN IntMtToSet = _FALSE; ++ BOOLEAN ACIntToSet = _FALSE; ++ ++ ++ // Retrieve current interrupt migration and Tx four ACs IMR settings first. ++ bCurrentIntMt = pHalData->bInterruptMigration; ++ bCurrentACIntDisable = pHalData->bDisableTxInt; ++ ++ // ++ // Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics ++ // when interrupt migration is set before. 2010.03.05. ++ // ++ if(!Adapter->registrypriv.wifi_spec && ++ (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && ++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) ++ { ++ IntMtToSet = _TRUE; ++ ++ // To check whether we should disable Tx interrupt or not. ++ if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic ) ++ ACIntToSet = _TRUE; ++ } ++ ++ //Update current settings. ++ if( bCurrentIntMt != IntMtToSet ){ ++ DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet); ++ if(IntMtToSet) ++ { ++ // ++ // Set interrrupt migration timer and corresponging Tx/Rx counter. ++ // timer 25ns*0xfa0=100us for 0xf packets. ++ // 2010.03.05. ++ // ++ rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx ++ pHalData->bInterruptMigration = IntMtToSet; ++ } ++ else ++ { ++ // Reset all interrupt migration settings. ++ rtw_write32(Adapter, REG_INT_MIG, 0); ++ pHalData->bInterruptMigration = IntMtToSet; ++ } ++ } ++ ++ /*if( bCurrentACIntDisable != ACIntToSet ){ ++ DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet); ++ if(ACIntToSet) // Disable four ACs interrupts. ++ { ++ // ++ // Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. ++ // When extremely highly Rx OK occurs, we will disable Tx interrupts. ++ // 2010.03.05. ++ // ++ UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS ); ++ pHalData->bDisableTxInt = ACIntToSet; ++ } ++ else// Enable four ACs interrupts. ++ { ++ UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 ); ++ pHalData->bDisableTxInt = ACIntToSet; ++ } ++ }*/ ++ ++} ++ ++#endif ++ ++// ++// Initialize GPIO setting registers ++// ++static void ++dm_InitGPIOSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ ++ u8 tmp1byte; ++ ++ tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG); ++ tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); ++ ++#ifdef CONFIG_BT_COEXIST ++ // UMB-B cut bug. We need to support the modification. ++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) && ++ pHalData->bt_coexist.BT_Coexist) ++ { ++ tmp1byte |= (BIT5); ++ } ++#endif ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); ++ ++} ++ ++//============================================================ ++// functions ++//============================================================ ++static void Init_ODM_ComInfo_88E(PADAPTER Adapter) ++{ ++ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ u8 cut_ver,fab_ver; ++ ++ // ++ // Init Value ++ // ++ _rtw_memset(pDM_Odm,0,sizeof(pDM_Odm)); ++ ++ pDM_Odm->Adapter = Adapter; ++ ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE); ++ ++ if(Adapter->interface_type == RTW_GSPI ) ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO); ++ else ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE ++ ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E); ++ ++ fab_ver = ODM_TSMC; ++ cut_ver = ODM_CUT_A; ++ ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver); ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver); ++ ++ ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID)); ++ ++#if 0 ++//#ifdef CONFIG_USB_HCI ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType); ++ ++ if(pHalData->BoardType == BOARD_USB_High_PA){ ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE); ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE); ++ } ++#endif ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID); ++ // ODM_CMNINFO_BINHCT_TEST only for MP Team ++ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec); ++ ++ ++ if(pHalData->rf_type == RF_1T1R){ ++ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R); ++ } ++ else if(pHalData->rf_type == RF_2T2R){ ++ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R); ++ } ++ else if(pHalData->rf_type == RF_1T2R){ ++ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R); ++ } ++ ++ ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); ++ ++ #ifdef CONFIG_DISABLE_ODM ++ pdmpriv->InitODMFlag = 0; ++ #else ++ pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | ++ ODM_RF_TX_PWR_TRACK //| ++ ; ++ //if(pHalData->AntDivCfg) ++ // pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; ++ #endif ++ ++ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); ++ ++} ++static void Update_ODM_ComInfo_88E(PADAPTER Adapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ int i; ++ ++ pdmpriv->InitODMFlag = 0 ++ | ODM_BB_DIG ++#ifdef CONFIG_ODM_REFRESH_RAMASK ++ | ODM_BB_RA_MASK ++#endif ++ | ODM_BB_DYNAMIC_TXPWR ++ | ODM_BB_FA_CNT ++ | ODM_BB_RSSI_MONITOR ++ | ODM_BB_CCK_PD ++ | ODM_BB_PWR_SAVE ++ | ODM_RF_CALIBRATION ++ | ODM_RF_TX_PWR_TRACK ++#ifdef CONFIG_ODM_ADAPTIVITY ++ | ODM_BB_ADAPTIVITY ++#endif ++ ; ++ ++ if (!Adapter->registrypriv.qos_opt_enable) { ++ pdmpriv->InitODMFlag |= ODM_MAC_EDCA_TURBO; ++ } ++ ++ if(pHalData->AntDivCfg) ++ pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; ++ ++#if (MP_DRIVER==1) ++ if (Adapter->registrypriv.mp_mode == 1) { ++ pdmpriv->InitODMFlag = 0 ++ | ODM_RF_CALIBRATION ++ | ODM_RF_TX_PWR_TRACK ++ ; ++ } ++#endif//(MP_DRIVER==1) ++ ++#ifdef CONFIG_DISABLE_ODM ++ pdmpriv->InitODMFlag = 0; ++#endif//CONFIG_DISABLE_ODM ++ ++ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); ++ ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW )); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode)); ++ ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp)); ++ //================= only for 8192D ================= ++ /* ++ //pHalData->CurrentBandType92D ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp)); ++ //================= only for 8192D ================= ++ // driver havn't those variable now ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp)); ++ */ ++ ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess)); ++ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving)); ++ ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ //pDM_Odm->pODM_StaInfo[i] = NULL; ++ ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL); ++ } ++} ++ ++void ++rtl8188e_InitHalDm( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ u8 i; ++ ++#ifdef CONFIG_USB_HCI ++ dm_InitGPIOSetting(Adapter); ++#endif ++ ++ pdmpriv->DM_Type = DM_Type_ByDriver; ++ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE; ++ ++ Update_ODM_ComInfo_88E(Adapter); ++ ODM_DMInit(pDM_Odm); ++ ++ Adapter->fix_rate = 0xFF; ++ ++} ++ ++ ++VOID ++rtl8188e_HalDmWatchDog( ++ IN PADAPTER Adapter ++ ) ++{ ++ BOOLEAN bFwCurrentInPSMode = _FALSE; ++ BOOLEAN bFwPSAwake = _TRUE; ++ u8 hw_init_completed = _FALSE; ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++#endif //CONFIG_CONCURRENT_MODE ++ ++ _func_enter_; ++ ++ hw_init_completed = Adapter->hw_init_completed; ++ ++ if (hw_init_completed == _FALSE) ++ goto skip_dm; ++ ++#ifdef CONFIG_LPS ++ bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode; ++ rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); ++#endif ++ ++#ifdef CONFIG_P2P_PS ++ // Fw is under p2p powersaving mode, driver should stop dynamic mechanism. ++ // modifed by thomas. 2011.06.11. ++ if(Adapter->wdinfo.p2p_ps_mode) ++ bFwPSAwake = _FALSE; ++#endif //CONFIG_P2P_PS ++ ++ if( (hw_init_completed == _TRUE) ++ && ((!bFwCurrentInPSMode) && bFwPSAwake)) ++ { ++ // ++ // Calculate Tx/Rx statistics. ++ // ++ dm_CheckStatistics(Adapter); ++ ++ // ++ // Dynamically switch RTS/CTS protection. ++ // ++ //dm_CheckProtection(Adapter); ++ ++#ifdef CONFIG_PCI_HCI ++ // 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. ++ // Tx Migration settings. ++ //dm_InterruptMigration(Adapter); ++ ++ //if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) ++ // PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); ++#endif ++ ++ } ++ ++ ++ //ODM ++ if (hw_init_completed == _TRUE) ++ { ++ u8 bLinked=_FALSE; ++ u8 bsta_state = _FALSE; ++ ++ #ifdef CONFIG_DISABLE_ODM ++ pHalData->odmpriv.SupportAbility = 0; ++ #endif ++ ++ if(rtw_linked_check(Adapter)) ++ bLinked = _TRUE; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) ++ bLinked = _TRUE; ++#endif //CONFIG_CONCURRENT_MODE ++ ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked); ++ ++ ++ if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE)) ++ bsta_state = _TRUE; ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_adapter && check_fwstate(&pbuddy_adapter->mlmepriv, WIFI_STATION_STATE)) ++ bsta_state = _TRUE; ++#endif //CONFIG_CONCURRENT_MODE ++ ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_STATION_STATE, bsta_state); ++ ++ ODM_DMWatchdog(&pHalData->odmpriv); ++ ++ } ++ ++skip_dm: ++ ++ // Check GPIO to determine current RF on/off and Pbc status. ++ // Check Hardware Radio ON/OFF or not ++#ifdef CONFIG_PCI_HCI ++ if(pHalData->bGpioHwWpsPbc) ++#endif ++ { ++ //temp removed ++ //dm_CheckPbcGPIO(Adapter); ++ } ++ return; ++} ++ ++void rtl8188e_init_dm_priv(IN PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T podmpriv = &pHalData->odmpriv; ++ _rtw_memset(pdmpriv, 0, sizeof(struct dm_priv)); ++ //_rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); ++ Init_ODM_ComInfo_88E(Adapter); ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter); ++ ODM_InitAllTimers(podmpriv ); ++#endif ++ ODM_InitDebugSetting(podmpriv); ++} ++ ++void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T podmpriv = &pHalData->odmpriv; ++ //_rtw_spinlock_free(&pHalData->odm_stainfo_lock); ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); ++ ODM_CancelAllTimers(podmpriv); ++#endif ++} ++ ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// Add new function to reset the state of antenna diversity before link. ++// ++// Compare RSSI for deciding antenna ++void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src) ++{ ++ //PADAPTER Adapter = pDM_Odm->Adapter ; ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ if(0 != pHalData->AntDivCfg ) ++ { ++ //DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), ++ // src->Rssi,query_rx_pwr_percentage(src->Rssi)); ++ //select optimum_antenna for before linked =>For antenna diversity ++ if(dst->Rssi >= src->Rssi )//keep org parameter ++ { ++ src->Rssi = dst->Rssi; ++ src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; ++ } ++ } ++} ++ ++// Add new function to reset the state of antenna diversity before link. ++u8 AntDivBeforeLink8188E(PADAPTER Adapter ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T pDM_Odm =&pHalData->odmpriv; ++ SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ ++ // Condition that does not need to use antenna diversity. ++ if(pHalData->AntDivCfg==0) ++ { ++ //DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); ++ return _FALSE; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ return _FALSE; ++ } ++ ++ ++ if(pDM_SWAT_Table->SWAS_NoLink_State == 0){ ++ //switch channel ++ pDM_SWAT_Table->SWAS_NoLink_State = 1; ++ pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna); ++ rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE); ++ //DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"); ++ return _TRUE; ++ } ++ else ++ { ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ return _FALSE; ++ } ++ ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_hal_init.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_hal_init.c +new file mode 100644 +index 00000000..1e38e220 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_hal_init.c +@@ -0,0 +1,3800 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HAL_INIT_C_ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#if defined(CONFIG_IOL) ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++static void iol_mode_enable(PADAPTER padapter, u8 enable) ++{ ++ u8 reg_0xf0 = 0; ++ ++ if(enable) ++ { ++ //Enable initial offload ++ reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG); ++ //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0|SW_OFFLOAD_EN); ++ rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN); ++ ++ if(padapter->bFWReady == _FALSE) ++ { ++ printk("bFWReady == _FALSE call reset 8051...\n"); ++ _8051Reset88E(padapter); ++ } ++ ++ } ++ else ++ { ++ //disable initial offload ++ reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG); ++ //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0& ~SW_OFFLOAD_EN); ++ rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN); ++ } ++} ++ ++static s32 iol_execute(PADAPTER padapter, u8 control) ++{ ++ s32 status = _FAIL; ++ u8 reg_0x88 = 0,reg_1c7=0; ++ u32 start = 0, passing_time = 0; ++ ++ u32 t1,t2; ++ control = control&0x0f; ++ reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0); ++ //DBG_871X("%s reg_0x88:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x88, reg_0x88|control); ++ rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control); ++ ++ t1 = start = rtw_get_current_time(); ++ while( ++ //(reg_1c7 = rtw_read8(padapter, 0x1c7) >1) && ++ (reg_0x88=rtw_read8(padapter, REG_HMEBOX_E0)) & control ++ && (passing_time=rtw_get_passing_time_ms(start))<1000 ++ ) { ++ //DBG_871X("%s polling reg_0x88:0x%02x,reg_0x1c7:0x%02x\n", __FUNCTION__, reg_0x88,rtw_read8(padapter, 0x1c7) ); ++ //rtw_udelay_os(100); ++ } ++ ++ reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0); ++ status = (reg_0x88 & control)?_FAIL:_SUCCESS; ++ if(reg_0x88 & control<<4) ++ status = _FAIL; ++ t2= rtw_get_current_time(); ++ //printk("==> step iol_execute : %5u reg-0x1c0= 0x%02x\n",rtw_get_time_interval_ms(t1,t2),rtw_read8(padapter, 0x1c0)); ++ //DBG_871X("%s in %u ms, reg_0x88:0x%02x\n", __FUNCTION__, passing_time, reg_0x88); ++ ++ return status; ++} ++ ++static s32 iol_InitLLTTable( ++ PADAPTER padapter, ++ u8 txpktbuf_bndy ++ ) ++{ ++ s32 rst = _SUCCESS; ++ iol_mode_enable(padapter, 1); ++ //DBG_871X("%s txpktbuf_bndy:%u\n", __FUNCTION__, txpktbuf_bndy); ++ rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); ++ rst = iol_execute(padapter, CMD_INIT_LLT); ++ iol_mode_enable(padapter, 0); ++ return rst; ++} ++ ++static VOID ++efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) ++{ ++ u8 *efuseTbl = NULL; ++ u8 rtemp8; ++ u16 eFuse_Addr = 0; ++ u8 offset, wren; ++ u16 i, j; ++ u16 **eFuseWord = NULL; ++ u16 efuse_utilized = 0; ++ u8 efuse_usage = 0; ++ u8 u1temp = 0; ++ ++ ++ efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E); ++ if(efuseTbl == NULL) ++ { ++ DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); ++ if(eFuseWord == NULL) ++ { ++ DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ // 0. Refresh efuse init map as all oxFF. ++ for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) ++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) ++ eFuseWord[i][j] = 0xFFFF; ++ ++ // ++ // 1. Read the first byte to check if efuse is empty!!! ++ // ++ // ++ rtemp8 = *(phymap+eFuse_Addr); ++ if(rtemp8 != 0xFF) ++ { ++ efuse_utilized++; ++ //printk("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); ++ eFuse_Addr++; ++ } ++ else ++ { ++ DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, rtemp8); ++ goto exit; ++ } ++ ++ ++ // ++ // 2. Read real efuse content. Filter PG header and every section data. ++ // ++ while((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); ++ ++ // Check PG header for section num. ++ if((rtemp8 & 0x1F ) == 0x0F) //extended header ++ { ++ u1temp =( (rtemp8 & 0xE0) >> 5); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); ++ ++ rtemp8 = *(phymap+eFuse_Addr); ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); ++ ++ if((rtemp8 & 0x0F) == 0x0F) ++ { ++ eFuse_Addr++; ++ rtemp8 = *(phymap+eFuse_Addr); ++ ++ if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ eFuse_Addr++; ++ } ++ continue; ++ } ++ else ++ { ++ offset = ((rtemp8 & 0xF0) >> 1) | u1temp; ++ wren = (rtemp8 & 0x0F); ++ eFuse_Addr++; ++ } ++ } ++ else ++ { ++ offset = ((rtemp8 >> 4) & 0x0f); ++ wren = (rtemp8 & 0x0f); ++ } ++ ++ if(offset < EFUSE_MAX_SECTION_88E) ++ { ++ // Get word enable value from PG header ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); ++ ++ for(i=0; i= EFUSE_REAL_CONTENT_LEN_88E) ++ break; ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); ++ rtemp8 = *(phymap+eFuse_Addr); ++ eFuse_Addr++; ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); ++ ++ efuse_utilized++; ++ eFuseWord[offset][i] |= (((u2Byte)rtemp8 << 8) & 0xff00); ++ ++ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) ++ break; ++ } ++ ++ wren >>= 1; ++ ++ } ++ } ++ ++ // Read next PG header ++ rtemp8 = *(phymap+eFuse_Addr); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); ++ ++ if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ efuse_utilized++; ++ eFuse_Addr++; ++ } ++ } ++ ++ // ++ // 3. Collect 16 sections and 4 word unit into Efuse map. ++ // ++ for(i=0; i> 8) & 0xff); ++ } ++ } ++ ++ ++ // ++ // 4. Copy from Efuse map to output pointer memory!!! ++ // ++ for(i=0; i<_size_byte; i++) ++ { ++ pbuf[i] = efuseTbl[_offset+i]; ++ } ++ ++ // ++ // 5. Calculate Efuse utilization. ++ // ++ efuse_usage = (u1Byte)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E); ++ //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized); ++ ++exit: ++ if(efuseTbl) ++ rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E); ++ ++ if(eFuseWord) ++ rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); ++} ++ ++void efuse_read_phymap_from_txpktbuf( ++ ADAPTER *adapter, ++ int bcnhead, //beacon head, where FW store len(2-byte) and efuse physical map. ++ u8 *content, //buffer to store efuse physical map ++ u16 *size //for efuse content: the max byte to read. will update to byte read ++ ) ++{ ++ u16 dbg_addr = 0; ++ u32 start = 0, passing_time = 0; ++ u8 reg_0x143 = 0; ++ u8 reg_0x106 = 0; ++ u32 lo32 = 0, hi32 = 0; ++ u16 len = 0, count = 0; ++ int i = 0; ++ u16 limit = *size; ++ ++ u8 *pos = content; ++ ++ if(bcnhead<0) //if not valid ++ bcnhead = rtw_read8(adapter, REG_TDECTRL+1); ++ ++ DBG_871X("%s bcnhead:%d\n", __FUNCTION__, bcnhead); ++ ++ //reg_0x106 = rtw_read8(adapter, REG_PKT_BUFF_ACCESS_CTRL); ++ //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); ++ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); ++ //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(adapter, 0x106)); ++ ++ dbg_addr = bcnhead*128/8; //8-bytes addressing ++ ++ while(1) ++ { ++ //DBG_871X("%s dbg_addr:0x%x\n", __FUNCTION__, dbg_addr+i); ++ rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i); ++ ++ //DBG_871X("%s write reg_0x143:0x00\n", __FUNCTION__); ++ rtw_write8(adapter, REG_TXPKTBUF_DBG, 0); ++ start = rtw_get_current_time(); ++ while(!(reg_0x143=rtw_read8(adapter, REG_TXPKTBUF_DBG))//dbg ++ //while(rtw_read8(adapter, REG_TXPKTBUF_DBG) & BIT0 ++ && (passing_time=rtw_get_passing_time_ms(start))<1000 ++ ) { ++ DBG_871X("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __FUNCTION__, reg_0x143, rtw_read8(adapter, 0x106)); ++ rtw_usleep_os(100); ++ } ++ ++ ++ lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L); ++ hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H); ++ ++ #if 0 ++ DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, lo32 ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3) ++ ); ++ DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, hi32 ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2) ++ , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3) ++ ); ++ #endif ++ ++ if(i==0) ++ { ++ #if 1 //for debug ++ u8 lenc[2]; ++ u16 lenbak, aaabak; ++ u16 aaa; ++ lenc[0] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L); ++ lenc[1] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1); ++ ++ aaabak = le16_to_cpup((u16*)lenc); ++ lenbak = le16_to_cpu(*((u16*)lenc)); ++ aaa = le16_to_cpup((u16*)&lo32); ++ #endif ++ len = le16_to_cpu(*((u16*)&lo32)); ++ ++ limit = (len-2=count+2)?2:limit-count); ++ count+= (limit>=count+2)?2:limit-count; ++ pos=content+count; ++ ++ } ++ else ++ { ++ _rtw_memcpy(pos, ((u8*)&lo32), (limit>=count+4)?4:limit-count); ++ count+=(limit>=count+4)?4:limit-count; ++ pos=content+count; ++ ++ ++ } ++ ++ if(limit>count && len-2>count) { ++ _rtw_memcpy(pos, (u8*)&hi32, (limit>=count+4)?4:limit-count); ++ count+=(limit>=count+4)?4:limit-count; ++ pos=content+count; ++ } ++ ++ if(limit<=count || len-2<=count) ++ break; ++ ++ i++; ++ } ++ ++ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS); ++ ++ DBG_871X("%s read count:%u\n", __FUNCTION__, count); ++ *size = count; ++ ++} ++ ++ ++static s32 iol_read_efuse( ++ PADAPTER padapter, ++ u8 txpktbuf_bndy, ++ u16 offset, ++ u16 size_byte, ++ u8 *logical_map ++ ) ++{ ++ s32 status = _FAIL; ++ u8 reg_0x106 = 0; ++ u8 physical_map[512]; ++ u16 size = 512; ++ int i; ++ ++ ++ rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); ++ _rtw_memset(physical_map, 0xFF, 512); ++ ++ ///reg_0x106 = rtw_read8(padapter, REG_PKT_BUFF_ACCESS_CTRL); ++ //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); ++ rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); ++ //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(padapter, 0x106)); ++ ++ status = iol_execute(padapter, CMD_READ_EFUSE_MAP); ++ ++ if(status == _SUCCESS) ++ efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size); ++ ++ #if 0 ++ DBG_871X("%s physical map\n", __FUNCTION__); ++ for(i=0;i %s \n",__FUNCTION__); ++ ++ if(rtw_IOL_applied(padapter)){ ++ iol_mode_enable(padapter, 1); ++ result = iol_execute(padapter, CMD_READ_EFUSE_MAP); ++ if(result == _SUCCESS) ++ result = iol_execute(padapter, CMD_EFUSE_PATCH); ++ ++ iol_mode_enable(padapter, 0); ++ } ++ return result; ++} ++ ++static s32 iol_ioconfig( ++ PADAPTER padapter, ++ u8 iocfg_bndy ++ ) ++{ ++ s32 rst = _SUCCESS; ++ ++ //DBG_871X("%s iocfg_bndy:%u\n", __FUNCTION__, iocfg_bndy); ++ rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy); ++ rst = iol_execute(padapter, CMD_IOCONFIG); ++ ++ return rst; ++} ++ ++int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms,u32 bndy_cnt) ++{ ++ ++ u32 start_time = rtw_get_current_time(); ++ u32 passing_time_ms; ++ u8 polling_ret,i; ++ int ret = _FAIL; ++ u32 t1,t2; ++ ++ //printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt); ++ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) ++ goto exit; ++#ifdef CONFIG_USB_HCI ++ { ++ struct pkt_attrib *pattrib = &xmit_frame->attrib; ++ if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz)) ++ { ++ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) ++ goto exit; ++ } ++ } ++#endif //CONFIG_USB_HCI ++ ++ //rtw_IOL_cmd_buf_dump(adapter,xmit_frame->attrib.pktlen+TXDESC_OFFSET,xmit_frame->buf_addr); ++ //rtw_hal_mgnt_xmit(adapter, xmit_frame); ++ //rtw_dump_xframe_sync(adapter, xmit_frame); ++ ++ dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms); ++ ++ t1= rtw_get_current_time(); ++ iol_mode_enable(adapter, 1); ++ for(i=0;i %s : %5u\n",__FUNCTION__,rtw_get_time_interval_ms(t1,t2)); ++exit: ++ //restore BCN_HEAD ++ rtw_write8(adapter, REG_TDECTRL+1, 0); ++ return ret; ++} ++ ++void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter,int data_len) ++{ ++ u32 fifo_data,reg_140; ++ u32 addr,rstatus,loop=0; ++ ++ u16 data_cnts = (data_len/8)+1; ++ u8 *pbuf =rtw_zvmalloc(data_len+10); ++ printk("###### %s ######\n",__FUNCTION__); ++ ++ rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); ++ if(pbuf){ ++ for(addr=0;addr< data_cnts;addr++){ ++ //printk("==> addr:0x%02x\n",addr); ++ rtw_write32(Adapter,0x140,addr); ++ rtw_usleep_os(2); ++ loop=0; ++ do{ ++ rstatus=(reg_140=rtw_read32(Adapter,REG_PKTBUF_DBG_CTRL)&BIT24); ++ //printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140); ++ if(rstatus){ ++ fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_L); ++ //printk("fifo_data_144:0x%08x\n",fifo_data); ++ _rtw_memcpy(pbuf+(addr*8),&fifo_data , 4); ++ ++ fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_H); ++ //printk("fifo_data_148:0x%08x\n",fifo_data); ++ _rtw_memcpy(pbuf+(addr*8+4), &fifo_data, 4); ++ ++ } ++ rtw_usleep_os(2); ++ }while( !rstatus && (loop++ <10)); ++ } ++ rtw_IOL_cmd_buf_dump(Adapter,data_len,pbuf); ++ rtw_vmfree(pbuf, data_len+10); ++ ++ } ++ printk("###### %s ######\n",__FUNCTION__); ++} ++ ++#endif /* defined(CONFIG_IOL) */ ++ ++ ++static VOID ++_FWDownloadEnable( ++ IN PADAPTER padapter, ++ IN BOOLEAN enable ++ ) ++{ ++ u8 tmp; ++ ++ if(enable) ++ { ++ // MCU firmware download enable. ++ tmp = rtw_read8(padapter, REG_MCUFWDL); ++ rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); ++ ++ // 8051 reset ++ tmp = rtw_read8(padapter, REG_MCUFWDL+2); ++ rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); ++ } ++ else ++ { ++ ++ // MCU firmware download disable. ++ tmp = rtw_read8(padapter, REG_MCUFWDL); ++ rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe); ++ ++ // Reserved for fw extension. ++ rtw_write8(padapter, REG_MCUFWDL+1, 0x00); ++ } ++} ++#define MAX_REG_BOLCK_SIZE 196 ++static int ++_BlockWrite( ++ IN PADAPTER padapter, ++ IN PVOID buffer, ++ IN u32 buffSize ++ ) ++{ ++ int ret = _SUCCESS; ++ ++ u32 blockSize_p1 = 4; // (Default) Phase #1 : PCI muse use 4-byte write to download FW ++ u32 blockSize_p2 = 8; // Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. ++ u32 blockSize_p3 = 1; // Phase #3 : Use 1-byte, the remnant of FW image. ++ u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; ++ u32 remainSize_p1 = 0, remainSize_p2 = 0; ++ u8 *bufferPtr = (u8*)buffer; ++ u32 i=0, offset=0; ++#ifdef CONFIG_PCI_HCI ++ u8 remainFW[4] = {0, 0, 0, 0}; ++ u8 *p = NULL; ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ blockSize_p1 = MAX_REG_BOLCK_SIZE; ++#endif ++ ++ //3 Phase #1 ++ blockCount_p1 = buffSize / blockSize_p1; ++ remainSize_p1 = buffSize % blockSize_p1; ++ ++ if (blockCount_p1) { ++ RT_TRACE(_module_hal_init_c_, _drv_notice_, ++ ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n", ++ buffSize, blockSize_p1, blockCount_p1, remainSize_p1)); ++ } ++ ++ for (i = 0; i < blockCount_p1; i++) ++ { ++#ifdef CONFIG_USB_HCI ++ ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1)); ++#else ++ ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32*)(bufferPtr + i * blockSize_p1)))); ++#endif ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ ++#ifdef CONFIG_PCI_HCI ++ p = (u8*)((u32*)(bufferPtr + blockCount_p1 * blockSize_p1)); ++ if (remainSize_p1) { ++ switch (remainSize_p1) { ++ case 0: ++ break; ++ case 3: ++ remainFW[2]=*(p+2); ++ case 2: ++ remainFW[1]=*(p+1); ++ case 1: ++ remainFW[0]=*(p); ++ ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + blockCount_p1 * blockSize_p1), ++ le32_to_cpu(*(u32*)remainFW)); ++ } ++ return ret; ++ } ++#endif ++ ++ //3 Phase #2 ++ if (remainSize_p1) ++ { ++ offset = blockCount_p1 * blockSize_p1; ++ ++ blockCount_p2 = remainSize_p1/blockSize_p2; ++ remainSize_p2 = remainSize_p1%blockSize_p2; ++ ++ if (blockCount_p2) { ++ RT_TRACE(_module_hal_init_c_, _drv_notice_, ++ ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n", ++ (buffSize-offset), blockSize_p2 ,blockCount_p2, remainSize_p2)); ++ } ++ ++#ifdef CONFIG_USB_HCI ++ for (i = 0; i < blockCount_p2; i++) { ++ ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2)); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++#endif ++ } ++ ++ //3 Phase #3 ++ if (remainSize_p2) ++ { ++ offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); ++ ++ blockCount_p3 = remainSize_p2 / blockSize_p3; ++ ++ RT_TRACE(_module_hal_init_c_, _drv_notice_, ++ ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n", ++ (buffSize-offset), blockSize_p3, blockCount_p3)); ++ ++ for(i = 0 ; i < blockCount_p3 ; i++){ ++ ret =rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ } ++ ++exit: ++ return ret; ++} ++ ++static int ++_PageWrite( ++ IN PADAPTER padapter, ++ IN u32 page, ++ IN PVOID buffer, ++ IN u32 size ++ ) ++{ ++ u8 value8; ++ u8 u8Page = (u8) (page & 0x07) ; ++ ++ value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page ; ++ rtw_write8(padapter, REG_MCUFWDL+2,value8); ++ ++ return _BlockWrite(padapter,buffer,size); ++} ++ ++static VOID ++_FillDummy( ++ u8* pFwBuf, ++ u32* pFwLen ++ ) ++{ ++ u32 FwLen = *pFwLen; ++ u8 remain = (u8)(FwLen%4); ++ remain = (remain==0)?0:(4-remain); ++ ++ while(remain>0) ++ { ++ pFwBuf[FwLen] = 0; ++ FwLen++; ++ remain--; ++ } ++ ++ *pFwLen = FwLen; ++} ++ ++static int ++_WriteFW( ++ IN PADAPTER padapter, ++ IN PVOID buffer, ++ IN u32 size ++ ) ++{ ++ // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. ++ // We can remove _ReadChipVersion from ReadpadapterInfo8192C later. ++ int ret = _SUCCESS; ++ u32 pageNums,remainSize ; ++ u32 page, offset; ++ u8 *bufferPtr = (u8*)buffer; ++ ++#ifdef CONFIG_PCI_HCI ++ // 20100120 Joseph: Add for 88CE normal chip. ++ // Fill in zero to make firmware image to dword alignment. ++// _FillDummy(bufferPtr, &size); ++#endif ++ ++ pageNums = size / MAX_PAGE_SIZE ; ++ //RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n")); ++ remainSize = size % MAX_PAGE_SIZE; ++ ++ for (page = 0; page < pageNums; page++) { ++ offset = page * MAX_PAGE_SIZE; ++ ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_PAGE_SIZE); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ if (remainSize) { ++ offset = pageNums * MAX_PAGE_SIZE; ++ page = pageNums; ++ ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize); ++ ++ if(ret == _FAIL) ++ goto exit; ++ ++ } ++ RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n")); ++ ++exit: ++ return ret; ++} ++ ++void _MCUIO_Reset88E(PADAPTER padapter,u8 bReset) ++{ ++ u8 u1bTmp; ++ ++ if(bReset==_TRUE){ ++ // Reset MCU IO Wrapper- sugggest by SD1-Gimmy ++ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); ++ rtw_write8(padapter,REG_RSV_CTRL+1, (u1bTmp&(~BIT3))); ++ }else{ ++ // Enable MCU IO Wrapper ++ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); ++ rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp|BIT3); ++ } ++ ++} ++void _8051Reset88E(PADAPTER padapter) ++{ ++ u8 u1bTmp; ++ ++ _MCUIO_Reset88E(padapter,_TRUE); ++ u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); ++ rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); ++ _MCUIO_Reset88E(padapter,_FALSE); ++ rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2)); ++ ++ DBG_871X("=====> _8051Reset88E(): 8051 reset success .\n"); ++} ++ ++static s32 _FWFreeToGo(PADAPTER padapter) ++{ ++ u32 counter = 0; ++ u32 value32; ++ u8 value8; ++ ++ // polling CheckSum report ++ do { ++ value32 = rtw_read32(padapter, REG_MCUFWDL); ++ if (value32 & FWDL_ChkSum_rpt) break; ++ } while (counter++ < POLLING_READY_TIMEOUT_COUNT); ++ ++ if (counter >= POLLING_READY_TIMEOUT_COUNT) { ++ DBG_871X("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); ++ return _FAIL; ++ } ++ DBG_871X("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); ++ ++ ++ value32 = rtw_read32(padapter, REG_MCUFWDL); ++ value32 |= MCUFWDL_RDY; ++ value32 &= ~WINTINI_RDY; ++ rtw_write32(padapter, REG_MCUFWDL, value32); ++ ++ _8051Reset88E(padapter); ++ ++ // polling for FW ready ++ counter = 0; ++ do { ++ value32 = rtw_read32(padapter, REG_MCUFWDL); ++ if (value32 & WINTINI_RDY) { ++ DBG_871X("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); ++ return _SUCCESS; ++ } ++ rtw_udelay_os(5); ++ } while (counter++ < POLLING_READY_TIMEOUT_COUNT); ++ ++ DBG_871X ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); ++ return _FAIL; ++} ++ ++#define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0) ++ ++ ++#ifdef CONFIG_FILE_FWIMG ++extern char *rtw_fw_file_path; ++u8 FwBuffer8188E[FW_8188E_SIZE]; ++#endif //CONFIG_FILE_FWIMG ++#ifdef CONFIG_WOWLAN ++// ++// Description: ++// Download 8192C firmware code. ++// ++// ++s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw) ++#else ++s32 rtl8188e_FirmwareDownload(PADAPTER padapter) ++#endif ++{ ++ s32 rtStatus = _SUCCESS; ++ u8 writeFW_retry = 0; ++ u32 fwdl_start_time; ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ++ ++ u8 *FwImage; ++ u32 FwImageLen; ++ u8 *pFwImageFileName; ++#ifdef CONFIG_WOWLAN ++ u8 *FwImageWoWLAN; ++ u32 FwImageWoWLANLen; ++#endif ++ u8 *pucMappedFile = NULL; ++ PRT_FIRMWARE_8188E pFirmware = NULL; ++ PRT_8188E_FIRMWARE_HDR pFwHdr = NULL; ++ u8 *pFirmwareBuf; ++ u32 FirmwareLen; ++ ++ ++ RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __FUNCTION__)); ++ pFirmware = (PRT_FIRMWARE_8188E)rtw_zmalloc(sizeof(RT_FIRMWARE_8188E)); ++ if(!pFirmware) ++ { ++ ++ rtStatus = _FAIL; ++ goto Exit; ++ } ++ ++ FwImage = (u8*)Rtl8188E_FwImageArray; ++ FwImageLen = Rtl8188E_FWImgArrayLength; ++ ++#ifdef CONFIG_WOWLAN ++ FwImageWoWLAN = (u8*)Rtl8188E_FwWoWImageArray; ++ FwImageWoWLANLen = Rtl8188E_FwWoWImgArrayLength; ++#endif //CONFIG_WOWLAN ++ ++// RT_TRACE(_module_hal_init_c_, _drv_err_, ("rtl8723a_FirmwareDownload: %s\n", pFwImageFileName)); ++ ++ #ifdef CONFIG_FILE_FWIMG ++ if(rtw_is_file_readable(rtw_fw_file_path) == _TRUE) ++ { ++ DBG_871X("%s accquire FW from file:%s\n", __FUNCTION__, rtw_fw_file_path); ++ pFirmware->eFWSource = FW_SOURCE_IMG_FILE; ++ } ++ else ++ #endif //CONFIG_FILE_FWIMG ++ { ++ pFirmware->eFWSource = FW_SOURCE_HEADER_FILE; ++ } ++ ++ switch(pFirmware->eFWSource) ++ { ++ case FW_SOURCE_IMG_FILE: ++ #ifdef CONFIG_FILE_FWIMG ++ rtStatus = rtw_retrive_from_file(rtw_fw_file_path, FwBuffer8188E, FW_8188E_SIZE); ++ pFirmware->ulFwLength = rtStatus>=0?rtStatus:0; ++ pFirmware->szFwBuffer = FwBuffer8188E; ++ #endif //CONFIG_FILE_FWIMG ++ break; ++ case FW_SOURCE_HEADER_FILE: ++ if (FwImageLen > FW_8188E_SIZE) { ++ rtStatus = _FAIL; ++ RT_TRACE(_module_hal_init_c_, _drv_err_, ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE) ); ++ goto Exit; ++ } ++ ++ pFirmware->szFwBuffer = FwImage; ++ pFirmware->ulFwLength = FwImageLen; ++#ifdef CONFIG_WOWLAN ++ if(bUsedWoWLANFw){ ++ pFirmware->szWoWLANFwBuffer = FwImageWoWLAN; ++ pFirmware->ulWoWLANFwLength = FwImageWoWLANLen; ++ } ++#endif //CONFIG_WOWLAN ++ break; ++ } ++#ifdef CONFIG_WOWLAN ++ if(bUsedWoWLANFw) { ++ pFirmwareBuf = pFirmware->szWoWLANFwBuffer; ++ FirmwareLen = pFirmware->ulWoWLANFwLength; ++ pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmware->szWoWLANFwBuffer; ++ } else ++#endif ++ { ++ pFirmwareBuf = pFirmware->szFwBuffer; ++ FirmwareLen = pFirmware->ulFwLength; ++ DBG_871X_LEVEL(_drv_info_, "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, FirmwareLen); ++ ++ // To Check Fw header. Added by tynli. 2009.12.04. ++ pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmware->szFwBuffer; ++ } ++ ++ pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version); ++ pHalData->FirmwareSubVersion = pFwHdr->Subversion; ++ pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature); ++ ++ DBG_871X ("%s: fw_ver=%d fw_subver=%d sig=0x%x\n", ++ __FUNCTION__, pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, pHalData->FirmwareSignature); ++ ++ if (IS_FW_HEADER_EXIST(pFwHdr)) ++ { ++ // Shift 32 bytes for FW header ++ pFirmwareBuf = pFirmwareBuf + 32; ++ FirmwareLen = FirmwareLen - 32; ++ } ++ ++ // Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, ++ // or it will cause download Fw fail. 2010.02.01. by tynli. ++ if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) //8051 RAM code ++ { ++ rtw_write8(padapter, REG_MCUFWDL, 0x00); ++ _8051Reset88E(padapter); ++ } ++ ++ _FWDownloadEnable(padapter, _TRUE); ++ fwdl_start_time = rtw_get_current_time(); ++ while(1) { ++ //reset the FWDL chksum ++ rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt); ++ ++ rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); ++ ++ if(rtStatus == _SUCCESS || padapter->bDriverStopped || padapter->bSurpriseRemoved ++ ||(writeFW_retry++ >= 3 && rtw_get_passing_time_ms(fwdl_start_time) > 500) ++ ) ++ break; ++ } ++ _FWDownloadEnable(padapter, _FALSE); ++ ++ DBG_871X("%s writeFW_retry:%u, time after fwdl_start_time:%ums\n", __FUNCTION__ ++ , writeFW_retry ++ , rtw_get_passing_time_ms(fwdl_start_time) ++ ); ++ ++ if(_SUCCESS != rtStatus){ ++ DBG_871X("DL Firmware failed!\n"); ++ goto Exit; ++ } ++ ++ rtStatus = _FWFreeToGo(padapter); ++ if (_SUCCESS != rtStatus) { ++ DBG_871X("DL Firmware failed!\n"); ++ goto Exit; ++ } ++ RT_TRACE(_module_hal_init_c_, _drv_info_, ("Firmware is ready to run!\n")); ++ ++Exit: ++ ++ if (pFirmware) ++ rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_8188E)); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n")); ++#ifdef CONFIG_WOWLAN ++ if (adapter_to_pwrctl(padapter)->wowlan_mode) ++ rtl8188e_InitializeFirmwareVars(padapter); ++ else ++ DBG_871X_LEVEL(_drv_always_, "%s: wowland_mode:%d wowlan_wake_reason:%d\n", ++ __func__, adapter_to_pwrctl(padapter)->wowlan_mode, ++ adapter_to_pwrctl(padapter)->wowlan_wake_reason); ++#endif ++ ++ return rtStatus; ++} ++ ++#ifdef CONFIG_WOWLAN ++void rtl8188e_InitializeFirmwareVars(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ ++ // Init Fw LPS related. ++ pwrpriv->bFwCurrentInPSMode = _FALSE; ++ // Init H2C counter. by tynli. 2009.12.09. ++ pHalData->LastHMEBoxNum = 0; ++} ++ ++//=========================================== ++ ++// ++// Description: Prepare some information to Fw for WoWLAN. ++// (1) Download wowlan Fw. ++// (2) Download RSVD page packets. ++// (3) Enable AP offload if needed. ++// ++// 2011.04.12 by tynli. ++// ++VOID ++SetFwRelatedForWoWLAN8188ES( ++ IN PADAPTER padapter, ++ IN u8 bHostIsGoingtoSleep ++) ++{ ++ int status=_FAIL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 bRecover = _FALSE; ++ // ++ // 1. Before WoWLAN we need to re-download WoWLAN Fw. ++ // ++ status = rtl8188e_FirmwareDownload(padapter, bHostIsGoingtoSleep); ++ if(status != _SUCCESS) { ++ DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware failed!!\n"); ++ return; ++ } else { ++ DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware Success !!\n"); ++ } ++ // ++ // 2. Re-Init the variables about Fw related setting. ++ // ++ rtl8188e_InitializeFirmwareVars(padapter); ++} ++#else ++void rtl8188e_InitializeFirmwareVars(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ++ ++ // Init Fw LPS related. ++ adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE; ++ ++ // Init H2C counter. by tynli. 2009.12.09. ++ pHalData->LastHMEBoxNum = 0; ++// pHalData->H2CQueueHead = 0; ++// pHalData->H2CQueueTail = 0; ++// pHalData->H2CStopInsertQueue = FALSE; ++} ++#endif //CONFIG_WOWLAN ++ ++static void rtl8188e_free_hal_data(PADAPTER padapter) ++{ ++_func_enter_; ++ ++ if(padapter->HalData) ++ { ++ rtw_mfree(padapter->HalData, sizeof(HAL_DATA_TYPE)); ++ padapter->HalData = NULL; ++ } ++ ++_func_exit_; ++} ++ ++//=========================================================== ++// Efuse related code ++//=========================================================== ++enum{ ++ VOLTAGE_V25 = 0x03, ++ LDOE25_SHIFT = 28 , ++ }; ++ ++static BOOLEAN ++hal_EfusePgPacketWrite2ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++static BOOLEAN ++hal_EfusePgPacketWrite1ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++static BOOLEAN ++hal_EfusePgPacketWriteData( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++ ++static VOID ++hal_EfusePowerSwitch_RTL8188E( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ u8 tempval; ++ u16 tmpV16; ++ ++ if (PwrState == _TRUE) ++ { ++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); ++ ++ // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL); ++ if( ! (tmpV16 & PWC_EV12V ) ){ ++ tmpV16 |= PWC_EV12V ; ++ rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16); ++ } ++ // Reset: 0x0000h[28], default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN); ++ if( !(tmpV16 & FEN_ELDR) ){ ++ tmpV16 |= FEN_ELDR ; ++ rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16); ++ } ++ ++ // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR); ++ if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){ ++ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ; ++ rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16); ++ } ++ ++ if(bWrite == _TRUE) ++ { ++ // Enable LDO 2.5V before read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ tempval &= 0x0F; ++ tempval |= (VOLTAGE_V25 << 4); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80)); ++ } ++ } ++ else ++ { ++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); ++ ++ if(bWrite == _TRUE){ ++ // Disable LDO 2.5V after read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F)); ++ } ++ } ++} ++ ++static VOID ++rtl8188e_EfusePowerSwitch( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ hal_EfusePowerSwitch_RTL8188E(pAdapter, bWrite, PwrState); ++} ++ ++ ++ ++static bool efuse_read_phymap( ++ PADAPTER Adapter, ++ u8 *pbuf, //buffer to store efuse physical map ++ u16 *size //the max byte to read. will update to byte read ++ ) ++{ ++ u8 *pos = pbuf; ++ u16 limit = *size; ++ u16 addr = 0; ++ bool reach_end = _FALSE; ++ ++ // ++ // Refresh efuse init map as all 0xFF. ++ // ++ _rtw_memset(pbuf, 0xFF, limit); ++ ++ ++ // ++ // Read physical efuse content. ++ // ++ while(addr < limit) ++ { ++ ReadEFuseByte(Adapter, addr, pos, _FALSE); ++ if(*pos != 0xFF) ++ { ++ pos++; ++ addr++; ++ } ++ else ++ { ++ reach_end = _TRUE; ++ break; ++ } ++ } ++ ++ *size = addr; ++ ++ return reach_end; ++ ++} ++ ++static VOID ++Hal_EfuseReadEFuse88E( ++ PADAPTER Adapter, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ //u8 efuseTbl[EFUSE_MAP_LEN_88E]; ++ u8 *efuseTbl = NULL; ++ u8 rtemp8[1]; ++ u16 eFuse_Addr = 0; ++ u8 offset, wren; ++ u16 i, j; ++ //u16 eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT]; ++ u16 **eFuseWord = NULL; ++ u16 efuse_utilized = 0; ++ u8 efuse_usage = 0; ++ u8 u1temp = 0; ++ ++ // ++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. ++ // ++ if((_offset + _size_byte)>EFUSE_MAP_LEN_88E) ++ {// total E-Fuse table is 512bytes ++ DBG_8192C("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte); ++ goto exit; ++ } ++ ++ efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E); ++ if(efuseTbl == NULL) ++ { ++ DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); ++ if(eFuseWord == NULL) ++ { ++ DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ // 0. Refresh efuse init map as all oxFF. ++ for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) ++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) ++ eFuseWord[i][j] = 0xFFFF; ++ ++ // ++ // 1. Read the first byte to check if efuse is empty!!! ++ // ++ // ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ if(*rtemp8 != 0xFF) ++ { ++ efuse_utilized++; ++ //DBG_8192C("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); ++ eFuse_Addr++; ++ } ++ else ++ { ++ DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); ++ goto exit; ++ } ++ ++ ++ // ++ // 2. Read real efuse content. Filter PG header and every section data. ++ // ++ while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); ++ ++ // Check PG header for section num. ++ if((*rtemp8 & 0x1F ) == 0x0F) //extended header ++ { ++ u1temp =( (*rtemp8 & 0xE0) >> 5); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); ++ ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); ++ ++ if((*rtemp8 & 0x0F) == 0x0F) ++ { ++ eFuse_Addr++; ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ ++ if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ eFuse_Addr++; ++ } ++ continue; ++ } ++ else ++ { ++ offset = ((*rtemp8 & 0xF0) >> 1) | u1temp; ++ wren = (*rtemp8 & 0x0F); ++ eFuse_Addr++; ++ } ++ } ++ else ++ { ++ offset = ((*rtemp8 >> 4) & 0x0f); ++ wren = (*rtemp8 & 0x0f); ++ } ++ ++ if(offset < EFUSE_MAX_SECTION_88E) ++ { ++ // Get word enable value from PG header ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); ++ ++ for(i=0; i= EFUSE_REAL_CONTENT_LEN_88E) ++ break; ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ eFuse_Addr++; ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); ++ ++ efuse_utilized++; ++ eFuseWord[offset][i] |= (((u2Byte)*rtemp8 << 8) & 0xff00); ++ ++ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) ++ break; ++ } ++ ++ wren >>= 1; ++ ++ } ++ } ++ ++ // Read next PG header ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); ++ ++ if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) ++ { ++ efuse_utilized++; ++ eFuse_Addr++; ++ } ++ } ++ ++ // ++ // 3. Collect 16 sections and 4 word unit into Efuse map. ++ // ++ for(i=0; i> 8) & 0xff); ++ } ++ } ++ ++ ++ // ++ // 4. Copy from Efuse map to output pointer memory!!! ++ // ++ for(i=0; i<_size_byte; i++) ++ { ++ pbuf[i] = efuseTbl[_offset+i]; ++ } ++ ++ // ++ // 5. Calculate Efuse utilization. ++ // ++ efuse_usage = (u1Byte)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr); ++ ++exit: ++ if(efuseTbl) ++ rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E); ++ ++ if(eFuseWord) ++ rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); ++} ++ ++ ++static BOOLEAN ++Hal_EfuseSwitchToBank( ++ IN PADAPTER pAdapter, ++ IN u8 bank, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet = _FALSE; ++ u32 value32=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Efuse switch bank to %d\n", bank)); ++ if(bPseudoTest) ++ { ++ fakeEfuseBank = bank; ++ bRet = _TRUE; ++ } ++ else ++ { ++ if(IS_HARDWARE_TYPE_8723A(pAdapter) && ++ INCLUDE_MULTI_FUNC_BT(pAdapter)) ++ { ++ value32 = rtw_read32(pAdapter, EFUSE_TEST); ++ bRet = _TRUE; ++ switch(bank) ++ { ++ case 0: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); ++ break; ++ case 1: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); ++ break; ++ case 2: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); ++ break; ++ case 3: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); ++ break; ++ default: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); ++ bRet = _FALSE; ++ break; ++ } ++ rtw_write32(pAdapter, EFUSE_TEST, value32); ++ } ++ else ++ bRet = _TRUE; ++ } ++ return bRet; ++} ++ ++ ++ ++static VOID ++ReadEFuseByIC( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++#ifdef DBG_IOL_READ_EFUSE_MAP ++ u8 logical_map[512]; ++#endif ++ ++#ifdef CONFIG_IOL_READ_EFUSE_MAP ++ if(!bPseudoTest )//&& rtw_IOL_applied(Adapter)) ++ { ++ int ret = _FAIL; ++ if(rtw_IOL_applied(Adapter)) ++ { ++ rtw_hal_power_on(Adapter); ++ ++ iol_mode_enable(Adapter, 1); ++ #ifdef DBG_IOL_READ_EFUSE_MAP ++ iol_read_efuse(Adapter, 0, _offset, _size_byte, logical_map); ++ #else ++ ret = iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf); ++ #endif ++ iol_mode_enable(Adapter, 0); ++ ++ if(_SUCCESS == ret) ++ goto exit; ++ } ++ } ++#endif ++ Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest); ++ ++exit: ++ ++#ifdef DBG_IOL_READ_EFUSE_MAP ++ if(_rtw_memcmp(logical_map, Adapter->eeprompriv.efuse_eeprom_data, 0x130) == _FALSE) ++ { ++ int i; ++ DBG_871X("%s compare first 0x130 byte fail\n", __FUNCTION__); ++ for(i=0;i<512;i++) ++ { ++ if(i%16==0) ++ DBG_871X("0x%03x: ", i); ++ DBG_871X("%02x ", logical_map[i]); ++ if(i%16==15) ++ DBG_871X("\n"); ++ } ++ DBG_871X("\n"); ++ } ++#endif ++ ++ return; ++} ++ ++static VOID ++ReadEFuse_Pseudo( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest); ++} ++ ++static VOID ++rtl8188e_ReadEFuse( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ if(bPseudoTest) ++ { ++ ReadEFuse_Pseudo(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); ++ } ++ else ++ { ++ ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); ++ } ++} ++ ++//Do not support BT ++VOID ++Hal_EFUSEGetEfuseDefinition88E( ++ IN PADAPTER pAdapter, ++ IN u1Byte efuseType, ++ IN u1Byte type, ++ OUT PVOID pOut ++ ) ++{ ++ switch(type) ++ { ++ case TYPE_EFUSE_MAX_SECTION: ++ { ++ u8* pMax_section; ++ pMax_section = (u8*)pOut; ++ *pMax_section = EFUSE_MAX_SECTION_88E; ++ } ++ break; ++ case TYPE_EFUSE_REAL_CONTENT_LEN: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (u16*)pOut; ++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E; ++ } ++ break; ++ case TYPE_EFUSE_CONTENT_LEN_BANK: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (u16*)pOut; ++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E; ++ } ++ break; ++ case TYPE_AVAILABLE_EFUSE_BYTES_BANK: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (u16*)pOut; ++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (u16*)pOut; ++ *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ case TYPE_EFUSE_MAP_LEN: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (u16*)pOut; ++ *pu2Tmp = (u16)EFUSE_MAP_LEN_88E; ++ } ++ break; ++ case TYPE_EFUSE_PROTECT_BYTES_BANK: ++ { ++ u8* pu1Tmp; ++ pu1Tmp = (u8*)pOut; ++ *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ default: ++ { ++ u8* pu1Tmp; ++ pu1Tmp = (u8*)pOut; ++ *pu1Tmp = 0; ++ } ++ break; ++ } ++} ++VOID ++Hal_EFUSEGetEfuseDefinition_Pseudo88E( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u8 type, ++ OUT PVOID pOut ++ ) ++{ ++ switch(type) ++ { ++ case TYPE_EFUSE_MAX_SECTION: ++ { ++ u8* pMax_section; ++ pMax_section = (pu1Byte)pOut; ++ *pMax_section = EFUSE_MAX_SECTION_88E; ++ } ++ break; ++ case TYPE_EFUSE_REAL_CONTENT_LEN: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (pu2Byte)pOut; ++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E; ++ } ++ break; ++ case TYPE_EFUSE_CONTENT_LEN_BANK: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (pu2Byte)pOut; ++ *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E; ++ } ++ break; ++ case TYPE_AVAILABLE_EFUSE_BYTES_BANK: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (pu2Byte)pOut; ++ *pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (pu2Byte)pOut; ++ *pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ case TYPE_EFUSE_MAP_LEN: ++ { ++ u16* pu2Tmp; ++ pu2Tmp = (pu2Byte)pOut; ++ *pu2Tmp = (u2Byte)EFUSE_MAP_LEN_88E; ++ } ++ break; ++ case TYPE_EFUSE_PROTECT_BYTES_BANK: ++ { ++ u8* pu1Tmp; ++ pu1Tmp = (u8*)pOut; ++ *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E); ++ } ++ break; ++ default: ++ { ++ u8* pu1Tmp; ++ pu1Tmp = (u8*)pOut; ++ *pu1Tmp = 0; ++ } ++ break; ++ } ++} ++ ++ ++static VOID ++rtl8188e_EFUSE_GetEfuseDefinition( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u8 type, ++ OUT void *pOut, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ if(bPseudoTest) ++ { ++ Hal_EFUSEGetEfuseDefinition_Pseudo88E(pAdapter, efuseType, type, pOut); ++ } ++ else ++ { ++ Hal_EFUSEGetEfuseDefinition88E(pAdapter, efuseType, type, pOut); ++ } ++} ++ ++static u8 ++Hal_EfuseWordEnableDataWrite( IN PADAPTER pAdapter, ++ IN u16 efuse_addr, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 tmpaddr = 0; ++ u16 start_addr = efuse_addr; ++ u8 badworden = 0x0F; ++ u8 tmpdata[8]; ++ ++ _rtw_memset((PVOID)tmpdata, 0xff, PGPKT_DATA_SIZE); ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr)); ++ ++ if(!(word_en&BIT0)) ++ { ++ tmpaddr = start_addr; ++ efuse_OneByteWrite(pAdapter,start_addr++, data[0], bPseudoTest); ++ efuse_OneByteWrite(pAdapter,start_addr++, data[1], bPseudoTest); ++ ++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[0], bPseudoTest); ++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[1], bPseudoTest); ++ if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){ ++ badworden &= (~BIT0); ++ } ++ } ++ if(!(word_en&BIT1)) ++ { ++ tmpaddr = start_addr; ++ efuse_OneByteWrite(pAdapter,start_addr++, data[2], bPseudoTest); ++ efuse_OneByteWrite(pAdapter,start_addr++, data[3], bPseudoTest); ++ ++ efuse_OneByteRead(pAdapter,tmpaddr , &tmpdata[2], bPseudoTest); ++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[3], bPseudoTest); ++ if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){ ++ badworden &=( ~BIT1); ++ } ++ } ++ if(!(word_en&BIT2)) ++ { ++ tmpaddr = start_addr; ++ efuse_OneByteWrite(pAdapter,start_addr++, data[4], bPseudoTest); ++ efuse_OneByteWrite(pAdapter,start_addr++, data[5], bPseudoTest); ++ ++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[4], bPseudoTest); ++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[5], bPseudoTest); ++ if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){ ++ badworden &=( ~BIT2); ++ } ++ } ++ if(!(word_en&BIT3)) ++ { ++ tmpaddr = start_addr; ++ efuse_OneByteWrite(pAdapter,start_addr++, data[6], bPseudoTest); ++ efuse_OneByteWrite(pAdapter,start_addr++, data[7], bPseudoTest); ++ ++ efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[6], bPseudoTest); ++ efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[7], bPseudoTest); ++ if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){ ++ badworden &=( ~BIT3); ++ } ++ } ++ return badworden; ++} ++ ++static u8 ++Hal_EfuseWordEnableDataWrite_Pseudo( IN PADAPTER pAdapter, ++ IN u16 efuse_addr, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ret=0; ++ ++ ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static u8 ++rtl8188e_Efuse_WordEnableDataWrite( IN PADAPTER pAdapter, ++ IN u16 efuse_addr, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ret=0; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfuseWordEnableDataWrite_Pseudo(pAdapter, efuse_addr, word_en, data, bPseudoTest); ++ } ++ else ++ { ++ ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++ ++static u16 ++hal_EfuseGetCurrentSize_8188e(IN PADAPTER pAdapter, ++ IN BOOLEAN bPseudoTest) ++{ ++ int bContinual = _TRUE; ++ ++ u16 efuse_addr = 0; ++ u8 hoffset=0,hworden=0; ++ u8 efuse_data,word_cnts=0; ++ ++ if(bPseudoTest) ++ { ++ efuse_addr = (u16)(fakeEfuseUsedBytes); ++ } ++ else ++ { ++ rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); ++ } ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), start_efuse_addr = %d\n", efuse_addr)); ++ ++ while ( bContinual && ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) && ++ AVAILABLE_EFUSE_ADDR(efuse_addr)) ++ { ++ if(efuse_data!=0xFF) ++ { ++ if((efuse_data&0x1F) == 0x0F) //extended header ++ { ++ hoffset = efuse_data; ++ efuse_addr++; ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest); ++ if((efuse_data & 0x0F) == 0x0F) ++ { ++ efuse_addr++; ++ continue; ++ } ++ else ++ { ++ hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ hworden = efuse_data & 0x0F; ++ } ++ } ++ else ++ { ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ } ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ //read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ } ++ else ++ { ++ bContinual = _FALSE ; ++ } ++ } ++ ++ if(bPseudoTest) ++ { ++ fakeEfuseUsedBytes = efuse_addr; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", fakeEfuseUsedBytes)); ++ } ++ else ++ { ++ rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", efuse_addr)); ++ } ++ ++ return efuse_addr; ++} ++ ++static u16 ++Hal_EfuseGetCurrentSize_Pseudo(IN PADAPTER pAdapter, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest); ++ ++ return ret; ++} ++ ++ ++static u16 ++rtl8188e_EfuseGetCurrentSize( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest); ++ } ++ else ++ { ++ ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest); ++ ++ } ++ ++ return ret; ++} ++ ++ ++static int ++hal_EfusePgPacketRead_8188e( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ReadState = PG_STATE_HEADER; ++ ++ int bContinual = _TRUE; ++ int bDataEmpty = _TRUE ; ++ ++ u8 efuse_data,word_cnts = 0; ++ u16 efuse_addr = 0; ++ u8 hoffset = 0,hworden = 0; ++ u8 tmpidx = 0; ++ u8 tmpdata[8]; ++ u8 max_section = 0; ++ u8 tmp_header = 0; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest); ++ ++ if(data==NULL) ++ return _FALSE; ++ if(offset>max_section) ++ return _FALSE; ++ ++ _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ ++ ++ // ++ // Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. ++ // Skip dummy parts to prevent unexpected data read from Efuse. ++ // By pass right now. 2009.02.19. ++ // ++ while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) ) ++ { ++ //------- Header Read ------------- ++ if(ReadState & PG_STATE_HEADER) ++ { ++ if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF)) ++ { ++ if(EXT_HEADER(efuse_data)) ++ { ++ tmp_header = efuse_data; ++ efuse_addr++; ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest); ++ if(!ALL_WORDS_DISABLED(efuse_data)) ++ { ++ hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ hworden = efuse_data & 0x0F; ++ } ++ else ++ { ++ DBG_8192C("Error, All words disabled\n"); ++ efuse_addr++; ++ continue; ++ } ++ } ++ else ++ { ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ } ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ bDataEmpty = _TRUE ; ++ ++ if(hoffset==offset) ++ { ++ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++) ++ { ++ if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) ) ++ { ++ tmpdata[tmpidx] = efuse_data; ++ if(efuse_data!=0xff) ++ { ++ bDataEmpty = _FALSE; ++ } ++ } ++ } ++ if(bDataEmpty==_FALSE){ ++ ReadState = PG_STATE_DATA; ++ }else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ } ++ else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ else{ ++ bContinual = _FALSE ; ++ } ++ } ++ //------- Data section Read ------------- ++ else if(ReadState & PG_STATE_DATA) ++ { ++ efuse_WordEnableDataRead(hworden,tmpdata,data); ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ ++ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) && ++ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff)) ++ return _FALSE; ++ else ++ return _TRUE; ++ ++} ++ ++static int ++Hal_EfusePgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest); ++ ++ ++ return ret; ++} ++ ++static int ++Hal_EfusePgPacketRead_Pseudo( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static int ++rtl8188e_Efuse_PgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfusePgPacketRead_Pseudo(pAdapter, offset, data, bPseudoTest); ++ } ++ else ++ { ++ ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++static BOOLEAN ++hal_EfuseFixHeaderProcess( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN PPGPKT_STRUCT pFixPkt, ++ IN u16 *pAddr, ++ IN BOOLEAN bPseudoTest ++) ++{ ++ u8 originaldata[8], badworden=0; ++ u16 efuse_addr=*pAddr; ++ u32 PgWriteSuccess=0; ++ ++ _rtw_memset((PVOID)originaldata, 0xff, 8); ++ ++ if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) ++ { //check if data exist ++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest); ++ ++ if(badworden != 0xf) // write fail ++ { ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest); ++ ++ if(!PgWriteSuccess) ++ return _FALSE; ++ else ++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ } ++ else ++ { ++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; ++ } ++ } ++ else ++ { ++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; ++ } ++ *pAddr = efuse_addr; ++ return _TRUE; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite2ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE, bContinual=_TRUE; ++ u16 efuse_addr=*pAddr, efuse_max_available_len=0; ++ u8 pg_header=0, tmp_header=0, pg_header_temp=0; ++ u8 repeatcnt=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n")); ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest); ++ ++ while(efuse_addr < efuse_max_available_len) ++ { ++ pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header)); ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n")); ++ return _FALSE; ++ } ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ //to write ext_header ++ if(tmp_header == pg_header) ++ { ++ efuse_addr++; ++ pg_header_temp = pg_header; ++ pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n")); ++ return _FALSE; ++ } ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ if((tmp_header & 0x0F) == 0x0F) //word_en PG fail ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n")); ++ return _FALSE; ++ } ++ else ++ { ++ efuse_addr++; ++ continue; ++ } ++ } ++ else if(pg_header != tmp_header) //offset PG fail ++ { ++ PGPKT_STRUCT fixPkt; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n")); ++ fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1); ++ fixPkt.word_en = tmp_header & 0x0F; ++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); ++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) ++ return _FALSE; ++ } ++ else ++ { ++ bRet = _TRUE; ++ break; ++ } ++ } ++ else if ((tmp_header & 0x1F) == 0x0F) //wrong extended header ++ { ++ efuse_addr+=2; ++ continue; ++ } ++ } ++ ++ *pAddr = efuse_addr; ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite1ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 pg_header=0, tmp_header=0; ++ u16 efuse_addr=*pAddr; ++ u8 repeatcnt=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n")); ++ pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en; ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ return _FALSE; ++ } ++ efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ if(pg_header == tmp_header) ++ { ++ bRet = _TRUE; ++ } ++ else ++ { ++ PGPKT_STRUCT fixPkt; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n")); ++ fixPkt.offset = (tmp_header>>4) & 0x0F; ++ fixPkt.word_en = tmp_header & 0x0F; ++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); ++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) ++ return _FALSE; ++ } ++ ++ *pAddr = efuse_addr; ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWriteData( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ u16 efuse_addr=*pAddr; ++ u8 badworden=0; ++ u32 PgWriteSuccess=0; ++ ++ badworden = 0x0f; ++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); ++ if(badworden == 0x0F) ++ { ++ // write ok ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n")); ++ return _TRUE; ++ } ++ else ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n")); ++ //reorganize other pg packet ++ ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ ++ if(!PgWriteSuccess) ++ return _FALSE; ++ else ++ return _TRUE; ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWriteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ ++ if(pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) ++ { ++ bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest); ++ } ++ else ++ { ++ bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest); ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++wordEnMatched( ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN PPGPKT_STRUCT pCurPkt, ++ IN u8 *pWden ++) ++{ ++ u8 match_word_en = 0x0F; // default all words are disabled ++ u8 i; ++ ++ // check if the same words are enabled both target and current PG packet ++ if( ((pTargetPkt->word_en & BIT0) == 0) && ++ ((pCurPkt->word_en & BIT0) == 0) ) ++ { ++ match_word_en &= ~BIT0; // enable word 0 ++ } ++ if( ((pTargetPkt->word_en & BIT1) == 0) && ++ ((pCurPkt->word_en & BIT1) == 0) ) ++ { ++ match_word_en &= ~BIT1; // enable word 1 ++ } ++ if( ((pTargetPkt->word_en & BIT2) == 0) && ++ ((pCurPkt->word_en & BIT2) == 0) ) ++ { ++ match_word_en &= ~BIT2; // enable word 2 ++ } ++ if( ((pTargetPkt->word_en & BIT3) == 0) && ++ ((pCurPkt->word_en & BIT3) == 0) ) ++ { ++ match_word_en &= ~BIT3; // enable word 3 ++ } ++ ++ *pWden = match_word_en; ++ ++ if(match_word_en != 0xf) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++static BOOLEAN ++hal_EfuseCheckIfDatafollowed( ++ IN PADAPTER pAdapter, ++ IN u8 word_cnts, ++ IN u16 startAddr, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 i, efuse_data; ++ ++ for(i=0; i<(word_cnts*2) ; i++) ++ { ++ if(efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF)) ++ bRet = _TRUE; ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePartialWriteCheck( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 i, efuse_data=0, cur_header=0; ++ u8 new_wden=0, matched_wden=0, badworden=0; ++ u16 startAddr=0, efuse_max_available_len=0, efuse_max=0; ++ PGPKT_STRUCT curPkt; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest); ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&efuse_max, bPseudoTest); ++ ++ if(efuseType == EFUSE_WIFI) ++ { ++ if(bPseudoTest) ++ { ++ startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ else ++ { ++ rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); ++ startAddr%=EFUSE_REAL_CONTENT_LEN; ++ } ++ } ++ else ++ { ++ if(bPseudoTest) ++ { ++ startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ else ++ { ++ startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ } ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr)); ++ ++ while(1) ++ { ++ if(startAddr >= efuse_max_available_len) ++ { ++ bRet = _FALSE; ++ break; ++ } ++ ++ if(efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data!=0xFF)) ++ { ++ if(EXT_HEADER(efuse_data)) ++ { ++ cur_header = efuse_data; ++ startAddr++; ++ efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest); ++ if(ALL_WORDS_DISABLED(efuse_data)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled")); ++ bRet = _FALSE; ++ break; ++ } ++ else ++ { ++ curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ curPkt.word_en = efuse_data & 0x0F; ++ } ++ } ++ else ++ { ++ cur_header = efuse_data; ++ curPkt.offset = (cur_header>>4) & 0x0F; ++ curPkt.word_en = cur_header & 0x0F; ++ } ++ ++ curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); ++ // if same header is found but no data followed ++ // write some part of data followed by the header. ++ if( (curPkt.offset == pTargetPkt->offset) && ++ (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) && ++ wordEnMatched(pTargetPkt, &curPkt, &matched_wden) ) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n")); ++ // Here to write partial data ++ badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest); ++ if(badworden != 0x0F) ++ { ++ u32 PgWriteSuccess=0; ++ // if write fail on some words, write these bad words again ++ ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ ++ if(!PgWriteSuccess) ++ { ++ bRet = _FALSE; // write fail, return ++ break; ++ } ++ } ++ // partial write ok, update the target packet for later use ++ for(i=0; i<4; i++) ++ { ++ if((matched_wden & (0x1<word_en |= (0x1<word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); ++ } ++ // read from next header ++ startAddr = startAddr + (curPkt.word_cnts*2) +1; ++ } ++ else ++ { ++ // not used header, 0xff ++ *pAddr = startAddr; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr)); ++ bRet = _TRUE; ++ break; ++ } ++ } ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgCheckAvailableAddr( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ u16 efuse_max_available_len=0; ++ ++ //Change to check TYPE_EFUSE_MAP_LEN ,beacuse 8188E raw 256,logic map over 256. ++ EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&efuse_max_available_len, _FALSE); ++ ++ //EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&efuse_max_available_len, bPseudoTest); ++ //RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len)); ++ ++ if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n")); ++ return _FALSE; ++ } ++ return _TRUE; ++} ++ ++static VOID ++hal_EfuseConstructPGPkt( ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN PPGPKT_STRUCT pTargetPkt ++ ++) ++{ ++ _rtw_memset((PVOID)pTargetPkt->data, 0xFF, sizeof(u8)*8); ++ pTargetPkt->offset = offset; ++ pTargetPkt->word_en= word_en; ++ efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); ++ pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts)); ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite_BT( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ PGPKT_STRUCT targetPkt; ++ u16 startAddr=0; ++ u8 efuseType=EFUSE_BT; ++ ++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest)) ++ return _FALSE; ++ ++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); ++ ++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ return _TRUE; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite_8188e( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ PGPKT_STRUCT targetPkt; ++ u16 startAddr=0; ++ u8 efuseType=EFUSE_WIFI; ++ ++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest)) ++ return _FALSE; ++ ++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); ++ ++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ return _TRUE; ++} ++ ++ ++static int ++Hal_EfusePgPacketWrite_Pseudo(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static int ++Hal_EfusePgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ ++ return ret; ++} ++ ++static int ++rtl8188e_Efuse_PgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfusePgPacketWrite_Pseudo(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ else ++ { ++ ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ return ret; ++} ++ ++static HAL_VERSION ++ReadChipVersion8188E( ++ IN PADAPTER padapter ++ ) ++{ ++ u32 value32; ++ HAL_VERSION ChipVersion; ++ HAL_DATA_TYPE *pHalData; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ ++ value32 = rtw_read32(padapter, REG_SYS_CFG); ++ ChipVersion.ICType = CHIP_8188E ; ++ ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP); ++ ++ ChipVersion.RFType = RF_TYPE_1T1R; ++ ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC); ++ ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; // IC version (CUT) ++ ++ // For regulator mode. by tynli. 2011.01.14 ++ pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); ++ ++ ChipVersion.ROMVer = 0; // ROM code version. ++ pHalData->MultiFunc = RT_MULTI_FUNC_NONE; ++ ++ ++//#if DBG ++#if 1 ++ dump_chip_info(ChipVersion); ++#endif ++ ++ pHalData->VersionID = ChipVersion; ++ ++ if (IS_1T2R(ChipVersion)){ ++ pHalData->rf_type = RF_1T2R; ++ pHalData->NumTotalRFPath = 2; ++ } ++ else if (IS_2T2R(ChipVersion)){ ++ pHalData->rf_type = RF_2T2R; ++ pHalData->NumTotalRFPath = 2; ++ } ++ else{ ++ pHalData->rf_type = RF_1T1R; ++ pHalData->NumTotalRFPath = 1; ++ } ++ ++ MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type); ++ ++ return ChipVersion; ++} ++ ++static void rtl8188e_read_chip_version(PADAPTER padapter) ++{ ++ ReadChipVersion8188E(padapter); ++} ++void rtl8188e_GetHalODMVar( ++ PADAPTER Adapter, ++ HAL_ODM_VARIABLE eVariable, ++ PVOID pValue1, ++ BOOLEAN bSet) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T podmpriv = &pHalData->odmpriv; ++ switch(eVariable){ ++ case HAL_ODM_STA_INFO: ++ break; ++ default: ++ break; ++ } ++} ++void rtl8188e_SetHalODMVar( ++ PADAPTER Adapter, ++ HAL_ODM_VARIABLE eVariable, ++ PVOID pValue1, ++ BOOLEAN bSet) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PDM_ODM_T podmpriv = &pHalData->odmpriv; ++ //_irqL irqL; ++ switch(eVariable){ ++ case HAL_ODM_STA_INFO: ++ { ++ struct sta_info *psta = (struct sta_info *)pValue1; ++ if(bSet){ ++ DBG_8192C("### Set STA_(%d) info\n",psta->mac_id); ++ ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta); ++ #if(RATE_ADAPTIVE_SUPPORT==1) ++ ODM_RAInfo_Init(podmpriv,psta->mac_id); ++ #endif ++ } ++ else{ ++ DBG_8192C("### Clean STA_(%d) info\n",psta->mac_id); ++ //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ++ ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,NULL); ++ ++ //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ++ } ++ } ++ break; ++ case HAL_ODM_P2P_STATE: ++ ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DIRECT,bSet); ++ break; ++ case HAL_ODM_WIFI_DISPLAY_STATE: ++ ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DISPLAY,bSet); ++ break; ++ default: ++ break; ++ } ++} ++ ++void rtl8188e_start_thread(_adapter *padapter) ++{ ++#ifdef CONFIG_SDIO_HCI ++#ifndef CONFIG_SDIO_TX_TASKLET ++ struct xmit_priv *xmitpriv = &padapter->xmitpriv; ++ ++ xmitpriv->SdioXmitThread = kthread_run(rtl8188es_xmit_thread, padapter, "RTWHALXT"); ++ if (IS_ERR(xmitpriv->SdioXmitThread)) ++ { ++ RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8188es_xmit_thread FAIL!!\n", __FUNCTION__)); ++ } ++#endif ++#endif ++} ++ ++void rtl8188e_stop_thread(_adapter *padapter) ++{ ++#ifdef CONFIG_SDIO_HCI ++#ifndef CONFIG_SDIO_TX_TASKLET ++ struct xmit_priv *xmitpriv = &padapter->xmitpriv; ++ ++ // stop xmit_buf_thread ++ if (xmitpriv->SdioXmitThread ) { ++ _rtw_up_sema(&xmitpriv->SdioXmitSema); ++ _rtw_down_sema(&xmitpriv->SdioXmitTerminateSema); ++ xmitpriv->SdioXmitThread = 0; ++ } ++#endif ++#endif ++} ++void hal_notch_filter_8188e(_adapter *adapter, bool enable) ++{ ++ if (enable) { ++ DBG_871X("Enable notch filter\n"); ++ rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1); ++ } else { ++ DBG_871X("Disable notch filter\n"); ++ rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); ++ } ++} ++void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) ++{ ++ pHalFunc->free_hal_data = &rtl8188e_free_hal_data; ++ ++ pHalFunc->dm_init = &rtl8188e_init_dm_priv; ++ pHalFunc->dm_deinit = &rtl8188e_deinit_dm_priv; ++ ++ pHalFunc->read_chip_version = &rtl8188e_read_chip_version; ++ ++ pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E; ++ pHalFunc->set_channel_handler = &PHY_SwChnl8188E; ++ ++ pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog; ++ ++ pHalFunc->Add_RateATid = &rtl8188e_Add_RateATid; ++ ++ pHalFunc->run_thread= &rtl8188e_start_thread; ++ pHalFunc->cancel_thread= &rtl8188e_stop_thread; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E; ++ pHalFunc->AntDivCompareHandler = &AntDivCompare8188E; ++#endif ++ ++ pHalFunc->read_bbreg = &rtl8188e_PHY_QueryBBReg; ++ pHalFunc->write_bbreg = &rtl8188e_PHY_SetBBReg; ++ pHalFunc->read_rfreg = &rtl8188e_PHY_QueryRFReg; ++ pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg; ++ ++ ++ // Efuse related function ++ pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch; ++ pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse; ++ pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition; ++ pHalFunc->EfuseGetCurrentSize = &rtl8188e_EfuseGetCurrentSize; ++ pHalFunc->Efuse_PgPacketRead = &rtl8188e_Efuse_PgPacketRead; ++ pHalFunc->Efuse_PgPacketWrite = &rtl8188e_Efuse_PgPacketWrite; ++ pHalFunc->Efuse_WordEnableDataWrite = &rtl8188e_Efuse_WordEnableDataWrite; ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ pHalFunc->sreset_init_value = &sreset_init_value; ++ pHalFunc->sreset_reset_value = &sreset_reset_value; ++ pHalFunc->silentreset = &sreset_reset; ++ pHalFunc->sreset_xmit_status_check = &rtl8188e_sreset_xmit_status_check; ++ pHalFunc->sreset_linked_status_check = &rtl8188e_sreset_linked_status_check; ++ pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status; ++ pHalFunc->sreset_inprogress= &sreset_inprogress; ++#endif //DBG_CONFIG_ERROR_DETECT ++ ++ pHalFunc->GetHalODMVarHandler = &rtl8188e_GetHalODMVar; ++ pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar; ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++ pHalFunc->xmit_thread_handler = &hal_xmit_handler; ++#endif ++ ++#ifdef CONFIG_IOL ++ pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync; ++#endif ++ ++ pHalFunc->hal_notch_filter = &hal_notch_filter_8188e; ++ ++} ++ ++u8 GetEEPROMSize8188E(PADAPTER padapter) ++{ ++ u8 size = 0; ++ u32 cr; ++ ++ cr = rtw_read16(padapter, REG_9346CR); ++ // 6: EEPROM used is 93C46, 4: boot from E-Fuse. ++ size = (cr & BOOT_FROM_EEPROM) ? 6 : 4; ++ ++ MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46"); ++ ++ return size; ++} ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) ++//------------------------------------------------------------------------- ++// ++// LLT R/W/Init function ++// ++//------------------------------------------------------------------------- ++s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data) ++{ ++ s32 status = _SUCCESS; ++ s32 count = 0; ++ u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); ++ u16 LLTReg = REG_LLT_INIT; ++ ++ ++ rtw_write32(padapter, LLTReg, value); ++ ++ //polling ++ do { ++ value = rtw_read32(padapter, LLTReg); ++ if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) { ++ break; ++ } ++ ++ if (count > POLLING_LLT_THRESHOLD) { ++ RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address)); ++ status = _FAIL; ++ break; ++ } ++ } while (count++); ++ ++ return status; ++} ++ ++u8 _LLTRead(PADAPTER padapter, u32 address) ++{ ++ s32 count = 0; ++ u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS); ++ u16 LLTReg = REG_LLT_INIT; ++ ++ ++ rtw_write32(padapter, LLTReg, value); ++ ++ //polling and get value ++ do { ++ value = rtw_read32(padapter, LLTReg); ++ if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) { ++ return (u8)value; ++ } ++ ++ if (count > POLLING_LLT_THRESHOLD) { ++ RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling read LLT done at address %d!\n", address)); ++ break; ++ } ++ } while (count++); ++ ++ return 0xFF; ++} ++void Read_LLT_Tab(PADAPTER padapter) ++{ ++ u32 addr,next_addr; ++ printk("############### %s ###################\n",__FUNCTION__); ++ for(addr=0;addr<176;addr++) ++ { ++ next_addr = _LLTRead(padapter,addr); ++ printk("%d->",next_addr); ++ if(((addr+1) %8) ==0) ++ printk("\n"); ++ } ++ printk("\n##################################\n"); ++ ++} ++ ++s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy) ++{ ++ s32 status = _FAIL; ++ u32 i; ++ u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;// 176, 22k ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++#if defined(CONFIG_IOL_LLT) ++ if(rtw_IOL_applied(padapter)) ++ { ++ status = iol_InitLLTTable(padapter, txpktbuf_bndy); ++ } ++ else ++#endif ++ { ++ for (i = 0; i < (txpktbuf_bndy - 1); i++) { ++ status = _LLTWrite(padapter, i, i + 1); ++ if (_SUCCESS != status) { ++ return status; ++ } ++ } ++ ++ // end of list ++ status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF); ++ if (_SUCCESS != status) { ++ return status; ++ } ++ ++ // Make the other pages as ring buffer ++ // This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. ++ // Otherwise used as local loopback buffer. ++ for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) { ++ status = _LLTWrite(padapter, i, (i + 1)); ++ if (_SUCCESS != status) { ++ return status; ++ } ++ } ++ ++ // Let last entry point to the start entry of ring buffer ++ status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy); ++ if (_SUCCESS != status) { ++ return status; ++ } ++ } ++ ++ return status; ++} ++#endif ++ ++ ++void ++Hal_InitPGData88E(PADAPTER padapter) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u32 i; ++ u16 value16; ++ ++ if(_FALSE == pEEPROM->bautoload_fail_flag) ++ { // autoload OK. ++ if (is_boot_from_eeprom(padapter)) ++ { ++ // Read all Content from EEPROM or EFUSE. ++ for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2) ++ { ++// value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1))); ++// *((u16*)(&PROMContent[i])) = value16; ++ } ++ } ++ else ++ { ++ // Read EFUSE real map to shadow. ++ EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE); ++ } ++ } ++ else ++ {//autoload fail ++ RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n")); ++// pHalData->AutoloadFailFlag = _TRUE; ++ //update to default value 0xFF ++ if (!is_boot_from_eeprom(padapter)) ++ EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE); ++ } ++} ++ ++void ++Hal_EfuseParseIDCode88E( ++ IN PADAPTER padapter, ++ IN u8 *hwinfo ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u16 EEPROMId; ++ ++ ++ // Checl 0x8129 again for making sure autoload status!! ++ EEPROMId = le16_to_cpu(*((u16*)hwinfo)); ++ if (EEPROMId != RTL_EEPROM_ID) ++ { ++ DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); ++ pEEPROM->bautoload_fail_flag = _TRUE; ++ } ++ else ++ { ++ pEEPROM->bautoload_fail_flag = _FALSE; ++ } ++ ++ DBG_871X("EEPROM ID=0x%04x\n", EEPROMId); ++} ++ ++static void ++Hal_EEValueCheck( ++ IN u8 EEType, ++ IN PVOID pInValue, ++ OUT PVOID pOutValue ++ ) ++{ ++ switch(EEType) ++ { ++ case EETYPE_TX_PWR: ++ { ++ u8 *pIn, *pOut; ++ pIn = (u8*)pInValue; ++ pOut = (u8*)pOutValue; ++ if(*pIn >= 0 && *pIn <= 63) ++ { ++ *pOut = *pIn; ++ } ++ else ++ { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EETYPE_TX_PWR, value=%d is invalid, set to default=0x%x\n", ++ *pIn, EEPROM_Default_TxPowerLevel)); ++ *pOut = EEPROM_Default_TxPowerLevel; ++ } ++ } ++ break; ++ default: ++ break; ++ } ++} ++ ++static void ++Hal_ReadPowerValueFromPROM_8188E( ++ IN PADAPTER padapter, ++ IN PTxPowerInfo24G pwrInfo24G, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u32 rfPath, eeAddr=EEPROM_TX_PWR_INX_88E, group,TxCount=0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ _rtw_memset(pwrInfo24G, 0, sizeof(TxPowerInfo24G)); ++ ++ if(AutoLoadFail) ++ { ++ for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) ++ { ++ //2.4G default value ++ for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++) ++ { ++ pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; ++ pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; ++ } ++ for(TxCount=0;TxCountBW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; ++ pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; ++ } ++ else ++ { ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ } ++ } ++ ++ ++ } ++ ++ //pHalData->bNOPG = TRUE; ++ return; ++ } ++ ++ for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) ++ { ++ //2.4G default value ++ for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++) ++ { ++ //printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); ++ pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; ++ //printk(" IndexCCK_Base:%02x \n",pwrInfo24G->IndexCCK_Base[rfPath][group] ); ++ if(pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) ++ { ++ pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; ++// pHalData->bNOPG = TRUE; ++ } ++ } ++ for(group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) ++ { ++ //printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); ++ pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; ++ //printk(" IndexBW40_Base: %02x \n",pwrInfo24G->IndexBW40_Base[rfPath][group] ); ++ if(pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) ++ pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; ++ } ++ for(TxCount=0;TxCountBW40_Diff[rfPath][TxCount] = 0; ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF; ++ else ++ { ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; ++ if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF; ++ else ++ { ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); ++ if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; ++ eeAddr++; ++ } ++ else ++ { ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ else ++ { ++ pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; ++ if(pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ else ++ { ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); ++ if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ eeAddr++; ++ ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ else ++ { ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; ++ if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ ++ if(PROMContent[eeAddr] == 0xFF) ++ pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; ++ else ++ { ++ pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); ++ if(pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; ++ } ++ eeAddr++; ++ } ++ } ++ ++ } ++ ++ ++} ++ ++static u8 ++Hal_GetChnlGroup( ++ IN u8 chnl ++ ) ++{ ++ u8 group=0; ++ ++ if (chnl < 3) // Cjanel 1-3 ++ group = 0; ++ else if (chnl < 9) // Channel 4-9 ++ group = 1; ++ else // Channel 10-14 ++ group = 2; ++ ++ return group; ++} ++static u8 ++Hal_GetChnlGroup88E( ++ IN u8 chnl, ++ OUT u8* pGroup ++ ) ++{ ++ u8 bIn24G=_TRUE; ++ ++ if(chnl<=14) ++ { ++ bIn24G=_TRUE; ++ ++ if (chnl < 3) // Chanel 1-2 ++ *pGroup = 0; ++ else if (chnl < 6) // Channel 3-5 ++ *pGroup = 1; ++ else if(chnl <9) // Channel 6-8 ++ *pGroup = 2; ++ else if(chnl <12) // Channel 9-11 ++ *pGroup = 3; ++ else if(chnl <14) // Channel 12-13 ++ *pGroup = 4; ++ else if(chnl ==14) // Channel 14 ++ *pGroup = 5; ++ else ++ { ++ //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 2.4 G, but Channel %d in Group not found \n",chnl)); ++ } ++ } ++ else ++ { ++ bIn24G=_FALSE; ++ ++ if (chnl <=40) ++ *pGroup = 0; ++ else if (chnl <=48) ++ *pGroup = 1; ++ else if(chnl <=56) ++ *pGroup = 2; ++ else if(chnl <=64) ++ *pGroup = 3; ++ else if(chnl <=104) ++ *pGroup = 4; ++ else if(chnl <=112) ++ *pGroup = 5; ++ else if(chnl <=120) ++ *pGroup = 5; ++ else if(chnl <=128) ++ *pGroup = 6; ++ else if(chnl <=136) ++ *pGroup = 7; ++ else if(chnl <=144) ++ *pGroup = 8; ++ else if(chnl <=153) ++ *pGroup = 9; ++ else if(chnl <=161) ++ *pGroup = 10; ++ else if(chnl <=177) ++ *pGroup = 11; ++ else ++ { ++ //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 5G, but Channel %d in Group not found \n",chnl)); ++ } ++ ++ } ++ //RT_TRACE(COMP_EFUSE,DBG_LOUD,("<==Hal_GetChnlGroup88E, Channel = %d, bIn24G =%d,\n",chnl,bIn24G)); ++ return bIn24G; ++} ++ ++void Hal_ReadPowerSavingMode88E( ++ PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); ++ u8 tmpvalue; ++ ++ if(AutoLoadFail){ ++ pwrctl->bHWPowerdown = _FALSE; ++ pwrctl->bSupportRemoteWakeup = _FALSE; ++ } ++ else { ++ ++ //hw power down mode selection , 0:rf-off / 1:power down ++ ++ if(padapter->registrypriv.hwpdn_mode==2) ++ pwrctl->bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4)?_TRUE:_FALSE; ++ else ++ pwrctl->bHWPowerdown = padapter->registrypriv.hwpdn_mode; ++ ++ pwrctl->bHWPwrPindetect = padapter->registrypriv.hwpwrp_detect; ++ ++ // decide hw if support remote wakeup function ++ // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume ++#ifdef CONFIG_USB_HCI ++ pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE; ++#endif //CONFIG_USB_HCI ++ ++ //if(SUPPORT_HW_RADIO_DETECT(Adapter)) ++ //Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ; ++ ++ DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__, ++ pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup); ++ ++ DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",padapter->registrypriv.power_mgnt,padapter->registrypriv.usbss_enable); ++ ++ } ++ ++} ++ ++void ++Hal_ReadTxPowerInfo88E( ++ IN PADAPTER padapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ TxPowerInfo24G pwrInfo24G; ++ u8 rfPath, ch, group, rfPathMax=1; ++ u8 pwr, diff,bIn24G,TxCount; ++ ++ Hal_ReadPowerValueFromPROM_8188E(padapter,&pwrInfo24G, PROMContent, AutoLoadFail); ++ ++ if(!AutoLoadFail) ++ pHalData->bTXPowerDataReadFromEEPORM = TRUE; ++ ++ //for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) ++ for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) ++ { ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++) ++ { ++ bIn24G = Hal_GetChnlGroup88E(ch+1,&group); ++ if(bIn24G) ++ { ++ ++ pHalData->Index24G_CCK_Base[rfPath][ch]=pwrInfo24G.IndexCCK_Base[rfPath][group]; ++ ++ if(ch==(14-1)) ++ pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][4]; ++ else ++ pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][group]; ++ } ++ ++ if(bIn24G) ++ { ++ DBG_871X("======= Path %d, Channel %d =======\n",rfPath,ch+1 ); ++ DBG_871X("Index24G_CCK_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_CCK_Base[rfPath][ch]); ++ DBG_871X("Index24G_BW40_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_BW40_Base[rfPath][ch]); ++ } ++ } ++ ++ for(TxCount=0;TxCountCCK_24G_Diff[rfPath][TxCount]=pwrInfo24G.CCK_Diff[rfPath][TxCount]; ++ pHalData->OFDM_24G_Diff[rfPath][TxCount]=pwrInfo24G.OFDM_Diff[rfPath][TxCount]; ++ pHalData->BW20_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW20_Diff[rfPath][TxCount]; ++ pHalData->BW40_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW40_Diff[rfPath][TxCount]; ++#if DBG ++ DBG_871X("======= TxCount %d =======\n",TxCount ); ++ DBG_871X("CCK_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->CCK_24G_Diff[rfPath][TxCount]); ++ DBG_871X("OFDM_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->OFDM_24G_Diff[rfPath][TxCount]); ++ DBG_871X("BW20_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW20_24G_Diff[rfPath][TxCount]); ++ DBG_871X("BW40_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW40_24G_Diff[rfPath][TxCount]); ++#endif ++ } ++ } ++ ++ ++ // 2010/10/19 MH Add Regulator recognize for EU. ++ if(!AutoLoadFail) ++ { ++ struct registry_priv *registry_par = &padapter->registrypriv; ++ if( registry_par->regulatory_tid == 0xff){ ++ if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) ++ pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); //bit0~2 ++ else ++ pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); //bit0~2 ++ }else{ ++ pHalData->EEPROMRegulatory = registry_par->regulatory_tid; ++ } ++ } ++ else ++ { ++ pHalData->EEPROMRegulatory = 0; ++ } ++ DBG_871X("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory); ++ ++} ++ ++ ++VOID ++Hal_EfuseParseXtal_8188E( ++ IN PADAPTER pAdapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if(!AutoLoadFail) ++ { ++ pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E]; ++ if(pHalData->CrystalCap == 0xFF) ++ pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E; ++ } ++ else ++ { ++ pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E; ++ } ++ DBG_871X("CrystalCap: 0x%2x\n", pHalData->CrystalCap); ++} ++ ++void ++Hal_EfuseParseBoardType88E( ++ IN PADAPTER pAdapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if (!AutoLoadFail) ++ pHalData->BoardType = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5); ++ else ++ pHalData->BoardType = 0; ++ DBG_871X("Board Type: 0x%2x\n", pHalData->BoardType); ++} ++ ++void ++Hal_EfuseParseEEPROMVer88E( ++ IN PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if(!AutoLoadFail){ ++ pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E]; ++ if(pHalData->EEPROMVersion == 0xFF) ++ pHalData->EEPROMVersion = EEPROM_Default_Version; ++ } ++ else{ ++ pHalData->EEPROMVersion = 1; ++ } ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n", ++ pHalData->EEPROMVersion)); ++} ++ ++void ++rtl8188e_EfuseParseChnlPlan( ++ IN PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ padapter->mlmepriv.ChannelPlan = hal_com_get_channel_plan( ++ padapter ++ , hwinfo?hwinfo[EEPROM_ChannelPlan_88E]:0xFF ++ , padapter->registrypriv.channel_plan ++ , RT_CHANNEL_DOMAIN_WORLD_WIDE_13 ++ , AutoLoadFail ++ ); ++ ++ DBG_871X("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan); ++} ++ ++void ++Hal_EfuseParseCustomerID88E( ++ IN PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if (!AutoLoadFail) ++ { ++ pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E]; ++ //pHalData->EEPROMSubCustomerID = hwinfo[EEPROM_CUSTOMERID_88E]; ++ } ++ else ++ { ++ pHalData->EEPROMCustomerID = 0; ++ pHalData->EEPROMSubCustomerID = 0; ++ } ++ DBG_871X("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID); ++ //DBG_871X("EEPROM SubCustomer ID: 0x%02x\n", pHalData->EEPROMSubCustomerID); ++} ++ ++ ++void ++Hal_ReadAntennaDiversity88E( ++ IN PADAPTER pAdapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct registry_priv *registry_par = &pAdapter->registrypriv; ++ ++ if(!AutoLoadFail) ++ { ++ // Antenna Diversity setting. ++ if(registry_par->antdiv_cfg == 2)// 2:By EFUSE ++ { ++ pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3; ++ if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) ++ pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;; ++ } ++ else ++ { ++ pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, 2:By EFUSE ++ } ++ ++ if(registry_par->antdiv_type == 0)// If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. ++ { ++ pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E]; ++ if (pHalData->TRxAntDivType == 0xFF) ++ pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) ++ } ++ else{ ++ pHalData->TRxAntDivType = registry_par->antdiv_type ; ++ } ++ ++ if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV) ++ pHalData->AntDivCfg = 1; // 0xC1[3] is ignored. ++ } ++ else ++ { ++ pHalData->AntDivCfg = 0; ++ pHalData->TRxAntDivType = pHalData->TRxAntDivType; // The value in the driver setting of device manager. ++ } ++ ++ DBG_871X("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n",pHalData->AntDivCfg, pHalData->TRxAntDivType); ++ ++ ++} ++ ++void ++Hal_ReadThermalMeter_88E( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u1Byte tempval; ++ ++ // ++ // ThermalMeter from EEPROM ++ // ++ if(!AutoloadFail) ++ pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E]; ++ else ++ pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; ++// pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0] ++ ++ if(pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) ++ { ++ pHalData->bAPKThermalMeterIgnore = _TRUE; ++ pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; ++ } ++ ++ //pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter; ++ DBG_871X("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter); ++ ++} ++ ++ ++void ++Hal_InitChannelPlan( ++ IN PADAPTER padapter ++ ) ++{ ++#if 0 ++ PMGNT_INFO pMgntInfo = &(padapter->MgntInfo); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if((pMgntInfo->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)) ++ { ++ pMgntInfo->ChannelPlan = hal_MapChannelPlan8192C(padapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK)))); ++ pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan. ++ } ++ else ++ { ++ pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan; ++ } ++ ++ switch(pMgntInfo->ChannelPlan) ++ { ++ case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN: ++ { ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo); ++ ++ pDot11dInfo->bEnabled = TRUE; ++ } ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n")); ++ break; ++ ++ default: //for MacOSX compiler warning. ++ break; ++ } ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan)); ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt ChannelPlan = %d\n" , pMgntInfo->ChannelPlan)); ++#endif ++} ++ ++BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter) ++{ ++ u8 tmpvalue = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); ++ ++ EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue); ++ ++ // 2010/08/25 MH INF priority > PDN Efuse value. ++ if(tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode) ++ { ++ pHalData->pwrdown = _TRUE; ++ } ++ else ++ { ++ pHalData->pwrdown = _FALSE; ++ } ++ ++ DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown); ++ ++ return pHalData->pwrdown; ++} // HalDetectPwrDownMode ++ ++#ifdef CONFIG_WOWLAN ++void Hal_DetectWoWMode(PADAPTER pAdapter) ++{ ++ adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE; ++ DBG_871X("%s\n", __func__); ++} ++#endif ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++void Hal_ReadRFGainOffset( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail) ++{ ++ u8 buff[EFUSE_MAX_SIZE]; ++ u32 res; ++ // ++ // BB_RF Gain Offset from EEPROM ++ // ++ //res = rtw_efuse_access(Adapter, _FALSE, 0, EFUSE_MAX_SIZE, buff); ++ if(!AutoloadFail ){ ++ Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET_88E]; ++ Adapter->eeprompriv.EEPROMRFGainVal=EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL_88E); ++ } ++ else{ ++ Adapter->eeprompriv.EEPROMRFGainOffset = EEPROM_Default_RFGainOffset; ++ Adapter->eeprompriv.EEPROMRFGainVal=0xff; ++ } ++ DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset); ++} ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++//==================================================================================== ++// ++// 20100209 Joseph: ++// This function is used only for 92C to set REG_BCN_CTRL(0x550) register. ++// We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate ++// the value of the register via atomic operation. ++// This prevents from race condition when setting this register. ++// The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. ++// ++void SetBcnCtrlReg( ++ PADAPTER padapter, ++ u8 SetBits, ++ u8 ClearBits) ++{ ++ PHAL_DATA_TYPE pHalData; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ ++ pHalData->RegBcnCtrlVal |= SetBits; ++ pHalData->RegBcnCtrlVal &= ~ClearBits; ++ ++#if 0 ++//#ifdef CONFIG_SDIO_HCI ++ if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK)) ++ pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT; ++#endif ++ ++ rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_mp.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_mp.c +new file mode 100644 +index 00000000..e755d5cd +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_mp.c +@@ -0,0 +1,1157 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_MP_C_ ++#ifdef CONFIG_MP_INCLUDED ++ ++#include ++#include ++ ++#include ++#include ++ ++ ++s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ ++ if (!netif_running(padapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); ++ return _FAIL; ++ } ++ ++ if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); ++ return _FAIL; ++ } ++ ++ if (enable) ++ { ++ pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; ++ } ++ else ++ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit= _FALSE; ++ ++ return _SUCCESS; ++} ++ ++void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ ++ *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl; ++} ++ ++static void Hal_disable_dm(PADAPTER padapter) ++{ ++ u8 v8; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ ++ //3 1. disable firmware dynamic mechanism ++ // disable Power Training, Rate Adaptive ++ v8 = rtw_read8(padapter, REG_BCN_CTRL); ++ v8 &= ~EN_BCN_FUNCTION; ++ rtw_write8(padapter, REG_BCN_CTRL, v8); ++ ++ //3 2. disable driver dynamic mechanism ++ // disable Dynamic Initial Gain ++ // disable High Power ++ // disable Power Tracking ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ // enable APK, LCK and IQK but disable power tracking ++ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _TRUE); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: mpt_SwitchRfSetting ++ * ++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. ++ * ++ * Input: IN PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. ++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ u1Byte ChannelToSw = pmp->channel; ++ ULONG ulRateIdx = pmp->rateidx; ++ ULONG ulbandwidth = pmp->bandwidth; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++#if 0 ++ // <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. ++ pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); ++ pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); ++ PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD); ++ PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD); ++#else ++ // <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. ++ if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && ++ (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) ++ { ++ pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); ++ pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); ++ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); ++ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); ++ } ++ else if (IS_HARDWARE_TYPE_8188E(pAdapter)) ++ { ++ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pmp->MptCtx.backup0x52_RF_A); ++ PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pmp->MptCtx.backup0x52_RF_B); ++ } ++#endif ++ ++ return ; ++} ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) ++{ ++ u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0; ++ u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; ++ u8 i; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ ++ // get current cck swing value and check 0xa22 & 0xa23 later to match the table. ++ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); ++ ++ if (!bInCH14) ++ { ++ // Readback the current bb cck swing value and compare with the table to ++ // get the current swing index ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && ++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) ++ { ++ CCKSwingIndex = i; ++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", ++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); ++ break; ++ } ++ } ++ ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ; ++ ++ ++ //Write 0xa24 ~ 0xa27 ++ TempVal2 = 0; ++ TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+ ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24); ++ ++ //Write 0xa28 0xa29 ++ TempVal3 = 0; ++ TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ; ++ } ++ else ++ { ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) && ++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) ++ { ++ CCKSwingIndex = i; ++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", ++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); ++ break; ++ } ++ } ++ ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ; ++ ++ //Write 0xa24 ~ 0xa27 ++ TempVal2 = 0; ++ TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) + ++ (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+ ++ (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24); ++ ++ //Write 0xa28 0xa29 ++ TempVal3 = 0; ++ TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ; ++ } ++ ++ write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); ++ write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2); ++ write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3); ++} ++ ++void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) ++{ ++ s32 TempCCk; ++ u8 CCK_index, CCK_index_old; ++ u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even ++ u8 TimeOut = 100; ++ s32 i = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ ++ if (!IS_92C_SERIAL(pHalData->VersionID)) ++ return; ++#if 0 ++ while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE) ++ { ++ PlatformSleepUs(100); ++ TimeOut--; ++ if(TimeOut <= 0) ++ { ++ RTPRINT(FINIT, INIT_TxPower, ++ ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" )); ++ break; ++ } ++ } ++#endif ++ if (beven && !pMptCtx->bMptIndexEven) //odd->even ++ { ++ Action = 2; ++ pMptCtx->bMptIndexEven = _TRUE; ++ } ++ else if (!beven && pMptCtx->bMptIndexEven) //even->odd ++ { ++ Action = 1; ++ pMptCtx->bMptIndexEven = _FALSE; ++ } ++ ++ if (Action != 0) ++ { ++ //Query CCK default setting From 0xa24 ++ TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK; ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) ++ { ++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE) ++ { ++ CCK_index_old = (u8) i; ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n", ++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); ++ break; ++ } ++ } ++ else ++ { ++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE) ++ { ++ CCK_index_old = (u8) i; ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n", ++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); ++ break; ++ } ++ } ++ } ++ ++ if (Action == 1) ++ CCK_index = CCK_index_old - 1; ++ else ++ CCK_index = CCK_index_old + 1; ++ ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n", ++// CCK_index)); ++ ++ //Adjust CCK according to gain index ++ if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { ++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]); ++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]); ++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]); ++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]); ++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]); ++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]); ++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]); ++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]); ++ } else { ++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]); ++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]); ++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]); ++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]); ++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]); ++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]); ++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]); ++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]); ++ } ++ } ++#if 0 ++ RTPRINT(FINIT, INIT_TxPower, ++ ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20))); ++ ++ PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE); ++#endif ++} ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++ ++/* ++ * SetChannel ++ * Description ++ * Use H2C command to change channel, ++ * not only modify rf register, but also other setting need to be done. ++ */ ++void Hal_SetChannel(PADAPTER pAdapter) ++{ ++#if 0 ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ ++// SelectChannel(pAdapter, pmp->channel); ++ set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth); ++#else ++ u8 eRFPath; ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); ++ ++ u8 channel = pmp->channel; ++ u8 bandwidth = pmp->bandwidth; ++ u8 rate = pmp->rateidx; ++ ++ ++ // set RF channel register ++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) ++ { ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, ODM_CHANNEL, 0xFF, channel); ++ else ++ _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel); ++ } ++ Hal_mpt_SwitchRfSetting(pAdapter); ++ ++ SelectChannel(pAdapter, channel); ++ ++ if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) { ++ pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _TRUE; ++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14); ++ } ++ else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) { ++ pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE; ++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14); ++ } ++ ++#endif ++} ++ ++/* ++ * Notice ++ * Switch bandwitdth may change center frequency(channel) ++ */ ++void Hal_SetBandwidth(PADAPTER pAdapter) ++{ ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ ++ ++ SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset); ++ Hal_mpt_SwitchRfSetting(pAdapter); ++} ++ ++void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ u32 tmpval = 0; ++ ++ ++ // rf-A cck tx power ++ write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]); ++ tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A]; ++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); ++ ++ // rf-B cck tx power ++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]); ++ tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B]; ++ write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n", ++ TxPower[RF_PATH_A], TxPower[RF_PATH_B])); ++} ++ ++void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ u32 TxAGC = 0; ++ u8 tmpval = 0; ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ // HT Tx-rf(A) ++ tmpval = TxPower[RF_PATH_A]; ++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; ++ ++ write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); ++ ++ // HT Tx-rf(B) ++ tmpval = TxPower[RF_PATH_B]; ++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; ++ ++ write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); ++ ++} ++ ++void Hal_SetAntennaPathPower(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 TxPowerLevel[MAX_RF_PATH_NUMS]; ++ u8 rfPath; ++ ++ TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx; ++ TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b; ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ switch (pHalData->rf_chip) ++ { ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel); ++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); ++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++void Hal_SetTxPower(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 TxPower = pAdapter->mppriv.txpoweridx; ++ u8 TxPowerLevel[MAX_RF_PATH_NUMS]; ++ u8 rf, rfPath; ++ ++ for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) { ++ TxPowerLevel[rf] = TxPower; ++ } ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ switch (pHalData->rf_chip) ++ { ++ // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! ++ // We should call normal driver API later!! ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel); ++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); ++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); ++ break; ++ ++ default: ++ break; ++ } ++ ++// SetCCKTxPower(pAdapter, TxPower); ++// SetOFDMTxPower(pAdapter, TxPower); ++} ++ ++void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) ++{ ++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; ++ ++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); ++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); ++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); ++ ++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); ++ write_bbreg(pAdapter, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); ++} ++ ++void Hal_SetDataRate(PADAPTER pAdapter) ++{ ++ Hal_mpt_SwitchRfSetting(pAdapter); ++} ++ ++void Hal_SetAntenna(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ ++ R_ANTENNA_SELECT_CCK *p_cck_txrx; ++ ++ u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; ++ u8 chgTx = 0, chgRx = 0; ++ u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; ++ ++ ++ p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; ++ p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val; ++ ++ p_ofdm_tx->r_ant_ht1 = 0x1; ++ p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A ++ p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3 ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ p_ofdm_tx->r_tx_antenna = 0x1; ++ r_ofdm_tx_en_val = 0x1; ++ p_ofdm_tx->r_ant_l = 0x1; ++ p_ofdm_tx->r_ant_ht_s1 = 0x1; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x1; ++ p_cck_txrx->r_ccktx_enable = 0x8; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF A=TX and B as standby ++// if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); ++ r_ofdm_tx_en_val = 0x3; ++ ++ // Power save ++ //cosa r_ant_select_ofdm_val = 0x11111111; ++ ++ // We need to close RFB by SW control ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); ++ } ++ } ++ break; ++ ++ case ANTENNA_B: ++ p_ofdm_tx->r_tx_antenna = 0x2; ++ r_ofdm_tx_en_val = 0x2; ++ p_ofdm_tx->r_ant_l = 0x2; ++ p_ofdm_tx->r_ant_ht_s1 = 0x2; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x2; ++ p_cck_txrx->r_ccktx_enable = 0x4; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF A as standby ++ //if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); ++// r_ofdm_tx_en_val = 0x3; ++ ++ // Power save ++ //cosa r_ant_select_ofdm_val = 0x22222222; ++ ++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. ++ // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control ++ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); ++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); ++ } ++ } ++ break; ++ ++ case ANTENNA_AB: // For 8192S ++ p_ofdm_tx->r_tx_antenna = 0x3; ++ r_ofdm_tx_en_val = 0x3; ++ p_ofdm_tx->r_ant_l = 0x3; ++ p_ofdm_tx->r_ant_ht_s1 = 0x3; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x3; ++ p_cck_txrx->r_ccktx_enable = 0xC; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF B as standby ++ //if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); ++ ++ // Disable Power save ++ //cosa r_ant_select_ofdm_val = 0x3321333; ++#if 0 ++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table. ++ if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07. ++ { ++ mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A); ++ } ++#endif ++ // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); ++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ // ++ // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D ++ // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D ++ // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D ++ // ++ switch (pAdapter->mppriv.antenna_rx) ++ { ++ case ANTENNA_A: ++ r_rx_antenna_ofdm = 0x1; // A ++ p_cck_txrx->r_cckrx_enable = 0x0; // default: A ++ p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A ++ chgRx = 1; ++ break; ++ ++ case ANTENNA_B: ++ r_rx_antenna_ofdm = 0x2; // B ++ p_cck_txrx->r_cckrx_enable = 0x1; // default: B ++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B ++ chgRx = 1; ++ break; ++ ++ case ANTENNA_AB: ++ r_rx_antenna_ofdm = 0x3; // AB ++ p_cck_txrx->r_cckrx_enable = 0x0; // default:A ++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B ++ chgRx = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (chgTx && chgRx) ++ { ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ //r_ant_sel_cck_val = r_ant_select_cck_val; ++ PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx ++ PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx ++ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx ++ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx ++ ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); ++} ++ ++s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ if (!netif_running(pAdapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n")); ++ return _FAIL; ++ } ++ ++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n")); ++ return _FAIL; ++ } ++ ++ target_ther &= 0xff; ++ if (target_ther < 0x07) ++ target_ther = 0x07; ++ else if (target_ther > 0x1d) ++ target_ther = 0x1d; ++ ++ pHalData->EEPROMThermalMeter = target_ther; ++ ++ return _SUCCESS; ++} ++ ++void Hal_TriggerRFThermalMeter(PADAPTER pAdapter) ++{ ++ ++ _write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 ); ++ ++// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" )); ++} ++ ++u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter) ++{ ++ u32 ThermalValue = 0; ++ ++ //ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0] ++ ++ ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00); ++ ++// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue)); ++ return (u8)ThermalValue; ++} ++ ++void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value) ++{ ++#if 0 ++ fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER); ++ rtw_msleep_os(1000); ++ fw_cmd_data(pAdapter, value, 1); ++ *value &= 0xFF; ++#else ++ ++ Hal_TriggerRFThermalMeter(pAdapter); ++ rtw_msleep_os(1000); ++ *value = Hal_ReadRFThermalMeter(pAdapter); ++#endif ++} ++ ++void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; ++ if (bStart)// Start Single Carrier. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n")); ++ // 1. if OFDM block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on ++ ++ { ++ // 2. set CCK test mode off, set to CCK normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); ++ // 3. turn on scramble setting ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); ++ } ++ // 4. Turn On Single Carrier Tx and turn off the other test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++#ifdef CONFIG_RTL8192C ++ // 5. Disable TX power saving at STF & LLTF ++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1); ++#endif ++ //for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); ++ ++ } ++ else// Stop Single Carrier. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n")); ++ ++ // Turn off all test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++#ifdef CONFIG_RTL8192C ++ // Cancel disable TX power saving at STF&LLTF ++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0); ++#endif ++ //Delay 10 ms //delay_ms(10); ++ rtw_msleep_os(10); ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ ++ //Stop for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); ++ ++ } ++} ++ ++ ++void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ u8 rfPath; ++ u32 reg58 = 0x0; ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ pAdapter->mppriv.MptCtx.bSingleTone = bStart; ++ if (bStart)// Start Single Tone. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n")); ++ { // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) ++ if (IS_HARDWARE_TYPE_8188E(pAdapter)) ++ { ++ reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask); ++ reg58 &= 0xFFFFFFF0; ++ reg58 += 2; ++ PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58); ++ } ++ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); ++ PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); ++ } ++ ++ if (is92C) ++ { ++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01); ++ rtw_usleep_os(100); ++ if (rfPath == RF_PATH_A) ++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on. ++ else if (rfPath == RF_PATH_B) ++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on. ++ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on. ++ rtw_usleep_os(100); ++ } ++ else ++ { ++ write_rfreg(pAdapter, rfPath, 0x21, 0xd4000); ++ rtw_usleep_os(100); ++ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on. ++ rtw_usleep_os(100); ++ } ++ ++ //for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); ++ ++ } ++ else// Stop Single Tone. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n")); ++ ++ { // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) ++ // <20120326, Kordan> Only in single tone mode. (asked by Edlu) ++ if (IS_HARDWARE_TYPE_8188E(pAdapter)) ++ { ++ reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask); ++ reg58 &= 0xFFFFFFF0; ++ PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58); ++ } ++ ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); ++ } ++ if (is92C) { ++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00); ++ rtw_usleep_os(100); ++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on. ++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on. ++ rtw_usleep_os(100); ++ } else { ++ write_rfreg(pAdapter, rfPath, 0x21, 0x54000); ++ rtw_usleep_os(100); ++ write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on. ++ rtw_usleep_os(100); ++ } ++ ++ //Stop for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); ++ ++ } ++ ++} ++ ++ ++ ++void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) ++{ ++ pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; ++ if (bStart) // Start Carrier Suppression. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n")); ++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) ++ { ++ // 1. if CCK block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on ++ ++ //Turn Off All Test Mode ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting ++ ++ //Set CCK Tx Test Rate ++ //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate); ++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps ++ } ++ ++ //for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); ++ ++ } ++ else// Stop Carrier Suppression. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); ++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) { ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ } ++ ++ //Stop for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); ++ ++ } ++ //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n"); ++} ++ ++void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ u32 cckrate; ++ ++ if (bStart) ++ { ++ RT_TRACE(_module_mp_, _drv_alert_, ++ ("SetCCKContinuousTx: test start\n")); ++ ++ // 1. if CCK block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on ++ ++ //Turn Off All Test Mode ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ //Set CCK Tx Test Rate ++ #if 0 ++ switch(pAdapter->mppriv.rateidx) ++ { ++ case 2: ++ cckrate = 0; ++ break; ++ case 4: ++ cckrate = 1; ++ break; ++ case 11: ++ cckrate = 2; ++ break; ++ case 22: ++ cckrate = 3; ++ break; ++ default: ++ cckrate = 0; ++ break; ++ } ++ #else ++ cckrate = pAdapter->mppriv.rateidx; ++ #endif ++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting ++ ++ ++ // Patch for CCK 11M waveform ++ if (cckrate == MPT_RATE_1M) ++ write_bbreg(pAdapter, 0xA71, BIT(6), bDisable); ++ else ++ write_bbreg(pAdapter, 0xA71, BIT(6), bEnable); ++ ++ //for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); ++ ++ } ++ else { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("SetCCKContinuousTx: test stop\n")); ++ ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ ++ //Stop for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); ++ } ++ ++ pAdapter->mppriv.MptCtx.bCckContTx = bStart; ++ pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE; ++}/* mpt_StartCckContTx */ ++ ++void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if (bStart) { ++ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n")); ++ // 1. if OFDM block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on ++ { ++ ++ // 2. set CCK test mode off, set to CCK normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); ++ ++ // 3. turn on scramble setting ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); ++ } ++ // 4. Turn On Continue Tx and turn off the other test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ ++ //for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); ++ ++ } else { ++ RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n")); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ //Delay 10 ms ++ rtw_msleep_os(10); ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ ++ //Stop for dynamic set Power index. ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); ++ } ++ ++ pAdapter->mppriv.MptCtx.bCckContTx = _FALSE; ++ pAdapter->mppriv.MptCtx.bOfdmContTx = bStart; ++}/* mpt_StartOfdmContTx */ ++ ++void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++#if 0 ++ // ADC turn off [bit24-21] adc port0 ~ port1 ++ if (bStart) { ++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF); ++ rtw_usleep_os(100); ++ } ++#endif ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); ++ ++ pAdapter->mppriv.MptCtx.bStartContTx = bStart; ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) ++ { ++ Hal_SetCCKContinuousTx(pAdapter, bStart); ++ } ++ else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) && ++ (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15)) ++ { ++ Hal_SetOFDMContinuousTx(pAdapter, bStart); ++ } ++#if 0 ++ // ADC turn on [bit24-21] adc port0 ~ port1 ++ if (!bStart) { ++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000); ++ } ++#endif ++} ++ ++#endif // CONFIG_MP_INCLUDE ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_phycfg.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_phycfg.c +new file mode 100644 +index 00000000..99bc334c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_phycfg.c +@@ -0,0 +1,3552 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_PHYCFG_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_IOL ++#include ++#endif ++ ++#include ++ ++ ++/*---------------------------Define Local Constant---------------------------*/ ++/* Channel switch:The size of command tables for switch channel*/ ++#define MAX_PRECMD_CNT 16 ++#define MAX_RFDEPENDCMD_CNT 16 ++#define MAX_POSTCMD_CNT 16 ++ ++#define MAX_DOZE_WAITING_TIMES_9x 64 ++ ++/*---------------------------Define Local Constant---------------------------*/ ++ ++ ++/*------------------------Define global variable-----------------------------*/ ++ ++/*------------------------Define local variable------------------------------*/ ++ ++ ++/*--------------------Define export function prototype-----------------------*/ ++// Please refer to header file ++/*--------------------Define export function prototype-----------------------*/ ++ ++/*----------------------------Function Body----------------------------------*/ ++// ++// 1. BB register R/W API ++// ++ ++/** ++* Function: phy_CalculateBitShift ++* ++* OverView: Get shifted position of the BitMask ++* ++* Input: ++* u4Byte BitMask, ++* ++* Output: none ++* Return: u4Byte Return the shift bit bit position of the mask ++*/ ++static u32 ++phy_CalculateBitShift( ++ u32 BitMask ++ ) ++{ ++ u32 i; ++ ++ for(i=0; i<=31; i++) ++ { ++ if ( ((BitMask>>i) & 0x1 ) == 1) ++ break; ++ } ++ ++ return (i); ++} ++ ++#if(SIC_ENABLE == 1) ++static BOOLEAN ++sic_IsSICReady( ++ IN PADAPTER Adapter ++ ) ++{ ++ BOOLEAN bRet=_FALSE; ++ u32 retryCnt=0; ++ u8 sic_cmd=0xff; ++ ++ while(1) ++ { ++ if(retryCnt++ >= SIC_MAX_POLL_CNT) ++ { ++ //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n")); ++ return _FALSE; ++ } ++ ++ //if(RT_SDIO_CANNOT_IO(Adapter)) ++ // return _FALSE; ++ ++ sic_cmd = rtw_read8(Adapter, SIC_CMD_REG); ++ //sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG); ++#if(SIC_HW_SUPPORT == 1) ++ sic_cmd &= 0xf0; // [7:4] ++#endif ++ //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd)); ++ if(sic_cmd == SIC_CMD_READY) ++ return _TRUE; ++ else ++ { ++ rtw_msleep_os(1); ++ //delay_ms(1); ++ } ++ } ++ ++ return bRet; ++} ++ ++/* ++u32 ++sic_CalculateBitShift( ++ u32 BitMask ++ ) ++{ ++ u32 i; ++ ++ for(i=0; i<=31; i++) ++ { ++ if ( ((BitMask>>i) & 0x1 ) == 1) ++ break; ++ } ++ ++ return (i); ++} ++*/ ++ ++static u32 ++sic_Read4Byte( ++ PVOID Adapter, ++ u32 offset ++ ) ++{ ++ u32 u4ret=0xffffffff; ++#if RTL8188E_SUPPORT == 1 ++ u8 retry = 0; ++#endif ++ ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); ++ ++ if(sic_IsSICReady(Adapter)) ++ { ++#if(SIC_HW_SUPPORT == 1) ++ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); ++ //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD)); ++#endif ++ rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff)); ++ //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff))); ++ rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)); ++ //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8))); ++ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ); ++ //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); ++ ++#if RTL8188E_SUPPORT == 1 ++ retry = 4; ++ while(retry--){ ++ rtw_udelay_os(50); ++ //PlatformStallExecution(50); ++ } ++#else ++ rtw_udelay_os(200); ++ //PlatformStallExecution(200); ++#endif ++ ++ if(sic_IsSICReady(Adapter)) ++ { ++ u4ret = rtw_read32(Adapter, SIC_DATA_REG); ++ //u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG); ++ //RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret)); ++ //DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret); ++ } ++ } ++ ++ return u4ret; ++} ++ ++static VOID ++sic_Write4Byte( ++ PVOID Adapter, ++ u32 offset, ++ u32 data ++ ) ++{ ++#if RTL8188E_SUPPORT == 1 ++ u8 retry = 6; ++#endif ++ //DbgPrint("=>Write 0x%x = 0x%x\n", offset, data); ++ //RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data)); ++ if(sic_IsSICReady(Adapter)) ++ { ++#if(SIC_HW_SUPPORT == 1) ++ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE); ++ //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE)); ++#endif ++ rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff)); ++ //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff))); ++ rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)); ++ //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u1Byte)((offset&0xff00)>>8))); ++ rtw_write32(Adapter, SIC_DATA_REG, (u32)data); ++ //PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u4Byte)data); ++ //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data)); ++ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE); ++ //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE)); ++#if RTL8188E_SUPPORT == 1 ++ while(retry--){ ++ rtw_udelay_os(50); ++ //PlatformStallExecution(50); ++ } ++#else ++ rtw_udelay_os(150); ++ //PlatformStallExecution(150); ++#endif ++ ++ } ++} ++//============================================================ ++// extern function ++//============================================================ ++static VOID ++SIC_SetBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 OriginalValue, BitShift; ++ u16 BBWaitCounter = 0; ++ ++ //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n")); ++/* ++ while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE) ++ { ++ BBWaitCounter ++; ++ delay_ms(10); // 1 ms ++ ++ if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) ++ {// Wait too long, return FALSE to avoid to be stuck here. ++ RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter)); ++ return; ++ } ++ } ++*/ ++ // ++ // Critical section start ++ // ++ ++ //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); ++ ++ if(BitMask!= bMaskDWord){//if not "double word" write ++ OriginalValue = sic_Read4Byte(Adapter, RegAddr); ++ //BitShift = sic_CalculateBitShift(BitMask); ++ BitShift = phy_CalculateBitShift(BitMask); ++ Data = (((OriginalValue) & (~BitMask)) | (Data << BitShift)); ++ } ++ ++ sic_Write4Byte(Adapter, RegAddr, Data); ++ ++ //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE); ++ //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n")); ++} ++ ++static u32 ++SIC_QueryBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 ReturnValue = 0, OriginalValue, BitShift; ++ u16 BBWaitCounter = 0; ++ ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n")); ++ ++/* ++ while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE) ++ { ++ BBWaitCounter ++; ++ delay_ms(10); // 10 ms ++ ++ if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) ++ {// Wait too long, return FALSE to avoid to be stuck here. ++ RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter)); ++ return ReturnValue; ++ } ++ } ++*/ ++ OriginalValue = sic_Read4Byte(Adapter, RegAddr); ++ //BitShift = sic_CalculateBitShift(BitMask); ++ BitShift = phy_CalculateBitShift(BitMask); ++ ReturnValue = (OriginalValue & BitMask) >> BitShift; ++ ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue)); ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n")); ++ ++ //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE); ++ return (ReturnValue); ++} ++ ++VOID ++SIC_Init( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded ++ // because for 8723E at beginning 0x1b8=0x1e, that will cause ++ // sic always not be ready ++#if(SIC_HW_SUPPORT == 1) ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", ++ // SIC_INIT_REG, SIC_INIT_VAL)); ++ rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL); ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", ++ // SIC_CMD_REG, SIC_CMD_INIT)); ++ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT); ++ //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT); ++#else ++ //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n")); ++ rtw_write32(Adapter, SIC_CMD_REG, 0); ++ //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0); ++ rtw_write32(Adapter, SIC_CMD_REG+4, 0); ++ //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0); ++#endif ++} ++ ++static BOOLEAN ++SIC_LedOff( ++ IN PADAPTER Adapter ++ ) ++{ ++ // When SIC is enabled, led pin will be used as debug pin, ++ // so don't execute led function when SIC is enabled. ++ return _TRUE; ++} ++#endif ++ ++/** ++* Function: PHY_QueryBBReg ++* ++* OverView: Read "sepcific bits" from BB register ++* ++* Input: ++* PADAPTER Adapter, ++* u4Byte RegAddr, //The target address to be readback ++* u4Byte BitMask //The target bit position in the target address ++* //to be readback ++* Output: None ++* Return: u4Byte Data //The readback register value ++* Note: This function is equal to "GetRegSetting" in PHY programming guide ++*/ ++u32 ++rtl8188e_PHY_QueryBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ++ ) ++{ ++ u32 ReturnValue = 0, OriginalValue, BitShift; ++ u16 BBWaitCounter = 0; ++ ++#if (DISABLE_BB_RF == 1) ++ return 0; ++#endif ++ ++#if(SIC_ENABLE == 1) ++ return SIC_QueryBBReg(Adapter, RegAddr, BitMask); ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); ++ ++ OriginalValue = rtw_read32(Adapter, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ ReturnValue = (OriginalValue & BitMask) >> BitShift; ++ ++ //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue)); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue)); ++ ++ return (ReturnValue); ++ ++} ++ ++ ++/** ++* Function: PHY_SetBBReg ++* ++* OverView: Write "Specific bits" to BB register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* u4Byte RegAddr, //The target address to be modified ++* u4Byte BitMask //The target bit position in the target address ++* //to be modified ++* u4Byte Data //The new register value in the target bit position ++* //of the target address ++* ++* Output: None ++* Return: None ++* Note: This function is equal to "PutRegSetting" in PHY programming guide ++*/ ++ ++VOID ++rtl8188e_PHY_SetBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u16 BBWaitCounter = 0; ++ u32 OriginalValue, BitShift; ++ ++#if (DISABLE_BB_RF == 1) ++ return; ++#endif ++ ++#if(SIC_ENABLE == 1) ++ SIC_SetBBReg(Adapter, RegAddr, BitMask, Data); ++ return; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); ++ ++ if(BitMask!= bMaskDWord){//if not "double word" write ++ OriginalValue = rtw_read32(Adapter, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask)); ++ } ++ ++ rtw_write32(Adapter, RegAddr, Data); ++ ++ //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data)); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); ++ ++} ++ ++ ++// ++// 2. RF register R/W API ++// ++/** ++* Function: phy_RFSerialRead ++* ++* OverView: Read regster from RF chips ++* ++* Input: ++* PADAPTER Adapter, ++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte Offset, //The target address to be read ++* ++* Output: None ++* Return: u4Byte reback value ++* Note: Threre are three types of serial operations: ++* 1. Software serial write ++* 2. Hardware LSSI-Low Speed Serial Interface ++* 3. Hardware HSSI-High speed ++* serial write. Driver need to implement (1) and (2). ++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() ++*/ ++static u32 ++phy_RFSerialRead( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset ++ ) ++{ ++ u32 retValue = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ u32 NewOffset; ++ u32 tmplong,tmplong2; ++ u8 RfPiEnable=0; ++#if 0 ++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs ++ return retValue; ++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs ++ return retValue; ++#endif ++ // ++ // Make sure RF register offset is correct ++ // ++ Offset &= 0xff; ++ ++ // ++ // Switch page for 8256 RF IC ++ // ++ NewOffset = Offset; ++ ++ // 2009/06/17 MH We can not execute IO for power save or other accident mode. ++ //if(RT_CANNOT_IO(Adapter)) ++ //{ ++ // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); ++ // return 0xFFFFFFFF; ++ //} ++ ++ // For 92S LSSI Read RFLSSIRead ++ // For RF A/B write 0x824/82c(does not work in the future) ++ // We must use 0x824 for RF A and B to execute read trigger ++ tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); ++ if(eRFPath == RF_PATH_A) ++ tmplong2 = tmplong; ++ else ++ tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); ++ ++ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF ++ ++ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); ++ rtw_udelay_os(10);// PlatformStallExecution(10); ++ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); ++ rtw_udelay_os(100);//PlatformStallExecution(100); ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); ++ rtw_udelay_os(10);//PlatformStallExecution(10); ++ ++ if(eRFPath == RF_PATH_A) ++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); ++ else if(eRFPath == RF_PATH_B) ++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); ++ ++ if(RfPiEnable) ++ { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF ++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); ++ //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); ++ } ++ else ++ { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF ++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); ++ //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue); ++ } ++ //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); ++ ++ return retValue; ++ ++} ++ ++ ++ ++/** ++* Function: phy_RFSerialWrite ++* ++* OverView: Write data to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte Offset, //The target address to be read ++* u4Byte Data //The new register Data in the target bit position ++* //of the target to be read ++* ++* Output: None ++* Return: None ++* Note: Threre are three types of serial operations: ++* 1. Software serial write ++* 2. Hardware LSSI-Low Speed Serial Interface ++* 3. Hardware HSSI-High speed ++* serial write. Driver need to implement (1) and (2). ++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() ++ * ++ * Note: For RF8256 only ++ * The total count of RTL8256(Zebra4) register is around 36 bit it only employs ++ * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) ++ * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration ++ * programming guide" for more details. ++ * Thus, we define a sub-finction for RTL8526 register address conversion ++ * =========================================================== ++ * Register Mode RegCTL[1] RegCTL[0] Note ++ * (Reg00[12]) (Reg00[10]) ++ * =========================================================== ++ * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * ++ * 2008/09/02 MH Add 92S RF definition ++ * ++ * ++ * ++*/ ++static VOID ++phy_RFSerialWrite( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u32 Data ++ ) ++{ ++ u32 DataAndAddr = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ u32 NewOffset; ++ ++#if 0 ++ // We should check valid regs for RF_6052 case. ++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs ++ return; ++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs ++ return; ++#endif ++ ++ // 2009/06/17 MH We can not execute IO for power save or other accident mode. ++ //if(RT_CANNOT_IO(Adapter)) ++ //{ ++ // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n")); ++ // return; ++ //} ++ ++ Offset &= 0xff; ++ ++ // ++ // Shadow Update ++ // ++ //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); ++ ++ // ++ // Switch page for 8256 RF IC ++ // ++ NewOffset = Offset; ++ ++ // ++ // Put write addr in [5:0] and write data in [31:16] ++ // ++ //DataAndAddr = (Data<<16) | (NewOffset&0x3f); ++ DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF ++ ++ // ++ // Write Operation ++ // ++ PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); ++ //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); ++ ++} ++ ++ ++/** ++* Function: PHY_QueryRFReg ++* ++* OverView: Query "Specific bits" to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte RegAddr, //The target address to be read ++* u4Byte BitMask //The target bit position in the target address ++* //to be read ++* ++* Output: None ++* Return: u4Byte Readback value ++* Note: This function is equal to "GetRFRegSetting" in PHY programming guide ++*/ ++u32 ++rtl8188e_PHY_QueryRFReg( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ++ ) ++{ ++ u32 Original_Value, Readback_Value, BitShift; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u8 RFWaitCounter = 0; ++ //_irqL irqL; ++ ++#if (DISABLE_BB_RF == 1) ++ return 0; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask)); ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformAcquireMutex(&pHalData->mxRFOperate); ++#else ++ //_enter_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); ++ ++ BitShift = phy_CalculateBitShift(BitMask); ++ Readback_Value = (Original_Value & BitMask) >> BitShift; ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformReleaseMutex(&pHalData->mxRFOperate); ++#else ++ //_exit_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask, ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n", ++ // RegAddr, eRFPath, Original_Value)); ++ ++ return (Readback_Value); ++} ++ ++/** ++* Function: PHY_SetRFReg ++* ++* OverView: Write "Specific bits" to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte RegAddr, //The target address to be modified ++* u4Byte BitMask //The target bit position in the target address ++* //to be modified ++* u4Byte Data //The new register Data in the target bit position ++* //of the target address ++* ++* Output: None ++* Return: None ++* Note: This function is equal to "PutRFRegSetting" in PHY programming guide ++*/ ++VOID ++rtl8188e_PHY_SetRFReg( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ) ++{ ++ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u1Byte RFWaitCounter = 0; ++ u32 Original_Value, BitShift; ++ //_irqL irqL; ++ ++#if (DISABLE_BB_RF == 1) ++ return; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformAcquireMutex(&pHalData->mxRFOperate); ++#else ++ //_enter_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ // RF data is 12 bits only ++ if (BitMask != bRFRegOffsetMask) ++ { ++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ Data = ((Original_Value & (~BitMask)) | (Data<< BitShift)); ++ } ++ ++ phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); ++ ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformReleaseMutex(&pHalData->mxRFOperate); ++#else ++ //_exit_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ ++} ++ ++ ++// ++// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. ++// ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigMACWithParaFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: The format of MACPHY_REG.txt is different from PHY and RF. ++ * [Register][Mask][Value] ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigMACWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _FAIL; ++ ++ return rtStatus; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigMACWithHeaderFile() ++ * ++ * Overview: This function read BB parameters from Header file we gen, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: The format of MACPHY_REG.txt is different from PHY and RF. ++ * [Register][Mask][Value] ++ *---------------------------------------------------------------------------*/ ++#ifndef CONFIG_PHY_SETTING_WITH_ODM ++static int ++phy_ConfigMACWithHeaderFile( ++ IN PADAPTER Adapter ++) ++{ ++ u32 i = 0; ++ u32 ArrayLength = 0; ++ u32* ptrArray; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //2008.11.06 Modified by tynli. ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n")); ++ ArrayLength = Rtl8188E_MAC_ArrayLength; ++ ptrArray = (u32*)Rtl8188E_MAC_Array; ++ ++#ifdef CONFIG_IOL_MAC ++ { ++ struct xmit_frame *xmit_frame; ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ return _FAIL; ++ ++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column ++ rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]); ++ } ++ ++ return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); ++ } ++#else ++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column ++ rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]); ++ } ++#endif ++ ++ return _SUCCESS; ++ ++} ++#endif //#ifndef CONFIG_PHY_SETTING_WITH_ODM ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_MACConfig8192C ++ * ++ * Overview: Condig MAC by header file or parameter file. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 08/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++s32 PHY_MACConfig8188E(PADAPTER Adapter) ++{ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ s8 *pszMACRegFile; ++ s8 sz8188EMACRegFile[] = RTL8188E_PHY_MACREG; ++ ++ pszMACRegFile = sz8188EMACRegFile; ++ ++ // ++ // Config MAC ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv)) ++ rtStatus = _FAIL; ++ #else ++ rtStatus = phy_ConfigMACWithHeaderFile(Adapter); ++ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM ++#else ++ ++ // Not make sure EEPROM, add later ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n")); ++ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); ++#endif//CONFIG_EMBEDDED_FWIMG ++ ++ ++ // 2010.07.13 AMPDU aggregation number B ++ rtw_write8(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); ++ //rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); ++ ++ return rtStatus; ++ ++} ++ ++ ++/** ++* Function: phy_InitBBRFRegisterDefinition ++* ++* OverView: Initialize Register definition offset for Radio Path A/B/C/D ++* ++* Input: ++* PADAPTER Adapter, ++* ++* Output: None ++* Return: None ++* Note: The initialization value is constant and it should never be changes ++*/ ++static VOID ++phy_InitBBRFRegisterDefinition( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // RF Interface Sowrtware Control ++ pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 ++ pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) ++ pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 ++ pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) ++ ++ // RF Interface Readback Value ++ pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 ++ pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) ++ pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 ++ pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) ++ ++ // RF Interface Output (and Enable) ++ pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 ++ pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 ++ ++ // RF Interface (Output and) Enable ++ pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) ++ pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) ++ ++ //Addr of LSSI. Wirte RF register by driver ++ pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter ++ pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; ++ ++ // RF parameter ++ pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select ++ pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; ++ pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ ++ // Tx AGC Gain Stage (same for all path. Should we remove this?) ++ pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ ++ // Tranceiver A~D HSSI Parameter-1 ++ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 ++ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 ++ ++ // Tranceiver A~D HSSI Parameter-2 ++ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 ++ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 ++ ++ // RF switch Control ++ pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control ++ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; ++ pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ ++ // AGC control 1 ++ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; ++ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; ++ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; ++ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; ++ ++ // AGC control 2 ++ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; ++ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; ++ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; ++ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; ++ ++ // RX AFE control 1 ++ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; ++ ++ // RX AFE control 1 ++ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; ++ pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; ++ pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; ++ pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; ++ ++ // Tx AFE control 1 ++ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; ++ pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; ++ ++ // Tx AFE control 2 ++ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; ++ pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; ++ pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; ++ pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; ++ ++ // Tranceiver LSSI Readback SI mode ++ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; ++ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; ++ pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; ++ pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; ++ ++ // Tranceiver LSSI Readback PI mode ++ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; ++ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; ++ //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; ++ //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; ++ ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithParaFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * 2008/11/06 MH For 92S we do not support silent reset now. Disable ++ * parameter file compare!!!!!!?? ++ * ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ return rtStatus; ++} ++ ++ ++ ++//**************************************** ++// The following is for High Power PA ++//**************************************** ++VOID ++phy_ConfigBBExternalPA( ++ IN PADAPTER Adapter ++) ++{ ++#ifdef CONFIG_USB_HCI ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 i=0; ++ u32 temp=0; ++ ++ if(!pHalData->ExternalPA) ++ { ++ return; ++ } ++ ++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the ++ // same code as SU. It is already updated in PHY_REG_1T_HP.txt. ++#if 0 ++ PHY_SetBBReg(Adapter, 0xee8, BIT28, 1); ++ temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord); ++ temp |= (BIT26|BIT21|BIT10|BIT5); ++ PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp); ++ PHY_SetBBReg(Adapter, 0x870, BIT10, 0); ++ PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080); ++ PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100); ++#endif ++ ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithHeaderFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * u1Byte ConfigType 0 => PHY_CONFIG ++ * 1 =>AGC_TAB ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ *---------------------------------------------------------------------------*/ ++#ifndef CONFIG_PHY_SETTING_WITH_ODM ++static int ++phy_ConfigBBWithHeaderFile( ++ IN PADAPTER Adapter, ++ IN u8 ConfigType ++) ++{ ++ int i; ++ u32* Rtl819XPHY_REGArray_Table; ++ u32* Rtl819XAGCTAB_Array_Table; ++ u16 PHY_REGArrayLen, AGCTAB_ArrayLen; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++ int ret = _SUCCESS; ++ ++ ++ AGCTAB_ArrayLen = Rtl8188E_AGCTAB_1TArrayLength; ++ Rtl819XAGCTAB_Array_Table = (u32*)Rtl8188E_AGCTAB_1TArray; ++ PHY_REGArrayLen = Rtl8188E_PHY_REG_1TArrayLength; ++ Rtl819XPHY_REGArray_Table = (u32*)Rtl8188E_PHY_REG_1TArray; ++// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8188EAGCTAB_1TArray\n")); ++// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_1TArray\n")); ++ ++ if(ConfigType == CONFIG_BB_PHY_REG) ++ { ++ #ifdef CONFIG_IOL_BB_PHY_REG ++ { ++ struct xmit_frame *xmit_frame; ++ u32 tmp_value; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ for(i=0;iRFCalibrateInfo.RegA24 = Rtl819XPHY_REGArray_Table[i+1]; ++ ++ rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value); ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); ++ } ++ ++ ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); ++ } ++ #else ++ for(i=0;iRFCalibrateInfo.RegA24 = Rtl819XPHY_REGArray_Table[i+1]; ++ ++ PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); ++ ++ // Add 1us delay between BB/RF register setting. ++ rtw_udelay_os(1); ++ ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); ++ } ++ #endif ++ // for External PA ++ phy_ConfigBBExternalPA(Adapter); ++ } ++ else if(ConfigType == CONFIG_BB_AGC_TAB) ++ { ++ #ifdef CONFIG_IOL_BB_AGC_TAB ++ { ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ for(i=0;iMCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); ++ } ++ if(RegAddr == rTxAGC_A_Rate54_24) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]); ++ } ++ if(RegAddr == rTxAGC_A_CCK1_Mcs32) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]); ++ } ++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]); ++ } ++ if(RegAddr == rTxAGC_A_Mcs03_Mcs00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]); ++ } ++ if(RegAddr == rTxAGC_A_Mcs07_Mcs04) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]); ++ } ++ if(RegAddr == rTxAGC_A_Mcs11_Mcs08) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]); ++ } ++ if(RegAddr == rTxAGC_A_Mcs15_Mcs12) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]); ++ if(pHalData->rf_type== RF_1T1R) ++ { ++ //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); ++ pHalData->pwrGroupCnt++; ++ } ++ } ++ if(RegAddr == rTxAGC_B_Rate18_06) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]); ++ } ++ if(RegAddr == rTxAGC_B_Rate54_24) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]); ++ } ++ if(RegAddr == rTxAGC_B_CCK1_55_Mcs32) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]); ++ } ++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]); ++ } ++ if(RegAddr == rTxAGC_B_Mcs03_Mcs00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]); ++ } ++ if(RegAddr == rTxAGC_B_Mcs07_Mcs04) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]); ++ } ++ if(RegAddr == rTxAGC_B_Mcs11_Mcs08) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]); ++ } ++ if(RegAddr == rTxAGC_B_Mcs15_Mcs12) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; ++ //printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]); ++ ++ if(pHalData->rf_type != RF_1T1R) ++ { ++ //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); ++ pHalData->pwrGroupCnt++; ++ } ++ } ++} ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithPgParaFile ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/06/2008 MHC Create Version 0. ++ * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithPgParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ ++ return rtStatus; ++ ++} /* phy_ConfigBBWithPgParaFile */ ++ ++#ifndef CONFIG_PHY_SETTING_WITH_ODM ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithPgHeaderFile ++ * ++ * Overview: Config PHY_REG_PG array ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! ++ * 11/10/2008 tynli Modify to mew files. ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithPgHeaderFile( ++ IN PADAPTER Adapter, ++ IN u8 ConfigType) ++{ ++ int i; ++ u32* Rtl819XPHY_REGArray_Table_PG; ++ u16 PHY_REGArrayPGLen; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ ++ PHY_REGArrayPGLen = Rtl8188E_PHY_REG_Array_PGLength; ++ Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8188E_PHY_REG_Array_PG; ++ ++ if(ConfigType == CONFIG_BB_PHY_REG) ++ { ++ for(i=0;iphy_BB8192S_Config_ParaFile\n")); ++ ++ pszBBRegFile = sz8188EBBRegFile ; ++ pszAGCTableFile = sz8188EAGCTableFile; ++ pszBBRegPgFile = sz8188EBBRegPgFile; ++ pszBBRegMpFile = sz8188EBBRegMpFile; ++ ++ // ++ // 1. Read PHY_REG.TXT BB INIT!! ++ // We will seperate as 88C / 92C according to chip version ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) ++ rtStatus = _FAIL; ++ #else ++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_PHY_REG); ++ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM ++#else ++ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different ++ // type of parameter files to phy_reg.txt at first. ++ rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile); ++#endif//#ifdef CONFIG_EMBEDDED_FWIMG ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++ // ++ // 20100318 Joseph: Config 2T2R to 1T2R if necessary. ++ // ++ //if(pHalData->rf_type == RF_1T2R) ++ //{ ++ //phy_BB8192C_Config_1T(Adapter); ++ //DBG_8192C("phy_BB8188E_Config_ParaFile():Config to 1T!!\n"); ++ //} ++ ++ // ++ // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt ++ // ++ if (pEEPROM->bautoload_fail_flag == _FALSE) ++ { ++ pHalData->pwrGroupCnt = 0; ++ ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG)) ++ rtStatus = _FAIL; ++ #else ++ rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, CONFIG_BB_PHY_REG_PG); ++ #endif ++#else ++ rtStatus = phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile); ++#endif ++ } ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++ // ++ // 3. BB AGC table Initialization ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) ++ rtStatus = _FAIL; ++ #else ++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_AGC_TAB); ++ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM ++#else ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n")); ++ rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile); ++#endif//#ifdef CONFIG_EMBEDDED_FWIMG ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++ ++phy_BB8190_Config_ParaFile_Fail: ++ ++ return rtStatus; ++} ++ ++ ++int ++PHY_BBConfig8188E( ++ IN PADAPTER Adapter ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 RegVal; ++ u8 TmpU1B=0; ++ u8 value8,CrystalCap; ++ ++ phy_InitBBRFRegisterDefinition(Adapter); ++ ++ ++ // Enable BB and RF ++ RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); ++ ++ // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. ++ //rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); ++ //rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); ++ ++ rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); ++ ++#ifdef CONFIG_USB_HCI ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); ++#else ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); ++#endif ++ ++#if 0 ++#ifdef CONFIG_USB_HCI ++ //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. ++ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f); ++ rtw_write8(Adapter, 0x15, 0xe9); ++#endif ++ ++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ //rtw_write8(Adapter, 0x15, 0xe9); ++#endif ++ ++ ++#ifdef CONFIG_PCI_HCI ++ // Force use left antenna by default for 88C. ++ // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID)) ++ if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10) ++ { ++ RegVal = rtw_read32(Adapter, REG_LEDCFG0); ++ rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23); ++ } ++#endif ++ ++ // ++ // Config BB and AGC ++ // ++ rtStatus = phy_BB8188E_Config_ParaFile(Adapter); ++ ++ // write 0x24[16:11] = 0x24[22:17] = CrystalCap ++ CrystalCap = pHalData->CrystalCap & 0x3F; ++ PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); ++ ++ return rtStatus; ++ ++} ++ ++ ++int ++PHY_RFConfig8188E( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ int rtStatus = _SUCCESS; ++ ++ // ++ // RF config ++ // ++ rtStatus = PHY_RF6052_Config8188E(Adapter); ++#if 0 ++ switch(pHalData->rf_chip) ++ { ++ case RF_6052: ++ rtStatus = PHY_RF6052_Config(Adapter); ++ break; ++ case RF_8225: ++ rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ case RF_8256: ++ rtStatus = PHY_RF8256_Config(Adapter); ++ break; ++ case RF_8258: ++ break; ++ case RF_PSEUDO_11N: ++ rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch ++ break; ++ } ++#endif ++ return rtStatus; ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_ConfigRFWithParaFile() ++ * ++ * Overview: This function read RF parameters from general file format, and do RF 3-wire ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * RF_RADIO_PATH_E eRFPath ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: Delay may be required for RF configuration ++ *---------------------------------------------------------------------------*/ ++int ++rtl8188e_PHY_ConfigRFWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName, ++ RF_RADIO_PATH_E eRFPath ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ ++ return rtStatus; ++ ++} ++ ++//**************************************** ++// The following is for High Power PA ++//**************************************** ++#define HighPowerRadioAArrayLen 22 ++//This is for High power PA ++u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = { ++0x013,0x00029ea4, ++0x013,0x00025e74, ++0x013,0x00020ea4, ++0x013,0x0001ced0, ++0x013,0x00019f40, ++0x013,0x00014e70, ++0x013,0x000106a0, ++0x013,0x0000c670, ++0x013,0x000082a0, ++0x013,0x00004270, ++0x013,0x00000240, ++}; ++ ++int ++PHY_ConfigRFExternalPA( ++ IN PADAPTER Adapter, ++ RF_RADIO_PATH_E eRFPath ++) ++{ ++ int rtStatus = _SUCCESS; ++#ifdef CONFIG_USB_HCI ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 i=0; ++ ++ if(!pHalData->ExternalPA) ++ { ++ return rtStatus; ++ } ++ ++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the ++ // same code as SU. It is already updated in radio_a_1T_HP.txt. ++#if 0 ++ //add for SU High Power PA ++ for(i = 0;i PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); ++// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); ++ ++ switch (eRFPath) ++ { ++ case RF_PATH_A: ++ #ifdef CONFIG_IOL_RF_RF_PATH_A ++ { ++ struct xmit_frame *xmit_frame; ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { ++ rtStatus = _FAIL; ++ goto exit; ++ } ++ ++ for(i = 0;iPHYRegDef[eRFPath]; ++ u32 NewOffset = 0; ++ u32 DataAndAddr = 0; ++ ++ NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f; ++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF ++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); ++ } ++ } ++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); ++ } ++ #else ++ for(i = 0;iPHYRegDef[eRFPath]; ++ u32 NewOffset = 0; ++ u32 DataAndAddr = 0; ++ ++ NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f; ++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF ++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); ++ } ++ } ++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); ++ } ++ #else ++ for(i = 0;i actually we call PlatformStallExecution()) to do NdisStallExecution() ++ // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK ++ // to run at Dispatch level to achive it. ++ //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); ++ WriteData[i] &= 0xfff; ++ PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); ++ // TODO: we should not delay for such a long time. Ask SD3 ++ rtw_mdelay_os(10); ++ ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); ++ rtw_mdelay_os(10); ++ //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK); ++ break; ++ ++ default: ++ rtStatus = _FAIL; ++ break; ++ } ++ ++ ++ // ++ // Check whether readback data is correct ++ // ++ if(ulRegRead != WriteData[i]) ++ { ++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i])); ++ rtStatus = _FAIL; ++ break; ++ } ++ } ++ ++ return rtStatus; ++} ++ ++ ++VOID ++rtl8192c_PHY_GetHWRegOriginalValue( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // read rx initial gain ++ pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", ++ //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1], ++ //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3])); ++ ++ // read framesync ++ pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0); ++ pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n", ++ // rOFDM0_RxDetector3, pHalData->framesync)); ++} ++ ++ ++// ++// Description: ++// Map dBm into Tx power index according to ++// current HW model, for example, RF and PA, and ++// current wireless mode. ++// By Bruce, 2008-01-29. ++// ++static u8 ++phy_DbmToTxPwrIdx( ++ IN PADAPTER Adapter, ++ IN WIRELESS_MODE WirelessMode, ++ IN int PowerInDbm ++ ) ++{ ++ u8 TxPwrIdx = 0; ++ int Offset = 0; ++ ++ ++ // ++ // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to ++ // 3dbm, and OFDM HT equals to 0dbm repectively. ++ // Note: ++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. ++ // By Bruce, 2008-01-29. ++ // ++ switch(WirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ Offset = -7; ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ Offset = -8; ++ break; ++ default: ++ Offset = -8; ++ break; ++ } ++ ++ if((PowerInDbm - Offset) > 0) ++ { ++ TxPwrIdx = (u8)((PowerInDbm - Offset) * 2); ++ } ++ else ++ { ++ TxPwrIdx = 0; ++ } ++ ++ // Tx Power Index is too large. ++ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) ++ TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; ++ ++ return TxPwrIdx; ++} ++ ++// ++// Description: ++// Map Tx power index into dBm according to ++// current HW model, for example, RF and PA, and ++// current wireless mode. ++// By Bruce, 2008-01-29. ++// ++int ++phy_TxPwrIdxToDbm( ++ IN PADAPTER Adapter, ++ IN WIRELESS_MODE WirelessMode, ++ IN u8 TxPwrIdx ++ ) ++{ ++ int Offset = 0; ++ int PwrOutDbm = 0; ++ ++ // ++ // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. ++ // Note: ++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. ++ // By Bruce, 2008-01-29. ++ // ++ switch(WirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ Offset = -7; ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ Offset = -8; ++ default: ++ Offset = -8; ++ break; ++ } ++ ++ PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. ++ ++ return PwrOutDbm; ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: GetTxPowerLevel8190() ++ * ++ * Overview: This function is export to "common" moudule ++ * ++ * Input: PADAPTER Adapter ++ * psByte Power Level ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_GetTxPowerLevel8188E( ++ IN PADAPTER Adapter, ++ OUT u32* powerlevel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 TxPwrLevel = 0; ++ int TxPwrDbm; ++ ++ // ++ // Because the Tx power indexes are different, we report the maximum of them to ++ // meet the CCX TPC request. By Bruce, 2008-01-31. ++ // ++ ++ // CCK ++ TxPwrLevel = pHalData->CurrentCckTxPwrIdx; ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel); ++ ++ // Legacy OFDM ++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff; ++ ++ // Compare with Legacy OFDM Tx power. ++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel); ++ ++ // HT OFDM ++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx; ++ ++ // Compare with HT OFDM Tx power. ++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel); ++ ++ *powerlevel = TxPwrDbm; ++} ++ ++#if 0 ++static void getTxPowerIndex( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN OUT u8* cckPowerLevel, ++ IN OUT u8* ofdmPowerLevel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 index = (channel -1); ++ // 1. CCK ++ cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A ++ cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B ++ ++ // 2. OFDM for 1S or 2S ++ if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R) ++ { ++ // Read HT 40 OFDM TX power ++ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index]; ++ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index]; ++ } ++ else if (GET_RF_TYPE(Adapter) == RF_2T2R) ++ { ++ // Read HT 40 OFDM TX power ++ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index]; ++ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index]; ++ } ++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel)); ++} ++#endif ++ ++void getTxPowerIndex88E( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN OUT u8* cckPowerLevel, ++ IN OUT u8* ofdmPowerLevel, ++ IN OUT u8* BW20PowerLevel, ++ IN OUT u8* BW40PowerLevel ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 index = (channel -1); ++ u8 TxCount=0,path_nums; ++ ++ ++ if((RF_1T2R == pHalData->rf_type) ||(RF_1T1R ==pHalData->rf_type )) ++ path_nums = 1; ++ else ++ path_nums = 2; ++ ++ for(TxCount=0;TxCount< path_nums ;TxCount++) ++ { ++ if(TxCount==RF_PATH_A) ++ { ++ // 1. CCK ++ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; ++ //2. OFDM ++ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A]; ++ // 1. BW20 ++ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]; ++ //2. BW40 ++ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; ++ //RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x 20Mdiff=%d 20MBase=0x%x!!\n", ++ // pHalData->Index24G_BW40_Base[RF_PATH_A][index], ++ // pHalData->BW20_24G_Diff[TxCount][RF_PATH_A], ++ // BW20PowerLevel[TxCount])); ++ } ++ else if(TxCount==RF_PATH_B) ++ { ++ // 1. CCK ++ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; ++ //2. OFDM ++ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ // 1. BW20 ++ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ //2. BW40 ++ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; ++ } ++ else if(TxCount==RF_PATH_C) ++ { ++ // 1. CCK ++ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; ++ //2. OFDM ++ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ // 1. BW20 ++ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ //2. BW40 ++ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; ++ } ++ else if(TxCount==RF_PATH_D) ++ { ++ // 1. CCK ++ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; ++ //2. OFDM ++ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_C][index]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ ++ // 1. BW20 ++ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ ++ pHalData->BW20_24G_Diff[RF_PATH_C][index]+ ++ pHalData->BW20_24G_Diff[TxCount][index]; ++ ++ //2. BW40 ++ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; ++ } ++ else ++ { ++ } ++ } ++ ++#if 0 // (INTEL_PROXIMITY_SUPPORT == 1) ++ switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){ ++ case 1: // 100% ++ break; ++ case 2: // 70% ++ cckPowerLevel[0] -= 3; ++ cckPowerLevel[1] -= 3; ++ ofdmPowerLevel[0] -=3; ++ ofdmPowerLevel[1] -= 3; ++ break; ++ case 3: // 50% ++ cckPowerLevel[0] -= 6; ++ cckPowerLevel[1] -= 6; ++ ofdmPowerLevel[0] -=6; ++ ofdmPowerLevel[1] -= 6; ++ break; ++ case 4: // 35% ++ cckPowerLevel[0] -= 9; ++ cckPowerLevel[1] -= 9; ++ ofdmPowerLevel[0] -=9; ++ ofdmPowerLevel[1] -= 9; ++ break; ++ case 5: // 15% ++ cckPowerLevel[0] -= 17; ++ cckPowerLevel[1] -= 17; ++ ofdmPowerLevel[0] -=17; ++ ofdmPowerLevel[1] -= 17; ++ break; ++ ++ default: ++ break; ++ } ++#endif ++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel)); ++} ++ ++void phy_PowerIndexCheck88E( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN OUT u8 * cckPowerLevel, ++ IN OUT u8 * ofdmPowerLevel, ++ IN OUT u8 * BW20PowerLevel, ++ IN OUT u8 * BW40PowerLevel ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#if 0 // (CCX_SUPPORT == 1) ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo); ++ ++ // ++ // CCX 2 S31, AP control of client transmit power: ++ // 1. We shall not exceed Cell Power Limit as possible as we can. ++ // 2. Tolerance is +/- 5dB. ++ // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. ++ // ++ // TODO: ++ // 1. 802.11h power contraint ++ // ++ // 071011, by rcnjko. ++ // ++ if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && ++ pMgntInfo->mAssoc && ++ pCcxInfo->bUpdateCcxPwr && ++ pCcxInfo->bWithCcxCellPwr && ++ channel == pMgntInfo->dot11CurrentChannelNumber) ++ { ++ u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr); ++ u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr); ++ u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr); ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); ++ ++ // CCK ++ if(cckPowerLevel[0] > CckCellPwrIdx) ++ cckPowerLevel[0] = CckCellPwrIdx; ++ // Legacy OFDM, HT OFDM ++ if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx) ++ { ++ if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0) ++ { ++ ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff; ++ } ++ else ++ { ++ ofdmPowerLevel[0] = 0; ++ } ++ } ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", ++ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); ++ } ++#else ++ // Add or not ??? ++#endif ++ ++ pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; ++ pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; ++ pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0]; ++ pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0]; ++ ++ //DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x \n", ++ // pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx); ++} ++/*----------------------------------------------------------------------------- ++ * Function: SetTxPowerLevel8190() ++ * ++ * Overview: This function is export to "HalCommon" moudule ++ * We must consider RF path later!!!!!!! ++ * ++ * Input: PADAPTER Adapter ++ * u1Byte channel ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * 2008/11/04 MHC We remove EEPROM_93C56. ++ * We need to move CCX relative code to independet file. ++ * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_SetTxPowerLevel8188E( ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ u8 cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];// [0]:RF-A, [1]:RF-B ++ u8 BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; ++ u8 i=0; ++/* ++#if(MP_DRIVER == 1) ++ if (Adapter->registrypriv.mp_mode == 1) ++ return; ++#endif ++*/ ++ //getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); ++ getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]); ++ ++ //printk("Channel-%d, cckPowerLevel = 0x%x, ofdmPowerLeve = 0x%x, BW20PowerLevel = 0x%x, BW40PowerLevel = 0x%x,\n", ++ // channel, cckPowerLevel[0], ofdmPowerLevel[0], BW20PowerLevel[0] ,BW40PowerLevel[0]); ++ ++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", ++ // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1])); ++ ++ //ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); ++ phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]); ++ ++ rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); ++ rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel); ++ ++#if 0 ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]); ++ PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]); ++ break; ++ ++ case RF_8256: ++ PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]); ++ PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]); ++ break; ++ ++ case RF_6052: ++ PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); ++ PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); ++ break; ++ ++ case RF_8258: ++ break; ++ } ++#endif ++ ++} ++ ++ ++// ++// Description: ++// Update transmit power level of all channel supported. ++// ++// TODO: ++// A mode. ++// By Bruce, 2008-02-04. ++// ++BOOLEAN ++PHY_UpdateTxPowerDbm8188E( ++ IN PADAPTER Adapter, ++ IN int powerInDbm ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 idx; ++ u8 rf_path; ++ ++ // TODO: A mode Tx power. ++ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm); ++ u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm); ++ ++ if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0) ++ OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff; ++ else ++ OfdmTxPwrIdx = 0; ++ ++ //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); ++ ++ for(idx = 0; idx < 14; idx++) ++ { ++ for (rf_path = 0; rf_path < 2; rf_path++) ++ { ++ pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; ++ pHalData->TxPwrLevelHT40_1S[rf_path][idx] = ++ pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx; ++ } ++ } ++ ++ //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo ++ ++ return _TRUE; ++} ++ ++ ++/* ++ Description: ++ When beacon interval is changed, the values of the ++ hw registers should be modified. ++ By tynli, 2008.10.24. ++ ++*/ ++ ++ ++void ++rtl8192c_PHY_SetBeaconHwReg( ++ IN PADAPTER Adapter, ++ IN u16 BeaconInterval ++ ) ++{ ++ ++} ++ ++ ++VOID ++PHY_ScanOperationBackup8188E( ++ IN PADAPTER Adapter, ++ IN u8 Operation ++ ) ++{ ++#if 0 ++ IO_TYPE IoType; ++ ++ if(!Adapter->bDriverStopped) ++ { ++ switch(Operation) ++ { ++ case SCAN_OPT_BACKUP: ++ IoType = IO_CMD_PAUSE_DM_BY_SCAN; ++ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); ++ ++ break; ++ ++ case SCAN_OPT_RESTORE: ++ IoType = IO_CMD_RESUME_DM_BY_SCAN; ++ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); ++ break; ++ ++ default: ++ RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n")); ++ break; ++ } ++ } ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_SetBWModeCallback8192C() ++ * ++ * Overview: Timer callback function for SetSetBWMode ++ * ++ * Input: PRT_TIMER pTimer ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: (1) We do not take j mode into consideration now ++ * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run ++ * concurrently? ++ *---------------------------------------------------------------------------*/ ++static VOID ++_PHY_SetBWMode92C( ++ IN PADAPTER Adapter ++) ++{ ++// PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 regBwOpMode; ++ u8 regRRSR_RSC; ++ ++ //return; ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //u4Byte NowL, NowH; ++ //u8Byte BeginTime, EndTime; ++ ++ /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \ ++ pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/ ++ ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SetBWModeInProgress= _FALSE; ++ return; ++ } ++ ++ // There is no 40MHz mode in RF_8225. ++ if(pHalData->rf_chip==RF_8225) ++ return; ++ ++ if(Adapter->bDriverStopped) ++ return; ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR); ++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); ++ //BeginTime = ((u8Byte)NowH << 32) + NowL; ++ ++ //3// ++ //3//<1>Set MAC register ++ //3// ++ //Adapter->HalFunc.SetBWModeHandler(); ++ ++ regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE); ++ regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2); ++ //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode); ++ ++ switch(pHalData->CurrentChannelBW) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ regBwOpMode |= BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); ++ break; ++ ++ case HT_CHANNEL_WIDTH_40: ++ regBwOpMode &= ~BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); ++ ++ regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5); ++ rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC); ++ break; ++ ++ default: ++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): ++ unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/ ++ break; ++ } ++ ++ //3// ++ //3//<2>Set PHY related register ++ //3// ++ switch(pHalData->CurrentChannelBW) ++ { ++ /* 20 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20: ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); ++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); ++ //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); ++ ++ break; ++ ++ ++ /* 40 MHz channel*/ ++ case HT_CHANNEL_WIDTH_40: ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); ++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); ++ ++ // Set Control channel to upper or lower. These settings are required only for 40MHz ++ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); ++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); ++ //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); ++ ++ PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1); ++ ++ break; ++ ++ ++ ++ default: ++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\ ++ ,pHalData->CurrentChannelBW));*/ ++ break; ++ ++ } ++ //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR); ++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); ++ //EndTime = ((u8Byte)NowH << 32) + NowL; ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); ++ ++ //3<3>Set RF related register ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ case RF_8256: ++ // Please implement this function in Hal8190PciPhy8256.c ++ //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ case RF_8258: ++ // Please implement this function in Hal8190PciPhy8258.c ++ // PHY_SetRF8258Bandwidth(); ++ break; ++ ++ case RF_PSEUDO_11N: ++ // Do Nothing ++ break; ++ ++ case RF_6052: ++ rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ default: ++ //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); ++ break; ++ } ++ ++ //pHalData->SetBWModeInProgress= FALSE; ++ ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" )); ++} ++ ++ ++ /*----------------------------------------------------------------------------- ++ * Function: SetBWMode8190Pci() ++ * ++ * Overview: This function is export to "HalCommon" moudule ++ * ++ * Input: PADAPTER Adapter ++ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: We do not take j mode into consideration now ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_SetBWMode8188E( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M ++ IN unsigned char Offset // Upper, Lower, or Don't care ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW; ++ // Modified it for 20/40 mhz switch by guangan 070531 ++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; ++ ++ //return; ++ ++ //if(pHalData->SwChnlInProgress) ++// if(pMgntInfo->bScanInProgress) ++// { ++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n", ++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); ++// return; ++// } ++ ++// if(pHalData->SetBWModeInProgress) ++// { ++// // Modified it for 20/40 mhz switch by guangan 070531 ++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n", ++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); ++// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer); ++// //return; ++// } ++ ++ //if(pHalData->SetBWModeInProgress) ++ // return; ++ ++ //pHalData->SetBWModeInProgress= TRUE; ++ ++ pHalData->CurrentChannelBW = Bandwidth; ++ ++#if 0 ++ if(Offset==HT_EXTCHNL_OFFSET_LOWER) ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; ++ else if(Offset==HT_EXTCHNL_OFFSET_UPPER) ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; ++ else ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++#else ++ pHalData->nCur40MhzPrimeSC = Offset; ++#endif ++ ++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) ++ { ++ #if 0 ++ //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0); ++ #else ++ _PHY_SetBWMode92C(Adapter); ++ #endif ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n")); ++ //pHalData->SetBWModeInProgress= FALSE; ++ pHalData->CurrentChannelBW = tmpBW; ++ } ++ ++} ++ ++ ++static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel) ++{ ++ u8 eRFPath; ++ u32 param1, param2; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if ( Adapter->bNotifyChannelChange ) ++ { ++ DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel ); ++ } ++ ++ //s1. pre common command - CmdID_SetTxPowerLevel ++ PHY_SetTxPowerLevel8188E(Adapter, channel); ++ ++ //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel ++ param1 = RF_CHNLBW; ++ param2 = channel; ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2); ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); ++ } ++ ++ ++ //s3. post common command - CmdID_End, None ++ ++} ++// <20130708, James> A workaround to eliminate the 2480MHz spur for 8188E I-Cut ++void ++phy_SpurCalibration_8188E( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel); ++ if(pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13){ ++ PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); //enable CSI Mask ++ PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x3); //Fix CSI Mask Tone ++ } ++ else{ ++ PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x0); //disable CSI Mask ++ PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x0); ++ } ++ ++} ++VOID ++PHY_SwChnl8188E( // Call after initialization ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 tmpchannel = pHalData->CurrentChannel; ++ BOOLEAN bResult = _TRUE; ++ ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SwChnlInProgress=FALSE; ++ return; //return immediately if it is peudo-phy ++ } ++ ++ //if(pHalData->SwChnlInProgress) ++ // return; ++ ++ //if(pHalData->SetBWModeInProgress) ++ // return; ++ ++ //-------------------------------------------- ++ switch(pHalData->CurrentWirelessMode) ++ { ++ case WIRELESS_MODE_A: ++ case WIRELESS_MODE_N_5G: ++ //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); ++ break; ++ ++ case WIRELESS_MODE_B: ++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); ++ break; ++ ++ default: ++ //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); ++ break; ++ } ++ //-------------------------------------------- ++ ++ //pHalData->SwChnlInProgress = TRUE; ++ if(channel == 0) ++ channel = 1; ++ ++ pHalData->CurrentChannel=channel; ++ ++ //pHalData->SwChnlStage=0; ++ //pHalData->SwChnlStep=0; ++ ++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) ++ { ++ #if 0 ++ //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0); ++ #else ++ _PHY_SwChnl8192C(Adapter, channel); ++ #endif ++ if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter)) ++ phy_SpurCalibration_8188E( Adapter); ++ if(bResult) ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n")); ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n")); ++ //if(IS_HARDWARE_TYPE_8192SU(Adapter)) ++ //{ ++ // pHalData->SwChnlInProgress = FALSE; ++ pHalData->CurrentChannel = tmpchannel; ++ //} ++ } ++ ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n")); ++ //if(IS_HARDWARE_TYPE_8192SU(Adapter)) ++ //{ ++ // pHalData->SwChnlInProgress = FALSE; ++ pHalData->CurrentChannel = tmpchannel; ++ //} ++ } ++} ++ ++ ++static BOOLEAN ++phy_SwChnlStepByStep( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN u8 *stage, ++ IN u8 *step, ++ OUT u32 *delay ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PCHANNEL_ACCESS_SETTING pChnlAccessSetting; ++ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; ++ u4Byte PreCommonCmdCnt; ++ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; ++ u4Byte PostCommonCmdCnt; ++ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; ++ u4Byte RfDependCmdCnt; ++ SwChnlCmd *CurrentCmd; ++ u1Byte eRFPath; ++ u4Byte RfTXPowerCtrl; ++ BOOLEAN bAdjRfTXPowerCtrl = _FALSE; ++ ++ ++ RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n")); ++#if(MP_DRIVER != 1) ++ RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); ++#endif ++ RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n")); ++ ++ pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting; ++ RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n")); ++ ++ //for(eRFPath = RF_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ //{ ++ // <1> Fill up pre common command. ++ PreCommonCmdCnt = 0; ++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_SetTxPowerLevel, 0, 0, 0); ++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <2> Fill up post common command. ++ PostCommonCmdCnt = 0; ++ ++ phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <3> Fill up RF dependent command. ++ RfDependCmdCnt = 0; ++ switch( pHalData->RFChipID ) ++ { ++ case RF_8225: ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ // 2008/09/04 MH Change channel. ++ if(channel==14) channel++; ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_8256: ++ // TEST!! This is not the table for 8256!! ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rRfChannel, channel, 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_6052: ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, RF_CHNLBW, channel, 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ break; ++ ++ case RF_8258: ++ break; ++ ++ // For FPGA two MAC verification ++ case RF_PSEUDO_11N: ++ return TRUE; ++ default: ++ RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); ++ return FALSE; ++ break; ++ } ++ ++ ++ do{ ++ switch(*stage) ++ { ++ case 0: ++ CurrentCmd=&PreCommonCmd[*step]; ++ break; ++ case 1: ++ CurrentCmd=&RfDependCmd[*step]; ++ break; ++ case 2: ++ CurrentCmd=&PostCommonCmd[*step]; ++ break; ++ } ++ ++ if(CurrentCmd->CmdID==CmdID_End) ++ { ++ if((*stage)==2) ++ { ++ return TRUE; ++ } ++ else ++ { ++ (*stage)++; ++ (*step)=0; ++ continue; ++ } ++ } ++ ++ switch(CurrentCmd->CmdID) ++ { ++ case CmdID_SetTxPowerLevel: ++ PHY_SetTxPowerLevel8192C(Adapter,channel); ++ break; ++ case CmdID_WritePortUlong: ++ PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUshort: ++ PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUchar: ++ PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2); ++ break; ++ case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++#if 1 ++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2); ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); ++#else ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2)); ++#endif ++ } ++ break; ++ } ++ ++ break; ++ }while(TRUE); ++ //cosa }/*for(Number of RF paths)*/ ++ ++ (*delay)=CurrentCmd->msDelay; ++ (*step)++; ++ return FALSE; ++#endif ++ return _TRUE; ++} ++ ++ ++static BOOLEAN ++phy_SetSwChnlCmdArray( ++ SwChnlCmd* CmdTable, ++ u32 CmdTableIdx, ++ u32 CmdTableSz, ++ SwChnlCmdID CmdID, ++ u32 Para1, ++ u32 Para2, ++ u32 msDelay ++ ) ++{ ++ SwChnlCmd* pCmd; ++ ++ if(CmdTable == NULL) ++ { ++ //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); ++ return _FALSE; ++ } ++ if(CmdTableIdx >= CmdTableSz) ++ { ++ //RT_ASSERT(FALSE, ++ // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", ++ // CmdTableIdx, CmdTableSz)); ++ return _FALSE; ++ } ++ ++ pCmd = CmdTable + CmdTableIdx; ++ pCmd->CmdID = CmdID; ++ pCmd->Para1 = Para1; ++ pCmd->Para2 = Para2; ++ pCmd->msDelay = msDelay; ++ ++ return _TRUE; ++} ++ ++ ++static void ++phy_FinishSwChnlNow( // We should not call this function directly ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 delay; ++ ++ while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay)) ++ { ++ if(delay>0) ++ rtw_mdelay_os(delay); ++ } ++#endif ++} ++ ++ ++ ++// ++// Description: ++// Switch channel synchronously. Called by SwChnlByDelayHandler. ++// ++// Implemented by Bruce, 2008-02-14. ++// The following procedure is operted according to SwChanlCallback8190Pci(). ++// However, this procedure is performed synchronously which should be running under ++// passive level. ++// ++VOID ++PHY_SwChnlPhy8192C( // Only called during initialize ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); ++ ++ // Cannot IO. ++ //if(RT_CANNOT_IO(Adapter)) ++ // return; ++ ++ // Channel Switching is in progress. ++ //if(pHalData->SwChnlInProgress) ++ // return; ++ ++ //return immediately if it is peudo-phy ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SwChnlInProgress=FALSE; ++ return; ++ } ++ ++ //pHalData->SwChnlInProgress = TRUE; ++ if( channel == 0) ++ channel = 1; ++ ++ pHalData->CurrentChannel=channel; ++ ++ //pHalData->SwChnlStage = 0; ++ //pHalData->SwChnlStep = 0; ++ ++ phy_FinishSwChnlNow(Adapter,channel); ++ ++ //pHalData->SwChnlInProgress = FALSE; ++} ++ ++ ++// ++// Description: ++// Configure H/W functionality to enable/disable Monitor mode. ++// Note, because we possibly need to configure BB and RF in this function, ++// so caller should in PASSIVE_LEVEL. 080118, by rcnjko. ++// ++VOID ++PHY_SetMonitorMode8192C( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN bFilterOutNonAssociatedBSSID = FALSE; ++ ++ //2 Note: we may need to stop antenna diversity. ++ if(bEnableMonitorMode) ++ { ++ bFilterOutNonAssociatedBSSID = FALSE; ++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n")); ++ ++ pHalData->bInMonitorMode = TRUE; ++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE); ++ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); ++ } ++ else ++ { ++ bFilterOutNonAssociatedBSSID = TRUE; ++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n")); ++ ++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE); ++ pHalData->bInMonitorMode = FALSE; ++ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); ++ } ++#endif ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHYCheckIsLegalRfPath8190Pci() ++ * ++ * Overview: Check different RF type to execute legal judgement. If RF Path is illegal ++ * We will return false. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/15/2007 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++BOOLEAN ++PHY_CheckIsLegalRfPath8192C( ++ IN PADAPTER pAdapter, ++ IN u32 eRFPath) ++{ ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN rtValue = _TRUE; ++ ++ // NOt check RF Path now.! ++#if 0 ++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A) ++ { ++ rtValue = FALSE; ++ } ++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A) ++ { ++ ++ } ++#endif ++ return rtValue; ++ ++} /* PHY_CheckIsLegalRfPath8192C */ ++ ++static VOID _PHY_SetRFPathSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bMain, ++ IN BOOLEAN is2T ++ ) ++{ ++ u8 u1bTmp; ++ ++ if(!pAdapter->hw_init_completed) ++ { ++ u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7; ++ rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp); ++ //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++ if(is2T) ++ { ++ if(bMain) ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A ++ else ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT ++ } ++ else ++ { ++ ++ if(bMain) ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main ++ else ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux ++ } ++ ++} ++ ++//return value TRUE => Main; FALSE => Aux ++ ++static BOOLEAN _PHY_QueryRFPathSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++// if(is2T) ++// return _TRUE; ++ ++ if(!pAdapter->hw_init_completed) ++ { ++ PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++ if(is2T) ++ { ++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) ++ return _TRUE; ++ else ++ return _FALSE; ++ } ++ else ++ { ++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02) ++ return _TRUE; ++ else ++ return _FALSE; ++ } ++} ++ ++ ++static VOID ++_PHY_DumpRFReg(IN PADAPTER pAdapter) ++{ ++ u32 rfRegValue,rfRegOffset; ++ ++ //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); ++ ++ for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){ ++ rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord); ++ //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); ++ } ++ //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n")); ++} ++ ++ ++// ++// Move from phycfg.c to gen.c to be code independent later ++// ++//-------------------------Move to other DIR later----------------------------*/ ++#ifdef CONFIG_USB_HCI ++ ++// ++// Description: ++// To dump all Tx FIFO LLT related link-list table. ++// Added by Roger, 2009.03.10. ++// ++VOID ++DumpBBDbgPort_92CU( ++ IN PADAPTER Adapter ++ ) ++{ ++ ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n")); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n")); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); ++ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); ++ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord))); ++ ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rf6052.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rf6052.c +new file mode 100644 +index 00000000..33f63978 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rf6052.c +@@ -0,0 +1,1272 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192c_rf6052.c ( Source C File) ++ * ++ * Note: Provide RF 6052 series relative API. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * 11/05/2008 MHC Add API for tw power setting. ++ * ++ * ++******************************************************************************/ ++ ++#define _RTL8188E_RF6052_C_ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/*---------------------------Define Local Constant---------------------------*/ ++// Define local structure for debug!!!!! ++typedef struct RF_Shadow_Compare_Map { ++ // Shadow register value ++ u32 Value; ++ // Compare or not flag ++ u8 Compare; ++ // Record If it had ever modified unpredicted ++ u8 ErrorOrNot; ++ // Recorver Flag ++ u8 Recorver; ++ // ++ u8 Driver_Write; ++}RF_SHADOW_T; ++/*---------------------------Define Local Constant---------------------------*/ ++ ++ ++/*------------------------Define global variable-----------------------------*/ ++/*------------------------Define global variable-----------------------------*/ ++ ++ ++/*------------------------Define local variable------------------------------*/ ++// 2008/11/20 MH For Debug only, RF ++//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; ++static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; ++/*------------------------Define local variable------------------------------*/ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: RF_ChangeTxPath ++ * ++ * Overview: For RL6052, we must change some RF settign for 1T or 2T. ++ * ++ * Input: u2Byte DataRate // 0x80-8f, 0x90-9f ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/25/2008 MHC Create Version 0. ++ * Firmwaer support the utility later. ++ * ++ *---------------------------------------------------------------------------*/ ++void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate) ++{ ++// We do not support gain table change inACUT now !!!! Delete later !!! ++#if 0//(RTL92SE_FPGA_VERIFY == 0) ++ static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T ++ static u4Byte tx_gain_tbl1[6] ++ = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; ++ static u4Byte tx_gain_tbl2[6] ++ = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; ++ u1Byte i; ++ ++ if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) ++ { ++ // Set TX SYNC power G2G3 loop filter ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x0f000); ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1); ++ ++ // Change TX AGC gain table ++ for (i = 0; i < 6; i++) ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]); ++ ++ // Set PA to high value ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e39); ++ } ++ else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) ++ { ++ // Set TX SYNC power G2G3 loop filter ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x04440); ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1); ++ ++ // Change TX AGC gain table ++ for (i = 0; i < 6; i++) ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]); ++ ++ // Set PA low gain ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e19); ++ } ++#endif ++ ++} /* RF_ChangeTxPath */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetBandwidth() ++ * ++ * Overview: This function is called by SetBWModeCallback8190Pci() only ++ * ++ * Input: PADAPTER Adapter ++ * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: For RF type 0222D ++ *---------------------------------------------------------------------------*/ ++VOID ++rtl8188e_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ switch(Bandwidth) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11)); ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); ++ break; ++ ++ case HT_CHANNEL_WIDTH_40: ++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10)); ++ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); ++ break; ++ ++ default: ++ //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); ++ break; ++ } ++ ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetCckTxPower ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/05/2008 MHC Simulate 8192series.. ++ * ++ *---------------------------------------------------------------------------*/ ++ ++VOID ++rtl8188e_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; ++ u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value; ++ BOOLEAN TurboScanOff = _FALSE; ++ u8 idx1, idx2; ++ u8* ptr; ++ u8 direction; ++ //FOR CE ,must disable turbo scan ++ TurboScanOff = _TRUE; ++ ++ ++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ TxAGC[RF_PATH_A] = 0x3f3f3f3f; ++ TxAGC[RF_PATH_B] = 0x3f3f3f3f; ++ ++ TurboScanOff = _TRUE;//disable turbo scan ++ ++ if(TurboScanOff) ++ { ++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) ++ { ++ TxAGC[idx1] = ++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | ++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); ++#ifdef CONFIG_USB_HCI ++ // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. ++ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) ++ TxAGC[idx1] = 0x20; ++#endif ++ } ++ } ++ } ++ else ++ { ++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. ++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. ++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ { ++ TxAGC[RF_PATH_A] = 0x10101010; ++ TxAGC[RF_PATH_B] = 0x10101010; ++ } ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ { ++ TxAGC[RF_PATH_A] = 0x00000000; ++ TxAGC[RF_PATH_B] = 0x00000000; ++ } ++ else ++ { ++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) ++ { ++ TxAGC[idx1] = ++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | ++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); ++ } ++ ++ if(pHalData->EEPROMRegulatory==0) ++ { ++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + ++ (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); ++ TxAGC[RF_PATH_A] += tmpval; ++ ++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + ++ (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); ++ TxAGC[RF_PATH_B] += tmpval; ++ } ++ } ++ } ++ ++ ++ ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); ++ //printk("ODM_TxPwrTrackAdjust88E => direction:%02x, pwrtrac_value:%d \n", direction, pwrtrac_value); ++ //printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); ++ ++ if (direction == 1) // Increase TX pwoer ++ { ++ TxAGC[0] += pwrtrac_value; ++ TxAGC[1] += pwrtrac_value; ++ ++ } ++ else if (direction == 2) // Decrease TX pwoer ++ { ++ TxAGC[0] -= pwrtrac_value; ++ TxAGC[1] -= pwrtrac_value; ++ } ++ ++ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) ++ { ++ ptr = (u8*)(&(TxAGC[idx1])); ++ for(idx2=0; idx2<4; idx2++) ++ { ++ if(*ptr > RF6052_MAX_TX_PWR) ++ *ptr = RF6052_MAX_TX_PWR; ++ ptr++; ++ } ++ } ++ //printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); ++ ++ // rf-A cck tx power ++ tmpval = TxAGC[RF_PATH_A]&0xff; ++ PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); ++ //printk("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32); ++ ++ ++ tmpval = TxAGC[RF_PATH_A]>>8; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); ++ //printk("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); ++ ++/* ++ // rf-B cck tx power ++ tmpval = TxAGC[RF_PATH_B]>>24; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); ++ //printk("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); ++ tmpval = TxAGC[RF_PATH_B]&0x00ffffff; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); ++ //printk("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",tmpval, rTxAGC_B_CCK1_55_Mcs32); ++*/ ++} /* PHY_RF6052SetCckTxPower */ ++ ++#if 0 ++// ++// powerbase0 for OFDM rates ++// powerbase1 for HT MCS rates ++// ++static void getPowerBase( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel, ++ IN OUT u32* OfdmBase, ++ IN OUT u32* MCSBase ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 powerBase0, powerBase1; ++ u8 Legacy_pwrdiff=0, HT20_pwrdiff=0; ++ u8 i, powerlevel[2]; ++ ++ for(i=0; i<2; i++) ++ { ++ powerlevel[i] = pPowerLevel[i]; ++ Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1]; ++ powerBase0 = powerlevel[i] + Legacy_pwrdiff; ++ ++ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; ++ *(OfdmBase+i) = powerBase0; ++ //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i))); ++ } ++ ++ for(i=0; i<2; i++) ++ { ++ //Check HT20 to HT40 diff ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ { ++ HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1]; ++ powerlevel[i] += HT20_pwrdiff; ++ } ++ powerBase1 = powerlevel[i]; ++ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; ++ *(MCSBase+i) = powerBase1; ++ //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i))); ++ } ++} ++#endif ++// ++// powerbase0 for OFDM rates ++// powerbase1 for HT MCS rates ++// ++void getPowerBase88E( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevelOFDM, ++ IN u8* pPowerLevelBW20, ++ IN u8* pPowerLevelBW40, ++ IN u8 Channel, ++ IN OUT u32* OfdmBase, ++ IN OUT u32* MCSBase ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 powerBase0, powerBase1; ++ u8 Legacy_pwrdiff=0; ++ s8 HT20_pwrdiff=0; ++ u8 i, powerlevel[2]; ++ ++ for(i=0; i<2; i++) ++ { ++ powerBase0 = pPowerLevelOFDM[i]; ++ ++ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; ++ *(OfdmBase+i) = powerBase0; ++ //DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)); ++ } ++ ++ for(i=0; iNumTotalRFPath; i++) ++ { ++ //Check HT20 to HT40 diff ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ { ++ powerlevel[i] = pPowerLevelBW20[i]; ++ } ++ else ++ { ++ powerlevel[i] = pPowerLevelBW40[i]; ++ } ++ powerBase1 = powerlevel[i]; ++ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; ++ *(MCSBase+i) = powerBase1; ++ //DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)); ++ } ++} ++#if 0 ++static void getTxPowerWriteValByRegulatory( ++ IN PADAPTER Adapter, ++ IN u8 Channel, ++ IN u8 index, ++ IN u32* powerBase0, ++ IN u32* powerBase1, ++ OUT u32* pOutWriteVal ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 i, chnlGroup, pwr_diff_limit[4]; ++ u32 writeVal, customer_limit, rf; ++ ++ // ++ // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate ++ // ++ for(rf=0; rf<2; rf++) ++ { ++ switch(pHalData->EEPROMRegulatory) ++ { ++ case 0: // Realtek better performance ++ // increase power diff defined by Realtek for large power ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 1: // Realtek regulatory ++ // increase power diff defined by Realtek for regulatory ++ { ++ if(pHalData->pwrGroupCnt == 1) ++ chnlGroup = 0; ++ if(pHalData->pwrGroupCnt >= 3) ++ { ++ if(Channel <= 3) ++ chnlGroup = 0; ++ else if(Channel >= 4 && Channel <= 9) ++ chnlGroup = 1; ++ else if(Channel > 9) ++ chnlGroup = 2; ++ ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ chnlGroup++; ++ else ++ chnlGroup+=4; ++ } ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ } ++ break; ++ case 2: // Better regulatory ++ // don't increase any power diff ++ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 3: // Customer defined power diff. ++ // increase power diff defined by customer. ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) ++ { ++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n", ++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1])); ++ } ++ else ++ { ++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n", ++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1])); ++ } ++ for (i=0; i<4; i++) ++ { ++ pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8)); ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) ++ { ++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1]) ++ pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1]; ++ } ++ else ++ { ++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1]) ++ pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1]; ++ } ++ } ++ customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | ++ (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); ++ ++ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ default: ++ chnlGroup = 0; ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ } ++ ++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. ++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. ++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. ++ ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ writeVal = 0x14141414; ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ writeVal = 0x00000000; ++ ++ ++ // 20100628 Joseph: High power mode for BT-Coexist mechanism. ++ // This mechanism is only applied when Driver-Highpower-Mechanism is OFF. ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); ++ writeVal = writeVal - 0x06060606; ++ } ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); ++ writeVal = writeVal; ++ } ++ *(pOutWriteVal+rf) = writeVal; ++ } ++} ++#endif ++void getTxPowerWriteValByRegulatory88E( ++ IN PADAPTER Adapter, ++ IN u8 Channel, ++ IN u8 index, ++ IN u32* powerBase0, ++ IN u32* powerBase1, ++ OUT u32* pOutWriteVal ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit; ++ s1Byte pwr_diff=0; ++ u4Byte writeVal, customer_limit, rf; ++ u1Byte Regulatory = pHalData->EEPROMRegulatory; ++ ++ // ++ // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate ++ // ++#if 0 // (INTEL_PROXIMITY_SUPPORT == 1) ++ if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0) ++ Regulatory = 2; ++#endif ++ ++ for(rf=0; rf<2; rf++) ++ { ++ switch(Regulatory) ++ { ++ case 0: // Realtek better performance ++ // increase power diff defined by Realtek for large power ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 1: // Realtek regulatory ++ // increase power diff defined by Realtek for regulatory ++ { ++ if(pHalData->pwrGroupCnt == 1) ++ chnlGroup = 0; ++ //if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) ++ { ++ if (Channel < 3) // Chanel 1-2 ++ chnlGroup = 0; ++ else if (Channel < 6) // Channel 3-5 ++ chnlGroup = 1; ++ else if(Channel <9) // Channel 6-8 ++ chnlGroup = 2; ++ else if(Channel <12) // Channel 9-11 ++ chnlGroup = 3; ++ else if(Channel <14) // Channel 12-13 ++ chnlGroup = 4; ++ else if(Channel ==14) // Channel 14 ++ chnlGroup = 4; ++ ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ chnlGroup++; ++ else ++ chnlGroup+=6; ++ ++/* ++ if(Channel <= 3) ++ chnlGroup = 0; ++ else if(Channel >= 4 && Channel <= 9) ++ chnlGroup = 1; ++ else if(Channel > 9) ++ chnlGroup = 2; ++ ++ ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ chnlGroup++; ++ else ++ chnlGroup+=4; ++*/ ++ } ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ } ++ break; ++ case 2: // Better regulatory ++ // don't increase any power diff ++ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 3: // Customer defined power diff. ++ // increase power diff defined by customer. ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ ++ /* ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) ++ { ++ RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n", ++ ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1])); ++ } ++ else ++ { ++ RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n", ++ ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1])); ++ }*/ ++ ++ if(index < 2) ++ pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1]; ++ else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1]; ++ ++ //RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff)); ++ ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) ++ customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1]; ++ else ++ customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1]; ++ ++ //RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit)); ++ ++ if(pwr_diff >= customer_pwr_limit) ++ pwr_diff = 0; ++ else ++ pwr_diff = customer_pwr_limit - pwr_diff; ++ ++ for (i=0; i<4; i++) ++ { ++ pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8)); ++ ++ if(pwr_diff_limit[i] > pwr_diff) ++ pwr_diff_limit[i] = pwr_diff; ++ } ++ customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | ++ (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); ++ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ default: ++ chnlGroup = 0; ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ } ++ ++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. ++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. ++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. ++ //92d do not need this ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ writeVal = 0x14141414; ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ writeVal = 0x00000000; ++ ++ // 20100628 Joseph: High power mode for BT-Coexist mechanism. ++ // This mechanism is only applied when Driver-Highpower-Mechanism is OFF. ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); ++ writeVal = writeVal - 0x06060606; ++ } ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); ++ writeVal = writeVal ; ++ } ++ /* ++ if(pMgntInfo->bDisableTXPowerByRate) ++ { ++ // add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate ++ writeVal = 0x2c2c2c2c; ++ } ++ */ ++ *(pOutWriteVal+rf) = writeVal; ++ } ++} ++ ++static void writeOFDMPowerReg88E( ++ IN PADAPTER Adapter, ++ IN u8 index, ++ IN u32* pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, ++ rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, ++ rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; ++ u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, ++ rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, ++ rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; ++ u8 i, rf, pwr_val[4]; ++ u32 writeVal; ++ u16 RegOffset; ++ ++ for(rf=0; rf<2; rf++) ++ { ++ writeVal = pValue[rf]; ++ for(i=0; i<4; i++) ++ { ++ pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); ++ if (pwr_val[i] > RF6052_MAX_TX_PWR) ++ pwr_val[i] = RF6052_MAX_TX_PWR; ++ } ++ writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0]; ++ ++ if(rf == 0) ++ RegOffset = RegOffset_A[index]; ++ else ++ RegOffset = RegOffset_B[index]; ++ ++ PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); ++ //printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal); ++ ++ // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. ++ if(((pHalData->rf_type == RF_2T2R) && ++ (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| ++ ((pHalData->rf_type != RF_2T2R) && ++ (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) ) ++ { ++ writeVal = pwr_val[3]; ++ if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) ++ RegOffset = 0xc90; ++ if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) ++ RegOffset = 0xc98; ++ for(i=0; i<3; i++) ++ { ++ if(i!=2) ++ writeVal = (writeVal>8)?(writeVal-8):0; ++ else ++ writeVal = (writeVal>6)?(writeVal-6):0; ++ rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal); ++ } ++ } ++ } ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetOFDMTxPower ++ * ++ * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for ++ * different channel and read original value in TX power register area from ++ * 0xe00. We increase offset and original value to be correct tx pwr. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/05/2008 MHC Simulate 8192 series method. ++ * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to ++ * A/B pwr difference or legacy/HT pwr diff. ++ * 2. We concern with path B legacy/HT OFDM difference. ++ * 01/22/2009 MHC Support new EPRO format from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++ ++VOID ++rtl8188e_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevelOFDM, ++ IN u8* pPowerLevelBW20, ++ IN u8* pPowerLevelBW40, ++ IN u8 Channel) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value; ++ u8 direction; ++ u8 index = 0; ++ ++ ++ //DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel); ++ ++ getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); ++ ++ // ++ // 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. ++ // This is ued to fix unstable power tracking mode. ++ // ++ ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); ++ ++ for(index=0; index<6; index++) ++ { ++ getTxPowerWriteValByRegulatory88E(Adapter, Channel, index, ++ &powerBase0[0], &powerBase1[0], &writeVal[0]); ++ ++ if (direction == 1) ++ { ++ writeVal[0] += pwrtrac_value; ++ writeVal[1] += pwrtrac_value; ++ } ++ else if (direction == 2) ++ { ++ writeVal[0] -= pwrtrac_value; ++ writeVal[1] -= pwrtrac_value; ++ } ++ ++ writeOFDMPowerReg88E(Adapter, index, &writeVal[0]); ++ } ++} ++ ++ ++static VOID ++phy_RF6052_Config_HardCode( ++ IN PADAPTER Adapter ++ ) ++{ ++ ++ // Set Default Bandwidth to 20M ++ //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); ++ ++ // TODO: Set Default Channel to channel one for RTL8225 ++ ++} ++ ++static int ++phy_RF6052_Config_ParaFile( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 u4RegValue; ++ u8 eRFPath; ++ BB_REGISTER_DEFINITION_T *pPhyReg; ++ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A; ++ static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B; ++ char *pszRadioAFile, *pszRadioBFile; ++ ++ ++ ++ pszRadioAFile = sz88eRadioAFile; ++ pszRadioBFile = sz88eRadioBFile; ++ ++ ++ //3//----------------------------------------------------------------- ++ //3// <2> Initialize RF ++ //3//----------------------------------------------------------------- ++ //for(eRFPath = RF_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ ++ pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ ++ /*----Store original RFENV control type----*/ ++ switch(eRFPath) ++ { ++ case RF_PATH_A: ++ case RF_PATH_C: ++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); ++ break; ++ case RF_PATH_B : ++ case RF_PATH_D: ++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); ++ break; ++ } ++ ++ /*----Set RF_ENV enable----*/ ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /*----Set RF_ENV output high----*/ ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /* Set bit number of Address and Data for RF register */ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /*----Initialize RF fom connfiguration file----*/ ++ switch(eRFPath) ++ { ++ case RF_PATH_A: ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) ++ rtStatus= _FAIL; ++ #else ++ rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); ++ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM ++#else ++ rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath); ++#endif//#ifdef CONFIG_EMBEDDED_FWIMG ++ break; ++ case RF_PATH_B: ++#ifdef CONFIG_EMBEDDED_FWIMG ++ #ifdef CONFIG_PHY_SETTING_WITH_ODM ++ if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) ++ rtStatus= _FAIL; ++ #else ++ rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); ++ #endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM ++#else ++ rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath); ++#endif ++ break; ++ case RF_PATH_C: ++ break; ++ case RF_PATH_D: ++ break; ++ } ++ ++ /*----Restore RFENV control type----*/; ++ switch(eRFPath) ++ { ++ case RF_PATH_A: ++ case RF_PATH_C: ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); ++ break; ++ case RF_PATH_B : ++ case RF_PATH_D: ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); ++ break; ++ } ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); ++ goto phy_RF6052_Config_ParaFile_Fail; ++ } ++ ++ } ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); ++ return rtStatus; ++ ++phy_RF6052_Config_ParaFile_Fail: ++ return rtStatus; ++} ++ ++ ++int ++PHY_RF6052_Config8188E( ++ IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ int rtStatus = _SUCCESS; ++ ++ // ++ // Initialize general global value ++ // ++ // TODO: Extend RF_PATH_C and RF_PATH_D in the future ++ if(pHalData->rf_type == RF_1T1R) ++ pHalData->NumTotalRFPath = 1; ++ else ++ pHalData->NumTotalRFPath = 2; ++ ++ // ++ // Config BB and RF ++ // ++ rtStatus = phy_RF6052_Config_ParaFile(Adapter); ++#if 0 ++ switch( Adapter->MgntInfo.bRegHwParaFile ) ++ { ++ case 0: ++ phy_RF6052_Config_HardCode(Adapter); ++ break; ++ ++ case 1: ++ rtStatus = phy_RF6052_Config_ParaFile(Adapter); ++ break; ++ ++ case 2: ++ // Partial Modify. ++ phy_RF6052_Config_HardCode(Adapter); ++ phy_RF6052_Config_ParaFile(Adapter); ++ break; ++ ++ default: ++ phy_RF6052_Config_HardCode(Adapter); ++ break; ++ } ++#endif ++ return rtStatus; ++ ++} ++ ++ ++// ++// ==> RF shadow Operation API Code Section!!! ++// ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RFShadowRead ++ * PHY_RFShadowWrite ++ * PHY_RFShadowCompare ++ * PHY_RFShadowRecorver ++ * PHY_RFShadowCompareAll ++ * PHY_RFShadowRecorverAll ++ * PHY_RFShadowCompareFlagSet ++ * PHY_RFShadowRecorverFlagSet ++ * ++ * Overview: When we set RF register, we must write shadow at first. ++ * When we are running, we must compare shadow abd locate error addr. ++ * Decide to recorver or not. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/20/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++u32 ++PHY_RFShadowRead( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ return RF_Shadow[eRFPath][Offset].Value; ++ ++} /* PHY_RFShadowRead */ ++ ++ ++VOID ++PHY_RFShadowWrite( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u32 Data) ++{ ++ RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); ++ RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE; ++ ++} /* PHY_RFShadowWrite */ ++ ++ ++BOOLEAN ++PHY_RFShadowCompare( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ u32 reg; ++ // Check if we need to check the register ++ if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) ++ { ++ reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask); ++ // Compare shadow and real rf register for 20bits!! ++ if (RF_Shadow[eRFPath][Offset].Value != reg) ++ { ++ // Locate error position. ++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE; ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", ++ //eRFPath, Offset, reg)); ++ } ++ return RF_Shadow[eRFPath][Offset].ErrorOrNot ; ++ } ++ return _FALSE; ++} /* PHY_RFShadowCompare */ ++ ++ ++VOID ++PHY_RFShadowRecorver( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ // Check if the address is error ++ if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) ++ { ++ // Check if we need to recorver the register. ++ if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) ++ { ++ PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask, ++ RF_Shadow[eRFPath][Offset].Value); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", ++ //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); ++ } ++ } ++ ++} /* PHY_RFShadowRecorver */ ++ ++ ++VOID ++PHY_RFShadowCompareAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset); ++ } ++ } ++ ++} /* PHY_RFShadowCompareAll */ ++ ++ ++VOID ++PHY_RFShadowRecorverAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset); ++ } ++ } ++ ++} /* PHY_RFShadowRecorverAll */ ++ ++ ++VOID ++PHY_RFShadowCompareFlagSet( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u8 Type) ++{ ++ // Set True or False!!! ++ RF_Shadow[eRFPath][Offset].Compare = Type; ++ ++} /* PHY_RFShadowCompareFlagSet */ ++ ++ ++VOID ++PHY_RFShadowRecorverFlagSet( ++ IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u8 Type) ++{ ++ // Set True or False!!! ++ RF_Shadow[eRFPath][Offset].Recorver= Type; ++ ++} /* PHY_RFShadowRecorverFlagSet */ ++ ++ ++VOID ++PHY_RFShadowCompareFlagSetAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! ++ if (Offset != 0x26 && Offset != 0x27) ++ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE); ++ else ++ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE); ++ } ++ } ++ ++} /* PHY_RFShadowCompareFlagSetAll */ ++ ++ ++VOID ++PHY_RFShadowRecorverFlagSetAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! ++ if (Offset != 0x26 && Offset != 0x27) ++ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE); ++ else ++ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE); ++ } ++ } ++ ++} /* PHY_RFShadowCompareFlagSetAll */ ++ ++VOID ++PHY_RFShadowRefresh( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ RF_Shadow[eRFPath][Offset].Value = 0; ++ RF_Shadow[eRFPath][Offset].Compare = _FALSE; ++ RF_Shadow[eRFPath][Offset].Recorver = _FALSE; ++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE; ++ RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE; ++ } ++ } ++ ++} /* PHY_RFShadowRead */ ++ ++/* End of HalRf6052.c */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rxdesc.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rxdesc.c +new file mode 100644 +index 00000000..7489a66a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_rxdesc.c +@@ -0,0 +1,350 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_REDESC_C_ ++ ++#include ++#include ++#include ++#include ++ ++static s32 translate2dbm(u8 signal_strength_idx) ++{ ++ s32 signal_power; // in dBm. ++ ++ ++ // Translate to dBm (x=0.5y-95). ++ signal_power = (s32)((signal_strength_idx + 1) >> 1); ++ signal_power -= 95; ++ ++ return signal_power; ++} ++ ++ ++static void process_rssi(_adapter *padapter,union recv_frame *prframe) ++{ ++ u32 last_rssi, tmp_val; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); ++ //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) ++ { ++ ++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(signal_stat->update_req) { ++ signal_stat->total_num = 0; ++ signal_stat->total_val = 0; ++ signal_stat->update_req = 0; ++ } ++ ++ signal_stat->total_num++; ++ signal_stat->total_val += pattrib->phy_info.SignalStrength; ++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; ++ #else //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //Adapter->RxStats.RssiCalculateCnt++; //For antenna Test ++ if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX; ++ last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; ++ padapter->recvpriv.signal_strength_data.total_val -= last_rssi; ++ } ++ padapter->recvpriv.signal_strength_data.total_val +=pattrib->phy_info.SignalStrength; ++ ++ padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength; ++ if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) ++ padapter->recvpriv.signal_strength_data.index = 0; ++ ++ ++ tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num; ++ ++ if(padapter->recvpriv.is_signal_dbg) { ++ padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg; ++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg); ++ } else { ++ padapter->recvpriv.signal_strength= tmp_val; ++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val); ++ } ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num)); ++ #endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ } ++ ++}// Process_UI_RSSI_8192C ++ ++ ++ ++static void process_link_qual(_adapter *padapter,union recv_frame *prframe) ++{ ++ u32 last_evm=0, tmpVal; ++ struct rx_pkt_attrib *pattrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ struct signal_stat * signal_stat; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ if(prframe == NULL || padapter==NULL){ ++ return; ++ } ++ ++ pattrib = &prframe->u.hdr.attrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ signal_stat = &padapter->recvpriv.signal_qual_data; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(signal_stat->update_req) { ++ signal_stat->total_num = 0; ++ signal_stat->total_val = 0; ++ signal_stat->update_req = 0; ++ } ++ ++ signal_stat->total_num++; ++ signal_stat->total_val += pattrib->phy_info.SignalQuality; ++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; ++ ++#else //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(pattrib->phy_info.SignalQuality != 0) ++ { ++ // ++ // 1. Record the general EVM to the sliding window. ++ // ++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; ++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; ++ padapter->recvpriv.signal_qual_data.total_val -= last_evm; ++ } ++ padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality; ++ ++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality; ++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ padapter->recvpriv.signal_qual_data.index = 0; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality)); ++ ++ // <1> Showed on UI for user, in percentage. ++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; ++ padapter->recvpriv.signal_qual=(u8)tmpVal; ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality)); ++ } ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++} ++ ++//void rtl8188e_process_phy_info(_adapter *padapter, union recv_frame *prframe) ++void rtl8188e_process_phy_info(_adapter *padapter, void *prframe) ++{ ++ union recv_frame *precvframe = (union recv_frame *)prframe; ++ ++ // ++ // Check RSSI ++ // ++ process_rssi(padapter, precvframe); ++ // ++ // Check PWDB. ++ // ++ //process_PWDB(padapter, precvframe); ++ ++ //UpdateRxSignalStatistics8192C(Adapter, pRfd); ++ // ++ // Check EVM ++ // ++ process_link_qual(padapter, precvframe); ++ ++} ++ ++ ++void update_recvframe_attrib_88e( ++ union recv_frame *precvframe, ++ struct recv_stat *prxstat) ++{ ++ struct rx_pkt_attrib *pattrib; ++ struct recv_stat report; ++ PRXREPORT prxreport; ++ //struct recv_frame_hdr *phdr; ++ ++ //phdr = &precvframe->u.hdr; ++ ++ report.rxdw0 = le32_to_cpu(prxstat->rxdw0); ++ report.rxdw1 = le32_to_cpu(prxstat->rxdw1); ++ report.rxdw2 = le32_to_cpu(prxstat->rxdw2); ++ report.rxdw3 = le32_to_cpu(prxstat->rxdw3); ++ report.rxdw4 = le32_to_cpu(prxstat->rxdw4); ++ report.rxdw5 = le32_to_cpu(prxstat->rxdw5); ++ ++ prxreport = (PRXREPORT)&report; ++ ++ pattrib = &precvframe->u.hdr.attrib; ++ _rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); ++ ++ pattrib->crc_err = (u8)((report.rxdw0 >> 14) & 0x1);;//(u8)prxreport->crc32; ++ ++ // update rx report to recv_frame attribute ++ pattrib->pkt_rpt_type = (u8)((report.rxdw3 >> 14) & 0x3);//prxreport->rpt_sel; ++ ++ if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet ++ { ++ pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen; ++ pattrib->drvinfo_sz = (u8)((report.rxdw0 >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3); ++ ++ pattrib->physt = (u8)((report.rxdw0 >> 26) & 0x1);//(u8)prxreport->physt; ++ ++ pattrib->bdecrypted = (report.rxdw0 & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1); ++ pattrib->encrypt = (u8)((report.rxdw0 >> 20) & 0x7);//(u8)prxreport->security; ++ ++ pattrib->qos = (u8)((report.rxdw0 >> 23) & 0x1);//(u8)prxreport->qos; ++ pattrib->priority = (u8)((report.rxdw1 >> 8) & 0xf);//(u8)prxreport->tid; ++ ++ pattrib->amsdu = (u8)((report.rxdw1 >> 13) & 0x1);//(u8)prxreport->amsdu; ++ ++ pattrib->seq_num = (u16)(report.rxdw2 & 0x00000fff);//(u16)prxreport->seq; ++ pattrib->frag_num = (u8)((report.rxdw2 >> 12) & 0xf);//(u8)prxreport->frag; ++ pattrib->mfrag = (u8)((report.rxdw1 >> 27) & 0x1);//(u8)prxreport->mf; ++ pattrib->mdata = (u8)((report.rxdw1 >> 26) & 0x1);//(u8)prxreport->md; ++ ++ pattrib->mcs_rate = (u8)(report.rxdw3 & 0x3f);//(u8)prxreport->rxmcs; ++ pattrib->rxht = (u8)((report.rxdw3 >> 6) & 0x1);//(u8)prxreport->rxht; ++ ++ pattrib->icv_err = (u8)((report.rxdw0 >> 15) & 0x1);//(u8)prxreport->icverr; ++ pattrib->shift_sz = (u8)((report.rxdw0 >> 24) & 0x3); ++ ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT1)//CCX ++ { ++ pattrib->pkt_len = TX_RPT1_PKT_LEN; ++ pattrib->drvinfo_sz = 0; ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT2)// TX RPT ++ { ++ pattrib->pkt_len =(u16)(report.rxdw0 & 0x3FF);//Rx length[9:0] ++ pattrib->drvinfo_sz = 0; ++ ++ // ++ // Get TX report MAC ID valid. ++ // ++ pattrib->MacIDValidEntry[0] = report.rxdw4; ++ pattrib->MacIDValidEntry[1] = report.rxdw5; ++ ++ } ++ else if(pattrib->pkt_rpt_type == HIS_REPORT)// USB HISR RPT ++ { ++ pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen; ++ } ++ ++} ++ ++/* ++ * Notice: ++ * Before calling this function, ++ * precvframe->u.hdr.rx_data should be ready! ++ */ ++void update_recvframe_phyinfo_88e( ++ union recv_frame *precvframe, ++ struct phy_stat *pphy_status) ++{ ++ PADAPTER padapter = precvframe->u.hdr.adapter; ++ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info); ++ u8 *wlanhdr; ++ ODM_PACKET_INFO_T pkt_info; ++ u8 *sa; ++ struct sta_priv *pstapriv; ++ struct sta_info *psta; ++ //_irqL irqL; ++ ++ pkt_info.bPacketMatchBSSID =_FALSE; ++ pkt_info.bPacketToSelf = _FALSE; ++ pkt_info.bPacketBeacon = _FALSE; ++ ++ wlanhdr = get_recvframe_data(precvframe); ++ ++ pkt_info.bPacketMatchBSSID = ((!IsFrameTypeCtrl(wlanhdr)) && ++ !pattrib->icv_err && !pattrib->crc_err && ++ _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN)); ++ ++ pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && (_rtw_memcmp(get_da(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN)); ++ ++ pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON); ++ ++ if(pkt_info.bPacketBeacon){ ++ if(check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ sa = padapter->mlmepriv.cur_network.network.MacAddress; ++ #if 0 ++ { ++ DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n", ++ sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]); ++ } ++ #endif ++ } ++ else ++ sa = get_sa(wlanhdr); ++ } ++ else{ ++ sa = get_sa(wlanhdr); ++ } ++ ++ pstapriv = &padapter->stapriv; ++ pkt_info.StationID = 0xFF; ++ psta = rtw_get_stainfo(pstapriv, sa); ++ if (psta) ++ { ++ pkt_info.StationID = psta->mac_id; ++ //DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID); ++ } ++ pkt_info.Rate = pattrib->mcs_rate; ++ //rtl8188e_query_rx_phy_status(precvframe, pphy_status); ++ ++ //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ++ ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info)); ++ //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ++ ++ precvframe->u.hdr.psta = NULL; ++ if (pkt_info.bPacketMatchBSSID && ++ (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)) ++ { ++ if (psta) ++ { ++ precvframe->u.hdr.psta = psta; ++ rtl8188e_process_phy_info(padapter, precvframe); ++ ++ } ++ } ++ else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) ++ { ++ if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ if (psta) ++ { ++ precvframe->u.hdr.psta = psta; ++ } ++ } ++ rtl8188e_process_phy_info(padapter, precvframe); ++ } ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_sreset.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_sreset.c +new file mode 100644 +index 00000000..7c588cb1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_sreset.c +@@ -0,0 +1,125 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_SRESET_C_ ++ ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ ++void rtl8188e_sreset_xmit_status_check(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ unsigned long current_time; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ unsigned int diff_time; ++ u32 txdma_status; ++ ++ if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){ ++ DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); ++ rtw_hal_sreset_reset(padapter); ++ } ++#ifdef CONFIG_USB_HCI ++ //total xmit irp = 4 ++ //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); ++ //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) ++ current_time = rtw_get_current_time(); ++ ++ if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) { ++ ++ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time); ++ ++ if (diff_time > 2000) { ++ if (psrtpriv->last_tx_complete_time == 0) { ++ psrtpriv->last_tx_complete_time = current_time; ++ } ++ else{ ++ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time); ++ if (diff_time > 4000) { ++ u32 ability; ++ ++ //padapter->Wifi_Error_Status = WIFI_TX_HANG; ++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &ability); ++ ++ DBG_871X("%s tx hang %s\n", __FUNCTION__, ++ (ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : ""); ++ ++ if (!(ability & ODM_BB_ADAPTIVITY)) ++ rtw_hal_sreset_reset(padapter); ++ } ++ } ++ } ++ } ++#endif //CONFIG_USB_HCI ++ ++ if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) { ++ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; ++ rtw_hal_sreset_reset(padapter); ++ return; ++ } ++} ++ ++void rtl8188e_sreset_linked_status_check(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ u32 rx_dma_status = 0; ++ u8 fw_status=0; ++ rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS); ++ if(rx_dma_status!= 0x00){ ++ DBG_8192C("%s REG_RXDMA_STATUS:0x%08x \n",__FUNCTION__,rx_dma_status); ++ rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status); ++ } ++ fw_status = rtw_read8(padapter,REG_FMETHR); ++ if(fw_status != 0x00) ++ { ++ if(fw_status == 1) ++ DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !! \n",__FUNCTION__,fw_status); ++ else if(fw_status == 2) ++ DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__FUNCTION__,fw_status); ++ } ++#if 0 ++ u32 regc50,regc58,reg824,reg800; ++ regc50 = rtw_read32(padapter,0xc50); ++ regc58 = rtw_read32(padapter,0xc58); ++ reg824 = rtw_read32(padapter,0x824); ++ reg800 = rtw_read32(padapter,0x800); ++ if( ((regc50&0xFFFFFF00)!= 0x69543400)|| ++ ((regc58&0xFFFFFF00)!= 0x69543400)|| ++ (((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))|| ++ ( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000))) ++ { ++ DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__, ++ regc50, regc58, reg824, reg800); ++ rtw_hal_sreset_reset(padapter); ++ } ++#endif ++ ++ if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) { ++ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; ++ rtw_hal_sreset_reset(padapter); ++ return; ++ } ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_xmit.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_xmit.c +new file mode 100644 +index 00000000..d472236c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/rtl8188e_xmit.c +@@ -0,0 +1,292 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_XMIT_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_XMIT_ACK ++void dump_txrpt_ccx_88e(void *buf) ++{ ++ struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf; ++ ++ DBG_871X("%s:\n" ++ "tag1:%u, pkt_num:%u, txdma_underflow:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n" ++ "mac_id:%u, pkt_ok:%u, bmc:%u\n" ++ "retry_cnt:%u, lifetime_over:%u, retry_over:%u\n" ++ "ccx_qtime:%u\n" ++ "final_data_rate:0x%02x\n" ++ "qsel:%u, sw:0x%03x\n" ++ , __func__ ++ , txrpt_ccx->tag1, txrpt_ccx->pkt_num, txrpt_ccx->txdma_underflow, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx ++ , txrpt_ccx->mac_id, txrpt_ccx->pkt_ok, txrpt_ccx->bmc ++ , txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over ++ , txrpt_ccx_qtime_88e(txrpt_ccx) ++ , txrpt_ccx->final_data_rate ++ , txrpt_ccx->qsel, txrpt_ccx_sw_88e(txrpt_ccx) ++ ); ++} ++ ++void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf) ++{ ++ struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf; ++ ++ #ifdef DBG_CCX ++ dump_txrpt_ccx_88e(buf); ++ #endif ++ ++ if (txrpt_ccx->int_ccx) { ++ if (txrpt_ccx->pkt_ok) ++ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); ++ else ++ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); ++ } ++} ++#endif //CONFIG_XMIT_ACK ++ ++void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc) ++{ ++ u8 bDumpTxPkt; ++ u8 bDumpTxDesc = _FALSE; ++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt)); ++ ++ if(bDumpTxPkt ==1){//dump txdesc for data frame ++ DBG_871X("dump tx_desc for data frame\n"); ++ if((frame_tag&0x0f) == DATA_FRAMETAG){ ++ bDumpTxDesc = _TRUE; ++ } ++ } ++ else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame ++ DBG_871X("dump tx_desc for mgnt frame\n"); ++ if((frame_tag&0x0f) == MGNT_FRAMETAG){ ++ bDumpTxDesc = _TRUE; ++ } ++ } ++ else if(bDumpTxPkt ==3){//dump early info ++ } ++ ++ if(bDumpTxDesc){ ++ // ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M ++ // ptxdesc->txdw6 = 0x6666f800; ++ DBG_8192C("=====================================\n"); ++ DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0); ++ DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1); ++ DBG_8192C("txdw2(0x%08x)\n",ptxdesc->txdw2); ++ DBG_8192C("txdw3(0x%08x)\n",ptxdesc->txdw3); ++ DBG_8192C("txdw4(0x%08x)\n",ptxdesc->txdw4); ++ DBG_8192C("txdw5(0x%08x)\n",ptxdesc->txdw5); ++ DBG_8192C("txdw6(0x%08x)\n",ptxdesc->txdw6); ++ DBG_8192C("txdw7(0x%08x)\n",ptxdesc->txdw7); ++ DBG_8192C("=====================================\n"); ++ } ++ ++} ++ ++/* ++ * Description: ++ * Aggregation packets and send to hardware ++ * ++ * Return: ++ * 0 Success ++ * -1 Hardware resource(TX FIFO) not ready ++ * -2 Software resource(xmitbuf) not ready ++ */ ++#ifdef CONFIG_TX_EARLY_MODE ++ ++//#define DBG_EMINFO ++ ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ #define EARLY_MODE_MAX_PKT_NUM 10 ++#else ++ #define EARLY_MODE_MAX_PKT_NUM 5 ++#endif ++ ++ ++struct EMInfo{ ++ u8 EMPktNum; ++ u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM]; ++}; ++ ++ ++void ++InsertEMContent_8188E( ++ struct EMInfo *pEMInfo, ++ IN pu1Byte VirtualAddress) ++{ ++ ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ u1Byte index=0; ++ u4Byte dwtmp=0; ++#endif ++ ++ _rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE); ++ if(pEMInfo->EMPktNum==0) ++ return; ++ ++ #ifdef DBG_EMINFO ++ { ++ int i; ++ DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum); ++ for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){ ++ DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]); ++ } ++ ++ } ++ #endif ++ ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum); ++ ++ if(pEMInfo->EMPktNum == 1){ ++ dwtmp = pEMInfo->EMPktLen[0]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[0]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[1]; ++ } ++ SET_EARLYMODE_LEN0(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 3){ ++ dwtmp = pEMInfo->EMPktLen[2]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[2]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[3]; ++ } ++ SET_EARLYMODE_LEN1(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 5){ ++ dwtmp = pEMInfo->EMPktLen[4]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[4]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[5]; ++ } ++ SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF); ++ SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4); ++ if(pEMInfo->EMPktNum <= 7){ ++ dwtmp = pEMInfo->EMPktLen[6]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[6]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[7]; ++ } ++ SET_EARLYMODE_LEN3(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 9){ ++ dwtmp = pEMInfo->EMPktLen[8]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[8]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[9]; ++ } ++ SET_EARLYMODE_LEN4(VirtualAddress, dwtmp); ++#else ++ SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum); ++ SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]); ++ SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]); ++ SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF); ++ SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4); ++ SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]); ++ SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]); ++#endif ++ //RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8); ++ ++} ++ ++ ++ ++void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf ) ++{ ++ //_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq ++ int index,j; ++ u16 offset,pktlen; ++ PTXDESC ptxdesc; ++ ++ u8 *pmem,*pEMInfo_mem; ++ s8 node_num_0=0,node_num_1=0; ++ struct EMInfo eminfo; ++ struct agg_pkt_info *paggpkt; ++ struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data; ++ pmem= pframe->buf_addr; ++ ++ #ifdef DBG_EMINFO ++ DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num); ++ for(index=0;indexagg_num;index++){ ++ offset = pxmitpriv->agg_pkt[index].offset; ++ pktlen = pxmitpriv->agg_pkt[index].pkt_len; ++ DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset); ++ DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen); ++ } ++ #endif ++ ++ if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM) ++ { ++ node_num_0 = pframe->agg_num; ++ node_num_1= EARLY_MODE_MAX_PKT_NUM-1; ++ } ++ ++ for(index=0;indexagg_num;index++){ ++ ++ offset = pxmitpriv->agg_pkt[index].offset; ++ pktlen = pxmitpriv->agg_pkt[index].pkt_len; ++ ++ _rtw_memset(&eminfo,0,sizeof(struct EMInfo)); ++ if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){ ++ if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){ ++ eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM; ++ node_num_0--; ++ } ++ else{ ++ eminfo.EMPktNum = node_num_1; ++ node_num_1--; ++ } ++ } ++ else{ ++ eminfo.EMPktNum = pframe->agg_num-(index+1); ++ } ++ for(j=0;j< eminfo.EMPktNum ;j++){ ++ eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC ++ } ++ ++ if(pmem){ ++ if(index==0){ ++ ptxdesc = (PTXDESC)(pmem); ++ pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE; ++ } ++ else{ ++ pmem = pmem + pxmitpriv->agg_pkt[index-1].offset; ++ ptxdesc = (PTXDESC)(pmem); ++ pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE; ++ } ++ ++ #ifdef DBG_EMINFO ++ DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen); ++ #endif ++ InsertEMContent_8188E(&eminfo,pEMInfo_mem); ++ } ++ ++ ++ } ++ _rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM); ++ ++} ++#endif ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_led.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_led.c +new file mode 100644 +index 00000000..06c90c55 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_led.c +@@ -0,0 +1,124 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8189ES_LED_C_ ++ ++#include "drv_types.h" ++#include "rtl8188e_hal.h" ++ ++//================================================================================ ++// LED object. ++//================================================================================ ++ ++ ++//================================================================================ ++// Prototype of protected function. ++//================================================================================ ++ ++//================================================================================ ++// LED_819xUsb routines. ++//================================================================================ ++ ++// ++// Description: ++// Turn on LED according to LedPin specified. ++// ++void ++SwLedOn( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ return; ++ } ++ ++ pLed->bLedOn = _TRUE; ++} ++ ++ ++// ++// Description: ++// Turn off LED according to LedPin specified. ++// ++void ++SwLedOff( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ goto exit; ++ } ++ ++exit: ++ pLed->bLedOn = _FALSE; ++ ++} ++ ++//================================================================================ ++// Default LED behavior. ++//================================================================================ ++ ++// ++// Description: ++// Initialize all LED_871x objects. ++// ++void ++rtl8188es_InitSwLeds( ++ _adapter *padapter ++ ) ++{ ++ struct led_priv *pledpriv = &(padapter->ledpriv); ++ ++#if 0 ++ pledpriv->LedControlHandler = LedControl871x; ++ ++ InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); ++ ++ InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1); ++#endif ++} ++ ++ ++// ++// Description: ++// DeInitialize all LED_819xUsb objects. ++// ++void ++rtl8188es_DeInitSwLeds( ++ _adapter *padapter ++ ) ++{ ++#if 0 ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ DeInitLed871x( &(ledpriv->SwLed0) ); ++ DeInitLed871x( &(ledpriv->SwLed1) ); ++#endif ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_recv.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_recv.c +new file mode 100644 +index 00000000..ccbb3407 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_recv.c +@@ -0,0 +1,861 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8189ES_RECV_C_ ++ ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#include ++#include ++#include ++ ++static void rtl8188es_recv_tasklet(void *priv); ++ ++static s32 initrecvbuf(struct recv_buf *precvbuf, PADAPTER padapter) ++{ ++ _rtw_init_listhead(&precvbuf->list); ++ _rtw_spinlock_init(&precvbuf->recvbuf_lock); ++ ++ precvbuf->adapter = padapter; ++ ++ return _SUCCESS; ++} ++ ++static void freerecvbuf(struct recv_buf *precvbuf) ++{ ++ _rtw_spinlock_free(&precvbuf->recvbuf_lock); ++} ++ ++/* ++ * Initialize recv private variable for hardware dependent ++ * 1. recv buf ++ * 2. recv tasklet ++ * ++ */ ++s32 rtl8188es_init_recv_priv(PADAPTER padapter) ++{ ++ s32 res; ++ u32 i, n; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ ++ ++ res = _SUCCESS; ++ precvpriv = &padapter->recvpriv; ++ ++ //3 1. init recv buffer ++ _rtw_init_queue(&precvpriv->free_recv_buf_queue); ++ _rtw_init_queue(&precvpriv->recv_buf_pending_queue); ++ ++ n = NR_RECVBUFF * sizeof(struct recv_buf) + 4; ++ precvpriv->pallocated_recv_buf = rtw_zmalloc(n); ++ if (precvpriv->pallocated_recv_buf == NULL) { ++ res = _FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n")); ++ goto exit; ++ } ++ ++ precvpriv->precv_buf = (u8*)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4); ++ ++ // init each recv buffer ++ precvbuf = (struct recv_buf*)precvpriv->precv_buf; ++ for (i = 0; i < NR_RECVBUFF; i++) ++ { ++ res = initrecvbuf(precvbuf, padapter); ++ if (res == _FAIL) ++ break; ++ ++ res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf); ++ if (res == _FAIL) { ++ freerecvbuf(precvbuf); ++ break; ++ } ++ ++#ifdef CONFIG_SDIO_RX_COPY ++ if (precvbuf->pskb == NULL) { ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ ++ precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++ ++ if(precvbuf->pskb) ++ { ++ precvbuf->pskb->dev = padapter->pnetdev; ++ ++ tmpaddr = (SIZE_PTR)precvbuf->pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); ++ precvbuf->pend = skb_end_pointer(precvbuf->pskb); ++ precvbuf->len = 0; ++ } ++ ++ if (precvbuf->pskb == NULL) { ++ DBG_871X("%s: alloc_skb fail!\n", __FUNCTION__); ++ } ++ } ++#endif ++ ++ rtw_list_insert_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue); ++ ++ precvbuf++; ++ } ++ precvpriv->free_recv_buf_queue_cnt = i; ++ ++ if (res == _FAIL) ++ goto initbuferror; ++ ++ //3 2. init tasklet ++#ifdef PLATFORM_LINUX ++ tasklet_init(&precvpriv->recv_tasklet, ++ (void(*)(unsigned long))rtl8188es_recv_tasklet, ++ (unsigned long)padapter); ++#endif ++ ++ goto exit; ++ ++initbuferror: ++ precvbuf = (struct recv_buf*)precvpriv->precv_buf; ++ if (precvbuf) { ++ n = precvpriv->free_recv_buf_queue_cnt; ++ precvpriv->free_recv_buf_queue_cnt = 0; ++ for (i = 0; i < n ; i++) ++ { ++ rtw_list_delete(&precvbuf->list); ++ rtw_os_recvbuf_resource_free(padapter, precvbuf); ++ freerecvbuf(precvbuf); ++ precvbuf++; ++ } ++ precvpriv->precv_buf = NULL; ++ } ++ ++ if (precvpriv->pallocated_recv_buf) { ++ n = NR_RECVBUFF * sizeof(struct recv_buf) + 4; ++ rtw_mfree(precvpriv->pallocated_recv_buf, n); ++ precvpriv->pallocated_recv_buf = NULL; ++ } ++ ++exit: ++ return res; ++} ++ ++/* ++ * Free recv private variable of hardware dependent ++ * 1. recv buf ++ * 2. recv tasklet ++ * ++ */ ++void rtl8188es_free_recv_priv(PADAPTER padapter) ++{ ++ u32 i, n; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ ++ ++ precvpriv = &padapter->recvpriv; ++ ++ //3 1. kill tasklet ++#ifdef PLATFORM_LINUX ++ tasklet_kill(&precvpriv->recv_tasklet); ++#endif ++ ++ //3 2. free all recv buffers ++ precvbuf = (struct recv_buf*)precvpriv->precv_buf; ++ if (precvbuf) { ++ n = NR_RECVBUFF; ++ precvpriv->free_recv_buf_queue_cnt = 0; ++ for (i = 0; i < n ; i++) ++ { ++ rtw_list_delete(&precvbuf->list); ++ rtw_os_recvbuf_resource_free(padapter, precvbuf); ++ freerecvbuf(precvbuf); ++ precvbuf++; ++ } ++ precvpriv->precv_buf = NULL; ++ } ++ ++ if (precvpriv->pallocated_recv_buf) { ++ n = NR_RECVBUFF * sizeof(struct recv_buf) + 4; ++ rtw_mfree(precvpriv->pallocated_recv_buf, n); ++ precvpriv->pallocated_recv_buf = NULL; ++ } ++} ++ ++#ifdef CONFIG_SDIO_RX_COPY ++static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf *precvbuf, struct phy_stat *pphy_status) ++{ ++ s32 ret=_SUCCESS; ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 *primary_myid, *secondary_myid, *paddr1; ++ union recv_frame *precvframe_if2 = NULL; ++ _adapter *primary_padapter = precvframe->u.hdr.adapter; ++ _adapter *secondary_padapter = primary_padapter->pbuddy_adapter; ++ struct recv_priv *precvpriv = &primary_padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(primary_padapter); ++ ++ if(!secondary_padapter) ++ return ret; ++ ++ paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data); ++ ++ if(IS_MCAST(paddr1) == _FALSE)//unicast packets ++ { ++ //primary_myid = myid(&primary_padapter->eeprompriv); ++ secondary_myid = myid(&secondary_padapter->eeprompriv); ++ ++ if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN)) ++ { ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ } ++ ++ //ret = recv_entry(precvframe); ++ ++ } ++ else // Handle BC/MC Packets ++ { ++ //clone/copy to if2 ++ _pkt *pkt_copy = NULL; ++ struct rx_pkt_attrib *pattrib = NULL; ++ ++ precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue); ++ ++ if(!precvframe_if2) ++ return _FAIL; ++ ++ precvframe_if2->u.hdr.adapter = secondary_padapter; ++ _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); ++ pattrib = &precvframe_if2->u.hdr.attrib; ++ ++ //driver need to set skb len for rtw_skb_copy(). ++ //If skb->len is zero, rtw_skb_copy() will not copy data from original skb. ++ skb_put(precvframe->u.hdr.pkt, pattrib->pkt_len); ++ ++ pkt_copy = rtw_skb_copy( precvframe->u.hdr.pkt); ++ if (pkt_copy == NULL) ++ { ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) ++ { ++ DBG_8192C("pre_recv_entry(): rtw_skb_copy fail , drop frag frame \n"); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ return ret; ++ } ++ ++ pkt_copy = rtw_skb_clone(precvframe->u.hdr.pkt); ++ if(pkt_copy == NULL) ++ { ++ DBG_8192C("pre_recv_entry(): rtw_skb_clone fail , drop frame\n"); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ return ret; ++ } ++ } ++ ++ pkt_copy->dev = secondary_padapter->pnetdev; ++ ++ precvframe_if2->u.hdr.pkt = pkt_copy; ++ precvframe_if2->u.hdr.rx_head = pkt_copy->head; ++ precvframe_if2->u.hdr.rx_data = pkt_copy->data; ++ precvframe_if2->u.hdr.rx_tail = skb_tail_pointer(pkt_copy); ++ precvframe_if2->u.hdr.rx_end = skb_end_pointer(pkt_copy); ++ precvframe_if2->u.hdr.len = pkt_copy->len; ++ ++ //recvframe_put(precvframe_if2, pattrib->pkt_len); ++ ++ if ( pHalData->ReceiveConfig & RCR_APPFCS) ++ recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN); ++ ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe_if2, pphy_status); ++ ++ if(rtw_recv_entry(precvframe_if2) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ ++ if (precvframe->u.hdr.attrib.physt) ++ update_recvframe_phyinfo_88e(precvframe, pphy_status); ++ ret = rtw_recv_entry(precvframe); ++ ++#endif ++ ++ return ret; ++ ++} ++ ++static void rtl8188es_recv_tasklet(void *priv) ++{ ++ PADAPTER padapter; ++ PHAL_DATA_TYPE pHalData; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ union recv_frame *precvframe; ++ struct recv_frame_hdr *phdr; ++ struct rx_pkt_attrib *pattrib; ++ _irqL irql; ++ u8 *ptr; ++ u32 pkt_offset, skb_len, alloc_sz; ++ s32 transfer_len; ++ _pkt *pkt_copy = NULL; ++ struct phy_stat *pphy_status = NULL; ++ u8 shift_sz = 0, rx_report_sz = 0; ++ ++ ++ padapter = (PADAPTER)priv; ++ pHalData = GET_HAL_DATA(padapter); ++ precvpriv = &padapter->recvpriv; ++ ++ do { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); ++ break; ++ } ++ ++ precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue); ++ if (NULL == precvbuf) break; ++ ++ transfer_len = (s32)precvbuf->len; ++ ptr = precvbuf->pdata; ++ ++ do { ++ precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue); ++ if (precvframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__)); ++ rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ // The case of can't allocte recvframe should be temporary, ++ // schedule again and hope recvframe is available next time. ++#ifdef PLATFORM_LINUX ++ tasklet_schedule(&precvpriv->recv_tasklet); ++#endif ++ return; ++ } ++ ++ //rx desc parsing ++ update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr); ++ ++ pattrib = &precvframe->u.hdr.attrib; ++ ++ // fix Hardware RX data error, drop whole recv_buffer ++ if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) ++ { ++ DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ ++ if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) ++ rx_report_sz = RXDESC_SIZE + 4 + pattrib->drvinfo_sz; ++ else ++ rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz; ++ ++ pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len; ++ ++ if ((pattrib->pkt_len==0) || (pkt_offset>transfer_len)) { ++ DBG_8192C("%s()-%d: RX Warning!,pkt_len==0 or pkt_offset(%d)> transfoer_len(%d) \n", __FUNCTION__, __LINE__, pkt_offset, transfer_len); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ ++ if ((pattrib->crc_err) || (pattrib->icv_err)) ++ { ++ #ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ { ++ if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0)) ++ { ++ if (pattrib->crc_err == 1) ++ padapter->mppriv.rx_crcerrpktcount++; ++ } ++ } ++ #endif ++ DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ } ++ else ++ { ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if (pattrib->qos) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ skb_len = pattrib->pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ pkt_copy = rtw_skb_alloc(alloc_sz); ++ ++ if(pkt_copy) ++ { ++ pkt_copy->dev = padapter->pnetdev; ++ precvframe->u.hdr.pkt = pkt_copy; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len); ++ precvframe->u.hdr.rx_head = pkt_copy->head; ++ precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; ++ precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy); ++ } ++ else ++ { ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) ++ { ++ DBG_8192C("rtl8188es_recv_tasklet: alloc_skb fail , drop frag frame \n"); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ ++ precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb); ++ if(precvframe->u.hdr.pkt) ++ { ++ _pkt *pkt_clone = precvframe->u.hdr.pkt; ++ ++ pkt_clone->data = ptr + rx_report_sz + pattrib->shift_sz; ++ skb_reset_tail_pointer(pkt_clone); ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail ++ = pkt_clone->data; ++ precvframe->u.hdr.rx_end = pkt_clone->data + skb_len; ++ } ++ else ++ { ++ DBG_8192C("rtl8188es_recv_tasklet: rtw_skb_clone fail\n"); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ } ++ ++ recvframe_put(precvframe, skb_len); ++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++ ++ if (pHalData->ReceiveConfig & RCR_APPFCS) ++ recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN); ++ ++ // update drv info ++ if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) { ++ //rtl8723s_update_bassn(padapter, (ptr + RXDESC_SIZE)); ++ } ++ ++ if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet ++ { ++ pphy_status = (struct phy_stat *)(ptr + (rx_report_sz - pattrib->drvinfo_sz)); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)pphy_status) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ else ++#endif ++ { ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); ++ ++ if (rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: rtw_recv_entry(precvframe) != _SUCCESS\n",__FUNCTION__)); ++ } ++ } ++ } ++ else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP ++ ++ //enqueue recvframe to txrtp queue ++ if(pattrib->pkt_rpt_type == TX_REPORT1){ ++ //DBG_8192C("rx CCX \n"); ++ //CCX-TXRPT ack for xmit mgmt frames. ++ handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data); ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT2){ ++ //printk("rx TX RPT \n"); ++ ODM_RA_TxRPT2Handle_8188E( ++ &pHalData->odmpriv, ++ precvframe->u.hdr.rx_data, ++ pattrib->pkt_len, ++ pattrib->MacIDValidEntry[0], ++ pattrib->MacIDValidEntry[1] ++ ); ++ ++ } ++ /* ++ else if(pattrib->pkt_rpt_type == HIS_REPORT){ ++ printk("rx USB HISR \n"); ++ }*/ ++ ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ ++ } ++ } ++ ++ // Page size of receive package is 128 bytes alignment =>DMA AGG ++ // refer to _InitTransferPageSize() ++ pkt_offset = _RND128(pkt_offset); ++ transfer_len -= pkt_offset; ++ ptr += pkt_offset; ++ precvframe = NULL; ++ pkt_copy = NULL; ++ }while(transfer_len>0); ++ ++ precvbuf->len = 0; ++ ++ rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue); ++ } while (1); ++ ++} ++#else ++static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf *precvbuf, struct phy_stat *pphy_status) ++{ ++ s32 ret=_SUCCESS; ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 *primary_myid, *secondary_myid, *paddr1; ++ union recv_frame *precvframe_if2 = NULL; ++ _adapter *primary_padapter = precvframe->u.hdr.adapter; ++ _adapter *secondary_padapter = primary_padapter->pbuddy_adapter; ++ struct recv_priv *precvpriv = &primary_padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ u8 *pbuf = precvframe->u.hdr.rx_head; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(primary_padapter); ++ ++ if(!secondary_padapter) ++ return ret; ++ ++ paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data); ++ ++ if(IS_MCAST(paddr1) == _FALSE)//unicast packets ++ { ++ //primary_myid = myid(&primary_padapter->eeprompriv); ++ secondary_myid = myid(&secondary_padapter->eeprompriv); ++ ++ if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN)) ++ { ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ } ++ ++ //ret = recv_entry(precvframe); ++ ++ } ++ else // Handle BC/MC Packets ++ { ++ //clone/copy to if2 ++ u8 shift_sz = 0; ++ u32 alloc_sz, skb_len; ++ _pkt *pkt_copy = NULL; ++ struct rx_pkt_attrib *pattrib = NULL; ++ ++ precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue); ++ ++ if(!precvframe_if2) ++ return _FAIL; ++ ++ precvframe_if2->u.hdr.adapter = secondary_padapter; ++ _rtw_init_listhead(&precvframe_if2->u.hdr.list); ++ precvframe_if2->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe_if2->u.hdr.len=0; ++ _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); ++ pattrib = &precvframe_if2->u.hdr.attrib; ++ ++ pkt_copy = rtw_skb_copy( precvframe->u.hdr.pkt); ++ if (pkt_copy == NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__)); ++ rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue); ++ rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ // The case of can't allocte skb is serious and may never be recovered, ++ // once bDriverStopped is enable, this task should be stopped. ++ if (secondary_padapter->bDriverStopped == _FALSE) ++#ifdef PLATFORM_LINUX ++ tasklet_schedule(&precvpriv->recv_tasklet); ++#endif ++ return ret; ++ } ++ pkt_copy->dev = secondary_padapter->pnetdev; ++ ++ ++ ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++#if 1 ++ precvframe_if2->u.hdr.pkt = pkt_copy; ++ precvframe_if2->u.hdr.rx_head = pkt_copy->head; ++ precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data; ++ precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++#endif ++ recvframe_put(precvframe_if2, pkt_offset); ++ recvframe_pull(precvframe_if2, RXDESC_SIZE + pattrib->drvinfo_sz); ++ ++ if ( pHalData->ReceiveConfig & RCR_APPFCS) ++ recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN); ++ ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe_if2, pphy_status); ++ ++ if(rtw_recv_entry(precvframe_if2) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ ++ if (precvframe->u.hdr.attrib.physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); ++ ret = rtw_recv_entry(precvframe); ++ ++#endif ++ ++ return ret; ++ ++} ++ ++static void rtl8188es_recv_tasklet(void *priv) ++{ ++ PADAPTER padapter; ++ PHAL_DATA_TYPE pHalData; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ union recv_frame *precvframe; ++ struct recv_frame_hdr *phdr; ++ struct rx_pkt_attrib *pattrib; ++ u8 *ptr; ++ _pkt *ppkt; ++ u32 pkt_offset; ++ _irqL irql; ++#ifdef CONFIG_CONCURRENT_MODE ++ struct recv_stat *prxstat; ++#endif ++ ++ padapter = (PADAPTER)priv; ++ pHalData = GET_HAL_DATA(padapter); ++ precvpriv = &padapter->recvpriv; ++ ++ do { ++ precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue); ++ if (NULL == precvbuf) break; ++ ++ ptr = precvbuf->pdata; ++ ++ while (ptr < precvbuf->ptail) ++ { ++ precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue); ++ if (precvframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__)); ++ rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ // The case of can't allocte recvframe should be temporary, ++ // schedule again and hope recvframe is available next time. ++#ifdef PLATFORM_LINUX ++ tasklet_schedule(&precvpriv->recv_tasklet); ++#endif ++ return; ++ } ++ ++ phdr = &precvframe->u.hdr; ++ pattrib = &phdr->attrib; ++ ++ //rx desc parsing ++ update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr); ++#ifdef CONFIG_CONCURRENT_MODE ++ prxstat = (struct recv_stat*)ptr; ++#endif ++ // fix Hardware RX data error, drop whole recv_buffer ++ if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) ++ { ++ DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ ++ pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->pkt_len; ++ ++ if ((ptr + pkt_offset) > precvbuf->ptail) { ++ DBG_8192C("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __FUNCTION__, __LINE__, ptr, pkt_offset, precvbuf->ptail); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ break; ++ } ++ ++ if ((pattrib->crc_err) || (pattrib->icv_err)) ++ { ++ #ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ { ++ if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0)) ++ { ++ if (pattrib->crc_err == 1) ++ padapter->mppriv.rx_crcerrpktcount++; ++ } ++ } ++ #endif ++ ++ DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ } ++ else ++ { ++ ppkt = rtw_skb_clone(precvbuf->pskb); ++ if (ppkt == NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__)); ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ // The case of can't allocte skb is serious and may never be recovered, ++ // once bDriverStopped is enable, this task should be stopped. ++ if (padapter->bDriverStopped == _FALSE) { ++#ifdef PLATFORM_LINUX ++ tasklet_schedule(&precvpriv->recv_tasklet); ++#endif ++ } ++ ++ return; ++ } ++ ++ phdr->pkt = ppkt; ++ phdr->len = 0; ++ phdr->rx_head = precvbuf->phead; ++ phdr->rx_data = phdr->rx_tail = precvbuf->pdata; ++ phdr->rx_end = precvbuf->pend; ++ ++ recvframe_put(precvframe, pkt_offset); ++ recvframe_pull(precvframe, RXDESC_SIZE + pattrib->drvinfo_sz); ++ ++ if (pHalData->ReceiveConfig & RCR_APPFCS) ++ recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN); ++ ++ // move to drv info position ++ ptr += RXDESC_SIZE; ++ ++ // update drv info ++ if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) { ++// rtl8723s_update_bassn(padapter, pdrvinfo); ++ ptr += 4; ++ } ++ ++ if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)ptr) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ else ++#endif ++ { ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)ptr); ++ ++ if (rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ } ++ else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP ++ ++ //enqueue recvframe to txrtp queue ++ if(pattrib->pkt_rpt_type == TX_REPORT1){ ++ DBG_8192C("rx CCX \n"); ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT2){ ++ //DBG_8192C("rx TX RPT \n"); ++ ODM_RA_TxRPT2Handle_8188E( ++ &pHalData->odmpriv, ++ precvframe->u.hdr.rx_data, ++ pattrib->pkt_len, ++ pattrib->MacIDValidEntry[0], ++ pattrib->MacIDValidEntry[1] ++ ); ++ ++ } ++ /* ++ else if(pattrib->pkt_rpt_type == HIS_REPORT){ ++ DBG_8192C("rx USB HISR \n"); ++ }*/ ++ ++ rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); ++ ++ } ++ } ++ ++ // Page size of receive package is 128 bytes alignment =>DMA AGG ++ // refer to _InitTransferPageSize() ++ pkt_offset = _RND128(pkt_offset); ++ precvbuf->pdata += pkt_offset; ++ ptr = precvbuf->pdata; ++ ++ } ++ ++ rtw_skb_free(precvbuf->pskb); ++ precvbuf->pskb = NULL; ++ rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue); ++ ++ } while (1); ++ ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_xmit.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_xmit.c +new file mode 100644 +index 00000000..73c6a5a4 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/rtl8189es_xmit.c +@@ -0,0 +1,1720 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8189ES_XMIT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++static void fill_txdesc_sectype(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ if ((pattrib->encrypt > 0) && !pattrib->bswenc) ++ { ++ switch (pattrib->encrypt) ++ { ++ // SEC_TYPE ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ ptxdesc->sectype = 1; ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ ptxdesc->sectype = 2; ++ break; ++#endif ++ case _AES_: ++ ptxdesc->sectype = 3; ++ break; ++ ++ case _NO_PRIVACY_: ++ default: ++ break; ++ } ++ } ++} ++ ++ ++ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ //DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); ++ ++ switch (pattrib->vcs_mode) ++ { ++ case RTS_CTS: ++ ptxdesc->rtsen = 1; ++ break; ++ ++ case CTS_TO_SELF: ++ ptxdesc->cts2self = 1; ++ break; ++ ++ case NONE_VCS: ++ default: ++ break; ++ } ++ ++ if(pattrib->vcs_mode) { ++ ptxdesc->hw_rts_en = 1; // ENABLE HW RTS ++ ++ // Set RTS BW ++ if(pattrib->ht_en) ++ { ++ if (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ++ ptxdesc->rts_bw = 1; ++ ++ switch (pattrib->ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ ptxdesc->rts_sc = 0; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ ptxdesc->rts_sc = 1; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ ptxdesc->rts_sc = 2; ++ break; ++ ++ default: ++ ptxdesc->rts_sc = 3; // Duplicate ++ break; ++ } ++ } ++ } ++} ++ ++static void fill_txdesc_phy(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); ++ ++ if (pattrib->ht_en) ++ { ++ if (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ++ ptxdesc->data_bw = 1; ++ ++ switch (pattrib->ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ ptxdesc->data_sc = 0; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ ptxdesc->data_sc = 1; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ ptxdesc->data_sc = 2; ++ break; ++ ++ default: ++ ptxdesc->data_sc = 3; // Duplicate ++ break; ++ } ++ } ++} ++ ++static void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc) ++{ ++ u16 *usPtr = (u16*)ptxdesc; ++ u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times ++ u32 index; ++ u16 checksum = 0; ++ ++ ++ // Clear first ++ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); ++ ++ for (index = 0; index < count; index++) { ++ checksum ^= le16_to_cpu(*(usPtr + index)); ++ } ++ ++ ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff); ++} ++// ++// Description: In normal chip, we should send some packet to Hw which will be used by Fw ++// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then ++// Fw can tell Hw to send these packet derectly. ++// ++void rtl8188e_fill_fake_txdesc( ++ PADAPTER padapter, ++ u8* pDesc, ++ u32 BufferLen, ++ u8 IsPsPoll, ++ u8 IsBTQosNull) ++{ ++ struct tx_desc *ptxdesc; ++ ++ ++ // Clear all status ++ ptxdesc = (struct tx_desc*)pDesc; ++ _rtw_memset(pDesc, 0, TXDESC_SIZE); ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg; ++ ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<txdw1 |= cpu_to_le32(NAVUSEHDR); ++ } ++ else ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ } ++ ++ if (_TRUE == IsBTQosNull) ++ { ++ ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL ++ } ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++ // USB interface drop packet if the checksum of descriptor isn't correct. ++ // Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). ++ rtl8188e_cal_txdesc_chksum(ptxdesc); ++#endif ++} ++ ++ ++#define SDIO_TX_AGG_MAX (5) ++//#define CONFIG_FIX_CORE_DUMP ==> have bug ++//#define DBG_EMINFO ++ ++#if 0 ++void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc) ++{ ++ u16 *usPtr = (u16*)ptxdesc; ++ u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times ++ u32 index; ++ u16 checksum = 0; ++ ++ ++ // Clear first ++ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); ++ ++ for (index = 0; index < count; index++) { ++ checksum ^= le16_to_cpu(*(usPtr + index)); ++ } ++ ++ ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff); ++} ++ ++static void fill_txdesc_sectype(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ if ((pattrib->encrypt > 0) && !pattrib->bswenc) ++ { ++ switch (pattrib->encrypt) ++ { ++ // SEC_TYPE ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ ptxdesc->sectype = 1; ++ break; ++ ++ case _AES_: ++ ptxdesc->sectype = 3; ++ break; ++ ++ case _NO_PRIVACY_: ++ default: ++ break; ++ } ++ } ++} ++ ++static void fill_txdesc_vcs(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ //DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); ++ ++ switch (pattrib->vcs_mode) ++ { ++ case RTS_CTS: ++ ptxdesc->rtsen = 1; ++ break; ++ ++ case CTS_TO_SELF: ++ ptxdesc->cts2self = 1; ++ break; ++ ++ case NONE_VCS: ++ default: ++ break; ++ } ++ ++ if (pattrib->vcs_mode) ++ ptxdesc->hw_rts_en = 1; // ENABLE HW RTS ++} ++ ++static void fill_txdesc_phy(struct pkt_attrib *pattrib, PTXDESC ptxdesc) ++{ ++ //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); ++ ++ if (pattrib->ht_en) ++ { ++ if (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ++ ptxdesc->data_bw = 1; ++ ++ switch (pattrib->ch_offset) ++ { ++ case HAL_PRIME_CHNL_OFFSET_DONT_CARE: ++ ptxdesc->data_sc = 0; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_LOWER: ++ ptxdesc->data_sc = 1; ++ break; ++ ++ case HAL_PRIME_CHNL_OFFSET_UPPER: ++ ptxdesc->data_sc = 2; ++ break; ++ ++ default: ++ ptxdesc->data_sc = 3; // Duplicate ++ break; ++ } ++ } ++} ++#endif ++ ++void rtl8188es_fill_default_txdesc( ++ struct xmit_frame *pxmitframe, ++ u8 *pbuf) ++{ ++ PADAPTER padapter; ++ HAL_DATA_TYPE *pHalData; ++ struct mlme_ext_priv *pmlmeext; ++ struct mlme_ext_info *pmlmeinfo; ++ struct dm_priv *pdmpriv; ++ struct pkt_attrib *pattrib; ++ PTXDESC ptxdesc; ++ s32 bmcst; ++ ++ ++ padapter = pxmitframe->padapter; ++ pHalData = GET_HAL_DATA(padapter); ++ //pdmpriv = &pHalData->dmpriv; ++ pmlmeext = &padapter->mlmeextpriv; ++ pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ pattrib = &pxmitframe->attrib; ++ bmcst = IS_MCAST(pattrib->ra); ++ ++ ptxdesc = (PTXDESC)pbuf; ++ ++ ++ if (pxmitframe->frame_tag == DATA_FRAMETAG) ++ { ++ ptxdesc->macid = pattrib->mac_id; // CAM_ID(MAC_ID) ++ ++ if (pattrib->ampdu_en == _TRUE) ++ ptxdesc->agg_en = 1; // AGG EN ++ else ++ ptxdesc->bk = 1; // AGG BK ++ ++ ptxdesc->qsel = pattrib->qsel; ++ ptxdesc->rate_id = pattrib->raid; ++ ++ fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ ptxdesc->seq = pattrib->seqnum; ++ ++ //todo: qos_en ++ ++ ptxdesc->userate = 1; // driver uses rate ++ ++ if ((pattrib->ether_type != 0x888e) && ++ (pattrib->ether_type != 0x0806) && ++ (pattrib->dhcp_pkt != 1)) ++ { ++ // Non EAP & ARP & DHCP type data packet ++ ++ fill_txdesc_vcs(pattrib, ptxdesc); ++ fill_txdesc_phy(pattrib, ptxdesc); ++ ++ ptxdesc->rtsrate = 8; // RTS Rate=24M ++ ptxdesc->data_ratefb_lmt = 0x1F; ++ ptxdesc->rts_ratefb_lmt = 0xF; ++ #if (RATE_ADAPTIVE_SUPPORT == 1) ++ if(pattrib->ht_en){ ++ ptxdesc->sgi = ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id); ++ } ++ ptxdesc->datarate = ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id); ++ ++ //for debug ++ #if 1 ++ if(padapter->fix_rate!= 0xFF){ ++ ptxdesc->datarate = padapter->fix_rate; ++ } ++ #endif ++ #if (POWER_TRAINING_ACTIVE==1) ++ ptxdesc->pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id); ++ #endif ++ #else ++ ptxdesc->datarate = 0x13; //MCS7 ++ ptxdesc->sgi = 1; // SGI ++ if(padapter->fix_rate!= 0xFF){//modify datat by iwpriv ++ ptxdesc->datarate = padapter->fix_rate; ++ } ++ #endif ++ ++ ++ } ++ else ++ { ++ // EAP data packet and ARP and DHCP packet. ++ // Use the 1M or 6M data rate to send the EAP/ARP packet. ++ // This will maybe make the handshake smooth. ++ ++ ptxdesc->bk = 1; // AGG BK ++ ++ if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) ++ ptxdesc->data_short = 1;// DATA_SHORT ++ ++ ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); ++ } ++ ++ ptxdesc->usb_txagg_num = pxmitframe->agg_num; ++ } ++ else if (pxmitframe->frame_tag == MGNT_FRAMETAG) ++ { ++// RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MGNT_FRAMETAG\n", __FUNCTION__)); ++ ++ ptxdesc->macid = pattrib->mac_id; // CAM_ID(MAC_ID) ++ ptxdesc->qsel = pattrib->qsel; ++ ptxdesc->rate_id = pattrib->raid; // Rate ID ++ ptxdesc->seq = pattrib->seqnum; ++ ptxdesc->userate = 1; // driver uses rate, 1M ++ ptxdesc->rty_lmt_en = 1; // retry limit enable ++ ptxdesc->data_rt_lmt = 6; // retry limit = 6 ++ ++#ifdef CONFIG_XMIT_ACK ++ //CCX-TXRPT ack for xmit mgmt frames. ++ if (pxmitframe->ack_report) { ++ #ifdef DBG_CCX ++ static u16 ccx_sw = 0x123; ++ txdesc_set_ccx_sw_88e(ptxdesc, ccx_sw); ++ DBG_871X("%s set ccx, sw:0x%03x\n", __func__, ccx_sw); ++ ccx_sw = (ccx_sw+1)%0xfff; ++ #endif ++ ptxdesc->ccx = 1; ++ } ++#endif //CONFIG_XMIT_ACK ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){ ++ DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate); ++ ptxdesc->datarate = pattrib->rate; ++ } ++ else ++#endif ++ { ++ ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); ++ } ++ } ++ else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) ++ { ++ RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __FUNCTION__)); ++ } ++#ifdef CONFIG_MP_INCLUDED ++ else if (pxmitframe->frame_tag == MP_FRAMETAG) ++ { ++ struct tx_desc *pdesc; ++ ++ pdesc = (struct tx_desc*)ptxdesc; ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MP_FRAMETAG\n", __FUNCTION__)); ++ fill_txdesc_for_mp(padapter, pdesc); ++ ++ pdesc->txdw0 = le32_to_cpu(pdesc->txdw0); ++ pdesc->txdw1 = le32_to_cpu(pdesc->txdw1); ++ pdesc->txdw2 = le32_to_cpu(pdesc->txdw2); ++ pdesc->txdw3 = le32_to_cpu(pdesc->txdw3); ++ pdesc->txdw4 = le32_to_cpu(pdesc->txdw4); ++ pdesc->txdw5 = le32_to_cpu(pdesc->txdw5); ++ pdesc->txdw6 = le32_to_cpu(pdesc->txdw6); ++ pdesc->txdw7 = le32_to_cpu(pdesc->txdw7); ++ } ++#endif // CONFIG_MP_INCLUDED ++ else ++ { ++ RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag=0x%x\n", __FUNCTION__, pxmitframe->frame_tag)); ++ ++ ptxdesc->macid = 4; // CAM_ID(MAC_ID) ++ ptxdesc->rate_id = 6; // Rate ID ++ ptxdesc->seq = pattrib->seqnum; ++ ptxdesc->userate = 1; // driver uses rate ++ ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); ++ } ++ ++ ptxdesc->pktlen = pattrib->last_txcmdsz; ++ if (pxmitframe->frame_tag == DATA_FRAMETAG){ ++ #ifdef CONFIG_TX_EARLY_MODE ++ ptxdesc->offset = TXDESC_SIZE +EARLY_MODE_INFO_SIZE ; ++ ptxdesc->pkt_offset = 0x01; ++ #else ++ ptxdesc->offset = TXDESC_SIZE ; ++ ptxdesc->pkt_offset = 0; ++ #endif ++ } ++ else{ ++ ptxdesc->offset = TXDESC_SIZE ; ++ } ++ ++ if (bmcst) ptxdesc->bmc = 1; ++ ptxdesc->ls = 1; ++ ptxdesc->fs = 1; ++ ptxdesc->own = 1; ++ ++ // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. ++ // (1) The sequence number of each non-Qos frame / broadcast / multicast / ++ // mgnt frame should be controled by Hw because Fw will also send null data ++ // which we cannot control when Fw LPS enable. ++ // --> default enable non-Qos data sequense number. 2010.06.23. by tynli. ++ // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. ++ // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. ++ // 2010.06.23. Added by tynli. ++ if (!pattrib->qos_en) ++ { ++ // Hw set sequence number ++ ptxdesc->hwseq_en = 1; // HWSEQ_EN ++ ptxdesc->hwseq_sel = 0; // HWSEQ_SEL ++ } ++ ++} ++ ++/* ++ * Description: ++ * ++ * Parameters: ++ * pxmitframe xmitframe ++ * pbuf where to fill tx desc ++ */ ++void rtl8188es_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) ++{ ++ struct tx_desc *pdesc; ++ ++ ++ pdesc = (struct tx_desc*)pbuf; ++ _rtw_memset(pdesc, 0, sizeof(struct tx_desc)); ++ ++ rtl8188es_fill_default_txdesc(pxmitframe, pbuf); ++ ++ pdesc->txdw0 = cpu_to_le32(pdesc->txdw0); ++ pdesc->txdw1 = cpu_to_le32(pdesc->txdw1); ++ pdesc->txdw2 = cpu_to_le32(pdesc->txdw2); ++ pdesc->txdw3 = cpu_to_le32(pdesc->txdw3); ++ pdesc->txdw4 = cpu_to_le32(pdesc->txdw4); ++ pdesc->txdw5 = cpu_to_le32(pdesc->txdw5); ++ pdesc->txdw6 = cpu_to_le32(pdesc->txdw6); ++ pdesc->txdw7 = cpu_to_le32(pdesc->txdw7); ++ ++ rtl8188e_cal_txdesc_chksum(pdesc); ++} ++ ++static inline u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr) ++{ ++ return pdvobj->Queue2Pipe[addr]; ++} ++ ++#ifdef CONFIG_SDIO_REDUCE_TX_POLLING ++static u8 rtl8188es_query_tx_freepage(_adapter *padapter, struct xmit_buf *pxmitbuf) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ u8 TxRequiredPageNum = 0; ++ u8 DedicatedPgNum = 0; ++ u8 RequiredPublicFreePgNum = 0; ++ u8 PageIdx = 0; ++ u8 CheckStep = 0; ++ u8 bResult = _TRUE; ++ u8 bUpdatePageNum = _FALSE; ++ u32 deviceId; ++ ++ ++ TxRequiredPageNum = pxmitbuf->pg_num; ++ ++ deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr); ++ ++ // translate fifo addr to queue index ++ switch (deviceId) { ++ case WLAN_TX_HIQ_DEVICE_ID: ++ PageIdx = HI_QUEUE_IDX; ++ break; ++ ++ case WLAN_TX_MIQ_DEVICE_ID: ++ PageIdx = MID_QUEUE_IDX; ++ break; ++ ++ case WLAN_TX_LOQ_DEVICE_ID: ++ PageIdx = LOW_QUEUE_IDX; ++ break; ++ } ++ ++ do { ++ if ( ++ (padapter->bSurpriseRemoved == _TRUE) || (padapter->bDriverStopped == _TRUE) ++#ifdef CONFIG_CONCURRENT_MODE ++ ||((padapter->pbuddy_adapter) ++ && ((padapter->pbuddy_adapter->bSurpriseRemoved) ||(padapter->pbuddy_adapter->bDriverStopped))) ++#endif ++ ++ ){ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bSurpriseRemoved(update TX FIFO page)\n", __FUNCTION__)); ++ break; ++ } ++ ++ // The number of page which public page is included is available . ++ if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) > (TxRequiredPageNum+1)) { ++ DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx]; ++ if (TxRequiredPageNum <= DedicatedPgNum) { ++ pHalData->SdioTxFIFOFreePage[PageIdx] -= TxRequiredPageNum; ++ break; ++ } else { ++ pHalData->SdioTxFIFOFreePage[PageIdx] = 0; ++ RequiredPublicFreePgNum = TxRequiredPageNum - DedicatedPgNum; ++ pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum; ++ break; ++ } ++ } else { // Total number of page is NOT available, so update current FIFO status. ++ if (!bUpdatePageNum) { ++ bResult = HalQueryTxBufferStatus8189ESdio(padapter); // Set to default value. ++ bUpdatePageNum = _TRUE; ++ } else { ++ bResult = _FALSE; ++ } ++ } ++ }while(++CheckStep < 2); // step1: user page variables, step2: physical page number ++ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s(): HIQ(%#x), MIQ(%#x), LOQ(%#x), PUBQ(%#x)\n", ++ __FUNCTION__, ++ pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); ++ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s(): TxRequiredPageNum(%d) is available to send?(%d)\n", ++ __FUNCTION__, TxRequiredPageNum, bResult)); ++ ++ return bResult; ++} ++#else ++static u8 rtl8188es_query_tx_freepage(_adapter *padapter, struct xmit_buf *pxmitbuf) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ u8 TxRequiredPageNum = 0; ++ u8 DedicatedPgNum = 0; ++ u8 RequiredPublicFreePgNum = 0; ++ u8 PageIdx = 0; ++ u8 bResult = _TRUE; ++ u32 n, deviceId; ++ ++ TxRequiredPageNum = pxmitbuf->pg_num; ++ ++ deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr); ++ ++ // translate fifo addr to queue index ++ switch (deviceId) { ++ case WLAN_TX_HIQ_DEVICE_ID: ++ PageIdx = HI_QUEUE_IDX; ++ break; ++ ++ case WLAN_TX_MIQ_DEVICE_ID: ++ PageIdx = MID_QUEUE_IDX; ++ break; ++ ++ case WLAN_TX_LOQ_DEVICE_ID: ++ PageIdx = LOW_QUEUE_IDX; ++ break; ++ } ++ ++ // check if hardware tx fifo page is enough ++ n = 0; ++ do { ++ if ( ++ (padapter->bSurpriseRemoved == _TRUE) || (padapter->bDriverStopped == _TRUE) ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ||((padapter->pbuddy_adapter) ++ && ((padapter->pbuddy_adapter->bSurpriseRemoved) ||(padapter->pbuddy_adapter->bDriverStopped))) ++#endif ++ ){ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bSurpriseRemoved(update TX FIFO page)\n", __FUNCTION__)); ++ break; ++ } ++ ++ ++ // The number of page which public page is included is available . ++ if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) > (TxRequiredPageNum+1)) { ++ DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx]; ++ if (TxRequiredPageNum <= DedicatedPgNum) { ++ pHalData->SdioTxFIFOFreePage[PageIdx] -= TxRequiredPageNum; ++ break; ++ } else { ++ pHalData->SdioTxFIFOFreePage[PageIdx] = 0; ++ RequiredPublicFreePgNum = TxRequiredPageNum - DedicatedPgNum; ++ pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum; ++ break; ++ } ++ } ++ ++ n++; ++ ++#if 0 ++ if (n >= 5000) ++ { ++ u8 reg_value_1 = 0; ++ u8 reg_value_2 = 0; ++ u8 reg_value_3 = 0; ++ ++ //try to recover the transmission ++ reg_value_1 = rtw_read8(padapter, REG_SYS_FUNC_EN); ++ reg_value_2 = rtw_read8(padapter, REG_CR); ++ reg_value_3 = rtw_read8(padapter, REG_TXPAUSE); ++ DBG_871X("Before recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n", reg_value_1, reg_value_2, reg_value_3); ++ ++ rtw_write8(padapter, REG_SYS_FUNC_EN, reg_value_1 | 0x01); ++ rtw_write8(padapter, REG_CR, reg_value_2 | 0xC0); ++ rtw_write8(padapter, REG_TXPAUSE, 0); ++ DBG_871X("After recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n", ++ rtw_read8(padapter, REG_SYS_FUNC_EN), rtw_read8(padapter, REG_CR), rtw_read8(padapter, REG_TXPAUSE)); ++ } ++#endif ++ ++ if ((n % 60) == 0) {//or 80 ++ //DBG_871X("%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n", ++ // __func__, n, pxmitbuf->len, pxmitbuf->agg_num, pframe->pg_num, freePage[PageIdx] + freePage[PUBLIC_QUEUE_IDX]); ++ rtw_msleep_os(10); ++ rtw_yield_os(); ++ } ++ ++ // Total number of page is NOT available, so update current FIFO status ++ HalQueryTxBufferStatus8189ESdio(padapter); ++ } while (1); ++ ++ return bResult; ++} ++#endif ++ ++//todo: static ++s32 rtl8188es_dequeue_writeport(PADAPTER padapter, u8 *freePage) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct xmit_buf *pxmitbuf; ++ PADAPTER pri_padapter = padapter; ++ s32 ret = 0; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->adapter_type > 0) ++ pri_padapter = padapter->pbuddy_adapter; ++ ++ if(rtw_buddy_adapter_up(padapter)) ++ ret = check_buddy_fwstate( padapter, _FW_UNDER_SURVEY); ++#endif ++ ++ ret = ret || check_fwstate(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ if (_TRUE == ret) ++ pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv); ++ else ++ pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); ++ ++ if (pxmitbuf == NULL) ++ return _TRUE; ++ ++query_free_page: ++ // check if hardware tx fifo page is enough ++ if( _FALSE == rtl8188es_query_tx_freepage(pri_padapter, pxmitbuf)) ++ { ++ rtw_msleep_os(1); ++ goto query_free_page; ++ } ++ ++ if ((padapter->bSurpriseRemoved == _TRUE) ++ || (padapter->bDriverStopped == _TRUE) ++#ifdef CONFIG_CONCURRENT_MODE ++ ||((padapter->pbuddy_adapter) ++ && ((padapter->pbuddy_adapter->bSurpriseRemoved) ||(padapter->pbuddy_adapter->bDriverStopped))) ++#endif ++ ){ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bSurpriseRemoved(wirte port)\n", __FUNCTION__)); ++ goto free_xmitbuf; ++ } ++ ++ rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, (u8 *)pxmitbuf); ++ ++free_xmitbuf: ++ //rtw_free_xmitframe(pxmitpriv, pframe); ++ //pxmitbuf->priv_data = NULL; ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ ++#ifdef CONFIG_SDIO_TX_TASKLET ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++#endif ++ ++ return _FAIL; ++} ++ ++/* ++ * Description ++ * Transmit xmitbuf to hardware tx fifo ++ * ++ * Return ++ * _SUCCESS ok ++ * _FAIL something error ++ */ ++s32 rtl8188es_xmit_buf_handler(PADAPTER padapter) ++{ ++ struct mlme_priv *pmlmepriv; ++ struct xmit_priv *pxmitpriv; ++ struct xmit_buf *pxmitbuf; ++ struct xmit_frame *pframe; ++ u8 *freePage; ++ u32 requiredPage; ++ u8 PageIdx , queue_empty; ++ _irqL irql; ++ u32 n; ++ s32 ret; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#ifdef CONFIG_CONCURRENT_MODE ++ s32 buddy_rm_stop = _FAIL; ++#endif ++ ++ pmlmepriv = &padapter->mlmepriv; ++ pxmitpriv = &padapter->xmitpriv; ++ freePage = pHalData->SdioTxFIFOFreePage; ++ ++ ret = _rtw_down_sema(&pxmitpriv->xmit_sema); ++ if (ret == _FAIL) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ("down SdioXmitBufSema fail!\n")); ++ return _FAIL; ++ } ++ ++//#ifdef CONFIG_CONCURRENT_MODE ++// if (padapter->pbuddy_adapter->bup){ ++// if ((padapter->pbuddy_adapter->bSurpriseRemoved == _TRUE) || ++// (padapter->pbuddy_adapter->bDriverStopped == _TRUE)) ++// buddy_rm_stop = _TRUE; ++// } ++//#endif ++ if ((padapter->bSurpriseRemoved == _TRUE) || ++ (padapter->bDriverStopped == _TRUE) ++//#ifdef CONFIG_CONCURRENT_MODE ++// ||(buddy_rm_stop == _TRUE) ++//#endif ++ ) { ++ ++#ifdef CONFIG_LPS_LCLK ++ rtw_unregister_tx_alive(padapter); ++#endif ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n", ++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ return _FAIL; ++ } ++ ++#ifdef CONFIG_LPS_LCLK ++ ret = rtw_register_tx_alive(padapter); ++ if (ret != _SUCCESS) return _SUCCESS; ++#endif ++ ++ do { ++ queue_empty = rtl8188es_dequeue_writeport(padapter, freePage); ++// dump secondary adapter xmitbuf ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ queue_empty &= rtl8188es_dequeue_writeport(padapter->pbuddy_adapter, freePage); ++#endif ++ ++ } while ( !queue_empty); ++ ++#ifdef CONFIG_LPS_LCLK ++ rtw_unregister_tx_alive(padapter); ++#endif ++ return _SUCCESS; ++} ++ ++#if 0 ++/* ++ * Description: ++ * Aggregation packets and send to hardware ++ * ++ * Return: ++ * 0 Success ++ * -1 Hardware resource(TX FIFO) not ready ++ * -2 Software resource(xmitbuf) not ready ++ */ ++#ifdef CONFIG_TX_EARLY_MODE ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ #define EARLY_MODE_MAX_PKT_NUM 10 ++#else ++ #define EARLY_MODE_MAX_PKT_NUM 5 ++#endif ++ ++ ++struct EMInfo{ ++ u8 EMPktNum; ++ u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM]; ++}; ++ ++ ++void ++InsertEMContent_8188E( ++ struct EMInfo *pEMInfo, ++ IN pu1Byte VirtualAddress) ++{ ++ ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ u1Byte index=0; ++ u4Byte dwtmp=0; ++#endif ++ ++ _rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE); ++ if(pEMInfo->EMPktNum==0) ++ return; ++ ++ #ifdef DBG_EMINFO ++ { ++ int i; ++ DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum); ++ for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){ ++ DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]); ++ } ++ ++ } ++ #endif ++ ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum); ++ ++ if(pEMInfo->EMPktNum == 1){ ++ dwtmp = pEMInfo->EMPktLen[0]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[0]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[1]; ++ } ++ SET_EARLYMODE_LEN0(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 3){ ++ dwtmp = pEMInfo->EMPktLen[2]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[2]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[3]; ++ } ++ SET_EARLYMODE_LEN1(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 5){ ++ dwtmp = pEMInfo->EMPktLen[4]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[4]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[5]; ++ } ++ SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF); ++ SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4); ++ if(pEMInfo->EMPktNum <= 7){ ++ dwtmp = pEMInfo->EMPktLen[6]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[6]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[7]; ++ } ++ SET_EARLYMODE_LEN3(VirtualAddress, dwtmp); ++ if(pEMInfo->EMPktNum <= 9){ ++ dwtmp = pEMInfo->EMPktLen[8]; ++ }else{ ++ dwtmp = pEMInfo->EMPktLen[8]; ++ dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4; ++ dwtmp += pEMInfo->EMPktLen[9]; ++ } ++ SET_EARLYMODE_LEN4(VirtualAddress, dwtmp); ++#else ++ SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum); ++ SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]); ++ SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]); ++ SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF); ++ SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4); ++ SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]); ++ SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]); ++#endif ++ //RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8); ++ ++} ++ ++ ++ ++void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf ) ++{ ++ //_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq ++ int index,j; ++ u16 offset,pktlen; ++ PTXDESC ptxdesc; ++ ++ u8 *pmem,*pEMInfo_mem; ++ s8 node_num_0=0,node_num_1=0; ++ struct EMInfo eminfo; ++ struct agg_pkt_info *paggpkt; ++ struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data; ++ pmem= pframe->buf_addr; ++ ++ #ifdef DBG_EMINFO ++ DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num); ++ for(index=0;indexagg_num;index++){ ++ offset = pxmitpriv->agg_pkt[index].offset; ++ pktlen = pxmitpriv->agg_pkt[index].pkt_len; ++ DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset); ++ DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen); ++ } ++ #endif ++ ++ if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM) ++ { ++ node_num_0 = pframe->agg_num; ++ node_num_1= EARLY_MODE_MAX_PKT_NUM-1; ++ } ++ ++ for(index=0;indexagg_num;index++){ ++ offset = pxmitpriv->agg_pkt[index].offset; ++ pktlen = pxmitpriv->agg_pkt[index].pkt_len; ++ ++ _rtw_memset(&eminfo,0,sizeof(struct EMInfo)); ++ if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){ ++ if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){ ++ eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM; ++ node_num_0--; ++ } ++ else{ ++ eminfo.EMPktNum = node_num_1; ++ node_num_1--; ++ } ++ } ++ else{ ++ eminfo.EMPktNum = pframe->agg_num-(index+1); ++ } ++ for(j=0;j< eminfo.EMPktNum ;j++){ ++ eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;//CRC ++ } ++ ++ if(pmem){ ++ ptxdesc = (PTXDESC)(pmem+offset); ++ pEMInfo_mem = pmem+offset+TXDESC_SIZE; ++ #ifdef DBG_EMINFO ++ DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen); ++ #endif ++ InsertEMContent_8188E(&eminfo,pEMInfo_mem); ++ } ++ ++ ++ } ++ _rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM); ++ ++} ++#endif ++ ++#endif ++ ++#ifdef CONFIG_SDIO_TX_TASKLET ++static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv) ++{ ++ s32 ret; ++ _irqL irqL; ++ struct xmit_buf *pxmitbuf; ++ struct hw_xmit *phwxmit = pxmitpriv->hwxmits; ++ struct tx_servq *ptxservq = NULL; ++ _list *xmitframe_plist = NULL, *xmitframe_phead = NULL; ++ struct xmit_frame *pxmitframe = NULL, *pfirstframe = NULL; ++ u32 pbuf = 0; // next pkt address ++ u32 pbuf_tail = 0; // last pkt tail ++ u32 txlen = 0; //packet length, except TXDESC_SIZE and PKT_OFFSET ++ u32 total_len = 0; ++ u8 ac_index = 0; ++ u8 bfirst = _TRUE;//first aggregation xmitframe ++ u8 bulkstart = _FALSE; ++#ifdef CONFIG_TX_EARLY_MODE ++ u8 pkt_index=0; ++#endif ++ ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: xmit_buf is not enough!\n", __FUNCTION__)); ++ return _FALSE; ++ } ++ ++ do { ++ //3 1. pick up first frame ++ if(bfirst) ++ { ++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); ++ if (pxmitframe == NULL) { ++ // no more xmit frame, release xmit buffer ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ return _FALSE; ++ } ++ ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pxmitframe; ++ pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); ++ ++ pfirstframe = pxmitframe; ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ptxservq = rtw_get_sta_pending(padapter, pfirstframe->attrib.psta, pfirstframe->attrib.priority, (u8 *)(&ac_index)); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ } ++ //3 2. aggregate same priority and same DA(AP or STA) frames ++ else ++ { ++ // dequeue same priority packet from station tx queue ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if (_rtw_queue_empty(&ptxservq->sta_pending) == _FALSE) ++ { ++ xmitframe_phead = get_list_head(&ptxservq->sta_pending); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ // check xmit_buf size enough or not ++ txlen = TXDESC_SIZE + ++ #ifdef CONFIG_TX_EARLY_MODE ++ EARLY_MODE_INFO_SIZE + ++ #endif ++ rtw_wlan_pkt_size(pxmitframe); ++ ++ if (pbuf + _RND8(txlen) > MAX_XMITBUF_SZ) ++ { ++ bulkstart = _TRUE; ++ } ++ else ++ { ++ rtw_list_delete(&pxmitframe->list); ++ ptxservq->qcnt--; ++ phwxmit[ac_index].accnt--; ++ ++ //Remove sta node when there is no pending packets. ++ if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE) ++ rtw_list_delete(&ptxservq->tx_pending); ++ } ++ } ++ else ++ { ++ bulkstart = _TRUE; ++ } ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if(bulkstart) ++ { ++ break; ++ } ++ ++ pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; ++ ++ pxmitframe->agg_num = 0; // not first frame of aggregation ++ } ++ ++ ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (ret == _FAIL) { ++ DBG_871X("%s: coalesce FAIL!", __FUNCTION__); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ // always return ndis_packet after rtw_xmitframe_coalesce ++ //rtw_os_xmit_complete(padapter, pxmitframe); ++ ++#ifdef CONFIG_TX_EARLY_MODE ++ pxmitpriv->agg_pkt[pkt_index].pkt_len = pxmitframe->attrib.last_txcmdsz; //get from rtw_xmitframe_coalesce ++ pxmitpriv->agg_pkt[pkt_index].offset = _RND8(pxmitframe->attrib.last_txcmdsz+ TXDESC_SIZE+EARLY_MODE_INFO_SIZE); ++ pkt_index++; ++#endif ++ ++ if(bfirst) ++ { ++ txlen = TXDESC_SIZE + ++ #ifdef CONFIG_TX_EARLY_MODE ++ EARLY_MODE_INFO_SIZE + ++ #endif ++ pxmitframe->attrib.last_txcmdsz; ++ ++ total_len = txlen; ++ ++ pxmitframe->pg_num = (txlen + 127)/128; ++ pxmitbuf->pg_num = (txlen + 127)/128; ++ pbuf_tail = txlen; ++ pbuf = _RND8(pbuf_tail); ++ bfirst = _FALSE; ++ } ++ else ++ { ++ rtl8188es_update_txdesc(pxmitframe, pxmitframe->buf_addr); ++ ++ // don't need xmitframe any more ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ pxmitframe->pg_num = (txlen + 127)/128; ++ //pfirstframe->pg_num += pxmitframe->pg_num; ++ pxmitbuf->pg_num += (txlen + 127)/128; ++ ++ total_len += txlen; ++ ++ // handle pointer and stop condition ++ pbuf_tail = pbuf + txlen; ++ pbuf = _RND8(pbuf_tail); ++ ++ pfirstframe->agg_num++; ++ #ifdef SDIO_TX_AGG_MAX ++ if(pfirstframe->agg_num >= SDIO_TX_AGG_MAX) ++ break; ++ #endif ++ } ++ }while(1); ++ ++ //3 3. update first frame txdesc ++ rtl8188es_update_txdesc(pfirstframe, pfirstframe->buf_addr); ++#ifdef CONFIG_TX_EARLY_MODE ++ UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf ); ++#endif ++ ++ // ++ pxmitbuf->agg_num = pfirstframe->agg_num; ++ pxmitbuf->priv_data = NULL; ++ ++ //3 4. write xmit buffer to USB FIFO ++ pxmitbuf->len = pbuf_tail; ++ enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); ++ ++ //3 5. update statisitc ++ rtw_count_tx_stats(padapter, pfirstframe, total_len); ++ ++ rtw_free_xmitframe(pxmitpriv, pfirstframe); ++ ++ //rtw_yield_os(); ++ ++ return _TRUE; ++} ++ ++void rtl8188es_xmit_tasklet(void *priv) ++{ ++ int ret = _FALSE; ++ _adapter *padapter = (_adapter*)priv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ while(1) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE)) ++ { ++ DBG_871X("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n"); ++ break; ++ } ++ ++ ret = xmit_xmitframes(padapter, pxmitpriv); ++ if(ret==_FALSE) ++ break; ++ ++ } ++} ++#else ++static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv) ++{ ++ u32 err, agg_num=0; ++ u8 pkt_index=0; ++ struct hw_xmit *hwxmits, *phwxmit; ++ u8 idx, hwentry; ++ _irqL irql; ++ struct tx_servq *ptxservq; ++ _list *sta_plist, *sta_phead, *frame_plist, *frame_phead; ++ struct xmit_frame *pxmitframe; ++ _queue *pframe_queue; ++ struct xmit_buf *pxmitbuf; ++ u32 txlen; ++ s32 ret; ++ int inx[4]; ++ ++ err = 0; ++ hwxmits = pxmitpriv->hwxmits; ++ hwentry = pxmitpriv->hwxmit_entry; ++ ptxservq = NULL; ++ pxmitframe = NULL; ++ pframe_queue = NULL; ++ pxmitbuf = NULL; ++ ++ if (padapter->registrypriv.wifi_spec == 1) { ++ for(idx=0; idx<4; idx++) ++ inx[idx] = pxmitpriv->wmm_para_seq[idx]; ++ } else { ++ inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; ++ } ++ ++ // 0(VO), 1(VI), 2(BE), 3(BK) ++ for (idx = 0; idx < hwentry; idx++) ++ { ++ phwxmit = hwxmits + inx[idx]; ++ ++// _enter_critical(&hwxmits->sta_queue->lock, &irqL0); ++ _enter_critical_bh(&pxmitpriv->lock, &irql); ++ ++ sta_phead = get_list_head(phwxmit->sta_queue); ++ sta_plist = get_next(sta_phead); ++ ++ while (rtw_end_of_queue_search(sta_phead, sta_plist) == _FALSE) ++ { ++ ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); ++ ++ sta_plist = get_next(sta_plist); ++ ++ pframe_queue = &ptxservq->sta_pending; ++ ++// _enter_critical(&pframe_queue->lock, &irqL1); ++ //_enter_critical_bh(&pxmitpriv->lock, &irql); ++ ++ frame_phead = get_list_head(pframe_queue); ++ frame_plist = get_next(frame_phead); ++ ++ while (rtw_end_of_queue_search(frame_phead, frame_plist) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(frame_plist, struct xmit_frame, list); ++ ++ // check xmit_buf size enough or not ++ #ifdef CONFIG_TX_EARLY_MODE ++ txlen = TXDESC_SIZE +EARLY_MODE_INFO_SIZE+ rtw_wlan_pkt_size(pxmitframe); ++ #else ++ txlen = TXDESC_SIZE + rtw_wlan_pkt_size(pxmitframe); ++ #endif ++ if ((NULL == pxmitbuf) || ++ ((pxmitbuf->ptail + txlen) > pxmitbuf->pend) ++ #ifdef SDIO_TX_AGG_MAX ++ || (agg_num>= SDIO_TX_AGG_MAX) ++ #endif ++ ) ++ { ++ if (pxmitbuf) { ++ struct xmit_frame *pframe; ++ pframe = (struct xmit_frame*)pxmitbuf->priv_data; ++ pframe->agg_num = agg_num; ++ pxmitbuf->agg_num = agg_num; ++ //DBG_8192C("==> agg_num:%d\n",agg_num); ++ rtl8188es_update_txdesc(pframe, pframe->buf_addr); ++ #ifdef CONFIG_TX_EARLY_MODE ++ UpdateEarlyModeInfo8188E(pxmitpriv, pxmitbuf); ++ #endif ++ rtw_free_xmitframe(pxmitpriv, pframe); ++ pxmitbuf->priv_data = NULL; ++ enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); ++ //rtw_yield_os(); ++ } ++ ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: xmit_buf is not enough!\n", __FUNCTION__)); ++ err = -2; ++ break; ++ } ++ agg_num = 0; ++ pkt_index =0; ++ } ++ ++ // ok to send, remove frame from queue ++ ++ ++ frame_plist = get_next(frame_plist); ++ rtw_list_delete(&pxmitframe->list); ++ ptxservq->qcnt--; ++ phwxmit->accnt--; ++ ++ ++ if (agg_num == 0) { ++ pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); ++ pxmitbuf->priv_data = (u8*)pxmitframe; ++ } ++ ++ // coalesce the xmitframe to xmitbuf ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->ptail; ++ ++ ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (ret == _FAIL) { ++ DBG_871X("%s: coalesce FAIL!", __FUNCTION__); ++ // Todo: error handler ++ //rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ } else { ++ agg_num++; ++ if (agg_num != 1) ++ rtl8188es_update_txdesc(pxmitframe, pxmitframe->buf_addr); ++ rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz); ++ #ifdef CONFIG_TX_EARLY_MODE ++ txlen = TXDESC_SIZE+ EARLY_MODE_INFO_SIZE+ pxmitframe->attrib.last_txcmdsz; ++ #else ++ txlen = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz; ++ #endif ++ pxmitframe->pg_num = (txlen + 127)/128; ++ pxmitbuf->pg_num += (txlen + 127)/128; ++ //if (agg_num != 1) ++ //((struct xmit_frame*)pxmitbuf->priv_data)->pg_num += pxmitframe->pg_num; ++ ++ #ifdef CONFIG_TX_EARLY_MODE ++ pxmitpriv->agg_pkt[pkt_index].pkt_len = pxmitframe->attrib.last_txcmdsz; //get from rtw_xmitframe_coalesce ++ pxmitpriv->agg_pkt[pkt_index].offset = _RND8(pxmitframe->attrib.last_txcmdsz+ TXDESC_SIZE+EARLY_MODE_INFO_SIZE); ++ #endif ++ ++ pkt_index++; ++ pxmitbuf->ptail += _RND(txlen, 8); // round to 8 bytes alignment ++ pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen; ++ } ++ ++ if (agg_num != 1) ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ pxmitframe = NULL; ++ } ++ ++ if (_rtw_queue_empty(pframe_queue)) { ++ rtw_list_delete(&ptxservq->tx_pending); ++ } ++ ++// _exit_critical(&pframe_queue->lock, &irqL1); ++ //_exit_critical_bh(&pxmitpriv->lock, &irql); ++ ++ } ++ ++// _exit_critical(&hwxmits->sta_queue->lock, &irqL0); ++ _exit_critical_bh(&pxmitpriv->lock, &irql); ++ ++ // dump xmit_buf to hw tx fifo ++ if (pxmitbuf) ++ { ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("pxmitbuf->len=%d enqueue\n",pxmitbuf->len)); ++ ++ if (pxmitbuf->len > 0) { ++ struct xmit_frame *pframe; ++ pframe = (struct xmit_frame*)pxmitbuf->priv_data; ++ pframe->agg_num = agg_num; ++ pxmitbuf->agg_num = agg_num; ++ rtl8188es_update_txdesc(pframe, pframe->buf_addr); ++ #ifdef CONFIG_TX_EARLY_MODE ++ UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf ); ++ #endif ++ rtw_free_xmitframe(pxmitpriv, pframe); ++ pxmitbuf->priv_data = NULL; ++ enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); ++ rtw_yield_os(); ++ } ++ else ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ ++ pxmitbuf = NULL; ++ ++ } ++ ++ } ++ ++ return err; ++ ++} ++ ++/* ++ * Description ++ * Transmit xmitframe from queue ++ * ++ * Return ++ * _SUCCESS ok ++ * _FAIL something error ++ */ ++s32 rtl8188es_xmit_handler(PADAPTER padapter) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv ; ++ s32 ret; ++ _irqL irql; ++//#ifdef CONFIG_CONCURRENT_MODE ++// s32 buddy_rm_stop = _FAIL; ++//#endif ++ ++ ++wait: ++ ret = _rtw_down_sema(&pxmitpriv->SdioXmitSema); ++ if (_FAIL == ret) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ("%s: down sema fail!\n", __FUNCTION__)); ++ return _FAIL; ++ } ++ ++next: ++//#ifdef CONFIG_CONCURRENT_MODE ++// if (padapter->pbuddy_adapter){ ++// if ((padapter->pbuddy_adapter->bSurpriseRemoved == _TRUE) || ++// (padapter->pbuddy_adapter->bDriverStopped == _TRUE)) ++// buddy_rm_stop = _TRUE; ++// } ++//#endif ++ if ((padapter->bSurpriseRemoved == _TRUE) || ++ (padapter->bDriverStopped == _TRUE) ++//#ifdef CONFIG_CONCURRENT_MODE ++// ||(buddy_rm_stop == _TRUE) ++//#endif ++ ) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n", ++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ return _FAIL; ++ } ++ _enter_critical_bh(&pxmitpriv->lock, &irql); ++ ret = rtw_txframes_pending(padapter); ++ _exit_critical_bh(&pxmitpriv->lock, &irql); ++ if (ret == 0) { ++ return _SUCCESS; ++ } ++ // dequeue frame and write to hardware ++ ++ ret = xmit_xmitframes(padapter, pxmitpriv); ++ if (ret == -2) { ++ rtw_msleep_os(1); ++ goto next; ++ } ++ _enter_critical_bh(&pxmitpriv->lock, &irql); ++ ret = rtw_txframes_pending(padapter); ++ _exit_critical_bh(&pxmitpriv->lock, &irql); ++ if (ret == 1) { ++ rtw_msleep_os(1); ++ goto next; ++ } ++ ++ return _SUCCESS; ++} ++ ++thread_return rtl8188es_xmit_thread(thread_context context) ++{ ++ s32 ret; ++ PADAPTER padapter= (PADAPTER)context; ++ struct xmit_priv *pxmitpriv= &padapter->xmitpriv; ++ ++ ret = _SUCCESS; ++ ++ thread_enter("RTWHALXT"); ++ ++ DBG_871X("start %s\n", __FUNCTION__); ++ ++ do { ++ ret = rtl8188es_xmit_handler(padapter); ++ if (signal_pending(current)) { ++ flush_signals(current); ++ } ++ } while (_SUCCESS == ret); ++ ++ _rtw_up_sema(&pxmitpriv->SdioXmitTerminateSema); ++ ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("-%s\n", __FUNCTION__)); ++ DBG_871X("exit %s\n", __FUNCTION__); ++ ++ thread_exit(); ++} ++#endif ++ ++#ifdef CONFIG_IOL_IOREG_CFG_DBG ++#include ++#endif ++s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe) ++{ ++ s32 ret = _SUCCESS; ++ struct pkt_attrib *pattrib; ++ struct xmit_buf *pxmitbuf; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ u8 *pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ u8 pattrib_subtype; ++ ++ RT_TRACE(_module_hal_xmit_c_, _drv_info_, ("+%s\n", __FUNCTION__)); ++ ++ pattrib = &pmgntframe->attrib; ++ pxmitbuf = pmgntframe->pxmitbuf; ++ ++ rtl8188es_update_txdesc(pmgntframe, pmgntframe->buf_addr); ++ ++ pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; ++ //pmgntframe->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size ++ pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size ++ pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len; ++ pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe); ++ ++ rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz); ++ pattrib_subtype = pattrib->subtype; ++ rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ ++ pxmitbuf->priv_data = NULL; ++ ++ if((pattrib_subtype == WIFI_BEACON) || (GetFrameSubType(pframe)==WIFI_BEACON)) //dump beacon directly ++ { ++#ifdef CONFIG_IOL_IOREG_CFG_DBG ++ rtw_IOL_cmd_buf_dump(padapter,pxmitbuf->len,pxmitbuf->pdata); ++#endif ++ ++ rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, (u8 *)pxmitbuf); ++ ++ //rtw_free_xmitframe(pxmitpriv, pmgntframe); ++ ++ //pxmitbuf->priv_data = NULL; ++ ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ } ++ else ++ { ++ enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); ++ } ++ ++ if (ret != _SUCCESS) ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); ++ ++ return ret; ++} ++ ++/* ++ * Description: ++ * Handle xmitframe(packet) come from rtw_xmit() ++ * ++ * Return: ++ * _TRUE dump packet directly ok ++ * _FALSE enqueue, temporary can't transmit packets to hardware ++ */ ++s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irql; ++ s32 err; ++ ++ //pxmitframe->attrib.qsel = pxmitframe->attrib.priority; ++ ++#ifdef CONFIG_80211N_HT ++ if ((pxmitframe->frame_tag == DATA_FRAMETAG) && ++ (pxmitframe->attrib.ether_type != 0x0806) && ++ (pxmitframe->attrib.ether_type != 0x888e) && ++ (pxmitframe->attrib.dhcp_pkt != 1)) ++ { ++ if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) ++ rtw_issue_addbareq_cmd(padapter, pxmitframe); ++ } ++#endif ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irql); ++ err = rtw_xmitframe_enqueue(padapter, pxmitframe); ++ _exit_critical_bh(&pxmitpriv->lock, &irql); ++ if (err != _SUCCESS) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: enqueue xmitframe fail\n",__FUNCTION__)); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ // Trick, make the statistics correct ++ pxmitpriv->tx_pkts--; ++ pxmitpriv->tx_drop++; ++ return _TRUE; ++ } ++ ++#ifdef CONFIG_SDIO_TX_TASKLET ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++#else ++ _rtw_up_sema(&pxmitpriv->SdioXmitSema); ++#endif ++ ++ return _FALSE; ++} ++ ++s32 rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ s32 err; ++ ++ if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) ++ { ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ // Trick, make the statistics correct ++ pxmitpriv->tx_pkts--; ++ pxmitpriv->tx_drop++; ++ } ++ else ++ { ++#ifdef CONFIG_SDIO_TX_TASKLET ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++#else ++ _rtw_up_sema(&pxmitpriv->SdioXmitSema); ++#endif ++ } ++ ++ return err; ++ ++} ++ ++ ++/* ++ * Return ++ * _SUCCESS start thread ok ++ * _FAIL start thread fail ++ * ++ */ ++s32 rtl8188es_init_xmit_priv(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++#ifdef CONFIG_SDIO_TX_TASKLET ++#ifdef PLATFORM_LINUX ++ tasklet_init(&pxmitpriv->xmit_tasklet, ++ (void(*)(unsigned long))rtl8188es_xmit_tasklet, ++ (unsigned long)padapter); ++#endif ++#else //CONFIG_SDIO_TX_TASKLET ++ ++ _rtw_init_sema(&pxmitpriv->SdioXmitSema, 0); ++ _rtw_init_sema(&pxmitpriv->SdioXmitTerminateSema, 0); ++#endif //CONFIG_SDIO_TX_TASKLET ++ ++ _rtw_spinlock_init(&pHalData->SdioTxFIFOFreePageLock); ++ ++#ifdef CONFIG_TX_EARLY_MODE ++ pHalData->bEarlyModeEnable = padapter->registrypriv.early_mode; ++#endif ++ ++ return _SUCCESS; ++} ++ ++void rtl8188es_free_xmit_priv(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ _rtw_spinlock_free(&pHalData->SdioTxFIFOFreePageLock); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_halinit.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_halinit.c +new file mode 100644 +index 00000000..c3ae471e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_halinit.c +@@ -0,0 +1,4218 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _SDIO_HALINIT_C_ ++ ++#include ++#include ++#include ++ ++#ifndef CONFIG_SDIO_HCI ++#error "CONFIG_SDIO_HCI shall be on!\n" ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++#include ++#include ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++ ++/* ++ * Description: ++ * Call this function to make sure power on successfully ++ * ++ * Return: ++ * _SUCCESS enable success ++ * _FAIL enable fail ++ */ ++ ++static int PowerOnCheck(PADAPTER padapter) ++{ ++ u32 val_offset0, val_offset1, val_offset2, val_offset3; ++ u32 val_mix = 0; ++ u32 res = 0; ++ u8 ret = _FAIL; ++ int index = 0; ++ ++ val_offset0 = rtw_read8(padapter, REG_CR); ++ val_offset1 = rtw_read8(padapter, REG_CR+1); ++ val_offset2 = rtw_read8(padapter, REG_CR+2); ++ val_offset3 = rtw_read8(padapter, REG_CR+3); ++ ++ if (val_offset0 == 0xEA || val_offset1 == 0xEA || ++ val_offset2 == 0xEA || val_offset3 ==0xEA) { ++ DBG_871X("%s: power on fail, do Power on again\n", __func__); ++ return ret; ++ } ++ ++ val_mix = val_offset3 << 24 | val_mix; ++ val_mix = val_offset2 << 16 | val_mix; ++ val_mix = val_offset1 << 8 | val_mix; ++ val_mix = val_offset0 | val_mix; ++ ++ res = rtw_read32(padapter, REG_CR); ++ ++ DBG_871X("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res); ++ ++ while(index < 100) { ++ if (res == val_mix) { ++ DBG_871X("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__); ++ ret = _SUCCESS; ++ break; ++ } else { ++ DBG_871X("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index); ++ res = rtw_read32(padapter, REG_CR); ++ index ++; ++ ret = _FAIL; ++ } ++ } ++ ++ if (ret) { ++ index = 0; ++ while(index < 100) { ++ rtw_write32(padapter, 0x1B8, 0x12345678); ++ res = rtw_read32(padapter, 0x1B8); ++ if (res == 0x12345678) { ++ DBG_871X("%s: 0x1B8 test Pass.\n", __func__); ++ ret = _SUCCESS; ++ break; ++ } else { ++ index ++; ++ DBG_871X("%s: 0x1B8 test Fail(index: %d).\n", __func__, index); ++ ret = _FAIL; ++ } ++ } ++ } else { ++ DBG_871X("%s: fail at cmd52, cmd53.\n", __func__); ++ } ++ return ret; ++} ++ ++#ifdef CONFIG_EXT_CLK ++void EnableGpio5ClockReq(PADAPTER Adapter, u8 in_interrupt, u32 Enable) ++{ ++ u32 value32; ++ HAL_DATA_TYPE *pHalData; ++ ++ pHalData = GET_HAL_DATA(Adapter); ++ if(IS_D_CUT(pHalData->VersionID)) ++ return; ++ ++ //dbgdump("%s Enable:%x time:%d", __RTL_FUNC__, Enable, rtw_get_current_time()); ++ ++ if(in_interrupt) ++ value32 = _sdio_read32(Adapter, REG_GPIO_PIN_CTRL); ++ else ++ value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL); ++ ++ //open GPIO 5 ++ if (Enable) ++ value32 |= BIT(13);//5+8 ++ else ++ value32 &= ~BIT(13); ++ ++ //GPIO 5 out put ++ value32 |= BIT(21);//5+16 ++ ++ //if (Enable) ++ // rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x20); ++ //else ++ // rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x00); ++ ++ if(in_interrupt) ++ _sdio_write32(Adapter, REG_GPIO_PIN_CTRL, value32); ++ else ++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32); ++ ++} //end of _rtl8192cs_disable_gpio() ++ ++void _InitClockTo26MHz( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 u1temp = 0; ++ HAL_DATA_TYPE *pHalData; ++ ++ pHalData = GET_HAL_DATA(Adapter); ++ ++ if(IS_D_CUT(pHalData->VersionID)) { ++ //FW special init ++ u1temp = rtw_read8(Adapter, REG_XCK_OUT_CTRL); ++ u1temp |= 0x18; ++ rtw_write8(Adapter, REG_XCK_OUT_CTRL, u1temp); ++ MSG_8192C("D cut version\n"); ++ } ++ ++ EnableGpio5ClockReq(Adapter, _FALSE, 1); ++ ++ //0x2c[3:0] = 5 will set clock to 26MHz ++ u1temp = rtw_read8(Adapter, REG_APE_PLL_CTRL_EXT); ++ u1temp = (u1temp & 0xF0) | 0x05; ++ rtw_write8(Adapter, REG_APE_PLL_CTRL_EXT, u1temp); ++} ++#endif ++ ++ ++static void rtl8188es_interface_configure(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; ++ ++ ++ pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID; ++ pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID; ++ pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID; ++ ++ if (bWiFiConfig) ++ pHalData->OutEpNumber = 2; ++ else ++ pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE; ++ ++ switch(pHalData->OutEpNumber){ ++ case 3: ++ pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ; ++ break; ++ case 2: ++ pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ; ++ break; ++ case 1: ++ pHalData->OutEpQueueSel=TX_SELE_HQ; ++ break; ++ default: ++ break; ++ } ++ ++ Hal_MappingOutPipe(padapter, pHalData->OutEpNumber); ++} ++ ++/* ++ * Description: ++ * Call power on sequence to enable card ++ * ++ * Return: ++ * _SUCCESS enable success ++ * _FAIL enable fail ++ */ ++static u8 _CardEnable(PADAPTER padapter) ++{ ++ u8 bMacPwrCtrlOn; ++ u8 ret; ++ ++ DBG_871X("=>%s\n", __FUNCTION__); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (bMacPwrCtrlOn == _FALSE) ++ { ++#ifdef CONFIG_PLATFORM_SPRD ++ u8 val8; ++#endif // CONFIG_PLATFORM_SPRD ++ ++ // RSV_CTRL 0x1C[7:0] = 0x00 ++ // unlock ISO/CLK/Power control register ++ rtw_write8(padapter, REG_RSV_CTRL, 0x0); ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifdef CONFIG_EXT_CLK ++ _InitClockTo26MHz(padapter); ++#endif //CONFIG_EXT_CLK ++ ++ val8 = rtw_read8(padapter, 0x4); ++ val8 = val8 & ~BIT(5); ++ rtw_write8(padapter, 0x4, val8); ++#endif // CONFIG_PLATFORM_SPRD ++ ++ ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_ENABLE_FLOW); ++ if (ret == _SUCCESS) { ++ u8 bMacPwrCtrlOn = _TRUE; ++ rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ } ++ else ++ { ++ DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__); ++ return _FAIL; ++ } ++ ++ } ++ else ++ { ++ ret = _SUCCESS; ++ } ++ ++ DBG_871X("<=%s\n", __FUNCTION__); ++ ++ return ret; ++ ++} ++ ++static u32 InitPowerOn_rtl8188es(PADAPTER padapter) ++{ ++ u8 value8; ++ u16 value16; ++ u32 value32; ++ u8 ret; ++ ++ DBG_871X("=>%s\n", __FUNCTION__); ++ ++ ret = _CardEnable(padapter); ++ if (ret == _FAIL) { ++ return ret; ++ } ++ ++/* ++ // Radio-Off Pin Trigger ++ value8 = rtw_read8(padapter, REG_GPIO_INTM+1); ++ value8 |= BIT(1); // Enable falling edge triggering interrupt ++ rtw_write8(padapter, REG_GPIO_INTM+1, value8); ++ value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1); ++ value8 |= BIT(1); ++ rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8); ++*/ ++ ++ // Enable power down and GPIO interrupt ++ value16 = rtw_read16(padapter, REG_APS_FSMCO); ++ value16 |= EnPDN; // Enable HW power down and RF on ++ rtw_write16(padapter, REG_APS_FSMCO, value16); ++ ++ ++ // Enable MAC DMA/WMAC/SCHEDULE/SEC block ++ value16 = rtw_read16(padapter, REG_CR); ++ value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN ++ | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN); ++ // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. ++ ++ rtw_write16(padapter, REG_CR, value16); ++ ++ ++ ++ // Enable CMD53 R/W Operation ++// bMacPwrCtrlOn = TRUE; ++// rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, (pu8)(&bMacPwrCtrlOn)); ++ ++ DBG_871X("<=%s\n", __FUNCTION__); ++ ++ return _SUCCESS; ++ ++} ++ ++static void _InitQueueReservedPage(PADAPTER padapter) ++{ ++#ifdef RTL8188ES_MAC_LOOPBACK ++ ++//#define MAC_LOOPBACK_PAGE_NUM_PUBQ 0x26 ++//#define MAC_LOOPBACK_PAGE_NUM_HPQ 0x0b ++//#define MAC_LOOPBACK_PAGE_NUM_LPQ 0x0b ++//#define MAC_LOOPBACK_PAGE_NUM_NPQ 0x0b // 71 pages=>9088 bytes, 8.875k ++ ++ rtw_write16(padapter, REG_RQPN_NPQ, 0x0b0b); ++ rtw_write32(padapter, REG_RQPN, 0x80260b0b); ++ ++#else //TX_PAGE_BOUNDARY_LOOPBACK_MODE ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ u32 outEPNum = (u32)pHalData->OutEpNumber; ++ u32 numHQ = 0; ++ u32 numLQ = 0; ++ u32 numNQ = 0; ++ u32 numPubQ; ++ u32 value32; ++ u8 value8; ++ BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; ++ ++ if(bWiFiConfig) ++ { ++ if (pHalData->OutEpQueueSel & TX_SELE_HQ) ++ { ++ numHQ = 0x29; ++ } ++ ++ if (pHalData->OutEpQueueSel & TX_SELE_LQ) ++ { ++ numLQ = 0x1C; ++ } ++ ++ // NOTE: This step shall be proceed before writting REG_RQPN. ++ if (pHalData->OutEpQueueSel & TX_SELE_NQ) { ++ numNQ = 0x1C; ++ } ++ value8 = (u8)_NPQ(numNQ); ++ rtw_write8(padapter, REG_RQPN_NPQ, value8); ++ ++ numPubQ = 0xA9 - numHQ - numLQ - numNQ; ++ ++ // TX DMA ++ value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; ++ rtw_write32(padapter, REG_RQPN, value32); ++ } ++ else ++ { ++ rtw_write16(padapter, REG_RQPN_NPQ, 0x0000); ++ rtw_write32(padapter,REG_RQPN, 0x80a00900); ++ } ++#endif ++ return; ++} ++ ++static void _InitTxBufferBoundary(PADAPTER padapter, u8 txpktbuf_bndy) ++{ ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ //u16 txdmactrl; ++ ++ rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); ++ rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); ++ rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); ++ rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy); ++ rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); ++ ++} ++ ++static VOID ++_InitNormalChipRegPriority( ++ IN PADAPTER Adapter, ++ IN u16 beQ, ++ IN u16 bkQ, ++ IN u16 viQ, ++ IN u16 voQ, ++ IN u16 mgtQ, ++ IN u16 hiQ ++ ) ++{ ++ u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7); ++ ++ value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | ++ _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | ++ _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ); ++ ++ rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); ++} ++ ++static VOID ++_InitNormalChipOneOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ u16 value = 0; ++ switch(pHalData->OutEpQueueSel) ++ { ++ case TX_SELE_HQ: ++ value = QUEUE_HIGH; ++ break; ++ case TX_SELE_LQ: ++ value = QUEUE_LOW; ++ break; ++ case TX_SELE_NQ: ++ value = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ _InitNormalChipRegPriority(Adapter, ++ value, ++ value, ++ value, ++ value, ++ value, ++ value ++ ); ++ ++} ++ ++static VOID ++_InitNormalChipTwoOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; ++ ++ ++ u16 valueHi = 0; ++ u16 valueLow = 0; ++ ++ switch(pHalData->OutEpQueueSel) ++ { ++ case (TX_SELE_HQ | TX_SELE_LQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_NQ | TX_SELE_LQ): ++ valueHi = QUEUE_NORMAL; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_HQ | TX_SELE_NQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ if(!pregistrypriv->wifi_spec ){ ++ beQ = valueLow; ++ bkQ = valueLow; ++ viQ = valueHi; ++ voQ = valueHi; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE ++ beQ = valueLow; ++ bkQ = valueHi; ++ viQ = valueHi; ++ voQ = valueLow; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ ++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++ ++} ++ ++static VOID ++_InitNormalChipThreeOutEpPriority( ++ IN PADAPTER padapter ++ ) ++{ ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; ++ ++ if (!pregistrypriv->wifi_spec){// typical setting ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_LOW; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ else {// for WMM ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_NORMAL; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ _InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++} ++ ++static VOID ++_InitNormalChipQueuePriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ switch(pHalData->OutEpNumber) ++ { ++ case 1: ++ _InitNormalChipOneOutEpPriority(Adapter); ++ break; ++ case 2: ++ _InitNormalChipTwoOutEpPriority(Adapter); ++ break; ++ case 3: ++ _InitNormalChipThreeOutEpPriority(Adapter); ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ ++} ++ ++ ++static void _InitQueuePriority(PADAPTER padapter) ++{ ++ _InitNormalChipQueuePriority(padapter); ++} ++ ++static void _InitPageBoundary(PADAPTER padapter) ++{ ++ // RX Page Boundary ++ u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1; ++ ++ rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy); ++ ++} ++ ++static void _InitTransferPageSize(PADAPTER padapter) ++{ ++ // Tx page size is always 128. ++ ++ u8 value8; ++ value8 = _PSRX(PBP_128) | _PSTX(PBP_128); ++ rtw_write8(padapter, REG_PBP, value8); ++} ++ ++void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize) ++{ ++ rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize); ++} ++ ++void _InitNetworkType(PADAPTER padapter) ++{ ++ u32 value32; ++ ++ value32 = rtw_read32(padapter, REG_CR); ++ ++ // TODO: use the other function to set network type ++// value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); ++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); ++ ++ rtw_write32(padapter, REG_CR, value32); ++} ++ ++void _InitWMACSetting(PADAPTER padapter) ++{ ++ u16 value16; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ ++ //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYSTS | RCR_APP_ICV | RCR_APP_MIC; ++ // don't turn on AAP, it will allow all packets to driver ++ pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; ++ ++ rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig); ++ ++ // Accept all data frames ++ value16 = 0xFFFF; ++ rtw_write16(padapter, REG_RXFLTMAP2, value16); ++ ++ // 2010.09.08 hpfan ++ // Since ADF is removed from RCR, ps-poll will not be indicate to driver, ++ // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. ++ value16 = 0x400; ++ rtw_write16(padapter, REG_RXFLTMAP1, value16); ++ ++ // Accept all management frames ++ value16 = 0xFFFF; ++ rtw_write16(padapter, REG_RXFLTMAP0, value16); ++ ++} ++ ++void _InitAdaptiveCtrl(PADAPTER padapter) ++{ ++ u16 value16; ++ u32 value32; ++ ++ // Response Rate Set ++ value32 = rtw_read32(padapter, REG_RRSR); ++ value32 &= ~RATE_BITMAP_ALL; ++ value32 |= RATE_RRSR_CCK_ONLY_1M; ++ rtw_write32(padapter, REG_RRSR, value32); ++ ++ // CF-END Threshold ++ //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); ++ ++ // SIFS (used in NAV) ++ value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); ++ rtw_write16(padapter, REG_SPEC_SIFS, value16); ++ ++ // Retry Limit ++ value16 = _LRL(0x30) | _SRL(0x30); ++ rtw_write16(padapter, REG_RL, value16); ++} ++ ++void _InitEDCA(PADAPTER padapter) ++{ ++ // Set Spec SIFS (used in NAV) ++ rtw_write16(padapter, REG_SPEC_SIFS, 0x100a); ++ rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a); ++ ++ // Set SIFS for CCK ++ rtw_write16(padapter, REG_SIFS_CTX, 0x100a); ++ ++ // Set SIFS for OFDM ++ rtw_write16(padapter, REG_SIFS_TRX, 0x100a); ++ ++ // TXOP ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B); ++ rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F); ++ rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324); ++ rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226); ++} ++ ++void _InitRateFallback(PADAPTER padapter) ++{ ++ // Set Data Auto Rate Fallback Retry Count register. ++ rtw_write32(padapter, REG_DARFRC, 0x00000000); ++ rtw_write32(padapter, REG_DARFRC+4, 0x10080404); ++ rtw_write32(padapter, REG_RARFRC, 0x04030201); ++ rtw_write32(padapter, REG_RARFRC+4, 0x08070605); ++ ++} ++ ++void _InitRetryFunction(PADAPTER padapter) ++{ ++ u8 value8; ++ ++ value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL); ++ value8 |= EN_AMPDU_RTY_NEW; ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8); ++ ++ // Set ACK timeout ++ rtw_write8(padapter, REG_ACKTO, 0x40); ++} ++ ++static void HalRxAggr8188ESdio(PADAPTER padapter) ++{ ++#if 1 ++ struct registry_priv *pregistrypriv; ++ u8 valueDMATimeout; ++ u8 valueDMAPageCount; ++ ++ ++ pregistrypriv = &padapter->registrypriv; ++ ++ if (pregistrypriv->wifi_spec) ++ { ++ // 2010.04.27 hpfan ++ // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer ++ // Timeout value is calculated by 34 / (2^n) ++ valueDMATimeout = 0x0f; ++ valueDMAPageCount = 0x01; ++ } ++ else ++ { ++ valueDMATimeout = 0x06; ++ //valueDMAPageCount = 0x0F; ++ //valueDMATimeout = 0x0a; ++ valueDMAPageCount = 0x24; ++ } ++ ++ rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout); ++ rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount); ++#endif ++} ++ ++void sdio_AggSettingRxUpdate(PADAPTER padapter) ++{ ++#if 1 ++ //HAL_DATA_TYPE *pHalData; ++ u8 valueDMA; ++ ++ ++ //pHalData = GET_HAL_DATA(padapter); ++ ++ valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL); ++ valueDMA |= RXDMA_AGG_EN; ++ rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA); ++ ++#if 0 ++ switch (RX_PAGE_SIZE_REG_VALUE) ++ { ++ case PBP_64: ++ pHalData->HwRxPageSize = 64; ++ break; ++ case PBP_128: ++ pHalData->HwRxPageSize = 128; ++ break; ++ case PBP_256: ++ pHalData->HwRxPageSize = 256; ++ break; ++ case PBP_512: ++ pHalData->HwRxPageSize = 512; ++ break; ++ case PBP_1024: ++ pHalData->HwRxPageSize = 1024; ++ break; ++ default: ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ++ ("%s: RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n", __FUNCTION__)); ++ break; ++ } ++#endif ++#endif ++} ++ ++void _initSdioAggregationSetting(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ // Tx aggregation setting ++ //sdio_AggSettingTxUpdate(padapter); ++ ++ // Rx aggregation setting ++ HalRxAggr8188ESdio(padapter); ++ sdio_AggSettingRxUpdate(padapter); ++ ++ // 201/12/10 MH Add for USB agg mode dynamic switch. ++ pHalData->UsbRxHighSpeedMode = _FALSE; ++} ++ ++ ++void _InitOperationMode(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData; ++ struct mlme_ext_priv *pmlmeext; ++ u8 regBwOpMode = 0; ++ u32 regRATR = 0, regRRSR = 0; ++ u8 MinSpaceCfg; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ pmlmeext = &padapter->mlmeextpriv; ++ ++ //1 This part need to modified according to the rate set we filtered!! ++ // ++ // Set RRSR, RATR, and REG_BWOPMODE registers ++ // ++ switch(pmlmeext->cur_wireless_mode) ++ { ++ case WIRELESS_MODE_B: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK; ++ regRRSR = RATE_ALL_CCK; ++ break; ++ case WIRELESS_MODE_A: ++// RT_ASSERT(FALSE,("Error wireless a mode\n")); ++#if 0 ++ regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_OFDM_AG; ++#endif ++ break; ++ case WIRELESS_MODE_G: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_AUTO: ++#if 0 ++ if (padapter->bInHctTest) ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ else ++#endif ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ break; ++ case WIRELESS_MODE_N_24G: ++ // It support CCK rate by default. ++ // CCK rate will be filtered out only when associated AP does not support it. ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_N_5G: ++// RT_ASSERT(FALSE,("Error wireless mode")); ++#if 0 ++ regBwOpMode = BW_OPMODE_5G; ++ regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_OFDM_AG; ++#endif ++ break; ++ ++ default: //for MacOSX compiler warning. ++ break; ++ } ++ ++ rtw_write8(padapter, REG_BWOPMODE, regBwOpMode); ++ ++ // For Min Spacing configuration. ++ switch(pHalData->rf_type) ++ { ++ case RF_1T2R: ++ case RF_1T1R: ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter: RF_Type%s\n", (pHalData->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"))); ++// padapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3); ++ MinSpaceCfg = (MAX_MSS_DENSITY_1T << 3); ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter:RF_Type(2T2R)\n")); ++// padapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3); ++ MinSpaceCfg = (MAX_MSS_DENSITY_2T << 3); ++ break; ++ } ++ ++// rtw_write8(padapter, REG_AMPDU_MIN_SPACE, padapter->MgntInfo.MinSpaceCfg); ++ rtw_write8(padapter, REG_AMPDU_MIN_SPACE, MinSpaceCfg); ++} ++ ++ ++void _InitBeaconParameters(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ ++ rtw_write16(padapter, REG_BCN_CTRL, 0x1010); ++ ++ // TODO: Remove these magic number ++ rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);// ms ++ rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);//ms ++ rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); ++ ++ // Suggested by designer timchen. Change beacon AIFS to the largest number ++ // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 ++ rtw_write16(padapter, REG_BCNTCFG, 0x660F); ++ ++ ++ pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL); ++ pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); ++ pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); ++ pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2); ++ pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1); ++ ++} ++ ++void _InitBeaconMaxError(PADAPTER padapter, BOOLEAN InfraMode) ++{ ++#ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING ++ rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); ++#endif ++} ++ ++void _InitInterrupt(PADAPTER padapter) ++{ ++ ++ //HISR write one to clear ++ rtw_write32(padapter, REG_HISR_88E, 0xFFFFFFFF); ++ ++ // HIMR - turn all off ++ rtw_write32(padapter, REG_HIMR_88E, 0); ++ ++ // ++ // Initialize and enable SDIO Host Interrupt. ++ // ++ InitInterrupt8188ESdio(padapter); ++ ++ ++ // ++ // Initialize and enable system Host Interrupt. ++ // ++ //InitSysInterrupt8188ESdio(Adapter);//TODO: ++ ++ // ++ // Enable SDIO Host Interrupt. ++ // ++ //EnableInterrupt8188ESdio(padapter);//Move to sd_intf_start()/stop ++ ++} ++ ++void _InitRDGSetting(PADAPTER padapter) ++{ ++ rtw_write8(padapter, REG_RD_CTRL, 0xFF); ++ rtw_write16(padapter, REG_RD_NAV_NXT, 0x200); ++ rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05); ++} ++ ++ ++static void _InitRxSetting(PADAPTER padapter) ++{ ++ rtw_write32(padapter, REG_MACID, 0x87654321); ++ rtw_write32(padapter, 0x0700, 0x87654321); ++} ++ ++ ++static void _InitRFType(PADAPTER padapter) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ //BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID); ++ BOOLEAN is2T2R = IS_2T2R(pHalData->VersionID); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++ return; ++#endif ++ ++ pHalData->rf_chip = RF_6052; ++ ++ //if (_FALSE == is92CU) { ++ if(_FALSE == is2T2R){ ++ pHalData->rf_type = RF_1T1R; ++ DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); ++ return; ++ } ++ ++ // TODO: Consider that EEPROM set 92CU to 1T1R later. ++ // Force to overwrite setting according to chip version. Ignore EEPROM setting. ++ //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; ++ MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type); ++} ++ ++// Set CCK and OFDM Block "ON" ++static void _BBTurnOnBlock(PADAPTER padapter) ++{ ++#if (DISABLE_BB_RF) ++ return; ++#endif ++ ++ PHY_SetBBReg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1); ++ PHY_SetBBReg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1); ++} ++ ++#if 0 ++static void _InitAntenna_Selection(PADAPTER padapter) ++{ ++ rtw_write8(padapter, REG_LEDCFG2, 0x82); ++} ++#endif ++ ++static void _InitPABias(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 pa_setting; ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ //FIXED PA current issue ++ //efuse_one_byte_read(padapter, 0x1FA, &pa_setting); ++ pa_setting = EFUSE_Read1Byte(padapter, 0x1FA); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting)); ++ ++ if(!(pa_setting & BIT0)) ++ { ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); ++ } ++ ++ if(!(pa_setting & BIT1) && is92C) ++ { ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); ++ } ++ ++ if(!(pa_setting & BIT4)) ++ { ++ pa_setting = rtw_read8(padapter, 0x16); ++ pa_setting &= 0x0F; ++ rtw_write8(padapter, 0x16, pa_setting | 0x80); ++ rtw_write8(padapter, 0x16, pa_setting | 0x90); ++ } ++} ++ ++#if 0 ++VOID ++_InitRDGSetting_8188E( ++ IN PADAPTER Adapter ++ ) ++{ ++ PlatformEFIOWrite1Byte(Adapter,REG_RD_CTRL,0xFF); ++ PlatformEFIOWrite2Byte(Adapter, REG_RD_NAV_NXT, 0x200); ++ PlatformEFIOWrite1Byte(Adapter,REG_RD_RESP_PKT_TH,0x05); ++} ++#endif ++ ++static u32 rtl8188es_hal_init(PADAPTER padapter) ++{ ++ s32 ret; ++ u8 txpktbuf_bndy; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ u8 is92C = IS_92C_SERIAL(pHalData->VersionID); ++ rt_rf_power_state eRfPowerStateToSet; ++ u8 value8; ++ u16 value16; ++ ++ u32 init_start_time = rtw_get_current_time(); ++ ++#ifdef DBG_HAL_INIT_PROFILING ++ enum HAL_INIT_STAGES { ++ HAL_INIT_STAGES_BEGIN = 0, ++ HAL_INIT_STAGES_INIT_PW_ON, ++ HAL_INIT_STAGES_MISC01, ++ HAL_INIT_STAGES_DOWNLOAD_FW, ++ HAL_INIT_STAGES_MAC, ++ HAL_INIT_STAGES_BB, ++ HAL_INIT_STAGES_RF, ++ HAL_INIT_STAGES_EFUSE_PATCH, ++ HAL_INIT_STAGES_INIT_LLTT, ++ ++ HAL_INIT_STAGES_MISC02, ++ HAL_INIT_STAGES_TURN_ON_BLOCK, ++ HAL_INIT_STAGES_INIT_SECURITY, ++ HAL_INIT_STAGES_MISC11, ++ HAL_INIT_STAGES_INIT_HAL_DM, ++ //HAL_INIT_STAGES_RF_PS, ++ HAL_INIT_STAGES_IQK, ++ HAL_INIT_STAGES_PW_TRACK, ++ HAL_INIT_STAGES_LCK, ++ //HAL_INIT_STAGES_MISC21, ++ HAL_INIT_STAGES_INIT_PABIAS, ++ //HAL_INIT_STAGES_ANTENNA_SEL, ++ HAL_INIT_STAGES_MISC31, ++ HAL_INIT_STAGES_END, ++ HAL_INIT_STAGES_NUM ++ }; ++ ++ char * hal_init_stages_str[] = { ++ "HAL_INIT_STAGES_BEGIN", ++ "HAL_INIT_STAGES_INIT_PW_ON", ++ "HAL_INIT_STAGES_MISC01", ++ "HAL_INIT_STAGES_DOWNLOAD_FW", ++ "HAL_INIT_STAGES_MAC", ++ "HAL_INIT_STAGES_BB", ++ "HAL_INIT_STAGES_RF", ++ "HAL_INIT_STAGES_EFUSE_PATCH", ++ "HAL_INIT_STAGES_INIT_LLTT", ++ "HAL_INIT_STAGES_MISC02", ++ "HAL_INIT_STAGES_TURN_ON_BLOCK", ++ "HAL_INIT_STAGES_INIT_SECURITY", ++ "HAL_INIT_STAGES_MISC11", ++ "HAL_INIT_STAGES_INIT_HAL_DM", ++ //"HAL_INIT_STAGES_RF_PS", ++ "HAL_INIT_STAGES_IQK", ++ "HAL_INIT_STAGES_PW_TRACK", ++ "HAL_INIT_STAGES_LCK", ++ //"HAL_INIT_STAGES_MISC21", ++ "HAL_INIT_STAGES_INIT_PABIAS" ++ //"HAL_INIT_STAGES_ANTENNA_SEL", ++ "HAL_INIT_STAGES_MISC31", ++ "HAL_INIT_STAGES_END", ++ }; ++ ++ ++ int hal_init_profiling_i; ++ u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_iwowlan_wake_reason & FWDecisionDisconnect)) { ++ u8 reg_val=0; ++ DBG_8192C("+Reset Entry+\n"); ++ rtw_write8(padapter, REG_MCUFWDL, 0x00); ++ _8051Reset88E(padapter); ++ //reset BB ++ reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN); ++ reg_val &= ~(BIT(0) | BIT(1)); ++ rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val); ++ //reset RF ++ rtw_write8(padapter, REG_RF_CTRL, 0); ++ //reset TRX path ++ rtw_write16(padapter, REG_CR, 0); ++ //reset MAC, Digital Core ++ reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1); ++ reg_val &= ~(BIT(4) | BIT(7)); ++ rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val); ++ reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1); ++ reg_val |= BIT(4) | BIT(7); ++ rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val); ++ DBG_8192C("-Reset Entry-\n"); ++ } ++#endif //CONFIG_WOWLAN ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); ++ ret = InitPowerOn_rtl8188es(padapter); ++ if (_FAIL == ret) { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n")); ++ goto exit; ++ } ++ ++ ret = PowerOnCheck(padapter); ++ if (_FAIL == ret ) { ++ DBG_871X("Power on Fail! do it again\n"); ++ ret = InitPowerOn_rtl8188es(padapter); ++ if (_FAIL == ret) { ++ DBG_871X("Failed to init Power On!\n"); ++ goto exit; ++ } ++ } ++ DBG_871X("Power on ok!\n"); ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); ++ if (!pregistrypriv->wifi_spec) { ++ txpktbuf_bndy = TX_PAGE_BOUNDARY_88E; ++ } else { ++ // for WMM ++ txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E; ++ } ++ _InitQueueReservedPage(padapter); ++ _InitQueuePriority(padapter); ++ _InitPageBoundary(padapter); ++ _InitTransferPageSize(padapter); ++#ifdef CONFIG_IOL_IOREG_CFG ++ _InitTxBufferBoundary(padapter, 0); ++#endif ++ // ++ // Configure SDIO TxRx Control to enable Rx DMA timer masking. ++ // 2010.02.24. ++ // ++ value8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_TX_CTRL); ++ SdioLocalCmd52Write1Byte(padapter, SDIO_REG_TX_CTRL, 0x02); ++ ++ rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, 0); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); ++#if (MP_DRIVER == 1) ++ if (padapter->registrypriv.mp_mode == 1) ++ { ++ _InitRxSetting(padapter); ++ } ++#endif //MP_DRIVER == 1 ++ { ++#if 0 ++ padapter->bFWReady = _FALSE; //because no fw for test chip ++ pHalData->fw_ractrl = _FALSE; ++#else ++#ifdef CONFIG_WOWLAN ++ ret = rtl8188e_FirmwareDownload(padapter, _FALSE); ++#else ++ ret = rtl8188e_FirmwareDownload(padapter); ++#endif //CONFIG_WOWLAN ++ ++ if (ret != _SUCCESS) { ++ DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__); ++ padapter->bFWReady = _FALSE; ++ pHalData->fw_ractrl = _FALSE; ++ goto exit; ++ } else { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n")); ++ padapter->bFWReady = _TRUE; ++ pHalData->fw_ractrl = _FALSE; ++ } ++#endif ++ } ++ ++ rtl8188e_InitializeFirmwareVars(padapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); ++#if (HAL_MAC_ENABLE == 1) ++ ret = PHY_MACConfig8188E(padapter); ++ if(ret != _SUCCESS){ ++// RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n")); ++ goto exit; ++ } ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); ++ // ++ //d. Initialize BB related configurations. ++ // ++#if (HAL_BB_ENABLE == 1) ++ ret = PHY_BBConfig8188E(padapter); ++ if(ret != _SUCCESS){ ++// RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n")); ++ goto exit; ++ } ++#endif ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); ++ ++#if (HAL_RF_ENABLE == 1) ++ ret = PHY_RFConfig8188E(padapter); ++ ++ if(ret != _SUCCESS){ ++// RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n")); ++ goto exit; ++ } ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH); ++#if defined(CONFIG_IOL_EFUSE_PATCH) ++ ret = rtl8188e_iol_efuse_patch(padapter); ++ if(ret != _SUCCESS){ ++ DBG_871X("%s rtl8188e_iol_efuse_patch failed \n",__FUNCTION__); ++ goto exit; ++ } ++#endif ++ _InitTxBufferBoundary(padapter, txpktbuf_bndy); ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); ++ ret = InitLLTTable(padapter, txpktbuf_bndy); ++ if (_SUCCESS != ret) { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT Table!\n")); ++ goto exit; ++ } ++ ++#if (RATE_ADAPTIVE_SUPPORT==1) ++ {//Enable TX Report ++ //Enable Tx Report Timer ++ value8 = rtw_read8(padapter, REG_TX_RPT_CTRL); ++ rtw_write8(padapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); ++ //Set MAX RPT MACID ++ rtw_write8(padapter, REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP ++ //Tx RPT Timer. Unit: 32us ++ rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0); ++ } ++#endif ++ ++#if 0 ++ if(pHTInfo->bRDGEnable){ ++ _InitRDGSetting_8188E(Adapter); ++ } ++#endif ++ ++#ifdef CONFIG_TX_EARLY_MODE ++ if( pHalData->bEarlyModeEnable) ++ { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n")); ++ ++ value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL); ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ value8 = value8|0x1f; ++#else ++ value8 = value8|0xf; ++#endif ++ rtw_write8(padapter, REG_EARLY_MODE_CONTROL, value8); ++ ++ rtw_write8(padapter, REG_EARLY_MODE_CONTROL+3, 0x80); ++ ++ value8 = rtw_read8(padapter, REG_TCR+1); ++ value8 = value8|0x40; ++ rtw_write8(padapter,REG_TCR+1, value8); ++ } ++ else ++#endif ++ { ++ rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0); ++ } ++ ++ ++#if(SIC_ENABLE == 1) ++ SIC_Init(padapter); ++#endif ++ ++ ++ if (pwrctrlpriv->reg_rfoff == _TRUE) { ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ } ++ ++ // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting ++ // HW GPIO pin. Before PHY_RFConfig8192C. ++ HalDetectPwrDownMode88E(padapter); ++ ++ ++ // Set RF type for BB/RF configuration ++ _InitRFType(padapter); ++ ++ // Save target channel ++ // Current Channel will be updated again later. ++ pHalData->CurrentChannel = 1; ++ ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); ++ // Get Rx PHY status in order to report RSSI and others. ++ _InitDriverInfoSize(padapter, 4); ++ hal_init_macaddr(padapter); ++ _InitNetworkType(padapter); ++ _InitWMACSetting(padapter); ++ _InitAdaptiveCtrl(padapter); ++ _InitEDCA(padapter); ++ _InitRateFallback(padapter); ++ _InitRetryFunction(padapter); ++ _initSdioAggregationSetting(padapter); ++ _InitOperationMode(padapter); ++ _InitBeaconParameters(padapter); ++ _InitBeaconMaxError(padapter, _TRUE); ++ _InitInterrupt(padapter); ++ ++ // Enable MACTXEN/MACRXEN block ++ value16 = rtw_read16(padapter, REG_CR); ++ value16 |= (MACTXEN | MACRXEN); ++ rtw_write8(padapter, REG_CR, value16); ++ ++ rtw_write32(padapter,REG_MACID_NO_LINK_0,0xFFFFFFFF); ++ rtw_write32(padapter,REG_MACID_NO_LINK_1,0xFFFFFFFF); ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) ++ ++#ifdef CONFIG_CHECK_AC_LIFETIME ++ // Enable lifetime check for the four ACs ++ rtw_write8(padapter, REG_LIFETIME_EN, 0x0F); ++#endif // CONFIG_CHECK_AC_LIFETIME ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++ rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++#else // CONFIG_TX_MCAST2UNI ++ rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s ++ rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s ++#endif // CONFIG_TX_MCAST2UNI ++#endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI ++ ++ ++ ++ ++#endif //HAL_RF_ENABLE == 1 ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); ++ _BBTurnOnBlock(padapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); ++#if 1 ++ invalidate_cam_all(padapter); ++#else ++ CamResetAllEntry(padapter); ++ padapter->HalFunc.EnableHWSecCfgHandler(padapter); ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); ++ // 2010/12/17 MH We need to set TX power according to EFUSE content at first. ++ PHY_SetTxPowerLevel8188E(padapter, pHalData->CurrentChannel); ++ // Record original value for template. This is arough data, we can only use the data ++ // for power adjust. The value can not be adjustde according to different power!!! ++// pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; ++// pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; ++ ++// Move by Neo for USB SS to below setp ++//_RfPowerSave(padapter); ++#if 0 //ANTENNA_SELECTION_STATIC_SETTING ++#if 0 ++ if (!IS_92C_SERIAL( pHalData->VersionID) && (pHalData->AntDivCfg!=0)) ++#else ++ if (IS_1T1R( pHalData->VersionID) && (pHalData->AntDivCfg!=0)) ++#endif ++ { //for 88CU ,1T1R ++ _InitAntenna_Selection(padapter); ++ } ++#endif ++ ++ // ++ // Disable BAR, suggested by Scott ++ // 2010.04.09 add by hpfan ++ // ++ rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff); ++ ++ // HW SEQ CTRL ++ // set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. ++ rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); ++ ++ ++#ifdef RTL8188ES_MAC_LOOPBACK ++ value8 = rtw_read8(padapter, REG_SYS_FUNC_EN); ++ value8 &= ~(FEN_BBRSTB|FEN_BB_GLB_RSTn); ++ rtw_write8(padapter, REG_SYS_FUNC_EN, value8);//disable BB, CCK/OFDM ++ ++ rtw_write8(padapter, REG_RD_CTRL, 0x0F); ++ rtw_write8(padapter, REG_RD_CTRL+1, 0xCF); ++ //rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);//to check _InitPageBoundary() ++ rtw_write32(padapter, REG_CR, 0x0b0202ff);//0x100[28:24]=0x01011, enable mac loopback, no HW Security Eng. ++#endif ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); ++ // InitHalDm(padapter); ++ rtl8188e_InitHalDm(padapter); ++ ++ ++#if (MP_DRIVER == 1) ++ if (padapter->registrypriv.mp_mode == 1) ++ { ++ padapter->mppriv.channel = pHalData->CurrentChannel; ++ MPT_InitializeAdapter(padapter, padapter->mppriv.channel); ++ } ++ else ++#endif //(MP_DRIVER == 1) ++ { ++ // ++ // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status ++ // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not ++ // call init_adapter. May cause some problem?? ++ // ++ // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed ++ // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState ++ // is the same as eRfOff, we should change it to eRfOn after we config RF parameters. ++ // Added by tynli. 2010.03.30. ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC); ++ ++ // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off. ++ // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization. ++// pHalData->bHwRadioOff = _FALSE; ++ pwrctrlpriv->b_hw_radio_off = _FALSE; ++ eRfPowerStateToSet = rf_on; ++ ++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. ++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. ++ if(pHalData->pwrdown && eRfPowerStateToSet == rf_off) ++ { ++ // Enable register area 0x0-0xc. ++ rtw_write8(padapter, REG_RSV_CTRL, 0x0); ++ ++ // ++ // We should configure HW PDn source for WiFi ONLY, and then ++ // our HW will be set in power-down mode if PDn source from all functions are configured. ++ // 2010.10.06. ++ // ++ if(IS_HARDWARE_TYPE_8723AS(padapter)) ++ { ++ value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL); ++ rtw_write8(padapter, REG_MULTI_FUNC_CTRL, (value8|WL_HWPDN_EN)); ++ } ++ else ++ { ++ rtw_write16(padapter, REG_APS_FSMCO, 0x8812); ++ } ++ } ++ //DrvIFIndicateCurrentPhyStatus(padapter); // 2010/08/17 MH Disable to prevent BSOD. ++ ++ // 2010/08/26 MH Merge from 8192CE. ++ if(pwrctrlpriv->rf_pwrstate == rf_on) ++ { ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); ++ if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){ ++// PHY_IQCalibrate(padapter, _TRUE); ++ PHY_IQCalibrate_8188E(padapter,_TRUE); ++ } ++ else ++ { ++// PHY_IQCalibrate(padapter, _FALSE); ++ PHY_IQCalibrate_8188E(padapter,_FALSE); ++ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE; ++ } ++ ++// dm_CheckTXPowerTracking(padapter); ++// PHY_LCCalibrate(padapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); ++ ODM_TXPowerTrackingCheck(&pHalData->odmpriv ); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); ++ PHY_LCCalibrate_8188E(padapter); ++ ++ ++ } ++} ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); ++ //if(pHalData->eRFPowerState == eRfOn) ++ { ++ _InitPABias(padapter); ++ } ++ ++ // Init BT hw config. ++// HALBT_InitHwConfig(padapter); ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31); ++ // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting. ++ // 2010/05/18 MH For SE series only now. Init GPIO detect time ++#if 0 ++ if(pDevice->RegUsbSS) ++ { ++ RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart\n")); ++ GpioDetectTimerStart(padapter); // Disable temporarily ++ } ++#endif ++ ++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter ++ // suspend mode automatically. ++ //HwSuspendModeEnable92Cu(padapter, FALSE); ++ ++ // 2010/12/17 MH For TX power level OID modification from UI. ++// padapter->HalFunc.GetTxPowerLevelHandler( padapter, &pHalData->DefaultTxPwrDbm ); ++ //DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); ++ ++// if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) // The lowest Beacon Type that HW can support ++// pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; ++ ++ // ++ // Update current Tx FIFO page status. ++ // ++ HalQueryTxBufferStatus8189ESdio(padapter); ++ ++ ++ if(pregistrypriv->wifi_spec) ++ rtw_write16(padapter,REG_FAST_EDCA_CTRL ,0); ++ ++ ++ //TODO:Setting HW_VAR_NAV_UPPER !!!!!!!!!!!!!!!!!!!! ++ //rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, ((pu1Byte)&NavUpper)); ++ ++ if(IS_HARDWARE_TYPE_8188ES(padapter)) ++ { ++ value8= rtw_read8(padapter, 0x4d3); ++ rtw_write8(padapter, 0x4d3, (value8|0x1)); ++ } ++ ++ //pHalData->PreRpwmVal = PlatformEFSdioLocalCmd52Read1Byte(Adapter, SDIO_REG_HRPWM1)&0x80; ++ ++ ++ // enable Tx report. ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+1, 0x0F); ++/* ++ // Suggested by SD1 pisa. Added by tynli. 2011.10.21. ++ PlatformEFIOWrite1Byte(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01); ++ ++*/ //tynli_test_tx_report. ++ rtw_write16(padapter, REG_TX_RPT_TIME, 0x3DF0); ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n")); ++ ++ ++ //enable tx DMA to drop the redundate data of packet ++ rtw_write16(padapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(padapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN)); ++ ++//#debug print for checking compile flags ++ //DBG_8192C("RTL8188E_FPGA_TRUE_PHY_VERIFICATION=%d\n", RTL8188E_FPGA_TRUE_PHY_VERIFICATION); ++ DBG_8192C("DISABLE_BB_RF=%d\n", DISABLE_BB_RF); ++ DBG_8192C("IS_HARDWARE_TYPE_8188ES=%d\n", IS_HARDWARE_TYPE_8188ES(padapter)); ++//# ++ ++#ifdef CONFIG_PLATFORM_SPRD ++ // For Power Consumption, set all GPIO pin to ouput mode ++ //0x44~0x47 (GPIO 0~7), Note:GPIO5 is enabled for controlling external 26MHz request ++ rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46, set to o/p mode ++ ++ //0x42~0x43 (GPIO 8~11) ++ value8 = rtw_read8(padapter, REG_GPIO_IO_SEL); ++ rtw_write8(padapter, REG_GPIO_IO_SEL, (value8<<4)|value8); ++ value8 = rtw_read8(padapter, REG_GPIO_IO_SEL+1); ++ rtw_write8(padapter, REG_GPIO_IO_SEL+1, value8|0x0F);//Reg0x43 ++#endif //CONFIG_PLATFORM_SPRD ++ ++ ++#ifdef CONFIG_XMIT_ACK ++ //ack for xmit mgmt frames. ++ rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12)); ++#endif //CONFIG_XMIT_ACK ++ ++ ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---Initializepadapter8192CSdio()\n")); ++ DBG_8192C("-rtl8188es_hal_init\n"); ++ ++exit: ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); ++ ++ DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time)); ++ ++ #ifdef DBG_HAL_INIT_PROFILING ++ hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time(); ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_i%s\n", __FUNCTION__); ++ ++ ++ //Stop Tx Report Timer. 0x4EC[Bit1]=b'0 ++ u1bTmp = rtw_read8(padapter, REG_TX_RPT_CTRL); ++ rtw_write8(padapter, REG_TX_RPT_CTRL, u1bTmp&(~BIT1)); ++ ++ // stop rx ++ rtw_write8(padapter,REG_CR, 0x0); ++ ++ ++#ifdef CONFIG_EXT_CLK //for sprd For Power Consumption. ++ EnableGpio5ClockReq(padapter, _FALSE, 0); ++#endif //CONFIG_EXT_CLK ++ ++#if 1 ++ // For Power Consumption. ++ u1bTmp = rtw_read8(padapter, GPIO_IN); ++ rtw_write8(padapter, GPIO_OUT, u1bTmp); ++ rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46 ++ ++ u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL); ++ rtw_write8(padapter, REG_GPIO_IO_SEL, (u1bTmp<<4)|u1bTmp); ++ u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL+1); ++ rtw_write8(padapter, REG_GPIO_IO_SEL+1, u1bTmp|0x0F);//Reg0x43 ++#endif ++ ++ ++ // Run LPS WL RFOFF flow ++ ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW); ++ if (ret == _FALSE) { ++ DBG_871X("%s: run RF OFF flow fail!\n", __func__); ++ } ++ ++ // ==== Reset digital sequence ====== ++ ++ u1bTmp = rtw_read8(padapter, REG_MCUFWDL); ++ if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) //8051 RAM code ++ { ++ //rtl8723a_FirmwareSelfReset(padapter); ++ //_8051Reset88E(padapter); ++ ++ // Reset MCU 0x2[10]=0. ++ u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); ++ u1bTmp &= ~BIT(2); // 0x2[10], FEN_CPUEN ++ rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp); ++ } ++ ++ //u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); ++ //u1bTmp &= ~BIT(2); // 0x2[10], FEN_CPUEN ++ //rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp); ++ ++ // MCUFWDL 0x80[1:0]=0 ++ // reset MCU ready status ++ rtw_write8(padapter, REG_MCUFWDL, 0); ++ ++ //==== Reset digital sequence end ====== ++ ++ ++ bMacPwrCtrlOn = _FALSE; // Disable CMD53 R/W ++ rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ ++ ++/* ++ if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) && pHalData->pwrdown) ++ {// Power Down ++ ++ // Card disable power action flow ++ ret = HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_PDN_FLOW); ++ } ++ else ++*/ ++ { // Non-Power Down ++ ++ // Card disable power action flow ++ ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_DISABLE_FLOW); ++ ++ ++ if (ret == _FALSE) { ++ DBG_871X("%s: run CARD DISABLE flow fail!\n", __func__); ++ } ++ } ++ ++ ++/* ++ // Reset MCU IO Wrapper, added by Roger, 2011.08.30 ++ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); ++ u1bTmp &= ~BIT(0); ++ rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp); ++ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); ++ u1bTmp |= BIT(0); ++ rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp); ++*/ ++ ++ ++ // RSV_CTRL 0x1C[7:0]=0x0E ++ // lock ISO/CLK/Power control register ++ rtw_write8(padapter, REG_RSV_CTRL, 0x0E); ++ ++ padapter->bFWReady = _FALSE; ++ DBG_871X("<=%s\n", __FUNCTION__); ++ ++} ++ ++static u32 rtl8188es_hal_deinit(PADAPTER padapter) ++{ ++ DBG_871X("=>%s\n", __FUNCTION__); ++ ++ if (padapter->hw_init_completed == _TRUE) ++ hal_poweroff_rtl8188es(padapter); ++ ++ DBG_871X("<=%s\n", __FUNCTION__); ++ ++ return _SUCCESS; ++} ++ ++static u32 rtl8188es_inirp_init(PADAPTER padapter) ++{ ++ u32 status; ++ ++_func_enter_; ++ ++ status = _SUCCESS; ++ ++_func_exit_; ++ ++ return status; ++} ++ ++static u32 rtl8188es_inirp_deinit(PADAPTER padapter) ++{ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("+rtl8188es_inirp_deinit\n")); ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("-rtl8188es_inirp_deinit\n")); ++ ++ return _SUCCESS; ++} ++ ++static void rtl8188es_init_default_value(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData; ++ struct pwrctrl_priv *pwrctrlpriv; ++ struct dm_priv *pdmpriv; ++ u8 i; ++ ++ pHalData = GET_HAL_DATA(padapter); ++ pwrctrlpriv = adapter_to_pwrctl(padapter); ++ pdmpriv = &pHalData->dmpriv; ++ ++ ++ //init default value ++ pHalData->fw_ractrl = _FALSE; ++ if(!pwrctrlpriv->bkeepfwalive) ++ pHalData->LastHMEBoxNum = 0; ++ ++ //init dm default value ++ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE; ++ pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK ++ //pdmpriv->binitialized = _FALSE; ++// pdmpriv->prv_traffic_idx = 3; ++// pdmpriv->initialize = 0; ++ pHalData->pwrGroupCnt = 0; ++ pHalData->PGMaxGroup= 13; ++ pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; ++ for(i = 0; i < HP_THERMAL_NUM; i++) ++ pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0; ++ ++ // interface related variable ++ pHalData->SdioRxFIFOCnt = 0; ++} ++ ++// ++// Description: ++// We should set Efuse cell selection to WiFi cell in default. ++// ++// Assumption: ++// PASSIVE_LEVEL ++// ++// Added by Roger, 2010.11.23. ++// ++static void _EfuseCellSel( ++ IN PADAPTER padapter ++ ) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ u32 value32; ++ ++ //if(INCLUDE_MULTI_FUNC_BT(padapter)) ++ { ++ value32 = rtw_read32(padapter, EFUSE_TEST); ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); ++ rtw_write32(padapter, EFUSE_TEST, value32); ++ } ++} ++ ++static VOID ++_ReadRFType( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++#else ++ pHalData->rf_chip = RF_6052; ++#endif ++} ++ ++static void ++Hal_EfuseParsePIDVID_8188ES( ++ IN PADAPTER pAdapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ // ++ // The PID/VID info was parsed from CISTPL_MANFID Tuple in CIS area before. ++ // VID is parsed from Manufacture code field and PID is parsed from Manufacture information field. ++ // 2011.04.01. ++ // ++ ++// RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID)); ++// RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID)); ++} ++ ++static void ++Hal_EfuseParseMACAddr_8188ES( ++ IN PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u16 i, usValue; ++ u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x77}; ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ ++ if (AutoLoadFail) ++ { ++// sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254); ++ for (i=0; i<6; i++) ++ pEEPROM->mac_addr[i] = sMacAddr[i]; ++ } ++ else ++ { ++ //Read Permanent MAC address ++ _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88ES], ETH_ALEN); ++ ++ } ++// NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress); ++ ++ DBG_871X("Hal_EfuseParseMACAddr_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", ++ pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], ++ pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], ++ pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]); ++} ++ ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++static u32 Hal_readPGDataFromConfigFile( ++ PADAPTER padapter) ++{ ++ u32 i; ++ struct file *fp; ++ mm_segment_t fs; ++ u8 temp[3]; ++ loff_t pos = 0; ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ u8 *PROMContent = pEEPROM->efuse_eeprom_data; ++ ++ ++ temp[2] = 0; // add end of string '\0' ++ ++ fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDONLY, 0); ++ if (IS_ERR(fp)) { ++ pEEPROM->bloadfile_fail_flag = _TRUE; ++ DBG_871X("Error, Efuse configure file doesn't exist.\n"); ++ return _FAIL; ++ } ++ ++ fs = get_fs(); ++ set_fs(KERNEL_DS); ++ ++ DBG_871X("Efuse configure file:\n"); ++ for (i=0; ibloadfile_fail_flag = _FALSE; ++ return _SUCCESS; ++} ++ ++static void ++Hal_ReadMACAddrFromFile_8188ES( ++ PADAPTER padapter ++ ) ++{ ++ u32 i; ++ struct file *fp; ++ mm_segment_t fs; ++ u8 source_addr[18]; ++ loff_t pos = 0; ++ u32 curtime = rtw_get_current_time(); ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ u8 *head, *end; ++ ++ u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0}; ++ u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ _rtw_memset(source_addr, 0, 18); ++ _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN); ++ ++ fp = filp_open("/data/wifimac.txt", O_RDWR, 0644); ++ if (IS_ERR(fp)) { ++ pEEPROM->bloadmac_fail_flag = _TRUE; ++ DBG_871X("Error, wifi mac address file doesn't exist.\n"); ++ } else { ++ fs = get_fs(); ++ set_fs(KERNEL_DS); ++ ++ DBG_871X("wifi mac address:\n"); ++ vfs_read(fp, source_addr, 18, &pos); ++ source_addr[17] = ':'; ++ ++ head = end = source_addr; ++ for (i=0; imac_addr[i] = simple_strtoul(head, NULL, 16 ); ++ ++ if (end) { ++ end++; ++ head = end; ++ } ++ DBG_871X("%02x \n", pEEPROM->mac_addr[i]); ++ } ++ DBG_871X("\n"); ++ set_fs(fs); ++ pEEPROM->bloadmac_fail_flag = _FALSE; ++ filp_close(fp, NULL); ++ } ++ ++ if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) || ++ (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) { ++ pEEPROM->mac_addr[0] = 0x00; ++ pEEPROM->mac_addr[1] = 0xe0; ++ pEEPROM->mac_addr[2] = 0x4c; ++ pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ; ++ pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ; ++ pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ; ++ } ++ ++ DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", ++ pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], ++ pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], ++ pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]); ++} ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++static VOID ++readAdapterInfo_8188ES( ++ IN PADAPTER padapter ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ ++ /* parse the eeprom/efuse content */ ++ Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data); ++ Hal_EfuseParsePIDVID_8188ES(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++ Hal_ReadMACAddrFromFile_8188ES(padapter); ++#else //CONFIG_EFUSE_CONFIG_FILE ++ Hal_EfuseParseMACAddr_8188ES(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++ Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ //Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ // ++ // The following part initialize some vars by PG info. ++ // ++ Hal_InitChannelPlan(padapter); ++#ifdef CONFIG_WOWLAN ++ Hal_DetectWoWMode(padapter); ++#endif //CONFIG_WOWLAN ++#ifdef CONFIG_RF_GAIN_OFFSET ++ Hal_ReadRFGainOffset(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++#endif //CONFIG_RF_GAIN_OFFSET ++} ++ ++static void _ReadPROMContent( ++ IN PADAPTER padapter ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ u8 eeValue; ++ ++ /* check system boot selection */ ++ eeValue = rtw_read8(padapter, REG_9346CR); ++ pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE; ++ pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE; ++ ++ DBG_871X("%s: 9346CR=0x%02X, Boot from %s, Autoload %s\n", ++ __FUNCTION__, eeValue, ++ (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), ++ (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")); ++ ++// pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++ Hal_readPGDataFromConfigFile(padapter); ++#else //CONFIG_EFUSE_CONFIG_FILE ++ Hal_InitPGData88E(padapter); ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ readAdapterInfo_8188ES(padapter); ++} ++ ++static VOID ++_InitOtherVariable( ++ IN PADAPTER Adapter ++ ) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ ++ //if(Adapter->bInHctTest){ ++ // pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ // pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ // pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ // pMgntInfo->keepAliveLevel = 0; ++ //} ++ ++ ++} ++ ++// ++// Description: ++// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. ++// ++// Assumption: ++// PASSIVE_LEVEL (SDIO interface) ++// ++// ++static s32 _ReadAdapterInfo8188ES(PADAPTER padapter) ++{ ++ u32 start; ++ ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8188ES\n")); ++ ++ // before access eFuse, make sure card enable has been called ++ if(_CardEnable(padapter) == _FAIL) ++ { ++ DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__); ++ return _FAIL; ++ } ++ ++ start = rtw_get_current_time(); ++ ++// Efuse_InitSomeVar(Adapter); ++// pHalData->VersionID = ReadChipVersion(Adapter); ++// _EfuseCellSel(padapter); ++ ++ _ReadRFType(padapter);//rf_chip -> _InitRFType() ++ _ReadPROMContent(padapter); ++ ++ // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize. ++ //ReadSilmComboMode(Adapter); ++ _InitOtherVariable(padapter); ++ ++ ++ //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type); ++ MSG_8192C("<==== ReadAdapterInfo8188ES in %d ms\n", rtw_get_passing_time_ms(start)); ++ ++ return _SUCCESS; ++} ++ ++static void ReadAdapterInfo8188ES(PADAPTER padapter) ++{ ++ // Read EEPROM size before call any EEPROM function ++ padapter->EepromAddressSize = GetEEPROMSize8188E(padapter); ++ ++ _ReadAdapterInfo8188ES(padapter); ++} ++ ++static void ResumeTxBeacon(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n")); ++ ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6); ++ pHalData->RegFwHwTxQCtrl |= BIT6; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff); ++ pHalData->RegReg542 |= BIT0; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++} ++ ++static void StopTxBeacon(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n")); ++ ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6)); ++ pHalData->RegFwHwTxQCtrl &= (~BIT6); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); ++ pHalData->RegReg542 &= ~(BIT0); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++ ++ CheckFwRsvdPageContent(padapter); // 2010.06.23. Added by tynli. ++} ++ ++// todo static ++void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 val8; ++ u8 mode = *((u8 *)val); ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ // disable Port1 TSF update ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ ++ // set net_type ++ val8 = rtw_read8(Adapter, MSR)&0x03; ++ val8 |= (mode<<2); ++ rtw_write8(Adapter, MSR, val8); ++ ++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode); ++ ++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) ++ { ++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++ { ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms ++ UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK); ++ #endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK)); ++ #endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++ StopTxBeacon(Adapter); ++ } ++ ++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x11);//disable atim wnd and disable beacon function ++ //rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18); ++ } ++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) ++ { ++ ResumeTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a); ++ //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ } ++ else if(mode == _HW_STATE_AP_) ++ { ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ResumeTxBeacon(Adapter); ++ ++ rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12); ++ ++ //enable SW Beacon ++ rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8)); ++ ++ //Set RCR ++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 ++ rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,Reject ICV_ERROR packets ++ ++ //enable to rx data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); ++ //enable to rx ps-poll ++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); ++ ++ //Beacon Control related register for first time ++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms ++ ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++ rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1 ++ rtw_write16(Adapter, REG_BCNTCFG, 0x00); ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); ++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms) ++ ++ //reset TSF2 ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)); ++ ++ ++ //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ //enable BCN1 Function for if2 ++ //don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1))); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE)) ++ rtw_write8(Adapter, REG_BCN_CTRL, ++ rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION); ++#endif ++ //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked ++ //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5)); ++ //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3)); ++ ++ //dis BCN0 ATIM WND if if1 is station ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0)); ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Reset TSF for STA+AP concurrent mode ++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) { ++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ } ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ // disable Port0 TSF update ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ ++ // set net_type ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= mode; ++ rtw_write8(Adapter, MSR, val8); ++ ++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode); ++ ++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms ++ UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK)); ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN ++ StopTxBeacon(Adapter); ++ } ++ ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd ++ //rtw_write8(Adapter,REG_BCN_CTRL, 0x18); ++ } ++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) ++ { ++ ResumeTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x1a); ++ //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ } ++ else if(mode == _HW_STATE_AP_) ++ { ++ ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++ ResumeTxBeacon(Adapter); ++ ++ rtw_write8(Adapter, REG_BCN_CTRL, 0x12); ++ ++ //enable SW Beacon ++ rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8)); ++ ++ //Set RCR ++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 ++ rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet ++ //enable to rx data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); ++ //enable to rx ps-poll ++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); ++ ++ //Beacon Control related register for first time ++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms ++ ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++ rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms ++ rtw_write16(Adapter, REG_BCNTCFG, 0x00); ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); ++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms) ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); ++ ++ //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ ++ //enable BCN0 Function for if1 ++ //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) ++ rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1))); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE)) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, ++ rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION); ++#endif ++ ++ //dis BCN1 ATIM WND if if2 is station ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Reset TSF for STA+AP concurrent mode ++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) { ++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ } ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ } ++ ++} ++ ++static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 idx = 0; ++ u32 reg_macid; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ reg_macid = REG_MACID1; ++ } ++ else ++#endif ++ { ++ reg_macid = REG_MACID; ++ } ++ ++ for(idx = 0 ; idx < 6; idx++) ++ { ++ rtw_write8(Adapter, (reg_macid+idx), val[idx]); ++ } ++ ++} ++ ++static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 idx = 0; ++ u32 reg_bssid; ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ reg_bssid = REG_BSSID1; ++ } ++ else ++#endif ++ { ++ reg_bssid = REG_BSSID; ++ } ++ ++printk("hw_var_set_bssid reg=%x \n", reg_bssid); ++ ++ for(idx = 0 ; idx < 6; idx++) ++ { ++ rtw_write8(Adapter, (reg_bssid+idx), val[idx]); ++ } ++ ++} ++ ++static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u32 bcn_ctrl_reg; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ bcn_ctrl_reg = REG_BCN_CTRL_1; ++ } ++ else ++#endif ++ { ++ bcn_ctrl_reg = REG_BCN_CTRL; ++ } ++ ++ if(*((u8 *)val)) ++ { ++ rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); ++ } ++ else ++ { ++ rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT))); ++ } ++ ++ ++} ++ ++static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ u64 tsf; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++ ++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); ++ StopTxBeacon(Adapter); ++ } ++ ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR1, tsf); ++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32); ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3)); ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE ++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ++ ) { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue! ++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ ++ } ++ else ++ { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE ++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ++ ) { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR1, tsf); ++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", ++ __FUNCTION__, __LINE__); ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ } ++ ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause &= (~STOP_BCNQ); ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); ++ ResumeTxBeacon(Adapter); ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++ ++ ++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_)) ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0x00); ++ ++ ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ //reset TSF1 ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)); ++ ++ //disable update TSF1 ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ ++ // disable Port1's beacon function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ } ++ else ++ { ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(*((u8 *)val))//under sitesurvey ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_BCN); ++ rtw_write32(Adapter, REG_RCR, v); ++ ++ //disable update TSF ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ } ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ StopTxBeacon(Adapter); ++ } ++ ++ } ++ else//sitesurvey done ++ { ++ //enable to rx data frame ++ //write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4))); ++ else ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ } ++ ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 RetryLimit = 0x30; ++ u8 type = *((u8 *)val); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(type == 0) // prepare to join ++ { ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ StopTxBeacon(Adapter); ++ } ++ ++ //enable to rx data frame.Accept all data frame ++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ else ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; ++ } ++ else // Ad-hoc Mode ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ else if(type == 1) //joinbss_event call back when join res < 0 ++ { ++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_)) ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ ++ //reset TSF 1/2 after ResumeTxBeacon ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0)); ++ ++ } ++ } ++ else if(type == 2) //sta add event call back ++ { ++ ++ //enable update TSF ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4))); ++ else ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ //fixed beacon issue for 8191su........... ++ rtw_write8(Adapter,0x542 ,0x02); ++ RetryLimit = 0x7; ++ } ++ ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ ++ //reset TSF 1/2 after ResumeTxBeacon ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0)); ++ } ++ ++ } ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ ++#endif ++} ++static void SetHwReg8188ES(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++_func_enter_; ++ ++ switch(variable) ++ { ++ case HW_VAR_MEDIA_STATUS: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= *((u8 *)val); ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_MEDIA_STATUS1: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x03; ++ val8 |= *((u8 *)val) <<2; ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_SET_OPMODE: ++ hw_var_set_opmode(Adapter, variable, val); ++ break; ++ case HW_VAR_MAC_ADDR: ++ hw_var_set_macaddr(Adapter, variable, val); ++ break; ++ case HW_VAR_BSSID: ++ hw_var_set_bssid(Adapter, variable, val); ++ break; ++ case HW_VAR_BASIC_RATE: ++ { ++ u16 BrateCfg = 0; ++ u8 RateIndex = 0; ++ ++ // 2007.01.16, by Emily ++ // Select RRSR (in Legacy-OFDM and CCK) ++ // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. ++ // We do not use other rates. ++ HalSetBrateCfg( Adapter, val, &BrateCfg ); ++ DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg); ++ ++ //2011.03.30 add by Luke Lee ++ //CCK 2M ACK should be disabled for some BCM and Atheros AP IOT ++ //because CCK 2M has poor TXEVM ++ //CCK 5.5M & 11M ACK should be enabled for better performance ++ ++ pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d; ++ ++ BrateCfg |= 0x01; // default enable 1M ACK rate ++ // Set RRSR rate table. ++ rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff); ++ rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff); ++ rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0); ++ ++ // Set RTS initial rate ++ while(BrateCfg > 0x1) ++ { ++ BrateCfg = (BrateCfg>> 1); ++ RateIndex++; ++ } ++ // Ziv - Check ++ rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex); ++ } ++ break; ++ case HW_VAR_TXPAUSE: ++ rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val)); ++ break; ++ case HW_VAR_BCN_FUNC: ++ hw_var_set_bcn_func(Adapter, variable, val); ++ break; ++ case HW_VAR_CORRECT_TSF: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_correct_tsf(Adapter, variable, val); ++#else ++ { ++ u64 tsf; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //f = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; //us ++ ++ if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ++ ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); ++ StopTxBeacon(Adapter); ++ } ++ ++ // disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ // enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++ ++ if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ++ ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause &= (~STOP_BCNQ); ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); ++ ResumeTxBeacon(Adapter); ++ } ++ } ++#endif ++ break; ++ case HW_VAR_CHECK_BSSID: ++ if(*((u8 *)val)) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ u32 val32; ++ ++ val32 = rtw_read32(Adapter, REG_RCR); ++ ++ val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); ++ ++ rtw_write32(Adapter, REG_RCR, val32); ++ } ++ break; ++ case HW_VAR_MLME_DISCONNECT: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_disconnect(Adapter, variable, val); ++#else ++ { ++ //Set RCR to not to receive data frame when NO LINK state ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); ++ //reject all data frames ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++#endif ++ break; ++ case HW_VAR_MLME_SITESURVEY: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_sitesurvey(Adapter, variable, val); ++#else ++ if(*((u8 *)val))//under sitesurvey ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_BCN); ++ rtw_write32(Adapter, REG_RCR, v); ++ //reject all data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ else//sitesurvey done ++ { ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((is_client_associated_to_ap(Adapter) == _TRUE) || ++ ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ) ++ { ++ //enable to rx data frame ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ ++ if(Adapter->in_cta_test) ++ { ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(Adapter, REG_RCR, v); ++ } ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ } ++ } ++#endif ++ break; ++ case HW_VAR_MLME_JOIN: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_join(Adapter, variable, val); ++#else ++ { ++ u8 RetryLimit = 0x30; ++ u8 type = *((u8 *)val); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(type == 0) // prepare to join ++ { ++ //enable to rx data frame.Accept all data frame ++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ if(Adapter->in_cta_test) ++ { ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(Adapter, REG_RCR, v); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; ++ } ++ else // Ad-hoc Mode ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ else if(type == 1) //joinbss_event call back when join res < 0 ++ { ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ } ++ else if(type == 2) //sta add event call back ++ { ++ // enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ } ++#endif ++ break; ++ case HW_VAR_ON_RCR_AM: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM); ++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR)); ++ break; ++ case HW_VAR_OFF_RCR_AM: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM)); ++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR)); ++ break; ++ case HW_VAR_BEACON_INTERVAL: ++ rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val)); ++ ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ { ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u16 bcn_interval = *((u16 *)val); ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){ ++ DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1); ++ rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio ++ } ++ else{ ++ ++ } ++ } ++#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ break; ++ case HW_VAR_SLOT_TIME: ++ { ++ u8 u1bAIFS, aSifsTime; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ rtw_write8(Adapter, REG_SLOT, val[0]); ++ ++ if(pmlmeinfo->WMM_enable == 0) ++ { ++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B) ++ aSifsTime = 10; ++ else ++ aSifsTime = 16; ++ ++ u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime); ++ ++ // Temporary removed, 2008.06.20. ++ rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS); ++ } ++ } ++ break; ++ case HW_VAR_RESP_SIFS: ++ { ++#if 0 ++ // SIFS for OFDM Data ACK ++ rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]); ++ // SIFS for OFDM consecutive tx like CTS data! ++ rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]); ++ ++ rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]); ++ rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]); ++ ++ // 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. ++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]); ++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]); ++#else ++ //SIFS_Timer = 0x0a0a0808; ++ //RESP_SIFS for CCK ++ rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08) ++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08) ++ //RESP_SIFS for OFDM ++ rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a) ++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a) ++#endif ++ } ++ break; ++ case HW_VAR_ACK_PREAMBLE: ++ { ++ u8 regTmp; ++ u8 bShortPreamble = *( (PBOOLEAN)val ); ++ // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) ++ regTmp = (pHalData->nCur40MhzPrimeSC)<<5; ++ //regTmp = 0; ++ if(bShortPreamble) ++ regTmp |= 0x80; ++ ++ rtw_write8(Adapter, REG_RRSR+2, regTmp); ++ } ++ break; ++ case HW_VAR_SEC_CFG: ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC ++#else ++ rtw_write8(Adapter, REG_SECCFG, *((u8 *)val)); ++#endif ++ break; ++ case HW_VAR_DM_FLAG: ++ podmpriv->SupportAbility = *((u8 *)val); ++ break; ++ case HW_VAR_DM_FUNC_OP: ++ if(val[0]) ++ {// save dm flag ++ podmpriv->BK_SupportAbility = podmpriv->SupportAbility; ++ } ++ else ++ {// restore dm flag ++ podmpriv->SupportAbility = podmpriv->BK_SupportAbility; ++ } ++ break; ++ case HW_VAR_DM_FUNC_SET: ++ if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){ ++ pdmpriv->DMFlag = pdmpriv->InitDMFlag; ++ podmpriv->SupportAbility = pdmpriv->InitODMFlag; ++ } ++ else{ ++ podmpriv->SupportAbility |= *((u32 *)val); ++ } ++ break; ++ case HW_VAR_DM_FUNC_CLR: ++ podmpriv->SupportAbility &= *((u32 *)val); ++ break; ++ case HW_VAR_CAM_EMPTY_ENTRY: ++ { ++ u8 ucIndex = *((u8 *)val); ++ u8 i; ++ u32 ulCommand=0; ++ u32 ulContent=0; ++ u32 ulEncAlgo=CAM_AES; ++ ++ for(i=0;iAcParam_BE = ((u32 *)(val))[0]; ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_AC_PARAM_BK: ++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_AMPDU_MIN_SPACE: ++ { ++ u8 MinSpacingToSet; ++ u8 SecMinSpace; ++ ++ MinSpacingToSet = *((u8 *)val); ++ if(MinSpacingToSet <= 7) ++ { ++ switch(Adapter->securitypriv.dot11PrivacyAlgrthm) ++ { ++ case _NO_PRIVACY_: ++ case _AES_: ++ SecMinSpace = 0; ++ break; ++ ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ SecMinSpace = 6; ++ break; ++ default: ++ SecMinSpace = 7; ++ break; ++ } ++ ++ if(MinSpacingToSet < SecMinSpace){ ++ MinSpacingToSet = SecMinSpace; ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg)); ++ rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet); ++ } ++ } ++ break; ++ case HW_VAR_AMPDU_FACTOR: ++ { ++ u8 RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9}; ++ u8 RegToSet_BT[4]={0x31,0x74,0x42, 0x97}; ++ u8 FactorToSet; ++ u8 *pRegToSet; ++ u8 index = 0; ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pHalData->bt_coexist.BT_Coexist) && ++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) ) ++ pRegToSet = RegToSet_BT; // 0x97427431; ++ else ++#endif ++ pRegToSet = RegToSet_Normal; // 0xb972a841; ++ ++ FactorToSet = *((u8 *)val); ++ if(FactorToSet <= 3) ++ { ++ FactorToSet = (1<<(FactorToSet + 2)); ++ if(FactorToSet>0xf) ++ FactorToSet = 0xf; ++ ++ for(index=0; index<4; index++) ++ { ++ if((pRegToSet[index] & 0xf0) > (FactorToSet<<4)) ++ pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4); ++ ++ if((pRegToSet[index] & 0x0f) > FactorToSet) ++ pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet); ++ ++ rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]); ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); ++ } ++ } ++ break; ++ case HW_VAR_RXDMA_AGG_PG_TH: ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, *((u8 *)val)); ++ break; ++ case HW_VAR_SET_RPWM: ++#ifdef CONFIG_LPS_LCLK ++ { ++ u8 ps_state = *((u8 *)val); ++ DBG_871X_LEVEL(_drv_debug_, "+%s: ps_state:0x%02x+\n", __func__, ps_state); ++ //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. ++ //BIT0 value - 1: 32k, 0:40MHz. ++ //BIT6 value - 1: report cpwm value after success set, 0:do not report. ++ //BIT7 value - Toggle bit change. ++ //modify by Thomas. 2012/4/2. ++ ps_state = ps_state & 0xC1; ++ ++#ifdef CONFIG_EXT_CLK //for sprd ++ if(ps_state&BIT(6)) // want to leave 32k ++ { ++ //enable ext clock req before leave LPS-32K ++ //DBG_871X("enable ext clock req before leaving LPS-32K\n"); ++ EnableGpio5ClockReq(Adapter, _FALSE, 1); ++ } ++#endif //CONFIG_EXT_CLK ++ ++ //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state); ++ rtw_write8(Adapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, ps_state); ++ DBG_871X_LEVEL(_drv_debug_, "-%s: ps_state:0x%02x-\n", __func__, ps_state); ++ } ++#endif ++ break; ++ case HW_VAR_H2C_FW_PWRMODE: ++ { ++ u8 psmode = (*(u8 *)val); ++ ++ // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power ++ // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. ++ if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID))) ++ { ++ ODM_RF_Saving(podmpriv, _TRUE); ++ } ++ rtl8188e_set_FwPwrMode_cmd(Adapter, psmode); ++ } ++ break; ++ case HW_VAR_H2C_FW_JOINBSSRPT: ++ { ++ u8 mstatus = (*(u8 *)val); ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus); ++ } ++ break; ++#ifdef CONFIG_P2P_PS ++ case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: ++ { ++ u8 p2p_ps_state = (*(u8 *)val); ++ rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state); ++ } ++ break; ++#endif // CONFIG_P2P_PS ++ case HW_VAR_INITIAL_GAIN: ++ { ++ DIG_T *pDigTable = &podmpriv->DM_DigTable; ++ u32 rx_gain = ((u32 *)(val))[0]; ++ ++ if(rx_gain == 0xff){//restore rx gain ++ ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue); ++ } ++ else{ ++ pDigTable->BackupIGValue = pDigTable->CurIGValue; ++ ODM_Write_DIG(podmpriv,rx_gain); ++ } ++ } ++ break; ++ case HW_VAR_TRIGGER_GPIO_0: ++// rtl8192cu_trigger_gpio_0(Adapter); ++ break; ++#ifdef CONFIG_BT_COEXIST ++ case HW_VAR_BT_SET_COEXIST: ++ { ++ u8 bStart = (*(u8 *)val); ++ rtl8192c_set_dm_bt_coexist(Adapter, bStart); ++ } ++ break; ++ case HW_VAR_BT_ISSUE_DELBA: ++ { ++ u8 dir = (*(u8 *)val); ++ rtl8192c_issue_delete_ba(Adapter, dir); ++ } ++ break; ++#endif ++#if (RATE_ADAPTIVE_SUPPORT==1) ++ case HW_VAR_RPT_TIMER_SETTING: ++ { ++ u16 min_rpt_time = (*(u16 *)val); ++ ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Optimum_antenna); ++ ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time); ++ } ++ break; ++#endif ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ case HW_VAR_ANTENNA_DIVERSITY_LINK: ++ //SwAntDivRestAfterLink8192C(Adapter); ++ ODM_SwAntDivRestAfterLink(podmpriv); ++ break; ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case HW_VAR_ANTENNA_DIVERSITY_SELECT: ++ { ++ u8 Optimum_antenna = (*(u8 *)val); ++ u8 Ant ; ++ //switch antenna to Optimum_antenna ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ if(pHalData->CurAntenna != Optimum_antenna) ++ { ++ Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT; ++ ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant); ++ ++ pHalData->CurAntenna = Optimum_antenna ; ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ } ++ } ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22. ++ pHalData->EfuseUsedBytes = *((u16 *)val); ++ break; ++ case HW_VAR_FIFO_CLEARN_UP: ++ { ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); ++ u8 trycnt = 100; ++ ++ //pause tx ++ rtw_write8(Adapter,REG_TXPAUSE,0xff); ++ ++ //keep sn ++ Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ); ++ ++ //RX DMA stop ++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); ++ do{ ++ if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE)) ++ break; ++ }while(trycnt--); ++ if(trycnt ==0) ++ DBG_8192C("Stop RX DMA failed...... \n"); ++ ++ //RQPN Load 0 ++ rtw_write16(Adapter,REG_RQPN_NPQ,0x0); ++ rtw_write32(Adapter,REG_RQPN,0x80000000); ++ rtw_mdelay_os(10); ++ ++ } ++ break; ++ case HW_VAR_CHECK_TXBUF: ++#ifdef CONFIG_CONCURRENT_MODE ++ { ++ int i; ++ u8 RetryLimit = 0x01; ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ for(i=0;i<1000;i++) ++ { ++ if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204)) ++ { ++ //DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i); ++ rtw_msleep_os(10); ++ } ++ else ++ { ++ DBG_871X("no packet in tx packet buffer (%d)\n", i); ++ break; ++ } ++ } ++ ++ RetryLimit = 0x30; ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ ++ } ++#endif ++ break; ++#ifdef CONFIG_WOWLAN ++ case HW_VAR_WOWLAN: ++ { ++ struct wowlan_ioctl_param *poidparam; ++ struct recv_buf *precvbuf; ++ struct security_priv *psecuritypriv = &Adapter->securitypriv; ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); ++ int res, i; ++ u32 tmp; ++ u16 len = 0; ++ u64 iv_low = 0, iv_high = 0; ++ u8 mstatus = (*(u8 *)val); ++ u8 trycnt = 100; ++ u8 data[4]; ++ u8 val8; ++ ++ poidparam = (struct wowlan_ioctl_param *)val; ++ switch (poidparam->subcode){ ++ case WOWLAN_ENABLE: ++ DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n"); ++ ++ val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; ++ rtw_write8(Adapter, REG_SECCFG, val8); ++ DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG)); ++ ++ SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE); ++ ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1); ++ rtw_msleep_os(2); ++ ++ //Set Pattern ++ //if(adapter_to_pwrctl(Adapter)->wowlan_pattern==_TRUE) ++ // rtw_wowlan_reload_pattern(Adapter); ++ ++ //RX DMA stop ++ DBG_871X_LEVEL(_drv_always_, "Pause DMA\n"); ++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); ++ do{ ++ if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) { ++ DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n"); ++ break; ++ } else { ++ // If RX_DMA is not idle, receive one pkt from DMA ++ res = sdio_local_read(Adapter, SDIO_REG_RX0_REQ_LEN, 4, (u8*)&tmp); ++ //len = le16_to_cpu(*(u16*)data); ++ if (tmp == 0){ ++ res = sdio_local_read(Adapter, SDIO_REG_HISR, 4, (u8*)&tmp); ++ DBG_871X_LEVEL(_drv_info_, "read SDIO_REG_HISR: 0x%08x\n", tmp); ++ } ++ res = RecvOnePkt(Adapter, tmp); ++ DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res); ++ } ++ }while(trycnt--); ++ if(trycnt ==0) ++ DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n"); ++ ++ //Enable CPWM2 only. ++ DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n"); ++ res = sdio_local_read(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp); ++ if (!res) ++ DBG_871X_LEVEL(_drv_info_, "read SDIO_REG_HIMR: 0x%08x\n", tmp); ++ else ++ DBG_871X_LEVEL(_drv_info_, "sdio_local_read fail\n"); ++ ++ tmp = SDIO_HIMR_CPWM2_MSK; ++ ++ res = sdio_local_write(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp); ++ ++ if (!res){ ++ res = sdio_local_read(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp); ++ DBG_871X_LEVEL(_drv_info_, "read again SDIO_REG_HIMR: 0x%08x\n", tmp); ++ }else ++ DBG_871X_LEVEL(_drv_info_, "sdio_local_write fail\n"); ++ ++ //Set WOWLAN H2C command. ++ DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n"); ++ rtl8188es_set_wowlan_cmd(Adapter, 1); ++ ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ trycnt = 10; ++ ++ while(!(mstatus&BIT1) && trycnt>1) { ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus); ++ trycnt --; ++ rtw_msleep_os(2); ++ } ++ ++ pwrctl->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON); ++ DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n", pwrctl->wowlan_wake_reason); ++ ++ //rtw_msleep_os(10); ++ break; ++ case WOWLAN_DISABLE: ++ trycnt = 10; ++ ++ DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n"); ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, 0); ++ ++ rtw_write8( Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC ++ DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG)); ++ ++ pwrctl->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON); ++ DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n", pwrctl->wowlan_wake_reason); ++ rtl8188es_set_wowlan_cmd(Adapter, 0); ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus); ++ ++ while(mstatus&BIT1 && trycnt>1) { ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus); ++ trycnt --; ++ rtw_msleep_os(2); ++ } ++ ++ if (mstatus & BIT1) { ++ printk("System did not release RX_DMA\n"); ++ } else { ++ // 3.1 read fw iv ++ iv_low = rtw_read32(Adapter, REG_TXPKTBUF_IV_LOW); ++ iv_high = rtw_read32(Adapter, REG_TXPKTBUF_IV_HIGH); ++ pwrctl->wowlan_fw_iv = iv_high << 32 | iv_low; ++ DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv); ++ //Update TX iv data. ++ //rtw_set_sec_iv(Adapter); ++ SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE); ++ } ++ if((pwrctl->wowlan_wake_reason != FWDecisionDisconnect) && ++ (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) && ++ (pwrctl->wowlan_wake_reason != Rx_DisAssoc) && ++ (pwrctl->wowlan_wake_reason != Rx_DeAuth)) ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1); ++ ++ rtw_msleep_os(5); ++ ++ //rtw_msleep_os(10); ++ break; ++ default: ++ break; ++ } ++ } ++ break; ++#endif //CONFIG_WOWLAN ++ case HW_VAR_APFM_ON_MAC: ++ pHalData->bMacPwrCtrlOn = *val; ++ DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn); ++ break; ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ case HW_VAR_TX_RPT_MAX_MACID: ++ { ++ u8 maxMacid = *val; ++ DBG_8192C("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1); ++ rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1); ++ } ++ break; ++#endif // (RATE_ADAPTIVE_SUPPORT == 1) ++ case HW_VAR_H2C_MEDIA_STATUS_RPT: ++ { ++ rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val)); ++ } ++ break; ++ case HW_VAR_BCN_VALID: ++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw ++ rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0); ++ break; ++ default: ++ ++ break; ++ } ++ ++_func_exit_; ++} ++ ++static void GetHwReg8188ES(PADAPTER padapter, u8 variable, u8 *val) ++{ ++ PHAL_DATA_TYPE pHalData= GET_HAL_DATA(padapter); ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++_func_enter_; ++ ++ switch (variable) ++ { ++ case HW_VAR_BASIC_RATE: ++ *((u16*)val) = pHalData->BasicRateSet; ++ break; ++ ++ case HW_VAR_TXPAUSE: ++ val[0] = rtw_read8(padapter, REG_TXPAUSE); ++ break; ++ ++ case HW_VAR_BCN_VALID: ++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 ++ val[0] = (BIT0 & rtw_read8(padapter, REG_TDECTRL+2))?_TRUE:_FALSE; ++ break; ++ ++ case HW_VAR_DM_FLAG: ++ val[0] = podmpriv->SupportAbility; ++ break; ++ ++ case HW_VAR_RF_TYPE: ++ val[0] = pHalData->rf_type; ++ break; ++ ++ case HW_VAR_FWLPS_RF_ON: ++ { ++ //When we halt NIC, we should check if FW LPS is leave. ++ if ((padapter->bSurpriseRemoved == _TRUE) || ++ (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) ++ { ++ // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, ++ // because Fw is unload. ++ val[0] = _TRUE; ++ } ++ else ++ { ++ u32 valRCR; ++ valRCR = rtw_read32(padapter, REG_RCR); ++ valRCR &= 0x00070000; ++ if(valRCR) ++ val[0] = _FALSE; ++ else ++ val[0] = _TRUE; ++ } ++ } ++ break; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case HW_VAR_CURRENT_ANTENNA: ++ val[0] = pHalData->CurAntenna; ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22. ++ *((u16*)val) = pHalData->EfuseUsedBytes; ++ break; ++ ++ case HW_VAR_APFM_ON_MAC: ++ *val = pHalData->bMacPwrCtrlOn; ++ break; ++ case HW_VAR_CHK_HI_QUEUE_EMPTY: ++ *val = ((rtw_read32(padapter, REG_HGQ_INFORMATION)&0x0000ff00)==0) ? _TRUE:_FALSE; ++ break; ++ case HW_VAR_GET_CPWM: ++ *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1); ++ break; ++ case HW_VAR_C2HEVT_CLEAR: ++ *val = rtw_read8(padapter, REG_C2HEVT_CLEAR); ++ break; ++ case HW_VAR_C2HEVT_MSG_NORMAL: ++ *val = rtw_read8(padapter, REG_C2HEVT_MSG_NORMAL); ++ break; ++ case HW_VAR_SYS_CLKR: ++ *val = rtw_read8(padapter, REG_SYS_CLKR); ++ break; ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++// ++// Description: ++// Query setting of specified variable. ++// ++u8 ++GetHalDefVar8188ESDIO( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 bResult = _SUCCESS; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: ++ { ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct sta_priv * pstapriv = &Adapter->stapriv; ++ struct sta_info * psta; ++ psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); ++ if(psta) ++ { ++ *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ } ++ } ++ ++ break; ++ case HAL_DEF_IS_SUPPORT_ANT_DIV: ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ *((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE; ++ #endif ++ break; ++ case HAL_DEF_CURRENT_ANTENNA: ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ *(( u8*)pValue) = pHalData->CurAntenna; ++#endif ++ break; ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ case HAL_DEF_RA_DECISION_RATE: ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID); ++ } ++ break; ++ ++ case HAL_DEF_RA_SGI: ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID); ++ } ++ break; ++#endif ++ ++ ++ case HAL_DEF_PT_PWR_STATUS: ++#if(POWER_TRAINING_ACTIVE==1) ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID); ++ } ++#endif //(POWER_TRAINING_ACTIVE==1) ++ break; ++ ++ case HW_VAR_MAX_RX_AMPDU_FACTOR: ++ *(( u32*)pValue) = MAX_AMPDU_FACTOR_16K; ++ break; ++ ++ case HW_DEF_RA_INFO_DUMP: ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ { ++ u8 entry_id = *((u8*)pValue); ++ u8 i; ++ u8 bLinked = _FALSE; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++#endif //CONFIG_CONCURRENT_MODE ++ ++ //if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== _TRUE) ++ ++ if(rtw_linked_check(Adapter)) ++ bLinked = _TRUE; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) ++ bLinked = _TRUE; ++#endif ++ ++ if(bLinked){ ++ DBG_871X("============ RA status check ===================\n"); ++ if(Adapter->bRxRSSIDisplay >30) ++ Adapter->bRxRSSIDisplay = 1; ++ for(i=0;i< Adapter->bRxRSSIDisplay;i++){ ++ DBG_8192C("Mac_id:%d ,RSSI:%d ,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n", ++ i, ++ pHalData->odmpriv.RAInfo[i].RssiStaRA, ++ pHalData->odmpriv.RAInfo[i].RateID, ++ pHalData->odmpriv.RAInfo[i].RAUseRate, ++ pHalData->odmpriv.RAInfo[i].RateSGI, ++ pHalData->odmpriv.RAInfo[i].DecisionRate, ++ pHalData->odmpriv.RAInfo[i].PTStage); ++ } ++ } ++ } ++#endif // (RATE_ADAPTIVE_SUPPORT == 1) ++ break; ++ ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ *(( u8*)pValue) = pHalData->bDumpRxPkt; ++ break; ++ case HAL_DEF_DBG_DUMP_TXPKT: ++ *(( u8*)pValue) = pHalData->bDumpTxPkt; ++ break; ++ default: ++ bResult = GetHalDefVar(Adapter, eVariable, pValue); ++ break; ++ } ++ ++ return bResult; ++} ++ ++ ++ ++ ++// ++// Description: ++// Change default setting of specified variable. ++// ++u8 ++SetHalDefVar8188ESDIO( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 bResult = _TRUE; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_DBG_DM_FUNC: ++ { ++ u8 dm_func = *(( u8*)pValue); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++ ++ if(dm_func == 0){ //disable all dynamic func ++ podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE; ++ DBG_8192C("==> Disable all dynamic function...\n"); ++ } ++ else if(dm_func == 1){//disable DIG ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG); ++ DBG_8192C("==> Disable DIG...\n"); ++ } ++ else if(dm_func == 2){//disable High power ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR); ++ } ++ else if(dm_func == 3){//disable tx power tracking ++ podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION); ++ DBG_8192C("==> Disable tx power tracking...\n"); ++ } ++ //else if(dm_func == 4){//disable BT coexistence ++ // pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); ++ //} ++ else if(dm_func == 5){//disable antenna diversity ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV); ++ } ++ else if(dm_func == 6){//turn on all dynamic func ++ if(!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) ++ { ++ DIG_T *pDigTable = &podmpriv->DM_DigTable; ++ pDigTable->CurIGValue= rtw_read8(Adapter,0xc50); ++ } ++ //pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; ++ podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE; ++ DBG_8192C("==> Turn on all dynamic function...\n"); ++ } ++ } ++ break; ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ pHalData->bDumpRxPkt = *(( u8*)pValue); ++ break; ++ case HAL_DEF_DBG_DUMP_TXPKT: ++ pHalData->bDumpTxPkt = *(( u8*)pValue); ++ break; ++ default: ++ bResult = SetHalDefVar(Adapter, eVariable, pValue); ++ break; ++ } ++ ++ return bResult; ++} ++ ++void UpdateHalRAMask8188ESdio(PADAPTER padapter, u32 mac_id, u8 rssi_level) ++{ ++ //volatile unsigned int result; ++ u8 init_rate=0; ++ u8 networkType, raid; ++ u32 mask,rate_bitmap; ++ u8 shortGIrate = _FALSE; ++ int supportRateNum = 0; ++ struct sta_info *psta; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ //struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ if (mac_id >= NUM_STA) //CAM_SIZE ++ { ++ return; ++ } ++ ++ psta = pmlmeinfo->FW_sta_info[mac_id].psta; ++ if(psta == NULL) ++ { ++ return; ++ } ++ ++ switch (mac_id) ++ { ++ case 0:// for infra mode ++#ifdef CONFIG_CONCURRENT_MODE ++ case 2:// first station uses macid=0, second station uses macid=2 ++#endif ++ supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates); ++ networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0; ++ ++ ++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps))) ++ { ++ shortGIrate = _TRUE; ++ } ++ ++ break; ++ ++ case 1://for broadcast/multicast ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ networkType = WIRELESS_11B; ++ else ++ networkType = WIRELESS_11G; ++ raid = networktype_to_raid(networkType); ++ mask = update_basic_rate(cur_network->SupportedRates, supportRateNum); ++ ++ ++ break; ++ ++ default: //for each sta in IBSS ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ ++ //todo: support HT in IBSS ++ ++ break; ++ } ++ ++ //mask &=0xffffffff; ++ rate_bitmap = 0x0fffffff; ++#ifdef CONFIG_ODM_REFRESH_RAMASK ++ { ++ rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level); ++ DBG_8192C("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", ++ __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap); ++ } ++#endif ++ mask &= rate_bitmap; ++ ++ ++ init_rate = get_highest_rate_idx(mask)&0x3f; ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ u8 arg = 0; ++ ++ //arg = (cam_idx-4)&0x1f;//MACID ++ arg = mac_id&0x1f;//MACID ++ ++ arg |= BIT(7); ++ ++ if (shortGIrate==_TRUE) ++ arg |= BIT(5); ++ mask |= ((raid<<28)&0xf0000000); ++ ++ DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg); ++ psta->ra_mask=mask; ++#ifdef CONFIG_INTEL_PROXIM ++ if(padapter->proximity.proxim_on ==_TRUE){ ++ arg &= ~BIT(6); ++ } ++ else { ++ arg |= BIT(6); ++ } ++#endif //CONFIG_INTEL_PROXIM ++ rtl8188e_set_raid_cmd(padapter, mask); ++ ++ } ++ else ++ { ++ ++#if(RATE_ADAPTIVE_SUPPORT == 1) ++ ++ ODM_RA_UpdateRateInfo_8188E( ++ &(pHalData->odmpriv), ++ mac_id, ++ raid, ++ mask, ++ shortGIrate ++ ); ++ ++#endif ++ } ++ ++ ++ //set ra_id ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ ++} ++ ++ ++static VOID ++_BeaconFunctionEnable( ++ IN PADAPTER padapter, ++ IN BOOLEAN Enable, ++ IN BOOLEAN Linked ++ ) ++{ ++ rtw_write8(padapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); ++// RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("_BeaconFunctionEnable 0x550 0x%x\n", rtw_read8(padapter, 0x550))); ++ ++ rtw_write8(padapter, REG_RD_CTRL+1, 0x6F); ++} ++ ++void SetBeaconRelatedRegisters8188ESdio(PADAPTER padapter) ++{ ++ u32 value32; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 bcn_ctrl_reg = REG_BCN_CTRL; ++ //reset TSF, enable update TSF, correcting TSF On Beacon ++ ++ //REG_BCN_INTERVAL ++ //REG_BCNDMATIM ++ //REG_ATIMWND ++ //REG_TBTT_PROHIBIT ++ //REG_DRVERLYINT ++ //REG_BCN_MAX_ERR ++ //REG_BCNTCFG //(0x510) ++ //REG_DUAL_TSF_RST ++ //REG_BCN_CTRL //(0x550) ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->iface_type == IFACE_PORT1){ ++ bcn_ctrl_reg = REG_BCN_CTRL_1; ++ } ++#endif ++ // ++ // ATIM window ++ // ++ rtw_write16(padapter, REG_ATIMWND, 2); ++ ++ // ++ // Beacon interval (in unit of TU). ++ // ++ rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); ++ ++ _InitBeaconParameters(padapter); ++ ++ rtw_write8(padapter, REG_SLOT, 0x09); ++ ++ // ++ // Force beacon frame transmission even after receiving beacon frame from other ad hoc STA ++ // ++ //PlatformEFIOWrite1Byte(Adapter, BCN_ERR_THRESH, 0x0a); // We force beacon sent to prevent unexpect disconnect status in Ad hoc mode ++ ++ // ++ // Reset TSF Timer to zero, added by Roger. 2008.06.24 ++ // ++ value32 = rtw_read32(padapter, REG_TCR); ++ value32 &= ~TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ value32 |= TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ // TODO: Modify later (Find the right parameters) ++ // NOTE: Fix test chip's bug (about contention windows's randomness) ++// if (OpMode == RT_OP_MODE_IBSS || OpMode == RT_OP_MODE_AP) ++ if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_AP_STATE) == _TRUE) ++ { ++ rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); ++ rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); ++ } ++ ++ _BeaconFunctionEnable(padapter, _TRUE, _TRUE); ++ ++ ResumeTxBeacon(padapter); ++ rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1)); ++} ++ ++void rtl8188es_set_hal_ops(PADAPTER padapter) ++{ ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++ ++_func_enter_; ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->isprimary) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ //set hardware operation functions ++ padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); ++ if(padapter->HalData == NULL){ ++ DBG_8192C("cant not alloc memory for HAL DATA \n"); ++ } ++ } ++ ++ padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); ++ ++ pHalFunc->hal_power_on = InitPowerOn_rtl8188es; ++ pHalFunc->hal_power_off = hal_poweroff_rtl8188es; ++ ++ pHalFunc->hal_init = &rtl8188es_hal_init; ++ pHalFunc->hal_deinit = &rtl8188es_hal_deinit; ++ ++ pHalFunc->inirp_init = &rtl8188es_inirp_init; ++ pHalFunc->inirp_deinit = &rtl8188es_inirp_deinit; ++ ++ pHalFunc->init_xmit_priv = &rtl8188es_init_xmit_priv; ++ pHalFunc->free_xmit_priv = &rtl8188es_free_xmit_priv; ++ ++ pHalFunc->init_recv_priv = &rtl8188es_init_recv_priv; ++ pHalFunc->free_recv_priv = &rtl8188es_free_recv_priv; ++ ++ pHalFunc->InitSwLeds = &rtl8188es_InitSwLeds; ++ pHalFunc->DeInitSwLeds = &rtl8188es_DeInitSwLeds; ++ ++ pHalFunc->init_default_value = &rtl8188es_init_default_value; ++ pHalFunc->intf_chip_configure = &rtl8188es_interface_configure; ++ pHalFunc->read_adapter_info = &ReadAdapterInfo8188ES; ++ ++ pHalFunc->enable_interrupt = &EnableInterrupt8188ESdio; ++ pHalFunc->disable_interrupt = &DisableInterrupt8188ESdio; ++ ++#ifdef CONFIG_WOWLAN ++ pHalFunc->clear_interrupt = &ClearInterrupt8189ESdio; ++#endif ++ ++ pHalFunc->SetHwRegHandler = &SetHwReg8188ES; ++ pHalFunc->GetHwRegHandler = &GetHwReg8188ES; ++ ++ pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188ESDIO; ++ pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188ESDIO; ++ ++ pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188ESdio; ++ pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188ESdio; ++ ++ pHalFunc->hal_xmit = &rtl8188es_hal_xmit; ++ pHalFunc->mgnt_xmit = &rtl8188es_mgnt_xmit; ++ pHalFunc->hal_xmitframe_enqueue = &rtl8188es_hal_xmitframe_enqueue; ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ pHalFunc->hostap_mgnt_xmit_entry = NULL; ++// pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry; ++#endif ++ rtl8188e_set_hal_ops(pHalFunc); ++_func_exit_; ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_ops.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_ops.c +new file mode 100644 +index 00000000..979518c5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/sdio/sdio_ops.c +@@ -0,0 +1,1959 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#define _SDIO_OPS_C_ ++ ++#include ++#include ++#include ++#include ++ ++//#define SDIO_DEBUG_IO 1 ++ ++#ifdef CONFIG_EXT_CLK ++void EnableGpio5ClockReq(PADAPTER Adapter, u8 in_interrupt, u32 Enable); ++#endif //CONFIG_EXT_CLK ++// ++// Description: ++// The following mapping is for SDIO host local register space. ++// ++// Creadted by Roger, 2011.01.31. ++// ++static void HalSdioGetCmdAddr8723ASdio( ++ IN PADAPTER padapter, ++ IN u8 DeviceID, ++ IN u32 Addr, ++ OUT u32* pCmdAddr ++ ) ++{ ++ switch (DeviceID) ++ { ++ case SDIO_LOCAL_DEVICE_ID: ++ *pCmdAddr = ((SDIO_LOCAL_DEVICE_ID << 13) | (Addr & SDIO_LOCAL_MSK)); ++ break; ++ ++ case WLAN_IOREG_DEVICE_ID: ++ *pCmdAddr = ((WLAN_IOREG_DEVICE_ID << 13) | (Addr & WLAN_IOREG_MSK)); ++ break; ++ ++ case WLAN_TX_HIQ_DEVICE_ID: ++ *pCmdAddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK)); ++ break; ++ ++ case WLAN_TX_MIQ_DEVICE_ID: ++ *pCmdAddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK)); ++ break; ++ ++ case WLAN_TX_LOQ_DEVICE_ID: ++ *pCmdAddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK)); ++ break; ++ ++ case WLAN_RX0FF_DEVICE_ID: ++ *pCmdAddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (Addr & WLAN_RX0FF_MSK)); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static u8 get_deviceid(u32 addr) ++{ ++ u8 devideId; ++ u16 pseudoId; ++ ++ ++ pseudoId = (u16)(addr >> 16); ++ switch (pseudoId) ++ { ++ case 0x1025: ++ devideId = SDIO_LOCAL_DEVICE_ID; ++ break; ++ ++ case 0x1026: ++ devideId = WLAN_IOREG_DEVICE_ID; ++ break; ++ ++// case 0x1027: ++// devideId = SDIO_FIRMWARE_FIFO; ++// break; ++ ++ case 0x1031: ++ devideId = WLAN_TX_HIQ_DEVICE_ID; ++ break; ++ ++ case 0x1032: ++ devideId = WLAN_TX_MIQ_DEVICE_ID; ++ break; ++ ++ case 0x1033: ++ devideId = WLAN_TX_LOQ_DEVICE_ID; ++ break; ++ ++ case 0x1034: ++ devideId = WLAN_RX0FF_DEVICE_ID; ++ break; ++ ++ default: ++// devideId = (u8)((addr >> 13) & 0xF); ++ devideId = WLAN_IOREG_DEVICE_ID; ++ break; ++ } ++ ++ return devideId; ++} ++ ++/* ++ * Ref: ++ * HalSdioGetCmdAddr8723ASdio() ++ */ ++static u32 _cvrt2ftaddr(const u32 addr, u8 *pdeviceId, u16 *poffset) ++{ ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ ++ ++ deviceId = get_deviceid(addr); ++ offset = 0; ++ ++ switch (deviceId) ++ { ++ case SDIO_LOCAL_DEVICE_ID: ++ offset = addr & SDIO_LOCAL_MSK; ++ break; ++ ++ case WLAN_TX_HIQ_DEVICE_ID: ++ case WLAN_TX_MIQ_DEVICE_ID: ++ case WLAN_TX_LOQ_DEVICE_ID: ++ offset = addr & WLAN_FIFO_MSK; ++ break; ++ ++ case WLAN_RX0FF_DEVICE_ID: ++ offset = addr & WLAN_RX0FF_MSK; ++ break; ++ ++ case WLAN_IOREG_DEVICE_ID: ++ default: ++ deviceId = WLAN_IOREG_DEVICE_ID; ++ offset = addr & WLAN_IOREG_MSK; ++ break; ++ } ++ ftaddr = (deviceId << 13) | offset; ++ ++ if (pdeviceId) *pdeviceId = deviceId; ++ if (poffset) *poffset = offset; ++ ++ return ftaddr; ++} ++ ++u8 _sdio_read8(PADAPTER padapter, u32 addr) ++{ ++ struct intf_hdl * pintfhdl; ++ u32 ftaddr; ++ u8 val; ++ ++_func_enter_; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ ftaddr = _cvrt2ftaddr(addr, NULL, NULL); ++ val = _sd_read8(pintfhdl, ftaddr, NULL); ++ ++_func_exit_; ++ ++ return val; ++} ++ ++u8 sdio_read8(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u32 ftaddr; ++ u8 val; ++ ++_func_enter_; ++ ftaddr = _cvrt2ftaddr(addr, NULL, NULL); ++ val = sd_read8(pintfhdl, ftaddr, NULL); ++ ++_func_exit_; ++ ++ return val; ++} ++ ++u16 sdio_read16(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u32 ftaddr; ++ u16 val; ++ ++_func_enter_; ++ ++ ftaddr = _cvrt2ftaddr(addr, NULL, NULL); ++ sd_cmd52_read(pintfhdl, ftaddr, 2, (u8*)&val); ++ val = le16_to_cpu(val); ++ ++_func_exit_; ++ ++ return val; ++} ++ ++u32 _sdio_read32(PADAPTER padapter, u32 addr) ++{ ++ //PADAPTER padapter; ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ u32 val; ++ s32 err; ++ ++_func_enter_; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = _sd_cmd52_read(pintfhdl, ftaddr, 4, (u8*)&val); ++#ifdef SDIO_DEBUG_IO ++ if (!err) { ++#endif ++ val = le32_to_cpu(val); ++ return val; ++#ifdef SDIO_DEBUG_IO ++ } ++ ++ DBG_871X(KERN_ERR "%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n", __func__, err, addr); ++ return SDIO_ERR_VAL32; ++#endif ++ } ++ ++ // 4 bytes alignment ++ shift = ftaddr & 0x3; ++ if (shift == 0) { ++ val = _sd_read32(pintfhdl, ftaddr, NULL); ++ } else { ++ u8 *ptmpbuf; ++ ++ ptmpbuf = (u8*)rtw_malloc(8); ++ if (NULL == ptmpbuf) { ++ DBG_871X(KERN_ERR "%s: Allocate memory FAIL!(size=8) addr=0x%x\n", __func__, addr); ++ return SDIO_ERR_VAL32; ++ } ++ ++ ftaddr &= ~(u16)0x3; ++ _sd_read(pintfhdl, ftaddr, 8, ptmpbuf); ++ _rtw_memcpy(&val, ptmpbuf+shift, 4); ++ val = le32_to_cpu(val); ++ ++ rtw_mfree(ptmpbuf, 8); ++ } ++ ++_func_exit_; ++ ++ return val; ++} ++ ++u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ PADAPTER padapter; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ u32 val; ++ s32 err; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = sd_cmd52_read(pintfhdl, ftaddr, 4, (u8*)&val); ++#ifdef SDIO_DEBUG_IO ++ if (!err) { ++#endif ++ val = le32_to_cpu(val); ++ return val; ++#ifdef SDIO_DEBUG_IO ++ } ++ ++ DBG_871X(KERN_ERR "%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n", __func__, err, addr); ++ return SDIO_ERR_VAL32; ++#endif ++ } ++ ++ // 4 bytes alignment ++ shift = ftaddr & 0x3; ++ if (shift == 0) { ++ val = sd_read32(pintfhdl, ftaddr, NULL); ++ } else { ++ u8 *ptmpbuf; ++ ++ ptmpbuf = (u8*)rtw_malloc(8); ++ if (NULL == ptmpbuf) { ++ DBG_871X(KERN_ERR "%s: Allocate memory FAIL!(size=8) addr=0x%x\n", __func__, addr); ++ return SDIO_ERR_VAL32; ++ } ++ ++ ftaddr &= ~(u16)0x3; ++ sd_read(pintfhdl, ftaddr, 8, ptmpbuf); ++ _rtw_memcpy(&val, ptmpbuf+shift, 4); ++ val = le32_to_cpu(val); ++ ++ rtw_mfree(ptmpbuf, 8); ++ } ++ ++_func_exit_; ++ ++ return val; ++} ++ ++s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf) ++{ ++ PADAPTER padapter; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ s32 err; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ err = 0; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = sd_cmd52_read(pintfhdl, ftaddr, cnt, pbuf); ++ return err; ++ } ++ ++ // 4 bytes alignment ++ shift = ftaddr & 0x3; ++ if (shift == 0) { ++ err = sd_read(pintfhdl, ftaddr, cnt, pbuf); ++ } else { ++ u8 *ptmpbuf; ++ u32 n; ++ ++ ftaddr &= ~(u16)0x3; ++ n = cnt + shift; ++ ptmpbuf = rtw_malloc(n); ++ if (NULL == ptmpbuf) return -1; ++ err = sd_read(pintfhdl, ftaddr, n, ptmpbuf); ++ if (!err) ++ _rtw_memcpy(pbuf, ptmpbuf+shift, cnt); ++ rtw_mfree(ptmpbuf, n); ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++s32 sdio_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ++{ ++ u32 ftaddr; ++ s32 err; ++ ++_func_enter_; ++ ftaddr = _cvrt2ftaddr(addr, NULL, NULL); ++ sd_write8(pintfhdl, ftaddr, val, &err); ++ ++_func_exit_; ++ ++ return err; ++} ++ ++s32 sdio_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ++{ ++ u32 ftaddr; ++ u8 shift; ++ s32 err; ++ ++_func_enter_; ++ ftaddr = _cvrt2ftaddr(addr, NULL, NULL); ++ val = cpu_to_le16(val); ++ err = sd_cmd52_write(pintfhdl, ftaddr, 2, (u8*)&val); ++ ++_func_exit_; ++ ++ return err; ++} ++ ++s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val) ++{ ++ //PADAPTER padapter; ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ s32 err; ++ ++_func_enter_; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ err = 0; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ val = cpu_to_le32(val); ++ err = _sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); ++ return err; ++ } ++ ++ // 4 bytes alignment ++ shift = ftaddr & 0x3; ++#if 1 ++ if (shift == 0) ++ { ++ _sd_write32(pintfhdl, ftaddr, val, &err); ++ } ++ else ++ { ++ val = cpu_to_le32(val); ++ err = _sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); ++ } ++#else ++ if (shift == 0) { ++ sd_write32(pintfhdl, ftaddr, val, &err); ++ } else { ++ u8 *ptmpbuf; ++ ++ ptmpbuf = (u8*)rtw_malloc(8); ++ if (NULL == ptmpbuf) return (-1); ++ ++ ftaddr &= ~(u16)0x3; ++ err = sd_read(pintfhdl, ftaddr, 8, ptmpbuf); ++ if (err) { ++ rtw_mfree(ptmpbuf, 8); ++ return err; ++ } ++ val = cpu_to_le32(val); ++ _rtw_memcpy(ptmpbuf+shift, &val, 4); ++ err = sd_write(pintfhdl, ftaddr, 8, ptmpbuf); ++ ++ rtw_mfree(ptmpbuf, 8); ++ } ++#endif ++ ++_func_exit_; ++ ++ return err; ++} ++ ++ ++s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ++{ ++ PADAPTER padapter; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ s32 err; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ err = 0; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ val = cpu_to_le32(val); ++ err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); ++ return err; ++ } ++ ++ // 4 bytes alignment ++ shift = ftaddr & 0x3; ++#if 1 ++ if (shift == 0) ++ { ++ sd_write32(pintfhdl, ftaddr, val, &err); ++ } ++ else ++ { ++ val = cpu_to_le32(val); ++ err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); ++ } ++#else ++ if (shift == 0) { ++ sd_write32(pintfhdl, ftaddr, val, &err); ++ } else { ++ u8 *ptmpbuf; ++ ++ ptmpbuf = (u8*)rtw_malloc(8); ++ if (NULL == ptmpbuf) return (-1); ++ ++ ftaddr &= ~(u16)0x3; ++ err = sd_read(pintfhdl, ftaddr, 8, ptmpbuf); ++ if (err) { ++ rtw_mfree(ptmpbuf, 8); ++ return err; ++ } ++ val = cpu_to_le32(val); ++ _rtw_memcpy(ptmpbuf+shift, &val, 4); ++ err = sd_write(pintfhdl, ftaddr, 8, ptmpbuf); ++ ++ rtw_mfree(ptmpbuf, 8); ++ } ++#endif ++ ++_func_exit_; ++ ++ return err; ++} ++ ++s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf) ++{ ++ PADAPTER padapter; ++ u8 bMacPwrCtrlOn; ++ u8 deviceId; ++ u16 offset; ++ u32 ftaddr; ++ u8 shift; ++ s32 err; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ err = 0; ++ ++ ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) ++ || (_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = sd_cmd52_write(pintfhdl, ftaddr, cnt, pbuf); ++ return err; ++ } ++ ++ shift = ftaddr & 0x3; ++ if (shift == 0) { ++ err = sd_write(pintfhdl, ftaddr, cnt, pbuf); ++ } else { ++ u8 *ptmpbuf; ++ u32 n; ++ ++ ftaddr &= ~(u16)0x3; ++ n = cnt + shift; ++ ptmpbuf = rtw_malloc(n); ++ if (NULL == ptmpbuf) return -1; ++ err = sd_read(pintfhdl, ftaddr, 4, ptmpbuf); ++ if (err) { ++ rtw_mfree(ptmpbuf, n); ++ return err; ++ } ++ _rtw_memcpy(ptmpbuf+shift, pbuf, cnt); ++ err = sd_write(pintfhdl, ftaddr, n, ptmpbuf); ++ rtw_mfree(ptmpbuf, n); ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++void sdio_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ s32 err; ++ ++_func_enter_; ++ ++ err = sdio_readN(pintfhdl, addr, cnt, rmem); ++ ++_func_exit_; ++} ++ ++void sdio_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++_func_enter_; ++ ++ sdio_writeN(pintfhdl, addr, cnt, wmem); ++ ++_func_exit_; ++} ++ ++/* ++ * Description: ++ * Read from RX FIFO ++ * Round read size to block size, ++ * and make sure data transfer will be done in one command. ++ * ++ * Parameters: ++ * pintfhdl a pointer of intf_hdl ++ * addr port ID ++ * cnt size to read ++ * rmem address to put data ++ * ++ * Return: ++ * _SUCCESS(1) Success ++ * _FAIL(0) Fail ++ */ ++static u32 sdio_read_port( ++ struct intf_hdl *pintfhdl, ++ u32 addr, ++ u32 cnt, ++ u8 *mem) ++{ ++ PADAPTER padapter = pintfhdl->padapter; ++ PSDIO_DATA psdio= &adapter_to_dvobj(padapter)->intf_data; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ s32 err; ++ ++ HalSdioGetCmdAddr8723ASdio(padapter, addr, pHalData->SdioRxFIFOCnt++, &addr); ++ ++ ++ cnt = _RND4(cnt); ++ if (cnt > psdio->block_transfer_len) ++ cnt = _RND(cnt, psdio->block_transfer_len); ++ ++// cnt = sdio_align_size(cnt); ++ ++ err = _sd_read(pintfhdl, addr, cnt, mem); ++ //err = sd_read(pintfhdl, addr, cnt, mem); ++ ++ ++ ++ if (err) return _FAIL; ++ return _SUCCESS; ++} ++ ++/* ++ * Description: ++ * Write to TX FIFO ++ * Align write size block size, ++ * and make sure data could be written in one command. ++ * ++ * Parameters: ++ * pintfhdl a pointer of intf_hdl ++ * addr port ID ++ * cnt size to write ++ * wmem data pointer to write ++ * ++ * Return: ++ * _SUCCESS(1) Success ++ * _FAIL(0) Fail ++ */ ++static u32 sdio_write_port( ++ struct intf_hdl *pintfhdl, ++ u32 addr, ++ u32 cnt, ++ u8 *mem) ++{ ++ PADAPTER padapter; ++ PSDIO_DATA psdio; ++ s32 err; ++ struct xmit_buf *xmitbuf = (struct xmit_buf *)mem; ++ ++ padapter = pintfhdl->padapter; ++ psdio = &adapter_to_dvobj(padapter)->intf_data; ++ ++ if(padapter->hw_init_completed == _FALSE) ++ { ++ DBG_871X("%s [addr=0x%x cnt=%d] padapter->hw_init_completed == _FALSE \n",__func__,addr,cnt); ++ return _FAIL; ++ } ++ ++ cnt = _RND4(cnt); ++ HalSdioGetCmdAddr8723ASdio(padapter, addr, cnt >> 2, &addr); ++ ++ if (cnt > psdio->block_transfer_len) ++ cnt = _RND(cnt, psdio->block_transfer_len); ++// cnt = sdio_align_size(cnt); ++ ++ err = sd_write(pintfhdl, addr, cnt, xmitbuf->pdata); ++ ++ rtw_sctx_done_err(&xmitbuf->sctx, ++ err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); ++ ++ if (err) ++ { ++ DBG_871X("%s, error=%d\n", __func__, err); ++ ++ return _FAIL; ++ } ++ return _SUCCESS; ++} ++ ++void sdio_set_intf_ops(struct _io_ops *pops) ++{ ++_func_enter_; ++ ++ pops->_read8 = &sdio_read8; ++ pops->_read16 = &sdio_read16; ++ pops->_read32 = &sdio_read32; ++ pops->_read_mem = &sdio_read_mem; ++ pops->_read_port = &sdio_read_port; ++ ++ pops->_write8 = &sdio_write8; ++ pops->_write16 = &sdio_write16; ++ pops->_write32 = &sdio_write32; ++ pops->_writeN = &sdio_writeN; ++ pops->_write_mem = &sdio_write_mem; ++ pops->_write_port = &sdio_write_port; ++ ++_func_exit_; ++} ++ ++/* ++ * Todo: align address to 4 bytes. ++ */ ++s32 _sdio_local_read( ++ PADAPTER padapter, ++ u32 addr, ++ u32 cnt, ++ u8 *pbuf) ++{ ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ s32 err; ++ u8 *ptmpbuf; ++ u32 n; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if ((_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++// || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = _sd_cmd52_read(pintfhdl, addr, cnt, pbuf); ++ return err; ++ } ++ ++ n = RND4(cnt); ++ ptmpbuf = (u8*)rtw_malloc(n); ++ if(!ptmpbuf) ++ return (-1); ++ ++ err = _sd_read(pintfhdl, addr, n, ptmpbuf); ++ if (!err) ++ _rtw_memcpy(pbuf, ptmpbuf, cnt); ++ ++ if(ptmpbuf) ++ rtw_mfree(ptmpbuf, n); ++ ++ return err; ++} ++ ++/* ++ * Todo: align address to 4 bytes. ++ */ ++s32 sdio_local_read( ++ PADAPTER padapter, ++ u32 addr, ++ u32 cnt, ++ u8 *pbuf) ++{ ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ s32 err; ++ u8 *ptmpbuf; ++ u32 n; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if ((_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = sd_cmd52_read(pintfhdl, addr, cnt, pbuf); ++ return err; ++ } ++ ++ n = RND4(cnt); ++ ptmpbuf = (u8*)rtw_malloc(n); ++ if(!ptmpbuf) ++ return (-1); ++ ++ err = sd_read(pintfhdl, addr, n, ptmpbuf); ++ if (!err) ++ _rtw_memcpy(pbuf, ptmpbuf, cnt); ++ ++ if(ptmpbuf) ++ rtw_mfree(ptmpbuf, n); ++ ++ return err; ++} ++ ++/* ++ * Todo: align address to 4 bytes. ++ */ ++s32 _sdio_local_write( ++ PADAPTER padapter, ++ u32 addr, ++ u32 cnt, ++ u8 *pbuf) ++{ ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ s32 err; ++ u8 *ptmpbuf; ++ ++ if(addr & 0x3) ++ DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__); ++ ++ if(cnt & 0x3) ++ DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if ((_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++// || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = _sd_cmd52_write(pintfhdl, addr, cnt, pbuf); ++ return err; ++ } ++ ++ ptmpbuf = (u8*)rtw_malloc(cnt); ++ if(!ptmpbuf) ++ return (-1); ++ ++ _rtw_memcpy(ptmpbuf, pbuf, cnt); ++ ++ err = _sd_write(pintfhdl, addr, cnt, ptmpbuf); ++ ++ if (ptmpbuf) ++ rtw_mfree(ptmpbuf, cnt); ++ ++ return err; ++} ++ ++/* ++ * Todo: align address to 4 bytes. ++ */ ++s32 sdio_local_write( ++ PADAPTER padapter, ++ u32 addr, ++ u32 cnt, ++ u8 *pbuf) ++{ ++ ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ s32 err; ++ u8 *ptmpbuf; ++ ++ if(addr & 0x3) ++ DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__); ++ ++ if(cnt & 0x3) ++ DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if ((_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ err = sd_cmd52_write(pintfhdl, addr, cnt, pbuf); ++ return err; ++ } ++ ++ ptmpbuf = (u8*)rtw_malloc(cnt); ++ if(!ptmpbuf) ++ return (-1); ++ ++ _rtw_memcpy(ptmpbuf, pbuf, cnt); ++ ++ err = sd_write(pintfhdl, addr, cnt, ptmpbuf); ++ ++ if (ptmpbuf) ++ rtw_mfree(ptmpbuf, cnt); ++ ++ return err; ++} ++ ++u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr) ++{ ++ struct intf_hdl * pintfhdl; ++ u8 val = 0; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ sd_cmd52_read(pintfhdl, addr, 1, &val); ++ ++ return val; ++} ++ ++u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr) ++{ ++ struct intf_hdl * pintfhdl; ++ u16 val = 0; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ sd_cmd52_read(pintfhdl, addr, 2, (u8*)&val); ++ ++ val = le16_to_cpu(val); ++ ++ return val; ++} ++ ++u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr) ++{ ++ struct intf_hdl * pintfhdl; ++ u32 val = 0; ++ ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ sd_cmd52_read(pintfhdl, addr, 4, (u8*)&val); ++ ++ val = le32_to_cpu(val); ++ ++ return val; ++} ++ ++u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr) ++{ ++ struct intf_hdl * pintfhdl; ++ u8 bMacPwrCtrlOn; ++ u32 val=0; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if ((_FALSE == bMacPwrCtrlOn) ++#ifdef CONFIG_LPS_LCLK ++ || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) ++#endif ++ ) ++ { ++ sd_cmd52_read(pintfhdl, addr, 4, (u8*)&val); ++ val = le32_to_cpu(val); ++ } ++ else ++ val = sd_read32(pintfhdl, addr, NULL); ++ ++ return val; ++} ++ ++void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v) ++{ ++ struct intf_hdl * pintfhdl; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ sd_cmd52_write(pintfhdl, addr, 1, &v); ++} ++ ++void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v) ++{ ++ struct intf_hdl * pintfhdl; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ v = cpu_to_le16(v); ++ sd_cmd52_write(pintfhdl, addr, 2, (u8*)&v); ++} ++ ++void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v) ++{ ++ struct intf_hdl * pintfhdl; ++ ++ pintfhdl=&padapter->iopriv.intf; ++ HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); ++ v = cpu_to_le32(v); ++ sd_cmd52_write(pintfhdl, addr, 4, (u8*)&v); ++} ++ ++#if 0 ++void ++DumpLoggedInterruptHistory8723Sdio( ++ PADAPTER padapter ++) ++{ ++ HAL_DATA_TYPE *pHalData=GET_HAL_DATA(padapter); ++ u4Byte DebugLevel = DBG_LOUD; ++ ++ if (DBG_Var.DbgPrintIsr == 0) ++ return; ++ ++ DBG_ChkDrvResource(padapter); ++ ++ ++ if(pHalData->InterruptLog.nISR_RX_REQUEST) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RX_REQUEST[%ld]\t\n", pHalData->InterruptLog.nISR_RX_REQUEST)); ++ ++ if(pHalData->InterruptLog.nISR_AVAL) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# AVAL[%ld]\t\n", pHalData->InterruptLog.nISR_AVAL)); ++ ++ if(pHalData->InterruptLog.nISR_TXERR) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXERR[%ld]\t\n", pHalData->InterruptLog.nISR_TXERR)); ++ ++ if(pHalData->InterruptLog.nISR_RXERR) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RXERR[%ld]\t\n", pHalData->InterruptLog.nISR_RXERR)); ++ ++ if(pHalData->InterruptLog.nISR_TXFOVW) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXFOVW[%ld]\t\n", pHalData->InterruptLog.nISR_TXFOVW)); ++ ++ if(pHalData->InterruptLog.nISR_RXFOVW) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RXFOVW[%ld]\t\n", pHalData->InterruptLog.nISR_RXFOVW)); ++ ++ if(pHalData->InterruptLog.nISR_TXBCNOK) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXBCNOK[%ld]\t\n", pHalData->InterruptLog.nISR_TXBCNOK)); ++ ++ if(pHalData->InterruptLog.nISR_TXBCNERR) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXBCNERR[%ld]\t\n", pHalData->InterruptLog.nISR_TXBCNERR)); ++ ++ if(pHalData->InterruptLog.nISR_BCNERLY_INT) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# BCNERLY_INT[%ld]\t\n", pHalData->InterruptLog.nISR_BCNERLY_INT)); ++ ++ if(pHalData->InterruptLog.nISR_C2HCMD) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# C2HCMD[%ld]\t\n", pHalData->InterruptLog.nISR_C2HCMD)); ++ ++ if(pHalData->InterruptLog.nISR_CPWM1) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CPWM1L[%ld]\t\n", pHalData->InterruptLog.nISR_CPWM1)); ++ ++ if(pHalData->InterruptLog.nISR_CPWM2) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CPWM2[%ld]\t\n", pHalData->InterruptLog.nISR_CPWM2)); ++ ++ if(pHalData->InterruptLog.nISR_HSISR_IND) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# HSISR_IND[%ld]\t\n", pHalData->InterruptLog.nISR_HSISR_IND)); ++ ++ if(pHalData->InterruptLog.nISR_GTINT3_IND) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# GTINT3_IND[%ld]\t\n", pHalData->InterruptLog.nISR_GTINT3_IND)); ++ ++ if(pHalData->InterruptLog.nISR_GTINT4_IND) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# GTINT4_IND[%ld]\t\n", pHalData->InterruptLog.nISR_GTINT4_IND)); ++ ++ if(pHalData->InterruptLog.nISR_PSTIMEOUT) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# PSTIMEOUT[%ld]\t\n", pHalData->InterruptLog.nISR_PSTIMEOUT)); ++ ++ if(pHalData->InterruptLog.nISR_OCPINT) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# OCPINT[%ld]\t\n", pHalData->InterruptLog.nISR_OCPINT)); ++ ++ if(pHalData->InterruptLog.nISR_ATIMEND) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# ATIMEND[%ld]\t\n", pHalData->InterruptLog.nISR_ATIMEND)); ++ ++ if(pHalData->InterruptLog.nISR_ATIMEND_E) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# ATIMEND_E[%ld]\t\n", pHalData->InterruptLog.nISR_ATIMEND_E)); ++ ++ if(pHalData->InterruptLog.nISR_CTWEND) ++ RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CTWEND[%ld]\t\n", pHalData->InterruptLog.nISR_CTWEND)); ++} ++ ++void ++LogInterruptHistory8723Sdio( ++ PADAPTER padapter, ++ PRT_ISR_CONTENT pIsrContent ++) ++{ ++ HAL_DATA_TYPE *pHalData=GET_HAL_DATA(padapter); ++ ++ if((pHalData->IntrMask[0] & SDIO_HIMR_RX_REQUEST_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_RX_REQUEST)) ++ pHalData->InterruptLog.nISR_RX_REQUEST ++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_AVAL_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_AVAL)) ++ pHalData->InterruptLog.nISR_AVAL++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_TXERR_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_TXERR)) ++ pHalData->InterruptLog.nISR_TXERR++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_RXERR_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_RXERR)) ++ pHalData->InterruptLog.nISR_RXERR++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_TXFOVW_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_TXFOVW)) ++ pHalData->InterruptLog.nISR_TXFOVW++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_RXFOVW_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_RXFOVW)) ++ pHalData->InterruptLog.nISR_RXFOVW++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNOK_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNOK)) ++ pHalData->InterruptLog.nISR_TXBCNOK++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNERR_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNERR)) ++ pHalData->InterruptLog.nISR_TXBCNERR++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_BCNERLY_INT_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_BCNERLY_INT)) ++ pHalData->InterruptLog.nISR_BCNERLY_INT ++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_C2HCMD_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_C2HCMD)) ++ pHalData->InterruptLog.nISR_C2HCMD++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_CPWM1_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_CPWM1)) ++ pHalData->InterruptLog.nISR_CPWM1++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_CPWM2_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_CPWM2)) ++ pHalData->InterruptLog.nISR_CPWM2++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_HSISR_IND_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_HSISR_IND)) ++ pHalData->InterruptLog.nISR_HSISR_IND++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_GTINT3_IND_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_GTINT3_IND)) ++ pHalData->InterruptLog.nISR_GTINT3_IND++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_GTINT4_IND_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_GTINT4_IND)) ++ pHalData->InterruptLog.nISR_GTINT4_IND++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_PSTIMEOUT_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_PSTIMEOUT)) ++ pHalData->InterruptLog.nISR_PSTIMEOUT++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_OCPINT_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_OCPINT)) ++ pHalData->InterruptLog.nISR_OCPINT++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND)) ++ pHalData->InterruptLog.nISR_ATIMEND++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_E_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND_E)) ++ pHalData->InterruptLog.nISR_ATIMEND_E++; ++ if((pHalData->IntrMask[0] & SDIO_HIMR_CTWEND_MSK) && ++ (pIsrContent->IntArray[0] & SDIO_HISR_CTWEND)) ++ pHalData->InterruptLog.nISR_CTWEND++; ++ ++} ++ ++void ++DumpHardwareProfile8723Sdio( ++ IN PADAPTER padapter ++) ++{ ++ DumpLoggedInterruptHistory8723Sdio(padapter); ++} ++#endif ++ ++#ifdef CONFIG_USING_CMD52_READ_INT ++static s32 ReadInterrupt8188ESdio(PADAPTER padapter, u32 *phisr) ++{ ++ u8 val8, hisr_len; ++ u32 hisr, himr; ++ ++ ++ if (phisr == NULL) ++ return _FALSE; ++ ++ himr = GET_HAL_DATA(padapter)->sdio_himr; ++ ++ // decide how many bytes need to be read ++ hisr_len = 0; ++ while (himr) ++ { ++ hisr_len++; ++ himr >>= 8; ++ } ++ ++ hisr = 0; ++ ++ while (hisr_len != 0) ++ { ++ hisr_len--; ++ val8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR+hisr_len); ++ hisr |= (val8 << (8*hisr_len)); ++ } ++ ++ *phisr = hisr; ++ ++ return _TRUE; ++} ++#endif ++ ++// ++// Description: ++// Initialize SDIO Host Interrupt Mask configuration variables for future use. ++// ++// Assumption: ++// Using SDIO Local register ONLY for configuration. ++// ++// Created by Roger, 2011.02.11. ++// ++void InitInterrupt8188ESdio(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ pHalData->sdio_himr = (u32)( \ ++ SDIO_HIMR_RX_REQUEST_MSK | ++// SDIO_HIMR_AVAL_MSK | ++// SDIO_HIMR_TXERR_MSK | ++// SDIO_HIMR_RXERR_MSK | ++// SDIO_HIMR_TXFOVW_MSK | ++// SDIO_HIMR_RXFOVW_MSK | ++// SDIO_HIMR_TXBCNOK_MSK | ++// SDIO_HIMR_TXBCNERR_MSK | ++#ifdef CONFIG_EXT_CLK ++//for sprd ++ SDIO_HIMR_BCNERLY_INT_MSK | ++#endif //CONFIG_EXT_CLK ++// SDIO_HIMR_C2HCMD_MSK | ++#if defined(CONFIG_LPS_LCLK) && (!defined(CONFIG_DETECT_CPWM_BY_POLLING)) ++ SDIO_HIMR_CPWM1_MSK | ++ SDIO_HIMR_CPWM2_MSK | ++#endif ++// SDIO_HIMR_HSISR_IND_MSK | ++// SDIO_HIMR_GTINT3_IND_MSK | ++// SDIO_HIMR_GTINT4_IND_MSK | ++// SDIO_HIMR_PSTIMEOUT_MSK | ++// SDIO_HIMR_OCPINT_MSK | ++// SDIO_HIMR_ATIMEND_MSK | ++// SDIO_HIMR_ATIMEND_E_MSK | ++// SDIO_HIMR_CTWEND_MSK | ++ 0); ++} ++ ++// ++// Description: ++// Clear corresponding SDIO Host ISR interrupt service. ++// ++// Assumption: ++// Using SDIO Local register ONLY for configuration. ++// ++// Created by Roger, 2011.02.11. ++// ++void ClearInterrupt8723ASdio(PADAPTER padapter) ++{ ++ u32 tmp = 0; ++ tmp = SdioLocalCmd52Read4Byte(padapter, SDIO_REG_HISR); ++ SdioLocalCmd52Write4Byte(padapter, SDIO_REG_HISR, tmp); ++// padapter->IsrContent.IntArray[0] = 0; ++ padapter->IsrContent = 0; ++} ++ ++// ++// Description: ++// Enalbe SDIO Host Interrupt Mask configuration on SDIO local domain. ++// ++// Assumption: ++// 1. Using SDIO Local register ONLY for configuration. ++// 2. PASSIVE LEVEL ++// ++// Created by Roger, 2011.02.11. ++// ++void EnableInterrupt8188ESdio(PADAPTER padapter) ++{ ++ PHAL_DATA_TYPE pHalData; ++ u32 himr; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){ ++ padapter = padapter->pbuddy_adapter; ++ } ++#endif ++ pHalData = GET_HAL_DATA(padapter); ++ himr = cpu_to_le32(pHalData->sdio_himr); ++ sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8*)&himr); ++ ++ ++ // ++ // There are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM. ++ // So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore. ++ // 2011.10.19. ++ // ++ rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); ++ ++} ++ ++// ++// Description: ++// Disable SDIO Host IMR configuration to mask unnecessary interrupt service. ++// ++// Assumption: ++// Using SDIO Local register ONLY for configuration. ++// ++// Created by Roger, 2011.02.11. ++// ++void DisableInterrupt8188ESdio(PADAPTER padapter) ++{ ++ u32 himr; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){ ++ padapter = padapter->pbuddy_adapter; ++ } ++#endif ++ himr = cpu_to_le32(SDIO_HIMR_DISABLED); ++ sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8*)&himr); ++ ++} ++ ++// ++// Description: ++// Update SDIO Host Interrupt Mask configuration on SDIO local domain. ++// ++// Assumption: ++// 1. Using SDIO Local register ONLY for configuration. ++// 2. PASSIVE LEVEL ++// ++// Created by Roger, 2011.02.11. ++// ++void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR) ++{ ++ HAL_DATA_TYPE *pHalData; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){ ++ padapter = padapter->pbuddy_adapter; ++ } ++#endif ++ pHalData = GET_HAL_DATA(padapter); ++ ++ if (AddMSR) ++ pHalData->sdio_himr |= AddMSR; ++ ++ if (RemoveMSR) ++ pHalData->sdio_himr &= (~RemoveMSR); ++ ++ DisableInterrupt8188ESdio(padapter); ++ EnableInterrupt8188ESdio(padapter); ++} ++ ++#ifdef CONFIG_WOWLAN ++void ClearInterrupt8189ESdio(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u32 v32 = 0; ++ ++ v32 = pHalData->sdio_himr | SDIO_HISR_CPWM2; ++ ++ pHalData->sdio_hisr &= v32; ++ ++ // clear HISR ++ v32 = pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR; ++ if (v32) { ++ v32 = cpu_to_le32(v32); ++ sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8*)&v32); ++ } ++} ++#endif ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++static void sd_recv_loopback(PADAPTER padapter, u32 size) ++{ ++ PLOOPBACKDATA ploopback; ++ u32 readsize, allocsize; ++ u8 *preadbuf; ++ ++ ++ readsize = size; ++ DBG_8192C("%s: read size=%d\n", __func__, readsize); ++ allocsize = _RND(readsize, adapter_to_dvobj(padapter)->intf_data.block_transfer_len); ++ ++ ploopback = padapter->ploopback; ++ if (ploopback) { ++ ploopback->rxsize = readsize; ++ preadbuf = ploopback->rxbuf; ++ } ++ else { ++ preadbuf = rtw_malloc(allocsize); ++ if (preadbuf == NULL) { ++ DBG_8192C("%s: malloc fail size=%d\n", __func__, allocsize); ++ return; ++ } ++ } ++ ++// rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ ++ if (ploopback) ++ _rtw_up_sema(&ploopback->sema); ++ else { ++ u32 i; ++ ++ DBG_8192C("%s: drop pkt\n", __func__); ++ for (i = 0; i < readsize; i+=4) { ++ DBG_8192C("%08X", *(u32*)(preadbuf + i)); ++ if ((i+4) & 0x1F) printk(" "); ++ else printk("\n"); ++ } ++ printk("\n"); ++ rtw_mfree(preadbuf, allocsize); ++ } ++} ++#endif // CONFIG_MAC_LOOPBACK_DRIVER ++ ++#ifdef CONFIG_SDIO_RX_COPY ++static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) ++{ ++ u32 readsize, ret; ++ u8 *preadbuf; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ ++ ++ readsize = size; ++ ++ //3 1. alloc recvbuf ++ precvpriv = &padapter->recvpriv; ++ precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue); ++ if (precvbuf == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc recvbuf FAIL!\n", __FUNCTION__)); ++ return NULL; ++ } ++ ++ //3 2. alloc skb ++ if (precvbuf->pskb == NULL) { ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ ++ DBG_871X("%s: alloc_skb for rx buffer\n", __FUNCTION__); ++ ++ precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++ ++ if(precvbuf->pskb) ++ { ++ precvbuf->pskb->dev = padapter->pnetdev; ++ ++ tmpaddr = (SIZE_PTR)precvbuf->pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); ++ precvbuf->pend = skb_end_pointer(precvbuf->pskb); ++ precvbuf->len = 0; ++ } ++ ++ if (precvbuf->pskb == NULL) { ++ DBG_871X("%s: alloc_skb fail! read=%d\n", __FUNCTION__, readsize); ++ return NULL; ++ } ++ } ++ ++ //3 3. read data from rxfifo ++ preadbuf = precvbuf->pdata; ++// rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ if (ret == _FAIL) { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n", __FUNCTION__)); ++ return NULL; ++ } ++ ++ ++ //3 4. init recvbuf ++ precvbuf->len = readsize; ++ ++ return precvbuf; ++} ++#else ++static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) ++{ ++ u32 readsize, allocsize, ret; ++ u8 *preadbuf; ++ _pkt *ppkt; ++ struct recv_priv *precvpriv; ++ struct recv_buf *precvbuf; ++ ++ ++ readsize = size; ++ ++ //3 1. alloc skb ++ // align to block size ++ allocsize = _RND(readsize, adapter_to_dvobj(padapter)->intf_data.block_transfer_len); ++ ++ ppkt = rtw_skb_alloc(allocsize); ++ ++ if (ppkt == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc_skb fail! alloc=%d read=%d\n", __FUNCTION__, allocsize, readsize)); ++ return NULL; ++ } ++ ++ //3 2. read data from rxfifo ++ preadbuf = skb_put(ppkt, readsize); ++// rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ++ if (ret == _FAIL) { ++ rtw_skb_free(ppkt); ++ RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n", __FUNCTION__)); ++ return NULL; ++ } ++ ++ //3 3. alloc recvbuf ++ precvpriv = &padapter->recvpriv; ++ precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue); ++ if (precvbuf == NULL) { ++ rtw_skb_free(ppkt); ++ RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc recvbuf FAIL!\n", __FUNCTION__)); ++ return NULL; ++ } ++ ++ //3 4. init recvbuf ++ precvbuf->pskb = ppkt; ++ ++ precvbuf->len = ppkt->len; ++ ++ precvbuf->phead = ppkt->head; ++ precvbuf->pdata = ppkt->data; ++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); ++ precvbuf->pend = skb_end_pointer(precvbuf->pskb); ++ ++ return precvbuf; ++} ++#endif ++ ++static void sd_rxhandler(PADAPTER padapter, struct recv_buf *precvbuf) ++{ ++ struct recv_priv *precvpriv; ++ _queue *ppending_queue; ++ ++ ++ precvpriv = &padapter->recvpriv; ++ ppending_queue = &precvpriv->recv_buf_pending_queue; ++ ++ //3 1. enqueue recvbuf ++ rtw_enqueue_recvbuf(precvbuf, ppending_queue); ++ ++ //3 2. schedule tasklet ++#ifdef PLATFORM_LINUX ++ tasklet_schedule(&precvpriv->recv_tasklet); ++#endif ++} ++ ++void sd_int_dpc(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct intf_hdl * pintfhdl=&padapter->iopriv.intf; ++ if (pHalData->sdio_hisr & SDIO_HISR_CPWM1) ++ { ++ struct reportpwrstate_parm report; ++ ++#ifdef CONFIG_LPS_RPWM_TIMER ++ u8 bcancelled; ++ _cancel_timer(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer), &bcancelled); ++#endif // CONFIG_LPS_RPWM_TIMER ++ ++#ifdef CONFIG_USING_CMD52_READ_INT ++ report.state = SdioLocalCmd52Read1Byte(padapter,SDIO_REG_HCPWM1); ++#else //CONFIG_USING_CMD52_READ_INT ++ _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); ++#endif ++ ++#ifdef CONFIG_LPS_LCLK ++ //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. ++ //modify by Thomas. 2012/4/2. ++ ++#ifdef CONFIG_EXT_CLK //for sprd ++ if(report.state & BIT(4)) //indicate FW entering 32k ++ { ++ u8 chk_cnt = 0; ++ ++ do{ ++ if(_sdio_read8(padapter, 0x90)&BIT(0))//FW in 32k already ++ { ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ ++ if(pwrpriv->rpwm < PS_STATE_S2) ++ { ++ //DBG_871X("disable ext clk when FW in LPS-32K already!\n"); ++ EnableGpio5ClockReq(padapter, _TRUE, 0); ++ } ++ ++ break; ++ } ++ ++ chk_cnt++; ++ ++ }while(chk_cnt<10); ++ ++ if(chk_cnt==10) ++ { ++ DBG_871X("polling fw in 32k already, fail!\n"); ++ } ++ ++ } ++ else //indicate fw leaving 32K ++#endif //CONFIG_EXT_CLK ++ { ++ report.state |= PS_STATE_S2; ++ //cpwm_int_hdl(padapter, &report); ++ _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); ++ } ++#endif ++ } ++ ++#ifdef CONFIG_WOWLAN ++ if (pHalData->sdio_hisr & SDIO_HISR_CPWM2) { ++ u32 value; ++ value = rtw_read32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR); ++ DBG_871X_LEVEL(_drv_always_, "Reset SDIO HISR(0x%08x) original:0x%08x\n", ++ SDIO_LOCAL_BASE+SDIO_REG_HISR, value); ++ value |= BIT19; ++ rtw_write32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR, value); ++ ++ value = rtw_read8(padapter, SDIO_LOCAL_BASE+SDIO_REG_HIMR+2); ++ DBG_871X_LEVEL(_drv_always_, "Reset SDIO HIMR CPWM2(0x%08x) original:0x%02x\n", ++ SDIO_LOCAL_BASE+SDIO_REG_HIMR + 2, value); ++ } ++#endif ++ if (pHalData->sdio_hisr & SDIO_HISR_TXERR) ++ { ++ u8 *status; ++ u32 addr; ++ ++ status = rtw_malloc(4); ++ if (status) ++ { ++ addr = REG_TXDMA_STATUS; ++ HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); ++ _sd_read(pintfhdl, addr, 4, status); ++ _sd_write(pintfhdl, addr, 4, status); ++ DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); ++ rtw_mfree(status, 4); ++ } else { ++ DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); ++ } ++ } ++ ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) ++ #endif ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ if (pHalData->sdio_hisr & (SDIO_HISR_TXBCNOK|SDIO_HISR_TXBCNERR)) ++ #endif ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ #if 0 //for debug ++ if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) ++ DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__); ++ ++ if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK) ++ DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); ++ ++ if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR) ++ DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); ++ #endif ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ //send_beacon(padapter); ++ if(pmlmepriv->update_bcn == _TRUE) ++ { ++ //tx_beacon_hdl(padapter, NULL); ++ set_tx_beacon_cmd(padapter); ++ } ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ { ++ //send_beacon(padapter); ++ if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) ++ { ++ //tx_beacon_hdl(padapter, NULL); ++ set_tx_beacon_cmd(padapter->pbuddy_adapter); ++ } ++ } ++#endif ++ } ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++#ifdef CONFIG_EXT_CLK ++ if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ //DBG_8192C("BCNERLY_INT for enabling ext clk\n"); ++ EnableGpio5ClockReq(padapter, _TRUE, 1); ++ } ++ } ++#endif //CONFIG_EXT_CLK ++ ++ if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD) ++ { ++ DBG_8192C("%s: C2H Command\n", __func__); ++ } ++ ++ if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST) ++ { ++ struct recv_buf *precvbuf; ++#ifdef CONFIG_USING_CMD52_READ_INT ++ u32 hisr; ++ u8 data[4]; ++ ++ //DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); ++ pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++ sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); ++#else ++ _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); ++ pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); ++ ++ do { ++ //pHalData->SdioRxFIFOSize = SdioLocalCmd52Read2Byte(padapter, SDIO_REG_RX0_REQ_LEN); ++ ++ if(pHalData->SdioRxFIFOSize == 0){ ++ _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); ++ pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); ++ } ++ ++ if(pHalData->SdioRxFIFOSize != 0) ++ { ++ precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); ++ ++ pHalData->SdioRxFIFOSize = 0; ++ ++ if (precvbuf) ++ sd_rxhandler(padapter, precvbuf); ++ else ++ break; ++ } ++ else ++ { ++ //DBG_871X("%s, WARNING!!, SdioRxFIFOSize = 0!!\n", __func__); ++ break; ++ } ++ ++#ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP ++ } while (0); ++#else ++ } while (1); ++ ++#endif //CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP ++#endif //CONFIG_MAC_LOOPBACK_DRIVER ++#else //!CONFIG_USING_CMD52_READ_INT ++ ++ //DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); ++ pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++ sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); ++#else ++ do { ++ //Sometimes rx length will be zero. driver need to use cmd53 read again. ++ if(pHalData->SdioRxFIFOSize == 0) ++ { ++ u8 data[4]; ++ ++ _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); ++ ++ pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); ++ } ++ ++ if(pHalData->SdioRxFIFOSize) ++ { ++ precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); ++ ++ pHalData->SdioRxFIFOSize = 0; ++ ++ if (precvbuf) ++ sd_rxhandler(padapter, precvbuf); ++ else ++ break; ++ } ++ else{ ++ ++ break; ++ } ++#ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP ++ } while (0); ++#else ++ } while (1); ++#endif //CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP ++#endif //CONFIG_MAC_LOOPBACK_DRIVER ++#endif //CONFIG_USING_CMD52_READ_INT ++ } ++} ++ ++void sd_int_hdl(PADAPTER padapter) ++{ ++ u8 data[6]; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ if ((padapter->bDriverStopped == _TRUE) || ++ (padapter->bSurpriseRemoved == _TRUE)) ++ return; ++ ++#ifdef CONFIG_USING_CMD52_READ_INT ++ pHalData->sdio_hisr = 0; ++ //ReadInterrupt8188ESdio(padapter, &pHalData->sdio_hisr); ++ pHalData->sdio_hisr = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR); ++#else //CONFIG_USING_CMD52_READ_INT ++ _sdio_local_read(padapter, SDIO_REG_HISR, 6, data); ++ pHalData->sdio_hisr = le32_to_cpu(*(u32*)data); ++ pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)&data[4]); ++#endif ++ ++ if (pHalData->sdio_hisr & pHalData->sdio_himr) ++ { ++ u32 v32; ++ ++ pHalData->sdio_hisr &= pHalData->sdio_himr; ++ ++ // clear HISR ++ v32 = pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR; ++ if (v32) { ++#ifdef CONFIG_USING_CMD52_READ_INT ++ SdioLocalCmd52Write4Byte(padapter, SDIO_REG_HISR, v32); ++#else //CONFIG_USING_CMD52_READ_INT ++ v32 = cpu_to_le32(v32); ++ _sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8*)&v32); ++#endif ++ } ++ ++ sd_int_dpc(padapter); ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_c_, _drv_err_, ++ ("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n", ++ __FUNCTION__, pHalData->sdio_hisr, pHalData->sdio_himr)); ++ } ++ ++} ++ ++// ++// Description: ++// Query SDIO Local register to query current the number of Free TxPacketBuffer page. ++// ++// Assumption: ++// 1. Running at PASSIVE_LEVEL ++// 2. RT_TX_SPINLOCK is NOT acquired. ++// ++// Created by Roger, 2011.01.28. ++// ++u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u32 NumOfFreePage; ++// _irqL irql; ++ ++ ++ pHalData = GET_HAL_DATA(padapter); ++ ++ NumOfFreePage = SdioLocalCmd53Read4Byte(padapter, SDIO_REG_FREE_TXPG); ++ ++// _enter_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); ++ _rtw_memcpy(pHalData->SdioTxFIFOFreePage, &NumOfFreePage, 4); ++ RT_TRACE(_module_hci_ops_c_, _drv_notice_, ++ ("%s: Free page for HIQ(%#x),MIDQ(%#x),LOWQ(%#x),PUBQ(%#x)\n", ++ __FUNCTION__, ++ pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX], ++ pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); ++// _exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); ++ ++ return _TRUE; ++} ++ ++#ifdef CONFIG_WOWLAN ++u8 RecvOnePkt(PADAPTER padapter, u32 size) ++{ ++ struct recv_buf *precvbuf; ++ struct dvobj_priv *psddev; ++ PSDIO_DATA psdio_data; ++ struct sdio_func *func; ++ ++ u8 res = _FALSE; ++ ++ DBG_8192C("+%s: size: %d+\n", __func__, size); ++ ++ if (padapter == NULL) { ++ DBG_8192C(KERN_ERR "%s: padapter is NULL!\n", __func__); ++ return _FALSE; ++ } ++ ++ psddev = padapter->dvobj; ++ psdio_data = &psddev->intf_data; ++ func = psdio_data->func; ++ ++ if(size) { ++ sdio_claim_host(func); ++ precvbuf = sd_recv_rxfifo(padapter, size); ++ ++ if (precvbuf) { ++ //printk("Completed Recv One Pkt.\n"); ++ sd_rxhandler(padapter, precvbuf); ++ res = _TRUE; ++ }else{ ++ res = _FALSE; ++ } ++ sdio_release_host(func); ++ } ++ DBG_8192C("-%s-\n", __func__); ++ return res; ++} ++#endif //CONFIG_WOWLAN +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_led.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_led.c +new file mode 100644 +index 00000000..712965a8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_led.c +@@ -0,0 +1,170 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++#include ++#include ++#include ++ ++//================================================================================ ++// LED object. ++//================================================================================ ++ ++ ++//================================================================================ ++// Prototype of protected function. ++//================================================================================ ++ ++ ++//================================================================================ ++// LED_819xUsb routines. ++//================================================================================ ++ ++// ++// Description: ++// Turn on LED according to LedPin specified. ++// ++void ++SwLedOn( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ return; ++ } ++ ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2); ++ switch(pLed->LedPin) ++ { ++ case LED_PIN_LED0: ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on. ++ break; ++ ++ case LED_PIN_LED1: ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on. ++ break; ++ ++ default: ++ break; ++ } ++ ++ pLed->bLedOn = _TRUE; ++} ++ ++ ++// ++// Description: ++// Turn off LED according to LedPin specified. ++// ++void ++SwLedOff( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ goto exit; ++ } ++ ++ ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E ++ ++ switch(pLed->LedPin) ++ { ++ case LED_PIN_LED0: ++ if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED) ++ { ++ LedCfg &= 0x90; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); ++ LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG); ++ LedCfg &= 0xFE; ++ rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg); ++ } ++ else ++ { ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); ++ } ++ break; ++ ++ case LED_PIN_LED1: ++ LedCfg &= 0x0f; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); ++ break; ++ ++ default: ++ break; ++ } ++exit: ++ pLed->bLedOn = _FALSE; ++ ++} ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++ ++ ++//================================================================================ ++// Default LED behavior. ++//================================================================================ ++ ++// ++// Description: ++// Initialize all LED_871x objects. ++// ++void ++rtl8188eu_InitSwLeds( ++ _adapter *padapter ++ ) ++{ ++ struct led_priv *pledpriv = &(padapter->ledpriv); ++ ++ pledpriv->LedControlHandler = LedControl871x; ++ ++ InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); ++ ++ InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1); ++} ++ ++ ++// ++// Description: ++// DeInitialize all LED_819xUsb objects. ++// ++void ++rtl8188eu_DeInitSwLeds( ++ _adapter *padapter ++ ) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ DeInitLed871x( &(ledpriv->SwLed0) ); ++ DeInitLed871x( &(ledpriv->SwLed1) ); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_recv.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_recv.c +new file mode 100644 +index 00000000..db833e2b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_recv.c +@@ -0,0 +1,234 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188EU_RECV_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++ ++#include ++ ++ ++void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ ++ precvbuf->transfer_len = 0; ++ ++ precvbuf->len = 0; ++ ++ precvbuf->ref_cnt = 0; ++ ++ if(precvbuf->pbuf) ++ { ++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf; ++ precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ; ++ } ++ ++} ++ ++int rtl8188eu_init_recv_priv(_adapter *padapter) ++{ ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ int i, res = _SUCCESS; ++ struct recv_buf *precvbuf; ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ _rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed ++ _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed ++#endif ++ ++#ifdef PLATFORM_LINUX ++ tasklet_init(&precvpriv->recv_tasklet, ++ (void(*)(unsigned long))rtl8188eu_recv_tasklet, ++ (unsigned long)padapter); ++#endif ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++#ifdef PLATFORM_LINUX ++ precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL); ++ if(precvpriv->int_in_urb == NULL){ ++ res= _FAIL; ++ DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n"); ++ goto exit; ++ } ++#endif ++ precvpriv->int_in_buf = rtw_zmalloc(INTERRUPT_MSG_FORMAT_LEN); ++ if(precvpriv->int_in_buf == NULL){ ++ res= _FAIL; ++ DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n"); ++ goto exit; ++ } ++#endif ++ ++ //init recv_buf ++ _rtw_init_queue(&precvpriv->free_recv_buf_queue); ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ _rtw_init_queue(&precvpriv->recv_buf_pending_queue); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ if(precvpriv->pallocated_recv_buf==NULL){ ++ res= _FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n")); ++ goto exit; ++ } ++ _rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ ++ precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4); ++ //precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 - ++ // ((uint) (precvpriv->pallocated_recv_buf) &(4-1)); ++ ++ ++ precvbuf = (struct recv_buf*)precvpriv->precv_buf; ++ ++ for(i=0; i < NR_RECVBUFF ; i++) ++ { ++ _rtw_init_listhead(&precvbuf->list); ++ ++ _rtw_spinlock_init(&precvbuf->recvbuf_lock); ++ ++ precvbuf->alloc_sz = MAX_RECVBUF_SZ; ++ ++ res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf); ++ if(res==_FAIL) ++ break; ++ ++ precvbuf->ref_cnt = 0; ++ precvbuf->adapter =padapter; ++ ++ ++ //rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); ++ ++ precvbuf++; ++ ++ } ++ ++ precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF; ++ ++#ifdef PLATFORM_LINUX ++ ++ skb_queue_head_init(&precvpriv->rx_skb_queue); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ { ++ int i; ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ struct sk_buff *pskb=NULL; ++ ++ skb_queue_head_init(&precvpriv->free_recv_skb_queue); ++ ++ for(i=0; idev = padapter->pnetdev; ++ ++ tmpaddr = (SIZE_PTR)pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); ++ } ++ ++ pskb=NULL; ++ ++ } ++ } ++#endif ++ ++#endif ++ ++exit: ++ ++ return res; ++ ++} ++ ++void rtl8188eu_free_recv_priv (_adapter *padapter) ++{ ++ int i; ++ struct recv_buf *precvbuf; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ precvbuf = (struct recv_buf *)precvpriv->precv_buf; ++ ++ for(i=0; i < NR_RECVBUFF ; i++) ++ { ++ rtw_os_recvbuf_resource_free(padapter, precvbuf); ++ precvbuf++; ++ } ++ ++ if(precvpriv->pallocated_recv_buf) ++ rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++#ifdef PLATFORM_LINUX ++ if(precvpriv->int_in_urb) ++ { ++ usb_free_urb(precvpriv->int_in_urb); ++ } ++#endif//PLATFORM_LINUX ++ ++ if(precvpriv->int_in_buf) ++ rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN); ++#endif//CONFIG_USB_INTERRUPT_IN_PIPE ++ ++#ifdef PLATFORM_LINUX ++ ++ if (skb_queue_len(&precvpriv->rx_skb_queue)) { ++ DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n"); ++ } ++ ++ rtw_skb_queue_purge(&precvpriv->rx_skb_queue); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ ++ if (skb_queue_len(&precvpriv->free_recv_skb_queue)) { ++ DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue)); ++ } ++ ++ rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue); ++ ++#endif ++ ++#endif ++ ++} ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_xmit.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_xmit.c +new file mode 100644 +index 00000000..5a23b830 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/rtl8188eu_xmit.c +@@ -0,0 +1,1370 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8188E_XMIT_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++s32 rtl8188eu_init_xmit_priv(_adapter *padapter) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++#ifdef PLATFORM_LINUX ++ tasklet_init(&pxmitpriv->xmit_tasklet, ++ (void(*)(unsigned long))rtl8188eu_xmit_tasklet, ++ (unsigned long)padapter); ++#endif ++#ifdef CONFIG_TX_EARLY_MODE ++ pHalData->bEarlyModeEnable = padapter->registrypriv.early_mode; ++#endif ++ ++ return _SUCCESS; ++} ++ ++void rtl8188eu_free_xmit_priv(_adapter *padapter) ++{ ++} ++ ++u8 urb_zero_packet_chk(_adapter *padapter, int sz) ++{ ++#if 1 ++ u8 blnSetTxDescOffset; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ blnSetTxDescOffset = (((sz + TXDESC_SIZE) % pHalData->UsbBulkOutSize) ==0)?1:0; ++ ++#else ++ ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); ++ if ( pdvobj->ishighspeed ) ++ { ++ if ( ( (sz + TXDESC_SIZE) % 512 ) == 0 ) { ++ blnSetTxDescOffset = 1; ++ } else { ++ blnSetTxDescOffset = 0; ++ } ++ } ++ else ++ { ++ if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) { ++ blnSetTxDescOffset = 1; ++ } else { ++ blnSetTxDescOffset = 0; ++ } ++ } ++#endif ++ return blnSetTxDescOffset; ++ ++} ++ ++void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc) ++{ ++ u16 *usPtr = (u16*)ptxdesc; ++ u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times ++ u32 index; ++ u16 checksum = 0; ++ ++ //Clear first ++ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); ++ ++ for(index = 0 ; index < count ; index++){ ++ checksum = checksum ^ le16_to_cpu(*(usPtr + index)); ++ } ++ ++ ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum); ++ ++} ++// ++// Description: In normal chip, we should send some packet to Hw which will be used by Fw ++// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then ++// Fw can tell Hw to send these packet derectly. ++// ++void rtl8188e_fill_fake_txdesc( ++ PADAPTER padapter, ++ u8* pDesc, ++ u32 BufferLen, ++ u8 IsPsPoll, ++ u8 IsBTQosNull) ++{ ++ struct tx_desc *ptxdesc; ++ ++ ++ // Clear all status ++ ptxdesc = (struct tx_desc*)pDesc; ++ _rtw_memset(pDesc, 0, TXDESC_SIZE); ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg; ++ ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<txdw1 |= cpu_to_le32(NAVUSEHDR); ++ } ++ else ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ } ++ ++ if (_TRUE == IsBTQosNull) ++ { ++ ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL ++ } ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) ++ // USB interface drop packet if the checksum of descriptor isn't correct. ++ // Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). ++ rtl8188eu_cal_txdesc_chksum(ptxdesc); ++#endif ++} ++ ++void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc) ++{ ++ if ((pattrib->encrypt > 0) && !pattrib->bswenc) ++ { ++ switch (pattrib->encrypt) ++ { ++ //SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES ++ case _WEP40_: ++ case _WEP104_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x01<txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x01<txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case _SMS4_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x02<txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); ++ break; ++#endif ++ case _AES_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x03<txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); ++ break; ++ case _NO_PRIVACY_: ++ default: ++ break; ++ ++ } ++ ++ } ++ ++} ++ ++void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw) ++{ ++ //DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); ++ ++ switch(pattrib->vcs_mode) ++ { ++ case RTS_CTS: ++ *pdw |= cpu_to_le32(RTS_EN); ++ break; ++ case CTS_TO_SELF: ++ *pdw |= cpu_to_le32(CTS_2_SELF); ++ break; ++ case NONE_VCS: ++ default: ++ break; ++ } ++ ++ if(pattrib->vcs_mode) { ++ *pdw |= cpu_to_le32(HW_RTS_EN); ++ ++ // Set RTS BW ++ if(pattrib->ht_en) ++ { ++ *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0; ++ ++ if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ *pdw |= cpu_to_le32((0x01<<28)&0x30000000); ++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) ++ *pdw |= cpu_to_le32((0x02<<28)&0x30000000); ++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ++ *pdw |= 0; ++ else ++ *pdw |= cpu_to_le32((0x03<<28)&0x30000000); ++ } ++ } ++} ++ ++void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw) ++{ ++ //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); ++ ++ if(pattrib->ht_en) ++ { ++ *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(25)):0; ++ ++ if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ *pdw |= cpu_to_le32((0x01<ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) ++ *pdw |= cpu_to_le32((0x02<ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ++ *pdw |= 0; ++ else ++ *pdw |= cpu_to_le32((0x03<padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ //struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct tx_desc *ptxdesc = (struct tx_desc *)pmem; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ sint bmcst = IS_MCAST(pattrib->ra); ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++if (padapter->registrypriv.mp_mode == 0) ++{ ++ if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0 ++ //if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==_FALSE)) ++ { ++ ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ); ++ //DBG_8192C("==> non-agg-pkt,shift pointer...\n"); ++ pull = 1; ++ } ++} ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ _rtw_memset(ptxdesc, 0, sizeof(struct tx_desc)); ++ ++ //4 offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ //DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt); ++ ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE ++ ++ offset = TXDESC_SIZE + OFFSET_SZ; ++ ++ #ifdef CONFIG_TX_EARLY_MODE ++ if(bagg_pkt){ ++ offset += EARLY_MODE_INFO_SIZE ;//0x28 ++ } ++ #endif ++ //DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset); ++ ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc ++ ++ if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC); ++ ++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++if (padapter->registrypriv.mp_mode == 0) ++{ ++ if(!bagg_pkt){ ++ if((pull) && (pxmitframe->pkt_offset>0)) { ++ pxmitframe->pkt_offset = pxmitframe->pkt_offset -1; ++ } ++ } ++} ++#endif ++ //DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); ++ ++ // pkt_offset, unit:8 bytes padding ++ if (pxmitframe->pkt_offset > 0) ++ ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000); ++ ++ //driver uses rate ++ ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver ++ ++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ //DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F); ++ ++ qsel = (uint)(pattrib->qsel & 0x0000001f); ++ //DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); ++ ++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000); ++ ++ fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ if(pattrib->ampdu_en==_TRUE){ ++ ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN ++ ++ //SET_TX_DESC_MAX_AGG_NUM_88E(pDesc, 0x1F); ++ //SET_TX_DESC_MCSG1_MAX_LEN_88E(pDesc, 0x6); ++ //SET_TX_DESC_MCSG2_MAX_LEN_88E(pDesc, 0x6); ++ //SET_TX_DESC_MCSG3_MAX_LEN_88E(pDesc, 0x6); ++ //SET_TX_DESC_MCS7_SGI_MAX_LEN_88E(pDesc, 0x6); ++ ptxdesc->txdw6 = 0x6666f800; ++ } ++ else{ ++ ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK ++ } ++ ++ //offset 8 ++ ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000); ++ ++ ++ //offset 16 , offset 20 ++ if (pattrib->qos_en) ++ ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS ++ ++ //offset 20 ++ #ifdef CONFIG_USB_TX_AGGREGATION ++ if (pxmitframe->agg_num > 1){ ++ //DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); ++ ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000); ++ } ++ #endif ++ ++ if ((pattrib->ether_type != 0x888e) && ++ (pattrib->ether_type != 0x0806) && ++ (pattrib->ether_type != 0x88b4) && ++ (pattrib->dhcp_pkt != 1)) ++ { ++ //Non EAP & ARP & DHCP type data packet ++ ++ fill_txdesc_vcs(pattrib, &ptxdesc->txdw4); ++ fill_txdesc_phy(pattrib, &ptxdesc->txdw4); ++ ++ ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M ++ ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS Rate FB LMT ++ ++ #if (RATE_ADAPTIVE_SUPPORT == 1) ++ if(pattrib->ht_en){ ++ if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id)) ++ ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI ++ } ++ ++ data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id); ++ //for debug ++ #if 1 ++ if(padapter->fix_rate!= 0xFF){ ++ ++ data_rate = padapter->fix_rate; ++ ptxdesc->txdw4 |= cpu_to_le32(DISDATAFB); ++ //printk("==> fix data_rate:0x%02x\n",data_rate); ++ } ++ #endif ++ ++ ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); ++ ++ #if (POWER_TRAINING_ACTIVE==1) ++ pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id); ++ ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT); ++ #endif //(POWER_TRAINING_ACTIVE==1) ++ #else//if (RATE_ADAPTIVE_SUPPORT == 1) ++ ++ if(pattrib->ht_en) ++ ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI ++ ++ data_rate = 0x13; //default rate: MCS7 ++ if(padapter->fix_rate!= 0xFF){//rate control by iwpriv ++ data_rate = padapter->fix_rate; ++ ptxdesc->txdw4 | cpu_to_le32(DISDATAFB); ++ } ++ ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); ++ ++ #endif//if (RATE_ADAPTIVE_SUPPORT == 1) ++ ++ } ++ else ++ { ++ // EAP data packet and ARP packet and DHCP. ++ // Use the 1M data rate to send the EAP/ARP packet. ++ // This will maybe make the handshake smooth. ++ ++ ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK ++ ++ if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT ++ ++ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); ++ } ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ //offset 24 ++ if ( pattrib->hw_tcp_csum == 1 ) { ++ // ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!! ++ u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8; ++ ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16); ++ DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7); ++ } ++#endif ++ } ++ else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) ++ { ++ //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f); ++ ++ qsel = (uint)(pattrib->qsel&0x0000001f); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel<txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000); ++ ++ //fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ //offset 8 ++#ifdef CONFIG_XMIT_ACK ++ //CCX-TXRPT ack for xmit mgmt frames. ++ if (pxmitframe->ack_report) { ++ #ifdef DBG_CCX ++ static u16 ccx_sw = 0x123; ++ ptxdesc->txdw7 |= cpu_to_le32(((ccx_sw)<<16)&0x0fff0000); ++ DBG_871X("%s set ccx, sw:0x%03x\n", __func__, ccx_sw); ++ ccx_sw = (ccx_sw+1)%0xfff; ++ #endif ++ ptxdesc->txdw2 |= cpu_to_le32(BIT(19)); ++ } ++#endif //CONFIG_XMIT_ACK ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable ++ if(pattrib->retry_ctrl == _TRUE) ++ ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6 ++ else ++ ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12 ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){ ++ DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate); ++ ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate); ++ } ++ else ++#endif ++ { ++ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); ++ } ++ } ++ else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) ++ { ++ DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); ++ } ++#ifdef CONFIG_MP_INCLUDED ++ else if(((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) && ++ (padapter->registrypriv.mp_mode == 1)) ++ { ++ fill_txdesc_for_mp(padapter, ptxdesc); ++ } ++#endif ++ else ++ { ++ DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID) ++ ++ ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid ++ ++ //offset 8 ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); ++ } ++ ++ // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. ++ // (1) The sequence number of each non-Qos frame / broadcast / multicast / ++ // mgnt frame should be controled by Hw because Fw will also send null data ++ // which we cannot control when Fw LPS enable. ++ // --> default enable non-Qos data sequense number. 2010.06.23. by tynli. ++ // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. ++ // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. ++ // 2010.06.23. Added by tynli. ++ if(!pattrib->qos_en) ++ { ++ //ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ //ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ ++ ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number ++ ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number ++ ++ } ++ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY ++ ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id); ++#endif ++ ++ rtl8188eu_cal_txdesc_chksum(ptxdesc); ++ _dbg_dump_tx_info(padapter,pxmitframe->frame_tag,ptxdesc); ++ return pull; ++ ++} ++ ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++/* ++ * Description ++ * Transmit xmitbuf to hardware tx fifo ++ * ++ * Return ++ * _SUCCESS ok ++ * _FAIL something error ++ */ ++s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter) ++{ ++ //PHAL_DATA_TYPE phal; ++ struct xmit_priv *pxmitpriv; ++ struct xmit_buf *pxmitbuf; ++ s32 ret; ++ ++ ++ //phal = GET_HAL_DATA(padapter); ++ pxmitpriv = &padapter->xmitpriv; ++ ++ ret = _rtw_down_sema(&pxmitpriv->xmit_sema); ++ if (_FAIL == ret) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ++ ("%s: down SdioXmitBufSema fail!\n", __FUNCTION__)); ++ return _FAIL; ++ } ++ ++ ret = (padapter->bDriverStopped == _TRUE) || (padapter->bSurpriseRemoved == _TRUE); ++ if (ret) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)!\n", ++ __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ return _FAIL; ++ } ++ ++ if(check_pending_xmitbuf(pxmitpriv) == _FALSE) ++ return _SUCCESS; ++ ++#ifdef CONFIG_LPS_LCLK ++ ret = rtw_register_tx_alive(padapter); ++ if (ret != _SUCCESS) { ++ RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ++ ("%s: wait to leave LPS_LCLK\n", __FUNCTION__)); ++ return _SUCCESS; ++ } ++#endif ++ ++ do { ++ pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) break; ++ ++ rtw_write_port(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char*)pxmitbuf); ++ ++ } while (1); ++ ++#ifdef CONFIG_LPS_LCLK ++ rtw_unregister_tx_alive(padapter); ++#endif ++ ++ return _SUCCESS; ++} ++#endif ++ ++#ifdef CONFIG_IOL_IOREG_CFG_DBG ++#include ++#endif ++//for non-agg data frame or management frame ++static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ s32 ret = _SUCCESS; ++ s32 inner_ret = _SUCCESS; ++ int t, sz, w_sz, pull=0; ++ u8 *mem_addr; ++ u32 ff_hwaddr; ++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++#ifdef CONFIG_80211N_HT ++ if ((pxmitframe->frame_tag == DATA_FRAMETAG) && ++ (pxmitframe->attrib.ether_type != 0x0806) && ++ (pxmitframe->attrib.ether_type != 0x888e) && ++ (pxmitframe->attrib.ether_type != 0x88b4) && ++ (pxmitframe->attrib.dhcp_pkt != 1)) ++ { ++ rtw_issue_addbareq_cmd(padapter, pxmitframe); ++ } ++#endif //CONFIG_80211N_HT ++ mem_addr = pxmitframe->buf_addr; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n")); ++ ++ for (t = 0; t < pattrib->nr_frags; t++) ++ { ++ if (inner_ret != _SUCCESS && ret == _SUCCESS) ++ ret = _FAIL; ++ ++ if (t != (pattrib->nr_frags - 1)) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags)); ++ ++ sz = pxmitpriv->frag_len; ++ sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); ++ } ++ else //no frag ++ { ++ sz = pattrib->last_txcmdsz; ++ } ++ ++ pull = update_txdesc(pxmitframe, mem_addr, sz, _FALSE); ++ ++ if(pull) ++ { ++ mem_addr += PACKET_OFFSET_SZ; //pull txdesc head ++ ++ //pxmitbuf ->pbuf = mem_addr; ++ pxmitframe->buf_addr = mem_addr; ++ ++ w_sz = sz + TXDESC_SIZE; ++ } ++ else ++ { ++ w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ; ++ } ++#ifdef CONFIG_IOL_IOREG_CFG_DBG ++ rtw_IOL_cmd_buf_dump(padapter,w_sz,pxmitframe->buf_addr); ++#endif ++ ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++ pxmitbuf->len = w_sz; ++ pxmitbuf->ff_hwaddr = ff_hwaddr; ++ enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); ++#else ++ inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf); ++#endif ++ ++ rtw_count_tx_stats(padapter, pxmitframe, sz); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz)); ++ //DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); ++ ++ mem_addr += w_sz; ++ ++ mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr))); ++ ++ } ++ ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ if (ret != _SUCCESS) ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) ++{ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ u32 len = 0; ++ ++ // no consider fragement ++ len = pattrib->hdrlen + pattrib->iv_len + ++ SNAP_SIZE + sizeof(u16) + ++ pattrib->pktlen + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0); ++ ++ if(pattrib->encrypt ==_TKIP_) ++ len += 8; ++ ++ return len; ++} ++ ++#define IDEA_CONDITION 1 // check all packets before enqueue ++s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct xmit_frame *pxmitframe = NULL; ++ struct xmit_frame *pfirstframe = NULL; ++ ++ // aggregate variable ++ struct hw_xmit *phwxmit; ++ struct sta_info *psta = NULL; ++ struct tx_servq *ptxservq = NULL; ++ ++ _irqL irqL; ++ _list *xmitframe_plist = NULL, *xmitframe_phead = NULL; ++ ++ u32 pbuf; // next pkt address ++ u32 pbuf_tail; // last pkt tail ++ u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET ++ ++ u32 bulkSize = pHalData->UsbBulkOutSize; ++ u8 descCount; ++ u32 bulkPtr; ++ ++ // dump frame variable ++ u32 ff_hwaddr; ++ ++#ifndef IDEA_CONDITION ++ int res = _SUCCESS; ++#endif ++ ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n")); ++ ++ ++ // check xmitbuffer is ok ++ if (pxmitbuf == NULL) { ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL){ ++ //DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__); ++ return _FALSE; ++ } ++ } ++ ++//DBG_8192C("%s ===================================== \n",__FUNCTION__); ++ //3 1. pick up first frame ++ do { ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); ++ if (pxmitframe == NULL) { ++ // no more xmit frame, release xmit buffer ++ //DBG_8192C("no more xmit frame ,return\n"); ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ return _FALSE; ++ } ++ ++#ifndef IDEA_CONDITION ++ if (pxmitframe->frame_tag != DATA_FRAMETAG) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", ++ pxmitframe->frame_tag, DATA_FRAMETAG)); ++// rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ // TID 0~15 ++ if ((pxmitframe->attrib.priority < 0) || ++ (pxmitframe->attrib.priority > 15)) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: TID(%d) should be 0~15!\n", ++ pxmitframe->attrib.priority)); ++// rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pxmitframe; ++ ++ pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1. ++ #ifdef CONFIG_TX_EARLY_MODE ++ pxmitframe->pkt_offset = 2; // first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check ++ #else ++ pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset ++ #endif ++ ++ if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { ++ DBG_871X("%s coalesce 1st xmitframe failed \n",__FUNCTION__); ++ continue; ++ } ++ ++ // always return ndis_packet after rtw_xmitframe_coalesce ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ ++ break; ++ } while (1); ++ ++ //3 2. aggregate same priority and same DA(AP or STA) frames ++ pfirstframe = pxmitframe; ++ len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE+(pfirstframe->pkt_offset*PACKET_OFFSET_SZ); ++ pbuf_tail = len; ++ pbuf = _RND8(pbuf_tail); ++ ++ // check pkt amount in one bulk ++ descCount = 0; ++ bulkPtr = bulkSize; ++ if (pbuf < bulkPtr) ++ descCount++; ++ else { ++ descCount = 0; ++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize ++ } ++ ++ // dequeue same priority packet from station tx queue ++ //psta = pfirstframe->attrib.psta; ++ psta = rtw_get_stainfo(&padapter->stapriv, pfirstframe->attrib.ra); ++ if(pfirstframe->attrib.psta != psta){ ++ DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pfirstframe->attrib.psta, psta); ++ } ++ if (psta == NULL) { ++ DBG_8192C("rtw_xmit_classifier: psta == NULL\n"); ++ } ++ if(!(psta->state &_FW_LINKED)){ ++ DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); ++ } ++ ++ switch (pfirstframe->attrib.priority) { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ phwxmit = pxmitpriv->hwxmits + 3; ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ phwxmit = pxmitpriv->hwxmits + 1; ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ phwxmit = pxmitpriv->hwxmits; ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ phwxmit = pxmitpriv->hwxmits + 2; ++ break; ++ } ++//DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n", ++ //pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset ); ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&ptxservq->sta_pending); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ pxmitframe->agg_num = 0; // not first frame of aggregation ++ #ifdef CONFIG_TX_EARLY_MODE ++ pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info ++ #else ++ pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset ++ #endif ++ ++ len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE +(pxmitframe->pkt_offset*PACKET_OFFSET_SZ); ++ ++ if (_RND8(pbuf + len) > MAX_XMITBUF_SZ) ++ //if (_RND8(pbuf + len) > (MAX_XMITBUF_SZ/2))//to do : for TX TP finial tune , Georgia 2012-0323 ++ { ++ //DBG_8192C("%s....len> MAX_XMITBUF_SZ\n",__FUNCTION__); ++ pxmitframe->agg_num = 1; ++ pxmitframe->pkt_offset = 1; ++ break; ++ } ++ rtw_list_delete(&pxmitframe->list); ++ ptxservq->qcnt--; ++ phwxmit->accnt--; ++ ++#ifndef IDEA_CONDITION ++ // suppose only data frames would be in queue ++ if (pxmitframe->frame_tag != DATA_FRAMETAG) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", ++ pxmitframe->frame_tag, DATA_FRAMETAG)); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ // TID 0~15 ++ if ((pxmitframe->attrib.priority < 0) || ++ (pxmitframe->attrib.priority > 15)) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: TID(%d) should be 0~15!\n", ++ pxmitframe->attrib.priority)); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ ++// pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; ++ ++ if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { ++ DBG_871X("%s coalesce failed \n",__FUNCTION__); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); ++ // always return ndis_packet after rtw_xmitframe_coalesce ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ ++ // (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz ++ update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz,_TRUE); ++ ++ // don't need xmitframe any more ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ // handle pointer and stop condition ++ pbuf_tail = pbuf + len; ++ pbuf = _RND8(pbuf_tail); ++ ++ ++ pfirstframe->agg_num++; ++#ifdef CONFIG_TX_EARLY_MODE ++ pxmitpriv->agg_pkt[pfirstframe->agg_num-1].offset = _RND8(len); ++ pxmitpriv->agg_pkt[pfirstframe->agg_num-1].pkt_len = pxmitframe->attrib.last_txcmdsz; ++#endif ++ if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num) ++ break; ++ ++ if (pbuf < bulkPtr) { ++ descCount++; ++ if (descCount == pHalData->UsbTxAggDescNum) ++ break; ++ } else { ++ descCount = 0; ++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; ++ } ++ }//end while( aggregate same priority and same DA(AP or STA) frames) ++ ++ ++ if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE) ++ rtw_list_delete(&ptxservq->tx_pending); ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++#ifdef CONFIG_80211N_HT ++ if ((pfirstframe->attrib.ether_type != 0x0806) && ++ (pfirstframe->attrib.ether_type != 0x888e) && ++ (pfirstframe->attrib.ether_type != 0x88b4) && ++ (pfirstframe->attrib.dhcp_pkt != 1)) ++ { ++ rtw_issue_addbareq_cmd(padapter, pfirstframe); ++ } ++#endif //CONFIG_80211N_HT ++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ //3 3. update first frame txdesc ++ if ((pbuf_tail % bulkSize) == 0) { ++ // remove pkt_offset ++ pbuf_tail -= PACKET_OFFSET_SZ; ++ pfirstframe->buf_addr += PACKET_OFFSET_SZ; ++ pfirstframe->pkt_offset--; ++ //DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n"); ++ } ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz,_TRUE); ++ ++ #ifdef CONFIG_TX_EARLY_MODE ++ //prepare EM info for first frame, agg_num value start from 1 ++ pxmitpriv->agg_pkt[0].offset = _RND8(pfirstframe->attrib.last_txcmdsz +TXDESC_SIZE +(pfirstframe->pkt_offset*PACKET_OFFSET_SZ)); ++ pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;//get from rtw_xmitframe_coalesce ++ ++ UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf ); ++ #endif ++ ++ //3 4. write xmit buffer to USB FIFO ++ ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); ++//DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail); ++ // xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr ++ rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf); ++ ++ ++ //3 5. update statisitc ++ pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE); ++ pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); ++ ++ ++ rtw_count_tx_stats(padapter, pfirstframe, pbuf_tail); ++ ++ rtw_free_xmitframe(pxmitpriv, pfirstframe); ++ ++ return _TRUE; ++} ++ ++#else ++ ++s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ ++ struct hw_xmit *phwxmits; ++ sint hwentry; ++ struct xmit_frame *pxmitframe=NULL; ++ int res=_SUCCESS, xcnt = 0; ++ ++ phwxmits = pxmitpriv->hwxmits; ++ hwentry = pxmitpriv->hwxmit_entry; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete()\n")); ++ ++ if(pxmitbuf==NULL) ++ { ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if(!pxmitbuf) ++ { ++ return _FALSE; ++ } ++ } ++ ++ ++ do ++ { ++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, phwxmits, hwentry); ++ ++ if(pxmitframe) ++ { ++ pxmitframe->pxmitbuf = pxmitbuf; ++ ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ ++ pxmitbuf->priv_data = pxmitframe; ++ ++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ if(pxmitframe->attrib.priority<=15)//TID0~15 ++ { ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ } ++ //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); ++ rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce ++ } ++ ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete(): rtw_dump_xframe\n")); ++ ++ ++ if(res == _SUCCESS) ++ { ++ rtw_dump_xframe(padapter, pxmitframe); ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ } ++ ++ xcnt++; ++ ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ return _FALSE; ++ } ++ ++ break; ++ ++ }while(0/*xcnt < (NR_XMITFRAME >> 3)*/); ++ ++ return _TRUE; ++ ++} ++#endif ++ ++ ++ ++static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ s32 res = _SUCCESS; ++//DBG_8192C("==> %s \n",__FUNCTION__); ++ ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (res == _SUCCESS) { ++ rtw_dump_xframe(padapter, pxmitframe); ++ } ++ else{ ++ DBG_8192C("==> %s xmitframe_coalsece failed\n",__FUNCTION__); ++ } ++ ++ return res; ++} ++ ++/* ++ * Return ++ * _TRUE dump packet directly ++ * _FALSE enqueue packet ++ */ ++static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ s32 res; ++ struct xmit_buf *pxmitbuf = NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++#endif ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++//DBG_8192C("==> %s \n",__FUNCTION__); ++ ++ if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) ++ { ++ //DBG_8192C("enqueue AC(%d)\n",pattrib->priority); ++ goto enqueue; ++ } ++ ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ goto enqueue; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_fwstate(pbuddy_mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ goto enqueue; ++#endif ++ ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) ++ goto enqueue; ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pxmitframe; ++ ++ if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ } ++ ++ return _TRUE; ++ ++enqueue: ++ res = rtw_xmitframe_enqueue(padapter, pxmitframe); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if (res != _SUCCESS) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n")); ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ // Trick, make the statistics correct ++ pxmitpriv->tx_pkts--; ++ pxmitpriv->tx_drop++; ++ return _TRUE; ++ } ++ ++ return _FALSE; ++} ++ ++s32 rtl8188eu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++ return rtw_dump_xframe(padapter, pmgntframe); ++} ++ ++/* ++ * Return ++ * _TRUE dump packet directly ok ++ * _FALSE temporary can't transmit packets to hardware ++ */ ++s32 rtl8188eu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ return pre_xmitframe(padapter, pxmitframe); ++} ++ ++s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ s32 err; ++ ++ if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) ++ { ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ // Trick, make the statistics correct ++ pxmitpriv->tx_pkts--; ++ pxmitpriv->tx_drop++; ++ } ++ else ++ { ++#ifdef PLATFORM_LINUX ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++#endif ++ } ++ ++ return err; ++ ++} ++ ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ ++static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb) ++{ ++#ifdef PLATFORM_LINUX ++ struct sk_buff *skb = (struct sk_buff *)urb->context; ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ rtw_skb_free(skb); ++#endif ++} ++ ++s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) ++{ ++#ifdef PLATFORM_LINUX ++ u16 fc; ++ int rc, len, pipe; ++ unsigned int bmcst, tid, qsel; ++ struct sk_buff *skb, *pxmit_skb; ++ struct urb *urb; ++ unsigned char *pxmitbuf; ++ struct tx_desc *ptxdesc; ++ struct rtw_ieee80211_hdr *tx_hdr; ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); ++ ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ skb = pkt; ++ ++ len = skb->len; ++ tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data); ++ fc = le16_to_cpu(tx_hdr->frame_ctl); ++ bmcst = IS_MCAST(tx_hdr->addr1); ++ ++ if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT) ++ goto _exit; ++ ++ pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE); ++ ++ if(!pxmit_skb) ++ goto _exit; ++ ++ pxmitbuf = pxmit_skb->data; ++ ++ urb = usb_alloc_urb(0, GFP_ATOMIC); ++ if (!urb) { ++ goto _exit; ++ } ++ ++ // ----- fill tx desc ----- ++ ptxdesc = (struct tx_desc *)pxmitbuf; ++ _rtw_memset(ptxdesc, 0, sizeof(*ptxdesc)); ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ ++ if(bmcst) ++ { ++ ptxdesc->txdw0 |= cpu_to_le32(BIT(24)); ++ } ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID ++ ++ ptxdesc->txdw1 |= cpu_to_le32((0x12<txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode ++ ++ //offset 8 ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000); ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ //offset 20 ++ ++ ++ //HW append seq ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ ++ ++ rtl8188eu_cal_txdesc_chksum(ptxdesc); ++ // ----- end of fill tx desc ----- ++ ++ // ++ skb_put(pxmit_skb, len + TXDESC_SIZE); ++ pxmitbuf = pxmitbuf + TXDESC_SIZE; ++ _rtw_memcpy(pxmitbuf, skb->data, len); ++ ++ //DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); ++ ++ ++ // ----- prepare urb for submit ----- ++ ++ //translate DMA FIFO addr to pipehandle ++ //pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); ++ pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f); ++ ++ usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, ++ pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb); ++ ++ urb->transfer_flags |= URB_ZERO_PACKET; ++ usb_anchor_urb(urb, &phostapdpriv->anchored); ++ rc = usb_submit_urb(urb, GFP_ATOMIC); ++ if (rc < 0) { ++ usb_unanchor_urb(urb); ++ kfree_skb(skb); ++ } ++ usb_free_urb(urb); ++ ++ ++_exit: ++ ++ rtw_skb_free(skb); ++ ++#endif ++ ++ return 0; ++ ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_halinit.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_halinit.c +new file mode 100644 +index 00000000..5408f6ea +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_halinit.c +@@ -0,0 +1,5370 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_HAL_INIT_C_ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_IOL ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifndef CONFIG_USB_HCI ++ ++#error "CONFIG_USB_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++#include ++#include ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++#if DISABLE_BB_RF ++ #define HAL_MAC_ENABLE 0 ++ #define HAL_BB_ENABLE 0 ++ #define HAL_RF_ENABLE 0 ++#else ++ #define HAL_MAC_ENABLE 1 ++ #define HAL_BB_ENABLE 1 ++ #define HAL_RF_ENABLE 1 ++#endif ++ ++ ++static VOID ++_ConfigNormalChipOutEP_8188E( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ switch(NumOutPipe){ ++ case 3: ++ pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ; ++ pHalData->OutEpNumber=3; ++ break; ++ case 2: ++ pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ; ++ pHalData->OutEpNumber=2; ++ break; ++ case 1: ++ pHalData->OutEpQueueSel=TX_SELE_HQ; ++ pHalData->OutEpNumber=1; ++ break; ++ default: ++ break; ++ ++ } ++ DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber ); ++ ++} ++ ++static BOOLEAN HalUsbSetQueuePipeMapping8188EUsb( ++ IN PADAPTER pAdapter, ++ IN u8 NumInPipe, ++ IN u8 NumOutPipe ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN result = _FALSE; ++ ++ _ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe); ++ ++ // Normal chip with one IN and one OUT doesn't have interrupt IN EP. ++ if(1 == pHalData->OutEpNumber){ ++ if(1 != NumInPipe){ ++ return result; ++ } ++ } ++ ++ // All config other than above support one Bulk IN and one Interrupt IN. ++ //if(2 != NumInPipe){ ++ // return result; ++ //} ++ ++ result = Hal_MappingOutPipe(pAdapter, NumOutPipe); ++ ++ return result; ++ ++} ++ ++void rtl8188eu_interface_configure(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ ++ if (pdvobjpriv->ishighspeed == _TRUE) ++ { ++ pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes ++ } ++ else ++ { ++ pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes ++ } ++ ++ pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pHalData->UsbTxAggMode = 1; ++ pHalData->UsbTxAggDescNum = 0x6; // only 4 bits ++#endif ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ pHalData->UsbRxAggMode = USB_RX_AGG_DMA;// USB_RX_AGG_DMA; ++ pHalData->UsbRxAggBlockCount = 8; //unit : 512b ++ pHalData->UsbRxAggBlockTimeout = 0x6; ++ pHalData->UsbRxAggPageCount = 48; //uint :128 b //0x0A; // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize ++ pHalData->UsbRxAggPageTimeout = 0x4; //6, absolute time = 34ms/(2^6) ++#endif ++ ++ HalUsbSetQueuePipeMapping8188EUsb(padapter, ++ pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); ++ ++} ++ ++static u32 InitPowerOn_rtl8188eu(_adapter *padapter) ++{ ++ u16 value16; ++ u8 bMacPwrCtrlOn=_FALSE; ++ // HW Power on sequence ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if(bMacPwrCtrlOn == _TRUE) ++ return _SUCCESS; ++ ++ if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) ++ { ++ DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__); ++ return _FAIL; ++ } ++ ++ // Enable MAC DMA/WMAC/SCHEDULE/SEC block ++ // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. ++ rtw_write16(padapter, REG_CR, 0x00); //suggseted by zhouzhou, by page, 20111230 ++ ++ ++ // Enable MAC DMA/WMAC/SCHEDULE/SEC block ++ value16 = rtw_read16(padapter, REG_CR); ++ value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN ++ | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN); ++ // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. ++ ++ rtw_write16(padapter, REG_CR, value16); ++ ++ bMacPwrCtrlOn = _TRUE; ++ rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ ++ return _SUCCESS; ++ ++} ++ ++ ++static void _dbg_dump_macreg(_adapter *padapter) ++{ ++ u32 offset = 0; ++ u32 val32 = 0; ++ u32 index =0 ; ++ for(index=0;index<64;index++) ++ { ++ offset = index*4; ++ val32 = rtw_read32(padapter,offset); ++ DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32); ++ } ++} ++ ++ ++static void _InitPABias(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 pa_setting; ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ //FIXED PA current issue ++ //efuse_one_byte_read(padapter, 0x1FA, &pa_setting); ++ pa_setting = EFUSE_Read1Byte(padapter, 0x1FA); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting)); ++ ++ if(!(pa_setting & BIT0)) ++ { ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); ++ } ++ ++ if(!(pa_setting & BIT1) && is92C) ++ { ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); ++ } ++ ++ if(!(pa_setting & BIT4)) ++ { ++ pa_setting = rtw_read8(padapter, 0x16); ++ pa_setting &= 0x0F; ++ rtw_write8(padapter, 0x16, pa_setting | 0x80); ++ rtw_write8(padapter, 0x16, pa_setting | 0x90); ++ } ++} ++#ifdef CONFIG_BT_COEXIST ++static void _InitBTCoexist(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ u8 u1Tmp; ++ ++ if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4) ++ { ++ ++//#if MP_DRIVER != 1 ++ if (padapter->registrypriv.mp_mode == 0) ++ { ++ if(pbtpriv->BT_Ant_isolation) ++ { ++ rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0); ++ } ++ } ++//#endif ++ ++ u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0; ++ u1Tmp = u1Tmp | ++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) | ++ ((pbtpriv->BT_Service==BT_SCO)?0:BIT2); ++ rtw_write8( padapter, 0x4fd, u1Tmp); ++ DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp); ++ ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa); ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040); ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010); ++ ++ //Config to 1T1R ++ u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable); ++ u1Tmp &= ~(BIT1); ++ rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp); ++ DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp); ++ ++ u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable); ++ u1Tmp &= ~(BIT1); ++ rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp); ++ DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp); ++ ++ } ++} ++#endif ++ ++ ++ ++//--------------------------------------------------------------- ++// ++// MAC init functions ++// ++//--------------------------------------------------------------- ++static VOID ++_SetMacID( ++ IN PADAPTER Adapter, u8* MacID ++ ) ++{ ++ u32 i; ++ for(i=0 ; i< MAC_ADDR_LEN ; i++){ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write32(Adapter, REG_MACID1+i, MacID[i]); ++ else ++#endif ++ rtw_write32(Adapter, REG_MACID+i, MacID[i]); ++ } ++} ++ ++static VOID ++_SetBSSID( ++ IN PADAPTER Adapter, u8* BSSID ++ ) ++{ ++ u32 i; ++ for(i=0 ; i< MAC_ADDR_LEN ; i++){ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]); ++ else ++#endif ++ rtw_write32(Adapter, REG_BSSID+i, BSSID[i]); ++ } ++} ++ ++ ++// Shall USB interface init this? ++static VOID ++_InitInterrupt( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 imr,imr_ex; ++ u8 usb_opt; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //HISR write one to clear ++ rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF); ++ // HIMR - ++ imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E ; ++ rtw_write32(Adapter, REG_HIMR_88E, imr); ++ pHalData->IntrMask[0]=imr; ++ ++ imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E |IMR_RXFOVW_88E; ++ rtw_write32(Adapter, REG_HIMRE_88E, imr_ex); ++ pHalData->IntrMask[1]=imr_ex; ++ ++#ifdef CONFIG_SUPPORT_USB_INT ++ // REG_USB_SPECIAL_OPTION - BIT(4) ++ // 0; Use interrupt endpoint to upload interrupt pkt ++ // 1; Use bulk endpoint to upload interrupt pkt, ++ usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION); ++ ++ ++ if(!adapter_to_dvobj(Adapter)->ishighspeed ++ #ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ || pHalData->RtIntInPipe == 0x05 ++ #endif ++ ) ++ usb_opt = usb_opt & (~INT_BULK_SEL); ++ else ++ usb_opt = usb_opt | (INT_BULK_SEL); ++ ++ rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt ); ++ ++#endif//CONFIG_SUPPORT_USB_INT ++ ++} ++ ++ ++static VOID ++_InitQueueReservedPage( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u32 outEPNum = (u32)pHalData->OutEpNumber; ++ u32 numHQ = 0; ++ u32 numLQ = 0; ++ u32 numNQ = 0; ++ u32 numPubQ; ++ u32 value32; ++ u8 value8; ++ BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; ++ ++ if((bWiFiConfig)|| (pregistrypriv->qos_opt_enable)) ++ { ++ if (pHalData->OutEpQueueSel & TX_SELE_HQ) ++ { ++ numHQ = 0x29; ++ } ++ ++ if (pHalData->OutEpQueueSel & TX_SELE_LQ) ++ { ++ numLQ = 0x1C; ++ } ++ ++ // NOTE: This step shall be proceed before writting REG_RQPN. ++ if (pHalData->OutEpQueueSel & TX_SELE_NQ) { ++ numNQ = 0x1C; ++ } ++ value8 = (u8)_NPQ(numNQ); ++ rtw_write8(Adapter, REG_RQPN_NPQ, value8); ++ ++ numPubQ = 0xA8 - numHQ - numLQ - numNQ; ++ ++ // TX DMA ++ value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; ++ rtw_write32(Adapter, REG_RQPN, value32); ++ } ++ else ++ { ++ rtw_write16(Adapter,REG_RQPN_NPQ, 0x0000);//Just follow MP Team,??? Georgia 03/28 ++ rtw_write16(Adapter,REG_RQPN_NPQ, 0x0d); ++ rtw_write32(Adapter,REG_RQPN, 0x808E000d);//reserve 7 page for LPS ++ } ++} ++ ++static VOID ++_InitTxBufferBoundary( ++ IN PADAPTER Adapter, ++ IN u8 txpktbuf_bndy ++ ) ++{ ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ //u16 txdmactrl; ++ ++ rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy); ++ ++} ++ ++static VOID ++_InitPageBoundary( ++ IN PADAPTER Adapter ++ ) ++{ ++ // RX Page Boundary ++ // ++ u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1; ++ ++ #if 0 ++ ++ // RX Page Boundary ++ //srand(static_cast(time(NULL)) ); ++ if(bSupportRemoteWakeUp) ++ { ++ Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE; ++ Offset = Offset / 128; // RX page size = 128 byte ++ rxff_bndy= (Offset*128) -1; ++ } ++ else ++ ++ #endif ++ rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); ++} ++ ++ ++static VOID ++_InitNormalChipRegPriority( ++ IN PADAPTER Adapter, ++ IN u16 beQ, ++ IN u16 bkQ, ++ IN u16 viQ, ++ IN u16 voQ, ++ IN u16 mgtQ, ++ IN u16 hiQ ++ ) ++{ ++ u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7); ++ ++ value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | ++ _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | ++ _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ); ++ ++ rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); ++} ++ ++static VOID ++_InitNormalChipOneOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ u16 value = 0; ++ switch(pHalData->OutEpQueueSel) ++ { ++ case TX_SELE_HQ: ++ value = QUEUE_HIGH; ++ break; ++ case TX_SELE_LQ: ++ value = QUEUE_LOW; ++ break; ++ case TX_SELE_NQ: ++ value = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ _InitNormalChipRegPriority(Adapter, ++ value, ++ value, ++ value, ++ value, ++ value, ++ value ++ ); ++ ++} ++ ++static VOID ++_InitNormalChipTwoOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; ++ ++ ++ u16 valueHi = 0; ++ u16 valueLow = 0; ++ ++ switch(pHalData->OutEpQueueSel) ++ { ++ case (TX_SELE_HQ | TX_SELE_LQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_NQ | TX_SELE_LQ): ++ valueHi = QUEUE_NORMAL; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_HQ | TX_SELE_NQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ if(!pregistrypriv->wifi_spec ){ ++ beQ = valueLow; ++ bkQ = valueLow; ++ viQ = valueHi; ++ voQ = valueHi; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE ++ beQ = valueLow; ++ bkQ = valueHi; ++ viQ = valueHi; ++ voQ = valueLow; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ ++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++ ++} ++ ++static VOID ++_InitNormalChipThreeOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; ++ ++ if(!pregistrypriv->wifi_spec ){// typical setting ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_LOW; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ else{// for WMM ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_NORMAL; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++} ++ ++static VOID ++_InitQueuePriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ switch(pHalData->OutEpNumber) ++ { ++ case 1: ++ _InitNormalChipOneOutEpPriority(Adapter); ++ break; ++ case 2: ++ _InitNormalChipTwoOutEpPriority(Adapter); ++ break; ++ case 3: ++ _InitNormalChipThreeOutEpPriority(Adapter); ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ ++} ++ ++ ++ ++static VOID ++_InitHardwareDropIncorrectBulkOut( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifdef ENABLE_USB_DROP_INCORRECT_OUT ++ u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK); ++ value32 |= DROP_DATA_EN; ++ rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32); ++#endif ++} ++ ++static VOID ++_InitNetworkType( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ ++ value32 = rtw_read32(Adapter, REG_CR); ++ // TODO: use the other function to set network type ++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); ++ ++ rtw_write32(Adapter, REG_CR, value32); ++// RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); ++} ++ ++static VOID ++_InitTransferPageSize( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Tx page size is always 128. ++ ++ u8 value8; ++ value8 = _PSRX(PBP_128) | _PSTX(PBP_128); ++ rtw_write8(Adapter, REG_PBP, value8); ++} ++ ++static VOID ++_InitDriverInfoSize( ++ IN PADAPTER Adapter, ++ IN u8 drvInfoSize ++ ) ++{ ++ rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize); ++} ++ ++static VOID ++_InitWMACSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ //u4Byte value32; ++ //u16 value16; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; ++ //pHalData->ReceiveConfig = ++ //RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; ++ // don't turn on AAP, it will allow all packets to driver ++ pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; ++ ++#if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC) ++ pHalData->ReceiveConfig |= ACRC32; ++#endif ++ ++ // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() ++ rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); ++ ++ // Accept all multicast address ++ rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF); ++ rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); ++ ++ ++ // Accept all data frames ++ //value16 = 0xFFFF; ++ //rtw_write16(Adapter, REG_RXFLTMAP2, value16); ++ ++ // 2010.09.08 hpfan ++ // Since ADF is removed from RCR, ps-poll will not be indicate to driver, ++ // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. ++ //value16 = 0x400; ++ //rtw_write16(Adapter, REG_RXFLTMAP1, value16); ++ ++ // Accept all management frames ++ //value16 = 0xFFFF; ++ //rtw_write16(Adapter, REG_RXFLTMAP0, value16); ++ ++ //enable RX_SHIFT bits ++ //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1)); ++ ++} ++ ++static VOID ++_InitAdaptiveCtrl( ++ IN PADAPTER Adapter ++ ) ++{ ++ u16 value16; ++ u32 value32; ++ ++ // Response Rate Set ++ value32 = rtw_read32(Adapter, REG_RRSR); ++ value32 &= ~RATE_BITMAP_ALL; ++ value32 |= RATE_RRSR_CCK_ONLY_1M; ++ rtw_write32(Adapter, REG_RRSR, value32); ++ ++ // CF-END Threshold ++ //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); ++ ++ // SIFS (used in NAV) ++ value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); ++ rtw_write16(Adapter, REG_SPEC_SIFS, value16); ++ ++ // Retry Limit ++ value16 = _LRL(0x30) | _SRL(0x30); ++ rtw_write16(Adapter, REG_RL, value16); ++ ++} ++ ++static VOID ++_InitRateFallback( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Set Data Auto Rate Fallback Retry Count register. ++ rtw_write32(Adapter, REG_DARFRC, 0x00000000); ++ rtw_write32(Adapter, REG_DARFRC+4, 0x10080404); ++ rtw_write32(Adapter, REG_RARFRC, 0x04030201); ++ rtw_write32(Adapter, REG_RARFRC+4, 0x08070605); ++ ++} ++ ++ ++static VOID ++_InitEDCA( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Set Spec SIFS (used in NAV) ++ rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a); ++ rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a); ++ ++ // Set SIFS for CCK ++ rtw_write16(Adapter,REG_SIFS_CTX, 0x100a); ++ ++ // Set SIFS for OFDM ++ rtw_write16(Adapter,REG_SIFS_TRX, 0x100a); ++ ++ // TXOP ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); ++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); ++ rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); ++ rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); ++} ++ ++ ++static VOID ++_InitBeaconMaxError( ++ IN PADAPTER Adapter, ++ IN BOOLEAN InfraMode ++ ) ++{ ++ ++} ++ ++ ++#ifdef CONFIG_LED ++static void _InitHWLed(PADAPTER Adapter) ++{ ++ struct led_priv *pledpriv = &(Adapter->ledpriv); ++ ++ if( pledpriv->LedStrategy != HW_LED) ++ return; ++ ++// HW led control ++// to do .... ++//must consider cases of antenna diversity/ commbo card/solo card/mini card ++ ++} ++#endif //CONFIG_LED ++ ++static VOID ++_InitRDGSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ rtw_write8(Adapter,REG_RD_CTRL,0xFF); ++ rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200); ++ rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05); ++} ++ ++static VOID ++_InitRxSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ rtw_write32(Adapter, REG_MACID, 0x87654321); ++ rtw_write32(Adapter, 0x0700, 0x87654321); ++} ++ ++static VOID ++_InitRetryFunction( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 value8; ++ //#if 0 //MAC SPEC ++ value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL); ++ value8 |= EN_AMPDU_RTY_NEW; ++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); ++ //#endif ++ // Set ACK timeout ++ rtw_write8(Adapter, REG_ACKTO, 0x40); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: usb_AggSettingTxUpdate() ++ * ++ * Overview: Seperate TX/RX parameters update independent for TP detection and ++ * dynamic TX/RX aggreagtion parameters update. ++ * ++ * Input: PADAPTER ++ * ++ * Output/Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Seperate to smaller function. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++usb_AggSettingTxUpdate( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u32 value32; ++ ++ if(Adapter->registrypriv.wifi_spec) ++ pHalData->UsbTxAggMode = _FALSE; ++ ++ if(pHalData->UsbTxAggMode){ ++ value32 = rtw_read32(Adapter, REG_TDECTRL); ++ value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT); ++ value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT); ++ ++ rtw_write32(Adapter, REG_TDECTRL, value32); ++ } ++ ++#endif ++} // usb_AggSettingTxUpdate ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: usb_AggSettingRxUpdate() ++ * ++ * Overview: Seperate TX/RX parameters update independent for TP detection and ++ * dynamic TX/RX aggreagtion parameters update. ++ * ++ * Input: PADAPTER ++ * ++ * Output/Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Seperate to smaller function. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++usb_AggSettingRxUpdate( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u8 valueDMA; ++ u8 valueUSB; ++ ++ valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL); ++ valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION); ++ ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ valueDMA |= RXDMA_AGG_EN; ++ valueUSB &= ~USB_AGG_EN; ++ break; ++ case USB_RX_AGG_USB: ++ valueDMA &= ~RXDMA_AGG_EN; ++ valueUSB |= USB_AGG_EN; ++ break; ++ case USB_RX_AGG_MIX: ++ valueDMA |= RXDMA_AGG_EN; ++ valueUSB |= USB_AGG_EN; ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ valueDMA &= ~RXDMA_AGG_EN; ++ valueUSB &= ~USB_AGG_EN; ++ break; ++ } ++ ++ rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA); ++ rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB); ++ ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount); ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, pHalData->UsbRxAggPageTimeout); ++ break; ++ case USB_RX_AGG_USB: ++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount); ++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout); ++ break; ++ case USB_RX_AGG_MIX: ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount); ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));//0x280[12:8] ++ ++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount); ++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout); ++ ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ // TODO: ++ break; ++ } ++ ++ switch(PBP_128) ++ { ++ case PBP_128: ++ pHalData->HwRxPageSize = 128; ++ break; ++ case PBP_64: ++ pHalData->HwRxPageSize = 64; ++ break; ++ case PBP_256: ++ pHalData->HwRxPageSize = 256; ++ break; ++ case PBP_512: ++ pHalData->HwRxPageSize = 512; ++ break; ++ case PBP_1024: ++ pHalData->HwRxPageSize = 1024; ++ break; ++ default: ++ //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n")); ++ break; ++ } ++#endif ++} // usb_AggSettingRxUpdate ++ ++static VOID ++InitUsbAggregationSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // Tx aggregation setting ++ usb_AggSettingTxUpdate(Adapter); ++ ++ // Rx aggregation setting ++ usb_AggSettingRxUpdate(Adapter); ++ ++ // 201/12/10 MH Add for USB agg mode dynamic switch. ++ pHalData->UsbRxHighSpeedMode = _FALSE; ++} ++VOID ++HalRxAggr8188EUsb( ++ IN PADAPTER Adapter, ++ IN BOOLEAN Value ++ ) ++{ ++#if 0//USB_RX_AGGREGATION_92C ++ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ u1Byte valueDMATimeout; ++ u1Byte valueDMAPageCount; ++ u1Byte valueUSBTimeout; ++ u1Byte valueUSBBlockCount; ++ ++ // selection to prevent bad TP. ++ if( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg) ++ { ++ // 2010.04.27 hpfan ++ // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer ++ // Timeout value is calculated by 34 / (2^n) ++ valueDMATimeout = 0x0f; ++ valueDMAPageCount = 0x01; ++ valueUSBTimeout = 0x0f; ++ valueUSBBlockCount = 0x01; ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount); ++ } ++ else ++ { ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout); ++ rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount); ++ } ++ ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: USB_AggModeSwitch() ++ * ++ * Overview: When RX traffic is more than 40M, we need to adjust some parameters to increase ++ * RX speed by increasing batch indication size. This will decrease TCP ACK speed, we ++ * need to monitor the influence of FTP/network share. ++ * For TX mode, we are still ubder investigation. ++ * ++ * Input: PADAPTER ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++USB_AggModeSwitch( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ ++ //pHalData->UsbRxHighSpeedMode = FALSE; ++ // How to measure the RX speed? We assume that when traffic is more than ++ if (pMgntInfo->bRegAggDMEnable == FALSE) ++ { ++ return; // Inf not support. ++ } ++ ++ ++ if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE && ++ pHalData->UsbRxHighSpeedMode == FALSE) ++ { ++ pHalData->UsbRxHighSpeedMode = TRUE; ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n")); ++ } ++ else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE && ++ pHalData->UsbRxHighSpeedMode == TRUE) ++ { ++ pHalData->UsbRxHighSpeedMode = FALSE; ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n")); ++ } ++ else ++ { ++ return; ++ } ++ ++ ++#if USB_RX_AGGREGATION_92C ++ if (pHalData->UsbRxHighSpeedMode == TRUE) ++ { ++ // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator. ++ // USB mode ++#if (RT_PLATFORM == PLATFORM_LINUX) ++ if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic) ++ { ++ pHalData->RxAggBlockCount = 16; ++ pHalData->RxAggBlockTimeout = 7; ++ } ++ else ++#endif ++ { ++ pHalData->RxAggBlockCount = 40; ++ pHalData->RxAggBlockTimeout = 5; ++ } ++ // Mix mode ++ pHalData->RxAggPageCount = 72; ++ pHalData->RxAggPageTimeout = 6; ++ } ++ else ++ { ++ // USB mode ++ pHalData->RxAggBlockCount = pMgntInfo->RegRxAggBlockCount; ++ pHalData->RxAggBlockTimeout = pMgntInfo->RegRxAggBlockTimeout; ++ // Mix mode ++ pHalData->RxAggPageCount = pMgntInfo->RegRxAggPageCount; ++ pHalData->RxAggPageTimeout = pMgntInfo->RegRxAggPageTimeout; ++ } ++ ++ if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT) ++ pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT; ++#if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX) // do not support WINXP to prevent usbehci.sys BSOD ++ if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter)) ++ { ++ // ++ // 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test ++ // with the aggregation dynamic change!! We need to disable the function to prevent it is broken ++ // in usbehci.sys. ++ // ++ usb_AggSettingRxUpdate_8188E(Adapter); ++ ++ // 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse ++ // there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the ++ // issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may ++ // BSOD. ++ } ++#endif ++ ++#endif ++#endif ++} // USB_AggModeSwitch ++ ++static VOID ++_InitOperationMode( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0//gtest ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ u1Byte regBwOpMode = 0; ++ u4Byte regRATR = 0, regRRSR = 0; ++ ++ ++ //1 This part need to modified according to the rate set we filtered!! ++ // ++ // Set RRSR, RATR, and REG_BWOPMODE registers ++ // ++ switch(Adapter->RegWirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK; ++ regRRSR = RATE_ALL_CCK; ++ break; ++ case WIRELESS_MODE_A: ++ regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_G: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_AUTO: ++ if (Adapter->bInHctTest) ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ else ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ break; ++ case WIRELESS_MODE_N_24G: ++ // It support CCK rate by default. ++ // CCK rate will be filtered out only when associated AP does not support it. ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_N_5G: ++ regBwOpMode = BW_OPMODE_5G; ++ regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_OFDM_AG; ++ break; ++ ++ default: //for MacOSX compiler warning. ++ break; ++ } ++ ++ // Ziv ???????? ++ //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR); ++ PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode); ++#endif ++} ++ ++ ++ static VOID ++_InitBeaconParameters( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ rtw_write16(Adapter, REG_BCN_CTRL, 0x1010); ++ ++ // TODO: Remove these magic number ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms ++ rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);// 5ms ++ rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); // 2ms ++ ++ // Suggested by designer timchen. Change beacon AIFS to the largest number ++ // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 ++ rtw_write16(Adapter, REG_BCNTCFG, 0x660F); ++ ++ pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL); ++ pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE); ++ pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2); ++ pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2); ++ pHalData->RegCR_1 = rtw_read8(Adapter, REG_CR+1); ++} ++ ++static VOID ++_InitRFType( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++ return; ++#endif ++ ++ pHalData->rf_chip = RF_6052; ++ ++ if(_FALSE == is92CU){ ++ pHalData->rf_type = RF_1T1R; ++ DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); ++ return; ++ } ++ ++ // TODO: Consider that EEPROM set 92CU to 1T1R later. ++ // Force to overwrite setting according to chip version. Ignore EEPROM setting. ++ //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; ++ MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type); ++ ++} ++ ++ ++static VOID ++_BeaconFunctionEnable( ++ IN PADAPTER Adapter, ++ IN BOOLEAN Enable, ++ IN BOOLEAN Linked ++ ) ++{ ++ rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); ++ //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00); ++ //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550))); ++ ++ rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F); ++} ++ ++ ++// Set CCK and OFDM Block "ON" ++static VOID _BBTurnOnBlock( ++ IN PADAPTER Adapter ++ ) ++{ ++#if (DISABLE_BB_RF) ++ return; ++#endif ++ ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); ++} ++ ++static VOID _RfPowerSave( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u1Byte eRFPath; ++ ++#if (DISABLE_BB_RF) ++ return; ++#endif ++ ++ if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry. ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n")); ++ MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW); ++ // Those action will be discard in MgntActSet_RF_State because off the same state ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); ++ } ++ else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep. ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason)); ++ MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason); ++ } ++ else{ ++ pHalData->eRFPowerState = eRfOn; ++ pMgntInfo->RfOffReason = 0; ++ if(Adapter->bInSetPower || Adapter->bResetInProgress) ++ PlatformUsbEnableInPipes(Adapter); ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n")); ++ } ++#endif ++} ++ ++enum { ++ Antenna_Lfet = 1, ++ Antenna_Right = 2, ++}; ++ ++static VOID ++_InitAntenna_Selection(IN PADAPTER Adapter) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(pHalData->AntDivCfg==0) ++ return; ++ DBG_8192C("==> %s ....\n",__FUNCTION__); ++ ++ rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23); ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ ++ if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) ++ pHalData->CurAntenna = Antenna_A; ++ else ++ pHalData->CurAntenna = Antenna_B; ++ DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == Antenna_A)?"Antenna_A":"Antenna_B"); ++ ++ ++} ++ ++// ++// 2010/08/26 MH Add for selective suspend mode check. ++// If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and ++// slim card. ++// ++static VOID ++HalDetectSelectiveSuspendMode( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ u8 tmpvalue; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); ++ ++ // If support HW radio detect, we need to enable WOL ability, otherwise, we ++ // can not use FW to notify host the power state switch. ++ ++ EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue); ++ ++ DBG_8192C("HalDetectSelectiveSuspendMode(): SS "); ++ if(tmpvalue & BIT1) ++ { ++ DBG_8192C("Enable\n"); ++ } ++ else ++ { ++ DBG_8192C("Disable\n"); ++ pdvobjpriv->RegUsbSS = _FALSE; ++ } ++ ++ // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode. ++ if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData)) ++ { ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ ++ //if (!pMgntInfo->bRegDongleSS) ++ //{ ++ // RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n")); ++ pdvobjpriv->RegUsbSS = _FALSE; ++ //} ++ } ++#endif ++} // HalDetectSelectiveSuspendMode ++/*----------------------------------------------------------------------------- ++ * Function: HwSuspendModeEnable92Cu() ++ * ++ * Overview: HW suspend mode switch. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 08/23/2010 MHC HW suspend mode switch test.. ++ *---------------------------------------------------------------------------*/ ++static VOID ++HwSuspendModeEnable_88eu( ++ IN PADAPTER pAdapter, ++ IN u8 Type ++ ) ++{ ++ //PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); ++ u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG); ++ ++ //if (!pDevice->RegUsbSS) ++ { ++ return; ++ } ++ ++ // ++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW ++ // to enter suspend mode automatically. Otherwise, it will shut down major power ++ // domain and 8051 will stop. When we try to enter selective suspend mode, we ++ // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will ++ // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). ++ // We need to enable HW suspend mode when enter S3/S4 or disable. We need ++ // to disable HW suspend mode for IPS/radio_off. ++ // ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); ++ if (Type == _FALSE) ++ { ++ reg |= BIT14; ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ reg |= BIT12; ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ } ++ else ++ { ++ reg &= (~BIT12); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ reg &= (~BIT14); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ } ++ ++} // HwSuspendModeEnable92Cu ++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 val8; ++ rt_rf_power_state rfpowerstate = rf_off; ++ ++ if(adapter_to_pwrctl(pAdapter)->bHWPowerdown) ++ { ++ val8 = rtw_read8(pAdapter, REG_HSISR); ++ DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8); ++ rfpowerstate = (val8 & BIT7) ? rf_off: rf_on; ++ } ++ else // rf on/off ++ { ++ rtw_write8( pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3)); ++ val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL); ++ DBG_8192C("GPIO_IN=%02x\n", val8); ++ rfpowerstate = (val8 & BIT3) ? rf_on : rf_off; ++ } ++ return rfpowerstate; ++} // HalDetectPwrDownMode ++ ++void _ps_open_RF(_adapter *padapter); ++ ++u32 rtl8188eu_hal_init(PADAPTER Adapter) ++{ ++ u8 value8 = 0; ++ u16 value16; ++ u8 txpktbuf_bndy; ++ u32 status = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ ++ rt_rf_power_state eRfPowerStateToSet; ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ ++ u32 init_start_time = rtw_get_current_time(); ++ ++ ++#ifdef DBG_HAL_INIT_PROFILING ++ ++ enum HAL_INIT_STAGES { ++ HAL_INIT_STAGES_BEGIN = 0, ++ HAL_INIT_STAGES_INIT_PW_ON, ++ HAL_INIT_STAGES_MISC01, ++ HAL_INIT_STAGES_DOWNLOAD_FW, ++ HAL_INIT_STAGES_MAC, ++ HAL_INIT_STAGES_BB, ++ HAL_INIT_STAGES_RF, ++ HAL_INIT_STAGES_EFUSE_PATCH, ++ HAL_INIT_STAGES_INIT_LLTT, ++ ++ HAL_INIT_STAGES_MISC02, ++ HAL_INIT_STAGES_TURN_ON_BLOCK, ++ HAL_INIT_STAGES_INIT_SECURITY, ++ HAL_INIT_STAGES_MISC11, ++ HAL_INIT_STAGES_INIT_HAL_DM, ++ //HAL_INIT_STAGES_RF_PS, ++ HAL_INIT_STAGES_IQK, ++ HAL_INIT_STAGES_PW_TRACK, ++ HAL_INIT_STAGES_LCK, ++ //HAL_INIT_STAGES_MISC21, ++ //HAL_INIT_STAGES_INIT_PABIAS, ++ #ifdef CONFIG_BT_COEXIST ++ HAL_INIT_STAGES_BT_COEXIST, ++ #endif ++ //HAL_INIT_STAGES_ANTENNA_SEL, ++ //HAL_INIT_STAGES_MISC31, ++ HAL_INIT_STAGES_END, ++ HAL_INIT_STAGES_NUM ++ }; ++ ++ char * hal_init_stages_str[] = { ++ "HAL_INIT_STAGES_BEGIN", ++ "HAL_INIT_STAGES_INIT_PW_ON", ++ "HAL_INIT_STAGES_MISC01", ++ "HAL_INIT_STAGES_DOWNLOAD_FW", ++ "HAL_INIT_STAGES_MAC", ++ "HAL_INIT_STAGES_BB", ++ "HAL_INIT_STAGES_RF", ++ "HAL_INIT_STAGES_EFUSE_PATCH", ++ "HAL_INIT_STAGES_INIT_LLTT", ++ "HAL_INIT_STAGES_MISC02", ++ "HAL_INIT_STAGES_TURN_ON_BLOCK", ++ "HAL_INIT_STAGES_INIT_SECURITY", ++ "HAL_INIT_STAGES_MISC11", ++ "HAL_INIT_STAGES_INIT_HAL_DM", ++ //"HAL_INIT_STAGES_RF_PS", ++ "HAL_INIT_STAGES_IQK", ++ "HAL_INIT_STAGES_PW_TRACK", ++ "HAL_INIT_STAGES_LCK", ++ //"HAL_INIT_STAGES_MISC21", ++ #ifdef CONFIG_BT_COEXIST ++ "HAL_INIT_STAGES_BT_COEXIST", ++ #endif ++ //"HAL_INIT_STAGES_ANTENNA_SEL", ++ //"HAL_INIT_STAGES_MISC31", ++ "HAL_INIT_STAGES_END", ++ }; ++ ++ int hal_init_profiling_i; ++ u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_iwowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON); ++ DBG_8192C("%s wowlan_wake_reason: 0x%02x\n", ++ __func__, pwrctrlpriv->wowlan_wake_reason); ++ ++ if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7){ /*&& ++ (pwrctrlpriv->wowlan_wake_reason & FWDecisionDisconnect)) {*/ ++ u8 reg_val=0; ++ DBG_8192C("+Reset Entry+\n"); ++ rtw_write8(Adapter, REG_MCUFWDL, 0x00); ++ _8051Reset88E(Adapter); ++ //reset BB ++ reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN); ++ reg_val &= ~(BIT(0) | BIT(1)); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, reg_val); ++ //reset RF ++ rtw_write8(Adapter, REG_RF_CTRL, 0); ++ //reset TRX path ++ rtw_write16(Adapter, REG_CR, 0); ++ //reset MAC, Digital Core ++ reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ reg_val &= ~(BIT(4) | BIT(7)); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val); ++ reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ reg_val |= BIT(4) | BIT(7); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val); ++ DBG_8192C("-Reset Entry-\n"); ++ } ++#endif //CONFIG_WOWLAN ++ ++ if(pwrctrlpriv->bkeepfwalive) ++ { ++ _ps_open_RF(Adapter); ++ ++ if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){ ++// PHY_IQCalibrate(padapter, _TRUE); ++ PHY_IQCalibrate_8188E(Adapter,_TRUE); ++ } ++ else ++ { ++// PHY_IQCalibrate(padapter, _FALSE); ++ PHY_IQCalibrate_8188E(Adapter,_FALSE); ++ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE; ++ } ++ ++// dm_CheckTXPowerTracking(padapter); ++// PHY_LCCalibrate(padapter); ++ ODM_TXPowerTrackingCheck(&pHalData->odmpriv ); ++ PHY_LCCalibrate_8188E(Adapter); ++ ++ goto exit; ++ } ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); ++ status = InitPowerOn_rtl8188eu(Adapter); ++ if(status == _FAIL){ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n")); ++ goto exit; ++ } ++ ++ // Save target channel ++ pHalData->CurrentChannel = 6;//default set to 6 ++ ++ ++ if(pwrctrlpriv->reg_rfoff == _TRUE){ ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ } ++ ++ // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting ++ // HW GPIO pin. Before PHY_RFConfig8192C. ++ //HalDetectPwrDownMode(Adapter); ++ // 2010/08/26 MH If Efuse does not support sective suspend then disable the function. ++ //HalDetectSelectiveSuspendMode(Adapter); ++ ++ if (!pregistrypriv->wifi_spec) { ++ txpktbuf_bndy = TX_PAGE_BOUNDARY_88E; ++ } else { ++ // for WMM ++ txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); ++ _InitQueueReservedPage(Adapter); ++ _InitQueuePriority(Adapter); ++ _InitPageBoundary(Adapter); ++ _InitTransferPageSize(Adapter); ++ ++#ifdef CONFIG_IOL_IOREG_CFG ++ _InitTxBufferBoundary(Adapter, 0); ++#endif ++ ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); ++#if (MP_DRIVER == 1) ++ if (Adapter->registrypriv.mp_mode == 1) ++ { ++ _InitRxSetting(Adapter); ++ } ++#endif //MP_DRIVER == 1 ++ { ++ #if 0 ++ Adapter->bFWReady = _FALSE; //because no fw for test chip ++ pHalData->fw_ractrl = _FALSE; ++ #else ++ ++#ifdef CONFIG_WOWLAN ++ status = rtl8188e_FirmwareDownload(Adapter, _FALSE); ++#else ++ status = rtl8188e_FirmwareDownload(Adapter); ++#endif //CONFIG_WOWLAN ++ ++ if (status != _SUCCESS) { ++ DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__); ++ Adapter->bFWReady = _FALSE; ++ pHalData->fw_ractrl = _FALSE; ++ return status; ++ } else { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n")); ++ Adapter->bFWReady = _TRUE; ++ pHalData->fw_ractrl = _FALSE; ++ } ++ #endif ++ } ++ ++ ++ rtl8188e_InitializeFirmwareVars(Adapter); ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); ++#if (HAL_MAC_ENABLE == 1) ++ status = PHY_MACConfig8188E(Adapter); ++ if(status == _FAIL) ++ { ++ DBG_871X(" ### Failed to init MAC ...... \n "); ++ goto exit; ++ } ++#endif ++ ++ // ++ //d. Initialize BB related configurations. ++ // ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); ++#if (HAL_BB_ENABLE == 1) ++ status = PHY_BBConfig8188E(Adapter); ++ if(status == _FAIL) ++ { ++ DBG_871X(" ### Failed to init BB ...... \n "); ++ goto exit; ++ } ++#endif ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); ++#if (HAL_RF_ENABLE == 1) ++ status = PHY_RFConfig8188E(Adapter); ++ if(status == _FAIL) ++ { ++ DBG_871X(" ### Failed to init RF ...... \n "); ++ goto exit; ++ } ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH); ++#if defined(CONFIG_IOL_EFUSE_PATCH) ++ status = rtl8188e_iol_efuse_patch(Adapter); ++ if(status == _FAIL){ ++ DBG_871X("%s rtl8188e_iol_efuse_patch failed \n",__FUNCTION__); ++ goto exit; ++ } ++#endif ++ ++ _InitTxBufferBoundary(Adapter, txpktbuf_bndy); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); ++ status = InitLLTTable(Adapter, txpktbuf_bndy); ++ if(status == _FAIL){ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n")); ++ goto exit; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); ++ // Get Rx PHY status in order to report RSSI and others. ++ _InitDriverInfoSize(Adapter, DRVINFO_SZ); ++ ++ _InitInterrupt(Adapter); ++ hal_init_macaddr(Adapter);//set mac_address ++ _InitNetworkType(Adapter);//set msr ++ _InitWMACSetting(Adapter); ++ _InitAdaptiveCtrl(Adapter); ++ _InitEDCA(Adapter); ++ //_InitRateFallback(Adapter);//just follow MP Team ???Georgia ++ _InitRetryFunction(Adapter); ++ InitUsbAggregationSetting(Adapter); ++ _InitOperationMode(Adapter);//todo ++ _InitBeaconParameters(Adapter); ++ _InitBeaconMaxError(Adapter, _TRUE); ++ ++ // ++ // Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch ++ // Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. ++ // ++ // Enable MACTXEN/MACRXEN block ++ value16 = rtw_read16(Adapter, REG_CR); ++ value16 |= (MACTXEN | MACRXEN); ++ rtw_write8(Adapter, REG_CR, value16); ++ ++ ++ _InitHardwareDropIncorrectBulkOut(Adapter); ++ ++ ++ if(pHalData->bRDGEnable){ ++ _InitRDGSetting(Adapter); ++ } ++ ++#if (RATE_ADAPTIVE_SUPPORT==1) ++ {//Enable TX Report ++ //Enable Tx Report Timer ++ value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL); ++ rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); ++ //Set MAX RPT MACID ++ rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP ++ //Tx RPT Timer. Unit: 32us ++ rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0); ++ } ++#endif ++ ++#if 0 ++ if(pHTInfo->bRDGEnable){ ++ _InitRDGSetting_8188E(Adapter); ++ } ++#endif ++ ++#ifdef CONFIG_TX_EARLY_MODE ++ if( pHalData->bEarlyModeEnable) ++ { ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n")); ++ ++ value8 = rtw_read8(Adapter, REG_EARLY_MODE_CONTROL); ++#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 ++ value8 = value8|0x1f; ++#else ++ value8 = value8|0xf; ++#endif ++ rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, value8); ++ ++ rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x80); ++ ++ value8 = rtw_read8(Adapter, REG_TCR+1); ++ value8 = value8|0x40; ++ rtw_write8(Adapter,REG_TCR+1, value8); ++ } ++ else ++#endif ++ { ++ rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0); ++ } ++ ++ rtw_write32(Adapter,REG_MACID_NO_LINK_0,0xFFFFFFFF); ++ rtw_write32(Adapter,REG_MACID_NO_LINK_1,0xFFFFFFFF); ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) ++ ++#ifdef CONFIG_CHECK_AC_LIFETIME ++ // Enable lifetime check for the four ACs ++ rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F); ++#endif // CONFIG_CHECK_AC_LIFETIME ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++#else // CONFIG_TX_MCAST2UNI ++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s ++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s ++#endif // CONFIG_TX_MCAST2UNI ++#endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI ++ ++ ++#ifdef CONFIG_LED ++ _InitHWLed(Adapter); ++#endif //CONFIG_LED ++ ++ ++ // ++ // Joseph Note: Keep RfRegChnlVal for later use. ++ // ++ pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask); ++ pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); ++ _BBTurnOnBlock(Adapter); ++ //NicIFSetMacAddress(padapter, padapter->PermanentAddress); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); ++ invalidate_cam_all(Adapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); ++ // 2010/12/17 MH We need to set TX power according to EFUSE content at first. ++ PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel); ++ ++// Move by Neo for USB SS to below setp ++//_RfPowerSave(Adapter); ++ ++ _InitAntenna_Selection(Adapter); ++ ++ // ++ // Disable BAR, suggested by Scott ++ // 2010.04.09 add by hpfan ++ // ++ rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); ++ ++ // HW SEQ CTRL ++ //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. ++ rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF); ++ ++ if(pregistrypriv->wifi_spec) ++ rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0); ++ ++ //Nav limit , suggest by scott ++ rtw_write8(Adapter, 0x652, 0x0); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); ++ rtl8188e_InitHalDm(Adapter); ++ ++#if (MP_DRIVER == 1) ++ if (Adapter->registrypriv.mp_mode == 1) ++ { ++ Adapter->mppriv.channel = pHalData->CurrentChannel; ++ MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel); ++ } ++ else ++#endif //#if (MP_DRIVER == 1) ++ { ++ // ++ // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status ++ // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not ++ // call init_adapter. May cause some problem?? ++ // ++ // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed ++ // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState ++ // is the same as eRfOff, we should change it to eRfOn after we config RF parameters. ++ // Added by tynli. 2010.03.30. ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ ++#if 0 //to do ++ RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC); ++#if 1 //Todo ++ // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off. ++ // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization. ++ ++ eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter); ++ pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW; ++ pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0; ++ ++ if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW) ++ pwrctrlpriv->b_hw_radio_off = _TRUE; ++ ++ DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet); ++ ++ if(pwrctrlpriv->reg_rfoff == _TRUE) ++ { // User disable RF via registry. ++ DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n"); ++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE); ++ ++ // Those action will be discard in MgntActSet_RF_State because off the same state ++ //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); ++ } ++ else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS) ++ { // H/W or S/W RF OFF before sleep. ++ DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason); ++ //pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ //MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ else ++ { ++ // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09. ++ if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/) ++ { ++ DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet); ++ if (eRfPowerStateToSet == rf_off) ++ { ++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE); ++ pwrctrlpriv->b_hw_radio_off = _TRUE; ++ } ++ else ++ { ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ pwrctrlpriv->b_hw_radio_off = _FALSE; ++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ } ++ else ++ { ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ ++ pwrctrlpriv->rfoff_reason = 0; ++ pwrctrlpriv->b_hw_radio_off = _FALSE; ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ rtw_led_control(Adapter, LED_CTL_POWER_ON); ++ ++ } ++ ++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. ++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. ++ if(pHalData->pwrdown && eRfPowerStateToSet == rf_off) ++ { ++ // Enable register area 0x0-0xc. ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0); ++ ++ // ++ // We should configure HW PDn source for WiFi ONLY, and then ++ // our HW will be set in power-down mode if PDn source from all functions are configured. ++ // 2010.10.06. ++ // ++ //if(IS_HARDWARE_TYPE_8723AU(Adapter)) ++ //{ ++ // u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL); ++ // rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN)); ++ //} ++ //else ++ //{ ++ rtw_write16(Adapter, REG_APS_FSMCO, 0x8812); ++ //} ++ } ++ //DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD. ++#endif ++#endif ++ ++ ++ // enable Tx report. ++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F); ++ ++ // Suggested by SD1 pisa. Added by tynli. 2011.10.21. ++ rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);//Pretx_en, for WEP/TKIP SEC ++ ++ //tynli_test_tx_report. ++ rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0); ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n")); ++ ++ //enable tx DMA to drop the redundate data of packet ++ rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN)); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); ++ // 2010/08/26 MH Merge from 8192CE. ++ if(pwrctrlpriv->rf_pwrstate == rf_on) ++ { ++ if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){ ++ PHY_IQCalibrate_8188E(Adapter,_TRUE); ++ } ++ else ++ { ++ PHY_IQCalibrate_8188E(Adapter,_FALSE); ++ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); ++ ++ ODM_TXPowerTrackingCheck(&pHalData->odmpriv ); ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); ++ PHY_LCCalibrate_8188E(Adapter); ++ } ++} ++ ++//HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); ++// _InitPABias(Adapter); ++ rtw_write8(Adapter, REG_USB_HRPWM, 0); ++ ++#ifdef CONFIG_XMIT_ACK ++ //ack for xmit mgmt frames. ++ rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12)); ++#endif //CONFIG_XMIT_ACK ++ ++exit: ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); ++ ++ DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time)); ++ ++ #ifdef DBG_HAL_INIT_PROFILING ++ hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time(); ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_iMgntInfo); ++ u8 val8; ++ u16 val16; ++ u32 val32; ++ u8 bMacPwrCtrlOn=_FALSE; ++ ++ rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if(bMacPwrCtrlOn == _FALSE) ++ return ; ++ ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n",__FUNCTION__)); ++ ++ //Stop Tx Report Timer. 0x4EC[Bit1]=b'0 ++ val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL); ++ rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1)); ++ ++ // stop rx ++ rtw_write8(Adapter, REG_CR, 0x0); ++ ++ // Run LPS WL RFOFF flow ++ HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW); ++ ++ ++ // 2. 0x1F[7:0] = 0 // turn off RF ++ //rtw_write8(Adapter, REG_RF_CTRL, 0x00); ++ ++ val8 = rtw_read8(Adapter, REG_MCUFWDL); ++ if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code ++ { ++ //rtl8723a_FirmwareSelfReset(padapter); ++ //_8051Reset88E(padapter); ++ ++ // Reset MCU 0x2[10]=0. ++ val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8); ++ } ++ ++ //val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ //val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN ++ //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8); ++ ++ // MCUFWDL 0x80[1:0]=0 ++ // reset MCU ready status ++ rtw_write8(Adapter, REG_MCUFWDL, 0); ++ ++ //YJ,add,111212 ++ //Disable 32k ++ val8 = rtw_read8(Adapter, REG_32K_CTRL); ++ rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0)); ++ ++ // Card disable power action flow ++ HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW); ++ ++ // Reset MCU IO Wrapper ++ val8 = rtw_read8(Adapter, REG_RSV_CTRL+1); ++ rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3))); ++ val8 = rtw_read8(Adapter, REG_RSV_CTRL+1); ++ rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3); ++ ++#if 0 ++ // 7. RSV_CTRL 0x1C[7:0] = 0x0E // lock ISO/CLK/Power control register ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0e); ++#endif ++#if 1 ++ //YJ,test add, 111207. For Power Consumption. ++ val8 = rtw_read8(Adapter, GPIO_IN); ++ rtw_write8(Adapter, GPIO_OUT, val8); ++ rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46 ++ ++ val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL); ++ //rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8); ++ rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)); ++ val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1); ++ rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43 ++ rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode ++#endif ++ bMacPwrCtrlOn = _FALSE; ++ rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ Adapter->bFWReady = _FALSE; ++} ++static void rtl8188eu_hw_power_down(_adapter *padapter) ++{ ++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. ++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. ++ ++ // Enable register area 0x0-0xc. ++ rtw_write8(padapter,REG_RSV_CTRL, 0x0); ++ rtw_write16(padapter, REG_APS_FSMCO, 0x8812); ++} ++ ++u32 rtl8188eu_hal_deinit(PADAPTER Adapter) ++ { ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ DBG_8192C("==> %s \n",__FUNCTION__); ++ ++#ifdef CONFIG_SUPPORT_USB_INT ++ rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E); ++ rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E); ++#endif ++ ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ DBG_8192C("bkeepfwalive(%x)\n", pwrctl->bkeepfwalive); ++ if(pwrctl->bkeepfwalive) ++ { ++ _ps_close_RF(Adapter); ++ if((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown)) ++ rtl8188eu_hw_power_down(Adapter); ++ } ++ else ++#endif ++ { ++ if(Adapter->hw_init_completed == _TRUE){ ++ hal_poweroff_rtl8188eu(Adapter); ++ ++ if((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown)) ++ rtl8188eu_hw_power_down(Adapter); ++ ++ } ++ } ++ return _SUCCESS; ++ } ++ ++ ++unsigned int rtl8188eu_inirp_init(PADAPTER Adapter) ++{ ++ u8 i; ++ struct recv_buf *precvbuf; ++ uint status; ++ struct dvobj_priv *pdev= adapter_to_dvobj(Adapter); ++ struct intf_hdl * pintfhdl=&Adapter->iopriv.intf; ++ struct recv_priv *precvpriv = &(Adapter->recvpriv); ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); ++#endif ++ ++_func_enter_; ++ ++ _read_port = pintfhdl->io_ops._read_port; ++ ++ status = _SUCCESS; ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n")); ++ ++ precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; ++ ++ //issue Rx irp to receive data ++ precvbuf = (struct recv_buf *)precvpriv->precv_buf; ++ for(i=0; iff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE ) ++ { ++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n")); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ precvbuf++; ++ precvpriv->free_recv_buf_queue_cnt--; ++ } ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ if(pHalData->RtIntInPipe != 0x05) ++ { ++ status = _FAIL; ++ DBG_871X("%s =>Warning !! Have not USB Int-IN pipe, pHalData->RtIntInPipe(%d)!!!\n",__FUNCTION__,pHalData->RtIntInPipe); ++ goto exit; ++ } ++ _read_interrupt = pintfhdl->io_ops._read_interrupt; ++ if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE ) ++ { ++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n")); ++ status = _FAIL; ++ } ++#endif ++ ++exit: ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n")); ++ ++_func_exit_; ++ ++ return status; ++ ++} ++ ++unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter) ++{ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n")); ++ ++ rtw_read_port_cancel(Adapter); ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n")); ++ ++ return _SUCCESS; ++} ++ ++ ++ ++//------------------------------------------------------------------------- ++// ++// EEPROM Power index mapping ++// ++//------------------------------------------------------------------------- ++#if 0 ++ static VOID ++_ReadPowerValueFromPROM( ++ IN PTxPowerInfo pwrInfo, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u32 rfPath, eeAddr, group; ++ ++ _rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo)); ++ ++ if(AutoLoadFail){ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){ ++ pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel; ++ pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel; ++ pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff; ++ pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff; ++ pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff; ++ pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset; ++ pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset; ++ } ++ } ++ ++ pwrInfo->TSSI_A = EEPROM_Default_TSSI; ++ pwrInfo->TSSI_B = EEPROM_Default_TSSI; ++ ++ return; ++ } ++ ++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group; ++ pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr]; ++ ++ eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group; ++ pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr]; ++ } ++ } ++ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){ ++ pwrInfo->HT40_2SIndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++ ++#if 1 ++ pwrInfo->HT20IndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++ if(pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0; ++#else ++ pwrInfo->HT20IndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++#endif ++ ++ pwrInfo->OFDMIndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF; ++ ++ pwrInfo->HT40MaxOffset[rfPath][group] = ++ (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF; ++ ++ pwrInfo->HT20MaxOffset[rfPath][group] = ++ (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF; ++ } ++ } ++ ++ pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A]; ++ pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B]; ++ ++} ++ ++ ++static u32 ++_GetChannelGroup( ++ IN u32 channel ++ ) ++{ ++ //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n")); ++ ++ if(channel < 3){ // Channel 1~3 ++ return 0; ++ } ++ else if(channel < 9){ // Channel 4~9 ++ return 1; ++ } ++ ++ return 2; // Channel 10~14 ++} ++ ++ ++static VOID ++ReadTxPowerInfo( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ TxPowerInfo pwrInfo; ++ u32 rfPath, ch, group; ++ u8 pwr, diff; ++ ++ _ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail); ++ ++ if(!AutoLoadFail) ++ pHalData->bTXPowerDataReadFromEEPORM = _TRUE; ++ ++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ group = _GetChannelGroup(ch); ++ ++ pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group]; ++ pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group]; ++ ++ pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group]; ++ pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group]; ++ pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group]; ++ pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group]; ++ ++ pwr = pwrInfo.HT40_1SIndex[rfPath][group]; ++ diff = pwrInfo.HT40_2SIndexDiff[rfPath][group]; ++ ++ pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0; ++ } ++ } ++ ++#if 0 //DBG ++ ++ for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ++ ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", ++ rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch], ++ pHalData->TxPwrLevelHT40_1S[rfPath][ch], ++ pHalData->TxPwrLevelHT40_2S[rfPath][ch])); ++ ++ } ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch])); ++ } ++ ++#endif ++ // 2010/10/19 MH Add Regulator recognize for CU. ++ if(!AutoLoadFail) ++ { ++ pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2 ++ } ++ else ++ { ++ pHalData->EEPROMRegulatory = 0; ++ } ++ DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory); ++ ++} ++#endif ++ ++//------------------------------------------------------------------- ++// ++// EEPROM/EFUSE Content Parsing ++// ++//------------------------------------------------------------------- ++static void ++_ReadIDs( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(_FALSE == AutoloadFail){ ++ // VID, PID ++ pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]); ++ pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]); ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID]; ++ pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID]; ++ ++ } ++ else{ ++ pHalData->EEPROMVID = EEPROM_Default_VID; ++ pHalData->EEPROMPID = EEPROM_Default_PID; ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID; ++ pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; ++ ++ } ++ ++ // For customized behavior. ++ if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo. ++ pHalData->CustomerID = RT_CID_819x_HP; ++ ++ // Decide CustomerID according to VID/DID or EEPROM ++ switch(pHalData->EEPROMCustomerID) ++ { ++ case EEPROM_CID_DEFAULT: ++ if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ break; ++ case EEPROM_CID_WHQL: ++/* ++ Adapter->bInHctTest = TRUE; ++ ++ pMgntInfo->bSupportTurboMode = FALSE; ++ pMgntInfo->bAutoTurboBy8186 = FALSE; ++ ++ pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ ++ pMgntInfo->keepAliveLevel = 0; ++ ++ Adapter->bUnloadDriverwhenS3S4 = FALSE; ++*/ ++ break; ++ default: ++ pHalData->CustomerID = RT_CID_DEFAULT; ++ break; ++ ++ } ++ ++ MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID); ++ MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID); ++ MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID); ++ MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID); ++ ++ MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID); ++#endif ++} ++ ++ ++static VOID ++_ReadMACAddress( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++#if 0 ++ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ ++ if(_FALSE == AutoloadFail){ ++ //Read Permanent MAC address and set value to hardware ++ _rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN); ++ } ++ else{ ++ //Random assigh MAC address ++ u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; ++ //sMacAddr[5] = (u8)GetRandomNumber(1, 254); ++ _rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN); ++ } ++ DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr)); ++ //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); ++ //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress); ++#endif ++} ++ ++static VOID ++_ReadBoardType( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ ++} ++ ++ ++static VOID ++_ReadLEDSetting( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ struct led_priv *pledpriv = &(Adapter->ledpriv); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#ifdef CONFIG_SW_LED ++ pledpriv->bRegUseLed = _TRUE; ++ ++ switch(pHalData->CustomerID) ++ { ++ default: ++ pledpriv->LedStrategy = SW_LED_MODE1; ++ break; ++ } ++ pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++#else // HW LED ++ pledpriv->LedStrategy = HW_LED; ++#endif //CONFIG_SW_LED ++} ++ ++static VOID ++_ReadThermalMeter( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 tempval; ++ ++ // ++ // ThermalMeter from EEPROM ++ // ++ if(!AutoloadFail) ++ tempval = PROMContent[EEPROM_THERMAL_METER]; ++ else ++ tempval = EEPROM_Default_ThermalMeter; ++ ++ pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0] ++ ++ if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail) ++ pdmpriv->bAPKThermalMeterIgnore = _TRUE; ++ ++#if 0 ++ if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c) ++ pHalData->EEPROMThermalMeter = 0x12; ++#endif ++ ++ pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter; ++ ++ //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter)); ++#endif ++} ++ ++static VOID ++_ReadRFSetting( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++} ++ ++static void ++_ReadPROMVersion( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(AutoloadFail){ ++ pHalData->EEPROMVersion = EEPROM_Default_Version; ++ } ++ else{ ++ pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION]; ++ } ++#endif ++} ++ ++static VOID ++readAntennaDiversity( ++ IN PADAPTER pAdapter, ++ IN u8 *hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct registry_priv *registry_par = &pAdapter->registrypriv; ++ ++ pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct registry_priv *registry_par = &pAdapter->registrypriv; ++ ++ if(!AutoLoadFail) ++ { ++ // Antenna Diversity setting. ++ if(registry_par->antdiv_cfg == 2) // 2: From Efuse ++ pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3; ++ else ++ pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, ++ ++ DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg); ++ ++ //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1) ++ // pHalData->AntDivCfg = 0; ++ } ++ else ++ { ++ pHalData->AntDivCfg = 0; ++ } ++#endif ++} ++ ++static VOID ++hal_InitPGData( ++ IN PADAPTER pAdapter, ++ IN OUT u8 *PROMContent ++ ) ++{ ++#if 0 ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u32 i; ++ u16 value16; ++ ++ if(_FALSE == pEEPROM->bautoload_fail_flag) ++ { // autoload OK. ++ if (_TRUE == pEEPROM->EepromOrEfuse) ++ { ++ // Read all Content from EEPROM or EFUSE. ++ for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2) ++ { ++ //value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1))); ++ //*((u16 *)(&PROMContent[i])) = value16; ++ } ++ } ++ else ++ { ++ // Read EFUSE real map to shadow. ++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE); ++ _rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E); ++ } ++ } ++ else ++ {//autoload fail ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n")); ++ pEEPROM->bautoload_fail_flag = _TRUE; ++ //update to default value 0xFF ++ if (_FALSE == pEEPROM->EepromOrEfuse) ++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE); ++ } ++#endif ++} ++static void ++Hal_EfuseParsePIDVID_8188EU( ++ IN PADAPTER pAdapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if( !AutoLoadFail ) ++ { ++ // VID, PID ++ pHalData->EEPROMVID = EF2Byte( *(u16 *)&hwinfo[EEPROM_VID_88EU] ); ++ pHalData->EEPROMPID = EF2Byte( *(u16 *)&hwinfo[EEPROM_PID_88EU] ); ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E]; ++ pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; ++ ++ } ++ else ++ { ++ pHalData->EEPROMVID = EEPROM_Default_VID; ++ pHalData->EEPROMPID = EEPROM_Default_PID; ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID; ++ pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; ++ ++ } ++ ++ DBG_871X("VID = 0x%04X, PID = 0x%04X\n", pHalData->EEPROMVID, pHalData->EEPROMPID); ++ DBG_871X("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", pHalData->EEPROMCustomerID, pHalData->EEPROMSubCustomerID); ++} ++ ++static void ++Hal_EfuseParseMACAddr_8188EU( ++ IN PADAPTER padapter, ++ IN u8* hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u16 i, usValue; ++ u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02}; ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ ++ if (AutoLoadFail) ++ { ++// sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254); ++ for (i=0; i<6; i++) ++ pEEPROM->mac_addr[i] = sMacAddr[i]; ++ } ++ else ++ { ++ //Read Permanent MAC address ++ _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN); ++ ++ } ++// NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress); ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ++ ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", ++ pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], ++ pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], ++ pEEPROM->mac_addr[4], pEEPROM->mac_addr[5])); ++} ++ ++ ++static void ++Hal_CustomizeByCustomerID_8188EU( ++ IN PADAPTER padapter ++ ) ++{ ++#if 0 ++ PMGNT_INFO pMgntInfo = &(padapter->MgntInfo); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ // For customized behavior. ++ if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo. ++ pMgntInfo->CustomerID = RT_CID_819x_HP; ++ ++ // Decide CustomerID according to VID/DID or EEPROM ++ switch(pHalData->EEPROMCustomerID) ++ { ++ case EEPROM_CID_DEFAULT: ++ if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308)) ++ pMgntInfo->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309)) ++ pMgntInfo->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a)) ++ pMgntInfo->CustomerID = RT_CID_DLINK; ++ break; ++ case EEPROM_CID_WHQL: ++ padapter->bInHctTest = TRUE; ++ ++ pMgntInfo->bSupportTurboMode = FALSE; ++ pMgntInfo->bAutoTurboBy8186 = FALSE; ++ ++ pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE; ++ pMgntInfo->keepAliveLevel = 0; ++ ++ padapter->bUnloadDriverwhenS3S4 = FALSE; ++ break; ++ default: ++ pMgntInfo->CustomerID = RT_CID_DEFAULT; ++ break; ++ ++ } ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pMgntInfo->CustomerID)); ++ ++ hal_CustomizedBehavior_8723U(padapter); ++#endif ++} ++ ++// Read HW power down mode selection ++static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail) ++{ ++#if 0 ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); ++ ++ if(AutoloadFail){ ++ pwrctl->bHWPowerdown = _FALSE; ++ pwrctl->bSupportRemoteWakeup = _FALSE; ++ } ++ else { ++ //if(SUPPORT_HW_RADIO_DETECT(Adapter)) ++ pwrctl->bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect; ++ //else ++ //pwrctl->bHWPwrPindetect = _FALSE;//dongle not support new ++ ++ ++ //hw power down mode selection , 0:rf-off / 1:power down ++ ++ if(Adapter->registrypriv.hwpdn_mode==2) ++ pwrctl->bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4); ++ else ++ pwrctl->bHWPowerdown = Adapter->registrypriv.hwpdn_mode; ++ ++ // decide hw if support remote wakeup function ++ // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume ++ pwrctl->bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE; ++ ++ //if(SUPPORT_HW_RADIO_DETECT(Adapter)) ++ //Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ; ++ ++ DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__, ++ pwrctl->bHWPwrPindetect,pwrctl->bHWPowerdown ,pwrctl->bSupportRemoteWakeup); ++ ++ DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable); ++ ++ } ++#endif ++} ++ ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++static u32 Hal_readPGDataFromConfigFile( ++ PADAPTER padapter) ++{ ++ u32 i; ++ struct file *fp; ++ mm_segment_t fs; ++ u8 temp[3]; ++ loff_t pos = 0; ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ u8 *PROMContent = pEEPROM->efuse_eeprom_data; ++ ++ ++ temp[2] = 0; // add end of string '\0' ++ ++ fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR, 0644); ++ if (IS_ERR(fp)) { ++ pEEPROM->bloadfile_fail_flag = _TRUE; ++ DBG_871X("Error, Efuse configure file doesn't exist.\n"); ++ return _FAIL; ++ } ++ ++ fs = get_fs(); ++ set_fs(KERNEL_DS); ++ ++ DBG_871X("Efuse configure file:\n"); ++ for (i=0; ibloadfile_fail_flag = _FALSE; ++ ++ return _SUCCESS; ++} ++ ++static void ++Hal_ReadMACAddrFromFile_8188EU( ++ PADAPTER padapter ++ ) ++{ ++ u32 i; ++ struct file *fp; ++ mm_segment_t fs; ++ u8 source_addr[18]; ++ loff_t pos = 0; ++ u32 curtime = rtw_get_current_time(); ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ u8 *head, *end; ++ ++ u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0}; ++ u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ _rtw_memset(source_addr, 0, 18); ++ _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN); ++ ++ fp = filp_open("/data/wifimac.txt", O_RDWR, 0644); ++ if (IS_ERR(fp)) { ++ pEEPROM->bloadmac_fail_flag = _TRUE; ++ DBG_871X("Error, wifi mac address file doesn't exist.\n"); ++ } else { ++ fs = get_fs(); ++ set_fs(KERNEL_DS); ++ ++ DBG_871X("wifi mac address:\n"); ++ vfs_read(fp, source_addr, 18, &pos); ++ source_addr[17] = ':'; ++ ++ head = end = source_addr; ++ for (i=0; imac_addr[i] = simple_strtoul(head, NULL, 16 ); ++ ++ if (end) { ++ end++; ++ head = end; ++ } ++ DBG_871X("%02x \n", pEEPROM->mac_addr[i]); ++ } ++ DBG_871X("\n"); ++ set_fs(fs); ++ pEEPROM->bloadmac_fail_flag = _FALSE; ++ filp_close(fp, NULL); ++ } ++ ++ if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) || ++ (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) { ++ pEEPROM->mac_addr[0] = 0x00; ++ pEEPROM->mac_addr[1] = 0xe0; ++ pEEPROM->mac_addr[2] = 0x4c; ++ pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ; ++ pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ; ++ pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ; ++ } ++ ++ DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", ++ pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], ++ pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], ++ pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]); ++} ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++static VOID ++readAdapterInfo_8188EU( ++ IN PADAPTER padapter ++ ) ++{ ++#if 1 ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ ++ /* parse the eeprom/efuse content */ ++ Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data); ++ Hal_EfuseParsePIDVID_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++ Hal_ReadMACAddrFromFile_8188EU(padapter); ++#else //CONFIG_EFUSE_CONFIG_FILE ++ Hal_EfuseParseMACAddr_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ ++ Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ ++ // ++ // The following part initialize some vars by PG info. ++ // ++ Hal_InitChannelPlan(padapter); ++#if defined(CONFIG_WOWLAN) && defined(CONFIG_SDIO_HCI) ++ Hal_DetectWoWMode(padapter); ++#endif //CONFIG_WOWLAN && CONFIG_SDIO_HCI ++ Hal_CustomizeByCustomerID_8188EU(padapter); ++ ++ _ReadLEDSetting(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); ++ ++#else ++ ++#ifdef CONFIG_INTEL_PROXIM ++ /* for intel proximity */ ++ if (pHalData->rf_type== RF_1T1R) { ++ Adapter->proximity.proxim_support = _TRUE; ++ } else if (pHalData->rf_type== RF_2T2R) { ++ if ((pHalData->EEPROMPID == 0x8186) && ++ (pHalData->EEPROMVID== 0x0bda)) ++ Adapter->proximity.proxim_support = _TRUE; ++ } else { ++ Adapter->proximity.proxim_support = _FALSE; ++ } ++#endif //CONFIG_INTEL_PROXIM ++#endif ++} ++ ++static void _ReadPROMContent( ++ IN PADAPTER Adapter ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ u8 eeValue; ++ ++ /* check system boot selection */ ++ eeValue = rtw_read8(Adapter, REG_9346CR); ++ pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE; ++ pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE; ++ ++ ++ DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), ++ (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") ); ++ ++ //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; ++#ifdef CONFIG_EFUSE_CONFIG_FILE ++ Hal_readPGDataFromConfigFile(Adapter); ++#else //CONFIG_EFUSE_CONFIG_FILE ++ Hal_InitPGData88E(Adapter); ++#endif //CONFIG_EFUSE_CONFIG_FILE ++ readAdapterInfo_8188EU(Adapter); ++} ++ ++ ++ ++static VOID ++_ReadRFType( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++#else ++ pHalData->rf_chip = RF_6052; ++#endif ++} ++ ++static int _ReadAdapterInfo8188EU(PADAPTER Adapter) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 start=rtw_get_current_time(); ++ ++ MSG_8192C("====> %s\n", __FUNCTION__); ++ ++ //Efuse_InitSomeVar(Adapter); ++ ++ //if(IS_HARDWARE_TYPE_8723A(Adapter)) ++ // _EfuseCellSel(Adapter); ++ ++ _ReadRFType(Adapter);//rf_chip -> _InitRFType() ++ _ReadPROMContent(Adapter); ++ ++ //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type); ++ ++ MSG_8192C("<==== %s in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); ++ ++ return _SUCCESS; ++} ++ ++ ++static void ReadAdapterInfo8188EU(PADAPTER Adapter) ++{ ++ // Read EEPROM size before call any EEPROM function ++ Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter); ++ ++ _ReadAdapterInfo8188EU(Adapter); ++} ++ ++ ++#define GPIO_DEBUG_PORT_NUM 0 ++static void rtl8192cu_trigger_gpio_0(_adapter *padapter) ++{ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++ u32 gpioctrl; ++ DBG_8192C("==> trigger_gpio_0...\n"); ++ rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0); ++ rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF); ++ gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16); ++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl); ++ gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8); ++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl); ++ DBG_8192C("<=== trigger_gpio_0...\n"); ++#endif ++} ++ ++static void ResumeTxBeacon(_adapter *padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6); ++ pHalData->RegFwHwTxQCtrl |= BIT6; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff); ++ pHalData->RegReg542 |= BIT0; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++} ++void UpdateInterruptMask8188EU(PADAPTER padapter,u8 bHIMR0 ,u32 AddMSR, u32 RemoveMSR) ++{ ++ HAL_DATA_TYPE *pHalData; ++ ++ u32 *himr; ++ pHalData = GET_HAL_DATA(padapter); ++ ++ if(bHIMR0) ++ himr = &(pHalData->IntrMask[0]); ++ else ++ himr = &(pHalData->IntrMask[1]); ++ ++ if (AddMSR) ++ *himr |= AddMSR; ++ ++ if (RemoveMSR) ++ *himr &= (~RemoveMSR); ++ ++ if(bHIMR0) ++ rtw_write32(padapter, REG_HIMR_88E, *himr); ++ else ++ rtw_write32(padapter, REG_HIMRE_88E, *himr); ++ ++} ++ ++static void StopTxBeacon(_adapter *padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6)); ++ pHalData->RegFwHwTxQCtrl &= (~BIT6); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); ++ pHalData->RegReg542 &= ~(BIT0); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++ ++ //todo: CheckFwRsvdPageContent(Adapter); // 2010.06.23. Added by tynli. ++ ++} ++ ++ ++static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 val8; ++ u8 mode = *((u8 *)val); ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ // disable Port1 TSF update ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ ++ // set net_type ++ val8 = rtw_read8(Adapter, MSR)&0x03; ++ val8 |= (mode<<2); ++ rtw_write8(Adapter, MSR, val8); ++ ++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode); ++ ++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) ++ { ++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++ { ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms ++ UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E); ++ #endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E)); ++ #endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++ StopTxBeacon(Adapter); ++ } ++ ++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x11);//disable atim wnd and disable beacon function ++ //rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18); ++ } ++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) ++ { ++ ResumeTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a); ++ //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ } ++ else if(mode == _HW_STATE_AP_) ++ { ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ResumeTxBeacon(Adapter); ++ ++ rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12); ++ ++ //Set RCR ++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 ++ //rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 ++ rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet ++ //enable to rx data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); ++ //enable to rx ps-poll ++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); ++ ++ //Beacon Control related register for first time ++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms ++ ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++ rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1 ++ rtw_write16(Adapter, REG_BCNTCFG, 0x00); ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); ++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms) ++ ++ //reset TSF2 ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)); ++ ++ ++ //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ //enable BCN1 Function for if2 ++ //don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1))); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE)) ++ rtw_write8(Adapter, REG_BCN_CTRL, ++ rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION); ++#endif ++ //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked ++ //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5)); ++ //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3)); ++ ++ //dis BCN0 ATIM WND if if1 is station ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0)); ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Reset TSF for STA+AP concurrent mode ++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) { ++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ } ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ } ++ else ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ // disable Port0 TSF update ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ ++ // set net_type ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= mode; ++ rtw_write8(Adapter, MSR, val8); ++ ++ DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode); ++ ++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms ++ UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E)); ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++ #endif //CONFIG_INTERRUPT_BASED_TXBCN ++ StopTxBeacon(Adapter); ++ } ++ ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd ++ //rtw_write8(Adapter,REG_BCN_CTRL, 0x18); ++ } ++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) ++ { ++ ResumeTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x1a); ++ //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ } ++ else if(mode == _HW_STATE_AP_) ++ { ++ ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0); ++ #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++ ResumeTxBeacon(Adapter); ++ ++ rtw_write8(Adapter, REG_BCN_CTRL, 0x12); ++ ++ //Set RCR ++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 ++ //rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 ++ rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet ++ //enable to rx data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); ++ //enable to rx ps-poll ++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); ++ ++ //Beacon Control related register for first time ++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms ++ ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++ rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms ++ rtw_write16(Adapter, REG_BCNTCFG, 0x00); ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); ++ rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms) ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); ++ ++ //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 ++ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); ++ ++ //enable BCN0 Function for if1 ++ //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) ++ #if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR) ++ rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1))); ++ #else ++ rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION |BIT(1))); ++ #endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE)) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, ++ rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION); ++#endif ++ ++ //dis BCN1 ATIM WND if if2 is station ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Reset TSF for STA+AP concurrent mode ++ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) { ++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ } ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ } ++ ++} ++ ++static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 idx = 0; ++ u32 reg_macid; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ reg_macid = REG_MACID1; ++ } ++ else ++#endif ++ { ++ reg_macid = REG_MACID; ++ } ++ ++ for(idx = 0 ; idx < 6; idx++) ++ { ++ rtw_write8(Adapter, (reg_macid+idx), val[idx]); ++ } ++ ++} ++ ++static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u8 idx = 0; ++ u32 reg_bssid; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ reg_bssid = REG_BSSID1; ++ } ++ else ++#endif ++ { ++ reg_bssid = REG_BSSID; ++ } ++ ++ for(idx = 0 ; idx < 6; idx++) ++ { ++ rtw_write8(Adapter, (reg_bssid+idx), val[idx]); ++ } ++ ++} ++ ++static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ u32 bcn_ctrl_reg; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ bcn_ctrl_reg = REG_BCN_CTRL_1; ++ } ++ else ++#endif ++ { ++ bcn_ctrl_reg = REG_BCN_CTRL; ++ } ++ ++ if(*((u8 *)val)) ++ { ++ rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); ++ } ++ else ++ { ++ rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT))); ++ } ++ ++ ++} ++ ++static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ u64 tsf; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++ ++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); ++ StopTxBeacon(Adapter); ++ } ++ ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR1, tsf); ++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32); ++ ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3)); ++ ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE ++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ++ ) { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue! ++ if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", ++ __FUNCTION__, __LINE__); ++ ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ ++ ++ } ++ else ++ { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++ ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE ++ && check_buddy_fwstate(Adapter, WIFI_AP_STATE) ++ ) { ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR1, tsf); ++ rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3)); ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++ // Update buddy port's TSF if it is SoftAP for beacon TX issue! ++ if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE) ++ DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", ++ __FUNCTION__, __LINE__); ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ } ++ ++ } ++ ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause &= (~STOP_BCNQ); ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); ++ ResumeTxBeacon(Adapter); ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++ ++ ++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_)) ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0x00); ++ ++ ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ //reset TSF1 ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)); ++ ++ //disable update TSF1 ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ ++ // disable Port1's beacon function ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3))); ++ } ++ else ++ { ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(*((u8 *)val))//under sitesurvey ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_BCN); ++ rtw_write32(Adapter, REG_RCR, v); ++ ++ //disable update TSF ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ if(Adapter->iface_type == IFACE_PORT1) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4)); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ } ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ StopTxBeacon(Adapter); ++ } ++ } ++ else//sitesurvey done ++ { ++ //enable to rx data frame ++ //write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4))); ++ else ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ } ++ } ++#endif ++} ++ ++static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val) ++{ ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 RetryLimit = 0x30; ++ u8 type = *((u8 *)val); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(type == 0) // prepare to join ++ { ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ StopTxBeacon(Adapter); ++ } ++ ++ //enable to rx data frame.Accept all data frame ++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE)) ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ else ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; ++ } ++ else // Ad-hoc Mode ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ else if(type == 1) //joinbss_event call back when join res < 0 ++ { ++ if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_)) ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ ++ //reset TSF 1/2 after ResumeTxBeacon ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0)); ++ ++ } ++ } ++ else if(type == 2) //sta add event call back ++ { ++ ++ //enable update TSF ++ if(Adapter->iface_type == IFACE_PORT1) ++ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4))); ++ else ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ //fixed beacon issue for 8191su........... ++ rtw_write8(Adapter,0x542 ,0x02); ++ RetryLimit = 0x7; ++ } ++ ++ ++ if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) && ++ check_buddy_fwstate(Adapter, _FW_LINKED)) ++ { ++ ResumeTxBeacon(Adapter); ++ ++ //reset TSF 1/2 after ResumeTxBeacon ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0)); ++ } ++ ++ } ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ ++#endif ++} ++ ++void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++_func_enter_; ++ ++ switch(variable) ++ { ++ case HW_VAR_MEDIA_STATUS: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= *((u8 *)val); ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_MEDIA_STATUS1: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x03; ++ val8 |= *((u8 *)val) <<2; ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_SET_OPMODE: ++ hw_var_set_opmode(Adapter, variable, val); ++ break; ++ case HW_VAR_MAC_ADDR: ++ hw_var_set_macaddr(Adapter, variable, val); ++ break; ++ case HW_VAR_BSSID: ++ hw_var_set_bssid(Adapter, variable, val); ++ break; ++ case HW_VAR_BASIC_RATE: ++ { ++ u16 BrateCfg = 0; ++ u8 RateIndex = 0; ++ ++ // 2007.01.16, by Emily ++ // Select RRSR (in Legacy-OFDM and CCK) ++ // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. ++ // We do not use other rates. ++ HalSetBrateCfg( Adapter, val, &BrateCfg ); ++ DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg); ++ ++ //2011.03.30 add by Luke Lee ++ //CCK 2M ACK should be disabled for some BCM and Atheros AP IOT ++ //because CCK 2M has poor TXEVM ++ //CCK 5.5M & 11M ACK should be enabled for better performance ++ ++ pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d; ++ ++ BrateCfg |= 0x01; // default enable 1M ACK rate ++ // Set RRSR rate table. ++ rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff); ++ rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff); ++ rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0); ++ ++ // Set RTS initial rate ++ while(BrateCfg > 0x1) ++ { ++ BrateCfg = (BrateCfg>> 1); ++ RateIndex++; ++ } ++ // Ziv - Check ++ rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex); ++ } ++ break; ++ case HW_VAR_TXPAUSE: ++ rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val)); ++ break; ++ case HW_VAR_BCN_FUNC: ++ hw_var_set_bcn_func(Adapter, variable, val); ++ break; ++ case HW_VAR_CORRECT_TSF: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_correct_tsf(Adapter, variable, val); ++#else ++ { ++ u64 tsf; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); ++ StopTxBeacon(Adapter); ++ } ++ ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++ ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause &= (~STOP_BCNQ); ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); ++ ResumeTxBeacon(Adapter); ++ } ++ } ++#endif ++ break; ++ case HW_VAR_CHECK_BSSID: ++ if(*((u8 *)val)) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ u32 val32; ++ ++ val32 = rtw_read32(Adapter, REG_RCR); ++ ++ val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); ++ ++ rtw_write32(Adapter, REG_RCR, val32); ++ } ++ break; ++ case HW_VAR_MLME_DISCONNECT: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_disconnect(Adapter, variable, val); ++#else ++ { ++ //Set RCR to not to receive data frame when NO LINK state ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); ++ //reject all data frames ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++#endif ++ break; ++ case HW_VAR_MLME_SITESURVEY: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_sitesurvey(Adapter, variable, val); ++#else ++ if(*((u8 *)val))//under sitesurvey ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_BCN); ++ rtw_write32(Adapter, REG_RCR, v); ++ //reject all data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ else//sitesurvey done ++ { ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((is_client_associated_to_ap(Adapter) == _TRUE) || ++ ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ) ++ { ++ //enable to rx data frame ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ else ++ { ++ if(Adapter->in_cta_test) ++ { ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(Adapter, REG_RCR, v); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ } ++ } ++ } ++#endif ++ break; ++ case HW_VAR_MLME_JOIN: ++#ifdef CONFIG_CONCURRENT_MODE ++ hw_var_set_mlme_join(Adapter, variable, val); ++#else ++ { ++ u8 RetryLimit = 0x30; ++ u8 type = *((u8 *)val); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(type == 0) // prepare to join ++ { ++ //enable to rx data frame.Accept all data frame ++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ if(Adapter->in_cta_test) ++ { ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(Adapter, REG_RCR, v); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; ++ } ++ else // Ad-hoc Mode ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ else if(type == 1) //joinbss_event call back when join res < 0 ++ { ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ } ++ else if(type == 2) //sta add event call back ++ { ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ } ++#endif ++ break; ++ case HW_VAR_ON_RCR_AM: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM); ++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR)); ++ break; ++ case HW_VAR_OFF_RCR_AM: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM)); ++ DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR)); ++ break; ++ case HW_VAR_BEACON_INTERVAL: ++ rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val)); ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ { ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u16 bcn_interval = *((u16 *)val); ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){ ++ DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1); ++ rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio ++ } ++ } ++#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ ++ break; ++ case HW_VAR_SLOT_TIME: ++ { ++ u8 u1bAIFS, aSifsTime; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ rtw_write8(Adapter, REG_SLOT, val[0]); ++ ++ if(pmlmeinfo->WMM_enable == 0) ++ { ++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B) ++ aSifsTime = 10; ++ else ++ aSifsTime = 16; ++ ++ u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime); ++ ++ // Temporary removed, 2008.06.20. ++ rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS); ++ } ++ } ++ break; ++ case HW_VAR_RESP_SIFS: ++ { ++#if 0 ++ // SIFS for OFDM Data ACK ++ rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]); ++ // SIFS for OFDM consecutive tx like CTS data! ++ rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]); ++ ++ rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]); ++ rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]); ++ ++ // 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. ++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]); ++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]); ++#else ++ ++ //SIFS_Timer = 0x0a0a0808; ++ //RESP_SIFS for CCK ++ rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08) ++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08) ++ //RESP_SIFS for OFDM ++ rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a) ++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a) ++#endif ++ } ++ break; ++ case HW_VAR_ACK_PREAMBLE: ++ { ++ u8 regTmp; ++ u8 bShortPreamble = *( (PBOOLEAN)val ); ++ // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) ++ regTmp = (pHalData->nCur40MhzPrimeSC)<<5; ++ //regTmp = 0; ++ if(bShortPreamble) ++ regTmp |= 0x80; ++ ++ rtw_write8(Adapter, REG_RRSR+2, regTmp); ++ } ++ break; ++ case HW_VAR_SEC_CFG: ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC ++#else ++ rtw_write8(Adapter, REG_SECCFG, *((u8 *)val)); ++#endif ++ break; ++ case HW_VAR_DM_FLAG: ++ podmpriv->SupportAbility = *((u8 *)val); ++ //DBG_871X("HW_VAR_DM_FLAG ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); ++ break; ++ case HW_VAR_DM_FUNC_OP: ++ if(val[0]) ++ {// save dm flag ++ podmpriv->BK_SupportAbility = podmpriv->SupportAbility; ++ } ++ else ++ {// restore dm flag ++ podmpriv->SupportAbility = podmpriv->BK_SupportAbility; ++ } ++ //DBG_871X("HW_VAR_DM_FUNC_OP ==> %s SupportAbility:0x%08x \n", ++ // (val[0]==1)?"Save":"Restore", ++ // podmpriv->SupportAbility ++ // ); ++ break; ++ case HW_VAR_DM_FUNC_SET: ++ if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){ ++ pdmpriv->DMFlag = pdmpriv->InitDMFlag; ++ podmpriv->SupportAbility = pdmpriv->InitODMFlag; ++ } ++ else{ ++ podmpriv->SupportAbility |= *((u32 *)val); ++ } ++ //DBG_871X("HW_VAR_DM_FUNC_SET ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); ++ break; ++ case HW_VAR_DM_FUNC_CLR: ++ podmpriv->SupportAbility &= *((u32 *)val); ++ break; ++ ++ case HW_VAR_CAM_EMPTY_ENTRY: ++ { ++ u8 ucIndex = *((u8 *)val); ++ u8 i; ++ u32 ulCommand=0; ++ u32 ulContent=0; ++ u32 ulEncAlgo=CAM_AES; ++ ++ for(i=0;iAcParam_BE = ((u32 *)(val))[0]; ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_AC_PARAM_BK: ++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_ACM_CTRL: ++ { ++ u8 acm_ctrl = *((u8 *)val); ++ u8 AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL); ++ ++ if(acm_ctrl > 1) ++ AcmCtrl = AcmCtrl | 0x1; ++ ++ if(acm_ctrl & BIT(3)) ++ AcmCtrl |= AcmHw_VoqEn; ++ else ++ AcmCtrl &= (~AcmHw_VoqEn); ++ ++ if(acm_ctrl & BIT(2)) ++ AcmCtrl |= AcmHw_ViqEn; ++ else ++ AcmCtrl &= (~AcmHw_ViqEn); ++ ++ if(acm_ctrl & BIT(1)) ++ AcmCtrl |= AcmHw_BeqEn; ++ else ++ AcmCtrl &= (~AcmHw_BeqEn); ++ ++ DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ); ++ rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl ); ++ } ++ break; ++ case HW_VAR_AMPDU_MIN_SPACE: ++ { ++ u8 MinSpacingToSet; ++ u8 SecMinSpace; ++ ++ MinSpacingToSet = *((u8 *)val); ++ if(MinSpacingToSet <= 7) ++ { ++ switch(Adapter->securitypriv.dot11PrivacyAlgrthm) ++ { ++ case _NO_PRIVACY_: ++ case _AES_: ++ SecMinSpace = 0; ++ break; ++ ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ SecMinSpace = 6; ++ break; ++ default: ++ SecMinSpace = 7; ++ break; ++ } ++ ++ if(MinSpacingToSet < SecMinSpace){ ++ MinSpacingToSet = SecMinSpace; ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg)); ++ rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet); ++ } ++ } ++ break; ++ case HW_VAR_AMPDU_FACTOR: ++ { ++ u8 RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9}; ++ u8 RegToSet_BT[4]={0x31,0x74,0x42, 0x97}; ++ u8 FactorToSet; ++ u8 *pRegToSet; ++ u8 index = 0; ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pHalData->bt_coexist.BT_Coexist) && ++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) ) ++ pRegToSet = RegToSet_BT; // 0x97427431; ++ else ++#endif ++ pRegToSet = RegToSet_Normal; // 0xb972a841; ++ ++ FactorToSet = *((u8 *)val); ++ if(FactorToSet <= 3) ++ { ++ FactorToSet = (1<<(FactorToSet + 2)); ++ if(FactorToSet>0xf) ++ FactorToSet = 0xf; ++ ++ for(index=0; index<4; index++) ++ { ++ if((pRegToSet[index] & 0xf0) > (FactorToSet<<4)) ++ pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4); ++ ++ if((pRegToSet[index] & 0x0f) > FactorToSet) ++ pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet); ++ ++ rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]); ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); ++ } ++ } ++ break; ++ case HW_VAR_RXDMA_AGG_PG_TH: ++ #ifdef CONFIG_USB_RX_AGGREGATION ++ { ++ u8 threshold = *((u8 *)val); ++ if( threshold == 0) ++ { ++ threshold = pHalData->UsbRxAggPageCount; ++ } ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold); ++ } ++ #endif ++ break; ++ case HW_VAR_SET_RPWM: ++#ifdef CONFIG_LPS_LCLK ++ { ++ u8 ps_state = *((u8 *)val); ++ //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. ++ //BIT0 value - 1: 32k, 0:40MHz. ++ //BIT6 value - 1: report cpwm value after success set, 0:do not report. ++ //BIT7 value - Toggle bit change. ++ //modify by Thomas. 2012/4/2. ++ ps_state = ps_state & 0xC1; ++ //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state); ++ rtw_write8(Adapter, REG_USB_HRPWM, ps_state); ++ } ++#endif ++ break; ++ case HW_VAR_H2C_FW_PWRMODE: ++ { ++ u8 psmode = (*(u8 *)val); ++ ++ // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power ++ // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. ++ if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID))) ++ { ++ ODM_RF_Saving(podmpriv, _TRUE); ++ } ++ rtl8188e_set_FwPwrMode_cmd(Adapter, psmode); ++ } ++ break; ++ case HW_VAR_H2C_FW_JOINBSSRPT: ++ { ++ u8 mstatus = (*(u8 *)val); ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus); ++ } ++ break; ++#ifdef CONFIG_P2P_PS ++ case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: ++ { ++ u8 p2p_ps_state = (*(u8 *)val); ++ rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state); ++ } ++ break; ++#endif //CONFIG_P2P_PS ++#ifdef CONFIG_TDLS ++ case HW_VAR_TDLS_WRCR: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~RCR_CBSSID_DATA )); ++ break; ++ case HW_VAR_TDLS_INIT_CH_SEN: ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ RCR_CBSSID_DATA )&(~RCR_CBSSID_BCN )); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xffff); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ break; ++ case HW_VAR_TDLS_DONE_CH_SEN: ++ { ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4))); ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_BCN )); ++ } ++ break; ++ case HW_VAR_TDLS_RS_RCR: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_DATA)); ++ break; ++#endif //CONFIG_TDLS ++ case HW_VAR_INITIAL_GAIN: ++ { ++ DIG_T *pDigTable = &podmpriv->DM_DigTable; ++ u32 rx_gain = ((u32 *)(val))[0]; ++ ++ if(rx_gain == 0xff){//restore rx gain ++ ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue); ++ } ++ else{ ++ pDigTable->BackupIGValue = pDigTable->CurIGValue; ++ ODM_Write_DIG(podmpriv,rx_gain); ++ } ++ } ++ break; ++ case HW_VAR_TRIGGER_GPIO_0: ++ rtl8192cu_trigger_gpio_0(Adapter); ++ break; ++#ifdef CONFIG_BT_COEXIST ++ case HW_VAR_BT_SET_COEXIST: ++ { ++ u8 bStart = (*(u8 *)val); ++ rtl8192c_set_dm_bt_coexist(Adapter, bStart); ++ } ++ break; ++ case HW_VAR_BT_ISSUE_DELBA: ++ { ++ u8 dir = (*(u8 *)val); ++ rtl8192c_issue_delete_ba(Adapter, dir); ++ } ++ break; ++#endif ++#if (RATE_ADAPTIVE_SUPPORT==1) ++ case HW_VAR_RPT_TIMER_SETTING: ++ { ++ u16 min_rpt_time = (*(u16 *)val); ++ ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time); ++ } ++ break; ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ ++ case HW_VAR_ANTENNA_DIVERSITY_LINK: ++ //odm_SwAntDivRestAfterLink8192C(Adapter); ++ ODM_SwAntDivRestAfterLink(podmpriv); ++ break; ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case HW_VAR_ANTENNA_DIVERSITY_SELECT: ++ { ++ u8 Optimum_antenna = (*(u8 *)val); ++ u8 Ant ; ++ //switch antenna to Optimum_antenna ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ if(pHalData->CurAntenna != Optimum_antenna) ++ { ++ Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT; ++ ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant); ++ ++ pHalData->CurAntenna = Optimum_antenna ; ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ } ++ } ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22. ++ pHalData->EfuseUsedBytes = *((u16 *)val); ++ break; ++ case HW_VAR_FIFO_CLEARN_UP: ++ { ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); ++ u8 trycnt = 100; ++ ++ //pause tx ++ rtw_write8(Adapter,REG_TXPAUSE,0xff); ++ ++ //keep sn ++ Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ); ++ ++ if(pwrpriv->bkeepfwalive != _TRUE) ++ { ++ //RX DMA stop ++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); ++ do{ ++ if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE)) ++ break; ++ }while(trycnt--); ++ if(trycnt ==0) ++ DBG_8192C("Stop RX DMA failed...... \n"); ++ ++ //RQPN Load 0 ++ rtw_write16(Adapter,REG_RQPN_NPQ,0x0); ++ rtw_write32(Adapter,REG_RQPN,0x80000000); ++ rtw_mdelay_os(10); ++ } ++ } ++ break; ++ case HW_VAR_CHECK_TXBUF: ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ { ++ int i; ++ #if 0 //for Miracast source PKT lost issue ++ u8 RetryLimit = 0x01; ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ #endif ++ ++ for(i=0;i<1000;i++) ++ { ++ if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204)) ++ { ++ //DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i); ++ rtw_msleep_os(10); ++ } ++ else ++ { ++ DBG_871X("no packet in tx packet buffer (%d)\n", i); ++ break; ++ } ++ } ++ #if 0 //for Miracast source PKT lost issue ++ RetryLimit = 0x30; ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ #endif ++ } ++#endif ++ break; ++ ++ case HW_VAR_APFM_ON_MAC: ++ pHalData->bMacPwrCtrlOn = *val; ++ DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn); ++ break; ++ ++#ifdef CONFIG_WOWLAN ++ case HW_VAR_WOWLAN: ++ { ++ struct wowlan_ioctl_param *poidparam; ++ struct recv_buf *precvbuf; ++ int res, i; ++ u32 tmp; ++ u16 len = 0; ++ u8 mstatus = (*(u8 *)val); ++ u8 trycnt = 100; ++ u8 data[4]; ++ ++ poidparam = (struct wowlan_ioctl_param *)val; ++ switch (poidparam->subcode){ ++ case WOWLAN_ENABLE: ++ DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n"); ++ ++ SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE); ++ ++ //Set Pattern ++ //if(adapter_to_pwrctl(Adapter)->wowlan_pattern==_TRUE) ++ // rtw_wowlan_reload_pattern(Adapter); ++ ++ //RX DMA stop ++ DBG_871X_LEVEL(_drv_always_, "Pause DMA\n"); ++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); ++ do{ ++ if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) { ++ DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n"); ++ break; ++ } else { ++ // If RX_DMA is not idle, receive one pkt from DMA ++ DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is not true\n"); ++ } ++ }while(trycnt--); ++ if(trycnt ==0) ++ DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n"); ++ ++ //Set WOWLAN H2C command. ++ DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n"); ++ rtl8188es_set_wowlan_cmd(Adapter, 1); ++ ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ trycnt = 10; ++ ++ while(!(mstatus&BIT1) && trycnt>1) { ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus); ++ trycnt --; ++ rtw_msleep_os(2); ++ } ++ ++ adapter_to_pwrctl(Adapter)->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON); ++ DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n", ++ adapter_to_pwrctl(Adapter)->wowlan_wake_reason); ++ ++ /* Invoid SE0 reset signal during suspending*/ ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x20); ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x60); ++ ++ //rtw_msleep_os(10); ++ break; ++ case WOWLAN_DISABLE: ++ DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n"); ++ trycnt = 10; ++ rtl8188es_set_wowlan_cmd(Adapter, 0); ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus); ++ ++ while(mstatus&BIT1 && trycnt>1) { ++ mstatus = rtw_read8(Adapter, REG_WOW_CTRL); ++ DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus); ++ trycnt --; ++ rtw_msleep_os(2); ++ } ++ ++ if (mstatus & BIT1) ++ printk("System did not release RX_DMA\n"); ++ else ++ SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE); ++ ++ rtw_msleep_os(2); ++ if(!(adapter_to_pwrctl(Adapter)->wowlan_wake_reason & FWDecisionDisconnect)) ++ rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1); ++ //rtw_msleep_os(10); ++ break; ++ default: ++ break; ++ } ++ } ++ break; ++#endif //CONFIG_WOWLAN ++ ++ ++ #if (RATE_ADAPTIVE_SUPPORT == 1) ++ case HW_VAR_TX_RPT_MAX_MACID: ++ { ++ u8 maxMacid = *val; ++ DBG_871X("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1); ++ rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1); ++ } ++ break; ++ #endif ++ case HW_VAR_H2C_MEDIA_STATUS_RPT: ++ { ++ rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val)); ++ } ++ break; ++ case HW_VAR_BCN_VALID: ++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw ++ rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0); ++ break; ++ default: ++ ++ break; ++ } ++ ++_func_exit_; ++} ++ ++void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++_func_enter_; ++ ++ switch(variable) ++ { ++ case HW_VAR_BASIC_RATE: ++ *((u16 *)(val)) = pHalData->BasicRateSet; ++ case HW_VAR_TXPAUSE: ++ val[0] = rtw_read8(Adapter, REG_TXPAUSE); ++ break; ++ case HW_VAR_BCN_VALID: ++ //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 ++ val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?_TRUE:_FALSE; ++ break; ++ case HW_VAR_DM_FLAG: ++ val[0] = podmpriv->SupportAbility; ++ break; ++ case HW_VAR_RF_TYPE: ++ val[0] = pHalData->rf_type; ++ break; ++ case HW_VAR_FWLPS_RF_ON: ++ { ++ //When we halt NIC, we should check if FW LPS is leave. ++ if(adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) ++ { ++ // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, ++ // because Fw is unload. ++ val[0] = _TRUE; ++ } ++ else ++ { ++ u32 valRCR; ++ valRCR = rtw_read32(Adapter, REG_RCR); ++ valRCR &= 0x00070000; ++ if(valRCR) ++ val[0] = _FALSE; ++ else ++ val[0] = _TRUE; ++ } ++ } ++ break; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case HW_VAR_CURRENT_ANTENNA: ++ val[0] = pHalData->CurAntenna; ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22. ++ *((u16 *)(val)) = pHalData->EfuseUsedBytes; ++ break; ++ case HW_VAR_APFM_ON_MAC: ++ *val = pHalData->bMacPwrCtrlOn; ++ break; ++ case HW_VAR_CHK_HI_QUEUE_EMPTY: ++ *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00)==0) ? _TRUE:_FALSE; ++ break; ++ ++ case HW_VAR_READ_LLT_TAB: ++ { ++ Read_LLT_Tab(Adapter); ++ } ++ break; ++ case HW_VAR_GET_CPWM: ++#ifdef CONFIG_LPS_LCLK ++ { ++ *val = rtw_read8(Adapter, REG_USB_HCPWM); ++ } ++#endif ++ break; ++ case HW_VAR_C2HEVT_CLEAR: ++ *val = rtw_read8(Adapter, REG_C2HEVT_CLEAR); ++ break; ++ case HW_VAR_C2HEVT_MSG_NORMAL: ++ *val = rtw_read8(Adapter, REG_C2HEVT_MSG_NORMAL); ++ break; ++ ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++// ++// Description: ++// Query setting of specified variable. ++// ++u8 ++GetHalDefVar8188EUsb( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++ u8 bResult = _SUCCESS; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: ++#if 1 //trunk ++ { ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct sta_priv * pstapriv = &Adapter->stapriv; ++ struct sta_info * psta; ++ psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); ++ if(psta) ++ { ++ *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ } ++ } ++#else //V4 branch ++ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB; ++ } ++ else{ ++ ++ } ++#endif ++ break; ++ case HAL_DEF_IS_SUPPORT_ANT_DIV: ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ *((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE; ++#endif ++ break; ++ case HAL_DEF_CURRENT_ANTENNA: ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ *(( u8*)pValue) = pHalData->CurAntenna; ++#endif ++ break; ++ case HAL_DEF_DRVINFO_SZ: ++ *(( u32*)pValue) = DRVINFO_SZ; ++ break; ++ case HAL_DEF_MAX_RECVBUF_SZ: ++ *(( u32*)pValue) = MAX_RECVBUF_SZ; ++ break; ++ case HAL_DEF_RX_PACKET_OFFSET: ++ *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ; ++ break; ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ case HAL_DEF_RA_DECISION_RATE: ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(podmpriv, MacID); ++ } ++ break; ++ ++ case HAL_DEF_RA_SGI: ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetShortGI_8188E(podmpriv, MacID); ++ } ++ break; ++#endif ++ ++ ++ case HAL_DEF_PT_PWR_STATUS: ++#if(POWER_TRAINING_ACTIVE==1) ++ { ++ u8 MacID = *((u8*)pValue); ++ *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(podmpriv, MacID); ++ } ++#endif//(POWER_TRAINING_ACTIVE==1) ++ break; ++ ++ case HW_VAR_MAX_RX_AMPDU_FACTOR: ++ *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K; ++ break; ++ ++ case HW_DEF_RA_INFO_DUMP: ++#if (RATE_ADAPTIVE_SUPPORT == 1) ++ { ++ u8 entry_id = *((u8*)pValue); ++ u8 i; ++ u8 bLinked = _FALSE; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; ++#endif //CONFIG_CONCURRENT_MODE ++ ++ //if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== _TRUE) ++ ++ if(rtw_linked_check(Adapter)) ++ bLinked = _TRUE; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) ++ bLinked = _TRUE; ++#endif ++ ++ if(bLinked){ ++ DBG_871X("============ RA status check ===================\n"); ++ if(Adapter->bRxRSSIDisplay >30) ++ Adapter->bRxRSSIDisplay = 1; ++ for(i=0;i< Adapter->bRxRSSIDisplay;i++){ ++ DBG_8192C("Mac_id:%d ,RSSI:%d,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d, RetryOver drop:%d, LifeTimeOver drop:%d\n", ++ i, ++ podmpriv->RAInfo[i].RssiStaRA, ++ podmpriv->RAInfo[i].RateID, ++ podmpriv->RAInfo[i].RAUseRate, ++ podmpriv->RAInfo[i].RateSGI, ++ podmpriv->RAInfo[i].DecisionRate, ++ podmpriv->RAInfo[i].PTStage, ++ podmpriv->RAInfo[i].DROP, ++ podmpriv->RAInfo[i].DROP1 ++ ); ++ } ++ } ++ } ++#endif //(RATE_ADAPTIVE_SUPPORT == 1) ++ break; ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ *(( u8*)pValue) = pHalData->bDumpRxPkt; ++ break; ++ case HAL_DEF_DBG_DUMP_TXPKT: ++ *(( u8*)pValue) = pHalData->bDumpTxPkt; ++ break; ++ ++ default: ++ bResult = GetHalDefVar(Adapter, eVariable, pValue); ++ break; ++ } ++ ++ return bResult; ++} ++ ++ ++ ++ ++// ++// Description: ++// Change default setting of specified variable. ++// ++u8 ++SetHalDefVar8188EUsb( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DM_ODM_T *podmpriv = &pHalData->odmpriv; ++ u8 bResult = _SUCCESS; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_DBG_DM_FUNC: ++ { ++ u8 dm_func = *(( u8*)pValue); ++ ++ if(dm_func == 0){ //disable all dynamic func ++ podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE; ++ DBG_8192C("==> Disable all dynamic function...\n"); ++ } ++ else if(dm_func == 1){//disable DIG ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG); ++ DBG_8192C("==> Disable DIG...\n"); ++ } ++ else if(dm_func == 2){//disable High power ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR); ++ } ++ else if(dm_func == 3){//disable tx power tracking ++ podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION); ++ DBG_8192C("==> Disable tx power tracking...\n"); ++ } ++ //else if(dm_func == 4){//disable BT coexistence ++ // pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); ++ //} ++ else if(dm_func == 5){//disable antenna diversity ++ podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV); ++ } ++ else if(dm_func == 6){//turn on all dynamic func ++ if(!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) ++ { ++ DIG_T *pDigTable = &podmpriv->DM_DigTable; ++ pDigTable->CurIGValue= rtw_read8(Adapter,0xc50); ++ } ++ //pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; ++ podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE; ++ DBG_8192C("==> Turn on all dynamic function...\n"); ++ } ++ } ++ break; ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ pHalData->bDumpRxPkt = *(( u8*)pValue); ++ break; ++ case HAL_DEF_DBG_DUMP_TXPKT: ++ pHalData->bDumpTxPkt = *(( u8*)pValue); ++ break; ++ default: ++ bResult = SetHalDefVar(Adapter, eVariable, pValue); ++ break; ++ } ++ ++ return bResult; ++} ++/* ++u32 _update_92cu_basic_rate(_adapter *padapter, unsigned int mask) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ unsigned int BrateCfg = 0; ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pbtpriv->BT_Coexist) && (pbtpriv->BT_CoexistType == BT_CSR_BC4) ) ++ { ++ BrateCfg = mask & 0x151; ++ //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151); ++ } ++ else ++#endif ++ { ++ //if(pHalData->VersionID != VERSION_TEST_CHIP_88C) ++ BrateCfg = mask & 0x15F; ++ //else //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning ++ // BrateCfg = mask & 0x159; ++ } ++ ++ BrateCfg |= 0x01; // default enable 1M ACK rate ++ ++ return BrateCfg; ++} ++*/ ++void _update_response_rate(_adapter *padapter,unsigned int mask) ++{ ++ u8 RateIndex = 0; ++ // Set RRSR rate table. ++ rtw_write8(padapter, REG_RRSR, mask&0xff); ++ rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff); ++ ++ // Set RTS initial rate ++ while(mask > 0x1) ++ { ++ mask = (mask>> 1); ++ RateIndex++; ++ } ++ rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex); ++} ++ ++void UpdateHalRAMask8188EUsb(PADAPTER padapter, u32 mac_id, u8 rssi_level) ++{ ++ //volatile unsigned int result; ++ u8 init_rate=0; ++ u8 networkType, raid; ++ u32 mask,rate_bitmap; ++ u8 shortGIrate = _FALSE; ++ int supportRateNum = 0; ++ struct sta_info *psta; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ //struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ if (mac_id >= NUM_STA) //CAM_SIZE ++ { ++ return; ++ } ++ ++ psta = pmlmeinfo->FW_sta_info[mac_id].psta; ++ if(psta == NULL) ++ { ++ return; ++ } ++ ++ switch (mac_id) ++ { ++ case 0:// for infra mode ++#ifdef CONFIG_CONCURRENT_MODE ++ case 2:// first station uses macid=0, second station uses macid=2 ++#endif ++ supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates); ++ networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0; ++ ++ ++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps))) ++ { ++ shortGIrate = _TRUE; ++ } ++ ++ break; ++ ++ case 1://for broadcast/multicast ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ networkType = WIRELESS_11B; ++ else ++ networkType = WIRELESS_11G; ++ raid = networktype_to_raid(networkType); ++ mask = update_basic_rate(cur_network->SupportedRates, supportRateNum); ++ ++ ++ break; ++ ++ default: //for each sta in IBSS ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ ++ //todo: support HT in IBSS ++ ++ break; ++ } ++ ++ //mask &=0x0fffffff; ++ rate_bitmap = 0x0fffffff; ++#ifdef CONFIG_ODM_REFRESH_RAMASK ++ { ++ rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level); ++ printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", ++ __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap); ++ } ++#endif ++ ++ mask &= rate_bitmap; ++ ++ init_rate = get_highest_rate_idx(mask)&0x3f; ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ u8 arg = 0; ++ ++ //arg = (cam_idx-4)&0x1f;//MACID ++ arg = mac_id&0x1f;//MACID ++ ++ arg |= BIT(7); ++ ++ if (shortGIrate==_TRUE) ++ arg |= BIT(5); ++ mask |= ((raid<<28)&0xf0000000); ++ DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg); ++ psta->ra_mask=mask; ++#ifdef CONFIG_INTEL_PROXIM ++ if(padapter->proximity.proxim_on ==_TRUE){ ++ arg &= ~BIT(6); ++ } ++ else { ++ arg |= BIT(6); ++ } ++#endif //CONFIG_INTEL_PROXIM ++ mask |= ((raid<<28)&0xf0000000); ++ ++ //to do ++ /* ++ *(pu4Byte)&RateMask=EF4Byte((ratr_bitmap&0x0fffffff) | (ratr_index<<28)); ++ RateMask[4] = macId | (bShortGI?0x20:0x00) | 0x80; ++ */ ++ rtl8188e_set_raid_cmd(padapter, mask); ++ ++ } ++ else ++ { ++ ++#if(RATE_ADAPTIVE_SUPPORT == 1) ++ ++ ODM_RA_UpdateRateInfo_8188E( ++ &(pHalData->odmpriv), ++ mac_id, ++ raid, ++ mask, ++ shortGIrate ++ ); ++ ++#endif ++ } ++ ++ ++ //set ra_id ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ ++} ++ ++ ++void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter) ++{ ++ u32 value32; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 bcn_ctrl_reg = REG_BCN_CTRL; ++ //reset TSF, enable update TSF, correcting TSF On Beacon ++ ++ //REG_BCN_INTERVAL ++ //REG_BCNDMATIM ++ //REG_ATIMWND ++ //REG_TBTT_PROHIBIT ++ //REG_DRVERLYINT ++ //REG_BCN_MAX_ERR ++ //REG_BCNTCFG //(0x510) ++ //REG_DUAL_TSF_RST ++ //REG_BCN_CTRL //(0x550) ++ ++ //BCN interval ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->iface_type == IFACE_PORT1){ ++ bcn_ctrl_reg = REG_BCN_CTRL_1; ++ } ++#endif ++ rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); ++ rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms ++ ++ _InitBeaconParameters(padapter); ++ ++ rtw_write8(padapter, REG_SLOT, 0x09); ++ ++ value32 =rtw_read32(padapter, REG_TCR); ++ value32 &= ~TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ value32 |= TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ // NOTE: Fix test chip's bug (about contention windows's randomness) ++ rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); ++ rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); ++ ++ _BeaconFunctionEnable(padapter, _TRUE, _TRUE); ++ ++ ResumeTxBeacon(padapter); ++ ++ //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6)); ++ ++ //rtw_write8(padapter, 0x541, 0xff); ++ ++ //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0)); ++ ++ rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1)); ++ ++} ++ ++static void rtl8188eu_init_default_value(_adapter * padapter) ++{ ++ PHAL_DATA_TYPE pHalData; ++ struct pwrctrl_priv *pwrctrlpriv; ++ struct dm_priv *pdmpriv; ++ u8 i; ++ ++ pHalData = GET_HAL_DATA(padapter); ++ pwrctrlpriv = adapter_to_pwrctl(padapter); ++ pdmpriv = &pHalData->dmpriv; ++ ++ ++ //init default value ++ pHalData->fw_ractrl = _FALSE; ++ if(!pwrctrlpriv->bkeepfwalive) ++ pHalData->LastHMEBoxNum = 0; ++ ++ //init dm default value ++ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE; ++ pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK ++ //pdmpriv->binitialized = _FALSE; ++// pdmpriv->prv_traffic_idx = 3; ++// pdmpriv->initialize = 0; ++ pHalData->pwrGroupCnt = 0; ++ pHalData->PGMaxGroup= 13; ++ pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; ++ for(i = 0; i < HP_THERMAL_NUM; i++) ++ pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0; ++} ++ ++static u8 rtl8188eu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val) ++{ ++ u8 bResult = _TRUE; ++ switch(efunc_id){ ++ ++ #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) ++ case HAL_USB_SELECT_SUSPEND: ++ { ++ u8 bfwpoll = *(( u8*)val); ++ //rtl8188e_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect ++ } ++ break; ++ #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED ++ ++ default: ++ break; ++ } ++ return bResult; ++} ++ ++void rtl8188eu_set_hal_ops(_adapter * padapter) ++{ ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++ ++_func_enter_; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->isprimary) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); ++ if(padapter->HalData == NULL){ ++ DBG_8192C("cant not alloc memory for HAL DATA \n"); ++ } ++ } ++ ++ //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE)); ++ padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); ++ ++ pHalFunc->hal_power_on = InitPowerOn_rtl8188eu; ++ pHalFunc->hal_power_off = hal_poweroff_rtl8188eu; ++ ++ pHalFunc->hal_init = &rtl8188eu_hal_init; ++ pHalFunc->hal_deinit = &rtl8188eu_hal_deinit; ++ ++ //pHalFunc->free_hal_data = &rtl8192c_free_hal_data; ++ ++ pHalFunc->inirp_init = &rtl8188eu_inirp_init; ++ pHalFunc->inirp_deinit = &rtl8188eu_inirp_deinit; ++ ++ pHalFunc->init_xmit_priv = &rtl8188eu_init_xmit_priv; ++ pHalFunc->free_xmit_priv = &rtl8188eu_free_xmit_priv; ++ ++ pHalFunc->init_recv_priv = &rtl8188eu_init_recv_priv; ++ pHalFunc->free_recv_priv = &rtl8188eu_free_recv_priv; ++#ifdef CONFIG_SW_LED ++ pHalFunc->InitSwLeds = &rtl8188eu_InitSwLeds; ++ pHalFunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds; ++#else //case of hw led or no led ++ pHalFunc->InitSwLeds = NULL; ++ pHalFunc->DeInitSwLeds = NULL; ++#endif//CONFIG_SW_LED ++ ++ pHalFunc->init_default_value = &rtl8188eu_init_default_value; ++ pHalFunc->intf_chip_configure = &rtl8188eu_interface_configure; ++ pHalFunc->read_adapter_info = &ReadAdapterInfo8188EU; ++ ++ //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C; ++ //pHalFunc->set_channel_handler = &PHY_SwChnl8192C; ++ ++ //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog; ++ ++ ++ pHalFunc->SetHwRegHandler = &SetHwReg8188EU; ++ pHalFunc->GetHwRegHandler = &GetHwReg8188EU; ++ pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb; ++ pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb; ++ ++ pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb; ++ pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb; ++ ++ //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid; ++ ++ pHalFunc->hal_xmit = &rtl8188eu_hal_xmit; ++ pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit; ++ pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue; ++ ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ pHalFunc->hostap_mgnt_xmit_entry = &rtl8188eu_hostap_mgnt_xmit_entry; ++#endif ++ pHalFunc->interface_ps_func = &rtl8188eu_ps_func; ++ ++ rtl8188e_set_hal_ops(pHalFunc); ++_func_exit_; ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_ops_linux.c b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_ops_linux.c +new file mode 100644 +index 00000000..93f4604b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/hal/rtl8188e/usb/usb_ops_linux.c +@@ -0,0 +1,1743 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_OPS_OS_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ _adapter *padapter = pintfhdl->padapter; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ unsigned int pipe; ++ int status = 0; ++ u32 tmp_buflen=0; ++ u8 reqtype; ++ u8 *pIo_buf; ++ int vendorreq_times = 0; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ u8 *tmp_buf; ++ #else // use stack memory ++ u8 tmp_buf[MAX_USB_IO_CTL_SIZE]; ++ #endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->adapter_type > PRIMARY_ADAPTER) ++ { ++ padapter = padapter->pbuddy_adapter; ++ pdvobjpriv = adapter_to_dvobj(padapter); ++ udev = pdvobjpriv->pusbdev; ++ } ++#endif ++ ++ //DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); ++ ++ if((padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobjpriv)->pnp_bstop_trx)){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); ++ status = -EPERM; ++ goto exit; ++ } ++ ++ if(len>MAX_VENDOR_REQ_CMD_SIZE){ ++ DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ ); ++ status = -EINVAL; ++ goto exit; ++ } ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); ++ #endif ++ ++ ++ // Acquire IO memory for vendorreq ++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ pIo_buf = pdvobjpriv->usb_vendor_req_buf; ++#else ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT); ++ tmp_buflen = (u32)len + ALIGNMENT_UNIT; ++ #else // use stack memory ++ tmp_buflen = MAX_USB_IO_CTL_SIZE; ++ #endif ++ ++ // Added by Albert 2010/02/09 ++ // For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. ++ // Trying to fix it here. ++ pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f ); ++#endif ++ ++ if ( pIo_buf== NULL) { ++ DBG_8192C( "[%s] pIo_buf == NULL \n", __FUNCTION__ ); ++ status = -ENOMEM; ++ goto release_mutex; ++ } ++ ++ while(++vendorreq_times<= MAX_USBCTRL_VENDORREQ_TIMES) ++ { ++ _rtw_memset(pIo_buf, 0, len); ++ ++ if (requesttype == 0x01) ++ { ++ pipe = usb_rcvctrlpipe(udev, 0);//read_in ++ reqtype = REALTEK_USB_VENQT_READ; ++ } ++ else ++ { ++ pipe = usb_sndctrlpipe(udev, 0);//write_out ++ reqtype = REALTEK_USB_VENQT_WRITE; ++ _rtw_memcpy( pIo_buf, pdata, len); ++ } ++ ++ #if 0 ++ //timeout test for firmware downloading ++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len ++ , (value == FW_8188E_START_ADDRESS) ?RTW_USB_CONTROL_MSG_TIMEOUT_TEST : RTW_USB_CONTROL_MSG_TIMEOUT ++ ); ++ #else ++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT); ++ #endif ++ ++ if ( status == len) // Success this control transfer. ++ { ++ rtw_reset_continual_io_error(pdvobjpriv); ++ if ( requesttype == 0x01 ) ++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. ++ _rtw_memcpy( pdata, pIo_buf, len ); ++ } ++ } ++ else { // error cases ++ DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" ++ , value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times); ++ ++ if (status < 0) { ++ if(status == (-ESHUTDOWN) || status == -ENODEV ) ++ { ++ padapter->bSurpriseRemoved = _TRUE; ++ } else { ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL; ++ } ++ #endif ++ } ++ } ++ else // status != len && status >= 0 ++ { ++ if(status > 0) { ++ if ( requesttype == 0x01 ) ++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. ++ _rtw_memcpy( pdata, pIo_buf, len ); ++ } ++ } ++ } ++ ++ if(rtw_inc_and_chk_continual_io_error(pdvobjpriv) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ ++ } ++ ++ // firmware download is checksumed, don't retry ++ if( (value >= FW_8188E_START_ADDRESS && value <= FW_8188E_END_ADDRESS) || status == len ) ++ break; ++ ++ } ++ ++ // release IO memory used by vendorreq ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ rtw_mfree(tmp_buf, tmp_buflen); ++ #endif ++ ++release_mutex: ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); ++ #endif ++exit: ++ return status; ++ ++} ++ ++static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u8 data=0; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 1; ++ ++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return data; ++ ++} ++ ++static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u16 data=0; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 2; ++ ++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return data; ++ ++} ++ ++static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data=0; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 4; ++ ++ usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return data; ++ ++} ++ ++static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u8 data; ++ int ret; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 1; ++ ++ data = val; ++ ++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u16 data; ++ int ret; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 2; ++ ++ data = val; ++ ++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data; ++ int ret; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 4; ++ data =val; ++ ++ ret =usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0}; ++ int ret; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = length; ++ _rtw_memcpy(buf, pdata, len ); ++ ++ ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_SUPPORT_USB_INT ++void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf) ++{ ++ HAL_DATA_TYPE *pHalData=GET_HAL_DATA(padapter); ++ struct reportpwrstate_parm pwr_rpt; ++ ++ if ( pkt_len != INTERRUPT_MSG_FORMAT_LEN ) ++ { ++ DBG_8192C("%s Invalid interrupt content length (%d)!\n", __FUNCTION__, pkt_len); ++ return ; ++ } ++ ++ // HISR ++ _rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4); ++ _rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4); ++ ++ #if 0 //DBG ++ { ++ u32 hisr=0 ,hisr_ex=0; ++ _rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4); ++ hisr = le32_to_cpu(hisr); ++ ++ _rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4); ++ hisr_ex = le32_to_cpu(hisr_ex); ++ ++ if((hisr != 0) || (hisr_ex!=0)) ++ DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x \n",__FUNCTION__,hisr,hisr_ex); ++ } ++ #endif ++ ++ ++#ifdef CONFIG_LPS_LCLK ++ if( pHalData->IntArray[0] & IMR_CPWM_88E ) ++ { ++ _rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1); ++ //_rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1); ++ ++ //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. ++ pwr_rpt.state |= PS_STATE_S2; ++ _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); ++ } ++#endif//CONFIG_LPS_LCLK ++ ++#ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) ++ #endif ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ if (pHalData->IntArray[0] & (IMR_TBDER_88E|IMR_TBDOK_88E)) ++ #endif ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ #if 0 ++ if(pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) ++ DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__); ++ if(pHalData->IntArray[0] & IMR_TBDOK_88E) ++ DBG_8192C("%s: HISR_TXBCNOK\n", __func__); ++ if(pHalData->IntArray[0] & IMR_TBDER_88E) ++ DBG_8192C("%s: HISR_TXBCNERR\n", __func__); ++ #endif ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ //send_beacon(padapter); ++ if(pmlmepriv->update_bcn == _TRUE) ++ { ++ //tx_beacon_hdl(padapter, NULL); ++ set_tx_beacon_cmd(padapter); ++ } ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) ++ { ++ //send_beacon(padapter); ++ if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) ++ { ++ //tx_beacon_hdl(padapter, NULL); ++ set_tx_beacon_cmd(padapter->pbuddy_adapter); ++ } ++ } ++#endif ++ ++ } ++#endif //CONFIG_INTERRUPT_BASED_TXBCN ++ ++ ++ ++ ++#ifdef DBG_CONFIG_ERROR_DETECT_INT ++ if( pHalData->IntArray[1] & IMR_TXERR_88E ) ++ DBG_871X("===> %s Tx Error Flag Interrupt Status \n",__FUNCTION__); ++ if( pHalData->IntArray[1] & IMR_RXERR_88E ) ++ DBG_871X("===> %s Rx Error Flag INT Status \n",__FUNCTION__); ++ if( pHalData->IntArray[1] & IMR_TXFOVW_88E ) ++ DBG_871X("===> %s Transmit FIFO Overflow \n",__FUNCTION__); ++ if( pHalData->IntArray[1] & IMR_RXFOVW_88E ) ++ DBG_871X("===> %s Receive FIFO Overflow \n",__FUNCTION__); ++#endif//DBG_CONFIG_ERROR_DETECT_INT ++ ++ ++ // C2H Event ++ if(pbuf[0]!= 0){ ++ _rtw_memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16); ++ //rtw_c2h_wk_cmd(padapter); to do.. ++ } ++ ++} ++#endif ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ int err; ++ _adapter *padapter = (_adapter *)purb->context; ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) ++ { ++ DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", ++ __FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel); ++ ++ return; ++ } ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN) ++ { ++ DBG_8192C("usb_read_interrupt_complete: purb->actual_length > INTERRUPT_MSG_FORMAT_LEN(%d)\n",INTERRUPT_MSG_FORMAT_LEN); ++ } ++ ++ interrupt_handler_8188eu(padapter, purb->actual_length,purb->transfer_buffer ); ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, purb->status); ++ } ++ } ++ else ++ { ++ DBG_8192C("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status); ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ } ++ ++} ++ ++static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ int err; ++ unsigned int pipe; ++ u32 ret = _SUCCESS; ++ _adapter *adapter = pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++_func_enter_; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, ++ precvpriv->int_in_buf, ++ INTERRUPT_MSG_FORMAT_LEN, ++ usb_read_interrupt_complete, ++ adapter, ++ 1); ++ ++ err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, precvpriv->int_in_urb->status); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif ++ ++static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxstat, struct phy_stat *pphy_status) ++{ ++ s32 ret=_SUCCESS; ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 *primary_myid, *secondary_myid, *paddr1; ++ union recv_frame *precvframe_if2 = NULL; ++ _adapter *primary_padapter = precvframe->u.hdr.adapter; ++ _adapter *secondary_padapter = primary_padapter->pbuddy_adapter; ++ struct recv_priv *precvpriv = &primary_padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ u8 *pbuf = precvframe->u.hdr.rx_data; ++ ++ if(!secondary_padapter) ++ return ret; ++ ++ paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data); ++ ++ if(IS_MCAST(paddr1) == _FALSE)//unicast packets ++ { ++ //primary_myid = myid(&primary_padapter->eeprompriv); ++ secondary_myid = myid(&secondary_padapter->eeprompriv); ++ ++ if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN)) ++ { ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ } ++ ++ //ret = recv_entry(precvframe); ++ ++ } ++ else // Handle BC/MC Packets ++ { ++ ++ u8 clone = _TRUE; ++#if 0 ++ u8 type, subtype, *paddr2, *paddr3; ++ ++ type = GetFrameType(pbuf); ++ subtype = GetFrameSubType(pbuf); //bit(7)~bit(2) ++ ++ switch (type) ++ { ++ case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets ++ if(subtype == WIFI_BEACON) ++ { ++ paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data); ++ ++ if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) && ++ _rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN)) ++ { ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ clone = _FALSE; ++ } ++ ++ if(check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) && ++ _rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN)) ++ { ++ if(clone==_FALSE) ++ { ++ clone = _TRUE; ++ } ++ else ++ { ++ clone = _FALSE; ++ } ++ ++ precvframe->u.hdr.adapter = primary_padapter; ++ } ++ ++ if(check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) || ++ check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)) ++ { ++ clone = _TRUE; ++ precvframe->u.hdr.adapter = primary_padapter; ++ } ++ ++ } ++ else if(subtype == WIFI_PROBEREQ) ++ { ++ //probe req frame is only for interface2 ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ clone = _FALSE; ++ } ++ break; ++ case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets ++ ++ break; ++ case WIFI_DATA_TYPE: //Handle BC/MC data Packets ++ //Notes: AP MODE never rx BC/MC data packets ++ ++ paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data); ++ ++ if(_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN)) ++ { ++ //change to secondary interface ++ precvframe->u.hdr.adapter = secondary_padapter; ++ clone = _FALSE; ++ } ++ ++ break; ++ default: ++ ++ break; ++ } ++#endif ++ ++ if(_TRUE == clone) ++ { ++ //clone/copy to if2 ++ u8 shift_sz = 0; ++ u32 alloc_sz, skb_len; ++ _pkt *pkt_copy = NULL; ++ struct rx_pkt_attrib *pattrib = NULL; ++ ++ precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue); ++ if(precvframe_if2) ++ { ++ precvframe_if2->u.hdr.adapter = secondary_padapter; ++ ++ _rtw_init_listhead(&precvframe_if2->u.hdr.list); ++ precvframe_if2->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe_if2->u.hdr.len=0; ++ ++ _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); ++ ++ pattrib = &precvframe_if2->u.hdr.attrib; ++ ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if (pattrib->qos) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ skb_len = pattrib->pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ pkt_copy = rtw_skb_alloc(alloc_sz); ++ ++ if(pkt_copy) ++ { ++ pkt_copy->dev = secondary_padapter->pnetdev; ++ precvframe_if2->u.hdr.pkt = pkt_copy; ++ precvframe_if2->u.hdr.rx_head = pkt_copy->data; ++ precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, pbuf, skb_len); ++ precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data; ++ ++ ++ recvframe_put(precvframe_if2, skb_len); ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe_if2, (struct phy_stat*)pphy_status); ++ ret = rtw_recv_entry(precvframe_if2); ++ ++ } ++ else { ++ rtw_free_recvframe(precvframe_if2, pfree_recv_queue); ++ DBG_8192C("%s()-%d: alloc_skb() failed!\n", __FUNCTION__, __LINE__); ++ } ++ ++ } ++ ++ } ++ ++ } ++ if (precvframe->u.hdr.attrib.physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); ++ ret = rtw_recv_entry(precvframe); ++ ++#endif ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ u8 *pbuf; ++ u8 shift_sz = 0; ++ u16 pkt_cnt, drvinfo_sz; ++ u32 pkt_offset, skb_len, alloc_sz; ++ s32 transfer_len; ++ struct recv_stat *prxstat; ++ struct phy_stat *pphy_status = NULL; ++ _pkt *pkt_copy = NULL; ++ union recv_frame *precvframe = NULL; ++ struct rx_pkt_attrib *pattrib = NULL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ ++ ++ transfer_len = (s32)precvbuf->transfer_len; ++ pbuf = precvbuf->pbuf; ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++#if 0 //temp remove when disable usb rx aggregation ++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_lenrxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4)); ++ ++ prxstat = (struct recv_stat *)pbuf; ++ ++ precvframe = rtw_alloc_recvframe(pfree_recv_queue); ++ if(precvframe==NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n")); ++ DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe->u.hdr.len=0; ++ ++ //rtl8192c_query_rx_desc_status(precvframe, prxstat); ++ update_recvframe_attrib_88e(precvframe, prxstat); ++ ++ pattrib = &precvframe->u.hdr.attrib; ++ ++ if ((padapter->registrypriv.mp_mode == 0) &&((pattrib->crc_err) || (pattrib->icv_err))) ++ { ++ DBG_8192C("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); ++ ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ ++ if( (pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX)) ++ { ++ pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET); ++ } ++ ++ pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len; ++ ++ if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n")); ++ DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__); ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if (pattrib->qos) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ skb_len = pattrib->pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ pkt_copy = rtw_skb_alloc(alloc_sz); ++ ++ if(pkt_copy) ++ { ++ pkt_copy->dev = padapter->pnetdev; ++ precvframe->u.hdr.pkt = pkt_copy; ++ precvframe->u.hdr.rx_head = pkt_copy->data; ++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len); ++ precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; ++ } ++ else ++ { ++ DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n"); ++ //precvframe->u.hdr.pkt = rtw_skb_clone(pskb); ++ //precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; ++ //precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); ++ ++ precvframe->u.hdr.pkt = NULL; ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ recvframe_put(precvframe, skb_len); ++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ case USB_RX_AGG_MIX: ++ pkt_offset = (u16)_RND128(pkt_offset); ++ break; ++ case USB_RX_AGG_USB: ++ pkt_offset = (u16)_RND4(pkt_offset); ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ break; ++ } ++#endif ++ ++ if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ if(pre_recv_entry(precvframe, prxstat, pphy_status) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ else ++#endif ++ { ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); ++ if(rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ ++ } ++ else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP ++ ++ //enqueue recvframe to txrtp queue ++ if(pattrib->pkt_rpt_type == TX_REPORT1){ ++ //DBG_8192C("rx CCX \n"); ++ //CCX-TXRPT ack for xmit mgmt frames. ++ handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data); ++ ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT2){ ++ //DBG_8192C("rx TX RPT \n"); ++ ODM_RA_TxRPT2Handle_8188E( ++ &pHalData->odmpriv, ++ precvframe->u.hdr.rx_data, ++ pattrib->pkt_len, ++ pattrib->MacIDValidEntry[0], ++ pattrib->MacIDValidEntry[1] ++ ); ++ ++ } ++ else if(pattrib->pkt_rpt_type == HIS_REPORT) ++ { ++ //DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); ++ #ifdef CONFIG_SUPPORT_USB_INT ++ interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data); ++ #endif ++ } ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ ++ } ++ ++ pkt_cnt--; ++ transfer_len -= pkt_offset; ++ pbuf += pkt_offset; ++ precvframe = NULL; ++ pkt_copy = NULL; ++ ++ if(transfer_len>0 && pkt_cnt==0) ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++ }while((transfer_len>0) && (pkt_cnt>0)); ++ ++_exit_recvbuf2recvframe: ++ ++ return _SUCCESS; ++} ++ ++void rtl8188eu_recv_tasklet(void *priv) ++{ ++ struct recv_buf *precvbuf = NULL; ++ _adapter *padapter = (_adapter*)priv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); ++ ++ break; ++ } ++ ++ ++ recvbuf2recvframe(padapter, precvbuf); ++ ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ ++} ++ ++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context; ++ _adapter *padapter =(_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); ++ ++ precvpriv->rx_pending_cnt --; ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", ++ __FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel); ++ goto exit; ++ } ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); ++ ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); ++ ++ precvbuf->transfer_len = purb->actual_length; ++ ++ //rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); ++ rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ tasklet_schedule(&precvpriv->recv_tasklet); ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ ++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); ++ ++ if(rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ case -EILSEQ: ++ case -ETIME: ++ case -ECOMM: ++ case -EOVERFLOW: ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; ++ } ++ #endif ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ int err; ++ unsigned int pipe; ++ u32 ret = _SUCCESS; ++ PURB purb = NULL; ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ _adapter *adapter = pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++_func_enter_; ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++ if(precvbuf !=NULL) ++ { ++ rtl8188eu_init_recvbuf(adapter, precvbuf); ++ ++ if(precvbuf->pbuf) ++ { ++ precvpriv->rx_pending_cnt++; ++ ++ purb = precvbuf->purb; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ precvbuf->pbuf, ++ MAX_RECVBUF_SZ, ++ usb_read_port_complete, ++ precvbuf);//context is precvbuf ++ ++ purb->transfer_dma = precvbuf->dma_transfer_addr; ++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); ++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status); ++ ret = _FAIL; ++ } ++ ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n")); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#else // CONFIG_USE_USB_BUFFER_ALLOC_RX ++static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) ++{ ++ u8 *pbuf; ++ u8 shift_sz = 0; ++ u16 pkt_cnt; ++ u32 pkt_offset, skb_len, alloc_sz; ++ s32 transfer_len; ++ struct recv_stat *prxstat; ++ struct phy_stat *pphy_status = NULL; ++ _pkt *pkt_copy = NULL; ++ union recv_frame *precvframe = NULL; ++ struct rx_pkt_attrib *pattrib = NULL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ ++ ++ transfer_len = (s32)pskb->len; ++ pbuf = pskb->data; ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++#if 0 //temp remove when disable usb rx aggregation ++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_lenrxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4)); ++ ++ prxstat = (struct recv_stat *)pbuf; ++ ++ precvframe = rtw_alloc_recvframe(pfree_recv_queue); ++ if(precvframe==NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n")); ++ DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe->u.hdr.len=0; ++ ++ //rtl8192c_query_rx_desc_status(precvframe, prxstat); ++ update_recvframe_attrib_88e(precvframe, prxstat); ++ ++ pattrib = &precvframe->u.hdr.attrib; ++ ++ if ((padapter->registrypriv.mp_mode == 0) &&((pattrib->crc_err) || (pattrib->icv_err))) ++ { ++ DBG_8192C("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); ++ ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ if( (pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX)) ++ { ++ pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET); ++ } ++ ++ pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len; ++ ++ if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n")); ++ DBG_8192C("%s()-%d: RX Warning!,pkt_len<=0 or pkt_offset> transfoer_len \n", __FUNCTION__, __LINE__); ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if (pattrib->qos) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ skb_len = pattrib->pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ pkt_copy = rtw_skb_alloc(alloc_sz); ++ ++ if(pkt_copy) ++ { ++ pkt_copy->dev = padapter->pnetdev; ++ precvframe->u.hdr.pkt = pkt_copy; ++ precvframe->u.hdr.rx_head = pkt_copy->data; ++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len); ++ precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; ++ } ++ else ++ { ++ if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) ++ { ++ DBG_8192C("recvbuf2recvframe: alloc_skb fail , drop frag frame \n"); ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ precvframe->u.hdr.pkt = rtw_skb_clone(pskb); ++ if(precvframe->u.hdr.pkt) ++ { ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail ++ = pbuf+ pattrib->drvinfo_sz + RXDESC_SIZE; ++ precvframe->u.hdr.rx_end = pbuf +pattrib->drvinfo_sz + RXDESC_SIZE+ alloc_sz; ++ } ++ else ++ { ++ DBG_8192C("recvbuf2recvframe: rtw_skb_clone fail\n"); ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ } ++ ++ recvframe_put(precvframe, skb_len); ++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ case USB_RX_AGG_MIX: ++ pkt_offset = (u16)_RND128(pkt_offset); ++ break; ++ case USB_RX_AGG_USB: ++ pkt_offset = (u16)_RND4(pkt_offset); ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ break; ++ } ++#endif ++ ++ if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ if(pre_recv_entry(precvframe, prxstat, pphy_status) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ else ++#endif ++ { ++ if (pattrib->physt) ++ update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); ++ if(rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ++ ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ } ++ else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP ++ ++ //enqueue recvframe to txrtp queue ++ if(pattrib->pkt_rpt_type == TX_REPORT1){ ++ //DBG_8192C("rx CCX \n"); ++ //CCX-TXRPT ack for xmit mgmt frames. ++ handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data); ++ } ++ else if(pattrib->pkt_rpt_type == TX_REPORT2){ ++ //DBG_8192C("rx TX RPT \n"); ++ ODM_RA_TxRPT2Handle_8188E( ++ &pHalData->odmpriv, ++ precvframe->u.hdr.rx_data, ++ pattrib->pkt_len, ++ pattrib->MacIDValidEntry[0], ++ pattrib->MacIDValidEntry[1] ++ ); ++ ++ } ++ else if(pattrib->pkt_rpt_type == HIS_REPORT) ++ { ++ //DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); ++ #ifdef CONFIG_SUPPORT_USB_INT ++ interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data); ++ #endif ++ } ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ ++ } ++ ++ pkt_cnt--; ++ transfer_len -= pkt_offset; ++ pbuf += pkt_offset; ++ precvframe = NULL; ++ pkt_copy = NULL; ++ ++ if(transfer_len>0 && pkt_cnt==0) ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++ }while((transfer_len>0) && (pkt_cnt>0)); ++ ++_exit_recvbuf2recvframe: ++ ++ return _SUCCESS; ++} ++ ++void rtl8188eu_recv_tasklet(void *priv) ++{ ++ _pkt *pskb; ++ _adapter *padapter = (_adapter*)priv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); ++ rtw_skb_free(pskb); ++ break; ++ } ++ ++ recvbuf2recvframe(padapter, pskb); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ ++ skb_reset_tail_pointer(pskb); ++ ++ pskb->len = 0; ++ ++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); ++ ++#else ++ rtw_skb_free(pskb); ++#endif ++ ++ } ++ ++} ++ ++ ++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ _irqL irqL; ++ uint isevt, *pbuf; ++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context; ++ _adapter *padapter =(_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); ++ ++ //_enter_critical(&precvpriv->lock, &irqL); ++ //precvbuf->irp_pending=_FALSE; ++ //precvpriv->rx_pending_cnt --; ++ //_exit_critical(&precvpriv->lock, &irqL); ++ ++ precvpriv->rx_pending_cnt --; ++ ++ //if(precvpriv->rx_pending_cnt== 0) ++ //{ ++ // RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); ++ // _rtw_up_sema(&precvpriv->allrxreturnevt); ++ //} ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ ++ #ifdef CONFIG_PREALLOC_RECV_SKB ++ precvbuf->reuse = _TRUE; ++ #else ++ if(precvbuf->pskb){ ++ DBG_8192C("==> free skb(%p)\n",precvbuf->pskb); ++ rtw_skb_free(precvbuf->pskb); ++ } ++ #endif ++ DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", ++ __FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel); ++ goto exit; ++ } ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); ++ precvbuf->reuse = _TRUE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); ++ ++ precvbuf->transfer_len = purb->actual_length; ++ skb_put(precvbuf->pskb, purb->actual_length); ++ skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); ++ ++ if (skb_queue_len(&precvpriv->rx_skb_queue)<=1) ++ tasklet_schedule(&precvpriv->recv_tasklet); ++ ++ precvbuf->pskb = NULL; ++ precvbuf->reuse = _FALSE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ ++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); ++ ++ if(rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ case -EILSEQ: ++ case -ETIME: ++ case -ECOMM: ++ case -EOVERFLOW: ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; ++ } ++ #endif ++ precvbuf->reuse = _TRUE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ _irqL irqL; ++ int err; ++ unsigned int pipe; ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ u32 ret = _SUCCESS; ++ PURB purb = NULL; ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ _adapter *adapter = pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++ ++_func_enter_; ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL)) ++ { ++ if (NULL != (precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue))) ++ { ++ precvbuf->reuse = _TRUE; ++ } ++ } ++#endif ++ ++ ++ if(precvbuf !=NULL) ++ { ++ rtl8188eu_init_recvbuf(adapter, precvbuf); ++ ++ //re-assign for linux based on skb ++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL)) ++ { ++ precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++ ++ if(precvbuf->pskb == NULL) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n")); ++ DBG_8192C("#### usb_read_port() alloc_skb fail!#####\n"); ++ return _FAIL; ++ } ++ ++ tmpaddr = (SIZE_PTR)precvbuf->pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); ++ precvbuf->pend = skb_end_pointer(precvbuf->pskb); ++ precvbuf->pbuf = precvbuf->pskb->data; ++ } ++ else//reuse skb ++ { ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); ++ precvbuf->pend = skb_end_pointer(precvbuf->pskb); ++ precvbuf->pbuf = precvbuf->pskb->data; ++ ++ precvbuf->reuse = _FALSE; ++ } ++ ++ //_enter_critical(&precvpriv->lock, &irqL); ++ //precvpriv->rx_pending_cnt++; ++ //precvbuf->irp_pending = _TRUE; ++ //_exit_critical(&precvpriv->lock, &irqL); ++ ++ precvpriv->rx_pending_cnt++; ++ ++ purb = precvbuf->purb; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ precvbuf->pbuf, ++ MAX_RECVBUF_SZ, ++ usb_read_port_complete, ++ precvbuf);//context is precvbuf ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); ++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status); ++ ret = _FAIL; ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n")); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++void rtl8188eu_xmit_tasklet(void *priv) ++{ ++ int ret = _FALSE; ++ _adapter *padapter = (_adapter*)priv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ return; ++ ++ while(1) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE)) ++ { ++ DBG_8192C("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n"); ++ break; ++ } ++ ++ ret = rtl8188eu_xmitframe_complete(padapter, pxmitpriv, NULL); ++ ++ if(ret==_FALSE) ++ break; ++ ++ } ++ ++} ++ ++void rtl8188eu_set_intf_ops(struct _io_ops *pops) ++{ ++ _func_enter_; ++ ++ _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops)); ++ ++ pops->_read8 = &usb_read8; ++ pops->_read16 = &usb_read16; ++ pops->_read32 = &usb_read32; ++ pops->_read_mem = &usb_read_mem; ++ pops->_read_port = &usb_read_port; ++ ++ pops->_write8 = &usb_write8; ++ pops->_write16 = &usb_write16; ++ pops->_write32 = &usb_write32; ++ pops->_writeN = &usb_writeN; ++ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++ pops->_write8_async= &usb_async_write8; ++ pops->_write16_async = &usb_async_write16; ++ pops->_write32_async = &usb_async_write32; ++#endif ++ pops->_write_mem = &usb_write_mem; ++ pops->_write_port = &usb_write_port; ++ ++ pops->_read_port_cancel = &usb_read_port_cancel; ++ pops->_write_port_cancel = &usb_write_port_cancel; ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ pops->_read_interrupt = &usb_read_interrupt; ++#endif ++ ++ _func_exit_; ++ ++} ++ ++void rtl8188eu_set_hw_type(_adapter *padapter) ++{ ++ padapter->chip_type = RTL8188E; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8188EU; ++ DBG_871X("CHIP TYPE: RTL8188E\n"); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/ifcfg-wlan0 b/drivers/net/wireless/rtl818x/rtl8189/ifcfg-wlan0 +new file mode 100644 +index 00000000..20dcbec2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/ifcfg-wlan0 +@@ -0,0 +1,4 @@ ++#DHCP client ++DEVICE=wlan0 ++BOOTPROTO=dhcp ++ONBOOT=yes +\ No newline at end of file +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyCfg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyCfg.h +new file mode 100644 +index 00000000..e9b97cc1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyCfg.h +@@ -0,0 +1,429 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8188EPHYCFG_H__ ++#define __INC_HAL8188EPHYCFG_H__ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define LOOP_LIMIT 5 ++#define MAX_STALL_TIME 50 //us ++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) ++#define MAX_TXPWR_IDX_NMODE_92S 63 ++#define Reset_Cnt_Limit 3 ++ ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 9 ++#define HP_THERMAL_NUM 8 ++ ++#ifdef CONFIG_PCI_HCI ++#define MAX_AGGR_NUM 0x0B ++#else ++#define MAX_AGGR_NUM 0x07 ++#endif // CONFIG_PCI_HCI ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}SwChnlCmd; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++typedef enum _RF_RADIO_PATH{ ++ RF_PATH_A = 0, //Radio Path A ++ RF_PATH_B = 1, //Radio Path B ++ RF_PATH_C = 2, //Radio Path C ++ RF_PATH_D = 3, //Radio Path D ++ //RF_PATH_MAX //Max RF number 90 support ++}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; ++ ++#define MAX_PG_GROUP 13 ++ ++#define RF_PATH_MAX 2 ++#define MAX_RF_PATH RF_PATH_MAX ++#define MAX_TX_COUNT_88E 1 ++#define MAX_TX_COUNT MAX_TX_COUNT_88E // 4 //path numbers ++ ++#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number ++#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups ++#define CHANNEL_GROUP_MAX_88E 6 ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = BIT2, ++ WIRELESS_MODE_B = BIT0, ++ WIRELESS_MODE_G = BIT1, ++ WIRELESS_MODE_AUTO = BIT5, ++ WIRELESS_MODE_N_24G = BIT3, ++ WIRELESS_MODE_N_5G = BIT4, ++ WIRELESS_MODE_AC = BIT6 ++} WIRELESS_MODE; ++ ++ ++typedef enum _PHY_Rate_Tx_Power_Offset_Area{ ++ RA_OFFSET_LEGACY_OFDM1, ++ RA_OFFSET_LEGACY_OFDM2, ++ RA_OFFSET_HT_OFDM1, ++ RA_OFFSET_HT_OFDM2, ++ RA_OFFSET_HT_OFDM3, ++ RA_OFFSET_HT_OFDM4, ++ RA_OFFSET_HT_CCK, ++}RA_OFFSET_AREA,*PRA_OFFSET_AREA; ++ ++ ++/* BB/RF related */ ++typedef enum _RF_TYPE_8190P{ ++ RF_TYPE_MIN, // 0 ++ RF_8225=1, // 1 11b/g RF for verification only ++ RF_8256=2, // 2 11b/g/n ++ RF_8258=3, // 3 11a/b/g/n RF ++ RF_6052=4, // 4 11b/g/n RF ++ //RF_6052=5, // 4 11b/g/n RF ++ // TODO: We sholud remove this psudo PHY RF after we get new RF. ++ RF_PSEUDO_11N=5, // 5, It is a temporality RF. ++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; ++ ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: ++ // 0x870~0x877[8 bytes] ++ ++ u32 rfintfi; // readback data: ++ // 0x8e0~0x8e7[8 bytes] ++ ++ u32 rfintfo; // output data: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rfintfe; // output enable: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rf3wireOffset; // LSSI data: ++ // 0x840~0x84f [16 bytes] ++ ++ u32 rfLSSI_Select; // BB Band Select: ++ // 0x878~0x87f [8 bytes] ++ ++ u32 rfTxGainStage; // Tx gain stage: ++ // 0x80c~0x80f [4 bytes] ++ ++ u32 rfHSSIPara1; // wire parameter control1 : ++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ ++ u32 rfHSSIPara2; // wire parameter control2 : ++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ ++ u32 rfSwitchControl; //Tx Rx antenna control : ++ // 0x858~0x85f [16 bytes] ++ ++ u32 rfAGCControl1; //AGC parameter control1 : ++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ ++ u32 rfAGCControl2; //AGC parameter control2 : ++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : ++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : ++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix ++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type ++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ ++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode ++ // 0x8a0~0x8af [16 bytes] ++ ++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B ++ ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++typedef struct _R_ANTENNA_SELECT_OFDM{ ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK{ ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++// ++// BB and RF register read/write ++// ++u32 rtl8188e_PHY_QueryBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8188e_PHY_SetBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8188e_PHY_QueryRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8188e_PHY_SetRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++int PHY_MACConfig8188E(IN PADAPTER Adapter ); ++int PHY_BBConfig8188E(IN PADAPTER Adapter ); ++int PHY_RFConfig8188E(IN PADAPTER Adapter ); ++ ++/* RF config */ ++int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath); ++int rtl8188e_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath); ++ ++/* Read initi reg value for tx power setting. */ ++void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter ); ++ ++// ++// RF Power setting ++// ++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, ++// IN RT_RF_POWER_STATE eRFPowerState); ++ ++// ++// BB TX Power R/W ++// ++void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter, ++ OUT u32* powerlevel ); ++void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter, ++ IN u8 channel ); ++BOOLEAN PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter, ++ IN int powerInDbm ); ++ ++// ++VOID ++PHY_ScanOperationBackup8188E(IN PADAPTER Adapter, ++ IN u8 Operation ); ++ ++// ++// Switch bandwidth for 8192S ++// ++//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SetBWMode8188E( IN PADAPTER pAdapter, ++ IN HT_CHANNEL_WIDTH ChnlWidth, ++ IN unsigned char Offset ); ++ ++// ++// Set FW CMD IO for 8192S. ++// ++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, ++// IN IO_TYPE IOType); ++ ++// ++// Set A2 entry to fw for 8192S ++// ++extern void FillA2Entry8192C( IN PADAPTER Adapter, ++ IN u8 index, ++ IN u8* val); ++ ++ ++// ++// channel switch related funciton ++// ++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SwChnl8188E( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ // Call after initialization ++void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ ++void ChkFwCmdIoDone( IN PADAPTER Adapter); ++ ++// ++// BB/MAC/RF other monitor API ++// ++void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ); ++ ++BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter, ++ IN u32 eRFPath ); ++ ++VOID PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN BOOLEAN bMain); ++ ++extern VOID ++PHY_SwitchEphyParameter( ++ IN PADAPTER Adapter ++ ); ++ ++extern VOID ++PHY_EnableHostClkReq( ++ IN PADAPTER Adapter ++ ); ++ ++BOOLEAN ++SetAntennaConfig92C( ++ IN PADAPTER Adapter, ++ IN u8 DefaultAnt ++ ); ++ ++#ifdef CONFIG_PHY_SETTING_WITH_ODM ++VOID ++storePwrIndexDiffRateOffset( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ); ++#endif //CONFIG_PHY_SETTING_WITH_ODM ++/*--------------------------Exported Function prototype---------------------*/ ++ ++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask)) ++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask)) ++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) ++ ++#define PHY_SetMacReg PHY_SetBBReg ++#define PHY_QueryMacReg PHY_QueryBBReg ++ ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++//extern s32 PHY_MACConfig8723(PADAPTER padapter); ++//s32 PHY_BBConfig8723(PADAPTER padapter); ++//s32 PHY_RFConfig8723(PADAPTER padapter); ++ ++ ++ ++//================================================================== ++// Note: If SIC_ENABLE under PCIE, because of the slow operation ++// you should ++// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows ++// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed. ++// ++#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) ++#define SIC_ENABLE 1 ++#define SIC_HW_SUPPORT 1 ++#else ++#define SIC_ENABLE 0 ++#define SIC_HW_SUPPORT 0 ++#endif ++//================================================================== ++ ++ ++#define SIC_MAX_POLL_CNT 5 ++ ++#if(SIC_HW_SUPPORT == 1) ++#define SIC_CMD_READY 0 ++#define SIC_CMD_PREWRITE 0x1 ++#if(RTL8188E_SUPPORT == 1) ++#define SIC_CMD_WRITE 0x40 ++#define SIC_CMD_PREREAD 0x2 ++#define SIC_CMD_READ 0x80 ++#define SIC_CMD_INIT 0xf0 ++#define SIC_INIT_VAL 0xff ++ ++#define SIC_INIT_REG 0x1b7 ++#define SIC_CMD_REG 0x1EB // 1byte ++#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes ++#define SIC_DATA_REG 0x1EC // 1b0~1b3 ++#else ++#define SIC_CMD_WRITE 0x11 ++#define SIC_CMD_PREREAD 0x2 ++#define SIC_CMD_READ 0x12 ++#define SIC_CMD_INIT 0x1f ++#define SIC_INIT_VAL 0xff ++ ++#define SIC_INIT_REG 0x1b7 ++#define SIC_CMD_REG 0x1b6 // 1byte ++#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes ++#define SIC_DATA_REG 0x1b0 // 1b0~1b3 ++#endif ++#else ++#define SIC_CMD_READY 0 ++#define SIC_CMD_WRITE 1 ++#define SIC_CMD_READ 2 ++ ++#if(RTL8188E_SUPPORT == 1) ++#define SIC_CMD_REG 0x1EB // 1byte ++#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes ++#define SIC_DATA_REG 0x1EC // 1bc~1bf ++#else ++#define SIC_CMD_REG 0x1b8 // 1byte ++#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes ++#define SIC_DATA_REG 0x1bc // 1bc~1bf ++#endif ++#endif ++ ++#if(SIC_ENABLE == 1) ++VOID SIC_Init(IN PADAPTER Adapter); ++#endif ++ ++ ++#endif // __INC_HAL8192CPHYCFG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyReg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyReg.h +new file mode 100644 +index 00000000..f83e6096 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPhyReg.h +@@ -0,0 +1,1112 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8188EPHYREG_H__ ++#define __INC_HAL8188EPHYREG_H__ ++/*--------------------------Define Parameters-------------------------------*/ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++ ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 ++#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback ++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// PageB(0xB00) ++// ++#define rPdp_AntA 0xb00 ++#define rPdp_AntA_4 0xb04 ++#define rConfig_Pmpd_AntA 0xb28 ++#define rConfig_AntA 0xb68 ++#define rConfig_AntB 0xb6c ++#define rPdp_AntB 0xb70 ++#define rPdp_AntB_4 0xb74 ++#define rConfig_Pmpd_AntB 0xb98 ++#define rAPK 0xbd8 ++ ++ ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++ ++#define rOFDM0_RxIQExtAnta 0xca0 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++ ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_csi_fix_mask 0xd40 ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_A_Rate18_06 0xe00 ++#define rTxAGC_A_Rate54_24 0xe04 ++#define rTxAGC_A_CCK1_Mcs32 0xe08 ++#define rTxAGC_A_Mcs03_Mcs00 0xe10 ++#define rTxAGC_A_Mcs07_Mcs04 0xe14 ++#define rTxAGC_A_Mcs11_Mcs08 0xe18 ++#define rTxAGC_A_Mcs15_Mcs12 0xe1c ++ ++#define rTxAGC_B_Rate18_06 0x830 ++#define rTxAGC_B_Rate54_24 0x834 ++#define rTxAGC_B_CCK1_55_Mcs32 0x838 ++#define rTxAGC_B_Mcs03_Mcs00 0x83c ++#define rTxAGC_B_Mcs07_Mcs04 0x848 ++#define rTxAGC_B_Mcs11_Mcs08 0x84c ++#define rTxAGC_B_Mcs15_Mcs12 0x868 ++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c ++ ++#define rFPGA0_IQK 0xe28 ++#define rTx_IQK_Tone_A 0xe30 ++#define rRx_IQK_Tone_A 0xe34 ++#define rTx_IQK_PI_A 0xe38 ++#define rRx_IQK_PI_A 0xe3c ++ ++#define rTx_IQK 0xe40 ++#define rRx_IQK 0xe44 ++#define rIQK_AGC_Pts 0xe48 ++#define rIQK_AGC_Rsp 0xe4c ++#define rTx_IQK_Tone_B 0xe50 ++#define rRx_IQK_Tone_B 0xe54 ++#define rTx_IQK_PI_B 0xe58 ++#define rRx_IQK_PI_B 0xe5c ++#define rIQK_AGC_Cont 0xe60 ++ ++#define rBlue_Tooth 0xe6c ++#define rRx_Wait_CCA 0xe70 ++#define rTx_CCK_RFON 0xe74 ++#define rTx_CCK_BBON 0xe78 ++#define rTx_OFDM_RFON 0xe7c ++#define rTx_OFDM_BBON 0xe80 ++#define rTx_To_Rx 0xe84 ++#define rTx_To_Tx 0xe88 ++#define rRx_CCK 0xe8c ++ ++#define rTx_Power_Before_IQK_A 0xe94 ++#define rTx_Power_After_IQK_A 0xe9c ++ ++#define rRx_Power_Before_IQK_A 0xea0 ++#define rRx_Power_Before_IQK_A_2 0xea4 ++#define rRx_Power_After_IQK_A 0xea8 ++#define rRx_Power_After_IQK_A_2 0xeac ++ ++#define rTx_Power_Before_IQK_B 0xeb4 ++#define rTx_Power_After_IQK_B 0xebc ++ ++#define rRx_Power_Before_IQK_B 0xec0 ++#define rRx_Power_Before_IQK_B_2 0xec4 ++#define rRx_Power_After_IQK_B 0xec8 ++#define rRx_Power_After_IQK_B_2 0xecc ++ ++#define rRx_OFDM 0xed0 ++#define rRx_Wait_RIFS 0xed4 ++#define rRx_TO_Rx 0xed8 ++#define rStandby 0xedc ++#define rSleep 0xee0 ++#define rPMPD_ANAEN 0xeec ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 // RF channel switch ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++ ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_IPA_G 0x09 // ++#define RF_TXBIAS_G 0x0A ++#define RF_TXPA_AG 0x0B ++#define RF_IPA_A 0x0C // ++#define RF_TXBIAS_A 0x0D ++#define RF_BS_PA_APSET_G9_G11 0x0E ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_TXBIAS 0x16 ++#define RF_POW_ABILITY 0x17 // ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++//#if HARDWARE_TYPE_IS_RTL8192D == 1 ++#define RF_T_METER_92D 0x42 // ++//#else ++#define RF_T_METER_88E 0x42 // ++#define RF_T_METER 0x24 // ++ ++//#endif ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++#define RF_TX_BIAS_A 0x35 ++#define RF_TX_BIAS_D 0x36 ++#define RF_LOBF_9 0x38 ++#define RF_RXRF_A3 0x3C // ++#define RF_TRSW 0x3F ++ ++#define RF_TXRF_A2 0x41 ++#define RF_TXPA_G4 0x46 ++#define RF_TXPA_A4 0x4B ++#define RF_0x52 0x52 ++#define RF_WE_LUT 0xEF ++ ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bAntennaSelect 0x0300 ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++ ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++ ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++ ++#define bLSSIReadBackData 0xfffff // T65 RF ++ ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMask12Bits 0xfff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++ ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 // Useless ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPwrSeq.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPwrSeq.h +new file mode 100644 +index 00000000..915da604 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8188EPwrSeq.h +@@ -0,0 +1,177 @@ ++ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __HAL8188EPWRSEQ_H__ ++#define __HAL8188EPWRSEQ_H__ ++ ++#include "HalPwrSeqCmd.h" ++ ++/* ++ Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd ++ There are 6 HW Power States: ++ 0: POFF--Power Off ++ 1: PDN--Power Down ++ 2: CARDEMU--Card Emulation ++ 3: ACT--Active Mode ++ 4: LPS--Low Power State ++ 5: SUS--Suspend ++ ++ The transision from different states are defined below ++ TRANS_CARDEMU_TO_ACT ++ TRANS_ACT_TO_CARDEMU ++ TRANS_CARDEMU_TO_SUS ++ TRANS_SUS_TO_CARDEMU ++ TRANS_CARDEMU_TO_PDN ++ TRANS_ACT_TO_LPS ++ TRANS_LPS_TO_ACT ++ ++ TRANS_END ++ ++ PWR SEQ Version: rtl8188E_PwrSeq_V09.h ++*/ ++#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 ++#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 ++#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 ++#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 ++#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 ++#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 ++#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 ++#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 ++#define RTL8188E_TRANS_END_STEPS 1 ++ ++ ++#define RTL8188E_TRANS_CARDEMU_TO_ACT \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \ ++ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \ ++ {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \ ++ ++#define RTL8188E_TRANS_ACT_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ ++ ++#define RTL8188E_TRANS_CARDEMU_TO_SUS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ ++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ ++ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ ++ {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ ++ ++#define RTL8188E_TRANS_SUS_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ ++ ++#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ ++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ ++ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ ++ {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ ++ ++#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ ++ ++#define RTL8188E_TRANS_CARDEMU_TO_PDN \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ ++ ++#define RTL8188E_TRANS_PDN_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ ++ ++//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step ++#define RTL8188E_TRANS_ACT_TO_LPS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ ++ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ ++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ ++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ ++ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ ++ ++ ++#define RTL8188E_TRANS_LPS_TO_ACT \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ ++ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ ++ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ ++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ ++ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ ++ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ ++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ ++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ ++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ ++ ++#define RTL8188E_TRANS_END \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // ++ ++ ++extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; ++ ++#endif //__HAL8188EPWRSEQ_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyCfg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyCfg.h +new file mode 100644 +index 00000000..b27642c7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyCfg.h +@@ -0,0 +1,396 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * Module: __INC_HAL8192CPHYCFG_H ++ * ++ * ++ * Note: ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * ++ *****************************************************************************/ ++ /* Check to see if the file has been included already. */ ++#ifndef __INC_HAL8192CPHYCFG_H ++#define __INC_HAL8192CPHYCFG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define LOOP_LIMIT 5 ++#define MAX_STALL_TIME 50 //us ++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) ++#define MAX_TXPWR_IDX_NMODE_92S 63 ++#define Reset_Cnt_Limit 3 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define MAX_AGGR_NUM 0x0A0A ++#else ++#define MAX_AGGR_NUM 0x0909 ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \ ++{ \ ++ u1Byte u1bTmp; \ ++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \ ++ u1bTmp |= BIT0; \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \ ++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++ delay_us(100); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++} ++#endif ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}SwChnlCmd; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++typedef enum _RF_RADIO_PATH{ ++ RF_PATH_A = 0, //Radio Path A ++ RF_PATH_B = 1, //Radio Path B ++ RF_PATH_C = 2, //Radio Path C ++ RF_PATH_D = 3, //Radio Path D ++ //RF_PATH_MAX //Max RF number 90 support ++}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; ++ ++#define RF_PATH_MAX 2 ++ ++#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number ++#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = BIT2, ++ WIRELESS_MODE_B = BIT0, ++ WIRELESS_MODE_G = BIT1, ++ WIRELESS_MODE_AUTO = BIT5, ++ WIRELESS_MODE_N_24G = BIT3, ++ WIRELESS_MODE_N_5G = BIT4, ++ WIRELESS_MODE_AC = BIT6 ++} WIRELESS_MODE; ++ ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, //Radio Path A ++ BaseBand_Config_AGC_TAB = 1, //Radio Path B ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++ ++ ++typedef enum _PHY_Rate_Tx_Power_Offset_Area{ ++ RA_OFFSET_LEGACY_OFDM1, ++ RA_OFFSET_LEGACY_OFDM2, ++ RA_OFFSET_HT_OFDM1, ++ RA_OFFSET_HT_OFDM2, ++ RA_OFFSET_HT_OFDM3, ++ RA_OFFSET_HT_OFDM4, ++ RA_OFFSET_HT_CCK, ++}RA_OFFSET_AREA,*PRA_OFFSET_AREA; ++ ++ ++/* BB/RF related */ ++typedef enum _RF_TYPE_8190P{ ++ RF_TYPE_MIN, // 0 ++ RF_8225=1, // 1 11b/g RF for verification only ++ RF_8256=2, // 2 11b/g/n ++ RF_8258=3, // 3 11a/b/g/n RF ++ RF_6052=4, // 4 11b/g/n RF ++ //RF_6052=5, // 4 11b/g/n RF ++ // TODO: We sholud remove this psudo PHY RF after we get new RF. ++ RF_PSEUDO_11N=5, // 5, It is a temporality RF. ++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; ++ ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: ++ // 0x870~0x877[8 bytes] ++ ++ u32 rfintfi; // readback data: ++ // 0x8e0~0x8e7[8 bytes] ++ ++ u32 rfintfo; // output data: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rfintfe; // output enable: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rf3wireOffset; // LSSI data: ++ // 0x840~0x84f [16 bytes] ++ ++ u32 rfLSSI_Select; // BB Band Select: ++ // 0x878~0x87f [8 bytes] ++ ++ u32 rfTxGainStage; // Tx gain stage: ++ // 0x80c~0x80f [4 bytes] ++ ++ u32 rfHSSIPara1; // wire parameter control1 : ++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ ++ u32 rfHSSIPara2; // wire parameter control2 : ++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ ++ u32 rfSwitchControl; //Tx Rx antenna control : ++ // 0x858~0x85f [16 bytes] ++ ++ u32 rfAGCControl1; //AGC parameter control1 : ++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ ++ u32 rfAGCControl2; //AGC parameter control2 : ++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : ++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : ++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix ++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type ++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ ++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode ++ // 0x8a0~0x8af [16 bytes] ++ ++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B ++ ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++typedef struct _R_ANTENNA_SELECT_OFDM{ ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK{ ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++// ++// BB and RF register read/write ++// ++u32 rtl8192c_PHY_QueryBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192c_PHY_SetBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192c_PHY_QueryRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192c_PHY_SetRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++int PHY_MACConfig8192C( IN PADAPTER Adapter ); ++int PHY_BBConfig8192C( IN PADAPTER Adapter ); ++int PHY_RFConfig8192C( IN PADAPTER Adapter ); ++/* RF config */ ++int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, ++ IN u8* pFileName, ++ IN RF_RADIO_PATH_E eRFPath); ++int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath); ++ ++/* BB/RF readback check for making sure init OK */ ++int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter, ++ IN HW90_BLOCK_E CheckBlock, ++ IN RF_RADIO_PATH_E eRFPath ); ++/* Read initi reg value for tx power setting. */ ++void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter ); ++ ++// ++// RF Power setting ++// ++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, ++// IN RT_RF_POWER_STATE eRFPowerState); ++ ++// ++// BB TX Power R/W ++// ++void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter, ++ OUT u32* powerlevel ); ++void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter, ++ IN u8 channel ); ++BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter, ++ IN int powerInDbm ); ++ ++// ++VOID ++PHY_ScanOperationBackup8192C(IN PADAPTER Adapter, ++ IN u8 Operation ); ++ ++// ++// Switch bandwidth for 8192S ++// ++//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SetBWMode8192C( IN PADAPTER pAdapter, ++ IN HT_CHANNEL_WIDTH ChnlWidth, ++ IN unsigned char Offset ); ++ ++// ++// Set FW CMD IO for 8192S. ++// ++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, ++// IN IO_TYPE IOType); ++ ++// ++// Set A2 entry to fw for 8192S ++// ++extern void FillA2Entry8192C( IN PADAPTER Adapter, ++ IN u8 index, ++ IN u8* val); ++ ++ ++// ++// channel switch related funciton ++// ++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SwChnl8192C( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ // Call after initialization ++void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ ++void ChkFwCmdIoDone( IN PADAPTER Adapter); ++ ++// ++// BB/MAC/RF other monitor API ++// ++void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ); ++ ++BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter, ++ IN u32 eRFPath ); ++ ++ ++VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain); ++ ++// ++// Modify the value of the hw register when beacon interval be changed. ++// ++void ++rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter, ++ IN u16 BeaconInterval ); ++ ++ ++extern VOID ++PHY_SwitchEphyParameter( ++ IN PADAPTER Adapter ++ ); ++ ++extern VOID ++PHY_EnableHostClkReq( ++ IN PADAPTER Adapter ++ ); ++ ++BOOLEAN ++SetAntennaConfig92C( ++ IN PADAPTER Adapter, ++ IN u8 DefaultAnt ++ ); ++ ++#ifdef RTL8192C_RECONFIG_TO_1T1R ++extern void PHY_Reconfig_To_1T1R(_adapter *padapter); ++#endif ++/*--------------------------Exported Function prototype---------------------*/ ++ ++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask)) ++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask)) ++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) ++ ++#define PHY_SetMacReg PHY_SetBBReg ++#define PHY_QueryMacReg PHY_QueryBBReg ++ ++#endif // __INC_HAL8192CPHYCFG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyReg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyReg.h +new file mode 100644 +index 00000000..49029956 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192CPhyReg.h +@@ -0,0 +1,1123 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192CPHYREG_H ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __INC_HAL8192CPHYREG_H ++#define __INC_HAL8192CPHYREG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++#define rTxAGC_B_Rate18_06 0x830 ++#define rTxAGC_B_Rate54_24 0x834 ++#define rTxAGC_B_CCK1_55_Mcs32 0x838 ++#define rTxAGC_B_Mcs03_Mcs00 0x83c ++ ++#define rTxAGC_B_Mcs07_Mcs04 0x848 ++#define rTxAGC_B_Mcs11_Mcs08 0x84c ++ ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++ ++#define rTxAGC_B_Mcs15_Mcs12 0x868 ++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 // Useless now ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback ++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++// ++// PageB(0xB00) ++// ++#define rPdp_AntA 0xb00 ++#define rPdp_AntA_4 0xb04 ++#define rConfig_Pmpd_AntA 0xb28 ++#define rConfig_AntA 0xb68 ++#define rConfig_AntB 0xb6c ++#define rPdp_AntB 0xb70 ++#define rPdp_AntB_4 0xb74 ++#define rConfig_Pmpd_AntB 0xb98 ++#define rAPK 0xbd8 ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++ ++#define rOFDM0_RxIQExtAnta 0xca0 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_A_Rate18_06 0xe00 ++#define rTxAGC_A_Rate54_24 0xe04 ++#define rTxAGC_A_CCK1_Mcs32 0xe08 ++#define rTxAGC_A_Mcs03_Mcs00 0xe10 ++#define rTxAGC_A_Mcs07_Mcs04 0xe14 ++#define rTxAGC_A_Mcs11_Mcs08 0xe18 ++#define rTxAGC_A_Mcs15_Mcs12 0xe1c ++ ++#define rFPGA0_IQK 0xe28 ++#define rTx_IQK_Tone_A 0xe30 ++#define rRx_IQK_Tone_A 0xe34 ++#define rTx_IQK_PI_A 0xe38 ++#define rRx_IQK_PI_A 0xe3c ++ ++#define rTx_IQK 0xe40 ++#define rRx_IQK 0xe44 ++#define rIQK_AGC_Pts 0xe48 ++#define rIQK_AGC_Rsp 0xe4c ++#define rTx_IQK_Tone_B 0xe50 ++#define rRx_IQK_Tone_B 0xe54 ++#define rTx_IQK_PI_B 0xe58 ++#define rRx_IQK_PI_B 0xe5c ++#define rIQK_AGC_Cont 0xe60 ++ ++#define rBlue_Tooth 0xe6c ++#define rRx_Wait_CCA 0xe70 ++#define rTx_CCK_RFON 0xe74 ++#define rTx_CCK_BBON 0xe78 ++#define rTx_OFDM_RFON 0xe7c ++#define rTx_OFDM_BBON 0xe80 ++#define rTx_To_Rx 0xe84 ++#define rTx_To_Tx 0xe88 ++#define rRx_CCK 0xe8c ++ ++#define rTx_Power_Before_IQK_A 0xe94 ++#define rTx_Power_After_IQK_A 0xe9c ++ ++#define rRx_Power_Before_IQK_A 0xea0 ++#define rRx_Power_Before_IQK_A_2 0xea4 ++#define rRx_Power_After_IQK_A 0xea8 ++#define rRx_Power_After_IQK_A_2 0xeac ++ ++#define rTx_Power_Before_IQK_B 0xeb4 ++#define rTx_Power_After_IQK_B 0xebc ++ ++#define rRx_Power_Before_IQK_B 0xec0 ++#define rRx_Power_Before_IQK_B_2 0xec4 ++#define rRx_Power_After_IQK_B 0xec8 ++#define rRx_Power_After_IQK_B_2 0xecc ++ ++#define rRx_OFDM 0xed0 ++#define rRx_Wait_RIFS 0xed4 ++#define rRx_TO_Rx 0xed8 ++#define rStandby 0xedc ++#define rSleep 0xee0 ++#define rPMPD_ANAEN 0xeec ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 // RF channel switch ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_BS_PA_APSET_G1_G4 0x03 ++#define RF_BS_PA_APSET_G5_G8 0x04 ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_IPA_G 0x09 // ++#define RF_TXBIAS_G 0x0A ++#define RF_TXPA_AG 0x0B ++#define RF_IPA_A 0x0C // ++#define RF_TXBIAS_A 0x0D ++#define RF_BS_PA_APSET_G9_G11 0x0E ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_TXBIAS 0x16 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x24 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bAntennaSelect 0x0300 ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++ ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++ ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++ ++#define bLSSIReadBackData 0xfffff // T65 RF ++ ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMask12Bits 0xfff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++ ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 // Useless ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyCfg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyCfg.h +new file mode 100644 +index 00000000..f2e55df8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyCfg.h +@@ -0,0 +1,487 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192DPHYCFG_H ++ * ++ * ++ * Note: ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * ++ *****************************************************************************/ ++ /* Check to see if the file has been included already. */ ++#ifndef __INC_HAL8192DPHYCFG_H ++#define __INC_HAL8192DPHYCFG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define LOOP_LIMIT 5 ++#define MAX_STALL_TIME 50 //us ++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) ++#define MAX_TXPWR_IDX_NMODE_92S 63 ++#define Reset_Cnt_Limit 3 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \ ++{ \ ++ u1Byte u1bTmp; \ ++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \ ++ u1bTmp |= BIT0; \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \ ++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++ delay_us(100); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++} ++#endif ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}SwChnlCmd; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++//vivi added this for read parameter from header, 20100908 ++typedef enum _RF_CONTENT{ ++ radioa_txt = 0x1000, ++ radiob_txt = 0x1001, ++ radioc_txt = 0x1002, ++ radiod_txt = 0x1003 ++} RF_CONTENT; ++ ++typedef enum _RF_RADIO_PATH{ ++ RF_PATH_A = 0, //Radio Path A ++ RF_PATH_B = 1, //Radio Path B ++ RF_PATH_C = 2, //Radio Path C ++ RF_PATH_D = 3, //Radio Path D ++ //RF_PATH_MAX //Max RF number 90 support ++}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; ++ ++#define RF_PATH_MAX 2 ++ ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = 0x01, ++ WIRELESS_MODE_B = 0x02, ++ WIRELESS_MODE_G = 0x04, ++ WIRELESS_MODE_AUTO = 0x08, ++ WIRELESS_MODE_N_24G = 0x10, ++ WIRELESS_MODE_N_5G = 0x20 ++} WIRELESS_MODE; ++ ++ ++#if(TX_POWER_FOR_5G_BAND == 1) ++#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number ++#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups ++#define MAX_PG_GROUP 13 ++#else ++#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number ++#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups ++#define MAX_PG_GROUP 7 ++#endif ++#define CHANNEL_GROUP_MAX_2G 3 ++#define CHANNEL_GROUP_IDX_5GL 3 ++#define CHANNEL_GROUP_IDX_5GM 6 ++#define CHANNEL_GROUP_IDX_5GH 9 ++#define CHANNEL_GROUP_MAX_5G 9 ++#define CHANNEL_MAX_NUMBER_2G 14 ++ ++#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1) ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, ++ BaseBand_Config_AGC_TAB = 1, ++ BaseBand_Config_AGC_TAB_2G = 2, ++ BaseBand_Config_AGC_TAB_5G = 3, ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++#else ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, //Radio Path A ++ BaseBand_Config_AGC_TAB = 1, //Radio Path B ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++#endif ++ ++ ++typedef enum _MACPHY_MODE_8192D{ ++ SINGLEMAC_SINGLEPHY, //SMSP ++ DUALMAC_DUALPHY, //DMDP ++ DUALMAC_SINGLEPHY, //DMSP ++}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; ++ ++typedef enum _MACPHY_MODE_CHANGE_ACTION{ ++ DMDP2DMSP = 0, ++ DMSP2DMDP = 1, ++ DMDP2SMSP = 2, ++ SMSP2DMDP = 3, ++ DMSP2SMSP = 4, ++ SMSP2DMSP = 5, ++ MAXACTION ++}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION; ++ ++typedef enum _BAND_TYPE{ ++ BAND_ON_2_4G = 1, ++ BAND_ON_5G = 2, ++ BAND_ON_BOTH, ++ BANDMAX ++}BAND_TYPE,*PBAND_TYPE; ++ ++typedef enum _PHY_Rate_Tx_Power_Offset_Area{ ++ RA_OFFSET_LEGACY_OFDM1, ++ RA_OFFSET_LEGACY_OFDM2, ++ RA_OFFSET_HT_OFDM1, ++ RA_OFFSET_HT_OFDM2, ++ RA_OFFSET_HT_OFDM3, ++ RA_OFFSET_HT_OFDM4, ++ RA_OFFSET_HT_CCK, ++}RA_OFFSET_AREA,*PRA_OFFSET_AREA; ++ ++ ++/* BB/RF related */ ++typedef enum _RF_TYPE_8190P{ ++ RF_TYPE_MIN, // 0 ++ RF_8225=1, // 1 11b/g RF for verification only ++ RF_8256=2, // 2 11b/g/n ++ RF_8258=3, // 3 11a/b/g/n RF ++ RF_6052=4, // 4 11b/g/n RF ++ //RF_6052=5, // 4 11b/g/n RF ++ // TODO: We sholud remove this psudo PHY RF after we get new RF. ++ RF_PSEUDO_11N=5, // 5, It is a temporality RF. ++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; ++ ++ ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: ++ // 0x870~0x877[8 bytes] ++ ++ u32 rfintfi; // readback data: ++ // 0x8e0~0x8e7[8 bytes] ++ ++ u32 rfintfo; // output data: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rfintfe; // output enable: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rf3wireOffset; // LSSI data: ++ // 0x840~0x84f [16 bytes] ++ ++ u32 rfLSSI_Select; // BB Band Select: ++ // 0x878~0x87f [8 bytes] ++ ++ u32 rfTxGainStage; // Tx gain stage: ++ // 0x80c~0x80f [4 bytes] ++ ++ u32 rfHSSIPara1; // wire parameter control1 : ++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ ++ u32 rfHSSIPara2; // wire parameter control2 : ++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ ++ u32 rfSwitchControl; //Tx Rx antenna control : ++ // 0x858~0x85f [16 bytes] ++ ++ u32 rfAGCControl1; //AGC parameter control1 : ++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ ++ u32 rfAGCControl2; //AGC parameter control2 : ++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : ++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : ++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix ++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type ++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ ++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode ++ // 0x8a0~0x8af [16 bytes] ++ ++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B ++ ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++ ++typedef struct _R_ANTENNA_SELECT_OFDM{ ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK{ ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++// ++// BB and RF register read/write ++// ++void rtl8192d_PHY_SetBBReg1Byte( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192d_PHY_QueryBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192d_PHY_SetBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192d_PHY_QueryRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192d_PHY_SetRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++extern int PHY_MACConfig8192D( IN PADAPTER Adapter ); ++extern int PHY_BBConfig8192D( IN PADAPTER Adapter ); ++extern int PHY_RFConfig8192D( IN PADAPTER Adapter ); ++/* RF config */ ++int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, ++ IN u8* pFileName, ++ IN RF_RADIO_PATH_E eRFPath); ++int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter, ++ IN RF_CONTENT Content, ++ IN RF_RADIO_PATH_E eRFPath); ++/* BB/RF readback check for making sure init OK */ ++int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter, ++ IN HW90_BLOCK_E CheckBlock, ++ IN RF_RADIO_PATH_E eRFPath ); ++/* Read initi reg value for tx power setting. */ ++void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter ); ++ ++// ++// RF Power setting ++// ++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, ++// IN RT_RF_POWER_STATE eRFPowerState); ++ ++// ++// BB TX Power R/W ++// ++void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter, ++ OUT u32* powerlevel ); ++void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter, ++ IN u8 channel ); ++BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter, ++ IN int powerInDbm ); ++ ++// ++VOID ++PHY_ScanOperationBackup8192D(IN PADAPTER Adapter, ++ IN u8 Operation ); ++ ++// ++// Switch bandwidth for 8192S ++// ++//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SetBWMode8192D( IN PADAPTER pAdapter, ++ IN HT_CHANNEL_WIDTH ChnlWidth, ++ IN unsigned char Offset ); ++ ++// ++// Set FW CMD IO for 8192S. ++// ++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, ++// IN IO_TYPE IOType); ++ ++// ++// Set A2 entry to fw for 8192S ++// ++extern void FillA2Entry8192C( IN PADAPTER Adapter, ++ IN u8 index, ++ IN u8* val); ++ ++ ++// ++// channel switch related funciton ++// ++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SwChnl8192D( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ // Call after initialization ++void PHY_SwChnlPhy8192D( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ ++extern void ChkFwCmdIoDone( IN PADAPTER Adapter); ++ ++ ++// ++// BB/MAC/RF other monitor API ++// ++void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ); ++ ++BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter, ++ IN u32 eRFPath ); ++ ++ ++// ++// Modify the value of the hw register when beacon interval be changed. ++// ++void ++rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter, ++ IN u16 BeaconInterval ); ++ ++ ++extern VOID ++PHY_SwitchEphyParameter( ++ IN PADAPTER Adapter ++ ); ++ ++extern VOID ++PHY_EnableHostClkReq( ++ IN PADAPTER Adapter ++ ); ++ ++BOOLEAN ++SetAntennaConfig92C( ++ IN PADAPTER Adapter, ++ IN u8 DefaultAnt ++ ); ++ ++VOID ++PHY_UpdateBBRFConfiguration8192D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bisBandSwitch ++); ++ ++VOID PHY_ReadMacPhyMode92D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN AutoloadFail ++); ++ ++VOID PHY_ConfigMacPhyMode92D( ++ IN PADAPTER Adapter ++); ++ ++VOID PHY_ConfigMacPhyModeInfo92D( ++ IN PADAPTER Adapter ++); ++ ++VOID PHY_ConfigMacCoexist_RFPage92D( ++ IN PADAPTER Adapter ++); ++ ++VOID ++rtl8192d_PHY_InitRxSetting( ++ IN PADAPTER Adapter ++); ++ ++ ++VOID ++rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain); ++ ++VOID ++HalChangeCCKStatus8192D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bCCKDisable ++); ++ ++VOID ++PHY_InitPABias92D(IN PADAPTER Adapter); ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask)) ++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask)) ++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) ++ ++#define PHY_SetMacReg PHY_SetBBReg ++#define PHY_QueryMacReg PHY_QueryBBReg ++ ++#endif // __INC_HAL8192SPHYCFG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyReg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyReg.h +new file mode 100644 +index 00000000..de23a415 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8192DPhyReg.h +@@ -0,0 +1,1172 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192DPHYREG_H ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __INC_HAL8192DPHYREG_H ++#define __INC_HAL8192DPHYREG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++ ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 ++#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback ++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// PageB(0xB00) ++// ++#define rPdp_AntA 0xb00 ++#define rPdp_AntA_4 0xb04 ++#define rPdp_AntA_8 0xb08 ++#define rPdp_AntA_C 0xb0c ++#define rPdp_AntA_10 0xb10 ++#define rPdp_AntA_14 0xb14 ++#define rPdp_AntA_18 0xb18 ++#define rPdp_AntA_1C 0xb1c ++#define rPdp_AntA_20 0xb20 ++#define rPdp_AntA_24 0xb24 ++ ++#define rConfig_Pmpd_AntA 0xb28 ++#define rConfig_ram64x16 0xb2c ++ ++#define rBndA 0xb30 ++#define rHssiPar 0xb34 ++ ++#define rConfig_AntA 0xb68 ++#define rConfig_AntB 0xb6c ++ ++#define rPdp_AntB 0xb70 ++#define rPdp_AntB_4 0xb74 ++#define rPdp_AntB_8 0xb78 ++#define rPdp_AntB_C 0xb7c ++#define rPdp_AntB_10 0xb80 ++#define rPdp_AntB_14 0xb84 ++#define rPdp_AntB_18 0xb88 ++#define rPdp_AntB_1C 0xb8c ++#define rPdp_AntB_20 0xb90 ++#define rPdp_AntB_24 0xb94 ++ ++#define rConfig_Pmpd_AntB 0xb98 ++ ++#define rBndB 0xba0 ++ ++#define rAPK 0xbd8 ++#define rPm_Rx0_AntA 0xbdc ++#define rPm_Rx1_AntA 0xbe0 ++#define rPm_Rx2_AntA 0xbe4 ++#define rPm_Rx3_AntA 0xbe8 ++#define rPm_Rx0_AntB 0xbec ++#define rPm_Rx1_AntB 0xbf0 ++#define rPm_Rx2_AntB 0xbf4 ++#define rPm_Rx3_AntB 0xbf8 ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++ ++#define rOFDM0_RxIQExtAnta 0xca0 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_A_Rate18_06 0xe00 ++#define rTxAGC_A_Rate54_24 0xe04 ++#define rTxAGC_A_CCK1_Mcs32 0xe08 ++#define rTxAGC_A_Mcs03_Mcs00 0xe10 ++#define rTxAGC_A_Mcs07_Mcs04 0xe14 ++#define rTxAGC_A_Mcs11_Mcs08 0xe18 ++#define rTxAGC_A_Mcs15_Mcs12 0xe1c ++ ++#define rTxAGC_B_Rate18_06 0x830 ++#define rTxAGC_B_Rate54_24 0x834 ++#define rTxAGC_B_CCK1_55_Mcs32 0x838 ++#define rTxAGC_B_Mcs03_Mcs00 0x83c ++#define rTxAGC_B_Mcs07_Mcs04 0x848 ++#define rTxAGC_B_Mcs11_Mcs08 0x84c ++#define rTxAGC_B_Mcs15_Mcs12 0x868 ++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c ++ ++#define rFPGA0_IQK 0xe28 ++#define rTx_IQK_Tone_A 0xe30 ++#define rRx_IQK_Tone_A 0xe34 ++#define rTx_IQK_PI_A 0xe38 ++#define rRx_IQK_PI_A 0xe3c ++ ++#define rTx_IQK 0xe40 ++#define rRx_IQK 0xe44 ++#define rIQK_AGC_Pts 0xe48 ++#define rIQK_AGC_Rsp 0xe4c ++#define rTx_IQK_Tone_B 0xe50 ++#define rRx_IQK_Tone_B 0xe54 ++#define rTx_IQK_PI_B 0xe58 ++#define rRx_IQK_PI_B 0xe5c ++#define rIQK_AGC_Cont 0xe60 ++ ++#define rBlue_Tooth 0xe6c ++#define rRx_Wait_CCA 0xe70 ++#define rTx_CCK_RFON 0xe74 ++#define rTx_CCK_BBON 0xe78 ++#define rTx_OFDM_RFON 0xe7c ++#define rTx_OFDM_BBON 0xe80 ++#define rTx_To_Rx 0xe84 ++#define rTx_To_Tx 0xe88 ++#define rRx_CCK 0xe8c ++ ++#define rTx_Power_Before_IQK_A 0xe94 ++#define rTx_Power_After_IQK_A 0xe9c ++ ++#define rRx_Power_Before_IQK_A 0xea0 ++#define rRx_Power_Before_IQK_A_2 0xea4 ++#define rRx_Power_After_IQK_A 0xea8 ++#define rRx_Power_After_IQK_A_2 0xeac ++ ++#define rTx_Power_Before_IQK_B 0xeb4 ++#define rTx_Power_After_IQK_B 0xebc ++ ++#define rRx_Power_Before_IQK_B 0xec0 ++#define rRx_Power_Before_IQK_B_2 0xec4 ++#define rRx_Power_After_IQK_B 0xec8 ++#define rRx_Power_After_IQK_B_2 0xecc ++ ++#define rRx_OFDM 0xed0 ++#define rRx_Wait_RIFS 0xed4 ++#define rRx_TO_Rx 0xed8 ++#define rStandby 0xedc ++#define rSleep 0xee0 ++#define rPMPD_ANAEN 0xeec ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 // RF channel switch ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_BS_PA_APSET_G1_G4 0x03 ++#define RF_BS_PA_APSET_G5_G8 0x04 ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_IPA_G 0x09 // ++#define RF_TXBIAS_G 0x0A ++#define RF_TXPA_AG 0x0B ++#define RF_IPA_A 0x0C // ++#define RF_TXBIAS_A 0x0D ++#define RF_BS_PA_APSET_G9_G11 0x0E ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_TXBIAS 0x16 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x42 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++#define RF_LOBF_9 0x38 ++#define RF_RXRF_A3 0x3C // ++#define RF_TRSW 0x3F ++ ++#define RF_TXRF_A2 0x41 ++#define RF_TXPA_G4 0x46 ++#define RF_TXPA_A4 0x4B ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bAntennaSelect 0x0300 ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++ ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++ ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++ ++#define bLSSIReadBackData 0xfffff // T65 RF ++ ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMask12Bits 0xfff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++//#define bRFRegOffsetMask 0xfff ++ ++//MAC0 will wirte PHY1 ++#define MAC0_ACCESS_PHY1 0x4000 ++//MAC1 will wirte PHY0 ++#define MAC1_ACCESS_PHY0 0x2000 ++ ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 // Useless ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyCfg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyCfg.h +new file mode 100644 +index 00000000..3ec89725 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyCfg.h +@@ -0,0 +1,30 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8723PHYCFG_H__ ++#define __INC_HAL8723PHYCFG_H__ ++ ++#include ++/* MAC/BB/RF HAL config */ ++int PHY_BBConfig8723A( IN PADAPTER Adapter ); ++int PHY_RFConfig8723A( IN PADAPTER Adapter ); ++s32 PHY_MACConfig8723A(PADAPTER padapter); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyReg.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyReg.h +new file mode 100644 +index 00000000..7b244b4d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723APhyReg.h +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8723APHYREG_H__ ++#define __INC_HAL8723APHYREG_H__ ++ ++#include ++ ++// ++// PageB(0xB00) ++// ++#define rPdp_AntA 0xb00 ++#define rPdp_AntA_4 0xb04 ++#define rPdp_AntA_8 0xb08 ++#define rPdp_AntA_C 0xb0c ++#define rPdp_AntA_10 0xb10 ++#define rPdp_AntA_14 0xb14 ++#define rPdp_AntA_18 0xb18 ++#define rPdp_AntA_1C 0xb1c ++#define rPdp_AntA_20 0xb20 ++#define rPdp_AntA_24 0xb24 ++ ++#define rConfig_Pmpd_AntA 0xb28 ++#define rConfig_ram64x16 0xb2c ++ ++#define rBndA 0xb30 ++#define rHssiPar 0xb34 ++ ++#define rConfig_AntA 0xb68 ++#define rConfig_AntB 0xb6c ++ ++#define rPdp_AntB 0xb70 ++#define rPdp_AntB_4 0xb74 ++#define rPdp_AntB_8 0xb78 ++#define rPdp_AntB_C 0xb7c ++#define rPdp_AntB_10 0xb80 ++#define rPdp_AntB_14 0xb84 ++#define rPdp_AntB_18 0xb88 ++#define rPdp_AntB_1C 0xb8c ++#define rPdp_AntB_20 0xb90 ++#define rPdp_AntB_24 0xb94 ++ ++#define rConfig_Pmpd_AntB 0xb98 ++ ++#define rBndB 0xba0 ++ ++#define rAPK 0xbd8 ++#define rPm_Rx0_AntA 0xbdc ++#define rPm_Rx1_AntA 0xbe0 ++#define rPm_Rx2_AntA 0xbe4 ++#define rPm_Rx3_AntA 0xbe8 ++#define rPm_Rx0_AntB 0xbec ++#define rPm_Rx1_AntB 0xbf0 ++#define rPm_Rx2_AntB 0xbf4 ++#define rPm_Rx3_AntB 0xbf8 ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723PwrSeq.h b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723PwrSeq.h +new file mode 100644 +index 00000000..ab1c32a0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/Hal8723PwrSeq.h +@@ -0,0 +1,171 @@ ++#ifndef __HAL8723PWRSEQ_H__ ++#define __HAL8723PWRSEQ_H__ ++/* ++ Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd ++ There are 6 HW Power States: ++ 0: POFF--Power Off ++ 1: PDN--Power Down ++ 2: CARDEMU--Card Emulation ++ 3: ACT--Active Mode ++ 4: LPS--Low Power State ++ 5: SUS--Suspend ++ ++ The transision from different states are defined below ++ TRANS_CARDEMU_TO_ACT ++ TRANS_ACT_TO_CARDEMU ++ TRANS_CARDEMU_TO_SUS ++ TRANS_SUS_TO_CARDEMU ++ TRANS_CARDEMU_TO_PDN ++ TRANS_ACT_TO_LPS ++ TRANS_LPS_TO_ACT ++ ++ TRANS_END ++*/ ++#include "HalPwrSeqCmd.h" ++#include "rtl8723a_spec.h" ++ ++#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15 ++#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15 ++#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15 ++#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15 ++#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15 ++#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15 ++#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15 ++#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15 ++#define RTL8723A_TRANS_END_STEPS 1 ++ ++ ++#define RTL8723A_TRANS_CARDEMU_TO_ACT \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ ++ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ ++ {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ ++ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ ++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ ++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ ++ {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\ ++ ++#define RTL8723A_TRANS_ACT_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ ++ {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ ++ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ ++ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ ++ ++ ++#define RTL8723A_TRANS_CARDEMU_TO_SUS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ ++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ ++ ++#define RTL8723A_TRANS_SUS_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ ++ ++#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ ++ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ ++ ++#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ ++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ ++ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ ++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ ++ ++ ++#define RTL8723A_TRANS_CARDEMU_TO_PDN \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ ++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ ++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ ++ ++#define RTL8723A_TRANS_PDN_TO_CARDEMU \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ ++ ++#define RTL8723A_TRANS_ACT_TO_LPS \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ ++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ ++ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ ++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ ++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ ++ {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ ++ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ ++ ++ ++#define RTL8723A_TRANS_LPS_TO_ACT \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ ++ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ ++ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ ++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ ++ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ ++ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ ++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ ++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ ++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ ++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ ++ ++#define RTL8723A_TRANS_END \ ++ /* format */ \ ++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ ++ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // ++ ++ ++extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS]; ++extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]; ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/HalPwrSeqCmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/HalPwrSeqCmd.h +new file mode 100644 +index 00000000..5cf122fb +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/HalPwrSeqCmd.h +@@ -0,0 +1,138 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __HALPWRSEQCMD_H__ ++#define __HALPWRSEQCMD_H__ ++ ++#include ++ ++/*---------------------------------------------*/ ++//3 The value of cmd: 4 bits ++/*---------------------------------------------*/ ++#define PWR_CMD_READ 0x00 ++ // offset: the read register offset ++ // msk: the mask of the read value ++ // value: N/A, left by 0 ++ // note: dirver shall implement this function by read & msk ++ ++#define PWR_CMD_WRITE 0x01 ++ // offset: the read register offset ++ // msk: the mask of the write bits ++ // value: write value ++ // note: driver shall implement this cmd by read & msk after write ++ ++#define PWR_CMD_POLLING 0x02 ++ // offset: the read register offset ++ // msk: the mask of the polled value ++ // value: the value to be polled, masked by the msd field. ++ // note: driver shall implement this cmd by ++ // do{ ++ // if( (Read(offset) & msk) == (value & msk) ) ++ // break; ++ // } while(not timeout); ++ ++#define PWR_CMD_DELAY 0x03 ++ // offset: the value to delay ++ // msk: N/A ++ // value: the unit of delay, 0: us, 1: ms ++ ++#define PWR_CMD_END 0x04 ++ // offset: N/A ++ // msk: N/A ++ // value: N/A ++ ++/*---------------------------------------------*/ ++//3 The value of base: 4 bits ++/*---------------------------------------------*/ ++ // define the base address of each block ++#define PWR_BASEADDR_MAC 0x00 ++#define PWR_BASEADDR_USB 0x01 ++#define PWR_BASEADDR_PCIE 0x02 ++#define PWR_BASEADDR_SDIO 0x03 ++ ++/*---------------------------------------------*/ ++//3 The value of interface_msk: 4 bits ++/*---------------------------------------------*/ ++#define PWR_INTF_SDIO_MSK BIT(0) ++#define PWR_INTF_USB_MSK BIT(1) ++#define PWR_INTF_PCI_MSK BIT(2) ++#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ++ ++/*---------------------------------------------*/ ++//3 The value of fab_msk: 4 bits ++/*---------------------------------------------*/ ++#define PWR_FAB_TSMC_MSK BIT(0) ++#define PWR_FAB_UMC_MSK BIT(1) ++#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ++ ++/*---------------------------------------------*/ ++//3 The value of cut_msk: 8 bits ++/*---------------------------------------------*/ ++#define PWR_CUT_TESTCHIP_MSK BIT(0) ++#define PWR_CUT_A_MSK BIT(1) ++#define PWR_CUT_B_MSK BIT(2) ++#define PWR_CUT_C_MSK BIT(3) ++#define PWR_CUT_D_MSK BIT(4) ++#define PWR_CUT_E_MSK BIT(5) ++#define PWR_CUT_F_MSK BIT(6) ++#define PWR_CUT_G_MSK BIT(7) ++#define PWR_CUT_ALL_MSK 0xFF ++ ++ ++typedef enum _PWRSEQ_CMD_DELAY_UNIT_ ++{ ++ PWRSEQ_DELAY_US, ++ PWRSEQ_DELAY_MS, ++} PWRSEQ_DELAY_UNIT; ++ ++typedef struct _WL_PWR_CFG_ ++{ ++ u16 offset; ++ u8 cut_msk; ++ u8 fab_msk:4; ++ u8 interface_msk:4; ++ u8 base:4; ++ u8 cmd:4; ++ u8 msk; ++ u8 value; ++} WLAN_PWR_CFG, *PWLAN_PWR_CFG; ++ ++ ++#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset ++#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk ++#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk ++#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk ++#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base ++#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd ++#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk ++#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value ++ ++ ++//================================================================================ ++// Prototype of protected function. ++//================================================================================ ++u8 HalPwrSeqCmdParsing( ++ PADAPTER padapter, ++ u8 CutVersion, ++ u8 FabVersion, ++ u8 InterfaceType, ++ WLAN_PWR_CFG PwrCfgCmd[]); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/HalVerDef.h b/drivers/net/wireless/rtl818x/rtl8189/include/HalVerDef.h +new file mode 100644 +index 00000000..204c3ac8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/HalVerDef.h +@@ -0,0 +1,164 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __HAL_VERSION_DEF_H__ ++#define __HAL_VERSION_DEF_H__ ++ ++#define TRUE _TRUE ++#define FALSE _FALSE ++ ++// HAL_IC_TYPE_E ++typedef enum tag_HAL_IC_Type_Definition ++{ ++ CHIP_8192S = 0, ++ CHIP_8188C = 1, ++ CHIP_8192C = 2, ++ CHIP_8192D = 3, ++ CHIP_8723A = 4, ++ CHIP_8188E = 5, ++ CHIP_8881A = 6, ++ CHIP_8812A = 7, ++ CHIP_8821A = 8, ++ CHIP_8723B = 9, ++ CHIP_8192E = 10, ++}HAL_IC_TYPE_E; ++ ++//HAL_CHIP_TYPE_E ++typedef enum tag_HAL_CHIP_Type_Definition ++{ ++ TEST_CHIP = 0, ++ NORMAL_CHIP = 1, ++ FPGA = 2, ++}HAL_CHIP_TYPE_E; ++ ++//HAL_CUT_VERSION_E ++typedef enum tag_HAL_Cut_Version_Definition ++{ ++ A_CUT_VERSION = 0, ++ B_CUT_VERSION = 1, ++ C_CUT_VERSION = 2, ++ D_CUT_VERSION = 3, ++ E_CUT_VERSION = 4, ++ F_CUT_VERSION = 5, ++ G_CUT_VERSION = 6, ++ H_CUT_VERSION = 7, ++ I_CUT_VERSION = 8, ++ J_CUT_VERSION = 9, ++ K_CUT_VERSION = 10, ++}HAL_CUT_VERSION_E; ++ ++// HAL_Manufacturer ++typedef enum tag_HAL_Manufacturer_Version_Definition ++{ ++ CHIP_VENDOR_TSMC = 0, ++ CHIP_VENDOR_UMC = 1, ++}HAL_VENDOR_E; ++ ++typedef enum tag_HAL_RF_Type_Definition ++{ ++ RF_TYPE_1T1R = 0, ++ RF_TYPE_1T2R = 1, ++ RF_TYPE_2T2R = 2, ++ RF_TYPE_2T3R = 3, ++ RF_TYPE_2T4R = 4, ++ RF_TYPE_3T3R = 5, ++ RF_TYPE_3T4R = 6, ++ RF_TYPE_4T4R = 7, ++}HAL_RF_TYPE_E; ++ ++typedef struct tag_HAL_VERSION ++{ ++ HAL_IC_TYPE_E ICType; ++ HAL_CHIP_TYPE_E ChipType; ++ HAL_CUT_VERSION_E CUTVersion; ++ HAL_VENDOR_E VendorType; ++ HAL_RF_TYPE_E RFType; ++ u8 ROMVer; ++}HAL_VERSION,*PHAL_VERSION; ++ ++//VERSION_8192C VersionID; ++//HAL_VERSION VersionID; ++ ++// Get element ++#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType) ) ++#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType) ) ++#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType)) ++#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType)) ++#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion)) ++#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK) ++ ++//---------------------------------------------------------------------------- ++//Common Macro. -- ++//---------------------------------------------------------------------------- ++//HAL_VERSION VersionID ++ ++// HAL_IC_TYPE_E ++#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? TRUE : FALSE) ++#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE) ++#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? TRUE : FALSE) ++#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE) ++ ++//HAL_CHIP_TYPE_E ++#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? TRUE: FALSE) ++#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE) ++ ++//HAL_CUT_VERSION_E ++#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE) ++#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE) ++#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE) ++#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE) ++#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) ++#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE) ++#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE) ++#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE) ++ ++#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) ++ ++//HAL_VENDOR_E ++#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? TRUE: FALSE) ++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? TRUE: FALSE) ++ ++//HAL_RF_TYPE_E ++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? TRUE : FALSE ) ++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE) ++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE) ++ ++ ++//---------------------------------------------------------------------------- ++//Chip version Macro. -- ++//---------------------------------------------------------------------------- ++#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE) ++ ++#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE) ++#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) ++#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) ++#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) ++ ++#define IS_NORMAL_CHIP92D(version) (( IS_92D(version))?((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE):FALSE) ++ ++#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE: FALSE) : FALSE) ++#define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) ++#define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE) ++#define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE) ++ ++#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?TRUE : FALSE) : FALSE) ++#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE) ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/autoconf.h b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf.h +new file mode 100644 +index 00000000..620c115c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf.h +@@ -0,0 +1,26 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifdef CONFIG_RTL8189ES ++#include "autoconf_rtl8189e_sdio_linux.h" ++#else ++#include "autoconf_rtl8189e_usb_linux.h" ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_sdio_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_sdio_linux.h +new file mode 100644 +index 00000000..6d605fe9 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_sdio_linux.h +@@ -0,0 +1,311 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2010 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/* ++ * Automatically generated C config: don't edit ++ */ ++ ++//***** temporarily flag ******* ++#define CONFIG_ODM_REFRESH_RAMASK ++#define CONFIG_PHY_SETTING_WITH_ODM ++//***** temporarily flag ******* ++ ++ ++#define AUTOCONF_INCLUDED ++#define RTL871X_MODULE_NAME "8189ES" ++#define DRV_NAME "rtl8189es" ++ ++#define CONFIG_RTL8188E ++#define CONFIG_SDIO_HCI ++#define PLATFORM_LINUX ++ ++//#define CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ //#define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */ ++ #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER ++ //#define CONFIG_DEBUG_CFG80211 ++ #define CONFIG_SET_SCAN_DENY_TIMER ++#endif ++ ++#define CONFIG_EMBEDDED_FWIMG ++ ++#define CONFIG_XMIT_ACK ++#ifdef CONFIG_XMIT_ACK ++ #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++#endif ++#define CONFIG_80211N_HT ++#define CONFIG_RECV_REORDERING_CTRL ++ ++#define CONFIG_CONCURRENT_MODE ++#ifdef CONFIG_CONCURRENT_MODE ++ #define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC. ++ //#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri ++ //#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++#endif ++ ++#define CONFIG_AP_MODE ++#ifdef CONFIG_AP_MODE ++ ++ #define CONFIG_INTERRUPT_BASED_TXBCN // Tx Beacon when driver early interrupt occurs ++ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) ++ #undef CONFIG_INTERRUPT_BASED_TXBCN ++ #endif ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ //#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ #define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ #endif ++ ++ #define CONFIG_NATIVEAP_MLME ++ #ifndef CONFIG_NATIVEAP_MLME ++ #define CONFIG_HOSTAPD_MLME ++ #endif ++ //#define CONFIG_FIND_BEST_CHANNEL ++ //#define CONFIG_NO_WIRELESS_HANDLERS ++#endif ++ ++#define CONFIG_TX_MCAST2UNI // Support IP multicast->unicast ++//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs. ++ ++#define CONFIG_P2P ++#ifdef CONFIG_P2P ++ //The CONFIG_WFD is for supporting the Wi-Fi display ++ #define CONFIG_WFD ++ ++ #ifndef CONFIG_WIFI_TEST ++ #define CONFIG_P2P_REMOVE_GROUP_INFO ++ #endif ++ //#define CONFIG_DBG_P2P ++ ++ #define CONFIG_P2P_PS ++ //#define CONFIG_P2P_IPS ++ #define P2P_OP_CHECK_SOCIAL_CH ++#endif ++ ++// Added by Kurt 20110511 ++//#define CONFIG_TDLS ++#ifdef CONFIG_TDLS ++// #ifndef CONFIG_WFD ++// #define CONFIG_WFD ++// #endif ++// #define CONFIG_TDLS_AUTOSETUP ++// #define CONFIG_TDLS_AUTOCHECKALIVE ++#endif ++ ++#define CONFIG_SKB_COPY //for amsdu ++ ++#define CONFIG_LAYER2_ROAMING ++#define CONFIG_LAYER2_ROAMING_RESUME ++ ++#define CONFIG_LONG_DELAY_ISSUE ++#define CONFIG_NEW_SIGNAL_STAT_PROCESS ++#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */ ++#define CONFIG_DEAUTH_BEFORE_CONNECT ++ ++//#define CONFIG_ARP_KEEP_ALIVE ++ ++/* ++ * Hardware Related Config ++ */ ++ ++//#define SUPPORT_HW_RFOFF_DETECTED ++ ++//#define CONFIG_SW_LED ++#define CONFIG_REGULATORY_CTRL ++ ++/* ++ * Interface Related Config ++ */ ++//#define CONFIG_SDIO_TX_TASKLET ++#define CONFIG_SDIO_RX_COPY ++//#define CONFIG_SDIO_REDUCE_TX_POLLING ++ ++ ++/* ++ * Others ++ */ ++//#define CONFIG_MAC_LOOPBACK_DRIVER ++ ++ ++/* ++ * Auto Config Section ++ */ ++#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI) ++#define CONFIG_RTL8188E_SDIO ++#define CONFIG_XMIT_THREAD_MODE ++#endif ++ ++#define CONFIG_IPS ++ ++#define CONFIG_LPS ++#if defined(CONFIG_LPS) && defined(CONFIG_SDIO_HCI) ++#define CONFIG_LPS_LCLK ++ ++ #define CONFIG_LPS_RPWM_TIMER ++ #ifdef CONFIG_LPS_RPWM_TIMER ++ #define LPS_RPWM_WAIT_MS 300 ++ #endif ++#endif ++ ++#ifdef CONFIG_LPS_LCLK ++//#define CONFIG_DETECT_CPWM_BY_POLLING ++#endif ++ ++#ifdef CONFIG_DETECT_CPWM_BY_POLLING ++#define CONFIG_USING_CMD52_READ_INT /*for cmd53 I/O fail issue,read 0x18 only*/ ++#endif ++ ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++#undef CONFIG_AP_MODE ++#undef CONFIG_NATIVEAP_MLME ++#undef CONFIG_POWER_SAVING ++#undef SUPPORT_HW_RFOFF_DETECTED ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++ ++ #define MP_DRIVER 1 ++ #define CONFIG_MP_IWPRIV_SUPPORT ++ ++ // disable unnecessary functions for MP ++ //#undef CONFIG_IPS ++ //#undef CONFIG_LPS ++ //#undef CONFIG_LPS_LCLK ++ //#undef SUPPORT_HW_RFOFF_DETECTED ++ ++#else// #ifdef CONFIG_MP_INCLUDED ++ ++ #define MP_DRIVER 0 ++ ++#endif // #ifdef CONFIG_MP_INCLUDED ++ ++#define CONFIG_IOL ++#ifdef CONFIG_IOL ++ #define CONFIG_IOL_NEW_GENERATION ++ #define CONFIG_IOL_READ_EFUSE_MAP ++ //#define DBG_IOL_READ_EFUSE_MAP ++ //#define CONFIG_IOL_LLT ++ #define CONFIG_IOL_EFUSE_PATCH ++ //#define CONFIG_IOL_IOREG_CFG ++ //#define CONFIG_IOL_IOREG_CFG_DBG ++#endif ++ ++ ++#define CONFIG_TX_AGGREGATION ++ ++#ifdef CONFIG_PLATFORM_ACTIONS_ATV5201 ++#define CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP ++#endif ++ ++/* ++ * Outsource Related Config ++ */ ++ ++#define RTL8192CE_SUPPORT 0 ++#define RTL8192CU_SUPPORT 0 ++#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT) ++ ++#define RTL8192DE_SUPPORT 0 ++#define RTL8192DU_SUPPORT 0 ++#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT) ++ ++#define RTL8723_FPGA_VERIFICATION 0 ++#define RTL8723AU_SUPPORT 0 ++#define RTL8723AS_SUPPORT 0 ++#define RTL8723AE_SUPPORT 0 ++#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT) ++ ++#define RTL8188EE_SUPPORT 0 ++#define RTL8188EU_SUPPORT 0 ++#define RTL8188ES_SUPPORT 1 ++#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT) ++#define RTL8188E_FOR_TEST_CHIP 0 ++//#if (RTL8188E_SUPPORT==1) ++#define RATE_ADAPTIVE_SUPPORT 1 ++#define POWER_TRAINING_ACTIVE 1 ++//#define CONFIG_TX_EARLY_MODE ++ ++#ifdef CONFIG_TX_EARLY_MODE ++#define RTL8188E_EARLY_MODE_PKT_NUM_10 0 ++#endif ++//#endif ++ ++#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR ++ ++/* ++ * HAL Related Config ++ */ ++ ++//for FPGA VERIFICATION config ++#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0 ++ ++#define DISABLE_BB_RF 0 ++ ++#if DISABLE_BB_RF ++ #define HAL_MAC_ENABLE 1 ++ #define HAL_BB_ENABLE 0 ++ #define HAL_RF_ENABLE 0 ++#else ++ #define HAL_MAC_ENABLE 1 ++ #define HAL_BB_ENABLE 1 ++ #define HAL_RF_ENABLE 1 ++#endif ++ ++#define CONFIG_80211D ++ ++ ++ ++/* ++ * Debug Related Config ++ */ ++#define DBG 0 ++ ++//#define CONFIG_DEBUG /* DBG_871X, etc... */ ++//#define CONFIG_DEBUG_RTL871X /* RT_TRACE, RT_PRINT_DATA, _func_enter_, _func_exit_ */ ++ ++//#define CONFIG_PROC_DEBUG ++ ++//#define DBG_CONFIG_ERROR_DETECT ++//#define DBG_CONFIG_ERROR_RESET ++ ++//#define DBG_IO ++//#define DBG_DELAY_OS ++//#define DBG_MEM_ALLOC ++//#define DBG_IOCTL ++ ++//#define DBG_TX ++//#define DBG_XMIT_BUF ++//#define DBG_XMIT_BUF_EXT ++//#define DBG_TX_DROP_FRAME ++ ++//#define DBG_RX_DROP_FRAME ++//#define DBG_RX_SEQ ++//#define DBG_RX_SIGNAL_DISPLAY_PROCESSING ++//#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap" ++ ++ ++//#define HAL_8195A_USB 0 ++ ++//#define RTL8188E_FOR_MP_TEST 1 ++ ++//#define DOWNLOAD_FW_TO_TXPKT_BUF 0 ++ ++//#define DBG_HAL_INIT_PROFILING ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_usb_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_usb_linux.h +new file mode 100644 +index 00000000..f87ab3a8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/autoconf_rtl8189e_usb_linux.h +@@ -0,0 +1,406 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++//***** temporarily flag ******* ++ ++//#define CONFIG_DISABLE_ODM ++//#define CONFIG_ATMEL_RC_PATCH ++ ++#define CONFIG_ODM_REFRESH_RAMASK ++#define CONFIG_PHY_SETTING_WITH_ODM ++//for FPGA VERIFICATION config ++#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0 ++ ++//***** temporarily flag ******* ++/* ++ * Public General Config ++ */ ++#define AUTOCONF_INCLUDED ++#define RTL871X_MODULE_NAME "88EU" ++#define DRV_NAME "rtl8188eu" ++ ++#define CONFIG_USB_HCI ++ ++#define CONFIG_RTL8188E ++ ++#define PLATFORM_LINUX ++ ++//#define CONFIG_IOCTL_CFG80211 ++//#define CONFIG_IEEE80211W ++ ++#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X) ++ #ifndef CONFIG_IOCTL_CFG80211 ++ #define CONFIG_IOCTL_CFG80211 ++ #endif ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ //#define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */ ++ #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER ++ //#define CONFIG_DEBUG_CFG80211 ++ //#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2 ++ #define CONFIG_SET_SCAN_DENY_TIMER ++ ++#endif ++ ++/* ++ * Internal General Config ++ */ ++ ++//#define CONFIG_H2CLBK ++ ++#define CONFIG_EMBEDDED_FWIMG ++//#define CONFIG_FILE_FWIMG ++ ++#define CONFIG_XMIT_ACK ++#ifdef CONFIG_XMIT_ACK ++ #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK ++#endif ++#define CONFIG_80211N_HT ++ ++#define CONFIG_RECV_REORDERING_CTRL ++ ++//#define CONFIG_TCP_CSUM_OFFLOAD_RX ++ ++//#define CONFIG_DRVEXT_MODULE ++ ++ #define CONFIG_SUPPORT_USB_INT ++ #ifdef CONFIG_SUPPORT_USB_INT ++//#define CONFIG_USB_INTERRUPT_IN_PIPE ++#endif ++ ++//#ifndef CONFIG_MP_INCLUDED ++ #define CONFIG_IPS ++ #ifdef CONFIG_IPS ++ //#define CONFIG_IPS_LEVEL_2 //enable this to set default IPS mode to IPS_LEVEL_2 ++ #endif ++ #define SUPPORT_HW_RFOFF_DETECTED ++ ++ #define CONFIG_LPS ++ #if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT) ++ ++ ++ //#define CONFIG_LPS_LCLK ++ #endif ++ ++ #ifdef CONFIG_LPS_LCLK ++ #define CONFIG_XMIT_THREAD_MODE ++ #endif ++ ++ //befor link ++ #define CONFIG_ANTENNA_DIVERSITY ++ ++ //after link ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ #define CONFIG_HW_ANTENNA_DIVERSITY ++ #endif ++ ++ ++ #define CONFIG_CONCURRENT_MODE ++ #ifdef CONFIG_CONCURRENT_MODE ++ //#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri ++ //#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE ++ #define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC. ++ #endif ++ ++ #define CONFIG_IOL ++//#else //#ifndef CONFIG_MP_INCLUDED ++ ++//#endif //#ifndef CONFIG_MP_INCLUDED ++ ++#define CONFIG_AP_MODE ++#ifdef CONFIG_AP_MODE ++ //#define CONFIG_INTERRUPT_BASED_TXBCN // Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs ++ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) ++ #undef CONFIG_INTERRUPT_BASED_TXBCN ++ #endif ++ #ifdef CONFIG_INTERRUPT_BASED_TXBCN ++ //#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT ++ #define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR ++ #endif ++ ++ #define CONFIG_NATIVEAP_MLME ++ #ifndef CONFIG_NATIVEAP_MLME ++ #define CONFIG_HOSTAPD_MLME ++ #endif ++ #define CONFIG_FIND_BEST_CHANNEL ++ //#define CONFIG_NO_WIRELESS_HANDLERS ++#endif ++ ++#define CONFIG_P2P ++#ifdef CONFIG_P2P ++ //The CONFIG_WFD is for supporting the Wi-Fi display ++ #define CONFIG_WFD ++ ++ #ifndef CONFIG_WIFI_TEST ++ #define CONFIG_P2P_REMOVE_GROUP_INFO ++ #endif ++ //#define CONFIG_DBG_P2P ++ ++ #define CONFIG_P2P_PS ++ //#define CONFIG_P2P_IPS ++ #define P2P_OP_CHECK_SOCIAL_CH ++#endif ++ ++// Added by Kurt 20110511 ++//#define CONFIG_TDLS ++#ifdef CONFIG_TDLS ++// #ifndef CONFIG_WFD ++// #define CONFIG_WFD ++// #endif ++// #define CONFIG_TDLS_AUTOSETUP ++// #define CONFIG_TDLS_AUTOCHECKALIVE ++#endif ++ ++ ++#define CONFIG_SKB_COPY //for amsdu ++ ++//#define CONFIG_LED ++#ifdef CONFIG_LED ++ #define CONFIG_SW_LED ++ #ifdef CONFIG_SW_LED ++ //#define CONFIG_LED_HANDLED_BY_CMD_THREAD ++ #endif ++#endif // CONFIG_LED ++ ++#ifdef CONFIG_IOL ++ #define CONFIG_IOL_NEW_GENERATION ++ #define CONFIG_IOL_READ_EFUSE_MAP ++ //#define DBG_IOL_READ_EFUSE_MAP ++ //#define CONFIG_IOL_LLT ++ #define CONFIG_IOL_EFUSE_PATCH ++ //#define CONFIG_IOL_IOREG_CFG ++ //#define CONFIG_IOL_IOREG_CFG_DBG ++#endif ++ ++ ++#define USB_INTERFERENCE_ISSUE // this should be checked in all usb interface ++#define CONFIG_GLOBAL_UI_PID ++ ++#define CONFIG_LAYER2_ROAMING ++#define CONFIG_LAYER2_ROAMING_RESUME ++//#define CONFIG_ADAPTOR_INFO_CACHING_FILE // now just applied on 8192cu only, should make it general... ++//#define CONFIG_RESUME_IN_WORKQUEUE ++//#define CONFIG_SET_SCAN_DENY_TIMER ++#define CONFIG_LONG_DELAY_ISSUE ++#define CONFIG_NEW_SIGNAL_STAT_PROCESS ++//#define CONFIG_SIGNAL_DISPLAY_DBM //display RX signal with dbm ++#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */ ++#define CONFIG_DEAUTH_BEFORE_CONNECT ++ ++#define CONFIG_BR_EXT // Enable NAT2.5 support for STA mode interface with a L2 Bridge ++#ifdef CONFIG_BR_EXT ++#define CONFIG_BR_EXT_BRNAME "br0" ++#endif // CONFIG_BR_EXT ++ ++#define CONFIG_TX_MCAST2UNI // Support IP multicast->unicast ++//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs. ++ ++/* ++ * Interface Related Config ++ */ ++ ++#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ #define CONFIG_USB_TX_AGGREGATION ++ #define CONFIG_USB_RX_AGGREGATION ++#endif ++ ++#define CONFIG_PREALLOC_RECV_SKB ++//#define CONFIG_REDUCE_USB_TX_INT // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. ++//#define CONFIG_EASY_REPLACEMENT ++ ++/* ++ * CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now! ++ */ ++//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. ++//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++#undef CONFIG_PREALLOC_RECV_SKB ++#endif ++ ++/* ++ * USB VENDOR REQ BUFFER ALLOCATION METHOD ++ * if not set we'll use function local variable (stack memory) ++ */ ++//#define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ ++#define CONFIG_USB_VENDOR_REQ_MUTEX ++#define CONFIG_VENDOR_REQ_RETRY ++ ++//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++ ++ ++/* ++ * HAL Related Config ++ */ ++ ++#define RTL8188E_RX_PACKET_INCLUDE_CRC 0 ++ ++#define SUPPORTED_BLOCK_IO ++#define CONFIG_REGULATORY_CTRL ++ ++//#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0 ++ ++#define CONFIG_OUT_EP_WIFI_MODE 0 ++ ++#define ENABLE_USB_DROP_INCORRECT_OUT ++ ++ ++//#define RTL8192CU_ADHOC_WORKAROUND_SETTING ++ ++#define DISABLE_BB_RF 0 ++ ++//#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0 ++ ++#ifdef CONFIG_MP_INCLUDED ++ #define MP_DRIVER 1 ++ #define CONFIG_MP_IWPRIV_SUPPORT ++ //#undef CONFIG_USB_TX_AGGREGATION ++ //#undef CONFIG_USB_RX_AGGREGATION ++#else ++ #define MP_DRIVER 0 ++#endif ++ ++ ++/* ++ * Platform Related Config ++ */ ++#ifdef CONFIG_PLATFORM_MN10300 ++ #define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ #define CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ #if defined (CONFIG_SW_ANTENNA_DIVERSITY) ++ #undef CONFIG_SW_ANTENNA_DIVERSITY ++ #define CONFIG_HW_ANTENNA_DIVERSITY ++ #endif ++ ++ #if defined (CONFIG_POWER_SAVING) ++ #undef CONFIG_POWER_SAVING ++ #endif ++ ++#endif//CONFIG_PLATFORM_MN10300 ++ ++ ++ ++#ifdef CONFIG_PLATFORM_TI_DM365 ++#define CONFIG_USE_USB_BUFFER_ALLOC_RX ++#endif ++ ++ ++#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X) ++ #ifdef CONFIG_USB_TX_AGGREGATION ++ #undef CONFIG_USB_TX_AGGREGATION ++ #endif ++ #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ #define CONFIG_USE_USB_BUFFER_ALLOC_TX ++ #endif ++ #ifndef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ #define CONFIG_USE_USB_BUFFER_ALLOC_RX ++ #endif ++#endif ++ ++ ++/* ++ * Outsource Related Config ++ */ ++ ++#define RTL8192CE_SUPPORT 0 ++#define RTL8192CU_SUPPORT 0 ++#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT) ++ ++#define RTL8192DE_SUPPORT 0 ++#define RTL8192DU_SUPPORT 0 ++#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT) ++ ++#define RTL8723AU_SUPPORT 0 ++#define RTL8723AS_SUPPORT 0 ++#define RTL8723AE_SUPPORT 0 ++#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT) ++ ++#define RTL8723_FPGA_VERIFICATION 0 ++ ++#define RTL8188EE_SUPPORT 0 ++#define RTL8188EU_SUPPORT 1 ++#define RTL8188ES_SUPPORT 0 ++#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT) ++#define RTL8188E_FOR_TEST_CHIP 0 ++//#if (RTL8188E_SUPPORT==1) ++#define RATE_ADAPTIVE_SUPPORT 1 ++#define POWER_TRAINING_ACTIVE 1 ++ ++//#endif ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++//#define CONFIG_TX_EARLY_MODE ++#endif ++ ++#ifdef CONFIG_TX_EARLY_MODE ++#define RTL8188E_EARLY_MODE_PKT_NUM_10 0 ++#endif ++ ++#define CONFIG_80211D ++ ++#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR ++ ++/* ++ * Debug Related Config ++ */ ++#define DBG 0 ++ ++//#define CONFIG_DEBUG /* DBG_871X, etc... */ ++//#define CONFIG_DEBUG_RTL871X /* RT_TRACE, RT_PRINT_DATA, _func_enter_, _func_exit_ */ ++ ++//#define CONFIG_PROC_DEBUG ++ ++//#define DBG_CONFIG_ERROR_DETECT ++//#define DBG_CONFIG_ERROR_DETECT_INT ++//#define DBG_CONFIG_ERROR_RESET ++ ++//#define DBG_IO ++//#define DBG_DELAY_OS ++//#define DBG_MEM_ALLOC ++//#define DBG_IOCTL ++ ++//#define DBG_TX ++//#define DBG_XMIT_BUF ++//#define DBG_XMIT_BUF_EXT ++//#define DBG_TX_DROP_FRAME ++ ++//#define DBG_TRX_STA_PKTS ++ ++//#define DBG_RX_DROP_FRAME ++//#define DBG_RX_SEQ ++//#define DBG_RX_SIGNAL_DISPLAY_PROCESSING ++//#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap" ++ ++ ++ ++//#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++//#define DBG_ROAMING_TEST ++ ++//#define DBG_HAL_INIT_PROFILING ++ ++//#define DBG_MEMORY_LEAK ++ ++//TX use 1 urb ++//#define CONFIG_SINGLE_XMIT_BUF ++//RX use 1 urb ++//#define CONFIG_SINGLE_RECV_BUF ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/basic_types.h b/drivers/net/wireless/rtl818x/rtl8189/include/basic_types.h +new file mode 100644 +index 00000000..9532f2aa +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/basic_types.h +@@ -0,0 +1,338 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __BASIC_TYPES_H__ ++#define __BASIC_TYPES_H__ ++ ++#include ++ ++ ++#define SUCCESS 0 ++#define FAIL (-1) ++ ++#ifndef TRUE ++ #define _TRUE 1 ++#else ++ #define _TRUE TRUE ++#endif ++ ++#ifndef FALSE ++ #define _FALSE 0 ++#else ++ #define _FALSE FALSE ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ typedef signed char s8; ++ typedef unsigned char u8; ++ ++ typedef signed short s16; ++ typedef unsigned short u16; ++ ++ typedef signed long s32; ++ typedef unsigned long u32; ++ ++ typedef unsigned int uint; ++ typedef signed int sint; ++ ++ ++ typedef signed long long s64; ++ typedef unsigned long long u64; ++ ++ #ifdef NDIS50_MINIPORT ++ ++ #define NDIS_MAJOR_VERSION 5 ++ #define NDIS_MINOR_VERSION 0 ++ ++ #endif ++ ++ #ifdef NDIS51_MINIPORT ++ ++ #define NDIS_MAJOR_VERSION 5 ++ #define NDIS_MINOR_VERSION 1 ++ ++ #endif ++ ++ typedef NDIS_PROC proc_t; ++ ++ typedef LONG atomic_t; ++ ++#endif ++ ++ ++#ifdef PLATFORM_LINUX ++ ++ #include ++ #define IN ++ #define OUT ++ #define VOID void ++ #define NDIS_OID uint ++ #define NDIS_STATUS uint ++ ++ typedef signed int sint; ++ ++ #ifndef PVOID ++ typedef void * PVOID; ++ //#define PVOID (void *) ++ #endif ++ ++ #define UCHAR u8 ++ #define USHORT u16 ++ #define UINT u32 ++ #define ULONG u32 ++ ++ typedef void (*proc_t)(void*); ++ ++ typedef __kernel_size_t SIZE_T; ++ typedef __kernel_ssize_t SSIZE_T; ++ #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) ++ ++#endif ++ ++ ++#ifdef PLATFORM_FREEBSD ++ ++ typedef signed char s8; ++ typedef unsigned char u8; ++ ++ typedef signed short s16; ++ typedef unsigned short u16; ++ ++ typedef signed int s32; ++ typedef unsigned int u32; ++ ++ typedef unsigned int uint; ++ typedef signed int sint; ++ typedef long atomic_t; ++ ++ typedef signed long long s64; ++ typedef unsigned long long u64; ++ #define IN ++ #define OUT ++ #define VOID void ++ #define NDIS_OID uint ++ #define NDIS_STATUS uint ++ ++ #ifndef PVOID ++ typedef void * PVOID; ++ //#define PVOID (void *) ++ #endif ++ typedef u32 dma_addr_t; ++ #define UCHAR u8 ++ #define USHORT u16 ++ #define UINT u32 ++ #define ULONG u32 ++ ++ typedef void (*proc_t)(void*); ++ ++ typedef unsigned int __kernel_size_t; ++ typedef int __kernel_ssize_t; ++ ++ typedef __kernel_size_t SIZE_T; ++ typedef __kernel_ssize_t SSIZE_T; ++ #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) ++ ++#endif ++ ++#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) ++#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) ++ ++#define SIZE_PTR SIZE_T ++#define SSIZE_PTR SSIZE_T ++ ++//port from fw by thomas ++// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness ++ ++/* ++ * Call endian free function when ++ * 1. Read/write packet content. ++ * 2. Before write integer to IO. ++ * 3. After read integer from IO. ++*/ ++ ++// ++// Byte Swapping routine. ++// ++#define EF1Byte ++#define EF2Byte le16_to_cpu ++#define EF4Byte le32_to_cpu ++ ++// ++// Read LE format data from memory ++// ++#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) ++#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) ++#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) ++ ++// ++// Write LE data to memory ++// ++#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) ++#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) ++#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) ++ ++// ++// Example: ++// BIT_LEN_MASK_32(0) => 0x00000000 ++// BIT_LEN_MASK_32(1) => 0x00000001 ++// BIT_LEN_MASK_32(2) => 0x00000003 ++// BIT_LEN_MASK_32(32) => 0xFFFFFFFF ++// ++#define BIT_LEN_MASK_32(__BitLen) \ ++ (0xFFFFFFFF >> (32 - (__BitLen))) ++// ++// Example: ++// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 ++// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 ++// ++#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) ++ ++// ++// Description: ++// Return 4-byte value in host byte ordering from ++// 4-byte pointer in litten-endian system. ++// ++#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ ++ (EF4Byte(*((u32 *)(__pStart)))) ++ ++// ++// Description: ++// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to ++// 4-byte value in host byte ordering. ++// ++#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_32(__BitLen) \ ++ ) ++ ++// ++// Description: ++// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering ++// and return the result in 4-byte value in host byte ordering. ++// ++#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ ++ ) ++ ++// ++// Description: ++// Set subfield of little-endian 4-byte value to specified value. ++// ++#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u32 *)(__pStart)) = \ ++ EF4Byte( \ ++ LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++ ++#define BIT_LEN_MASK_16(__BitLen) \ ++ (0xFFFF >> (16 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) ++ ++#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ (EF2Byte(*((u16 *)(__pStart)))) ++ ++#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_16(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u16 *)(__pStart)) = \ ++ EF2Byte( \ ++ LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++#define BIT_LEN_MASK_8(__BitLen) \ ++ (0xFF >> (8 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) ++ ++#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ (EF1Byte(*((u8 *)(__pStart)))) ++ ++#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_8(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u8 *)(__pStart)) = \ ++ EF1Byte( \ ++ LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++//pclint ++#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ ) ++ ++//pclint ++#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \ ++{ \ ++ *((pu1Byte)(__pStart)) = \ ++ EF1Byte( \ ++ LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ((u1Byte)__Value) \ ++ ); \ ++} ++ ++// Get the N-bytes aligment offset from the current length ++#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) ++ ++typedef unsigned char BOOLEAN,*PBOOLEAN; ++ ++#endif //__BASIC_TYPES_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/big_endian.h b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/big_endian.h +new file mode 100644 +index 00000000..ccb31328 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/big_endian.h +@@ -0,0 +1,88 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H ++#define _LINUX_BYTEORDER_BIG_ENDIAN_H ++ ++#ifndef __BIG_ENDIAN ++#define __BIG_ENDIAN 4321 ++#endif ++#ifndef __BIG_ENDIAN_BITFIELD ++#define __BIG_ENDIAN_BITFIELD ++#endif ++ ++#include ++ ++#define __constant_htonl(x) ((__u32)(x)) ++#define __constant_ntohl(x) ((__u32)(x)) ++#define __constant_htons(x) ((__u16)(x)) ++#define __constant_ntohs(x) ((__u16)(x)) ++#define __constant_cpu_to_le64(x) ___constant_swab64((x)) ++#define __constant_le64_to_cpu(x) ___constant_swab64((x)) ++#define __constant_cpu_to_le32(x) ___constant_swab32((x)) ++#define __constant_le32_to_cpu(x) ___constant_swab32((x)) ++#define __constant_cpu_to_le16(x) ___constant_swab16((x)) ++#define __constant_le16_to_cpu(x) ___constant_swab16((x)) ++#define __constant_cpu_to_be64(x) ((__u64)(x)) ++#define __constant_be64_to_cpu(x) ((__u64)(x)) ++#define __constant_cpu_to_be32(x) ((__u32)(x)) ++#define __constant_be32_to_cpu(x) ((__u32)(x)) ++#define __constant_cpu_to_be16(x) ((__u16)(x)) ++#define __constant_be16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_le64(x) __swab64((x)) ++#define __le64_to_cpu(x) __swab64((x)) ++#define __cpu_to_le32(x) __swab32((x)) ++#define __le32_to_cpu(x) __swab32((x)) ++#define __cpu_to_le16(x) __swab16((x)) ++#define __le16_to_cpu(x) __swab16((x)) ++#define __cpu_to_be64(x) ((__u64)(x)) ++#define __be64_to_cpu(x) ((__u64)(x)) ++#define __cpu_to_be32(x) ((__u32)(x)) ++#define __be32_to_cpu(x) ((__u32)(x)) ++#define __cpu_to_be16(x) ((__u16)(x)) ++#define __be16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_le64p(x) __swab64p((x)) ++#define __le64_to_cpup(x) __swab64p((x)) ++#define __cpu_to_le32p(x) __swab32p((x)) ++#define __le32_to_cpup(x) __swab32p((x)) ++#define __cpu_to_le16p(x) __swab16p((x)) ++#define __le16_to_cpup(x) __swab16p((x)) ++#define __cpu_to_be64p(x) (*(__u64*)(x)) ++#define __be64_to_cpup(x) (*(__u64*)(x)) ++#define __cpu_to_be32p(x) (*(__u32*)(x)) ++#define __be32_to_cpup(x) (*(__u32*)(x)) ++#define __cpu_to_be16p(x) (*(__u16*)(x)) ++#define __be16_to_cpup(x) (*(__u16*)(x)) ++#define __cpu_to_le64s(x) __swab64s((x)) ++#define __le64_to_cpus(x) __swab64s((x)) ++#define __cpu_to_le32s(x) __swab32s((x)) ++#define __le32_to_cpus(x) __swab32s((x)) ++#define __cpu_to_le16s(x) __swab16s((x)) ++#define __le16_to_cpus(x) __swab16s((x)) ++#define __cpu_to_be64s(x) do {} while (0) ++#define __be64_to_cpus(x) do {} while (0) ++#define __cpu_to_be32s(x) do {} while (0) ++#define __be32_to_cpus(x) do {} while (0) ++#define __cpu_to_be16s(x) do {} while (0) ++#define __be16_to_cpus(x) do {} while (0) ++ ++#include ++ ++#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/generic.h b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/generic.h +new file mode 100644 +index 00000000..759b0c47 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/generic.h +@@ -0,0 +1,213 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_GENERIC_H ++#define _LINUX_BYTEORDER_GENERIC_H ++ ++/* ++ * linux/byteorder_generic.h ++ * Generic Byte-reordering support ++ * ++ * Francois-Rene Rideau 19970707 ++ * gathered all the good ideas from all asm-foo/byteorder.h into one file, ++ * cleaned them up. ++ * I hope it is compliant with non-GCC compilers. ++ * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, ++ * because I wasn't sure it would be ok to put it in types.h ++ * Upgraded it to 2.1.43 ++ * Francois-Rene Rideau 19971012 ++ * Upgraded it to 2.1.57 ++ * to please Linus T., replaced huge #ifdef's between little/big endian ++ * by nestedly #include'd files. ++ * Francois-Rene Rideau 19971205 ++ * Made it to 2.1.71; now a facelift: ++ * Put files under include/linux/byteorder/ ++ * Split swab from generic support. ++ * ++ * TODO: ++ * = Regular kernel maintainers could also replace all these manual ++ * byteswap macros that remain, disseminated among drivers, ++ * after some grep or the sources... ++ * = Linus might want to rename all these macros and files to fit his taste, ++ * to fit his personal naming scheme. ++ * = it seems that a few drivers would also appreciate ++ * nybble swapping support... ++ * = every architecture could add their byteswap macro in asm/byteorder.h ++ * see how some architectures already do (i386, alpha, ppc, etc) ++ * = cpu_to_beXX and beXX_to_cpu might some day need to be well ++ * distinguished throughout the kernel. This is not the case currently, ++ * since little endian, big endian, and pdp endian machines needn't it. ++ * But this might be the case for, say, a port of Linux to 20/21 bit ++ * architectures (and F21 Linux addict around?). ++ */ ++ ++/* ++ * The following macros are to be defined by : ++ * ++ * Conversion of long and short int between network and host format ++ * ntohl(__u32 x) ++ * ntohs(__u16 x) ++ * htonl(__u32 x) ++ * htons(__u16 x) ++ * It seems that some programs (which? where? or perhaps a standard? POSIX?) ++ * might like the above to be functions, not macros (why?). ++ * if that's true, then detect them, and take measures. ++ * Anyway, the measure is: define only ___ntohl as a macro instead, ++ * and in a separate file, have ++ * unsigned long inline ntohl(x){return ___ntohl(x);} ++ * ++ * The same for constant arguments ++ * __constant_ntohl(__u32 x) ++ * __constant_ntohs(__u16 x) ++ * __constant_htonl(__u32 x) ++ * __constant_htons(__u16 x) ++ * ++ * Conversion of XX-bit integers (16- 32- or 64-) ++ * between native CPU format and little/big endian format ++ * 64-bit stuff only defined for proper architectures ++ * cpu_to_[bl]eXX(__uXX x) ++ * [bl]eXX_to_cpu(__uXX x) ++ * ++ * The same, but takes a pointer to the value to convert ++ * cpu_to_[bl]eXXp(__uXX x) ++ * [bl]eXX_to_cpup(__uXX x) ++ * ++ * The same, but change in situ ++ * cpu_to_[bl]eXXs(__uXX x) ++ * [bl]eXX_to_cpus(__uXX x) ++ * ++ * See asm-foo/byteorder.h for examples of how to provide ++ * architecture-optimized versions ++ * ++ */ ++ ++ ++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) ++/* ++ * inside the kernel, we can use nicknames; ++ * outside of it, we must avoid POSIX namespace pollution... ++ */ ++#define cpu_to_le64 __cpu_to_le64 ++#define le64_to_cpu __le64_to_cpu ++#define cpu_to_le32 __cpu_to_le32 ++#define le32_to_cpu __le32_to_cpu ++#define cpu_to_le16 __cpu_to_le16 ++#define le16_to_cpu __le16_to_cpu ++#define cpu_to_be64 __cpu_to_be64 ++#define be64_to_cpu __be64_to_cpu ++#define cpu_to_be32 __cpu_to_be32 ++#define be32_to_cpu __be32_to_cpu ++#define cpu_to_be16 __cpu_to_be16 ++#define be16_to_cpu __be16_to_cpu ++#define cpu_to_le64p __cpu_to_le64p ++#define le64_to_cpup __le64_to_cpup ++#define cpu_to_le32p __cpu_to_le32p ++#define le32_to_cpup __le32_to_cpup ++#define cpu_to_le16p __cpu_to_le16p ++#define le16_to_cpup __le16_to_cpup ++#define cpu_to_be64p __cpu_to_be64p ++#define be64_to_cpup __be64_to_cpup ++#define cpu_to_be32p __cpu_to_be32p ++#define be32_to_cpup __be32_to_cpup ++#define cpu_to_be16p __cpu_to_be16p ++#define be16_to_cpup __be16_to_cpup ++#define cpu_to_le64s __cpu_to_le64s ++#define le64_to_cpus __le64_to_cpus ++#define cpu_to_le32s __cpu_to_le32s ++#define le32_to_cpus __le32_to_cpus ++#define cpu_to_le16s __cpu_to_le16s ++#define le16_to_cpus __le16_to_cpus ++#define cpu_to_be64s __cpu_to_be64s ++#define be64_to_cpus __be64_to_cpus ++#define cpu_to_be32s __cpu_to_be32s ++#define be32_to_cpus __be32_to_cpus ++#define cpu_to_be16s __cpu_to_be16s ++#define be16_to_cpus __be16_to_cpus ++#endif ++ ++ ++/* ++ * Handle ntohl and suches. These have various compatibility ++ * issues - like we want to give the prototype even though we ++ * also have a macro for them in case some strange program ++ * wants to take the address of the thing or something.. ++ * ++ * Note that these used to return a "long" in libc5, even though ++ * long is often 64-bit these days.. Thus the casts. ++ * ++ * They have to be macros in order to do the constant folding ++ * correctly - if the argument passed into a inline function ++ * it is no longer constant according to gcc.. ++ */ ++ ++#undef ntohl ++#undef ntohs ++#undef htonl ++#undef htons ++ ++/* ++ * Do the prototypes. Somebody might want to take the ++ * address or some such sick thing.. ++ */ ++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) ++extern __u32 ntohl(__u32); ++extern __u32 htonl(__u32); ++#else //defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) ++#ifndef PLATFORM_FREEBSD ++extern unsigned long int ntohl(unsigned long int); ++extern unsigned long int htonl(unsigned long int); ++#endif ++#endif ++#ifndef PLATFORM_FREEBSD ++extern unsigned short int ntohs(unsigned short int); ++extern unsigned short int htons(unsigned short int); ++#endif ++ ++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) ++ ++#define ___htonl(x) __cpu_to_be32(x) ++#define ___htons(x) __cpu_to_be16(x) ++#define ___ntohl(x) __be32_to_cpu(x) ++#define ___ntohs(x) __be16_to_cpu(x) ++ ++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) ++#define htonl(x) ___htonl(x) ++#define ntohl(x) ___ntohl(x) ++#else ++#define htonl(x) ((unsigned long)___htonl(x)) ++#define ntohl(x) ((unsigned long)___ntohl(x)) ++#endif ++#define htons(x) ___htons(x) ++#define ntohs(x) ___ntohs(x) ++ ++#endif /* OPTIMIZE */ ++ ++ ++#if defined (PLATFORM_WINDOWS) ++ ++#define htonl(x) __cpu_to_be32(x) ++#define ntohl(x) __be32_to_cpu(x) ++#define htons(x) __cpu_to_be16(x) ++#define ntohs(x) __be16_to_cpu(x) ++ ++ ++#endif ++ ++#endif /* _LINUX_BYTEORDER_GENERIC_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/little_endian.h b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/little_endian.h +new file mode 100644 +index 00000000..5a3c8ab4 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/little_endian.h +@@ -0,0 +1,90 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H ++#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H ++ ++#ifndef __LITTLE_ENDIAN ++#define __LITTLE_ENDIAN 1234 ++#endif ++#ifndef __LITTLE_ENDIAN_BITFIELD ++#define __LITTLE_ENDIAN_BITFIELD ++#endif ++ ++#include ++ ++#ifndef __constant_htonl ++#define __constant_htonl(x) ___constant_swab32((x)) ++#define __constant_ntohl(x) ___constant_swab32((x)) ++#define __constant_htons(x) ___constant_swab16((x)) ++#define __constant_ntohs(x) ___constant_swab16((x)) ++#define __constant_cpu_to_le64(x) ((__u64)(x)) ++#define __constant_le64_to_cpu(x) ((__u64)(x)) ++#define __constant_cpu_to_le32(x) ((__u32)(x)) ++#define __constant_le32_to_cpu(x) ((__u32)(x)) ++#define __constant_cpu_to_le16(x) ((__u16)(x)) ++#define __constant_le16_to_cpu(x) ((__u16)(x)) ++#define __constant_cpu_to_be64(x) ___constant_swab64((x)) ++#define __constant_be64_to_cpu(x) ___constant_swab64((x)) ++#define __constant_cpu_to_be32(x) ___constant_swab32((x)) ++#define __constant_be32_to_cpu(x) ___constant_swab32((x)) ++#define __constant_cpu_to_be16(x) ___constant_swab16((x)) ++#define __constant_be16_to_cpu(x) ___constant_swab16((x)) ++#define __cpu_to_le64(x) ((__u64)(x)) ++#define __le64_to_cpu(x) ((__u64)(x)) ++#define __cpu_to_le32(x) ((__u32)(x)) ++#define __le32_to_cpu(x) ((__u32)(x)) ++#define __cpu_to_le16(x) ((__u16)(x)) ++#define __le16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_be64(x) __swab64((x)) ++#define __be64_to_cpu(x) __swab64((x)) ++#define __cpu_to_be32(x) __swab32((x)) ++#define __be32_to_cpu(x) __swab32((x)) ++#define __cpu_to_be16(x) __swab16((x)) ++#define __be16_to_cpu(x) __swab16((x)) ++#define __cpu_to_le64p(x) (*(__u64*)(x)) ++#define __le64_to_cpup(x) (*(__u64*)(x)) ++#define __cpu_to_le32p(x) (*(__u32*)(x)) ++#define __le32_to_cpup(x) (*(__u32*)(x)) ++#define __cpu_to_le16p(x) (*(__u16*)(x)) ++#define __le16_to_cpup(x) (*(__u16*)(x)) ++#define __cpu_to_be64p(x) __swab64p((x)) ++#define __be64_to_cpup(x) __swab64p((x)) ++#define __cpu_to_be32p(x) __swab32p((x)) ++#define __be32_to_cpup(x) __swab32p((x)) ++#define __cpu_to_be16p(x) __swab16p((x)) ++#define __be16_to_cpup(x) __swab16p((x)) ++#define __cpu_to_le64s(x) do {} while (0) ++#define __le64_to_cpus(x) do {} while (0) ++#define __cpu_to_le32s(x) do {} while (0) ++#define __le32_to_cpus(x) do {} while (0) ++#define __cpu_to_le16s(x) do {} while (0) ++#define __le16_to_cpus(x) do {} while (0) ++#define __cpu_to_be64s(x) __swab64s((x)) ++#define __be64_to_cpus(x) __swab64s((x)) ++#define __cpu_to_be32s(x) __swab32s((x)) ++#define __be32_to_cpus(x) __swab32s((x)) ++#define __cpu_to_be16s(x) __swab16s((x)) ++#define __be16_to_cpus(x) __swab16s((x)) ++#endif // __constant_htonl ++ ++#include ++ ++#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swab.h b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swab.h +new file mode 100644 +index 00000000..067c8e43 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swab.h +@@ -0,0 +1,141 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_SWAB_H ++#define _LINUX_BYTEORDER_SWAB_H ++ ++#if !defined(CONFIG_PLATFORM_MSTAR) ++#ifndef __u16 ++typedef unsigned short __u16; ++#endif ++ ++#ifndef __u32 ++typedef unsigned int __u32; ++#endif ++ ++#ifndef __u8 ++typedef unsigned char __u8; ++#endif ++ ++#ifndef __u64 ++typedef unsigned long long __u64; ++#endif ++ ++ ++__inline static __u16 ___swab16(__u16 x) ++{ ++ __u16 __x = x; ++ return ++ ((__u16)( ++ (((__u16)(__x) & (__u16)0x00ffU) << 8) | ++ (((__u16)(__x) & (__u16)0xff00U) >> 8) )); ++ ++} ++ ++__inline static __u32 ___swab32(__u32 x) ++{ ++ __u32 __x = (x); ++ return ((__u32)( ++ (((__u32)(__x) & (__u32)0x000000ffUL) << 24) | ++ (((__u32)(__x) & (__u32)0x0000ff00UL) << 8) | ++ (((__u32)(__x) & (__u32)0x00ff0000UL) >> 8) | ++ (((__u32)(__x) & (__u32)0xff000000UL) >> 24) )); ++} ++ ++__inline static __u64 ___swab64(__u64 x) ++{ ++ __u64 __x = (x); ++ ++ return ++ ((__u64)( \ ++ (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) << 8) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >> 8) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \ ++ (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \ ++} ++#endif // CONFIG_PLATFORM_MSTAR ++ ++#ifndef __arch__swab16 ++__inline static __u16 __arch__swab16(__u16 x) ++{ ++ return ___swab16(x); ++} ++ ++#endif ++ ++#ifndef __arch__swab32 ++__inline static __u32 __arch__swab32(__u32 x) ++{ ++ __u32 __tmp = (x) ; ++ return ___swab32(__tmp); ++} ++#endif ++ ++#ifndef __arch__swab64 ++ ++__inline static __u64 __arch__swab64(__u64 x) ++{ ++ __u64 __tmp = (x) ; ++ return ___swab64(__tmp); ++} ++ ++ ++#endif ++ ++#ifndef __swab16 ++#define __swab16(x) __fswab16(x) ++#define __swab32(x) __fswab32(x) ++#define __swab64(x) __fswab64(x) ++#endif // __swab16 ++ ++#ifdef PLATFORM_FREEBSD ++__inline static __u16 __fswab16(__u16 x) ++#else ++__inline static const __u16 __fswab16(__u16 x) ++#endif //PLATFORM_FREEBSD ++{ ++ return __arch__swab16(x); ++} ++#ifdef PLATFORM_FREEBSD ++__inline static __u32 __fswab32(__u32 x) ++#else ++__inline static const __u32 __fswab32(__u32 x) ++#endif //PLATFORM_FREEBSD ++{ ++ return __arch__swab32(x); ++} ++ ++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) ++#define swab16 __swab16 ++#define swab32 __swab32 ++#define swab64 __swab64 ++#define swab16p __swab16p ++#define swab32p __swab32p ++#define swab64p __swab64p ++#define swab16s __swab16s ++#define swab32s __swab32s ++#define swab64s __swab64s ++#endif ++ ++#endif /* _LINUX_BYTEORDER_SWAB_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swabb.h b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swabb.h +new file mode 100644 +index 00000000..dbbd50f8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/byteorder/swabb.h +@@ -0,0 +1,157 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_SWABB_H ++#define _LINUX_BYTEORDER_SWABB_H ++ ++/* ++ * linux/byteorder/swabb.h ++ * SWAp Bytes Bizarrely ++ * swaHHXX[ps]?(foo) ++ * ++ * Support for obNUXIous pdp-endian and other bizarre architectures. ++ * Will Linux ever run on such ancient beasts? if not, this file ++ * will be but a programming pearl. Still, it's a reminder that we ++ * shouldn't be making too many assumptions when trying to be portable. ++ * ++ */ ++ ++/* ++ * Meaning of the names I chose (vaxlinux people feel free to correct them): ++ * swahw32 swap 16-bit half-words in a 32-bit word ++ * swahb32 swap 8-bit halves of each 16-bit half-word in a 32-bit word ++ * ++ * No 64-bit support yet. I don't know NUXI conventions for long longs. ++ * I guarantee it will be a mess when it's there, though :-> ++ * It will be even worse if there are conflicting 64-bit conventions. ++ * Hopefully, no one ever used 64-bit objects on NUXI machines. ++ * ++ */ ++ ++#define ___swahw32(x) \ ++({ \ ++ __u32 __x = (x); \ ++ ((__u32)( \ ++ (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \ ++ (((__u32)(__x) & (__u32)0xffff0000UL) >> 16) )); \ ++}) ++#define ___swahb32(x) \ ++({ \ ++ __u32 __x = (x); \ ++ ((__u32)( \ ++ (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \ ++ (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8) )); \ ++}) ++ ++#define ___constant_swahw32(x) \ ++ ((__u32)( \ ++ (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ ++ (((__u32)(x) & (__u32)0xffff0000UL) >> 16) )) ++#define ___constant_swahb32(x) \ ++ ((__u32)( \ ++ (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ ++ (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) )) ++ ++/* ++ * provide defaults when no architecture-specific optimization is detected ++ */ ++#ifndef __arch__swahw32 ++# define __arch__swahw32(x) ___swahw32(x) ++#endif ++#ifndef __arch__swahb32 ++# define __arch__swahb32(x) ___swahb32(x) ++#endif ++ ++#ifndef __arch__swahw32p ++# define __arch__swahw32p(x) __swahw32(*(x)) ++#endif ++#ifndef __arch__swahb32p ++# define __arch__swahb32p(x) __swahb32(*(x)) ++#endif ++ ++#ifndef __arch__swahw32s ++# define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0) ++#endif ++#ifndef __arch__swahb32s ++# define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0) ++#endif ++ ++ ++/* ++ * Allow constant folding ++ */ ++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) ++# define __swahw32(x) \ ++(__builtin_constant_p((__u32)(x)) ? \ ++ ___swahw32((x)) : \ ++ __fswahw32((x))) ++# define __swahb32(x) \ ++(__builtin_constant_p((__u32)(x)) ? \ ++ ___swahb32((x)) : \ ++ __fswahb32((x))) ++#else ++# define __swahw32(x) __fswahw32(x) ++# define __swahb32(x) __fswahb32(x) ++#endif /* OPTIMIZE */ ++ ++ ++__inline static__ __const__ __u32 __fswahw32(__u32 x) ++{ ++ return __arch__swahw32(x); ++} ++__inline static__ __u32 __swahw32p(__u32 *x) ++{ ++ return __arch__swahw32p(x); ++} ++__inline static__ void __swahw32s(__u32 *addr) ++{ ++ __arch__swahw32s(addr); ++} ++ ++ ++__inline static__ __const__ __u32 __fswahb32(__u32 x) ++{ ++ return __arch__swahb32(x); ++} ++__inline static__ __u32 __swahb32p(__u32 *x) ++{ ++ return __arch__swahb32p(x); ++} ++__inline static__ void __swahb32s(__u32 *addr) ++{ ++ __arch__swahb32s(addr); ++} ++ ++#ifdef __BYTEORDER_HAS_U64__ ++/* ++ * Not supported yet ++ */ ++#endif /* __BYTEORDER_HAS_U64__ */ ++ ++#if defined(PLATFORM_LINUX) ++#define swahw32 __swahw32 ++#define swahb32 __swahb32 ++#define swahw32p __swahw32p ++#define swahb32p __swahb32p ++#define swahw32s __swahw32s ++#define swahb32s __swahb32s ++#endif ++ ++#endif /* _LINUX_BYTEORDER_SWABB_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/circ_buf.h b/drivers/net/wireless/rtl818x/rtl8189/include/circ_buf.h +new file mode 100644 +index 00000000..23523164 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/circ_buf.h +@@ -0,0 +1,28 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CIRC_BUF_H_ ++#define __CIRC_BUF_H_ 1 ++ ++#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) ++ ++#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) ++ ++#endif //_CIRC_BUF_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/cmd_osdep.h b/drivers/net/wireless/rtl818x/rtl8189/include/cmd_osdep.h +new file mode 100644 +index 00000000..077efa73 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/cmd_osdep.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CMD_OSDEP_H_ ++#define __CMD_OSDEP_H_ ++ ++ ++#include ++#include ++#include ++ ++extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); ++extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv); ++extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv); ++extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); ++extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj); ++extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/custom_gpio.h b/drivers/net/wireless/rtl818x/rtl8189/include/custom_gpio.h +new file mode 100644 +index 00000000..c76b340f +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/custom_gpio.h +@@ -0,0 +1,32 @@ ++#ifndef __CUSTOM_GPIO_H__ ++#define __CUSTOM_GPIO_H___ ++ ++#include ++#include ++ ++#ifdef PLATFORM_OS_XP ++#include ++#endif ++ ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++typedef enum cust_gpio_modes { ++ WLAN_PWDN_ON, ++ WLAN_PWDN_OFF, ++ WLAN_POWER_ON, ++ WLAN_POWER_OFF, ++ WLAN_BT_PWDN_ON, ++ WLAN_BT_PWDN_OFF ++} cust_gpio_modes_t; ++ ++extern int rtw_wifi_gpio_init(void); ++extern int rtw_wifi_gpio_deinit(void); ++extern void rtw_wifi_gpio_wlan_ctrl(int onoff); ++ ++#endif +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_conf.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_conf.h +new file mode 100644 +index 00000000..13176879 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_conf.h +@@ -0,0 +1,78 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_CONF_H__ ++#define __DRV_CONF_H__ ++#include "autoconf.h" ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++//Older Android kernel doesn't has CONFIG_ANDROID defined, ++//add this to force CONFIG_ANDROID defined ++#ifdef CONFIG_PLATFORM_ANDROID ++#define CONFIG_ANDROID ++#endif ++ ++#ifdef CONFIG_ANDROID ++//Some Android build will restart the UI while non-printable ascii is passed ++//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID ++//for Android here. If you are sure there is no risk on your system about this, ++//mask this macro define to support non-printable ascii ssid. ++//#define CONFIG_VALIDATE_SSID ++ ++//Android expect dbm as the rx signal strength unit ++#define CONFIG_SIGNAL_DISPLAY_DBM ++#endif ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE) ++ #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" ++ #undef CONFIG_RESUME_IN_WORKQUEUE ++#endif ++ ++#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE) ++ #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" ++ #undef CONFIG_RESUME_IN_WORKQUEUE ++#endif ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this... ++ #if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) ++ #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." ++ #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." ++ #endif ++#endif ++ ++//About USB VENDOR REQ ++#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" ++ #define CONFIG_USB_VENDOR_REQ_MUTEX ++#endif ++#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" ++ #define CONFIG_USB_VENDOR_REQ_MUTEX ++#endif ++ ++ ++//#include ++ ++#endif // __DRV_CONF_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types.h +new file mode 100644 +index 00000000..57bd5172 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types.h +@@ -0,0 +1,695 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*------------------------------------------------------------------------------- ++ ++ For type defines and data structure defines ++ ++--------------------------------------------------------------------------------*/ ++ ++ ++#ifndef __DRV_TYPES_H__ ++#define __DRV_TYPES_H__ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++#include ++#endif ++ ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++enum _NIC_VERSION { ++ ++ RTL8711_NIC, ++ RTL8712_NIC, ++ RTL8713_NIC, ++ RTL8716_NIC ++ ++}; ++ ++ ++typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER; ++ ++#ifdef CONFIG_80211N_HT ++#include ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_WAPI_SUPPORT ++#include ++#endif ++ ++#ifdef CONFIG_DRVEXT_MODULE ++#include ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++#include ++#endif ++ ++#ifdef CONFIG_BR_EXT ++#include ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ #include "ioctl_cfg80211.h" ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#define SPEC_DEV_ID_NONE BIT(0) ++#define SPEC_DEV_ID_DISABLE_HT BIT(1) ++#define SPEC_DEV_ID_ENABLE_PS BIT(2) ++#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) ++#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) ++#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) ++ ++struct specific_device_id{ ++ ++ u32 flags; ++ ++ u16 idVendor; ++ u16 idProduct; ++ ++}; ++ ++struct registry_priv ++{ ++ u8 chip_version; ++ u8 rfintfs; ++ u8 lbkmode; ++ u8 hci; ++ NDIS_802_11_SSID ssid; ++ u8 network_mode; //infra, ad-hoc, auto ++ u8 channel;//ad-hoc support requirement ++ u8 wireless_mode;//A, B, G, auto ++ u8 scan_mode;//active, passive ++ u8 radio_enable; ++ u8 preamble;//long, short, auto ++ u8 vrtl_carrier_sense;//Enable, Disable, Auto ++ u8 vcs_type;//RTS/CTS, CTS-to-self ++ u16 rts_thresh; ++ u16 frag_thresh; ++ u8 adhoc_tx_pwr; ++ u8 soft_ap; ++ u8 power_mgnt; ++ u8 ips_mode; ++ u8 smart_ps; ++ u8 long_retry_lmt; ++ u8 short_retry_lmt; ++ u16 busy_thresh; ++ u8 ack_policy; ++ u8 mp_mode; ++ u8 software_encrypt; ++ u8 software_decrypt; ++ #ifdef CONFIG_TX_EARLY_MODE ++ u8 early_mode; ++ #endif ++ u8 acm_method; ++ //UAPSD ++ u8 wmm_enable; ++ u8 uapsd_enable; ++ u8 uapsd_max_sp; ++ u8 uapsd_acbk_en; ++ u8 uapsd_acbe_en; ++ u8 uapsd_acvi_en; ++ u8 uapsd_acvo_en; ++ ++ WLAN_BSSID_EX dev_network; ++ ++#ifdef CONFIG_80211N_HT ++ u8 ht_enable; ++ u8 cbw40_enable; ++ u8 ampdu_enable;//for tx ++ u8 rx_stbc; ++ u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted ++#endif ++ u8 lowrate_two_xmit; ++ ++ u8 rf_config ; ++ u8 low_power ; ++ ++ u8 wifi_spec;// !turbo_mode ++ ++ u8 channel_plan; ++#ifdef CONFIG_BT_COEXIST ++ u8 btcoex; ++ u8 bt_iso; ++ u8 bt_sco; ++ u8 bt_ampdu; ++#endif ++ BOOLEAN bAcceptAddbaReq; ++ ++ u8 antdiv_cfg; ++ u8 antdiv_type; ++ ++ u8 usbss_enable;//0:disable,1:enable ++ u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config ++ u8 hwpwrp_detect;//0:disable,1:enable ++ ++ u8 hw_wps_pbc;//0:disable,1:enable ++ ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ char adaptor_info_caching_file_path[PATH_LENGTH_MAX]; ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ u8 max_roaming_times; // the max number driver will try to roaming ++#endif ++ ++#ifdef CONFIG_IOL ++ u8 fw_iol; //enable iol without other concern ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ u8 dmsp;//0:disable,1:enable ++#endif ++ ++#ifdef CONFIG_80211D ++ u8 enable80211d; ++#endif ++ ++ u8 ifname[16]; ++ u8 if2name[16]; ++ ++ u8 notch_filter; ++ ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ u8 force_ant;//0 normal,1 main,2 aux ++ u8 force_igi;//0 normal ++#endif ++ u8 regulatory_tid; ++ u8 qos_opt_enable; ++}; ++ ++ ++//For registry parameters ++#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field)) ++#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field) ++#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field)) ++#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) ++ ++ ++ ++#ifdef CONFIG_SDIO_HCI ++#include ++#define INTF_DATA SDIO_DATA ++#elif defined(CONFIG_GSPI_HCI) ++#include ++#define INTF_DATA GSPI_DATA ++#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) ++#else ++#define is_primary_adapter(adapter) (1) ++#endif ++#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->if1) ++ ++#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums) ++#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id]) ++ ++enum _IFACE_ID { ++ IFACE_ID0, //maping to PRIMARY_ADAPTER ++ IFACE_ID1, //maping to SECONDARY_ADAPTER ++ IFACE_ID2, ++ IFACE_ID3, ++ IFACE_ID_MAX, ++}; ++ ++struct dvobj_priv ++{ ++ _adapter *if1; //PRIMARY_ADAPTER ++ _adapter *if2; //SECONDARY_ADAPTER ++ ++ s32 processing_dev_remove; ++ ++ //for local/global synchronization ++ _mutex hw_init_mutex; ++ _mutex h2c_fwcmd_mutex; ++ _mutex setch_mutex; ++ _mutex setbw_mutex; ++ ++ unsigned char oper_channel; //saved channel info when call set_channel_bw ++ unsigned char oper_bwmode; ++ unsigned char oper_ch_offset;//PRIME_CHNL_OFFSET ++ u32 on_oper_ch_time; ++ ++ _adapter *padapters[IFACE_ID_MAX]; ++ u8 iface_nums; // total number of ifaces used runtime ++ ++ //For 92D, DMDP have 2 interface. ++ u8 InterfaceNumber; ++ u8 NumInterfaces; ++ ++ //In /Out Pipe information ++ int RtInPipe[2]; ++ int RtOutPipe[3]; ++ u8 Queue2Pipe[HW_QUEUE_ENTRY];//for out pipe mapping ++ ++ u8 irq_alloc; ++ ATOMIC_T continual_io_error; ++ ++ struct pwrctrl_priv pwrctl_priv; ++ ++/*-------- below is for SDIO INTERFACE --------*/ ++ ++#ifdef INTF_DATA ++ INTF_DATA intf_data; ++#endif ++ ++/*-------- below is for USB INTERFACE --------*/ ++ ++#ifdef CONFIG_USB_HCI ++ ++ u8 nr_endpoint; ++ u8 ishighspeed; ++ u8 RtNumInPipes; ++ u8 RtNumOutPipes; ++ int ep_num[5]; //endpoint number ++ ++ int RegUsbSS; ++ ++ _sema usb_suspend_sema; ++ ++#ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _mutex usb_vendor_req_mutex; ++#endif ++ ++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ u8 * usb_alloc_vendor_req_buf; ++ u8 * usb_vendor_req_buf; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ //related device objects ++ PDEVICE_OBJECT pphysdevobj;//pPhysDevObj; ++ PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj; ++ PDEVICE_OBJECT pnextdevobj;//pNextDevObj; ++ ++ u8 nextdevstacksz;//unsigned char NextDeviceStackSize; //= (CHAR)CEdevice->pUsbDevObj->StackSize + 1; ++ ++ //urb for control diescriptor request ++ ++#ifdef PLATFORM_OS_XP ++ struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb; ++ PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;//UsbConfigurationDescriptor; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ WCHAR active_path[MAX_ACTIVE_REG_PATH]; // adapter regpath ++ USB_EXTENSION usb_extension; ++ ++ _nic_hdl pipehdls_r8192c[0x10]; ++#endif ++ ++ u32 config_descriptor_len;//ULONG UsbConfigurationDescriptorLength; ++#endif//PLATFORM_WINDOWS ++ ++#ifdef PLATFORM_LINUX ++ struct usb_interface *pusbintf; ++ struct usb_device *pusbdev; ++#endif//PLATFORM_LINUX ++ ++#ifdef PLATFORM_FREEBSD ++ struct usb_interface *pusbintf; ++ struct usb_device *pusbdev; ++#endif//PLATFORM_FREEBSD ++ ++#endif//CONFIG_USB_HCI ++ ++/*-------- below is for PCIE INTERFACE --------*/ ++ ++#ifdef CONFIG_PCI_HCI ++ ++#ifdef PLATFORM_LINUX ++ struct pci_dev *ppcidev; ++ ++ //PCI MEM map ++ unsigned long pci_mem_end; /* shared mem end */ ++ unsigned long pci_mem_start; /* shared mem start */ ++ ++ //PCI IO map ++ unsigned long pci_base_addr; /* device I/O address */ ++ ++ //PciBridge ++ struct pci_priv pcipriv; ++ ++ u16 irqline; ++ u8 irq_enabled; ++ RT_ISR_CONTENT isr_content; ++ _lock irq_th_lock; ++ ++ //ASPM ++ u8 const_pci_aspm; ++ u8 const_amdpci_aspm; ++ u8 const_hwsw_rfoff_d3; ++ u8 const_support_pciaspm; ++ // pci-e bridge */ ++ u8 const_hostpci_aspm_setting; ++ // pci-e device */ ++ u8 const_devicepci_aspm_setting; ++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. ++ u8 b_support_backdoor; ++ u8 bdma64; ++#endif//PLATFORM_LINUX ++ ++#endif//CONFIG_PCI_HCI ++}; ++ ++#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv)) ++#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv) ++ ++#ifdef PLATFORM_LINUX ++static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) ++{ ++ /* todo: get interface type from dvobj and the return the dev accordingly */ ++#ifdef RTW_DVOBJ_CHIP_HW_TYPE ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ return &dvobj->pusbintf->dev; ++#endif ++#ifdef CONFIG_SDIO_HCI ++ return &dvobj->intf_data.func->dev; ++#endif ++#ifdef CONFIG_GSPI_HCI ++ return &dvobj->intf_data.func->dev; ++#endif ++#ifdef CONFIG_PCI_HCI ++ return &dvobj->ppcidev->dev; ++#endif ++} ++#endif ++ ++enum _IFACE_TYPE { ++ IFACE_PORT0, //mapping to port0 for C/D series chips ++ IFACE_PORT1, //mapping to port1 for C/D series chip ++ MAX_IFACE_PORT, ++}; ++ ++enum _ADAPTER_TYPE { ++ PRIMARY_ADAPTER, ++ SECONDARY_ADAPTER, ++ MAX_ADAPTER, ++}; ++ ++typedef enum _DRIVER_STATE{ ++ DRIVER_NORMAL = 0, ++ DRIVER_DISAPPEAR = 1, ++ DRIVER_REPLACE_DONGLE = 2, ++}DRIVER_STATE; ++ ++#ifdef CONFIG_INTEL_PROXIM ++struct proxim { ++ bool proxim_support; ++ bool proxim_on; ++ ++ void *proximity_priv; ++ int (*proxim_rx)(_adapter *padapter, ++ union recv_frame *precv_frame); ++ u8 (*proxim_get_var)(_adapter* padapter, u8 type); ++}; ++#endif //CONFIG_INTEL_PROXIM ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++typedef struct loopbackdata ++{ ++ _sema sema; ++ _thread_hdl_ lbkthread; ++ u8 bstop; ++ u32 cnt; ++ u16 size; ++ u16 txsize; ++ u8 txbuf[0x8000]; ++ u16 rxsize; ++ u8 rxbuf[0x8000]; ++ u8 msg[100]; ++ ++}LOOPBACKDATA, *PLOOPBACKDATA; ++#endif ++ ++struct _ADAPTER{ ++ int DriverState;// for disable driver using module, use dongle to replace module. ++ int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd ++ int bDongle;//build-in module or external dongle ++ u16 chip_type; ++ u16 HardwareType; ++ u16 interface_type;//USB,SDIO,SPI,PCI ++ ++ struct dvobj_priv *dvobj; ++ struct mlme_priv mlmepriv; ++ struct mlme_ext_priv mlmeextpriv; ++ struct cmd_priv cmdpriv; ++ struct evt_priv evtpriv; ++ //struct io_queue *pio_queue; ++ struct io_priv iopriv; ++ struct xmit_priv xmitpriv; ++ struct recv_priv recvpriv; ++ struct sta_priv stapriv; ++ struct security_priv securitypriv; ++ _lock security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use ++ struct registry_priv registrypriv; ++ struct eeprom_priv eeprompriv; ++ struct led_priv ledpriv; ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ //Check BT status for BT Hung. ++ struct workqueue_struct *priv_checkbt_wq; ++ struct delayed_work checkbt_work; ++#endif ++#ifdef CONFIG_MP_INCLUDED ++ struct mp_priv mppriv; ++#endif ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ struct drvext_priv drvextpriv; ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ struct hostapd_priv *phostapdpriv; ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++#ifdef CONFIG_P2P ++ struct cfg80211_wifidirect_info cfg80211_wdinfo; ++#endif //CONFIG_P2P ++#endif //CONFIG_IOCTL_CFG80211 ++ u32 setband; ++#ifdef CONFIG_P2P ++ struct wifidirect_info wdinfo; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info tdlsinfo; ++#endif //CONFIG_TDLS ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ u8 WapiSupport; ++ RT_WAPI_T wapiInfo; ++#endif ++ ++ ++#ifdef CONFIG_WFD ++ struct wifi_display_info wfd_info; ++#endif //CONFIG_WFD ++ ++ PVOID HalData; ++ u32 hal_data_sz; ++ struct hal_ops HalFunc; ++ ++ s32 bDriverStopped; ++ s32 bSurpriseRemoved; ++ s32 bCardDisableWOHSM; ++ ++ u32 IsrContent; ++ u32 ImrContent; ++ ++ u8 EepromAddressSize; ++ u8 hw_init_completed; ++ u8 bDriverIsGoingToUnload; ++ u8 init_adpt_in_progress; ++ u8 bHaltInProgress; ++ ++ _thread_hdl_ cmdThread; ++ _thread_hdl_ evtThread; ++ _thread_hdl_ xmitThread; ++ _thread_hdl_ recvThread; ++ ++#ifndef PLATFORM_LINUX ++ NDIS_STATUS (*dvobj_init)(struct dvobj_priv *dvobj); ++ void (*dvobj_deinit)(struct dvobj_priv *dvobj); ++#endif ++ ++ void (*intf_start)(_adapter * adapter); ++ void (*intf_stop)(_adapter * adapter); ++ ++#ifdef PLATFORM_WINDOWS ++ _nic_hdl hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle); ++ _nic_hdl hndis_config;//hNdisConfiguration; ++ NDIS_STRING fw_img; ++ ++ u32 NdisPacketFilter; ++ u8 MCList[MAX_MCAST_LIST_NUM][6]; ++ u32 MCAddrCount; ++#endif //end of PLATFORM_WINDOWS ++ ++ ++#ifdef PLATFORM_LINUX ++ _nic_hdl pnetdev; ++ ++ // used by rtw_rereg_nd_name related function ++ struct rereg_nd_name_data { ++ _nic_hdl old_pnetdev; ++ char old_ifname[IFNAMSIZ]; ++ u8 old_ips_mode; ++ u8 old_bRegUseLed; ++ } rereg_nd_name_priv; ++ ++ int bup; ++ struct net_device_stats stats; ++ struct iw_statistics iwstats; ++ struct proc_dir_entry *dir_dev;// for proc directory ++ struct proc_dir_entry *dir_odm; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct wireless_dev *rtw_wdev; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#endif //end of PLATFORM_LINUX ++ ++#ifdef PLATFORM_FREEBSD ++ _nic_hdl pifp; ++ int bup; ++ _lock glock; ++#endif //PLATFORM_FREEBSD ++ int net_closed; ++ ++ u8 bFWReady; ++ u8 bBTFWReady; ++ u8 bReadPortCancel; ++ u8 bWritePortCancel; ++ u8 bRxRSSIDisplay; ++ // Added by Albert 2012/10/26 ++ // The driver will show up the desired channel number when this flag is 1. ++ u8 bNotifyChannelChange; ++#ifdef CONFIG_P2P ++ // Added by Albert 2012/12/06 ++ // The driver will show the current P2P status when the upper application reads it. ++ u8 bShowGetP2PState; ++#endif ++#ifdef CONFIG_AUTOSUSPEND ++ u8 bDisableAutosuspend; ++#endif ++ ++ _adapter *pbuddy_adapter; ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) ++ u8 isprimary; //is primary adapter or not ++ //notes: ++ // if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER ++ // if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for SECONDARY_ADAPTER ++ // refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff. ++ u8 adapter_type;//used only in two inteface case(PRIMARY_ADAPTER and SECONDARY_ADAPTER) . ++ u8 iface_type; //interface port type, it depends on HW port ++#endif ++ ++ //extend to support multi interface ++ //IFACE_ID0 is equals to PRIMARY_ADAPTER ++ //IFACE_ID1 is equals to SECONDARY_ADAPTER ++ u8 iface_id; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ u8 DualMacConcurrent; // 1: DMSP 0:DMDP ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ _lock br_ext_lock; ++ //unsigned int macclone_completed; ++ struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; ++ int pppoe_connection_in_progress; ++ unsigned char pppoe_addr[MACADDRLEN]; ++ unsigned char scdb_mac[MACADDRLEN]; ++ unsigned char scdb_ip[4]; ++ struct nat25_network_db_entry *scdb_entry; ++ unsigned char br_mac[MACADDRLEN]; ++ unsigned char br_ip[4]; ++ ++ struct br_ext_info ethBrExtInfo; ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_INTEL_PROXIM ++ /* intel Proximity, should be alloc mem ++ * in intel Proximity module and can only ++ * be used in intel Proximity mode */ ++ struct proxim proximity; ++#endif //CONFIG_INTEL_PROXIM ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++ PLOOPBACKDATA ploopback; ++#endif ++ ++ u8 fix_rate; ++ ++ unsigned char in_cta_test; ++ ++}; ++ ++#define adapter_to_dvobj(adapter) (adapter->dvobj) ++#define adapter_to_pwrctl(adapter) (&(adapter->dvobj->pwrctl_priv)) ++ ++int rtw_handle_dualmac(_adapter *adapter, bool init); ++ ++__inline static u8 *myid(struct eeprom_priv *peepriv) ++{ ++ return (peepriv->mac_addr); ++} ++ ++ ++#endif //__DRV_TYPES_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_ce.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_ce.h +new file mode 100644 +index 00000000..b3d35235 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_ce.h +@@ -0,0 +1,93 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_CE_H__ ++#define __DRV_TYPES_CE_H__ ++ ++#include ++#include ++ ++#include ++ ++#define MAX_ACTIVE_REG_PATH 256 ++ ++#define MAX_MCAST_LIST_NUM 32 ++ ++ ++ ++//for ioctl ++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) ++ ++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h ++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++ ++typedef struct _MP_REG_ENTRY ++{ ++ ++ NDIS_STRING RegName; // variable name text ++ BOOLEAN bRequired; // 1 -> required, 0 -> optional ++ ++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString ++ uint FieldOffset; // offset to MP_ADAPTER field ++ uint FieldSize; // size (in bytes) of the field ++ ++#ifdef UNDER_AMD64 ++ u64 Default; ++#else ++ u32 Default; // default value to use ++#endif ++ ++ u32 Min; // minimum value allowed ++ u32 Max; // maximum value allowed ++} MP_REG_ENTRY, *PMP_REG_ENTRY; ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _USB_EXTENSION { ++ LPCUSB_FUNCS _lpUsbFuncs; ++ USB_HANDLE _hDevice; ++ PVOID pAdapter; ++ ++#if 0 ++ USB_ENDPOINT_DESCRIPTOR _endpACLIn; ++ USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh; ++ USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal; ++ ++ USB_PIPE pPipeIn; ++ USB_PIPE pPipeOutNormal; ++ USB_PIPE pPipeOutHigh; ++#endif ++ ++} USB_EXTENSION, *PUSB_EXTENSION; ++#endif ++ ++ ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++} OCTET_STRING, *POCTET_STRING; ++ ++ ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_gspi.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_gspi.h +new file mode 100644 +index 00000000..4d42c9cc +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_gspi.h +@@ -0,0 +1,49 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_GSPI_H__ ++#define __DRV_TYPES_GSPI_H__ ++ ++#include ++#include ++ ++// SPI Header Files ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++ ++typedef struct gspi_data ++{ ++ u8 func_number; ++ ++ u8 tx_block_mode; ++ u8 rx_block_mode; ++ u32 block_transfer_len; ++ ++#ifdef PLATFORM_LINUX ++ struct spi_device *func; ++ ++ struct workqueue_struct *priv_wq; ++ struct delayed_work irq_work; ++#endif ++} GSPI_DATA, *PGSPI_DATA; ++ ++#endif // #ifndef __DRV_TYPES_GSPI_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_linux.h +new file mode 100644 +index 00000000..db1c5856 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_linux.h +@@ -0,0 +1,25 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_LINUX_H__ ++#define __DRV_TYPES_LINUX_H__ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_sdio.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_sdio.h +new file mode 100644 +index 00000000..7e2b9ed2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_sdio.h +@@ -0,0 +1,71 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_SDIO_H__ ++#define __DRV_TYPES_SDIO_H__ ++ ++#include ++#include ++ ++// SDIO Header Files ++#ifdef PLATFORM_LINUX ++#include ++#endif ++#ifdef PLATFORM_OS_XP ++#include ++#include ++#endif ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++ ++typedef struct sdio_data ++{ ++ u8 func_number; ++ ++ u8 tx_block_mode; ++ u8 rx_block_mode; ++ u32 block_transfer_len; ++ ++#ifdef PLATFORM_LINUX ++ struct sdio_func *func; ++ _thread_hdl_ sys_sdio_irq_thd; ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ PDEVICE_OBJECT pphysdevobj; ++ PDEVICE_OBJECT pfuncdevobj; ++ PDEVICE_OBJECT pnextdevobj; ++ SDBUS_INTERFACE_STANDARD sdbusinft; ++ u8 nextdevstacksz; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ SD_DEVICE_HANDLE hDevice; ++ SD_CARD_RCA sd_rca; ++ SD_CARD_INTERFACE card_intf; ++ BOOLEAN enableIsarWithStatus; ++ WCHAR active_path[MAX_ACTIVE_REG_PATH]; ++ SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap; ++#endif ++} SDIO_DATA, *PSDIO_DATA; ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_xp.h b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_xp.h +new file mode 100644 +index 00000000..2d51b1db +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/drv_types_xp.h +@@ -0,0 +1,95 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_XP_H__ ++#define __DRV_TYPES_XP_H__ ++ ++#include ++#include ++ ++ ++ ++#define MAX_MCAST_LIST_NUM 32 ++ ++ ++ ++//for ioctl ++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) ++ ++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h ++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++ ++ ++#undef ON_VISTA ++//added by Jackson ++#ifndef ON_VISTA ++// ++// Bus driver versions ++// ++ ++#define SDBUS_DRIVER_VERSION_1 0x100 ++#define SDBUS_DRIVER_VERSION_2 0x200 ++ ++#define SDP_FUNCTION_TYPE 4 ++#define SDP_BUS_DRIVER_VERSION 5 ++#define SDP_BUS_WIDTH 6 ++#define SDP_BUS_CLOCK 7 ++#define SDP_BUS_INTERFACE_CONTROL 8 ++#define SDP_HOST_BLOCK_LENGTH 9 ++#define SDP_FUNCTION_BLOCK_LENGTH 10 ++#define SDP_FN0_BLOCK_LENGTH 11 ++#define SDP_FUNCTION_INT_ENABLE 12 ++#endif ++ ++ ++typedef struct _MP_REG_ENTRY ++{ ++ ++ NDIS_STRING RegName; // variable name text ++ BOOLEAN bRequired; // 1 -> required, 0 -> optional ++ ++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString ++ uint FieldOffset; // offset to MP_ADAPTER field ++ uint FieldSize; // size (in bytes) of the field ++ ++#ifdef UNDER_AMD64 ++ u64 Default; ++#else ++ u32 Default; // default value to use ++#endif ++ ++ u32 Min; // minimum value allowed ++ u32 Max; // maximum value allowed ++} MP_REG_ENTRY, *PMP_REG_ENTRY; ++ ++ ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++} OCTET_STRING, *POCTET_STRING; ++ ++ ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/ethernet.h b/drivers/net/wireless/rtl818x/rtl8189/include/ethernet.h +new file mode 100644 +index 00000000..cadc8c1d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/ethernet.h +@@ -0,0 +1,42 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*! \file */ ++#ifndef __INC_ETHERNET_H ++#define __INC_ETHERNET_H ++ ++#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length ++#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length ++#define LLC_HEADER_SIZE 6 //!< LLC Header Length ++#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size ++#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size ++#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size ++ ++#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address? ++#define RT_ETH_IS_BROADCAST(_pAddr) ( \ ++ ((UCHAR *)(_pAddr))[0]==0xff && \ ++ ((UCHAR *)(_pAddr))[1]==0xff && \ ++ ((UCHAR *)(_pAddr))[2]==0xff && \ ++ ((UCHAR *)(_pAddr))[3]==0xff && \ ++ ((UCHAR *)(_pAddr))[4]==0xff && \ ++ ((UCHAR *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address? ++ ++ ++#endif // #ifndef __INC_ETHERNET_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/gspi_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_hal.h +new file mode 100644 +index 00000000..8146d6a5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_hal.h +@@ -0,0 +1,37 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __GSPI_HAL_H__ ++#define __GSPI_HAL_H__ ++ ++ ++void spi_int_dpc(PADAPTER padapter); ++ ++#ifdef CONFIG_RTL8723A ++void rtl8723as_set_hal_ops(PADAPTER padapter); ++#define hal_set_hal_ops rtl8723as_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188es_set_hal_ops(PADAPTER padapter); ++#define hal_set_hal_ops rtl8188es_set_hal_ops ++#endif ++ ++#endif //__GSPI_HAL_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops.h b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops.h +new file mode 100644 +index 00000000..ffd98c5a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops.h +@@ -0,0 +1,171 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __GSPI_OPS_H__ ++#define __GSPI_OPS_H__ ++ ++/* follwing defination is based on ++ * GSPI spec of RTL8723, we temp ++ * suppose that it will be the same ++ * for diff chips of GSPI, if not ++ * we should move it to HAL folder */ ++#define SPI_LOCAL_DOMAIN 0x0 ++#define WLAN_IOREG_DOMAIN 0x8 ++#define FW_FIFO_DOMAIN 0x4 ++#define TX_HIQ_DOMAIN 0xc ++#define TX_MIQ_DOMAIN 0xd ++#define TX_LOQ_DOMAIN 0xe ++#define RX_RXFIFO_DOMAIN 0x1f ++ ++//IO Bus domain address mapping ++#define DEFUALT_OFFSET 0x0 ++#define SPI_LOCAL_OFFSET 0x10250000 ++#define WLAN_IOREG_OFFSET 0x10260000 ++#define FW_FIFO_OFFSET 0x10270000 ++#define TX_HIQ_OFFSET 0x10310000 ++#define TX_MIQ_OFFSET 0x1032000 ++#define TX_LOQ_OFFSET 0x10330000 ++#define RX_RXOFF_OFFSET 0x10340000 ++ ++//SPI Local registers ++#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control ++#define SPI_REG_STATUS_RECOVERY 0x0004 ++#define SPI_REG_INT_TIMEOUT 0x0006 ++#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask ++#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine ++#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length ++#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page ++#define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 ++#define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 ++#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion ++#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 ++#define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 ++#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock ++#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control ++#define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always ++#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always ++#define SPI_REG_CFG 0x00F0 //SPI Configuration Register ++ ++#define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET) ++#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET) ++#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET) ++#define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET) ++#define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET) ++#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET) ++#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET) ++ ++#define SPI_HIMR_DISABLED 0 ++ ++//SPI HIMR MASK diff with SDIO ++#define SPI_HISR_RX_REQUEST BIT(0) ++#define SPI_HISR_AVAL BIT(1) ++#define SPI_HISR_TXERR BIT(2) ++#define SPI_HISR_RXERR BIT(3) ++#define SPI_HISR_TXFOVW BIT(4) ++#define SPI_HISR_RXFOVW BIT(5) ++#define SPI_HISR_TXBCNOK BIT(6) ++#define SPI_HISR_TXBCNERR BIT(7) ++#define SPI_HISR_BCNERLY_INT BIT(16) ++#define SPI_HISR_ATIMEND BIT(17) ++#define SPI_HISR_ATIMEND_E BIT(18) ++#define SPI_HISR_CTWEND BIT(19) ++#define SPI_HISR_C2HCMD BIT(20) ++#define SPI_HISR_CPWM1 BIT(21) ++#define SPI_HISR_CPWM2 BIT(22) ++#define SPI_HISR_HSISR_IND BIT(23) ++#define SPI_HISR_GTINT3_IND BIT(24) ++#define SPI_HISR_GTINT4_IND BIT(25) ++#define SPI_HISR_PSTIMEOUT BIT(26) ++#define SPI_HISR_OCPINT BIT(27) ++#define SPI_HISR_TSF_BIT32_TOGGLE BIT(29) ++ ++#define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\ ++ SPI_HISR_RXERR |\ ++ SPI_HISR_TXFOVW |\ ++ SPI_HISR_RXFOVW |\ ++ SPI_HISR_TXBCNOK |\ ++ SPI_HISR_TXBCNERR |\ ++ SPI_HISR_C2HCMD |\ ++ SPI_HISR_CPWM1 |\ ++ SPI_HISR_CPWM2 |\ ++ SPI_HISR_HSISR_IND |\ ++ SPI_HISR_GTINT3_IND |\ ++ SPI_HISR_GTINT4_IND |\ ++ SPI_HISR_PSTIMEOUT |\ ++ SPI_HISR_OCPINT) ++ ++#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24) ++#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) ++#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) ++#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) ++#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) ++ ++#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24) ++//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) ++#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) ++#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) ++#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) ++ ++ ++//get status dword0 ++#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) ++#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) ++#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) ++#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) ++#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) ++ ++//get status dword1 ++#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) ++#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) ++#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) ++#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) ++#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) ++ ++ ++#define RXDESC_SIZE 24 ++ ++ ++struct spi_more_data { ++ unsigned long more_data; ++ unsigned long len; ++}; ++ ++#ifdef CONFIG_RTL8723A ++void rtl8723as_set_hal_ops(PADAPTER padapter); ++#define set_hal_ops rtl8723as_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188es_set_hal_ops(PADAPTER padapter); ++#define set_hal_ops rtl8188es_set_hal_ops ++#endif ++extern void spi_set_chip_endian(PADAPTER padapter); ++extern void spi_set_intf_ops(struct _io_ops *pops); ++extern void spi_set_chip_endian(PADAPTER padapter); ++extern void InitInterrupt8723ASdio(PADAPTER padapter); ++extern void InitSysInterrupt8723ASdio(PADAPTER padapter); ++extern void EnableInterrupt8723ASdio(PADAPTER padapter); ++extern void DisableInterrupt8723ASdio(PADAPTER padapter); ++extern void spi_int_hdl(PADAPTER padapter); ++extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); ++extern void InitInterrupt8188ESdio(PADAPTER padapter); ++extern void EnableInterrupt8188ESdio(PADAPTER padapter); ++extern void DisableInterrupt8188ESdio(PADAPTER padapter); ++ ++#endif //__GSPI_OPS_H__ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops_linux.h +new file mode 100644 +index 00000000..6358a0fa +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_ops_linux.h +@@ -0,0 +1,24 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_OPS_LINUX_H__ ++#define __SDIO_OPS_LINUX_H__ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/gspi_osintf.h b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_osintf.h +new file mode 100644 +index 00000000..f00da10d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/gspi_osintf.h +@@ -0,0 +1,35 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_OSINTF_H__ ++#define __SDIO_OSINTF_H__ ++ ++ ++#include ++#include ++#include ++ ++#ifdef PLATFORM_OS_CE ++extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter); ++SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter); ++extern void sd_setup_irs(PADAPTER padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/h2clbk.h b/drivers/net/wireless/rtl818x/rtl8189/include/h2clbk.h +new file mode 100644 +index 00000000..6034a026 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/h2clbk.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _H2CLBK_H_ ++ ++ ++#include ++#include ++ ++ ++void _lbk_cmd(PADAPTER Adapter); ++ ++void _lbk_rsp(PADAPTER Adapter); ++ ++void _lbk_evt(IN PADAPTER Adapter); ++ ++void h2c_event_callback(unsigned char *dev, unsigned char *pbuf); ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/hal_com.h b/drivers/net/wireless/rtl818x/rtl8189/include/hal_com.h +new file mode 100644 +index 00000000..e1542783 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/hal_com.h +@@ -0,0 +1,185 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __HAL_COMMON_H__ ++#define __HAL_COMMON_H__ ++ ++//---------------------------------------------------------------------------- ++// Rate Definition ++//---------------------------------------------------------------------------- ++//CCK ++#define RATR_1M 0x00000001 ++#define RATR_2M 0x00000002 ++#define RATR_55M 0x00000004 ++#define RATR_11M 0x00000008 ++//OFDM ++#define RATR_6M 0x00000010 ++#define RATR_9M 0x00000020 ++#define RATR_12M 0x00000040 ++#define RATR_18M 0x00000080 ++#define RATR_24M 0x00000100 ++#define RATR_36M 0x00000200 ++#define RATR_48M 0x00000400 ++#define RATR_54M 0x00000800 ++//MCS 1 Spatial Stream ++#define RATR_MCS0 0x00001000 ++#define RATR_MCS1 0x00002000 ++#define RATR_MCS2 0x00004000 ++#define RATR_MCS3 0x00008000 ++#define RATR_MCS4 0x00010000 ++#define RATR_MCS5 0x00020000 ++#define RATR_MCS6 0x00040000 ++#define RATR_MCS7 0x00080000 ++//MCS 2 Spatial Stream ++#define RATR_MCS8 0x00100000 ++#define RATR_MCS9 0x00200000 ++#define RATR_MCS10 0x00400000 ++#define RATR_MCS11 0x00800000 ++#define RATR_MCS12 0x01000000 ++#define RATR_MCS13 0x02000000 ++#define RATR_MCS14 0x04000000 ++#define RATR_MCS15 0x08000000 ++ ++//CCK ++#define RATE_1M BIT(0) ++#define RATE_2M BIT(1) ++#define RATE_5_5M BIT(2) ++#define RATE_11M BIT(3) ++//OFDM ++#define RATE_6M BIT(4) ++#define RATE_9M BIT(5) ++#define RATE_12M BIT(6) ++#define RATE_18M BIT(7) ++#define RATE_24M BIT(8) ++#define RATE_36M BIT(9) ++#define RATE_48M BIT(10) ++#define RATE_54M BIT(11) ++//MCS 1 Spatial Stream ++#define RATE_MCS0 BIT(12) ++#define RATE_MCS1 BIT(13) ++#define RATE_MCS2 BIT(14) ++#define RATE_MCS3 BIT(15) ++#define RATE_MCS4 BIT(16) ++#define RATE_MCS5 BIT(17) ++#define RATE_MCS6 BIT(18) ++#define RATE_MCS7 BIT(19) ++//MCS 2 Spatial Stream ++#define RATE_MCS8 BIT(20) ++#define RATE_MCS9 BIT(21) ++#define RATE_MCS10 BIT(22) ++#define RATE_MCS11 BIT(23) ++#define RATE_MCS12 BIT(24) ++#define RATE_MCS13 BIT(25) ++#define RATE_MCS14 BIT(26) ++#define RATE_MCS15 BIT(27) ++ ++// ALL CCK Rate ++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M ++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ ++ RATR_36M|RATR_48M|RATR_54M ++#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ ++ RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 ++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ ++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 ++ ++/*------------------------------ Tx Desc definition Macro ------------------------*/ ++//#pragma mark -- Tx Desc related definition. -- ++//---------------------------------------------------------------------------- ++//----------------------------------------------------------- ++// Rate ++//----------------------------------------------------------- ++// CCK Rates, TxHT = 0 ++#define DESC_RATE1M 0x00 ++#define DESC_RATE2M 0x01 ++#define DESC_RATE5_5M 0x02 ++#define DESC_RATE11M 0x03 ++ ++// OFDM Rates, TxHT = 0 ++#define DESC_RATE6M 0x04 ++#define DESC_RATE9M 0x05 ++#define DESC_RATE12M 0x06 ++#define DESC_RATE18M 0x07 ++#define DESC_RATE24M 0x08 ++#define DESC_RATE36M 0x09 ++#define DESC_RATE48M 0x0a ++#define DESC_RATE54M 0x0b ++ ++// MCS Rates, TxHT = 1 ++#define DESC_RATEMCS0 0x0c ++#define DESC_RATEMCS1 0x0d ++#define DESC_RATEMCS2 0x0e ++#define DESC_RATEMCS3 0x0f ++#define DESC_RATEMCS4 0x10 ++#define DESC_RATEMCS5 0x11 ++#define DESC_RATEMCS6 0x12 ++#define DESC_RATEMCS7 0x13 ++#define DESC_RATEMCS8 0x14 ++#define DESC_RATEMCS9 0x15 ++#define DESC_RATEMCS10 0x16 ++#define DESC_RATEMCS11 0x17 ++#define DESC_RATEMCS12 0x18 ++#define DESC_RATEMCS13 0x19 ++#define DESC_RATEMCS14 0x1a ++#define DESC_RATEMCS15 0x1b ++#define DESC_RATEMCS15_SG 0x1c ++#define DESC_RATEMCS32 0x20 ++ ++#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) ++#define REG_NOA_DESC_SEL 0x05CF ++#define REG_NOA_DESC_DURATION 0x05E0 ++#define REG_NOA_DESC_INTERVAL 0x05E4 ++#define REG_NOA_DESC_START 0x05E8 ++#define REG_NOA_DESC_COUNT 0x05EC ++ ++#include "HalVerDef.h" ++void dump_chip_info(HAL_VERSION ChipVersion); ++ ++ ++u8 //return the final channel plan decision ++hal_com_get_channel_plan( ++ IN PADAPTER padapter, ++ IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom) ++ IN u8 sw_channel_plan, //channel plan from SW (registry/module param) ++ IN u8 def_channel_plan, //channel plan used when the former two is invalid ++ IN BOOLEAN AutoLoadFail ++ ); ++ ++u8 MRateToHwRate(u8 rate); ++ ++void HalSetBrateCfg( ++ IN PADAPTER Adapter, ++ IN u8 *mBratesOS, ++ OUT u16 *pBrateCfg); ++ ++BOOLEAN ++Hal_MappingOutPipe( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe ++ ); ++ ++void hal_init_macaddr(_adapter *adapter); ++ ++void c2h_evt_clear(_adapter *adapter); ++s32 c2h_evt_read(_adapter *adapter, u8 *buf); ++ ++u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); ++u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); ++ ++#endif //__HAL_COMMON_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/hal_intf.h b/drivers/net/wireless/rtl818x/rtl8189/include/hal_intf.h +new file mode 100644 +index 00000000..2048321a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/hal_intf.h +@@ -0,0 +1,487 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __HAL_INTF_H__ ++#define __HAL_INTF_H__ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++ ++enum RTL871X_HCI_TYPE { ++ RTW_PCIE = BIT0, ++ RTW_USB = BIT1, ++ RTW_SDIO = BIT2, ++ RTW_GSPI = BIT3, ++}; ++ ++enum _CHIP_TYPE { ++ ++ NULL_CHIP_TYPE, ++ RTL8712_8188S_8191S_8192S, ++ RTL8188C_8192C, ++ RTL8192D, ++ RTL8723A, ++ RTL8188E, ++ MAX_CHIP_TYPE ++}; ++ ++ ++typedef enum _HW_VARIABLES{ ++ HW_VAR_MEDIA_STATUS, ++ HW_VAR_MEDIA_STATUS1, ++ HW_VAR_SET_OPMODE, ++ HW_VAR_MAC_ADDR, ++ HW_VAR_BSSID, ++ HW_VAR_INIT_RTS_RATE, ++ HW_VAR_BASIC_RATE, ++ HW_VAR_TXPAUSE, ++ HW_VAR_BCN_FUNC, ++ HW_VAR_CORRECT_TSF, ++ HW_VAR_CHECK_BSSID, ++ HW_VAR_MLME_DISCONNECT, ++ HW_VAR_MLME_SITESURVEY, ++ HW_VAR_MLME_JOIN, ++ HW_VAR_ON_RCR_AM, ++ HW_VAR_OFF_RCR_AM, ++ HW_VAR_BEACON_INTERVAL, ++ HW_VAR_SLOT_TIME, ++ HW_VAR_RESP_SIFS, ++ HW_VAR_ACK_PREAMBLE, ++ HW_VAR_SEC_CFG, ++ HW_VAR_BCN_VALID, ++ HW_VAR_RF_TYPE, ++ HW_VAR_DM_FLAG, ++ HW_VAR_DM_FUNC_OP, ++ HW_VAR_DM_FUNC_SET, ++ HW_VAR_DM_FUNC_CLR, ++ HW_VAR_CAM_EMPTY_ENTRY, ++ HW_VAR_CAM_INVALID_ALL, ++ HW_VAR_CAM_WRITE, ++ HW_VAR_CAM_READ, ++ HW_VAR_AC_PARAM_VO, ++ HW_VAR_AC_PARAM_VI, ++ HW_VAR_AC_PARAM_BE, ++ HW_VAR_AC_PARAM_BK, ++ HW_VAR_ACM_CTRL, ++ HW_VAR_AMPDU_MIN_SPACE, ++ HW_VAR_AMPDU_FACTOR, ++ HW_VAR_RXDMA_AGG_PG_TH, ++ HW_VAR_SET_RPWM, ++ HW_VAR_GET_CPWM, ++ HW_VAR_H2C_FW_PWRMODE, ++ HW_VAR_H2C_FW_JOINBSSRPT, ++ HW_VAR_FWLPS_RF_ON, ++ HW_VAR_H2C_FW_P2P_PS_OFFLOAD, ++ HW_VAR_TDLS_WRCR, ++ HW_VAR_TDLS_INIT_CH_SEN, ++ HW_VAR_TDLS_RS_RCR, ++ HW_VAR_TDLS_DONE_CH_SEN, ++ HW_VAR_INITIAL_GAIN, ++ HW_VAR_TRIGGER_GPIO_0, ++ HW_VAR_BT_SET_COEXIST, ++ HW_VAR_BT_ISSUE_DELBA, ++ HW_VAR_CURRENT_ANTENNA, ++ HW_VAR_ANTENNA_DIVERSITY_LINK, ++ HW_VAR_ANTENNA_DIVERSITY_SELECT, ++ HW_VAR_SWITCH_EPHY_WoWLAN, ++ HW_VAR_EFUSE_USAGE, ++ HW_VAR_EFUSE_BYTES, ++ HW_VAR_EFUSE_BT_USAGE, ++ HW_VAR_EFUSE_BT_BYTES, ++ HW_VAR_FIFO_CLEARN_UP, ++ HW_VAR_CHECK_TXBUF, ++ HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only ++ // The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. ++ // Unit in microsecond. 0 means disable this function. ++#ifdef CONFIG_WOWLAN ++ HW_VAR_WOWLAN, ++#endif ++ HW_VAR_SYS_CLKR, ++ HW_VAR_NAV_UPPER, ++ HW_VAR_RPT_TIMER_SETTING, ++ HW_VAR_TX_RPT_MAX_MACID, ++ HW_VAR_H2C_MEDIA_STATUS_RPT, ++ HW_VAR_CHK_HI_QUEUE_EMPTY, ++ HW_VAR_READ_LLT_TAB, ++ HW_VAR_C2HEVT_CLEAR, ++ HW_VAR_C2HEVT_MSG_NORMAL, ++}HW_VARIABLES; ++ ++typedef enum _HAL_DEF_VARIABLE{ ++ HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, ++ HAL_DEF_IS_SUPPORT_ANT_DIV, ++ HAL_DEF_CURRENT_ANTENNA, ++ HAL_DEF_DRVINFO_SZ, ++ HAL_DEF_MAX_RECVBUF_SZ, ++ HAL_DEF_RX_PACKET_OFFSET, ++ HAL_DEF_DBG_DUMP_RXPKT,//for dbg ++ HAL_DEF_DBG_DM_FUNC,//for dbg ++ HAL_DEF_RA_DECISION_RATE, ++ HAL_DEF_RA_SGI, ++ HAL_DEF_PT_PWR_STATUS, ++ HW_VAR_MAX_RX_AMPDU_FACTOR, ++ HW_DEF_RA_INFO_DUMP, ++ HAL_DEF_DBG_DUMP_TXPKT, ++ HW_DEF_FA_CNT_DUMP, ++ HW_DEF_ODM_DBG_FLAG, ++ HW_DEF_ODM_DBG_LEVEL, ++}HAL_DEF_VARIABLE; ++ ++typedef enum _HAL_ODM_VARIABLE{ ++ HAL_ODM_STA_INFO, ++ HAL_ODM_P2P_STATE, ++ HAL_ODM_WIFI_DISPLAY_STATE, ++}HAL_ODM_VARIABLE; ++ ++typedef enum _HAL_INTF_PS_FUNC{ ++ HAL_USB_SELECT_SUSPEND, ++ HAL_MAX_ID, ++}HAL_INTF_PS_FUNC; ++ ++typedef s32 (*c2h_id_filter)(u8 id); ++ ++struct hal_ops { ++ u32 (*hal_power_on)(_adapter *padapter); ++ void (*hal_power_off)(_adapter *padapter); ++ u32 (*hal_init)(_adapter *padapter); ++ u32 (*hal_deinit)(_adapter *padapter); ++ ++ void (*free_hal_data)(_adapter *padapter); ++ ++ u32 (*inirp_init)(_adapter *padapter); ++ u32 (*inirp_deinit)(_adapter *padapter); ++ ++ s32 (*init_xmit_priv)(_adapter *padapter); ++ void (*free_xmit_priv)(_adapter *padapter); ++ ++ s32 (*init_recv_priv)(_adapter *padapter); ++ void (*free_recv_priv)(_adapter *padapter); ++ ++ void (*InitSwLeds)(_adapter *padapter); ++ void (*DeInitSwLeds)(_adapter *padapter); ++ ++ void (*dm_init)(_adapter *padapter); ++ void (*dm_deinit)(_adapter *padapter); ++ void (*read_chip_version)(_adapter *padapter); ++ ++ void (*init_default_value)(_adapter *padapter); ++ ++ void (*intf_chip_configure)(_adapter *padapter); ++ ++ void (*read_adapter_info)(_adapter *padapter); ++ ++ void (*enable_interrupt)(_adapter *padapter); ++ void (*disable_interrupt)(_adapter *padapter); ++ s32 (*interrupt_handler)(_adapter *padapter); ++#ifdef CONFIG_WOWLAN ++ void (*clear_interrupt)(_adapter *padapter); ++#endif ++ void (*set_bwmode_handler)(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset); ++ void (*set_channel_handler)(_adapter *padapter, u8 channel); ++ ++ void (*hal_dm_watchdog)(_adapter *padapter); ++ ++ void (*SetHwRegHandler)(_adapter *padapter, u8 variable,u8* val); ++ void (*GetHwRegHandler)(_adapter *padapter, u8 variable,u8* val); ++ ++ u8 (*GetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++ u8 (*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++ ++ void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); ++ void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); ++ ++ void (*UpdateRAMaskHandler)(_adapter *padapter, u32 mac_id, u8 rssi_level); ++ void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); ++ ++ void (*Add_RateATid)(_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level); ++ ++ void (*run_thread)(_adapter *padapter); ++ void (*cancel_thread)(_adapter *padapter); ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ u8 (*AntDivBeforeLinkHandler)(_adapter *padapter); ++ void (*AntDivCompareHandler)(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); ++#endif ++ u8 (*interface_ps_func)(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val); ++ ++ s32 (*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe); ++ s32 (*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe); ++ s32 (*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++ u32 (*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); ++ void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); ++ u32 (*read_rfreg)(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); ++ void (*write_rfreg)(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ s32 (*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt); ++#endif ++ ++ void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); ++ void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest); ++ void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); ++ u16 (*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest); ++ int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); ++ int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ u8 (*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ BOOLEAN (*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ void (*sreset_init_value)(_adapter *padapter); ++ void (*sreset_reset_value)(_adapter *padapter); ++ void (*silentreset)(_adapter *padapter); ++ void (*sreset_xmit_status_check)(_adapter *padapter); ++ void (*sreset_linked_status_check) (_adapter *padapter); ++ u8 (*sreset_get_wifi_status)(_adapter *padapter); ++ bool (*sreset_inprogress)(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_IOL ++ int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++ s32 (*xmit_thread_handler)(_adapter *padapter); ++#endif ++ void (*hal_notch_filter)(_adapter * adapter, bool enable); ++ void (*hal_reset_security_engine)(_adapter * adapter); ++ s32 (*c2h_handler)(_adapter *padapter, struct c2h_evt_hdr *c2h_evt); ++ c2h_id_filter c2h_id_filter_ccx; ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ void (*hal_init_checkbthang_workqueue)(_adapter * padapter); ++ void (*hal_free_checkbthang_workqueue)(_adapter * padapter); ++ void (*hal_cancel_checkbthang_workqueue)(_adapter * padapter); ++ void (*hal_checke_bt_hang)(_adapter * padapter); ++#endif ++}; ++ ++typedef enum _RT_EEPROM_TYPE{ ++ EEPROM_93C46, ++ EEPROM_93C56, ++ EEPROM_BOOT_EFUSE, ++}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE; ++ ++ ++ ++#define RF_CHANGE_BY_INIT 0 ++#define RF_CHANGE_BY_IPS BIT28 ++#define RF_CHANGE_BY_PS BIT29 ++#define RF_CHANGE_BY_HW BIT30 ++#define RF_CHANGE_BY_SW BIT31 ++ ++typedef enum _HARDWARE_TYPE{ ++ HARDWARE_TYPE_RTL8180, ++ HARDWARE_TYPE_RTL8185, ++ HARDWARE_TYPE_RTL8187, ++ HARDWARE_TYPE_RTL8188, ++ HARDWARE_TYPE_RTL8190P, ++ HARDWARE_TYPE_RTL8192E, ++ HARDWARE_TYPE_RTL819xU, ++ HARDWARE_TYPE_RTL8192SE, ++ HARDWARE_TYPE_RTL8192SU, ++ HARDWARE_TYPE_RTL8192CE, ++ HARDWARE_TYPE_RTL8192CU, ++ HARDWARE_TYPE_RTL8192DE, ++ HARDWARE_TYPE_RTL8192DU, ++ HARDWARE_TYPE_RTL8723AE, ++ HARDWARE_TYPE_RTL8723AU, ++ HARDWARE_TYPE_RTL8723AS, ++ HARDWARE_TYPE_RTL8188EE, ++ HARDWARE_TYPE_RTL8188EU, ++ HARDWARE_TYPE_RTL8188ES, ++ HARDWARE_TYPE_MAX, ++}HARDWARE_TYPE; ++ ++// ++// RTL8192C Series ++// ++#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE) ++#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU) ++#define IS_HARDWARE_TYPE_8192C(_Adapter) \ ++(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter)) ++ ++// ++// RTL8192D Series ++// ++#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE) ++#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU) ++#define IS_HARDWARE_TYPE_8192D(_Adapter) \ ++(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter)) ++ ++// ++// RTL8723A Series ++// ++#define IS_HARDWARE_TYPE_8723AE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE) ++#define IS_HARDWARE_TYPE_8723AU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU) ++#define IS_HARDWARE_TYPE_8723AS(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS) ++#define IS_HARDWARE_TYPE_8723A(_Adapter) \ ++(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter)) ++ ++// ++// RTL8188E Series ++// ++#define IS_HARDWARE_TYPE_8188EE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE) ++#define IS_HARDWARE_TYPE_8188EU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU) ++#define IS_HARDWARE_TYPE_8188ES(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES) ++#define IS_HARDWARE_TYPE_8188E(_Adapter) \ ++(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter)) ++ ++ ++typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV; ++#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv) ++#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) ++ ++#ifdef CONFIG_WOWLAN ++typedef enum _wowlan_subcode{ ++ WOWLAN_PATTERN_MATCH = 1, ++ WOWLAN_MAGIC_PACKET = 2, ++ WOWLAN_UNICAST = 3, ++ WOWLAN_SET_PATTERN = 4, ++ WOWLAN_DUMP_REG = 5, ++ WOWLAN_ENABLE = 6, ++ WOWLAN_DISABLE = 7, ++ WOWLAN_STATUS = 8, ++ WOWLAN_DEBUG_RELOAD_FW = 9, ++ WOWLAN_DEBUG_1 =10, ++ WOWLAN_DEBUG_2 =11 ++}wowlan_subcode; ++ ++struct wowlan_ioctl_param{ ++ unsigned int subcode; ++ unsigned int subcode_value; ++ unsigned int wakeup_reason; ++ unsigned int len; ++ unsigned char pattern[0]; ++}; ++ ++#define Rx_Pairwisekey 0x01 ++#define Rx_GTK 0x02 ++#define Rx_DisAssoc 0x04 ++#define Rx_DeAuth 0x08 ++#define FWDecisionDisconnect 0x10 ++#define Rx_MagicPkt 0x21 ++#define Rx_UnicastPkt 0x22 ++#define Rx_PatternPkt 0x23 ++#endif // CONFIG_WOWLAN ++ ++void rtw_hal_def_value_init(_adapter *padapter); ++ ++void rtw_hal_free_data(_adapter *padapter); ++ ++void rtw_hal_dm_init(_adapter *padapter); ++void rtw_hal_dm_deinit(_adapter *padapter); ++void rtw_hal_sw_led_init(_adapter *padapter); ++void rtw_hal_sw_led_deinit(_adapter *padapter); ++ ++u32 rtw_hal_power_on(_adapter *padapter); ++void rtw_hal_power_off(_adapter *padapter); ++uint rtw_hal_init(_adapter *padapter); ++uint rtw_hal_deinit(_adapter *padapter); ++void rtw_hal_stop(_adapter *padapter); ++void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); ++void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); ++ ++void rtw_hal_chip_configure(_adapter *padapter); ++void rtw_hal_read_chip_info(_adapter *padapter); ++void rtw_hal_read_chip_version(_adapter *padapter); ++ ++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++ ++void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); ++void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); ++ ++void rtw_hal_enable_interrupt(_adapter *padapter); ++void rtw_hal_disable_interrupt(_adapter *padapter); ++ ++u32 rtw_hal_inirp_init(_adapter *padapter); ++u32 rtw_hal_inirp_deinit(_adapter *padapter); ++ ++u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val); ++ ++s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtw_hal_init_xmit_priv(_adapter *padapter); ++void rtw_hal_free_xmit_priv(_adapter *padapter); ++ ++s32 rtw_hal_init_recv_priv(_adapter *padapter); ++void rtw_hal_free_recv_priv(_adapter *padapter); ++ ++void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level); ++void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level); ++ ++void rtw_hal_start_thread(_adapter *padapter); ++void rtw_hal_stop_thread(_adapter *padapter); ++ ++void rtw_hal_bcn_related_reg_setting(_adapter *padapter); ++ ++u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); ++void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); ++u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); ++void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); ++ ++s32 rtw_hal_interrupt_handler(_adapter *padapter); ++ ++void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset); ++void rtw_hal_set_chan(_adapter *padapter, u8 channel); ++void rtw_hal_dm_watchdog(_adapter *padapter); ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++u8 rtw_hal_antdiv_before_linked(_adapter *padapter); ++void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); ++#endif ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++void rtw_hal_sreset_init(_adapter *padapter); ++void rtw_hal_sreset_reset(_adapter *padapter); ++void rtw_hal_sreset_reset_value(_adapter *padapter); ++void rtw_hal_sreset_xmit_status_check(_adapter *padapter); ++void rtw_hal_sreset_linked_status_check (_adapter *padapter); ++u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); ++bool rtw_hal_sreset_inprogress(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_IOL ++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++s32 rtw_hal_xmit_thread_handler(_adapter *padapter); ++#endif ++ ++void rtw_hal_notch_filter(_adapter * adapter, bool enable); ++void rtw_hal_reset_security_engine(_adapter * adapter); ++ ++s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt); ++c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter); ++ ++#endif //__HAL_INTF_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211.h b/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211.h +new file mode 100644 +index 00000000..422c47ab +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211.h +@@ -0,0 +1,1589 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IEEE80211_H ++#define __IEEE80211_H ++ ++ ++#ifndef CONFIG_RTL8711FW ++ ++ #include ++ #include ++ #include ++ #include "wifi.h" ++ ++ #if defined PLATFORM_OS_XP ++ #include ++ #endif ++ #if defined PLATFORM_LINUX ++ #include ++ #endif ++#else ++ ++ #include ++ ++#endif ++ ++#define MGMT_QUEUE_NUM 5 ++ ++#define ETH_ALEN 6 ++#define ETH_TYPE_LEN 2 ++#define PAYLOAD_TYPE_LEN 1 ++ ++#ifdef CONFIG_AP_MODE ++ ++#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) ++ ++/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ ++enum { ++ RTL871X_HOSTAPD_FLUSH = 1, ++ RTL871X_HOSTAPD_ADD_STA = 2, ++ RTL871X_HOSTAPD_REMOVE_STA = 3, ++ RTL871X_HOSTAPD_GET_INFO_STA = 4, ++ /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ ++ RTL871X_HOSTAPD_GET_WPAIE_STA = 5, ++ RTL871X_SET_ENCRYPTION = 6, ++ RTL871X_GET_ENCRYPTION = 7, ++ RTL871X_HOSTAPD_SET_FLAGS_STA = 8, ++ RTL871X_HOSTAPD_GET_RID = 9, ++ RTL871X_HOSTAPD_SET_RID = 10, ++ RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, ++ RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, ++ RTL871X_HOSTAPD_MLME = 13, ++ RTL871X_HOSTAPD_SCAN_REQ = 14, ++ RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, ++ RTL871X_HOSTAPD_SET_BEACON=16, ++ RTL871X_HOSTAPD_SET_WPS_BEACON = 17, ++ RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, ++ RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, ++ RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, ++ RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, ++ RTL871X_HOSTAPD_ACL_ADD_STA = 22, ++ RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, ++}; ++ ++/* STA flags */ ++#define WLAN_STA_AUTH BIT(0) ++#define WLAN_STA_ASSOC BIT(1) ++#define WLAN_STA_PS BIT(2) ++#define WLAN_STA_TIM BIT(3) ++#define WLAN_STA_PERM BIT(4) ++#define WLAN_STA_AUTHORIZED BIT(5) ++#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ ++#define WLAN_STA_SHORT_PREAMBLE BIT(7) ++#define WLAN_STA_PREAUTH BIT(8) ++#define WLAN_STA_WME BIT(9) ++#define WLAN_STA_MFP BIT(10) ++#define WLAN_STA_HT BIT(11) ++#define WLAN_STA_WPS BIT(12) ++#define WLAN_STA_MAYBE_WPS BIT(13) ++#define WLAN_STA_NONERP BIT(31) ++ ++#endif ++ ++#define IEEE_CMD_SET_WPA_PARAM 1 ++#define IEEE_CMD_SET_WPA_IE 2 ++#define IEEE_CMD_SET_ENCRYPTION 3 ++#define IEEE_CMD_MLME 4 ++ ++#define IEEE_PARAM_WPA_ENABLED 1 ++#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 ++#define IEEE_PARAM_DROP_UNENCRYPTED 3 ++#define IEEE_PARAM_PRIVACY_INVOKED 4 ++#define IEEE_PARAM_AUTH_ALGS 5 ++#define IEEE_PARAM_IEEE_802_1X 6 ++#define IEEE_PARAM_WPAX_SELECT 7 ++ ++#define AUTH_ALG_OPEN_SYSTEM 0x1 ++#define AUTH_ALG_SHARED_KEY 0x2 ++#define AUTH_ALG_LEAP 0x00000004 ++ ++#define IEEE_MLME_STA_DEAUTH 1 ++#define IEEE_MLME_STA_DISASSOC 2 ++ ++#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 ++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 ++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 ++#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 ++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 ++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 ++ ++ ++#define IEEE_CRYPT_ALG_NAME_LEN 16 ++ ++#define WPA_CIPHER_NONE BIT(0) ++#define WPA_CIPHER_WEP40 BIT(1) ++#define WPA_CIPHER_WEP104 BIT(2) ++#define WPA_CIPHER_TKIP BIT(3) ++#define WPA_CIPHER_CCMP BIT(4) ++ ++ ++ ++#define WPA_SELECTOR_LEN 4 ++extern u8 RTW_WPA_OUI_TYPE[] ; ++extern u16 RTW_WPA_VERSION ; ++extern u8 WPA_AUTH_KEY_MGMT_NONE[]; ++extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; ++extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; ++extern u8 WPA_CIPHER_SUITE_NONE[]; ++extern u8 WPA_CIPHER_SUITE_WEP40[]; ++extern u8 WPA_CIPHER_SUITE_TKIP[]; ++extern u8 WPA_CIPHER_SUITE_WRAP[]; ++extern u8 WPA_CIPHER_SUITE_CCMP[]; ++extern u8 WPA_CIPHER_SUITE_WEP104[]; ++ ++ ++#define RSN_HEADER_LEN 4 ++#define RSN_SELECTOR_LEN 4 ++ ++extern u16 RSN_VERSION_BSD; ++extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[]; ++extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; ++extern u8 RSN_CIPHER_SUITE_NONE[]; ++extern u8 RSN_CIPHER_SUITE_WEP40[]; ++extern u8 RSN_CIPHER_SUITE_TKIP[]; ++extern u8 RSN_CIPHER_SUITE_WRAP[]; ++extern u8 RSN_CIPHER_SUITE_CCMP[]; ++extern u8 RSN_CIPHER_SUITE_WEP104[]; ++ ++typedef enum _RATR_TABLE_MODE{ ++ RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS ++ RATR_INX_WIRELESS_NG = 1, // GN or N ++ RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN ++ RATR_INX_WIRELESS_N = 3, ++ RATR_INX_WIRELESS_GB = 4, ++ RATR_INX_WIRELESS_G = 5, ++ RATR_INX_WIRELESS_B = 6, ++ RATR_INX_WIRELESS_MC = 7, ++ RATR_INX_WIRELESS_AC_N = 8, ++}RATR_TABLE_MODE, *PRATR_TABLE_MODE; ++ ++enum NETWORK_TYPE ++{ ++ WIRELESS_INVALID = 0, ++ //Sub-Element ++ WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck ++ WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm ++ WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only ++ WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck ++ WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only ++ //WIRELESS_AUTO = BIT(5), ++ WIRELESS_AC = BIT(6), ++ ++ //Combination ++ WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm ++ WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm ++ WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only ++ WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck ++ WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only ++ WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), ++}; ++ ++#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) ++#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N) ++ ++#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) ++#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) ++ ++#define IsEnableHWCCK(NetType) IsSupported24G(NetType) ++#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) ++ ++#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) ++#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) ++#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType) ++ ++#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) ++#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE) ++#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE) ++ ++ ++typedef struct ieee_param { ++ u32 cmd; ++ u8 sta_addr[ETH_ALEN]; ++ union { ++ struct { ++ u8 name; ++ u32 value; ++ } wpa_param; ++ struct { ++ u32 len; ++ u8 reserved[32]; ++ u8 data[0]; ++ } wpa_ie; ++ struct{ ++ int command; ++ int reason_code; ++ } mlme; ++ struct { ++ u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; ++ u8 set_tx; ++ u32 err; ++ u8 idx; ++ u8 seq[8]; /* sequence counter (set: RX, get: TX) */ ++ u16 key_len; ++ u8 key[0]; ++ } crypt; ++#ifdef CONFIG_AP_MODE ++ struct { ++ u16 aid; ++ u16 capability; ++ int flags; ++ u8 tx_supp_rates[16]; ++ struct rtw_ieee80211_ht_cap ht_cap; ++ } add_sta; ++ struct { ++ u8 reserved[2];//for set max_num_sta ++ u8 buf[0]; ++ } bcn_ie; ++#endif ++ ++ } u; ++}ieee_param; ++ ++#ifdef CONFIG_AP_MODE ++typedef struct ieee_param_ex { ++ u32 cmd; ++ u8 sta_addr[ETH_ALEN]; ++ u8 data[0]; ++}ieee_param_ex; ++ ++struct sta_data{ ++ u16 aid; ++ u16 capability; ++ int flags; ++ u32 sta_set; ++ u8 tx_supp_rates[16]; ++ u32 tx_supp_rates_len; ++ struct rtw_ieee80211_ht_cap ht_cap; ++ u64 rx_pkts; ++ u64 rx_bytes; ++ u64 rx_drops; ++ u64 tx_pkts; ++ u64 tx_bytes; ++ u64 tx_drops; ++}; ++#endif ++ ++ ++#if WIRELESS_EXT < 17 ++#define IW_QUAL_QUAL_INVALID 0x10 ++#define IW_QUAL_LEVEL_INVALID 0x20 ++#define IW_QUAL_NOISE_INVALID 0x40 ++#define IW_QUAL_QUAL_UPDATED 0x1 ++#define IW_QUAL_LEVEL_UPDATED 0x2 ++#define IW_QUAL_NOISE_UPDATED 0x4 ++#endif ++ ++#define IEEE80211_DATA_LEN 2304 ++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section ++ 6.2.1.1.2. ++ ++ The figure in section 7.1.2 suggests a body size of up to 2312 ++ bytes is allowed, which is a bit confusing, I suspect this ++ represents the 2304 bytes of real data, plus a possible 8 bytes of ++ WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ ++ ++ ++#define IEEE80211_HLEN 30 ++#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) ++ ++ ++/* this is stolen from ipw2200 driver */ ++#define IEEE_IBSS_MAC_HASH_SIZE 31 ++ ++struct ieee_ibss_seq { ++ u8 mac[ETH_ALEN]; ++ u16 seq_num; ++ u16 frag_num; ++ unsigned long packet_time; ++ _list list; ++}; ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD) ++ ++struct rtw_ieee80211_hdr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++} __attribute__ ((packed)); ++ ++struct rtw_ieee80211_hdr_3addr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++} __attribute__ ((packed)); ++ ++ ++struct rtw_ieee80211_hdr_qos { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u16 qc; ++} __attribute__ ((packed)); ++ ++struct rtw_ieee80211_hdr_3addr_qos { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u16 qc; ++} __attribute__ ((packed)); ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++} __attribute__ ((packed)); ++ ++#endif ++ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct rtw_ieee80211_hdr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++}; ++ ++struct rtw_ieee80211_hdr_3addr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++}; ++ ++ ++struct rtw_ieee80211_hdr_qos { ++ struct rtw_ieee80211_hdr wlan_hdr; ++ u16 qc; ++}; ++ ++struct rtw_ieee80211_hdr_3addr_qos { ++ struct rtw_ieee80211_hdr_3addr wlan_hdr; ++ u16 qc; ++}; ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++}; ++#pragma pack() ++ ++#endif ++ ++ ++ ++enum eap_type { ++ EAP_PACKET = 0, ++ EAPOL_START, ++ EAPOL_LOGOFF, ++ EAPOL_KEY, ++ EAPOL_ENCAP_ASF_ALERT ++}; ++ ++#define IEEE80211_3ADDR_LEN 24 ++#define IEEE80211_4ADDR_LEN 30 ++#define IEEE80211_FCS_LEN 4 ++ ++#define MIN_FRAG_THRESHOLD 256U ++#define MAX_FRAG_THRESHOLD 2346U ++ ++/* Frame control field constants */ ++#define RTW_IEEE80211_FCTL_VERS 0x0003 ++#define RTW_IEEE80211_FCTL_FTYPE 0x000c ++#define RTW_IEEE80211_FCTL_STYPE 0x00f0 ++#define RTW_IEEE80211_FCTL_TODS 0x0100 ++#define RTW_IEEE80211_FCTL_FROMDS 0x0200 ++#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 ++#define RTW_IEEE80211_FCTL_RETRY 0x0800 ++#define RTW_IEEE80211_FCTL_PM 0x1000 ++#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 ++#define RTW_IEEE80211_FCTL_PROTECTED 0x4000 ++#define RTW_IEEE80211_FCTL_ORDER 0x8000 ++#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00 ++ ++#define RTW_IEEE80211_FTYPE_MGMT 0x0000 ++#define RTW_IEEE80211_FTYPE_CTL 0x0004 ++#define RTW_IEEE80211_FTYPE_DATA 0x0008 ++#define RTW_IEEE80211_FTYPE_EXT 0x000c ++ ++/* management */ ++#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 ++#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 ++#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 ++#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 ++#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 ++#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 ++#define RTW_IEEE80211_STYPE_BEACON 0x0080 ++#define RTW_IEEE80211_STYPE_ATIM 0x0090 ++#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 ++#define RTW_IEEE80211_STYPE_AUTH 0x00B0 ++#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 ++#define RTW_IEEE80211_STYPE_ACTION 0x00D0 ++ ++/* control */ ++#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 ++#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 ++#define RTW_IEEE80211_STYPE_BACK 0x0090 ++#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 ++#define RTW_IEEE80211_STYPE_RTS 0x00B0 ++#define RTW_IEEE80211_STYPE_CTS 0x00C0 ++#define RTW_IEEE80211_STYPE_ACK 0x00D0 ++#define RTW_IEEE80211_STYPE_CFEND 0x00E0 ++#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 ++ ++/* data */ ++#define RTW_IEEE80211_STYPE_DATA 0x0000 ++#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 ++#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 ++#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 ++#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 ++#define RTW_IEEE80211_STYPE_CFACK 0x0050 ++#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 ++#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 ++#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 ++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 ++#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 ++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0 ++#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0 ++#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0 ++#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0 ++#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0 ++ ++/* sequence control field */ ++#define RTW_IEEE80211_SCTL_FRAG 0x000F ++#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 ++ ++ ++#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) ++#define RTW_ERP_INFO_USE_PROTECTION BIT(1) ++#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) ++ ++/* QoS,QOS */ ++#define NORMAL_ACK 0 ++#define NO_ACK 1 ++#define NON_EXPLICIT_ACK 2 ++#define BLOCK_ACK 3 ++ ++#ifndef ETH_P_PAE ++#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ ++#endif /* ETH_P_PAE */ ++ ++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ ++ ++#define ETH_P_ECONET 0x0018 ++ ++#ifndef ETH_P_80211_RAW ++#define ETH_P_80211_RAW (ETH_P_ECONET + 1) ++#endif ++ ++/* IEEE 802.11 defines */ ++ ++#define P80211_OUI_LEN 3 ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD) ++ ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++}; ++#pragma pack() ++ ++#endif ++ ++ ++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) ++ ++#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) ++#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) ++ ++#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) ++ ++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) ++#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) ++ ++/* Authentication algorithms */ ++#define WLAN_AUTH_OPEN 0 ++#define WLAN_AUTH_SHARED_KEY 1 ++ ++#define WLAN_AUTH_CHALLENGE_LEN 128 ++ ++#define WLAN_CAPABILITY_BSS (1<<0) ++#define WLAN_CAPABILITY_IBSS (1<<1) ++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) ++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) ++#define WLAN_CAPABILITY_PRIVACY (1<<4) ++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) ++#define WLAN_CAPABILITY_PBCC (1<<6) ++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) ++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) ++ ++/* Status codes */ ++#define WLAN_STATUS_SUCCESS 0 ++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 ++#define WLAN_STATUS_CAPS_UNSUPPORTED 10 ++#define WLAN_STATUS_REASSOC_NO_ASSOC 11 ++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 ++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 ++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 ++#define WLAN_STATUS_CHALLENGE_FAIL 15 ++#define WLAN_STATUS_AUTH_TIMEOUT 16 ++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 ++#define WLAN_STATUS_ASSOC_DENIED_RATES 18 ++/* 802.11b */ ++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 ++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 ++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 ++ ++/* Reason codes */ ++#define WLAN_REASON_UNSPECIFIED 1 ++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 ++#define WLAN_REASON_DEAUTH_LEAVING 3 ++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 ++#define WLAN_REASON_DISASSOC_AP_BUSY 5 ++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 ++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 ++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 ++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 ++#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 ++#define WLAN_REASON_EXPIRATION_CHK 65535 ++ ++/* Information Element IDs */ ++#define WLAN_EID_SSID 0 ++#define WLAN_EID_SUPP_RATES 1 ++#define WLAN_EID_FH_PARAMS 2 ++#define WLAN_EID_DS_PARAMS 3 ++#define WLAN_EID_CF_PARAMS 4 ++#define WLAN_EID_TIM 5 ++#define WLAN_EID_IBSS_PARAMS 6 ++#define WLAN_EID_CHALLENGE 16 ++/* EIDs defined by IEEE 802.11h - START */ ++#define WLAN_EID_PWR_CONSTRAINT 32 ++#define WLAN_EID_PWR_CAPABILITY 33 ++#define WLAN_EID_TPC_REQUEST 34 ++#define WLAN_EID_TPC_REPORT 35 ++#define WLAN_EID_SUPPORTED_CHANNELS 36 ++#define WLAN_EID_CHANNEL_SWITCH 37 ++#define WLAN_EID_MEASURE_REQUEST 38 ++#define WLAN_EID_MEASURE_REPORT 39 ++#define WLAN_EID_QUITE 40 ++#define WLAN_EID_IBSS_DFS 41 ++/* EIDs defined by IEEE 802.11h - END */ ++#define WLAN_EID_ERP_INFO 42 ++#define WLAN_EID_HT_CAP 45 ++#define WLAN_EID_RSN 48 ++#define WLAN_EID_EXT_SUPP_RATES 50 ++#define WLAN_EID_MOBILITY_DOMAIN 54 ++#define WLAN_EID_FAST_BSS_TRANSITION 55 ++#define WLAN_EID_TIMEOUT_INTERVAL 56 ++#define WLAN_EID_RIC_DATA 57 ++#define WLAN_EID_HT_OPERATION 61 ++#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 ++#define WLAN_EID_20_40_BSS_COEXISTENCE 72 ++#define WLAN_EID_20_40_BSS_INTOLERANT 73 ++#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 ++#define WLAN_EID_MMIE 76 ++#define WLAN_EID_VENDOR_SPECIFIC 221 ++#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) ++ ++#define IEEE80211_MGMT_HDR_LEN 24 ++#define IEEE80211_DATA_HDR3_LEN 24 ++#define IEEE80211_DATA_HDR4_LEN 30 ++ ++ ++#define IEEE80211_STATMASK_SIGNAL (1<<0) ++#define IEEE80211_STATMASK_RSSI (1<<1) ++#define IEEE80211_STATMASK_NOISE (1<<2) ++#define IEEE80211_STATMASK_RATE (1<<3) ++#define IEEE80211_STATMASK_WEMASK 0x7 ++ ++ ++#define IEEE80211_CCK_MODULATION (1<<0) ++#define IEEE80211_OFDM_MODULATION (1<<1) ++ ++#define IEEE80211_24GHZ_BAND (1<<0) ++#define IEEE80211_52GHZ_BAND (1<<1) ++ ++#define IEEE80211_CCK_RATE_LEN 4 ++#define IEEE80211_NUM_OFDM_RATESLEN 8 ++ ++ ++#define IEEE80211_CCK_RATE_1MB 0x02 ++#define IEEE80211_CCK_RATE_2MB 0x04 ++#define IEEE80211_CCK_RATE_5MB 0x0B ++#define IEEE80211_CCK_RATE_11MB 0x16 ++#define IEEE80211_OFDM_RATE_LEN 8 ++#define IEEE80211_OFDM_RATE_6MB 0x0C ++#define IEEE80211_OFDM_RATE_9MB 0x12 ++#define IEEE80211_OFDM_RATE_12MB 0x18 ++#define IEEE80211_OFDM_RATE_18MB 0x24 ++#define IEEE80211_OFDM_RATE_24MB 0x30 ++#define IEEE80211_OFDM_RATE_36MB 0x48 ++#define IEEE80211_OFDM_RATE_48MB 0x60 ++#define IEEE80211_OFDM_RATE_54MB 0x6C ++#define IEEE80211_BASIC_RATE_MASK 0x80 ++ ++#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) ++#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) ++#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) ++#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) ++#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) ++#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) ++#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) ++#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) ++#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) ++#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) ++#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) ++#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) ++ ++#define IEEE80211_CCK_RATES_MASK 0x0000000F ++#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ ++ IEEE80211_CCK_RATE_2MB_MASK) ++#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ ++ IEEE80211_CCK_RATE_5MB_MASK | \ ++ IEEE80211_CCK_RATE_11MB_MASK) ++ ++#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 ++#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ ++ IEEE80211_OFDM_RATE_12MB_MASK | \ ++ IEEE80211_OFDM_RATE_24MB_MASK) ++#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ ++ IEEE80211_OFDM_RATE_9MB_MASK | \ ++ IEEE80211_OFDM_RATE_18MB_MASK | \ ++ IEEE80211_OFDM_RATE_36MB_MASK | \ ++ IEEE80211_OFDM_RATE_48MB_MASK | \ ++ IEEE80211_OFDM_RATE_54MB_MASK) ++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ ++ IEEE80211_CCK_DEFAULT_RATES_MASK) ++ ++#define IEEE80211_NUM_OFDM_RATES 8 ++#define IEEE80211_NUM_CCK_RATES 4 ++#define IEEE80211_OFDM_SHIFT_MASK_A 4 ++ ++ ++ ++ ++/* NOTE: This data is for statistical purposes; not all hardware provides this ++ * information for frames received. Not setting these will not cause ++ * any adverse affects. */ ++struct ieee80211_rx_stats { ++ //u32 mac_time[2]; ++ s8 rssi; ++ u8 signal; ++ u8 noise; ++ u8 received_channel; ++ u16 rate; /* in 100 kbps */ ++ //u8 control; ++ u8 mask; ++ u8 freq; ++ u16 len; ++}; ++ ++/* IEEE 802.11 requires that STA supports concurrent reception of at least ++ * three fragmented frames. This define can be increased to support more ++ * concurrent frames, but it should be noted that each entry can consume about ++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ ++#define IEEE80211_FRAG_CACHE_LEN 4 ++ ++struct ieee80211_frag_entry { ++ u32 first_frag_time; ++ uint seq; ++ uint last_frag; ++ uint qos; //jackson ++ uint tid; //jackson ++ struct sk_buff *skb; ++ u8 src_addr[ETH_ALEN]; ++ u8 dst_addr[ETH_ALEN]; ++}; ++ ++#ifndef PLATFORM_FREEBSD //Baron BSD has already defined ++struct ieee80211_stats { ++ uint tx_unicast_frames; ++ uint tx_multicast_frames; ++ uint tx_fragments; ++ uint tx_unicast_octets; ++ uint tx_multicast_octets; ++ uint tx_deferred_transmissions; ++ uint tx_single_retry_frames; ++ uint tx_multiple_retry_frames; ++ uint tx_retry_limit_exceeded; ++ uint tx_discards; ++ uint rx_unicast_frames; ++ uint rx_multicast_frames; ++ uint rx_fragments; ++ uint rx_unicast_octets; ++ uint rx_multicast_octets; ++ uint rx_fcs_errors; ++ uint rx_discards_no_buffer; ++ uint tx_discards_wrong_sa; ++ uint rx_discards_undecryptable; ++ uint rx_message_in_msg_fragments; ++ uint rx_message_in_bad_msg_fragments; ++}; ++#endif //PLATFORM_FREEBSD ++struct ieee80211_softmac_stats{ ++ uint rx_ass_ok; ++ uint rx_ass_err; ++ uint rx_probe_rq; ++ uint tx_probe_rs; ++ uint tx_beacons; ++ uint rx_auth_rq; ++ uint rx_auth_rs_ok; ++ uint rx_auth_rs_err; ++ uint tx_auth_rq; ++ uint no_auth_rs; ++ uint no_ass_rs; ++ uint tx_ass_rq; ++ uint rx_ass_rq; ++ uint tx_probe_rq; ++ uint reassoc; ++ uint swtxstop; ++ uint swtxawake; ++}; ++ ++#define SEC_KEY_1 (1<<0) ++#define SEC_KEY_2 (1<<1) ++#define SEC_KEY_3 (1<<2) ++#define SEC_KEY_4 (1<<3) ++#define SEC_ACTIVE_KEY (1<<4) ++#define SEC_AUTH_MODE (1<<5) ++#define SEC_UNICAST_GROUP (1<<6) ++#define SEC_LEVEL (1<<7) ++#define SEC_ENABLED (1<<8) ++ ++#define SEC_LEVEL_0 0 /* None */ ++#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ ++#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ ++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ ++#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ ++ ++#define WEP_KEYS 4 ++#define WEP_KEY_LEN 13 ++ ++#ifdef CONFIG_IEEE80211W ++#define BIP_MAX_KEYID 5 ++#define BIP_AAD_SIZE 20 ++#endif //CONFIG_IEEE80211W ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][WEP_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][WEP_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} ; ++#pragma pack() ++ ++#endif ++ ++/* ++ ++ 802.11 data frame from AP ++ ++ ,-------------------------------------------------------------------. ++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | ++ |------|------|---------|---------|---------|------|---------|------| ++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | ++ | | tion | (BSSID) | | | ence | data | | ++ `-------------------------------------------------------------------' ++ ++Total: 28-2340 bytes ++ ++*/ ++ ++struct ieee80211_header_data { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[6]; ++ u8 addr2[6]; ++ u8 addr3[6]; ++ u16 seq_ctrl; ++}; ++ ++#define BEACON_PROBE_SSID_ID_POSITION 12 ++ ++/* Management Frame Information Element Types */ ++#define MFIE_TYPE_SSID 0 ++#define MFIE_TYPE_RATES 1 ++#define MFIE_TYPE_FH_SET 2 ++#define MFIE_TYPE_DS_SET 3 ++#define MFIE_TYPE_CF_SET 4 ++#define MFIE_TYPE_TIM 5 ++#define MFIE_TYPE_IBSS_SET 6 ++#define MFIE_TYPE_CHALLENGE 16 ++#define MFIE_TYPE_ERP 42 ++#define MFIE_TYPE_RSN 48 ++#define MFIE_TYPE_RATES_EX 50 ++#define MFIE_TYPE_GENERIC 221 ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} __attribute__ ((packed)); ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} __attribute__ ((packed)); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} ; ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} ; ++#pragma pack() ++ ++#endif ++ ++ ++/* ++ * These are the data types that can make up management packets ++ * ++ u16 auth_algorithm; ++ u16 auth_sequence; ++ u16 beacon_interval; ++ u16 capability; ++ u8 current_ap[ETH_ALEN]; ++ u16 listen_interval; ++ struct { ++ u16 association_id:14, reserved:2; ++ } __attribute__ ((packed)); ++ u32 time_stamp[2]; ++ u16 reason; ++ u16 status; ++*/ ++ ++#define IEEE80211_DEFAULT_TX_ESSID "Penguin" ++#define IEEE80211_DEFAULT_BASIC_RATE 10 ++ ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++ ++struct ieee80211_authentication { ++ struct ieee80211_header_data header; ++ u16 algorithm; ++ u16 transaction; ++ u16 status; ++ //struct ieee80211_info_element_hdr info_element; ++} __attribute__ ((packed)); ++ ++ ++struct ieee80211_probe_response { ++ struct ieee80211_header_data header; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 capability; ++ struct ieee80211_info_element info_element; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_request { ++ struct ieee80211_header_data header; ++ /*struct ieee80211_info_element info_element;*/ ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_request_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 listen_interval; ++ //u8 current_ap[ETH_ALEN]; ++ struct ieee80211_info_element_hdr info_element; ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_response_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 status; ++ u16 aid; ++// struct ieee80211_info_element info_element; /* supported rates */ ++} __attribute__ ((packed)); ++#endif ++ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct ieee80211_authentication { ++ struct ieee80211_header_data header; ++ u16 algorithm; ++ u16 transaction; ++ u16 status; ++ //struct ieee80211_info_element_hdr info_element; ++} ; ++ ++ ++struct ieee80211_probe_response { ++ struct ieee80211_header_data header; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 capability; ++ struct ieee80211_info_element info_element; ++} ; ++ ++struct ieee80211_probe_request { ++ struct ieee80211_header_data header; ++ /*struct ieee80211_info_element info_element;*/ ++} ; ++ ++struct ieee80211_assoc_request_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 listen_interval; ++ //u8 current_ap[ETH_ALEN]; ++ struct ieee80211_info_element_hdr info_element; ++} ; ++ ++struct ieee80211_assoc_response_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 status; ++ u16 aid; ++// struct ieee80211_info_element info_element; /* supported rates */ ++}; ++ ++#pragma pack() ++ ++#endif ++ ++ ++ ++ ++struct ieee80211_txb { ++ u8 nr_frags; ++ u8 encrypted; ++ u16 reserved; ++ u16 frag_size; ++ u16 payload_size; ++ struct sk_buff *fragments[0]; ++}; ++ ++ ++/* SWEEP TABLE ENTRIES NUMBER*/ ++#define MAX_SWEEP_TAB_ENTRIES 42 ++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 ++/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs ++ * only use 8, and then use extended rates for the remaining supported ++ * rates. Other APs, however, stick all of their supported rates on the ++ * main rates information element... */ ++#define MAX_RATES_LENGTH ((u8)12) ++#define MAX_RATES_EX_LENGTH ((u8)16) ++#define MAX_NETWORK_COUNT 128 ++#define MAX_CHANNEL_NUMBER 161 ++#define IEEE80211_SOFTMAC_SCAN_TIME 400 ++//(HZ / 2) ++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) ++ ++#define CRC_LENGTH 4U ++ ++#define MAX_WPA_IE_LEN (256) ++#define MAX_WPS_IE_LEN (512) ++#define MAX_P2P_IE_LEN (256) ++#define MAX_WFD_IE_LEN (128) ++ ++#define NETWORK_EMPTY_ESSID (1<<0) ++#define NETWORK_HAS_OFDM (1<<1) ++#define NETWORK_HAS_CCK (1<<2) ++ ++#define IEEE80211_DTIM_MBCAST 4 ++#define IEEE80211_DTIM_UCAST 2 ++#define IEEE80211_DTIM_VALID 1 ++#define IEEE80211_DTIM_INVALID 0 ++ ++#define IEEE80211_PS_DISABLED 0 ++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST ++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST ++#define IW_ESSID_MAX_SIZE 32 ++#if 0 ++struct ieee80211_network { ++ /* These entries are used to identify a unique network */ ++ u8 bssid[ETH_ALEN]; ++ u8 channel; ++ /* Ensure null-terminated for any debug msgs */ ++ u8 ssid[IW_ESSID_MAX_SIZE + 1]; ++ u8 ssid_len; ++ u8 rssi; //relative signal strength ++ u8 sq; //signal quality ++ ++ /* These are network statistics */ ++ //struct ieee80211_rx_stats stats; ++ u16 capability; ++ u16 aid; ++ u8 rates[MAX_RATES_LENGTH]; ++ u8 rates_len; ++ u8 rates_ex[MAX_RATES_EX_LENGTH]; ++ u8 rates_ex_len; ++ ++ u8 edca_parmsets[18]; ++ ++ u8 mode; ++ u8 flags; ++ u8 time_stamp[8]; ++ u16 beacon_interval; ++ u16 listen_interval; ++ u16 atim_window; ++ u8 wpa_ie[MAX_WPA_IE_LEN]; ++ size_t wpa_ie_len; ++ u8 rsn_ie[MAX_WPA_IE_LEN]; ++ size_t rsn_ie_len; ++ u8 country[6]; ++ u8 dtim_period; ++ u8 dtim_data; ++ u8 power_constraint; ++ u8 qosinfo; ++ u8 qbssload[5]; ++ u8 network_type; ++ int join_res; ++ unsigned long last_scanned; ++}; ++#endif ++/* ++join_res: ++-1: authentication fail ++-2: association fail ++> 0: TID ++*/ ++ ++#ifndef PLATFORM_FREEBSD //Baron BSD has already defined ++ ++enum ieee80211_state { ++ ++ /* the card is not linked at all */ ++ IEEE80211_NOLINK = 0, ++ ++ /* IEEE80211_ASSOCIATING* are for BSS client mode ++ * the driver shall not perform RX filtering unless ++ * the state is LINKED. ++ * The driver shall just check for the state LINKED and ++ * defaults to NOLINK for ALL the other states (including ++ * LINKED_SCANNING) ++ */ ++ ++ /* the association procedure will start (wq scheduling)*/ ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATING_RETRY, ++ ++ /* the association procedure is sending AUTH request*/ ++ IEEE80211_ASSOCIATING_AUTHENTICATING, ++ ++ /* the association procedure has successfully authentcated ++ * and is sending association request ++ */ ++ IEEE80211_ASSOCIATING_AUTHENTICATED, ++ ++ /* the link is ok. the card associated to a BSS or linked ++ * to a ibss cell or acting as an AP and creating the bss ++ */ ++ IEEE80211_LINKED, ++ ++ /* same as LINKED, but the driver shall apply RX filter ++ * rules as we are in NO_LINK mode. As the card is still ++ * logically linked, but it is doing a syncro site survey ++ * then it will be back to LINKED state. ++ */ ++ IEEE80211_LINKED_SCANNING, ++ ++}; ++#endif //PLATFORM_FREEBSD ++ ++#define DEFAULT_MAX_SCAN_AGE (15 * HZ) ++#define DEFAULT_FTS 2346 ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++#define IP_FMT "%d.%d.%d.%d" ++#define IP_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3] ++ ++#ifdef PLATFORM_FREEBSD //Baron change func to macro ++#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff)) ++#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \ ++(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \ ++(((Addr[5]) & 0xff) == 0xff)) ++#else ++extern __inline int is_multicast_mac_addr(const u8 *addr) ++{ ++ return ((addr[0] != 0xff) && (0x01 & addr[0])); ++} ++ ++extern __inline int is_broadcast_mac_addr(const u8 *addr) ++{ ++ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ ++ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); ++} ++ ++extern __inline int is_zero_mac_addr(const u8 *addr) ++{ ++ return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \ ++ (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00)); ++} ++#endif //PLATFORM_FREEBSD ++ ++#define CFG_IEEE80211_RESERVE_FCS (1<<0) ++#define CFG_IEEE80211_COMPUTE_FCS (1<<1) ++ ++typedef struct tx_pending_t{ ++ int frag; ++ struct ieee80211_txb *txb; ++}tx_pending_t; ++ ++ ++ ++#define MAXTID 16 ++ ++#define IEEE_A (1<<0) ++#define IEEE_B (1<<1) ++#define IEEE_G (1<<2) ++#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) ++ ++//Baron move to ieee80211.c ++int ieee80211_is_empty_essid(const char *essid, int essid_len); ++int ieee80211_get_hdrlen(u16 fc); ++ ++#if 0 ++/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ ++#define WLAN_ACTION_SPECTRUM_MGMT 0 ++#define WLAN_ACTION_QOS 1 ++#define WLAN_ACTION_DLS 2 ++#define WLAN_ACTION_BLOCK_ACK 3 ++#define WLAN_ACTION_RADIO_MEASUREMENT 5 ++#define WLAN_ACTION_FT 6 ++#define WLAN_ACTION_SA_QUERY 8 ++#define WLAN_ACTION_WMM 17 ++#endif ++ ++ ++/* Action category code */ ++enum rtw_ieee80211_category { ++ RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, ++ RTW_WLAN_CATEGORY_QOS = 1, ++ RTW_WLAN_CATEGORY_DLS = 2, ++ RTW_WLAN_CATEGORY_BACK = 3, ++ RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames ++ RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, ++ RTW_WLAN_CATEGORY_FT = 6, ++ RTW_WLAN_CATEGORY_HT = 7, ++ RTW_WLAN_CATEGORY_SA_QUERY = 8, ++ RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, // add for CONFIG_IEEE80211W, none 11w also can use ++ RTW_WLAN_CATEGORY_TDLS = 12, ++ RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, // add for CONFIG_IEEE80211W, none 11w also can use ++ RTW_WLAN_CATEGORY_WMM = 17, ++ RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames ++}; ++ ++/* SPECTRUM_MGMT action code */ ++enum rtw_ieee80211_spectrum_mgmt_actioncode { ++ RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, ++ RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, ++ RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, ++ RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, ++ RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, ++ RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, ++}; ++ ++enum _PUBLIC_ACTION{ ++ ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence ++ ACT_PUBLIC_DSE_ENABLE = 1, ++ ACT_PUBLIC_DSE_DEENABLE = 2, ++ ACT_PUBLIC_DSE_REG_LOCATION = 3, ++ ACT_PUBLIC_EXT_CHL_SWITCH = 4, ++ ACT_PUBLIC_DSE_MSR_REQ = 5, ++ ACT_PUBLIC_DSE_MSR_RPRT = 6, ++ ACT_PUBLIC_MP = 7, // Measurement Pilot ++ ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, ++ ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT ++ ACT_PUBLIC_GAS_INITIAL_REQ = 10, ++ ACT_PUBLIC_GAS_INITIAL_RSP = 11, ++ ACT_PUBLIC_GAS_COMEBACK_REQ = 12, ++ ACT_PUBLIC_GAS_COMEBACK_RSP = 13, ++ ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, ++ ACT_PUBLIC_LOCATION_TRACK = 15, ++ ACT_PUBLIC_MAX ++}; ++ ++#ifdef CONFIG_TDLS ++enum TDLS_ACTION_FIELD{ ++ TDLS_SETUP_REQUEST = 0, ++ TDLS_SETUP_RESPONSE = 1, ++ TDLS_SETUP_CONFIRM = 2, ++ TDLS_TEARDOWN = 3, ++ TDLS_PEER_TRAFFIC_INDICATION = 4, ++ TDLS_CHANNEL_SWITCH_REQUEST = 5, ++ TDLS_CHANNEL_SWITCH_RESPONSE = 6, ++ TDLS_PEER_PSM_REQUEST = 7, ++ TDLS_PEER_PSM_RESPONSE = 8, ++ TDLS_PEER_TRAFFIC_RESPONSE = 9, ++ TDLS_DISCOVERY_REQUEST = 10, ++ TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame ++}; ++ ++#define TUNNELED_PROBE_REQ 15 ++#define TUNNELED_PROBE_RSP 16 ++#endif //CONFIG_TDLS ++ ++/* BACK action code */ ++enum rtw_ieee80211_back_actioncode { ++ RTW_WLAN_ACTION_ADDBA_REQ = 0, ++ RTW_WLAN_ACTION_ADDBA_RESP = 1, ++ RTW_WLAN_ACTION_DELBA = 2, ++}; ++ ++/* HT features action code */ ++enum rtw_ieee80211_ht_actioncode { ++ RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, ++ RTW_WLAN_ACTION_SM_PS = 1, ++ RTW_WLAN_ACTION_PSPM = 2, ++ RTW_WLAN_ACTION_PCO_PHASE = 3, ++ RTW_WLAN_ACTION_MIMO_CSI_MX = 4, ++ RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, ++ RTW_WLAN_ACTION_MIMP_CP_BF = 6, ++ RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, ++ RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, ++}; ++ ++/* BACK (block-ack) parties */ ++enum rtw_ieee80211_back_parties { ++ RTW_WLAN_BACK_RECIPIENT = 0, ++ RTW_WLAN_BACK_INITIATOR = 1, ++ RTW_WLAN_BACK_TIMER = 2, ++}; ++ ++ ++#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) ++ * 00:50:F2 */ ++#ifndef PLATFORM_FREEBSD //Baron BSD has defined ++#define WME_OUI_TYPE 2 ++#endif //PLATFORM_FREEBSD ++#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 ++#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 ++#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 ++#define WME_VERSION 1 ++ ++#define WME_ACTION_CODE_SETUP_REQUEST 0 ++#define WME_ACTION_CODE_SETUP_RESPONSE 1 ++#define WME_ACTION_CODE_TEARDOWN 2 ++ ++#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 ++#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 ++#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 ++ ++#define WME_TSPEC_DIRECTION_UPLINK 0 ++#define WME_TSPEC_DIRECTION_DOWNLINK 1 ++#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 ++ ++ ++#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ ++ ++#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ ++ ++/** ++ * enum rtw_ieee80211_channel_flags - channel flags ++ * ++ * Channel flags set by the regulatory control code. ++ * ++ * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled. ++ * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted ++ * on this channel. ++ * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel. ++ * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel. ++ * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel ++ * is not permitted. ++ * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel ++ * is not permitted. ++ */ ++ enum rtw_ieee80211_channel_flags { ++ RTW_IEEE80211_CHAN_DISABLED = 1<<0, ++ RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1, ++ RTW_IEEE80211_CHAN_NO_IBSS = 1<<2, ++ RTW_IEEE80211_CHAN_RADAR = 1<<3, ++ RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4, ++ RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5, ++ }; ++ ++ #define RTW_IEEE80211_CHAN_NO_HT40 \ ++ (RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS) ++ ++/* Represent channel details, subset of ieee80211_channel */ ++struct rtw_ieee80211_channel { ++ //enum ieee80211_band band; ++ //u16 center_freq; ++ u16 hw_value; ++ u32 flags; ++ //int max_antenna_gain; ++ //int max_power; ++ //int max_reg_power; ++ //bool beacon_found; ++ //u32 orig_flags; ++ //int orig_mag; ++ //int orig_mpwr; ++}; ++ ++#define CHAN_FMT \ ++ /*"band:%d, "*/ \ ++ /*"center_freq:%u, "*/ \ ++ "hw_value:%u, " \ ++ "flags:0x%08x" \ ++ /*"max_antenna_gain:%d\n"*/ \ ++ /*"max_power:%d\n"*/ \ ++ /*"max_reg_power:%d\n"*/ \ ++ /*"beacon_found:%u\n"*/ \ ++ /*"orig_flags:0x%08x\n"*/ \ ++ /*"orig_mag:%d\n"*/ \ ++ /*"orig_mpwr:%d\n"*/ ++ ++#define CHAN_ARG(channel) \ ++ /*(channel)->band*/ \ ++ /*, (channel)->center_freq*/ \ ++ (channel)->hw_value \ ++ , (channel)->flags \ ++ /*, (channel)->max_antenna_gain*/ \ ++ /*, (channel)->max_power*/ \ ++ /*, (channel)->max_reg_power*/ \ ++ /*, (channel)->beacon_found*/ \ ++ /*, (channel)->orig_flags*/ \ ++ /*, (channel)->orig_mag*/ \ ++ /*, (channel)->orig_mpwr*/ \ ++ ++/* Parsed Information Elements */ ++struct rtw_ieee802_11_elems { ++ u8 *ssid; ++ u8 ssid_len; ++ u8 *supp_rates; ++ u8 supp_rates_len; ++ u8 *fh_params; ++ u8 fh_params_len; ++ u8 *ds_params; ++ u8 ds_params_len; ++ u8 *cf_params; ++ u8 cf_params_len; ++ u8 *tim; ++ u8 tim_len; ++ u8 *ibss_params; ++ u8 ibss_params_len; ++ u8 *challenge; ++ u8 challenge_len; ++ u8 *erp_info; ++ u8 erp_info_len; ++ u8 *ext_supp_rates; ++ u8 ext_supp_rates_len; ++ u8 *wpa_ie; ++ u8 wpa_ie_len; ++ u8 *rsn_ie; ++ u8 rsn_ie_len; ++ u8 *wme; ++ u8 wme_len; ++ u8 *wme_tspec; ++ u8 wme_tspec_len; ++ u8 *wps_ie; ++ u8 wps_ie_len; ++ u8 *power_cap; ++ u8 power_cap_len; ++ u8 *supp_channels; ++ u8 supp_channels_len; ++ u8 *mdie; ++ u8 mdie_len; ++ u8 *ftie; ++ u8 ftie_len; ++ u8 *timeout_int; ++ u8 timeout_int_len; ++ u8 *ht_capabilities; ++ u8 ht_capabilities_len; ++ u8 *ht_operation; ++ u8 ht_operation_len; ++ u8 *vendor_ht_cap; ++ u8 vendor_ht_cap_len; ++}; ++ ++typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; ++ ++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, ++ struct rtw_ieee802_11_elems *elems, ++ int show_errors); ++ ++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); ++u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); ++ ++enum secondary_ch_offset { ++ SCN = 0, /* no secondary channel */ ++ SCA = 1, /* secondary channel above */ ++ SCB = 3, /* secondary channel below */ ++}; ++u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset); ++u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset); ++u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt); ++u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); ++u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); ++ ++u8 *rtw_get_ie(u8*pbuf, sint index, sint *len, sint limit); ++u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); ++int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); ++ ++void rtw_set_supported_rate(u8* SupportedRates, uint mode) ; ++ ++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); ++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); ++int rtw_get_wpa_cipher_suite(u8 *s); ++int rtw_get_wpa2_cipher_suite(u8 *s); ++int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len); ++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); ++int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); ++ ++int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len); ++ ++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); ++u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type); ++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); ++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr); ++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content); ++ ++/** ++ * for_each_ie - iterate over continuous IEs ++ * @ie: ++ * @buf: ++ * @buf_len: ++ */ ++#define for_each_ie(ie, buf, buf_len) \ ++ for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2)) ++ ++void dump_ies(u8 *buf, u32 buf_len); ++void dump_wps_ie(u8 *ie, u32 ie_len); ++ ++#ifdef CONFIG_P2P ++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); ++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); ++void dump_p2p_ie(u8 *ie, u32 ie_len); ++u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); ++u8 *rtw_get_p2p_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type); ++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr); ++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content); ++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); ++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); ++#endif ++ ++#ifdef CONFIG_WFD ++void dump_wfd_ie(u8 *ie, u32 ie_len); ++int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); ++int rtw_get_wfd_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type); ++int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen); ++#endif // CONFIG_WFD ++ ++uint rtw_get_rateset_len(u8 *rateset); ++ ++struct registry_priv; ++int rtw_generate_ie(struct registry_priv *pregistrypriv); ++ ++ ++int rtw_get_bit_value_from_ieee_value(u8 val); ++ ++uint rtw_is_cckrates_included(u8 *rate); ++ ++uint rtw_is_cckratesonly_included(u8 *rate); ++ ++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); ++ ++void rtw_get_bcn_info(struct wlan_network *pnetwork); ++ ++void rtw_macaddr_cfg(u8 *mac_addr); ++ ++u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate); ++ ++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action); ++const char *action_public_str(u8 action); ++ ++#endif /* IEEE80211_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211_ext.h b/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211_ext.h +new file mode 100644 +index 00000000..14f1b239 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/ieee80211_ext.h +@@ -0,0 +1,477 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IEEE80211_EXT_H ++#define __IEEE80211_EXT_H ++ ++#include ++#include ++#include ++ ++#define WMM_OUI_TYPE 2 ++#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0 ++#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1 ++#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2 ++#define WMM_VERSION 1 ++ ++#define WPA_PROTO_WPA BIT(0) ++#define WPA_PROTO_RSN BIT(1) ++ ++#define WPA_KEY_MGMT_IEEE8021X BIT(0) ++#define WPA_KEY_MGMT_PSK BIT(1) ++#define WPA_KEY_MGMT_NONE BIT(2) ++#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3) ++#define WPA_KEY_MGMT_WPA_NONE BIT(4) ++ ++ ++#define WPA_CAPABILITY_PREAUTH BIT(0) ++#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6) ++#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9) ++ ++ ++#define PMKID_LEN 16 ++ ++ ++#ifdef PLATFORM_LINUX ++struct wpa_ie_hdr { ++ u8 elem_id; ++ u8 len; ++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ ++ u8 version[2]; /* little endian */ ++}__attribute__ ((packed)); ++ ++struct rsn_ie_hdr { ++ u8 elem_id; /* WLAN_EID_RSN */ ++ u8 len; ++ u8 version[2]; /* little endian */ ++}__attribute__ ((packed)); ++ ++struct wme_ac_parameter { ++#if defined(CONFIG_LITTLE_ENDIAN) ++ /* byte 1 */ ++ u8 aifsn:4, ++ acm:1, ++ aci:2, ++ reserved:1; ++ ++ /* byte 2 */ ++ u8 eCWmin:4, ++ eCWmax:4; ++#elif defined(CONFIG_BIG_ENDIAN) ++ /* byte 1 */ ++ u8 reserved:1, ++ aci:2, ++ acm:1, ++ aifsn:4; ++ ++ /* byte 2 */ ++ u8 eCWmax:4, ++ eCWmin:4; ++#else ++#error "Please fix " ++#endif ++ ++ /* bytes 3 & 4 */ ++ u16 txopLimit; ++} __attribute__ ((packed)); ++ ++struct wme_parameter_element { ++ /* required fields for WME version 1 */ ++ u8 oui[3]; ++ u8 oui_type; ++ u8 oui_subtype; ++ u8 version; ++ u8 acInfo; ++ u8 reserved; ++ struct wme_ac_parameter ac[4]; ++ ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct wpa_ie_hdr { ++ u8 elem_id; ++ u8 len; ++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ ++ u8 version[2]; /* little endian */ ++}; ++ ++struct rsn_ie_hdr { ++ u8 elem_id; /* WLAN_EID_RSN */ ++ u8 len; ++ u8 version[2]; /* little endian */ ++}; ++ ++#pragma pack() ++ ++#endif ++ ++#define WPA_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define WPA_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define WPA_PUT_LE32(a, val) \ ++ do { \ ++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[0] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val)) ++//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) ++ ++ ++ ++/* Action category code */ ++enum ieee80211_category { ++ WLAN_CATEGORY_SPECTRUM_MGMT = 0, ++ WLAN_CATEGORY_QOS = 1, ++ WLAN_CATEGORY_DLS = 2, ++ WLAN_CATEGORY_BACK = 3, ++ WLAN_CATEGORY_HT = 7, ++ WLAN_CATEGORY_WMM = 17, ++}; ++ ++/* SPECTRUM_MGMT action code */ ++enum ieee80211_spectrum_mgmt_actioncode { ++ WLAN_ACTION_SPCT_MSR_REQ = 0, ++ WLAN_ACTION_SPCT_MSR_RPRT = 1, ++ WLAN_ACTION_SPCT_TPC_REQ = 2, ++ WLAN_ACTION_SPCT_TPC_RPRT = 3, ++ WLAN_ACTION_SPCT_CHL_SWITCH = 4, ++ WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, ++}; ++ ++/* BACK action code */ ++enum ieee80211_back_actioncode { ++ WLAN_ACTION_ADDBA_REQ = 0, ++ WLAN_ACTION_ADDBA_RESP = 1, ++ WLAN_ACTION_DELBA = 2, ++}; ++ ++/* HT features action code */ ++enum ieee80211_ht_actioncode { ++ WLAN_ACTION_NOTIFY_CH_WIDTH = 0, ++ WLAN_ACTION_SM_PS = 1, ++ WLAN_ACTION_PSPM = 2, ++ WLAN_ACTION_PCO_PHASE = 3, ++ WLAN_ACTION_MIMO_CSI_MX = 4, ++ WLAN_ACTION_MIMO_NONCP_BF = 5, ++ WLAN_ACTION_MIMP_CP_BF = 6, ++ WLAN_ACTION_ASEL_INDICATES_FB = 7, ++ WLAN_ACTION_HI_INFO_EXCHG = 8, ++}; ++ ++/* BACK (block-ack) parties */ ++enum ieee80211_back_parties { ++ WLAN_BACK_RECIPIENT = 0, ++ WLAN_BACK_INITIATOR = 1, ++ WLAN_BACK_TIMER = 2, ++}; ++ ++#ifdef PLATFORM_LINUX ++ ++struct ieee80211_mgmt { ++ u16 frame_control; ++ u16 duration; ++ u8 da[6]; ++ u8 sa[6]; ++ u8 bssid[6]; ++ u16 seq_ctrl; ++ union { ++ struct { ++ u16 auth_alg; ++ u16 auth_transaction; ++ u16 status_code; ++ /* possibly followed by Challenge text */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) auth; ++ struct { ++ u16 reason_code; ++ } __attribute__ ((packed)) deauth; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) assoc_req; ++ struct { ++ u16 capab_info; ++ u16 status_code; ++ u16 aid; ++ /* followed by Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) assoc_resp, reassoc_resp; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ u8 current_ap[6]; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) reassoc_req; ++ struct { ++ u16 reason_code; ++ } __attribute__ ((packed)) disassoc; ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params, TIM */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) beacon; ++ struct { ++ /* only variable items: SSID, Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) probe_req; ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) probe_resp; ++ struct { ++ u8 category; ++ union { ++ struct { ++ u8 action_code; ++ u8 dialog_token; ++ u8 status_code; ++ u8 variable[0]; ++ } __attribute__ ((packed)) wme_action; ++#if 0 ++ struct{ ++ u8 action_code; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_channel_sw_ie sw_elem; ++ } __attribute__ ((packed)) chan_switch; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_msrment_ie msr_elem; ++ } __attribute__ ((packed)) measurement; ++#endif ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 capab; ++ u16 timeout; ++ u16 start_seq_num; ++ } __attribute__ ((packed)) addba_req; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 status; ++ u16 capab; ++ u16 timeout; ++ } __attribute__ ((packed)) addba_resp; ++ struct{ ++ u8 action_code; ++ u16 params; ++ u16 reason_code; ++ } __attribute__ ((packed)) delba; ++ struct{ ++ u8 action_code; ++ /* capab_info for open and confirm, ++ * reason for close ++ */ ++ u16 aux; ++ /* Followed in plink_confirm by status ++ * code, AID and supported rates, ++ * and directly by supported rates in ++ * plink_open and plink_close ++ */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) plink_action; ++ struct{ ++ u8 action_code; ++ u8 variable[0]; ++ } __attribute__ ((packed)) mesh_action; ++ } __attribute__ ((packed)) u; ++ } __attribute__ ((packed)) action; ++ } __attribute__ ((packed)) u; ++}__attribute__ ((packed)); ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct ieee80211_mgmt { ++ u16 frame_control; ++ u16 duration; ++ u8 da[6]; ++ u8 sa[6]; ++ u8 bssid[6]; ++ u16 seq_ctrl; ++ union { ++ struct { ++ u16 auth_alg; ++ u16 auth_transaction; ++ u16 status_code; ++ /* possibly followed by Challenge text */ ++ u8 variable[0]; ++ } auth; ++ struct { ++ u16 reason_code; ++ } deauth; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } assoc_req; ++ struct { ++ u16 capab_info; ++ u16 status_code; ++ u16 aid; ++ /* followed by Supported rates */ ++ u8 variable[0]; ++ } assoc_resp, reassoc_resp; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ u8 current_ap[6]; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } reassoc_req; ++ struct { ++ u16 reason_code; ++ } disassoc; ++#if 0 ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params, TIM */ ++ u8 variable[0]; ++ } beacon; ++ struct { ++ /* only variable items: SSID, Supported rates */ ++ u8 variable[0]; ++ } probe_req; ++ ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params */ ++ u8 variable[0]; ++ } probe_resp; ++#endif ++ struct { ++ u8 category; ++ union { ++ struct { ++ u8 action_code; ++ u8 dialog_token; ++ u8 status_code; ++ u8 variable[0]; ++ } wme_action; ++/* ++ struct{ ++ u8 action_code; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_channel_sw_ie sw_elem; ++ } chan_switch; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_msrment_ie msr_elem; ++ } measurement; ++*/ ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 capab; ++ u16 timeout; ++ u16 start_seq_num; ++ } addba_req; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 status; ++ u16 capab; ++ u16 timeout; ++ } addba_resp; ++ struct{ ++ u8 action_code; ++ u16 params; ++ u16 reason_code; ++ } delba; ++ struct{ ++ u8 action_code; ++ /* capab_info for open and confirm, ++ * reason for close ++ */ ++ u16 aux; ++ /* Followed in plink_confirm by status ++ * code, AID and supported rates, ++ * and directly by supported rates in ++ * plink_open and plink_close ++ */ ++ u8 variable[0]; ++ } plink_action; ++ struct{ ++ u8 action_code; ++ u8 variable[0]; ++ } mesh_action; ++ } u; ++ } action; ++ } u; ++} ; ++ ++#pragma pack() ++ ++#endif ++ ++/* mgmt header + 1 byte category code */ ++#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/if_ether.h b/drivers/net/wireless/rtl818x/rtl8189/include/if_ether.h +new file mode 100644 +index 00000000..93ed096d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/if_ether.h +@@ -0,0 +1,113 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef _LINUX_IF_ETHER_H ++#define _LINUX_IF_ETHER_H ++ ++/* ++ * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble ++ * and FCS/CRC (frame check sequence). ++ */ ++ ++#define ETH_ALEN 6 /* Octets in one ethernet addr */ ++#define ETH_HLEN 14 /* Total octets in header. */ ++#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ ++#define ETH_DATA_LEN 1500 /* Max. octets in payload */ ++#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ ++ ++/* ++ * These are the defined Ethernet Protocol ID's. ++ */ ++ ++#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ ++#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ ++#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ ++#define ETH_P_IP 0x0800 /* Internet Protocol packet */ ++#define ETH_P_X25 0x0805 /* CCITT X.25 */ ++#define ETH_P_ARP 0x0806 /* Address Resolution packet */ ++#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ ++#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ ++#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ ++#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ ++#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ ++#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ ++#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ ++#define ETH_P_LAT 0x6004 /* DEC LAT */ ++#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ ++#define ETH_P_CUST 0x6006 /* DEC Customer use */ ++#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ ++#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ ++#define ETH_P_ATALK 0x809B /* Appletalk DDP */ ++#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ ++#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ ++#define ETH_P_IPX 0x8137 /* IPX over DIX */ ++#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ ++#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ ++#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ ++#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ ++#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport ++ * over Ethernet ++ */ ++ ++/* ++ * Non DIX types. Won't clash for 1500 types. ++ */ ++ ++#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ ++#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ ++#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ ++#define ETH_P_802_2 0x0004 /* 802.2 frames */ ++#define ETH_P_SNAP 0x0005 /* Internal only */ ++#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ ++#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ ++#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ ++#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ ++#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ ++#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ ++#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */ ++#define ETH_P_CONTROL 0x0016 /* Card specific control frames */ ++#define ETH_P_IRDA 0x0017 /* Linux-IrDA */ ++#define ETH_P_ECONET 0x0018 /* Acorn Econet */ ++ ++/* ++ * This is an Ethernet frame header. ++ */ ++ ++struct ethhdr ++{ ++ unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ ++ unsigned char h_source[ETH_ALEN]; /* source ether addr */ ++ unsigned short h_proto; /* packet type ID field */ ++}; ++ ++struct _vlan { ++ unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID ++ unsigned short h_vlan_encapsulated_proto; ++}; ++ ++ ++ ++#define get_vlan_id(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff) ++#define get_vlan_priority(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13) ++#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short )pvlan->h_vlan_encapsulated_proto)) ++ ++ ++#endif /* _LINUX_IF_ETHER_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/ioctl_cfg80211.h b/drivers/net/wireless/rtl818x/rtl8189/include/ioctl_cfg80211.h +new file mode 100644 +index 00000000..88647e84 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/ioctl_cfg80211.h +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IOCTL_CFG80211_H__ ++#define __IOCTL_CFG80211_H__ ++ ++ ++#if defined(RTW_USE_CFG80211_STA_EVENT) ++ #undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER ++#endif ++ ++struct rtw_wdev_invit_info { ++ u8 state; /* 0: req, 1:rep */ ++ u8 peer_mac[ETH_ALEN]; ++ u8 active; ++ u8 token; ++ u8 flags; ++ u8 status; ++ u8 req_op_ch; ++ u8 rsp_op_ch; ++}; ++ ++#define rtw_wdev_invit_info_init(invit_info) \ ++ do { \ ++ (invit_info)->state = 0xff; \ ++ _rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \ ++ (invit_info)->active = 0xff; \ ++ (invit_info)->token = 0; \ ++ (invit_info)->flags = 0x00; \ ++ (invit_info)->status = 0xff; \ ++ (invit_info)->req_op_ch = 0; \ ++ (invit_info)->rsp_op_ch = 0; \ ++ } while (0) ++ ++struct rtw_wdev_nego_info { ++ u8 state; /* 0: req, 1:rep, 3:conf */ ++ u8 peer_mac[ETH_ALEN]; ++ u8 active; ++ u8 token; ++ u8 status; ++ u8 req_intent; ++ u8 req_op_ch; ++ u8 req_listen_ch; ++ u8 rsp_intent; ++ u8 rsp_op_ch; ++ u8 conf_op_ch; ++}; ++ ++#define rtw_wdev_nego_info_init(nego_info) \ ++ do { \ ++ (nego_info)->state = 0xff; \ ++ _rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \ ++ (nego_info)->active = 0xff; \ ++ (nego_info)->token = 0; \ ++ (nego_info)->status = 0xff; \ ++ (nego_info)->req_intent = 0xff; \ ++ (nego_info)->req_op_ch = 0; \ ++ (nego_info)->req_listen_ch = 0; \ ++ (nego_info)->rsp_intent = 0xff; \ ++ (nego_info)->rsp_op_ch = 0; \ ++ (nego_info)->conf_op_ch = 0; \ ++ } while (0) ++ ++struct rtw_wdev_priv ++{ ++ struct wireless_dev *rtw_wdev; ++ ++ _adapter *padapter; ++ ++ struct cfg80211_scan_request *scan_request; ++ _lock scan_req_lock; ++ ++ struct net_device *pmon_ndev;//for monitor interface ++ char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface ++ ++ u8 p2p_enabled; ++ ++ u8 provdisc_req_issued; ++ ++ struct rtw_wdev_invit_info invit_info; ++ struct rtw_wdev_nego_info nego_info; ++ ++ u8 bandroid_scan; ++ bool block; ++ bool power_mgmt; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ATOMIC_T ro_ch_to; ++ ATOMIC_T switch_ch_to; ++#endif ++ ++}; ++ ++#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w))) ++ ++#define wiphy_to_adapter(x) (_adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter) ++ ++#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev) ++ ++int rtw_wdev_alloc(_adapter *padapter, struct device *dev); ++void rtw_wdev_free(struct wireless_dev *wdev); ++void rtw_wdev_unregister(struct wireless_dev *wdev); ++ ++void rtw_cfg80211_init_wiphy(_adapter *padapter); ++ ++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter); ++struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork); ++int rtw_cfg80211_check_bss(_adapter *padapter); ++void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter); ++void rtw_cfg80211_indicate_connect(_adapter *padapter); ++void rtw_cfg80211_indicate_disconnect(_adapter *padapter); ++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted); ++ ++#ifdef CONFIG_AP_MODE ++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); ++#endif //CONFIG_AP_MODE ++ ++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); ++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg); ++ ++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); ++ ++bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) ++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp) ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) ++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp) ++#else ++#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) ++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len) ++#else ++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) ++#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp) ++#else ++#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) ++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp) ++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp) ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp) ++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp) ++#else ++#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp) ++#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp) ++#endif ++ ++#endif //__IOCTL_CFG80211_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/ip.h b/drivers/net/wireless/rtl818x/rtl8189/include/ip.h +new file mode 100644 +index 00000000..db079bc7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/ip.h +@@ -0,0 +1,142 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_IP_H ++#define _LINUX_IP_H ++#include ++ ++/* SOL_IP socket options */ ++ ++#define IPTOS_TOS_MASK 0x1E ++#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) ++#define IPTOS_LOWDELAY 0x10 ++#define IPTOS_THROUGHPUT 0x08 ++#define IPTOS_RELIABILITY 0x04 ++#define IPTOS_MINCOST 0x02 ++ ++#define IPTOS_PREC_MASK 0xE0 ++#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) ++#define IPTOS_PREC_NETCONTROL 0xe0 ++#define IPTOS_PREC_INTERNETCONTROL 0xc0 ++#define IPTOS_PREC_CRITIC_ECP 0xa0 ++#define IPTOS_PREC_FLASHOVERRIDE 0x80 ++#define IPTOS_PREC_FLASH 0x60 ++#define IPTOS_PREC_IMMEDIATE 0x40 ++#define IPTOS_PREC_PRIORITY 0x20 ++#define IPTOS_PREC_ROUTINE 0x00 ++ ++ ++/* IP options */ ++#define IPOPT_COPY 0x80 ++#define IPOPT_CLASS_MASK 0x60 ++#define IPOPT_NUMBER_MASK 0x1f ++ ++#define IPOPT_COPIED(o) ((o)&IPOPT_COPY) ++#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) ++#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) ++ ++#define IPOPT_CONTROL 0x00 ++#define IPOPT_RESERVED1 0x20 ++#define IPOPT_MEASUREMENT 0x40 ++#define IPOPT_RESERVED2 0x60 ++ ++#define IPOPT_END (0 |IPOPT_CONTROL) ++#define IPOPT_NOOP (1 |IPOPT_CONTROL) ++#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT) ++#define IPOPT_RR (7 |IPOPT_CONTROL) ++#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY) ++ ++#define IPVERSION 4 ++#define MAXTTL 255 ++#define IPDEFTTL 64 ++ ++/* struct timestamp, struct route and MAX_ROUTES are removed. ++ ++ REASONS: it is clear that nobody used them because: ++ - MAX_ROUTES value was wrong. ++ - "struct route" was wrong. ++ - "struct timestamp" had fatally misaligned bitfields and was completely unusable. ++ */ ++ ++#define IPOPT_OPTVAL 0 ++#define IPOPT_OLEN 1 ++#define IPOPT_OFFSET 2 ++#define IPOPT_MINOFF 4 ++#define MAX_IPOPTLEN 40 ++#define IPOPT_NOP IPOPT_NOOP ++#define IPOPT_EOL IPOPT_END ++#define IPOPT_TS IPOPT_TIMESTAMP ++ ++#define IPOPT_TS_TSONLY 0 /* timestamps only */ ++#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ ++#define IPOPT_TS_PRESPEC 3 /* specified modules only */ ++ ++#ifdef PLATFORM_LINUX ++ ++struct ip_options { ++ __u32 faddr; /* Saved first hop address */ ++ unsigned char optlen; ++ unsigned char srr; ++ unsigned char rr; ++ unsigned char ts; ++ unsigned char is_setbyuser:1, /* Set by setsockopt? */ ++ is_data:1, /* Options in __data, rather than skb */ ++ is_strictroute:1, /* Strict source route */ ++ srr_is_hit:1, /* Packet destination addr was our one */ ++ is_changed:1, /* IP checksum more not valid */ ++ rr_needaddr:1, /* Need to record addr of outgoing dev */ ++ ts_needtime:1, /* Need to record timestamp */ ++ ts_needaddr:1; /* Need to record addr of outgoing dev */ ++ unsigned char router_alert; ++ unsigned char __pad1; ++ unsigned char __pad2; ++ unsigned char __data[0]; ++}; ++ ++#define optlength(opt) (sizeof(struct ip_options) + opt->optlen) ++#endif ++ ++struct iphdr { ++#if defined(__LITTLE_ENDIAN_BITFIELD) ++ __u8 ihl:4, ++ version:4; ++#elif defined (__BIG_ENDIAN_BITFIELD) ++ __u8 version:4, ++ ihl:4; ++#else ++#error "Please fix " ++#endif ++ __u8 tos; ++ __u16 tot_len; ++ __u16 id; ++ __u16 frag_off; ++ __u8 ttl; ++ __u8 protocol; ++ __u16 check; ++ __u32 saddr; ++ __u32 daddr; ++ /*The options start here. */ ++}; ++ ++#endif /* _LINUX_IP_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/linux/wireless.h b/drivers/net/wireless/rtl818x/rtl8189/include/linux/wireless.h +new file mode 100644 +index 00000000..955ea8d3 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/linux/wireless.h +@@ -0,0 +1,91 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef _LINUX_WIRELESS_H ++#define _LINUX_WIRELESS_H ++ ++/***************************** INCLUDES *****************************/ ++ ++#if 0 ++#include /* for __u* and __s* typedefs */ ++#include /* for "struct sockaddr" et al */ ++#include /* for IFNAMSIZ and co... */ ++#else ++#define __user ++//typedef uint16_t __u16; ++#include /* for "struct sockaddr" et al */ ++#include /* for IFNAMSIZ and co... */ ++#endif ++ ++/****************************** TYPES ******************************/ ++ ++/* --------------------------- SUBTYPES --------------------------- */ ++/* ++ * For all data larger than 16 octets, we need to use a ++ * pointer to memory allocated in user space. ++ */ ++struct iw_point ++{ ++ void __user *pointer; /* Pointer to the data (in user space) */ ++ __u16 length; /* number of fields or size in bytes */ ++ __u16 flags; /* Optional params */ ++}; ++ ++ ++/* ------------------------ IOCTL REQUEST ------------------------ */ ++/* ++ * This structure defines the payload of an ioctl, and is used ++ * below. ++ * ++ * Note that this structure should fit on the memory footprint ++ * of iwreq (which is the same as ifreq), which mean a max size of ++ * 16 octets = 128 bits. Warning, pointers might be 64 bits wide... ++ * You should check this when increasing the structures defined ++ * above in this file... ++ */ ++union iwreq_data ++{ ++ /* Config - generic */ ++ char name[IFNAMSIZ]; ++ /* Name : used to verify the presence of wireless extensions. ++ * Name of the protocol/provider... */ ++ ++ struct iw_point data; /* Other large parameters */ ++}; ++ ++/* ++ * The structure to exchange data for ioctl. ++ * This structure is the same as 'struct ifreq', but (re)defined for ++ * convenience... ++ * Do I need to remind you about structure size (32 octets) ? ++ */ ++struct iwreq ++{ ++ union ++ { ++ char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ ++ } ifr_ifrn; ++ ++ /* Data part (defined just above) */ ++ union iwreq_data u; ++}; ++ ++#endif /* _LINUX_WIRELESS_H */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/mlme_osdep.h b/drivers/net/wireless/rtl818x/rtl8189/include/mlme_osdep.h +new file mode 100644 +index 00000000..75754db1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/mlme_osdep.h +@@ -0,0 +1,40 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __MLME_OSDEP_H_ ++#define __MLME_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) ++extern int time_after(u32 now, u32 old); ++#endif ++ ++extern void rtw_init_mlme_timer(_adapter *padapter); ++extern void rtw_os_indicate_disconnect( _adapter *adapter ); ++extern void rtw_os_indicate_connect( _adapter *adapter ); ++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted); ++extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie); ++ ++void rtw_reset_securitypriv( _adapter *adapter ); ++ ++#endif //_MLME_OSDEP_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/mp_custom_oid.h b/drivers/net/wireless/rtl818x/rtl8189/include/mp_custom_oid.h +new file mode 100644 +index 00000000..9cf1c827 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/mp_custom_oid.h +@@ -0,0 +1,354 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CUSTOM_OID_H ++#define __CUSTOM_OID_H ++ ++// by Owen ++// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit ++// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility ++// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility ++ ++// ++ ++// by Owen for Production Kit ++// For Production Kit with Agilent Equipments ++// in order to make our custom oids hopefully somewhat unique ++// we will use 0xFF (indicating implementation specific OID) ++// 81(first byte of non zero Realtek unique identifier) ++// 80 (second byte of non zero Realtek unique identifier) ++// XX (the custom OID number - providing 255 possible custom oids) ++ ++#define OID_RT_PRO_RESET_DUT 0xFF818000 ++#define OID_RT_PRO_SET_DATA_RATE 0xFF818001 ++#define OID_RT_PRO_START_TEST 0xFF818002 ++#define OID_RT_PRO_STOP_TEST 0xFF818003 ++#define OID_RT_PRO_SET_PREAMBLE 0xFF818004 ++#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005 ++#define OID_RT_PRO_SET_FILTER_BB 0xFF818006 ++#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007 ++#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008 ++#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009 ++#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A ++ ++#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D ++#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E ++#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F ++#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010 ++#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011 ++#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012 ++#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013 ++#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014 ++#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015 ++#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016 ++#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017 ++#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018 ++#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019 ++#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A ++#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B ++#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C ++#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D ++#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E ++#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F ++#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020 ++#define OID_RT_PRO_WRITE_EEPROM 0xFF818021 ++#define OID_RT_PRO_READ_EEPROM 0xFF818022 ++#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023 ++#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024 ++#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025 ++#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026 ++#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027 ++#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028 ++#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 ++#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A ++#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C ++// added by Owen on 04/08/03 for Cameo's request ++#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D ++#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E ++#define OID_RT_PRO_SET_MODULATION 0xFF81802F ++// ++ ++//Sean ++#define OID_RT_DRIVER_OPTION 0xFF818080 ++#define OID_RT_RF_OFF 0xFF818081 ++#define OID_RT_AUTH_STATUS 0xFF818082 ++ ++//======================================================================== ++#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B ++#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C ++#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B ++#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 ++//======================================================================== ++ ++ ++// by Owen for RTL8185 Phy Status Report Utility ++#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580 ++#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 ++#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 ++#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 ++#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 ++#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 ++#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 ++// ++ ++// by Owen on 03/09/19-03/09/22 for RTL8185 ++#define OID_RT_WIRELESS_MODE 0xFF818500 ++#define OID_RT_SUPPORTED_RATES 0xFF818501 ++#define OID_RT_DESIRED_RATES 0xFF818502 ++#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 ++// ++ ++#define OID_RT_GET_CONNECT_STATE 0xFF030001 ++#define OID_RT_RESCAN 0xFF030002 ++#define OID_RT_SET_KEY_LENGTH 0xFF030003 ++#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004 ++ ++#define OID_RT_SET_CHANNEL 0xFF010182 ++#define OID_RT_SET_SNIFFER_MODE 0xFF010183 ++#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184 ++#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185 ++#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186 ++#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 ++#define OID_RT_GET_TX_RETRY 0xFF010188 ++#define OID_RT_GET_RX_RETRY 0xFF010189 ++#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S ++#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S ++ ++#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 ++#define OID_RT_GET_TX_BEACON_OK 0xFF010191 ++#define OID_RT_GET_TX_BEACON_ERR 0xFF010192 ++#define OID_RT_GET_RX_ICV_ERR 0xFF010193 ++#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194 ++#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195 ++#define OID_RT_GET_PREAMBLE_MODE 0xFF010196 ++#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197 ++#define OID_RT_GET_AP_IP 0xFF010198 ++#define OID_RT_GET_CHANNELPLAN 0xFF010199 ++#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A ++#define OID_RT_SET_BCN_INTVL 0xFF01019B ++#define OID_RT_GET_RF_VENDER 0xFF01019C ++#define OID_RT_DEDICATE_PROBE 0xFF01019D ++#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E ++ ++#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F ++ ++#define OID_RT_GET_CCA_ERR 0xFF0101A0 ++#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1 ++#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2 ++ ++#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 ++#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 ++ ++// by Owen on 03/31/03 for Cameo's request ++#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 ++// ++#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 ++#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 ++#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 ++#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8 ++#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9 ++#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA ++#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB ++#define OID_RT_GET_CHANNEL 0xFF0101AC ++ ++#define OID_RT_SET_CHANNELPLAN 0xFF0101AD ++#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE ++#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF ++#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0 ++#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1 ++#define OID_RT_GET_IS_ROAMING 0xFF0101B2 ++#define OID_RT_GET_IS_PRIVACY 0xFF0101B3 ++#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4 ++#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5 ++#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6 ++#define OID_RT_RESET_LOG 0xFF0101B7 ++#define OID_RT_GET_LOG 0xFF0101B8 ++#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9 ++#define OID_RT_GET_HEADER_FAIL 0xFF0101BA ++#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB ++#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC ++#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD ++#define OID_RT_GET_TX_INFO 0xFF0101BE ++#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF ++#define OID_RT_RF_READ_WRITE 0xFF0101C0 ++ ++// For Netgear request. 2005.01.13, by rcnjko. ++#define OID_RT_FORCED_DATA_RATE 0xFF0101C1 ++#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 ++// For Netgear request. 2005.02.17, by rcnjko. ++#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 ++// For AZ project. 2005.06.27, by rcnjko. ++#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 ++ ++// Vincent 8185MP ++#define OID_RT_PRO_RX_FILTER 0xFF0111C0 ++ ++//Andy TEST ++//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 ++//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 ++#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 ++#define OID_CE_USB_READ_REGISTRY 0xFF0111C2 ++ ++ ++#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3 ++#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 ++#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 ++#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6 ++#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7 ++#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8 ++#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 ++#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA ++ ++// AP OID ++#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 ++#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 ++#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 ++#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 ++#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko. ++#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. ++ ++// 8187MP. 2004.09.06, by rcnjko. ++#define OID_RT_PRO8187_WI_POLL 0xFF818780 ++#define OID_RT_PRO_WRITE_BB_REG 0xFF818781 ++#define OID_RT_PRO_READ_BB_REG 0xFF818782 ++#define OID_RT_PRO_WRITE_RF_REG 0xFF818783 ++#define OID_RT_PRO_READ_RF_REG 0xFF818784 ++ ++// Meeting House. added by Annie, 2005-07-20. ++#define OID_RT_MH_VENDER_ID 0xFFEDC100 ++ ++//8711 MP OID added 20051230. ++#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S ++ ++#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q ++#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S ++ ++#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q ++#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S ++ ++#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S ++ ++#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q ++#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S ++ ++#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S ++#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q ++ ++#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q ++#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q ++#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q ++#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S ++ ++ ++//Method 2 for H2C/C2H ++#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S ++#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q ++#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S ++#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q ++#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q ++ ++#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S ++ ++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S ++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S ++#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q ++#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q ++ ++#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S ++#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q ++#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S ++#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q ++#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S ++#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q ++ ++#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S ++#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S ++#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S ++#define OID_RT_PRO_READ_TSSI 0xFF871123//S ++#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S ++ ++ ++#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q ++#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S ++ ++//Method 2 , using workitem ++#define OID_RT_SET_READ_REG 0xFF871181 //S ++#define OID_RT_SET_WRITE_REG 0xFF871182 //S ++#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S ++#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S ++#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S ++#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S ++#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S ++#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q ++ ++//For SDIO INTERFACE only ++#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S ++#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 ++ ++//For USB INTERFACE only ++#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S ++#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S ++#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S ++#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q ++#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q ++ ++#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S ++#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S ++#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE ++ ++#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S ++#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S ++#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S ++#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q ++ ++#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S ++ ++#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q ++#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S ++#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S ++#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q ++ ++#define OID_RT_SET_BANDWIDTH 0xFF871209 //S ++#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S ++ ++#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S ++ ++#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q ++ ++#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S ++ ++#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S ++ ++#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S ++ ++#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q ++ ++#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S ++#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q ++#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q ++ ++#define OID_RT_SET_POWER_DOWN 0xFF871214 //S ++ ++#define OID_RT_GET_POWER_MODE 0xFF871215 //Q ++ ++#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S ++#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S ++ ++#endif //#ifndef __CUSTOM_OID_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/nic_spec.h b/drivers/net/wireless/rtl818x/rtl8189/include/nic_spec.h +new file mode 100644 +index 00000000..18e7b2c0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/nic_spec.h +@@ -0,0 +1,47 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __NIC_SPEC_H__ ++#define __NIC_SPEC_H__ ++ ++#include ++ ++#define RTL8711_MCTRL_ (0x20000) ++#define RTL8711_UART_ (0x30000) ++#define RTL8711_TIMER_ (0x40000) ++#define RTL8711_FINT_ (0x50000) ++#define RTL8711_HINT_ (0x50000) ++#define RTL8711_GPIO_ (0x60000) ++#define RTL8711_WLANCTRL_ (0x200000) ++#define RTL8711_WLANFF_ (0xe00000) ++#define RTL8711_HCICTRL_ (0x600000) ++#define RTL8711_SYSCFG_ (0x620000) ++#define RTL8711_SYSCTRL_ (0x620000) ++#define RTL8711_MCCTRL_ (0x020000) ++ ++ ++#include ++ ++#include ++ ++ ++#endif // __RTL8711_SPEC_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/osdep_ce_service.h b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_ce_service.h +new file mode 100644 +index 00000000..6d2cc48f +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_ce_service.h +@@ -0,0 +1,171 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __OSDEP_CE_SERVICE_H_ ++#define __OSDEP_CE_SERVICE_H_ ++ ++ ++#include ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++#include "SDCardDDK.h" ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++typedef HANDLE _sema; ++typedef LIST_ENTRY _list; ++typedef NDIS_STATUS _OS_STATUS; ++ ++typedef NDIS_SPIN_LOCK _lock; ++ ++typedef HANDLE _rwlock; //Mutex ++ ++typedef u32 _irqL; ++ ++typedef NDIS_HANDLE _nic_hdl; ++ ++ ++typedef NDIS_MINIPORT_TIMER _timer; ++ ++struct __queue { ++ LIST_ENTRY queue; ++ _lock lock; ++}; ++ ++typedef NDIS_PACKET _pkt; ++typedef NDIS_BUFFER _buffer; ++typedef struct __queue _queue; ++ ++typedef HANDLE _thread_hdl_; ++typedef DWORD thread_return; ++typedef void* thread_context; ++typedef NDIS_WORK_ITEM _workitem; ++ ++#define thread_exit() ExitThread(STATUS_SUCCESS); return 0; ++ ++ ++#define SEMA_UPBND (0x7FFFFFFF) //8192 ++ ++__inline static _list *get_prev(_list *list) ++{ ++ return list->Blink; ++} ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->Flink; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) ++ ++__inline static void _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisAcquireSpinLock(plock); ++} ++ ++__inline static void _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisReleaseSpinLock(plock); ++} ++ ++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++ ++__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) ++{ ++ WaitForSingleObject(*prwlock, INFINITE ); ++ ++} ++ ++__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) ++{ ++ ReleaseMutex(*prwlock); ++} ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ RemoveEntryList(plist); ++ InitializeListHead(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) ++{ ++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ NdisMSetTimer(ptimer,delay_time); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ NdisMCancelTimer(ptimer,bcancelled); ++} ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++ ++ NdisInitializeWorkItem(pwork, pfunc, cntx); ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ NdisScheduleWorkItem(pwork); ++} ++ ++#define ATOMIC_INIT(i) { (i) } ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ ++ { \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++ NdisMSleep(10000); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++} ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/osdep_intf.h b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_intf.h +new file mode 100644 +index 00000000..6a4f1cde +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_intf.h +@@ -0,0 +1,160 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __OSDEP_INTF_H_ ++#define __OSDEP_INTF_H_ ++ ++#include ++#include ++#include ++ ++struct intf_priv { ++ ++ u8 *intf_dev; ++ u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 ++ u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 ++ u32 max_recvsz; //USB2.0: unlimited, SDIO:512 ++ ++ volatile u8 *io_rwmem; ++ volatile u8 *allocated_io_rwmem; ++ u32 io_wsz; //unit: 4bytes ++ u32 io_rsz;//unit: 4bytes ++ u8 intf_status; ++ ++ void (*_bus_io)(u8 *priv); ++ ++/* ++Under Sync. IRP (SDIO/USB) ++A protection mechanism is necessary for the io_rwmem(read/write protocol) ++ ++Under Async. IRP (SDIO/USB) ++The protection mechanism is through the pending queue. ++*/ ++ ++ _mutex ioctl_mutex; ++ ++ ++#ifdef PLATFORM_LINUX ++ #ifdef CONFIG_USB_HCI ++ // when in USB, IO is through interrupt in/out endpoints ++ struct usb_device *udev; ++ PURB piorw_urb; ++ u8 io_irp_cnt; ++ u8 bio_irp_pending; ++ _sema io_retevt; ++ _timer io_timer; ++ u8 bio_irp_timeout; ++ u8 bio_timer_cancel; ++ #endif ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ #ifdef CONFIG_SDIO_HCI ++ // below is for io_rwmem... ++ PMDL pmdl; ++ PSDBUS_REQUEST_PACKET sdrp; ++ PSDBUS_REQUEST_PACKET recv_sdrp; ++ PSDBUS_REQUEST_PACKET xmit_sdrp; ++ ++ PIRP piorw_irp; ++ ++ #endif ++ #ifdef CONFIG_USB_HCI ++ PURB piorw_urb; ++ PIRP piorw_irp; ++ u8 io_irp_cnt; ++ u8 bio_irp_pending; ++ _sema io_retevt; ++ #endif ++#endif ++ ++}; ++ ++ ++#ifdef CONFIG_R871X_TEST ++int rtw_start_pseudo_adhoc(_adapter *padapter); ++int rtw_stop_pseudo_adhoc(_adapter *padapter); ++#endif ++ ++u8 rtw_init_drv_sw(_adapter *padapter); ++u8 rtw_free_drv_sw(_adapter *padapter); ++u8 rtw_reset_drv_sw(_adapter *padapter); ++ ++u32 rtw_start_drv_threads(_adapter *padapter); ++void rtw_stop_drv_threads (_adapter *padapter); ++#ifdef CONFIG_WOWLAN ++void rtw_cancel_dynamic_chk_timer(_adapter *padapter); ++#endif ++void rtw_cancel_all_timer(_adapter *padapter); ++ ++#ifdef PLATFORM_LINUX ++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); ++ ++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); ++struct net_device *rtw_init_netdev(_adapter *padapter); ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++u16 rtw_recv_select_queue(struct sk_buff *skb); ++#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35) ++ ++#ifdef CONFIG_PROC_DEBUG ++void rtw_proc_init_one(struct net_device *dev); ++void rtw_proc_remove_one(struct net_device *dev); ++#else //!CONFIG_PROC_DEBUG ++static void rtw_proc_init_one(struct net_device *dev){} ++static void rtw_proc_remove_one(struct net_device *dev){} ++#endif //!CONFIG_PROC_DEBUG ++#endif //PLATFORM_LINUX ++ ++ ++#ifdef PLATFORM_FREEBSD ++extern int rtw_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data); ++#endif ++ ++void rtw_ips_dev_unload(_adapter *padapter); ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++void rtw_bb_rf_gain_offset(_adapter *padapter); ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++#ifdef CONFIG_IPS ++int rtw_ips_pwr_up(_adapter *padapter); ++void rtw_ips_pwr_down(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++struct _io_ops; ++_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops)); ++void rtw_drv_if2_free(_adapter *if2); ++void rtw_drv_if2_stop(_adapter *if2); ++#endif ++ ++int rtw_drv_register_netdev(_adapter *padapter); ++void rtw_ndev_destructor(_nic_hdl ndev); ++ ++int rtw_suspend_common(_adapter *padapter); ++int rtw_resume_common(_adapter *padapter); ++ ++#ifdef CONFIG_ARP_KEEP_ALIVE ++int rtw_gw_addr_query(_adapter *padapter); ++#endif ++ ++#endif //_OSDEP_INTF_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/osdep_service.h b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_service.h +new file mode 100644 +index 00000000..683a2808 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/osdep_service.h +@@ -0,0 +1,1854 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __OSDEP_SERVICE_H_ ++#define __OSDEP_SERVICE_H_ ++ ++#include ++#include ++//#include ++ ++#define _FAIL 0 ++#define _SUCCESS 1 ++#define RTW_RX_HANDLED 2 ++//#define RTW_STATUS_TIMEDOUT -110 ++ ++#undef _TRUE ++#define _TRUE 1 ++ ++#undef _FALSE ++#define _FALSE 0 ++ ++ ++#ifdef PLATFORM_FREEBSD ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "usbdevs.h" ++ ++#define USB_DEBUG_VAR rum_debug ++#include ++ ++#if 1 //Baron porting from linux, it's all temp solution, needs to check again ++#include ++#include /* XXX for PCPU_GET */ ++// typedef struct semaphore _sema; ++ typedef struct sema _sema; ++// typedef spinlock_t _lock; ++ typedef struct mtx _lock; ++ typedef struct mtx _mutex; ++ typedef struct timer_list _timer; ++ struct list_head { ++ struct list_head *next, *prev; ++ }; ++ struct __queue { ++ struct list_head queue; ++ _lock lock; ++ }; ++ ++ //typedef struct sk_buff _pkt; ++ typedef struct mbuf _pkt; ++ typedef struct mbuf _buffer; ++ ++ typedef struct __queue _queue; ++ typedef struct list_head _list; ++ typedef int _OS_STATUS; ++ //typedef u32 _irqL; ++ typedef unsigned long _irqL; ++ typedef struct ifnet * _nic_hdl; ++ ++ typedef pid_t _thread_hdl_; ++// typedef struct thread _thread_hdl_; ++ typedef void thread_return; ++ typedef void* thread_context; ++ ++ //#define thread_exit() complete_and_exit(NULL, 0) ++ ++ typedef void timer_hdl_return; ++ typedef void* timer_hdl_context; ++ typedef struct work_struct _workitem; ++ ++#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) ++/* emulate a modern version */ ++#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) ++ ++#define WIRELESS_EXT -1 ++#define HZ hz ++#define spin_lock_irqsave mtx_lock_irqsave ++#define spin_lock_bh mtx_lock_irqsave ++#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} ++//#define IFT_RTW 0xf9 //ifnet allocate type for RTW ++#define free_netdev if_free ++#define LIST_CONTAINOR(ptr, type, member) \ ++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) ++#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) ++/* ++ * Linux timers are emulated using FreeBSD callout functions ++ * (and taskqueue functionality). ++ * ++ * Currently no timer stats functionality. ++ * ++ * See (linux_compat) processes.c ++ * ++ */ ++struct timer_list { ++ ++ /* FreeBSD callout related fields */ ++ struct callout callout; ++ ++ //timeout function ++ void (*function)(void*); ++ //argument ++ void *arg; ++ ++}; ++struct workqueue_struct; ++struct work_struct; ++typedef void (*work_func_t)(struct work_struct *work); ++/* Values for the state of an item of work (work_struct) */ ++typedef enum work_state { ++ WORK_STATE_UNSET = 0, ++ WORK_STATE_CALLOUT_PENDING = 1, ++ WORK_STATE_TASK_PENDING = 2, ++ WORK_STATE_WORK_CANCELLED = 3 ++} work_state_t; ++ ++struct work_struct { ++ struct task task; /* FreeBSD task */ ++ work_state_t state; /* the pending or otherwise state of work. */ ++ work_func_t func; ++}; ++#define spin_unlock_irqrestore mtx_unlock_irqrestore ++#define spin_unlock_bh mtx_unlock_irqrestore ++#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); ++extern void _rtw_spinlock_init(_lock *plock); ++ ++//modify private structure to match freebsd ++#define BITS_PER_LONG 32 ++union ktime { ++ s64 tv64; ++#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) ++ struct { ++#ifdef __BIG_ENDIAN ++ s32 sec, nsec; ++#else ++ s32 nsec, sec; ++#endif ++ } tv; ++#endif ++}; ++#define kmemcheck_bitfield_begin(name) ++#define kmemcheck_bitfield_end(name) ++#define CHECKSUM_NONE 0 ++typedef unsigned char *sk_buff_data_t; ++typedef union ktime ktime_t; /* Kill this */ ++ ++void rtw_mtx_lock(_lock *plock); ++ ++void rtw_mtx_unlock(_lock *plock); ++ ++/** ++ * struct sk_buff - socket buffer ++ * @next: Next buffer in list ++ * @prev: Previous buffer in list ++ * @sk: Socket we are owned by ++ * @tstamp: Time we arrived ++ * @dev: Device we arrived on/are leaving by ++ * @transport_header: Transport layer header ++ * @network_header: Network layer header ++ * @mac_header: Link layer header ++ * @_skb_refdst: destination entry (with norefcount bit) ++ * @sp: the security path, used for xfrm ++ * @cb: Control buffer. Free for use by every layer. Put private vars here ++ * @len: Length of actual data ++ * @data_len: Data length ++ * @mac_len: Length of link layer header ++ * @hdr_len: writable header length of cloned skb ++ * @csum: Checksum (must include start/offset pair) ++ * @csum_start: Offset from skb->head where checksumming should start ++ * @csum_offset: Offset from csum_start where checksum should be stored ++ * @local_df: allow local fragmentation ++ * @cloned: Head may be cloned (check refcnt to be sure) ++ * @nohdr: Payload reference only, must not modify header ++ * @pkt_type: Packet class ++ * @fclone: skbuff clone status ++ * @ip_summed: Driver fed us an IP checksum ++ * @priority: Packet queueing priority ++ * @users: User count - see {datagram,tcp}.c ++ * @protocol: Packet protocol from driver ++ * @truesize: Buffer size ++ * @head: Head of buffer ++ * @data: Data head pointer ++ * @tail: Tail pointer ++ * @end: End pointer ++ * @destructor: Destruct function ++ * @mark: Generic packet mark ++ * @nfct: Associated connection, if any ++ * @ipvs_property: skbuff is owned by ipvs ++ * @peeked: this packet has been seen already, so stats have been ++ * done for it, don't do them again ++ * @nf_trace: netfilter packet trace flag ++ * @nfctinfo: Relationship of this skb to the connection ++ * @nfct_reasm: netfilter conntrack re-assembly pointer ++ * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c ++ * @skb_iif: ifindex of device we arrived on ++ * @rxhash: the packet hash computed on receive ++ * @queue_mapping: Queue mapping for multiqueue devices ++ * @tc_index: Traffic control index ++ * @tc_verd: traffic control verdict ++ * @ndisc_nodetype: router type (from link layer) ++ * @dma_cookie: a cookie to one of several possible DMA operations ++ * done by skb DMA functions ++ * @secmark: security marking ++ * @vlan_tci: vlan tag control information ++ */ ++ ++struct sk_buff { ++ /* These two members must be first. */ ++ struct sk_buff *next; ++ struct sk_buff *prev; ++ ++ ktime_t tstamp; ++ ++ struct sock *sk; ++ //struct net_device *dev; ++ struct ifnet *dev; ++ ++ /* ++ * This is the control buffer. It is free to use for every ++ * layer. Please put your private variables there. If you ++ * want to keep them across layers you have to do a skb_clone() ++ * first. This is owned by whoever has the skb queued ATM. ++ */ ++ char cb[48] __aligned(8); ++ ++ unsigned long _skb_refdst; ++#ifdef CONFIG_XFRM ++ struct sec_path *sp; ++#endif ++ unsigned int len, ++ data_len; ++ u16 mac_len, ++ hdr_len; ++ union { ++ u32 csum; ++ struct { ++ u16 csum_start; ++ u16 csum_offset; ++ }smbol2; ++ }smbol1; ++ u32 priority; ++ kmemcheck_bitfield_begin(flags1); ++ u8 local_df:1, ++ cloned:1, ++ ip_summed:2, ++ nohdr:1, ++ nfctinfo:3; ++ u8 pkt_type:3, ++ fclone:2, ++ ipvs_property:1, ++ peeked:1, ++ nf_trace:1; ++ kmemcheck_bitfield_end(flags1); ++ u16 protocol; ++ ++ void (*destructor)(struct sk_buff *skb); ++#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) ++ struct nf_conntrack *nfct; ++ struct sk_buff *nfct_reasm; ++#endif ++#ifdef CONFIG_BRIDGE_NETFILTER ++ struct nf_bridge_info *nf_bridge; ++#endif ++ ++ int skb_iif; ++#ifdef CONFIG_NET_SCHED ++ u16 tc_index; /* traffic control index */ ++#ifdef CONFIG_NET_CLS_ACT ++ u16 tc_verd; /* traffic control verdict */ ++#endif ++#endif ++ ++ u32 rxhash; ++ ++ kmemcheck_bitfield_begin(flags2); ++ u16 queue_mapping:16; ++#ifdef CONFIG_IPV6_NDISC_NODETYPE ++ u8 ndisc_nodetype:2, ++ deliver_no_wcard:1; ++#else ++ u8 deliver_no_wcard:1; ++#endif ++ kmemcheck_bitfield_end(flags2); ++ ++ /* 0/14 bit hole */ ++ ++#ifdef CONFIG_NET_DMA ++ dma_cookie_t dma_cookie; ++#endif ++#ifdef CONFIG_NETWORK_SECMARK ++ u32 secmark; ++#endif ++ union { ++ u32 mark; ++ u32 dropcount; ++ }symbol3; ++ ++ u16 vlan_tci; ++ ++ sk_buff_data_t transport_header; ++ sk_buff_data_t network_header; ++ sk_buff_data_t mac_header; ++ /* These elements must be at the end, see alloc_skb() for details. */ ++ sk_buff_data_t tail; ++ sk_buff_data_t end; ++ unsigned char *head, ++ *data; ++ unsigned int truesize; ++ atomic_t users; ++}; ++struct sk_buff_head { ++ /* These two members must be first. */ ++ struct sk_buff *next; ++ struct sk_buff *prev; ++ ++ u32 qlen; ++ _lock lock; ++}; ++#define skb_tail_pointer(skb) skb->tail ++static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) ++{ ++ unsigned char *tmp = skb_tail_pointer(skb); ++ //SKB_LINEAR_ASSERT(skb); ++ skb->tail += len; ++ skb->len += len; ++ return tmp; ++} ++ ++static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) ++{ ++ skb->len -= len; ++ if(skb->len < skb->data_len) ++ printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); ++ return skb->data += len; ++} ++static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) ++{ ++ #ifdef PLATFORM_FREEBSD ++ return __skb_pull(skb, len); ++ #else ++ return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); ++ #endif //PLATFORM_FREEBSD ++} ++static inline u32 skb_queue_len(const struct sk_buff_head *list_) ++{ ++ return list_->qlen; ++} ++static inline void __skb_insert(struct sk_buff *newsk, ++ struct sk_buff *prev, struct sk_buff *next, ++ struct sk_buff_head *list) ++{ ++ newsk->next = next; ++ newsk->prev = prev; ++ next->prev = prev->next = newsk; ++ list->qlen++; ++} ++static inline void __skb_queue_before(struct sk_buff_head *list, ++ struct sk_buff *next, ++ struct sk_buff *newsk) ++{ ++ __skb_insert(newsk, next->prev, next, list); ++} ++static inline void skb_queue_tail(struct sk_buff_head *list, ++ struct sk_buff *newsk) ++{ ++ mtx_lock(&list->lock); ++ __skb_queue_before(list, (struct sk_buff *)list, newsk); ++ mtx_unlock(&list->lock); ++} ++static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) ++{ ++ struct sk_buff *list = ((struct sk_buff *)list_)->next; ++ if (list == (struct sk_buff *)list_) ++ list = NULL; ++ return list; ++} ++static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) ++{ ++ struct sk_buff *next, *prev; ++ ++ list->qlen--; ++ next = skb->next; ++ prev = skb->prev; ++ skb->next = skb->prev = NULL; ++ next->prev = prev; ++ prev->next = next; ++} ++ ++static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) ++{ ++ mtx_lock(&list->lock); ++ ++ struct sk_buff *skb = skb_peek(list); ++ if (skb) ++ __skb_unlink(skb, list); ++ ++ mtx_unlock(&list->lock); ++ ++ return skb; ++} ++static inline void skb_reserve(struct sk_buff *skb, int len) ++{ ++ skb->data += len; ++ skb->tail += len; ++} ++static inline void __skb_queue_head_init(struct sk_buff_head *list) ++{ ++ list->prev = list->next = (struct sk_buff *)list; ++ list->qlen = 0; ++} ++/* ++ * This function creates a split out lock class for each invocation; ++ * this is needed for now since a whole lot of users of the skb-queue ++ * infrastructure in drivers have different locking usage (in hardirq) ++ * than the networking core (in softirq only). In the long run either the ++ * network layer or drivers should need annotation to consolidate the ++ * main types of usage into 3 classes. ++ */ ++static inline void skb_queue_head_init(struct sk_buff_head *list) ++{ ++ _rtw_spinlock_init(&list->lock); ++ __skb_queue_head_init(list); ++} ++unsigned long copy_from_user(void *to, const void *from, unsigned long n); ++unsigned long copy_to_user(void *to, const void *from, unsigned long n); ++struct sk_buff * dev_alloc_skb(unsigned int size); ++struct sk_buff *skb_clone(const struct sk_buff *skb); ++void dev_kfree_skb_any(struct sk_buff *skb); ++#endif //Baron porting from linux, it's all temp solution, needs to check again ++ ++ ++#if 1 // kenny add Linux compatibility code for Linux USB driver ++#include ++ ++#define __init // __attribute ((constructor)) ++#define __exit // __attribute ((destructor)) ++ ++/* ++ * Definitions for module_init and module_exit macros. ++ * ++ * These macros will use the SYSINIT framework to call a specified ++ * function (with no arguments) on module loading or unloading. ++ * ++ */ ++ ++void module_init_exit_wrapper(void *arg); ++ ++#define module_init(initfn) \ ++ SYSINIT(mod_init_ ## initfn, \ ++ SI_SUB_KLD, SI_ORDER_FIRST, \ ++ module_init_exit_wrapper, initfn) ++ ++#define module_exit(exitfn) \ ++ SYSUNINIT(mod_exit_ ## exitfn, \ ++ SI_SUB_KLD, SI_ORDER_ANY, \ ++ module_init_exit_wrapper, exitfn) ++ ++/* ++ * The usb_register and usb_deregister functions are used to register ++ * usb drivers with the usb subsystem. ++ */ ++int usb_register(struct usb_driver *driver); ++int usb_deregister(struct usb_driver *driver); ++ ++/* ++ * usb_get_dev and usb_put_dev - increment/decrement the reference count ++ * of the usb device structure. ++ * ++ * Original body of usb_get_dev: ++ * ++ * if (dev) ++ * get_device(&dev->dev); ++ * return dev; ++ * ++ * Reference counts are not currently used in this compatibility ++ * layer. So these functions will do nothing. ++ */ ++static inline struct usb_device * ++usb_get_dev(struct usb_device *dev) ++{ ++ return dev; ++} ++ ++static inline void ++usb_put_dev(struct usb_device *dev) ++{ ++ return; ++} ++ ++ ++// rtw_usb_compat_linux ++int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); ++int rtw_usb_unlink_urb(struct urb *urb); ++int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); ++int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, ++ uint8_t request, uint8_t requesttype, ++ uint16_t value, uint16_t index, void *data, ++ uint16_t size, usb_timeout_t timeout); ++int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); ++int rtw_usb_setup_endpoint(struct usb_device *dev, ++ struct usb_host_endpoint *uhe, usb_size_t bufsize); ++struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); ++struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); ++struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); ++struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); ++void *rtw_usb_buffer_alloc(struct usb_device *dev, usb_size_t size, uint8_t *dma_addr); ++void *rtw_usbd_get_intfdata(struct usb_interface *intf); ++void rtw_usb_linux_register(void *arg); ++void rtw_usb_linux_deregister(void *arg); ++void rtw_usb_linux_free_device(struct usb_device *dev); ++void rtw_usb_buffer_free(struct usb_device *dev, usb_size_t size, ++ void *addr, uint8_t dma_addr); ++void rtw_usb_free_urb(struct urb *urb); ++void rtw_usb_init_urb(struct urb *urb); ++void rtw_usb_kill_urb(struct urb *urb); ++void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); ++void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, ++ struct usb_host_endpoint *uhe, void *buf, ++ int length, usb_complete_t callback, void *arg); ++int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, ++ void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); ++void *usb_get_intfdata(struct usb_interface *intf); ++int usb_linux_init_endpoints(struct usb_device *udev); ++ ++ ++ ++typedef struct urb * PURB; ++ ++typedef unsigned gfp_t; ++#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ ++#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ ++#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ ++#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ ++#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ ++#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ ++#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ ++#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ ++#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ ++#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ ++#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ ++#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ ++#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ ++#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ ++ ++/* This equals 0, but use constants in case they ever change */ ++#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) ++/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ ++#define GFP_ATOMIC (__GFP_HIGH) ++#define GFP_NOIO (__GFP_WAIT) ++#define GFP_NOFS (__GFP_WAIT | __GFP_IO) ++#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) ++#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) ++#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ ++ __GFP_HIGHMEM) ++ ++ ++#endif // kenny add Linux compatibility code for Linux USB ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->next; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++ ++#define LIST_CONTAINOR(ptr, type, member) \ ++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) ++ ++ ++__inline static void _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_bh(plock, *pirqL); ++} ++ ++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_bh(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ ++ mtx_lock(pmutex); ++ ++} ++ ++ ++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ ++ mtx_unlock(pmutex); ++ ++} ++static inline void __list_del(struct list_head * prev, struct list_head * next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++static inline void INIT_LIST_HEAD(struct list_head *list) ++{ ++ list->next = list; ++ list->prev = list; ++} ++__inline static void rtw_list_delete(_list *plist) ++{ ++ __list_del(plist->prev, plist->next); ++ INIT_LIST_HEAD(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl padapter,void *pfunc,void* cntx) ++{ ++ ptimer->function = pfunc; ++ ptimer->arg = cntx; ++ callout_init(&ptimer->callout, CALLOUT_MPSAFE); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ // mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); ++ if(ptimer->function && ptimer->arg){ ++ rtw_mtx_lock(NULL); ++ callout_reset(&ptimer->callout, delay_time,ptimer->function, ptimer->arg); ++ rtw_mtx_unlock(NULL); ++ } ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ // del_timer_sync(ptimer); ++ // *bcancelled= _TRUE;//TRUE ==1; FALSE==0 ++ rtw_mtx_lock(NULL); ++ callout_drain(&ptimer->callout); ++ rtw_mtx_unlock(NULL); ++} ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++ printf("%s Not implement yet! \n",__FUNCTION__); ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ printf("%s Not implement yet! \n",__FUNCTION__); ++// schedule_work(pwork); ++} ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++} ++ ++#define ATOMIC_INIT(i) { (i) } ++ ++#endif //PLATFORM_FREEBSD ++ ++ ++#ifdef PLATFORM_LINUX ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5)) ++ #include ++#endif ++ //#include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ #include ++#else ++ #include ++#endif ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include // Necessary because we use the proc fs ++ #include // for struct tasklet_struct ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++// #include ++ #include ++ #include ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ #include ++ #include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ #include ++#else ++ #include ++#endif ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ #include ++#endif ++ ++ ++#ifdef CONFIG_USB_HCI ++ typedef struct urb * PURB; ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) ++#ifdef CONFIG_USB_SUSPEND ++#define CONFIG_AUTOSUSPEND 1 ++#endif ++#endif ++#endif ++ ++ typedef struct semaphore _sema; ++ typedef spinlock_t _lock; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ typedef struct mutex _mutex; ++#else ++ typedef struct semaphore _mutex; ++#endif ++ typedef struct timer_list _timer; ++ ++ struct __queue { ++ struct list_head queue; ++ _lock lock; ++ }; ++ ++ typedef struct sk_buff _pkt; ++ typedef unsigned char _buffer; ++ ++ typedef struct __queue _queue; ++ typedef struct list_head _list; ++ typedef int _OS_STATUS; ++ //typedef u32 _irqL; ++ typedef unsigned long _irqL; ++ typedef struct net_device * _nic_hdl; ++ ++ typedef void* _thread_hdl_; ++ typedef int thread_return; ++ typedef void* thread_context; ++ ++ #define thread_exit() complete_and_exit(NULL, 0) ++ ++ typedef void timer_hdl_return; ++ typedef void* timer_hdl_context; ++ typedef struct work_struct _workitem; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) ++// Porting from linux kernel, for compatible with old kernel. ++static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) ++{ ++ return skb->tail; ++} ++ ++static inline void skb_reset_tail_pointer(struct sk_buff *skb) ++{ ++ skb->tail = skb->data; ++} ++ ++static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) ++{ ++ skb->tail = skb->data + offset; ++} ++ ++static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) ++{ ++ return skb->end; ++} ++#endif ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->next; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++ ++#define LIST_CONTAINOR(ptr, type, member) \ ++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) ++ ++ ++__inline static void _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_bh(plock); ++} ++ ++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_bh(plock); ++} ++ ++__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ int ret = 0; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ //mutex_lock(pmutex); ++ ret = mutex_lock_interruptible(pmutex); ++#else ++ ret = down_interruptible(pmutex); ++#endif ++ return ret; ++} ++ ++ ++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_unlock(pmutex); ++#else ++ up(pmutex); ++#endif ++} ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ list_del_init(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx) ++{ ++ //setup_timer(ptimer, pfunc,(u32)cntx); ++ ptimer->function = pfunc; ++ ptimer->data = (unsigned long)cntx; ++ init_timer(ptimer); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ del_timer_sync(ptimer); ++ *bcancelled= _TRUE;//TRUE ==1; FALSE==0 ++} ++ ++#ifdef PLATFORM_LINUX ++#define RTW_TIMER_HDL_ARGS void *FunctionContext ++#elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS) ++#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 ++#endif ++ ++#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl ++#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) ++ ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++ INIT_WORK(pwork, pfunc); ++#else ++ INIT_WORK(pwork, pfunc,pwork); ++#endif ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ schedule_work(pwork); ++} ++ ++__inline static void _cancel_workitem_sync(_workitem *pwork) ++{ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) ++ cancel_work_sync(pwork); ++#else ++ flush_scheduled_work(); ++#endif ++} ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\ ++ { \ ++ atomic_dec((atomic_t *)&(_MutexCounter)); \ ++ msleep(10); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ atomic_dec((atomic_t *)&(_MutexCounter)); \ ++} ++ ++static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) ++{ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && ++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && ++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && ++ netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) ); ++#else ++ return netif_queue_stopped(pnetdev); ++#endif ++} ++ ++static inline void rtw_netif_wake_queue(struct net_device *pnetdev) ++{ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ netif_tx_wake_all_queues(pnetdev); ++#else ++ netif_wake_queue(pnetdev); ++#endif ++} ++ ++static inline void rtw_netif_start_queue(struct net_device *pnetdev) ++{ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ netif_tx_start_all_queues(pnetdev); ++#else ++ netif_start_queue(pnetdev); ++#endif ++} ++ ++static inline void rtw_netif_stop_queue(struct net_device *pnetdev) ++{ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ netif_tx_stop_all_queues(pnetdev); ++#else ++ netif_stop_queue(pnetdev); ++#endif ++} ++ ++#endif // PLATFORM_LINUX ++ ++ ++#ifdef PLATFORM_OS_XP ++ ++ #include ++ #include ++ #include ++ #include ++ ++#ifdef CONFIG_USB_HCI ++ #include ++ #include ++ #include ++#endif ++ ++ typedef KSEMAPHORE _sema; ++ typedef LIST_ENTRY _list; ++ typedef NDIS_STATUS _OS_STATUS; ++ ++ ++ typedef NDIS_SPIN_LOCK _lock; ++ ++ typedef KMUTEX _mutex; ++ ++ typedef KIRQL _irqL; ++ ++ // USB_PIPE for WINCE , but handle can be use just integer under windows ++ typedef NDIS_HANDLE _nic_hdl; ++ ++ ++ typedef NDIS_MINIPORT_TIMER _timer; ++ ++ struct __queue { ++ LIST_ENTRY queue; ++ _lock lock; ++ }; ++ ++ typedef NDIS_PACKET _pkt; ++ typedef NDIS_BUFFER _buffer; ++ typedef struct __queue _queue; ++ ++ typedef PKTHREAD _thread_hdl_; ++ typedef void thread_return; ++ typedef void* thread_context; ++ ++ typedef NDIS_WORK_ITEM _workitem; ++ ++ #define thread_exit() PsTerminateSystemThread(STATUS_SUCCESS); ++ ++ #define HZ 10000000 ++ #define SEMA_UPBND (0x7FFFFFFF) //8192 ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->Flink; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++ ++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) ++ ++ ++__inline static _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisReleaseSpinLock(plock); ++} ++ ++ ++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); ++} ++ ++ ++__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ KeReleaseMutex(pmutex, FALSE); ++} ++ ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ RemoveEntryList(plist); ++ InitializeListHead(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) ++{ ++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ NdisMSetTimer(ptimer,delay_time); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ NdisMCancelTimer(ptimer,bcancelled); ++} ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++ ++ NdisInitializeWorkItem(pwork, pfunc, cntx); ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ NdisScheduleWorkItem(pwork); ++} ++ ++ ++#define ATOMIC_INIT(i) { (i) } ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ ++ { \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++ NdisMSleep(10000); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++} ++ ++#endif // PLATFORM_OS_XP ++ ++ ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++#include ++ ++#ifndef BIT ++ #define BIT(x) ( 1 << (x)) ++#endif ++ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++#define BIT32 0x0100000000 ++#define BIT33 0x0200000000 ++#define BIT34 0x0400000000 ++#define BIT35 0x0800000000 ++#define BIT36 0x1000000000 ++ ++extern int RTW_STATUS_CODE(int error_code); ++ ++//#define CONFIG_USE_VMALLOC ++ ++/* flags used for rtw_mstat_update() */ ++enum mstat_f { ++ /* type: 0x00ff */ ++ MSTAT_TYPE_VIR = 0x00, ++ MSTAT_TYPE_PHY= 0x01, ++ MSTAT_TYPE_SKB = 0x02, ++ MSTAT_TYPE_USB = 0x03, ++ MSTAT_TYPE_MAX = 0x04, ++ ++ /* func: 0xff00 */ ++ MSTAT_FUNC_UNSPECIFIED = 0x00<<8, ++ MSTAT_FUNC_IO = 0x01<<8, ++ MSTAT_FUNC_TX_IO = 0x02<<8, ++ MSTAT_FUNC_RX_IO = 0x03<<8, ++ MSTAT_FUNC_TX = 0x04<<8, ++ MSTAT_FUNC_RX = 0x05<<8, ++ MSTAT_FUNC_MAX = 0x06<<8, ++}; ++ ++#define mstat_tf_idx(flags) ((flags)&0xff) ++#define mstat_ff_idx(flags) (((flags)&0xff00) >> 8) ++ ++typedef enum mstat_status{ ++ MSTAT_ALLOC_SUCCESS = 0, ++ MSTAT_ALLOC_FAIL, ++ MSTAT_FREE ++} MSTAT_STATUS; ++ ++#ifdef DBG_MEM_ALLOC ++void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); ++int _rtw_mstat_dump(char *buf, int len); ++void rtw_mstat_dump (void); ++u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); ++u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); ++void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); ++u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); ++u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); ++void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); ++ ++struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); ++void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); ++struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); ++struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); ++int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); ++void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line); ++ ++#ifdef CONFIG_USB_HCI ++void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line); ++void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line); ++#endif /* CONFIG_USB_HCI */ ++ ++#ifdef CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) ++#else /* CONFIG_USE_VMALLOC */ ++#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#endif /* CONFIG_USE_VMALLOC */ ++#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) ++ ++#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) ++#ifdef CONFIG_USB_HCI ++#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) ++#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) ++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__) ++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__) ++#endif /* CONFIG_USB_HCI */ ++ ++#else /* DBG_MEM_ALLOC */ ++#define rtw_mstat_update(flag, status, sz) do {} while(0) ++#define rtw_mstat_dump() do {} while(0) ++u8* _rtw_vmalloc(u32 sz); ++u8* _rtw_zvmalloc(u32 sz); ++void _rtw_vmfree(u8 *pbuf, u32 sz); ++u8* _rtw_zmalloc(u32 sz); ++u8* _rtw_malloc(u32 sz); ++void _rtw_mfree(u8 *pbuf, u32 sz); ++ ++struct sk_buff *_rtw_skb_alloc(u32 sz); ++void _rtw_skb_free(struct sk_buff *skb); ++struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); ++struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); ++int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); ++void _rtw_skb_queue_purge(struct sk_buff_head *list); ++ ++#ifdef CONFIG_USB_HCI ++void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma); ++void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); ++#endif /* CONFIG_USB_HCI */ ++ ++#ifdef CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) ++#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) ++#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) ++#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) ++#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) ++#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) ++#else /* CONFIG_USE_VMALLOC */ ++#define rtw_vmalloc(sz) _rtw_malloc((sz)) ++#define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) ++#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) ++#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) ++#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) ++#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) ++#endif /* CONFIG_USE_VMALLOC */ ++#define rtw_malloc(sz) _rtw_malloc((sz)) ++#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) ++#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) ++#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) ++#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) ++#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) ++ ++#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) ++#define rtw_skb_free(skb) _rtw_skb_free((skb)) ++#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) ++#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) ++#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) ++#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) ++#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) ++#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) ++#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) ++#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head) ++#ifdef CONFIG_USB_HCI ++#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma)) ++#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) ++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma)) ++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) ++#endif /* CONFIG_USB_HCI */ ++#endif /* DBG_MEM_ALLOC */ ++ ++extern void* rtw_malloc2d(int h, int w, int size); ++extern void rtw_mfree2d(void *pbuf, int h, int w, int size); ++ ++extern void _rtw_memcpy(void* dec, void* sour, u32 sz); ++extern int _rtw_memcmp(void *dst, void *src, u32 sz); ++extern void _rtw_memset(void *pbuf, int c, u32 sz); ++ ++extern void _rtw_init_listhead(_list *list); ++extern u32 rtw_is_list_empty(_list *phead); ++extern void rtw_list_insert_head(_list *plist, _list *phead); ++extern void rtw_list_insert_tail(_list *plist, _list *phead); ++#ifndef PLATFORM_FREEBSD ++extern void rtw_list_delete(_list *plist); ++#endif //PLATFORM_FREEBSD ++ ++extern void _rtw_init_sema(_sema *sema, int init_val); ++extern void _rtw_free_sema(_sema *sema); ++extern void _rtw_up_sema(_sema *sema); ++extern u32 _rtw_down_sema(_sema *sema); ++extern void _rtw_mutex_init(_mutex *pmutex); ++extern void _rtw_mutex_free(_mutex *pmutex); ++#ifndef PLATFORM_FREEBSD ++extern void _rtw_spinlock_init(_lock *plock); ++#endif //PLATFORM_FREEBSD ++extern void _rtw_spinlock_free(_lock *plock); ++extern void _rtw_spinlock(_lock *plock); ++extern void _rtw_spinunlock(_lock *plock); ++extern void _rtw_spinlock_ex(_lock *plock); ++extern void _rtw_spinunlock_ex(_lock *plock); ++ ++extern void _rtw_init_queue(_queue *pqueue); ++extern u32 _rtw_queue_empty(_queue *pqueue); ++extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); ++ ++extern u32 rtw_get_current_time(void); ++extern u32 rtw_systime_to_ms(u32 systime); ++extern u32 rtw_ms_to_systime(u32 ms); ++extern s32 rtw_get_passing_time_ms(u32 start); ++extern s32 rtw_get_time_interval_ms(u32 start, u32 end); ++ ++extern void rtw_sleep_schedulable(int ms); ++ ++extern void rtw_msleep_os(int ms); ++extern void rtw_usleep_os(int us); ++ ++extern u32 rtw_atoi(u8* s); ++ ++#ifdef DBG_DELAY_OS ++#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) ++#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) ++extern void _rtw_mdelay_os(int ms, const char *func, const int line); ++extern void _rtw_udelay_os(int us, const char *func, const int line); ++#else ++extern void rtw_mdelay_os(int ms); ++extern void rtw_udelay_os(int us); ++#endif ++ ++extern void rtw_yield_os(void); ++ ++ ++__inline static unsigned char _cancel_timer_ex(_timer *ptimer) ++{ ++#ifdef PLATFORM_LINUX ++ return del_timer_sync(ptimer); ++#endif ++#ifdef PLATFORM_FREEBSD ++ _cancel_timer(ptimer,0); ++ return 0; ++#endif ++#ifdef PLATFORM_WINDOWS ++ u8 bcancelled; ++ ++ _cancel_timer(ptimer, &bcancelled); ++ ++ return bcancelled; ++#endif ++} ++ ++#ifdef PLATFORM_FREEBSD ++static __inline void thread_enter(char *name); ++#endif //PLATFORM_FREEBSD ++static __inline void thread_enter(char *name) ++{ ++#ifdef PLATFORM_LINUX ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) ++ daemonize("%s", name); ++ #endif ++ allow_signal(SIGTERM); ++#endif ++#ifdef PLATFORM_FREEBSD ++ printf("%s", "RTKTHREAD_enter"); ++#endif ++} ++ ++#ifdef PLATFORM_FREEBSD ++#define thread_exit() do{printf("%s", "RTKTHREAD_exit");}while(0) ++#endif //PLATFORM_FREEBSD ++__inline static void flush_signals_thread(void) ++{ ++#ifdef PLATFORM_LINUX ++ if (signal_pending (current)) ++ { ++ flush_signals(current); ++ } ++#endif ++} ++ ++__inline static _OS_STATUS res_to_status(sint res) ++{ ++ ++ ++#if defined (PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD) ++ return res; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ if (res == _SUCCESS) ++ return NDIS_STATUS_SUCCESS; ++ else ++ return NDIS_STATUS_FAILURE; ++ ++#endif ++ ++} ++ ++__inline static void rtw_dump_stack(void) ++{ ++#ifdef PLATFORM_LINUX ++ dump_stack(); ++#endif ++} ++ ++#ifdef PLATFORM_LINUX ++#define rtw_warn_on(condition) WARN_ON(condition) ++#else ++#define rtw_warn_on(condition) do {} while (0) ++#endif ++ ++#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) ++#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) ++ ++__inline static u32 _RND4(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND8(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND128(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND256(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND512(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; ++ ++ return val; ++ ++} ++ ++__inline static u32 bitshift(u32 bitmask) ++{ ++ u32 i; ++ ++ for (i = 0; i <= 31; i++) ++ if (((bitmask>>i) & 0x1) == 1) break; ++ ++ return i; ++} ++ ++#ifndef MAC_FMT ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#endif ++#ifndef MAC_ARG ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++#endif ++ ++//#ifdef __GNUC__ ++#ifdef PLATFORM_LINUX ++#define STRUCT_PACKED __attribute__ ((packed)) ++#else ++#define STRUCT_PACKED ++#endif ++ ++ ++// limitation of path length ++#ifdef PLATFORM_LINUX ++ #define PATH_LENGTH_MAX PATH_MAX ++#elif defined(PLATFORM_WINDOWS) ++ #define PATH_LENGTH_MAX MAX_PATH ++#endif ++ ++ ++// Suspend lock prevent system from going suspend ++#ifdef CONFIG_WAKELOCK ++#include ++#elif defined(CONFIG_ANDROID_POWER) ++#include ++#endif ++ ++extern void rtw_suspend_lock_init(void); ++extern void rtw_suspend_lock_uninit(void); ++extern void rtw_lock_suspend(void); ++extern void rtw_unlock_suspend(void); ++extern void rtw_lock_suspend_timeout(u32 timeout_ms); ++extern void rtw_lock_ext_suspend_timeout(u32 timeout_ms); ++ ++ ++//Atomic integer operations ++#ifdef PLATFORM_LINUX ++ #define ATOMIC_T atomic_t ++#elif defined(PLATFORM_WINDOWS) ++ #define ATOMIC_T LONG ++#elif defined(PLATFORM_FREEBSD) ++ typedef uint32_t ATOMIC_T ; ++#endif ++ ++extern void ATOMIC_SET(ATOMIC_T *v, int i); ++extern int ATOMIC_READ(ATOMIC_T *v); ++extern void ATOMIC_ADD(ATOMIC_T *v, int i); ++extern void ATOMIC_SUB(ATOMIC_T *v, int i); ++extern void ATOMIC_INC(ATOMIC_T *v); ++extern void ATOMIC_DEC(ATOMIC_T *v); ++extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); ++extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); ++extern int ATOMIC_INC_RETURN(ATOMIC_T *v); ++extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); ++ ++//File operation APIs, just for linux now ++extern int rtw_is_file_readable(char *path); ++extern int rtw_retrive_from_file(char *path, u8* buf, u32 sz); ++extern int rtw_store_to_file(char *path, u8* buf, u32 sz); ++ ++ ++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR ++struct rtw_netdev_priv_indicator { ++ void *priv; ++ u32 sizeof_priv; ++}; ++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); ++extern struct net_device * rtw_alloc_etherdev(int sizeof_priv); ++ ++#ifndef PLATFORM_FREEBSD ++#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv ) ++#else //PLATFORM_FREEBSD ++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) ++#endif //PLATFORM_FREEBSD ++ ++#ifndef PLATFORM_FREEBSD ++extern void rtw_free_netdev(struct net_device * netdev); ++#else //PLATFORM_FREEBSD ++#define rtw_free_netdev(netdev) if_free((netdev)) ++#endif //PLATFORM_FREEBSD ++ ++#else //MEM_ALLOC_REFINE_ADAPTOR ++ ++#define rtw_alloc_etherdev(sizeof_priv) alloc_etherdev((sizeof_priv)) ++ ++#ifndef PLATFORM_FREEBSD ++#define rtw_netdev_priv(netdev) netdev_priv((netdev)) ++#define rtw_free_netdev(netdev) free_netdev((netdev)) ++#else //PLATFORM_FREEBSD ++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) ++#define rtw_free_netdev(netdev) if_free((netdev)) ++#endif //PLATFORM_FREEBSD ++#endif ++ ++#ifdef PLATFORM_LINUX ++#define NDEV_FMT "%s" ++#define NDEV_ARG(ndev) ndev->name ++#define ADPT_FMT "%s" ++#define ADPT_ARG(adapter) adapter->pnetdev->name ++#define FUNC_NDEV_FMT "%s(%s)" ++#define FUNC_NDEV_ARG(ndev) __func__, ndev->name ++#define FUNC_ADPT_FMT "%s(%s)" ++#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name ++#else ++#define NDEV_FMT "%s" ++#define NDEV_ARG(ndev) "" ++#define ADPT_FMT "%s" ++#define ADPT_ARG(adapter) "" ++#define FUNC_NDEV_FMT "%s" ++#define FUNC_NDEV_ARG(ndev) __func__ ++#define FUNC_ADPT_FMT "%s" ++#define FUNC_ADPT_ARG(adapter) __func__ ++#endif ++ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) ++#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) ++#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) ++#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) ++#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) ++#endif //PLATFORM_LINUX ++ ++extern u64 rtw_modular64(u64 x, u64 y); ++extern u64 rtw_division64(u64 x, u64 y); ++ ++ ++/* Macros for handling unaligned memory accesses */ ++ ++#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) ++#define RTW_PUT_BE16(a, val) \ ++ do { \ ++ (a)[0] = ((u16) (val)) >> 8; \ ++ (a)[1] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) ++#define RTW_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ ++ ((u32) (a)[2])) ++#define RTW_PUT_BE24(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[2] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ ++ (((u32) (a)[2]) << 8) | ((u32) (a)[3])) ++#define RTW_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ ++ (((u32) (a)[1]) << 8) | ((u32) (a)[0])) ++#define RTW_PUT_LE32(a, val) \ ++ do { \ ++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[0] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ ++ (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ ++ (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ ++ (((u64) (a)[6]) << 8) | ((u64) (a)[7])) ++#define RTW_PUT_BE64(a, val) \ ++ do { \ ++ (a)[0] = (u8) (((u64) (val)) >> 56); \ ++ (a)[1] = (u8) (((u64) (val)) >> 48); \ ++ (a)[2] = (u8) (((u64) (val)) >> 40); \ ++ (a)[3] = (u8) (((u64) (val)) >> 32); \ ++ (a)[4] = (u8) (((u64) (val)) >> 24); \ ++ (a)[5] = (u8) (((u64) (val)) >> 16); \ ++ (a)[6] = (u8) (((u64) (val)) >> 8); \ ++ (a)[7] = (u8) (((u64) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ ++ (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ ++ (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ ++ (((u64) (a)[1]) << 8) | ((u64) (a)[0])) ++ ++void rtw_buf_free(u8 **buf, u32 *buf_len); ++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); ++ ++struct rtw_cbuf { ++ u32 write; ++ u32 read; ++ u32 size; ++ void *bufs[0]; ++}; ++ ++bool rtw_cbuf_full(struct rtw_cbuf *cbuf); ++bool rtw_cbuf_empty(struct rtw_cbuf *cbuf); ++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf); ++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf); ++struct rtw_cbuf *rtw_cbuf_alloc(u32 size); ++void rtw_cbuf_free(struct rtw_cbuf *cbuf); ++ ++#endif ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/pci_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/pci_hal.h +new file mode 100644 +index 00000000..b6c95c2f +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/pci_hal.h +@@ -0,0 +1,177 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_HAL_H__ ++#define __PCI_HAL_H__ ++ ++ ++#define INTEL_VENDOR_ID 0x8086 ++#define SIS_VENDOR_ID 0x1039 ++#define ATI_VENDOR_ID 0x1002 ++#define ATI_DEVICE_ID 0x7914 ++#define AMD_VENDOR_ID 0x1022 ++ ++#define PCI_MAX_BRIDGE_NUMBER 255 ++#define PCI_MAX_DEVICES 32 ++#define PCI_MAX_FUNCTION 8 ++ ++#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address ++#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data ++ ++#define PCI_CLASS_BRIDGE_DEV 0x06 ++#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 ++ ++#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 ++ ++#define U1DONTCARE 0xFF ++#define U2DONTCARE 0xFFFF ++#define U4DONTCARE 0xFFFFFFFF ++ ++#define PCI_VENDER_ID_REALTEK 0x10ec ++ ++#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 ++#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b ++#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b ++#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b ++#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190 ++#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E ++#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E ++#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE ++#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE ++#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab ++#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE ++#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron ++#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga ++#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga ++#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga ++#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga ++#define HAL_HW_PCI_700F_DEVICE_ID 0x700F ++#define HAL_HW_PCI_701F_DEVICE_ID 0x701F ++#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 ++#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce ++#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce ++#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce ++#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce ++#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce ++#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de ++#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD ++#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179 ++ ++#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 ++#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers ++ ++enum pci_bridge_vendor { ++ PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001 ++ PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010 ++ PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100 ++ PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000 ++ PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000 ++ PCI_BRIDGE_VENDOR_MAX ,//= 0x80 ++} ; ++ ++struct rt_pci_capabilities_header { ++ u8 capability_id; ++ u8 next; ++}; ++ ++struct pci_priv{ ++ u8 linkctrl_reg; ++ ++ u8 busnumber; ++ u8 devnumber; ++ u8 funcnumber; ++ ++ u8 pcibridge_busnum; ++ u8 pcibridge_devnum; ++ u8 pcibridge_funcnum; ++ u8 pcibridge_vendor; ++ u16 pcibridge_vendorid; ++ u16 pcibridge_deviceid; ++ u8 pcibridge_pciehdr_offset; ++ u8 pcibridge_linkctrlreg; ++ ++ u8 amd_l1_patch; ++}; ++ ++typedef struct _RT_ISR_CONTENT ++{ ++ union{ ++ u32 IntArray[2]; ++ u32 IntReg4Byte; ++ u16 IntReg2Byte; ++ }; ++}RT_ISR_CONTENT, *PRT_ISR_CONTENT; ++ ++//#define RegAddr(addr) (addr + 0xB2000000UL) ++//some platform macros will def here ++static inline void NdisRawWritePortUlong(u32 port, u32 val) ++{ ++ outl(val, port); ++ //writel(val, (u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawWritePortUchar(u32 port, u8 val) ++{ ++ outb(val, port); ++ //writeb(val, (u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUchar(u32 port, u8 *pval) ++{ ++ *pval = inb(port); ++ //*pval = readb((u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUshort(u32 port, u16 *pval) ++{ ++ *pval = inw(port); ++ //*pval = readw((u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUlong(u32 port, u32 *pval) ++{ ++ *pval = inl(port); ++ //*pval = readl((u8 *)RegAddr(port)); ++} ++ ++#ifdef CONFIG_RTL8192C ++void rtl8192ce_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8192ce_set_hal_ops ++#endif ++#ifdef CONFIG_RTL8192D ++void rtl8192de_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8192de_set_hal_ops ++#endif ++ ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188ee_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8188ee_set_hal_ops ++#endif ++ ++#endif //__PCIE_HAL_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/pci_ops.h b/drivers/net/wireless/rtl818x/rtl8189/include/pci_ops.h +new file mode 100644 +index 00000000..be8cad5e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/pci_ops.h +@@ -0,0 +1,78 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_OPS_H_ ++#define __PCI_OPS_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CONFIG_RTL8188E ++u32 rtl8188ee_init_desc_ring(_adapter * padapter); ++u32 rtl8188ee_free_desc_ring(_adapter * padapter); ++void rtl8188ee_reset_desc_ring(_adapter * padapter); ++#ifdef CONFIG_64BIT_DMA ++u8 PlatformEnable88EEDMA64(PADAPTER Adapter); ++#endif ++int rtl8188ee_interrupt(PADAPTER Adapter); ++void rtl8188ee_xmit_tasklet(void *priv); ++void rtl8188ee_recv_tasklet(void *priv); ++void rtl8188ee_prepare_bcn_tasklet(void *priv); ++void rtl8188ee_set_intf_ops(struct _io_ops *pops); ++#define pci_set_intf_ops rtl8188ee_set_intf_ops ++#endif ++ ++ ++#ifdef CONFIG_RTL8192C ++u32 rtl8192ce_init_desc_ring(_adapter * padapter); ++u32 rtl8192ce_free_desc_ring(_adapter * padapter); ++void rtl8192ce_reset_desc_ring(_adapter * padapter); ++#ifdef CONFIG_64BIT_DMA ++u8 PlatformEnable92CEDMA64(PADAPTER Adapter); ++#endif ++int rtl8192ce_interrupt(PADAPTER Adapter); ++void rtl8192ce_xmit_tasklet(void *priv); ++void rtl8192ce_recv_tasklet(void *priv); ++void rtl8192ce_prepare_bcn_tasklet(void *priv); ++void rtl8192ce_set_intf_ops(struct _io_ops *pops); ++#define pci_set_intf_ops rtl8192ce_set_intf_ops ++#endif ++ ++#ifdef CONFIG_RTL8192D ++u32 rtl8192de_init_desc_ring(_adapter * padapter); ++u32 rtl8192de_free_desc_ring(_adapter * padapter); ++void rtl8192de_reset_desc_ring(_adapter * padapter); ++#ifdef CONFIG_64BIT_DMA ++u8 PlatformEnable92DEDMA64(PADAPTER Adapter); ++#endif ++int rtl8192de_interrupt(PADAPTER Adapter); ++void rtl8192de_xmit_tasklet(void *priv); ++void rtl8192de_recv_tasklet(void *priv); ++void rtl8192de_prepare_bcn_tasklet(void *priv); ++void rtl8192de_set_intf_ops(struct _io_ops *pops); ++#define pci_set_intf_ops rtl8192de_set_intf_ops ++u32 MpReadPCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u8 Direct); ++void MpWritePCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u32 Value, IN u8 Direct); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/pci_osintf.h b/drivers/net/wireless/rtl818x/rtl8189/include/pci_osintf.h +new file mode 100644 +index 00000000..09715af4 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/pci_osintf.h +@@ -0,0 +1,33 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_OSINTF_H ++#define __PCI_OSINTF_H ++ ++#include ++#include ++#include ++ ++ ++void rtw_pci_disable_aspm(_adapter *padapter); ++void rtw_pci_enable_aspm(_adapter *padapter); ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/recv_osdep.h b/drivers/net/wireless/rtl818x/rtl8189/include/recv_osdep.h +new file mode 100644 +index 00000000..536ed310 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/recv_osdep.h +@@ -0,0 +1,58 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RECV_OSDEP_H_ ++#define __RECV_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++ ++extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); ++extern void _rtw_free_recv_priv (struct recv_priv *precvpriv); ++ ++ ++extern s32 rtw_recv_entry(union recv_frame *precv_frame); ++extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); ++extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); ++ ++extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); ++extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup); ++ ++ ++int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); ++void rtw_free_recv_priv (struct recv_priv *precvpriv); ++ ++ ++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); ++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); ++void rtw_os_recv_resource_free(struct recv_priv *precvpriv); ++ ++ ++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); ++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); ++ ++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); ++ ++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); ++ ++ ++#endif // ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_cmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_cmd.h +new file mode 100644 +index 00000000..9899f67b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_cmd.h +@@ -0,0 +1,258 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_CMD_H__ ++#define __RTL8188E_CMD_H__ ++ ++#if 0 ++enum cmd_msg_element_id ++{ ++ NONE_CMDMSG_EID, ++ AP_OFFLOAD_EID = 0, ++ SET_PWRMODE_EID = 1, ++ JOINBSS_RPT_EID = 2, ++ RSVD_PAGE_EID = 3, ++ RSSI_4_EID = 4, ++ RSSI_SETTING_EID = 5, ++ MACID_CONFIG_EID = 6, ++ MACID_PS_MODE_EID = 7, ++ P2P_PS_OFFLOAD_EID = 8, ++ SELECTIVE_SUSPEND_ROF_CMD = 9, ++ P2P_PS_CTW_CMD_EID = 32, ++ MAX_CMDMSG_EID ++}; ++#else ++typedef enum _RTL8188E_H2C_CMD_ID ++{ ++ //Class Common ++ H2C_COM_RSVD_PAGE =0x00, ++ H2C_COM_MEDIA_STATUS_RPT =0x01, ++ H2C_COM_SCAN =0x02, ++ H2C_COM_KEEP_ALIVE =0x03, ++ H2C_COM_DISCNT_DECISION =0x04, ++#ifndef CONFIG_WOWLAN ++ H2C_COM_WWLAN =0x05, ++#endif ++ H2C_COM_INIT_OFFLOAD =0x06, ++ H2C_COM_REMOTE_WAKE_CTL =0x07, ++ H2C_COM_AP_OFFLOAD =0x08, ++ H2C_COM_BCN_RSVD_PAGE =0x09, ++ H2C_COM_PROB_RSP_RSVD_PAGE =0x0A, ++ ++ //Class PS ++ H2C_PS_PWR_MODE =0x20, ++ H2C_PS_TUNE_PARA =0x21, ++ H2C_PS_TUNE_PARA_2 =0x22, ++ H2C_PS_LPS_PARA =0x23, ++ H2C_PS_P2P_OFFLOAD =0x24, ++ ++ //Class DM ++ H2C_DM_MACID_CFG =0x40, ++ H2C_DM_TXBF =0x41, ++ ++ //Class BT ++ H2C_BT_COEX_MASK =0x60, ++ H2C_BT_COEX_GPIO_MODE =0x61, ++ H2C_BT_DAC_SWING_VAL =0x62, ++ H2C_BT_PSD_RST =0x63, ++ ++ //Class Remote WakeUp ++#ifdef CONFIG_WOWLAN ++ H2C_COM_WWLAN =0x80, ++ H2C_COM_REMOTE_WAKE_CTRL =0x81, ++ H2C_COM_AOAC_GLOBAL_INFO =0x82, ++ H2C_COM_AOAC_RSVD_PAGE =0x83, ++#endif ++ ++ //Class ++ H2C_RESET_TSF =0xc0, ++}RTL8188E_H2C_CMD_ID; ++ ++#endif ++ ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++enum{ ++ PWRS ++}; ++ ++typedef struct _SETPWRMODE_PARM { ++ u8 Mode;//0:Active,1:LPS,2:WMMPS ++ //u8 RLBM:4;//0:Min,1:Max,2: User define ++ u8 SmartPS_RLBM;//LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData ++ u8 AwakeInterval; // unit: beacon interval ++ u8 bAllQueueUAPSD; ++ u8 PwrState;//AllON(0x0c),RFON(0x04),RFOFF(0x00) ++} SETPWRMODE_PARM, *PSETPWRMODE_PARM; ++ ++struct H2C_SS_RFOFF_PARAM{ ++ u8 ROFOn; // 1: on, 0:off ++ u16 gpio_period; // unit: 1024 us ++}__attribute__ ((packed)); ++ ++ ++typedef struct JOINBSSRPT_PARM{ ++ u8 OpMode; // RT_MEDIA_STATUS ++#ifdef CONFIG_WOWLAN ++ u8 MacID; // MACID ++#endif //CONFIG_WOWLAN ++}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM; ++ ++typedef struct _RSVDPAGE_LOC { ++ u8 LocProbeRsp; ++ u8 LocPsPoll; ++ u8 LocNullData; ++ u8 LocQosNull; ++ u8 LocBTQosNull; ++#ifdef CONFIG_WOWLAN ++ u8 LocRemoteCtrlInfo; ++ u8 LocArpRsp; ++ u8 LocNbrAdv; ++ u8 LocGTKRsp; ++ u8 LocGTKInfo; ++ u8 LocProbeReq; ++ u8 LocNetList; ++#endif //CONFIG_WOWLAN ++} RSVDPAGE_LOC, *PRSVDPAGE_LOC; ++ ++struct P2P_PS_Offload_t { ++ u8 Offload_En:1; ++ u8 role:1; // 1: Owner, 0: Client ++ u8 CTWindow_En:1; ++ u8 NoA0_En:1; ++ u8 NoA1_En:1; ++ u8 AllStaSleep:1; // Only valid in Owner ++ u8 discovery:1; ++ u8 rsvd:1; ++}; ++ ++struct P2P_PS_CTWPeriod_t { ++ u8 CTWPeriod; //TU ++}; ++ ++ ++// host message to firmware cmd ++void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); ++void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); ++u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param); ++u8 rtl8188e_set_raid_cmd(PADAPTER padapter, u32 mask); ++void rtl8188e_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg, u8 rssi_level); ++//u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); ++ ++ ++#ifdef CONFIG_P2P ++void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++void CheckFwRsvdPageContent(PADAPTER padapter); ++void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt ); ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++//u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port); ++int reset_tsf(PADAPTER Adapter, u8 reset_port ); ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ ++#define H2C_8188E_RSVDPAGE_LOC_LEN 5 ++#define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 ++ ++#ifdef CONFIG_WOWLAN ++typedef struct _SETWOWLAN_PARM{ ++ u8 mode; ++ u8 gpio_index; ++ u8 gpio_duration; ++ u8 second_mode; ++ u8 reserve; ++}SETWOWLAN_PARM, *PSETWOWLAN_PARM; ++ ++typedef struct _SETAOAC_GLOBAL_INFO{ ++ u8 pairwiseEncAlg; ++ u8 groupEncAlg; ++}SETAOAC_GLOBAL_INFO, *PSETAOAC_GLOBAL_INFO; ++ ++#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) ++#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) ++#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3]) ++ ++// ++// ARP packet ++// ++// LLC Header ++#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6) ++ ++//ARP element ++#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6) ++#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8) ++#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14) ++#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18) ++#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value) ++#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value) ++#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value) ++#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value) ++#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value) ++#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val)) ++#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val)) ++#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val)) ++#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val)) ++ ++#define FW_WOWLAN_FUN_EN BIT(0) ++#define FW_WOWLAN_PATTERN_MATCH BIT(1) ++#define FW_WOWLAN_MAGIC_PKT BIT(2) ++#define FW_WOWLAN_UNICAST BIT(3) ++#define FW_WOWLAN_ALL_PKT_DROP BIT(4) ++#define FW_WOWLAN_GPIO_ACTIVE BIT(5) ++#define FW_WOWLAN_REKEY_WAKEUP BIT(6) ++#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) ++ ++#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) ++#define FW_FW_PARSE_MAGIC_PKT BIT(1) ++ ++#define FW_WOWLAN_KEEP_ALIVE_EN BIT(0) ++#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2) ++ ++#define FW_REMOTE_WAKE_CTRL_EN BIT(0) ++#define FW_ARP_EN BIT(1) ++#define FW_REALWOWLAN_EN BIT(5) ++#define FW_WOW_FW_UNICAST_EN BIT(7) ++ ++#define FW_ADOPT_USER BIT(1) ++void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable); ++void SetFwRelatedForWoWLAN8188ES(_adapter* padapter, u8 bHostIsGoingtoSleep); ++#endif//CONFIG_WOWLAN ++ ++//---------------------------------------------------------------------------------------------------------// ++//---------------------------------- H2C CMD CONTENT --------------------------------------------------// ++//---------------------------------------------------------------------------------------------------------// ++//_RSVDPAGE_LOC_CMD_0x00 ++#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) ++#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) ++ ++// AOAC_RSVDPAGE_LOC_0x83 ++#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) ++#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++ ++#endif//__RTL8188E_CMD_H__ ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_dm.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_dm.h +new file mode 100644 +index 00000000..d35d27fa +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_dm.h +@@ -0,0 +1,179 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_DM_H__ ++#define __RTL8188E_DM_H__ ++enum{ ++ UP_LINK, ++ DOWN_LINK, ++}; ++//###### duplicate code,will move to ODM ######### ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 9 ++#define HP_THERMAL_NUM 8 ++//###### duplicate code,will move to ODM ######### ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag; ++ u8 InitDMFlag; ++ u32 InitODMFlag; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ int MinUndecoratedPWDBForDM; ++ int LastMinUndecoratedPWDBForDM; ++ ++//###### duplicate code,will move to ODM ######### ++/* ++ //for DIG ++ u8 bDMInitialGainEnable; ++ u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++*/ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ u8 PowerIndex_backup[6]; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++#if 0 ++ //for tx power tracking ++ u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ ++ ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_DPK; ++ ++ u8 bRfPiEnable; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ u8 bDPdone; ++ u8 bDPPathAOK; ++ u8 bDPPathBOK; ++ ++ //for IQK ++ u32 RegC04; ++ u32 Reg874; ++ u32 RegC08; ++ u32 RegB68; ++ u32 RegB6C; ++ u32 Reg870; ++ u32 Reg860; ++ u32 Reg864; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup_recover[9]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ ++ ++ u8 bCCKinCH14; ++ ++ u8 CCK_index; ++ u8 OFDM_index[2]; ++ ++ u8 bDoneTxpower; ++ u8 CCK_index_HP; ++ u8 OFDM_index_HP[2]; ++ u8 ThermalValue_HP[HP_THERMAL_NUM]; ++ u8 ThermalValue_HP_index; ++ ++ //for TxPwrTracking ++ s32 RegE94; ++ s32 RegE9C; ++ s32 RegEB4; ++ s32 RegEBC; ++ ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++/* ++ // for dm_RF_Saving ++ u8 initialize; ++ u32 rf_saving_Reg874; ++ u32 rf_saving_RegC70; ++ u32 rf_saving_Reg85C; ++ u32 rf_saving_RegA74; ++*/ ++ //for Antenna diversity ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// SWAT_T DM_SWAT_Table; ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++// _timer SwAntennaSwitchTimer; ++/* ++ u64 lastTxOkCnt; ++ u64 lastRxOkCnt; ++ u64 TXByteCnt_A; ++ u64 TXByteCnt_B; ++ u64 RXByteCnt_A; ++ u64 RXByteCnt_B; ++ u8 DoubleComfirm; ++ u8 TrafficLoad; ++*/ ++#endif ++ ++ s32 OFDM_Pkt_Cnt; ++ u8 RSSI_Select; ++// u8 DIG_Dynamic_MIN ; ++//###### duplicate code,will move to ODM ######### ++#endif ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ //u8 INIDATA_RATE[32]; ++}; ++ ++ ++void rtl8188e_init_dm_priv(IN PADAPTER Adapter); ++void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter); ++void rtl8188e_InitHalDm(IN PADAPTER Adapter); ++void rtl8188e_HalDmWatchDog(IN PADAPTER Adapter); ++ ++//VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); ++ ++//void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); ++u8 AntDivBeforeLink8188E(PADAPTER Adapter ); ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_hal.h +new file mode 100644 +index 00000000..3c7d574b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_hal.h +@@ -0,0 +1,715 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_HAL_H__ ++#define __RTL8188E_HAL_H__ ++ ++ ++//include HAL Related header after HAL Related compiling flags ++#include "rtl8188e_spec.h" ++#include "Hal8188EPhyReg.h" ++#include "Hal8188EPhyCfg.h" ++#include "rtl8188e_rf.h" ++#include "rtl8188e_dm.h" ++#include "rtl8188e_recv.h" ++#include "rtl8188e_xmit.h" ++#include "rtl8188e_cmd.h" ++#include "Hal8188EPwrSeq.h" ++#ifdef DBG_CONFIG_ERROR_DETECT ++#include "rtl8188e_sreset.h" ++#endif ++#include "rtw_efuse.h" ++ ++#include "../hal/OUTSRC/odm_precomp.h" ++ ++ // Fw Array ++ #define Rtl8188E_FwImageArray Rtl8188EFwImgArray ++ #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength ++#ifdef CONFIG_WOWLAN ++ #define Rtl8188E_FwWoWImageArray Array_8188E_FW_WoWLAN ++ #define Rtl8188E_FwWoWImgArrayLength ArrayLength_8188E_FW_WoWLAN ++#endif //CONFIG_WOWLAN ++ ++ ++#ifdef CONFIG_SDIO_HCI ++ ++ //TODO: We should define 8188ES firmware related macro settings here!! ++ //TODO: The following need to check!! ++ #define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" ++ #define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" ++ #define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" ++ #define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" ++ #define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" ++ #define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" ++ #define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" ++ #define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8188E From header ++//--------------------------------------------------------------------- ++#if 0 ++ #define Rtl8188E_PHY_REG_Array_PG Rtl8188ESPHY_REG_Array_PG ++ #define Rtl8188E_PHY_REG_Array_PGLength Rtl8188ESPHY_REG_Array_PGLength ++ ++#endif ++ ++ //--------------------------------------------------------------------- ++ // RTL8188E Power Configuration CMDs for USB/SDIO interfaces ++ //--------------------------------------------------------------------- ++ #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow ++ #define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow ++ #define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow ++ #define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow ++ #define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow ++ #define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow ++ #define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow ++ #define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow ++ #define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow ++ ++#elif defined(CONFIG_USB_HCI) ++ #define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" ++ #define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" ++ #define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" ++ #define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" ++ #define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" ++ #define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" ++ #define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" ++ #define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" ++ ++#if 0 ++ #define Rtl8188E_PHY_REG_Array_PG Rtl8188EUPHY_REG_Array_PG ++ #define Rtl8188E_PHY_REG_Array_PGLength Rtl8188EUPHY_REG_Array_PGLength ++ ++#endif ++ ++ //--------------------------------------------------------------------- ++ // RTL8188E Power Configuration CMDs for USB/SDIO interfaces ++ //--------------------------------------------------------------------- ++ #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow ++ #define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow ++ #define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow ++ #define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow ++ #define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow ++ #define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow ++ #define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow ++ #define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow ++ #define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow ++ ++#elif defined(CONFIG_PCI_HCI) ++ #define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" ++ #define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" ++ #define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" ++ #define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" ++ #define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" ++ #define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" ++ #define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" ++ #define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" ++ ++ #define Rtl8188E_PHY_REG_Array_PG Rtl8188EEPHY_REG_Array_PG ++ #define Rtl8188E_PHY_REG_Array_PGLength Rtl8188EEPHY_REG_Array_PGLength ++ ++ ++ #ifndef CONFIG_PHY_SETTING_WITH_ODM ++ #if MP_DRIVER == 1 ++ #define Rtl8188ES_PHY_REG_Array_MP Rtl8188ESPHY_REG_Array_MP ++ #endif ++ #endif ++ ++ //--------------------------------------------------------------------- ++ // RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces ++ //--------------------------------------------------------------------- ++ #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow ++ #define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow ++ #define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow ++ #define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow ++ #define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow ++ #define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow ++ #define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow ++ #define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow ++ #define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow ++#endif //CONFIG_***_HCI ++ ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++ ++#if 1 // download firmware related data structure ++#define FW_8188E_SIZE 0x4000 //16384,16k ++#define FW_8188E_START_ADDRESS 0x1000 ++#define FW_8188E_END_ADDRESS 0x1FFF //0x5FFF ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) ++ ++typedef enum _FIRMWARE_SOURCE { ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE { ++ FIRMWARE_SOURCE eFWSource; ++#ifdef CONFIG_EMBEDDED_FWIMG ++ u8* szFwBuffer; ++#else ++ u8 szFwBuffer[FW_8188E_SIZE]; ++#endif ++ u32 ulFwLength; ++ ++#ifdef CONFIG_WOWLAN ++ u8* szWoWLANFwBuffer; ++ u32 ulWoWLANFwLength; ++#endif //CONFIG_WOWLAN ++} RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E; ++ ++// ++// This structure must be cared byte-ordering ++// ++ ++typedef struct _RT_8188E_FIRMWARE_HDR ++{ ++ // 8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u16 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u8 Foundry; ++ u8 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++}RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR; ++#endif // download firmware related data structure ++ ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_MIX ++}USB_RX_AGG_MODE; ++ ++//#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++#define MAX_RX_DMA_BUFFER_SIZE_88E (1024*256) //9k for 88E nornal chip , //MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) ++ ++//modify by liming 1k --> 16k ++#define MAX_TX_REPORT_BUFFER_SIZE (1024*32) // 1k ++ ++//modify by liming 9 --> 300 ++// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. ++#define MAX_TX_QUEUE 800 ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++// 22k = 22528 bytes = 176 pages (@page = 128 bytes) ++// must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) ++// 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data ++ ++#define TX_TOTAL_PAGE_NUMBER_88E 0xA9// 169 (21632=> 21k) ++ ++#ifdef RTL8188ES_MAC_LOOPBACK ++#define TX_PAGE_BOUNDARY_88E 0x48 //72 ++#else //TX_PAGE_BOUNDARY_LOOPBACK_MODE ++#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) ++#endif ++ ++ ++//Note: For Normal Chip Setting ,modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_88E //0xA9 , 0xb0=>176=>22k ++#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) //0xA9 ++ ++ ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++#include "HalVerDef.h" ++#include "hal_com.h" ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan ++{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++typedef struct _TxPowerInfo ++{ ++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; ++ u8 TSSI_A[3]; ++ u8 TSSI_B[3]; ++ u8 TSSI_A_5G[3]; //5GL/5GM/5GH ++ u8 TSSI_B_5G[3]; ++} TxPowerInfo, *PTxPowerInfo; ++ ++typedef struct _TxPowerInfo24G{ ++ u1Byte IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; ++ u1Byte IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1]; ++ //If only one tx, only BW20 and OFDM are used. ++ s1Byte CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s1Byte OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s1Byte BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s1Byte BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++}TxPowerInfo24G, *PTxPowerInfo24G; ++ ++#define EFUSE_REAL_CONTENT_LEN 512 ++#define EFUSE_MAP_LEN 128 ++#define EFUSE_MAX_SECTION 16 ++#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. ++#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) ++// ++// ++// To prevent out of boundary programming case, ++// leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 1byte|----8bytes----|1byte|--5bytes--| ++// | | Reserved(14bytes) | ++// ++#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. ++ ++#define HWSET_MAX_SIZE_88E 512 ++ ++#define EFUSE_REAL_CONTENT_LEN_88E 256 ++#define EFUSE_MAP_LEN_88E 512 ++#define EFUSE_MAX_SECTION_88E 64 ++#define EFUSE_MAX_WORD_UNIT_88E 4 ++#define EFUSE_IC_ID_OFFSET_88E 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. ++#define AVAILABLE_EFUSE_ADDR_88E(addr) (addr < EFUSE_REAL_CONTENT_LEN_88E) ++// To prevent out of boundary programming case, leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 2byte|----8bytes----|1byte|--7bytes--| //92D ++#define EFUSE_OOB_PROTECT_BYTES_88E 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. ++#define EFUSE_PROTECT_BYTES_BANK_88E 16 ++ ++ ++//======================================================== ++// EFUSE for BT definition ++//======================================================== ++#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 ++#define EFUSE_BT_MAP_LEN 1024 // 1k bytes ++#define EFUSE_BT_MAX_SECTION 128 // 1024/8 ++ ++#define EFUSE_PROTECT_BYTES_BANK 16 ++ ++// ++// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. ++// ++typedef enum _RT_MULTI_FUNC { ++ RT_MULTI_FUNC_NONE = 0x00, ++ RT_MULTI_FUNC_WIFI = 0x01, ++ RT_MULTI_FUNC_BT = 0x02, ++ RT_MULTI_FUNC_GPS = 0x04, ++} RT_MULTI_FUNC, *PRT_MULTI_FUNC; ++ ++// ++// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. ++// ++typedef enum _RT_POLARITY_CTL { ++ RT_POLARITY_LOW_ACT = 0, ++ RT_POLARITY_HIGH_ACT = 1, ++} RT_POLARITY_CTL, *PRT_POLARITY_CTL; ++ ++// For RTL8723 regulator mode. by tynli. 2011.01.14. ++typedef enum _RT_REGULATOR_MODE { ++ RT_SWITCHING_REGULATOR = 0, ++ RT_LDO_REGULATOR = 1, ++} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; ++ ++ ++typedef struct hal_data_8188e ++{ ++ HAL_VERSION VersionID; ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ u16 FirmwareSignature; ++ u8 PGMaxGroup; ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ u8 BoardType; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMVersion; ++ u8 EEPROMRegulatory; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 EEPROMThermalMeter; ++ u8 bAPKThermalMeterIgnore; ++ ++ BOOLEAN EepromOrEfuse; ++ u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u8 EfuseUsedPercentage; ++ EFUSE_HAL EfuseHal; ++ ++ //u8 bIQKInitialized; ++ ++ ++ u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; ++ u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; ++ //If only one tx, only BW20 and OFDM are used. ++ s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ u8 CurrentBW2024GTxPwrIdx; ++ u8 CurrentBW4024GTxPwrIdx; ++ ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u8 CrystalCap; ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ //u8 bCurrentTurboEDCA; ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ u32 RfRegChnlVal[2]; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 RegCR_1; ++ ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ u8 CurAntenna; ++ u8 AntDivCfg; ++ u8 TRxAntDivType; ++ ++ ++ u8 bDumpRxPkt;//for debug ++ u8 bDumpTxPkt;//for debug ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // 2010/08/09 MH Add CU power down mode. ++ BOOLEAN pwrdown; ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. ++ BOOLEAN UsbRxHighSpeedMode; ++ ++ // 2010/11/22 MH Add for slim combo debug mode selective. ++ // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. ++ BOOLEAN SlimComboDbg; ++ ++ u16 EfuseUsedBytes; ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif ++ ++ // Auto FSM to Turn On, include clock, isolation, power control for MAC only ++ u8 bMacPwrCtrlOn; ++ ++#ifdef CONFIG_SDIO_HCI ++ // ++ // For SDIO Interface HAL related ++ // ++ ++ // ++ // SDIO ISR Related ++ // ++// u32 IntrMask[1]; ++// u32 IntrMaskToSet[1]; ++// LOG_INTERRUPT InterruptLog; ++ u32 sdio_himr; ++ u32 sdio_hisr; ++ ++ // ++ // SDIO Tx FIFO related. ++ // ++ // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg ++ u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; ++ _lock SdioTxFIFOFreePageLock; ++ ++ // ++ // SDIO Rx FIFO related. ++ // ++ u8 SdioRxFIFOCnt; ++ u16 SdioRxFIFOSize; ++#endif //CONFIG_SDIO_HCI ++ ++#ifdef CONFIG_USB_HCI ++ u32 UsbBulkOutSize; ++ ++ // Interrupt relatd register information. ++ u32 IntArray[3];//HISR0,HISR1,HSISR ++ u32 IntrMask[3]; ++ u8 C2hArray[16]; ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 UsbTxAggMode; ++ u8 UsbTxAggDescNum; ++#endif ++#ifdef CONFIG_USB_RX_AGGREGATION ++ u16 HwRxPageSize; // Hardware setting ++ u32 MaxUsbRxAggBlock; ++ ++ USB_RX_AGG_MODE UsbRxAggMode; ++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed ++ u8 UsbRxAggBlockTimeout; ++ u8 UsbRxAggPageCount; // 8192C DMA page count ++ u8 UsbRxAggPageTimeout; ++#endif ++#endif //CONFIG_USB_HCI ++ ++ ++#ifdef CONFIG_PCI_HCI ++ ++ // ++ // EEPROM setting. ++ // ++ ++ u16 EEPROMDID; ++ u16 EEPROMSMID; ++ u16 EEPROMChannelPlan; ++ ++ u8 EEPROMTSSI[2]; ++ u8 EEPROMBoardType; ++ u32 TransmitConfig; ++ ++ u32 IntrMask[2]; ++ u32 IntrMaskToSet[2]; ++ ++ u8 bDefaultAntenna; ++ u8 bIQKInitialized; ++ ++ u8 bInterruptMigration; ++ u8 bDisableTxInt; ++ u8 bGpioHwWpsPbc; ++#endif //CONFIG_PCI_HCI ++ ++ ++#ifdef CONFIG_TX_EARLY_MODE ++ u8 bEarlyModeEnable; ++#endif ++} HAL_DATA_8188E, *PHAL_DATA_8188E; ++ ++typedef struct hal_data_8188e HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++ ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) ++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) ++ ++//#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) ++ ++//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) ++ ++#ifdef CONFIG_PCI_HCI ++void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent); ++void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); ++#endif //CONFIG_PCI_HCI ++ ++// rtl8188e_hal_init.c ++#ifdef CONFIG_WOWLAN ++s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); ++#else ++s32 rtl8188e_FirmwareDownload(PADAPTER padapter); ++#endif ++void _8051Reset88E(PADAPTER padapter); ++void rtl8188e_InitializeFirmwareVars(PADAPTER padapter); ++ ++ ++s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy); ++void Read_LLT_Tab(PADAPTER padapter); ++ ++// EFuse ++u8 GetEEPROMSize8188E(PADAPTER padapter); ++void Hal_InitPGData88E(PADAPTER padapter); ++void Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo); ++void Hal_ReadTxPowerInfo88E(PADAPTER padapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++ ++void Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_ReadAntennaDiversity88E (PADAPTER pAdapter,u8*PROMContent,BOOLEAN AutoLoadFail); ++void Hal_ReadThermalMeter_88E(PADAPTER Adapter,u8* PROMContent,BOOLEAN AutoloadFail); ++void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++void Hal_EfuseParseBoardType88E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++ ++BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter); ++ ++#ifdef CONFIG_WOWLAN ++void Hal_DetectWoWMode(PADAPTER pAdapter); ++#endif //CONFIG_WOWLAN ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan); ++//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter); ++//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoloadFail); ++void Hal_InitChannelPlan(PADAPTER padapter); ++ ++void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); ++ ++// register ++void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); ++ ++void rtl8188e_start_thread(_adapter *padapter); ++void rtl8188e_stop_thread(_adapter *padapter); ++ ++void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter,int data_len); ++#ifdef CONFIG_IOL_EFUSE_PATCH ++s32 rtl8188e_iol_efuse_patch(PADAPTER padapter); ++#endif//CONFIG_IOL_EFUSE_PATCH ++ ++#endif //__RTL8188E_HAL_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_led.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_led.h +new file mode 100644 +index 00000000..2bafb83f +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_led.h +@@ -0,0 +1,46 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_LED_H__ ++#define __RTL8188E_LED_H__ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8188eu_InitSwLeds(PADAPTER padapter); ++void rtl8188eu_DeInitSwLeds(PADAPTER padapter); ++#endif ++#ifdef CONFIG_PCI_HCI ++void rtl8188ee_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8188ee_InitSwLeds(PADAPTER padapter); ++void rtl8188ee_DeInitSwLeds(PADAPTER padapter); ++#endif ++#ifdef CONFIG_SDIO_HCI ++void rtl8188es_InitSwLeds(PADAPTER padapter); ++void rtl8188es_DeInitSwLeds(PADAPTER padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_recv.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_recv.h +new file mode 100644 +index 00000000..2c190d05 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_recv.h +@@ -0,0 +1,146 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_RECV_H__ ++#define __RTL8188E_RECV_H__ ++ ++#include ++ ++#define TX_RPT1_PKT_LEN 8 ++ ++typedef enum _RX_PACKET_TYPE{ ++ NORMAL_RX,//Normal rx packet ++ TX_REPORT1,//CCX ++ TX_REPORT2,//TX RPT ++ HIS_REPORT,// USB HISR RPT ++}RX_PACKET_TYPE, *PRX_PACKET_TYPE; ++ ++typedef struct rxreport_8188e ++{ ++ //Offset 0 ++ u32 pktlen:14; ++ u32 crc32:1; ++ u32 icverr:1; ++ u32 drvinfosize:4; ++ u32 security:3; ++ u32 qos:1; ++ u32 shift:2; ++ u32 physt:1; ++ u32 swdec:1; ++ u32 ls:1; ++ u32 fs:1; ++ u32 eor:1; ++ u32 own:1; ++ ++ //Offset 4 ++ u32 macid:5; ++ u32 tid:4; ++ u32 hwrsvd:4; ++ u32 amsdu:1; ++ u32 paggr:1; ++ u32 faggr:1; ++ u32 a1fit:4; ++ u32 a2fit:4; ++ u32 pam:1; ++ u32 pwr:1; ++ u32 md:1; ++ u32 mf:1; ++ u32 type:2; ++ u32 mc:1; ++ u32 bc:1; ++ ++ //Offset 8 ++ u32 seq:12; ++ u32 frag:4; ++ u32 nextpktlen:14; ++ u32 nextind:1; ++ u32 rsvd0831:1; ++ ++ //Offset 12 ++ u32 rxmcs:6; ++ u32 rxht:1; ++ u32 gf:1; ++ u32 splcp:1; ++ u32 bw:1; ++ u32 htc:1; ++ u32 eosp:1; ++ u32 bssidfit:2; ++ u32 rpt_sel:2; ++ u32 rsvd1216:13; ++ u32 pattern_match:1; ++ u32 unicastwake:1; ++ u32 magicwake:1; ++ ++ //Offset 16 ++ /* ++ u32 pattern0match:1; ++ u32 pattern1match:1; ++ u32 pattern2match:1; ++ u32 pattern3match:1; ++ u32 pattern4match:1; ++ u32 pattern5match:1; ++ u32 pattern6match:1; ++ u32 pattern7match:1; ++ u32 pattern8match:1; ++ u32 pattern9match:1; ++ u32 patternamatch:1; ++ u32 patternbmatch:1; ++ u32 patterncmatch:1; ++ u32 rsvd1613:19; ++ */ ++ u32 rsvd16; ++ ++ //Offset 20 ++ u32 tsfl; ++ ++ //Offset 24 ++ u32 bassn:12; ++ u32 bavld:1; ++ u32 rsvd2413:19; ++} RXREPORT, *PRXREPORT; ++ ++ ++#ifdef CONFIG_SDIO_HCI ++s32 rtl8188es_init_recv_priv(PADAPTER padapter); ++void rtl8188es_free_recv_priv(PADAPTER padapter); ++void rtl8188es_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#define INTERRUPT_MSG_FORMAT_LEN 60 ++void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); ++s32 rtl8188eu_init_recv_priv(PADAPTER padapter); ++void rtl8188eu_free_recv_priv(PADAPTER padapter); ++void rtl8188eu_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf); ++void rtl8188eu_recv_tasklet(void *priv); ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8188ee_init_recv_priv(PADAPTER padapter); ++void rtl8188ee_free_recv_priv(PADAPTER padapter); ++#endif ++ ++void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat); ++void rtl8188e_process_phy_info(PADAPTER padapter, void *prframe); ++void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status); ++void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_rf.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_rf.h +new file mode 100644 +index 00000000..bafa6ad7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_rf.h +@@ -0,0 +1,45 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_RF_H__ ++#define __RTL8188E_RF_H__ ++ ++#define RF6052_MAX_TX_PWR 0x3F ++#define RF6052_MAX_REG 0x3F ++#define RF6052_MAX_PATH 2 ++ ++ ++int PHY_RF6052_Config8188E( IN PADAPTER Adapter ); ++void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate); ++void rtl8188e_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth); ++VOID rtl8188e_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel); ++VOID rtl8188e_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevelOFDM, ++ IN u8* pPowerLevelBW20, ++ IN u8* pPowerLevelBW40, ++ IN u8 Channel); ++ ++#endif//__RTL8188E_RF_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_spec.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_spec.h +new file mode 100644 +index 00000000..0421da90 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_spec.h +@@ -0,0 +1,1741 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#ifndef __RTL8188E_SPEC_H__ ++#define __RTL8188E_SPEC_H__ ++ ++#include ++ ++#ifndef BIT ++#define BIT(x) (1 << (x)) ++#endif ++ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++//============================================================ ++// 8192C Regsiter offset definition ++//============================================================ ++ ++#define HAL_PS_TIMER_INT_DELAY 50 // 50 microseconds ++#define HAL_92C_NAV_UPPER_UNIT 128 // micro-second ++ ++#define MAC_ADDR_LEN 6 ++// 8188E PKT_BUFF_ACCESS_CTRL value ++#define TXPKT_BUF_SELECT 0x69 ++#define RXPKT_BUF_SELECT 0xA5 ++#define DISABLE_TRXPKT_BUF_ACCESS 0x0 ++ ++//============================================================ ++// ++//============================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYS_ISO_CTRL 0x0000 ++#define REG_SYS_FUNC_EN 0x0002 ++#define REG_APS_FSMCO 0x0004 ++#define REG_SYS_CLKR 0x0008 ++#define REG_9346CR 0x000A ++#define REG_EE_VPD 0x000C ++#define REG_AFE_MISC 0x0010 ++#define REG_SPS0_CTRL 0x0011 ++#define REG_SPS_OCP_CFG 0x0018 ++#define REG_RSV_CTRL 0x001C ++#define REG_RF_CTRL 0x001F ++#define REG_LDOA15_CTRL 0x0020 ++#define REG_LDOV12D_CTRL 0x0021 ++#define REG_LDOHCI12_CTRL 0x0022 ++#define REG_LPLDO_CTRL 0x0023 ++#define REG_AFE_XTAL_CTRL 0x0024 ++#define REG_AFE_PLL_CTRL 0x0028 ++#define REG_APE_PLL_CTRL_EXT 0x002c ++#define REG_EFUSE_CTRL 0x0030 ++#define REG_EFUSE_TEST 0x0034 ++#define REG_GPIO_MUXCFG 0x0040 ++#define REG_GPIO_IO_SEL 0x0042 ++#define REG_MAC_PINMUX_CFG 0x0043 ++#define REG_GPIO_PIN_CTRL 0x0044 ++#define REG_GPIO_INTM 0x0048 ++#define REG_LEDCFG0 0x004C ++#define REG_LEDCFG1 0x004D ++#define REG_LEDCFG2 0x004E ++#define REG_LEDCFG3 0x004F ++#define REG_FSIMR 0x0050 ++#define REG_FSISR 0x0054 ++#define REG_HSIMR 0x0058 ++#define REG_HSISR 0x005c ++#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. ++#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. ++#define REG_BB_PAD_CTRL 0x0064 ++#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. ++#define REG_GPIO_OUTPUT 0x006c ++#define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E ++#define REG_XCK_OUT_CTRL 0x007c //RTL8188E ++#define REG_MCUFWDL 0x0080 ++#define REG_WOL_EVENT 0x0081 //RTL8188E ++#define REG_MCUTSTCFG 0x0084 ++#define REG_HMEBOX_E0 0x0088 ++#define REG_HMEBOX_E1 0x008A ++#define REG_HMEBOX_E2 0x008C ++#define REG_HMEBOX_E3 0x008E ++#define REG_HMEBOX_EXT_0 0x01F0 ++#define REG_HMEBOX_EXT_1 0x01F4 ++#define REG_HMEBOX_EXT_2 0x01F8 ++#define REG_HMEBOX_EXT_3 0x01FC ++#define REG_HIMR_88E 0x00B0 ++#define REG_HISR_88E 0x00B4 ++#define REG_HIMRE_88E 0x00B8 ++#define REG_HISRE_88E 0x00BC ++#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 ++#define REG_BIST_SCAN 0x00D0 ++#define REG_BIST_RPT 0x00D4 ++#define REG_BIST_ROM_RPT 0x00D8 ++#define REG_USB_SIE_INTF 0x00E0 ++#define REG_PCIE_MIO_INTF 0x00E4 ++#define REG_PCIE_MIO_INTD 0x00E8 ++#define REG_HPON_FSM 0x00EC ++#define REG_SYS_CFG 0x00F0 ++#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. ++#define REG_TYPE_ID 0x00FC ++ ++#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_CR 0x0100 ++#define REG_PBP 0x0104 ++#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 ++#define REG_TRXDMA_CTRL 0x010C ++#define REG_TRXFF_BNDY 0x0114 ++#define REG_TRXFF_STATUS 0x0118 ++#define REG_RXFF_PTR 0x011C ++//#define REG_HIMR 0x0120 ++//#define REG_HISR 0x0124 ++#define REG_HIMRE 0x0128 ++#define REG_HISRE 0x012C ++#define REG_CPWM 0x012F ++#define REG_FWIMR 0x0130 ++#define REG_FTIMR 0x0138 ++#define REG_FWISR 0x0134 ++#define REG_PKTBUF_DBG_CTRL 0x0140 ++#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) ++#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) ++#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) ++#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) ++#define REG_PKTBUF_DBG_DATA_L 0x0144 ++#define REG_PKTBUF_DBG_DATA_H 0x0148 ++ ++#define REG_TC0_CTRL 0x0150 ++#define REG_TC1_CTRL 0x0154 ++#define REG_TC2_CTRL 0x0158 ++#define REG_TC3_CTRL 0x015C ++#define REG_TC4_CTRL 0x0160 ++#define REG_TCUNIT_BASE 0x0164 ++#define REG_MBIST_START 0x0174 ++#define REG_MBIST_DONE 0x0178 ++#define REG_MBIST_FAIL 0x017C ++#define REG_32K_CTRL 0x0194 //RTL8188E ++#define REG_C2HEVT_MSG_NORMAL 0x01A0 ++#define REG_C2HEVT_CLEAR 0x01AF ++#define REG_MCUTST_1 0x01c0 ++#ifdef CONFIG_WOWLAN ++#define REG_WOWLAN_WAKE_REASON 0x01c7 ++#endif ++#define REG_FMETHR 0x01C8 ++#define REG_HMETFR 0x01CC ++#define REG_HMEBOX_0 0x01D0 ++#define REG_HMEBOX_1 0x01D4 ++#define REG_HMEBOX_2 0x01D8 ++#define REG_HMEBOX_3 0x01DC ++ ++#define REG_LLT_INIT 0x01E0 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RQPN 0x0200 ++#define REG_FIFOPAGE 0x0204 ++#define REG_TDECTRL 0x0208 ++#define REG_TXDMA_OFFSET_CHK 0x020C ++#define REG_TXDMA_STATUS 0x0210 ++#define REG_RQPN_NPQ 0x0214 ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RXDMA_AGG_PG_TH 0x0280 ++#define REG_RXPKT_NUM 0x0284 ++#define REG_RXDMA_STATUS 0x0288 ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++#define REG_PCIE_CTRL_REG 0x0300 ++#define REG_INT_MIG 0x0304 // Interrupt Migration ++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address ++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address ++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address ++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address ++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address ++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address ++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address ++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address ++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_DBG_SEL 0x0360 // Debug Selection Register ++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM ++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM ++#define REG_WATCH_DOG 0x0368 ++ ++// RTL8723 series ------------------------------- ++#define REG_PCIE_HISR 0x03A0 ++ ++// spec version 11 ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++#define REG_VOQ_INFORMATION 0x0400 ++#define REG_VIQ_INFORMATION 0x0404 ++#define REG_BEQ_INFORMATION 0x0408 ++#define REG_BKQ_INFORMATION 0x040C ++#define REG_MGQ_INFORMATION 0x0410 ++#define REG_HGQ_INFORMATION 0x0414 ++#define REG_BCNQ_INFORMATION 0x0418 ++#define REG_TXPKT_EMPTY 0x041A ++ ++#define REG_CPU_MGQ_INFORMATION 0x041C ++#define REG_FWHW_TXQ_CTRL 0x0420 ++#define REG_HWSEQ_CTRL 0x0423 ++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 ++#define REG_TXPKTBUF_MGQ_BDNY 0x0425 ++#define REG_LIFETIME_EN 0x0426 ++#define REG_MULTI_BCNQ_OFFSET 0x0427 ++#define REG_SPEC_SIFS 0x0428 ++#define REG_RL 0x042A ++#define REG_DARFRC 0x0430 ++#define REG_RARFRC 0x0438 ++#define REG_RRSR 0x0440 ++#define REG_ARFR0 0x0444 ++#define REG_ARFR1 0x0448 ++#define REG_ARFR2 0x044C ++#define REG_ARFR3 0x0450 ++#define REG_AGGLEN_LMT 0x0458 ++#define REG_AMPDU_MIN_SPACE 0x045C ++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D ++#define REG_FAST_EDCA_CTRL 0x0460 ++#define REG_RD_RESP_PKT_TH 0x0463 ++#define REG_INIRTS_RATE_SEL 0x0480 ++//#define REG_INIDATA_RATE_SEL 0x0484 ++#define REG_MACID_NO_LINK_0 0x0484 ++#define REG_MACID_NO_LINK_1 0x0488 ++ ++#define REG_POWER_STATUS 0x04A4 ++#define REG_POWER_STAGE1 0x04B4 ++#define REG_POWER_STAGE2 0x04B8 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 ++#define REG_STBC_SETTING 0x04C4 ++#define REG_PROT_MODE_CTRL 0x04C8 ++#define REG_MAX_AGGR_NUM 0x04CA ++#define REG_RTS_MAX_AGGR_NUM 0x04CB ++#define REG_BAR_MODE_CTRL 0x04CC ++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF ++#define REG_EARLY_MODE_CONTROL 0x4D0 ++#define REG_NQOS_SEQ 0x04DC ++#define REG_QOS_SEQ 0x04DE ++#define REG_NEED_CPU_HANDLE 0x04E0 ++#define REG_PKT_LOSE_RPT 0x04E1 ++#define REG_PTCL_ERR_STATUS 0x04E2 ++#define REG_TX_RPT_CTRL 0x04EC ++#define REG_TX_RPT_TIME 0x04F0 // 2 byte ++#define REG_DUMMY 0x04FC ++ ++#ifdef CONFIG_WOWLAN ++#define REG_TXPKTBUF_IV_LOW 0x0484 ++#define REG_TXPKTBUF_IV_HIGH 0x0488 ++#endif ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++#define REG_EDCA_VO_PARAM 0x0500 ++#define REG_EDCA_VI_PARAM 0x0504 ++#define REG_EDCA_BE_PARAM 0x0508 ++#define REG_EDCA_BK_PARAM 0x050C ++#define REG_BCNTCFG 0x0510 ++#define REG_PIFS 0x0512 ++#define REG_RDG_PIFS 0x0513 ++#define REG_SIFS_CTX 0x0514 ++#define REG_SIFS_TRX 0x0516 ++#define REG_TSFTR_SYN_OFFSET 0x0518 ++#define REG_AGGR_BREAK_TIME 0x051A ++#define REG_SLOT 0x051B ++#define REG_TX_PTCL_CTRL 0x0520 ++#define REG_TXPAUSE 0x0522 ++#define REG_DIS_TXREQ_CLR 0x0523 ++#define REG_RD_CTRL 0x0524 ++// ++// Format for offset 540h-542h: ++// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. ++// [7:4]: Reserved. ++// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. ++// [23:20]: Reserved ++// Description: ++// | ++// |<--Setup--|--Hold------------>| ++// --------------|---------------------- ++// | ++// TBTT ++// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. ++// Described by Designer Tim and Bruce, 2011-01-14. ++// ++#define REG_TBTT_PROHIBIT 0x0540 ++#define REG_RD_NAV_NXT 0x0544 ++#define REG_NAV_PROT_LEN 0x0546 ++#define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 ++#define REG_MBID_NUM 0x0552 ++#define REG_DUAL_TSF_RST 0x0553 ++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE ++#define REG_DRVERLYINT 0x0558 ++#define REG_BCNDMATIM 0x0559 ++#define REG_ATIMWND 0x055A ++#define REG_BCN_MAX_ERR 0x055D ++#define REG_RXTSF_OFFSET_CCK 0x055E ++#define REG_RXTSF_OFFSET_OFDM 0x055F ++#define REG_TSFTR 0x0560 ++#define REG_TSFTR1 0x0568 ++#define REG_ATIMWND_1 0x0570 ++#define REG_PSTIMER 0x0580 ++#define REG_TIMER0 0x0584 ++#define REG_TIMER1 0x0588 ++#define REG_ACMHWCTRL 0x05C0 ++ ++//#define REG_FW_TSF_SYNC_CNT 0x04A0 ++#define REG_FW_RESET_TSF_CNT_1 0x05FC ++#define REG_FW_RESET_TSF_CNT_0 0x05FD ++#define REG_FW_BCN_DIS_CNT 0x05FE ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++#define REG_APSD_CTRL 0x0600 ++#define REG_BWOPMODE 0x0603 ++#define REG_TCR 0x0604 ++#define REG_RCR 0x0608 ++#define REG_RX_PKT_LIMIT 0x060C ++#define REG_RX_DLK_TIME 0x060D ++#define REG_RX_DRVINFO_SZ 0x060F ++ ++#define REG_MACID 0x0610 ++#define REG_BSSID 0x0618 ++#define REG_MAR 0x0620 ++#define REG_MBIDCAMCFG 0x0628 ++ ++#define REG_USTIME_EDCA 0x0638 ++#define REG_MAC_SPEC_SIFS 0x063A ++ ++// 20100719 Joseph: Hardware register definition change. (HW datasheet v54) ++#define REG_R2T_SIFS 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK ++#define REG_T2T_SIFS 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK ++#define REG_ACKTO 0x0640 ++#define REG_CTS2TO 0x0641 ++#define REG_EIFS 0x0642 ++ ++ ++//RXERR_RPT ++#define RXERR_TYPE_OFDM_PPDU 0 ++#define RXERR_TYPE_OFDM_FALSE_ALARM 1 ++#define RXERR_TYPE_OFDM_MPDU_OK 2 ++#define RXERR_TYPE_OFDM_MPDU_FAIL 3 ++#define RXERR_TYPE_CCK_PPDU 4 ++#define RXERR_TYPE_CCK_FALSE_ALARM 5 ++#define RXERR_TYPE_CCK_MPDU_OK 6 ++#define RXERR_TYPE_CCK_MPDU_FAIL 7 ++#define RXERR_TYPE_HT_PPDU 8 ++#define RXERR_TYPE_HT_FALSE_ALARM 9 ++#define RXERR_TYPE_HT_MPDU_TOTAL 10 ++#define RXERR_TYPE_HT_MPDU_OK 11 ++#define RXERR_TYPE_HT_MPDU_FAIL 12 ++#define RXERR_TYPE_RX_FULL_DROP 15 ++ ++#define RXERR_COUNTER_MASK 0xFFFFF ++#define RXERR_RPT_RST BIT(27) ++#define _RXERR_RPT_SEL(type) ((type) << 28) ++ ++ ++// ++// Note: ++// The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is ++// always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending ++// CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. ++// The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented ++// by SD1 Scott. ++// By Bruce, 2011-07-18. ++// ++#define REG_NAV_UPPER 0x0652 // unit of 128 ++ ++//WMA, BA, CCX ++//#define REG_NAV_CTRL 0x0650 ++#define REG_BACAMCMD 0x0654 ++#define REG_BACAMCONTENT 0x0658 ++#define REG_LBDLY 0x0660 ++#define REG_FWDLY 0x0661 ++#define REG_RXERR_RPT 0x0664 ++#define REG_WMAC_TRXPTCL_CTL 0x0668 ++ ++// Security ++#define REG_CAMCMD 0x0670 ++#define REG_CAMWRITE 0x0674 ++#define REG_CAMREAD 0x0678 ++#define REG_CAMDBG 0x067C ++#define REG_SECCFG 0x0680 ++ ++// Power ++#define REG_WOW_CTRL 0x0690 ++#define REG_PS_RX_INFO 0x0692 ++#define REG_UAPSD_TID 0x0693 ++#define REG_WKFMCAM_CMD 0x0698 ++#define REG_WKFMCAM_NUM_88E 0x698 ++#define REG_RXFLTMAP0 0x06A0 ++#define REG_RXFLTMAP1 0x06A2 ++#define REG_RXFLTMAP2 0x06A4 ++#define REG_BCN_PSR_RPT 0x06A8 ++#define REG_BT_COEX_TABLE 0x06C0 ++ ++ ++// Hardware Port 2 ++#define REG_MACID1 0x0700 ++#define REG_BSSID1 0x0708 ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++ ++// For normal chip ++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_NORMAL_SIE_OPTIONAL 0xFE64 ++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 ++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B ++#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C ++#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. ++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF ++ ++ ++//----------------------------------------------------- ++// ++// Redifine 8192C register definition for compatibility ++// ++//----------------------------------------------------- ++ ++// TODO: use these definition when using REG_xxx naming rule. ++// NOTE: DO NOT Remove these definition. Use later. ++ ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. ++#define MSR (REG_CR + 2) // Media Status register ++#define ISR REG_HISR_88E ++#define TSFR REG_TSFTR // Timing Sync Function Timer Register. ++ ++#define PBP REG_PBP ++ ++// Redifine MACID register, to compatible prior ICs. ++#define IDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 ++#define IDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 ++ ++ ++// ++// 9. Security Control Registers (Offset: ) ++// ++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd ++#define WCAMI REG_CAMWRITE // Software write CAM input content ++#define RCAMO REG_CAMREAD // Software read/write CAM config ++#define CAMDBG REG_CAMDBG ++#define SECR REG_SECCFG //Security Configuration Register ++ ++// Unused register ++#define UnusedRegister 0x1BF ++#define DCAM UnusedRegister ++#define PSR UnusedRegister ++#define BBAddr UnusedRegister ++#define PhyDataR UnusedRegister ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C Cmd9346CR bits (Offset 0xA, 16bit) ++//---------------------------------------------------------------------------- ++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 ++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 ++#define Cmd9346CR_9356SEL BIT4 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++//---------------------------------------------------------------------------- ++// 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) ++//---------------------------------------------------------------------------- ++#define HSIMR_GPIO12_0_INT_EN BIT0 ++#define HSIMR_SPS_OCP_INT_EN BIT5 ++#define HSIMR_RON_INT_EN BIT6 ++#define HSIMR_PDN_INT_EN BIT7 ++#define HSIMR_GPIO9_INT_EN BIT25 ++ ++ ++//---------------------------------------------------------------------------- ++// 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) ++//---------------------------------------------------------------------------- ++#define HSISR_GPIO12_0_INT BIT0 ++#define HSISR_SPS_OCP_INT BIT5 ++#define HSISR_RON_INT_EN BIT6 ++#define HSISR_PDNINT BIT7 ++#define HSISR_GPIO9_INT BIT25 ++ ++//---------------------------------------------------------------------------- ++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++/* ++Network Type ++00: No link ++01: Link in ad hoc network ++10: Link in infrastructure network ++11: AP mode ++Default: 00b. ++*/ ++#define MSR_NOLINK 0x00 ++#define MSR_ADHOC 0x01 ++#define MSR_INFRA 0x02 ++#define MSR_AP 0x03 ++ ++//---------------------------------------------------------------------------- ++// 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++#define USB_INTR_CONTENT_C2H_OFFSET 0 ++#define USB_INTR_CONTENT_CPWM1_OFFSET 16 ++#define USB_INTR_CONTENT_CPWM2_OFFSET 20 ++#define USB_INTR_CONTENT_HISR_OFFSET 48 ++#define USB_INTR_CONTENT_HISRE_OFFSET 52 ++ ++ ++//---------------------------------------------------------------------------- ++// 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) ++//---------------------------------------------------------------------------- ++//IOL config for REG_FDHM0(Reg0x88) ++#define CMD_INIT_LLT BIT0 ++#define CMD_READ_EFUSE_MAP BIT1 ++#define CMD_EFUSE_PATCH BIT2 ++#define CMD_IOCONFIG BIT3 ++#define CMD_INIT_LLT_ERR BIT4 ++#define CMD_READ_EFUSE_MAP_ERR BIT5 ++#define CMD_EFUSE_PATCH_ERR BIT6 ++#define CMD_IOCONFIG_ERR BIT7 ++ ++// ++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) ++// ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x181, 24bits) ++//---------------------------------------------------------------------------- ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++ ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x1BF, 8bits) ++//---------------------------------------------------------------------------- ++// WOL bit information ++#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 ++#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 ++ ++//---------------------------------------------------------------------------- ++// 8192C BW_OPMODE bits (Offset 0x203, 8bit) ++//---------------------------------------------------------------------------- ++#define BW_OPMODE_20MHZ BIT2 ++#define BW_OPMODE_5G BIT1 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C CAM Config Setting (offset 0x250, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_CONTENT_COUNT 8 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++#define CAM_SMS4 0x6 ++ ++#define TOTAL_CAM_ENTRY 32 ++#define HALF_CAM_ENTRY 16 ++ ++#define CAM_CONFIG_USEDK _TRUE ++#define CAM_CONFIG_NO_USEDK _FALSE ++ ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++ ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++// ++// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) ++// ++#define WOW_PMEN BIT0 // Power management Enable. ++#define WOW_WOMEN BIT1 // WoW function on or off. ++#define WOW_MAGIC BIT2 // Magic packet ++#define WOW_UWF BIT3 // Unicast Wakeup frame. ++ ++// ++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) ++// ++//---------------------------------------------------------------------------- ++//---------------------------------------------------------------------------- ++// 8188 IMR/ISR bits ++//---------------------------------------------------------------------------- ++#define IMR_DISABLED_88E 0x0 ++// IMR DW0(0x0060-0063) Bit 0-31 ++#define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set ++#define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt ++#define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1 ++#define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1 ++#define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error ++#define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK ++#define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt ++#define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0 ++#define IMR_BCNDERR0_88E BIT16 // Beacon Queue DMA Error 0 ++#define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) ++#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 ++#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End ++#define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) ++#define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear ++#define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear ++#define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear ++#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK ++#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK ++#define IMR_BKDOK_88E BIT5 // AC_BK DMA OK ++#define IMR_BEDOK_88E BIT4 // AC_BE DMA OK ++#define IMR_VIDOK_88E BIT3 // AC_VI DMA OK ++#define IMR_VODOK_88E BIT2 // AC_VO DMA OK ++#define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable ++#define IMR_ROK_88E BIT0 // Receive DMA OK ++ ++// IMR DW1(0x00B4-00B7) Bit 0-31 ++#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 ++#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 ++#define IMR_BCNDERR7_88E BIT20 // Beacon Queue DMA Error Interrup 7 ++#define IMR_BCNDERR6_88E BIT19 // Beacon Queue DMA Error Interrup 6 ++#define IMR_BCNDERR5_88E BIT18 // Beacon Queue DMA Error Interrup 5 ++#define IMR_BCNDERR4_88E BIT17 // Beacon Queue DMA Error Interrup 4 ++#define IMR_BCNDERR3_88E BIT16 // Beacon Queue DMA Error Interrup 3 ++#define IMR_BCNDERR2_88E BIT15 // Beacon Queue DMA Error Interrup 2 ++#define IMR_BCNDERR1_88E BIT14 // Beacon Queue DMA Error Interrup 1 ++#define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7 ++#define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. ++#define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear ++#define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow ++#define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow ++ ++#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI. ++ ++ ++#ifdef CONFIG_PCI_HCI ++//#define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) ++#define IMR_TX_MASK (IMR_VODOK_88E|IMR_VIDOK_88E|IMR_BEDOK_88E|IMR_BKDOK_88E|IMR_MGNTDOK_88E|IMR_HIGHDOK_88E|IMR_BCNDERR0_88E) ++ ++#ifdef CONFIG_CONCURRENT_MODE ++#define RT_IBSS_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E) ++#else ++#define RT_IBSS_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E) ++#endif ++ ++#define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E|IMR_BKDOK_88E) ++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS) ++#endif ++ ++ ++// 8192C EFUSE ++//---------------------------------------------------------------------------- ++#define HWSET_MAX_SIZE 256 ++#define HWSET_MAX_SIZE_88E 512 ++ ++ ++ ++/*=================================================================== ++===================================================================== ++Here the register defines are for 92C. When the define is as same with 92C, ++we will use the 92C's define for the consistency ++So the following defines for 92C is not entire!!!!!! ++===================================================================== ++=====================================================================*/ ++/* ++Based on Datasheet V33---090401 ++Register Summary ++Current IOREG MAP ++0x0000h ~ 0x00FFh System Configuration (256 Bytes) ++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) ++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) ++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) ++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) ++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) ++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) ++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) ++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) ++*/ ++ //---------------------------------------------------------------------------- ++ // 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) ++ //---------------------------------------------------------------------------- ++// Note: ++// The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, ++// the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. ++// 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. ++// By Bruce, 2011-09-22. ++#define StopBecon BIT6 ++#define StopHigh BIT5 ++#define StopMgt BIT4 ++#define StopBK BIT3 ++#define StopBE BIT2 ++#define StopVI BIT1 ++#define StopVO BIT0 ++ ++//---------------------------------------------------------------------------- ++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) ++//---------------------------------------------------------------------------- ++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload ++#define RCR_APP_MIC BIT30 // ++#define RCR_APP_PHYSTS BIT28// ++#define RCR_APP_ICV BIT29 // ++#define RCR_APP_PHYST_RXFF BIT28 // ++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN ++#define RCR_ENMBID BIT24 //Enable Multiple BssId. ++#define RCR_LSIGEN BIT23 ++#define RCR_MFBEN BIT22 ++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 ++#define RCR_AMF BIT13 //Accept management type frame ++#define RCR_ACF BIT12 //Accept control type frame ++#define RCR_ADF BIT11 //Accept data type frame ++#define RCR_AICV BIT9 //Accept ICV error packet ++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet ++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) ++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) ++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet ++#define RCR_APWRMGT BIT5 //Accept power management packet ++#define RCR_ADD3 BIT4 //Accept address 3 match packet ++#define RCR_AB BIT3 //Accept broadcast packet ++#define RCR_AM BIT2 //Accept multicast packet ++#define RCR_APM BIT1 //Accept physical match packet ++#define RCR_AAP BIT0 //Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++#define REG_USB_HRPWM 0xFE58 ++#define REG_USB_HCPWM 0xFE57 ++ ++//============================================================================ ++// 8192C Regsiter Bit and Content definition ++//============================================================================ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SYS_ISO_CTRL ++#define ISO_MD2PP BIT(0) ++#define ISO_UA2USB BIT(1) ++#define ISO_UD2CORE BIT(2) ++#define ISO_PA2PCIE BIT(3) ++#define ISO_PD2CORE BIT(4) ++#define ISO_IP2MAC BIT(5) ++#define ISO_DIOP BIT(6) ++#define ISO_DIOE BIT(7) ++#define ISO_EB2CORE BIT(8) ++#define ISO_DIOR BIT(9) ++#define PWC_EV12V BIT(15) ++ ++ ++//2 SYS_FUNC_EN ++#define FEN_BBRSTB BIT(0) ++#define FEN_BB_GLB_RSTn BIT(1) ++#define FEN_USBA BIT(2) ++#define FEN_UPLL BIT(3) ++#define FEN_USBD BIT(4) ++#define FEN_DIO_PCIE BIT(5) ++#define FEN_PCIEA BIT(6) ++#define FEN_PPLL BIT(7) ++#define FEN_PCIED BIT(8) ++#define FEN_DIOE BIT(9) ++#define FEN_CPUEN BIT(10) ++#define FEN_DCORE BIT(11) ++#define FEN_ELDR BIT(12) ++#define FEN_DIO_RF BIT(13) ++#define FEN_HWPDN BIT(14) ++#define FEN_MREGEN BIT(15) ++ ++//2 APS_FSMCO ++#define PFM_LDALL BIT(0) ++#define PFM_ALDN BIT(1) ++#define PFM_LDKP BIT(2) ++#define PFM_WOWL BIT(3) ++#define EnPDN BIT(4) ++#define PDN_PL BIT(5) ++#define APFM_ONMAC BIT(8) ++#define APFM_OFF BIT(9) ++#define APFM_RSM BIT(10) ++#define AFSM_HSUS BIT(11) ++#define AFSM_PCIE BIT(12) ++#define APDM_MAC BIT(13) ++#define APDM_HOST BIT(14) ++#define APDM_HPDN BIT(15) ++#define RDY_MACON BIT(16) ++#define SUS_HOST BIT(17) ++#define ROP_ALD BIT(20) ++#define ROP_PWR BIT(21) ++#define ROP_SPS BIT(22) ++#define SOP_MRST BIT(25) ++#define SOP_FUSE BIT(26) ++#define SOP_ABG BIT(27) ++#define SOP_AMB BIT(28) ++#define SOP_RCK BIT(29) ++#define SOP_A8M BIT(30) ++#define XOP_BTCK BIT(31) ++ ++//2 SYS_CLKR ++#define ANAD16V_EN BIT(0) ++#define ANA8M BIT(1) ++#define MACSLP BIT(4) ++#define LOADER_CLK_EN BIT(5) ++ ++ ++//2 9346CR ++ ++#define BOOT_FROM_EEPROM BIT(4) ++#define EEPROM_EN BIT(5) ++ ++ ++//2 SPS0_CTRL ++ ++ ++//2 SPS_OCP_CFG ++ ++ ++//2 RF_CTRL ++#define RF_EN BIT(0) ++#define RF_RSTB BIT(1) ++#define RF_SDMRSTB BIT(2) ++ ++ ++ ++//2 LDOV12D_CTRL ++#define LDV12_EN BIT(0) ++#define LDV12_SDBY BIT(1) ++#define LPLDO_HSM BIT(2) ++#define LPLDO_LSM_DIS BIT(3) ++#define _LDV12_VADJ(x) (((x) & 0xF) << 4) ++ ++ ++//2EFUSE_CTRL ++#define ALD_EN BIT(18) ++#define EF_PD BIT(19) ++#define EF_FLAG BIT(31) ++ ++//2 EFUSE_TEST (For RTL8723 partially) ++#define EF_TRPT BIT(7) ++#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 ++#define LDOE25_EN BIT(31) ++#define EFUSE_SEL(x) (((x) & 0x3) << 8) ++#define EFUSE_SEL_MASK 0x300 ++#define EFUSE_WIFI_SEL_0 0x0 ++#define EFUSE_BT_SEL_0 0x1 ++#define EFUSE_BT_SEL_1 0x2 ++#define EFUSE_BT_SEL_2 0x3 ++ ++#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. ++#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. ++ ++ ++//2 8051FWDL ++//2 MCUFWDL ++#define MCUFWDL_EN BIT(0) ++#define MCUFWDL_RDY BIT(1) ++#define FWDL_ChkSum_rpt BIT(2) ++#define MACINI_RDY BIT(3) ++#define BBINI_RDY BIT(4) ++#define RFINI_RDY BIT(5) ++#define WINTINI_RDY BIT(6) ++#define RAM_DL_SEL BIT(7) // 1:RAM, 0:ROM ++#define ROM_DLEN BIT(19) ++#define CPRST BIT(23) ++ ++ ++ ++//2 REG_SYS_CFG ++#define XCLK_VLD BIT(0) ++#define ACLK_VLD BIT(1) ++#define UCLK_VLD BIT(2) ++#define PCLK_VLD BIT(3) ++#define PCIRSTB BIT(4) ++#define V15_VLD BIT(5) ++#define SW_OFFLOAD_EN BIT(7) ++#define SIC_IDLE BIT(8) ++#define BD_MAC2 BIT(9) ++#define BD_MAC1 BIT(10) ++#define IC_MACPHY_MODE BIT(11) ++#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ++#define BT_FUNC BIT(16) ++#define VENDOR_ID BIT(19) ++#define PAD_HWPD_IDN BIT(22) ++#define TRP_VAUX_EN BIT(23) // RTL ID ++#define TRP_BT_EN BIT(24) ++#define BD_PKG_SEL BIT(25) ++#define BD_HCI_SEL BIT(26) ++#define TYPE_ID BIT(27) ++ ++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 ++#define CHIP_VER_RTL_SHIFT 12 ++ ++ ++//2REG_GPIO_OUTSTS (For RTL8723 only) ++#define EFS_HCI_SEL (BIT(0)|BIT(1)) ++#define PAD_HCI_SEL (BIT(2)|BIT(3)) ++#define HCI_SEL (BIT(4)|BIT(5)) ++#define PKG_SEL_HCI BIT(6) ++#define FEN_GPS BIT(7) ++#define FEN_BT BIT(8) ++#define FEN_WL BIT(9) ++#define FEN_PCI BIT(10) ++#define FEN_USB BIT(11) ++#define BTRF_HWPDN_N BIT(12) ++#define WLRF_HWPDN_N BIT(13) ++#define PDN_BT_N BIT(14) ++#define PDN_GPS_N BIT(15) ++#define BT_CTL_HWPDN BIT(16) ++#define GPS_CTL_HWPDN BIT(17) ++#define PPHY_SUSB BIT(20) ++#define UPHY_SUSB BIT(21) ++#define PCI_SUSEN BIT(22) ++#define USB_SUSEN BIT(23) ++#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) ++ ++ ++//2SYS_CFG ++#define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL) ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++ ++//2 Function Enable Registers ++//2 CR ++ ++ ++ ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++#define CALTMR_EN BIT(10) // 32k CAL TMR enable ++ ++// Network type ++#define _NETTYPE(x) (((x) & 0x3) << 16) ++#define MASK_NETTYPE 0x30000 ++#define NT_NO_LINK 0x0 ++#define NT_LINK_AD_HOC 0x1 ++#define NT_LINK_AP 0x2 ++#define NT_AS_AP 0x3 ++ ++ ++ ++//2 PBP - Page Size Register ++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) ++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) ++#define _PSRX_MASK 0xF ++#define _PSTX_MASK 0xF0 ++#define _PSRX(x) (x) ++#define _PSTX(x) ((x) << 4) ++ ++#define PBP_64 0x0 ++#define PBP_128 0x1 ++#define PBP_256 0x2 ++#define PBP_512 0x3 ++#define PBP_1024 0x4 ++ ++ ++//2 TX/RXDMA ++#define RXDMA_ARBBW_EN BIT(0) ++#define RXSHFT_EN BIT(1) ++#define RXDMA_AGG_EN BIT(2) ++#define QS_VO_QUEUE BIT(8) ++#define QS_VI_QUEUE BIT(9) ++#define QS_BE_QUEUE BIT(10) ++#define QS_BK_QUEUE BIT(11) ++#define QS_MANAGER_QUEUE BIT(12) ++#define QS_HIGH_QUEUE BIT(13) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++// For normal driver, 0x10C ++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) ++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) ++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) ++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) ++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++ ++ ++//2 TRXFF_BNDY ++ ++ ++//2 LLT_INIT ++#define _LLT_NO_ACTIVE 0x0 ++#define _LLT_WRITE_ACCESS 0x1 ++#define _LLT_READ_ACCESS 0x2 ++ ++#define _LLT_INIT_DATA(x) ((x) & 0xFF) ++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) ++#define _LLT_OP(x) (((x) & 0x3) << 30) ++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++//2RQPN ++#define _HPQ(x) ((x) & 0xFF) ++#define _LPQ(x) (((x) & 0xFF) << 8) ++#define _PUBQ(x) (((x) & 0xFF) << 16) ++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register ++ ++ ++#define HPQ_PUBLIC_DIS BIT(24) ++#define LPQ_PUBLIC_DIS BIT(25) ++#define LD_RQPN BIT(31) ++ ++ ++//2TDECTRL ++#define BCN_VALID BIT(16) ++#define BCN_HEAD(x) (((x) & 0xFF) << 8) ++#define BCN_HEAD_MASK 0xFF00 ++ ++ ++//2 TDECTL ++#define BLK_DESC_NUM_SHIFT 4 ++#define BLK_DESC_NUM_MASK 0xF ++ ++ ++//2 TXDMA_OFFSET_CHK ++#define DROP_DATA_EN BIT(9) ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x028Bh RX DMA Configuration ++// ++//----------------------------------------------------- ++ ++// REG_RXDMA_CONTROL, 0x0286h ++// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before ++// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. ++//#define RXPKT_RELEASE_POLL BIT(0) ++// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in ++// this bit. FW can start releasing packets after RXDMA entering idle mode. ++//#define RXDMA_IDLE BIT(1) ++// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host ++// completed, and stop DMA packet to host. RXDMA will then report Default: 0; ++//#define RW_RELEASE_EN BIT(2) ++ ++//2 REG_RXPKT_NUM, 0x0284 ++#define RXPKT_RELEASE_POLL BIT(16) ++#define RXDMA_IDLE BIT(17) ++#define RW_RELEASE_EN BIT(18) ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//2 FWHW_TXQ_CTRL ++#define EN_AMPDU_RTY_NEW BIT(7) ++ ++ ++//2 SPEC SIFS ++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) ++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) ++ ++//2 RL ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++ ++ ++//2 EDCA setting ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ ++ ++ ++#define _LRL(x) ((x) & 0x3F) ++#define _SRL(x) (((x) & 0x3F) << 8) ++ ++ ++//2 BCN_CTRL ++#define EN_MBSSID BIT(1) ++#define EN_TXBCN_RPT BIT(2) ++#define EN_BCN_FUNCTION BIT(3) ++#define DIS_TSF_UPDATE BIT(3) ++ ++// The same function but different bit field. ++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) ++#define DIS_TSF_UDT0_TEST_CHIP BIT(5) ++#define STOP_BCNQ BIT(6) ++ ++ ++//2 ACMHWCTRL ++#define AcmHw_HwEn BIT(0) ++#define AcmHw_BeqEn BIT(1) ++#define AcmHw_ViqEn BIT(2) ++#define AcmHw_VoqEn BIT(3) ++#define AcmHw_BeqStatus BIT(4) ++#define AcmHw_ViqStatus BIT(5) ++#define AcmHw_VoqStatus BIT(6) ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++//2APSD_CTRL ++#define APSDOFF BIT(6) ++#define APSDOFF_STATUS BIT(7) ++ ++ ++#define RATE_BITMAP_ALL 0xFFFFF ++ ++// Only use CCK 1M rate for ACK ++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 ++ ++//2 TCR ++#define TSFRST BIT(0) ++#define DIS_GCLK BIT(1) ++#define PAD_SEL BIT(2) ++#define PWR_ST BIT(6) ++#define PWRBIT_OW_EN BIT(7) ++#define ACRC BIT(8) ++#define CFENDFORM BIT(9) ++#define ICV BIT(10) ++ ++ ++ ++//2 RCR ++#define AAP BIT(0) ++#define APM BIT(1) ++#define AM BIT(2) ++#define AB BIT(3) ++#define ADD3 BIT(4) ++#define APWRMGT BIT(5) ++#define CBSSID BIT(6) ++#define CBSSID_DATA BIT(6) ++#define CBSSID_BCN BIT(7) ++#define ACRC32 BIT(8) ++#define AICV BIT(9) ++#define ADF BIT(11) ++#define ACF BIT(12) ++#define AMF BIT(13) ++#define HTC_LOC_CTRL BIT(14) ++#define UC_DATA_EN BIT(16) ++#define BM_DATA_EN BIT(17) ++#define MFBEN BIT(22) ++#define LSIGEN BIT(23) ++#define EnMBID BIT(24) ++#define APP_BASSN BIT(27) ++#define APP_PHYSTS BIT(28) ++#define APP_ICV BIT(29) ++#define APP_MIC BIT(30) ++#define APP_FCS BIT(31) ++ ++ ++//2 SECCFG ++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key ++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption ++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption ++#define SCR_SKByA2 BIT(4) //Search kEY BY A2 ++#define SCR_NoSKMC BIT(5) //No Key Search Multicast ++#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key ++#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key ++ ++ ++//----------------------------------------------------- ++// ++// RTL8188E SDIO Configuration ++// ++//----------------------------------------------------- ++ ++// I/O bus domain address mapping ++#define SDIO_LOCAL_BASE 0x10250000 ++#define WLAN_IOREG_BASE 0x10260000 ++#define FIRMWARE_FIFO_BASE 0x10270000 ++#define TX_HIQ_BASE 0x10310000 ++#define TX_MIQ_BASE 0x10320000 ++#define TX_LOQ_BASE 0x10330000 ++#define RX_RX0FF_BASE 0x10340000 ++ ++// SDIO host local register space mapping. ++#define SDIO_LOCAL_MSK 0x0FFF ++#define WLAN_IOREG_MSK 0x7FFF ++#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] ++#define WLAN_RX0FF_MSK 0x0003 ++ ++#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID ++#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] ++#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] ++#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] ++#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] ++#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] ++#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] ++ ++// SDIO Tx Free Page Index ++#define HI_QUEUE_IDX 0 ++#define MID_QUEUE_IDX 1 ++#define LOW_QUEUE_IDX 2 ++#define PUBLIC_QUEUE_IDX 3 ++ ++#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ ++#define SDIO_MAX_RX_QUEUE 1 ++ ++#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control ++#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask ++#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine ++#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode ++#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length ++#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page ++#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 ++#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 ++#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion ++#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 ++#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 ++#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock ++#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control ++#define SDIO_REG_HIMR_ON 0x0090 // SDIO Host Extension Interrupt Mask Always ++#define SDIO_REG_HISR_ON 0x0091 // SDIO Host Extension Interrupt Status Always ++ ++#define SDIO_HIMR_DISABLED 0 ++ ++// RTL8188E SDIO Host Interrupt Mask Register ++#define SDIO_HIMR_RX_REQUEST_MSK BIT0 ++#define SDIO_HIMR_AVAL_MSK BIT1 ++#define SDIO_HIMR_TXERR_MSK BIT2 ++#define SDIO_HIMR_RXERR_MSK BIT3 ++#define SDIO_HIMR_TXFOVW_MSK BIT4 ++#define SDIO_HIMR_RXFOVW_MSK BIT5 ++#define SDIO_HIMR_TXBCNOK_MSK BIT6 ++#define SDIO_HIMR_TXBCNERR_MSK BIT7 ++#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 ++#define SDIO_HIMR_C2HCMD_MSK BIT17 ++#define SDIO_HIMR_CPWM1_MSK BIT18 ++#define SDIO_HIMR_CPWM2_MSK BIT19 ++#define SDIO_HIMR_HSISR_IND_MSK BIT20 ++#define SDIO_HIMR_GTINT3_IND_MSK BIT21 ++#define SDIO_HIMR_GTINT4_IND_MSK BIT22 ++#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 ++#define SDIO_HIMR_OCPINT_MSK BIT24 ++#define SDIO_HIMR_ATIMEND_MSK BIT25 ++#define SDIO_HIMR_ATIMEND_E_MSK BIT26 ++#define SDIO_HIMR_CTWEND_MSK BIT27 ++ ++//RTL8188E SDIO Specific ++#define SDIO_HIMR_MCU_ERR_MSK BIT28 ++#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 ++ ++// SDIO Host Interrupt Service Routine ++#define SDIO_HISR_RX_REQUEST BIT0 ++#define SDIO_HISR_AVAL BIT1 ++#define SDIO_HISR_TXERR BIT2 ++#define SDIO_HISR_RXERR BIT3 ++#define SDIO_HISR_TXFOVW BIT4 ++#define SDIO_HISR_RXFOVW BIT5 ++#define SDIO_HISR_TXBCNOK BIT6 ++#define SDIO_HISR_TXBCNERR BIT7 ++#define SDIO_HISR_BCNERLY_INT BIT16 ++#define SDIO_HISR_C2HCMD BIT17 ++#define SDIO_HISR_CPWM1 BIT18 ++#define SDIO_HISR_CPWM2 BIT19 ++#define SDIO_HISR_HSISR_IND BIT20 ++#define SDIO_HISR_GTINT3_IND BIT21 ++#define SDIO_HISR_GTINT4_IND BIT22 ++#define SDIO_HISR_PSTIMEOUT BIT23 ++#define SDIO_HISR_OCPINT BIT24 ++#define SDIO_HISR_ATIMEND BIT25 ++#define SDIO_HISR_ATIMEND_E BIT26 ++#define SDIO_HISR_CTWEND BIT27 ++ ++//RTL8188E SDIO Specific ++#define SDIO_HISR_MCU_ERR BIT28 ++#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 ++ ++#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ ++ SDIO_HISR_RXERR |\ ++ SDIO_HISR_TXFOVW |\ ++ SDIO_HISR_RXFOVW |\ ++ SDIO_HISR_TXBCNOK |\ ++ SDIO_HISR_TXBCNERR |\ ++ SDIO_HISR_C2HCMD |\ ++ SDIO_HISR_CPWM1 |\ ++ SDIO_HISR_CPWM2 |\ ++ SDIO_HISR_HSISR_IND |\ ++ SDIO_HISR_GTINT3_IND |\ ++ SDIO_HISR_GTINT4_IND |\ ++ SDIO_HISR_PSTIMEOUT |\ ++ SDIO_HISR_OCPINT) ++ ++// SDIO HCI Suspend Control Register ++#define HCI_RESUME_PWR_RDY BIT1 ++#define HCI_SUS_CTRL BIT0 ++ ++// SDIO Tx FIFO related ++#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page ++#define SDIO_TX_FIFO_PAGE_SZ 128 ++ ++/* move to rtl8188e_xmit.h ++#if DEV_BUS_TYPE == RT_SDIO_INTERFACE ++ #define MAX_TX_AGG_PACKET_NUMBER 0x8 ++#else ++ #define MAX_TX_AGG_PACKET_NUMBER 0xFF ++#endif ++*/ ++ ++// vivi added for new cam search flow, 20091028 ++//#define SCR_TxUseBroadcastDK BIT6 // Force Tx Use Broadcast Default Key ++//#define SCR_RxUseBroadcastDK BIT7 // Force Rx Use Broadcast Default Key ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++ ++//2 USB Information (0xFE17) ++#define USB_IS_HIGH_SPEED 0 ++#define USB_IS_FULL_SPEED 1 ++#define USB_SPEED_MASK BIT(5) ++ ++#define USB_NORMAL_SIE_EP_MASK 0xF ++#define USB_NORMAL_SIE_EP_SHIFT 4 ++ ++ ++//2 Special Option ++#define USB_AGG_EN BIT(3) ++ ++// 0; Use interrupt endpoint to upload interrupt pkt ++// 1; Use bulk endpoint to upload interrupt pkt, ++#define INT_BULK_SEL BIT(4) ++ ++ ++ ++//2REG_C2HEVT_CLEAR ++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message ++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. ++ ++ ++//2REG_MULTI_FUNC_CTRL(For RTL8723 Only) ++#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source ++#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control ++#define WL_FUNC_EN BIT2 // WiFi function enable ++#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source ++#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source ++#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control ++#define BT_FUNC_EN BIT18 // BT function enable ++#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source ++#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source ++#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control ++#define GPS_FUNC_EN BIT22 // GPS function enable ++ ++ ++//3 REG_LIFECTRL_CTRL ++#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 ++#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 ++#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 ++#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 ++ ++#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. ++ ++//======================================================== ++// General definitions ++//======================================================== ++//#if (HAL_8195A_USB == 1) ++//#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 ++//#else ++#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 // 22k 22528 bytes ++//#endif ++ ++#define POLLING_LLT_THRESHOLD 20 ++//#if RTL8188E_FOR_MP_TEST == 1 ++//#define POLLING_READY_TIMEOUT_COUNT 3000 ++//#else ++#define POLLING_READY_TIMEOUT_COUNT 1000 ++//#endif ++// GPIO BIT ++#define HAL_8188E_HW_GPIO_WPS_BIT BIT7 ++ ++#if 0//(RTL8188E_SUPPORT == 1) ++////////////////////////////////ONLY for 88EE///////////////////////////////// ++// ++// Host Interrupt Status Registers (Offset: 0x00B4-00B7, 0x00BC-00BF) ++// Host Interrupt Mask Registers (Offset: 0x00B0-00B3, 0x00B8-00BB) ++// ++//---------------------------------------------------------------------------- ++// 8188 IMR/ISR bits ++//---------------------------------------------------------------------------- ++#define IMR_DISABLED_88E 0x0 ++// IMR DW0(0x00B0-00B3) Bit 0-31 ++#define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set ++#define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt ++#define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1 ++#define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1 ++#define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error ++#define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK ++#define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt ++#define IMR_BcnInt_88E BIT20 // Beacon DMA Interrupt 0 ++#define IMR_BDOK_88E BIT16 // Beacon Queue DMA OK0 ++#define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) ++#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 ++#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End ++#define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) ++#define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear ++#define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear ++#define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear ++#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK ++#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK ++#define IMR_BKDOK_88E BIT5 // AC_BK DMA OK ++#define IMR_BEDOK_88E BIT4 // AC_BE DMA OK ++#define IMR_VIDOK_88E BIT3 // AC_VI DMA OK ++#define IMR_VODOK_88E BIT2 // AC_VO DMA OK ++#define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable ++#define IMR_ROK_88E BIT0 // Receive DMA OK ++ ++// IMR DW1(0x00B8-00BB) Bit 0-31 ++#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 ++#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 ++#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7 ++#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6 ++#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5 ++#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4 ++#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3 ++#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2 ++#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1 ++#define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7 ++#define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. ++#define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear ++#define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow ++#define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow ++ ++ ++ ++////////////////////////////////ONLY for 88EE///////////////////////////////// ++#endif //(RTL8188E_SUPPORT == 1) ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C EEPROM/EFUSE share register definition. ++//---------------------------------------------------------------------------- ++ ++//==================================================== ++// EEPROM/Efuse PG Offset for 88EE/88EU/88ES ++//==================================================== ++#define EEPROM_TX_PWR_INX_88E 0x10 ++ ++#define EEPROM_ChannelPlan_88E 0xB8 ++#define EEPROM_XTAL_88E 0xB9 ++#define EEPROM_THERMAL_METER_88E 0xBA ++#define EEPROM_IQK_LCK_88E 0xBB ++ ++#define EEPROM_RF_BOARD_OPTION_88E 0xC1 ++#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 ++#define EEPROM_RF_BT_SETTING_88E 0xC3 ++#define EEPROM_VERSION_88E 0xC4 ++#define EEPROM_CUSTOMERID_88E 0xC5 ++#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++#define EEPROM_RF_GAIN_OFFSET_88E 0xC1 ++#define EEPROM_RF_GAIN_VAL_88E 0xF6 //Physical address which is the BB gain offset value ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++// RTL88EE ++#define EEPROM_MAC_ADDR_88EE 0xD0 ++#define EEPROM_VID_88EE 0xD6 ++#define EEPROM_DID_88EE 0xD8 ++#define EEPROM_SVID_88EE 0xDA ++#define EEPROM_SMID_88EE 0xDC ++ ++//RTL88EU ++#define EEPROM_MAC_ADDR_88EU 0xD7 ++#define EEPROM_VID_88EU 0xD0 ++#define EEPROM_PID_88EU 0xD2 ++#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 ++ ++// RTL88ES ++#define EEPROM_MAC_ADDR_88ES 0x11A ++ ++ ++ ++ ++//==================================================== ++// EEPROM/Efuse Value Type ++//==================================================== ++#define EETYPE_TX_PWR 0x0 ++ ++// ++// Default Value for EEPROM or EFUSE!!! ++// ++#define EEPROM_Default_TSSI 0x0 ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_CrystalCap 0x5 ++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_Default_HT2T_TxPwr 0x10 ++ ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_ThermalMeter 0x12 ++ ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#if (RTL8188ES_SUPPORT==1) //for SDIO ++#define EEPROM_Default_TxPowerLevel 0x25 ++#else //for USB/PCIE ++#define EEPROM_Default_TxPowerLevel 0x2A ++#endif ++ ++#define EEPROM_Default_HT40_2SDiff 0x0 ++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_HT40_PwrMaxOffset 0 ++#define EEPROM_Default_HT20_PwrMaxOffset 0 ++ ++#define EEPROM_Default_CrystalCap_88E 0x20 ++#define EEPROM_Default_ThermalMeter_88E 0x18 ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++#define EEPROM_Default_RFGainOffset 0xff ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++//New EFUSE deafult value ++#define EEPROM_DEFAULT_24G_INDEX 0x2D ++#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 ++#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 ++ ++#define EEPROM_DEFAULT_5G_INDEX 0X2A ++#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 ++#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 ++ ++#define EEPROM_DEFAULT_DIFF 0XFE ++#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F ++#define EEPROM_DEFAULT_BOARD_OPTION 0x00 ++#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 ++#define EEPROM_DEFAULT_BT_OPTION 0x10 ++ ++ ++// For debug ++#define EEPROM_Default_PID 0x1234 ++#define EEPROM_Default_VID 0x5678 ++#define EEPROM_Default_CustomerID 0xAB ++#define EEPROM_Default_CustomerID_8188E 0x00 ++#define EEPROM_Default_SubCustomerID 0xCD ++#define EEPROM_Default_Version 0 ++ ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_NCC 0xB ++#define EEPROM_USB_OPTIONAL1 0xE ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_TOSHIBA 0x4 ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#define EEPROM_CID_QMI 0x0D ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define RTL_EEPROM_ID 0x8129 ++ ++#endif //__RTL8188E_SPEC_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_sreset.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_sreset.h +new file mode 100644 +index 00000000..67ae34c4 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_sreset.h +@@ -0,0 +1,33 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8188E_SRESET_H_ ++#define _RTL8188E_SRESET_H_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter); ++extern void rtl8188e_sreset_linked_status_check(_adapter *padapter); ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_xmit.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_xmit.h +new file mode 100644 +index 00000000..842afc1a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8188e_xmit.h +@@ -0,0 +1,311 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8188E_XMIT_H__ ++#define __RTL8188E_XMIT_H__ ++ ++#define MAX_TX_AGG_PACKET_NUMBER 0xFF ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x2//0x01 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x5//0x4 ++#define QSLT_VO 0x7//0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++//For 88e early mode ++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) ++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) ++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) ++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) ++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) ++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) ++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) ++ ++// ++//defined for TX DESC Operation ++// ++ ++#define MAX_TID (15) ++ ++//OFFSET 0 ++#define OFFSET_SZ 0 ++#define OFFSET_SHT 16 ++#define BMC BIT(24) ++#define LSG BIT(26) ++#define FSG BIT(27) ++#define OWN BIT(31) ++ ++ ++//OFFSET 4 ++#define PKT_OFFSET_SZ 0 ++#define QSEL_SHT 8 ++#define RATE_ID_SHT 16 ++#define NAVUSEHDR BIT(20) ++#define SEC_TYPE_SHT 22 ++#define PKT_OFFSET_SHT 26 ++ ++//OFFSET 8 ++#define AGG_EN BIT(12) ++#define AGG_BK BIT(16) ++#define AMPDU_DENSITY_SHT 20 ++#define ANTSEL_A BIT(24) ++#define ANTSEL_B BIT(25) ++#define TX_ANT_CCK_SHT 26 ++#define TX_ANTL_SHT 28 ++#define TX_ANT_HT_SHT 30 ++ ++//OFFSET 12 ++#define SEQ_SHT 16 ++#define EN_HWSEQ BIT(31) ++ ++//OFFSET 16 ++#define QOS BIT(6) ++#define HW_SSN BIT(7) ++#define USERATE BIT(8) ++#define DISDATAFB BIT(10) ++#define CTS_2_SELF BIT(11) ++#define RTS_EN BIT(12) ++#define HW_RTS_EN BIT(13) ++#define DATA_SHORT BIT(24) ++#define PWR_STATUS_SHT 15 ++#define DATA_SC_SHT 20 ++#define DATA_BW BIT(25) ++ ++//OFFSET 20 ++#define RTY_LMT_EN BIT(17) ++ ++enum TXDESC_SC{ ++ SC_DONT_CARE = 0x00, ++ SC_UPPER= 0x01, ++ SC_LOWER=0x02, ++ SC_DUPLICATE=0x03 ++}; ++//OFFSET 20 ++#define SGI BIT(6) ++#define USB_TXAGG_NUM_SHT 24 ++ ++typedef struct txdesc_88e ++{ ++ //Offset 0 ++ u32 pktlen:16; ++ u32 offset:8; ++ u32 bmc:1; ++ u32 htc:1; ++ u32 ls:1; ++ u32 fs:1; ++ u32 linip:1; ++ u32 noacm:1; ++ u32 gf:1; ++ u32 own:1; ++ ++ //Offset 4 ++ u32 macid:6; ++ u32 rsvd0406:2; ++ u32 qsel:5; ++ u32 rd_nav_ext:1; ++ u32 lsig_txop_en:1; ++ u32 pifs:1; ++ u32 rate_id:4; ++ u32 navusehdr:1; ++ u32 en_desc_id:1; ++ u32 sectype:2; ++ u32 rsvd0424:2; ++ u32 pkt_offset:5; // unit: 8 bytes ++ u32 rsvd0431:1; ++ ++ //Offset 8 ++ u32 rts_rc:6; ++ u32 data_rc:6; ++ u32 agg_en:1; ++ u32 rd_en:1; ++ u32 bar_rty_th:2; ++ u32 bk:1; ++ u32 morefrag:1; ++ u32 raw:1; ++ u32 ccx:1; ++ u32 ampdu_density:3; ++ u32 bt_null:1; ++ u32 ant_sel_a:1; ++ u32 ant_sel_b:1; ++ u32 tx_ant_cck:2; ++ u32 tx_antl:2; ++ u32 tx_ant_ht:2; ++ ++ //Offset 12 ++ u32 nextheadpage:8; ++ u32 tailpage:8; ++ u32 seq:12; ++ u32 cpu_handle:1; ++ u32 tag1:1; ++ u32 trigger_int:1; ++ u32 hwseq_en:1; ++ ++ //Offset 16 ++ u32 rtsrate:5; ++ u32 ap_dcfe:1; ++ u32 hwseq_sel:2; ++ u32 userate:1; ++ u32 disrtsfb:1; ++ u32 disdatafb:1; ++ u32 cts2self:1; ++ u32 rtsen:1; ++ u32 hw_rts_en:1; ++ u32 port_id:1; ++ u32 pwr_status:3; ++ u32 wait_dcts:1; ++ u32 cts2ap_en:1; ++ u32 data_sc:2; ++ u32 data_stbc:2; ++ u32 data_short:1; ++ u32 data_bw:1; ++ u32 rts_short:1; ++ u32 rts_bw:1; ++ u32 rts_sc:2; ++ u32 vcs_stbc:2; ++ ++ //Offset 20 ++ u32 datarate:6; ++ u32 sgi:1; ++ u32 try_rate:1; ++ u32 data_ratefb_lmt:5; ++ u32 rts_ratefb_lmt:4; ++ u32 rty_lmt_en:1; ++ u32 data_rt_lmt:6; ++ u32 usb_txagg_num:8; ++ ++ //Offset 24 ++ u32 txagg_a:5; ++ u32 txagg_b:5; ++ u32 use_max_len:1; ++ u32 max_agg_num:5; ++ u32 mcsg1_max_len:4; ++ u32 mcsg2_max_len:4; ++ u32 mcsg3_max_len:4; ++ u32 mcs7_sgi_max_len:4; ++ ++ //Offset 28 ++ u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB) ++ u32 sw0:8; /* offset 30 */ ++ u32 sw1:4; ++ u32 mcs15_sgi_max_len:4; ++}TXDESC, *PTXDESC; ++ ++#define txdesc_set_ccx_sw_88e(txdesc, value) \ ++ do { \ ++ ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \ ++ ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \ ++ } while (0) ++ ++struct txrpt_ccx_88e { ++ /* offset 0 */ ++ u8 tag1:1; ++ u8 pkt_num:3; ++ u8 txdma_underflow:1; ++ u8 int_bt:1; ++ u8 int_tri:1; ++ u8 int_ccx:1; ++ ++ /* offset 1 */ ++ u8 mac_id:6; ++ u8 pkt_ok:1; ++ u8 bmc:1; ++ ++ /* offset 2 */ ++ u8 retry_cnt:6; ++ u8 lifetime_over:1; ++ u8 retry_over:1; ++ ++ /* offset 3 */ ++ u8 ccx_qtime0; ++ u8 ccx_qtime1; ++ ++ /* offset 5 */ ++ u8 final_data_rate; ++ ++ /* offset 6 */ ++ u8 sw1:4; ++ u8 qsel:4; ++ ++ /* offset 7 */ ++ u8 sw0; ++}; ++ ++#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) ++#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) ++ ++void rtl8188e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull); ++#ifdef CONFIG_SDIO_HCI ++s32 rtl8188es_init_xmit_priv(PADAPTER padapter); ++void rtl8188es_free_xmit_priv(PADAPTER padapter); ++s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); ++s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); ++s32 rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++thread_return rtl8188es_xmit_thread(thread_context context); ++s32 rtl8188es_xmit_buf_handler(PADAPTER padapter); ++#define hal_xmit_handler rtl8188es_xmit_buf_handler ++ ++#ifdef CONFIG_SDIO_TX_TASKLET ++void rtl8188es_xmit_tasklet(void *priv); ++#endif ++#endif ++ ++#ifdef CONFIG_USB_HCI ++s32 rtl8188eu_init_xmit_priv(PADAPTER padapter); ++void rtl8188eu_free_xmit_priv(PADAPTER padapter); ++s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); ++s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); ++s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter); ++#define hal_xmit_handler rtl8188eu_xmit_buf_handler ++void rtl8188eu_xmit_tasklet(void *priv); ++s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8188ee_init_xmit_priv(PADAPTER padapter); ++void rtl8188ee_free_xmit_priv(PADAPTER padapter); ++struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring); ++void rtl8188ee_xmitframe_resume(_adapter *padapter); ++s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); ++s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); ++void rtl8188ee_xmit_tasklet(void *priv); ++#endif ++ ++ ++ ++#ifdef CONFIG_TX_EARLY_MODE ++void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf ); ++#endif ++ ++#ifdef CONFIG_XMIT_ACK ++void dump_txrpt_ccx_88e(void *buf); ++void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf); ++#else ++#define dump_txrpt_ccx_88e(buf) do {} while(0) ++#define handle_txrpt_ccx_88e(adapter, buf) do {} while(0) ++#endif //CONFIG_XMIT_ACK ++ ++void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); ++#endif //__RTL8188E_XMIT_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_cmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_cmd.h +new file mode 100644 +index 00000000..de1be78a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_cmd.h +@@ -0,0 +1,116 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192C_CMD_H_ ++#define __RTL8192C_CMD_H_ ++ ++ ++enum cmd_msg_element_id ++{ ++ NONE_CMDMSG_EID, ++ AP_OFFLOAD_EID=0, ++ SET_PWRMODE_EID=1, ++ JOINBSS_RPT_EID=2, ++ RSVD_PAGE_EID=3, ++ RSSI_4_EID = 4, ++ RSSI_SETTING_EID=5, ++ MACID_CONFIG_EID=6, ++ MACID_PS_MODE_EID=7, ++ P2P_PS_OFFLOAD_EID=8, ++ SELECTIVE_SUSPEND_ROF_CMD=9, ++ P2P_PS_CTW_CMD_EID=32, ++ H2C_92C_IO_OFFLOAD=44, ++ H2C_92C_TSF_SYNC=67, ++ H2C_92C_DISABLE_BCN_FUNC=68, ++ H2C_92C_RESET_TSF = 75, ++ H2C_92C_CMD_MAX ++}; ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++typedef struct _SETPWRMODE_PARM{ ++ u8 Mode; ++ u8 SmartPS; ++ u8 BcnPassTime; // unit: 100ms ++}SETPWRMODE_PARM, *PSETPWRMODE_PARM; ++ ++struct H2C_SS_RFOFF_PARAM{ ++ u8 ROFOn; // 1: on, 0:off ++ u16 gpio_period; // unit: 1024 us ++}__attribute__ ((packed)); ++ ++ ++typedef struct JOINBSSRPT_PARM{ ++ u8 OpMode; // RT_MEDIA_STATUS ++}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM; ++ ++typedef struct _RSVDPAGE_LOC{ ++ u8 LocProbeRsp; ++ u8 LocPsPoll; ++ u8 LocNullData; ++}RSVDPAGE_LOC, *PRSVDPAGE_LOC; ++ ++struct P2P_PS_Offload_t { ++ unsigned char Offload_En:1; ++ unsigned char role:1; // 1: Owner, 0: Client ++ unsigned char CTWindow_En:1; ++ unsigned char NoA0_En:1; ++ unsigned char NoA1_En:1; ++ unsigned char AllStaSleep:1; // Only valid in Owner ++ unsigned char discovery:1; ++ unsigned char rsvd:1; ++}; ++ ++struct P2P_PS_CTWPeriod_t { ++ unsigned char CTWPeriod; //TU ++}; ++ ++// host message to firmware cmd ++void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode); ++void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus); ++u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param); ++u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg); ++void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level); ++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period); ++#ifdef CONFIG_P2P ++void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_IOL ++typedef struct _IO_OFFLOAD_LOC{ ++ u8 LocCmd; ++}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC; ++int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); ++#endif //CONFIG_IOL ++ ++#ifdef CONFIG_BEACON_DISABLE_OFFLOAD ++u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter); ++#endif // CONFIG_BEACON_DISABLE_OFFLOAD ++ ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++u8 rtl8192c_reset_tsf(_adapter *padapter, u8 reset_port); ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ ++#endif // __RTL8192C_CMD_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_dm.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_dm.h +new file mode 100644 +index 00000000..b017fb22 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_dm.h +@@ -0,0 +1,263 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192C_DM_H__ ++#define __RTL8192C_DM_H__ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++ ++//============================================================ ++// function prototype ++//============================================================ ++#define DYNAMIC_FUNC_BT BIT(0) ++ ++enum{ ++ UP_LINK, ++ DOWN_LINK, ++}; ++typedef enum _BT_Ant_NUM{ ++ Ant_x2 = 0, ++ Ant_x1 = 1 ++} BT_Ant_NUM, *PBT_Ant_NUM; ++ ++typedef enum _BT_CoType{ ++ BT_2Wire = 0, ++ BT_ISSC_3Wire = 1, ++ BT_Accel = 2, ++ BT_CSR_BC4 = 3, ++ BT_CSR_BC8 = 4, ++ BT_RTL8756 = 5, ++} BT_CoType, *PBT_CoType; ++ ++typedef enum _BT_CurState{ ++ BT_OFF = 0, ++ BT_ON = 1, ++} BT_CurState, *PBT_CurState; ++ ++typedef enum _BT_ServiceType{ ++ BT_SCO = 0, ++ BT_A2DP = 1, ++ BT_HID = 2, ++ BT_HID_Idle = 3, ++ BT_Scan = 4, ++ BT_Idle = 5, ++ BT_OtherAction = 6, ++ BT_Busy = 7, ++ BT_OtherBusy = 8, ++ BT_PAN = 9, ++} BT_ServiceType, *PBT_ServiceType; ++ ++typedef enum _BT_RadioShared{ ++ BT_Radio_Shared = 0, ++ BT_Radio_Individual = 1, ++} BT_RadioShared, *PBT_RadioShared; ++ ++struct btcoexist_priv { ++ u8 BT_Coexist; ++ u8 BT_Ant_Num; ++ u8 BT_CoexistType; ++ u8 BT_State; ++ u8 BT_CUR_State; //0:on, 1:off ++ u8 BT_Ant_isolation; //0:good, 1:bad ++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic ++ u8 BT_Service; ++ u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. ++ u8 BT_RadioSharedType; ++ u32 Ratio_Tx; ++ u32 Ratio_PRI; ++ u8 BtRfRegOrigin1E; ++ u8 BtRfRegOrigin1F; ++ u8 BtRssiState; ++ u32 BtEdcaUL; ++ u32 BtEdcaDL; ++ u32 BT_EDCA[2]; ++ u8 bCOBT; ++ ++ u8 bInitSet; ++ u8 bBTBusyTraffic; ++ u8 bBTTrafficModeSet; ++ u8 bBTNonTrafficModeSet; ++ //BTTraffic BT21TrafficStatistics; ++ u32 CurrentState; ++ u32 PreviousState; ++ u8 BtPreRssiState; ++ u8 bFWCoexistAllOff; ++ u8 bSWCoexistAllOff; ++}; ++ ++//============================================================ ++// structure and define ++//============================================================ ++ ++//###### duplicate code,will move to ODM ######### ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 9 ++#define HP_THERMAL_NUM 8 ++//###### duplicate code,will move to ODM ######### ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag; ++ u8 InitDMFlag; ++ u32 InitODMFlag; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ int MinUndecoratedPWDBForDM; ++ int LastMinUndecoratedPWDBForDM; ++ ++//###### duplicate code,will move to ODM ######### ++/* ++ //for DIG ++ u8 bDMInitialGainEnable; ++ u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++*/ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ ++ //for tx power tracking ++ u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_DPK; ++ ++ u8 bRfPiEnable; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ u8 bDPdone; ++ u8 bDPPathAOK; ++ u8 bDPPathBOK; ++ ++ //for IQK ++ u32 RegC04; ++ u32 Reg874; ++ u32 RegC08; ++ u32 RegB68; ++ u32 RegB6C; ++ u32 Reg870; ++ u32 Reg860; ++ u32 Reg864; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup_recover[9]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ u8 PowerIndex_backup[6]; ++ ++ u8 bCCKinCH14; ++ ++ u8 CCK_index; ++ u8 OFDM_index[2]; ++ ++ u8 bDoneTxpower; ++ u8 CCK_index_HP; ++ u8 OFDM_index_HP[2]; ++ u8 ThermalValue_HP[HP_THERMAL_NUM]; ++ u8 ThermalValue_HP_index; ++ ++ //for TxPwrTracking ++ s32 RegE94; ++ s32 RegE9C; ++ s32 RegEB4; ++ s32 RegEBC; ++ ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++/* ++ // for dm_RF_Saving ++ u8 initialize; ++ u32 rf_saving_Reg874; ++ u32 rf_saving_RegC70; ++ u32 rf_saving_Reg85C; ++ u32 rf_saving_RegA74; ++*/ ++ //for Antenna diversity ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// SWAT_T DM_SWAT_Table; ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++// _timer SwAntennaSwitchTimer; ++/* ++ u64 lastTxOkCnt; ++ u64 lastRxOkCnt; ++ u64 TXByteCnt_A; ++ u64 TXByteCnt_B; ++ u64 RXByteCnt_A; ++ u64 RXByteCnt_B; ++ u8 DoubleComfirm; ++ u8 TrafficLoad; ++*/ ++#endif ++ ++ s32 OFDM_Pkt_Cnt; ++ u8 RSSI_Select; ++// u8 DIG_Dynamic_MIN ; ++//###### duplicate code,will move to ODM ######### ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ u8 INIDATA_RATE[32]; ++}; ++ ++ ++//============================================================ ++// function prototype ++//============================================================ ++#ifdef CONFIG_BT_COEXIST ++void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart); ++void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir); ++#endif ++ ++void rtl8192c_init_dm_priv(IN PADAPTER Adapter); ++void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter); ++ ++void rtl8192c_InitHalDm( IN PADAPTER Adapter); ++void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter); ++ ++#endif //__HAL8190PCIDM_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_event.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_event.h +new file mode 100644 +index 00000000..7596531f +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_event.h +@@ -0,0 +1,28 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192C_EVENT_H_ ++#define _RTL8192C_EVENT_H_ ++ ++ ++ ++ ++#endif ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_hal.h +new file mode 100644 +index 00000000..2d54a198 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_hal.h +@@ -0,0 +1,849 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192C_HAL_H__ ++#define __RTL8192C_HAL_H__ ++ ++#include "rtl8192c_spec.h" ++#include "Hal8192CPhyReg.h" ++#include "Hal8192CPhyCfg.h" ++#include "rtl8192c_rf.h" ++#include "rtl8192c_dm.h" ++#include "rtl8192c_recv.h" ++#include "rtl8192c_xmit.h" ++#include "rtl8192c_cmd.h" ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++#include "rtl8192c_sreset.h" ++#endif ++#include "rtw_efuse.h" ++ ++#include "../hal/OUTSRC/odm_precomp.h" ++ ++ ++#ifdef CONFIG_PCI_HCI ++ ++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R ++ //#define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++ //2TODO: The following need to check!! ++ #define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin" ++ #define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin" ++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin" ++ ++ #define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt" ++ #define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt" ++ #define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt" ++ #define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt" ++ #define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt" ++ ++ #define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt" ++ #define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt" ++ #define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt" ++ #define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt" ++ #define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt" ++ ++ #define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt" ++ #define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt" ++ #define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt" ++ #define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt" ++ #define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt" ++ #define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt" ++ #define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt" ++ #define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt" ++ #define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt" ++ #define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt" ++ #define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt" ++ #define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt" ++ #define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt" ++ #define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt" ++ #define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt" ++ #define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt" ++ #define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt" ++ #define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map" ++ #define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map" ++ ++//--------------------------------------------------------------------- ++// RTL8723E From file ++//--------------------------------------------------------------------- ++ ++ // The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24. ++ #define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray ++ #define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray ++ #define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray ++ ++// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray ++ #define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array ++ #define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray ++ #define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray ++ #define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP ++ ++ #define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength ++ #define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength ++ #define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength ++ #define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength ++ #define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength ++ #define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength ++ //#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength ++ #define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength ++ #define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength ++ //#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength ++ //#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength ++ //#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength ++ #define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength ++ #define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength ++ #define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength ++ #define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength ++ //#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength ++ //#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength ++ //#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength ++ #define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength ++ #define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength ++ #define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength ++ #define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength ++ #define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength ++ //#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength ++ ++#elif defined(CONFIG_USB_HCI) ++ ++ ++ //2TODO: We should define 8192S firmware related macro settings here!! ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++ //TODO: The following need to check!! ++ #define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin" ++ #define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin" ++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin" ++ ++ //#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img" ++ //#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img" ++ //#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img" ++ ++ #define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt" ++ #define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt" ++ #define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt" ++ #define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt" ++ #define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt" ++ #define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt" ++ #define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt" ++ #define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt" ++ ++ #define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt" ++ #define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt" ++ #define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt" ++ #define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt" ++ #define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt" ++ ++ #define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8723U From file ++//--------------------------------------------------------------------- ++ ++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24. ++ #define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray ++ #define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray ++ #define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray ++ #define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray ++ ++ #define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array ++ #define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray ++ #define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray ++ #define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray ++ #define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray ++ #define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray ++ #define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray ++ #define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray ++ #define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray ++ #define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray ++ #define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard ++ #define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP ++ #define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP ++ ++ #define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength ++ #define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength ++ #define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength ++ #define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength ++ #define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength ++ #define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength ++ #define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength ++ #define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength ++ #define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength ++ #define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength ++ #define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength ++ #define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength ++ #define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength ++ #define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength ++ #define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength ++ #define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength ++ #define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength ++ #define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength ++ #define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength ++ #define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength ++ #define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength ++ #define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength ++ #define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength ++ #define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength ++ #define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength ++ #define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength ++ ++#endif ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++#define FW_8192C_SIZE 16384+32//16k ++#define FW_8192C_START_ADDRESS 0x1000 ++//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip ++#define FW_8192C_END_ADDRESS 0x1FFF ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300) ++ ++typedef enum _FIRMWARE_SOURCE{ ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE{ ++ FIRMWARE_SOURCE eFWSource; ++ u8* szFwBuffer; ++ u32 ulFwLength; ++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C; ++ ++// ++// This structure must be cared byte-ordering ++// ++// Added by tynli. 2009.12.04. ++typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u16 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u16 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++ ++}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR; ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_MIX ++}USB_RX_AGG_MODE; ++ ++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++ ++#define TX_TOTAL_PAGE_NUMBER 0xF8 ++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) ++ ++// For Normal Chip Setting ++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define NORMAL_PAGE_NUM_PUBQ 0xE7 ++#define NORMAL_PAGE_NUM_HPQ 0x0C ++#define NORMAL_PAGE_NUM_LPQ 0x02 ++#define NORMAL_PAGE_NUM_NPQ 0x02 ++ ++ ++// For Test Chip Setting ++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define TEST_PAGE_NUM_PUBQ 0x7E ++ ++ ++// For Test Chip Setting ++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 ++#define WMM_TEST_PAGE_NUM_HPQ 0x29 ++#define WMM_TEST_PAGE_NUM_LPQ 0x29 ++ ++ ++//Note: For Normal Chip Setting ,modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 ++#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C ++#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++ ++#include "HalVerDef.h" ++#include "hal_com.h" ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++typedef struct _TxPowerInfo{ ++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 TSSI_A; ++ u8 TSSI_B; ++}TxPowerInfo, *PTxPowerInfo; ++ ++#define EFUSE_REAL_CONTENT_LEN 512 ++#define EFUSE_MAP_LEN 128 ++#define EFUSE_MAX_SECTION 16 ++#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. ++#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) ++// ++// To prevent out of boundary programming case, leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 1byte|----8bytes----|1byte|--5bytes--| ++// | | Reserved(14bytes) | ++// ++#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. ++ ++ ++#define EFUSE_MAP_LEN_8723 256 ++#define EFUSE_MAX_SECTION_8723 32 ++ ++//======================================================== ++// EFUSE for BT definition ++//======================================================== ++#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 ++#define EFUSE_BT_MAP_LEN 1024 // 1k bytes ++#define EFUSE_BT_MAX_SECTION 128 // 1024/8 ++ ++#define EFUSE_PROTECT_BYTES_BANK 16 ++ ++// ++// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. ++// ++typedef enum _RT_MULTI_FUNC{ ++ RT_MULTI_FUNC_NONE = 0x00, ++ RT_MULTI_FUNC_WIFI = 0x01, ++ RT_MULTI_FUNC_BT = 0x02, ++ RT_MULTI_FUNC_GPS = 0x04, ++}RT_MULTI_FUNC,*PRT_MULTI_FUNC; ++ ++// ++// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. ++// ++typedef enum _RT_POLARITY_CTL{ ++ RT_POLARITY_LOW_ACT = 0, ++ RT_POLARITY_HIGH_ACT = 1, ++}RT_POLARITY_CTL,*PRT_POLARITY_CTL; ++ ++// For RTL8723 regulator mode. by tynli. 2011.01.14. ++typedef enum _RT_REGULATOR_MODE{ ++ RT_SWITCHING_REGULATOR = 0, ++ RT_LDO_REGULATOR = 1, ++}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE; ++ ++enum c2h_id_8192c { ++ C2H_DBG = 0, ++ C2H_TSF = 1, ++ C2H_AP_RPT_RSP = 2, ++ C2H_CCX_TX_RPT = 3, ++ C2H_BT_RSSI = 4, ++ C2H_BT_OP_MODE = 5, ++ C2H_EXT_RA_RPT = 6, ++ C2H_HW_INFO_EXCH = 10, ++ C2H_C2H_H2C_TEST = 11, ++ C2H_BT_INFO = 12, ++ C2H_BT_MP_INFO = 15, ++ MAX_C2HEVENT ++}; ++ ++#ifdef CONFIG_PCI_HCI ++struct hal_data_8192ce ++{ ++ HAL_VERSION VersionID; ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ u32 IntrMask[2]; ++ u32 IntrMaskToSet[2]; ++ ++ u32 DisabledFunctions; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ u32 TransmitConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ _lock rf_lock; ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ INTERFACE_SELECT_8192CPCIe InterfaceSel; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMDID; ++ u16 EEPROMSVID; ++ u16 EEPROMSMID; ++ u16 EEPROMChannelPlan; ++ u16 EEPROMVersion; ++ ++ u8 EEPROMChnlAreaTxPwrCCK[2][3]; ++ u8 EEPROMChnlAreaTxPwrHT40_1S[2][3]; ++ u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3]; ++ u8 EEPROMPwrLimitHT20[3]; ++ u8 EEPROMPwrLimitHT40[3]; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 EEPROMThermalMeter; ++ u8 EEPROMTSSI[2]; ++ ++ u8 EEPROMCustomerID; ++ u8 EEPROMBoardType; ++ u8 EEPROMRegulatory; ++ ++ u8 bDefaultAntenna; ++ u8 bIQKInitialized; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ BOOLEAN EepromOrEfuse; ++ u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u8 EfuseUsedPercentage; ++ EFUSE_HAL EfuseHal; ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[7][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ u32 RfRegChnlVal[2]; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 CurAntenna; ++ ++//### ODM-DUPLICATE CODE ### ++ u8 AntDivCfg; ++/* ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //SW Antenna Switch ++ s32 RSSI_sum_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_A; ++ s32 RSSI_cnt_B; ++ BOOLEAN RSSI_test; ++#endif ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ u32 CCK_Ant1_Cnt; ++ u32 CCK_Ant2_Cnt; ++ u32 OFDM_Ant1_Cnt; ++ u32 OFDM_Ant2_Cnt; ++#endif ++*/ ++//### ODM-DUPLICATE CODE ### ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++ u8 bDumpRxPkt;//for debug ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ u8 bInterruptMigration; ++ u8 bDisableTxInt; ++ u8 bGpioHwWpsPbc; ++ ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ u16 EfuseUsedBytes; ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++ ++// ++// Function disabled. ++// ++#define DF_TX_BIT BIT0 ++#define DF_RX_BIT BIT1 ++#define DF_IO_BIT BIT2 ++#define DF_IO_D3_BIT BIT3 ++ ++#define RT_DF_TYPE u32 ++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits))) ++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits)))) ++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) ++#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) ++ ++void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent); ++VOID UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++struct hal_data_8192cu ++{ ++ HAL_VERSION VersionID; ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ u8 BoardType; ++ //INTERFACE_SELECT_8192CUSB InterfaceSel; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMVersion; ++ u8 EEPROMRegulatory; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 EEPROMThermalMeter; ++ ++ u8 bIQKInitialized; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[7][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ u32 RfRegChnlVal[2]; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ u8 CurAntenna; ++ ++/*****ODM duplicate data********/ ++ u8 AntDivCfg; ++/* ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ ++ //SW Antenna Switch ++ s32 RSSI_sum_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_A; ++ s32 RSSI_cnt_B; ++ BOOLEAN RSSI_test; ++#endif ++ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ u32 CCK_Ant1_Cnt; ++ u32 CCK_Ant2_Cnt; ++ u32 OFDM_Ant1_Cnt; ++ u32 OFDM_Ant2_Cnt; ++#endif ++*/ ++ u8 bDumpRxPkt;//for debug ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // 2010/08/09 MH Add CU power down mode. ++ BOOLEAN pwrdown; ++ ++ // For 92C USB endpoint setting ++ // ++ ++ u32 UsbBulkOutSize; ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 UsbTxAggMode; ++ u8 UsbTxAggDescNum; ++#endif ++#ifdef CONFIG_USB_RX_AGGREGATION ++ u16 HwRxPageSize; // Hardware setting ++ u32 MaxUsbRxAggBlock; ++ ++ USB_RX_AGG_MODE UsbRxAggMode; ++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed ++ u8 UsbRxAggBlockTimeout; ++ u8 UsbRxAggPageCount; // 8192C DMA page count ++ u8 UsbRxAggPageTimeout; ++#endif ++ ++ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. ++ BOOLEAN UsbRxHighSpeedMode; ++ ++ // 2010/11/22 MH Add for slim combo debug mode selective. ++ // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. ++ BOOLEAN SlimComboDbg; ++ ++ u16 EfuseUsedBytes; ++ ++ BOOLEAN EepromOrEfuse; ++ u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u8 EfuseUsedPercentage; ++ EFUSE_HAL EfuseHal; ++ ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++#endif ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) ++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) ++ ++VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter); ++int FirmwareDownload92C(IN PADAPTER Adapter); ++VOID InitializeFirmwareVars92C(PADAPTER Adapter); ++u8 GetEEPROMSize8192C(PADAPTER Adapter); ++void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++ ++HAL_VERSION rtl8192c_ReadChipVersion(IN PADAPTER Adapter); ++void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); ++//void rtl8192c_free_hal_data(_adapter * padapter); ++VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo); ++void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc); ++ ++s32 c2h_id_filter_ccx_8192c(u8 id); ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_led.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_led.h +new file mode 100644 +index 00000000..df2a9998 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_led.h +@@ -0,0 +1,42 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192C_LED_H_ ++#define __RTL8192C_LED_H_ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8192cu_InitSwLeds(_adapter *padapter); ++void rtl8192cu_DeInitSwLeds(_adapter *padapter); ++#endif ++#ifdef CONFIG_PCI_HCI ++void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8192ce_InitSwLeds(_adapter *padapter); ++void rtl8192ce_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_recv.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_recv.h +new file mode 100644 +index 00000000..0a237dc1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_recv.h +@@ -0,0 +1,147 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192C_RECV_H_ ++#define _RTL8192C_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ #define NR_RECVBUFF (16) ++#elif defined(PLATFORM_OS_CE) ++ #define NR_RECVBUFF (4) ++#else ++ ++ #if defined(CONFIG_GSPI_HCI) ++ #define NR_RECVBUFF (32) ++ #elif defined(CONFIG_SDIO_HCI) ++ #define NR_RECVBUFF (8) ++ #else ++ #ifdef CONFIG_SINGLE_RECV_BUF ++ #define NR_RECVBUFF (1) ++ #else ++ #define NR_RECVBUFF (4) ++ #endif //CONFIG_SINGLE_RECV_BUF ++ #endif ++ ++ #define NR_PREALLOC_RECV_SKB (8) ++#endif ++ ++ ++#define RECV_BLK_SZ 512 ++#define RECV_BLK_CNT 16 ++#define RECV_BLK_TH RECV_BLK_CNT ++ ++#if defined(CONFIG_USB_HCI) ++ ++#ifdef PLATFORM_OS_CE ++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++#else ++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ //#define MAX_RECVBUF_SZ (32768) // 32k ++ //#define MAX_RECVBUF_SZ (16384) //16K ++ //#define MAX_RECVBUF_SZ (10240) //10K ++ #ifdef CONFIG_PLATFORM_MSTAR ++ #define MAX_RECVBUF_SZ (8192) // 8K ++ #else ++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k ++ #endif ++ //#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++ #else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++ #endif ++#endif ++ ++#elif defined(CONFIG_PCI_HCI) ++//#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++// #define MAX_RECVBUF_SZ (9100) ++//#else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++//#endif ++ ++#define RX_MPDU_QUEUE 0 ++#define RX_CMD_QUEUE 1 ++#define RX_MAX_QUEUE 2 ++ ++#elif defined(CONFIG_SDIO_HCI) ++ ++#define MAX_RECVBUF_SZ (10240) ++ ++#endif ++ ++ ++#define RECV_BULK_IN_ADDR 0x80 ++#define RECV_INT_IN_ADDR 0x81 ++ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++#define PHY_LINKQUALITY_SLID_WIN_MAX 20 ++ ++ ++struct phy_stat ++{ ++ unsigned int phydw0; ++ ++ unsigned int phydw1; ++ ++ unsigned int phydw2; ++ ++ unsigned int phydw3; ++ ++ unsigned int phydw4; ++ ++ unsigned int phydw5; ++ ++ unsigned int phydw6; ++ ++ unsigned int phydw7; ++}; ++ ++// Rx smooth factor ++#define Rx_Smooth_Factor (20) ++ ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _INTERRUPT_MSG_FORMAT_EX{ ++ unsigned int C2H_MSG0; ++ unsigned int C2H_MSG1; ++ unsigned int C2H_MSG2; ++ unsigned int C2H_MSG3; ++ unsigned int HISR; // from HISR Reg0x124, read to clear ++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear ++ unsigned int MSG_EX; ++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; ++ ++void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); ++int rtl8192cu_init_recv_priv(_adapter * padapter); ++void rtl8192cu_free_recv_priv(_adapter * padapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++int rtl8192ce_init_recv_priv(_adapter * padapter); ++void rtl8192ce_free_recv_priv(_adapter * padapter); ++#endif ++ ++void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status); ++void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_rf.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_rf.h +new file mode 100644 +index 00000000..2d6bd8cf +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_rf.h +@@ -0,0 +1,92 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192c_rf.h ( Header File) ++ * ++ * Note: Collect every HAL RF type exter API or constant. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * ++ * ++******************************************************************************/ ++#ifndef _RTL8192C_RF_H_ ++#define _RTL8192C_RF_H_ ++/* Check to see if the file has been included already. */ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++// ++// For RF 6052 Series ++// ++#define RF6052_MAX_TX_PWR 0x3F ++#define RF6052_MAX_REG 0x3F ++#define RF6052_MAX_PATH 2 ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++// ++// RF RL6052 Series API ++// ++void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate); ++void rtl8192c_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth); ++VOID rtl8192c_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel); ++VOID rtl8192c_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel); ++int PHY_RF6052_Config8192C( IN PADAPTER Adapter ); ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++ ++#endif/* End of HalRf.h */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_spec.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_spec.h +new file mode 100644 +index 00000000..ce88b022 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_spec.h +@@ -0,0 +1,1790 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192C_SPEC_H__ ++#define __RTL8192C_SPEC_H__ ++ ++#include ++ ++//============================================================ ++// 8192C Regsiter offset definition ++//============================================================ ++ ++ ++//============================================================ ++// ++//============================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYS_ISO_CTRL 0x0000 ++#define REG_SYS_FUNC_EN 0x0002 ++#define REG_APS_FSMCO 0x0004 ++#define REG_SYS_CLKR 0x0008 ++#define REG_9346CR 0x000A ++#define REG_EE_VPD 0x000C ++#define REG_AFE_MISC 0x0010 ++#define REG_SPS0_CTRL 0x0011 ++#define REG_SPS_OCP_CFG 0x0018 ++#define REG_RSV_CTRL 0x001C ++#define REG_RF_CTRL 0x001F ++#define REG_LDOA15_CTRL 0x0020 ++#define REG_LDOV12D_CTRL 0x0021 ++#define REG_LDOHCI12_CTRL 0x0022 ++#define REG_LPLDO_CTRL 0x0023 ++#define REG_AFE_XTAL_CTRL 0x0024 ++#define REG_AFE_PLL_CTRL 0x0028 ++#define REG_MAC_PHY_CTRL 0x002c ++#define REG_EFUSE_CTRL 0x0030 ++#define REG_EFUSE_TEST 0x0034 ++#define REG_PWR_DATA 0x0038 ++#define REG_CAL_TIMER 0x003C ++#define REG_ACLK_MON 0x003E ++#define REG_GPIO_MUXCFG 0x0040 ++#define REG_GPIO_IO_SEL 0x0042 ++#define REG_MAC_PINMUX_CFG 0x0043 ++#define REG_GPIO_PIN_CTRL 0x0044 ++#define REG_GPIO_INTM 0x0048 ++#define REG_LEDCFG0 0x004C ++#define REG_LEDCFG1 0x004D ++#define REG_LEDCFG2 0x004E ++#define REG_LEDCFG3 0x004F ++#define REG_LEDCFG REG_LEDCFG2 ++#define REG_FSIMR 0x0050 ++#define REG_FSISR 0x0054 ++#define REG_HSIMR 0x0058 ++#define REG_HSISR 0x005c ++#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. ++#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. ++#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. ++#define REG_MCUFWDL 0x0080 ++#define REG_HMEBOX_EXT_0 0x0088 ++#define REG_HMEBOX_EXT_1 0x008A ++#define REG_HMEBOX_EXT_2 0x008C ++#define REG_HMEBOX_EXT_3 0x008E ++#define REG_HOST_SUSP_CNT 0x00BC // Host suspend counter on FPGA platform ++#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 ++#define REG_BIST_SCAN 0x00D0 ++#define REG_BIST_RPT 0x00D4 ++#define REG_BIST_ROM_RPT 0x00D8 ++#define REG_USB_SIE_INTF 0x00E0 ++#define REG_PCIE_MIO_INTF 0x00E4 ++#define REG_PCIE_MIO_INTD 0x00E8 ++#define REG_HPON_FSM 0x00EC ++#define REG_SYS_CFG 0x00F0 ++#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_CR 0x0100 ++#define REG_PBP 0x0104 ++#define REG_TRXDMA_CTRL 0x010C ++#define REG_TRXFF_BNDY 0x0114 ++#define REG_TRXFF_STATUS 0x0118 ++#define REG_RXFF_PTR 0x011C ++#define REG_HIMR 0x0120 ++#define REG_HISR 0x0124 ++#define REG_HIMRE 0x0128 ++#define REG_HISRE 0x012C ++#define REG_CPWM 0x012F ++#define REG_FWIMR 0x0130 ++#define REG_FWISR 0x0134 ++#define REG_PKTBUF_DBG_CTRL 0x0140 ++#define REG_PKTBUF_DBG_DATA_L 0x0144 ++#define REG_PKTBUF_DBG_DATA_H 0x0148 ++ ++#define REG_TC0_CTRL 0x0150 ++#define REG_TC1_CTRL 0x0154 ++#define REG_TC2_CTRL 0x0158 ++#define REG_TC3_CTRL 0x015C ++#define REG_TC4_CTRL 0x0160 ++#define REG_TCUNIT_BASE 0x0164 ++#define REG_MBIST_START 0x0174 ++#define REG_MBIST_DONE 0x0178 ++#define REG_MBIST_FAIL 0x017C ++#define REG_C2HEVT_MSG_NORMAL 0x01A0 ++#define REG_C2HEVT_CLEAR 0x01AF ++#define REG_C2HEVT_MSG_TEST 0x01B8 ++#define REG_MCUTST_1 0x01c0 ++#define REG_FMETHR 0x01C8 ++#define REG_HMETFR 0x01CC ++#define REG_HMEBOX_0 0x01D0 ++#define REG_HMEBOX_1 0x01D4 ++#define REG_HMEBOX_2 0x01D8 ++#define REG_HMEBOX_3 0x01DC ++ ++#define REG_LLT_INIT 0x01E0 ++#define REG_BB_ACCEESS_CTRL 0x01E8 ++#define REG_BB_ACCESS_DATA 0x01EC ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RQPN 0x0200 ++#define REG_FIFOPAGE 0x0204 ++#define REG_TDECTRL 0x0208 ++#define REG_TXDMA_OFFSET_CHK 0x020C ++#define REG_TXDMA_STATUS 0x0210 ++#define REG_RQPN_NPQ 0x0214 ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RXDMA_AGG_PG_TH 0x0280 ++#define REG_RXPKT_NUM 0x0284 ++#define REG_RXDMA_STATUS 0x0288 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++#define REG_PCIE_CTRL_REG 0x0300 ++#define REG_INT_MIG 0x0304 // Interrupt Migration ++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address ++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address ++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address ++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address ++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address ++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address ++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address ++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address ++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration ++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_DBG_SEL 0x0360 // Debug Selection Register ++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM ++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM ++#define REG_UART_CTRL 0x0364 // UART Control ++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address ++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address ++ ++ ++// spec version 11 ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++#define REG_VOQ_INFORMATION 0x0400 ++#define REG_VIQ_INFORMATION 0x0404 ++#define REG_BEQ_INFORMATION 0x0408 ++#define REG_BKQ_INFORMATION 0x040C ++#define REG_MGQ_INFORMATION 0x0410 ++#define REG_HGQ_INFORMATION 0x0414 ++#define REG_BCNQ_INFORMATION 0x0418 ++ ++ ++#define REG_CPU_MGQ_INFORMATION 0x041C ++#define REG_FWHW_TXQ_CTRL 0x0420 ++#define REG_HWSEQ_CTRL 0x0423 ++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 ++#define REG_TXPKTBUF_MGQ_BDNY 0x0425 ++#define REG_LIFETIME_EN 0x0426 ++#define REG_MULTI_BCNQ_OFFSET 0x0427 ++#define REG_SPEC_SIFS 0x0428 ++#define REG_RL 0x042A ++#define REG_DARFRC 0x0430 ++#define REG_RARFRC 0x0438 ++#define REG_RRSR 0x0440 ++#define REG_ARFR0 0x0444 ++#define REG_ARFR1 0x0448 ++#define REG_ARFR2 0x044C ++#define REG_ARFR3 0x0450 ++#define REG_AGGLEN_LMT 0x0458 ++#define REG_AMPDU_MIN_SPACE 0x045C ++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D ++#define REG_FAST_EDCA_CTRL 0x0460 ++#define REG_RD_RESP_PKT_TH 0x0463 ++#define REG_INIRTS_RATE_SEL 0x0480 ++#define REG_INIDATA_RATE_SEL 0x0484 ++ ++ ++#define REG_POWER_STATUS 0x04A4 ++#define REG_POWER_STAGE1 0x04B4 ++#define REG_POWER_STAGE2 0x04B8 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 ++#define REG_STBC_SETTING 0x04C4 ++#define REG_PROT_MODE_CTRL 0x04C8 ++#define REG_MAX_AGGR_NUM 0x04CA ++#define REG_RTS_MAX_AGGR_NUM 0x04CB ++#define REG_BAR_MODE_CTRL 0x04CC ++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF ++#define REG_NQOS_SEQ 0x04DC ++#define REG_QOS_SEQ 0x04DE ++#define REG_NEED_CPU_HANDLE 0x04E0 ++#define REG_PKT_LOSE_RPT 0x04E1 ++#define REG_PTCL_ERR_STATUS 0x04E2 ++#define REG_DUMMY 0x04FC ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++#define REG_EDCA_VO_PARAM 0x0500 ++#define REG_EDCA_VI_PARAM 0x0504 ++#define REG_EDCA_BE_PARAM 0x0508 ++#define REG_EDCA_BK_PARAM 0x050C ++#define REG_BCNTCFG 0x0510 ++#define REG_PIFS 0x0512 ++#define REG_RDG_PIFS 0x0513 ++#define REG_SIFS_CCK 0x0514 ++#define REG_SIFS_OFDM 0x0516 ++#define REG_SIFS_CTX 0x0514 ++#define REG_SIFS_TRX 0x0516 ++#define REG_TSFTR_SYN_OFFSET 0x0518 ++#define REG_AGGR_BREAK_TIME 0x051A ++#define REG_SLOT 0x051B ++#define REG_TX_PTCL_CTRL 0x0520 ++#define REG_TXPAUSE 0x0522 ++#define REG_DIS_TXREQ_CLR 0x0523 ++#define REG_RD_CTRL 0x0524 ++#define REG_TBTT_PROHIBIT 0x0540 ++#define REG_RD_NAV_NXT 0x0544 ++#define REG_NAV_PROT_LEN 0x0546 ++#define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 ++#define REG_MBID_NUM 0x0552 ++#define REG_DUAL_TSF_RST 0x0553 ++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE ++#define REG_MBSSID_BCN_SPACE 0x0554 ++#define REG_DRVERLYINT 0x0558 ++#define REG_BCNDMATIM 0x0559 ++#define REG_ATIMWND 0x055A ++#define REG_BCN_MAX_ERR 0x055D ++#define REG_RXTSF_OFFSET_CCK 0x055E ++#define REG_RXTSF_OFFSET_OFDM 0x055F ++#define REG_TSFTR 0x0560 ++#define REG_TSFTR1 0x0568 ++#define REG_INIT_TSFTR 0x0564 ++#define REG_ATIMWND_1 0x0570 ++#define REG_PSTIMER 0x0580 ++#define REG_TIMER0 0x0584 ++#define REG_TIMER1 0x0588 ++#define REG_ACMHWCTRL 0x05C0 ++#define REG_ACMRSTCTRL 0x05C1 ++#define REG_ACMAVG 0x05C2 ++#define REG_VO_ADMTIME 0x05C4 ++#define REG_VI_ADMTIME 0x05C6 ++#define REG_BE_ADMTIME 0x05C8 ++#define REG_EDCA_RANDOM_GEN 0x05CC ++#define REG_SCH_TXCMD 0x05D0 ++ ++//#define REG_FW_TSF_SYNC_CNT 0x04A0 ++#define REG_FW_RESET_TSF_CNT_1 0x05FC ++#define REG_FW_RESET_TSF_CNT_0 0x05FD ++#define REG_FW_BCN_DIS_CNT 0x05FE ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++#define REG_APSD_CTRL 0x0600 ++#define REG_BWOPMODE 0x0603 ++#define REG_TCR 0x0604 ++#define REG_RCR 0x0608 ++#define REG_RX_PKT_LIMIT 0x060C ++#define REG_RX_DLK_TIME 0x060D ++#define REG_RX_DRVINFO_SZ 0x060F ++ ++#define REG_MACID 0x0610 ++#define REG_BSSID 0x0618 ++#define REG_MAR 0x0620 ++#define REG_MBIDCAMCFG 0x0628 ++ ++#define REG_USTIME_EDCA 0x0638 ++#define REG_MAC_SPEC_SIFS 0x063A ++ ++// 20100719 Joseph: Hardware register definition change. (HW datasheet v54) ++#define REG_R2T_SIFS 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK ++#define REG_T2T_SIFS 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK ++#define REG_ACKTO 0x0640 ++#define REG_CTS2TO 0x0641 ++#define REG_EIFS 0x0642 ++ ++//WMA, BA, CCX ++#define REG_NAV_CTRL 0x0650 ++#define REG_BACAMCMD 0x0654 ++#define REG_BACAMCONTENT 0x0658 ++#define REG_LBDLY 0x0660 ++#define REG_FWDLY 0x0661 ++#define REG_RXERR_RPT 0x0664 ++#define REG_WMAC_TRXPTCL_CTL 0x0668 ++ ++ ++// Security ++#define REG_CAMCMD 0x0670 ++#define REG_CAMWRITE 0x0674 ++#define REG_CAMREAD 0x0678 ++#define REG_CAMDBG 0x067C ++#define REG_SECCFG 0x0680 ++ ++// Power ++#define REG_WOW_CTRL 0x0690 ++#define REG_PSSTATUS 0x0691 ++#define REG_PS_RX_INFO 0x0692 ++#define REG_LPNAV_CTRL 0x0694 ++#define REG_WKFMCAM_CMD 0x0698 ++#define REG_WKFMCAM_RWD 0x069C ++#define REG_RXFLTMAP0 0x06A0 ++#define REG_RXFLTMAP1 0x06A2 ++#define REG_RXFLTMAP2 0x06A4 ++#define REG_BCN_PSR_RPT 0x06A8 ++#define REG_CALB32K_CTRL 0x06AC ++#define REG_PKT_MON_CTRL 0x06B4 ++#define REG_BT_COEX_TABLE 0x06C0 ++#define REG_WMAC_RESP_TXINFO 0x06D8 ++ ++#define REG_MACID1 0x0700 ++#define REG_BSSID1 0x0708 ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++// For test chip ++#define REG_TEST_USB_TXQS 0xFE48 ++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_TEST_SIE_OPTIONAL 0xFE64 ++#define REG_TEST_SIE_CHIRP_K 0xFE65 ++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B ++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 ++ ++ ++// For normal chip ++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_NORMAL_SIE_OPTIONAL 0xFE64 ++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 ++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B ++#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C ++#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. ++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF ++ ++ ++//----------------------------------------------------- ++// ++// Redifine 8192C register definition for compatibility ++// ++//----------------------------------------------------- ++ ++// TODO: use these definition when using REG_xxx naming rule. ++// NOTE: DO NOT Remove these definition. Use later. ++ ++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control. ++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable. ++#define SYS_CLK REG_SYS_CLKR ++#define CR9346 REG_9346CR // 93C46/93C56 Command Register. ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. ++#define MSR (REG_CR + 2) // Media Status register ++#define ISR REG_HISR ++#define TSFR REG_TSFTR // Timing Sync Function Timer Register. ++ ++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 ++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 ++ ++#define PBP REG_PBP ++ ++// Redifine MACID register, to compatible prior ICs. ++#define IDR0 MACIDR0 ++#define IDR4 MACIDR4 ++ ++ ++// ++// 9. Security Control Registers (Offset: ) ++// ++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd ++#define WCAMI REG_CAMWRITE // Software write CAM input content ++#define RCAMO REG_CAMREAD // Software read/write CAM config ++#define CAMDBG REG_CAMDBG ++#define SECR REG_SECCFG //Security Configuration Register ++ ++// Unused register ++#define UnusedRegister 0x1BF ++#define DCAM UnusedRegister ++#define PSR UnusedRegister ++#define BBAddr UnusedRegister ++#define PhyDataR UnusedRegister ++ ++#define InvalidBBRFValue 0x12345678 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C Cmd9346CR bits (Offset 0xA, 16bit) ++//---------------------------------------------------------------------------- ++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 ++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 ++#define Cmd9346CR_9356SEL BIT4 ++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) ++#define AutoLoadEFUSE CmdEEPROM_En ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++//---------------------------------------------------------------------------- ++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++/* ++Network Type ++00: No link ++01: Link in ad hoc network ++10: Link in infrastructure network ++11: AP mode ++Default: 00b. ++*/ ++#define MSR_NOLINK 0x00 ++#define MSR_ADHOC 0x01 ++#define MSR_INFRA 0x02 ++#define MSR_AP 0x03 ++ ++// ++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) ++// ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x181, 24bits) ++//---------------------------------------------------------------------------- ++#define RRSR_RSC_OFFSET 21 ++#define RRSR_SHORT_OFFSET 23 ++#define RRSR_RSC_BW_40M 0x600000 ++#define RRSR_RSC_UPSUBCHNL 0x400000 ++#define RRSR_RSC_LOWSUBCHNL 0x200000 ++#define RRSR_SHORT 0x800000 ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++#define BRSR_AckShortPmb BIT23 ++// CCK ACK: use Short Preamble or not ++ ++//---------------------------------------------------------------------------- ++// 8192C BW_OPMODE bits (Offset 0x203, 8bit) ++//---------------------------------------------------------------------------- ++#define BW_OPMODE_20MHZ BIT2 ++#define BW_OPMODE_5G BIT1 ++#define BW_OPMODE_11J BIT0 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C CAM Config Setting (offset 0x250, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_CONTENT_COUNT 8 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++ ++#define TOTAL_CAM_ENTRY 32 ++#define HALF_CAM_ENTRY 16 ++ ++#define CAM_CONFIG_USEDK _TRUE ++#define CAM_CONFIG_NO_USEDK _FALSE ++ ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++ ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++ ++// ++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) ++// ++//---------------------------------------------------------------------------- ++// 8190 IMR/ISR bits (offset 0xfd, 8bits) ++//---------------------------------------------------------------------------- ++#define IMR8190_DISABLED 0x0 ++// IMR DW0 Bit 0-31 ++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 ++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 ++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 ++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 ++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 ++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 ++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 ++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 ++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 ++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 ++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 ++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow ++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt ++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 ++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow ++#define IMR_RDU BIT11 // Receive Descriptor Unavailable ++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt ++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup ++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt ++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup ++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt ++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt ++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt ++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt ++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt ++#define IMR_ROK BIT0 // Receive DMA OK Interrupt ++ ++#define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW) ++#define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK|IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK|IMR_BDOK) ++ ++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) ++#define IMR_BcnInt_E BIT12 ++#define IMR_TXERR BIT11 ++#define IMR_RXERR BIT10 ++#define IMR_C2HCMD BIT9 ++#define IMR_CPWM BIT8 ++//RSVD [2-7] ++#define IMR_OCPINT BIT1 ++#define IMR_WLANOFF BIT0 ++ ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C EFUSE ++//---------------------------------------------------------------------------- ++#define HWSET_MAX_SIZE 128 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C EEPROM/EFUSE share register definition. ++//---------------------------------------------------------------------------- ++ ++// ++// Default Value for EEPROM or EFUSE!!! ++// ++#define EEPROM_Default_TSSI 0x0 ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_CrystalCap 0x5 ++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_Default_HT2T_TxPwr 0x10 ++ ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_ThermalMeter 0x12 ++ ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#define EEPROM_Default_TxPowerLevel 0x22 ++#define EEPROM_Default_HT40_2SDiff 0x0 ++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_HT40_PwrMaxOffset 0 ++#define EEPROM_Default_HT20_PwrMaxOffset 0 ++ ++// For debug ++#define EEPROM_Default_PID 0x1234 ++#define EEPROM_Default_VID 0x5678 ++#define EEPROM_Default_CustomerID 0xAB ++#define EEPROM_Default_SubCustomerID 0xCD ++#define EEPROM_Default_Version 0 ++ ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_NCC 0xB ++#define EEPROM_USB_OPTIONAL1 0xE ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_TOSHIBA 0x4 ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#define EEPROM_CID_QMI 0x0D ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define RTL_EEPROM_ID 0x8129 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER) ++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) ++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS) ++ ++// ++// Interface type. ++// ++typedef enum _INTERFACE_SELECT_8192CPCIe{ ++ INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard ++ INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard ++ INTF_SEL2_PCIe = 2, // PCIe Card ++} INTERFACE_SELECT_8192CPCIe, *PINTERFACE_SELECT_8192CPCIe; ++ ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_TESTR 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0x0A // SE Vendor ID.A-B ++#define EEPROM_DID 0x0C // SE Device ID. C-D ++#define EEPROM_SVID 0x0E // SE Vendor ID.E-F ++#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11 ++ ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++ ++//---------------------------------------------------------------- ++// Ziv - Let PCIe and USB use the same define. Modify address mapping later. ++#define EEPROM_CCK_TX_PWR_INX 0x5A ++#define EEPROM_HT40_1S_TX_PWR_INX 0x60 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 ++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C ++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F ++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 ++ ++#define EEPROM_CHANNEL_PLAN 0x75 ++#define EEPROM_TSSI_A 0x76 ++#define EEPROM_TSSI_B 0x77 ++#define EEPROM_THERMAL_METER 0x78 ++#define EEPROM_RF_OPT1 0x79 ++#define EEPROM_RF_OPT2 0x7A ++#define EEPROM_RF_OPT3 0x7B ++#define EEPROM_RF_OPT4 0x7C ++#define EEPROM_VERSION 0x7E ++#define EEPROM_CUSTOMER_ID 0x7F ++ ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++ ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++//should be renamed and moved to another file ++typedef enum _BOARD_TYPE_8192CUSB{ ++ BOARD_USB_DONGLE = 0, // USB dongle ++ BOARD_USB_High_PA = 1, // USB dongle with high power PA ++ BOARD_MINICARD = 2, // Minicard ++ BOARD_USB_SOLO = 3, // USB solo-Slim module ++ BOARD_USB_COMBO = 4, // USB Combo-Slim module ++} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB; ++ ++#define SUPPORT_HW_RADIO_DETECT(pHalData) (pHalData->BoardType == BOARD_MINICARD||\ ++ pHalData->BoardType == BOARD_USB_SOLO||\ ++ pHalData->BoardType == BOARD_USB_COMBO) ++ ++//--------------------------------------------------------------- ++// EEPROM address for Test chip ++//--------------------------------------------------------------- ++#define EEPROM_TEST_USB_OPT 0x0E ++#define EEPROM_TEST_CHIRP_K 0x0F ++#define EEPROM_TEST_EP_SETTING 0x0E ++#define EEPROM_TEST_USB_PHY 0x10 ++ ++ ++//--------------------------------------------------------------- ++// EEPROM address for Normal chip ++//--------------------------------------------------------------- ++#define EEPROM_NORMAL_USB_OPT 0x0E ++#define EEPROM_NORMAL_CHIRP_K 0x0E // Changed ++#define EEPROM_NORMAL_EP_SETTING 0x0F // Changed ++#define EEPROM_NORMAL_USB_PHY 0x12 // Changed ++ ++ ++// Test chip and normal chip common define ++//--------------------------------------------------------------- ++// EEPROM address for both ++//--------------------------------------------------------------- ++#define EEPROM_ID0 0x00 ++#define EEPROM_ID1 0x01 ++#define EEPROM_RTK_RSV1 0x02 ++#define EEPROM_RTK_RSV2 0x03 ++#define EEPROM_RTK_RSV3 0x04 ++#define EEPROM_RTK_RSV4 0x05 ++#define EEPROM_RTK_RSV5 0x06 ++#define EEPROM_DBG_SEL 0x07 ++#define EEPROM_RTK_RSV6 0x08 ++#define EEPROM_VID 0x0A ++#define EEPROM_PID 0x0C ++ ++#define EEPROM_MAC_ADDR 0x16 ++#define EEPROM_STRING 0x1C ++#define EEPROM_SUBCUSTOMER_ID 0x59 ++#define EEPROM_CCK_TX_PWR_INX 0x5A ++#define EEPROM_HT40_1S_TX_PWR_INX 0x60 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 ++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C ++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F ++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 ++ ++#define EEPROM_CHANNEL_PLAN 0x75 ++#define EEPROM_TSSI_A 0x76 ++#define EEPROM_TSSI_B 0x77 ++#define EEPROM_THERMAL_METER 0x78 ++#define EEPROM_RF_OPT1 0x79 ++#define EEPROM_RF_OPT2 0x7A ++#define EEPROM_RF_OPT3 0x7B ++#define EEPROM_RF_OPT4 0x7C ++#define EEPROM_VERSION 0x7E ++#define EEPROM_CUSTOMER_ID 0x7F ++ ++#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU ++#define EEPROM_TxPwIndex 0x5C //0x5C-0x76, Tx Power index. ++#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM. ++ ++#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power ++ ++// 2009/02/09 Cosa Add for SD3 requirement ++#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference ++#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference ++ ++#define EEPROM_TxPWRGroup 0x73// Power diff for channel group ++#define EEPROM_Regulatory 0x79// Check if power safety is need ++ ++#define EEPROM_BLUETOOTH_COEXIST 0x7E // 92cu, 0x7E[4] ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++#define BOARD_TYPE_NORMAL_MASK 0xE0 ++#define BOARD_TYPE_TEST_MASK 0x0F ++#define EEPROM_EASY_REPLACEMENT 0x50//BIT0 1 for build-in module, 0 for external dongle ++//------------------------------------------------------------- ++// EEPROM content definitions ++//------------------------------------------------------------- ++#define OS_LINK_SPEED BIT(5) ++ ++#define BOARD_TYPE_MASK 0xF ++ ++#define BT_COEXISTENCE BIT(4) ++#define BT_CO_SHIFT 4 ++ ++#define EP_NUMBER_MASK 0x30 //bit 4:5 0Eh ++#define EP_NUMBER_SHIFT 4 ++ ++ ++#define USB_PHY_PARA_SIZE 5 ++ ++ ++//------------------------------------------------------------- ++// EEPROM default value definitions ++//------------------------------------------------------------- ++// Use 0xABCD instead of 0x8192 for debug ++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00 ++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01 ++ ++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03 ++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04 ++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08 ++ ++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A ++#define EEPROM_DEF_VID_1 0x0B ++ ++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C ++#define EEPROM_DEF_PID_1 0x81 ++ ++ ++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E ++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E ++ ++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F ++ ++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10 ++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11 ++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12 ++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13 ++ ++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78 ++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79 ++ ++ ++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A ++ ++#define RF_OPTION1 0x79// Check if power safety spec is need ++#define RF_OPTION2 0x7A ++#define RF_OPTION3 0x7B ++#define RF_OPTION4 0x7C ++ ++ ++#define EEPROM_USB_SN BIT(0) ++#define EEPROM_USB_REMOTE_WAKEUP BIT(1) ++#define EEPROM_USB_DEVICE_PWR BIT(2) ++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) ++ ++#if 0 ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++#define EEPROM_CID_DEFAULT 0x0 ++ ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#endif ++ ++#endif ++ ++ ++/*=================================================================== ++===================================================================== ++Here the register defines are for 92C. When the define is as same with 92C, ++we will use the 92C's define for the consistency ++So the following defines for 92C is not entire!!!!!! ++===================================================================== ++=====================================================================*/ ++/* ++Based on Datasheet V33---090401 ++Register Summary ++Current IOREG MAP ++0x0000h ~ 0x00FFh System Configuration (256 Bytes) ++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) ++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) ++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) ++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) ++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) ++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) ++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) ++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) ++*/ ++ ++//---------------------------------------------------------------------------- ++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) ++//---------------------------------------------------------------------------- ++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload ++#define RCR_APP_MIC BIT30 // ++#define RCR_APP_PHYSTS BIT28// ++#define RCR_APP_ICV BIT29 // ++#define RCR_APP_PHYST_RXFF BIT28 // ++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN ++#define RCR_ENMBID BIT24 //Enable Multiple BssId. ++#define RCR_LSIGEN BIT23 ++#define RCR_MFBEN BIT22 ++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 ++#define RCR_AMF BIT13 //Accept management type frame ++#define RCR_ACF BIT12 //Accept control type frame ++#define RCR_ADF BIT11 //Accept data type frame ++#define RCR_AICV BIT9 //Accept ICV error packet ++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet ++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) ++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) ++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet ++#define RCR_APWRMGT BIT5 //Accept power management packet ++#define RCR_ADD3 BIT4 //Accept address 3 match packet ++#define RCR_AB BIT3 //Accept broadcast packet ++#define RCR_AM BIT2 //Accept multicast packet ++#define RCR_APM BIT1 //Accept physical match packet ++#define RCR_AAP BIT0 //Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ ++ ++ ++//============================================================================ ++// 8192c USB specific Regsiter Offset and Content definition, ++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver ++//============================================================================ ++//#define APS_FSMCO 0x0004 same with 92Ce ++#define RSV_CTRL 0x001C ++#define RD_CTRL 0x0524 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++#define REG_USB_VID 0xFE60 ++#define REG_USB_PID 0xFE62 ++#define REG_USB_OPTIONAL 0xFE64 ++#define REG_USB_CHIRP_K 0xFE65 ++#define REG_USB_PHY 0xFE66 ++#define REG_USB_MAC_ADDR 0xFE70 ++ ++#define REG_USB_HRPWM 0xFE58 ++#define REG_USB_HCPWM 0xFE57 ++ ++#define InvalidBBRFValue 0x12345678 ++ ++//============================================================================ ++// 8192C Regsiter Bit and Content definition ++//============================================================================ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SPS0_CTRL ++#define SW18_FPWM BIT(3) ++ ++ ++//2 SYS_ISO_CTRL ++#define ISO_MD2PP BIT(0) ++#define ISO_UA2USB BIT(1) ++#define ISO_UD2CORE BIT(2) ++#define ISO_PA2PCIE BIT(3) ++#define ISO_PD2CORE BIT(4) ++#define ISO_IP2MAC BIT(5) ++#define ISO_DIOP BIT(6) ++#define ISO_DIOE BIT(7) ++#define ISO_EB2CORE BIT(8) ++#define ISO_DIOR BIT(9) ++ ++#define PWC_EV25V BIT(14) ++#define PWC_EV12V BIT(15) ++ ++ ++//2 SYS_FUNC_EN ++#define FEN_BBRSTB BIT(0) ++#define FEN_BB_GLB_RSTn BIT(1) ++#define FEN_USBA BIT(2) ++#define FEN_UPLL BIT(3) ++#define FEN_USBD BIT(4) ++#define FEN_DIO_PCIE BIT(5) ++#define FEN_PCIEA BIT(6) ++#define FEN_PPLL BIT(7) ++#define FEN_PCIED BIT(8) ++#define FEN_DIOE BIT(9) ++#define FEN_CPUEN BIT(10) ++#define FEN_DCORE BIT(11) ++#define FEN_ELDR BIT(12) ++#define FEN_DIO_RF BIT(13) ++#define FEN_HWPDN BIT(14) ++#define FEN_MREGEN BIT(15) ++ ++//2 APS_FSMCO ++#define PFM_LDALL BIT(0) ++#define PFM_ALDN BIT(1) ++#define PFM_LDKP BIT(2) ++#define PFM_WOWL BIT(3) ++#define EnPDN BIT(4) ++#define PDN_PL BIT(5) ++#define APFM_ONMAC BIT(8) ++#define APFM_OFF BIT(9) ++#define APFM_RSM BIT(10) ++#define AFSM_HSUS BIT(11) ++#define AFSM_PCIE BIT(12) ++#define APDM_MAC BIT(13) ++#define APDM_HOST BIT(14) ++#define APDM_HPDN BIT(15) ++#define RDY_MACON BIT(16) ++#define SUS_HOST BIT(17) ++#define ROP_ALD BIT(20) ++#define ROP_PWR BIT(21) ++#define ROP_SPS BIT(22) ++#define SOP_MRST BIT(25) ++#define SOP_FUSE BIT(26) ++#define SOP_ABG BIT(27) ++#define SOP_AMB BIT(28) ++#define SOP_RCK BIT(29) ++#define SOP_A8M BIT(30) ++#define XOP_BTCK BIT(31) ++ ++//2 SYS_CLKR ++#define ANAD16V_EN BIT(0) ++#define ANA8M BIT(1) ++#define MACSLP BIT(4) ++#define LOADER_CLK_EN BIT(5) ++#define _80M_SSC_DIS BIT(7) ++#define _80M_SSC_EN_HO BIT(8) ++#define PHY_SSC_RSTB BIT(9) ++#define SEC_CLK_EN BIT(10) ++#define MAC_CLK_EN BIT(11) ++#define SYS_CLK_EN BIT(12) ++#define RING_CLK_EN BIT(13) ++ ++ ++//2 9346CR ++ ++ ++#define EEDO BIT(0) ++#define EEDI BIT(1) ++#define EESK BIT(2) ++#define EECS BIT(3) ++//#define EERPROMSEL BIT(4) ++//#define EEPROM_EN BIT(5) ++#define BOOT_FROM_EEPROM BIT(4) ++#define EEPROM_EN BIT(5) ++#define EEM0 BIT(6) ++#define EEM1 BIT(7) ++ ++ ++//2 AFE_MISC ++#define AFE_BGEN BIT(0) ++#define AFE_MBEN BIT(1) ++#define MAC_ID_EN BIT(7) ++ ++ ++//2 SPS0_CTRL ++ ++ ++//2 SPS_OCP_CFG ++ ++ ++//2 RSV_CTRL ++#define WLOCK_ALL BIT(0) ++#define WLOCK_00 BIT(1) ++#define WLOCK_04 BIT(2) ++#define WLOCK_08 BIT(3) ++#define WLOCK_40 BIT(4) ++#define R_DIS_PRST_0 BIT(5) ++#define R_DIS_PRST_1 BIT(6) ++#define LOCK_ALL_EN BIT(7) ++ ++//2 RF_CTRL ++#define RF_EN BIT(0) ++#define RF_RSTB BIT(1) ++#define RF_SDMRSTB BIT(2) ++ ++ ++ ++//2 LDOA15_CTRL ++#define LDA15_EN BIT(0) ++#define LDA15_STBY BIT(1) ++#define LDA15_OBUF BIT(2) ++#define LDA15_REG_VOS BIT(3) ++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) ++ ++ ++ ++//2 LDOV12D_CTRL ++#define LDV12_EN BIT(0) ++#define LDV12_SDBY BIT(1) ++#define LPLDO_HSM BIT(2) ++#define LPLDO_LSM_DIS BIT(3) ++#define _LDV12_VADJ(x) (((x) & 0xF) << 4) ++ ++ ++//2 AFE_XTAL_CTRL ++#define XTAL_EN BIT(0) ++#define XTAL_BSEL BIT(1) ++#define _XTAL_BOSC(x) (((x) & 0x3) << 2) ++#define _XTAL_CADJ(x) (((x) & 0xF) << 4) ++#define XTAL_GATE_USB BIT(8) ++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) ++#define XTAL_GATE_AFE BIT(11) ++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) ++#define XTAL_RF_GATE BIT(14) ++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) ++#define XTAL_GATE_DIG BIT(17) ++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) ++#define XTAL_BT_GATE BIT(20) ++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) ++#define _XTAL_GPIO(x) (((x) & 0x7) << 23) ++ ++ ++#define CKDLY_AFE BIT(26) ++#define CKDLY_USB BIT(27) ++#define CKDLY_DIG BIT(28) ++#define CKDLY_BT BIT(29) ++ ++ ++//2 AFE_PLL_CTRL ++#define APLL_EN BIT(0) ++#define APLL_320_EN BIT(1) ++#define APLL_FREF_SEL BIT(2) ++#define APLL_EDGE_SEL BIT(3) ++#define APLL_WDOGB BIT(4) ++#define APLL_LPFEN BIT(5) ++ ++#define APLL_REF_CLK_13MHZ 0x1 ++#define APLL_REF_CLK_19_2MHZ 0x2 ++#define APLL_REF_CLK_20MHZ 0x3 ++#define APLL_REF_CLK_25MHZ 0x4 ++#define APLL_REF_CLK_26MHZ 0x5 ++#define APLL_REF_CLK_38_4MHZ 0x6 ++#define APLL_REF_CLK_40MHZ 0x7 ++ ++#define APLL_320EN BIT(14) ++#define APLL_80EN BIT(15) ++#define APLL_1MEN BIT(24) ++ ++ ++//2 EFUSE_CTRL ++#define ALD_EN BIT(18) ++#define EF_PD BIT(19) ++#define EF_FLAG BIT(31) ++ ++//2 EFUSE_TEST (For RTL8723 partially) ++#define EF_TRPT BIT(7) ++#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 ++#define LDOE25_EN BIT(31) ++#define EFUSE_SEL(x) (((x) & 0x3) << 8) ++#define EFUSE_SEL_MASK 0x300 ++#define EFUSE_WIFI_SEL_0 0x0 ++#define EFUSE_BT_SEL_0 0x1 ++#define EFUSE_BT_SEL_1 0x2 ++#define EFUSE_BT_SEL_2 0x3 ++ ++#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. ++#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. ++ ++//2 PWR_DATA ++ ++//2 CAL_TIMER ++ ++//2 ACLK_MON ++#define RSM_EN BIT(0) ++#define Timer_EN BIT(4) ++ ++ ++//2 GPIO_MUXCFG ++#define TRSW0EN BIT(2) ++#define TRSW1EN BIT(3) ++#define EROM_EN BIT(4) ++#define EnBT BIT(5) ++#define EnUart BIT(8) ++#define Uart_910 BIT(9) ++#define EnPMAC BIT(10) ++#define SIC_SWRST BIT(11) ++#define EnSIC BIT(12) ++#define SIC_23 BIT(13) ++#define EnHDP BIT(14) ++#define SIC_LBK BIT(15) ++ ++//2 GPIO_PIN_CTRL ++ ++// GPIO BIT ++#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) ++ ++//2 GPIO_INTM ++ ++//2 LEDCFG ++#define LED0PL BIT(4) ++#define LED0DIS BIT(7) ++#define LED1DIS BIT(15) ++#define LED1PL BIT(12) ++ ++#define SECCAM_CLR BIT(30) ++ ++ ++//2 FSIMR ++ ++//2 FSISR ++ ++ ++//2 8051FWDL ++//2 MCUFWDL ++#define MCUFWDL_EN BIT(0) ++#define MCUFWDL_RDY BIT(1) ++#define FWDL_ChkSum_rpt BIT(2) ++#define MACINI_RDY BIT(3) ++#define BBINI_RDY BIT(4) ++#define RFINI_RDY BIT(5) ++#define WINTINI_RDY BIT(6) ++#define CPRST BIT(23) ++ ++//2REG_HPON_FSM ++#define BOND92CE_1T2R_CFG BIT(22) ++ ++ ++//2 REG_SYS_CFG ++#define XCLK_VLD BIT(0) ++#define ACLK_VLD BIT(1) ++#define UCLK_VLD BIT(2) ++#define PCLK_VLD BIT(3) ++#define PCIRSTB BIT(4) ++#define V15_VLD BIT(5) ++#define TRP_B15V_EN BIT(7) ++#define SIC_IDLE BIT(8) ++#define BD_MAC2 BIT(9) ++#define BD_MAC1 BIT(10) ++#define IC_MACPHY_MODE BIT(11) ++#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ++#define BT_FUNC BIT(16) ++#define VENDOR_ID BIT(19) ++#define PAD_HWPD_IDN BIT(22) ++#define TRP_VAUX_EN BIT(23) ++#define TRP_BT_EN BIT(24) ++#define BD_PKG_SEL BIT(25) ++#define BD_HCI_SEL BIT(26) ++#define TYPE_ID BIT(27) ++ ++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 ++#define CHIP_VER_RTL_SHIFT 12 ++ ++//2REG_GPIO_OUTSTS (For RTL8723 only) ++#define EFS_HCI_SEL (BIT(0)|BIT(1)) ++#define PAD_HCI_SEL (BIT(2)|BIT(3)) ++#define HCI_SEL (BIT(4)|BIT(5)) ++#define PKG_SEL_HCI BIT(6) ++#define FEN_GPS BIT(7) ++#define FEN_BT BIT(8) ++#define FEN_WL BIT(9) ++#define FEN_PCI BIT(10) ++#define FEN_USB BIT(11) ++#define BTRF_HWPDN_N BIT(12) ++#define WLRF_HWPDN_N BIT(13) ++#define PDN_BT_N BIT(14) ++#define PDN_GPS_N BIT(15) ++#define BT_CTL_HWPDN BIT(16) ++#define GPS_CTL_HWPDN BIT(17) ++#define PPHY_SUSB BIT(20) ++#define UPHY_SUSB BIT(21) ++#define PCI_SUSEN BIT(22) ++#define USB_SUSEN BIT(23) ++#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++ ++//2 Function Enable Registers ++//2 CR ++ ++#define REG_LBMODE (REG_CR + 3) ++ ++ ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++ ++// Network type ++#define _NETTYPE(x) (((x) & 0x3) << 16) ++#define MASK_NETTYPE 0x30000 ++#define NT_NO_LINK 0x0 ++#define NT_LINK_AD_HOC 0x1 ++#define NT_LINK_AP 0x2 ++#define NT_AS_AP 0x3 ++ ++#define _LBMODE(x) (((x) & 0xF) << 24) ++#define MASK_LBMODE 0xF000000 ++#define LOOPBACK_NORMAL 0x0 ++#define LOOPBACK_IMMEDIATELY 0xB ++#define LOOPBACK_MAC_DELAY 0x3 ++#define LOOPBACK_PHY 0x1 ++#define LOOPBACK_DMA 0x7 ++ ++ ++//2 PBP - Page Size Register ++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) ++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) ++#define _PSRX_MASK 0xF ++#define _PSTX_MASK 0xF0 ++#define _PSRX(x) (x) ++#define _PSTX(x) ((x) << 4) ++ ++#define PBP_64 0x0 ++#define PBP_128 0x1 ++#define PBP_256 0x2 ++#define PBP_512 0x3 ++#define PBP_1024 0x4 ++ ++ ++//2 TX/RXDMA ++#define RXDMA_ARBBW_EN BIT(0) ++#define RXSHFT_EN BIT(1) ++#define RXDMA_AGG_EN BIT(2) ++#define QS_VO_QUEUE BIT(8) ++#define QS_VI_QUEUE BIT(9) ++#define QS_BE_QUEUE BIT(10) ++#define QS_BK_QUEUE BIT(11) ++#define QS_MANAGER_QUEUE BIT(12) ++#define QS_HIGH_QUEUE BIT(13) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++// For normal driver, 0x10C ++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) ++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) ++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) ++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) ++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++ ++ ++//2 TRXFF_BNDY ++ ++ ++//2 LLT_INIT ++#define _LLT_NO_ACTIVE 0x0 ++#define _LLT_WRITE_ACCESS 0x1 ++#define _LLT_READ_ACCESS 0x2 ++ ++#define _LLT_INIT_DATA(x) ((x) & 0xFF) ++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) ++#define _LLT_OP(x) (((x) & 0x3) << 30) ++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) ++ ++ ++//2 BB_ACCESS_CTRL ++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) ++#define BB_WRITE_EN BIT(30) ++#define BB_READ_EN BIT(31) ++//#define BB_ADDR_MASK 0xFFF ++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK) ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++//2 RQPN ++#define _HPQ(x) ((x) & 0xFF) ++#define _LPQ(x) (((x) & 0xFF) << 8) ++#define _PUBQ(x) (((x) & 0xFF) << 16) ++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register ++ ++ ++#define HPQ_PUBLIC_DIS BIT(24) ++#define LPQ_PUBLIC_DIS BIT(25) ++#define LD_RQPN BIT(31) ++ ++ ++//2 TDECTRL ++#define BCN_VALID BIT(16) ++#define BCN_HEAD(x) (((x) & 0xFF) << 8) ++#define BCN_HEAD_MASK 0xFF00 ++ ++//2 TDECTL ++#define BLK_DESC_NUM_SHIFT 4 ++#define BLK_DESC_NUM_MASK 0xF ++ ++ ++//2 TXDMA_OFFSET_CHK ++#define DROP_DATA_EN BIT(9) ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//2 FWHW_TXQ_CTRL ++#define EN_AMPDU_RTY_NEW BIT(7) ++ ++//2 INIRTSMCS_SEL ++#define _INIRTSMCS_SEL(x) ((x) & 0x3F) ++ ++ ++//2 SPEC SIFS ++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) ++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) ++ ++ ++//2 RRSR ++ ++#define RATE_REG_BITMAP_ALL 0xFFFFF ++ ++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) ++ ++#define _RRSR_RSC(x) (((x) & 0x3) << 21) ++#define RRSR_RSC_RESERVED 0x0 ++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 ++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 ++#define RRSR_RSC_DUPLICATE_MODE 0x3 ++ ++ ++//2 ARFR ++#define USE_SHORT_G1 BIT(20) ++ ++//2 AGGLEN_LMT_L ++#define _AGGLMT_MCS0(x) ((x) & 0xF) ++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) ++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) ++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) ++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) ++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) ++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) ++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) ++ ++ ++//2 RL ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ ++ ++//2 DARFRC ++#define _DARF_RC1(x) ((x) & 0x1F) ++#define _DARF_RC2(x) (((x) & 0x1F) << 8) ++#define _DARF_RC3(x) (((x) & 0x1F) << 16) ++#define _DARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (DARFRC + 4) ++#define _DARF_RC5(x) ((x) & 0x1F) ++#define _DARF_RC6(x) (((x) & 0x1F) << 8) ++#define _DARF_RC7(x) (((x) & 0x1F) << 16) ++#define _DARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++//2 RARFRC ++#define _RARF_RC1(x) ((x) & 0x1F) ++#define _RARF_RC2(x) (((x) & 0x1F) << 8) ++#define _RARF_RC3(x) (((x) & 0x1F) << 16) ++#define _RARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (RARFRC + 4) ++#define _RARF_RC5(x) ((x) & 0x1F) ++#define _RARF_RC6(x) (((x) & 0x1F) << 8) ++#define _RARF_RC7(x) (((x) & 0x1F) << 16) ++#define _RARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++ ++ ++//2 EDCA setting ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ ++ ++//2 EDCA_VO_PARAM ++#define _AIFS(x) (x) ++#define _ECW_MAX_MIN(x) ((x) << 8) ++#define _TXOP_LIMIT(x) ((x) << 16) ++ ++ ++#define _BCNIFS(x) ((x) & 0xFF) ++#define _BCNECW(x) (((x) & 0xF))<< 8) ++ ++ ++#define _LRL(x) ((x) & 0x3F) ++#define _SRL(x) (((x) & 0x3F) << 8) ++ ++ ++//2 SIFS_CCK ++#define _SIFS_CCK_CTX(x) ((x) & 0xFF) ++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 SIFS_OFDM ++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) ++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 TBTT PROHIBIT ++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) ++ ++ ++//2 REG_RD_CTRL ++#define DIS_EDCA_CNT_DWN BIT(11) ++ ++ ++//2 BCN_CTRL ++#define EN_MBSSID BIT(1) ++#define EN_TXBCN_RPT BIT(2) ++#define EN_BCN_FUNCTION BIT(3) ++#define DIS_TSF_UPDATE BIT(3) ++ ++// The same function but different bit field. ++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) ++#define DIS_TSF_UDT0_TEST_CHIP BIT(5) ++ ++//2 ACMHWCTRL ++#define AcmHw_HwEn BIT(0) ++#define AcmHw_BeqEn BIT(1) ++#define AcmHw_ViqEn BIT(2) ++#define AcmHw_VoqEn BIT(3) ++#define AcmHw_BeqStatus BIT(4) ++#define AcmHw_ViqStatus BIT(5) ++#define AcmHw_VoqStatus BIT(6) ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++ ++//2 APSD_CTRL ++#define APSDOFF BIT(6) ++#define APSDOFF_STATUS BIT(7) ++ ++ ++//2 BWOPMODE ++#define BW_20MHZ BIT(2) ++//#define BW_OPMODE_20MHZ BIT(2) // For compability ++ ++ ++#define RATE_BITMAP_ALL 0xFFFFF ++ ++// Only use CCK 1M rate for ACK ++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 ++ ++//2 TCR ++#define TSFRST BIT(0) ++#define DIS_GCLK BIT(1) ++#define PAD_SEL BIT(2) ++#define PWR_ST BIT(6) ++#define PWRBIT_OW_EN BIT(7) ++#define ACRC BIT(8) ++#define CFENDFORM BIT(9) ++#define ICV BIT(10) ++ ++ ++ ++//2 RCR ++#define AAP BIT(0) ++#define APM BIT(1) ++#define AM BIT(2) ++#define AB BIT(3) ++#define ADD3 BIT(4) ++#define APWRMGT BIT(5) ++#define CBSSID BIT(6) ++#define CBSSID_BCN BIT(7) ++#define ACRC32 BIT(8) ++#define AICV BIT(9) ++#define ADF BIT(11) ++#define ACF BIT(12) ++#define AMF BIT(13) ++#define HTC_LOC_CTRL BIT(14) ++#define UC_DATA_EN BIT(16) ++#define BM_DATA_EN BIT(17) ++#define MFBEN BIT(22) ++#define LSIGEN BIT(23) ++#define EnMBID BIT(24) ++#define APP_BASSN BIT(27) ++#define APP_PHYSTS BIT(28) ++#define APP_ICV BIT(29) ++#define APP_MIC BIT(30) ++#define APP_FCS BIT(31) ++ ++//2 RX_PKT_LIMIT ++ ++//2 RX_DLK_TIME ++ ++//2 MBIDCAMCFG ++ ++ ++ ++//2 AMPDU_MIN_SPACE ++#define _MIN_SPACE(x) ((x) & 0x7) ++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) ++ ++ ++//2 RXERR_RPT ++#define RXERR_TYPE_OFDM_PPDU 0 ++#define RXERR_TYPE_OFDM_FALSE_ALARM 1 ++#define RXERR_TYPE_OFDM_MPDU_OK 2 ++#define RXERR_TYPE_OFDM_MPDU_FAIL 3 ++#define RXERR_TYPE_CCK_PPDU 4 ++#define RXERR_TYPE_CCK_FALSE_ALARM 5 ++#define RXERR_TYPE_CCK_MPDU_OK 6 ++#define RXERR_TYPE_CCK_MPDU_FAIL 7 ++#define RXERR_TYPE_HT_PPDU 8 ++#define RXERR_TYPE_HT_FALSE_ALARM 9 ++#define RXERR_TYPE_HT_MPDU_TOTAL 10 ++#define RXERR_TYPE_HT_MPDU_OK 11 ++#define RXERR_TYPE_HT_MPDU_FAIL 12 ++#define RXERR_TYPE_RX_FULL_DROP 15 ++ ++#define RXERR_COUNTER_MASK 0xFFFFF ++#define RXERR_RPT_RST BIT(27) ++#define _RXERR_RPT_SEL(type) ((type) << 28) ++ ++ ++//2 SECCFG ++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key ++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption ++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption ++#define SCR_SKByA2 BIT(4) //Search kEY BY A2 ++#define SCR_NoSKMC BIT(5) //No Key Search Multicast ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++ ++//2 USB Information (0xFE17) ++#define USB_IS_HIGH_SPEED 0 ++#define USB_IS_FULL_SPEED 1 ++#define USB_SPEED_MASK BIT(5) ++ ++#define USB_NORMAL_SIE_EP_MASK 0xF ++#define USB_NORMAL_SIE_EP_SHIFT 4 ++ ++#define USB_TEST_EP_MASK 0x30 ++#define USB_TEST_EP_SHIFT 4 ++ ++//2 Special Option ++#define USB_AGG_EN BIT(3) ++ ++ ++//2REG_C2HEVT_CLEAR ++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message ++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. ++ ++ ++//2REG_MULTI_FUNC_CTRL(For RTL8723 Only) ++#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source ++#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control ++#define WL_FUNC_EN BIT2 // WiFi function enable ++#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source ++#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source ++#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control ++#define BT_FUNC_EN BIT18 // BT function enable ++#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source ++#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source ++#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control ++#define GPS_FUNC_EN BIT22 // GPS function enable ++ ++//3 REG_LIFECTRL_CTRL ++#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 ++#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 ++#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 ++#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 ++ ++#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. ++ ++//======================================================== ++// General definitions ++//======================================================== ++ ++#define MAC_ADDR_LEN 6 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 ++ ++#define POLLING_LLT_THRESHOLD 20 ++#define POLLING_READY_TIMEOUT_COUNT 1000 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++ ++ ++#include "basic_types.h" ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_sreset.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_sreset.h +new file mode 100644 +index 00000000..93c36282 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_sreset.h +@@ -0,0 +1,33 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192C_SRESET_C_ ++#define _RTL8192C_SRESET_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter); ++extern void rtl8192c_sreset_linked_status_check(_adapter *padapter); ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_xmit.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_xmit.h +new file mode 100644 +index 00000000..332856c5 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192c_xmit.h +@@ -0,0 +1,165 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192C_XMIT_H_ ++#define _RTL8192C_XMIT_H_ ++ ++// ++//defined for TX DESC Operation ++// ++ ++#define MAX_TID (15) ++ ++//OFFSET 0 ++#define OFFSET_SZ 0 ++#define OFFSET_SHT 16 ++#define BMC BIT(24) ++#define LSG BIT(26) ++#define FSG BIT(27) ++#define OWN BIT(31) ++ ++ ++//OFFSET 4 ++#define PKT_OFFSET_SZ 0 ++#define BK BIT(6) ++#define QSEL_SHT 8 ++#define Rate_ID_SHT 16 ++#define NAVUSEHDR BIT(20) ++#define PKT_OFFSET_SHT 26 ++#define HWPC BIT(31) ++ ++//OFFSET 8 ++#define AGG_EN BIT(29) ++ ++//OFFSET 12 ++#define SEQ_SHT 16 ++ ++//OFFSET 16 ++#define QoS BIT(6) ++#define HW_SEQ_EN BIT(7) ++#define USERATE BIT(8) ++#define DISDATAFB BIT(10) ++#define DATA_SHORT BIT(24) ++#define DATA_BW BIT(25) ++ ++//OFFSET 20 ++#define SGI BIT(6) ++ ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x2//0x01 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x5//0x4 ++#define QSLT_VO 0x7//0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++struct txrpt_ccx_8192c { ++ /* offset 0 */ ++ u8 retry_cnt:6; ++ u8 rsvd_0:2; ++ ++ /* offset 1 */ ++ u8 rts_retry_cnt:6; ++ u8 rsvd_1:2; ++ ++ /* offset 2 */ ++ u8 ccx_qtime0; ++ u8 ccx_qtime1; ++ ++ /* offset 4 */ ++ u8 missed_pkt_num:5; ++ u8 rsvd_4:3; ++ ++ /* offset 5 */ ++ u8 mac_id:5; ++ u8 des1_fragssn:3; ++ ++ /* offset 6 */ ++ u8 rpt_pkt_num:5; ++ u8 pkt_drop:1; ++ u8 lifetime_over:1; ++ u8 retry_over:1; ++ ++ /* offset 7*/ ++ u8 edca_tx_queue:4; ++ u8 rsvd_7:1; ++ u8 bmc:1; ++ u8 pkt_ok:1; ++ u8 int_ccx:1; ++}; ++ ++#define txrpt_ccx_qtime_8192c(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) ++ ++#ifdef CONFIG_XMIT_ACK ++void dump_txrpt_ccx_8192c(void *buf); ++void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf); ++#else ++#define dump_txrpt_ccx_8192c(buf) do {} while(0) ++#define handle_txrpt_ccx_8192c(adapter, buf) do {} while(0) ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++#define MAX_TX_AGG_PACKET_NUMBER 0xFF ++#endif ++ ++s32 rtl8192cu_init_xmit_priv(_adapter * padapter); ++ ++void rtl8192cu_free_xmit_priv(_adapter * padapter); ++ ++void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++ ++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8192ce_init_xmit_priv(_adapter * padapter); ++void rtl8192ce_free_xmit_priv(_adapter * padapter); ++ ++s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf); ++struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring); ++ ++void rtl8192ce_xmitframe_resume(_adapter *padapter); ++ ++s32 rtl8192ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_cmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_cmd.h +new file mode 100644 +index 00000000..ef571f1d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_cmd.h +@@ -0,0 +1,103 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192D_CMD_H_ ++#define __RTL8192D_CMD_H_ ++ ++ ++//-------------------------------------------- ++//3 Host Message Box ++//-------------------------------------------- ++ ++// User Define Message [31:8] ++ ++//_SETPWRMODE_PARM ++#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) ++ ++//JOINBSSRPT_PARM ++#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++ ++//_RSVDPAGE_LOC ++#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) ++ ++//P2P_PS_OFFLOAD ++ ++struct P2P_PS_Offload_t { ++ unsigned char Offload_En:1; ++ unsigned char role:1; // 1: Owner, 0: Client ++ unsigned char CTWindow_En:1; ++ unsigned char NoA0_En:1; ++ unsigned char NoA1_En:1; ++ unsigned char AllStaSleep:1; // Only valid in Owner ++ unsigned char discovery:1; ++ unsigned char rsvd:1; ++}; ++ ++#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) ++ ++// Description: Determine the types of H2C commands that are the same in driver and Fw. ++// Fisrt constructed by tynli. 2009.10.09. ++typedef enum _RTL8192D_H2C_CMD ++{ ++ H2C_AP_OFFLOAD = 0, /*0*/ ++ H2C_SETPWRMODE = 1, /*1*/ ++ H2C_JOINBSSRPT = 2, /*2*/ ++ H2C_RSVDPAGE = 3, ++ H2C_RSSI_REPORT = 5, ++ H2C_RA_MASK = 6, ++ H2C_P2P_PS_OFFLOAD = 8, ++ H2C_MAC_MODE_SEL = 9, ++ H2C_PWRM=15, ++ H2C_P2P_PS_CTW_CMD = 24, ++ H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15 ++ H2C_CMD_MAX ++}RTL8192D_H2C_CMD; ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++ ++void FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer); ++ ++// host message to firmware cmd ++void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode); ++void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus); ++u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param); ++u8 rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg); ++void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level); ++#ifdef CONFIG_P2P ++void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++#endif ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_dm.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_dm.h +new file mode 100644 +index 00000000..b7b91b60 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_dm.h +@@ -0,0 +1,183 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192D_DM_H__ ++#define __RTL8192D_DM_H__ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++enum{ ++ UP_LINK, ++ DOWN_LINK, ++}; ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} ++//============================================================ ++// structure and define ++//============================================================ ++ ++//###### duplicate code,will move to ODM ######### ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 10 ++#define IQK_BB_REG_NUM_92C 9 ++#define IQK_BB_REG_NUM_92D 10 ++#define IQK_BB_REG_NUM_test 6 ++#define index_mapping_NUM 13 ++#define Rx_index_mapping_NUM 15 ++#define AVG_THERMAL_NUM 8 ++#define IQK_Matrix_REG_NUM 8 ++#define IQK_Matrix_Settings_NUM 1+24+21 ++//###### duplicate code,will move to ODM ######### ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag; ++ u8 InitDMFlag; ++ u32 InitODMFlag; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ int MinUndecoratedPWDBForDM; ++ int LastMinUndecoratedPWDBForDM; ++//###### duplicate code,will move to ODM ######### ++/* ++ //for DIG ++ u8 bDMInitialGainEnable; ++ //u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++*/ ++ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ ++ //for tx power tracking ++ u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_AVG[AVG_THERMAL_NUM]; ++ u8 ThermalValue_AVG_index; ++ u8 ThermalValue_RxGain; ++ u8 ThermalValue_Crystal; ++ u8 Delta_IQK; ++ u8 Delta_LCK; ++ u8 bRfPiEnable; ++ u8 bReloadtxpowerindex; ++ u8 bDoneTxpower; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ u32 RegA24; ++ ++ //for IQK ++ u32 Reg874; ++ u32 RegC08; ++ u32 Reg88C; ++ u8 Reg522; ++ u8 Reg550; ++ u8 Reg551; ++ u32 Reg870; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ ++ u8 bCCKinCH14; ++ ++ char CCK_index; ++ //u8 Record_CCK_20Mindex; ++ //u8 Record_CCK_40Mindex; ++ char OFDM_index[2]; ++ ++ BOOLEAN bDPKdone[2]; ++ ++ u8 PowerIndex_backup[6]; ++ ++ //for Antenna diversity ++//#ifdef CONFIG_ANTENNA_DIVERSITY ++ //SWAT_T DM_SWAT_Table; ++//#endif ++ //Neil Chen----2011--06--23----- ++ //3 Path Diversity ++ BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19 ++ BOOLEAN RSSI_test; ++ s32 RSSI_sum_A; ++ s32 RSSI_cnt_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_B; ++ struct sta_info *RSSI_target; ++ _timer PathDivSwitchTimer; ++ ++ //for TxPwrTracking ++ int RegE94; ++ int RegE9C; ++ int RegEB4; ++ int RegEBC; ++#if MP_DRIVER == 1 ++ u8 RegC04_MP; ++ u32 RegD04_MP; ++#endif ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++ u32 RegRF3C[2]; //pathA / pathB ++//###### duplicate code,will move to ODM ######### ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ u8 INIDATA_RATE[32]; ++}; ++ ++ ++//============================================================ ++// function prototype ++//============================================================ ++void rtl8192d_init_dm_priv(IN PADAPTER Adapter); ++void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter); ++ ++void rtl8192d_InitHalDm(IN PADAPTER Adapter); ++void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter); ++ ++#endif //__HAL8190PCIDM_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_hal.h +new file mode 100644 +index 00000000..97083f0a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_hal.h +@@ -0,0 +1,854 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192D_HAL_H__ ++#define __RTL8192D_HAL_H__ ++ ++#include "rtl8192d_spec.h" ++#include "Hal8192DPhyReg.h" ++#include "Hal8192DPhyCfg.h" ++#include "rtl8192d_rf.h" ++#include "rtl8192d_dm.h" ++#include "rtl8192d_recv.h" ++#include "rtl8192d_xmit.h" ++#include "rtl8192d_cmd.h" ++#include "rtw_efuse.h" ++ ++#include "../hal/OUTSRC/odm_precomp.h" ++ ++#ifdef CONFIG_PCI_HCI ++ #include ++ ++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R ++ ++//--------------------------------------------------------------------- ++// RTL8192DE From file ++//--------------------------------------------------------------------- ++ #define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin" ++ ++ #define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt" ++ #define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt" ++ #define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt" ++ ++ #define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt" ++ #define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt" ++ #define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt" ++ #define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt" ++ #define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt" ++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt" ++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt" ++ #define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8192DE From header ++//--------------------------------------------------------------------- ++ // Fw Array ++ #define Rtl8192D_FwImageArray Rtl8192DEFwImgArray ++ ++ // MAC/BB/PHY Array ++ #define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array ++ #define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array ++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray ++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray ++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray ++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray ++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray ++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray ++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG ++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP ++ #define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray ++ #define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray ++ #define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray ++ #define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray ++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray ++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray ++ ++ // Array length ++ #define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength ++ #define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength ++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength ++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength ++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength ++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength ++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength ++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength ++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength ++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength ++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength ++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength ++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength ++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength ++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength ++ ++#elif defined(CONFIG_USB_HCI) ++ ++ ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ ++//--------------------------------------------------------------------- ++// RTL8192DU From file ++//--------------------------------------------------------------------- ++ #define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin" ++ ++ #define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt" ++ #define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt" ++ #define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt" ++ ++ #define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt" ++ #define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt" ++ #define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt" ++ #define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt" ++ #define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt" ++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt" ++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt" ++ #define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8192DU From header ++//--------------------------------------------------------------------- ++ ++ // Fw Array ++ #define Rtl8192D_FwImageArray Rtl8192DUFwImgArray ++ ++ // MAC/BB/PHY Array ++ #define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array ++ #define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array ++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray ++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray ++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray ++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray ++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray ++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray ++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG ++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP ++ #define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray ++ #define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray ++ #define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray ++ #define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray ++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray ++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray ++ ++ // Array length ++ #define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength ++ #define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength ++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength ++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength ++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength ++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength ++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength ++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength ++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength ++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength ++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength ++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength ++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength ++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength ++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength ++ ++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24. ++/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray ++ #define Rtl819XMAC_Array Rtl8192DUMAC_2TArray ++ #define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array ++ #define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray ++ #define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray ++ #define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray ++ #define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray ++ #define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray ++ #define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP ++ ++ #define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/ ++ ++#endif ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++// ++// Check if FW header exists. We do not consider the lower 4 bits in this case. ++// By tynli. 2009.12.04. ++// ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 ) ++ ++#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length). ++#define FW_8192D_START_ADDRESS 0x1000 ++#define FW_8192D_END_ADDRESS 0x1FFF ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++typedef enum _FIRMWARE_SOURCE{ ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE{ ++ FIRMWARE_SOURCE eFWSource; ++ u8* szFwBuffer; ++ u32 ulFwLength; ++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D; ++ ++// ++// This structure must be cared byte-ordering ++// ++// Added by tynli. 2009.12.04. ++typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u8 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u16 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++ ++}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR; ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++typedef enum _BT_CoType{ ++ BT_2Wire = 0, ++ BT_ISSC_3Wire = 1, ++ BT_Accel = 2, ++ BT_CSR = 3, ++ BT_CSR_ENHAN = 4, ++ BT_RTL8756 = 5, ++} BT_CoType, *PBT_CoType; ++ ++typedef enum _BT_CurState{ ++ BT_OFF = 0, ++ BT_ON = 1, ++} BT_CurState, *PBT_CurState; ++ ++typedef enum _BT_ServiceType{ ++ BT_SCO = 0, ++ BT_A2DP = 1, ++ BT_HID = 2, ++ BT_HID_Idle = 3, ++ BT_Scan = 4, ++ BT_Idle = 5, ++ BT_OtherAction = 6, ++ BT_Busy = 7, ++ BT_OtherBusy = 8, ++} BT_ServiceType, *PBT_ServiceType; ++ ++typedef enum _BT_RadioShared{ ++ BT_Radio_Shared = 0, ++ BT_Radio_Individual = 1, ++} BT_RadioShared, *PBT_RadioShared; ++ ++typedef struct _BT_COEXIST_STR{ ++ u8 BluetoothCoexist; ++ u8 BT_Ant_Num; ++ u8 BT_CoexistType; ++ u8 BT_State; ++ u8 BT_CUR_State; //0:on, 1:off ++ u8 BT_Ant_isolation; //0:good, 1:bad ++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic ++ u8 BT_Service; ++ u8 BT_RadioSharedType; ++ u8 Ratio_Tx; ++ u8 Ratio_PRI; ++}BT_COEXIST_STR, *PBT_COEXIST_STR; ++ ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_DMA_USB ++}USB_RX_AGG_MODE; ++ ++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++ ++#define TX_TOTAL_PAGE_NUMBER 0xF8 ++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) ++ ++// For Normal Chip Setting ++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define NORMAL_PAGE_NUM_PUBQ 0x56 ++ ++ ++// For Test Chip Setting ++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define TEST_PAGE_NUM_PUBQ 0x89 ++#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A ++#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A ++#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0 ++ ++#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1) ++ ++// For Test Chip Setting ++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 ++#define WMM_TEST_PAGE_NUM_HPQ 0x29 ++#define WMM_TEST_PAGE_NUM_LPQ 0x29 ++ ++ ++//Note: For Normal Chip Setting ,modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 ++#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C ++#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82 ++#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30 ++#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30 ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++ ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++ ++#include "HalVerDef.h" ++#include "hal_com.h" ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++typedef struct _TxPowerInfo{ ++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 TSSI_A[3]; ++ u8 TSSI_B[3]; ++ u8 TSSI_A_5G[3]; //5GL/5GM/5GH ++ u8 TSSI_B_5G[3]; ++}TxPowerInfo, *PTxPowerInfo; ++ ++#define EFUSE_REAL_CONTENT_LEN 1024 ++#define EFUSE_MAP_LEN 256 ++#define EFUSE_MAX_SECTION 32 ++#define EFUSE_MAX_SECTION_BASE 16 ++// To prevent out of boundary programming case, leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 2byte|----8bytes----|1byte|--7bytes--| //92D ++#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. ++ ++typedef enum _PA_MODE { ++ PA_MODE_EXTERNAL = 0x00, ++ PA_MODE_INTERNAL_SP3T = 0x01, ++ PA_MODE_INTERNAL_SPDT = 0x02 ++} PA_MODE; ++ ++/* Copy from rtl8192c */ ++enum c2h_id_8192d { ++ C2H_DBG = 0, ++ C2H_TSF = 1, ++ C2H_AP_RPT_RSP = 2, ++ C2H_CCX_TX_RPT = 3, ++ C2H_BT_RSSI = 4, ++ C2H_BT_OP_MODE = 5, ++ C2H_EXT_RA_RPT = 6, ++ C2H_HW_INFO_EXCH = 10, ++ C2H_C2H_H2C_TEST = 11, ++ C2H_BT_INFO = 12, ++ C2H_BT_MP_INFO = 15, ++ MAX_C2HEVENT ++}; ++ ++#ifdef CONFIG_PCI_HCI ++struct hal_data_8192de ++{ ++ HAL_VERSION VersionID; ++ // add for 92D Phy mode/mac/Band mode ++ MACPHY_MODE_8192D MacPhyMode92D; ++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G ++ BAND_TYPE BandSet92D; ++ BOOLEAN bIsVS; ++ BOOLEAN bSupportRemoteWakeUp; ++ u8 AutoLoadStatusFor8192D; ++ ++ BOOLEAN bNOPG; ++ ++ BOOLEAN bMasterOfDMSP; ++ BOOLEAN bSlaveOfDMSP; ++ ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ u32 IntrMask[2]; ++ u32 IntrMaskToSet[2]; ++ ++ u32 DisabledFunctions; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ u32 TransmitConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMDID; ++ u16 EEPROMSVID; ++ u16 EEPROMSMID; ++ u16 EEPROMChannelPlan; ++ u16 EEPROMVersion; ++ ++ u8 EEPROMCustomerID; ++ u8 EEPROMBoardType; ++ u8 EEPROMRegulatory; ++ ++ u8 EEPROMThermalMeter; ++ ++ u8 EEPROMC9; ++ u8 EEPROMCC; ++ u8 PAMode; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ u8 CrystalCap; // CrystalCap. ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ u8 InternalPA5G[2]; //pathA / pathB ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ u32 RfRegChnlVal[2]; ++ ++ ++ BOOLEAN bPhyValueInitReady; ++ ++ BOOLEAN bTXPowerDataReadFromEEPORM; ++ ++ BOOLEAN bInSetPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress ++ BOOLEAN bNeedIQK; ++ ++ BOOLEAN bLCKInProgress; ++ ++ BOOLEAN bEarlyModeEnable; ++ ++#if 1 ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; ++#else ++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78 ++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. ++#endif ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegTxPause; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 RegCR_1; ++ ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++ u8 bInterruptMigration; ++ ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u16 RegRRSR; ++ ++ u16 EfuseUsedBytes; ++ ++ BOOLEAN EepromOrEfuse; ++ u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u8 EfuseUsedPercentage; ++ EFUSE_HAL EfuseHal; ++ ++ u8 RTSInitRate; // 2010.11.24.by tynli. ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++ ++// ++// Function disabled. ++// ++#define DF_TX_BIT BIT0 ++#define DF_RX_BIT BIT1 ++#define DF_IO_BIT BIT2 ++#define DF_IO_D3_BIT BIT3 ++ ++#define RT_DF_TYPE u32 ++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits))) ++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits)))) ++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) ++ ++void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent); ++VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++//should be renamed and moved to another file ++typedef enum _INTERFACE_SELECT_8192DUSB{ ++ INTF_SEL0_USB = 0, // USB ++ INTF_SEL1_MINICARD = 1, // Minicard ++ INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary ++ INTF_SEL3_PRO = 3, // Customized proprietary ++} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB; ++ ++typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB; ++ ++struct hal_data_8192du ++{ ++ HAL_VERSION VersionID; ++ ++ // add for 92D Phy mode/mac/Band mode ++ MACPHY_MODE_8192D MacPhyMode92D; ++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G ++ BAND_TYPE BandSet92D; ++ BOOLEAN bIsVS; ++ ++ BOOLEAN bNOPG; ++ ++ BOOLEAN bSupportRemoteWakeUp; ++ BOOLEAN bMasterOfDMSP; ++ BOOLEAN bSlaveOfDMSP; ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ BOOLEAN bInModeSwitchProcess; ++#endif ++ ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ u16 BasicRateSet; ++ ++ INTERFACE_SELECT_8192DUSB InterfaceSel; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ // ++ // EEPROM setting. ++ // ++ u8 EEPROMVersion; ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMRegulatory; ++ ++ u8 EEPROMThermalMeter; ++ ++ u8 EEPROMC9; ++ u8 EEPROMCC; ++ u8 PAMode; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ u8 CrystalCap; // CrystalCap. ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ u8 InternalPA5G[2]; //pathA / pathB ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ ++ u32 RfRegChnlVal[2]; ++ ++ ++ BOOLEAN bPhyValueInitReady; ++ ++ BOOLEAN bTXPowerDataReadFromEEPORM; ++ ++ BOOLEAN bInSetPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress ++ BOOLEAN bNeedIQK; ++ ++ BOOLEAN bLCKInProgress; ++ ++ BOOLEAN bEarlyModeEnable; ++ ++#if 1 ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; ++#else ++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78 ++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. ++#endif ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegTxPause; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 RegCR_1; ++ ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ //Query RF by FW ++ BOOLEAN bReadRFbyFW; ++ ++ // For 92C USB endpoint setting ++ // ++ ++ u32 UsbBulkOutSize; ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 UsbTxAggMode; ++ u8 UsbTxAggDescNum; ++#endif ++#ifdef CONFIG_USB_RX_AGGREGATION ++ u16 HwRxPageSize; // Hardware setting ++ u32 MaxUsbRxAggBlock; ++ ++ USB_RX_AGG_MODE UsbRxAggMode; ++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed ++ u8 UsbRxAggBlockTimeout; ++ u8 UsbRxAggPageCount; // 8192C DMA page count ++ u8 UsbRxAggPageTimeout; ++#endif ++ ++ u16 RegRRSR; ++ ++ u16 EfuseUsedBytes; ++ ++ BOOLEAN EepromOrEfuse; ++ u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u8 EfuseUsedPercentage; ++ EFUSE_HAL EfuseHal; ++ ++ u8 RTSInitRate; // 2010.11.24.by tynli. ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++#endif ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++int FirmwareDownload92D(IN PADAPTER Adapter); ++VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter); ++void rtl8192d_ReadChipVersion(IN PADAPTER Adapter); ++VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail); ++VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter); ++u8 GetEEPROMSize8192D(PADAPTER Adapter); ++BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter); ++VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter); ++//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter); ++void rtl8192d_free_hal_data(_adapter * padapter); ++void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc); ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_led.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_led.h +new file mode 100644 +index 00000000..c75df2ef +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_led.h +@@ -0,0 +1,43 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192D_LED_H_ ++#define __RTL8192D_LED_H_ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8192du_InitSwLeds(_adapter *padapter); ++void rtl8192du_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++void rtl8192de_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8192de_InitSwLeds(_adapter *padapter); ++void rtl8192de_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_recv.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_recv.h +new file mode 100644 +index 00000000..5ffec395 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_recv.h +@@ -0,0 +1,139 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192D_RECV_H_ ++#define _RTL8192D_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ #ifdef CONFIG_SDIO_HCI ++ #define NR_RECVBUFF 1024//512//128 ++ #else ++ #define NR_RECVBUFF (16) ++ #endif ++#elif defined(PLATFORM_OS_CE) ++ #ifdef CONFIG_SDIO_HCI ++ #define NR_RECVBUFF (128) ++ #else ++ #define NR_RECVBUFF (4) ++ #endif ++#else ++#ifdef CONFIG_SINGLE_RECV_BUF ++ #define NR_RECVBUFF (1) ++#else ++ #define NR_RECVBUFF (4) ++#endif //CONFIG_SINGLE_RECV_BUF ++ #define NR_PREALLOC_RECV_SKB (8) ++#endif ++ ++ ++ ++#define RECV_BLK_SZ 512 ++#define RECV_BLK_CNT 16 ++#define RECV_BLK_TH RECV_BLK_CNT ++ ++#if defined(CONFIG_USB_HCI) ++ ++#ifdef PLATFORM_OS_CE ++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++#else ++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ //#define MAX_RECVBUF_SZ (32768) // 32k ++ //#define MAX_RECVBUF_SZ (16384) //16K ++ //#define MAX_RECVBUF_SZ (10240) //10K ++ #ifdef CONFIG_PLATFORM_MSTAR ++ #define MAX_RECVBUF_SZ (8192) // 8K ++ #else ++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k ++ #endif ++ #else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++ #endif ++#endif ++ ++#elif defined(CONFIG_PCI_HCI) ++//#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++// #define MAX_RECVBUF_SZ (9100) ++//#else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++//#endif ++ ++#define RX_MPDU_QUEUE 0 ++#define RX_CMD_QUEUE 1 ++#define RX_MAX_QUEUE 2 ++#endif ++ ++#define RECV_BULK_IN_ADDR 0x80 ++#define RECV_INT_IN_ADDR 0x81 ++ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++#define PHY_LINKQUALITY_SLID_WIN_MAX 20 ++ ++struct phy_stat ++{ ++ unsigned int phydw0; ++ ++ unsigned int phydw1; ++ ++ unsigned int phydw2; ++ ++ unsigned int phydw3; ++ ++ unsigned int phydw4; ++ ++ unsigned int phydw5; ++ ++ unsigned int phydw6; ++ ++ unsigned int phydw7; ++}; ++ ++// Rx smooth factor ++#define Rx_Smooth_Factor (20) ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _INTERRUPT_MSG_FORMAT_EX{ ++ unsigned int C2H_MSG0; ++ unsigned int C2H_MSG1; ++ unsigned int C2H_MSG2; ++ unsigned int C2H_MSG3; ++ unsigned int HISR; // from HISR Reg0x124, read to clear ++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear ++ unsigned int MSG_EX; ++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; ++ ++void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); ++int rtl8192du_init_recv_priv(_adapter * padapter); ++void rtl8192du_free_recv_priv(_adapter * padapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++int rtl8192de_init_recv_priv(_adapter * padapter); ++void rtl8192de_free_recv_priv(_adapter * padapter); ++#endif ++ ++void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status); ++void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_rf.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_rf.h +new file mode 100644 +index 00000000..8fc17e25 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_rf.h +@@ -0,0 +1,97 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192d_rf.h ( Header File) ++ * ++ * Note: Collect every HAL RF type exter API or constant. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * ++ * ++******************************************************************************/ ++#ifndef _RTL8192D_RF_H_ ++#define _RTL8192D_RF_H_ ++/* Check to see if the file has been included already. */ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++// ++// For RF 6052 Series ++// ++#define RF6052_MAX_TX_PWR 0x3F ++#define RF6052_MAX_REG 0x3F ++#define RF6052_MAX_PATH 2 ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++// ++// RF RL6052 Series API ++// ++void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate); ++void rtl8192d_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth); ++VOID rtl8192d_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel); ++VOID rtl8192d_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel); ++int PHY_RF6052_Config8192D( IN PADAPTER Adapter ); ++ ++BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0); ++ ++void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0); ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++ ++#endif/* End of HalRf.h */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_spec.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_spec.h +new file mode 100644 +index 00000000..74e11d5a +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_spec.h +@@ -0,0 +1,1761 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __RTL8192D_SPEC_H__ ++#define __RTL8192D_SPEC_H__ ++ ++#include ++ ++//============================================================ ++// 8192D Regsiter offset definition ++//============================================================ ++ ++ ++//============================================================ ++// ++//============================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYS_ISO_CTRL 0x0000 ++#define REG_SYS_FUNC_EN 0x0002 ++#define REG_APS_FSMCO 0x0004 ++#define REG_SYS_CLKR 0x0008 ++#define REG_9346CR 0x000A ++#define REG_EE_VPD 0x000C ++#define REG_AFE_MISC 0x0010 ++#define REG_SPS0_CTRL 0x0011 ++#define REG_POWER_OFF_IN_PROCESS 0x0017 ++#define REG_SPS_OCP_CFG 0x0018 ++#define REG_RSV_CTRL 0x001C ++#define REG_RF_CTRL 0x001F ++#define REG_LDOA15_CTRL 0x0020 ++#define REG_LDOV12D_CTRL 0x0021 ++#define REG_LDOHCI12_CTRL 0x0022 ++#define REG_LPLDO_CTRL 0x0023 ++#define REG_AFE_XTAL_CTRL 0x0024 ++#define REG_AFE_PLL_CTRL 0x0028 ++#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl ++#define REG_EFUSE_CTRL 0x0030 ++#define REG_EFUSE_TEST 0x0034 ++#define REG_PWR_DATA 0x0038 ++#define REG_CAL_TIMER 0x003C ++#define REG_ACLK_MON 0x003E ++#define REG_GPIO_MUXCFG 0x0040 ++//#define REG_GPIO_MUXCFG 0x0041 ++#define REG_GPIO_IO_SEL 0x0042 ++#define REG_MAC_PINMUX_CFG 0x0043 ++#define REG_GPIO_PIN_CTRL 0x0044 ++#define REG_GPIO_INTM 0x0048 ++#define REG_LEDCFG0 0x004C ++#define REG_LEDCFG1 0x004D ++#define REG_LEDCFG2 0x004E ++#define REG_LEDCFG3 0x004F ++#define REG_FSIMR 0x0050 ++#define REG_FSISR 0x0054 ++ ++#define REG_MCUFWDL 0x0080 ++ ++#define REG_HMEBOX_EXT_0 0x0088 ++#define REG_HMEBOX_EXT_1 0x008A ++#define REG_HMEBOX_EXT_2 0x008C ++#define REG_HMEBOX_EXT_3 0x008E ++ ++#define REG_BIST_SCAN 0x00D0 ++#define REG_BIST_RPT 0x00D4 ++#define REG_BIST_ROM_RPT 0x00D8 ++#define REG_USB_SIE_INTF 0x00E0 ++#define REG_PCIE_MIO_INTF 0x00E4 ++#define REG_PCIE_MIO_INTD 0x00E8 ++#define REG_HPON_FSM 0x00EC ++#define REG_SYS_CFG 0x00F0 ++#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 ++ ++#define REG_MAC0 0x0081 ++#define REG_MAC1 0x0053 ++#define FW_MAC0_ready 0x18 ++#define FW_MAC1_ready 0x1A ++#define MAC0_ON BIT7 ++#define MAC1_ON BIT0 ++#define mac0_ready BIT0 ++#define mac1_ready BIT0 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_CR 0x0100 ++#define REG_PBP 0x0104 ++#define REG_TRXDMA_CTRL 0x010C ++#define REG_TRXFF_BNDY 0x0114 ++#define REG_TRXFF_STATUS 0x0118 ++#define REG_RXFF_PTR 0x011C ++#define REG_HIMR 0x0120 ++#define REG_HISR 0x0124 ++#define REG_HIMRE 0x0128 ++#define REG_HISRE 0x012C ++#define REG_CPWM 0x012F ++#define REG_FWIMR 0x0130 ++#define REG_FWISR 0x0134 ++#define REG_FTIMR 0x0138 ++#define REG_PKTBUF_DBG_CTRL 0x0140 ++#define REG_PKTBUF_DBG_DATA_L 0x0144 ++#define REG_PKTBUF_DBG_DATA_H 0x0148 ++ ++#define REG_TC0_CTRL 0x0150 ++#define REG_TC1_CTRL 0x0154 ++#define REG_TC2_CTRL 0x0158 ++#define REG_TC3_CTRL 0x015C ++#define REG_TC4_CTRL 0x0160 ++#define REG_TCUNIT_BASE 0x0164 ++#define REG_MBIST_START 0x0174 ++#define REG_MBIST_DONE 0x0178 ++#define REG_MBIST_FAIL 0x017C ++#define REG_C2HEVT_MSG_NORMAL 0x01A0 ++#define REG_C2HEVT_CLEAR 0x01AF ++#define REG_C2HEVT_MSG_TEST 0x01B8 ++#define REG_MCUTST_1 0x01c0 ++#define REG_FMETHR 0x01C8 ++#define REG_HMETFR 0x01CC ++#define REG_HMEBOX_0 0x01D0 ++#define REG_HMEBOX_1 0x01D4 ++#define REG_HMEBOX_2 0x01D8 ++#define REG_HMEBOX_3 0x01DC ++ ++#define REG_LLT_INIT 0x01E0 ++#define REG_BB_ACCEESS_CTRL 0x01E8 ++#define REG_BB_ACCESS_DATA 0x01EC ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RQPN 0x0200 ++#define REG_FIFOPAGE 0x0204 ++#define REG_TDECTRL 0x0208 ++#define REG_TXDMA_OFFSET_CHK 0x020C ++#define REG_TXDMA_STATUS 0x0210 ++#define REG_RQPN_NPQ 0x0214 ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RXDMA_AGG_PG_TH 0x0280 ++#define REG_RXPKT_NUM 0x0284 ++#define REG_RXDMA_STATUS 0x0288 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++#define REG_PCIE_CTRL_REG 0x0300 ++#define REG_INT_MIG 0x0304 // Interrupt Migration ++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address ++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address ++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address ++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address ++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address ++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address ++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address ++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address ++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration ++//sherry added for DBI Read/Write 20091126 ++#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration ++#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration ++#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration ++#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_DBG_SEL 0x0360 // Debug Selection Register ++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM ++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM ++#define REG_UART_CTRL 0x0364 // UART Control ++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address ++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address ++ ++ ++// spec version 11 ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++#define REG_VOQ_INFORMATION 0x0400 ++#define REG_VIQ_INFORMATION 0x0404 ++#define REG_BEQ_INFORMATION 0x0408 ++#define REG_BKQ_INFORMATION 0x040C ++#define REG_MGQ_INFORMATION 0x0410 ++#define REG_HGQ_INFORMATION 0x0414 ++#define REG_BCNQ_INFORMATION 0x0418 ++ ++ ++#define REG_CPU_MGQ_INFORMATION 0x041C ++#define REG_FWHW_TXQ_CTRL 0x0420 ++#define REG_HWSEQ_CTRL 0x0423 ++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 ++#define REG_TXPKTBUF_MGQ_BDNY 0x0425 ++#define REG_LIFETIME_EN 0x0426 ++#define REG_MULTI_BCNQ_OFFSET 0x0427 ++#define REG_SPEC_SIFS 0x0428 ++#define REG_RL 0x042A ++#define REG_DARFRC 0x0430 ++#define REG_RARFRC 0x0438 ++#define REG_RRSR 0x0440 ++#define REG_ARFR0 0x0444 ++#define REG_ARFR1 0x0448 ++#define REG_ARFR2 0x044C ++#define REG_ARFR3 0x0450 ++#define REG_AGGLEN_LMT 0x0458 ++#define REG_AMPDU_MIN_SPACE 0x045C ++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D ++#define REG_FAST_EDCA_CTRL 0x0460 ++#define REG_RD_RESP_PKT_TH 0x0463 ++#define REG_INIRTS_RATE_SEL 0x0480 ++#define REG_INIDATA_RATE_SEL 0x0484 ++ ++#define REG_FW_TSF_SYNC_CNT 0x04A0 ++#define REG_FW_BCN_DIS_CNT 0x04A1 ++ ++#define REG_POWER_STATUS 0x04A4 ++#define REG_POWER_STAGE1 0x04B4 ++#define REG_POWER_STAGE2 0x04B8 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 ++#define REG_STBC_SETTING 0x04C4 ++#define REG_PROT_MODE_CTRL 0x04C8 ++#define REG_MAX_AGGR_NUM 0x04CA ++#define REG_RTS_MAX_AGGR_NUM 0x04CB ++#define REG_BAR_MODE_CTRL 0x04CC ++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF ++#define REG_EARLY_MODE_CONTROL 0x04D0 ++#define REG_NQOS_SEQ 0x04DC ++#define REG_QOS_SEQ 0x04DE ++#define REG_NEED_CPU_HANDLE 0x04E0 ++#define REG_PKT_LOSE_RPT 0x04E1 ++#define REG_PTCL_ERR_STATUS 0x04E2 ++#define REG_DUMMY 0x04FC ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++#define REG_EDCA_VO_PARAM 0x0500 ++#define REG_EDCA_VI_PARAM 0x0504 ++#define REG_EDCA_BE_PARAM 0x0508 ++#define REG_EDCA_BK_PARAM 0x050C ++#define REG_BCNTCFG 0x0510 ++#define REG_PIFS 0x0512 ++#define REG_RDG_PIFS 0x0513 ++#define REG_SIFS_CTX 0x0514 ++#define REG_SIFS_TRX 0x0516 ++#define REG_TSFTR_SYN_OFFSET 0x0518 ++#define REG_AGGR_BREAK_TIME 0x051A ++#define REG_SLOT 0x051B ++#define REG_TX_PTCL_CTRL 0x0520 ++#define REG_TXPAUSE 0x0522 ++#define REG_DIS_TXREQ_CLR 0x0523 ++#define REG_RD_CTRL 0x0524 ++#define REG_TBTT_PROHIBIT 0x0540 ++#define REG_RD_NAV_NXT 0x0544 ++#define REG_NAV_PROT_LEN 0x0546 ++#define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 ++#define REG_MBID_NUM 0x0552 ++#define REG_DUAL_TSF_RST 0x0553 ++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE ++#define REG_MBSSID_BCN_SPACE 0x0554 ++#define REG_DRVERLYINT 0x0558 ++#define REG_BCNDMATIM 0x0559 ++#define REG_ATIMWND 0x055A ++#define REG_USTIME_TSF 0x055C ++#define REG_BCN_MAX_ERR 0x055D ++#define REG_RXTSF_OFFSET_CCK 0x055E ++#define REG_RXTSF_OFFSET_OFDM 0x055F ++#define REG_TSFTR 0x0560 ++#define REG_TSFTR1 0x0568 ++#define REG_INIT_TSFTR 0x0564 ++#define REG_ATIMWND_1 0x0570 ++#define REG_PSTIMER 0x0580 ++#define REG_TIMER0 0x0584 ++#define REG_TIMER1 0x0588 ++#define REG_ACMHWCTRL 0x05C0 ++#define REG_ACMRSTCTRL 0x05C1 ++#define REG_ACMAVG 0x05C2 ++#define REG_VO_ADMTIME 0x05C4 ++#define REG_VI_ADMTIME 0x05C6 ++#define REG_BE_ADMTIME 0x05C8 ++#define REG_EDCA_RANDOM_GEN 0x05CC ++#define REG_SCH_TXCMD 0x05D0 ++ ++#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++#define REG_APSD_CTRL 0x0600 ++#define REG_BWOPMODE 0x0603 ++#define REG_TCR 0x0604 ++#define REG_RCR 0x0608 ++#define REG_RX_PKT_LIMIT 0x060C ++#define REG_RX_DLK_TIME 0x060D ++#define REG_RX_DRVINFO_SZ 0x060F ++ ++#define REG_MACID 0x0610 ++#define REG_BSSID 0x0618 ++#define REG_MAR 0x0620 ++#define REG_MBIDCAMCFG 0x0628 ++ ++#define REG_USTIME_EDCA 0x0638 ++#define REG_MAC_SPEC_SIFS 0x063A ++#define REG_RESP_SIFS_CCK 0x063C ++#define REG_RESP_SIFS_OFDM 0x063E ++#define REG_ACKTO 0x0640 ++#define REG_CTS2TO 0x0641 ++#define REG_EIFS 0x0642 ++ ++ ++//WMA, BA, CCX ++#define REG_NAV_CTRL 0x0650 ++#define REG_BACAMCMD 0x0654 ++#define REG_BACAMCONTENT 0x0658 ++#define REG_LBDLY 0x0660 ++#define REG_FWDLY 0x0661 ++#define REG_RXERR_RPT 0x0664 ++#define REG_WMAC_TRXPTCL_CTL 0x0668 ++ ++ ++// Security ++#define REG_CAMCMD 0x0670 ++#define REG_CAMWRITE 0x0674 ++#define REG_CAMREAD 0x0678 ++#define REG_CAMDBG 0x067C ++#define REG_SECCFG 0x0680 ++ ++// Power ++#define REG_WOW_CTRL 0x0690 ++#define REG_PSSTATUS 0x0691 ++#define REG_PS_RX_INFO 0x0692 ++#define REG_LPNAV_CTRL 0x0694 ++#define REG_WKFMCAM_CMD 0x0698 ++#define REG_WKFMCAM_RWD 0x069C ++#define REG_RXFLTMAP0 0x06A0 ++#define REG_RXFLTMAP1 0x06A2 ++#define REG_RXFLTMAP2 0x06A4 ++#define REG_BCN_PSR_RPT 0x06A8 ++#define REG_CALB32K_CTRL 0x06AC ++#define REG_PKT_MON_CTRL 0x06B4 ++#define REG_BT_COEX_TABLE 0x06C0 ++#define REG_WMAC_RESP_TXINFO 0x06D8 ++ ++#define REG_MACID1 0x0700 ++#define REG_BSSID1 0x0708 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++// for 92DU high_Queue low_Queue Normal_Queue select ++#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 ++//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45 ++#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 ++//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48 ++ ++// For test chip ++#define REG_TEST_USB_TXQS 0xFE48 ++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_TEST_SIE_OPTIONAL 0xFE64 ++#define REG_TEST_SIE_CHIRP_K 0xFE65 ++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B ++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 ++ ++ ++// For normal chip ++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_NORMAL_SIE_OPTIONAL 0xFE64 ++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 ++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B ++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF ++ ++ ++//----------------------------------------------------- ++// ++// Redifine 8192C register definition for compatibility ++// ++//----------------------------------------------------- ++ ++// TODO: use these definition when using REG_xxx naming rule. ++// NOTE: DO NOT Remove these definition. Use later. ++ ++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control. ++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable. ++#define SYS_CLK REG_SYS_CLKR ++#define CR9346 REG_9346CR // 93C46/93C56 Command Register. ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. ++#define MSR (REG_CR + 2) // Media Status register ++#define ISR REG_HISR ++#define TSFR REG_TSFTR // Timing Sync Function Timer Register. ++ ++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 ++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 ++ ++#define PBP REG_PBP ++ ++// Redifine MACID register, to compatible prior ICs. ++#define IDR0 MACIDR0 ++#define IDR4 MACIDR4 ++ ++ ++// ++// 9. Security Control Registers (Offset: ) ++// ++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd ++#define WCAMI REG_CAMWRITE // Software write CAM input content ++#define RCAMO REG_CAMREAD // Software read/write CAM config ++#define CAMDBG REG_CAMDBG ++#define SECR REG_SECCFG //Security Configuration Register ++ ++// Unused register ++#define UnusedRegister 0x1BF ++#define DCAM UnusedRegister ++#define PSR UnusedRegister ++#define BBAddr UnusedRegister ++#define PhyDataR UnusedRegister ++ ++#define InvalidBBRFValue 0x12345678 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C Cmd9346CR bits (Offset 0xA, 16bit) ++//---------------------------------------------------------------------------- ++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 ++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 ++#define Cmd9346CR_9356SEL BIT4 ++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) ++#define AutoLoadEFUSE CmdEEPROM_En ++ ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++/* ++Network Type ++00: No link ++01: Link in ad hoc network ++10: Link in infrastructure network ++11: AP mode ++Default: 00b. ++*/ ++#define MSR_NOLINK 0x00 ++#define MSR_ADHOC 0x01 ++#define MSR_INFRA 0x02 ++#define MSR_AP 0x03 ++ ++// ++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) ++// ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x181, 24bits) ++//---------------------------------------------------------------------------- ++#define RRSR_RSC_OFFSET 21 ++#define RRSR_SHORT_OFFSET 23 ++#define RRSR_RSC_BW_40M 0x600000 ++#define RRSR_RSC_UPSUBCHNL 0x400000 ++#define RRSR_RSC_LOWSUBCHNL 0x200000 ++#define RRSR_SHORT 0x800000 ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++#define BRSR_AckShortPmb BIT23 ++// CCK ACK: use Short Preamble or not ++ ++//---------------------------------------------------------------------------- ++// 8192C BW_OPMODE bits (Offset 0x203, 8bit) ++//---------------------------------------------------------------------------- ++#define BW_OPMODE_20MHZ BIT2 ++#define BW_OPMODE_5G BIT1 ++#define BW_OPMODE_11J BIT0 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C CAM Config Setting (offset 0x250, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_CONTENT_COUNT 8 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++#define CAM_SMS4 0x6 ++ ++ ++#define TOTAL_CAM_ENTRY 32 ++#define HALF_CAM_ENTRY 16 ++ ++#define CAM_CONFIG_USEDK _TRUE ++#define CAM_CONFIG_NO_USEDK _FALSE ++ ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++ ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++ ++// ++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) ++// ++//---------------------------------------------------------------------------- ++// 8190 IMR/ISR bits (offset 0xfd, 8bits) ++//---------------------------------------------------------------------------- ++#define IMR8190_DISABLED 0x0 ++// IMR DW0 Bit 0-31 ++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 ++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 ++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 ++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 ++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 ++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 ++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 ++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 ++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 ++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 ++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 ++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow ++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt ++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 ++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow ++#define IMR_RDU BIT11 // Receive Descriptor Unavailable ++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt ++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup ++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt ++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup ++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt ++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt ++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt ++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt ++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt ++#define IMR_ROK BIT0 // Receive DMA OK Interrupt ++ ++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) ++#define IMR_TXERR BIT11 ++#define IMR_RXERR BIT10 ++#define IMR_C2HCMD BIT9 ++#define IMR_CPWM BIT8 ++//RSVD [2-7] ++#define IMR_OCPINT BIT1 ++#define IMR_WLANOFF BIT0 ++ ++ ++ ++//---------------------------------------------------------------------------- ++// 8192D EFUSE ++//---------------------------------------------------------------------------- ++#define HWSET_MAX_SIZE 256 ++ ++//---------------------------------------------------------------------------- ++// 8192C EEPROM/EFUSE share register definition. ++//---------------------------------------------------------------------------- ++ ++// ++// Default Value for EEPROM or EFUSE!!! ++// ++#define EEPROM_Default_TSSI 0x0 ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0 ++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_Default_HT2T_TxPwr 0x10 ++ ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 ++#define EEPROM_Default_ThermalMeter 0x12 ++ ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++//#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#define EEPROM_Default_TxPowerLevel_2G 0x2C ++#define EEPROM_Default_TxPowerLevel_5G 0x22 ++ ++#define EEPROM_Default_HT40_2SDiff 0x0 ++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff ++#define EEPROM_Default_HT40_PwrMaxOffset 0 ++#define EEPROM_Default_HT20_PwrMaxOffset 0 ++ ++// For debug ++#define EEPROM_Default_PID 0x1234 ++#define EEPROM_Default_VID 0x5678 ++#define EEPROM_Default_CustomerID 0xAB ++#define EEPROM_Default_SubCustomerID 0xCD ++#define EEPROM_Default_Version 0 ++ ++#define EEPROM_Default_externalPA_C9 0x00 ++#define EEPROM_Default_externalPA_CC 0xFF ++#define EEPROM_Default_internalPA_SP3T_C9 0xAA ++#define EEPROM_Default_internalPA_SP3T_CC 0xAF ++#define EEPROM_Default_internalPA_SPDT_C9 0xAA ++#ifdef CONFIG_PCI_HCI ++#define EEPROM_Default_internalPA_SPDT_CC 0xA0 ++#else ++#define EEPROM_Default_internalPA_SPDT_CC 0xFA ++#endif ++ ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_NCC 0xB ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_TOSHIBA 0x4 ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#define EEPROM_CID_QMI 0x0D ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define RTL8192_EEPROM_ID 0x8129 ++#define EEPROM_WAPI_SUPPORT 0x78 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER) ++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) ++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS) ++ ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0x28 // SE Vendor ID.A-B ++#define EEPROM_DID 0x2A // SE Device ID. C-D ++#define EEPROM_SVID 0x2C // SE Vendor ID.E-F ++#define EEPROM_SMID 0x2E // SE PCI Subsystem ID. 10-11 ++ ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++#define EEPROM_MAC_ADDR_MAC0_92D 0x55 ++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B ++//---------------------------------------------------------------- ++// 2.4G band Tx power index setting ++#define EEPROM_CCK_TX_PWR_INX_2G 0x61 ++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D ++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 ++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 ++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 ++ ++//5GL channel 32-64 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E ++ ++//5GM channel 100-140 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 ++ ++//5GH channel 149-165 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 ++ ++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels. ++#define EEPROM_IQK_DELTA 0xBC ++#define EEPROM_LCK_DELTA 0xBC ++#define EEPROM_XTAL_K 0xBD //[7:5] ++#define EEPROM_TSSI_A_5G 0xBE ++#define EEPROM_TSSI_B_5G 0xBF ++#define EEPROM_TSSI_AB_5G 0xC0 ++#define EEPROM_THERMAL_METER 0xC3 //[4:0] ++#define EEPROM_PATHDIV 0xC4 ++#define EEPROM_RF_OPT1 0xC4 ++#define EEPROM_RF_OPT2 0xC5 ++#define EEPROM_RF_OPT3 0xC6 ++#define EEPROM_RF_OPT4 0xC7 ++#define EEPROM_RF_OPT5 0xC8 ++#define EEPROM_RF_OPT6 0xC9 ++#define EEPROM_VERSION 0xCA ++#define EEPROM_CUSTOMER_ID 0xCB ++#define EEPROM_RF_OPT7 0xCC ++ ++#define EEPROM_WIDIPAIRING_ADDR 0xF0 ++#define EEPROM_WIDIPAIRING_KEY 0xF6 ++ ++#define EEPROM_DEF_PART_NO 0x3FD //Byte ++#define EEPROME_CHIP_VERSION_L 0x3FF ++#define EEPROME_CHIP_VERSION_H 0x3FE ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0xC // SE Vendor ID.A-B ++#define EEPROM_PID 0xE // SE Device ID. C-D ++#define EEPROM_ENDPOINT_SETTING 0x10 ++#define EEPROM_CHIRP_K 0x12 // Changed ++#define EEPROM_USB_PHY 0x13 // Changed ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++#define EEPROM_STRING 0x1F ++#define EEPROM_SUBCUSTOMER_ID 0x59 ++ ++#define EEPROM_MAC_ADDR_MAC0_92D 0x19 ++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B ++//---------------------------------------------------------------- ++// 2.4G band Tx power index setting ++#define EEPROM_CCK_TX_PWR_INX_2G 0x61 ++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D ++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 ++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 ++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 ++ ++//5GL channel 32-64 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E ++ ++//5GM channel 100-140 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 ++ ++//5GH channel 149-165 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 ++ ++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels. ++#define EEPROM_TEST_CHANNEL_PLAN 0xBB ++#define EEPROM_IQK_DELTA 0xBC ++#define EEPROM_LCK_DELTA 0xBC ++#define EEPROM_XTAL_K 0xBD //[7:5] ++#define EEPROM_TSSI_A_5G 0xBE ++#define EEPROM_TSSI_B_5G 0xBF ++#define EEPROM_TSSI_AB_5G 0xC0 ++#define EEPROM_THERMAL_METER 0xC3 //[4:0] ++#define EEPROM_RF_OPT1 0xC4 ++#define EEPROM_RF_OPT2 0xC5 ++#define EEPROM_RF_OPT3 0xC6 ++#define EEPROM_RF_OPT4 0xC7 ++#define EEPROM_RF_OPT5 0xC8 ++#define EEPROM_RF_OPT6 0xC9 ++#define EEPROM_VERSION 0xCA ++#define EEPROM_CUSTOMER_ID 0xCB ++#define EEPROM_RF_OPT7 0xCC ++ ++#define EEPROM_DEF_PART_NO 0x3FD //Byte ++#define EEPROME_CHIP_VERSION_L 0x3FF ++#define EEPROME_CHIP_VERSION_H 0x3FE ++ ++//------------------------------------------------------------- ++// EEPROM content definitions ++//------------------------------------------------------------- ++#define OS_LINK_SPEED_NORMAL_MASK BIT3 | BIT2 ++#define OS_LINK_SPEED_TEST_MASK BIT3 | BIT4 ++ ++#define BOARD_TYPE_NORMAL_MASK 0xE0 ++#define BOARD_TYPE_TEST_MASK 0xF ++ ++#define BT_COEXISTENCE_TEST BIT4 ++#define BT_COEXISTENCE_NORMAL BIT5 ++ ++#define BT_CO_SHIFT_TEST 4 ++#define BT_CO_SHIFT_NORMAL 5 ++ ++#define EP_NUMBER_MASK_TEST 0x30 //bit 4:5 0Eh ++#define EP_NUMBER_SHIFT_TEST 4 ++ ++#define USB_PHY_PARA_SIZE_TEST 6 ++#define USB_PHY_PARA_SIZE_NORMAL 4 ++ ++//------------------------------------------------------------- ++// EEPROM default value definitions ++//------------------------------------------------------------- ++// Use 0xABCD instead of 0x8192 for debug ++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00 ++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01 ++ ++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03 ++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04 ++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08 ++ ++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A ++#define EEPROM_DEF_VID_1 0x0B ++ ++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C ++#define EEPROM_DEF_PID_1 0x81 ++ ++ ++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E ++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E ++ ++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F ++ ++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10 ++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11 ++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12 ++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13 ++ ++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78 ++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79 ++ ++ ++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A ++ ++ ++#define EEPROM_USB_SN BIT(0) ++#define EEPROM_USB_REMOTE_WAKEUP BIT(1) ++#define EEPROM_USB_DEVICE_PWR BIT(2) ++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) ++ ++#if 0 ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++#define EEPROM_CID_DEFAULT 0x0 ++ ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++ ++#endif ++#endif ++ ++ ++/*=================================================================== ++===================================================================== ++Here the register defines are for 92C. When the define is as same with 92C, ++we will use the 92C's define for the consistency ++So the following defines for 92C is not entire!!!!!! ++===================================================================== ++=====================================================================*/ ++/* ++Based on Datasheet V33---090401 ++Register Summary ++Current IOREG MAP ++0x0000h ~ 0x00FFh System Configuration (256 Bytes) ++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) ++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) ++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) ++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) ++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) ++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) ++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) ++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) ++*/ ++ ++//---------------------------------------------------------------------------- ++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) ++//---------------------------------------------------------------------------- ++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload ++#define RCR_APP_MIC BIT30 // ++#define RCR_APP_ICV BIT29 // ++#define RCR_APP_PHYST_RXFF BIT28 // ++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN ++#define RCR_ENMBID BIT24 //Enable Multiple BssId. ++#define RCR_LSIGEN BIT23 ++#define RCR_MFBEN BIT22 ++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 ++#define RCR_AMF BIT13 //Accept management type frame ++#define RCR_ACF BIT12 //Accept control type frame ++#define RCR_ADF BIT11 //Accept data type frame ++#define RCR_AICV BIT9 //Accept ICV error packet ++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet ++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) ++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) ++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet ++#define RCR_APWRMGT BIT5 //Accept power management packet ++#define RCR_ADD3 BIT4 //Accept address 3 match packet ++#define RCR_AB BIT3 //Accept broadcast packet ++#define RCR_AM BIT2 //Accept multicast packet ++#define RCR_APM BIT1 //Accept physical match packet ++#define RCR_AAP BIT0 //Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ ++ ++ ++//============================================================================ ++// 8192c USB specific Regsiter Offset and Content definition, ++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver ++//============================================================================ ++//#define APS_FSMCO 0x0004 same with 92Ce ++#define RSV_CTRL 0x001C ++#define RD_CTRL 0x0524 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++#define REG_USB_VID 0xFE60 ++#define REG_USB_PID 0xFE62 ++#define REG_USB_OPTIONAL 0xFE64 ++#define REG_USB_CHIRP_K 0xFE65 ++#define REG_USB_PHY 0xFE66 ++#define REG_USB_MAC_ADDR 0xFE70 ++ ++#define REG_USB_HRPWM 0xFE58 ++#define REG_USB_HCPWM 0xFE57 ++ ++#define InvalidBBRFValue 0x12345678 ++ ++//============================================================================ ++// 8192C Regsiter Bit and Content definition ++//============================================================================ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SPS0_CTRL ++#define SW18_FPWM BIT(3) ++ ++ ++//2 SYS_ISO_CTRL ++#define ISO_MD2PP BIT(0) ++#define ISO_UA2USB BIT(1) ++#define ISO_UD2CORE BIT(2) ++#define ISO_PA2PCIE BIT(3) ++#define ISO_PD2CORE BIT(4) ++#define ISO_IP2MAC BIT(5) ++#define ISO_DIOP BIT(6) ++#define ISO_DIOE BIT(7) ++#define ISO_EB2CORE BIT(8) ++#define ISO_DIOR BIT(9) ++ ++#define PWC_EV25V BIT(14) ++#define PWC_EV12V BIT(15) ++ ++ ++//2 SYS_FUNC_EN ++#define FEN_BBRSTB BIT(0) ++#define FEN_BB_GLB_RSTn BIT(1) ++#define FEN_USBA BIT(2) ++#define FEN_UPLL BIT(3) ++#define FEN_USBD BIT(4) ++#define FEN_DIO_PCIE BIT(5) ++#define FEN_PCIEA BIT(6) ++#define FEN_PPLL BIT(7) ++#define FEN_PCIED BIT(8) ++#define FEN_DIOE BIT(9) ++#define FEN_CPUEN BIT(10) ++#define FEN_DCORE BIT(11) ++#define FEN_ELDR BIT(12) ++#define FEN_DIO_RF BIT(13) ++#define FEN_HWPDN BIT(14) ++#define FEN_MREGEN BIT(15) ++ ++//2 APS_FSMCO ++#define PFM_LDALL BIT(0) ++#define PFM_ALDN BIT(1) ++#define PFM_LDKP BIT(2) ++#define PFM_WOWL BIT(3) ++#define EnPDN BIT(4) ++#define PDN_PL BIT(5) ++#define APFM_ONMAC BIT(8) ++#define APFM_OFF BIT(9) ++#define APFM_RSM BIT(10) ++#define AFSM_HSUS BIT(11) ++#define AFSM_PCIE BIT(12) ++#define APDM_MAC BIT(13) ++#define APDM_HOST BIT(14) ++#define APDM_HPDN BIT(15) ++#define RDY_MACON BIT(16) ++#define SUS_HOST BIT(17) ++#define ROP_ALD BIT(20) ++#define ROP_PWR BIT(21) ++#define ROP_SPS BIT(22) ++#define SOP_MRST BIT(25) ++#define SOP_FUSE BIT(26) ++#define SOP_ABG BIT(27) ++#define SOP_AMB BIT(28) ++#define SOP_RCK BIT(29) ++#define SOP_A8M BIT(30) ++#define XOP_BTCK BIT(31) ++ ++//2 SYS_CLKR ++#define ANAD16V_EN BIT(0) ++#define ANA8M BIT(1) ++#define MACSLP BIT(4) ++#define LOADER_CLK_EN BIT(5) ++#define _80M_SSC_DIS BIT(7) ++#define _80M_SSC_EN_HO BIT(8) ++#define PHY_SSC_RSTB BIT(9) ++#define SEC_CLK_EN BIT(10) ++#define MAC_CLK_EN BIT(11) ++#define SYS_CLK_EN BIT(12) ++#define RING_CLK_EN BIT(13) ++ ++ ++//2 9346CR ++ ++#define BOOT_FROM_EEPROM BIT(4) ++#define EEPROM_EN BIT(5) ++ ++ ++//2 AFE_MISC ++#define AFE_BGEN BIT(0) ++#define AFE_MBEN BIT(1) ++#define MAC_ID_EN BIT(7) ++ ++ ++//2 SPS0_CTRL ++ ++ ++//2 SPS_OCP_CFG ++ ++ ++//2 RSV_CTRL ++#define WLOCK_ALL BIT(0) ++#define WLOCK_00 BIT(1) ++#define WLOCK_04 BIT(2) ++#define WLOCK_08 BIT(3) ++#define WLOCK_40 BIT(4) ++#define R_DIS_PRST_0 BIT(5) ++#define R_DIS_PRST_1 BIT(6) ++#define LOCK_ALL_EN BIT(7) ++ ++//2 RF_CTRL ++#define RF_EN BIT(0) ++#define RF_RSTB BIT(1) ++#define RF_SDMRSTB BIT(2) ++ ++ ++ ++//2 LDOA15_CTRL ++#define LDA15_EN BIT(0) ++#define LDA15_STBY BIT(1) ++#define LDA15_OBUF BIT(2) ++#define LDA15_REG_VOS BIT(3) ++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) ++ ++ ++ ++//2 LDOV12D_CTRL ++#define LDV12_EN BIT(0) ++#define LDV12_SDBY BIT(1) ++#define LPLDO_HSM BIT(2) ++#define LPLDO_LSM_DIS BIT(3) ++#define _LDV12_VADJ(x) (((x) & 0xF) << 4) ++ ++ ++//2 AFE_XTAL_CTRL ++#define XTAL_EN BIT(0) ++#define XTAL_BSEL BIT(1) ++#define _XTAL_BOSC(x) (((x) & 0x3) << 2) ++#define _XTAL_CADJ(x) (((x) & 0xF) << 4) ++#define XTAL_GATE_USB BIT(8) ++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) ++#define XTAL_GATE_AFE BIT(11) ++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) ++#define XTAL_RF_GATE BIT(14) ++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) ++#define XTAL_GATE_DIG BIT(17) ++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) ++#define XTAL_BT_GATE BIT(20) ++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) ++#define _XTAL_GPIO(x) (((x) & 0x7) << 23) ++ ++ ++#define CKDLY_AFE BIT(26) ++#define CKDLY_USB BIT(27) ++#define CKDLY_DIG BIT(28) ++#define CKDLY_BT BIT(29) ++ ++ ++//2 AFE_PLL_CTRL ++#define APLL_EN BIT(0) ++#define APLL_320_EN BIT(1) ++#define APLL_FREF_SEL BIT(2) ++#define APLL_EDGE_SEL BIT(3) ++#define APLL_WDOGB BIT(4) ++#define APLL_LPFEN BIT(5) ++ ++#define APLL_REF_CLK_13MHZ 0x1 ++#define APLL_REF_CLK_19_2MHZ 0x2 ++#define APLL_REF_CLK_20MHZ 0x3 ++#define APLL_REF_CLK_25MHZ 0x4 ++#define APLL_REF_CLK_26MHZ 0x5 ++#define APLL_REF_CLK_38_4MHZ 0x6 ++#define APLL_REF_CLK_40MHZ 0x7 ++ ++#define APLL_320EN BIT(14) ++#define APLL_80EN BIT(15) ++#define APLL_1MEN BIT(24) ++ ++ ++//2 EFUSE_CTRL ++#define ALD_EN BIT(18) ++#define EF_PD BIT(19) ++#define EF_FLAG BIT(31) ++ ++//2 EFUSE_TEST ++#define EF_TRPT BIT(7) ++#define LDOE25_EN BIT(31) ++ ++//2 PWR_DATA ++ ++//2 CAL_TIMER ++ ++//2 ACLK_MON ++#define RSM_EN BIT(0) ++#define Timer_EN BIT(4) ++ ++ ++//2 GPIO_MUXCFG ++#define TRSW0EN BIT(2) ++#define TRSW1EN BIT(3) ++#define EROM_EN BIT(4) ++#define EnBT BIT(5) ++#define EnUart BIT(8) ++#define Uart_910 BIT(9) ++#define EnPMAC BIT(10) ++#define SIC_SWRST BIT(11) ++#define EnSIC BIT(12) ++#define SIC_23 BIT(13) ++#define EnHDP BIT(14) ++#define SIC_LBK BIT(15) ++ ++//2 GPIO_PIN_CTRL ++ ++ ++ ++//2 GPIO_INTM ++ ++//2 LEDCFG ++#define LED0PL BIT(4) ++#define LED1PL BIT(12) ++#define LED0DIS BIT(7) ++ ++#define SECCAM_CLR BIT(30) ++ ++//2 FSIMR ++ ++//2 FSISR ++ ++ ++//2 8051FWDL ++//2 MCUFWDL ++#define MCUFWDL_EN BIT(0) ++#define MCUFWDL_RDY BIT(1) ++#define FWDL_ChkSum_rpt BIT(2) ++#define MACINI_RDY BIT(3) ++#define BBINI_RDY BIT(4) ++#define RFINI_RDY BIT(5) ++#define WINTINI_RDY BIT(6) ++#define MAC1_WINTINI_RDY BIT(11)// 0X81 BIT3 ++#define CPRST BIT(23) ++ ++ ++ ++ ++//2 REG_SYS_CFG ++#define XCLK_VLD BIT(0) ++#define ACLK_VLD BIT(1) ++#define UCLK_VLD BIT(2) ++#define PCLK_VLD BIT(3) ++#define PCIRSTB BIT(4) ++#define V15_VLD BIT(5) ++#define TRP_B15V_EN BIT(7) ++#define SIC_IDLE BIT(8) ++#define BD_MAC2 BIT(9) ++#define BD_MAC1 BIT(10) ++#define IC_MACPHY_MODE BIT(11) ++#define PAD_HWPD_IDN BIT(22) ++#define TRP_VAUX_EN BIT(23) ++#define TRP_BT_EN BIT(24) ++#define BD_PKG_SEL BIT(25) ++#define BD_HCI_SEL BIT(26) ++#define TYPE_ID BIT(27) ++ ++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 ++#define CHIP_VER_RTL_SHIFT 12 ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++ ++//2 Function Enable Registers ++//2 CR ++ ++#define REG_LBMODE (REG_CR + 3) ++ ++ ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++ ++// Network type ++#define _NETTYPE(x) (((x) & 0x3) << 16) ++#define MASK_NETTYPE 0x30000 ++#define NT_NO_LINK 0x0 ++#define NT_LINK_AD_HOC 0x1 ++#define NT_LINK_AP 0x2 ++#define NT_AS_AP 0x3 ++ ++#define _LBMODE(x) (((x) & 0xF) << 24) ++#define MASK_LBMODE 0xF000000 ++#define LOOPBACK_NORMAL 0x0 ++#define LOOPBACK_IMMEDIATELY 0xB ++#define LOOPBACK_MAC_DELAY 0x3 ++#define LOOPBACK_PHY 0x1 ++#define LOOPBACK_DMA 0x7 ++ ++ ++//2 PBP - Page Size Register ++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) ++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) ++#define _PSRX_MASK 0xF ++#define _PSTX_MASK 0xF0 ++#define _PSRX(x) (x) ++#define _PSTX(x) ((x) << 4) ++ ++#define PBP_64 0x0 ++#define PBP_128 0x1 ++#define PBP_256 0x2 ++#define PBP_512 0x3 ++#define PBP_1024 0x4 ++ ++ ++//2 TX/RXDMA ++#define RXDMA_ARBBW_EN BIT(0) ++#define RXSHFT_EN BIT(1) ++#define RXDMA_AGG_EN BIT(2) ++#define QS_VO_QUEUE BIT(8) ++#define QS_VI_QUEUE BIT(9) ++#define QS_BE_QUEUE BIT(10) ++#define QS_BK_QUEUE BIT(11) ++#define QS_MANAGER_QUEUE BIT(12) ++#define QS_HIGH_QUEUE BIT(13) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++// For normal driver, 0x10C ++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) ++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) ++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) ++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) ++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++ ++ ++//2 TRXFF_BNDY ++ ++ ++//2 LLT_INIT ++#define _LLT_NO_ACTIVE 0x0 ++#define _LLT_WRITE_ACCESS 0x1 ++#define _LLT_READ_ACCESS 0x2 ++ ++#define _LLT_INIT_DATA(x) ((x) & 0xFF) ++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) ++#define _LLT_OP(x) (((x) & 0x3) << 30) ++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) ++ ++ ++//2 BB_ACCESS_CTRL ++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) ++#define BB_WRITE_EN BIT(30) ++#define BB_READ_EN BIT(31) ++//#define BB_ADDR_MASK 0xFFF ++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK) ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++//2 RQPN ++#define _HPQ(x) ((x) & 0xFF) ++#define _LPQ(x) (((x) & 0xFF) << 8) ++#define _PUBQ(x) (((x) & 0xFF) << 16) ++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register ++ ++ ++#define HPQ_PUBLIC_DIS BIT(24) ++#define LPQ_PUBLIC_DIS BIT(25) ++#define LD_RQPN BIT(31) ++ ++ ++//2 TDECTRL ++#define BCN_VALID BIT(16) ++#define BCN_HEAD(x) (((x) & 0xFF) << 8) ++#define BCN_HEAD_MASK 0xFF00 ++ ++//2 TDECTL ++#define BLK_DESC_NUM_SHIFT 4 ++#define BLK_DESC_NUM_MASK 0xF ++ ++ ++//2 TXDMA_OFFSET_CHK ++#define DROP_DATA_EN BIT(9) ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//2 FWHW_TXQ_CTRL ++#define EN_AMPDU_RTY_NEW BIT(7) ++ ++//2 INIRTSMCS_SEL ++#define _INIRTSMCS_SEL(x) ((x) & 0x3F) ++ ++ ++//2 SPEC SIFS ++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) ++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) ++ ++ ++//2 RRSR ++ ++#define RATE_REG_BITMAP_ALL 0xFFFFF ++ ++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) ++ ++#define _RRSR_RSC(x) (((x) & 0x3) << 21) ++#define RRSR_RSC_RESERVED 0x0 ++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 ++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 ++#define RRSR_RSC_DUPLICATE_MODE 0x3 ++ ++ ++//2 ARFR ++#define USE_SHORT_G1 BIT(20) ++ ++//2 AGGLEN_LMT_L ++#define _AGGLMT_MCS0(x) ((x) & 0xF) ++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) ++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) ++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) ++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) ++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) ++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) ++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) ++ ++ ++//2 RL ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ ++ ++//2 DARFRC ++#define _DARF_RC1(x) ((x) & 0x1F) ++#define _DARF_RC2(x) (((x) & 0x1F) << 8) ++#define _DARF_RC3(x) (((x) & 0x1F) << 16) ++#define _DARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (DARFRC + 4) ++#define _DARF_RC5(x) ((x) & 0x1F) ++#define _DARF_RC6(x) (((x) & 0x1F) << 8) ++#define _DARF_RC7(x) (((x) & 0x1F) << 16) ++#define _DARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++//2 RARFRC ++#define _RARF_RC1(x) ((x) & 0x1F) ++#define _RARF_RC2(x) (((x) & 0x1F) << 8) ++#define _RARF_RC3(x) (((x) & 0x1F) << 16) ++#define _RARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (RARFRC + 4) ++#define _RARF_RC5(x) ((x) & 0x1F) ++#define _RARF_RC6(x) (((x) & 0x1F) << 8) ++#define _RARF_RC7(x) (((x) & 0x1F) << 16) ++#define _RARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++ ++ ++//2 EDCA setting ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ ++ ++//2 EDCA_VO_PARAM ++#define _AIFS(x) (x) ++#define _ECW_MAX_MIN(x) ((x) << 8) ++#define _TXOP_LIMIT(x) ((x) << 16) ++ ++ ++#define _BCNIFS(x) ((x) & 0xFF) ++#define _BCNECW(x) (((x) & 0xF))<< 8) ++ ++ ++#define _LRL(x) ((x) & 0x3F) ++#define _SRL(x) (((x) & 0x3F) << 8) ++ ++ ++//2 SIFS_CCK ++#define _SIFS_CCK_CTX(x) ((x) & 0xFF) ++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 SIFS_OFDM ++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) ++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 TBTT PROHIBIT ++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) ++ ++ ++//2 REG_RD_CTRL ++#define DIS_EDCA_CNT_DWN BIT(11) ++ ++ ++//2 BCN_CTRL ++#define EN_MBSSID BIT(1) ++#define EN_TXBCN_RPT BIT(2) ++#define EN_BCN_FUNCTION BIT(3) ++#define DIS_TSF_UPDATE BIT(3) ++ ++// The same function but different bit field. ++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) ++#define DIS_TSF_UDT0_TEST_CHIP BIT(5) ++ ++//2 ACMHWCTRL ++#define AcmHw_HwEn BIT(0) ++#define AcmHw_BeqEn BIT(1) ++#define AcmHw_ViqEn BIT(2) ++#define AcmHw_VoqEn BIT(3) ++#define AcmHw_BeqStatus BIT(4) ++#define AcmHw_ViqStatus BIT(5) ++#define AcmHw_VoqStatus BIT(6) ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++ ++//2 APSD_CTRL ++#define APSDOFF BIT(6) ++#define APSDOFF_STATUS BIT(7) ++ ++ ++//2 BWOPMODE ++#define BW_20MHZ BIT(2) ++//#define BW_OPMODE_20MHZ BIT(2) // For compability ++ ++ ++#define RATE_BITMAP_ALL 0xFFFFF ++ ++// Only use CCK 1M rate for ACK ++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 ++#define RATE_RRSR_WITHOUT_CCK 0xFFFF0 ++ ++//2 TCR ++#define TSFRST BIT(0) ++#define DIS_GCLK BIT(1) ++#define PAD_SEL BIT(2) ++#define PWR_ST BIT(6) ++#define PWRBIT_OW_EN BIT(7) ++#define ACRC BIT(8) ++#define CFENDFORM BIT(9) ++#define ICV BIT(10) ++ ++ ++ ++//2 RCR ++#define AAP BIT(0) ++#define APM BIT(1) ++#define AM BIT(2) ++#define AB BIT(3) ++#define ADD3 BIT(4) ++#define APWRMGT BIT(5) ++#define CBSSID BIT(6) ++#define CBSSID_BCN BIT(7) ++#define ACRC32 BIT(8) ++#define AICV BIT(9) ++#define ADF BIT(11) ++#define ACF BIT(12) ++#define AMF BIT(13) ++#define HTC_LOC_CTRL BIT(14) ++#define UC_DATA_EN BIT(16) ++#define BM_DATA_EN BIT(17) ++#define MFBEN BIT(22) ++#define LSIGEN BIT(23) ++#define EnMBID BIT(24) ++#define APP_BASSN BIT(27) ++#define APP_PHYSTS BIT(28) ++#define APP_ICV BIT(29) ++#define APP_MIC BIT(30) ++#define APP_FCS BIT(31) ++ ++//2 RX_PKT_LIMIT ++ ++//2 RX_DLK_TIME ++ ++//2 MBIDCAMCFG ++ ++ ++ ++//2 AMPDU_MIN_SPACE ++#define _MIN_SPACE(x) ((x) & 0x7) ++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) ++ ++ ++//2 RXERR_RPT ++#define RXERR_TYPE_OFDM_PPDU 0 ++#define RXERR_TYPE_OFDM_FALSE_ALARM 1 ++#define RXERR_TYPE_OFDM_MPDU_OK 2 ++#define RXERR_TYPE_OFDM_MPDU_FAIL 3 ++#define RXERR_TYPE_CCK_PPDU 4 ++#define RXERR_TYPE_CCK_FALSE_ALARM 5 ++#define RXERR_TYPE_CCK_MPDU_OK 6 ++#define RXERR_TYPE_CCK_MPDU_FAIL 7 ++#define RXERR_TYPE_HT_PPDU 8 ++#define RXERR_TYPE_HT_FALSE_ALARM 9 ++#define RXERR_TYPE_HT_MPDU_TOTAL 10 ++#define RXERR_TYPE_HT_MPDU_OK 11 ++#define RXERR_TYPE_HT_MPDU_FAIL 12 ++#define RXERR_TYPE_RX_FULL_DROP 15 ++ ++#define RXERR_COUNTER_MASK 0xFFFFF ++#define RXERR_RPT_RST BIT(27) ++#define _RXERR_RPT_SEL(type) ((type) << 28) ++ ++ ++//2 SECCFG ++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key ++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption ++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption ++#define SCR_SKByA2 BIT(4) //Search kEY BY A2 ++#define SCR_NoSKMC BIT(5) //No Key Search Multicast ++#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key ++#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key ++ ++//vivi added for new cam search flow, 20091028 ++#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW ++#define SCR_TxUseBroadcastDK BIT6 //Force Tx Use Broadcast Default Key ++#define SCR_RxUseBroadcastDK BIT7 //Force Rx Use Broadcast Default Key ++#endif ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++ ++//2 USB Information (0xFE17) ++#define USB_IS_HIGH_SPEED 0 ++#define USB_IS_FULL_SPEED 1 ++#define USB_SPEED_MASK BIT(5) ++ ++#define USB_NORMAL_SIE_EP_MASK 0xF ++#define USB_NORMAL_SIE_EP_SHIFT 4 ++ ++#define USB_TEST_EP_MASK 0x30 ++#define USB_TEST_EP_SHIFT 4 ++ ++//2 Special Option ++#define USB_AGG_EN BIT(3) ++ ++ ++//2REG_C2HEVT_CLEAR ++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message ++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. ++ ++//2 8192D PartNo. ++#define PARTNO_92D_NIC (BIT7|BIT6) ++#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) ++#define PARTNO_SINGLE_BAND_VS BIT3 ++#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 ++#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) ++#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) ++//======================================================== ++// General definitions ++//======================================================== ++ ++#define MAC_ADDR_LEN 6 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 ++ ++#define POLLING_LLT_THRESHOLD 20 ++#define POLLING_READY_TIMEOUT_COUNT 1000 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++// GPIO BIT ++#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 ++ ++ ++#include "basic_types.h" ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_xmit.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_xmit.h +new file mode 100644 +index 00000000..54f0511c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8192d_xmit.h +@@ -0,0 +1,181 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192D_XMIT_H_ ++#define _RTL8192D_XMIT_H_ ++ ++// ++//defined for TX DESC Operation ++// ++ ++#define MAX_TID (15) ++ ++//OFFSET 0 ++#define OFFSET_SZ 0 ++#define OFFSET_SHT 16 ++#define BMC BIT(24) ++#define LSG BIT(26) ++#define FSG BIT(27) ++#define OWN BIT(31) ++ ++ ++//OFFSET 4 ++#define PKT_OFFSET_SZ 0 ++#define BK BIT(6) ++#define QSEL_SHT 8 ++#define Rate_ID_SHT 16 ++#define NAVUSEHDR BIT(20) ++#define PKT_OFFSET_SHT 26 ++#define HWPC BIT(31) ++ ++//OFFSET 8 ++#define AGG_EN BIT(29) ++ ++//OFFSET 12 ++#define SEQ_SHT 16 ++ ++//OFFSET 16 ++#define QoS BIT(6) ++#define HW_SEQ_EN BIT(7) ++#define USERATE BIT(8) ++#define DISDATAFB BIT(10) ++#define DATA_SHORT BIT(24) ++#define DATA_BW BIT(25) ++ ++//OFFSET 20 ++#define SGI BIT(6) ++ ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x2//0x01 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x5//0x4 ++#define QSLT_VO 0x7//0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++//Because we open EM for normal case, we just always insert 2*8 bytes.by wl ++#define USB_92D_DUMMY_OFFSET 2 ++#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ) ++#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH) ++ ++//For 92D early mode ++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) ++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) ++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) ++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) ++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) ++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) ++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) ++ ++/* Copy from rtl8192c */ ++struct txrpt_ccx_8192d { ++ /* offset 0 */ ++ u8 retry_cnt:6; ++ u8 rsvd_0:2; ++ ++ /* offset 1 */ ++ u8 rts_retry_cnt:6; ++ u8 rsvd_1:2; ++ ++ /* offset 2 */ ++ u8 ccx_qtime0; ++ u8 ccx_qtime1; ++ ++ /* offset 4 */ ++ u8 missed_pkt_num:5; ++ u8 rsvd_4:3; ++ ++ /* offset 5 */ ++ u8 mac_id:5; ++ u8 des1_fragssn:3; ++ ++ /* offset 6 */ ++ u8 rpt_pkt_num:5; ++ u8 pkt_drop:1; ++ u8 lifetime_over:1; ++ u8 retry_over:1; ++ ++ /* offset 7*/ ++ u8 edca_tx_queue:4; ++ u8 rsvd_7:1; ++ u8 bmc:1; ++ u8 pkt_ok:1; ++ u8 int_ccx:1; ++}; ++ ++#define txrpt_ccx_qtime_8192d(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) ++ ++#ifdef CONFIG_XMIT_ACK ++void dump_txrpt_ccx_8192d(void *buf); ++void handle_txrpt_ccx_8192d(_adapter *adapter, void *buf); ++#else ++#define dump_txrpt_ccx_8192d(buf) do {} while(0) ++#define handle_txrpt_ccx_8192d(adapter, buf) do {} while(0) ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++#define MAX_TX_AGG_PACKET_NUMBER 0xFF ++#endif ++ ++s32 rtl8192du_init_xmit_priv(_adapter * padapter); ++ ++void rtl8192du_free_xmit_priv(_adapter * padapter); ++ ++void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++ ++s32 rtl8192du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++s32 rtl8192du_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192du_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192du_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8192de_init_xmit_priv(_adapter * padapter); ++void rtl8192de_free_xmit_priv(_adapter * padapter); ++ ++s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf); ++struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring); ++ ++void rtl8192de_xmitframe_resume(_adapter *padapter); ++ ++s32 rtl8192de_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192de_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_bt-coexist.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_bt-coexist.h +new file mode 100644 +index 00000000..78d64b8d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_bt-coexist.h +@@ -0,0 +1,1816 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_BT_COEXIST_H__ ++#define __RTL8723A_BT_COEXIST_H__ ++ ++#include ++#include "../hal/OUTSRC/odm_precomp.h" ++ ++ ++#define __BT_C__ 1 ++#define __BT_HANDLEPACKET_C__ 1 ++#define __BT_HCI_C__ 1 ++#define __HALBTC87231ANT_C__ 1 ++#define __HALBTC87232ANT_C__ 1 ++#define __HALBTC8723_C__ 1 ++#define __HALBTCCSR1ANT_C__ 1 ++#define __HALBTCCSR2ANT_C__ 1 ++#define __HALBTCOEXIST_C__ 1 ++#define __HALBT_C__ 1 ++ ++#ifdef __BT_C__ // COMMON/BT.h ++ ++// HEADER/PlatformDef.h ++typedef enum _RT_MEDIA_STATUS { ++ RT_MEDIA_DISCONNECT = 0, ++ RT_MEDIA_CONNECT = 1 ++} RT_MEDIA_STATUS; ++ ++// ===== Below this line is sync from SD7 driver COMMON/BT.h ===== ++ ++#define BT_TMP_BUF_SIZE 100 ++ ++void BT_SignalCompensation(PADAPTER padapter, u8 *rssi_wifi, u8 *rssi_bt); ++void BT_WifiScanNotify(PADAPTER padapter, u8 scanType); ++void BT_WifiAssociateNotify(PADAPTER padapter, u8 action); ++void BT_WifiMediaStatusNotify(PADAPTER padapter, RT_MEDIA_STATUS mstatus); ++void BT_SpecialPacketNotify(PADAPTER padapter); ++void BT_HaltProcess(PADAPTER padapter); ++void BT_LpsLeave(PADAPTER padapter); ++ ++ ++#define BT_HsConnectionEstablished(Adapter) _FALSE ++// ===== End of sync from SD7 driver COMMON/BT.h ===== ++#endif // __BT_C__ ++ ++#ifdef __BT_HCI_C__ // COMMON/bt_hci.h ++ ++// HEADER/SecurityType.h ++#define TKIP_ENC_KEY_POS 32 //(KEK_LEN+KEK_LEN) ++#define MAXRSNIELEN 256 ++ ++// HEADER/QoSType.h ++#if 0 ++// ++// BSS QOS data. ++// Ref: BssDscr in 8185 code. [def. in BssDscr.h] ++// ++typedef struct _BSS_QOS ++{ ++ // Part 0. Ref. 8185 QoS code (From Emily) ++ QOS_MODE bdQoSMode; ++ u8 bdWMMIEBuf[MAX_WMMELE_LENGTH]; ++ OCTET_STRING bdWMMIE; ++ ++ QOS_ELE_SUBTYPE EleSubType; ++ ++ // Part 2. EDCA Parameter (perAC) ++ u8 *pWMMInfoEle; ++ u8 *pWMMParamEle; ++ ++ // QBSS Load. ++ u8 QBssLoad[QBSS_LOAD_SIZE]; ++ u8 bQBssLoadValid; ++} BSS_QOS, *PBSS_QOS; ++#endif ++ ++// COMMON/Protocol802_11.h ++//---------------------------------------------------------------------------- ++// 802.11 Management frame Status Code field ++//---------------------------------------------------------------------------- ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++} OCTET_STRING, *POCTET_STRING; ++ ++ ++//====================================================================================== ++// AES_CCMP specific ++//====================================================================================== ++enum ++{ ++ AESCCMP_BLK_SIZE = 16, // # octets in an AES block ++ AESCCMP_MAX_PACKET = 4*512, // largest packet size ++ AESCCMP_N_RESERVED = 0, // reserved nonce octet value ++ AESCCMP_A_DATA = 0x40, // the Adata bit in the flags ++ AESCCMP_M_SHIFT = 3, // how much to shift the 3-bit M field ++ AESCCMP_L_SHIFT = 0, // how much to shift the 3-bit L field ++ AESCCMP_L_SIZE = 2, // size of the l(m) length field (in octets) ++ AESCCMP_OFFSET_SC = 22, ++ AESCCMP_OFFSET_DURATION = 4, ++ AESCCMP_OFFSET_A2 = 10, ++ AESCCMP_OFFSET_A4 = 24, ++ AESCCMP_QC_TID_MASK = 0x0f, ++ AESCCMP_BLK_SIZE_TOTAL = 16*16, // Added by Annie for CKIP AES MIC BSOD, 2006-08-17. ++ // 16*8 < 4*60 Resove to 16*16 ++}; ++ ++// ++// Key Length ++// ++#define PMK_LEN 32 ++#define PTK_LEN_TKIP 64 ++#define GTK_LEN 32 ++#define KEY_NONCE_LEN 32 ++ ++ ++// COMMON/Dot11d.h ++typedef struct _CHNL_TXPOWER_TRIPLE ++{ ++ u8 FirstChnl; ++ u8 NumChnls; ++ s8 MaxTxPowerInDbm; ++} CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; ++ ++ ++// ===== Below this line is sync from SD7 driver COMMON/bt_hci.h ===== ++#define BT_THREAD 0 ++#if(BT_THREAD == 1) ++#define SENDTXMEHTOD 2 ++#else ++#define SENDTXMEHTOD 1 // 0=workitem, 1= SendDirectily, 2=thread ++#endif ++ ++//============================================= ++// The following is for BT 3.0 + HS HCI COMMAND ERRORS CODES ++//============================================= ++ ++#define Max80211PALPDUSize 1492 ++#define Max80211AMPASSOCLen 672 ++#define MinGUserPrio 4 ++#define MaxGUserPrio 7 ++#define BEUserPrio0 0 ++#define BEUserPrio1 3 ++#define Max80211BeaconPeriod 2000 ++#define ShortRangeModePowerMax 4 ++ ++#define BT_Default_Chnl 10 ++#define ACLDataHeaderLen 4 ++ ++#define BTTotalDataBlockNum 0x100 ++#define BTLocalBufNum 0x200 ++#define BTMaxDataBlockLen 0x800 ++#define BTTOTALBANDWIDTH 0x7530 ++#define BTMAXBANDGUBANDWIDTH 0x4e20 ++#define TmpLocalBufSize 0x100 ++#define BTSynDataPacketLength 0xff ++//============================================= ++ ++#define BTMaxAuthCount 5 ++#define BTMaxAsocCount 5 ++ ++#define MAX_LOGICAL_LINK_NUM 2 //temporarily define ++#define MAX_BT_ASOC_ENTRY_NUM 2 //temporarily define ++ ++#define INVALID_PL_HANDLE 0xff ++#define INVALID_ENTRY_NUM 0xff ++//============================================= ++ ++#define CAM_BT_START_INDEX (HALF_CAM_ENTRY - 4) // MAX_BT_ASOC_ENTRY_NUM : 4 !!! ++#define BT_HWCAM_STAR CAM_BT_START_INDEX // We used HALF_CAM_ENTRY ~ HALF_CAM_ENTRY -MAX_BT_ASOC_ENTRY_NUM ++ ++typedef enum _HCI_STATUS ++{ ++ HCI_STATUS_SUCCESS =0x00, //Success ++ HCI_STATUS_UNKNOW_HCI_CMD =0x01, //Unknown HCI Command ++ HCI_STATUS_UNKNOW_CONNECT_ID =0X02, //Unknown Connection Identifier ++ HCI_STATUS_HW_FAIL =0X03, //Hardware Failure ++ HCI_STATUS_PAGE_TIMEOUT =0X04, //Page Timeout ++ HCI_STATUS_AUTH_FAIL =0X05, //Authentication Failure ++ HCI_STATUS_PIN_OR_KEY_MISSING =0X06, //PIN or Key Missing ++ HCI_STATUS_MEM_CAP_EXCEED =0X07, //Memory Capacity Exceeded ++ HCI_STATUS_CONNECT_TIMEOUT =0X08, //Connection Timeout ++ HCI_STATUS_CONNECT_LIMIT =0X09, //Connection Limit Exceeded ++ HCI_STATUS_SYN_CONNECT_LIMIT =0X0a, //Synchronous Connection Limit To A Device Exceeded ++ HCI_STATUS_ACL_CONNECT_EXISTS =0X0b, //ACL Connection Already Exists ++ HCI_STATUS_CMD_DISALLOW =0X0c, //Command Disallowed ++ HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE =0X0d, //Connection Rejected due to Limited Resources ++ HCI_STATUS_CONNECT_RJT_SEC_REASON =0X0e, //Connection Rejected Due To Security Reasons ++ HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR =0X0f, //Connection Rejected due to Unacceptable BD_ADDR ++ HCI_STATUS_CONNECT_ACCEPT_TIMEOUT =0X10, //Connection Accept Timeout Exceeded ++ HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE =0X11, //Unsupported Feature or Parameter Value ++ HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE =0X12, //Invalid HCI Command Parameters ++ HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT =0X13, //Remote User Terminated Connection ++ HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE =0X14, //Remote Device Terminated Connection due to Low Resources ++ HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF =0X15, //Remote Device Terminated Connection due to Power Off ++ HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST =0X16, //Connection Terminated By Local Host ++ HCI_STATUS_REPEATE_ATTEMPT =0X17, //Repeated Attempts ++ HCI_STATUS_PAIR_NOT_ALLOW =0X18, //Pairing Not Allowed ++ HCI_STATUS_UNKNOW_LMP_PDU =0X19, //Unknown LMP PDU ++ HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE =0X1a, //Unsupported Remote Feature / Unsupported LMP Feature ++ HCI_STATUS_SOC_OFFSET_REJECT =0X1b, //SCO Offset Rejected ++ HCI_STATUS_SOC_INTERVAL_REJECT =0X1c, //SCO Interval Rejected ++ HCI_STATUS_SOC_AIR_MODE_REJECT =0X1d,//SCO Air Mode Rejected ++ HCI_STATUS_INVALID_LMP_PARA =0X1e, //Invalid LMP Parameters ++ HCI_STATUS_UNSPECIFIC_ERROR =0X1f, //Unspecified Error ++ HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE =0X20, //Unsupported LMP Parameter Value ++ HCI_STATUS_ROLE_CHANGE_NOT_ALLOW =0X21, //Role Change Not Allowed ++ HCI_STATUS_LMP_RESPONSE_TIMEOUT =0X22, //LMP Response Timeout ++ HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION =0X23, //LMP Error Transaction Collision ++ HCI_STATUS_LMP_PDU_NOT_ALLOW =0X24, //LMP PDU Not Allowed ++ HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW =0X25, //Encryption Mode Not Acceptable ++ HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE =0X26, //Link Key Can Not be Changed ++ HCI_STATUS_REQUEST_QOS_NOT_SUPPORT =0X27, //Requested QoS Not Supported ++ HCI_STATUS_INSTANT_PASSED =0X28, //Instant Passed ++ HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT =0X29, //Pairing With Unit Key Not Supported ++ HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION =0X2a, //Different Transaction Collision ++ HCI_STATUS_RESERVE_1 =0X2b, //Reserved ++ HCI_STATUS_QOS_UNACCEPT_PARA =0X2c, //QoS Unacceptable Parameter ++ HCI_STATUS_QOS_REJECT =0X2d, //QoS Rejected ++ HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT =0X2e, //Channel Classification Not Supported ++ HCI_STATUS_INSUFFICIENT_SECURITY =0X2f, //Insufficient Security ++ HCI_STATUS_PARA_OUT_OF_RANGE =0x30, //Parameter Out Of Mandatory Range ++ HCI_STATUS_RESERVE_2 =0X31, //Reserved ++ HCI_STATUS_ROLE_SWITCH_PENDING =0X32, //Role Switch Pending ++ HCI_STATUS_RESERVE_3 =0X33, //Reserved ++ HCI_STATUS_RESERVE_SOLT_VIOLATION =0X34, //Reserved Slot Violation ++ HCI_STATUS_ROLE_SWITCH_FAIL =0X35, //Role Switch Failed ++ HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE =0X36, //Extended Inquiry Response Too Large ++ HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT =0X37, //Secure Simple Pairing Not Supported By Host. ++ HCI_STATUS_HOST_BUSY_PAIRING =0X38, //Host Busy - Pairing ++ HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND =0X39, //Connection Rejected due to No Suitable Channel Found ++ HCI_STATUS_CONTROLLER_BUSY =0X3a //CONTROLLER BUSY ++} HCI_STATUS,*PHCI_STATUS; ++ ++//============================================= ++// The following is for BT 3.0 + HS HCI COMMAND ++//============================================= ++ ++//bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ++// | OCF | OGF | ++// ++ ++//OGF 0x01 ++#define OGF_LINK_CONTROL_COMMANDS 0x01 ++typedef enum _LINK_CONTROL_COMMANDS ++{ ++ HCI_INQUIRY =0x0001, ++ HCI_INQUIRY_CANCEL =0x0002, ++ HCI_PERIODIC_INQUIRY_MODE =0x0003, ++ HCI_EXIT_PERIODIC_INQUIRY_MODE =0x0004, ++ HCI_CREATE_CONNECTION =0x0005, ++ HCI_DISCONNECT =0x0006, ++ HCI_CREATE_CONNECTION_CANCEL =0x0008, ++ HCI_ACCEPT_CONNECTIONREQUEST =0x0009, ++ HCI_REJECT_CONNECTION_REQUEST =0x000a, ++ HCI_LINK_KEY_REQUEST_REPLY =0x000b, ++ HCI_LINK_KEY_REQUEST_NEGATIVE_REPLY =0x000c, ++ HCI_PIN_CODE_REQUEST_REPLY =0x000d, ++ HCI_PIN_CODE_REQUEST_NEGATIVE_REPLY =0x000e, ++ HCI_CHANGE_CONNECTION_PACKET_TYPE =0x000f, ++ HCI_AUTHENTICATION_REQUESTED =0x0011, ++ HCI_SET_CONNECTION_ENCRYPTION =0x0013, ++ HCI_CHANGE_CONNECTION_LINK_KEY =0x0015, ++ HCI_MASTER_LINK_KEY =0x0017, ++ HCI_REMOTE_NAME_REQUEST =0x0019, ++ HCI_REMOTE_NAME_REQUEST_CANCEL =0x001a, ++ HCI_READ_REMOTE_SUPPORTED_FEATURES =0x001b, ++ HCI_READ_REMOTE_EXTENDED_FEATURES =0x001c, ++ HCI_READ_REMOTE_VERSION_INFORMATION =0x001d, ++ HCI_READ_CLOCK_OFFSET =0x001f, ++ HCI_READ_LMP_HANDLE =0x0020, ++ HCI_SETUP_SYNCHRONOUS_CONNECTION =0x0028, ++ HCI_ACCEPT_SYNCHRONOUS_CONNECTION_REQUEST =0x0029, ++ HCI_REJECT_SYNCHRONOUS_CONNECTION_REQUEST =0x002a, ++ HCI_IO_CAPABILITY_REQUEST_REPLY =0x002b, ++ HCI_USER_CONFIRMATION_REQUEST_REPLY =0x002c, ++ HCI_USER_CONFIRMATION_REQUEST_NEGATIVE_REPLY =0x002d, ++ HCI_USER_PASSKEY_REQUEST_REPLY =0x002e, ++ HCI_USER_PASSKEY_REQUESTNEGATIVE_REPLY =0x002f, ++ HCI_REMOTE_OOB_DATA_REQUEST_REPLY =0x0030, ++ HCI_REMOTE_OOB_DATA_REQUEST_NEGATIVE_REPLY =0x0033, ++ HCI_IO_CAPABILITY_REQUEST_NEGATIVE_REPLY =0x0034, ++ HCI_CREATE_PHYSICAL_LINK =0x0035, ++ HCI_ACCEPT_PHYSICAL_LINK =0x0036, ++ HCI_DISCONNECT_PHYSICAL_LINK =0x0037, ++ HCI_CREATE_LOGICAL_LINK =0x0038, ++ HCI_ACCEPT_LOGICAL_LINK =0x0039, ++ HCI_DISCONNECT_LOGICAL_LINK =0x003a, ++ HCI_LOGICAL_LINK_CANCEL =0x003b, ++ HCI_FLOW_SPEC_MODIFY =0x003c ++} LINK_CONTROL_COMMANDS,*PLINK_CONTROL_COMMANDS; ++ ++//OGF 0x02 ++#define OGF_HOLD_MODE_COMMAND 0x02 ++typedef enum _HOLD_MODE_COMMAND ++{ ++ HCI_HOLD_MODE =0x0001, ++ HCI_SNIFF_MODE =0x0002, ++ HCI_EXIT_SNIFF_MODE =0x0003, ++ HCI_PARK_STATE =0x0005, ++ HCI_EXIT_PARK_STATE =0x0006, ++ HCI_QOS_SETUP =0x0007, ++ HCI_ROLE_DISCOVERY =0x0009, ++ HCI_SWITCH_ROLE =0x000b, ++ HCI_READ_LINK_POLICY_SETTINGS =0x000c, ++ HCI_WRITE_LINK_POLICY_SETTINGS =0x000d, ++ HCI_READ_DEFAULT_LINK_POLICY_SETTINGS =0x000e, ++ HCI_WRITE_DEFAULT_LINK_POLICY_SETTINGS =0x000f, ++ HCI_FLOW_SPECIFICATION =0x0010, ++ HCI_SNIFF_SUBRATING =0x0011 ++} HOLD_MODE_COMMAND,*PHOLD_MODE_COMMAND; ++ ++//OGF 0x03 ++#define OGF_SET_EVENT_MASK_COMMAND 0x03 ++typedef enum _SET_EVENT_MASK_COMMAND ++{ ++ HCI_SET_EVENT_MASK =0x0001, ++ HCI_RESET =0x0003, ++ HCI_SET_EVENT_FILTER =0x0005, ++ HCI_FLUSH =0x0008, ++ HCI_READ_PIN_TYPE =0x0009, ++ HCI_WRITE_PIN_TYPE =0x000a, ++ HCI_CREATE_NEW_UNIT_KEY =0x000b, ++ HCI_READ_STORED_LINK_KEY =0x000d, ++ HCI_WRITE_STORED_LINK_KEY =0x0011, ++ HCI_DELETE_STORED_LINK_KEY =0x0012, ++ HCI_WRITE_LOCAL_NAME =0x0013, ++ HCI_READ_LOCAL_NAME =0x0014, ++ HCI_READ_CONNECTION_ACCEPT_TIMEOUT =0x0015, ++ HCI_WRITE_CONNECTION_ACCEPT_TIMEOUT =0x0016, ++ HCI_READ_PAGE_TIMEOUT =0x0017, ++ HCI_WRITE_PAGE_TIMEOUT =0x0018, ++ HCI_READ_SCAN_ENABLE =0x0019, ++ HCI_WRITE_SCAN_ENABLE =0x001a, ++ HCI_READ_PAGE_SCAN_ACTIVITY =0x001b, ++ HCI_WRITE_PAGE_SCAN_ACTIVITY =0x001c, ++ HCI_READ_INQUIRY_SCAN_ACTIVITY =0x001d, ++ HCI_WRITE_INQUIRY_SCAN_ACTIVITY =0x001e, ++ HCI_READ_AUTHENTICATION_ENABLE =0x001f, ++ HCI_WRITE_AUTHENTICATION_ENABLE =0x0020, ++ HCI_READ_CLASS_OF_DEVICE =0x0023, ++ HCI_WRITE_CLASS_OF_DEVICE =0x0024, ++ HCI_READ_VOICE_SETTING =0x0025, ++ HCI_WRITE_VOICE_SETTING =0x0026, ++ HCI_READ_AUTOMATIC_FLUSH_TIMEOUT =0x0027, ++ HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT =0x0028, ++ HCI_READ_NUM_BROADCAST_RETRANSMISSIONS =0x0029, ++ HCI_WRITE_NUM_BROADCAST_RETRANSMISSIONS =0x002a, ++ HCI_READ_HOLD_MODE_ACTIVITY =0x002b, ++ HCI_WRITE_HOLD_MODE_ACTIVITY =0x002c, ++ HCI_READ_SYNCHRONOUS_FLOW_CONTROL_ENABLE =0x002e, ++ HCI_WRITE_SYNCHRONOUS_FLOW_CONTROL_ENABLE =0x002f, ++ HCI_SET_CONTROLLER_TO_HOST_FLOW_CONTROL =0x0031, ++ HCI_HOST_BUFFER_SIZE =0x0033, ++ HCI_HOST_NUMBER_OF_COMPLETED_PACKETS =0x0035, ++ HCI_READ_LINK_SUPERVISION_TIMEOUT =0x0036, ++ HCI_WRITE_LINK_SUPERVISION_TIMEOUT =0x0037, ++ HCI_READ_NUMBER_OF_SUPPORTED_IAC =0x0038, ++ HCI_READ_CURRENT_IAC_LAP =0x0039, ++ HCI_WRITE_CURRENT_IAC_LAP =0x003a, ++ HCI_READ_PAGE_SCAN_MODE =0x003d, ++ HCI_WRITE_PAGE_SCAN_MODE =0x003e, ++ HCI_SET_AFH_HOST_CHANNEL_CLASSIFICATION =0x003f, ++ HCI_READ_INQUIRY_SCAN_TYPE =0x0042, ++ HCI_WRITE_INQUIRY_SCAN_TYPE =0x0043, ++ HCI_READ_INQUIRY_MODE =0x0044, ++ HCI_WRITE_INQUIRY_MODE =0x0045, ++ HCI_READ_PAGE_SCAN_TYPE =0x0046, ++ HCI_WRITE_PAGE_SCAN_TYPE =0x0047, ++ HCI_READ_AFH_CHANNEL_ASSESSMENT_MODE =0x0048, ++ HCI_WRITE_AFH_CHANNEL_ASSESSMENT_MODE =0x0049, ++ HCI_READ_EXTENDED_INQUIRY_RESPONSE =0x0051, ++ HCI_WRITE_EXTENDED_INQUIRY_RESPONSE =0x0052, ++ HCI_REFRESH_ENCRYPTION_KEY =0x0053, ++ HCI_READ_SIMPLE_PAIRING_MODE =0x0055, ++ HCI_WRITE_SIMPLE_PAIRING_MODE =0x0056, ++ HCI_READ_LOCAL_OOB_DATA =0x0057, ++ HCI_READ_INQUIRY_RESPONSE_TRANSMIT_POWER_LEVEL =0x0058, ++ HCI_WRITE_INQUIRY_TRANSMIT_POWER_LEVEL =0x0059, ++ HCI_READ_DEFAULT_ERRONEOUS_DATA_REPORTING =0x005a, ++ HCI_WRITE_DEFAULT_ERRONEOUS_DATA_REPORTING =0x005b, ++ HCI_ENHANCED_FLUSH =0x005f, ++ HCI_SEND_KEYPRESS_NOTIFICATION =0x0060, ++ HCI_READ_LOGICAL_LINK_ACCEPT_TIMEOUT =0x0061, ++ HCI_WRITE_LOGICAL_LINK_ACCEPT_TIMEOUT =0x0062, ++ HCI_SET_EVENT_MASK_PAGE_2 =0x0063, ++ HCI_READ_LOCATION_DATA =0x0064, ++ HCI_WRITE_LOCATION_DATA =0x0065, ++ HCI_READ_FLOW_CONTROL_MODE =0x0066, ++ HCI_WRITE_FLOW_CONTROL_MODE =0x0067, ++ HCI_READ_ENHANCE_TRANSMIT_POWER_LEVEL =0x0068, ++ HCI_READ_BEST_EFFORT_FLUSH_TIMEOUT =0x0069, ++ HCI_WRITE_BEST_EFFORT_FLUSH_TIMEOUT =0x006a, ++ HCI_SHORT_RANGE_MODE =0x006b ++}SET_EVENT_MASK_COMMAND,*PSET_EVENT_MASK_COMMAND; ++ ++//OGF 0x04 ++#define OGF_INFORMATIONAL_PARAMETERS 0x04 ++typedef enum _INFORMATIONAL_PARAMETERS ++{ ++ HCI_READ_LOCAL_VERSION_INFORMATION =0x0001, ++ HCI_READ_LOCAL_SUPPORTED_COMMANDS =0x0002, ++ HCI_READ_LOCAL_SUPPORTED_FEATURES =0x0003, ++ HCI_READ_LOCAL_EXTENDED_FEATURES =0x0004, ++ HCI_READ_BUFFER_SIZE =0x0005, ++ HCI_READ_BD_ADDR =0x0009, ++ HCI_READ_DATA_BLOCK_SIZE =0x000a ++} INFORMATIONAL_PARAMETERS,*PINFORMATIONAL_PARAMETERS; ++ ++//OGF 0x05 ++#define OGF_STATUS_PARAMETERS 0x05 ++typedef enum _STATUS_PARAMETERS ++{ ++ HCI_READ_FAILED_CONTACT_COUNTER =0x0001, ++ HCI_RESET_FAILED_CONTACT_COUNTER =0x0002, ++ HCI_READ_LINK_QUALITY =0x0003, ++ HCI_READ_RSSI =0x0005, ++ HCI_READ_AFH_CHANNEL_MAP =0x0006, ++ HCI_READ_CLOCK =0x0007, ++ HCI_READ_ENCRYPTION_KEY_SIZE =0x0008, ++ HCI_READ_LOCAL_AMP_INFO =0x0009, ++ HCI_READ_LOCAL_AMP_ASSOC =0x000a, ++ HCI_WRITE_REMOTE_AMP_ASSOC =0x000b ++} STATUS_PARAMETERS,*PSTATUS_PARAMETERS; ++ ++//OGF 0x06 ++#define OGF_TESTING_COMMANDS 0x06 ++typedef enum _TESTING_COMMANDS ++{ ++ HCI_READ_LOOPBACK_MODE =0x0001, ++ HCI_WRITE_LOOPBACK_MODE =0x0002, ++ HCI_ENABLE_DEVICE_UNDER_TEST_MODE =0x0003, ++ HCI_WRITE_SIMPLE_PAIRING_DEBUG_MODE =0x0004, ++ HCI_ENABLE_AMP_RECEIVER_REPORTS =0x0007, ++ HCI_AMP_TEST_END =0x0008, ++ HCI_AMP_TEST_COMMAND =0x0009 ++} TESTING_COMMANDS,*PTESTING_COMMANDS; ++ ++//OGF 0x3f ++#define OGF_EXTENSION 0X3f ++typedef enum _HCI_EXTENSION_COMMANDS ++{ ++ HCI_SET_ACL_LINK_DATA_FLOW_MODE =0x0010, ++ HCI_SET_ACL_LINK_STATUS =0x0020, ++ HCI_SET_SCO_LINK_STATUS =0x0030, ++ HCI_SET_RSSI_VALUE =0x0040, ++ HCI_SET_CURRENT_BLUETOOTH_STATUS =0x0041, ++ ++ //The following is for RTK8723 ++ HCI_EXTENSION_VERSION_NOTIFY =0x0100, ++ HCI_LINK_STATUS_NOTIFY =0x0101, ++ HCI_BT_OPERATION_NOTIFY =0x0102, ++ HCI_ENABLE_WIFI_SCAN_NOTIFY =0x0103, ++ ++ ++ //The following is for IVT ++ HCI_WIFI_CURRENT_CHANNEL =0x0300, ++ HCI_WIFI_CURRENT_BANDWIDTH =0x0301, ++ HCI_WIFI_CONNECTION_STATUS =0x0302, ++} HCI_EXTENSION_COMMANDS,*PHCI_EXTENSION_COMMANDS; ++ ++typedef enum _BT_SPEC ++{ ++ BT_SPEC_1_0_b =0x00, ++ BT_SPEC_1_1 =0x01, ++ BT_SPEC_1_2 =0x02, ++ BT_SPEC_2_0_EDR =0x03, ++ BT_SPEC_2_1_EDR =0x04, ++ BT_SPEC_3_0_HS =0x05, ++ BT_SPEC_4_0 =0x06 ++} BT_SPEC,*PBT_SPEC; ++ ++//============================================= ++// The following is for BT 3.0 + HS EVENTS ++//============================================= ++typedef enum _HCI_EVENT ++{ ++ HCI_EVENT_INQUIRY_COMPLETE =0x01, ++ HCI_EVENT_INQUIRY_RESULT =0x02, ++ HCI_EVENT_CONNECTION_COMPLETE =0x03, ++ HCI_EVENT_CONNECTION_REQUEST =0x04, ++ HCI_EVENT_DISCONNECTION_COMPLETE =0x05, ++ HCI_EVENT_AUTHENTICATION_COMPLETE =0x06, ++ HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE =0x07, ++ HCI_EVENT_ENCRYPTION_CHANGE =0x08, ++ HCI_EVENT_CHANGE_LINK_KEY_COMPLETE =0x09, ++ HCI_EVENT_MASTER_LINK_KEY_COMPLETE =0x0a, ++ HCI_EVENT_READ_REMOTE_SUPPORT_FEATURES_COMPLETE =0x0b, ++ HCI_EVENT_READ_REMOTE_VER_INFO_COMPLETE =0x0c, ++ HCI_EVENT_QOS_SETUP_COMPLETE =0x0d, ++ HCI_EVENT_COMMAND_COMPLETE =0x0e, ++ HCI_EVENT_COMMAND_STATUS =0x0f, ++ HCI_EVENT_HARDWARE_ERROR =0x10, ++ HCI_EVENT_FLUSH_OCCRUED =0x11, ++ HCI_EVENT_ROLE_CHANGE =0x12, ++ HCI_EVENT_NUMBER_OF_COMPLETE_PACKETS =0x13, ++ HCI_EVENT_MODE_CHANGE =0x14, ++ HCI_EVENT_RETURN_LINK_KEYS =0x15, ++ HCI_EVENT_PIN_CODE_REQUEST =0x16, ++ HCI_EVENT_LINK_KEY_REQUEST =0x17, ++ HCI_EVENT_LINK_KEY_NOTIFICATION =0x18, ++ HCI_EVENT_LOOPBACK_COMMAND =0x19, ++ HCI_EVENT_DATA_BUFFER_OVERFLOW =0x1a, ++ HCI_EVENT_MAX_SLOTS_CHANGE =0x1b, ++ HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE =0x1c, ++ HCI_EVENT_CONNECT_PACKET_TYPE_CHANGE =0x1d, ++ HCI_EVENT_QOS_VIOLATION =0x1e, ++ HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE =0x20, ++ HCI_EVENT_FLOW_SEPC_COMPLETE =0x21, ++ HCI_EVENT_INQUIRY_RESULT_WITH_RSSI =0x22, ++ HCI_EVENT_READ_REMOTE_EXT_FEATURES_COMPLETE =0x23, ++ HCI_EVENT_SYNC_CONNECT_COMPLETE =0x2c, ++ HCI_EVENT_SYNC_CONNECT_CHANGE =0x2d, ++ HCI_EVENT_SNIFFER_SUBRATING =0x2e, ++ HCI_EVENT_EXTENTED_INQUIRY_RESULT =0x2f, ++ HCI_EVENT_ENCRYPTION_KEY_REFLASH_COMPLETE =0x30, ++ HCI_EVENT_IO_CAPIBILITY_COMPLETE =0x31, ++ HCI_EVENT_IO_CAPIBILITY_RESPONSE =0x32, ++ HCI_EVENT_USER_CONFIRMTION_REQUEST =0x33, ++ HCI_EVENT_USER_PASSKEY_REQUEST =0x34, ++ HCI_EVENT_REMOTE_OOB_DATA_REQUEST =0x35, ++ HCI_EVENT_SIMPLE_PAIRING_COMPLETE =0x36, ++ HCI_EVENT_LINK_SUPERVISION_TIMEOUT_CHANGE =0x38, ++ HCI_EVENT_ENHANCED_FLUSH_COMPLETE =0x39, ++ HCI_EVENT_USER_PASSKEY_NOTIFICATION =0x3b, ++ HCI_EVENT_KEYPRESS_NOTIFICATION =0x3c, ++ HCI_EVENT_REMOTE_HOST_SUPPORT_FEATURES_NOTIFICATION =0x3d, ++ HCI_EVENT_PHY_LINK_COMPLETE =0x40, ++ HCI_EVENT_CHANNEL_SELECT =0x41, ++ HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE =0x42, ++ HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING =0x43, ++ HCI_EVENT_PHY_LINK_RECOVER =0x44, ++ HCI_EVENT_LOGICAL_LINK_COMPLETE =0x45, ++ HCI_EVENT_DISCONNECT_LOGICAL_LINK_COMPLETE =0x46, ++ HCI_EVENT_FLOW_SPEC_MODIFY_COMPLETE =0x47, ++ HCI_EVENT_NUM_OF_COMPLETE_DATA_BLOCKS =0x48, ++ HCI_EVENT_AMP_START_TEST =0x49, ++ HCI_EVENT_AMP_TEST_END =0x4a, ++ HCI_EVENT_AMP_RECEIVER_REPORT =0x4b, ++ HCI_EVENT_SHORT_RANGE_MODE_CHANGE_COMPLETE =0x4c, ++ HCI_EVENT_AMP_STATUS_CHANGE =0x4d, ++ HCI_EVENT_EXTENSION_RTK =0xfe, ++ HCI_EVENT_EXTENSION_MOTO =0xff, ++}HCI_EVENT, *PHCI_EVENT; ++ ++typedef enum _HCI_EXTENSION_EVENT_MOTO ++{ ++ HCI_EVENT_GET_BT_RSSI =0x01, ++} HCI_EXTENSION_EVENT_MOTO, *PHCI_EXTENSION_EVENT_MOTO; ++ ++typedef enum _HCI_EXTENSION_EVENT_RTK ++{ ++ HCI_EVENT_EXT_WIFI_SCAN_NOTIFY =0x01, ++} HCI_EXTENSION_EVENT_RTK, *PHCI_EXTENSION_EVENT_RTK; ++ ++typedef enum _HCI_EVENT_MASK_PAGE_2 ++{ ++ EMP2_HCI_EVENT_PHY_LINK_COMPLETE =0x0000000000000001, ++ EMP2_HCI_EVENT_CHANNEL_SELECT =0x0000000000000002, ++ EMP2_HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE =0x0000000000000004, ++ EMP2_HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING =0x0000000000000008, ++ EMP2_HCI_EVENT_PHY_LINK_RECOVER =0x0000000000000010, ++ EMP2_HCI_EVENT_LOGICAL_LINK_COMPLETE =0x0000000000000020, ++ EMP2_HCI_EVENT_DISCONNECT_LOGICAL_LINK_COMPLETE =0x0000000000000040, ++ EMP2_HCI_EVENT_FLOW_SPEC_MODIFY_COMPLETE =0x0000000000000080, ++ EMP2_HCI_EVENT_NUM_OF_COMPLETE_DATA_BLOCKS =0x0000000000000100, ++ EMP2_HCI_EVENT_AMP_START_TEST =0x0000000000000200, ++ EMP2_HCI_EVENT_AMP_TEST_END =0x0000000000000400, ++ EMP2_HCI_EVENT_AMP_RECEIVER_REPORT =0x0000000000000800, ++ EMP2_HCI_EVENT_SHORT_RANGE_MODE_CHANGE_COMPLETE =0x0000000000001000, ++ EMP2_HCI_EVENT_AMP_STATUS_CHANGE =0x0000000000002000, ++} HCI_EVENT_MASK_PAGE_2, *PHCI_EVENT_MASK_PAGE_2; ++ ++typedef enum _HCI_STATE_MACHINE ++{ ++ HCI_STATE_STARTING =0x01, ++ HCI_STATE_CONNECTING =0x02, ++ HCI_STATE_AUTHENTICATING =0x04, ++ HCI_STATE_CONNECTED =0x08, ++ HCI_STATE_DISCONNECTING =0x10, ++ HCI_STATE_DISCONNECTED =0x20 ++} HCI_STATE_MACHINE, *PHCI_STATE_MACHINE; ++ ++typedef enum _AMP_ASSOC_STRUCTURE_TYPE ++{ ++ AMP_MAC_ADDR =0x01, ++ AMP_PREFERRED_CHANNEL_LIST =0x02, ++ AMP_CONNECTED_CHANNEL =0x03, ++ AMP_80211_PAL_CAP_LIST =0x04, ++ AMP_80211_PAL_VISION =0x05, ++ AMP_RESERVED_FOR_TESTING =0x33 ++} AMP_ASSOC_STRUCTURE_TYPE, *PAMP_ASSOC_STRUCTURE_TYPE; ++ ++typedef enum _AMP_BTAP_TYPE ++{ ++ AMP_BTAP_NONE, ++ AMP_BTAP_CREATOR, ++ AMP_BTAP_JOINER ++} AMP_BTAP_TYPE, *PAMP_BTAP_TYPE; ++ ++typedef enum _HCI_STATE_WITH_CMD ++{ ++ STATE_CMD_CREATE_PHY_LINK, ++ STATE_CMD_ACCEPT_PHY_LINK, ++ STATE_CMD_DISCONNECT_PHY_LINK, ++ STATE_CMD_CONNECT_ACCEPT_TIMEOUT, ++ STATE_CMD_MAC_START_COMPLETE, ++ STATE_CMD_MAC_START_FAILED, ++ STATE_CMD_MAC_CONNECT_COMPLETE, ++ STATE_CMD_MAC_CONNECT_FAILED, ++ STATE_CMD_MAC_DISCONNECT_INDICATE, ++ STATE_CMD_MAC_CONNECT_CANCEL_INDICATE, ++ STATE_CMD_4WAY_FAILED, ++ STATE_CMD_4WAY_SUCCESSED, ++ STATE_CMD_ENTER_STATE, ++ STATE_CMD_NO_SUCH_CMD, ++} HCI_STATE_WITH_CMD, *PHCI_STATE_WITH_CMD; ++ ++typedef enum _HCI_SERVICE_TYPE ++{ ++ SERVICE_NO_TRAFFIC, ++ SERVICE_BEST_EFFORT, ++ SERVICE_GUARANTEE ++} HCI_SERVICE_TYPE, *PHCI_SERVICE_TYPE; ++ ++typedef enum _HCI_TRAFFIC_MODE ++{ ++ TRAFFIC_MODE_BEST_EFFORT =0x00, ++ TRAFFIC_MODE_GUARANTEED_LATENCY =0x01, ++ TRAFFIC_MODE_GUARANTEED_BANDWIDTH =0x02, ++ TRAFFIC_MODE_GUARANTEED_LATENCY_AND_BANDWIDTH =0x03 ++} HCI_TRAFFIC_MODE, *PHCI_TRAFFIC_MODE; ++ ++#define HCIOPCODE(_OCF, _OGF) (_OGF<<10|_OCF) ++#define HCIOPCODELOW(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)&0x00ff) ++#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8) ++ ++#define TWOBYTE_HIGHTBYTE(_DATA) (u8)(_DATA>>8) ++#define TWOBYTE_LOWBYTE(_DATA) (u8)(_DATA) ++ ++typedef enum _AMP_STATUS ++{ ++ AMP_STATUS_AVA_PHY_PWR_DWN = 0x0, ++ AMP_STATUS_BT_USE_ONLY = 0x1, ++ AMP_STATUS_NO_CAPACITY_FOR_BT = 0x2, ++ AMP_STATUS_LOW_CAPACITY_FOR_BT = 0x3, ++ AMP_STATUS_MEDIUM_CAPACITY_FOR_BT = 0x4, ++ AMP_STATUS_HIGH_CAPACITY_FOR_BT = 0x5, ++ AMP_STATUS_FULL_CAPACITY_FOR_BT = 0x6 ++} AMP_STATUS, *PAMP_STATUS; ++ ++typedef enum ++{ ++ Type_BT_4way1st = 0, ++ Type_BT_4way2nd = 1, ++ Type_BT_4way3rd = 2, ++ Type_BT_4way4th = 3, ++ Type_BT_unknow = 4 ++} BT_WPAMsgType; ++ ++typedef enum _BT_CONNECT_TYPE ++{ ++ BT_CONNECT_AUTH_REQ =0x00, ++ BT_CONNECT_AUTH_RSP =0x01, ++ BT_CONNECT_ASOC_REQ =0x02, ++ BT_CONNECT_ASOC_RSP =0x03, ++ BT_DISCONNECT =0x04 ++} BT_CONNECT_TYPE, *PBT_CONNECT_TYPE; ++ ++typedef enum _BT_LL_SERVICE_TYPE ++{ ++ BT_LL_BE = 0x01, ++ BT_LL_GU = 0x02 ++} BT_LL_SERVICE_TYPE; ++ ++typedef enum _BT_LL_FLOWSPEC ++{ ++ BT_TX_BE_FS, //TX best effort flowspec ++ BT_RX_BE_FS, //RX best effort flowspec ++ BT_TX_GU_FS, //TX guaranteed latency flowspec ++ BT_RX_GU_FS, //RX guaranteed latency flowspec ++ BT_TX_BE_AGG_FS, //TX aggregated best effort flowspec ++ BT_RX_BE_AGG_FS, //RX aggregated best effort flowspec ++ BT_TX_GU_BW_FS, //TX guaranteed bandwidth flowspec ++ BT_RX_GU_BW_FS, //RX guaranteed bandwidth flowspec ++ BT_TX_GU_LARGE_FS, //TX guaranteed latency flowspec, for testing only ++ BT_RX_GU_LARGE_FS, //RX guaranteed latency flowspec, for testing only ++} BT_LL_FLOWSPEC; ++ ++typedef enum _BT_TRAFFIC_MODE ++{ ++ BT_MOTOR_EXT_BE = 0x00, //Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. ++ BT_MOTOR_EXT_GUL = 0x01, //Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. ++ BT_MOTOR_EXT_GUB = 0X02, //Guaranteed Bandwidth. ++ BT_MOTOR_EXT_GULB = 0X03 //Guaranteed Latency and Bandwidth. for A2DP and VDP. ++} BT_TRAFFIC_MODE; ++ ++typedef enum _BT_TRAFFIC_MODE_PROFILE ++{ ++ BT_PROFILE_NONE, ++ BT_PROFILE_A2DP, ++ BT_PROFILE_PAN, ++ BT_PROFILE_HID, ++ BT_PROFILE_SCO ++} BT_TRAFFIC_MODE_PROFILE; ++ ++typedef enum _BT_LINK_ROLE ++{ ++ BT_LINK_MASTER = 0, ++ BT_LINK_SLAVE = 1 ++} BT_LINK_ROLE; ++ ++typedef enum _BT_STATE_WPA_AUTH ++{ ++ STATE_WPA_AUTH_UNINITIALIZED, ++ STATE_WPA_AUTH_WAIT_PACKET_1, // Join ++ STATE_WPA_AUTH_WAIT_PACKET_2, // Creat ++ STATE_WPA_AUTH_WAIT_PACKET_3, ++ STATE_WPA_AUTH_WAIT_PACKET_4, ++ STATE_WPA_AUTH_SUCCESSED ++} BT_STATE_WPA_AUTH, *PBT_STATE_WPA_AUTH; ++ ++#define BT_WPA_AUTH_TIMEOUT_PERIOD 1000 ++#define BTMaxWPAAuthReTransmitCoun 5 ++ ++#define MAX_AMP_ASSOC_FRAG_LEN 248 ++#define TOTAL_ALLOCIATE_ASSOC_LEN 1000 ++ ++typedef struct _HCI_FLOW_SPEC ++{ ++ u8 Identifier; ++ u8 ServiceType; ++ u16 MaximumSDUSize; ++ u32 SDUInterArrivalTime; ++ u32 AccessLatency; ++ u32 FlushTimeout; ++} HCI_FLOW_SPEC, *PHCI_FLOW_SPEC; ++ ++typedef struct _HCI_LOG_LINK_CMD_DATA ++{ ++ u8 BtPhyLinkhandle; ++ u16 BtLogLinkhandle; ++ u8 BtTxFlowSpecID; ++ HCI_FLOW_SPEC Tx_Flow_Spec; ++ HCI_FLOW_SPEC Rx_Flow_Spec; ++ u32 TxPacketCount; ++ u32 BestEffortFlushTimeout; ++ ++ u8 bLLCompleteEventIsSet; ++ ++ u8 bLLCancelCMDIsSetandComplete; ++} HCI_LOG_LINK_CMD_DATA, *PHCI_LOG_LINK_CMD_DATA; ++ ++typedef struct _HCI_PHY_LINK_CMD_DATA ++{ ++ //Physical_Link_Handle ++ u8 BtPhyLinkhandle; ++ ++ u16 LinkSuperversionTimeout; ++ ++ //u16 SuperTimeOutCnt; ++ ++ //Dedicated_AMP_Key_Length ++ u8 BtAMPKeyLen; ++ //Dedicated_AMP_Key_Type ++ u8 BtAMPKeyType; ++ //Dedicated_AMP_Key ++ u8 BtAMPKey[PMK_LEN]; ++} HCI_PHY_LINK_CMD_DATA, *PHCI_PHY_LINK_CMD_DATA; ++ ++typedef struct _AMP_ASSOC_STRUCTURE ++{ ++ //TYPE ID ++ u8 TypeID; ++ //Length ++ u16 Length; ++ //Value ++ u8 Data[1]; ++} AMP_ASSOC_STRUCTURE, *PAMP_ASSOC_STRUCTURE; ++ ++typedef struct _AMP_PREF_CHNL_REGULATORY ++{ ++ u8 reXId; ++ u8 regulatoryClass; ++ u8 coverageClass; ++} AMP_PREF_CHNL_REGULATORY, *PAMP_PREF_CHNL_REGULATORY; ++ ++typedef struct _AMP_ASSOC_CMD_DATA ++{ ++ //Physical_Link_Handle ++ u8 BtPhyLinkhandle; ++ //Length_So_Far ++ u16 LenSoFar; ++ ++ u16 MaxRemoteASSOCLen; ++ //AMP_ASSOC_Remaining_Length ++ u16 AMPAssocRemLen; ++ //AMP_ASSOC_fragment ++ void *AMPAssocfragment; ++} AMP_ASSOC_CMD_DATA, *PAMP_ASSOC_CMD_DATA; ++ ++typedef struct _HCI_LINK_INFO ++{ ++ u16 ConnectHandle; ++ u8 IncomingTrafficMode; ++ u8 OutgoingTrafficMode; ++ u8 BTProfile; ++ u8 BTCoreSpec; ++ s8 BT_RSSI; ++ u8 TrafficProfile; ++ u8 linkRole; ++} HCI_LINK_INFO, *PHCI_LINK_INFO; ++ ++typedef struct _HCI_EXT_CONFIG ++{ ++ HCI_LINK_INFO linkInfo[MAX_BT_ASOC_ENTRY_NUM]; ++ u8 btOperationCode; ++ u16 CurrentConnectHandle; ++ u8 CurrentIncomingTrafficMode; ++ u8 CurrentOutgoingTrafficMode; ++ s8 MIN_BT_RSSI; ++ u8 NumberOfHandle; ++ u8 NumberOfSCO; ++ u8 CurrentBTStatus; ++ u16 HCIExtensionVer; ++ ++ //Bt coexist related ++ u8 btProfileCase; ++ u8 btProfileAction; ++ u8 bManualControl; ++ u8 bBTBusy; ++ u8 bBTA2DPBusy; ++ u8 bEnableWifiScanNotify; ++ ++ u8 bHoldForBtOperation; ++ u32 bHoldPeriodCnt; ++ ++}HCI_EXT_CONFIG, *PHCI_EXT_CONFIG; ++ ++typedef struct _HCI_ACL_PACKET_DATA ++{ ++ u16 ACLDataPacketLen; ++ u8 SyncDataPacketLen; ++ u16 TotalNumACLDataPackets; ++ u16 TotalSyncNumDataPackets; ++} HCI_ACL_PACKET_DATA, *PHCI_ACL_PACKET_DATA; ++ ++typedef struct _HCI_PHY_LINK_BSS_INFO ++{ ++ u16 bdCap; // capability information ++ ++ // Qos related. Added by Annie, 2005-11-01. ++// BSS_QOS BssQos; // not implement yet ++ ++} HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO; ++ ++typedef struct _PACKET_IRP_HCICMD_DATA ++{ ++ u16 OCF:10; ++ u16 OGF:6; ++ u8 Length; ++ u8 Data[1]; ++} PACKET_IRP_HCICMD_DATA, *PPACKET_IRP_HCICMD_DATA; ++ ++typedef struct _BT_ASOC_ENTRY ++{ ++ u8 bUsed; ++ u8 mAssoc; ++ u8 b4waySuccess; ++ u8 Bssid[6]; ++ HCI_PHY_LINK_CMD_DATA PhyLinkCmdData; ++ ++ HCI_LOG_LINK_CMD_DATA LogLinkCmdData[MAX_LOGICAL_LINK_NUM]; ++ ++ HCI_ACL_PACKET_DATA ACLPacketsData; ++ ++ AMP_ASSOC_CMD_DATA AmpAsocCmdData; ++ OCTET_STRING BTSsid; ++ u8 BTSsidBuf[33]; ++ ++ HCI_STATUS PhyLinkDisconnectReason; ++ ++ u8 bSendSupervisionPacket; ++ //u8 CurrentSuervisionPacketSendNum; ++ //u8 LastSuervisionPacketSendNum; ++ u32 NoRxPktCnt; ++ //Is Creator or Joiner ++ AMP_BTAP_TYPE AMPRole; ++ ++ //BT current state ++ u8 BtCurrentState; ++ //BT next state ++ u8 BtNextState; ++ ++ u8 bNeedPhysLinkCompleteEvent; ++ ++ HCI_STATUS PhysLinkCompleteStatus; ++ ++ u8 BTRemoteMACAddr[6]; ++ ++ u32 BTCapability; ++ ++ u8 SyncDataPacketLen; ++ ++ u16 TotalSyncNumDataPackets; ++ u16 TotalNumACLDataPackets; ++ ++ u8 ShortRangeMode; ++ ++ u8 PTK[PTK_LEN_TKIP]; ++ u8 GTK[GTK_LEN]; ++ u8 ANonce[KEY_NONCE_LEN]; ++ u8 SNonce[KEY_NONCE_LEN]; ++ u64 KeyReplayCounter; ++ u8 WPAAuthReplayCount; ++ u8 AESKeyBuf[AESCCMP_BLK_SIZE_TOTAL]; ++ u8 PMK[PMK_LEN]; ++ BT_STATE_WPA_AUTH BTWPAAuthState; ++ s32 UndecoratedSmoothedPWDB; ++ ++ // Add for HW security !! ++ u8 HwCAMIndex; // Cam index ++ u8 bPeerQosSta; ++ ++ u32 rxSuvpPktCnt; ++}BT_ASOC_ENTRY, *PBT_ASOC_ENTRY; ++ ++typedef struct _BT_TRAFFIC_STATISTICS ++{ ++ u8 bTxBusyTraffic; ++ u8 bRxBusyTraffic; ++ u8 bIdle; ++ u32 TxPktCntInPeriod; ++ u32 RxPktCntInPeriod; ++ u64 TxPktLenInPeriod; ++ u64 RxPktLenInPeriod; ++} BT_TRAFFIC_STATISTICS, *PBT_TRAFFIC_STATISTICS; ++ ++typedef struct _BT_MGNT ++{ ++ u8 bBTConnectInProgress; ++ u8 bLogLinkInProgress; ++ u8 bPhyLinkInProgress; ++ u8 bPhyLinkInProgressStartLL; ++ u8 BtCurrentPhyLinkhandle; ++ u16 BtCurrentLogLinkhandle; ++ u8 CurrentConnectEntryNum; ++ u8 DisconnectEntryNum; ++ u8 CurrentBTConnectionCnt; ++ BT_CONNECT_TYPE BTCurrentConnectType; ++ BT_CONNECT_TYPE BTReceiveConnectPkt; ++ u8 BTAuthCount; ++ u8 BTAsocCount; ++ u8 bStartSendSupervisionPkt; ++ u8 BtOperationOn; ++ u8 BTNeedAMPStatusChg; ++ u8 JoinerNeedSendAuth; ++ HCI_PHY_LINK_BSS_INFO bssDesc; ++ HCI_EXT_CONFIG ExtConfig; ++ u8 bNeedNotifyAMPNoCap; ++ u8 bCreateSpportQos; ++ u8 bSupportProfile; ++ u8 BTChannel; ++ u8 CheckChnlIsSuit; ++ u8 bBtScan; ++ u8 btLogoTest; ++} BT_MGNT, *PBT_MGNT; ++ ++typedef struct _BT_HCI_DBG_INFO ++{ ++ u32 hciCmdCnt; ++ u32 hciCmdCntUnknown; ++ u32 hciCmdCntCreatePhyLink; ++ u32 hciCmdCntAcceptPhyLink; ++ u32 hciCmdCntDisconnectPhyLink; ++ u32 hciCmdPhyLinkStatus; ++ u32 hciCmdCntCreateLogLink; ++ u32 hciCmdCntAcceptLogLink; ++ u32 hciCmdCntDisconnectLogLink; ++ u32 hciCmdCntReadLocalAmpAssoc; ++ u32 hciCmdCntWriteRemoteAmpAssoc; ++ u32 hciCmdCntSetAclLinkStatus; ++ u32 hciCmdCntSetScoLinkStatus; ++ u32 hciCmdCntExtensionVersionNotify; ++ u32 hciCmdCntLinkStatusNotify; ++} BT_HCI_DBG_INFO, *PBT_HCI_DBG_INFO; ++ ++typedef struct _BT_IRP_DBG_INFO ++{ ++ u32 irpMJCreate; ++ // Io Control ++ u32 irpIoControl; ++ u32 irpIoCtrlHciCmd; ++ u32 irpIoCtrlHciEvent; ++ u32 irpIoCtrlHciTxData; ++ u32 irpIoCtrlHciRxData; ++ u32 irpIoCtrlUnknown; ++ ++ u32 irpIoCtrlHciTxData1s; ++} BT_IRP_DBG_INFO, *PBT_IRP_DBG_INFO; ++ ++typedef struct _BT_PACKET_DBG_INFO ++{ ++ u32 btPktTxProbReq; ++ u32 btPktRxProbReq; ++ u32 btPktRxProbReqFail; ++ u32 btPktTxProbRsp; ++ u32 btPktRxProbRsp; ++ u32 btPktTxAuth; ++ u32 btPktRxAuth; ++ u32 btPktRxAuthButDrop; ++ u32 btPktTxAssocReq; ++ u32 btPktRxAssocReq; ++ u32 btPktRxAssocReqButDrop; ++ u32 btPktTxAssocRsp; ++ u32 btPktRxAssocRsp; ++ u32 btPktTxDisassoc; ++ u32 btPktRxDisassoc; ++ u32 btPktRxDeauth; ++ u32 btPktTx4way1st; ++ u32 btPktRx4way1st; ++ u32 btPktTx4way2nd; ++ u32 btPktRx4way2nd; ++ u32 btPktTx4way3rd; ++ u32 btPktRx4way3rd; ++ u32 btPktTx4way4th; ++ u32 btPktRx4way4th; ++ u32 btPktTxLinkSuperReq; ++ u32 btPktRxLinkSuperReq; ++ u32 btPktTxLinkSuperRsp; ++ u32 btPktRxLinkSuperRsp; ++ u32 btPktTxData; ++ u32 btPktRxData; ++} BT_PACKET_DBG_INFO, *PBT_PACKET_DBG_INFO; ++ ++typedef struct _BT_DBG ++{ ++ u8 dbgCtrl; ++ u32 dbgProfile; ++ BT_HCI_DBG_INFO dbgHciInfo; ++ BT_IRP_DBG_INFO dbgIrpInfo; ++ BT_PACKET_DBG_INFO dbgBtPkt; ++} BT_DBG, *PBT_DBG; ++ ++typedef struct _BT_HCI_INFO ++{ ++ //802.11 Pal version specifier ++ u8 BTPalVersion; ++ u16 BTPalCompanyID; ++ u16 BTPalsubversion; ++ ++ //Connected channel list ++ u16 BTConnectChnlListLen; ++ u8 BTConnectChnllist[64]; ++ ++ //Fail contact counter ++ u16 FailContactCount; ++ ++ //Event mask ++ u64 BTEventMask; ++ u64 BTEventMaskPage2; ++ ++ //timeout var ++ u16 ConnAcceptTimeout; ++ u16 LogicalAcceptTimeout; ++ u16 PageTimeout; ++ ++ u8 LocationDomainAware; ++ u16 LocationDomain; ++ u8 LocationDomainOptions; ++ u8 LocationOptions; ++ ++ u8 FlowControlMode; ++ ++ //Preferred channel list ++ u16 BtPreChnlListLen; ++ u8 BTPreChnllist[64]; ++ ++ u16 enFlush_LLH; //enhanced flush handle ++ u16 FLTO_LLH; //enhanced flush handle ++ ++ //========================================== ++ //Test command only. ++ u8 bInTestMode; ++ u8 bTestIsEnd; ++ u8 bTestNeedReport; ++ u8 TestScenario; ++ u8 TestReportInterval; ++ u8 TestCtrType; ++ u32 TestEventType; ++ u16 TestNumOfFrame; ++ u16 TestNumOfErrFrame; ++ u16 TestNumOfBits; ++ u16 TestNumOfErrBits; ++ //========================================== ++} BT_HCI_INFO, *PBT_HCI_INFO; ++ ++typedef struct _BT_TRAFFIC ++{ ++ // Add for check replay data ++ u8 LastRxUniFragNum; ++ u16 LastRxUniSeqNum; ++ ++ //s32 EntryMaxUndecoratedSmoothedPWDB; ++ //s32 EntryMinUndecoratedSmoothedPWDB; ++ ++ BT_TRAFFIC_STATISTICS Bt30TrafficStatistics; ++} BT_TRAFFIC, *PBT_TRAFFIC; ++ ++#define RT_WORK_ITEM _workitem ++#define RT_THREAD _thread_hdl_ ++ ++typedef struct _BT_SECURITY ++{ ++ // WPA auth state ++ // May need to remove to BTSecInfo ... ++ //BT_STATE_WPA_AUTH BTWPAAuthState; ++ //u8 PMK[PMK_LEN]; ++ RT_TIMER BTWPAAuthTimer; ++ OCTET_STRING RSNIE; ++ u8 RSNIEBuf[MAXRSNIELEN]; ++ u8 bRegNoEncrypt; ++ u8 bUsedHwEncrypt; // It is define by OS version !! ++} BT_SECURITY, *PBT_SECURITY; ++ ++typedef struct _BT30Info ++{ ++ PADAPTER padapter; ++ BT_ASOC_ENTRY BtAsocEntry[MAX_BT_ASOC_ENTRY_NUM]; ++ BT_MGNT BtMgnt; ++ BT_DBG BtDbg; ++ BT_HCI_INFO BtHciInfo; ++ BT_TRAFFIC BtTraffic; ++ BT_SECURITY BtSec; ++ ++#if(BT_THREAD == 0) ++ RT_WORK_ITEM HCICmdWorkItem; ++ RT_TIMER BTHCICmdTimer; ++#endif ++#if (SENDTXMEHTOD==0) ++ RT_WORK_ITEM HCISendACLDataWorkItem; ++ RT_TIMER BTHCISendAclDataTimer; ++#elif(SENDTXMEHTOD==2) ++ RT_THREAD BTTxThread; ++#endif ++ RT_WORK_ITEM BTPsDisableWorkItem; ++ RT_WORK_ITEM BTConnectWorkItem; ++ RT_TIMER BTHCIDiscardAclDataTimer; ++ RT_TIMER BTHCIJoinTimeoutTimer; ++ RT_TIMER BTTestSendPacketTimer; ++ RT_TIMER BTSupervisionPktTimer; ++ RT_TIMER BTDisconnectPhyLinkTimer; ++ RT_TIMER BTBeaconTimer; ++ u8 BTBeaconTmrOn; ++ ++ RT_TIMER BTPsDisableTimer; ++ RT_TIMER BTAuthTimeoutTimer; ++ RT_TIMER BTAsocTimeoutTimer; ++ ++ PVOID pBtChnlList; ++}BT30Info, *PBT30Info; ++ ++typedef struct _PACKET_IRP_ACL_DATA ++{ ++ u16 Handle:12; ++ u16 PB_Flag:2; ++ u16 BC_Flag:2; ++ u16 Length; ++ u8 Data[1]; ++} PACKET_IRP_ACL_DATA, *PPACKET_IRP_ACL_DATA; ++ ++typedef struct _PACKET_IRP_HCIEVENT_DATA ++{ ++ u8 EventCode; ++ u8 Length; ++ u8 Data[1]; ++} PACKET_IRP_HCIEVENT_DATA, *PPACKET_IRP_HCIEVENT_DATA; ++ ++typedef struct _COMMON_TRIPLE ++{ ++ u8 byte_1st; ++ u8 byte_2nd; ++ u8 byte_3rd; ++} COMMON_TRIPLE, *PCOMMON_TRIPLE; ++ ++#define COUNTRY_STR_LEN 3 // country string len=3 ++ ++#define LOCAL_PMK 0 ++ ++typedef enum _HCI_WIFI_CONNECT_STATUS ++{ ++ HCI_WIFI_NOT_CONNECTED =0x0, ++ HCI_WIFI_CONNECTED =0x1, ++ HCI_WIFI_CONNECT_IN_PROGRESS =0x2, ++} HCI_WIFI_CONNECT_STATUS, *PHCI_WIFI_CONNECT_STATUS; ++ ++typedef enum _HCI_EXT_BT_OPERATION ++{ ++ HCI_BT_OP_NONE = 0x0, ++ HCI_BT_OP_INQUIRY_START = 0x1, ++ HCI_BT_OP_INQUIRY_FINISH = 0x2, ++ HCI_BT_OP_PAGING_START = 0x3, ++ HCI_BT_OP_PAGING_SUCCESS = 0x4, ++ HCI_BT_OP_PAGING_UNSUCCESS = 0x5, ++ HCI_BT_OP_PAIRING_START = 0x6, ++ HCI_BT_OP_PAIRING_FINISH = 0x7, ++ HCI_BT_OP_BT_DEV_ENABLE = 0x8, ++ HCI_BT_OP_BT_DEV_DISABLE = 0x9, ++ HCI_BT_OP_MAX ++} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION; ++ ++//====================================== ++// Function proto type ++//====================================== ++#define RT_LIST_ENTRY _list ++typedef struct _BTData_ENTRY ++{ ++ RT_LIST_ENTRY List; ++ void *pDataBlock; ++} BTData_ENTRY, *PBTData_ENTRY; ++ ++#define BTHCI_SM_WITH_INFO(_Adapter, _StateToEnter, _StateCmd, _EntryNum) \ ++{ \ ++ RTPRINT(FIOCTL, IOCTL_STATE, ("[BT state change] caused by ""%s"", line=%d\n", __FUNCTION__, __LINE__)); \ ++ BTHCI_StateMachine(_Adapter, _StateToEnter, _StateCmd, _EntryNum);\ ++} ++ ++void BTHCI_EventParse(PADAPTER padapter, void *pEvntData, u32 dataLen); ++#define BT_EventParse BTHCI_EventParse ++u8 BTHCI_HsConnectionEstablished(PADAPTER padapter); ++void BTHCI_UpdateBTProfileRTKToMoto(PADAPTER padapter); ++void BTHCI_WifiScanNotify(PADAPTER padapter, u8 scanType); ++void BTHCI_StateMachine(PADAPTER padapter, u8 StateToEnter, HCI_STATE_WITH_CMD StateCmd, u8 EntryNum); ++void BTHCI_DisconnectPeer(PADAPTER padapter, u8 EntryNum); ++void BTHCI_EventNumOfCompletedDataBlocks(PADAPTER padapter); ++void BTHCI_EventAMPStatusChange(PADAPTER padapter, u8 AMP_Status); ++void BTHCI_DisconnectAll(PADAPTER padapter); ++HCI_STATUS BTHCI_HandleHCICMD(PADAPTER padapter, PPACKET_IRP_HCICMD_DATA pHciCmd); ++ ++// ===== End of sync from SD7 driver COMMON/bt_hci.h ===== ++#endif // __BT_HCI_C__ ++ ++#ifdef __HALBTC87231ANT_C__ // HAL/BTCoexist/HalBtc87231Ant.h ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc87231Ant.h ===== ++#define GET_BT_INFO(padapter) (&GET_HAL_DATA(padapter)->BtInfo) ++ ++#define BTC_FOR_SCAN_START 1 ++#define BTC_FOR_SCAN_FINISH 0 ++ ++#define BT_TXRX_CNT_THRES_1 1200 ++#define BT_TXRX_CNT_THRES_2 1400 ++#define BT_TXRX_CNT_THRES_3 3000 ++#define BT_TXRX_CNT_LEVEL_0 0 // < 1200 ++#define BT_TXRX_CNT_LEVEL_1 1 // >= 1200 && < 1400 ++#define BT_TXRX_CNT_LEVEL_2 2 // >= 1400 ++#define BT_TXRX_CNT_LEVEL_3 3 // >= 3000 ++ ++typedef enum _BT_STATE_1ANT{ ++ BT_INFO_STATE_DISABLED = 0, ++ BT_INFO_STATE_NO_CONNECTION = 1, ++ BT_INFO_STATE_CONNECT_IDLE = 2, ++ BT_INFO_STATE_INQ_OR_PAG = 3, ++ BT_INFO_STATE_ACL_ONLY_BUSY = 4, ++ BT_INFO_STATE_SCO_ONLY_BUSY = 5, ++ BT_INFO_STATE_ACL_SCO_BUSY = 6, ++ BT_INFO_STATE_ACL_INQ_OR_PAG = 7, ++ BT_INFO_STATE_MAX = 8 ++} BT_STATE_1ANT, *PBT_STATE_1ANT; ++ ++typedef struct _BTDM_8723A_1ANT ++{ ++ u8 prePsTdma; ++ u8 curPsTdma; ++ u8 psTdmaDuAdjType; ++ u8 bPrePsTdmaOn; ++ u8 bCurPsTdmaOn; ++ u8 preWifiPara; ++ u8 curWifiPara; ++ u8 preCoexWifiCon; ++ u8 curCoexWifiCon; ++ u8 wifiRssiThresh; ++ ++ u32 psTdmaMonitorCnt; ++ u32 psTdmaGlobalCnt; ++ ++ //DurationAdjust For SCO ++ u32 psTdmaMonitorCntForSCO; ++ u8 psTdmaDuAdjTypeForSCO; ++ u8 RSSI_WiFi_Last; ++ u8 RSSI_BT_Last; ++ ++ u8 bWiFiHalt; ++ u8 bRAChanged; ++} BTDM_8723A_1ANT, *PBTDM_8723A_1ANT; ++ ++void BTDM_1AntSignalCompensation(PADAPTER padapter, u8 *rssi_wifi, u8 *rssi_bt); ++void BTDM_1AntForDhcp(PADAPTER padapter); ++void BTDM_1AntBtCoexist8723A(PADAPTER padapter); ++ ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc87231Ant.h ===== ++#endif // __HALBTC87231ANT_C__ ++ ++#ifdef __HALBTC87232ANT_C__ // HAL/BTCoexist/HalBtc87232Ant.h ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc87232Ant.h ===== ++typedef enum _BT_2ANT_BT_STATUS{ ++ BT_2ANT_BT_STATUS_IDLE = 0x0, ++ BT_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, ++ BT_2ANT_BT_STATUS_NON_IDLE = 0x2, ++ BT_2ANT_BT_STATUS_MAX ++}BT_2ANT_BT_STATUS,*PBT_2ANT_BT_STATUS; ++ ++typedef enum _BT_2ANT_COEX_ALGO{ ++ BT_2ANT_COEX_ALGO_UNDEFINED = 0x0, ++ BT_2ANT_COEX_ALGO_SCO = 0x1, ++ BT_2ANT_COEX_ALGO_HID = 0x2, ++ BT_2ANT_COEX_ALGO_A2DP = 0x3, ++ BT_2ANT_COEX_ALGO_PANEDR = 0x4, ++ BT_2ANT_COEX_ALGO_PANHS = 0x5, ++ BT_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6, ++ BT_2ANT_COEX_ALGO_PANEDR_HID = 0x7, ++ BT_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, ++ BT_2ANT_COEX_ALGO_HID_A2DP = 0x9, ++ BT_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xA, ++ BT_2ANT_COEX_ALGO_MAX = 0xB, ++}BT_2ANT_COEX_ALGO,*PBT_2ANT_COEX_ALGO; ++ ++typedef struct _BTDM_8723A_2ANT ++{ ++ u8 bPreDecBtPwr; ++ u8 bCurDecBtPwr; ++ ++ u8 preWlanActHi; ++ u8 curWlanActHi; ++ u8 preWlanActLo; ++ u8 curWlanActLo; ++ ++ u8 preFwDacSwingLvl; ++ u8 curFwDacSwingLvl; ++ ++ u8 bPreRfRxLpfShrink; ++ u8 bCurRfRxLpfShrink; ++ ++ u8 bPreLowPenaltyRa; ++ u8 bCurLowPenaltyRa; ++ ++ u8 preBtRetryIndex; ++ u8 curBtRetryIndex; ++ ++ u8 bPreDacSwingOn; ++ u32 preDacSwingLvl; ++ u8 bCurDacSwingOn; ++ u32 curDacSwingLvl; ++ ++ u8 bPreAdcBackOff; ++ u8 bCurAdcBackOff; ++ ++ u8 bPreAgcTableEn; ++ u8 bCurAgcTableEn; ++ ++ u32 preVal0x6c0; ++ u32 curVal0x6c0; ++ u32 preVal0x6c8; ++ u32 curVal0x6c8; ++ u8 preVal0x6cc; ++ u8 curVal0x6cc; ++ ++ u8 bCurIgnoreWlanAct; ++ u8 bPreIgnoreWlanAct; ++ ++ u8 prePsTdma; ++ u8 curPsTdma; ++ u8 psTdmaDuAdjType; ++ u8 bPrePsTdmaOn; ++ u8 bCurPsTdmaOn; ++ ++ u8 preAlgorithm; ++ u8 curAlgorithm; ++ u8 bResetTdmaAdjust; ++ ++ ++ u8 btStatus; ++} BTDM_8723A_2ANT, *PBTDM_8723A_2ANT; ++void BTDM_2AntBtCoexist8723A(PADAPTER padapter); ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc87232Ant.h ===== ++#endif // __HALBTC87232ANT_C__ ++ ++#ifdef __HALBTC8723_C__ // HAL/BTCoexist/HalBtc8723.h ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc8723.h ===== ++ ++#define BT_Q_PKT_OFF 0 ++#define BT_Q_PKT_ON 1 ++ ++#define BT_TX_PWR_OFF 0 ++#define BT_TX_PWR_ON 1 ++ ++// TDMA mode definition ++#define TDMA_2ANT 0 ++#define TDMA_1ANT 1 ++#define TDMA_NAV_OFF 0 ++#define TDMA_NAV_ON 1 ++#define TDMA_DAC_SWING_OFF 0 ++#define TDMA_DAC_SWING_ON 1 ++ ++#define BT_RSSI_LEVEL_H 0 ++#define BT_RSSI_LEVEL_M 1 ++#define BT_RSSI_LEVEL_L 2 ++ ++// PTA mode related definition ++#define BT_PTA_MODE_OFF 0 ++#define BT_PTA_MODE_ON 1 ++ ++// Penalty Tx Rate Adaptive ++#define BT_TX_RATE_ADAPTIVE_NORMAL 0 ++#define BT_TX_RATE_ADAPTIVE_LOW_PENALTY 1 ++ ++// RF Corner ++#define BT_RF_RX_LPF_CORNER_RESUME 0 ++#define BT_RF_RX_LPF_CORNER_SHRINK 1 ++ ++#define BT_INFO_ACL BIT(0) ++#define BT_INFO_SCO BIT(1) ++#define BT_INFO_INQ_PAG BIT(2) ++#define BT_INFO_ACL_BUSY BIT(3) ++#define BT_INFO_SCO_BUSY BIT(4) ++#define BT_INFO_HID BIT(5) ++#define BT_INFO_A2DP BIT(6) ++#define BT_INFO_FTP BIT(7) ++ ++ ++ ++typedef struct _BT_COEXIST_8723A ++{ ++ u32 highPriorityTx; ++ u32 highPriorityRx; ++ u32 lowPriorityTx; ++ u32 lowPriorityRx; ++ u8 btRssi; ++ u8 TotalAntNum; ++ u8 bC2hBtInfoSupport; ++ u8 c2hBtInfo; ++ u8 c2hBtInfoOriginal; ++ u8 prec2hBtInfo; // for 1Ant ++ u8 bC2hBtInquiryPage; ++ u64 btInqPageStartTime; // for 2Ant ++ u8 c2hBtProfile; // for 1Ant ++ u8 btRetryCnt; ++ u16 AclTp; ++ u8 btInfoExt; ++ u8 bC2hBtInfoReqSent; ++ u8 bForceFwBtInfo; ++ u8 bForceA2dpSink; ++// u8 bForceLps; ++// u8 bBtPwrSaveMode; ++ BTDM_8723A_2ANT btdm2Ant; ++ BTDM_8723A_1ANT btdm1Ant; ++} BT_COEXIST_8723A, *PBT_COEXIST_8723A; ++ ++void BTDM_SetFwChnlInfo(PADAPTER padapter, RT_MEDIA_STATUS mstatus); ++u8 BTDM_IsWifiConnectionExist(PADAPTER padapter); ++void BTDM_SetFw3a(PADAPTER padapter, u8 byte1, u8 byte2, u8 byte3, u8 byte4, u8 byte5); ++void BTDM_QueryBtInformation(PADAPTER padapter); ++void BTDM_SetSwRfRxLpfCorner(PADAPTER padapter, u8 type); ++void BTDM_SetSwPenaltyTxRateAdaptive(PADAPTER padapter, u8 raType); ++void BTDM_SetFwDecBtPwr(PADAPTER padapter, u8 bDecBtPwr); ++u8 BTDM_BtProfileSupport(PADAPTER padapter); ++void BTDM_LpsLeave(PADAPTER padapter); ++u8 BTDM_1Ant8723A(PADAPTER padapter); ++u8 BTDM_GetBtState8723A(PADAPTER padapter); ++u8 BTDM_IsBtInquiryPage8723A(PADAPTER padapter); ++#define BT_1Ant BTDM_1Ant8723A ++#define BT_GetBtState BTDM_GetBtState8723A ++#define BT_IsBtInquiryPage BTDM_IsBtInquiryPage8723A ++ ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc8723.h ===== ++#endif // __HALBTC8723_C__ ++ ++#ifdef __HALBTCCSR1ANT_C__ // HAL/BTCoexist/HalBtcCsr1Ant.h ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtcCsr1Ant.h ===== ++ ++enum BT_A2DP_INDEX{ ++ BT_A2DP_INDEX0 =0, // 32,12; the most critical for BT ++ BT_A2DP_INDEX1, // 12,24 ++ BT_A2DP_INDEX2, // 0,0 ++ BT_A2DP_INDEX_MAX ++}; ++ ++#define BT_A2DP_STATE_NOT_ENTERED 0 ++#define BT_A2DP_STATE_DETECTING 1 ++#define BT_A2DP_STATE_DETECTED 2 ++ ++#define BTDM_ANT_BT_IDLE 0 ++#define BTDM_ANT_WIFI 1 ++#define BTDM_ANT_BT 2 ++ ++ ++void BTDM_SingleAnt(PADAPTER padapter, u8 bSingleAntOn, u8 bInterruptOn, u8 bMultiNAVOn); ++void BTDM_CheckBTIdleChange1Ant(PADAPTER padapter); ++ ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtcCsr1Ant.h ===== ++#endif // __HALBTCCSR1ANT_C__ ++ ++#ifdef __HALBTCCSR2ANT_C__ // HAL/BTCoexist/HalBtcCsr2Ant.h ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtcCsr2Ant.h ===== ++ ++//=========================================== ++// For old core stack before v251 ++//=========================================== ++#define BT_RSSI_STATE_NORMAL_POWER BIT0 ++#define BT_RSSI_STATE_AMDPU_OFF BIT1 ++#define BT_RSSI_STATE_SPECIAL_LOW BIT2 ++#define BT_RSSI_STATE_BG_EDCA_LOW BIT3 ++#define BT_RSSI_STATE_TXPOWER_LOW BIT4 ++ ++#define BT_DACSWING_OFF 0 ++#define BT_DACSWING_M4 1 ++#define BT_DACSWING_M7 2 ++#define BT_DACSWING_M10 3 ++ ++void BTDM_DiminishWiFi(PADAPTER Adapter, u8 bDACOn, u8 bInterruptOn, u8 DACSwingLevel, u8 bNAVOn); ++ ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtcCsr2Ant.h ===== ++#endif // __HALBTCCSR2ANT_C__ ++ ++#ifdef __HALBTCOEXIST_C__ // HAL/BTCoexist/HalBtCoexist.h ++ ++// HEADER/TypeDef.h ++#define MAX_FW_SUPPORT_MACID_NUM 64 ++#define WIFI_BUSY_TRAFFIC_TH 25 ++ ++// ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtCoexist.h ===== ++ ++#define FW_VER_BT_REG 62 ++#define FW_VER_BT_REG1 74 ++#define REG_BT_ACTIVE 0x444 ++#define REG_BT_STATE 0x448 ++#define REG_BT_POLLING1 0x44c ++#define REG_BT_POLLING 0x700 ++ ++#define REG_BT_ACTIVE_OLD 0x488 ++#define REG_BT_STATE_OLD 0x48c ++#define REG_BT_POLLING_OLD 0x490 ++ ++// The reg define is for 8723 ++#define REG_HIGH_PRIORITY_TXRX 0x770 ++#define REG_LOW_PRIORITY_TXRX 0x774 ++ ++#define BT_FW_COEX_THRESH_TOL 6 ++#define BT_FW_COEX_THRESH_20 20 ++#define BT_FW_COEX_THRESH_23 23 ++#define BT_FW_COEX_THRESH_25 25 ++#define BT_FW_COEX_THRESH_30 30 ++#define BT_FW_COEX_THRESH_35 35 ++#define BT_FW_COEX_THRESH_40 40 ++#define BT_FW_COEX_THRESH_45 45 ++#define BT_FW_COEX_THRESH_47 47 ++#define BT_FW_COEX_THRESH_50 50 ++#define BT_FW_COEX_THRESH_55 55 ++#define BT_FW_COEX_THRESH_65 65 ++ ++#define BT_COEX_STATE_BT30 BIT(0) ++#define BT_COEX_STATE_WIFI_HT20 BIT(1) ++#define BT_COEX_STATE_WIFI_HT40 BIT(2) ++#define BT_COEX_STATE_WIFI_LEGACY BIT(3) ++ ++#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4) ++#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5) ++#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6) ++#define BT_COEX_STATE_DEC_BT_POWER BIT(7) ++ ++#define BT_COEX_STATE_WIFI_IDLE BIT(8) ++#define BT_COEX_STATE_WIFI_UPLINK BIT(9) ++#define BT_COEX_STATE_WIFI_DOWNLINK BIT(10) ++ ++#define BT_COEX_STATE_BT_INQ_PAGE BIT(11) ++#define BT_COEX_STATE_BT_IDLE BIT(12) ++#define BT_COEX_STATE_BT_UPLINK BIT(13) ++#define BT_COEX_STATE_BT_DOWNLINK BIT(14) ++//=========================================== ++// Todo: Remove these definitions ++#define BT_COEX_STATE_BT_PAN_IDLE BIT(15) ++#define BT_COEX_STATE_BT_PAN_UPLINK BIT(16) ++#define BT_COEX_STATE_BT_PAN_DOWNLINK BIT(17) ++#define BT_COEX_STATE_BT_A2DP_IDLE BIT(18) ++//=========================================== ++#define BT_COEX_STATE_BT_RSSI_LOW BIT(19) ++ ++#define BT_COEX_STATE_PROFILE_HID BIT(20) ++#define BT_COEX_STATE_PROFILE_A2DP BIT(21) ++#define BT_COEX_STATE_PROFILE_PAN BIT(22) ++#define BT_COEX_STATE_PROFILE_SCO BIT(23) ++ ++#define BT_COEX_STATE_WIFI_RSSI_1_LOW BIT(24) ++#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25) ++#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26) ++ ++#define BT_COEX_STATE_WIFI_RSSI_BEACON_LOW BIT(27) ++#define BT_COEX_STATE_WIFI_RSSI_BEACON_MEDIUM BIT(28) ++#define BT_COEX_STATE_WIFI_RSSI_BEACON_HIGH BIT(29) ++ ++ ++#define BT_COEX_STATE_BTINFO_COMMON BIT30 ++#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT31 ++#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT32 ++ ++#define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT33 ++#define BT_COEX_STATE_BT_CNT_LEVEL_1 BIT34 ++#define BT_COEX_STATE_BT_CNT_LEVEL_2 BIT35 ++#define BT_COEX_STATE_BT_CNT_LEVEL_3 BIT36 ++ ++#define BT_RSSI_STATE_HIGH 0 ++#define BT_RSSI_STATE_MEDIUM 1 ++#define BT_RSSI_STATE_LOW 2 ++#define BT_RSSI_STATE_STAY_HIGH 3 ++#define BT_RSSI_STATE_STAY_MEDIUM 4 ++#define BT_RSSI_STATE_STAY_LOW 5 ++ ++ ++ ++#define BT_AGCTABLE_OFF 0 ++#define BT_AGCTABLE_ON 1 ++ ++#define BT_BB_BACKOFF_OFF 0 ++#define BT_BB_BACKOFF_ON 1 ++ ++#define BT_FW_NAV_OFF 0 ++#define BT_FW_NAV_ON 1 ++ ++ ++#define BT_COEX_MECH_NONE 0 ++#define BT_COEX_MECH_SCO 1 ++#define BT_COEX_MECH_HID 2 ++#define BT_COEX_MECH_A2DP 3 ++#define BT_COEX_MECH_PAN 4 ++#define BT_COEX_MECH_HID_A2DP 5 ++#define BT_COEX_MECH_HID_PAN 6 ++#define BT_COEX_MECH_PAN_A2DP 7 ++#define BT_COEX_MECH_HID_SCO_ESCO 8 ++#define BT_COEX_MECH_FTP_A2DP 9 ++#define BT_COEX_MECH_COMMON 10 ++#define BT_COEX_MECH_MAX 11 ++//=========================================== ++// BT Dbg Ctrl ++//=========================================== ++#define BT_DBG_PROFILE_NONE 0 ++#define BT_DBG_PROFILE_SCO 1 ++#define BT_DBG_PROFILE_HID 2 ++#define BT_DBG_PROFILE_A2DP 3 ++#define BT_DBG_PROFILE_PAN 4 ++#define BT_DBG_PROFILE_HID_A2DP 5 ++#define BT_DBG_PROFILE_HID_PAN 6 ++#define BT_DBG_PROFILE_PAN_A2DP 7 ++#define BT_DBG_PROFILE_MAX 9 ++//=========================================== ++ ++typedef struct _BT_COEXIST_STR ++{ ++ u8 BluetoothCoexist; ++ u8 BT_Ant_Num; ++ u8 BT_CoexistType; ++ u8 BT_Ant_isolation; //0:good, 1:bad ++ u8 BT_RadioSharedType; ++ u32 Ratio_Tx; ++ u32 Ratio_PRI; ++ u8 bInitlized; ++ u32 BtRfRegOrigin1E; ++ u32 BtRfRegOrigin1F; ++ u8 bBTBusyTraffic; ++ u8 bBTTrafficModeSet; ++ u8 bBTNonTrafficModeSet; ++ BT_TRAFFIC_STATISTICS BT21TrafficStatistics; ++ u64 CurrentState; ++ u64 PreviousState; ++ u8 preRssiState; ++ u8 preRssiState1; ++ u8 preRssiStateBeacon; ++ u8 bFWCoexistAllOff; ++ u8 bSWCoexistAllOff; ++ u8 bHWCoexistAllOff; ++ u8 bBalanceOn; ++ u8 bSingleAntOn; ++ u8 bInterruptOn; ++ u8 bMultiNAVOn; ++ u8 PreWLANActH; ++ u8 PreWLANActL; ++ u8 WLANActH; ++ u8 WLANActL; ++ u8 A2DPState; ++ u8 AntennaState; ++ u32 lastBtEdca; ++ u16 last_aggr_num; ++ u8 bEDCAInitialized; ++ u8 exec_cnt; ++ u8 b8723aAgcTableOn; ++ u8 b92DAgcTableOn; ++ BT_COEXIST_8723A halCoex8723; ++ u8 btActiveZeroCnt; ++ u8 bCurBtDisabled; ++ u8 bPreBtDisabled; ++ u8 bNeedToRoamForBtDisableEnable; ++ u8 fw3aVal[5]; ++}BT_COEXIST_STR, *PBT_COEXIST_STR; ++ ++ ++void BTDM_CheckAntSelMode(PADAPTER padapter); ++void BTDM_FwC2hBtRssi(PADAPTER padapter, u8 *tmpBuf); ++#define BT_FwC2hBtRssi BTDM_FwC2hBtRssi ++void BTDM_FwC2hBtInfo(PADAPTER padapter, u8 *tmpBuf, u8 length); ++#define BT_FwC2hBtInfo BTDM_FwC2hBtInfo ++void BTDM_DisplayBtCoexInfo(PADAPTER padapter); ++#define BT_DisplayBtCoexInfo BTDM_DisplayBtCoexInfo ++void BTDM_RejectAPAggregatedPacket(PADAPTER padapter, u8 bReject); ++u8 BTDM_IsHT40(PADAPTER padapter); ++u8 BTDM_Legacy(PADAPTER padapter); ++void BTDM_CheckWiFiState(PADAPTER padapter); ++s32 BTDM_GetRxSS(PADAPTER padapter); ++u8 BTDM_CheckCoexBcnRssiState(PADAPTER padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); ++u8 BTDM_CheckCoexRSSIState1(PADAPTER padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); ++u8 BTDM_CheckCoexRSSIState(PADAPTER padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); ++u8 BTDM_DisableEDCATurbo(PADAPTER padapter); ++#define BT_DisableEDCATurbo BTDM_DisableEDCATurbo ++void BTDM_Balance(PADAPTER padapter, u8 bBalanceOn, u8 ms0, u8 ms1); ++void BTDM_AGCTable(PADAPTER padapter, u8 type); ++void BTDM_BBBackOffLevel(PADAPTER padapter, u8 type); ++void BTDM_FWCoexAllOff(PADAPTER padapter); ++void BTDM_SWCoexAllOff(PADAPTER padapter); ++void BTDM_HWCoexAllOff(PADAPTER padapter); ++void BTDM_CoexAllOff(PADAPTER padapter); ++void BTDM_TurnOffBtCoexistBeforeEnterIPS(PADAPTER padapter); ++void BTDM_SignalCompensation(PADAPTER padapter, u8 *rssi_wifi, u8 *rssi_bt); ++void BTDM_Coexist(PADAPTER padapter); ++#define BT_CoexistMechanism BTDM_Coexist ++void BTDM_UpdateCoexState(PADAPTER padapter); ++u8 BTDM_IsSameCoexistState(PADAPTER padapter); ++void BTDM_PWDBMonitor(PADAPTER padapter); ++u8 BTDM_IsBTBusy(PADAPTER padapter); ++#define BT_IsBtBusy BTDM_IsBTBusy ++u8 BTDM_IsWifiBusy(PADAPTER padapter); ++u8 BTDM_IsCoexistStateChanged(PADAPTER padapter); ++u8 BTDM_IsWifiUplink(PADAPTER padapter); ++u8 BTDM_IsWifiDownlink(PADAPTER padapter); ++u8 BTDM_IsBTHSMode(PADAPTER padapter); ++u8 BTDM_IsBTUplink(PADAPTER padapter); ++u8 BTDM_IsBTDownlink(PADAPTER padapter); ++void BTDM_AdjustForBtOperation(PADAPTER padapter); ++void BTDM_ForHalt(PADAPTER padapter); ++void BTDM_WifiScanNotify(PADAPTER padapter, u8 scanType); ++void BTDM_WifiAssociateNotify(PADAPTER padapter, u8 action); ++void BTDM_MediaStatusNotify(PADAPTER padapter, RT_MEDIA_STATUS mstatus); ++void BTDM_ForDhcp(PADAPTER padapter); ++void BTDM_ResetActionProfileState(PADAPTER padapter); ++void BTDM_SetBtCoexCurrAntNum(PADAPTER padapter, u8 antNum); ++#define BT_SetBtCoexCurrAntNum BTDM_SetBtCoexCurrAntNum ++u8 BTDM_IsActionSCO(PADAPTER padapter); ++u8 BTDM_IsActionHID(PADAPTER padapter); ++u8 BTDM_IsActionA2DP(PADAPTER padapter); ++u8 BTDM_IsActionPAN(PADAPTER padapter); ++u8 BTDM_IsActionHIDA2DP(PADAPTER padapter); ++u8 BTDM_IsActionHIDPAN(PADAPTER padapter); ++u8 BTDM_IsActionPANA2DP(PADAPTER padapter); ++u8 BTDM_IsBtDisabled(PADAPTER padapter); ++#define BT_IsBtDisabled BTDM_IsBtDisabled ++sint BTDM_CheckFWState(PADAPTER padapter, sint state); ++u32 BTDM_BtTxRxCounterH(PADAPTER padapter); ++u32 BTDM_BtTxRxCounterL(PADAPTER padapter); ++ ++// ===== End of sync from SD7 driver HAL/BTCoexist/HalBtCoexist.h ===== ++#endif // __HALBTCOEXIST_C__ ++ ++#ifdef __HALBT_C__ // HAL/HalBT.h ++// ===== Below this line is sync from SD7 driver HAL/HalBT.h ===== ++ ++#define RTS_CTS_NO_LEN_LIMIT 0 ++ ++u8 HALBT_GetPGAntNum(PADAPTER padapter); ++#define BT_GetPGAntNum HALBT_GetPGAntNum ++void HALBT_SetKey(PADAPTER padapter, u8 EntryNum); ++void HALBT_RemoveKey(PADAPTER padapter, u8 EntryNum); ++void HALBT_InitBTVars8723A(PADAPTER padapter); ++#define HALBT_InitHalVars HALBT_InitBTVars8723A ++#define BT_InitHalVars HALBT_InitHalVars ++u8 HALBT_IsBTExist(PADAPTER padapter); ++#define BT_IsBtExist HALBT_IsBTExist ++u8 HALBT_BTChipType(PADAPTER padapter); ++void HALBT_InitHwConfig(PADAPTER padapter); ++#define BT_InitHwConfig HALBT_InitHwConfig ++void HALBT_SetRtsCtsNoLenLimit(PADAPTER padapter); ++ ++// ===== End of sync from SD7 driver HAL/HalBT.c ===== ++#endif // __HALBT_C__ ++ ++#define _bt_dbg_off_ 0 ++#define _bt_dbg_on_ 1 ++ ++extern u32 BTCoexDbgLevel; ++ ++ ++ ++#endif // __RTL8723A_BT_COEXIST_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_cmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_cmd.h +new file mode 100644 +index 00000000..91202dc2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_cmd.h +@@ -0,0 +1,229 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_CMD_H__ ++#define __RTL8723A_CMD_H__ ++ ++ ++#define H2C_BT_FW_PATCH_LEN 3 ++#define H2C_BT_PWR_FORCE_LEN 3 ++ ++enum cmd_msg_element_id ++{ ++ NONE_CMDMSG_EID, ++ AP_OFFLOAD_EID = 0, ++ SET_PWRMODE_EID = 1, ++ JOINBSS_RPT_EID = 2, ++ RSVD_PAGE_EID = 3, ++ RSSI_4_EID = 4, ++ RSSI_SETTING_EID = 5, ++ MACID_CONFIG_EID = 6, ++ MACID_PS_MODE_EID = 7, ++ P2P_PS_OFFLOAD_EID = 8, ++ SELECTIVE_SUSPEND_ROF_CMD = 9, ++ BT_QUEUE_PKT_EID = 17, ++ BT_ANT_TDMA_EID = 20, ++ BT_2ANT_HID_EID = 21, ++ P2P_PS_CTW_CMD_EID = 32, ++ FORCE_BT_TX_PWR_EID = 33, ++ SET_TDMA_WLAN_ACT_TIME_EID = 34, ++ SET_BT_TX_RETRY_INDEX_EID = 35, ++ HID_PROFILE_ENABLE_EID = 36, ++ BT_IGNORE_WLAN_ACT_EID = 37, ++ BT_PTA_MANAGER_UPDATE_ENABLE_EID = 38, ++ DAC_SWING_VALUE_EID = 41, ++ TRADITIONAL_TDMA_EN_EID = 51, ++ H2C_BT_FW_PATCH = 54, ++ B_TYPE_TDMA_EID = 58, ++ SCAN_EN_EID = 59, ++ LOWPWR_LPS_EID = 71, ++ H2C_RESET_TSF = 75, ++ MAX_CMDMSG_EID ++}; ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++typedef struct _SETPWRMODE_PARM ++{ ++ u8 Mode; ++ u8 SmartPS; ++ u8 AwakeInterval; // unit: beacon interval ++ u8 bAllQueueUAPSD; ++ ++#if 0 ++ u8 LowRxBCN:1; ++ u8 AutoAntSwitch:1; ++ u8 PSAllowBTHighPriority:1; ++ u8 rsvd43:5; ++#else ++#define SETPM_LOWRXBCN BIT(0) ++#define SETPM_AUTOANTSWITCH BIT(1) ++#define SETPM_PSALLOWBTHIGHPRI BIT(2) ++ u8 BcnAntMode; ++#endif ++}__attribute__((__packed__)) SETPWRMODE_PARM, *PSETPWRMODE_PARM; ++ ++struct H2C_SS_RFOFF_PARAM{ ++ u8 ROFOn; // 1: on, 0:off ++ u16 gpio_period; // unit: 1024 us ++}__attribute__ ((packed)); ++ ++ ++typedef struct JOINBSSRPT_PARM{ ++ u8 OpMode; // RT_MEDIA_STATUS ++}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM; ++ ++typedef struct _RSVDPAGE_LOC { ++ u8 LocProbeRsp; ++ u8 LocPsPoll; ++ u8 LocNullData; ++ u8 LocQosNull; ++ u8 LocBTQosNull; ++} RSVDPAGE_LOC, *PRSVDPAGE_LOC; ++ ++struct P2P_PS_Offload_t { ++ u8 Offload_En:1; ++ u8 role:1; // 1: Owner, 0: Client ++ u8 CTWindow_En:1; ++ u8 NoA0_En:1; ++ u8 NoA1_En:1; ++ u8 AllStaSleep:1; // Only valid in Owner ++ u8 discovery:1; ++ u8 rsvd:1; ++}; ++ ++struct P2P_PS_CTWPeriod_t { ++ u8 CTWPeriod; //TU ++}; ++ ++ ++typedef struct _B_TYPE_TDMA_PARM ++{ ++#if 0 ++ u8 En:1; ++ u8 FixAntennaInBTSide:1; ++ u8 TxPspoll:1; ++ u8 val870:1; // value of 870, when disable ++ u8 AutoWakeUp:1; ++ u8 NoPS:1; ++ u8 WlanHighPriority:1; ++ u8 rsvd07:1; ++#else ++#define B_TDMA_EN BIT(0) ++#define B_TDMA_FIXANTINBT BIT(1) ++#define B_TDMA_TXPSPOLL BIT(2) ++#define B_TDMA_VAL870 BIT(3) ++#define B_TDMA_AUTOWAKEUP BIT(4) ++#define B_TDMA_NOPS BIT(5) ++#define B_TDMA_WLANHIGHPRI BIT(6) ++ u8 option; ++#endif ++ ++ u8 TBTTOnPeriod; ++ u8 MedPeriod; ++ u8 rsvd30; ++}__attribute__((__packed__)) B_TYPE_TDMA_PARM, *PB_TYPE_TDMA_PARM; ++ ++typedef struct _SCAN_EN_PARM { ++#if 0 ++ u8 En:1; ++ u8 rsvd01:7; ++#else ++ u8 En; ++#endif ++}__attribute__((__packed__)) SCAN_EN_PARM, *PSCAN_EN_PARM; ++ ++// BT_PWR ++#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value) ++ ++// BT_FW_PATCH ++#if 0 ++#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value) ++#else ++#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value) ++#endif ++ ++#if 0 ++/* ++ * H2C_LOWPWR_LPS ++ * h2c cmd = 71 ++ * byte1[6:0]= bcn count : how many bcn not recevied should return to old mechanism ++ * byte1[7] = enable : enable mechanism ++ * byte2=bcn period : bcn recv time of this AP, unit 32 us ++ * byte3= drop threshold : how many pkts be droped, rx dma should be release ++ * byte4 = max early period ++ * byte5 = max bcn timeout period ++ */ ++#define SET_H2CCMD_LOWPWR_LPS_BCN_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_TB_BCN_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_BCN_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_BCN_DROP_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_MAX_EARLY_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value) ++#define SET_H2CCMD_LOWPWR_LPS_MAX_BCN_TO_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value) ++#else ++typedef struct _LOWPWR_LPS_PARM ++{ ++ u8 bcn_count:4; ++ u8 tb_bcn_threshold:3; ++ u8 enable:1; ++ u8 bcn_interval; ++ u8 drop_threshold; ++ u8 max_early_period; ++ u8 max_bcn_timeout_period; ++}__attribute__((__packed__)) LOWPWR_LPS_PARM, *PLOWPWR_LPS_PARM; ++#endif ++ ++ ++// host message to firmware cmd ++void rtl8723a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); ++void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); ++#ifdef CONFIG_BT_COEXIST ++void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter); ++#endif ++u8 rtl8192c_set_rssi_cmd(PADAPTER padapter, u8 *param); ++//u8 rtl8723a_set_rssi_cmd(PADAPTER padapter, u8 *param); ++u8 rtl8192c_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg); ++//u8 rtl8723a_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg); ++void rtl8192c_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg, u8 rssi_level); ++//void rtl8723a_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg); ++u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); ++//u8 rtl8723a_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); ++ ++#ifdef CONFIG_P2P ++void rtl8192c_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); ++//void rtl8723a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++void CheckFwRsvdPageContent(PADAPTER padapter); ++ ++void rtl8723a_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt ); ++ ++#endif ++ ++#ifdef CONFIG_TSF_RESET_OFFLOAD ++u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port); ++#endif // CONFIG_TSF_RESET_OFFLOAD ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_dm.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_dm.h +new file mode 100644 +index 00000000..7b5da5ad +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_dm.h +@@ -0,0 +1,194 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_DM_H__ ++#define __RTL8723A_DM_H__ ++//============================================================ ++// Description: ++// ++// This file is for 8723A dynamic mechanism only ++// ++// ++//============================================================ ++#define DYNAMIC_FUNC_BT BIT(0) ++ ++enum{ ++ UP_LINK, ++ DOWN_LINK, ++}; ++//============================================================ ++// structure and define ++//============================================================ ++ ++//###### duplicate code,will move to ODM ######### ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 9 ++#define HP_THERMAL_NUM 8 ++//###### duplicate code,will move to ODM ######### ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag; ++ u8 InitDMFlag; ++ u32 InitODMFlag; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ int MinUndecoratedPWDBForDM; ++ int LastMinUndecoratedPWDBForDM; ++ ++ s32 UndecoratedSmoothedBeacon; ++ #ifdef CONFIG_BT_COEXIST ++ s32 BT_EntryMinUndecoratedSmoothedPWDB; ++ s32 BT_EntryMaxUndecoratedSmoothedPWDB; ++ #endif ++ ++//###### duplicate code,will move to ODM ######### ++/* ++ //for DIG ++ u8 bDMInitialGainEnable; ++ u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++*/ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ ++ //for tx power tracking ++ u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_DPK; ++ ++ u8 bRfPiEnable; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ u8 bDPdone; ++ u8 bDPPathAOK; ++ u8 bDPPathBOK; ++ ++ //for IQK ++ u32 RegC04; ++ u32 Reg874; ++ u32 RegC08; ++ u32 RegB68; ++ u32 RegB6C; ++ u32 Reg870; ++ u32 Reg860; ++ u32 Reg864; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup_recover[9]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ u8 PowerIndex_backup[6]; ++ ++ u8 bCCKinCH14; ++ ++ u8 CCK_index; ++ u8 OFDM_index[2]; ++ ++ u8 bDoneTxpower; ++ u8 CCK_index_HP; ++ u8 OFDM_index_HP[2]; ++ u8 ThermalValue_HP[HP_THERMAL_NUM]; ++ u8 ThermalValue_HP_index; ++ ++ //for TxPwrTracking ++ s32 RegE94; ++ s32 RegE9C; ++ s32 RegEB4; ++ s32 RegEBC; ++ ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++/* ++ // for dm_RF_Saving ++ u8 initialize; ++ u32 rf_saving_Reg874; ++ u32 rf_saving_RegC70; ++ u32 rf_saving_Reg85C; ++ u32 rf_saving_RegA74; ++*/ ++ //for Antenna diversity ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// SWAT_T DM_SWAT_Table; ++#endif ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++// _timer SwAntennaSwitchTimer; ++/* ++ u64 lastTxOkCnt; ++ u64 lastRxOkCnt; ++ u64 TXByteCnt_A; ++ u64 TXByteCnt_B; ++ u64 RXByteCnt_A; ++ u64 RXByteCnt_B; ++ u8 DoubleComfirm; ++ u8 TrafficLoad; ++*/ ++#endif ++ ++ s32 OFDM_Pkt_Cnt; ++ u8 RSSI_Select; ++// u8 DIG_Dynamic_MIN ; ++//###### duplicate code,will move to ODM ######### ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ u8 INIDATA_RATE[32]; ++}; ++ ++ ++//============================================================ ++// function prototype ++//============================================================ ++ ++void rtl8723a_init_dm_priv(PADAPTER padapter); ++void rtl8723a_deinit_dm_priv(PADAPTER padapter); ++ ++void rtl8723a_InitHalDm(PADAPTER padapter); ++void rtl8723a_HalDmWatchDog(PADAPTER padapter); ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_hal.h +new file mode 100644 +index 00000000..2111999b +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_hal.h +@@ -0,0 +1,849 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_HAL_H__ ++#define __RTL8723A_HAL_H__ ++ ++#include "rtl8723a_spec.h" ++#include "rtl8723a_pg.h" ++#include "Hal8723APhyReg.h" ++#include "Hal8723APhyCfg.h" ++#include "rtl8723a_rf.h" ++#ifdef CONFIG_BT_COEXIST ++#include "rtl8723a_bt-coexist.h" ++#endif ++#include "rtl8723a_dm.h" ++#include "rtl8723a_recv.h" ++#include "rtl8723a_xmit.h" ++#include "rtl8723a_cmd.h" ++#ifdef DBG_CONFIG_ERROR_DETECT ++#include "rtl8723a_sreset.h" ++#endif ++#include "rtw_efuse.h" ++ ++#include "../hal/OUTSRC/odm_precomp.h" ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ ++ //2TODO: We should define 8192S firmware related macro settings here!! ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++//--------------------------------------------------------------------- ++// RTL8723S From file ++//--------------------------------------------------------------------- ++ #define RTL8723_FW_UMC_IMG "rtl8723S\\rtl8723fw.bin" ++ #define RTL8723_FW_UMC_B_IMG "rtl8723S\\rtl8723fw_B.bin" ++ #define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt" ++ #define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt" ++ #define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt" ++ #define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt" ++ #define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt" ++ #define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt" ++ #define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8723S From header ++//--------------------------------------------------------------------- ++ ++ // Fw Array ++ #define Rtl8723_FwImageArray Rtl8723SFwImgArray ++ #define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723SFwUMCBCutImgArrayWithBT ++ #define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723SFwUMCBCutImgArrayWithoutBT ++ ++ #define Rtl8723_ImgArrayLength Rtl8723SImgArrayLength ++ #define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723SUMCBCutImgArrayWithBTLength ++ #define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723SUMCBCutImgArrayWithoutBTLength ++ ++ #define Rtl8723_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG ++ #define Rtl8723_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength ++#if MP_DRIVER == 1 ++ #define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray ++ #define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength ++ ++ #define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray ++ #define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength ++ ++ #define Rtl8723_PHY_REG_Array_MP Rtl8723SPHY_REG_Array_MP ++ #define Rtl8723_PHY_REG_Array_MPLength Rtl8723SPHY_REG_Array_MPLength ++#endif ++ ++#ifndef CONFIG_PHY_SETTING_WITH_ODM ++ // MAC/BB/PHY Array ++ #define Rtl8723_MAC_Array Rtl8723SMAC_2T_Array ++ //#define Rtl8723_AGCTAB_2TArray Rtl8723SAGCTAB_2TArray ++ #define Rtl8723_AGCTAB_1TArray Rtl8723SAGCTAB_1TArray ++ //#define Rtl8723_PHY_REG_2TArray Rtl8723SPHY_REG_2TArray ++ #define Rtl8723_PHY_REG_1TArray Rtl8723SPHY_REG_1TArray ++ //#define Rtl8723_RadioA_2TArray Rtl8723SRadioA_2TArray ++ #define Rtl8723_RadioA_1TArray Rtl8723SRadioA_1TArray ++ //#define Rtl8723_RadioB_2TArray Rtl8723SRadioB_2TArray ++ #define Rtl8723_RadioB_1TArray Rtl8723SRadioB_1TArray ++ ++ // Array length ++ #define Rtl8723_MAC_ArrayLength Rtl8723SMAC_2T_ArrayLength ++ #define Rtl8723_AGCTAB_1TArrayLength Rtl8723SAGCTAB_1TArrayLength ++ #define Rtl8723_PHY_REG_1TArrayLength Rtl8723SPHY_REG_1TArrayLength ++ ++ #define Rtl8723_RadioA_1TArrayLength Rtl8723SRadioA_1TArrayLength ++ #define Rtl8723_RadioB_1TArrayLength Rtl8723SRadioB_1TArrayLength ++#endif // CONFIG_PHY_SETTING_WITH_ODM ++#endif // CONFIG_SDIO_HCI ++ ++#ifdef CONFIG_USB_HCI ++ ++ //2TODO: We should define 8192S firmware related macro settings here!! ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++ //TODO: The following need to check!! ++ #define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin" ++ #define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin" ++ #define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt" ++ #define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt" ++ #define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt" ++ #define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt" ++ #define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt" ++ #define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt" ++ #define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8723S From header ++//--------------------------------------------------------------------- ++ ++ // Fw Array ++ #define Rtl8723_FwImageArray Rtl8723UFwImgArray ++ #define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723UFwUMCBCutImgArrayWithBT ++ #define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723UFwUMCBCutImgArrayWithoutBT ++ ++ #define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength ++ #define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723UUMCBCutImgArrayWithBTLength ++ #define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723UUMCBCutImgArrayWithoutBTLength ++ ++ #define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG ++ #define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength ++ ++#if MP_DRIVER == 1 ++ #define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray ++ #define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength ++ ++ #define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray ++ #define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength ++ ++ #define Rtl8723_PHY_REG_Array_MP Rtl8723UPHY_REG_Array_MP ++ #define Rtl8723_PHY_REG_Array_MPLength Rtl8723UPHY_REG_Array_MPLength ++#endif ++#ifndef CONFIG_PHY_SETTING_WITH_ODM ++ // MAC/BB/PHY Array ++ #define Rtl8723_MAC_Array Rtl8723UMAC_2T_Array ++ //#define Rtl8723_AGCTAB_2TArray Rtl8723UAGCTAB_2TArray ++ #define Rtl8723_AGCTAB_1TArray Rtl8723UAGCTAB_1TArray ++ //#define Rtl8723_PHY_REG_2TArray Rtl8723UPHY_REG_2TArray ++ #define Rtl8723_PHY_REG_1TArray Rtl8723UPHY_REG_1TArray ++ //#define Rtl8723_RadioA_2TArray Rtl8723URadioA_2TArray ++ #define Rtl8723_RadioA_1TArray Rtl8723URadioA_1TArray ++ //#define Rtl8723_RadioB_2TArray Rtl8723URadioB_2TArray ++ #define Rtl8723_RadioB_1TArray Rtl8723URadioB_1TArray ++ ++ ++ ++ // Array length ++ ++ #define Rtl8723_MAC_ArrayLength Rtl8723UMAC_2T_ArrayLength ++ #define Rtl8723_AGCTAB_1TArrayLength Rtl8723UAGCTAB_1TArrayLength ++ #define Rtl8723_PHY_REG_1TArrayLength Rtl8723UPHY_REG_1TArrayLength ++ ++ ++ #define Rtl8723_RadioA_1TArrayLength Rtl8723URadioA_1TArrayLength ++ #define Rtl8723_RadioB_1TArrayLength Rtl8723URadioB_1TArrayLength ++#endif ++#endif ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++#define FW_8723A_SIZE 0x8000 ++#define FW_8723A_START_ADDRESS 0x1000 ++#define FW_8723A_END_ADDRESS 0x1FFF //0x5FFF ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300) ++ ++typedef enum _FIRMWARE_SOURCE { ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE { ++ FIRMWARE_SOURCE eFWSource; ++#ifdef CONFIG_EMBEDDED_FWIMG ++ u8* szFwBuffer; ++#else ++ u8 szFwBuffer[FW_8723A_SIZE]; ++#endif ++ u32 ulFwLength; ++ ++#ifdef CONFIG_EMBEDDED_FWIMG ++ u8* szBTFwBuffer; ++#else ++ u8 szBTFwBuffer[FW_8723A_SIZE]; ++#endif ++ u32 ulBTFwLength; ++} RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_8723A, *PRT_FIRMWARE_8723A; ++ ++// ++// This structure must be cared byte-ordering ++// ++// Added by tynli. 2009.12.04. ++typedef struct _RT_8723A_FIRMWARE_HDR ++{ ++ // 8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u16 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u16 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++}RT_8723A_FIRMWARE_HDR, *PRT_8723A_FIRMWARE_HDR; ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_MIX ++}USB_RX_AGG_MODE; ++ ++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. ++#define MAX_TX_QUEUE 9 ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++#define TX_TOTAL_PAGE_NUMBER 0xF8 ++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) ++ ++// For Normal Chip Setting ++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define NORMAL_PAGE_NUM_PUBQ 0xE7 ++#define NORMAL_PAGE_NUM_HPQ 0x0C ++#define NORMAL_PAGE_NUM_LPQ 0x02 ++#define NORMAL_PAGE_NUM_NPQ 0x02 ++ ++// For Test Chip Setting ++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define TEST_PAGE_NUM_PUBQ 0x7E ++ ++// For Test Chip Setting ++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 ++#define WMM_TEST_PAGE_NUM_HPQ 0x29 ++#define WMM_TEST_PAGE_NUM_LPQ 0x29 ++ ++// Note: For Normal Chip Setting, modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 ++#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C ++#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C ++ ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++ ++#include "HalVerDef.h" ++#include "hal_com.h" ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan ++{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++#define HAL_EFUSE_MEMORY ++ ++#define EFUSE_REAL_CONTENT_LEN 512 ++#define EFUSE_MAP_LEN 128 ++#define EFUSE_MAX_SECTION 16 ++#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. ++#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) ++// ++// ++// To prevent out of boundary programming case, ++// leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 1byte|----8bytes----|1byte|--5bytes--| ++// | | Reserved(14bytes) | ++// ++ ++// PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. ++#define EFUSE_OOB_PROTECT_BYTES 15 ++ ++#define EFUSE_REAL_CONTENT_LEN_8723A 512 ++#define EFUSE_MAP_LEN_8723A 256 ++#define EFUSE_MAX_SECTION_8723A 32 ++ ++//======================================================== ++// EFUSE for BT definition ++//======================================================== ++#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 ++#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 ++#define EFUSE_BT_MAP_LEN 1024 // 1k bytes ++#define EFUSE_BT_MAX_SECTION 128 // 1024/8 ++ ++#define EFUSE_PROTECT_BYTES_BANK 16 ++ ++// ++// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. ++// ++typedef enum _RT_MULTI_FUNC { ++ RT_MULTI_FUNC_NONE = 0x00, ++ RT_MULTI_FUNC_WIFI = 0x01, ++ RT_MULTI_FUNC_BT = 0x02, ++ RT_MULTI_FUNC_GPS = 0x04, ++} RT_MULTI_FUNC, *PRT_MULTI_FUNC; ++ ++// ++// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. ++// ++typedef enum _RT_POLARITY_CTL { ++ RT_POLARITY_LOW_ACT = 0, ++ RT_POLARITY_HIGH_ACT = 1, ++} RT_POLARITY_CTL, *PRT_POLARITY_CTL; ++ ++// For RTL8723 regulator mode. by tynli. 2011.01.14. ++typedef enum _RT_REGULATOR_MODE { ++ RT_SWITCHING_REGULATOR = 0, ++ RT_LDO_REGULATOR = 1, ++} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; ++ ++// Description: Determine the types of C2H events that are the same in driver and Fw. ++// Fisrt constructed by tynli. 2009.10.09. ++typedef enum _RTL8192C_C2H_EVT ++{ ++ C2H_DBG = 0, ++ C2H_TSF = 1, ++ C2H_AP_RPT_RSP = 2, ++ C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet. ++ C2H_BT_RSSI = 4, ++ C2H_BT_OP_MODE = 5, ++ C2H_EXT_RA_RPT = 6, ++ C2H_HW_INFO_EXCH = 10, ++ C2H_C2H_H2C_TEST = 11, ++ C2H_BT_INFO = 12, ++ C2H_BT_MP_INFO = 15, ++ MAX_C2HEVENT ++} RTL8192C_C2H_EVT; ++ ++typedef struct hal_data_8723a ++{ ++ HAL_VERSION VersionID; ++ RT_CUSTOMER_ID CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ u16 FirmwareSignature; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ u8 BoardType; ++ u8 CrystalCap; ++ // ++ // EEPROM setting. ++ // ++ u8 EEPROMVersion; ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMRegulatory; ++ u8 EEPROMThermalMeter; ++ u8 EEPROMBluetoothCoexist; ++ u8 EEPROMBluetoothType; ++ u8 EEPROMBluetoothAntNum; ++ u8 EEPROMBluetoothAntIsolation; ++ u8 EEPROMBluetoothRadioShared; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 bAPKThermalMeterIgnore; ++ ++ u8 bIQKInitialized; ++ u8 bAntennaDetected; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[7][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 ExternalPA; ++ ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ // For EDCA Turbo mode ++// u8 bIsAnyNonBEPkts; // Adapter->recvpriv.bIsAnyNonBEPkts ++// u8 bCurrentTurboEDCA; ++// u8 bForcedDisableTurboEDCA; ++// u8 bIsCurRDLState; // pdmpriv->prv_traffic_idx ++ ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now. ++ ++ u32 RfRegChnlVal[2]; ++ ++ u8 bCckHighPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ ++ struct dm_priv dmpriv; ++ DM_ODM_T odmpriv; ++ //_lock odm_stainfo_lock; ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++ u8 bBTMode; ++ // BT only. ++ BT30Info BtInfo; ++ // For bluetooth co-existance ++ BT_COEXIST_STR bt_coexist; ++#endif ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ u8 CurAntenna; ++ ++ // SW Antenna Switch ++ s32 RSSI_sum_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_A; ++ s32 RSSI_cnt_B; ++ u8 RSSI_test; ++ u8 AntDivCfg; ++#endif ++ ++ u8 bDumpRxPkt;//for debug ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // 2010/08/09 MH Add CU power down mode. ++ u8 pwrdown; ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. ++ BOOLEAN UsbRxHighSpeedMode; ++ ++ // 2010/11/22 MH Add for slim combo debug mode selective. ++ // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. ++ BOOLEAN SlimComboDbg; ++ ++ // ++ // Add For EEPROM Efuse switch and Efuse Shadow map Setting ++ // ++ u8 EepromOrEfuse; ++// u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ u16 EfuseUsedBytes; ++ u8 EfuseUsedPercentage; ++#ifdef HAL_EFUSE_MEMORY ++ EFUSE_HAL EfuseHal; ++#endif ++ ++ // Interrupt relatd register information. ++ u32 SysIntrStatus; ++ u32 SysIntrMask; ++ ++ // ++ // 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an ++ // independent file in the future. ++ // ++ //------------------------8723-----------------------------------------// ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ //------------------------8723-----------------------------------------// ++ // ++ // 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an ++ // independent file in the future. ++ ++ BOOLEAN bMACFuncEnable; ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif ++ ++ ++ // ++ // For USB Interface HAL related ++ // ++#ifdef CONFIG_USB_HCI ++ u32 UsbBulkOutSize; ++ ++ // Interrupt relatd register information. ++ u32 IntArray[2]; ++ u32 IntrMask[2]; ++#endif ++ ++ ++ // ++ // For SDIO Interface HAL related ++ // ++ ++ // Auto FSM to Turn On, include clock, isolation, power control for MAC only ++ u8 bMacPwrCtrlOn; ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ // ++ // SDIO ISR Related ++ // ++// u32 IntrMask[1]; ++// u32 IntrMaskToSet[1]; ++// LOG_INTERRUPT InterruptLog; ++ u32 sdio_himr; ++ u32 sdio_hisr; ++ ++ // ++ // SDIO Tx FIFO related. ++ // ++ // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg ++ u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; ++ _lock SdioTxFIFOFreePageLock; ++ ++ // ++ // SDIO Rx FIFO related. ++ // ++ u8 SdioRxFIFOCnt; ++ u16 SdioRxFIFOSize; ++#endif ++} HAL_DATA_8723A, *PHAL_DATA_8723A; ++ ++#if 0 ++#define HAL_DATA_TYPE HAL_DATA_8723A ++#define PHAL_DATA_TYPE PHAL_DATA_8723A ++#else ++typedef struct hal_data_8723a HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++#endif ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) ++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) ++ ++typedef struct rxreport_8723a ++{ ++ u32 pktlen:14; ++ u32 crc32:1; ++ u32 icverr:1; ++ u32 drvinfosize:4; ++ u32 security:3; ++ u32 qos:1; ++ u32 shift:2; ++ u32 physt:1; ++ u32 swdec:1; ++ u32 ls:1; ++ u32 fs:1; ++ u32 eor:1; ++ u32 own:1; ++ ++ u32 macid:5; ++ u32 tid:4; ++ u32 hwrsvd:4; ++ u32 amsdu:1; ++ u32 paggr:1; ++ u32 faggr:1; ++ u32 a1fit:4; ++ u32 a2fit:4; ++ u32 pam:1; ++ u32 pwr:1; ++ u32 md:1; ++ u32 mf:1; ++ u32 type:2; ++ u32 mc:1; ++ u32 bc:1; ++ ++ u32 seq:12; ++ u32 frag:4; ++ u32 nextpktlen:14; ++ u32 nextind:1; ++ u32 rsvd0831:1; ++ ++ u32 rxmcs:6; ++ u32 rxht:1; ++ u32 gf:1; ++ u32 splcp:1; ++ u32 bw:1; ++ u32 htc:1; ++ u32 eosp:1; ++ u32 bssidfit:2; ++ u32 rsvd1214:16; ++ u32 unicastwake:1; ++ u32 magicwake:1; ++ ++ u32 pattern0match:1; ++ u32 pattern1match:1; ++ u32 pattern2match:1; ++ u32 pattern3match:1; ++ u32 pattern4match:1; ++ u32 pattern5match:1; ++ u32 pattern6match:1; ++ u32 pattern7match:1; ++ u32 pattern8match:1; ++ u32 pattern9match:1; ++ u32 patternamatch:1; ++ u32 patternbmatch:1; ++ u32 patterncmatch:1; ++ u32 rsvd1613:19; ++ ++ u32 tsfl; ++ ++ u32 bassn:12; ++ u32 bavld:1; ++ u32 rsvd2413:19; ++} RXREPORT, *PRXREPORT; ++ ++typedef struct phystatus_8723a ++{ ++ u32 rxgain_a:7; ++ u32 trsw_a:1; ++ u32 rxgain_b:7; ++ u32 trsw_b:1; ++ u32 chcorr_l:16; ++ ++ u32 sigqualcck:8; ++ u32 cfo_a:8; ++ u32 cfo_b:8; ++ u32 chcorr_h:8; ++ ++ u32 noisepwrdb_h:8; ++ u32 cfo_tail_a:8; ++ u32 cfo_tail_b:8; ++ u32 rsvd0824:8; ++ ++ u32 rsvd1200:8; ++ u32 rxevm_a:8; ++ u32 rxevm_b:8; ++ u32 rxsnr_a:8; ++ ++ u32 rxsnr_b:8; ++ u32 noisepwrdb_l:8; ++ u32 rsvd1616:8; ++ u32 postsnr_a:8; ++ ++ u32 postsnr_b:8; ++ u32 csi_a:8; ++ u32 csi_b:8; ++ u32 targetcsi_a:8; ++ ++ u32 targetcsi_b:8; ++ u32 sigevm:8; ++ u32 maxexpwr:8; ++ u32 exintflag:1; ++ u32 sgien:1; ++ u32 rxsc:2; ++ u32 idlelong:1; ++ u32 anttrainen:1; ++ u32 antselb:1; ++ u32 antsel:1; ++} PHYSTATUS, *PPHYSTATUS; ++ ++ ++// rtl8723a_hal_init.c ++int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware); ++s32 rtl8723a_FirmwareDownload(PADAPTER padapter); ++void rtl8723a_FirmwareSelfReset(PADAPTER padapter); ++void rtl8723a_InitializeFirmwareVars(PADAPTER padapter); ++void _8051Reset8723A(PADAPTER padapter); ++ ++void rtl8723a_InitAntenna_Selection(PADAPTER padapter); ++void rtl8723a_DeinitAntenna_Selection(PADAPTER padapter); ++void rtl8723a_CheckAntenna_Selection(PADAPTER padapter); ++void rtl8723a_init_default_value(PADAPTER padapter); ++ ++s32 InitLLTTable(PADAPTER padapter, u32 boundary); ++ ++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); ++s32 CardDisableWithoutHWSM(PADAPTER padapter); ++ ++// EFuse ++u8 GetEEPROMSize8723A(PADAPTER padapter); ++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); ++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); ++void Hal_EfuseParseTxPowerInfo_8723A(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseBTCoexistInfo_8723A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseEEPROMVer(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void rtl8723a_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseCustomerID(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseAntennaDiversity(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseRateIndicationOption(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); ++void Hal_EfuseParseXtal_8723A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); ++void Hal_EfuseParseThermalMeter_8723A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); ++ ++//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan); ++//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter); ++//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoloadFail); ++void Hal_InitChannelPlan(PADAPTER padapter); ++ ++void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc); ++void SetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val); ++void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val); ++#ifdef CONFIG_BT_COEXIST ++void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter); ++#endif ++ ++// register ++void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); ++void rtl8723a_InitBeaconParameters(PADAPTER padapter); ++void rtl8723a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); ++ ++void rtl8723a_start_thread(_adapter *padapter); ++void rtl8723a_stop_thread(_adapter *padapter); ++ ++s32 c2h_id_filter_ccx_8723a(u8 id); ++ ++ ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++void rtl8723a_init_checkbthang_workqueue(_adapter * padapter); ++void rtl8723a_free_checkbthang_workqueue(_adapter * padapter); ++void rtl8723a_cancel_checkbthang_workqueue(_adapter * padapter); ++void rtl8723a_hal_check_bt_hang(_adapter * padapter); ++#endif ++ ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_led.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_led.h +new file mode 100644 +index 00000000..1af41993 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_led.h +@@ -0,0 +1,50 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_LED_H__ ++#define __RTL8723A_LED_H__ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8723au_InitSwLeds(PADAPTER padapter); ++void rtl8723au_DeInitSwLeds(PADAPTER padapter); ++#endif ++#ifdef CONFIG_PCI_HCI ++void rtl8723ae_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8723ae_InitSwLeds(PADAPTER padapter); ++void rtl8723ae_DeInitSwLeds(PADAPTER padapter); ++#endif ++#ifdef CONFIG_SDIO_HCI ++void rtl8723as_InitSwLeds(PADAPTER padapter); ++void rtl8723as_DeInitSwLeds(PADAPTER padapter); ++#endif ++#ifdef CONFIG_GSPI_HCI ++void rtl8723as_InitSwLeds(PADAPTER padapter); ++void rtl8723as_DeInitSwLeds(PADAPTER padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_pg.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_pg.h +new file mode 100644 +index 00000000..68cc0985 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_pg.h +@@ -0,0 +1,146 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_PG_H__ ++#define __RTL8723A_PG_H__ ++ ++//==================================================== ++// EEPROM/Efuse PG Offset for 8723E/8723U/8723S ++//==================================================== ++#define EEPROM_CCK_TX_PWR_INX_8723A 0x10 ++#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F ++#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22 ++#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25 ++ ++#define EEPROM_ChannelPlan_8723A 0x28 ++#define EEPROM_TSSI_A_8723A 0x29 ++#define EEPROM_THERMAL_METER_8723A 0x2A ++#define RF_OPTION1_8723A 0x2B ++#define RF_OPTION2_8723A 0x2C ++#define RF_OPTION3_8723A 0x2D ++#define RF_OPTION4_8723A 0x2E ++#define EEPROM_VERSION_8723A 0x30 ++#define EEPROM_CustomID_8723A 0x31 ++#define EEPROM_SubCustomID_8723A 0x32 ++#define EEPROM_XTAL_K_8723A 0x33 ++#define EEPROM_Chipset_8723A 0x34 ++ ++// RTL8723AE ++#define EEPROM_VID_8723AE 0x49 ++#define EEPROM_DID_8723AE 0x4B ++#define EEPROM_SVID_8723AE 0x4D ++#define EEPROM_SMID_8723AE 0x4F ++#define EEPROM_MAC_ADDR_8723AE 0x67 ++ ++// RTL8723AU ++#define EEPROM_MAC_ADDR_8723AU 0xC6 ++#define EEPROM_VID_8723AU 0xB7 ++#define EEPROM_PID_8723AU 0xB9 ++ ++// RTL8723AS ++#define EEPROM_MAC_ADDR_8723AS 0xAA ++ ++//==================================================== ++// EEPROM/Efuse Value Type ++//==================================================== ++#define EETYPE_TX_PWR 0x0 ++ ++//==================================================== ++// EEPROM/Efuse Default Value ++//==================================================== ++#define EEPROM_Default_CrystalCap_8723A 0x20 ++ ++ ++//---------------------------------------------------------------------------- ++// EEPROM/EFUSE data structure definition. ++//---------------------------------------------------------------------------- ++#define MAX_RF_PATH_NUM 2 ++#define MAX_CHNL_GROUP 3+9 ++typedef struct _TxPowerInfo ++{ ++ u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; ++ u8 TSSI_A[3]; ++ u8 TSSI_B[3]; ++ u8 TSSI_A_5G[3]; //5GL/5GM/5GH ++ u8 TSSI_B_5G[3]; ++} TxPowerInfo, *PTxPowerInfo; ++ ++#if 0 ++#define MAX_RF_PATH 4 ++#define MAX_CHNL_GROUP_24G 6 ++#define MAX_CHNL_GROUP_5G 14 ++ ++// It must always set to 4, otherwise read efuse table secquence will be wrong. ++#define MAX_TX_COUNT 4 ++ ++typedef struct _TxPowerInfo24G ++{ ++ u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; ++ u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1]; ++ //If only one tx, only BW20 and OFDM are used. ++ s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++} TxPowerInfo24G, *PTxPowerInfo24G; ++ ++typedef struct _TxPowerInfo5G ++{ ++ u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; ++ //If only one tx, only BW20, OFDM, BW80 and BW160 are used. ++ s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++ s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; ++} TxPowerInfo5G, *PTxPowerInfo5G; ++#endif ++ ++typedef enum _BT_Ant_NUM ++{ ++ Ant_x2 = 0, ++ Ant_x1 = 1 ++} BT_Ant_NUM, *PBT_Ant_NUM; ++ ++typedef enum _BT_CoType ++{ ++ BT_2Wire = 0, ++ BT_ISSC_3Wire = 1, ++ BT_Accel = 2, ++ BT_CSR_BC4 = 3, ++ BT_CSR_BC8 = 4, ++ BT_RTL8756 = 5, ++ BT_RTL8723A = 6 ++} BT_CoType, *PBT_CoType; ++ ++typedef enum _BT_RadioShared ++{ ++ BT_Radio_Shared = 0, ++ BT_Radio_Individual = 1, ++} BT_RadioShared, *PBT_RadioShared; ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_recv.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_recv.h +new file mode 100644 +index 00000000..98831678 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_recv.h +@@ -0,0 +1,41 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_RECV_H__ ++#define __RTL8723A_RECV_H__ ++ ++#include ++ ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++#ifdef CONFIG_DIRECT_RECV ++void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf); ++#endif ++s32 rtl8723as_init_recv_priv(PADAPTER padapter); ++void rtl8723as_free_recv_priv(PADAPTER padapter); ++#endif ++ ++void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat); ++void rtl8192c_process_phy_info(PADAPTER padapter, void *prframe); ++#ifdef CONFIG_USB_HCI ++void update_recvframe_attrib(union recv_frame *precvframe, struct recv_stat *prxstat); ++void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info); ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_rf.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_rf.h +new file mode 100644 +index 00000000..187702f7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_rf.h +@@ -0,0 +1,27 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_RF_H__ ++#define __RTL8723A_RF_H__ ++ ++#include "rtl8192c_rf.h" ++int PHY_RF6052_Config8723A( IN PADAPTER Adapter ); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_spec.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_spec.h +new file mode 100644 +index 00000000..a51bc5a0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_spec.h +@@ -0,0 +1,538 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#ifndef __RTL8723A_SPEC_H__ ++#define __RTL8723A_SPEC_H__ ++ ++#include ++ ++ ++//============================================================================ ++// 8723A Regsiter offset definition ++//============================================================================ ++#define HAL_8723A_NAV_UPPER_UNIT 128 // micro-second ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYSON_REG_LOCK 0x001C ++ ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_FTIMR 0x0138 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++ ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++ ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++ ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//#define REG_EARLY_MODE_CONTROL 0x4D0 ++#define REG_MACID_NO_LINK 0x4D0 ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++//2 BCN_CTRL ++#define DIS_ATIM BIT(0) ++#define DIS_BCNQ_SUB BIT(1) ++#define DIS_TSF_UDT BIT(4) ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++// ++// Note: ++// The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is ++// always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending ++// CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. ++// The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented ++// by SD1 Scott. ++// By Bruce, 2011-07-18. ++// ++#define REG_NAV_UPPER 0x0652 // unit of 128 ++ ++#define REG_BT_COEX_TABLE_1 0x06C0 ++#define REG_BT_COEX_TABLE_2 0x06C4 ++ ++//============================================================================ ++// 8723 Regsiter Bit and Content definition ++//============================================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SPS0_CTRL ++ ++//2 SYS_ISO_CTRL ++ ++//2 SYS_FUNC_EN ++ ++//2 APS_FSMCO ++#define EN_WLON BIT(16) ++ ++//2 SYS_CLKR ++ ++//2 9346CR ++ ++//2 AFE_MISC ++ ++//2 SPS0_CTRL ++ ++//2 SPS_OCP_CFG ++ ++//2 SYSON_REG_LOCK ++#define WLOCK_ALL BIT(0) ++#define WLOCK_00 BIT(1) ++#define WLOCK_04 BIT(2) ++#define WLOCK_08 BIT(3) ++#define WLOCK_40 BIT(4) ++#define WLOCK_1C_B6 BIT(5) ++#define R_DIS_PRST_1 BIT(6) ++#define LOCK_ALL_EN BIT(7) ++ ++//2 RF_CTRL ++ ++//2 LDOA15_CTRL ++ ++//2 LDOV12D_CTRL ++ ++//2 AFE_XTAL_CTRL ++ ++//2 AFE_PLL_CTRL ++ ++//2 EFUSE_CTRL ++ ++//2 EFUSE_TEST (For RTL8723 partially) ++ ++//2 PWR_DATA ++ ++//2 CAL_TIMER ++ ++//2 ACLK_MON ++ ++//2 GPIO_MUXCFG ++ ++//2 GPIO_PIN_CTRL ++ ++//2 GPIO_INTM ++ ++//2 LEDCFG ++ ++//2 FSIMR ++ ++//2 FSISR ++ ++//2 HSIMR ++// 8723 Host System Interrupt Mask Register (offset 0x58, 32 byte) ++#define HSIMR_GPIO12_0_INT_EN BIT(0) ++#define HSIMR_SPS_OCP_INT_EN BIT(5) ++#define HSIMR_RON_INT_EN BIT(6) ++#define HSIMR_PDNINT_EN BIT(7) ++#define HSIMR_GPIO9_INT_EN BIT(25) ++ ++//2 HSISR ++// 8723 Host System Interrupt Status Register (offset 0x5C, 32 byte) ++#define HSISR_GPIO12_0_INT BIT(0) ++#define HSISR_SPS_OCP_INT BIT(5) ++#define HSISR_RON_INT BIT(6) ++#define HSISR_PDNINT BIT(7) ++#define HSISR_GPIO9_INT BIT(25) ++ ++// interrupt mask which needs to clear ++#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ ++ HSISR_SPS_OCP_INT |\ ++ HSISR_RON_INT |\ ++ HSISR_PDNINT |\ ++ HSISR_GPIO9_INT) ++ ++//2 MCUFWDL ++#define RAM_DL_SEL BIT7 // 1:RAM, 0:ROM ++ ++//2 HPON_FSM ++ ++//2 SYS_CFG ++#define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL) ++#define SPS_SEL BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode ++ ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++//2 Function Enable Registers ++ ++//2 CR ++#define CALTMR_EN BIT(10) ++ ++//2 PBP - Page Size Register ++ ++//2 TX/RXDMA ++ ++//2 TRXFF_BNDY ++ ++//2 LLT_INIT ++ ++//2 BB_ACCESS_CTRL ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++ ++//2 RQPN ++ ++//2 TDECTRL ++ ++//2 TDECTL ++ ++//2 TXDMA_OFFSET_CHK ++ ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++ ++//2 FWHW_TXQ_CTRL ++ ++//2 INIRTSMCS_SEL ++ ++//2 SPEC SIFS ++ ++//2 RRSR ++ ++//2 ARFR ++ ++//2 AGGLEN_LMT_L ++ ++//2 RL ++ ++//2 DARFRC ++ ++//2 RARFRC ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++//2 EDCA setting ++ ++//2 EDCA_VO_PARAM ++ ++//2 SIFS_CCK ++ ++//2 SIFS_OFDM ++ ++//2 TBTT PROHIBIT ++ ++//2 REG_RD_CTRL ++ ++//2 BCN_CTRL ++ ++//2 ACMHWCTRL ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++ ++//2 APSD_CTRL ++ ++//2 BWOPMODE ++ ++//2 TCR ++ ++//2 RCR ++ ++//2 RX_PKT_LIMIT ++ ++//2 RX_DLK_TIME ++ ++//2 MBIDCAMCFG ++ ++//2 AMPDU_MIN_SPACE ++ ++//2 RXERR_RPT ++ ++//2 SECCFG ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration ++// ++//----------------------------------------------------- ++ ++// I/O bus domain address mapping ++#define SDIO_LOCAL_BASE 0x10250000 ++#define WLAN_IOREG_BASE 0x10260000 ++#define FIRMWARE_FIFO_BASE 0x10270000 ++#define TX_HIQ_BASE 0x10310000 ++#define TX_MIQ_BASE 0x10320000 ++#define TX_LOQ_BASE 0x10330000 ++#define RX_RX0FF_BASE 0x10340000 ++ ++// SDIO host local register space mapping. ++#define SDIO_LOCAL_MSK 0x0FFF ++#define WLAN_IOREG_MSK 0x7FFF ++#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] ++#define WLAN_RX0FF_MSK 0x0003 ++ ++#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID ++#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] ++#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] ++#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] ++#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] ++#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] ++#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] ++ ++// SDIO Tx Free Page Index ++#define HI_QUEUE_IDX 0 ++#define MID_QUEUE_IDX 1 ++#define LOW_QUEUE_IDX 2 ++#define PUBLIC_QUEUE_IDX 3 ++ ++#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ ++#define SDIO_MAX_RX_QUEUE 1 ++ ++#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control ++#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask ++#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine ++#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode ++#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length ++#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page ++#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 ++#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 ++#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion ++#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 ++#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 ++#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock ++#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control ++#define SDIO_REG_HIMR_ON 0x0090 // SDIO Host Extension Interrupt Mask Always ++#define SDIO_REG_HISR_ON 0x0091 // SDIO Host Extension Interrupt Status Always ++ ++#define SDIO_HIMR_DISABLED 0 ++ ++// SDIO Host Interrupt Mask Register ++#define SDIO_HIMR_RX_REQUEST_MSK BIT0 ++#define SDIO_HIMR_AVAL_MSK BIT1 ++#define SDIO_HIMR_TXERR_MSK BIT2 ++#define SDIO_HIMR_RXERR_MSK BIT3 ++#define SDIO_HIMR_TXFOVW_MSK BIT4 ++#define SDIO_HIMR_RXFOVW_MSK BIT5 ++#define SDIO_HIMR_TXBCNOK_MSK BIT6 ++#define SDIO_HIMR_TXBCNERR_MSK BIT7 ++#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 ++#define SDIO_HIMR_C2HCMD_MSK BIT17 ++#define SDIO_HIMR_CPWM1_MSK BIT18 ++#define SDIO_HIMR_CPWM2_MSK BIT19 ++#define SDIO_HIMR_HSISR_IND_MSK BIT20 ++#define SDIO_HIMR_GTINT3_IND_MSK BIT21 ++#define SDIO_HIMR_GTINT4_IND_MSK BIT22 ++#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 ++#define SDIO_HIMR_OCPINT_MSK BIT24 ++#define SDIO_HIMR_ATIMEND_MSK BIT25 ++#define SDIO_HIMR_ATIMEND_E_MSK BIT26 ++#define SDIO_HIMR_CTWEND_MSK BIT27 ++ ++// SDIO Host Interrupt Service Routine ++#define SDIO_HISR_RX_REQUEST BIT0 ++#define SDIO_HISR_AVAL BIT1 ++#define SDIO_HISR_TXERR BIT2 ++#define SDIO_HISR_RXERR BIT3 ++#define SDIO_HISR_TXFOVW BIT4 ++#define SDIO_HISR_RXFOVW BIT5 ++#define SDIO_HISR_TXBCNOK BIT6 ++#define SDIO_HISR_TXBCNERR BIT7 ++#define SDIO_HISR_BCNERLY_INT BIT16 ++#define SDIO_HISR_C2HCMD BIT17 ++#define SDIO_HISR_CPWM1 BIT18 ++#define SDIO_HISR_CPWM2 BIT19 ++#define SDIO_HISR_HSISR_IND BIT20 ++#define SDIO_HISR_GTINT3_IND BIT21 ++#define SDIO_HISR_GTINT4_IND BIT22 ++#define SDIO_HISR_PSTIMEOUT BIT23 ++#define SDIO_HISR_OCPINT BIT24 ++#define SDIO_HISR_ATIMEND BIT25 ++#define SDIO_HISR_ATIMEND_E BIT26 ++#define SDIO_HISR_CTWEND BIT27 ++ ++#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ ++ SDIO_HISR_RXERR |\ ++ SDIO_HISR_TXFOVW |\ ++ SDIO_HISR_RXFOVW |\ ++ SDIO_HISR_TXBCNOK |\ ++ SDIO_HISR_TXBCNERR |\ ++ SDIO_HISR_C2HCMD |\ ++ SDIO_HISR_CPWM1 |\ ++ SDIO_HISR_CPWM2 |\ ++ SDIO_HISR_HSISR_IND |\ ++ SDIO_HISR_GTINT3_IND |\ ++ SDIO_HISR_GTINT4_IND |\ ++ SDIO_HISR_PSTIMEOUT |\ ++ SDIO_HISR_OCPINT) ++ ++// SDIO HCI Suspend Control Register ++#define HCI_RESUME_PWR_RDY BIT1 ++#define HCI_SUS_CTRL BIT0 ++ ++// SDIO Tx FIFO related ++#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page ++#define SDIO_TX_FIFO_PAGE_SZ 128 ++ ++// vivi added for new cam search flow, 20091028 ++#define SCR_TxUseBroadcastDK BIT6 // Force Tx Use Broadcast Default Key ++#define SCR_RxUseBroadcastDK BIT7 // Force Rx Use Broadcast Default Key ++ ++ ++//---------------------------------------------------------------------------- ++// 8723 EFUSE ++//---------------------------------------------------------------------------- ++#ifdef HWSET_MAX_SIZE ++#undef HWSET_MAX_SIZE ++#endif ++#define HWSET_MAX_SIZE 256 ++ ++ ++//----------------------------------------------------------------------------- ++//USB interrupt ++//----------------------------------------------------------------------------- ++#define UHIMR_TIMEOUT2 BIT31 ++#define UHIMR_TIMEOUT1 BIT30 ++#define UHIMR_PSTIMEOUT BIT29 ++#define UHIMR_GTINT4 BIT28 ++#define UHIMR_GTINT3 BIT27 ++#define UHIMR_TXBCNERR BIT26 ++#define UHIMR_TXBCNOK BIT25 ++#define UHIMR_TSF_BIT32_TOGGLE BIT24 ++#define UHIMR_BCNDMAINT3 BIT23 ++#define UHIMR_BCNDMAINT2 BIT22 ++#define UHIMR_BCNDMAINT1 BIT21 ++#define UHIMR_BCNDMAINT0 BIT20 ++#define UHIMR_BCNDOK3 BIT19 ++#define UHIMR_BCNDOK2 BIT18 ++#define UHIMR_BCNDOK1 BIT17 ++#define UHIMR_BCNDOK0 BIT16 ++#define UHIMR_HSISR_IND BIT15 ++#define UHIMR_BCNDMAINT_E BIT14 ++//RSVD BIT13 ++#define UHIMR_CTW_END BIT12 ++//RSVD BIT11 ++#define UHIMR_C2HCMD BIT10 ++#define UHIMR_CPWM2 BIT9 ++#define UHIMR_CPWM BIT8 ++#define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt ++#define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt ++#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt ++#define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt ++#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt ++#define UHIMR_RDU BIT1 // Receive Descriptor Unavailable ++#define UHIMR_ROK BIT0 // Receive DMA OK Interrupt ++ ++// USB Host Interrupt Status Extension bit ++#define UHIMR_BCNDMAINT7 BIT23 ++#define UHIMR_BCNDMAINT6 BIT22 ++#define UHIMR_BCNDMAINT5 BIT21 ++#define UHIMR_BCNDMAINT4 BIT20 ++#define UHIMR_BCNDOK7 BIT19 ++#define UHIMR_BCNDOK6 BIT18 ++#define UHIMR_BCNDOK5 BIT17 ++#define UHIMR_BCNDOK4 BIT16 ++// bit14-15: RSVD ++#define UHIMR_ATIMEND_E BIT13 ++#define UHIMR_ATIMEND BIT12 ++#define UHIMR_TXERR BIT11 ++#define UHIMR_RXERR BIT10 ++#define UHIMR_TXFOVW BIT9 ++#define UHIMR_RXFOVW BIT8 ++// bit2-7: RSVD ++#define UHIMR_OCPINT BIT1 ++// bit0: RSVD ++ ++#define REG_USB_HIMR 0xFE38 ++#define REG_USB_HIMRE 0xFE3C ++#define REG_USB_HISR 0xFE78 ++#define REG_USB_HISRE 0xFE7C ++ ++#define USB_INTR_CPWM_OFFSET 16 ++#define USB_INTR_CONTENT_HISR_OFFSET 48 ++#define USB_INTR_CONTENT_HISRE_OFFSET 52 ++#define USB_INTR_CONTENT_LENGTH 56 ++#define USB_C2H_CMDID_OFFSET 0 ++#define USB_C2H_SEQ_OFFSET 1 ++#define USB_C2H_EVENT_OFFSET 2 ++//============================================================================ ++// General definitions ++//============================================================================ ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++#define EEPROM_RF_GAIN_OFFSET 0x2F ++#define EEPROM_RF_GAIN_VAL 0x1F6 ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_sreset.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_sreset.h +new file mode 100644 +index 00000000..c6ca4dca +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_sreset.h +@@ -0,0 +1,33 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8188E_SRESET_H_ ++#define _RTL8188E_SRESET_H_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++extern void rtl8723a_sreset_xmit_status_check(_adapter *padapter); ++extern void rtl8723a_sreset_linked_status_check(_adapter *padapter); ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_xmit.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_xmit.h +new file mode 100644 +index 00000000..c3658435 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtl8723a_xmit.h +@@ -0,0 +1,238 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8723A_XMIT_H__ ++#define __RTL8723A_XMIT_H__ ++ ++#include ++ ++// ++//defined for TX DESC Operation ++// ++ ++#define MAX_TID (15) ++ ++//OFFSET 0 ++#define OFFSET_SZ 0 ++#define OFFSET_SHT 16 ++#define BMC BIT(24) ++#define LSG BIT(26) ++#define FSG BIT(27) ++#define OWN BIT(31) ++ ++ ++//OFFSET 4 ++#define PKT_OFFSET_SZ 0 ++#define BK BIT(6) ++#define QSEL_SHT 8 ++#define Rate_ID_SHT 16 ++#define NAVUSEHDR BIT(20) ++#define PKT_OFFSET_SHT 26 ++#define HWPC BIT(31) ++ ++//OFFSET 8 ++#define AGG_EN BIT(29) ++ ++//OFFSET 12 ++#define SEQ_SHT 16 ++ ++//OFFSET 16 ++#define QoS BIT(6) ++#define HW_SEQ_EN BIT(7) ++#define USERATE BIT(8) ++#define DISDATAFB BIT(10) ++#define DATA_SHORT BIT(24) ++#define DATA_BW BIT(25) ++ ++//OFFSET 20 ++#define SGI BIT(6) ++ ++typedef struct txdesc_8723a ++{ ++ u32 pktlen:16; ++ u32 offset:8; ++ u32 bmc:1; ++ u32 htc:1; ++ u32 ls:1; ++ u32 fs:1; ++ u32 linip:1; ++ u32 noacm:1; ++ u32 gf:1; ++ u32 own:1; ++ ++ u32 macid:5; ++ u32 agg_en:1; ++ u32 bk:1; ++ u32 rd_en:1; ++ u32 qsel:5; ++ u32 rd_nav_ext:1; ++ u32 lsig_txop_en:1; ++ u32 pifs:1; ++ u32 rate_id:4; ++ u32 navusehdr:1; ++ u32 en_desc_id:1; ++ u32 sectype:2; ++ u32 rsvd0424:2; ++ u32 pkt_offset:5; // unit: 8 bytes ++ u32 rsvd0431:1; ++ ++ u32 rts_rc:6; ++ u32 data_rc:6; ++ u32 rsvd0812:2; ++ u32 bar_rty_th:2; ++ u32 rsvd0816:1; ++ u32 morefrag:1; ++ u32 raw:1; ++ u32 ccx:1; ++ u32 ampdu_density:3; ++ u32 bt_null:1; ++ u32 ant_sel_a:1; ++ u32 ant_sel_b:1; ++ u32 tx_ant_cck:2; ++ u32 tx_antl:2; ++ u32 tx_ant_ht:2; ++ ++ u32 nextheadpage:8; ++ u32 tailpage:8; ++ u32 seq:12; ++ u32 cpu_handle:1; ++ u32 tag1:1; ++ u32 trigger_int:1; ++ u32 hwseq_en:1; ++ ++ u32 rtsrate:5; ++ u32 ap_dcfe:1; ++ u32 hwseq_sel:2; ++ u32 userate:1; ++ u32 disrtsfb:1; ++ u32 disdatafb:1; ++ u32 cts2self:1; ++ u32 rtsen:1; ++ u32 hw_rts_en:1; ++ u32 port_id:1; ++ u32 rsvd1615:3; ++ u32 wait_dcts:1; ++ u32 cts2ap_en:1; ++ u32 data_sc:2; ++ u32 data_stbc:2; ++ u32 data_short:1; ++ u32 data_bw:1; ++ u32 rts_short:1; ++ u32 rts_bw:1; ++ u32 rts_sc:2; ++ u32 vcs_stbc:2; ++ ++ u32 datarate:6; ++ u32 sgi:1; ++ u32 try_rate:1; ++ u32 data_ratefb_lmt:5; ++ u32 rts_ratefb_lmt:4; ++ u32 rty_lmt_en:1; ++ u32 data_rt_lmt:6; ++ u32 usb_txagg_num:8; ++ ++ u32 txagg_a:5; ++ u32 txagg_b:5; ++ u32 use_max_len:1; ++ u32 max_agg_num:5; ++ u32 mcsg1_max_len:4; ++ u32 mcsg2_max_len:4; ++ u32 mcsg3_max_len:4; ++ u32 mcs7_sgi_max_len:4; ++ ++ u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB) ++ u32 mcsg4_max_len:4; ++ u32 mcsg5_max_len:4; ++ u32 mcsg6_max_len:4; ++ u32 mcs15_sgi_max_len:4; ++}TXDESC, *PTXDESC; ++ ++#define txdesc_set_ccx_sw_8723a(txdesc, value) \ ++ do { \ ++ ((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \ ++ ((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \ ++ ((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \ ++ } while (0) ++ ++struct txrpt_ccx_8723a { ++ /* offset 0 */ ++ u8 tag1:1; ++ u8 rsvd:4; ++ u8 int_bt:1; ++ u8 int_tri:1; ++ u8 int_ccx:1; ++ ++ /* offset 1 */ ++ u8 mac_id:5; ++ u8 pkt_drop:1; ++ u8 pkt_ok:1; ++ u8 bmc:1; ++ ++ /* offset 2 */ ++ u8 retry_cnt:6; ++ u8 lifetime_over:1; ++ u8 retry_over:1; ++ ++ /* offset 3 */ ++ u8 ccx_qtime0; ++ u8 ccx_qtime1; ++ ++ /* offset 5 */ ++ u8 final_data_rate; ++ ++ /* offset 6 */ ++ u8 sw1:4; ++ u8 qsel:4; ++ ++ /* offset 7 */ ++ u8 sw0; ++}; ++ ++#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) ++#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) ++ ++#ifdef CONFIG_XMIT_ACK ++void dump_txrpt_ccx_8723a(void *buf); ++void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf); ++#else ++#define dump_txrpt_ccx_8723a(buf) do {} while(0) ++#define handle_txrpt_ccx_8723a(adapter, buf) do {} while(0) ++#endif //CONFIG_XMIT_ACK ++ ++void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); ++void rtl8723a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++s32 rtl8723as_init_xmit_priv(PADAPTER padapter); ++void rtl8723as_free_xmit_priv(PADAPTER padapter); ++s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); ++s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); ++s32 rtl8723as_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++s32 rtl8723as_xmit_buf_handler(PADAPTER padapter); ++thread_return rtl8723as_xmit_thread(thread_context context); ++#define hal_xmit_handler rtl8723as_xmit_buf_handler ++#endif ++ ++#ifdef CONFIG_USB_HCI ++s32 rtl8723au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++s32 rtl8723au_xmit_buf_handler(PADAPTER padapter); ++#define hal_xmit_handler rtl8723au_xmit_buf_handler ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_android.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_android.h +new file mode 100644 +index 00000000..f9214c2d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_android.h +@@ -0,0 +1,90 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __RTW_ANDROID_H__ ++#define __RTW_ANDROID_H__ ++ ++#include ++#include ++ ++enum ANDROID_WIFI_CMD { ++ ANDROID_WIFI_CMD_START, ++ ANDROID_WIFI_CMD_STOP, ++ ANDROID_WIFI_CMD_SCAN_ACTIVE, ++ ANDROID_WIFI_CMD_SCAN_PASSIVE, ++ ANDROID_WIFI_CMD_RSSI, ++ ANDROID_WIFI_CMD_LINKSPEED, ++ ANDROID_WIFI_CMD_RXFILTER_START, ++ ANDROID_WIFI_CMD_RXFILTER_STOP, ++ ANDROID_WIFI_CMD_RXFILTER_ADD, ++ ANDROID_WIFI_CMD_RXFILTER_REMOVE, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_START, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, ++ ANDROID_WIFI_CMD_BTCOEXMODE, ++ ANDROID_WIFI_CMD_SETSUSPENDOPT, ++ ANDROID_WIFI_CMD_P2P_DEV_ADDR, ++ ANDROID_WIFI_CMD_SETFWPATH, ++ ANDROID_WIFI_CMD_SETBAND, ++ ANDROID_WIFI_CMD_GETBAND, ++ ANDROID_WIFI_CMD_COUNTRY, ++ ANDROID_WIFI_CMD_P2P_SET_NOA, ++ ANDROID_WIFI_CMD_P2P_GET_NOA, ++ ANDROID_WIFI_CMD_P2P_SET_PS, ++ ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, ++#ifdef PNO_SUPPORT ++ ANDROID_WIFI_CMD_PNOSSIDCLR_SET, ++ ANDROID_WIFI_CMD_PNOSETUP_SET, ++ ANDROID_WIFI_CMD_PNOENABLE_SET, ++ ANDROID_WIFI_CMD_PNODEBUG_SET, ++#endif ++ ++ ANDROID_WIFI_CMD_MACADDR, ++ ++ ANDROID_WIFI_CMD_BLOCK, ++ ++ ANDROID_WIFI_CMD_WFD_ENABLE, ++ ANDROID_WIFI_CMD_WFD_DISABLE, ++ ++ ANDROID_WIFI_CMD_WFD_SET_TCPPORT, ++ ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT, ++ ANDROID_WIFI_CMD_WFD_SET_DEVTYPE, ++ ++ ANDROID_WIFI_CMD_MAX ++}; ++ ++int rtw_android_cmdstr_to_num(char *cmdstr); ++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd); ++ ++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) ++int rtw_android_wifictrl_func_add(void); ++void rtw_android_wifictrl_func_del(void); ++void* wl_android_prealloc(int section, unsigned long size); ++ ++int wifi_get_irq_number(unsigned long *irq_flags_ptr); ++int wifi_set_power(int on, unsigned long msec); ++int wifi_get_mac_addr(unsigned char *buf); ++void *wifi_get_country_code(char *ccode); ++#else ++static int rtw_android_wifictrl_func_add(void) { return 0; } ++static void rtw_android_wifictrl_func_del(void) {} ++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ ++ ++#endif //__RTW_ANDROID_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ap.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ap.h +new file mode 100644 +index 00000000..a93e1e8d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ap.h +@@ -0,0 +1,65 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_AP_H_ ++#define __RTW_AP_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++//external function ++extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); ++extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); ++ ++ ++void init_mlme_ap_info(_adapter *padapter); ++void free_mlme_ap_info(_adapter *padapter); ++//void update_BCNTIM(_adapter *padapter); ++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); ++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); ++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx); ++void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level); ++void expire_timeout_chk(_adapter *padapter); ++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); ++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); ++void rtw_ap_restore_network(_adapter *padapter); ++void rtw_set_macaddr_acl(_adapter *padapter, int mode); ++int rtw_acl_add_sta(_adapter *padapter, u8 *addr); ++int rtw_acl_remove_sta(_adapter *padapter, u8 *addr); ++ ++#ifdef CONFIG_NATIVEAP_MLME ++void associated_clients_update(_adapter *padapter, u8 updated); ++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); ++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); ++void sta_info_update(_adapter *padapter, struct sta_info *psta); ++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); ++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason); ++int rtw_sta_flush(_adapter *padapter); ++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); ++void start_ap_mode(_adapter *padapter); ++void stop_ap_mode(_adapter *padapter); ++#endif ++#endif //end of CONFIG_AP_MODE ++ ++#endif ++void update_bmc_sta(_adapter *padapter); +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_br_ext.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_br_ext.h +new file mode 100644 +index 00000000..c8d78016 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_br_ext.h +@@ -0,0 +1,76 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_BR_EXT_H_ ++#define _RTW_BR_EXT_H_ ++ ++#if 1 // rtw_wifi_driver ++#define CL_IPV6_PASS 1 ++#define MACADDRLEN 6 ++#define _DEBUG_ERR DBG_8192C ++#define _DEBUG_INFO //DBG_8192C ++#define DEBUG_WARN DBG_8192C ++#define DEBUG_INFO //DBG_8192C ++#define DEBUG_ERR DBG_8192C ++//#define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) ++#define GET_MY_HWADDR(padapter) ((padapter)->eeprompriv.mac_addr) ++#endif // rtw_wifi_driver ++ ++#define NAT25_HASH_BITS 4 ++#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS) ++#define NAT25_AGEING_TIME 300 ++ ++#ifdef CL_IPV6_PASS ++#define MAX_NETWORK_ADDR_LEN 17 ++#else ++#define MAX_NETWORK_ADDR_LEN 11 ++#endif ++ ++struct nat25_network_db_entry ++{ ++ struct nat25_network_db_entry *next_hash; ++ struct nat25_network_db_entry **pprev_hash; ++ atomic_t use_count; ++ unsigned char macAddr[6]; ++ unsigned long ageing_timer; ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++}; ++ ++enum NAT25_METHOD { ++ NAT25_MIN, ++ NAT25_CHECK, ++ NAT25_INSERT, ++ NAT25_LOOKUP, ++ NAT25_PARSE, ++ NAT25_MAX ++}; ++ ++struct br_ext_info { ++ unsigned int nat25_disable; ++ unsigned int macclone_enable; ++ unsigned int dhcp_bcst_disable; ++ int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable ++ unsigned char nat25_dmzMac[MACADDRLEN]; ++ unsigned int nat25sc_disable; ++}; ++ ++void nat25_db_cleanup(_adapter *priv); ++ ++#endif // _RTW_BR_EXT_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_bt_mp.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_bt_mp.h +new file mode 100644 +index 00000000..15746616 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_bt_mp.h +@@ -0,0 +1,318 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __RTW_BT_MP_H ++#define __RTW_BT_MP_H ++ ++#include ++#include ++#include ++ ++ ++#if(MP_DRIVER == 1) ++ ++#pragma pack(1) ++ ++// definition for BT_UP_OP_BT_READY ++#define MP_BT_NOT_READY 0 ++#define MP_BT_READY 1 ++ ++// definition for BT_UP_OP_BT_SET_MODE ++typedef enum _MP_BT_MODE{ ++ MP_BT_MODE_RF_TXRX_TEST_MODE = 0, ++ MP_BT_MODE_BT20_DUT_TEST_MODE = 1, ++ MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2, ++ MP_BT_MODE_CONNECT_TEST_MODE = 3, ++ MP_BT_MODE_MAX ++}MP_BT_MODE,*PMP_BT_MODE; ++ ++ ++// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER ++typedef struct _BT_TXRX_PARAMETERS{ ++ u1Byte txrxChannel; ++ u4Byte txrxTxPktCnt; ++ u1Byte txrxTxPktInterval; ++ u1Byte txrxPayloadType; ++ u1Byte txrxPktType; ++ u2Byte txrxPayloadLen; ++ u4Byte txrxPktHeader; ++ u1Byte txrxWhitenCoeff; ++ u1Byte txrxBdaddr[6]; ++ u1Byte txrxTxGainIndex; ++} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS; ++ ++// txrxPktType ++typedef enum _MP_BT_PKT_TYPE{ ++ MP_BT_PKT_DH1 = 0, ++ MP_BT_PKT_DH3 = 1, ++ MP_BT_PKT_DH5 = 2, ++ MP_BT_PKT_2DH1 = 3, ++ MP_BT_PKT_2DH3 = 4, ++ MP_BT_PKT_2DH5 = 5, ++ MP_BT_PKT_3DH1 = 6, ++ MP_BT_PKT_3DH3 = 7, ++ MP_BT_PKT_3DH5 = 8, ++ MP_BT_PKT_LE = 9, ++ MP_BT_PKT_MAX ++}MP_BT_PKT_TYPE,*PMP_BT_PKT_TYPE; ++// txrxPayloadType ++typedef enum _MP_BT_PAYLOAD_TYPE{ ++ MP_BT_PAYLOAD_01010101 = 0, ++ MP_BT_PAYLOAD_ALL_1 = 1, ++ MP_BT_PAYLOAD_ALL_0 = 2, ++ MP_BT_PAYLOAD_11110000 = 3, ++ MP_BT_PAYLOAD_PRBS9 = 4, ++ MP_BT_PAYLOAD_MAX ++}MP_BT_PAYLOAD_TYPE,*PMP_BT_PAYLOAD_TYPE; ++ ++ ++// definition for BT_UP_OP_BT_TEST_CTRL ++typedef enum _MP_BT_TEST_CTRL{ ++ MP_BT_TEST_STOP_ALL_TESTS = 0, ++ MP_BT_TEST_START_RX_TEST = 1, ++ MP_BT_TEST_START_PACKET_TX_TEST = 2, ++ MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3, ++ MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4, ++ MP_BT_TEST_START_PAGE_SCAN_TEST = 5, ++ MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6, ++ MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7, ++ MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8, ++ MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9, ++ MP_BT_TEST_MAX ++}MP_BT_TEST_CTRL,*PMP_BT_TEST_CTRL; ++ ++ ++typedef enum _RTL_EXT_C2H_EVT ++{ ++ EXT_C2H_WIFI_FW_ACTIVE_RSP = 0, ++ EXT_C2H_TRIG_BY_BT_FW = 1, ++ MAX_EXT_C2HEVENT ++}RTL_EXT_C2H_EVT; ++ ++ ++// return status definition to the user layer ++typedef enum _BT_CTRL_STATUS{ ++ BT_STATUS_SUCCESS = 0x00, // Success ++ BT_STATUS_BT_OP_SUCCESS = 0x01, // bt fw op execution success ++ BT_STATUS_H2C_SUCCESS = 0x02, // H2c success ++ BT_STATUS_H2C_TIMTOUT = 0x03, // H2c timeout ++ BT_STATUS_H2C_BT_NO_RSP = 0x04, // H2c sent, bt no rsp ++ BT_STATUS_C2H_SUCCESS = 0x05, // C2h success ++ BT_STATUS_C2H_REQNUM_MISMATCH = 0x06, // bt fw wrong rsp ++ BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x07, // Upper layer OP code version mismatch. ++ BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x08, // Lower layer OP code version mismatch. ++ BT_STATUS_UNKNOWN_OPCODE_U = 0x09, // Unknown Upper layer OP code ++ BT_STATUS_UNKNOWN_OPCODE_L = 0x0a, // Unknown Lower layer OP code ++ BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0b, // Wrong parameters sent by upper layer. ++ BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0c, // bt fw parameter format is not consistency ++ BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0d, // uppery layer parameter value is out of range ++ BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x0e, // bt fw parameter value is out of range ++ BT_STATUS_UNKNOWN_STATUS_L = 0x0f, // bt returned an defined status code ++ BT_STATUS_UNKNOWN_STATUS_H = 0x10, // driver need to do error handle or not handle-well. ++ BT_STATUS_WRONG_LEVEL = 0x11, // should be under passive level ++ BT_STATUS_MAX ++}BT_CTRL_STATUS,*PBT_CTRL_STATUS; ++ ++// OP codes definition between the user layer and driver ++typedef enum _BT_CTRL_OPCODE_UPPER{ ++ BT_UP_OP_BT_READY = 0x00, ++ BT_UP_OP_BT_SET_MODE = 0x01, ++ BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02, ++ BT_UP_OP_BT_SET_GENERAL = 0x03, ++ BT_UP_OP_BT_GET_GENERAL = 0x04, ++ BT_UP_OP_BT_TEST_CTRL = 0x05, ++ BT_UP_OP_TEST_BT = 0x06, ++ BT_UP_OP_MAX ++}BT_CTRL_OPCODE_UPPER,*PBT_CTRL_OPCODE_UPPER; ++ ++ ++typedef enum _BT_SET_GENERAL{ ++ BT_GSET_REG = 0x00, ++ BT_GSET_RESET = 0x01, ++ BT_GSET_TARGET_BD_ADDR = 0x02, ++ BT_GSET_TX_PWR_FINETUNE = 0x03, ++ BT_SET_TRACKING_INTERVAL = 0x04, ++ BT_SET_THERMAL_METER = 0x05, ++ BT_ENABLE_CFO_TRACKING = 0x06, ++ BT_GSET_UPDATE_BT_PATCH = 0x07, ++ BT_GSET_MAX ++}BT_SET_GENERAL,*PBT_SET_GENERAL; ++ ++typedef enum _BT_GET_GENERAL{ ++ BT_GGET_REG = 0x00, ++ BT_GGET_STATUS = 0x01, ++ BT_GGET_REPORT = 0x02, ++ BT_GGET_AFH_MAP = 0x03, ++ BT_GGET_AFH_STATUS = 0x04, ++ BT_GGET_MAX ++}BT_GET_GENERAL,*PBT_GET_GENERAL; ++ ++// definition for BT_UP_OP_BT_SET_GENERAL ++typedef enum _BT_REG_TYPE{ ++ BT_REG_RF = 0, ++ BT_REG_MODEM = 1, ++ BT_REG_BLUEWIZE = 2, ++ BT_REG_VENDOR = 3, ++ BT_REG_LE = 4, ++ BT_REG_MAX ++}BT_REG_TYPE,*PBT_REG_TYPE; ++ ++// definition for BT_LO_OP_GET_AFH_MAP ++typedef enum _BT_AFH_MAP_TYPE{ ++ BT_AFH_MAP_RESULT = 0, ++ BT_AFH_MAP_WIFI_PSD_ONLY = 1, ++ BT_AFH_MAP_WIFI_CH_BW_ONLY = 2, ++ BT_AFH_MAP_BT_PSD_ONLY = 3, ++ BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4, ++ BT_AFH_MAP_MAX ++}BT_AFH_MAP_TYPE,*PBT_AFH_MAP_TYPE; ++ ++// definition for BT_UP_OP_BT_GET_GENERAL ++typedef enum _BT_REPORT_TYPE{ ++ BT_REPORT_RX_PACKET_CNT = 0, ++ BT_REPORT_RX_ERROR_BITS = 1, ++ BT_REPORT_RSSI = 2, ++ BT_REPORT_CFO_HDR_QUALITY = 3, ++ BT_REPORT_CONNECT_TARGET_BD_ADDR = 4, ++ BT_REPORT_MAX ++}BT_REPORT_TYPE,*PBT_REPORT_TYPE; ++ ++VOID ++MPTBT_Test( ++ IN PADAPTER Adapter, ++ IN u1Byte opCode, ++ IN u1Byte byte1, ++ IN u1Byte byte2, ++ IN u1Byte byte3 ++ ); ++ ++NDIS_STATUS ++MPTBT_SendOidBT( ++ IN PADAPTER pAdapter, ++ IN PVOID InformationBuffer, ++ IN ULONG InformationBufferLength, ++ OUT PULONG BytesRead, ++ OUT PULONG BytesNeeded ++ ); ++ ++VOID ++MPTBT_FwC2hBtMpCtrl( ++ PADAPTER Adapter, ++ pu1Byte tmpBuf, ++ u1Byte length ++ ); ++ ++void MPh2c_timeout_handle(void *FunctionContext); ++ ++VOID mptbt_BtControlProcess( ++ PADAPTER Adapter, ++ PVOID pInBuf ++ ); ++ ++#define BT_H2C_MAX_RETRY 1 ++#define BT_MAX_C2H_LEN 20 ++ ++typedef struct _BT_REQ_CMD{ ++ UCHAR opCodeVer; ++ UCHAR OpCode; ++ USHORT paraLength; ++ UCHAR pParamStart[100]; ++} BT_REQ_CMD, *PBT_REQ_CMD; ++ ++typedef struct _BT_RSP_CMD{ ++ USHORT status; ++ USHORT paraLength; ++ UCHAR pParamStart[100]; ++} BT_RSP_CMD, *PBT_RSP_CMD; ++ ++ ++typedef struct _BT_H2C{ ++ u1Byte opCodeVer:4; ++ u1Byte reqNum:4; ++ u1Byte opCode; ++ u1Byte buf[100]; ++}BT_H2C, *PBT_H2C; ++ ++ ++ ++typedef struct _BT_EXT_C2H{ ++ u1Byte extendId; ++ u1Byte statusCode:4; ++ u1Byte retLen:4; ++ u1Byte opCodeVer:4; ++ u1Byte reqNum:4; ++ u1Byte buf[100]; ++}BT_EXT_C2H, *PBT_EXT_C2H; ++ ++typedef enum _BT_OPCODE_STATUS{ ++ BT_OP_STATUS_SUCCESS = 0x00, // Success ++ BT_OP_STATUS_VERSION_MISMATCH = 0x01, ++ BT_OP_STATUS_UNKNOWN_OPCODE = 0x02, ++ BT_OP_STATUS_ERROR_PARAMETER = 0x03, ++ BT_OP_STATUS_MAX ++}BT_OPCODE_STATUS,*PBT_OPCODE_STATUS; ++ ++ ++//OP codes definition between driver and bt fw ++typedef enum _BT_CTRL_OPCODE_LOWER{ ++ BT_LO_OP_GET_BT_VERSION = 0x00, ++ BT_LO_OP_RESET = 0x01, ++ BT_LO_OP_TEST_CTRL = 0x02, ++ BT_LO_OP_SET_BT_MODE = 0x03, ++ BT_LO_OP_SET_CHNL_TX_GAIN = 0x04, ++ BT_LO_OP_SET_PKT_TYPE_LEN = 0x05, ++ BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, ++ BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, ++ BT_LO_OP_SET_PKT_HEADER = 0x08, ++ BT_LO_OP_SET_WHITENCOEFF = 0x09, ++ BT_LO_OP_SET_BD_ADDR_L = 0x0a, ++ BT_LO_OP_SET_BD_ADDR_H = 0x0b, ++ BT_LO_OP_WRITE_REG_ADDR = 0x0c, ++ BT_LO_OP_WRITE_REG_VALUE = 0x0d, ++ BT_LO_OP_GET_BT_STATUS = 0x0e, ++ BT_LO_OP_GET_BD_ADDR_L = 0x0f, ++ BT_LO_OP_GET_BD_ADDR_H = 0x10, ++ BT_LO_OP_READ_REG = 0x11, ++ BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12, ++ BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13, ++ BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14, ++ BT_LO_OP_GET_RX_PKT_CNT_L = 0x15, ++ BT_LO_OP_GET_RX_PKT_CNT_H = 0x16, ++ BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17, ++ BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18, ++ BT_LO_OP_GET_RSSI = 0x19, ++ BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a, ++ BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b, ++ BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c, ++ BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d, ++ BT_LO_OP_GET_AFH_MAP_L = 0x1e, ++ BT_LO_OP_GET_AFH_MAP_M = 0x1f, ++ BT_LO_OP_GET_AFH_MAP_H = 0x20, ++ BT_LO_OP_GET_AFH_STATUS = 0x21, ++ BT_LO_OP_SET_TRACKING_INTERVAL = 0x22, ++ BT_LO_OP_SET_THERMAL_METER = 0x23, ++ BT_LO_OP_ENABLE_CFO_TRACKING = 0x24, ++ BT_LO_OP_MAX ++}BT_CTRL_OPCODE_LOWER,*PBT_CTRL_OPCODE_LOWER; ++ ++#endif /* #if(MP_DRIVER == 1) */ ++ ++#endif // #ifndef __INC_MPT_BT_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_byteorder.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_byteorder.h +new file mode 100644 +index 00000000..ad72188e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_byteorder.h +@@ -0,0 +1,40 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL871X_BYTEORDER_H_ ++#define _RTL871X_BYTEORDER_H_ ++ ++#include ++ ++#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN) ++#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n" ++#endif ++ ++#if defined (CONFIG_LITTLE_ENDIAN) ++#ifndef CONFIG_PLATFORM_MSTAR ++# include ++#endif ++#elif defined (CONFIG_BIG_ENDIAN) ++# include ++#else ++# error "Must be LITTLE/BIG Endian Host" ++#endif ++ ++#endif /* _RTL871X_BYTEORDER_H_ */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_cmd.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_cmd.h +new file mode 100644 +index 00000000..97a468c0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_cmd.h +@@ -0,0 +1,1178 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_CMD_H_ ++#define __RTW_CMD_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define C2H_MEM_SZ (16*1024) ++ ++#ifndef CONFIG_RTL8711FW ++ ++ #include ++ #include // ++ ++ ++ #define FREE_CMDOBJ_SZ 128 ++ ++ #define MAX_CMDSZ 1024 ++ #define MAX_RSPSZ 512 ++ #define MAX_EVTSZ 1024 ++ ++#ifdef PLATFORM_OS_CE ++ #define CMDBUFF_ALIGN_SZ 4 ++#else ++ #define CMDBUFF_ALIGN_SZ 512 ++#endif ++ ++ struct cmd_obj { ++ _adapter *padapter; ++ u16 cmdcode; ++ u8 res; ++ u8 *parmbuf; ++ u32 cmdsz; ++ u8 *rsp; ++ u32 rspsz; ++ //_sema cmd_sem; ++ _list list; ++ }; ++ ++ struct cmd_priv { ++ _sema cmd_queue_sema; ++ //_sema cmd_done_sema; ++ _sema terminate_cmdthread_sema; ++ _queue cmd_queue; ++ u8 cmd_seq; ++ u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *cmd_allocated_buf; ++ u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *rsp_allocated_buf; ++ u32 cmd_issued_cnt; ++ u32 cmd_done_cnt; ++ u32 rsp_cnt; ++ u8 cmdthd_running; ++ u8 stop_req; ++ _adapter *padapter; ++ }; ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ struct evt_obj { ++ u16 evtcode; ++ u8 res; ++ u8 *parmbuf; ++ u32 evtsz; ++ _list list; ++ }; ++#endif ++ ++ struct evt_priv { ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _sema evt_notify; ++ _sema terminate_evtthread_sema; ++ _queue evt_queue; ++#endif ++ ++#define CONFIG_C2H_WK ++#ifdef CONFIG_C2H_WK ++ _workitem c2h_wk; ++ bool c2h_wk_alive; ++ struct rtw_cbuf *c2h_queue; ++ #define C2H_QUEUE_MAX_LEN 10 ++#endif ++ ++#ifdef CONFIG_H2CLBK ++ _sema lbkevt_done; ++ u8 lbkevt_limit; ++ u8 lbkevt_num; ++ u8 *cmdevt_parm; ++#endif ++ ATOMIC_T event_seq; ++ u8 *evt_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *evt_allocated_buf; ++ u32 evt_done_cnt; ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ u8 *c2h_mem; ++ u8 *allocated_c2h_mem; ++#ifdef PLATFORM_OS_XP ++ PMDL pc2h_mdl; ++#endif ++#endif ++ ++ }; ++ ++#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ ++do {\ ++ _rtw_init_listhead(&pcmd->list);\ ++ pcmd->cmdcode = code;\ ++ pcmd->parmbuf = (u8 *)(pparm);\ ++ pcmd->cmdsz = sizeof (*pparm);\ ++ pcmd->rsp = NULL;\ ++ pcmd->rspsz = 0;\ ++} while(0) ++ ++struct c2h_evt_hdr { ++ u8 id:4; ++ u8 plen:4; ++ u8 seq; ++ u8 payload[0]; ++}; ++ ++#define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen) ++ ++extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); ++extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); ++extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); ++extern struct evt_obj *rtw_dequeue_evt(_queue *queue); ++extern void rtw_free_evt_obj(struct evt_obj *pcmd); ++#endif ++ ++void rtw_stop_cmd_thread(_adapter *adapter); ++thread_return rtw_cmd_thread(thread_context context); ++ ++extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); ++extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); ++ ++extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv); ++extern void rtw_free_evt_priv (struct evt_priv *pevtpriv); ++extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); ++extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); ++#ifdef CONFIG_P2P ++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ); ++#endif //CONFIG_P2P ++ ++#else ++ #include ++#endif /* CONFIG_RTL8711FW */ ++ ++enum rtw_drvextra_cmd_id ++{ ++ NONE_WK_CID, ++ DYNAMIC_CHK_WK_CID, ++ DM_CTRL_WK_CID, ++ PBC_POLLING_WK_CID, ++ POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend ++ LPS_CTRL_WK_CID, ++ ANT_SELECT_WK_CID, ++ P2P_PS_WK_CID, ++ P2P_PROTO_WK_CID, ++ CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty ++ INTEl_WIDI_WK_CID, ++ C2H_WK_CID, ++ RTP_TIMER_CFG_WK_CID, ++ RESET_SECURITYPRIV, // add for CONFIG_IEEE80211W, none 11w also can use ++ FREE_ASSOC_RESOURCES, // add for CONFIG_IEEE80211W, none 11w also can use ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ EVENT_POLLING_CID, ++#endif ++ MAX_WK_CID ++}; ++ ++enum LPS_CTRL_TYPE ++{ ++ LPS_CTRL_SCAN=0, ++ LPS_CTRL_JOINBSS=1, ++ LPS_CTRL_CONNECT=2, ++ LPS_CTRL_DISCONNECT=3, ++ LPS_CTRL_SPECIAL_PACKET=4, ++ LPS_CTRL_LEAVE=5, ++}; ++ ++enum RFINTFS { ++ SWSI, ++ HWSI, ++ HWPI, ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC(C) ++ ++Notes: To enter USB suspend mode ++ ++Command Mode ++ ++*/ ++struct usb_suspend_parm { ++ u32 action;// 1: sleep, 0:resume ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC ++ ++Notes: To join a known BSS. ++ ++Command-Event Mode ++ ++*/ ++ ++/* ++Caller Mode: Infra, Ad-Hoc ++ ++Notes: To join the specified bss ++ ++Command Event Mode ++ ++*/ ++struct joinbss_parm { ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC(C) ++ ++Notes: To disconnect the current associated BSS ++ ++Command Mode ++ ++*/ ++struct disconnect_parm { ++ u32 deauth_timeout_ms; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC(M) ++ ++Notes: To create a BSS ++ ++Command Mode ++*/ ++struct createbss_parm { ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC, Infra ++ ++Notes: To set the NIC mode of RTL8711 ++ ++Command Mode ++ ++The definition of mode: ++ ++#define IW_MODE_AUTO 0 // Let the driver decides which AP to join ++#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients) ++#define IW_MODE_INFRA 2 // Multi cell network, roaming, .. ++#define IW_MODE_MASTER 3 // Synchronisation master or Access Point ++#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder) ++#define IW_MODE_SECOND 5 // Secondary master/repeater (backup) ++#define IW_MODE_MONITOR 6 // Passive monitor (listen only) ++ ++*/ ++struct setopmode_parm { ++ u8 mode; ++ u8 rsvd[3]; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC, Infra ++ ++Notes: To ask RTL8711 performing site-survey ++ ++Command-Event Mode ++ ++*/ ++ ++#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9 ++#define RTW_CHANNEL_SCAN_AMOUNT (14+37) ++struct sitesurvey_parm { ++ sint scan_mode; //active: 1, passive: 0 ++ /* sint bsslimit; // 1 ~ 48 */ ++ u8 ssid_num; ++ u8 ch_num; ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++ struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To set the auth type of RTL8711. open/shared/802.1x ++ ++Command Mode ++ ++*/ ++struct setauth_parm { ++ u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x ++ u8 _1x; //0: PSK, 1: TLS ++ u8 rsvd[2]; ++}; ++ ++/* ++Caller Mode: Infra ++ ++a. algorithm: wep40, wep104, tkip & aes ++b. keytype: grp key/unicast key ++c. key contents ++ ++when shared key ==> keyid is the camid ++when 802.1x ==> keyid [0:1] ==> grp key ++when 802.1x ==> keyid > 2 ==> unicast key ++ ++*/ ++struct setkey_parm { ++ u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 ++ u8 keyid; ++ u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x ++ u8 set_tx; // 1: main tx key for wep. 0: other key. ++ u8 key[16]; // this could be 40 or 104 ++}; ++ ++/* ++When in AP or Ad-Hoc mode, this is used to ++allocate an sw/hw entry for a newly associated sta. ++ ++Command ++ ++when shared key ==> algorithm/keyid ++ ++*/ ++struct set_stakey_parm { ++ u8 addr[ETH_ALEN]; ++ u8 algorithm; ++ u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_ ++ u8 key[16]; ++}; ++ ++struct set_stakey_rsp { ++ u8 addr[ETH_ALEN]; ++ u8 keyid; ++ u8 rsvd; ++}; ++ ++/* ++Caller Ad-Hoc/AP ++ ++Command -Rsp(AID == CAMID) mode ++ ++This is to force fw to add an sta_data entry per driver's request. ++ ++FW will write an cam entry associated with it. ++ ++*/ ++struct set_assocsta_parm { ++ u8 addr[ETH_ALEN]; ++}; ++ ++struct set_assocsta_rsp { ++ u8 cam_id; ++ u8 rsvd[3]; ++}; ++ ++/* ++ Caller Ad-Hoc/AP ++ ++ Command mode ++ ++ This is to force fw to del an sta_data entry per driver's request ++ ++ FW will invalidate the cam entry associated with it. ++ ++*/ ++struct del_assocsta_parm { ++ u8 addr[ETH_ALEN]; ++}; ++ ++/* ++Caller Mode: AP/Ad-HoC(M) ++ ++Notes: To notify fw that given staid has changed its power state ++ ++Command Mode ++ ++*/ ++struct setstapwrstate_parm { ++ u8 staid; ++ u8 status; ++ u8 hwaddr[6]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To setup the basic rate of RTL8711 ++ ++Command Mode ++ ++*/ ++struct setbasicrate_parm { ++ u8 basicrates[NumRates]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To read the current basic rate ++ ++Command-Rsp Mode ++ ++*/ ++struct getbasicrate_parm { ++ u32 rsvd; ++}; ++ ++struct getbasicrate_rsp { ++ u8 basicrates[NumRates]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To setup the data rate of RTL8711 ++ ++Command Mode ++ ++*/ ++struct setdatarate_parm { ++#ifdef MP_FIRMWARE_OFFLOAD ++ u32 curr_rateidx; ++#else ++ u8 mac_id; ++ u8 datarates[NumRates]; ++#endif ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To read the current data rate ++ ++Command-Rsp Mode ++ ++*/ ++struct getdatarate_parm { ++ u32 rsvd; ++ ++}; ++struct getdatarate_rsp { ++ u8 datarates[NumRates]; ++}; ++ ++ ++/* ++Caller Mode: Any ++AP: AP can use the info for the contents of beacon frame ++Infra: STA can use the info when sitesurveying ++Ad-HoC(M): Like AP ++Ad-HoC(C): Like STA ++ ++ ++Notes: To set the phy capability of the NIC ++ ++Command Mode ++ ++*/ ++ ++struct setphyinfo_parm { ++ struct regulatory_class class_sets[NUM_REGULATORYS]; ++ u8 status; ++}; ++ ++struct getphyinfo_parm { ++ u32 rsvd; ++}; ++ ++struct getphyinfo_rsp { ++ struct regulatory_class class_sets[NUM_REGULATORYS]; ++ u8 status; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To set the channel/modem/band ++This command will be used when channel/modem/band is changed. ++ ++Command Mode ++ ++*/ ++struct setphy_parm { ++ u8 rfchannel; ++ u8 modem; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To get the current setting of channel/modem/band ++ ++Command-Rsp Mode ++ ++*/ ++struct getphy_parm { ++ u32 rsvd; ++ ++}; ++struct getphy_rsp { ++ u8 rfchannel; ++ u8 modem; ++}; ++ ++struct readBB_parm { ++ u8 offset; ++}; ++struct readBB_rsp { ++ u8 value; ++}; ++ ++struct readTSSI_parm { ++ u8 offset; ++}; ++struct readTSSI_rsp { ++ u8 value; ++}; ++ ++struct writeBB_parm { ++ u8 offset; ++ u8 value; ++}; ++ ++struct readRF_parm { ++ u8 offset; ++}; ++struct readRF_rsp { ++ u32 value; ++}; ++ ++struct writeRF_parm { ++ u32 offset; ++ u32 value; ++}; ++ ++struct getrfintfs_parm { ++ u8 rfintfs; ++}; ++ ++ ++struct Tx_Beacon_param ++{ ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++ Notes: This command is used for H2C/C2H loopback testing ++ ++ mac[0] == 0 ++ ==> CMD mode, return H2C_SUCCESS. ++ The following condition must be ture under CMD mode ++ mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; ++ s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; ++ s2 == (b1 << 8 | b0); ++ ++ mac[0] == 1 ++ ==> CMD_RSP mode, return H2C_SUCCESS_RSP ++ ++ The rsp layout shall be: ++ rsp: parm: ++ mac[0] = mac[5]; ++ mac[1] = mac[4]; ++ mac[2] = mac[3]; ++ mac[3] = mac[2]; ++ mac[4] = mac[1]; ++ mac[5] = mac[0]; ++ s0 = s1; ++ s1 = swap16(s0); ++ w0 = swap32(w1); ++ b0 = b1 ++ s2 = s0 + s1 ++ b1 = b0 ++ w1 = w0 ++ ++ mac[0] == 2 ++ ==> CMD_EVENT mode, return H2C_SUCCESS ++ The event layout shall be: ++ event: parm: ++ mac[0] = mac[5]; ++ mac[1] = mac[4]; ++ mac[2] = event's sequence number, starting from 1 to parm's marc[3] ++ mac[3] = mac[2]; ++ mac[4] = mac[1]; ++ mac[5] = mac[0]; ++ s0 = swap16(s0) - event.mac[2]; ++ s1 = s1 + event.mac[2]; ++ w0 = swap32(w0); ++ b0 = b1 ++ s2 = s0 + event.mac[2] ++ b1 = b0 ++ w1 = swap32(w1) - event.mac[2]; ++ ++ parm->mac[3] is the total event counts that host requested. ++ ++ ++ event will be the same with the cmd's param. ++ ++*/ ++ ++#ifdef CONFIG_H2CLBK ++ ++struct seth2clbk_parm { ++ u8 mac[6]; ++ u16 s0; ++ u16 s1; ++ u32 w0; ++ u8 b0; ++ u16 s2; ++ u8 b1; ++ u32 w1; ++}; ++ ++struct geth2clbk_parm { ++ u32 rsv; ++}; ++ ++struct geth2clbk_rsp { ++ u8 mac[6]; ++ u16 s0; ++ u16 s1; ++ u32 w0; ++ u8 b0; ++ u16 s2; ++ u8 b1; ++ u32 w1; ++}; ++ ++#endif /* CONFIG_H2CLBK */ ++ ++// CMD param Formart for driver extra cmd handler ++struct drvextra_cmd_parm { ++ int ec_id; //extra cmd id ++ int type_size; // Can use this field as the type id or command size ++ unsigned char *pbuf; ++}; ++ ++/*------------------- Below are used for RF/BB tunning ---------------------*/ ++ ++struct setantenna_parm { ++ u8 tx_antset; ++ u8 rx_antset; ++ u8 tx_antenna; ++ u8 rx_antenna; ++}; ++ ++struct enrateadaptive_parm { ++ u32 en; ++}; ++ ++struct settxagctbl_parm { ++ u32 txagc[MAX_RATES_LENGTH]; ++}; ++ ++struct gettxagctbl_parm { ++ u32 rsvd; ++}; ++struct gettxagctbl_rsp { ++ u32 txagc[MAX_RATES_LENGTH]; ++}; ++ ++struct setagcctrl_parm { ++ u32 agcctrl; // 0: pure hw, 1: fw ++}; ++ ++ ++struct setssup_parm { ++ u32 ss_ForceUp[MAX_RATES_LENGTH]; ++}; ++ ++struct getssup_parm { ++ u32 rsvd; ++}; ++struct getssup_rsp { ++ u8 ss_ForceUp[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setssdlevel_parm { ++ u8 ss_DLevel[MAX_RATES_LENGTH]; ++}; ++ ++struct getssdlevel_parm { ++ u32 rsvd; ++}; ++struct getssdlevel_rsp { ++ u8 ss_DLevel[MAX_RATES_LENGTH]; ++}; ++ ++struct setssulevel_parm { ++ u8 ss_ULevel[MAX_RATES_LENGTH]; ++}; ++ ++struct getssulevel_parm { ++ u32 rsvd; ++}; ++struct getssulevel_rsp { ++ u8 ss_ULevel[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setcountjudge_parm { ++ u8 count_judge[MAX_RATES_LENGTH]; ++}; ++ ++struct getcountjudge_parm { ++ u32 rsvd; ++}; ++struct getcountjudge_rsp { ++ u8 count_judge[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setratable_parm { ++ u8 ss_ForceUp[NumRates]; ++ u8 ss_ULevel[NumRates]; ++ u8 ss_DLevel[NumRates]; ++ u8 count_judge[NumRates]; ++}; ++ ++struct getratable_parm { ++ uint rsvd; ++}; ++struct getratable_rsp { ++ u8 ss_ForceUp[NumRates]; ++ u8 ss_ULevel[NumRates]; ++ u8 ss_DLevel[NumRates]; ++ u8 count_judge[NumRates]; ++}; ++ ++ ++//to get TX,RX retry count ++struct gettxretrycnt_parm{ ++ unsigned int rsvd; ++}; ++struct gettxretrycnt_rsp{ ++ unsigned long tx_retrycnt; ++}; ++ ++struct getrxretrycnt_parm{ ++ unsigned int rsvd; ++}; ++struct getrxretrycnt_rsp{ ++ unsigned long rx_retrycnt; ++}; ++ ++//to get BCNOK,BCNERR count ++struct getbcnokcnt_parm{ ++ unsigned int rsvd; ++}; ++struct getbcnokcnt_rsp{ ++ unsigned long bcnokcnt; ++}; ++ ++struct getbcnerrcnt_parm{ ++ unsigned int rsvd; ++}; ++struct getbcnerrcnt_rsp{ ++ unsigned long bcnerrcnt; ++}; ++ ++// to get current TX power level ++struct getcurtxpwrlevel_parm{ ++ unsigned int rsvd; ++}; ++struct getcurtxpwrlevel_rsp{ ++ unsigned short tx_power; ++}; ++ ++struct setprobereqextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setassocreqextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setproberspextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setassocrspextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++ ++struct addBaReq_parm ++{ ++ unsigned int tid; ++ u8 addr[ETH_ALEN]; ++}; ++ ++/*H2C Handler index: 46 */ ++struct set_ch_parm { ++ u8 ch; ++ u8 bw; ++ u8 ch_offset; ++}; ++ ++#ifdef MP_FIRMWARE_OFFLOAD ++/*H2C Handler index: 47 */ ++struct SetTxPower_parm ++{ ++ u8 TxPower; ++}; ++ ++/*H2C Handler index: 48 */ ++struct SwitchAntenna_parm ++{ ++ u16 antenna_tx; ++ u16 antenna_rx; ++// R_ANTENNA_SELECT_CCK cck_txrx; ++ u8 cck_txrx; ++}; ++ ++/*H2C Handler index: 49 */ ++struct SetCrystalCap_parm ++{ ++ u32 curr_crystalcap; ++}; ++ ++/*H2C Handler index: 50 */ ++struct SetSingleCarrierTx_parm ++{ ++ u8 bStart; ++}; ++ ++/*H2C Handler index: 51 */ ++struct SetSingleToneTx_parm ++{ ++ u8 bStart; ++ u8 curr_rfpath; ++}; ++ ++/*H2C Handler index: 52 */ ++struct SetCarrierSuppressionTx_parm ++{ ++ u8 bStart; ++ u32 curr_rateidx; ++}; ++ ++/*H2C Handler index: 53 */ ++struct SetContinuousTx_parm ++{ ++ u8 bStart; ++ u8 CCK_flag; /*1:CCK 2:OFDM*/ ++ u32 curr_rateidx; ++}; ++ ++/*H2C Handler index: 54 */ ++struct SwitchBandwidth_parm ++{ ++ u8 curr_bandwidth; ++}; ++ ++#endif /* MP_FIRMWARE_OFFLOAD */ ++ ++/*H2C Handler index: 59 */ ++struct SetChannelPlan_param ++{ ++ u8 channel_plan; ++}; ++ ++/*H2C Handler index: 60 */ ++struct LedBlink_param ++{ ++ PLED_871x pLed; ++}; ++ ++/*H2C Handler index: 61 */ ++struct SetChannelSwitch_param ++{ ++ u8 new_ch_no; ++}; ++ ++/*H2C Handler index: 62 */ ++struct TDLSoption_param ++{ ++ u8 addr[ETH_ALEN]; ++ u8 option; ++}; ++ ++#define GEN_CMD_CODE(cmd) cmd ## _CMD_ ++ ++ ++/* ++ ++Result: ++0x00: success ++0x01: sucess, and check Response. ++0x02: cmd ignored due to duplicated sequcne number ++0x03: cmd dropped due to invalid cmd code ++0x04: reserved. ++ ++*/ ++ ++#define H2C_RSP_OFFSET 512 ++ ++#define H2C_SUCCESS 0x00 ++#define H2C_SUCCESS_RSP 0x01 ++#define H2C_DUPLICATED 0x02 ++#define H2C_DROPPED 0x03 ++#define H2C_PARAMETERS_ERROR 0x04 ++#define H2C_REJECTED 0x05 ++#define H2C_CMD_OVERFLOW 0x06 ++#define H2C_RESERVED 0x07 ++ ++extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); ++extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); ++u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); ++extern u8 rtw_createbss_cmd(_adapter *padapter); ++extern u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz); ++extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); ++extern u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key, bool enqueue); ++extern u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue); ++extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork); ++u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue); ++extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); ++extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); ++extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); ++extern u8 rtw_setbbreg_cmd(_adapter * padapter, u8 offset, u8 val); ++extern u8 rtw_setrfreg_cmd(_adapter * padapter, u8 offset, u32 val); ++extern u8 rtw_getbbreg_cmd(_adapter * padapter, u8 offset, u8 * pval); ++extern u8 rtw_getrfreg_cmd(_adapter * padapter, u8 offset, u8 * pval); ++extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode); ++extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table); ++extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval); ++ ++extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset,u8 *pval); ++extern u8 rtw_setfwdig_cmd(_adapter*padapter, u8 type); ++extern u8 rtw_setfwra_cmd(_adapter*padapter, u8 type); ++ ++extern u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr); ++// add for CONFIG_IEEE80211W, none 11w also can use ++extern u8 rtw_reset_securitypriv_cmd(_adapter*padapter); ++extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter); ++extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); ++ ++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue); ++#if (RATE_ADAPTIVE_SUPPORT==1) ++u8 rtw_rpt_timer_cfg_cmd(_adapter*padapter, u16 minRptTime); ++#endif ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++extern u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue); ++#endif ++ ++extern u8 rtw_ps_cmd(_adapter*padapter); ++ ++#ifdef CONFIG_AP_MODE ++u8 rtw_chk_hi_queue_cmd(_adapter*padapter); ++#endif ++ ++u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); ++extern u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enqueue); ++extern u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed); ++extern u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no); ++extern u8 rtw_tdls_cmd(_adapter*padapter, u8 *addr, u8 option); ++ ++extern u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt); ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++extern u8 rtw_event_polling_cmd(_adapter*padapter); ++#endif ++ ++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); ++ ++extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++ ++ ++struct _cmd_callback { ++ u32 cmd_code; ++ void (*callback)(_adapter *padapter, struct cmd_obj *cmd); ++}; ++ ++enum rtw_h2c_cmd ++{ ++ GEN_CMD_CODE(_Read_MACREG) , /*0*/ ++ GEN_CMD_CODE(_Write_MACREG) , ++ GEN_CMD_CODE(_Read_BBREG) , ++ GEN_CMD_CODE(_Write_BBREG) , ++ GEN_CMD_CODE(_Read_RFREG) , ++ GEN_CMD_CODE(_Write_RFREG) , /*5*/ ++ GEN_CMD_CODE(_Read_EEPROM) , ++ GEN_CMD_CODE(_Write_EEPROM) , ++ GEN_CMD_CODE(_Read_EFUSE) , ++ GEN_CMD_CODE(_Write_EFUSE) , ++ ++ GEN_CMD_CODE(_Read_CAM) , /*10*/ ++ GEN_CMD_CODE(_Write_CAM) , ++ GEN_CMD_CODE(_setBCNITV), ++ GEN_CMD_CODE(_setMBIDCFG), ++ GEN_CMD_CODE(_JoinBss), /*14*/ ++ GEN_CMD_CODE(_DisConnect) , /*15*/ ++ GEN_CMD_CODE(_CreateBss) , ++ GEN_CMD_CODE(_SetOpMode) , ++ GEN_CMD_CODE(_SiteSurvey), /*18*/ ++ GEN_CMD_CODE(_SetAuth) , ++ ++ GEN_CMD_CODE(_SetKey) , /*20*/ ++ GEN_CMD_CODE(_SetStaKey) , ++ GEN_CMD_CODE(_SetAssocSta) , ++ GEN_CMD_CODE(_DelAssocSta) , ++ GEN_CMD_CODE(_SetStaPwrState) , ++ GEN_CMD_CODE(_SetBasicRate) , /*25*/ ++ GEN_CMD_CODE(_GetBasicRate) , ++ GEN_CMD_CODE(_SetDataRate) , ++ GEN_CMD_CODE(_GetDataRate) , ++ GEN_CMD_CODE(_SetPhyInfo) , ++ ++ GEN_CMD_CODE(_GetPhyInfo) , /*30*/ ++ GEN_CMD_CODE(_SetPhy) , ++ GEN_CMD_CODE(_GetPhy) , ++ GEN_CMD_CODE(_readRssi) , ++ GEN_CMD_CODE(_readGain) , ++ GEN_CMD_CODE(_SetAtim) , /*35*/ ++ GEN_CMD_CODE(_SetPwrMode) , ++ GEN_CMD_CODE(_JoinbssRpt), ++ GEN_CMD_CODE(_SetRaTable) , ++ GEN_CMD_CODE(_GetRaTable) , ++ ++ GEN_CMD_CODE(_GetCCXReport), /*40*/ ++ GEN_CMD_CODE(_GetDTMReport), ++ GEN_CMD_CODE(_GetTXRateStatistics), ++ GEN_CMD_CODE(_SetUsbSuspend), ++ GEN_CMD_CODE(_SetH2cLbk), ++ GEN_CMD_CODE(_AddBAReq) , /*45*/ ++ GEN_CMD_CODE(_SetChannel), /*46*/ ++ GEN_CMD_CODE(_SetTxPower), ++ GEN_CMD_CODE(_SwitchAntenna), ++ GEN_CMD_CODE(_SetCrystalCap), ++ GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ ++ ++ GEN_CMD_CODE(_SetSingleToneTx),/*51*/ ++ GEN_CMD_CODE(_SetCarrierSuppressionTx), ++ GEN_CMD_CODE(_SetContinuousTx), ++ GEN_CMD_CODE(_SwitchBandwidth), /*54*/ ++ GEN_CMD_CODE(_TX_Beacon), /*55*/ ++ ++ GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ ++ GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ ++ GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ ++ ++ GEN_CMD_CODE(_SetChannelPlan), /*59*/ ++ GEN_CMD_CODE(_LedBlink), /*60*/ ++ ++ GEN_CMD_CODE(_SetChannelSwitch), /*61*/ ++ GEN_CMD_CODE(_TDLS), /*62*/ ++ ++ MAX_H2CCMD ++}; ++ ++#define _GetBBReg_CMD_ _Read_BBREG_CMD_ ++#define _SetBBReg_CMD_ _Write_BBREG_CMD_ ++#define _GetRFReg_CMD_ _Read_RFREG_CMD_ ++#define _SetRFReg_CMD_ _Write_RFREG_CMD_ ++ ++#ifdef _RTW_CMD_C_ ++struct _cmd_callback rtw_cmd_callback[] = ++{ ++ {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/ ++ {GEN_CMD_CODE(_Write_MACREG), NULL}, ++ {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback}, ++ {GEN_CMD_CODE(_Write_BBREG), NULL}, ++ {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback}, ++ {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ ++ {GEN_CMD_CODE(_Read_EEPROM), NULL}, ++ {GEN_CMD_CODE(_Write_EEPROM), NULL}, ++ {GEN_CMD_CODE(_Read_EFUSE), NULL}, ++ {GEN_CMD_CODE(_Write_EFUSE), NULL}, ++ ++ {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/ ++ {GEN_CMD_CODE(_Write_CAM), NULL}, ++ {GEN_CMD_CODE(_setBCNITV), NULL}, ++ {GEN_CMD_CODE(_setMBIDCFG), NULL}, ++ {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/ ++ {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/ ++ {GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback}, ++ {GEN_CMD_CODE(_SetOpMode), NULL}, ++ {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/ ++ {GEN_CMD_CODE(_SetAuth), NULL}, ++ ++ {GEN_CMD_CODE(_SetKey), NULL}, /*20*/ ++ {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback}, ++ {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback}, ++ {GEN_CMD_CODE(_DelAssocSta), NULL}, ++ {GEN_CMD_CODE(_SetStaPwrState), NULL}, ++ {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/ ++ {GEN_CMD_CODE(_GetBasicRate), NULL}, ++ {GEN_CMD_CODE(_SetDataRate), NULL}, ++ {GEN_CMD_CODE(_GetDataRate), NULL}, ++ {GEN_CMD_CODE(_SetPhyInfo), NULL}, ++ ++ {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/ ++ {GEN_CMD_CODE(_SetPhy), NULL}, ++ {GEN_CMD_CODE(_GetPhy), NULL}, ++ {GEN_CMD_CODE(_readRssi), NULL}, ++ {GEN_CMD_CODE(_readGain), NULL}, ++ {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/ ++ {GEN_CMD_CODE(_SetPwrMode), NULL}, ++ {GEN_CMD_CODE(_JoinbssRpt), NULL}, ++ {GEN_CMD_CODE(_SetRaTable), NULL}, ++ {GEN_CMD_CODE(_GetRaTable) , NULL}, ++ ++ {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ ++ {GEN_CMD_CODE(_GetDTMReport), NULL}, ++ {GEN_CMD_CODE(_GetTXRateStatistics), NULL}, ++ {GEN_CMD_CODE(_SetUsbSuspend), NULL}, ++ {GEN_CMD_CODE(_SetH2cLbk), NULL}, ++ {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/ ++ {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/ ++ {GEN_CMD_CODE(_SetTxPower), NULL}, ++ {GEN_CMD_CODE(_SwitchAntenna), NULL}, ++ {GEN_CMD_CODE(_SetCrystalCap), NULL}, ++ {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/ ++ ++ {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/ ++ {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL}, ++ {GEN_CMD_CODE(_SetContinuousTx), NULL}, ++ {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/ ++ {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/ ++ ++ {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/ ++ {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/ ++ {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/ ++ {GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/ ++ {GEN_CMD_CODE(_LedBlink), NULL},/*60*/ ++ ++ {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/ ++ {GEN_CMD_CODE(_TDLS), NULL},/*62*/ ++}; ++#endif ++ ++#endif // _CMD_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_debug.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_debug.h +new file mode 100644 +index 00000000..f9f69416 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_debug.h +@@ -0,0 +1,482 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_DEBUG_H__ ++#define __RTW_DEBUG_H__ ++ ++#include ++#include ++#include ++ ++ ++#define _drv_always_ 1 ++#define _drv_emerg_ 2 ++#define _drv_alert_ 3 ++#define _drv_crit_ 4 ++#define _drv_err_ 5 ++#define _drv_warning_ 6 ++#define _drv_notice_ 7 ++#define _drv_info_ 8 ++#define _drv_dump_ 9 ++#define _drv_debug_ 10 ++ ++ ++#define _module_rtl871x_xmit_c_ BIT(0) ++#define _module_xmit_osdep_c_ BIT(1) ++#define _module_rtl871x_recv_c_ BIT(2) ++#define _module_recv_osdep_c_ BIT(3) ++#define _module_rtl871x_mlme_c_ BIT(4) ++#define _module_mlme_osdep_c_ BIT(5) ++#define _module_rtl871x_sta_mgt_c_ BIT(6) ++#define _module_rtl871x_cmd_c_ BIT(7) ++#define _module_cmd_osdep_c_ BIT(8) ++#define _module_rtl871x_io_c_ BIT(9) ++#define _module_io_osdep_c_ BIT(10) ++#define _module_os_intfs_c_ BIT(11) ++#define _module_rtl871x_security_c_ BIT(12) ++#define _module_rtl871x_eeprom_c_ BIT(13) ++#define _module_hal_init_c_ BIT(14) ++#define _module_hci_hal_init_c_ BIT(15) ++#define _module_rtl871x_ioctl_c_ BIT(16) ++#define _module_rtl871x_ioctl_set_c_ BIT(17) ++#define _module_rtl871x_ioctl_query_c_ BIT(18) ++#define _module_rtl871x_pwrctrl_c_ BIT(19) ++#define _module_hci_intfs_c_ BIT(20) ++#define _module_hci_ops_c_ BIT(21) ++#define _module_osdep_service_c_ BIT(22) ++#define _module_mp_ BIT(23) ++#define _module_hci_ops_os_c_ BIT(24) ++#define _module_rtl871x_ioctl_os_c BIT(25) ++#define _module_rtl8712_cmd_c_ BIT(26) ++//#define _module_efuse_ BIT(27) ++#define _module_rtl8192c_xmit_c_ BIT(28) ++#define _module_hal_xmit_c_ BIT(28) ++#define _module_efuse_ BIT(29) ++#define _module_rtl8712_recv_c_ BIT(30) ++#define _module_rtl8712_led_c_ BIT(31) ++ ++#undef _MODULE_DEFINE_ ++ ++#if defined _RTW_XMIT_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_ ++#elif defined _XMIT_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_xmit_osdep_c_ ++#elif defined _RTW_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_recv_c_ ++#elif defined _RECV_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_recv_osdep_c_ ++#elif defined _RTW_MLME_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_ ++#elif defined _MLME_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_ ++#elif defined _RTW_MLME_EXT_C_ ++ #define _MODULE_DEFINE_ 1 ++#elif defined _RTW_STA_MGT_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_ ++#elif defined _RTW_CMD_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_ ++#elif defined _CMD_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_cmd_osdep_c_ ++#elif defined _RTW_IO_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_io_c_ ++#elif defined _IO_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_io_osdep_c_ ++#elif defined _OS_INTFS_C_ ++ #define _MODULE_DEFINE_ _module_os_intfs_c_ ++#elif defined _RTW_SECURITY_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_security_c_ ++#elif defined _RTW_EEPROM_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_ ++#elif defined _HAL_INTF_C_ ++ #define _MODULE_DEFINE_ _module_hal_init_c_ ++#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_) ++ #define _MODULE_DEFINE_ _module_hci_hal_init_c_ ++#elif defined _RTL871X_IOCTL_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_ ++#elif defined _RTL871X_IOCTL_SET_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_ ++#elif defined _RTL871X_IOCTL_QUERY_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_ ++#elif defined _RTL871X_PWRCTRL_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_ ++#elif defined _RTW_PWRCTRL_C_ ++ #define _MODULE_DEFINE_ 1 ++#elif defined _HCI_INTF_C_ ++ #define _MODULE_DEFINE_ _module_hci_intfs_c_ ++#elif defined _HCI_OPS_C_ ++ #define _MODULE_DEFINE_ _module_hci_ops_c_ ++#elif defined _SDIO_OPS_C_ ++ #define _MODULE_DEFINE_ 1 ++#elif defined _OSDEP_HCI_INTF_C_ ++ #define _MODULE_DEFINE_ _module_hci_intfs_c_ ++#elif defined _OSDEP_SERVICE_C_ ++ #define _MODULE_DEFINE_ _module_osdep_service_c_ ++#elif defined _HCI_OPS_OS_C_ ++ #define _MODULE_DEFINE_ _module_hci_ops_os_c_ ++#elif defined _RTL871X_IOCTL_LINUX_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c ++#elif defined _RTL8712_CMD_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_ ++#elif defined _RTL8192C_XMIT_C_ ++ #define _MODULE_DEFINE_ 1 ++#elif defined _RTL8723AS_XMIT_C_ ++ #define _MODULE_DEFINE_ 1 ++#elif defined _RTL8712_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ ++#elif defined _RTL8192CU_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ ++#elif defined _RTL871X_MLME_EXT_C_ ++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_ ++#elif defined _RTW_MP_C_ ++ #define _MODULE_DEFINE_ _module_mp_ ++#elif defined _RTW_MP_IOCTL_C_ ++ #define _MODULE_DEFINE_ _module_mp_ ++#elif defined _RTW_EFUSE_C_ ++ #define _MODULE_DEFINE_ _module_efuse_ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++extern void rtl871x_cedbg(const char *fmt, ...); ++#endif ++ ++#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0) ++#define _func_enter_ do{}while(0) ++#define _func_exit_ do{}while(0) ++#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0) ++ ++#ifdef PLATFORM_WINDOWS ++ #define DBG_871X do {} while(0) ++ #define MSG_8192C do {} while(0) ++ #define DBG_8192C do {} while(0) ++ #define DBG_871X_LEVEL do {} while(0) ++#else ++ #define DBG_871X(x, ...) do {} while(0) ++ #define MSG_8192C(x, ...) do {} while(0) ++ #define DBG_8192C(x,...) do {} while(0) ++ #define DBG_871X_LEVEL(x,...) do {} while(0) ++#endif ++ ++#undef _dbgdump ++#ifdef PLATFORM_WINDOWS ++ ++ #ifdef PLATFORM_OS_XP ++ #define _dbgdump DbgPrint ++ #elif defined PLATFORM_OS_CE ++ #define _dbgdump rtl871x_cedbg ++ #endif ++ ++#elif defined PLATFORM_LINUX ++ #define _dbgdump printk ++#elif defined PLATFORM_FREEBSD ++ #define _dbgdump printf ++#endif ++ ++#define DRIVER_PREFIX "RTL871X: " ++#define DEBUG_LEVEL (_drv_err_) ++#if defined (_dbgdump) ++ #undef DBG_871X_LEVEL ++ #define DBG_871X_LEVEL(level, fmt, arg...) \ ++ do {\ ++ if (level <= DEBUG_LEVEL) {\ ++ if (level <= _drv_err_ && level > _drv_always_) \ ++ _dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\ ++ else \ ++ _dbgdump(DRIVER_PREFIX fmt, ##arg);\ ++ }\ ++ }while(0) ++#endif ++ ++#ifdef CONFIG_DEBUG ++#if defined (_dbgdump) ++ #undef DBG_871X ++ #define DBG_871X(...) do {\ ++ _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ ++ }while(0) ++ ++ #undef MSG_8192C ++ #define MSG_8192C(...) do {\ ++ _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ ++ }while(0) ++ ++ #undef DBG_8192C ++ #define DBG_8192C(...) do {\ ++ _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ ++ }while(0) ++#endif ++#endif /* CONFIG_DEBUG */ ++ ++#ifdef CONFIG_DEBUG_RTL871X ++#ifndef _RTL871X_DEBUG_C_ ++ extern u32 GlobalDebugLevel; ++ extern u64 GlobalDebugComponents; ++#endif ++ ++#if defined (_dbgdump) && defined (_MODULE_DEFINE_) ++ ++ #undef RT_TRACE ++ #define RT_TRACE(_Comp, _Level, Fmt)\ ++ do {\ ++ if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\ ++ _dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\ ++ _dbgdump Fmt;\ ++ }\ ++ }while(0) ++ ++#endif ++ ++ ++#if defined (_dbgdump) ++ ++ #undef _func_enter_ ++ #define _func_enter_ \ ++ do { \ ++ if (GlobalDebugLevel >= _drv_debug_) \ ++ { \ ++ _dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\ ++ } \ ++ } while(0) ++ ++ #undef _func_exit_ ++ #define _func_exit_ \ ++ do { \ ++ if (GlobalDebugLevel >= _drv_debug_) \ ++ { \ ++ _dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \ ++ } \ ++ } while(0) ++ ++ #undef RT_PRINT_DATA ++ #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \ ++ if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ ++ { \ ++ int __i; \ ++ u8 *ptr = (u8 *)_HexData; \ ++ _dbgdump("%s", DRIVER_PREFIX); \ ++ _dbgdump(_TitleString); \ ++ for( __i=0; __i<(int)_HexDataLen; __i++ ) \ ++ { \ ++ _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \ ++ if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ ++ } \ ++ _dbgdump("\n"); \ ++ } ++#endif ++#endif /* CONFIG_DEBUG_RTL871X */ ++ ++ ++#ifdef CONFIG_PROC_DEBUG ++ ++ int proc_get_drv_version(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++#ifdef DBG_MEM_ALLOC ++ int proc_get_mstat(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++#endif /* DBG_MEM_ALLOC */ ++ ++ int proc_get_write_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_write_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ int proc_get_read_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_read_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ ++ int proc_get_fwstate(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_sec_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_mlmext_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_qos_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_ht_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_ap_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_adapter_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_trx_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_mac_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_mac_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_mac_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_bb_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_bb_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_bb_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_reg_dump1(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_reg_dump2(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_reg_dump3(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_reg_dump4(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++#ifdef CONFIG_AP_MODE ++ ++ int proc_get_all_sta_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ int proc_get_malloc_cnt(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ int proc_get_best_channel(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ int proc_set_best_channel(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++#endif ++ ++ int proc_get_rx_signal(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_rx_signal(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++#ifdef CONFIG_80211N_HT ++ ++ int proc_get_ht_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_ht_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ int proc_get_cbw40_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_cbw40_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ int proc_get_ampdu_enable(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_ampdu_enable(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ int proc_get_rx_stbc(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_rx_stbc(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++#endif //CONFIG_80211N_HT ++ ++ int proc_get_two_path_rssi(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rssi_disp(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_rssi_disp(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++#ifdef CONFIG_BT_COEXIST ++ int proc_get_btcoex_dbg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_btcoex_dbg(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++#endif //CONFIG_BT_COEXIST ++ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data); ++int proc_set_sreset(struct file *file, const char *buffer, unsigned long count, void *data); ++#endif /* DBG_CONFIG_ERROR_DETECT */ ++ ++int proc_get_odm_dbg_comp(char *page, char **start, off_t offset, int count, int *eof, void *data); ++int proc_set_odm_dbg_comp(struct file *file, const char *buffer, unsigned long count, void *data); ++int proc_get_odm_dbg_level(char *page, char **start, off_t offset, int count, int *eof, void *data); ++int proc_set_odm_dbg_level(struct file *file, const char *buffer, unsigned long count, void *data); ++ ++int proc_get_odm_adaptivity(char *page, char **start, off_t offset, int count, int *eof, void *data); ++int proc_set_odm_adaptivity(struct file *file, const char *buffer, unsigned long count, void *data); ++ ++#endif //CONFIG_PROC_DEBUG ++ ++#endif //__RTW_DEBUG_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_eeprom.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_eeprom.h +new file mode 100644 +index 00000000..564f5cd2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_eeprom.h +@@ -0,0 +1,169 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_EEPROM_H__ ++#define __RTW_EEPROM_H__ ++ ++#include ++#include ++#include ++ ++#define RTL8712_EEPROM_ID 0x8712 ++//#define EEPROM_MAX_SIZE 256 ++ ++#define HWSET_MAX_SIZE_512 512 ++#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 ++ ++#define CLOCK_RATE 50 //100us ++ ++//- EEPROM opcodes ++#define EEPROM_READ_OPCODE 06 ++#define EEPROM_WRITE_OPCODE 05 ++#define EEPROM_ERASE_OPCODE 07 ++#define EEPROM_EWEN_OPCODE 19 // Erase/write enable ++#define EEPROM_EWDS_OPCODE 16 // Erase/write disable ++ ++//Country codes ++#define USA 0x555320 ++#define EUROPE 0x1 //temp, should be provided later ++#define JAPAN 0x2 //temp, should be provided later ++ ++#ifdef CONFIG_SDIO_HCI ++#define eeprom_cis0_sz 17 ++#define eeprom_cis1_sz 50 ++#endif ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_ALPHA 0x1 ++#define EEPROM_CID_Senao 0x3 ++#define EEPROM_CID_NetCore 0x5 ++#define EEPROM_CID_CAMEO 0X8 ++#define EEPROM_CID_SITECOM 0x9 ++#define EEPROM_CID_COREGA 0xB ++#define EEPROM_CID_EDIMAX_BELKIN 0xC ++#define EEPROM_CID_SERCOMM_BELKIN 0xE ++#define EEPROM_CID_CAMEO1 0xF ++#define EEPROM_CID_WNC_COREGA 0x12 ++#define EEPROM_CID_CLEVO 0x13 ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++// ++// Customer ID, note that: ++// This variable is initiailzed through EEPROM or registry, ++// however, its definition may be different with that in EEPROM for ++// EEPROM size consideration. So, we have to perform proper translation between them. ++// Besides, CustomerID of registry has precedence of that of EEPROM. ++// defined below. 060703, by rcnjko. ++// ++typedef enum _RT_CUSTOMER_ID ++{ ++ RT_CID_DEFAULT = 0, ++ RT_CID_8187_ALPHA0 = 1, ++ RT_CID_8187_SERCOMM_PS = 2, ++ RT_CID_8187_HW_LED = 3, ++ RT_CID_8187_NETGEAR = 4, ++ RT_CID_WHQL = 5, ++ RT_CID_819x_CAMEO = 6, ++ RT_CID_819x_RUNTOP = 7, ++ RT_CID_819x_Senao = 8, ++ RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. ++ RT_CID_819x_Netcore = 10, ++ RT_CID_Nettronix = 11, ++ RT_CID_DLINK = 12, ++ RT_CID_PRONET = 13, ++ RT_CID_COREGA = 14, ++ RT_CID_CHINA_MOBILE = 15, ++ RT_CID_819x_ALPHA = 16, ++ RT_CID_819x_Sitecom = 17, ++ RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. ++ RT_CID_819x_Lenovo = 19, ++ RT_CID_819x_QMI = 20, ++ RT_CID_819x_Edimax_Belkin = 21, ++ RT_CID_819x_Sercomm_Belkin = 22, ++ RT_CID_819x_CAMEO1 = 23, ++ RT_CID_819x_MSI = 24, ++ RT_CID_819x_Acer = 25, ++ RT_CID_819x_AzWave_ASUS = 26, ++ RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus ++ RT_CID_819x_HP = 28, ++ RT_CID_819x_WNC_COREGA = 29, ++ RT_CID_819x_Arcadyan_Belkin = 30, ++ RT_CID_819x_SAMSUNG = 31, ++ RT_CID_819x_CLEVO = 32, ++ RT_CID_819x_DELL = 33, ++ RT_CID_819x_PRONETS = 34, ++ RT_CID_819x_Edimax_ASUS = 35, ++ RT_CID_819x_CAMEO_NETGEAR = 36, ++ RT_CID_PLANEX = 37, ++ RT_CID_CC_C = 38, ++ RT_CID_819x_Xavi = 39, ++ RT_CID_819x_FUNAI_TV = 40, ++ RT_CID_819x_ALPHA_WD=41, ++}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; ++ ++struct eeprom_priv ++{ ++ u8 bautoload_fail_flag; ++ u8 bloadfile_fail_flag; ++ u8 bloadmac_fail_flag; ++ //u8 bempty; ++ //u8 sys_config; ++ u8 mac_addr[6]; //PermanentAddress ++ //u8 config0; ++ u16 channel_plan; ++ //u8 country_string[3]; ++ //u8 tx_power_b[15]; ++ //u8 tx_power_g[15]; ++ //u8 tx_power_a[201]; ++ ++ u8 EepromOrEfuse; ++ ++ u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++ u8 EEPROMRFGainOffset; ++ u8 EEPROMRFGainVal; ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++#ifdef CONFIG_SDIO_HCI ++ u8 sdio_setting; ++ u32 ocr; ++ u8 cis0[eeprom_cis0_sz]; ++ u8 cis1[eeprom_cis1_sz]; ++#endif ++}; ++ ++ ++extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data); ++extern u16 eeprom_read16(_adapter *padapter, u16 reg); ++extern void read_eeprom_content(_adapter *padapter); ++extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz); ++ ++extern void read_eeprom_content_by_attrib(_adapter * padapter ); ++ ++#ifdef PLATFORM_LINUX ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++extern int isAdaptorInfoFileValid(void); ++extern int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); ++extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++#endif //PLATFORM_LINUX ++ ++#endif //__RTL871X_EEPROM_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_efuse.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_efuse.h +new file mode 100644 +index 00000000..41a6ef96 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_efuse.h +@@ -0,0 +1,167 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_EFUSE_H__ ++#define __RTW_EFUSE_H__ ++ ++#include ++#include ++ ++#define EFUSE_ERROE_HANDLE 1 ++ ++#define PG_STATE_HEADER 0x01 ++#define PG_STATE_WORD_0 0x02 ++#define PG_STATE_WORD_1 0x04 ++#define PG_STATE_WORD_2 0x08 ++#define PG_STATE_WORD_3 0x10 ++#define PG_STATE_DATA 0x20 ++ ++#define PG_SWBYTE_H 0x01 ++#define PG_SWBYTE_L 0x02 ++ ++#define PGPKT_DATA_SIZE 8 ++ ++#define EFUSE_WIFI 0 ++#define EFUSE_BT 1 ++ ++enum _EFUSE_DEF_TYPE { ++ TYPE_EFUSE_MAX_SECTION = 0, ++ TYPE_EFUSE_REAL_CONTENT_LEN = 1, ++ TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, ++ TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, ++ TYPE_EFUSE_MAP_LEN = 4, ++ TYPE_EFUSE_PROTECT_BYTES_BANK = 5, ++ TYPE_EFUSE_CONTENT_LEN_BANK = 6, ++}; ++ ++/* E-Fuse */ ++#ifdef CONFIG_RTL8192D ++#define EFUSE_MAP_SIZE 256 ++#endif ++#ifdef CONFIG_RTL8192C ++#define EFUSE_MAP_SIZE 128 ++#endif ++#ifdef CONFIG_RTL8723A ++#define EFUSE_MAP_SIZE 256 ++#endif ++#ifdef CONFIG_RTL8188E ++#define EFUSE_MAP_SIZE 512 ++#endif ++ ++#ifdef CONFIG_RTL8188E ++#define EFUSE_MAX_SIZE 256 ++#else ++#define EFUSE_MAX_SIZE 512 ++#endif ++/* end of E-Fuse */ ++ ++#define EFUSE_MAX_MAP_LEN 256 ++#define EFUSE_MAX_HW_SIZE 512 ++#define EFUSE_MAX_SECTION_BASE 16 ++ ++#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) ++#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) ++#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) ++ ++#define EFUSE_REPEAT_THRESHOLD_ 3 ++ ++//============================================= ++// The following is for BT Efuse definition ++//============================================= ++#define EFUSE_BT_MAX_MAP_LEN 1024 ++#define EFUSE_MAX_BANK 4 ++#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) ++//============================================= ++/*--------------------------Define Parameters-------------------------------*/ ++#define EFUSE_MAX_WORD_UNIT 4 ++ ++/*------------------------------Define structure----------------------------*/ ++typedef struct PG_PKT_STRUCT_A{ ++ u8 offset; ++ u8 word_en; ++ u8 data[8]; ++ u8 word_cnts; ++}PGPKT_STRUCT,*PPGPKT_STRUCT; ++ ++/*------------------------------Define structure----------------------------*/ ++typedef struct _EFUSE_HAL{ ++ u8 fakeEfuseBank; ++ u32 fakeEfuseUsedBytes; ++ u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; ++ u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; ++ u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; ++ ++ u16 BTEfuseUsedBytes; ++ u8 BTEfuseUsedPercentage; ++ u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++ u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; ++ u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; ++ ++ u16 fakeBTEfuseUsedBytes; ++ u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++ u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; ++ u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; ++}EFUSE_HAL, *PEFUSE_HAL; ++ ++ ++/*------------------------Export global variable----------------------------*/ ++extern u8 fakeEfuseBank; ++extern u32 fakeEfuseUsedBytes; ++extern u8 fakeEfuseContent[]; ++extern u8 fakeEfuseInitMap[]; ++extern u8 fakeEfuseModifiedMap[]; ++ ++extern u32 BTEfuseUsedBytes; ++extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++extern u8 BTEfuseInitMap[]; ++extern u8 BTEfuseModifiedMap[]; ++ ++extern u32 fakeBTEfuseUsedBytes; ++extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++extern u8 fakeBTEfuseInitMap[]; ++extern u8 fakeBTEfuseModifiedMap[]; ++/*------------------------Export global variable----------------------------*/ ++ ++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); ++u16 efuse_GetMaxSize(PADAPTER padapter); ++u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); ++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++ ++u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); ++u8 Efuse_CalculateWordCnts(u8 word_en); ++void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; ++void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); ++u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); ++u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); ++ ++void Efuse_PowerSwitch(PADAPTER pAdapter,u8 bWrite,u8 PwrState); ++int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); ++int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); ++u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ ++u8 EFUSE_Read1Byte(PADAPTER pAdapter, u16 Address); ++void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); ++void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_event.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_event.h +new file mode 100644 +index 00000000..4299ddcf +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_event.h +@@ -0,0 +1,154 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_EVENT_H_ ++#define _RTW_EVENT_H_ ++#include ++#include ++ ++#ifndef CONFIG_RTL8711FW ++#ifdef PLATFORM_LINUX ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#include ++#else ++#include ++#endif ++#include ++#endif ++#else ++#include ++#endif//CONFIG_RTL8711FW ++ ++ ++ ++#ifdef CONFIG_H2CLBK ++#include ++#endif ++ ++/* ++Used to report a bss has been scanned ++ ++*/ ++struct survey_event { ++ WLAN_BSSID_EX bss; ++}; ++ ++/* ++Used to report that the requested site survey has been done. ++ ++bss_cnt indicates the number of bss that has been reported. ++ ++ ++*/ ++struct surveydone_event { ++ unsigned int bss_cnt; ++ ++}; ++ ++/* ++Used to report the link result of joinning the given bss ++ ++ ++join_res: ++-1: authentication fail ++-2: association fail ++> 0: TID ++ ++*/ ++struct joinbss_event { ++ struct wlan_network network; ++}; ++ ++/* ++Used to report a given STA has joinned the created BSS. ++It is used in AP/Ad-HoC(M) mode. ++ ++ ++*/ ++struct stassoc_event { ++ unsigned char macaddr[6]; ++ unsigned char rsvd[2]; ++ int cam_id; ++ ++}; ++ ++struct stadel_event { ++ unsigned char macaddr[6]; ++ unsigned char rsvd[2]; //for reason ++ int mac_id; ++}; ++ ++struct addba_event ++{ ++ unsigned int tid; ++}; ++ ++ ++#ifdef CONFIG_H2CLBK ++struct c2hlbk_event{ ++ unsigned char mac[6]; ++ unsigned short s0; ++ unsigned short s1; ++ unsigned int w0; ++ unsigned char b0; ++ unsigned short s2; ++ unsigned char b1; ++ unsigned int w1; ++}; ++#endif//CONFIG_H2CLBK ++ ++#define GEN_EVT_CODE(event) event ## _EVT_ ++ ++ ++ ++struct fwevent { ++ u32 parmsize; ++ void (*event_callback)(_adapter *dev, u8 *pbuf); ++}; ++ ++ ++#define C2HEVENT_SZ 32 ++ ++struct event_node{ ++ unsigned char *node; ++ unsigned char evt_code; ++ unsigned short evt_sz; ++ volatile int *caller_ff_tail; ++ int caller_ff_sz; ++}; ++ ++struct c2hevent_queue { ++ volatile int head; ++ volatile int tail; ++ struct event_node nodes[C2HEVENT_SZ]; ++ unsigned char seq; ++}; ++ ++#define NETWORK_QUEUE_SZ 4 ++ ++struct network_queue { ++ volatile int head; ++ volatile int tail; ++ WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ]; ++}; ++ ++ ++#endif // _WLANEVENT_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ht.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ht.h +new file mode 100644 +index 00000000..3cd904df +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ht.h +@@ -0,0 +1,50 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_HT_H_ ++#define _RTW_HT_H_ ++ ++#include ++#include ++#include "wifi.h" ++ ++struct ht_priv ++{ ++ u32 ht_option; ++ u32 ampdu_enable;//for enable Tx A-MPDU ++ //u8 baddbareq_issued[16]; ++ u32 tx_amsdu_enable;//for enable Tx A-MSDU ++ u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx ++ u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback. ++ ++ u8 bwmode;// ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ ++ //for processing Tx A-MPDU ++ u8 agg_enable_bitmap; ++ //u8 ADDBA_retry_count; ++ u8 candidate_tid_bitmap; ++ ++ struct rtw_ieee80211_ht_cap ht_cap; ++ ++}; ++ ++#endif //_RTL871X_HT_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_io.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_io.h +new file mode 100644 +index 00000000..bc09b0d8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_io.h +@@ -0,0 +1,534 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef _RTW_IO_H_ ++#define _RTW_IO_H_ ++ ++#include ++#include ++#include ++ ++#ifdef PLATFORM_LINUX ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#include ++#else ++#include ++#endif ++#include ++//#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++#include ++#else ++#include ++#endif ++ ++#endif //CONFIG_USB_HCI ++ ++#endif //PLATFORM_LINUX ++ ++ ++#define NUM_IOREQ 8 ++ ++#ifdef PLATFORM_WINDOWS ++#define MAX_PROT_SZ 64 ++#endif ++#ifdef PLATFORM_LINUX ++#define MAX_PROT_SZ (64-16) ++#endif ++ ++#define _IOREADY 0 ++#define _IO_WAIT_COMPLETE 1 ++#define _IO_WAIT_RSP 2 ++ ++// IO COMMAND TYPE ++#define _IOSZ_MASK_ (0x7F) ++#define _IO_WRITE_ BIT(7) ++#define _IO_FIXED_ BIT(8) ++#define _IO_BURST_ BIT(9) ++#define _IO_BYTE_ BIT(10) ++#define _IO_HW_ BIT(11) ++#define _IO_WORD_ BIT(12) ++#define _IO_SYNC_ BIT(13) ++#define _IO_CMDMASK_ (0x1F80) ++ ++ ++/* ++ For prompt mode accessing, caller shall free io_req ++ Otherwise, io_handler will free io_req ++*/ ++ ++ ++ ++// IO STATUS TYPE ++#define _IO_ERR_ BIT(2) ++#define _IO_SUCCESS_ BIT(1) ++#define _IO_DONE_ BIT(0) ++ ++ ++#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) ++#define IO_RD16 (_IO_SYNC_ | _IO_HW_) ++#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) ++ ++#define IO_RD32_ASYNC (_IO_WORD_) ++#define IO_RD16_ASYNC (_IO_HW_) ++#define IO_RD8_ASYNC (_IO_BYTE_) ++ ++#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) ++#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) ++#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) ++ ++#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) ++#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) ++#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) ++ ++/* ++ ++ Only Sync. burst accessing is provided. ++ ++*/ ++ ++#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) ++#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) ++ ++ ++ ++//below is for the intf_option bit defition... ++ ++#define _INTF_ASYNC_ BIT(0) //support async io ++ ++struct intf_priv; ++struct intf_hdl; ++struct io_queue; ++ ++struct _io_ops ++{ ++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); ++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); ++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); ++ ++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ ++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); ++ ++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem); ++ ++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl); ++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl); ++ ++}; ++ ++struct io_req { ++ _list list; ++ u32 addr; ++ volatile u32 val; ++ u32 command; ++ u32 status; ++ u8 *pbuf; ++ _sema sema; ++ ++#ifdef PLATFORM_OS_CE ++#ifdef CONFIG_USB_HCI ++ // URB handler for rtw_write_mem ++ USB_TRANSFER usb_transfer_write_mem; ++#endif ++#endif ++ ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt); ++ u8 *cnxt; ++ ++#ifdef PLATFORM_OS_XP ++ PMDL pmdl; ++ PIRP pirp; ++ ++#ifdef CONFIG_SDIO_HCI ++ PSDBUS_REQUEST_PACKET sdrp; ++#endif ++ ++#endif ++ ++ ++}; ++ ++struct intf_hdl { ++ ++/* ++ u32 intf_option; ++ u32 bus_status; ++ u32 do_flush; ++ u8 *adapter; ++ u8 *intf_dev; ++ struct intf_priv *pintfpriv; ++ u8 cnt; ++ void (*intf_hdl_init)(u8 *priv); ++ void (*intf_hdl_unload)(u8 *priv); ++ void (*intf_hdl_open)(u8 *priv); ++ void (*intf_hdl_close)(u8 *priv); ++ struct _io_ops io_ops; ++ //u8 intf_status;//moved to struct intf_priv ++ u16 len; ++ u16 done_len; ++*/ ++ _adapter *padapter; ++ struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv); ++ ++ struct _io_ops io_ops; ++ ++}; ++ ++struct reg_protocol_rd { ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ //DW1 ++ u32 NumOfTrans:4; ++ u32 Reserved1:4; ++ u32 Reserved2:24; ++ //DW2 ++ u32 ByteCount:7; ++ u32 WriteEnable:1; //0:read, 1:write ++ u32 FixOrContinuous:1; //0:continuous, 1: Fix ++ u32 BurstMode:1; ++ u32 Byte1Access:1; ++ u32 Byte2Access:1; ++ u32 Byte4Access:1; ++ u32 Reserved3:3; ++ u32 Reserved4:16; ++ //DW3 ++ u32 BusAddress; ++ //DW4 ++ //u32 Value; ++#else ++ ++ ++//DW1 ++ u32 Reserved1 :4; ++ u32 NumOfTrans :4; ++ ++ u32 Reserved2 :24; ++ ++ //DW2 ++ u32 WriteEnable : 1; ++ u32 ByteCount :7; ++ ++ ++ u32 Reserved3 : 3; ++ u32 Byte4Access : 1; ++ ++ u32 Byte2Access : 1; ++ u32 Byte1Access : 1; ++ u32 BurstMode :1 ; ++ u32 FixOrContinuous : 1; ++ ++ u32 Reserved4 : 16; ++ ++ //DW3 ++ u32 BusAddress; ++ ++ //DW4 ++ //u32 Value; ++ ++#endif ++ ++}; ++ ++ ++struct reg_protocol_wt { ++ ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ //DW1 ++ u32 NumOfTrans:4; ++ u32 Reserved1:4; ++ u32 Reserved2:24; ++ //DW2 ++ u32 ByteCount:7; ++ u32 WriteEnable:1; //0:read, 1:write ++ u32 FixOrContinuous:1; //0:continuous, 1: Fix ++ u32 BurstMode:1; ++ u32 Byte1Access:1; ++ u32 Byte2Access:1; ++ u32 Byte4Access:1; ++ u32 Reserved3:3; ++ u32 Reserved4:16; ++ //DW3 ++ u32 BusAddress; ++ //DW4 ++ u32 Value; ++ ++#else ++ //DW1 ++ u32 Reserved1 :4; ++ u32 NumOfTrans :4; ++ ++ u32 Reserved2 :24; ++ ++ //DW2 ++ u32 WriteEnable : 1; ++ u32 ByteCount :7; ++ ++ u32 Reserved3 : 3; ++ u32 Byte4Access : 1; ++ ++ u32 Byte2Access : 1; ++ u32 Byte1Access : 1; ++ u32 BurstMode :1 ; ++ u32 FixOrContinuous : 1; ++ ++ u32 Reserved4 : 16; ++ ++ //DW3 ++ u32 BusAddress; ++ ++ //DW4 ++ u32 Value; ++ ++#endif ++ ++}; ++#ifdef CONFIG_PCI_HCI ++#define MAX_CONTINUAL_IO_ERR 4 ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#define MAX_CONTINUAL_IO_ERR 4 ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++#define SD_IO_TRY_CNT (8) ++#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT ++#endif ++ ++ ++int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj); ++void rtw_reset_continual_io_error(struct dvobj_priv *dvobj); ++ ++/* ++Below is the data structure used by _io_handler ++ ++*/ ++ ++struct io_queue { ++ _lock lock; ++ _list free_ioreqs; ++ _list pending; //The io_req list that will be served in the single protocol read/write. ++ _list processing; ++ u8 *free_ioreqs_buf; // 4-byte aligned ++ u8 *pallocated_free_ioreqs_buf; ++ struct intf_hdl intf; ++}; ++ ++struct io_priv{ ++ ++ _adapter *padapter; ++ ++ struct intf_hdl intf; ++ ++}; ++ ++extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); ++extern void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue); ++extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); ++ ++ ++extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); ++extern struct io_req *alloc_ioreq(struct io_queue *pio_q); ++ ++extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); ++extern void unregister_intf_hdl(struct intf_hdl *pintfhdl); ++ ++extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++extern u8 _rtw_read8(_adapter *adapter, u32 addr); ++extern u16 _rtw_read16(_adapter *adapter, u32 addr); ++extern u32 _rtw_read32(_adapter *adapter, u32 addr); ++extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_read_port_cancel(_adapter *adapter); ++ ++ ++extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val); ++extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val); ++extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); ++extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); ++ ++extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); ++extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val); ++extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val); ++ ++extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms); ++extern void _rtw_write_port_cancel(_adapter *adapter); ++ ++#ifdef DBG_IO ++bool match_read_sniff_ranges(u16 addr, u16 len); ++bool match_write_sniff_ranges(u16 addr, u16 len); ++ ++extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); ++extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); ++extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line); ++ ++extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); ++extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); ++extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); ++extern int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line); ++ ++#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__) ++#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__) ++#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__) ++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) ++ ++#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) ++ ++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) ++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) ++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) ++ ++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) ++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) ++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) ++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) ++#else //DBG_IO ++#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) ++#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) ++#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) ++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) ++ ++#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) ++#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) ++#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) ++#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) ++ ++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) ++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) ++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) ++ ++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) ++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) ++#endif //DBG_IO ++ ++extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem); ++ ++//ioreq ++extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval); ++extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval); ++extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval); ++extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val); ++extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val); ++extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val); ++ ++ ++extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++ ++extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++extern void async_write8(_adapter *adapter, u32 addr, u8 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern void async_write16(_adapter *adapter, u32 addr, u16 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern void async_write32(_adapter *adapter, u32 addr, u32 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++ ++extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++ ++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops)); ++ ++ ++extern uint alloc_io_queue(_adapter *adapter); ++extern void free_io_queue(_adapter *adapter); ++extern void async_bus_io(struct io_queue *pio_q); ++extern void bus_sync_io(struct io_queue *pio_q); ++extern u32 _ioreq2rwmem(struct io_queue *pio_q); ++extern void dev_power_down(_adapter * Adapter, u8 bpwrup); ++ ++/* ++#define RTL_R8(reg) rtw_read8(padapter, reg) ++#define RTL_R16(reg) rtw_read16(padapter, reg) ++#define RTL_R32(reg) rtw_read32(padapter, reg) ++#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8) ++#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16) ++#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32) ++*/ ++ ++/* ++#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8) ++#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16) ++#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32) ++ ++#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32) ++#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg) ++*/ ++ ++#define PlatformEFIOWrite1Byte(_a,_b,_c) \ ++ rtw_write8(_a,_b,_c) ++#define PlatformEFIOWrite2Byte(_a,_b,_c) \ ++ rtw_write16(_a,_b,_c) ++#define PlatformEFIOWrite4Byte(_a,_b,_c) \ ++ rtw_write32(_a,_b,_c) ++ ++#define PlatformEFIORead1Byte(_a,_b) \ ++ rtw_read8(_a,_b) ++#define PlatformEFIORead2Byte(_a,_b) \ ++ rtw_read16(_a,_b) ++#define PlatformEFIORead4Byte(_a,_b) \ ++ rtw_read32(_a,_b) ++ ++#endif //_RTL8711_IO_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl.h +new file mode 100644 +index 00000000..ad6ac5d3 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl.h +@@ -0,0 +1,269 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_IOCTL_H_ ++#define _RTW_IOCTL_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifndef OID_802_11_CAPABILITY ++ #define OID_802_11_CAPABILITY 0x0d010122 ++#endif ++ ++#ifndef OID_802_11_PMKID ++ #define OID_802_11_PMKID 0x0d010123 ++#endif ++ ++ ++// For DDK-defined OIDs ++#define OID_NDIS_SEG1 0x00010100 ++#define OID_NDIS_SEG2 0x00010200 ++#define OID_NDIS_SEG3 0x00020100 ++#define OID_NDIS_SEG4 0x01010100 ++#define OID_NDIS_SEG5 0x01020100 ++#define OID_NDIS_SEG6 0x01020200 ++#define OID_NDIS_SEG7 0xFD010100 ++#define OID_NDIS_SEG8 0x0D010100 ++#define OID_NDIS_SEG9 0x0D010200 ++#define OID_NDIS_SEG10 0x0D020200 ++ ++#define SZ_OID_NDIS_SEG1 23 ++#define SZ_OID_NDIS_SEG2 3 ++#define SZ_OID_NDIS_SEG3 6 ++#define SZ_OID_NDIS_SEG4 6 ++#define SZ_OID_NDIS_SEG5 4 ++#define SZ_OID_NDIS_SEG6 8 ++#define SZ_OID_NDIS_SEG7 7 ++#define SZ_OID_NDIS_SEG8 36 ++#define SZ_OID_NDIS_SEG9 24 ++#define SZ_OID_NDIS_SEG10 19 ++ ++// For Realtek-defined OIDs ++#define OID_MP_SEG1 0xFF871100 ++#define OID_MP_SEG2 0xFF818000 ++ ++#define OID_MP_SEG3 0xFF818700 ++#define OID_MP_SEG4 0xFF011100 ++ ++#define DEBUG_OID(dbg, str) \ ++ if((!dbg)) \ ++ { \ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \ ++ } ++ ++ ++enum oid_type ++{ ++ QUERY_OID, ++ SET_OID ++}; ++ ++struct oid_funs_node { ++ unsigned int oid_start; //the starting number for OID ++ unsigned int oid_end; //the ending number for OID ++ struct oid_obj_priv *node_array; ++ unsigned int array_sz; //the size of node_array ++ int query_counter; //count the number of query hits for this segment ++ int set_counter; //count the number of set hits for this segment ++}; ++ ++struct oid_par_priv ++{ ++ void *adapter_context; ++ NDIS_OID oid; ++ void *information_buf; ++ u32 information_buf_len; ++ u32 *bytes_rw; ++ u32 *bytes_needed; ++ enum oid_type type_of_oid; ++ u32 dbg; ++}; ++ ++struct oid_obj_priv { ++ unsigned char dbg; // 0: without OID debug message 1: with OID debug message ++ NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv); ++}; ++ ++#if (defined(CONFIG_MP_INCLUDED) && defined(_RTW_MP_IOCTL_C_)) || \ ++ (defined(PLATFORM_WINDOWS) && defined(_RTW_IOCTL_RTL_C_)) ++static NDIS_STATUS oid_null_function(struct oid_par_priv* poid_par_priv) ++{ ++ _func_enter_; ++ _func_exit_; ++ return NDIS_STATUS_SUCCESS; ++} ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode); ++ ++//OID Handler for Segment 1 ++NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 2 ++NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv* poid_par_priv); ++ ++//OID Handler for Segment 3 ++NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 4 ++NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 5 ++NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 6 ++NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 7 ++NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 8 ++NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++ ++ ++//OID Handler for Segment 9 ++NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 10 ++NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment ED ++NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv* poid_par_priv); ++ ++void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast); ++ ++#endif// end of PLATFORM_WINDOWS ++ ++#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT) ++extern struct iw_handler_def rtw_handlers_def; ++#endif ++ ++extern NDIS_STATUS drv_query_info( ++ IN _nic_hdl MiniportAdapterContext, ++ IN NDIS_OID Oid, ++ IN void * InformationBuffer, ++ IN u32 InformationBufferLength, ++ OUT u32* BytesWritten, ++ OUT u32* BytesNeeded ++ ); ++ ++extern NDIS_STATUS drv_set_info( ++ IN _nic_hdl MiniportAdapterContext, ++ IN NDIS_OID Oid, ++ IN void * InformationBuffer, ++ IN u32 InformationBufferLength, ++ OUT u32* BytesRead, ++ OUT u32* BytesNeeded ++ ); ++ ++#endif // #ifndef __INC_CEINFO_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_query.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_query.h +new file mode 100644 +index 00000000..5b6018af +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_query.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_IOCTL_QUERY_H_ ++#define _RTW_IOCTL_QUERY_H_ ++ ++#include ++#include ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++u8 query_802_11_capability(_adapter* padapter,u8* pucBuf,u32 * pulOutLen); ++u8 query_802_11_association_information (_adapter * padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo); ++ ++#endif ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_rtl.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_rtl.h +new file mode 100644 +index 00000000..9a43c280 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_rtl.h +@@ -0,0 +1,84 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_IOCTL_RTL_H_ ++#define _RTW_IOCTL_RTL_H_ ++ ++#include ++#include ++#include ++ ++//************** oid_rtl_seg_01_01 ************** ++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84 ++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); //8a ++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); //8b ++ ++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);//93 ++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv); ++ ++//************** oid_rtl_seg_01_03 section start ************** ++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv); ++ ++// oid_rtl_seg_01_11 ++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv); ++ ++//************** oid_rtl_seg_03_00 section start ************** ++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_set.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_set.h +new file mode 100644 +index 00000000..5f755bd2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_ioctl_set.h +@@ -0,0 +1,78 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_IOCTL_SET_H_ ++#define __RTW_IOCTL_SET_H_ ++ ++#include ++#include ++ ++ ++typedef u8 NDIS_802_11_PMKID_VALUE[16]; ++ ++typedef struct _BSSIDInfo { ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ NDIS_802_11_PMKID_VALUE PMKID; ++} BSSIDInfo, *PBSSIDInfo; ++ ++ ++#ifdef PLATFORM_OS_XP ++typedef struct _NDIS_802_11_PMKID { ++ u32 Length; ++ u32 BSSIDInfoCount; ++ BSSIDInfo BSSIDInfo[1]; ++} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID; ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); ++u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test); ++u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); ++ ++u8 rtw_pnp_set_power_sleep(_adapter* padapter); ++u8 rtw_pnp_set_power_wakeup(_adapter* padapter); ++ ++void rtw_pnp_resume_wk(void *context); ++void rtw_pnp_sleep_wk(void * context); ++ ++#endif ++ ++u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key); ++u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); ++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid); ++u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep); ++u8 rtw_set_802_11_disassociate(_adapter * padapter); ++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num); ++u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); ++u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex); ++u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid); ++u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid); ++u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key); ++ ++u8 rtw_validate_bssid(u8 *bssid); ++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); ++ ++u16 rtw_get_cur_max_rate(_adapter *adapter); ++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); ++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); ++int rtw_set_country(_adapter *adapter, const char *country_code); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_iol.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_iol.h +new file mode 100644 +index 00000000..0b0672a1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_iol.h +@@ -0,0 +1,139 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_IOL_H_ ++#define __RTW_IOL_H_ ++ ++#include ++#include ++#include ++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter); ++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len); ++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary); ++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); ++bool rtw_IOL_applied(ADAPTER *adapter); ++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us); ++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms); ++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame); ++ ++ ++#ifdef CONFIG_IOL_NEW_GENERATION ++#define IOREG_CMD_END_LEN 4 ++ ++struct ioreg_cfg{ ++ u8 length; ++ u8 cmd_id; ++ u16 address; ++ u32 data; ++ u32 mask; ++}; ++enum ioreg_cmd{ ++ IOREG_CMD_LLT = 0x01, ++ IOREG_CMD_REFUSE = 0x02, ++ IOREG_CMD_EFUSE_PATH = 0x03, ++ IOREG_CMD_WB_REG = 0x04, ++ IOREG_CMD_WW_REG = 0x05, ++ IOREG_CMD_WD_REG = 0x06, ++ IOREG_CMD_W_RF = 0x07, ++ IOREG_CMD_DELAY_US = 0x10, ++ IOREG_CMD_DELAY_MS = 0x11, ++ IOREG_CMD_END = 0xFF, ++}; ++void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size); ++ ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask); ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask); ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask); ++int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask); ++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value) ,(mask)) ++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value),(mask)) ++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value),(mask)) ++#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value,mask) _rtw_IOL_append_WRF_cmd((xmit_frame),(rf_path), (addr), (value),(mask)) ++ ++u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame); ++void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf); ++ ++#ifdef CONFIG_IOL_IOREG_CFG_DBG ++ struct cmd_cmp{ ++ u16 addr; ++ u32 value; ++ }; ++#endif ++ ++#else //CONFIG_IOL_NEW_GENERATION ++ ++typedef struct _io_offload_cmd { ++ u8 rsvd0; ++ u8 cmd; ++ u16 address; ++ u32 value; ++} IO_OFFLOAD_CMD, IOL_CMD; ++ ++#define IOL_CMD_LLT 0x00 ++//#define IOL_CMD_R_EFUSE 0x01 ++#define IOL_CMD_WB_REG 0x02 ++#define IOL_CMD_WW_REG 0x03 ++#define IOL_CMD_WD_REG 0x04 ++//#define IOL_CMD_W_RF 0x05 ++#define IOL_CMD_DELAY_US 0x80 ++#define IOL_CMD_DELAY_MS 0x81 ++//#define IOL_CMD_DELAY_S 0x82 ++#define IOL_CMD_END 0x83 ++ ++/***************************************************** ++CMD Address Value ++(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) ++****************************************************** ++IOL_CMD_LLT - B7: PGBNDY ++//IOL_CMD_R_EFUSE - - ++IOL_CMD_WB_REG 0x0~0xFFFF B7 ++IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 ++IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 ++//IOL_CMD_W_RF RF Reg B5~B7 ++IOL_CMD_DELAY_US - B6~B7 ++IOL_CMD_DELAY_MS - B6~B7 ++//IOL_CMD_DELAY_S - B6~B7 ++IOL_CMD_END - - ++******************************************************/ ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value); ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value); ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value); ++ ++ ++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms); ++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms); ++ ++#ifdef DBG_IO ++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line); ++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line); ++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line); ++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#else ++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) ++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) ++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) ++#endif // DBG_IO ++#endif // CONFIG_IOL_NEW_GENERATION ++ ++ ++ ++#endif //__RTW_IOL_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_led.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_led.h +new file mode 100644 +index 00000000..2bba754c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_led.h +@@ -0,0 +1,237 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_LED_H_ ++#define __RTW_LED_H_ ++ ++#include ++#include ++#include ++ ++#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) ++ ++#define LED_BLINK_NORMAL_INTERVAL 100 ++#define LED_BLINK_SLOWLY_INTERVAL 200 ++#define LED_BLINK_LONG_INTERVAL 400 ++ ++#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 ++#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 ++#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 ++#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 ++#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 ++ ++#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 ++#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 ++ ++#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 ++#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 ++ ++#define LED_BLINK_FAST_INTERVAL_BITLAND 30 ++ ++// 060403, rcnjko: Customized for AzWave. ++#define LED_CM2_BLINK_ON_INTERVAL 250 ++#define LED_CM2_BLINK_OFF_INTERVAL 4750 ++ ++#define LED_CM8_BLINK_INTERVAL 500 //for QMI ++#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI ++ ++// 080124, lanhsin: Customized for RunTop ++#define LED_RunTop_BLINK_INTERVAL 300 ++ ++// 060421, rcnjko: Customized for Sercomm Printer Server case. ++#define LED_CM3_BLINK_INTERVAL 1500 ++ ++typedef enum _LED_CTL_MODE{ ++ LED_CTL_POWER_ON = 1, ++ LED_CTL_LINK = 2, ++ LED_CTL_NO_LINK = 3, ++ LED_CTL_TX = 4, ++ LED_CTL_RX = 5, ++ LED_CTL_SITE_SURVEY = 6, ++ LED_CTL_POWER_OFF = 7, ++ LED_CTL_START_TO_LINK = 8, ++ LED_CTL_START_WPS = 9, ++ LED_CTL_STOP_WPS = 10, ++ LED_CTL_START_WPS_BOTTON = 11, //added for runtop ++ LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA ++ LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN ++ LED_CTL_CONNECTION_NO_TRANSFER = 14, ++}LED_CTL_MODE; ++ ++typedef enum _LED_STATE_871x{ ++ LED_UNKNOWN = 0, ++ RTW_LED_ON = 1, ++ RTW_LED_OFF = 2, ++ LED_BLINK_NORMAL = 3, ++ LED_BLINK_SLOWLY = 4, ++ LED_BLINK_POWER_ON = 5, ++ LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. ++ LED_BLINK_NO_LINK = 7, // LED is blinking during no link state. ++ LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case ++ LED_BLINK_TXRX = 9, ++ LED_BLINK_WPS = 10, // LED is blinkg during WPS communication ++ LED_BLINK_WPS_STOP = 11, //for ALPHA ++ LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN ++ LED_BLINK_RUNTOP = 13, // Customized for RunTop ++ LED_BLINK_CAMEO = 14, ++ LED_BLINK_XAVI = 15, ++ LED_BLINK_ALWAYS_ON = 16, ++}LED_STATE_871x; ++ ++typedef enum _LED_PIN_871x{ ++ LED_PIN_NULL = 0, ++ LED_PIN_LED0 = 1, ++ LED_PIN_LED1 = 2, ++ LED_PIN_LED2 = 3, ++ LED_PIN_GPIO0 = 4, ++}LED_PIN_871x; ++ ++typedef struct _LED_871x{ ++ _adapter *padapter; ++ ++ LED_PIN_871x LedPin; // Identify how to implement this SW led. ++ LED_STATE_871x CurrLedState; // Current LED state. ++ LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. ++ ++ u8 bLedOn; // true if LED is ON, false if LED is OFF. ++ ++ u8 bLedBlinkInProgress; // true if it is blinking, false o.w.. ++ ++ u8 bLedWPSBlinkInProgress; ++ ++ u32 BlinkTimes; // Number of times to toggle led state for blinking. ++ ++ _timer BlinkTimer; // Timer object for led blinking. ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ u8 bSWLedCtrl; ++ ++ // ALPHA, added by chiyoko, 20090106 ++ u8 bLedNoLinkBlinkInProgress; ++ u8 bLedLinkBlinkInProgress; ++ u8 bLedStartToLinkBlinkInProgress; ++ u8 bLedScanBlinkInProgress; ++ ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)|| defined PLATFORM_FREEBSD ++ _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. ++ #endif ++#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ ++#if defined(CONFIG_PCI_HCI) ++ u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode ++#endif ++ ++} LED_871x, *PLED_871x; ++ ++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ ++#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \ ++ || ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \ ++ || ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress) ++ ++#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \ ++ ||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress) ++ ++//================================================================================ ++// LED customization. ++//================================================================================ ++ ++typedef enum _LED_STRATEGY_871x{ ++ SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option. ++ SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA. ++ SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. ++ SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. ++ SW_LED_MODE4 = 4, //for Edimax / Belkin ++ SW_LED_MODE5 = 5, //for Sercomm / Belkin ++ SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7 ++ HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) ++ LED_ST_NONE = 99, ++}LED_STRATEGY_871x, *PLED_STRATEGY_871x; ++ ++void ++LedControl871x( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++ ); ++#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ ++#if defined(CONFIG_PCI_HCI) ++//================================================================================ ++// LED customization. ++//================================================================================ ++ ++typedef enum _LED_STRATEGY_871x{ ++ SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option. ++ SW_LED_MODE1 = 1, // SW control for PCI Express ++ SW_LED_MODE2 = 2, // SW control for Cameo. ++ SW_LED_MODE3 = 3, // SW contorl for RunTop. ++ SW_LED_MODE4 = 4, // SW control for Netcore ++ SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK ++ SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET ++ SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec ++ SW_LED_MODE8 = 8, //added by chiyokolin, for QMI ++ SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1 ++ SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS ++ HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) ++ LED_ST_NONE = 99, ++}LED_STRATEGY_871x, *PLED_STRATEGY_871x; ++#endif //defined(CONFIG_PCI_HCI) ++ ++struct led_priv{ ++ /* add for led controll */ ++ LED_871x SwLed0; ++ LED_871x SwLed1; ++ LED_STRATEGY_871x LedStrategy; ++ u8 bRegUseLed; ++ void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); ++ /* add for led controll */ ++}; ++ ++#ifdef CONFIG_SW_LED ++#define rtw_led_control(adapter, LedAction) \ ++ do { \ ++ if((adapter)->ledpriv.LedControlHandler) \ ++ (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ ++ } while(0) ++#else //CONFIG_SW_LED ++#define rtw_led_control(adapter, LedAction) ++#endif //CONFIG_SW_LED ++ ++void BlinkTimerCallback(void *data); ++void BlinkWorkItemCallback(struct work_struct *work); ++ ++void ResetLedStatus(PLED_871x pLed); ++ ++void ++InitLed871x( ++ _adapter *padapter, ++ PLED_871x pLed, ++ LED_PIN_871x LedPin ++ ); ++ ++void ++DeInitLed871x( ++ PLED_871x pLed ++ ); ++ ++//hal... ++extern void BlinkHandler(PLED_871x pLed); ++ ++#endif //__RTW_LED_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme.h +new file mode 100644 +index 00000000..98738c8d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme.h +@@ -0,0 +1,870 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_MLME_H_ ++#define __RTW_MLME_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_INTEL_WIDI ++#include ++#endif ++ ++#define MAX_BSS_CNT 128 ++//#define MAX_JOIN_TIMEOUT 2000 ++//#define MAX_JOIN_TIMEOUT 2500 ++#define MAX_JOIN_TIMEOUT 6500 ++ ++// Commented by Albert 20101105 ++// Increase the scanning timeout because of increasing the SURVEY_TO value. ++ ++#define SCANNING_TIMEOUT 8000 ++ ++#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec ++ ++#ifdef PALTFORM_OS_WINCE ++#define SCANQUEUE_LIFETIME 12000000 // unit:us ++#else ++#define SCANQUEUE_LIFETIME 20 // unit:sec ++#endif ++ ++#define WIFI_NULL_STATE 0x00000000 ++ ++#define WIFI_ASOC_STATE 0x00000001 // Under Linked state... ++#define WIFI_REASOC_STATE 0x00000002 ++#define WIFI_SLEEP_STATE 0x00000004 ++#define WIFI_STATION_STATE 0x00000008 ++ ++#define WIFI_AP_STATE 0x00000010 ++#define WIFI_ADHOC_STATE 0x00000020 ++#define WIFI_ADHOC_MASTER_STATE 0x00000040 ++#define WIFI_UNDER_LINKING 0x00000080 ++ ++#define WIFI_UNDER_WPS 0x00000100 ++//#define WIFI_UNDER_CMD 0x00000200 ++//#define WIFI_UNDER_P2P 0x00000400 ++#define WIFI_STA_ALIVE_CHK_STATE 0x00000400 ++#define WIFI_SITE_MONITOR 0x00000800 //to indicate the station is under site surveying ++ ++#ifdef WDS ++#define WIFI_WDS 0x00001000 ++#define WIFI_WDS_RX_BEACON 0x00002000 // already rx WDS AP beacon ++#endif ++#ifdef AUTO_CONFIG ++#define WIFI_AUTOCONF 0x00004000 ++#define WIFI_AUTOCONF_IND 0x00008000 ++#endif ++ ++/* ++// ========== P2P Section Start =============== ++#define WIFI_P2P_LISTEN_STATE 0x00010000 ++#define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000 ++// ========== P2P Section End =============== ++*/ ++ ++//#ifdef UNDER_MPTEST ++#define WIFI_MP_STATE 0x00010000 ++#define WIFI_MP_CTX_BACKGROUND 0x00020000 // in continous tx background ++#define WIFI_MP_CTX_ST 0x00040000 // in continous tx with single-tone ++#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 // pending in continous tx background due to out of skb ++#define WIFI_MP_CTX_CCK_HW 0x00100000 // in continous tx ++#define WIFI_MP_CTX_CCK_CS 0x00200000 // in continous tx with carrier suppression ++#define WIFI_MP_LPBK_STATE 0x00400000 ++//#endif ++ ++//#define _FW_UNDER_CMD WIFI_UNDER_CMD ++#define _FW_UNDER_LINKING WIFI_UNDER_LINKING ++#define _FW_LINKED WIFI_ASOC_STATE ++#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR ++ ++ ++enum dot11AuthAlgrthmNum { ++ dot11AuthAlgrthm_Open = 0, ++ dot11AuthAlgrthm_Shared, ++ dot11AuthAlgrthm_8021X, ++ dot11AuthAlgrthm_Auto, ++ dot11AuthAlgrthm_WAPI, ++ dot11AuthAlgrthm_MaxNum ++}; ++ ++// Scan type including active and passive scan. ++typedef enum _RT_SCAN_TYPE ++{ ++ SCAN_PASSIVE, ++ SCAN_ACTIVE, ++ SCAN_MIX, ++}RT_SCAN_TYPE, *PRT_SCAN_TYPE; ++ ++enum _BAND ++{ ++ GHZ24_50 = 0, ++ GHZ_50, ++ GHZ_24, ++}; ++ ++enum DriverInterface { ++ DRIVER_WEXT = 1, ++ DRIVER_CFG80211 = 2 ++}; ++ ++enum SCAN_RESULT_TYPE ++{ ++ SCAN_RESULT_P2P_ONLY = 0, // Will return all the P2P devices. ++ SCAN_RESULT_ALL = 1, // Will return all the scanned device, include AP. ++ SCAN_RESULT_WFD_TYPE = 2 // Will just return the correct WFD device. ++ // If this device is Miracast sink device, it will just return all the Miracast source devices. ++}; ++ ++/* ++ ++there are several "locks" in mlme_priv, ++since mlme_priv is a shared resource between many threads, ++like ISR/Call-Back functions, the OID handlers, and even timer functions. ++ ++ ++Each _queue has its own locks, already. ++Other items are protected by mlme_priv.lock. ++ ++To avoid possible dead lock, any thread trying to modifiying mlme_priv ++SHALL not lock up more than one locks at a time! ++ ++*/ ++ ++ ++#define traffic_threshold 10 ++#define traffic_scan_period 500 ++ ++struct sitesurvey_ctrl { ++ u64 last_tx_pkts; ++ uint last_rx_pkts; ++ sint traffic_busy; ++ _timer sitesurvey_ctrl_timer; ++}; ++ ++typedef struct _RT_LINK_DETECT_T{ ++ u32 NumTxOkInPeriod; ++ u32 NumRxOkInPeriod; ++ u32 NumRxUnicastOkInPeriod; ++ BOOLEAN bBusyTraffic; ++ BOOLEAN bTxBusyTraffic; ++ BOOLEAN bRxBusyTraffic; ++ BOOLEAN bHigherBusyTraffic; // For interrupt migration purpose. ++ BOOLEAN bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic. ++ BOOLEAN bHigherBusyTxTraffic; // We may disable Tx interrupt according as Tx traffic. ++}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; ++ ++struct profile_info { ++ u8 ssidlen; ++ u8 ssid[ WLAN_SSID_MAXLEN ]; ++ u8 peermac[ ETH_ALEN ]; ++}; ++ ++struct tx_invite_req_info{ ++ u8 token; ++ u8 benable; ++ u8 go_ssid[ WLAN_SSID_MAXLEN ]; ++ u8 ssidlen; ++ u8 go_bssid[ ETH_ALEN ]; ++ u8 peer_macaddr[ ETH_ALEN ]; ++ u8 operating_ch; // This information will be set by using the p2p_set op_ch=x ++ u8 peer_ch; // The listen channel for peer P2P device ++ ++}; ++ ++struct tx_invite_resp_info{ ++ u8 token; // Used to record the dialog token of p2p invitation request frame. ++}; ++ ++#ifdef CONFIG_WFD ++ ++struct wifi_display_info{ ++ u16 wfd_enable; // Eanble/Disable the WFD function. ++ u16 rtsp_ctrlport; // TCP port number at which the this WFD device listens for RTSP messages ++ u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages ++ // This filed should be filled when receiving the gropu negotiation request ++ ++ u8 peer_session_avail; // WFD session is available or not for the peer wfd device. ++ // This variable will be set when sending the provisioning discovery request to peer WFD device. ++ // And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. ++ u8 ip_address[4]; ++ u8 peer_ip_address[4]; ++ u8 wfd_pc; // WFD preferred connection ++ // 0 -> Prefer to use the P2P for WFD connection on peer side. ++ // 1 -> Prefer to use the TDLS for WFD connection on peer side. ++ ++ u8 wfd_device_type; // WFD Device Type ++ // 0 -> WFD Source Device ++ // 1 -> WFD Primary Sink Device ++ enum SCAN_RESULT_TYPE scan_result_type; // Used when P2P is enable. This parameter will impact the scan result. ++}; ++#endif //CONFIG_WFD ++ ++struct tx_provdisc_req_info{ ++ u16 wps_config_method_request; // Used when sending the provisioning request frame ++ u16 peer_channel_num[2]; // The channel number which the receiver stands. ++ NDIS_802_11_SSID ssid; ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address ++ u8 benable; // This provision discovery request frame is trigger to send or not ++}; ++ ++struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame. ++ // The UI must know this information to know which config method the remote p2p device is requiring. ++}; ++ ++struct tx_nego_req_info{ ++ u16 peer_channel_num[2]; // The channel number which the receiver stands. ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 benable; // This negoitation request frame is trigger to send or not ++}; ++ ++struct group_id_info{ ++ u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group ++ u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group ++}; ++ ++struct scan_limit_info{ ++ u8 scan_op_ch_only; // When this flag is set, the driver should just scan the operation channel ++#ifndef P2P_OP_CHECK_SOCIAL_CH ++ u8 operation_ch[2]; // Store the operation channel of invitation request frame ++#else ++ u8 operation_ch[5]; // Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 ++#endif //P2P_OP_CHECK_SOCIAL_CH ++}; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++struct cfg80211_wifidirect_info{ ++ _timer remain_on_ch_timer; ++ u8 restore_channel; ++ struct ieee80211_channel remain_on_ch_channel; ++ enum nl80211_channel_type remain_on_ch_type; ++ u64 remain_on_ch_cookie; ++ bool is_ro_ch; ++}; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++struct wifidirect_info{ ++ _adapter* padapter; ++ _timer find_phase_timer; ++ _timer restore_p2p_state_timer; ++ ++ // Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. ++ _timer pre_tx_scan_timer; ++ _timer reset_ch_sitesurvey; ++ _timer reset_ch_sitesurvey2; // Just for resetting the scan limit function by using p2p nego ++#ifdef CONFIG_CONCURRENT_MODE ++ // Used to switch the channel between legacy AP and listen state. ++ _timer ap_p2p_switch_timer; ++#endif ++ struct tx_provdisc_req_info tx_prov_disc_info; ++ struct rx_provdisc_req_info rx_prov_disc_info; ++ struct tx_invite_req_info invitereq_info; ++ struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group ++ struct tx_invite_resp_info inviteresp_info; ++ struct tx_nego_req_info nego_req_info; ++ struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake. ++ struct scan_limit_info rx_invitereq_info; // Used for get the limit scan channel from the Invitation procedure ++ struct scan_limit_info p2p_info; // Used for get the limit scan channel from the P2P negotiation handshake ++#ifdef CONFIG_WFD ++ struct wifi_display_info *wfd_info; ++#endif ++ enum P2P_ROLE role; ++ enum P2P_STATE pre_p2p_state; ++ enum P2P_STATE p2p_state; ++ u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device. ++ u8 interface_addr[ETH_ALEN]; ++ u8 social_chan[4]; ++ u8 listen_channel; ++ u8 operating_channel; ++ u8 listen_dwell; // This value should be between 1 and 3 ++ u8 support_rate[8]; ++ u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; ++ u8 intent; // should only include the intent value. ++ u8 p2p_peer_interface_addr[ ETH_ALEN ]; ++ u8 p2p_peer_device_addr[ ETH_ALEN ]; ++ u8 peer_intent; // Included the intent value and tie breaker value. ++ u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen ++ u8 device_name_len; ++ u8 profileindex; // Used to point to the index of profileinfo array ++ u8 peer_operating_ch; ++ u8 find_phase_state_exchange_cnt; ++ u16 device_password_id_for_nego; // The device password ID for group negotation ++ u8 negotiation_dialog_token; ++ u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation ++ u8 nego_ssidlen; ++ u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; ++ u8 p2p_group_ssid_len; ++ u8 persistent_supported; // Flag to know the persistent function should be supported or not. ++ // In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. ++ // 0: disable ++ // 1: enable ++ u8 session_available; // Flag to set the WFD session available to enable or disable "by Sigma" ++ // In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. ++ // 0: disable ++ // 1: enable ++ ++ u8 wfd_tdls_enable; // Flag to enable or disable the TDLS by WFD Sigma ++ // 0: disable ++ // 1: enable ++ u8 wfd_tdls_weaksec; // Flag to enable or disable the weak security function for TDLS by WFD Sigma ++ // 0: disable ++ // In this case, the driver can't issue the tdsl setup request frame. ++ // 1: enable ++ // In this case, the driver can issue the tdls setup request frame ++ // even the current security is weak security. ++ ++ enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user. ++ u16 supported_wps_cm; // This field describes the WPS config method which this driver supported. ++ // The value should be the combination of config method defined in page104 of WPS v2.0 spec. ++ u8 external_uuid; // UUID flag ++ u8 uuid[16]; // UUID ++ uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. ++ u8 channel_list_attr[100]; // This field will contain the body of P2P Channel List attribute of group negotitation response frame. ++ // We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. ++ u8 driver_interface; // Indicate DRIVER_WEXT or DRIVER_CFG80211 ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ u16 ext_listen_interval; // The interval to be available with legacy AP (ms) ++ u16 ext_listen_period; // The time period to be available for P2P listen state (ms) ++#endif ++#ifdef CONFIG_P2P_PS ++ enum P2P_PS_MODE p2p_ps_mode; // indicate p2p ps mode ++ enum P2P_PS_STATE p2p_ps_state; // indicate p2p ps state ++ u8 noa_index; // Identifies and instance of Notice of Absence timing. ++ u8 ctwindow; // Client traffic window. A period of time in TU after TBTT. ++ u8 opp_ps; // opportunistic power save. ++ u8 noa_num; // number of NoA descriptor in P2P IE. ++ u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client. ++ u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client. ++ u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client. ++ u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer. ++#endif // CONFIG_P2P_PS ++}; ++ ++struct tdls_ss_record{ //signal strength record ++ u8 macaddr[ETH_ALEN]; ++ u8 RxPWDBAll; ++ u8 is_tdls_sta; // _TRUE: direct link sta, _FALSE: else ++}; ++ ++struct tdls_info{ ++ u8 ap_prohibited; ++ uint setup_state; ++ u8 sta_cnt; ++ u8 sta_maximum; // 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; ++ struct tdls_ss_record ss_record; ++ u8 macid_index; //macid entry that is ready to write ++ u8 clear_cam; //cam entry that is trying to clear, using it in direct link teardown ++ u8 ch_sensing; ++ u8 cur_channel; ++ u8 candidate_ch; ++ u8 collect_pkt_num[MAX_CHANNEL_NUM]; ++ _lock cmd_lock; ++ _lock hdl_lock; ++ u8 watchdog_count; ++ u8 dev_discovered; //WFD_TDLS: for sigma test ++ u8 enable; ++#ifdef CONFIG_WFD ++ struct wifi_display_info *wfd_info; ++#endif ++}; ++ ++struct mlme_priv { ++ ++ _lock lock; ++ sint fw_state; //shall we protect this variable? maybe not necessarily... ++ u8 bScanInProcess; ++ u8 to_join; //flag ++ #ifdef CONFIG_LAYER2_ROAMING ++ u8 to_roaming; // roaming trying times ++ #endif ++ ++ u8 *nic_hdl; ++ ++ u8 not_indic_disco; ++ _list *pscanned; ++ _queue free_bss_pool; ++ _queue scanned_queue; ++ u8 *free_bss_buf; ++ u32 num_of_scanned; ++ ++ NDIS_802_11_SSID assoc_ssid; ++ u8 assoc_bssid[6]; ++ ++ struct wlan_network cur_network; ++ struct wlan_network *cur_network_scanned; ++#ifdef CONFIG_ARP_KEEP_ALIVE ++ // for arp offload keep alive ++ u8 gw_mac_addr[6]; ++ u8 gw_ip[4]; ++#endif ++ ++ //uint wireless_mode; no used, remove it ++ ++ u32 scan_interval; ++ ++ _timer assoc_timer; ++ ++ uint assoc_by_bssid; ++ uint assoc_by_rssi; ++ ++ _timer scan_to_timer; // driver itself handles scan_timeout status. ++ u32 scan_start_time; // used to evaluate the time spent in scanning ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _timer set_scan_deny_timer; ++ ATOMIC_T set_scan_deny; //0: allowed, 1: deny ++ #endif ++ ++ #ifdef CONFIG_DETECT_C2H_BY_POLLING ++ _timer event_polling_timer; ++ #endif ++ ++ struct qos_priv qospriv; ++ ++#ifdef CONFIG_80211N_HT ++ ++ /* Number of non-HT AP/stations */ ++ int num_sta_no_ht; ++ ++ /* Number of HT AP/stations 20 MHz */ ++ //int num_sta_ht_20mhz; ++ ++ ++ int num_FortyMHzIntolerant; ++ ++ struct ht_priv htpriv; ++ ++#endif ++ ++ RT_LINK_DETECT_T LinkDetectInfo; ++ _timer dynamic_chk_timer; //dynamic/periodic check timer ++ ++ u8 acm_mask; // for wmm acm mask ++ u8 ChannelPlan; ++ RT_SCAN_TYPE scan_mode; // active: 1, passive: 0 ++ ++ //u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req ++ //int probereq_wpsie_len; ++ u8 *wps_probe_req_ie; ++ u32 wps_probe_req_ie_len; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ /* Number of associated Non-ERP stations (i.e., stations using 802.11b ++ * in 802.11g BSS) */ ++ int num_sta_non_erp; ++ ++ /* Number of associated stations that do not support Short Slot Time */ ++ int num_sta_no_short_slot_time; ++ ++ /* Number of associated stations that do not support Short Preamble */ ++ int num_sta_no_short_preamble; ++ ++ int olbc; /* Overlapping Legacy BSS Condition */ ++ ++ /* Number of HT associated stations that do not support greenfield */ ++ int num_sta_ht_no_gf; ++ ++ /* Number of associated non-HT stations */ ++ //int num_sta_no_ht; ++ ++ /* Number of HT associated stations 20 MHz */ ++ int num_sta_ht_20mhz; ++ ++ /* Overlapping BSS information */ ++ int olbc_ht; ++ ++#ifdef CONFIG_80211N_HT ++ u16 ht_op_mode; ++#endif /* CONFIG_80211N_HT */ ++ ++ u8 *assoc_req; ++ u32 assoc_req_len; ++ u8 *assoc_rsp; ++ u32 assoc_rsp_len; ++ ++ u8 *wps_beacon_ie; ++ //u8 *wps_probe_req_ie; ++ u8 *wps_probe_resp_ie; ++ u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie / wfd ie ++ ++ u32 wps_beacon_ie_len; ++ //u32 wps_probe_req_ie_len; ++ u32 wps_probe_resp_ie_len; ++ u32 wps_assoc_resp_ie_len; // for CONFIG_IOCTL_CFG80211, this IE len could include p2p ie / wfd ie ++ ++ u8 *p2p_beacon_ie; ++ u8 *p2p_probe_req_ie; ++ u8 *p2p_probe_resp_ie; ++ u8 *p2p_go_probe_resp_ie; //for GO ++ u8 *p2p_assoc_req_ie; ++ ++ u32 p2p_beacon_ie_len; ++ u32 p2p_probe_req_ie_len; ++ u32 p2p_probe_resp_ie_len; ++ u32 p2p_go_probe_resp_ie_len; //for GO ++ u32 p2p_assoc_req_ie_len; ++/* ++#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) ++ //u8 *wps_p2p_beacon_ie; ++ u8 *p2p_beacon_ie; ++ u8 *wps_p2p_probe_resp_ie; ++ u8 *wps_p2p_assoc_resp_ie; ++ //u32 wps_p2p_beacon_ie_len; ++ u32 p2p_beacon_ie_len; ++ u32 wps_p2p_probe_resp_ie_len; ++ u32 wps_p2p_assoc_resp_ie_len; ++#endif ++*/ ++ ++ _lock bcn_update_lock; ++ u8 update_bcn; ++ ++ ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ ++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) ++ ++ u8 *wfd_beacon_ie; ++ u8 *wfd_probe_req_ie; ++ u8 *wfd_probe_resp_ie; ++ u8 *wfd_go_probe_resp_ie; //for GO ++ u8 *wfd_assoc_req_ie; ++ ++ u32 wfd_beacon_ie_len; ++ u32 wfd_probe_req_ie_len; ++ u32 wfd_probe_resp_ie_len; ++ u32 wfd_go_probe_resp_ie_len; //for GO ++ u32 wfd_assoc_req_ie_len; ++ ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ // DMP kobject_hotplug function signal need in passive level ++ _workitem Linkup_workitem; ++ _workitem Linkdown_workitem; ++#endif ++ ++#ifdef CONFIG_INTEL_WIDI ++ int widi_state; ++ int listen_state; ++ _timer listen_timer; ++ ATOMIC_T rx_probe_rsp; // 1:receive probe respone from RDS source. ++ u8 *l2sdTaBuffer; ++ u8 channel_idx; ++ u8 group_cnt; //In WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed ++ u8 sa_ext[L2SDTA_SERVICE_VE_LEN]; ++ ++ u8 widi_enable; ++ /** ++ * For WiDi 4; upper layer would set ++ * p2p_primary_device_type_category_id ++ * p2p_primary_device_type_sub_category_id ++ * p2p_secondary_device_type_category_id ++ * p2p_secondary_device_type_sub_category_id ++ */ ++ u16 p2p_pdt_cid; ++ u16 p2p_pdt_scid; ++ u8 num_p2p_sdt; ++ u16 p2p_sdt_cid[MAX_NUM_P2P_SDT]; ++ u16 p2p_sdt_scid[MAX_NUM_P2P_SDT]; ++ u8 p2p_reject_disable; //When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close ++ //such that it will cause p2p disabled. Use this flag to reject. ++#endif // CONFIG_INTEL_WIDI ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ u8 scanning_via_buddy_intf; ++#endif ++ ++#ifdef CONFIG_FTP_PROTECT ++ u8 ftp_lock_flag; ++#endif //CONFIG_FTP_PROTECT ++}; ++ ++#ifdef CONFIG_AP_MODE ++ ++struct hostapd_priv ++{ ++ _adapter *padapter; ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ struct net_device *pmgnt_netdev; ++ struct usb_anchor anchored; ++#endif ++ ++}; ++ ++extern int hostapd_mode_init(_adapter *padapter); ++extern void hostapd_mode_unload(_adapter *padapter); ++#endif ++ ++ ++extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); ++extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); ++ ++#ifdef PLATFORM_WINDOWS ++extern thread_return event_thread(void *context); ++ ++extern void rtw_join_timeout_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++ ++extern void _rtw_scan_timeout_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++ ++#endif ++ ++#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD) ++extern int event_thread(void *context); ++extern void rtw_join_timeout_handler(void* FunctionContext); ++extern void _rtw_scan_timeout_handler(void* FunctionContext); ++#endif ++ ++extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall); ++extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv); ++ ++extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv); ++ ++ ++extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); ++extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx, bool enqueue); ++extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv); ++ ++__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) ++{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid ++ // if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address ++ return pmlmepriv->cur_network.network.MacAddress; ++} ++ ++__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ if (pmlmepriv->fw_state & state) ++ return _TRUE; ++ ++ return _FALSE; ++} ++ ++__inline static sint get_fwstate(struct mlme_priv *pmlmepriv) ++{ ++ return pmlmepriv->fw_state; ++} ++ ++/* ++ * No Limit on the calling context, ++ * therefore set it to be the critical section... ++ * ++ * ### NOTE:#### (!!!!) ++ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock ++ */ ++__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ pmlmepriv->fw_state |= state; ++ //FOR HW integration ++ if(_FW_UNDER_SURVEY==state){ ++ pmlmepriv->bScanInProcess = _TRUE; ++ } ++} ++ ++__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) ++{ ++ pmlmepriv->fw_state &= ~state; ++ //FOR HW integration ++ if(_FW_UNDER_SURVEY==state){ ++ pmlmepriv->bScanInProcess = _FALSE; ++ } ++} ++ ++/* ++ * No Limit on the calling context, ++ * therefore set it to be the critical section... ++ */ ++__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ if (check_fwstate(pmlmepriv, state) == _TRUE) ++ pmlmepriv->fw_state ^= state; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void clr_fwstate_ex(struct mlme_priv *pmlmepriv, sint state) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _clr_fwstate_(pmlmepriv, state); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void up_scanned_network(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned++; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++#ifdef CONFIG_CONCURRENT_MODE ++sint rtw_buddy_adapter_up(_adapter *padapter); ++sint check_buddy_fwstate(_adapter *padapter, sint state); ++u8 rtw_get_buddy_bBusyTraffic(_adapter *padapter); ++#endif //CONFIG_CONCURRENT_MODE ++ ++__inline static void down_scanned_network(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned--; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned = val; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); ++extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); ++extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc); ++extern void rtw_generate_random_ibss(u8 *pibss); ++extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr); ++extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue); ++ ++extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue); ++extern void rtw_indicate_disconnect(_adapter* adapter); ++extern void rtw_indicate_connect(_adapter* adapter); ++void rtw_indicate_scan_done( _adapter *padapter, bool aborted); ++void rtw_scan_abort(_adapter *adapter); ++ ++extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len); ++extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); ++extern void rtw_init_registrypriv_dev_network(_adapter *adapter); ++ ++extern void rtw_update_registrypriv_dev_network(_adapter *adapter); ++ ++extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); ++ ++extern void _rtw_join_timeout_handler(_adapter *adapter); ++extern void rtw_scan_timeout_handler(_adapter *adapter); ++ ++extern void rtw_dynamic_check_timer_handlder(_adapter *adapter); ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++bool rtw_is_scan_deny(_adapter *adapter); ++void rtw_clear_scan_deny(_adapter *adapter); ++void rtw_set_scan_deny_timer_hdl(_adapter *adapter); ++void rtw_set_scan_deny(_adapter *adapter, u32 ms); ++#else ++#define rtw_is_scan_deny(adapter) _FALSE ++#define rtw_clear_scan_deny(adapter) do {} while (0) ++#define rtw_set_scan_deny_timer_hdl(adapter) do {} while (0) ++#define rtw_set_scan_deny(adapter, ms) do {} while (0) ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++extern void rtw_event_polling_timer_hdl(_adapter *adapter); ++#endif ++ ++extern int _rtw_init_mlme_priv(_adapter *padapter); ++ ++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); ++ ++extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); ++ ++extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); ++ ++extern struct wlan_network* _rtw_dequeue_network(_queue *queue); ++ ++extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv); ++ ++ ++extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); ++extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); ++ ++ ++extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr); ++ ++extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall); ++ ++extern sint rtw_if_up(_adapter *padapter); ++ ++sint rtw_linked_check(_adapter *padapter); ++ ++u8 *rtw_get_capability_from_ie(u8 *ie); ++u8 *rtw_get_timestampe_from_ie(u8 *ie); ++u8 *rtw_get_beacon_interval_from_ie(u8 *ie); ++ ++ ++void rtw_joinbss_reset(_adapter *padapter); ++ ++#ifdef CONFIG_80211N_HT ++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); ++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len); ++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); ++#endif ++ ++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); ++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature); ++ ++#ifdef CONFIG_LAYER2_ROAMING ++void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); ++void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); ++void rtw_set_roaming(_adapter *adapter, u8 to_roaming); ++u8 rtw_to_roaming(_adapter *adapter); ++#else ++#define _rtw_roaming(adapter, tgt_network) do {} while(0) ++#define rtw_roaming(adapter, tgt_network) do {} while(0) ++#define rtw_set_roaming(adapter, to_roaming) do {} while(0) ++#define rtw_to_roaming(adapter) 0 ++#endif ++ ++void rtw_sta_media_status_rpt(_adapter *adapter,struct sta_info *psta, u32 mstatus); ++ ++#ifdef CONFIG_INTEL_PROXIM ++void rtw_proxim_enable(_adapter *padapter); ++void rtw_proxim_disable(_adapter *padapter); ++void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate); ++#endif //CONFIG_INTEL_PROXIM ++#endif //__RTL871X_MLME_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme_ext.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme_ext.h +new file mode 100644 +index 00000000..a4757732 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mlme_ext.h +@@ -0,0 +1,1021 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_MLME_EXT_H_ ++#define __RTW_MLME_EXT_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++// Commented by Albert 20101105 ++// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) ++// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. ++// So, this driver tried to extend the dwell time for each scanning channel. ++// This will increase the chance to receive the probe response from SoftAP. ++ ++#define SURVEY_TO (100) ++#define REAUTH_TO (300) //(50) ++#define REASSOC_TO (300) //(50) ++//#define DISCONNECT_TO (3000) ++#define ADDBA_TO (2000) ++ ++#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec ++ ++#define REAUTH_LIMIT (4) ++#define REASSOC_LIMIT (4) ++#define READDBA_LIMIT (2) ++ ++#ifdef CONFIG_GSPI_HCI ++ #define ROAMING_LIMIT 5 ++#else ++ #define ROAMING_LIMIT 8 ++#endif ++//#define IOCMD_REG0 0x10250370 ++//#define IOCMD_REG1 0x10250374 ++//#define IOCMD_REG2 0x10250378 ++ ++//#define FW_DYNAMIC_FUN_SWITCH 0x10250364 ++ ++//#define WRITE_BB_CMD 0xF0000001 ++//#define SET_CHANNEL_CMD 0xF3000000 ++//#define UPDATE_RA_CMD 0xFD0000A2 ++ ++#define DYNAMIC_FUNC_DISABLE (0x0) ++ ++// ====== ODM_ABILITY_E ======== ++// BB ODM section BIT 0-15 ++#define DYNAMIC_BB_DIG BIT(0) ++#define DYNAMIC_BB_RA_MASK BIT(1) ++#define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2) ++#define DYNAMIC_BB_BB_FA_CNT BIT(3) ++ ++#define DYNAMIC_BB_RSSI_MONITOR BIT(4) ++#define DYNAMIC_BB_CCK_PD BIT(5) ++#define DYNAMIC_BB_ANT_DIV BIT(6) ++#define DYNAMIC_BB_PWR_SAVE BIT(7) ++#define DYNAMIC_BB_PWR_TRAIN BIT(8) ++#define DYNAMIC_BB_RATE_ADAPTIVE BIT(9) ++#define DYNAMIC_BB_PATH_DIV BIT(10) ++#define DYNAMIC_BB_PSD BIT(11) ++ ++// MAC DM section BIT 16-23 ++#define DYNAMIC_MAC_EDCA_TURBO BIT(16) ++#define DYNAMIC_MAC_EARLY_MODE BIT(17) ++ ++// RF ODM section BIT 24-31 ++#define DYNAMIC_RF_TX_PWR_TRACK BIT(24) ++#define DYNAMIC_RF_RX_GAIN_TRACK BIT(25) ++#define DYNAMIC_RF_CALIBRATION BIT(26) ++ ++#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF ++ ++#define _HW_STATE_NOLINK_ 0x00 ++#define _HW_STATE_ADHOC_ 0x01 ++#define _HW_STATE_STATION_ 0x02 ++#define _HW_STATE_AP_ 0x03 ++ ++ ++#define _1M_RATE_ 0 ++#define _2M_RATE_ 1 ++#define _5M_RATE_ 2 ++#define _11M_RATE_ 3 ++#define _6M_RATE_ 4 ++#define _9M_RATE_ 5 ++#define _12M_RATE_ 6 ++#define _18M_RATE_ 7 ++#define _24M_RATE_ 8 ++#define _36M_RATE_ 9 ++#define _48M_RATE_ 10 ++#define _54M_RATE_ 11 ++ ++ ++extern unsigned char RTW_WPA_OUI[]; ++extern unsigned char WMM_OUI[]; ++extern unsigned char WPS_OUI[]; ++extern unsigned char WFD_OUI[]; ++extern unsigned char P2P_OUI[]; ++ ++extern unsigned char WMM_INFO_OUI[]; ++extern unsigned char WMM_PARA_OUI[]; ++ ++ ++// ++// Channel Plan Type. ++// Note: ++// We just add new channel plan when the new channel plan is different from any of the following ++// channel plan. ++// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, ++// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST. ++// ++typedef enum _RT_CHANNEL_DOMAIN ++{ ++ //===== old channel plan mapping =====// ++ RT_CHANNEL_DOMAIN_FCC = 0x00, ++ RT_CHANNEL_DOMAIN_IC = 0x01, ++ RT_CHANNEL_DOMAIN_ETSI = 0x02, ++ RT_CHANNEL_DOMAIN_SPAIN = 0x03, ++ RT_CHANNEL_DOMAIN_FRANCE = 0x04, ++ RT_CHANNEL_DOMAIN_MKK = 0x05, ++ RT_CHANNEL_DOMAIN_MKK1 = 0x06, ++ RT_CHANNEL_DOMAIN_ISRAEL = 0x07, ++ RT_CHANNEL_DOMAIN_TELEC = 0x08, ++ RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09, ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A, ++ RT_CHANNEL_DOMAIN_TAIWAN = 0x0B, ++ RT_CHANNEL_DOMAIN_CHINA = 0x0C, ++ RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D, ++ RT_CHANNEL_DOMAIN_KOREA = 0x0E, ++ RT_CHANNEL_DOMAIN_TURKEY = 0x0F, ++ RT_CHANNEL_DOMAIN_JAPAN = 0x10, ++ RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, ++ RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, ++ RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, ++ ++ //===== new channel plan mapping, (2GDOMAIN_5GDOMAIN) =====// ++ RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, ++ RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, ++ RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, ++ RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, ++ RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, ++ RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, ++ RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, ++ RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, ++ RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, ++ RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, ++ RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, ++ RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, ++ RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, ++ RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, ++ RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, ++ RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, ++ RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, ++ RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, ++ RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41, ++ //===== Add new channel plan above this line===============// ++ RT_CHANNEL_DOMAIN_MAX, ++ RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, ++}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; ++ ++typedef enum _RT_CHANNEL_DOMAIN_2G ++{ ++ RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, //Worldwird 13 ++ RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe ++ RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, //US ++ RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, //Japan ++ RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, //France ++ RT_CHANNEL_DOMAIN_2G_NULL = 0x05, ++ //===== Add new channel plan above this line===============// ++ RT_CHANNEL_DOMAIN_2G_MAX, ++}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; ++ ++typedef enum _RT_CHANNEL_DOMAIN_5G ++{ ++ RT_CHANNEL_DOMAIN_5G_NULL = 0x00, ++ RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe ++ RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, //Australia, New Zealand ++ RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, //Russia ++ RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, //US ++ RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, //FCC o/w DFS Channels ++ RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, //India, Mexico ++ RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, //Venezuela ++ RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, //China ++ RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, //Israel ++ RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, //US, Canada ++ RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, //Korea ++ RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, //Japan ++ RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, //Japan (W52, W53) ++ RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, //Japan (W56) ++ RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, //Taiwan ++ RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, //Taiwan o/w DFS ++ //===== Add new channel plan above this line===============// ++ //===== Driver Self Defined =====// ++ RT_CHANNEL_DOMAIN_5G_FCC = 0x11, ++ RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12, ++ RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS = 0x13, ++ RT_CHANNEL_DOMAIN_5G_MAX, ++}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; ++ ++#define rtw_is_channel_plan_valid(chplan) (chplansurvey_timer, (ms)); \ ++ } while(0) ++ ++#define set_link_timer(mlmeext, ms) \ ++ do { \ ++ /*DBG_871X("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ ++ _set_timer(&(mlmeext)->link_timer, (ms)); \ ++ } while(0) ++#ifdef CONFIG_IEEE80211W ++#define set_sa_query_timer(mlmeext, ms) \ ++ do { \ ++ DBG_871X("%s set_sa_query_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms)); \ ++ _set_timer(&(mlmeext)->sa_query_timer, (ms)); \ ++ } while(0) ++#endif //CONFIG_IEEE80211W ++extern int cckrates_included(unsigned char *rate, int ratelen); ++extern int cckratesonly_included(unsigned char *rate, int ratelen); ++ ++extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); ++ ++extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); ++extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state); ++void concurrent_chk_joinbss_done(_adapter *padapter, int join_res); ++#endif //CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++void dc_SelectChannel(_adapter *padapter, unsigned char channel); ++void dc_SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset); ++void dc_set_channel_bwmode_disconnect(_adapter *padapter); ++u8 dc_handle_join_request(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); ++void dc_handle_join_done(_adapter *padapter, u8 join_res); ++sint dc_check_fwstate(_adapter *padapter, sint fw_state); ++u8 dc_handle_site_survey(_adapter *padapter); ++void dc_report_survey_event(_adapter *padapter, union recv_frame *precv_frame); ++void dc_set_channel_bwmode_survey_done(_adapter *padapter); ++void dc_set_ap_channel_bandwidth(_adapter *padapter, u8 channel, u8 channel_offset, u8 bwmode); ++void dc_resume_xmit(_adapter *padapter); ++u8 dc_check_xmit(_adapter *padapter); ++#endif ++ ++int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); ++int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); ++ ++struct cmd_hdl { ++ uint parmsize; ++ u8 (*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); ++}; ++ ++ ++u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf); ++ ++ ++u8 NULL_hdl(_adapter *padapter, u8 *pbuf); ++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); ++u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); ++u8 createbss_hdl(_adapter *padapter, u8 *pbuf); ++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); ++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); ++u8 setauth_hdl(_adapter *padapter, u8 *pbuf); ++u8 setkey_hdl(_adapter *padapter, u8 *pbuf); ++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); ++u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); ++u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); ++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 set_ch_hdl(_adapter *padapter, u8 *pbuf); ++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie. ++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++ ++#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl}, ++#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, ++ ++#ifdef _RTW_CMD_C_ ++ ++struct cmd_hdl wlancmds[] = ++{ ++ GEN_DRV_CMD_HANDLER(0, NULL) /*0*/ ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*10*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*40*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*50*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/ ++ ++ GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/ ++ GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/ ++ ++ GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ ++ ++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ ++}; ++ ++#endif ++ ++struct C2HEvent_Header ++{ ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ unsigned int len:16; ++ unsigned int ID:8; ++ unsigned int seq:8; ++ ++#elif defined(CONFIG_BIG_ENDIAN) ++ ++ unsigned int seq:8; ++ unsigned int ID:8; ++ unsigned int len:16; ++ ++#else ++ ++# error "Must be LITTLE or BIG Endian" ++ ++#endif ++ ++ unsigned int rsvd; ++ ++}; ++ ++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf); ++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf); ++ ++enum rtw_c2h_event ++{ ++ GEN_EVT_CODE(_Read_MACREG)=0, /*0*/ ++ GEN_EVT_CODE(_Read_BBREG), ++ GEN_EVT_CODE(_Read_RFREG), ++ GEN_EVT_CODE(_Read_EEPROM), ++ GEN_EVT_CODE(_Read_EFUSE), ++ GEN_EVT_CODE(_Read_CAM), /*5*/ ++ GEN_EVT_CODE(_Get_BasicRate), ++ GEN_EVT_CODE(_Get_DataRate), ++ GEN_EVT_CODE(_Survey), /*8*/ ++ GEN_EVT_CODE(_SurveyDone), /*9*/ ++ ++ GEN_EVT_CODE(_JoinBss) , /*10*/ ++ GEN_EVT_CODE(_AddSTA), ++ GEN_EVT_CODE(_DelSTA), ++ GEN_EVT_CODE(_AtimDone) , ++ GEN_EVT_CODE(_TX_Report), ++ GEN_EVT_CODE(_CCX_Report), /*15*/ ++ GEN_EVT_CODE(_DTM_Report), ++ GEN_EVT_CODE(_TX_Rate_Statistics), ++ GEN_EVT_CODE(_C2HLBK), ++ GEN_EVT_CODE(_FWDBG), ++ GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ ++ GEN_EVT_CODE(_ADDBA), ++ GEN_EVT_CODE(_C2HBCN), ++ GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB ++ GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM ++ MAX_C2HEVT ++}; ++ ++ ++#ifdef _RTW_MLME_EXT_C_ ++ ++static struct fwevent wlanevents[] = ++{ ++ {0, rtw_dummy_event_callback}, /*0*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, &rtw_survey_event_callback}, /*8*/ ++ {sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/ ++ ++ {0, &rtw_joinbss_event_callback}, /*10*/ ++ {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, ++ {sizeof(struct stadel_event), &rtw_stadel_event_callback}, ++ {0, &rtw_atimdone_event_callback}, ++ {0, rtw_dummy_event_callback}, ++ {0, NULL}, /*15*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, rtw_fwdbg_event_callback}, ++ {0, NULL}, /*20*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, &rtw_cpwm_event_callback}, ++}; ++ ++#endif//_RTL8192C_CMD_C_ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp.h +new file mode 100644 +index 00000000..9a017a46 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp.h +@@ -0,0 +1,771 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_MP_H_ ++#define _RTW_MP_H_ ++ ++#ifndef PLATFORM_WINDOWS ++// 00 - Success ++// 11 - Error ++#define STATUS_SUCCESS (0x00000000L) ++#define STATUS_PENDING (0x00000103L) ++ ++#define STATUS_UNSUCCESSFUL (0xC0000001L) ++#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) ++#define STATUS_NOT_SUPPORTED (0xC00000BBL) ++ ++#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) ++#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) ++#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) ++#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) ++#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) ++#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) ++ ++#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) ++#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) ++#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) ++#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) ++#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) ++#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) ++#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) ++#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) ++#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) ++#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) ++#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) ++#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) ++#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) ++#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) ++#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) ++#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) ++#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) ++#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) ++#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) ++#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) ++#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) ++#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) ++#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) ++#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) ++#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) ++#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) ++#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) ++#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) ++#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) ++#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) ++#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) ++#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) ++ ++#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) ++#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) ++#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) ++#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) ++#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27 ++#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45 ++#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37 ++#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49 ++#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93 ++#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3 ++#endif /* #ifndef PLATFORM_WINDOWS */ ++ ++#if 0 ++#define MPT_NOOP 0 ++#define MPT_READ_MAC_1BYTE 1 ++#define MPT_READ_MAC_2BYTE 2 ++#define MPT_READ_MAC_4BYTE 3 ++#define MPT_WRITE_MAC_1BYTE 4 ++#define MPT_WRITE_MAC_2BYTE 5 ++#define MPT_WRITE_MAC_4BYTE 6 ++#define MPT_READ_BB_CCK 7 ++#define MPT_WRITE_BB_CCK 8 ++#define MPT_READ_BB_OFDM 9 ++#define MPT_WRITE_BB_OFDM 10 ++#define MPT_READ_RF 11 ++#define MPT_WRITE_RF 12 ++#define MPT_READ_EEPROM_1BYTE 13 ++#define MPT_WRITE_EEPROM_1BYTE 14 ++#define MPT_READ_EEPROM_2BYTE 15 ++#define MPT_WRITE_EEPROM_2BYTE 16 ++#define MPT_SET_CSTHRESHOLD 21 ++#define MPT_SET_INITGAIN 22 ++#define MPT_SWITCH_BAND 23 ++#define MPT_SWITCH_CHANNEL 24 ++#define MPT_SET_DATARATE 25 ++#define MPT_SWITCH_ANTENNA 26 ++#define MPT_SET_TX_POWER 27 ++#define MPT_SET_CONT_TX 28 ++#define MPT_SET_SINGLE_CARRIER 29 ++#define MPT_SET_CARRIER_SUPPRESSION 30 ++#define MPT_GET_RATE_TABLE 31 ++#define MPT_READ_TSSI 32 ++#define MPT_GET_THERMAL_METER 33 ++#endif ++ ++typedef enum _ANTENNA_PATH{ ++ ANTENNA_NONE = 0x00, ++ ANTENNA_D , ++ ANTENNA_C , ++ ANTENNA_CD , ++ ANTENNA_B , ++ ANTENNA_BD , ++ ANTENNA_BC , ++ ANTENNA_BCD , ++ ANTENNA_A , ++ ANTENNA_AD , ++ ANTENNA_AC , ++ ANTENNA_ACD , ++ ANTENNA_AB , ++ ANTENNA_ABD , ++ ANTENNA_ABC , ++ ANTENNA_ABCD ++} ANTENNA_PATH; ++ ++ ++#define MAX_MP_XMITBUF_SZ 2048 ++#define NR_MP_XMITFRAME 8 ++ ++struct mp_xmit_frame ++{ ++ _list list; ++ ++ struct pkt_attrib attrib; ++ ++ _pkt *pkt; ++ ++ int frame_tag; ++ ++ _adapter *padapter; ++ ++#ifdef CONFIG_USB_HCI ++ ++ //insert urb, irp, and irpcnt info below... ++ //max frag_cnt = 8 ++ ++ u8 *mem_addr; ++ u32 sz[8]; ++ ++#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) ++ PURB pxmit_urb[8]; ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ PIRP pxmit_irp[8]; ++#endif ++ ++ u8 bpending[8]; ++ sint ac_tag[8]; ++ sint last[8]; ++ uint irpcnt; ++ uint fragcnt; ++#endif /* CONFIG_USB_HCI */ ++ ++ uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; ++}; ++ ++struct mp_wiparam ++{ ++ u32 bcompleted; ++ u32 act_type; ++ u32 io_offset; ++ u32 io_value; ++}; ++ ++typedef void(*wi_act_func)(void* padapter); ++ ++#ifdef PLATFORM_WINDOWS ++struct mp_wi_cntx ++{ ++ u8 bmpdrv_unload; ++ ++ // Work Item ++ NDIS_WORK_ITEM mp_wi; ++ NDIS_EVENT mp_wi_evt; ++ _lock mp_wi_lock; ++ u8 bmp_wi_progress; ++ wi_act_func curractfunc; ++ // Variable needed in each implementation of CurrActFunc. ++ struct mp_wiparam param; ++}; ++#endif ++ ++struct mp_tx ++{ ++ u8 stop; ++ u32 count, sended; ++ u8 payload; ++ struct pkt_attrib attrib; ++ struct tx_desc desc; ++ u8 *pallocated_buf; ++ u8 *buf; ++ u32 buf_size, write_size; ++ _thread_hdl_ PktTxThread; ++}; ++ ++#if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) || defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8188E) ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++ ++#define MP_MAX_LINES 1000 ++#define MP_MAX_LINES_BYTES 256 ++#define u1Byte u8 ++#define s1Byte s8 ++#define u4Byte u32 ++#define s4Byte s32 ++#define u1Byte u8 ++#define pu1Byte u8* ++ ++#define u2Byte u16 ++#define pu2Byte u16* ++ ++#define u4Byte u32 ++#define pu4Byte u32* ++ ++#define u8Byte u64 ++#define pu8Byte u64* ++ ++#define s1Byte s8 ++#define ps1Byte s8* ++ ++#define s2Byte s16 ++#define ps2Byte s16* ++ ++#define s4Byte s32 ++#define ps4Byte s32* ++ ++#define s8Byte s64 ++#define ps8Byte s64* ++ ++#define UCHAR u8 ++#define USHORT u16 ++#define UINT u32 ++#define ULONG u32 ++#define PULONG u32* ++ ++ ++ ++typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter); ++typedef struct _MPT_CONTEXT ++{ ++ // Indicate if we have started Mass Production Test. ++ BOOLEAN bMassProdTest; ++ ++ // Indicate if the driver is unloading or unloaded. ++ BOOLEAN bMptDrvUnload; ++ ++ _sema MPh2c_Sema; ++ _timer MPh2c_timeout_timer; ++// Event used to sync H2c for BT control ++ ++ BOOLEAN MptH2cRspEvent; ++ BOOLEAN MptBtC2hEvent; ++ BOOLEAN bMPh2c_timeout; ++ ++ /* 8190 PCI does not support NDIS_WORK_ITEM. */ ++ // Work Item for Mass Production Test. ++ //NDIS_WORK_ITEM MptWorkItem; ++// RT_WORK_ITEM MptWorkItem; ++ // Event used to sync the case unloading driver and MptWorkItem is still in progress. ++// NDIS_EVENT MptWorkItemEvent; ++ // To protect the following variables. ++// NDIS_SPIN_LOCK MptWorkItemSpinLock; ++ // Indicate a MptWorkItem is scheduled and not yet finished. ++ BOOLEAN bMptWorkItemInProgress; ++ // An instance which implements function and context of MptWorkItem. ++ MPT_WORK_ITEM_HANDLER CurrMptAct; ++ ++ // 1=Start, 0=Stop from UI. ++ ULONG MptTestStart; ++ // _TEST_MODE, defined in MPT_Req2.h ++ ULONG MptTestItem; ++ // Variable needed in each implementation of CurrMptAct. ++ ULONG MptActType; // Type of action performed in CurrMptAct. ++ // The Offset of IO operation is depend of MptActType. ++ ULONG MptIoOffset; ++ // The Value of IO operation is depend of MptActType. ++ ULONG MptIoValue; ++ // The RfPath of IO operation is depend of MptActType. ++ ULONG MptRfPath; ++ ++ WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch. ++ u8 MptChannelToSw; // Channel to switch. ++ u8 MptInitGainToSet; // Initial gain to set. ++ //ULONG bMptAntennaA; // TRUE if we want to use antenna A. ++ ULONG MptBandWidth; // bandwidth to switch. ++ ULONG MptRateIndex; // rate index. ++ // Register value kept for Single Carrier Tx test. ++ u8 btMpCckTxPower; ++ // Register value kept for Single Carrier Tx test. ++ u8 btMpOfdmTxPower; ++ // For MP Tx Power index ++ u8 TxPwrLevel[2]; // rf-A, rf-B ++ ++ // Content of RCR Regsiter for Mass Production Test. ++ ULONG MptRCR; ++ // TRUE if we only receive packets with specific pattern. ++ BOOLEAN bMptFilterPattern; ++ // Rx OK count, statistics used in Mass Production Test. ++ ULONG MptRxOkCnt; ++ // Rx CRC32 error count, statistics used in Mass Production Test. ++ ULONG MptRxCrcErrCnt; ++ ++ BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test. ++ BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test. ++ BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test. ++ // TRUE if we are in Single Carrier Tx test. ++ BOOLEAN bSingleCarrier; ++ // TRUE if we are in Carrier Suppression Tx Test. ++ BOOLEAN bCarrierSuppression; ++ //TRUE if we are in Single Tone Tx test. ++ BOOLEAN bSingleTone; ++ ++ // ACK counter asked by K.Y.. ++ BOOLEAN bMptEnableAckCounter; ++ ULONG MptAckCounter; ++ ++ // SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! ++ //s1Byte BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; ++ //s1Byte BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; ++ //s4Byte RfReadLine[2]; ++ ++ u8 APK_bound[2]; //for APK path A/path B ++ BOOLEAN bMptIndexEven; ++ ++ u8 backup0xc50; ++ u8 backup0xc58; ++ u8 backup0xc30; ++ u8 backup0x52_RF_A; ++ u8 backup0x52_RF_B; ++ ++ u1Byte h2cReqNum; ++ u1Byte c2hBuf[20]; ++ ++ u1Byte btInBuf[100]; ++ ULONG mptOutLen; ++ u1Byte mptOutBuf[100]; ++ ++}MPT_CONTEXT, *PMPT_CONTEXT; ++#endif ++//#endif ++ ++//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) ++enum { ++ WRITE_REG = 1, ++ READ_REG, ++ WRITE_RF, ++ READ_RF, ++ MP_START, ++ MP_STOP, ++ MP_RATE, ++ MP_CHANNEL, ++ MP_BANDWIDTH, ++ MP_TXPOWER, ++ MP_ANT_TX, ++ MP_ANT_RX, ++ MP_CTX, ++ MP_QUERY, ++ MP_ARX, ++ MP_PSD, ++ MP_PWRTRK, ++ MP_THER, ++ MP_IOCTL, ++ EFUSE_GET, ++ EFUSE_SET, ++ MP_RESET_STATS, ++ MP_DUMP, ++ MP_PHYPARA, ++ MP_SetRFPathSwh, ++ MP_QueryDrvStats, ++ MP_SetBT, ++ CTA_TEST, ++ MP_DISABLE_BT_COEXIST, ++ MP_PwrCtlDM, ++#ifdef CONFIG_WOWLAN ++ MP_WOW_ENABLE, ++#endif ++ MP_NULL, ++}; ++ ++struct mp_priv ++{ ++ _adapter *papdater; ++ ++ //Testing Flag ++ u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD) ++ ++ u32 prev_fw_state; ++ ++ //OID cmd handler ++ struct mp_wiparam workparam; ++// u8 act_in_progress; ++ ++ //Tx Section ++ u8 TID; ++ u32 tx_pktcount; ++ struct mp_tx tx; ++ ++ //Rx Section ++ u32 rx_pktcount; ++ u32 rx_crcerrpktcount; ++ u32 rx_pktloss; ++ ++ struct recv_stat rxstat; ++ ++ //RF/BB relative ++ u8 channel; ++ u8 bandwidth; ++ u8 prime_channel_offset; ++ u8 txpoweridx; ++ u8 txpoweridx_b; ++ u8 rateidx; ++ u32 preamble; ++// u8 modem; ++ u32 CrystalCap; ++// u32 curr_crystalcap; ++ ++ u16 antenna_tx; ++ u16 antenna_rx; ++// u8 curr_rfpath; ++ ++ u8 check_mp_pkt; ++ ++ u8 bSetTxPower; ++// uint ForcedDataRate; ++ ++ struct wlan_network mp_network; ++ NDIS_802_11_MAC_ADDRESS network_macaddr; ++ ++#ifdef PLATFORM_WINDOWS ++ u32 rx_testcnt; ++ u32 rx_testcnt1; ++ u32 rx_testcnt2; ++ u32 tx_testcnt; ++ u32 tx_testcnt1; ++ ++ struct mp_wi_cntx wi_cntx; ++ ++ u8 h2c_result; ++ u8 h2c_seqnum; ++ u16 h2c_cmdcode; ++ u8 h2c_resp_parambuf[512]; ++ _lock h2c_lock; ++ _lock wkitm_lock; ++ u32 h2c_cmdcnt; ++ NDIS_EVENT h2c_cmd_evt; ++ NDIS_EVENT c2h_set; ++ NDIS_EVENT h2c_clr; ++ NDIS_EVENT cpwm_int; ++ ++ NDIS_EVENT scsir_full_evt; ++ NDIS_EVENT scsiw_empty_evt; ++#endif ++ ++ u8 *pallocated_mp_xmitframe_buf; ++ u8 *pmp_xmtframe_buf; ++ _queue free_mp_xmitqueue; ++ u32 free_mp_xmitframe_cnt; ++ ++ MPT_CONTEXT MptCtx; ++}; ++ ++typedef struct _IOCMD_STRUCT_ { ++ u8 cmdclass; ++ u16 value; ++ u8 index; ++}IOCMD_STRUCT; ++ ++struct rf_reg_param { ++ u32 path; ++ u32 offset; ++ u32 value; ++}; ++ ++struct bb_reg_param { ++ u32 offset; ++ u32 value; ++}; ++//======================================================================= ++ ++#define LOWER _TRUE ++#define RAISE _FALSE ++ ++/* Hardware Registers */ ++#if 0 ++#if 0 ++#define IOCMD_CTRL_REG 0x102502C0 ++#define IOCMD_DATA_REG 0x102502C4 ++#else ++#define IOCMD_CTRL_REG 0x10250370 ++#define IOCMD_DATA_REG 0x10250374 ++#endif ++ ++#define IOCMD_GET_THERMAL_METER 0xFD000028 ++ ++#define IOCMD_CLASS_BB_RF 0xF0 ++#define IOCMD_BB_READ_IDX 0x00 ++#define IOCMD_BB_WRITE_IDX 0x01 ++#define IOCMD_RF_READ_IDX 0x02 ++#define IOCMD_RF_WRIT_IDX 0x03 ++#endif ++#define BB_REG_BASE_ADDR 0x800 ++ ++/* MP variables */ ++#if 0 ++#define _2MAC_MODE_ 0 ++#define _LOOPBOOK_MODE_ 1 ++#endif ++typedef enum _MP_MODE_ { ++ MP_OFF, ++ MP_ON, ++ MP_ERR, ++ MP_CONTINUOUS_TX, ++ MP_SINGLE_CARRIER_TX, ++ MP_CARRIER_SUPPRISSION_TX, ++ MP_SINGLE_TONE_TX, ++ MP_PACKET_TX, ++ MP_PACKET_RX ++} MP_MODE; ++ ++ ++#define MAX_RF_PATH_NUMS RF_PATH_MAX ++ ++ ++extern u8 mpdatarate[NumRates]; ++ ++/* MP set force data rate base on the definition. */ ++typedef enum _MPT_RATE_INDEX ++{ ++ /* CCK rate. */ ++ MPT_RATE_1M, /* 0 */ ++ MPT_RATE_2M, ++ MPT_RATE_55M, ++ MPT_RATE_11M, /* 3 */ ++ ++ /* OFDM rate. */ ++ MPT_RATE_6M, /* 4 */ ++ MPT_RATE_9M, ++ MPT_RATE_12M, ++ MPT_RATE_18M, ++ MPT_RATE_24M, ++ MPT_RATE_36M, ++ MPT_RATE_48M, ++ MPT_RATE_54M, /* 11 */ ++ ++ /* HT rate. */ ++ MPT_RATE_MCS0, /* 12 */ ++ MPT_RATE_MCS1, ++ MPT_RATE_MCS2, ++ MPT_RATE_MCS3, ++ MPT_RATE_MCS4, ++ MPT_RATE_MCS5, ++ MPT_RATE_MCS6, ++ MPT_RATE_MCS7, /* 19 */ ++ MPT_RATE_MCS8, ++ MPT_RATE_MCS9, ++ MPT_RATE_MCS10, ++ MPT_RATE_MCS11, ++ MPT_RATE_MCS12, ++ MPT_RATE_MCS13, ++ MPT_RATE_MCS14, ++ MPT_RATE_MCS15, /* 27 */ ++ MPT_RATE_LAST ++}MPT_RATE_E, *PMPT_RATE_E; ++ ++#if 0 ++// Represent Channel Width in HT Capabilities ++typedef enum _HT_CHANNEL_WIDTH { ++ HT_CHANNEL_WIDTH_20 = 0, ++ HT_CHANNEL_WIDTH_40 = 1, ++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; ++#endif ++ ++#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F ++ ++typedef enum _POWER_MODE_ { ++ POWER_LOW = 0, ++ POWER_NORMAL ++}POWER_MODE; ++ ++ ++#define RX_PKT_BROADCAST 1 ++#define RX_PKT_DEST_ADDR 2 ++#define RX_PKT_PHY_MATCH 3 ++ ++#if 0 ++#define RPTMaxCount 0x000FFFFF; ++ ++// parameter 1 : BitMask ++// bit 0 : OFDM PPDU ++// bit 1 : OFDM False Alarm ++// bit 2 : OFDM MPDU OK ++// bit 3 : OFDM MPDU Fail ++// bit 4 : CCK PPDU ++// bit 5 : CCK False Alarm ++// bit 6 : CCK MPDU ok ++// bit 7 : CCK MPDU fail ++// bit 8 : HT PPDU counter ++// bit 9 : HT false alarm ++// bit 10 : HT MPDU total ++// bit 11 : HT MPDU OK ++// bit 12 : HT MPDU fail ++// bit 15 : RX full drop ++typedef enum _RXPHY_BITMASK_ ++{ ++ OFDM_PPDU_BIT = 0, ++ OFDM_FALSE_BIT, ++ OFDM_MPDU_OK_BIT, ++ OFDM_MPDU_FAIL_BIT, ++ CCK_PPDU_BIT, ++ CCK_FALSE_BIT, ++ CCK_MPDU_OK_BIT, ++ CCK_MPDU_FAIL_BIT, ++ HT_PPDU_BIT, ++ HT_FALSE_BIT, ++ HT_MPDU_BIT, ++ HT_MPDU_OK_BIT, ++ HT_MPDU_FAIL_BIT, ++} RXPHY_BITMASK; ++#endif ++ ++typedef enum _ENCRY_CTRL_STATE_ { ++ HW_CONTROL, //hw encryption& decryption ++ SW_CONTROL, //sw encryption& decryption ++ HW_ENCRY_SW_DECRY, //hw encryption & sw decryption ++ SW_ENCRY_HW_DECRY //sw encryption & hw decryption ++}ENCRY_CTRL_STATE; ++ ++#define Mac_OFDM_OK 0x00000000 ++#define Mac_OFDM_Fail 0x10000000 ++#define Mac_OFDM_FasleAlarm 0x20000000 ++#define Mac_CCK_OK 0x30000000 ++#define Mac_CCK_Fail 0x40000000 ++#define Mac_CCK_FasleAlarm 0x50000000 ++#define Mac_HT_OK 0x60000000 ++#define Mac_HT_Fail 0x70000000 ++#define Mac_HT_FasleAlarm 0x90000000 ++#define Mac_DropPacket 0xA0000000 ++ ++//======================================================================= ++//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); ++//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); ++ ++extern s32 init_mp_priv(PADAPTER padapter); ++extern void free_mp_priv(struct mp_priv *pmp_priv); ++extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); ++extern void MPT_DeInitAdapter(PADAPTER padapter); ++extern s32 mp_start_test(PADAPTER padapter); ++extern void mp_stop_test(PADAPTER padapter); ++ ++//======================================================================= ++//extern void IQCalibrateBcut(PADAPTER pAdapter); ++ ++//extern u32 bb_reg_read(PADAPTER Adapter, u16 offset); ++//extern u8 bb_reg_write(PADAPTER Adapter, u16 offset, u32 value); ++//extern u32 rf_reg_read(PADAPTER Adapter, u8 path, u8 offset); ++//extern u8 rf_reg_write(PADAPTER Adapter, u8 path, u8 offset, u32 value); ++ ++//extern u32 get_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask); ++//extern u8 set_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask, u32 value); ++//extern u32 get_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask); ++//extern u8 set_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask, u32 value); ++ ++extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); ++extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); ++ ++extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); ++extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); ++extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); ++extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); ++extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); ++extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); ++ ++extern void SetChannel(PADAPTER pAdapter); ++extern void SetBandwidth(PADAPTER pAdapter); ++extern void SetTxPower(PADAPTER pAdapter); ++extern void SetAntennaPathPower(PADAPTER pAdapter); ++//extern void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset); ++extern void SetDataRate(PADAPTER pAdapter); ++ ++extern void SetAntenna(PADAPTER pAdapter); ++ ++//extern void SetCrystalCap(PADAPTER pAdapter); ++ ++extern s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); ++extern void GetThermalMeter(PADAPTER pAdapter, u8 *value); ++ ++extern void SetContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); ++extern void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); ++extern void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); ++extern void PhySetTxPowerLevel(PADAPTER pAdapter); ++ ++extern void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc); ++extern void SetPacketTx(PADAPTER padapter); ++extern void SetPacketRx(PADAPTER pAdapter, u8 bStartRx); ++ ++extern void ResetPhyRxPktCount(PADAPTER pAdapter); ++extern u32 GetPhyRxPktReceived(PADAPTER pAdapter); ++extern u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); ++ ++extern s32 SetPowerTracking(PADAPTER padapter, u8 enable); ++extern void GetPowerTracking(PADAPTER padapter, u8 *enable); ++ ++extern u32 mp_query_psd(PADAPTER pAdapter, u8 *data); ++ ++ ++extern void Hal_SetAntenna(PADAPTER pAdapter); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetTxPower(PADAPTER pAdapter); ++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart ); ++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetDataRate(PADAPTER pAdapter); ++extern void Hal_SetChannel(PADAPTER pAdapter); ++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter); ++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); ++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable); ++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable); ++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value); ++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter); ++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); ++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven); ++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter); ++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter); ++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_ProSetCrystalCap (PADAPTER pAdapter , u32 CrystalCapVal); ++extern void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv); ++extern void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter ,BOOLEAN bMain); ++extern void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); ++ ++#endif //_RTW_MP_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_ioctl.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_ioctl.h +new file mode 100644 +index 00000000..962bc38e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_ioctl.h +@@ -0,0 +1,596 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_MP_IOCTL_H_ ++#define _RTW_MP_IOCTL_H_ ++ ++//#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define TESTFWCMDNUMBER 1000000 ++#define TEST_H2CINT_WAIT_TIME 500 ++#define TEST_C2HINT_WAIT_TIME 500 ++#define HCI_TEST_SYSCFG_HWMASK 1 ++#define _BUSCLK_40M (4 << 2) ++#endif ++//------------------------------------------------------------------------------ ++typedef struct CFG_DBG_MSG_STRUCT { ++ u32 DebugLevel; ++ u32 DebugComponent_H32; ++ u32 DebugComponent_L32; ++}CFG_DBG_MSG_STRUCT,*PCFG_DBG_MSG_STRUCT; ++ ++typedef struct _RW_REG { ++ u32 offset; ++ u32 width; ++ u32 value; ++}mp_rw_reg,RW_Reg, *pRW_Reg; ++ ++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM ++typedef struct _EEPROM_RW_PARAM { ++ u32 offset; ++ u16 value; ++}eeprom_rw_param,EEPROM_RWParam, *pEEPROM_RWParam; ++ ++typedef struct _EFUSE_ACCESS_STRUCT_ { ++ u16 start_addr; ++ u16 cnts; ++ u8 data[0]; ++}EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT; ++ ++typedef struct _BURST_RW_REG { ++ u32 offset; ++ u32 len; ++ u8 Data[256]; ++}burst_rw_reg,Burst_RW_Reg, *pBurst_RW_Reg; ++ ++typedef struct _USB_VendorReq{ ++ u8 bRequest; ++ u16 wValue; ++ u16 wIndex; ++ u16 wLength; ++ u8 u8Dir;//0:OUT, 1:IN ++ u8 u8InData; ++}usb_vendor_req, USB_VendorReq, *pUSB_VendorReq; ++ ++typedef struct _DR_VARIABLE_STRUCT_ { ++ u8 offset; ++ u32 variable; ++}DR_VARIABLE_STRUCT; ++ ++//int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid); ++ ++//void _irqlevel_changed_(_irqL *irqlevel, /*BOOLEAN*/unsigned char bLower); ++#ifdef PLATFORM_OS_XP ++static void _irqlevel_changed_(_irqL *irqlevel, u8 bLower) ++{ ++ ++ if (bLower == LOWER) { ++ *irqlevel = KeGetCurrentIrql(); ++ ++ if (*irqlevel > PASSIVE_LEVEL) { ++ KeLowerIrql(PASSIVE_LEVEL); ++ } ++ } else { ++ if (KeGetCurrentIrql() == PASSIVE_LEVEL) { ++ KeRaiseIrql(DISPATCH_LEVEL, irqlevel); ++ } ++ } ++ ++} ++#else ++#define _irqlevel_changed_(a,b) ++#endif ++ ++//oid_rtl_seg_81_80_00 ++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_81_80_20 ++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_81_87 ++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_81_85 ++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++// oid_rtl_seg_87_11_00 ++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv); ++// oid_rtl_seg_87_11_20 ++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_87_11_50 ++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_87_11_F0 ++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_87_12_00 ++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv); ++ ++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv); ++ ++#ifdef _RTW_MP_IOCTL_C_ ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_00[] = ++{ ++ {1, &oid_null_function}, //0x00 OID_RT_PRO_RESET_DUT ++ {1, &oid_rt_pro_set_data_rate_hdl}, //0x01 ++ {1, &oid_rt_pro_start_test_hdl}, //0x02 ++ {1, &oid_rt_pro_stop_test_hdl}, //0x03 ++ {1, &oid_null_function}, //0x04 OID_RT_PRO_SET_PREAMBLE ++ {1, &oid_null_function}, //0x05 OID_RT_PRO_SET_SCRAMBLER ++ {1, &oid_null_function}, //0x06 OID_RT_PRO_SET_FILTER_BB ++ {1, &oid_null_function}, //0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB ++ {1, &oid_rt_pro_set_channel_direct_call_hdl}, //0x08 ++ {1, &oid_null_function}, //0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL ++ {1, &oid_null_function}, //0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL ++ {1, &oid_rt_pro_set_continuous_tx_hdl}, //0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL ++ {1, &oid_rt_pro_set_single_carrier_tx_hdl}, //0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS ++ {1, &oid_null_function}, //0x0D OID_RT_PRO_SET_TX_ANTENNA_BB ++ {1, &oid_rt_pro_set_antenna_bb_hdl}, //0x0E ++ {1, &oid_null_function}, //0x0F OID_RT_PRO_SET_CR_SCRAMBLER ++ {1, &oid_null_function}, //0x10 OID_RT_PRO_SET_CR_NEW_FILTER ++ {1, &oid_rt_pro_set_tx_power_control_hdl}, //0x11 OID_RT_PRO_SET_TX_POWER_CONTROL ++ {1, &oid_null_function}, //0x12 OID_RT_PRO_SET_CR_TX_CONFIG ++ {1, &oid_null_function}, //0x13 OID_RT_PRO_GET_TX_POWER_CONTROL ++ {1, &oid_null_function}, //0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x15 OID_RT_PRO_SET_CR_SETPOINT ++ {1, &oid_null_function}, //0x16 OID_RT_PRO_SET_INTEGRATOR ++ {1, &oid_null_function}, //0x17 OID_RT_PRO_SET_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x18 OID_RT_PRO_GET_INTEGRATOR ++ {1, &oid_null_function}, //0x19 OID_RT_PRO_GET_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x1A OID_RT_PRO_QUERY_EEPROM_TYPE ++ {1, &oid_null_function}, //0x1B OID_RT_PRO_WRITE_MAC_ADDRESS ++ {1, &oid_null_function}, //0x1C OID_RT_PRO_READ_MAC_ADDRESS ++ {1, &oid_null_function}, //0x1D OID_RT_PRO_WRITE_CIS_DATA ++ {1, &oid_null_function}, //0x1E OID_RT_PRO_READ_CIS_DATA ++ {1, &oid_null_function} //0x1F OID_RT_PRO_WRITE_POWER_CONTROL ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_20[] = ++{ ++ {1, &oid_null_function}, //0x20 OID_RT_PRO_READ_POWER_CONTROL ++ {1, &oid_null_function}, //0x21 OID_RT_PRO_WRITE_EEPROM ++ {1, &oid_null_function}, //0x22 OID_RT_PRO_READ_EEPROM ++ {1, &oid_rt_pro_reset_tx_packet_sent_hdl}, //0x23 ++ {1, &oid_rt_pro_query_tx_packet_sent_hdl}, //0x24 ++ {1, &oid_rt_pro_reset_rx_packet_received_hdl}, //0x25 ++ {1, &oid_rt_pro_query_rx_packet_received_hdl}, //0x26 ++ {1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, //0x27 ++ {1, &oid_null_function}, //0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS ++ {1, &oid_null_function}, //0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS ++ {1, &oid_null_function}, //0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS ++ {1, &oid_rt_pro_set_carrier_suppression_tx_hdl},//0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX ++ {1, &oid_null_function}, //0x2C OID_RT_PRO_RECEIVE_PACKET ++ {1, &oid_null_function}, //0x2D OID_RT_PRO_WRITE_EEPROM_BYTE ++ {1, &oid_null_function}, //0x2E OID_RT_PRO_READ_EEPROM_BYTE ++ {1, &oid_rt_pro_set_modulation_hdl} //0x2F ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_40[] = ++{ ++ {1, &oid_null_function}, //0x40 ++ {1, &oid_null_function}, //0x41 ++ {1, &oid_null_function}, //0x42 ++ {1, &oid_rt_pro_set_single_tone_tx_hdl}, //0x43 ++ {1, &oid_null_function}, //0x44 ++ {1, &oid_null_function} //0x45 ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_80[] = ++{ ++ {1, &oid_null_function}, //0x80 OID_RT_DRIVER_OPTION ++ {1, &oid_null_function}, //0x81 OID_RT_RF_OFF ++ {1, &oid_null_function} //0x82 OID_RT_AUTH_STATUS ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_85[] = ++{ ++ {1, &oid_rt_wireless_mode_hdl} //0x00 OID_RT_WIRELESS_MODE ++}; ++ ++struct oid_obj_priv oid_rtl_seg_81_87[] = ++{ ++ {1, &oid_null_function}, //0x80 OID_RT_PRO8187_WI_POLL ++ {1, &oid_rt_pro_write_bb_reg_hdl}, //0x81 ++ {1, &oid_rt_pro_read_bb_reg_hdl}, //0x82 ++ {1, &oid_rt_pro_write_rf_reg_hdl}, //0x82 ++ {1, &oid_rt_pro_read_rf_reg_hdl} //0x83 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_00[] = ++{ ++ {1, &oid_rt_pro8711_join_bss_hdl}, //0x00 //S ++ {1, &oid_rt_pro_read_register_hdl}, //0x01 ++ {1, &oid_rt_pro_write_register_hdl}, //0x02 ++ {1, &oid_rt_pro_burst_read_register_hdl}, //0x03 ++ {1, &oid_rt_pro_burst_write_register_hdl}, //0x04 ++ {1, &oid_rt_pro_write_txcmd_hdl}, //0x05 ++ {1, &oid_rt_pro_read16_eeprom_hdl}, //0x06 ++ {1, &oid_rt_pro_write16_eeprom_hdl}, //0x07 ++ {1, &oid_null_function}, //0x08 OID_RT_PRO_H2C_SET_COMMAND ++ {1, &oid_null_function}, //0x09 OID_RT_PRO_H2C_QUERY_RESULT ++ {1, &oid_rt_pro8711_wi_poll_hdl}, //0x0A ++ {1, &oid_rt_pro8711_pkt_loss_hdl}, //0x0B ++ {1, &oid_rt_rd_attrib_mem_hdl}, //0x0C ++ {1, &oid_rt_wr_attrib_mem_hdl}, //0x0D ++ {1, &oid_null_function}, //0x0E ++ {1, &oid_null_function}, //0x0F ++ {1, &oid_null_function}, //0x10 OID_RT_PRO_H2C_CMD_MODE ++ {1, &oid_null_function}, //0x11 OID_RT_PRO_H2C_CMD_RSP_MODE ++ {1, &oid_null_function}, //0X12 OID_RT_PRO_WAIT_C2H_EVENT ++ {1, &oid_null_function}, //0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST ++ {1, &oid_null_function}, //0X14 OID_RT_PRO_SCSI_ACCESS_TEST ++ {1, &oid_null_function}, //0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT ++ {1, &oid_null_function}, //0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN ++ {1, &oid_null_function}, //0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL ++ {1, &oid_null_function}, //0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL ++ {1, &oid_null_function}, //0X19 OID_RT_RPO_SET_PWRMGT_TEST ++ {1, &oid_null_function}, //0X1A ++ {1, &oid_null_function}, //0X1B OID_RT_PRO_QRY_PWRMGT_TEST ++ {1, &oid_null_function}, //0X1C OID_RT_RPO_ASYNC_RWIO_TEST ++ {1, &oid_null_function}, //0X1D OID_RT_RPO_ASYNC_RWIO_POLL ++ {1, &oid_rt_pro_set_rf_intfs_hdl}, //0X1E ++ {1, &oid_rt_poll_rx_status_hdl} //0X1F ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_20[] = ++{ ++ {1, &oid_rt_pro_cfg_debug_message_hdl}, //0x20 ++ {1, &oid_rt_pro_set_data_rate_ex_hdl}, //0x21 ++ {1, &oid_rt_pro_set_basic_rate_hdl}, //0x22 ++ {1, &oid_rt_pro_read_tssi_hdl}, //0x23 ++ {1, &oid_rt_pro_set_power_tracking_hdl} //0x24 ++}; ++ ++ ++struct oid_obj_priv oid_rtl_seg_87_11_50[] = ++{ ++ {1, &oid_rt_pro_qry_pwrstate_hdl}, //0x50 ++ {1, &oid_rt_pro_set_pwrstate_hdl} //0x51 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_80[] = ++{ ++ {1, &oid_null_function} //0x80 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_B0[] = ++{ ++ {1, &oid_null_function} //0xB0 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_F0[] = ++{ ++ {1, &oid_null_function}, //0xF0 ++ {1, &oid_null_function}, //0xF1 ++ {1, &oid_null_function}, //0xF2 ++ {1, &oid_null_function}, //0xF3 ++ {1, &oid_null_function}, //0xF4 ++ {1, &oid_null_function}, //0xF5 ++ {1, &oid_null_function}, //0xF6 ++ {1, &oid_null_function}, //0xF7 ++ {1, &oid_null_function}, //0xF8 ++ {1, &oid_null_function}, //0xF9 ++ {1, &oid_null_function}, //0xFA ++ {1, &oid_rt_pro_h2c_set_rate_table_hdl}, //0xFB ++ {1, &oid_rt_pro_h2c_get_rate_table_hdl}, //0xFC ++ {1, &oid_null_function}, //0xFD ++ {1, &oid_null_function}, //0xFE OID_RT_PRO_H2C_C2H_LBK_TEST ++ {1, &oid_null_function} //0xFF ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_12_00[]= ++{ ++ {1, &oid_rt_pro_encryption_ctrl_hdl}, //0x00 Q&S ++ {1, &oid_rt_pro_add_sta_info_hdl}, //0x01 S ++ {1, &oid_rt_pro_dele_sta_info_hdl}, //0x02 S ++ {1, &oid_rt_pro_query_dr_variable_hdl}, //0x03 Q ++ {1, &oid_rt_pro_rx_packet_type_hdl}, //0x04 Q,S ++ {1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE ++ {1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE ++ {1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S ++ {1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q ++ {1, &oid_rt_set_bandwidth_hdl}, //0x09 ++ {1, &oid_rt_set_crystal_cap_hdl}, //0x0a ++ {1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S ++ {1, &oid_rt_get_efuse_max_size_hdl}, //0x0c ++ {1, &oid_rt_pro_set_tx_agc_offset_hdl}, //0x0d ++ {1, &oid_rt_pro_set_pkt_test_mode_hdl}, //0x0e ++ {1, &oid_null_function}, //0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING ++ {1, &oid_rt_get_thermal_meter_hdl}, //0x10 Q OID_RT_PRO_GET_THERMAL_METER ++ {1, &oid_rt_reset_phy_rx_packet_count_hdl}, //0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT ++ {1, &oid_rt_get_phy_rx_packet_received_hdl}, //0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED ++ {1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, //0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR ++ {1, &oid_rt_set_power_down_hdl}, //0x14 Q OID_RT_SET_POWER_DOWN ++ {1, &oid_rt_get_power_mode_hdl} //0x15 Q OID_RT_GET_POWER_MODE ++}; ++ ++#else /* _RTL871X_MP_IOCTL_C_ */ ++ ++extern struct oid_obj_priv oid_rtl_seg_81_80_00[32]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_20[16]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_40[6]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_80[3]; ++ ++extern struct oid_obj_priv oid_rtl_seg_81_85[1]; ++extern struct oid_obj_priv oid_rtl_seg_81_87[5]; ++ ++extern struct oid_obj_priv oid_rtl_seg_87_11_00[32]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_20[5]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_50[2]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_80[1]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16]; ++ ++extern struct oid_obj_priv oid_rtl_seg_87_12_00[32]; ++ ++#endif /* _RTL871X_MP_IOCTL_C_ */ ++ ++struct rwreg_param{ ++ u32 offset; ++ u32 width; ++ u32 value; ++}; ++ ++struct bbreg_param{ ++ u32 offset; ++ u32 phymask; ++ u32 value; ++}; ++/* ++struct rfchannel_param{ ++ u32 ch; ++ u32 modem; ++}; ++*/ ++struct txpower_param{ ++ u32 pwr_index; ++}; ++ ++ ++struct datarate_param{ ++ u32 rate_index; ++}; ++ ++ ++struct rfintfs_parm { ++ u32 rfintfs; ++}; ++ ++typedef struct _mp_xmit_parm_ { ++ u8 enable; ++ u32 count; ++ u16 length; ++ u8 payload_type; ++ u8 da[ETH_ALEN]; ++}MP_XMIT_PARM, *PMP_XMIT_PARM; ++ ++struct mp_xmit_packet { ++ u32 len; ++ u32 mem[MAX_MP_XMITBUF_SZ >> 2]; ++}; ++ ++struct psmode_param { ++ u32 ps_mode; ++ u32 smart_ps; ++}; ++ ++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM ++struct eeprom_rw_param { ++ u32 offset; ++ u16 value; ++}; ++ ++struct mp_ioctl_handler { ++ u32 paramsize; ++ u32 (*handler)(struct oid_par_priv* poid_par_priv); ++ u32 oid; ++}; ++ ++struct mp_ioctl_param{ ++ u32 subcode; ++ u32 len; ++ u8 data[0]; ++}; ++ ++#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_ ++ ++enum RTL871X_MP_IOCTL_SUBCODE { ++ GEN_MP_IOCTL_SUBCODE(MP_START), /*0*/ ++ GEN_MP_IOCTL_SUBCODE(MP_STOP), ++ GEN_MP_IOCTL_SUBCODE(READ_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_REG), ++ GEN_MP_IOCTL_SUBCODE(READ_BB_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG), /*5*/ ++ GEN_MP_IOCTL_SUBCODE(READ_RF_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG), ++ GEN_MP_IOCTL_SUBCODE(SET_CHANNEL), ++ GEN_MP_IOCTL_SUBCODE(SET_TXPOWER), ++ GEN_MP_IOCTL_SUBCODE(SET_DATARATE), /*10*/ ++ GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH), ++ GEN_MP_IOCTL_SUBCODE(SET_ANTENNA), ++ GEN_MP_IOCTL_SUBCODE(CNTU_TX), ++ GEN_MP_IOCTL_SUBCODE(SC_TX), ++ GEN_MP_IOCTL_SUBCODE(CS_TX), /*15*/ ++ GEN_MP_IOCTL_SUBCODE(ST_TX), ++ GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET), ++ GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE), ++ GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT), ++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV), /*20*/ ++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR), ++ GEN_MP_IOCTL_SUBCODE(READ16_EEPROM), ++ GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM), ++ GEN_MP_IOCTL_SUBCODE(EFUSE), ++ GEN_MP_IOCTL_SUBCODE(EFUSE_MAP), /*25*/ ++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE), ++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE), ++ GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER), ++ GEN_MP_IOCTL_SUBCODE(SET_PTM), ++ GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN), /*30*/ ++ GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO), ++ GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*35*/ ++ GEN_MP_IOCTL_SUBCODE(DEL_BA), /*36*/ ++ GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*37*/ ++ MAX_MP_IOCTL_SUBCODE, ++}; ++ ++u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv* poid_par_priv); ++ ++#ifdef _RTW_MP_IOCTL_C_ ++ ++#define GEN_MP_IOCTL_HANDLER(sz, hdl, oid) {sz, hdl, oid}, ++ ++#define EXT_MP_IOCTL_HANDLER(sz, subcode, oid) {sz, mp_ioctl_ ## subcode ## _hdl, oid}, ++ ++ ++struct mp_ioctl_handler mp_ioctl_hdl[] = { ++ ++/*0*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_start_test_hdl, OID_RT_PRO_START_TEST) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_stop_test_hdl, OID_RT_PRO_STOP_TEST) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_read_register_hdl, OID_RT_PRO_READ_REGISTER) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_write_register_hdl, OID_RT_PRO_WRITE_REGISTER) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_read_bb_reg_hdl, OID_RT_PRO_READ_BB_REG) ++/*5*/ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_write_bb_reg_hdl, OID_RT_PRO_WRITE_BB_REG) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_read_rf_reg_hdl, OID_RT_PRO_RF_READ_REGISTRY) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_write_rf_reg_hdl, OID_RT_PRO_RF_WRITE_REGISTRY) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_channel_direct_call_hdl, OID_RT_PRO_SET_CHANNEL_DIRECT_CALL) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct txpower_param), oid_rt_pro_set_tx_power_control_hdl, OID_RT_PRO_SET_TX_POWER_CONTROL) ++/*10*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_data_rate_hdl, OID_RT_PRO_SET_DATA_RATE) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_bandwidth_hdl, OID_RT_SET_BANDWIDTH) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_antenna_bb_hdl, OID_RT_PRO_SET_ANTENNA_BB) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_continuous_tx_hdl, OID_RT_PRO_SET_CONTINUOUS_TX) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_carrier_tx_hdl, OID_RT_PRO_SET_SINGLE_CARRIER_TX) ++/*15*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_carrier_suppression_tx_hdl, OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_tone_tx_hdl, OID_RT_PRO_SET_SINGLE_TONE_TX) ++ ++ EXT_MP_IOCTL_HANDLER(0, xmit_packet, 0) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_rx_packet_type_hdl, OID_RT_SET_RX_PACKET_TYPE) ++ GEN_MP_IOCTL_HANDLER(0, oid_rt_reset_phy_rx_packet_count_hdl, OID_RT_RESET_PHY_RX_PACKET_COUNT) ++/*20*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_received_hdl, OID_RT_GET_PHY_RX_PACKET_RECEIVED) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_crc32_error_hdl, OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) ++ GEN_MP_IOCTL_HANDLER(sizeof(EFUSE_ACCESS_STRUCT), oid_rt_pro_efuse_hdl, OID_RT_PRO_EFUSE) ++/*25*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_efuse_map_hdl, OID_RT_PRO_EFUSE_MAP) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_max_size_hdl, OID_RT_GET_EFUSE_MAX_SIZE) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_current_size_hdl, OID_RT_GET_EFUSE_CURRENT_SIZE) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_thermal_meter_hdl, OID_RT_PRO_GET_THERMAL_METER) ++ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_pro_set_power_tracking_hdl, OID_RT_PRO_SET_POWER_TRACKING) ++/*30*/ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_set_power_down_hdl, OID_RT_SET_POWER_DOWN) ++/*31*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_trigger_gpio_hdl, 0) ++ ++ ++}; ++ ++#else /* _RTW_MP_IOCTL_C_ */ ++ ++extern struct mp_ioctl_handler mp_ioctl_hdl[]; ++ ++#endif /* _RTW_MP_IOCTL_C_ */ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_phy_regdef.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_phy_regdef.h +new file mode 100644 +index 00000000..0f8df412 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_mp_phy_regdef.h +@@ -0,0 +1,1099 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __RTW_MP_PHY_REGDEF_H_ ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __RTW_MP_PHY_REGDEF_H_ ++#define __RTW_MP_PHY_REGDEF_H_ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++//#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++//#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++//#define rFPGA0_XC_RFTiming 0x818 ++//#define rFPGA0_XD_RFTiming 0x81c ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++#define rFPGA0_XC_HSSIParameter1 0x830 ++#define rFPGA0_XC_HSSIParameter2 0x834 ++#define rFPGA0_XD_HSSIParameter1 0x838 ++#define rFPGA0_XD_HSSIParameter2 0x83c ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++#define rFPGA0_XC_LSSIParameter 0x848 ++#define rFPGA0_XD_LSSIParameter 0x84c ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++#define rFPGA0_XC_RFInterfaceOE 0x868 ++#define rFPGA0_XD_RFInterfaceOE 0x86c ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 // Useless now ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++#define rOFDM0_RxIQExtAnta 0xca0 ++ ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++ ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_csi_fix_mask 0xd40 ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_Rate18_06 0xe00 ++#define rTxAGC_Rate54_24 0xe04 ++#define rTxAGC_CCK_Mcs32 0xe08 ++#define rTxAGC_Mcs03_Mcs00 0xe10 ++#define rTxAGC_Mcs07_Mcs04 0xe14 ++#define rTxAGC_Mcs11_Mcs08 0xe18 ++#define rTxAGC_Mcs15_Mcs12 0xe1c ++ ++// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] ++#define rRx_Wait_CCCA 0xe70 ++#define rAnapar_Ctrl_BB 0xee0 ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define RTL92SE_FPGA_VERIFY 0 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++//#if (RTL92SE_FPGA_VERIFY == 1) ++#define rZebra1_Channel 0x7 // RF channel switch ++//#else ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_TXBIAS 0x16 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x24 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++#if (RTL92SE_FPGA_VERIFY == 1) ++#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 ++#else ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++#endif ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++#if (RTL92SE_FPGA_VERIFY == 1) ++#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack ++#else ++#define bLSSIReadBackData 0xfffff // T65 RF ++#endif ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++#define bTxAGCRate18_06 0x7f7f7f7f // Useless ++#define bTxAGCRate54_24 0x7f7f7f7f ++#define bTxAGCRateMCS32 0x7f ++#define bTxAGCRateCCK 0x7f00 ++#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f ++#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f ++#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f ++#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++#define bMask12Bits 0xfff ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++#if (RTL92SE_FPGA_VERIFY == 1) ++//#define bMask12Bits 0xfff // RF Reg mask bits ++//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfff ++#else ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++#endif ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#if 0 ++#define ANTENNA_A 0x1 // Useless ++#define ANTENNA_B 0x2 ++#define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B ++ ++#define ANTENNA_C 0x4 ++#define ANTENNA_D 0x8 ++#endif ++ ++#define RCR_AAP BIT(0) // accept all physical address ++#define RCR_APM BIT(1) // accept physical match ++#define RCR_AM BIT(2) // accept multicast ++#define RCR_AB BIT(3) // accept broadcast ++#define RCR_ACRC32 BIT(5) // accept error packet ++#define RCR_9356SEL BIT(6) ++#define RCR_AICV BIT(12) // Accept ICV error packet ++#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold ++#define RCR_ADF BIT(18) // Accept Data(frame type) frame ++#define RCR_ACF BIT(19) // Accept control frame ++#define RCR_AMF BIT(20) // Accept management frame ++#define RCR_ADD3 BIT(21) ++#define RCR_APWRMGT BIT(22) // Accept power management packet ++#define RCR_CBSSID BIT(23) // Accept BSSID match packet ++#define RCR_ENMARP BIT(28) // enable mac auto reset phy ++#define RCR_EnCS1 BIT(29) // enable carrier sense method 1 ++#define RCR_EnCS2 BIT(30) // enable carrier sense method 2 ++#define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_odm.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_odm.h +new file mode 100644 +index 00000000..d01acd64 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_odm.h +@@ -0,0 +1,42 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2013 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_ODM_H__ ++#define __RTW_ODM_H__ ++ ++#include ++ ++/* ++* This file provides utilities/wrappers for rtw driver to use ODM ++*/ ++ ++int _rtw_odm_dbg_comp_msg(_adapter *adapter, char *buf, int len); ++void rtw_odm_dbg_comp_msg(_adapter *adapter); ++void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps); ++int _rtw_odm_dbg_level_msg(_adapter *adapter, char *buf, int len); ++void rtw_odm_dbg_level_msg(_adapter *adapter); ++void rtw_odm_dbg_level_set(_adapter *adapter, u32 level); ++ ++int _rtw_odm_adaptivity_parm_msg(_adapter *adapter, char *buf, int len); ++void rtw_odm_adaptivity_parm_msg(_adapter *adapter); ++void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, ++ s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound); ++ ++#endif // __RTW_ODM_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_p2p.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_p2p.h +new file mode 100644 +index 00000000..4249bc96 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_p2p.h +@@ -0,0 +1,161 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_P2P_H_ ++#define __RTW_P2P_H_ ++ ++#include ++ ++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ); ++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); ++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++#ifdef CONFIG_WFD ++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled); ++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++#endif //CONFIG_WFD ++ ++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); ++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe); ++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++ ++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType); ++ ++#ifdef CONFIG_P2P_PS ++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); ++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); ++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue); ++#endif // CONFIG_P2P_PS ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter); ++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); ++void rtw_append_wfd_ie(_adapter *padapter, u8 *buf, u32 *len); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++void reset_global_wifidirect_info( _adapter* padapter ); ++int rtw_init_wifi_display_info(_adapter* padapter); ++void rtw_init_wifidirect_timers(_adapter* padapter); ++void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr); ++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role); ++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role); ++ ++static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ if(wdinfo->p2p_state != state) { ++ //wdinfo->pre_p2p_state = wdinfo->p2p_state; ++ wdinfo->p2p_state = state; ++ } ++} ++static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ if(wdinfo->pre_p2p_state != state) { ++ wdinfo->pre_p2p_state = state; ++ } ++} ++#if 0 ++static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo) ++{ ++ if(wdinfo->pre_p2p_state != -1) { ++ wdinfo->p2p_state = wdinfo->pre_p2p_state; ++ wdinfo->pre_p2p_state = -1; ++ } ++} ++#endif ++static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) ++{ ++ if(wdinfo->role != role) { ++ wdinfo->role = role; ++ } ++} ++static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->p2p_state; ++} ++static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->pre_p2p_state; ++} ++static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->role; ++} ++static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ return wdinfo->p2p_state == state; ++} ++static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) ++{ ++ return wdinfo->role == role; ++} ++ ++#ifdef CONFIG_DBG_P2P ++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); ++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); ++//void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); ++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); ++#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) ++#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) ++#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) ++//#define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) ++#else //CONFIG_DBG_P2P ++#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) ++#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) ++#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) ++//#define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) ++#endif //CONFIG_DBG_P2P ++ ++#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) ++#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) ++#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) ++#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) ++#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) ++ ++#define rtw_p2p_findphase_ex_set(wdinfo, value) \ ++ (wdinfo)->find_phase_state_exchange_cnt = (value) ++ ++//is this find phase exchange for social channel scan? ++#define rtw_p2p_findphase_ex_is_social(wdinfo) \ ++ (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST ++ ++//should we need find phase exchange anymore? ++#define rtw_p2p_findphase_ex_is_needed(wdinfo) \ ++ ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ ++ (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE) ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_pwrctrl.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_pwrctrl.h +new file mode 100644 +index 00000000..4b63a1e0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_pwrctrl.h +@@ -0,0 +1,384 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_PWRCTRL_H_ ++#define __RTW_PWRCTRL_H_ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_HAS_EARLYSUSPEND ++#include ++#endif //CONFIG_HAS_EARLYSUSPEND ++ ++ ++#define FW_PWR0 0 ++#define FW_PWR1 1 ++#define FW_PWR2 2 ++#define FW_PWR3 3 ++ ++ ++#define HW_PWR0 7 ++#define HW_PWR1 6 ++#define HW_PWR2 2 ++#define HW_PWR3 0 ++#define HW_PWR4 8 ++ ++#define FW_PWRMSK 0x7 ++ ++ ++#define XMIT_ALIVE BIT(0) ++#define RECV_ALIVE BIT(1) ++#define CMD_ALIVE BIT(2) ++#define EVT_ALIVE BIT(3) ++ ++ ++enum Power_Mgnt ++{ ++ PS_MODE_ACTIVE = 0 , ++ PS_MODE_MIN , ++ PS_MODE_MAX , ++ PS_MODE_DTIM , ++ PS_MODE_VOIP , ++ PS_MODE_UAPSD_WMM , ++ PS_MODE_UAPSD , ++ PS_MODE_IBSS , ++ PS_MODE_WWLAN , ++ PM_Radio_Off , ++ PM_Card_Disable , ++ PS_MODE_NUM ++}; ++ ++ ++/* ++ BIT[2:0] = HW state ++ BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state ++ BIT[4] = sub-state ++*/ ++ ++#define PS_DPS BIT(0) ++#define PS_LCLK (PS_DPS) ++#define PS_RF_OFF BIT(1) ++#define PS_ALL_ON BIT(2) ++#define PS_ST_ACTIVE BIT(3) ++ ++#define PS_ISR_ENABLE BIT(4) ++#define PS_IMR_ENABLE BIT(5) ++#define PS_ACK BIT(6) ++#define PS_TOGGLE BIT(7) ++ ++#define PS_STATE_MASK (0x0F) ++#define PS_STATE_HW_MASK (0x07) ++#define PS_SEQ_MASK (0xc0) ++ ++#define PS_STATE(x) (PS_STATE_MASK & (x)) ++#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) ++#define PS_SEQ(x) (PS_SEQ_MASK & (x)) ++ ++#define PS_STATE_S0 (PS_DPS) ++#define PS_STATE_S1 (PS_LCLK) ++#define PS_STATE_S2 (PS_RF_OFF) ++#define PS_STATE_S3 (PS_ALL_ON) ++#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) ++ ++ ++#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) ++#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) ++#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) ++ ++ ++struct reportpwrstate_parm { ++ unsigned char mode; ++ unsigned char state; //the CPWM value ++ unsigned short rsvd; ++}; ++ ++ ++typedef _sema _pwrlock; ++ ++ ++__inline static void _init_pwrlock(_pwrlock *plock) ++{ ++ _rtw_init_sema(plock, 1); ++} ++ ++__inline static void _free_pwrlock(_pwrlock *plock) ++{ ++ _rtw_free_sema(plock); ++} ++ ++ ++__inline static void _enter_pwrlock(_pwrlock *plock) ++{ ++ _rtw_down_sema(plock); ++} ++ ++ ++__inline static void _exit_pwrlock(_pwrlock *plock) ++{ ++ _rtw_up_sema(plock); ++} ++ ++#define LPS_DELAY_TIME 1*HZ // 1 sec ++ ++#define EXE_PWR_NONE 0x01 ++#define EXE_PWR_IPS 0x02 ++#define EXE_PWR_LPS 0x04 ++ ++// RF state. ++typedef enum _rt_rf_power_state ++{ ++ rf_on, // RF is on after RFSleep or RFOff ++ rf_sleep, // 802.11 Power Save mode ++ rf_off, // HW/SW Radio OFF or Inactive Power Save ++ //=====Add the new RF state above this line=====// ++ rf_max ++}rt_rf_power_state; ++ ++// RF Off Level for IPS or HW/SW radio off ++#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM ++#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request ++#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode ++#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters ++#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW ++#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k ++#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization. ++#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd. ++#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM ++ ++#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE) ++#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) ++#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG) ++ ++ ++enum _PS_BBRegBackup_ { ++ PSBBREG_RF0 = 0, ++ PSBBREG_RF1, ++ PSBBREG_RF2, ++ PSBBREG_AFE0, ++ PSBBREG_TOTALCNT ++}; ++ ++enum { // for ips_mode ++ IPS_NONE=0, ++ IPS_NORMAL, ++ IPS_LEVEL_2, ++}; ++ ++struct pwrctrl_priv ++{ ++ _pwrlock lock; ++ volatile u8 rpwm; // requested power state for fw ++ volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level ++ volatile u8 tog; // toggling ++ volatile u8 cpwm_tog; // toggling ++ ++ u8 pwr_mode; ++ u8 smart_ps; ++ u8 bcn_ant_mode; ++ ++ u32 alives; ++ _workitem cpwm_event; ++#ifdef CONFIG_LPS_RPWM_TIMER ++ u8 brpwmtimeout; ++ _workitem rpwmtimeoutwi; ++ _timer pwr_rpwm_timer; ++#endif // CONFIG_LPS_RPWM_TIMER ++ u8 bpower_saving; ++ ++ u8 b_hw_radio_off; ++ u8 reg_rfoff; ++ u8 reg_pdnmode; //powerdown mode ++ u32 rfoff_reason; ++ ++ //RF OFF Level ++ u32 cur_ps_level; ++ u32 reg_rfps_level; ++ ++ ++ ++#ifdef CONFIG_PCI_HCI ++ //just for PCIE ASPM ++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. ++ u8 b_support_backdoor; ++ ++ //just for PCIE ASPM ++ u8 const_amdpci_aspm; ++#endif ++ ++ uint ips_enter_cnts; ++ uint ips_leave_cnts; ++ ++ u8 ips_mode; ++ u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later ++ uint bips_processing; ++ u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ ++ u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */ ++ ++ u8 bLeisurePs; ++ u8 LpsIdleCount; ++ u8 power_mgnt; ++ u8 bFwCurrentInPSMode; ++ u32 DelayLPSLastTimeStamp; ++ u8 btcoex_rfon; ++ s32 pnp_current_pwr_state; ++ u8 pnp_bstop_trx; ++ ++ ++ u8 bInternalAutoSuspend; ++ u8 bInSuspend; ++#ifdef CONFIG_BT_COEXIST ++ u8 bAutoResume; ++ u8 autopm_cnt; ++#endif ++ u8 bSupportRemoteWakeup; ++#ifdef CONFIG_WOWLAN ++ u8 wowlan_mode; ++ u8 wowlan_pattern; ++ u8 wowlan_magic; ++ u8 wowlan_unicast; ++ u8 wowlan_pattern_idx; ++ u8 wowlan_wake_reason; ++ u32 wowlan_pattern_context[8][5]; ++ u64 wowlan_fw_iv; ++#endif // CONFIG_WOWLAN ++ _timer pwr_state_check_timer; ++ int pwr_state_check_interval; ++ u8 pwr_state_check_cnts; ++ ++ int ps_flag; ++ ++ rt_rf_power_state rf_pwrstate;//cur power state ++ //rt_rf_power_state current_rfpwrstate; ++ rt_rf_power_state change_rfpwrstate; ++ ++ u8 bHWPowerdown;//if support hw power down ++ u8 bHWPwrPindetect; ++ u8 bkeepfwalive; ++ u8 brfoffbyhw; ++ unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ struct workqueue_struct *rtw_workqueue; ++ _workitem resume_work; ++ #endif ++ ++ #ifdef CONFIG_HAS_EARLYSUSPEND ++ struct early_suspend early_suspend; ++ u8 do_late_resume; ++ #endif //CONFIG_HAS_EARLYSUSPEND ++ ++ #ifdef CONFIG_ANDROID_POWER ++ android_early_suspend_t early_suspend; ++ u8 do_late_resume; ++ #endif ++ ++ #ifdef CONFIG_INTEL_PROXIM ++ u8 stored_power_mgnt; ++ #endif ++}; ++ ++#define rtw_get_ips_mode_req(pwrctl) \ ++ (pwrctl)->ips_mode_req ++ ++#define rtw_ips_mode_req(pwrctl, ips_mode) \ ++ (pwrctl)->ips_mode_req = (ips_mode) ++ ++#define RTW_PWR_STATE_CHK_INTERVAL 2000 ++ ++#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \ ++ do { \ ++ /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \ ++ _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \ ++ } while(0) ++ ++#define rtw_set_pwr_state_check_timer(pwrctl) \ ++ _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval) ++ ++extern void rtw_init_pwrctrl_priv(_adapter *adapter); ++extern void rtw_free_pwrctrl_priv(_adapter * adapter); ++ ++#ifdef CONFIG_LPS_LCLK ++extern s32 rtw_register_tx_alive(PADAPTER padapter); ++extern void rtw_unregister_tx_alive(PADAPTER padapter); ++extern s32 rtw_register_rx_alive(PADAPTER padapter); ++extern void rtw_unregister_rx_alive(PADAPTER padapter); ++extern s32 rtw_register_cmd_alive(PADAPTER padapter); ++extern void rtw_unregister_cmd_alive(PADAPTER padapter); ++extern s32 rtw_register_evt_alive(PADAPTER padapter); ++extern void rtw_unregister_evt_alive(PADAPTER padapter); ++extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); ++extern void LPS_Leave_check(PADAPTER padapter); ++#endif ++ ++extern void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode); ++extern void rtw_set_rpwm(_adapter * padapter, u8 val8); ++extern void LeaveAllPowerSaveMode(PADAPTER Adapter); ++#ifdef CONFIG_IPS ++void _ips_enter(_adapter * padapter); ++void ips_enter(_adapter * padapter); ++int _ips_leave(_adapter * padapter); ++int ips_leave(_adapter * padapter); ++#endif ++ ++void rtw_ps_processor(_adapter*padapter); ++ ++#ifdef CONFIG_AUTOSUSPEND ++int autoresume_enter(_adapter* padapter); ++#endif ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ); ++#endif ++ ++ ++#ifdef CONFIG_LPS ++s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); ++void LPS_Enter(PADAPTER padapter); ++void LPS_Leave(PADAPTER padapter); ++#endif ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) ++bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv); ++bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv); ++void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable); ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); ++#else ++#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE ++#define rtw_is_do_late_resume(pwrpriv) _FALSE ++#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0) ++#define rtw_register_early_suspend(pwrpriv) do {} while (0) ++#define rtw_unregister_early_suspend(pwrpriv) do {} while (0) ++#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ ++ ++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val); ++void rtw_set_ips_deny(_adapter *padapter, u32 ms); ++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); ++#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__) ++#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__) ++int rtw_pm_set_ips(_adapter *padapter, u8 mode); ++int rtw_pm_set_lps(_adapter *padapter, u8 mode); ++ ++#endif //__RTL871X_PWRCTRL_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_qos.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_qos.h +new file mode 100644 +index 00000000..a359c5fe +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_qos.h +@@ -0,0 +1,40 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef _RTW_QOS_H_ ++#define _RTW_QOS_H_ ++#include ++#include ++ ++ ++ ++ ++ ++ ++struct qos_priv { ++ ++ unsigned int qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack... ++ ++}; ++ ++ ++#endif //_RTL871X_QOS_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_recv.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_recv.h +new file mode 100644 +index 00000000..97ffea34 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_recv.h +@@ -0,0 +1,758 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_RECV_H_ ++#define _RTW_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#define NR_RECVFRAME 256 ++ ++#define RXFRAME_ALIGN 8 ++#define RXFRAME_ALIGN_SZ (1<signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++struct sta_recv_priv { ++ ++ _lock lock; ++ sint option; ++ ++ //_queue blk_strms[MAX_RX_NUMBLKS]; ++ _queue defrag_q; //keeping the fragment frame until defrag ++ ++ struct stainfo_rxcache rxcache; ++ ++ //uint sta_rx_bytes; ++ //uint sta_rx_pkts; ++ //uint sta_rx_fail; ++ ++}; ++ ++ ++struct recv_buf ++{ ++ _list list; ++ ++ _lock recvbuf_lock; ++ ++ u32 ref_cnt; ++ ++ PADAPTER adapter; ++ ++ u8 *pbuf; ++ u8 *pallocated_buf; ++ ++ u32 len; ++ u8 *phead; ++ u8 *pdata; ++ u8 *ptail; ++ u8 *pend; ++ ++#ifdef CONFIG_USB_HCI ++ ++ #if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX)||defined(PLATFORM_FREEBSD) ++ PURB purb; ++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ ++ u32 alloc_sz; ++ #endif ++ ++ #ifdef PLATFORM_OS_XP ++ PIRP pirp; ++ #endif ++ ++ #ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_read_port; ++ #endif ++ ++ u8 irp_pending; ++ int transfer_len; ++ ++#endif ++ ++#ifdef PLATFORM_LINUX ++ _pkt *pskb; ++ u8 reuse; ++#endif ++#ifdef PLATFORM_FREEBSD //skb solution ++ struct sk_buff *pskb; ++ u8 reuse; ++#endif //PLATFORM_FREEBSD //skb solution ++}; ++ ++ ++/* ++ head -----> ++ ++ data -----> ++ ++ payload ++ ++ tail -----> ++ ++ ++ end -----> ++ ++ len = (unsigned int )(tail - data); ++ ++*/ ++struct recv_frame_hdr ++{ ++ _list list; ++#ifndef CONFIG_BSD_RX_USE_MBUF ++ struct sk_buff *pkt; ++ struct sk_buff *pkt_newalloc; ++#else // CONFIG_BSD_RX_USE_MBUF ++ _pkt *pkt; ++ _pkt *pkt_newalloc; ++#endif // CONFIG_BSD_RX_USE_MBUF ++ ++ _adapter *adapter; ++ ++ u8 fragcnt; ++ ++ int frame_tag; ++ ++ struct rx_pkt_attrib attrib; ++ ++ uint len; ++ u8 *rx_head; ++ u8 *rx_data; ++ u8 *rx_tail; ++ u8 *rx_end; ++ ++ void *precvbuf; ++ ++ ++ // ++ struct sta_info *psta; ++ ++ //for A-MPDU Rx reordering buffer control ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ u8 UserPriority; ++ u8 WapiTempPN[16]; ++ u8 WapiSrcAddr[6]; ++ u8 bWapiCheckPNInDecrypt; ++ u8 bIsWaiPacket; ++#endif ++ ++}; ++ ++ ++union recv_frame{ ++ ++ union{ ++ _list list; ++ struct recv_frame_hdr hdr; ++ uint mem[RECVFRAME_HDR_ALIGN>>2]; ++ }u; ++ ++ //uint mem[MAX_RXSZ>>2]; ++ ++}; ++ ++ ++extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue ++extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue ++extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv); ++extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); ++ ++#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) ++extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); ++extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); ++ ++extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); ++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter); ++ ++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); ++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); ++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue); ++ ++void rtw_reordering_ctrl_timeout_handler(void *pcontext); ++ ++__inline static u8 *get_rxmem(union recv_frame *precvframe) ++{ ++ //always return rx_head... ++ if(precvframe==NULL) ++ return NULL; ++ ++ return precvframe->u.hdr.rx_head; ++} ++ ++__inline static u8 *get_rx_status(union recv_frame *precvframe) ++{ ++ ++ return get_rxmem(precvframe); ++ ++} ++ ++__inline static u8 *get_recvframe_data(union recv_frame *precvframe) ++{ ++ ++ //alwasy return rx_data ++ if(precvframe==NULL) ++ return NULL; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) ++{ ++ // append data before rx_data ++ ++ /* add data to the start of recv_frame ++ * ++ * This function extends the used data area of the recv_frame at the buffer ++ * start. rx_data must be still larger than rx_head, after pushing. ++ */ ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ ++ precvframe->u.hdr.rx_data -= sz ; ++ if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head ) ++ { ++ precvframe->u.hdr.rx_data += sz ; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len +=sz; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++ ++__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) ++{ ++ // rx_data += sz; move rx_data sz bytes hereafter ++ ++ //used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller ++ ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ ++ precvframe->u.hdr.rx_data += sz; ++ ++ if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) ++ { ++ precvframe->u.hdr.rx_data -= sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len -=sz; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) ++{ ++ // rx_tai += sz; move rx_tail sz bytes hereafter ++ ++ //used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller ++ //after putting, rx_tail must be still larger than rx_end. ++ unsigned char * prev_rx_tail; ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ prev_rx_tail = precvframe->u.hdr.rx_tail; ++ ++ precvframe->u.hdr.rx_tail += sz; ++ ++ if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) ++ { ++ precvframe->u.hdr.rx_tail -= sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len +=sz; ++ ++ return precvframe->u.hdr.rx_tail; ++ ++} ++ ++ ++ ++__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) ++{ ++ // rmv data from rx_tail (by yitsen) ++ ++ //used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller ++ //after pulling, rx_end must be still larger than rx_data. ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ precvframe->u.hdr.rx_tail -= sz; ++ ++ if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) ++ { ++ precvframe->u.hdr.rx_tail += sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len -=sz; ++ ++ return precvframe->u.hdr.rx_tail; ++ ++} ++ ++ ++ ++__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe) ++{ ++ _buffer * buf_desc; ++ ++ if(precvframe==NULL) ++ return NULL; ++#ifdef PLATFORM_WINDOWS ++ NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL); ++#endif ++ ++ return buf_desc; ++} ++ ++ ++__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) ++{ ++ //due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame ++ //from any given member of recv_frame. ++ // rxmem indicates the any member/address in recv_frame ++ ++ return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); ++ ++} ++ ++__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt) ++{ ++ ++ u8 * buf_star; ++ union recv_frame * precv_frame; ++#ifdef PLATFORM_WINDOWS ++ _buffer * buf_desc; ++ uint len; ++ ++ NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len); ++ NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority); ++#endif ++ precv_frame = rxmem_to_recvframe((unsigned char*)buf_star); ++ ++ return precv_frame; ++} ++ ++__inline static u8 *pkt_to_recvmem(_pkt *pkt) ++{ ++ // return the rx_head ++ ++ union recv_frame * precv_frame = pkt_to_recvframe(pkt); ++ ++ return precv_frame->u.hdr.rx_head; ++ ++} ++ ++__inline static u8 *pkt_to_recvdata(_pkt *pkt) ++{ ++ // return the rx_data ++ ++ union recv_frame * precv_frame =pkt_to_recvframe(pkt); ++ ++ return precv_frame->u.hdr.rx_data; ++ ++} ++ ++ ++__inline static sint get_recvframe_len(union recv_frame *precvframe) ++{ ++ return precvframe->u.hdr.len; ++} ++ ++ ++__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) ++{ ++ s32 SignalPower; // in dBm. ++ ++ // Translate to dBm (x=0.5y-95). ++ SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); ++ SignalPower -= 95; ++ ++ return SignalPower; ++} ++ ++ ++struct sta_info; ++ ++extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); ++ ++extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_rf.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_rf.h +new file mode 100644 +index 00000000..6ca44004 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_rf.h +@@ -0,0 +1,158 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_RF_H_ ++#define __RTW_RF_H_ ++ ++#include ++#include ++ ++#define OFDM_PHY 1 ++#define MIXED_PHY 2 ++#define CCK_PHY 3 ++ ++#define NumRates (13) ++ ++// slot time for 11g ++#define SHORT_SLOT_TIME 9 ++#define NON_SHORT_SLOT_TIME 20 ++ ++#define RTL8711_RF_MAX_SENS 6 ++#define RTL8711_RF_DEF_SENS 4 ++ ++// ++// We now define the following channels as the max channels in each channel plan. ++// 2G, total 14 chnls ++// {1,2,3,4,5,6,7,8,9,10,11,12,13,14} ++// 5G, total 24 chnls ++// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} ++#define MAX_CHANNEL_NUM_2G 14 ++#define MAX_CHANNEL_NUM_5G 24 ++#define MAX_CHANNEL_NUM 38//14+24 ++ ++//#define NUM_REGULATORYS 21 ++#define NUM_REGULATORYS 1 ++ ++//Country codes ++#define USA 0x555320 ++#define EUROPE 0x1 //temp, should be provided later ++#define JAPAN 0x2 //temp, should be provided later ++ ++struct regulatory_class { ++ u32 starting_freq; //MHz, ++ u8 channel_set[MAX_CHANNEL_NUM]; ++ u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm ++ u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm ++ u8 txpower_limit; //dbm ++ u8 channel_spacing; //MHz ++ u8 modem; ++}; ++ ++typedef enum _CAPABILITY{ ++ cESS = 0x0001, ++ cIBSS = 0x0002, ++ cPollable = 0x0004, ++ cPollReq = 0x0008, ++ cPrivacy = 0x0010, ++ cShortPreamble = 0x0020, ++ cPBCC = 0x0040, ++ cChannelAgility = 0x0080, ++ cSpectrumMgnt = 0x0100, ++ cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq ++ cShortSlotTime = 0x0400, ++ cAPSD = 0x0800, ++ cRM = 0x1000, // RRM (Radio Request Measurement) ++ cDSSS_OFDM = 0x2000, ++ cDelayedBA = 0x4000, ++ cImmediateBA = 0x8000, ++}CAPABILITY, *PCAPABILITY; ++ ++enum _REG_PREAMBLE_MODE{ ++ PREAMBLE_LONG = 1, ++ PREAMBLE_AUTO = 2, ++ PREAMBLE_SHORT = 3, ++}; ++ ++ ++enum _RTL8712_RF_MIMO_CONFIG_{ ++ RTL8712_RFCONFIG_1T=0x10, ++ RTL8712_RFCONFIG_2T=0x20, ++ RTL8712_RFCONFIG_1R=0x01, ++ RTL8712_RFCONFIG_2R=0x02, ++ RTL8712_RFCONFIG_1T1R=0x11, ++ RTL8712_RFCONFIG_1T2R=0x12, ++ RTL8712_RFCONFIG_TURBO=0x92, ++ RTL8712_RFCONFIG_2T2R=0x22 ++}; ++ ++ ++typedef enum _RF90_RADIO_PATH{ ++ RF90_PATH_A = 0, //Radio Path A ++ RF90_PATH_B = 1, //Radio Path B ++ RF90_PATH_C = 2, //Radio Path C ++ RF90_PATH_D = 3 //Radio Path D ++ //RF90_PATH_MAX //Max RF number 90 support ++}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; ++ ++// Bandwidth Offset ++#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 ++#define HAL_PRIME_CHNL_OFFSET_LOWER 1 ++#define HAL_PRIME_CHNL_OFFSET_UPPER 2 ++ ++// Represent Channel Width in HT Capabilities ++// ++typedef enum _HT_CHANNEL_WIDTH { ++ ++ HT_CHANNEL_WIDTH_20 = 0, ++ HT_CHANNEL_WIDTH_40 = 1, ++ HT_CHANNEL_WIDTH_80 = 2, ++ HT_CHANNEL_WIDTH_160 = 3, ++ HT_CHANNEL_WIDTH_10 = 4, ++ ++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; ++ ++// ++// Represent Extention Channel Offset in HT Capabilities ++// This is available only in 40Mhz mode. ++// ++typedef enum _HT_EXTCHNL_OFFSET{ ++ HT_EXTCHNL_OFFSET_NO_EXT = 0, ++ HT_EXTCHNL_OFFSET_UPPER = 1, ++ HT_EXTCHNL_OFFSET_NO_DEF = 2, ++ HT_EXTCHNL_OFFSET_LOWER = 3, ++}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET; ++ ++/* 2007/11/15 MH Define different RF type. */ ++typedef enum _RT_RF_TYPE_DEFINITION ++{ ++ RF_1T2R = 0, ++ RF_2T4R = 1, ++ RF_2T2R = 2, ++ RF_1T1R = 3, ++ RF_2T2R_GREEN = 4, ++ RF_819X_MAX_TYPE = 5, ++}RT_RF_TYPE_DEF_E; ++ ++ ++u32 rtw_ch2freq(u32 ch); ++u32 rtw_freq2ch(u32 freq); ++ ++ ++#endif //_RTL8711_RF_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_security.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_security.h +new file mode 100644 +index 00000000..730857c2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_security.h +@@ -0,0 +1,466 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_SECURITY_H_ ++#define __RTW_SECURITY_H_ ++ ++ ++#include ++#include ++#include ++ ++ ++#define _NO_PRIVACY_ 0x0 ++#define _WEP40_ 0x1 ++#define _TKIP_ 0x2 ++#define _TKIP_WTMIC_ 0x3 ++#define _AES_ 0x4 ++#define _WEP104_ 0x5 ++#define _WEP_WPA_MIXED_ 0x07 // WEP + WPA ++#define _SMS4_ 0x06 ++#ifdef CONFIG_IEEE80211W ++#define _BIP_ 0x8 ++#endif //CONFIG_IEEE80211W ++#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) ++ ++#define _WPA_IE_ID_ 0xdd ++#define _WPA2_IE_ID_ 0x30 ++ ++#define SHA256_MAC_LEN 32 ++#define AES_BLOCK_SIZE 16 ++#define AES_PRIV_SIZE (4 * 44) ++ ++typedef enum { ++ ENCRYP_PROTOCOL_OPENSYS, //open system ++ ENCRYP_PROTOCOL_WEP, //WEP ++ ENCRYP_PROTOCOL_WPA, //WPA ++ ENCRYP_PROTOCOL_WPA2, //WPA2 ++ ENCRYP_PROTOCOL_WAPI, //WAPI: Not support in this version ++ ENCRYP_PROTOCOL_MAX ++}ENCRYP_PROTOCOL_E; ++ ++ ++#ifndef Ndis802_11AuthModeWPA2 ++#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) ++#endif ++ ++#ifndef Ndis802_11AuthModeWPA2PSK ++#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) ++#endif ++ ++union pn48 { ++ ++ u64 val; ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++struct { ++ u8 TSC0; ++ u8 TSC1; ++ u8 TSC2; ++ u8 TSC3; ++ u8 TSC4; ++ u8 TSC5; ++ u8 TSC6; ++ u8 TSC7; ++} _byte_; ++ ++#elif defined(CONFIG_BIG_ENDIAN) ++ ++struct { ++ u8 TSC7; ++ u8 TSC6; ++ u8 TSC5; ++ u8 TSC4; ++ u8 TSC3; ++ u8 TSC2; ++ u8 TSC1; ++ u8 TSC0; ++} _byte_; ++ ++#endif ++ ++}; ++ ++union Keytype { ++ u8 skey[16]; ++ u32 lkey[4]; ++}; ++ ++ ++typedef struct _RT_PMKID_LIST ++{ ++ u8 bUsed; ++ u8 Bssid[6]; ++ u8 PMKID[16]; ++ u8 SsidBuf[33]; ++ u8* ssid_octet; ++ u16 ssid_length; ++} RT_PMKID_LIST, *PRT_PMKID_LIST; ++ ++ ++struct security_priv ++{ ++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch ++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. ++ ++ /* WEP */ ++ u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index) ++ union Keytype dot11DefKey[4]; // this is only valid for def. key ++ u32 dot11DefKeylen[4]; ++ u8 key_mask; /* use to restore wep key after hal_init */ ++ ++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key ++ u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index) ++ union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1 ++ union Keytype dot118021XGrptxmickey[4]; ++ union Keytype dot118021XGrprxmickey[4]; ++ union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit. ++ union pn48 dot11Grprxpn; // PN48 used for Grp Key recv. ++#ifdef CONFIG_IEEE80211W ++ u32 dot11wBIPKeyid; // key id used for BIP Key ( tx key index) ++ union Keytype dot11wBIPKey[6]; // BIP Key, for index4 and index5 ++ union pn48 dot11wBIPtxpn; // PN48 used for Grp Key xmit. ++ union pn48 dot11wBIPrxpn; // PN48 used for Grp Key recv. ++#endif //CONFIG_IEEE80211W ++#ifdef CONFIG_AP_MODE ++ //extend security capabilities for AP_MODE ++ unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x ++ unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 ++ unsigned int wpa_group_cipher; ++ unsigned int wpa2_group_cipher; ++ unsigned int wpa_pairwise_cipher; ++ unsigned int wpa2_pairwise_cipher; ++#endif ++ ++ u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req ++ int wps_ie_len; ++ ++ ++ u8 binstallGrpkey; ++#ifdef CONFIG_IEEE80211W ++ u8 binstallBIPkey; ++#endif //CONFIG_IEEE80211W ++ u8 busetkipkey; ++ //_timer tkip_timer; ++ u8 bcheck_grpkey; ++ u8 bgrpkey_handshake; ++ ++ //u8 packet_cnt;//unused, removed ++ ++ s32 sw_encrypt;//from registry_priv ++ s32 sw_decrypt;//from registry_priv ++ ++ s32 hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. ++ ++ ++ //keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) ++ u32 ndisauthtype; // NDIS_802_11_AUTHENTICATION_MODE ++ u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS ++ ++ WLAN_BSSID_EX sec_bss; //for joinbss (h2c buffer) usage ++ ++ NDIS_802_11_WEP ndiswep; ++#ifdef PLATFORM_WINDOWS ++ u8 KeyMaterial[16];// variable length depending on above field. ++#endif ++ ++ u8 assoc_info[600]; ++ u8 szofcapability[256]; //for wpa2 usage ++ u8 oidassociation[512]; //for wpa/wpa2 usage ++ u8 authenticator_ie[256]; //store ap security information element ++ u8 supplicant_ie[256]; //store sta security information element ++ ++ ++ //for tkip countermeasure ++ u32 last_mic_err_time; ++ u8 btkip_countermeasure; ++ u8 btkip_wait_report; ++ u32 btkip_countermeasure_time; ++ ++ //--------------------------------------------------------------------------- ++ // For WPA2 Pre-Authentication. ++ //--------------------------------------------------------------------------- ++ //u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. ++ //u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not. ++ RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. ++ u8 PMKIDIndex; ++ //u32 PMKIDCount; // Added by Annie, 2006-10-13. ++ //u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20. ++ ++ u8 bWepDefaultKeyIdxSet; ++}; ++ ++struct sha256_state { ++ u64 length; ++ u32 state[8], curlen; ++ u8 buf[64]; ++}; ++ ++#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ ++do{\ ++ switch(psecuritypriv->dot11AuthAlgrthm)\ ++ {\ ++ case dot11AuthAlgrthm_Open:\ ++ case dot11AuthAlgrthm_Shared:\ ++ case dot11AuthAlgrthm_Auto:\ ++ encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ ++ break;\ ++ case dot11AuthAlgrthm_8021X:\ ++ if(bmcst)\ ++ encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ ++ else\ ++ encry_algo =(u8) psta->dot118021XPrivacy;\ ++ break;\ ++ case dot11AuthAlgrthm_WAPI:\ ++ encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ ++ break;\ ++ }\ ++}while(0) ++ ++ ++#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\ ++do{\ ++ switch(encrypt)\ ++ {\ ++ case _WEP40_:\ ++ case _WEP104_:\ ++ iv_len = 4;\ ++ icv_len = 4;\ ++ break;\ ++ case _TKIP_:\ ++ iv_len = 8;\ ++ icv_len = 4;\ ++ break;\ ++ case _AES_:\ ++ iv_len = 8;\ ++ icv_len = 8;\ ++ break;\ ++ case _SMS4_:\ ++ iv_len = 18;\ ++ icv_len = 16;\ ++ break;\ ++ default:\ ++ iv_len = 0;\ ++ icv_len = 0;\ ++ break;\ ++ }\ ++}while(0) ++ ++ ++#define GET_TKIP_PN(iv,dot11txpn)\ ++do{\ ++ dot11txpn._byte_.TSC0=iv[2];\ ++ dot11txpn._byte_.TSC1=iv[0];\ ++ dot11txpn._byte_.TSC2=iv[4];\ ++ dot11txpn._byte_.TSC3=iv[5];\ ++ dot11txpn._byte_.TSC4=iv[6];\ ++ dot11txpn._byte_.TSC5=iv[7];\ ++}while(0) ++ ++ ++#define ROL32( A, n ) ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) ) ++#define ROR32( A, n ) ROL32( (A), 32-(n) ) ++ ++struct mic_data ++{ ++ u32 K0, K1; // Key ++ u32 L, R; // Current state ++ u32 M; // Message accumulator (single word) ++ u32 nBytesInM; // # bytes in M ++}; ++ ++extern const u32 Te0[256]; ++extern const u32 Te1[256]; ++extern const u32 Te2[256]; ++extern const u32 Te3[256]; ++extern const u32 Te4[256]; ++extern const u32 Td0[256]; ++extern const u32 Td1[256]; ++extern const u32 Td2[256]; ++extern const u32 Td3[256]; ++extern const u32 Td4[256]; ++extern const u32 rcon[10]; ++extern const u8 Td4s[256]; ++extern const u8 rcons[10]; ++ ++#define RCON(i) (rcons[(i)] << 24) ++ ++static inline u32 rotr(u32 val, int bits) ++{ ++ return (val >> bits) | (val << (32 - bits)); ++} ++ ++#define TE0(i) Te0[((i) >> 24) & 0xff] ++#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) ++#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) ++#define TE3(i) rotr(Te0[(i) & 0xff], 24) ++#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) ++#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) ++#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) ++#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) ++#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) ++#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) ++#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) ++#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) ++#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) ++ ++#define TD0(i) Td0[((i) >> 24) & 0xff] ++#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) ++#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) ++#define TD3(i) rotr(Td0[(i) & 0xff], 24) ++#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) ++#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) ++#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) ++#define TD44(i) (Td4s[(i) & 0xff]) ++#define TD0_(i) Td0[(i) & 0xff] ++#define TD1_(i) rotr(Td0[(i) & 0xff], 8) ++#define TD2_(i) rotr(Td0[(i) & 0xff], 16) ++#define TD3_(i) rotr(Td0[(i) & 0xff], 24) ++ ++#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ ++ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) ++ ++#define PUTU32(ct, st) { \ ++(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ ++(ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } ++ ++#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ ++ (((u32) (a)[2]) << 8) | ((u32) (a)[3])) ++ ++#define WPA_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define WPA_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define WPA_PUT_BE64(a, val) \ ++ do { \ ++ (a)[0] = (u8) (((u64) (val)) >> 56); \ ++ (a)[1] = (u8) (((u64) (val)) >> 48); \ ++ (a)[2] = (u8) (((u64) (val)) >> 40); \ ++ (a)[3] = (u8) (((u64) (val)) >> 32); \ ++ (a)[4] = (u8) (((u64) (val)) >> 24); \ ++ (a)[5] = (u8) (((u64) (val)) >> 16); \ ++ (a)[6] = (u8) (((u64) (val)) >> 8); \ ++ (a)[7] = (u8) (((u64) (val)) & 0xff); \ ++ } while (0) ++ ++/* ===== start - public domain SHA256 implementation ===== */ ++ ++/* This is based on SHA256 implementation in LibTomCrypt that was released into ++ * public domain by Tom St Denis. */ ++ ++/* the K array */ ++static const unsigned long K[64] = { ++ 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, ++ 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, ++ 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, ++ 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, ++ 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, ++ 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, ++ 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, ++ 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, ++ 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, ++ 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, ++ 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, ++ 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, ++ 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL ++}; ++ ++ ++/* Various logical functions */ ++#define RORc(x, y) \ ++( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ ++ ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) ++#define Ch(x,y,z) (z ^ (x & (y ^ z))) ++#define Maj(x,y,z) (((x | y) & z) | (x & y)) ++#define S(x, n) RORc((x), (n)) ++#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) ++#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) ++#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) ++#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) ++#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) ++#ifndef MIN ++#define MIN(x, y) (((x) < (y)) ? (x) : (y)) ++#endif ++#ifdef CONFIG_IEEE80211W ++int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); ++#endif //CONFIG_IEEE80211W ++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ); ++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ); ++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes ); ++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ); ++ ++void rtw_seccalctkipmic( ++ u8 * key, ++ u8 *header, ++ u8 *data, ++ u32 data_len, ++ u8 *Miccode, ++ u8 priority); ++ ++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe); ++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe); ++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe); ++ ++u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); ++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); ++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); ++#ifdef CONFIG_IEEE80211W ++u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); ++#endif //CONFIG_IEEE80211W ++#ifdef CONFIG_TDLS ++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta); ++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, ++ u8 *mic); ++int tdls_verify_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); ++#endif //CONFIG_TDLS ++ ++#ifdef PLATFORM_WINDOWS ++void rtw_use_tkipkey_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++#endif ++#ifdef PLATFORM_LINUX ++void rtw_use_tkipkey_handler(void* FunctionContext); ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++void rtw_use_tkipkey_handler(void* FunctionContext); ++#endif //PLATFORM_FREEBSD ++ ++void rtw_sec_restore_wep_key(_adapter *adapter); ++u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller); ++ ++#endif //__RTL871X_SECURITY_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_sreset.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_sreset.h +new file mode 100644 +index 00000000..45dd2bfb +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_sreset.h +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_SRESET_C_ ++#define _RTW_SRESET_C_ ++ ++#include ++#include ++#include ++ ++enum { ++ SRESET_TGP_NULL = 0, ++ SRESET_TGP_XMIT_STATUS = 1, ++ SRESET_TGP_LINK_STATUS = 2, ++}; ++ ++struct sreset_priv { ++ _mutex silentreset_mutex; ++ u8 silent_reset_inprogress; ++ u8 Wifi_Error_Status; ++ unsigned long last_tx_time; ++ unsigned long last_tx_complete_time; ++ ++ s32 dbg_trigger_point; ++}; ++ ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++ ++#define WIFI_STATUS_SUCCESS 0 ++#define USB_VEN_REQ_CMD_FAIL BIT0 ++#define USB_READ_PORT_FAIL BIT1 ++#define USB_WRITE_PORT_FAIL BIT2 ++#define WIFI_MAC_TXDMA_ERROR BIT3 ++#define WIFI_TX_HANG BIT4 ++#define WIFI_RX_HANG BIT5 ++#define WIFI_IF_NOT_EXIST BIT6 ++ ++void sreset_init_value(_adapter *padapter); ++void sreset_reset_value(_adapter *padapter); ++u8 sreset_get_wifi_status(_adapter *padapter); ++void sreset_set_wifi_error_status(_adapter *padapter, u32 status); ++void sreset_set_trigger_point(_adapter *padapter, s32 tgp); ++bool sreset_inprogress(_adapter *padapter); ++void sreset_reset(_adapter *padapter); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_tdls.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_tdls.h +new file mode 100644 +index 00000000..bc22cfee +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_tdls.h +@@ -0,0 +1,143 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_TDLS_H_ ++#define __RTW_TDLS_H_ ++ ++#include ++ ++#ifdef CONFIG_TDLS ++/* TDLS STA state */ ++#define TDLS_STATE_NONE 0x00000000 //default state ++#define TDLS_INITIATOR_STATE 0x10000000 ++#define TDLS_RESPONDER_STATE 0x20000000 ++#define TDLS_LINKED_STATE 0x40000000 ++#define TDLS_CH_SWITCH_ON_STATE 0x01000000 ++#define TDLS_PEER_AT_OFF_STATE 0x02000000 //could send pkt on target ch ++#define TDLS_AT_OFF_CH_STATE 0x04000000 ++#define TDLS_CH_SW_INITIATOR_STATE 0x08000000 //avoiding duplicated or unconditional ch. switch rsp. ++#define TDLS_APSD_CHSW_STATE 0x00100000 //in APSD and want to setup channel switch ++#define TDLS_PEER_SLEEP_STATE 0x00200000 //peer sta is sleeping ++#define TDLS_SW_OFF_STATE 0x00400000 //terminate channel swithcing ++#define TDLS_ALIVE_STATE 0x00010000 //Check if peer sta is alived. ++ ++#define TPK_RESEND_COUNT 301 ++#define CH_SWITCH_TIME 10 ++#define CH_SWITCH_TIMEOUT 30 ++#define TDLS_STAY_TIME 500 ++#define TDLS_SIGNAL_THRESH 0x20 ++#define TDLS_WATCHDOG_PERIOD 10 //Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec ++#define TDLS_ALIVE_TIMER_PH1 5000 ++#define TDLS_ALIVE_TIMER_PH2 2000 ++#define TDLS_STAY_TIME 500 ++#define TDLS_HANDSHAKE_TIME 8000 ++#define TDLS_ALIVE_COUNT 3 ++#define TDLS_INI_MACID_ENTRY 6 ++ ++/* TDLS */ ++#define TDLS_MIC_LEN 16 ++#define WPA_NONCE_LEN 32 ++#define TDLS_TIMEOUT_LEN 4 ++ ++struct wpa_tdls_ftie { ++ u8 ie_type; /* FTIE */ ++ u8 ie_len; ++ u8 mic_ctrl[2]; ++ u8 mic[TDLS_MIC_LEN]; ++ u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ ++ u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ ++ /* followed by optional elements */ ++} ; ++ ++struct wpa_tdls_lnkid { ++ u8 ie_type; /* Link Identifier IE */ ++ u8 ie_len; ++ u8 bssid[ETH_ALEN]; ++ u8 init_sta[ETH_ALEN]; ++ u8 resp_sta[ETH_ALEN]; ++} ; ++ ++static u8 TDLS_RSNIE[]={ 0x01, 0x00, //version shall be set to 1 ++ 0x00, 0x0f, 0xac, 0x07, //group sipher suite ++ 0x01, 0x00, //pairwise cipher suite count ++ 0x00, 0x0f, 0xac, 0x04, //pairwise cipher suite list; CCMP only ++ 0x01, 0x00, //AKM suite count ++ 0x00, 0x0f, 0xac, 0x07, //TPK Handshake ++ 0x00, 0x02, ++ //PMKID shall not be present ++ }; ++ ++static u8 TDLS_WMMIE[]={0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; //Qos info all set zero ++ ++static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20}; //bit(28), bit(30), bit(37) ++ ++// SRC: Supported Regulatory Classes ++static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 }; ++ ++void rtw_reset_tdls_info(_adapter* padapter); ++int rtw_init_tdls_info(_adapter* padapter); ++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo); ++void issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, struct sta_info *ptdls_sta, unsigned int power_mode); ++void init_TPK_timer(_adapter *padapter, struct sta_info *psta); ++void init_ch_switch_timer(_adapter *padapter, struct sta_info *psta); ++void init_base_ch_timer(_adapter *padapter, struct sta_info *psta); ++void init_off_ch_timer(_adapter *padapter, struct sta_info *psta); ++void init_tdls_alive_timer(_adapter *padapter, struct sta_info *psta); ++void init_handshake_timer(_adapter *padapter, struct sta_info *psta); ++void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta); ++#ifdef CONFIG_WFD ++void issue_tunneled_probe_req(_adapter *padapter); ++void issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame); ++#endif //CONFIG_WFD ++void issue_tdls_dis_req(_adapter *padapter, u8 *mac_addr); ++void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr); ++void issue_tdls_setup_rsp(_adapter *padapter, union recv_frame *precv_frame); ++void issue_tdls_setup_cfm(_adapter *padapter, union recv_frame *precv_frame); ++void issue_tdls_dis_rsp(_adapter * padapter, union recv_frame * precv_frame, u8 dialog); ++void issue_tdls_teardown(_adapter *padapter, u8 *mac_addr); ++void issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta); ++void issue_tdls_ch_switch_req(_adapter *padapter, u8 *mac_addr); ++void issue_tdls_ch_switch_rsp(_adapter *padapter, u8 *mac_addr); ++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); ++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); ++void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog); ++void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); ++ ++int update_sgi_tdls(_adapter *padapter, struct sta_info *psta); ++u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta); ++#endif //CONFIG_TDLS ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_version.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_version.h +new file mode 100644 +index 00000000..15d14e01 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_version.h +@@ -0,0 +1 @@ ++#define DRIVERVERSION "v4.1.8_9499.20131104" +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/rtw_wapi.h b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_wapi.h +new file mode 100644 +index 00000000..f72c666d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/rtw_wapi.h +@@ -0,0 +1,229 @@ ++#ifndef __INC_WAPI_H ++#define __INC_WAPI_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "rtl819x_Qos.h" ++ ++#define CONFIG_WAPI_SW_SMS4 ++#define WAPI_DEBUG ++ ++#define SMS4_MIC_LEN 16 ++#define WAPI_EXT_LEN 18 ++#define MAX_WAPI_IE_LEN 256 ++#define sMacHdrLng 24 // octets in data header, no WEP ++ ++#ifdef WAPI_DEBUG ++ ++/* WAPI trace debug */ ++extern u32 wapi_debug_component; ++ ++static inline void dump_buf(u8 *buf, u32 len) ++{ ++ u32 i; ++ printk("-----------------Len %d----------------\n", len); ++ for(i=0; i ++#include ++#include ++#ifdef PLATFORM_FREEBSD ++#include ++#endif //PLATFORM_FREEBSD ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++//#define MAX_XMITBUF_SZ (30720)// (2048) ++#ifdef CONFIG_TX_AGGREGATION ++#define MAX_XMITBUF_SZ (20480) // 20k ++#else ++#define MAX_XMITBUF_SZ (12288) //12k 1536*8 ++#endif ++ ++#if defined CONFIG_SDIO_HCI ++#define NR_XMITBUFF (16) ++#endif ++#if defined(CONFIG_GSPI_HCI) ++#define NR_XMITBUFF (128) ++#endif ++ ++#elif defined (CONFIG_USB_HCI) ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ #if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++ #define MAX_XMITBUF_SZ (12288) //12k 1536*8 ++ #elif defined (CONFIG_PLATFORM_MSTAR) ++ #define MAX_XMITBUF_SZ 7680 // 7.5k ++ #else ++ #define MAX_XMITBUF_SZ (20480) // 20k ++ #endif ++#else ++#define MAX_XMITBUF_SZ (2048) ++#endif ++#ifdef CONFIG_SINGLE_XMIT_BUF ++#define NR_XMITBUFF (1) ++#else ++#define NR_XMITBUFF (4) ++#endif //CONFIG_SINGLE_XMIT_BUF ++#elif defined (CONFIG_PCI_HCI) ++#define MAX_XMITBUF_SZ (1664) ++#define NR_XMITBUFF (128) ++#endif ++ ++#ifdef PLATFORM_OS_CE ++#define XMITBUF_ALIGN_SZ 4 ++#else ++#ifdef CONFIG_PCI_HCI ++#define XMITBUF_ALIGN_SZ 4 ++#else ++#define XMITBUF_ALIGN_SZ 512 ++#endif ++#endif ++ ++// xmit extension buff defination ++#define MAX_XMIT_EXTBUF_SZ (1536) ++#define NR_XMIT_EXTBUFF (32) ++ ++#define MAX_NUMBLKS (1) ++ ++#define XMIT_VO_QUEUE (0) ++#define XMIT_VI_QUEUE (1) ++#define XMIT_BE_QUEUE (2) ++#define XMIT_BK_QUEUE (3) ++ ++#define VO_QUEUE_INX 0 ++#define VI_QUEUE_INX 1 ++#define BE_QUEUE_INX 2 ++#define BK_QUEUE_INX 3 ++#define BCN_QUEUE_INX 4 ++#define MGT_QUEUE_INX 5 ++#define HIGH_QUEUE_INX 6 ++#define TXCMD_QUEUE_INX 7 ++ ++#define HW_QUEUE_ENTRY 8 ++ ++#ifdef CONFIG_PCI_HCI ++//#define TXDESC_NUM 64 ++#define TXDESC_NUM 128 ++#define TXDESC_NUM_BE_QUEUE 128 ++#endif ++ ++#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[2] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[3] = ((keyidx & 0x3)<<6);\ ++ dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++ ++#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ ++ pattrib_iv[2] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ ++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ ++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ ++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ ++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++#define AES_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[2] = 0;\ ++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ ++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ ++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ ++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ ++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++ ++#define HWXMIT_ENTRY 4 ++ ++ ++#define TXDESC_SIZE 32 ++ ++#ifdef CONFIG_TX_EARLY_MODE ++#define EARLY_MODE_INFO_SIZE 8 ++#endif ++ ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++#define TXDESC_OFFSET TXDESC_SIZE ++ ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#define PACKET_OFFSET_SZ (8) ++#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#define TXDESC_OFFSET 0 ++#define TX_DESC_NEXT_DESC_OFFSET 40 ++#endif ++ ++ ++ ++struct tx_desc{ ++ ++ //DWORD 0 ++ unsigned int txdw0; ++ ++ unsigned int txdw1; ++ ++ unsigned int txdw2; ++ ++ unsigned int txdw3; ++ ++ unsigned int txdw4; ++ ++ unsigned int txdw5; ++ ++ unsigned int txdw6; ++ ++ unsigned int txdw7; ++#ifdef CONFIG_PCI_HCI ++ unsigned int txdw8; ++ ++ unsigned int txdw9; ++ ++ unsigned int txdw10; ++ ++ unsigned int txdw11; ++ ++ // 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor ++ // size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute ++ // memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor ++ // number or enlarge descriptor size as 64 bytes. ++ unsigned int txdw12; ++ ++ unsigned int txdw13; ++ ++ unsigned int txdw14; ++ ++ unsigned int txdw15; ++#endif ++}; ++ ++ ++union txdesc { ++ struct tx_desc txdesc; ++ unsigned int value[TXDESC_SIZE>>2]; ++}; ++ ++#ifdef CONFIG_PCI_HCI ++#define PCI_MAX_TX_QUEUE_COUNT 8 ++ ++struct rtw_tx_ring { ++ struct tx_desc *desc; ++ dma_addr_t dma; ++ unsigned int idx; ++ unsigned int entries; ++ _queue queue; ++ u32 qlen; ++}; ++#endif ++ ++struct hw_xmit { ++ //_lock xmit_lock; ++ //_list pending; ++ _queue *sta_queue; ++ //struct hw_txqueue *phwtxqueue; ++ //sint txcmdcnt; ++ int accnt; ++}; ++ ++#if 0 ++struct pkt_attrib ++{ ++ u8 type; ++ u8 subtype; ++ u8 bswenc; ++ u8 dhcp_pkt; ++ u16 ether_type; ++ int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) ++ int pkt_hdrlen; //the original 802.3 pkt header len ++ int hdrlen; //the WLAN Header Len ++ int nr_frags; ++ int last_txcmdsz; ++ int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith ++ u8 iv[8]; ++ int iv_len; ++ u8 icv[8]; ++ int icv_len; ++ int priority; ++ int ack_policy; ++ int mac_id; ++ int vcs_mode; //virtual carrier sense method ++ ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++ u8 ta[ETH_ALEN]; ++ u8 ra[ETH_ALEN]; ++ ++ u8 key_idx; ++ ++ u8 qos_en; ++ u8 ht_en; ++ u8 raid;//rate adpative id ++ u8 bwmode; ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ u8 ampdu_en;//tx ampdu enable ++ u8 mdata;//more data bit ++ u8 eosp; ++ ++ u8 pctrl;//per packet txdesc control enable ++ u8 triggered;//for ap mode handling Power Saving sta ++ ++ u32 qsel; ++ u16 seqnum; ++ ++ struct sta_info * psta; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ u8 hw_tcp_csum; ++#endif ++}; ++#else ++//reduce size ++struct pkt_attrib ++{ ++ u8 type; ++ u8 subtype; ++ u8 bswenc; ++ u8 dhcp_pkt; ++ u16 ether_type; ++ u16 seqnum; ++ u16 pkt_hdrlen; //the original 802.3 pkt header len ++ u16 hdrlen; //the WLAN Header Len ++ u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) ++ u32 last_txcmdsz; ++ u8 nr_frags; ++ u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith ++ u8 iv_len; ++ u8 icv_len; ++ u8 iv[18]; ++ u8 icv[16]; ++ u8 priority; ++ u8 ack_policy; ++ u8 mac_id; ++ u8 vcs_mode; //virtual carrier sense method ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++ u8 ta[ETH_ALEN]; ++ u8 ra[ETH_ALEN]; ++ u8 key_idx; ++ u8 qos_en; ++ u8 ht_en; ++ u8 raid;//rate adpative id ++ u8 bwmode; ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ u8 ampdu_en;//tx ampdu enable ++ u8 mdata;//more data bit ++ u8 pctrl;//per packet txdesc control enable ++ u8 triggered;//for ap mode handling Power Saving sta ++ u8 qsel; ++ u8 eosp; ++ u8 rate; ++ u8 intel_proxim; ++ u8 retry_ctrl; ++ struct sta_info * psta; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ u8 hw_tcp_csum; ++#endif ++}; ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++#define ETH_ALEN 6 /* Octets in one ethernet addr */ ++#define ETH_HLEN 14 /* Total octets in header. */ ++#define ETH_P_IP 0x0800 /* Internet Protocol packet */ ++ ++/*struct rtw_ieee80211_hdr { ++ uint16_t frame_control; ++ uint16_t duration_id; ++ u8 addr1[6]; ++ u8 addr2[6]; ++ u8 addr3[6]; ++ uint16_t seq_ctrl; ++ u8 addr4[6]; ++} ;*/ ++#endif //PLATFORM_FREEBSD ++ ++#define WLANHDR_OFFSET 64 ++ ++#define NULL_FRAMETAG (0x0) ++#define DATA_FRAMETAG 0x01 ++#define L2_FRAMETAG 0x02 ++#define MGNT_FRAMETAG 0x03 ++#define AMSDU_FRAMETAG 0x04 ++ ++#define EII_FRAMETAG 0x05 ++#define IEEE8023_FRAMETAG 0x06 ++ ++#define MP_FRAMETAG 0x07 ++ ++#define TXAGG_FRAMETAG 0x08 ++ ++struct submit_ctx{ ++ u32 submit_time; /* */ ++ u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ ++ int status; /* status for operation */ ++#ifdef PLATFORM_LINUX ++ struct completion done; ++#endif ++}; ++ ++enum { ++ RTW_SCTX_SUBMITTED = -1, ++ RTW_SCTX_DONE_SUCCESS = 0, ++ RTW_SCTX_DONE_UNKNOWN, ++ RTW_SCTX_DONE_TIMEOUT, ++ RTW_SCTX_DONE_BUF_ALLOC, ++ RTW_SCTX_DONE_BUF_FREE, ++ RTW_SCTX_DONE_WRITE_PORT_ERR, ++ RTW_SCTX_DONE_TX_DESC_NA, ++ RTW_SCTX_DONE_TX_DENY, ++ RTW_SCTX_DONE_CCX_PKT_FAIL, ++ RTW_SCTX_DONE_DRV_STOP, ++ RTW_SCTX_DONE_DEV_REMOVE, ++}; ++ ++ ++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); ++int rtw_sctx_wait(struct submit_ctx *sctx); ++void rtw_sctx_done_err(struct submit_ctx **sctx, int status); ++void rtw_sctx_done(struct submit_ctx **sctx); ++ ++struct xmit_buf ++{ ++ _list list; ++ ++ _adapter *padapter; ++ ++ u8 *pallocated_buf; ++ ++ u8 *pbuf; ++ ++ void *priv_data; ++ ++ u16 ext_tag; // 0: Normal xmitbuf, 1: extension xmitbuf. ++ u16 flags; ++ u32 alloc_sz; ++ ++ u32 len; ++ ++ struct submit_ctx *sctx; ++ ++#ifdef CONFIG_USB_HCI ++ ++ //u32 sz[8]; ++ u32 ff_hwaddr; ++ ++#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) ++ PURB pxmit_urb[8]; ++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ PIRP pxmit_irp[8]; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_write_port; ++#endif ++ ++ u8 bpending[8]; ++ ++ sint last[8]; ++ ++#endif ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ u8 *phead; ++ u8 *pdata; ++ u8 *ptail; ++ u8 *pend; ++ u32 ff_hwaddr; ++ u8 pg_num; ++ u8 agg_num; ++#ifdef PLATFORM_OS_XP ++ PMDL pxmitbuf_mdl; ++ PIRP pxmitbuf_irp; ++ PSDBUS_REQUEST_PACKET pxmitbuf_sdrp; ++#endif ++#endif ++ ++#if defined(DBG_XMIT_BUF )|| defined(DBG_XMIT_BUF_EXT) ++ u8 no; ++#endif ++ ++}; ++ ++ ++struct xmit_frame ++{ ++ _list list; ++ ++ struct pkt_attrib attrib; ++ ++ _pkt *pkt; ++ ++ int frame_tag; ++ ++ _adapter *padapter; ++ ++ u8 *buf_addr; ++ ++ struct xmit_buf *pxmitbuf; ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ u8 pg_num; ++ u8 agg_num; ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 agg_num; ++#endif ++ s8 pkt_offset; ++#ifdef CONFIG_RTL8192D ++ u8 EMPktNum; ++ u16 EMPktLen[5];//The max value by HW ++#endif ++#endif ++ ++#ifdef CONFIG_XMIT_ACK ++ u8 ack_report; ++#endif ++ ++ u8 *alloc_addr; /* the actual address this xmitframe allocated */ ++ u8 ext_tag; /* 0:data, 1:mgmt */ ++ ++}; ++ ++struct tx_servq { ++ _list tx_pending; ++ _queue sta_pending; ++ int qcnt; ++}; ++ ++ ++struct sta_xmit_priv ++{ ++ _lock lock; ++ sint option; ++ sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD. ++ ++ ++ //struct tx_servq blk_q[MAX_NUMBLKS]; ++ struct tx_servq be_q; //priority == 0,3 ++ struct tx_servq bk_q; //priority == 1,2 ++ struct tx_servq vi_q; //priority == 4,5 ++ struct tx_servq vo_q; //priority == 6,7 ++ _list legacy_dz; ++ _list apsd; ++ ++ u16 txseq_tid[16]; ++ ++ //uint sta_tx_bytes; ++ //u64 sta_tx_pkts; ++ //uint sta_tx_fail; ++ ++ ++}; ++ ++ ++struct hw_txqueue { ++ volatile sint head; ++ volatile sint tail; ++ volatile sint free_sz; //in units of 64 bytes ++ volatile sint free_cmdsz; ++ volatile sint txsz[8]; ++ uint ff_hwaddr; ++ uint cmd_hwaddr; ++ sint ac_tag; ++}; ++ ++struct agg_pkt_info{ ++ u16 offset; ++ u16 pkt_len; ++}; ++ ++struct xmit_priv { ++ ++ _lock lock; ++ ++ _sema xmit_sema; ++ _sema terminate_xmitthread_sema; ++ ++ //_queue blk_strms[MAX_NUMBLKS]; ++ _queue be_pending; ++ _queue bk_pending; ++ _queue vi_pending; ++ _queue vo_pending; ++ _queue bm_pending; ++ ++ //_queue legacy_dz_queue; ++ //_queue apsd_queue; ++ ++ u8 *pallocated_frame_buf; ++ u8 *pxmit_frame_buf; ++ uint free_xmitframe_cnt; ++ _queue free_xmit_queue; ++ ++ //uint mapping_addr; ++ //uint pkt_sz; ++ ++ u8 *xframe_ext_alloc_addr; ++ u8 *xframe_ext; ++ uint free_xframe_ext_cnt; ++ _queue free_xframe_ext_queue; ++ ++ //struct hw_txqueue be_txqueue; ++ //struct hw_txqueue bk_txqueue; ++ //struct hw_txqueue vi_txqueue; ++ //struct hw_txqueue vo_txqueue; ++ //struct hw_txqueue bmc_txqueue; ++ ++ uint frag_len; ++ ++ _adapter *adapter; ++ ++ u8 vcs_setting; ++ u8 vcs; ++ u8 vcs_type; ++ //u16 rts_thresh; ++ ++ u64 tx_bytes; ++ u64 tx_pkts; ++ u64 tx_drop; ++ u64 last_tx_bytes; ++ u64 last_tx_pkts; ++ ++ struct hw_xmit *hwxmits; ++ u8 hwxmit_entry; ++ ++ u8 wmm_para_seq[4];//sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. ++ ++#ifdef CONFIG_USB_HCI ++ _sema tx_retevt;//all tx return event; ++ u8 txirp_cnt;// ++ ++#ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_write_port; ++// USB_TRANSFER usb_transfer_write_mem; ++#endif ++#ifdef PLATFORM_LINUX ++ struct tasklet_struct xmit_tasklet; ++#endif ++#ifdef PLATFORM_FREEBSD ++ struct task xmit_tasklet; ++#endif ++ //per AC pending irp ++ int beq_cnt; ++ int bkq_cnt; ++ int viq_cnt; ++ int voq_cnt; ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ // Tx ++ struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; ++ int txringcount[PCI_MAX_TX_QUEUE_COUNT]; ++ u8 beaconDMAing; //flag of indicating beacon is transmiting to HW by DMA ++#ifdef PLATFORM_LINUX ++ struct tasklet_struct xmit_tasklet; ++#endif ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++#ifdef CONFIG_SDIO_TX_TASKLET ++ #ifdef PLATFORM_LINUX ++ struct tasklet_struct xmit_tasklet; ++ #endif /* PLATFORM_LINUX */ ++#else ++ _thread_hdl_ SdioXmitThread; ++ _sema SdioXmitSema; ++ _sema SdioXmitTerminateSema; ++#endif /* CONFIG_SDIO_TX_TASKLET */ ++#endif /* CONFIG_SDIO_HCI */ ++ ++ _queue free_xmitbuf_queue; ++ _queue pending_xmitbuf_queue; ++ u8 *pallocated_xmitbuf; ++ u8 *pxmitbuf; ++ uint free_xmitbuf_cnt; ++ ++ _queue free_xmit_extbuf_queue; ++ u8 *pallocated_xmit_extbuf; ++ u8 *pxmit_extbuf; ++ uint free_xmit_extbuf_cnt; ++ ++ u16 nqos_ssn; ++ #ifdef CONFIG_TX_EARLY_MODE ++ ++ #ifdef CONFIG_SDIO_HCI ++ #define MAX_AGG_PKT_NUM 20 ++ #else ++ #define MAX_AGG_PKT_NUM 256 //Max tx ampdu coounts ++ #endif ++ ++ struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM]; ++ #endif ++ ++#ifdef CONFIG_XMIT_ACK ++ int ack_tx; ++ _mutex ack_tx_mutex; ++ struct submit_ctx ack_tx_ops; ++#endif ++ _lock lock_sctx; ++}; ++ ++extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); ++extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); ++extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); ++extern s32 rtw_put_snap(u8 *data, u16 h_proto); ++ ++extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); ++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); ++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); ++extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); ++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); ++extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); ++ ++extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); ++extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); ++#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) ++extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); ++#ifdef CONFIG_IEEE80211W ++extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); ++#endif //CONFIG_IEEE80211W ++#ifdef CONFIG_TDLS ++s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, u8 action); ++#endif ++s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag); ++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); ++ ++ ++s32 rtw_txframes_pending(_adapter *padapter); ++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); ++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); ++ ++ ++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); ++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv); ++ ++ ++void rtw_alloc_hwxmits(_adapter *padapter); ++void rtw_free_hwxmits(_adapter *padapter); ++ ++ ++s32 rtw_xmit(_adapter *padapter, _pkt **pkt); ++ ++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) ++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); ++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); ++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); ++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); ++#endif ++ ++u8 qos_acm(u8 acm_mask, u8 priority); ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++struct xmit_buf* dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); ++struct xmit_buf* dequeue_pending_xmitbuf_under_survey(struct xmit_priv *pxmitpriv); ++sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); ++thread_return rtw_xmit_thread(thread_context context); ++#endif ++ ++u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_XMIT_ACK ++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); ++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); ++#endif //CONFIG_XMIT_ACK ++ ++ ++//include after declaring struct xmit_buf, in order to avoid warning ++#include ++ ++#endif //_RTL871X_XMIT_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_hal.h +new file mode 100644 +index 00000000..60e261bc +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_hal.h +@@ -0,0 +1,41 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_HAL_H__ ++#define __SDIO_HAL_H__ ++ ++ ++extern u8 sd_hal_bus_init(PADAPTER padapter); ++extern u8 sd_hal_bus_deinit(PADAPTER padapter); ++ ++u8 sd_int_isr(PADAPTER padapter); ++void sd_int_dpc(PADAPTER padapter); ++ ++#ifdef CONFIG_RTL8723A ++void rtl8723as_set_hal_ops(PADAPTER padapter); ++#define hal_set_hal_ops rtl8723as_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188es_set_hal_ops(PADAPTER padapter); ++#define hal_set_hal_ops rtl8188es_set_hal_ops ++#endif ++ ++#endif //__SDIO_HAL_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops.h +new file mode 100644 +index 00000000..e79b0fc8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops.h +@@ -0,0 +1,84 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_OPS_H__ ++#define __SDIO_OPS_H__ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++#ifdef PLATFORM_OS_XP ++#include ++struct async_context ++{ ++ PMDL pmdl; ++ PSDBUS_REQUEST_PACKET sdrp; ++ unsigned char* r_buf; ++ unsigned char* padapter; ++}; ++#endif ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++#endif ++ ++ ++extern void sdio_set_intf_ops(struct _io_ops *pops); ++ ++//extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); ++//extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); ++extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr); ++extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v); ++extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); ++extern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); ++extern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); ++extern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); ++ ++u32 _sdio_read32(PADAPTER padapter, u32 addr); ++s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val); ++ ++extern void InitInterrupt8723ASdio(PADAPTER padapter); ++extern void InitSysInterrupt8723ASdio(PADAPTER padapter); ++extern void EnableInterrupt8723ASdio(PADAPTER padapter); ++extern void DisableInterrupt8723ASdio(PADAPTER padapter); ++extern void sd_int_hdl(PADAPTER padapter); ++#ifdef CONFIG_RTL8723A ++extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); ++#endif //CONFIG_RTL8723A ++#ifdef CONFIG_RTL8188E ++extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter); ++#endif //CONFIG_RTL8188E ++extern void InitInterrupt8188ESdio(PADAPTER padapter); ++extern void EnableInterrupt8188ESdio(PADAPTER padapter); ++extern void DisableInterrupt8188ESdio(PADAPTER padapter); ++extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); ++ ++#ifdef CONFIG_WOWLAN ++extern u8 RecvOnePkt(PADAPTER padapter, u32 size); ++extern void ClearInterrupt8189ESdio(PADAPTER padapter); ++#endif //CONFIG_WOWLAN ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_ce.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_ce.h +new file mode 100644 +index 00000000..d2da2933 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_ce.h +@@ -0,0 +1,55 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _SDIO_OPS_WINCE_H_ ++#define _SDIO_OPS_WINCE_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_CE ++ ++ ++extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); ++ ++ ++extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr,u8 val8); ++ ++ ++uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); ++extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern void sdio_read_int(_adapter *padapter, u32 addr,u8 sz,void *pdata); ++ ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_linux.h +new file mode 100644 +index 00000000..008c5bf0 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_linux.h +@@ -0,0 +1,52 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_OPS_LINUX_H__ ++#define __SDIO_OPS_LINUX_H__ ++ ++#define SDIO_ERR_VAL8 0xEA ++#define SDIO_ERR_VAL16 0xEAEA ++#define SDIO_ERR_VAL32 0xEAEAEAEA ++ ++u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); ++ ++s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++ ++u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); ++s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); ++void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err); ++void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); ++void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); ++s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); ++ ++ ++void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl); ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_xp.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_xp.h +new file mode 100644 +index 00000000..757b35d4 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_ops_xp.h +@@ -0,0 +1,55 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _SDIO_OPS_XP_H_ ++#define _SDIO_OPS_XP_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ ++ ++extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); ++ ++ ++extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr,u8 val8); ++ ++ ++uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); ++extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern void sdio_read_int(_adapter *padapter, u32 addr,u8 sz,void *pdata); ++ ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sdio_osintf.h b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_osintf.h +new file mode 100644 +index 00000000..51ec5b75 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sdio_osintf.h +@@ -0,0 +1,40 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __SDIO_OSINTF_H__ ++#define __SDIO_OSINTF_H__ ++ ++ ++#include ++#include ++#include ++ ++ ++u8 sd_hal_bus_init(PADAPTER padapter); ++u8 sd_hal_bus_deinit(PADAPTER padapter); ++void sd_c2h_hdl(PADAPTER padapter); ++ ++#ifdef PLATFORM_OS_CE ++extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter); ++SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter); ++extern void sd_setup_irs(PADAPTER padapter); ++#endif ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/sta_info.h b/drivers/net/wireless/rtl818x/rtl8189/include/sta_info.h +new file mode 100644 +index 00000000..3b8ed787 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/sta_info.h +@@ -0,0 +1,479 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __STA_INFO_H_ ++#define __STA_INFO_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define IBSS_START_MAC_ID 2 ++#define NUM_STA 32 ++#define NUM_ACL 16 ++ ++ ++//if mode ==0, then the sta is allowed once the addr is hit. ++//if mode ==1, then the sta is rejected once the addr is non-hit. ++struct rtw_wlan_acl_node { ++ _list list; ++ u8 addr[ETH_ALEN]; ++ u8 valid; ++}; ++ ++//mode=0, disable ++//mode=1, accept unless in deny list ++//mode=2, deny unless in accept list ++struct wlan_acl_pool { ++ int mode; ++ int num; ++ struct rtw_wlan_acl_node aclnode[NUM_ACL]; ++ _queue acl_node_q; ++}; ++ ++typedef struct _RSSI_STA{ ++ s32 UndecoratedSmoothedPWDB; ++ s32 UndecoratedSmoothedCCK; ++ s32 UndecoratedSmoothedOFDM; ++ u64 PacketMap; ++ u8 ValidBit; ++}RSSI_STA, *PRSSI_STA; ++ ++struct stainfo_stats { ++ ++ u64 rx_mgnt_pkts; ++ u64 rx_beacon_pkts; ++ u64 rx_probereq_pkts; ++ u64 rx_probersp_pkts; ++ u64 rx_probersp_bm_pkts; ++ u64 rx_probersp_uo_pkts; ++ u64 rx_ctrl_pkts; ++ u64 rx_data_pkts; ++ ++ u64 last_rx_mgnt_pkts; ++ u64 last_rx_beacon_pkts; ++ u64 last_rx_probereq_pkts; ++ u64 last_rx_probersp_pkts; ++ u64 last_rx_probersp_bm_pkts; ++ u64 last_rx_probersp_uo_pkts; ++ u64 last_rx_ctrl_pkts; ++ u64 last_rx_data_pkts; ++ ++ u64 rx_bytes; ++ u64 rx_drops; ++ ++ u64 tx_pkts; ++ u64 tx_bytes; ++ u64 tx_drops; ++ ++}; ++ ++#ifdef CONFIG_TDLS ++struct TDLS_PeerKey { ++ u8 kck[16]; /* TPK-KCK */ ++ u8 tk[16]; /* TPK-TK; only CCMP will be used */ ++} ; ++#endif //CONFIG_TDLS ++ ++struct sta_info { ++ ++ _lock lock; ++ _list list; //free_sta_queue ++ _list hash_list; //sta_hash ++ //_list asoc_list; //20061114 ++ //_list sleep_list;//sleep_q ++ //_list wakeup_list;//wakeup_q ++ _adapter *padapter; ++ ++ struct sta_xmit_priv sta_xmitpriv; ++ struct sta_recv_priv sta_recvpriv; ++ ++ _queue sleep_q; ++ unsigned int sleepq_len; ++ ++ uint state; ++ uint aid; ++ uint mac_id; ++ uint qos_option; ++ u8 hwaddr[ETH_ALEN]; ++ ++ uint ieee8021x_blocked; //0: allowed, 1:blocked ++ uint dot118021XPrivacy; //aes, tkip... ++ union Keytype dot11tkiptxmickey; ++ union Keytype dot11tkiprxmickey; ++ union Keytype dot118021x_UncstKey; ++ union pn48 dot11txpn; // PN48 used for Unicast xmit. ++#ifdef CONFIG_IEEE80211W ++ union pn48 dot11wtxpn; // PN48 used for Unicast mgmt xmit. ++#endif //CONFIG_IEEE80211W ++ union pn48 dot11rxpn; // PN48 used for Unicast recv. ++ ++ ++ u8 bssrateset[16]; ++ u32 bssratelen; ++ s32 rssi; ++ s32 signal_quality; ++ ++ u8 cts2self; ++ u8 rtsen; ++ ++ u8 raid; ++ u8 init_rate; ++ u32 ra_mask; ++ u8 wireless_mode; // NETWORK_TYPE ++ struct stainfo_stats sta_stats; ++ ++#ifdef CONFIG_TDLS ++ u32 tdls_sta_state; ++ u8 dialog; ++ u8 SNonce[32]; ++ u8 ANonce[32]; ++ u32 TDLS_PeerKey_Lifetime; ++ u16 TPK_count; ++ _timer TPK_timer; ++ struct TDLS_PeerKey tpk; ++ u16 stat_code; ++ u8 off_ch; ++ u16 ch_switch_time; ++ u16 ch_switch_timeout; ++ u8 option; ++ _timer option_timer; ++ _timer base_ch_timer; ++ _timer off_ch_timer; ++ ++ _timer handshake_timer; ++ _timer alive_timer1; ++ _timer alive_timer2; ++ u8 timer_flag; ++ u8 alive_count; ++#endif //CONFIG_TDLS ++ ++ //for A-MPDU TX, ADDBA timeout check ++ _timer addba_retry_timer; ++ ++ //for A-MPDU Rx reordering buffer control ++ struct recv_reorder_ctrl recvreorder_ctrl[16]; ++ ++ //for A-MPDU Tx ++ //unsigned char ampdu_txen_bitmap; ++ u16 BA_starting_seqctrl[16]; ++ ++ ++#ifdef CONFIG_80211N_HT ++ struct ht_priv htpriv; ++#endif ++ ++ //Notes: ++ //STA_Mode: ++ //curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO ++ //scan_q: AP CAP/INFO ++ ++ //AP_Mode: ++ //curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO ++ //sta_info: (AP & STA) CAP/INFO ++ ++#ifdef CONFIG_AP_MODE ++ ++ _list asoc_list; ++ _list auth_list; ++ ++ unsigned int expire_to; ++ unsigned int auth_seq; ++ unsigned int authalg; ++ unsigned char chg_txt[128]; ++ ++ u16 capability; ++ int flags; ++ ++ int dot8021xalg;//0:disable, 1:psk, 2:802.1x ++ int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 ++ int wpa_group_cipher; ++ int wpa2_group_cipher; ++ int wpa_pairwise_cipher; ++ int wpa2_pairwise_cipher; ++ ++ u8 bpairwise_key_installed; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ u8 wpa_ie[32]; ++ ++ u8 nonerp_set; ++ u8 no_short_slot_time_set; ++ u8 no_short_preamble_set; ++ u8 no_ht_gf_set; ++ u8 no_ht_set; ++ u8 ht_20mhz_set; ++#endif // CONFIG_NATIVEAP_MLME ++ ++#ifdef CONFIG_ATMEL_RC_PATCH ++ u8 flag_atmel_rc; ++#endif ++ ++ unsigned int tx_ra_bitmap; ++ u8 qos_info; ++ ++ u8 max_sp_len; ++ u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled ++ u8 uapsd_be; ++ u8 uapsd_vi; ++ u8 uapsd_vo; ++ ++ u8 has_legacy_ac; ++ unsigned int sleepq_ac_len; ++ ++#ifdef CONFIG_P2P ++ //p2p priv data ++ u8 is_p2p_device; ++ u8 p2p_status_code; ++ ++ //p2p client info ++ u8 dev_addr[ETH_ALEN]; ++ //u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN] ++ u8 dev_cap; ++ u16 config_methods; ++ u8 primary_dev_type[8]; ++ u8 num_of_secdev_type; ++ u8 secdev_types_list[32];// 32/8 == 4; ++ u16 dev_name_len; ++ u8 dev_name[32]; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ u8 under_exist_checking; ++#endif // CONFIG_TX_MCAST2UNI ++ ++ u8 keep_alive_trycnt; ++ ++#endif // CONFIG_AP_MODE ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ u8 *passoc_req; ++ u32 assoc_req_len; ++#endif ++ ++#ifdef DBG_TRX_STA_PKTS ++ //per AC dbg irp cnts ++ int rx_be_cnt; ++ int rx_bk_cnt; ++ int rx_vi_cnt; ++ int rx_vo_cnt; ++ //per AC dbg irp cnts ++ int tx_be_cnt; ++ int tx_bk_cnt; ++ int tx_vi_cnt; ++ int tx_vo_cnt; ++#endif ++ //for DM ++ RSSI_STA rssi_stat; ++ ++ //ODM_STA_INFO_T ++ // ================ODM Relative Info======================= ++ // Please be care, dont declare too much structure here. It will cost memory * STA support num. ++ // ++ // ++ // 2011/10/20 MH Add for ODM STA info. ++ // ++ // Driver Write ++ u8 bValid; // record the sta status link or not? ++ //u8 WirelessMode; // ++ u8 IOTPeer; // Enum value. HT_IOT_PEER_E ++ // ODM Write ++ //1 PHY_STATUS_INFO ++ u8 RSSI_Path[4]; // ++ u8 RSSI_Ave; ++ u8 RXEVM[4]; ++ u8 RXSNR[4]; ++ ++ u8 rssi_level; //for Refresh RA mask ++ // ODM Write ++ //1 TX_INFO (may changed by IC) ++ //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. ++ // ++ // ================ODM Relative Info======================= ++ // ++ ++ /* To store the sequence number of received management frame */ ++ u16 RxMgmtFrameSeqNum; ++}; ++ ++#define sta_rx_pkts(sta) \ ++ (sta->sta_stats.rx_mgnt_pkts \ ++ + sta->sta_stats.rx_ctrl_pkts \ ++ + sta->sta_stats.rx_data_pkts) ++ ++#define sta_last_rx_pkts(sta) \ ++ (sta->sta_stats.last_rx_mgnt_pkts \ ++ + sta->sta_stats.last_rx_ctrl_pkts \ ++ + sta->sta_stats.last_rx_data_pkts) ++ ++#define sta_rx_data_pkts(sta) \ ++ (sta->sta_stats.rx_data_pkts) ++ ++#define sta_last_rx_data_pkts(sta) \ ++ (sta->sta_stats.last_rx_data_pkts) ++ ++#define sta_rx_mgnt_pkts(sta) \ ++ (sta->sta_stats.rx_mgnt_pkts) ++ ++#define sta_last_rx_mgnt_pkts(sta) \ ++ (sta->sta_stats.last_rx_mgnt_pkts) ++ ++#define sta_rx_beacon_pkts(sta) \ ++ (sta->sta_stats.rx_beacon_pkts) ++ ++#define sta_last_rx_beacon_pkts(sta) \ ++ (sta->sta_stats.last_rx_beacon_pkts) ++ ++#define sta_rx_probereq_pkts(sta) \ ++ (sta->sta_stats.rx_probereq_pkts) ++ ++#define sta_last_rx_probereq_pkts(sta) \ ++ (sta->sta_stats.last_rx_probereq_pkts) ++ ++#define sta_rx_probersp_pkts(sta) \ ++ (sta->sta_stats.rx_probersp_pkts) ++ ++#define sta_last_rx_probersp_pkts(sta) \ ++ (sta->sta_stats.last_rx_probersp_pkts) ++ ++#define sta_rx_probersp_bm_pkts(sta) \ ++ (sta->sta_stats.rx_probersp_bm_pkts) ++ ++#define sta_last_rx_probersp_bm_pkts(sta) \ ++ (sta->sta_stats.last_rx_probersp_bm_pkts) ++ ++#define sta_rx_probersp_uo_pkts(sta) \ ++ (sta->sta_stats.rx_probersp_uo_pkts) ++ ++#define sta_last_rx_probersp_uo_pkts(sta) \ ++ (sta->sta_stats.last_rx_probersp_uo_pkts) ++ ++#define sta_update_last_rx_pkts(sta) \ ++ do { \ ++ sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ ++ sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ ++ sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ ++ sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \ ++ sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ ++ sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ ++ sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ ++ sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ ++ } while(0) ++ ++#define STA_RX_PKTS_ARG(sta) \ ++ sta->sta_stats.rx_mgnt_pkts \ ++ , sta->sta_stats.rx_ctrl_pkts \ ++ , sta->sta_stats.rx_data_pkts ++ ++#define STA_LAST_RX_PKTS_ARG(sta) \ ++ sta->sta_stats.last_rx_mgnt_pkts \ ++ , sta->sta_stats.last_rx_ctrl_pkts \ ++ , sta->sta_stats.last_rx_data_pkts ++ ++#define STA_RX_PKTS_DIFF_ARG(sta) \ ++ sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \ ++ , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \ ++ , sta->sta_stats.rx_data_pkts -sta->sta_stats.last_rx_data_pkts ++ ++#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" ++ ++struct sta_priv { ++ ++ u8 *pallocated_stainfo_buf; ++ u8 *pstainfo_buf; ++ _queue free_sta_queue; ++ ++ _lock sta_hash_lock; ++ _list sta_hash[NUM_STA]; ++ int asoc_sta_count; ++ _queue sleep_q; ++ _queue wakeup_q; ++ ++ _adapter *padapter; ++ ++ ++#ifdef CONFIG_AP_MODE ++ _list asoc_list; ++ _list auth_list; ++ _lock asoc_list_lock; ++ _lock auth_list_lock; ++ u8 asoc_list_cnt; ++ u8 auth_list_cnt; ++ ++ unsigned int auth_to; //sec, time to expire in authenticating. ++ unsigned int assoc_to; //sec, time to expire before associating. ++ unsigned int expire_to; //sec , time to expire after associated. ++ ++ /* pointers to STA info; based on allocated AID or NULL if AID free ++ * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 ++ * and so on ++ */ ++ struct sta_info *sta_aid[NUM_STA]; ++ ++ u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta. ++ u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15 ++ ++ u16 max_num_sta; ++ ++ struct wlan_acl_pool acl_list; ++#endif ++ ++#ifdef CONFIG_ATMEL_RC_PATCH ++ u8 atmel_rc_pattern [6]; ++#endif ++ ++}; ++ ++ ++__inline static u32 wifi_mac_hash(u8 *mac) ++{ ++ u32 x; ++ ++ x = mac[0]; ++ x = (x << 2) ^ mac[1]; ++ x = (x << 2) ^ mac[2]; ++ x = (x << 2) ^ mac[3]; ++ x = (x << 2) ^ mac[4]; ++ x = (x << 2) ^ mac[5]; ++ ++ x ^= x >> 8; ++ x = x & (NUM_STA - 1); ++ ++ return x; ++} ++ ++ ++extern u32 _rtw_init_sta_priv(struct sta_priv *pstapriv); ++extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); ++ ++#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0) ++int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); ++struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); ++ ++extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); ++extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); ++extern void rtw_free_all_stainfo(_adapter *padapter); ++extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); ++extern u32 rtw_init_bcmc_stainfo(_adapter* padapter); ++extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter); ++extern u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr); ++ ++#endif //_STA_INFO_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/usb_hal.h b/drivers/net/wireless/rtl818x/rtl8189/include/usb_hal.h +new file mode 100644 +index 00000000..c3ac5e97 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/usb_hal.h +@@ -0,0 +1,47 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __USB_HAL_H__ ++#define __USB_HAL_H__ ++ ++#ifdef CONFIG_RTL8192C ++void rtl8192cu_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8192cu_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8192D ++void rtl8192du_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8192du_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8723A ++void rtl8723au_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8723au_set_hal_ops ++#endif ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188eu_set_hal_ops(_adapter * padapter); ++#define hal_set_hal_ops rtl8188eu_set_hal_ops ++#endif ++ ++#ifdef CONFIG_INTEL_PROXIM ++extern _adapter *rtw_usb_get_sw_pointer(void); ++#endif //CONFIG_INTEL_PROXIM ++#endif //__USB_HAL_H__ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops.h b/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops.h +new file mode 100644 +index 00000000..bb0a2b6d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops.h +@@ -0,0 +1,123 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __USB_OPS_H_ ++#define __USB_OPS_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define REALTEK_USB_VENQT_READ 0xC0 ++#define REALTEK_USB_VENQT_WRITE 0x40 ++#define REALTEK_USB_VENQT_CMD_REQ 0x05 ++#define REALTEK_USB_VENQT_CMD_IDX 0x00 ++ ++enum{ ++ VENDOR_WRITE = 0x00, ++ VENDOR_READ = 0x01, ++}; ++#define ALIGNMENT_UNIT 16 ++#define MAX_VENDOR_REQ_CMD_SIZE 254 //8188cu SIE Support ++#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT) ++ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) ++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \ ++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms)) ++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ ++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms)) ++#else ++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size,timeout_ms) \ ++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \ ++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) ++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ ++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \ ++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) ++#endif ++#include ++#endif //PLATFORM_LINUX ++ ++#ifdef CONFIG_RTL8192C ++void rtl8192cu_set_hw_type(_adapter *padapter); ++#define hal_set_hw_type rtl8192cu_set_hw_type ++ ++void rtl8192cu_set_intf_ops(struct _io_ops *pops); ++#define usb_set_intf_ops rtl8192cu_set_intf_ops ++ ++void rtl8192cu_recv_tasklet(void *priv); ++ ++void rtl8192cu_xmit_tasklet(void *priv); ++#endif ++ ++#ifdef CONFIG_RTL8723A ++void rtl8723au_set_hw_type(_adapter *padapter); ++#define hal_set_hw_type rtl8723au_set_hw_type ++ ++void rtl8723au_set_intf_ops(struct _io_ops *pops); ++#define usb_set_intf_ops rtl8723au_set_intf_ops ++ ++void rtl8192cu_recv_tasklet(void *priv); ++ ++void rtl8192cu_xmit_tasklet(void *priv); ++#endif ++ ++#ifdef CONFIG_RTL8192D ++void rtl8192du_set_hw_type(_adapter *padapter); ++#define hal_set_hw_type rtl8192du_set_hw_type ++void rtl8192du_set_intf_ops(struct _io_ops *pops); ++#define usb_set_intf_ops rtl8192du_set_intf_ops ++#ifndef PLATFORM_FREEBSD ++void rtl8192du_recv_tasklet(void *priv); ++#else // PLATFORM_FREEBSD ++void rtl8192du_recv_tasklet(void *priv, int npending); ++#ifdef CONFIG_RX_INDICATE_QUEUE ++void rtw_rx_indicate_tasklet(void *priv, int npending); ++#endif // CONFIG_RX_INDICATE_QUEUE ++#endif // PLATFORM_FREEBSD ++ ++void rtl8192du_xmit_tasklet(void *priv); ++#endif ++ ++#ifdef CONFIG_RTL8188E ++void rtl8188eu_set_hw_type(_adapter *padapter); ++#define hal_set_hw_type rtl8188eu_set_hw_type ++void rtl8188eu_set_intf_ops(struct _io_ops *pops); ++#define usb_set_intf_ops rtl8188eu_set_intf_ops ++#endif ++ ++#define USB_HIGH_SPEED_BULK_SIZE 512 ++#define USB_FULL_SPEED_BULK_SIZE 64 ++ ++static inline u8 rtw_usb_bulk_size_boundary(_adapter * padapter,int buf_len) ++{ ++ u8 rst = _TRUE; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ ++ if (pdvobjpriv->ishighspeed == _TRUE) ++ rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE)?_TRUE:_FALSE; ++ else ++ rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE)?_TRUE:_FALSE; ++ return rst; ++} ++ ++ ++#endif //__USB_OPS_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops_linux.h b/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops_linux.h +new file mode 100644 +index 00000000..d418ba26 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/usb_ops_linux.h +@@ -0,0 +1,63 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __USB_OPS_LINUX_H__ ++#define __USB_OPS_LINUX_H__ ++ ++#define VENDOR_CMD_MAX_DATA_LEN 254 ++ ++#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10//ms ++#define RTW_USB_CONTROL_MSG_TIMEOUT 500//ms ++ ++#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */ ++#define MAX_USBCTRL_VENDORREQ_TIMES 10 ++#else ++#define MAX_USBCTRL_VENDORREQ_TIMES 1 ++#endif ++ ++#define RTW_USB_BULKOUT_TIMEOUT 5000//ms ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) ++#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) ++#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) ++#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) ++#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) ++#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) ++#endif ++ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ ++ ++unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr); ++ ++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); ++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); ++ ++void usb_read_port_cancel(struct intf_hdl *pintfhdl); ++ ++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); ++void usb_write_port_cancel(struct intf_hdl *pintfhdl); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/usb_osintf.h b/drivers/net/wireless/rtl818x/rtl8189/include/usb_osintf.h +new file mode 100644 +index 00000000..753013dd +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/usb_osintf.h +@@ -0,0 +1,38 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __USB_OSINTF_H ++#define __USB_OSINTF_H ++ ++#include ++#include ++#include ++#include ++ ++#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3) ++ ++ ++//uint usb_dvobj_init(_adapter * adapter); ++//void usb_dvobj_deinit(_adapter * adapter); ++ ++u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin); ++ ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/usb_vendor_req.h b/drivers/net/wireless/rtl818x/rtl8189/include/usb_vendor_req.h +new file mode 100644 +index 00000000..b60eefac +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/usb_vendor_req.h +@@ -0,0 +1,60 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _USB_VENDOR_REQUEST_H_ ++#define _USB_VENDOR_REQUEST_H_ ++ ++//4 Set/Get Register related wIndex/Data ++#define RT_USB_RESET_MASK_OFF 0 ++#define RT_USB_RESET_MASK_ON 1 ++#define RT_USB_SLEEP_MASK_OFF 0 ++#define RT_USB_SLEEP_MASK_ON 1 ++#define RT_USB_LDO_ON 1 ++#define RT_USB_LDO_OFF 0 ++ ++//4 Set/Get SYSCLK related wValue or Data ++#define RT_USB_SYSCLK_32KHZ 0 ++#define RT_USB_SYSCLK_40MHZ 1 ++#define RT_USB_SYSCLK_60MHZ 2 ++ ++ ++typedef enum _RT_USB_BREQUEST { ++ RT_USB_SET_REGISTER = 1, ++ RT_USB_SET_SYSCLK = 2, ++ RT_USB_GET_SYSCLK = 3, ++ RT_USB_GET_REGISTER = 4 ++} RT_USB_BREQUEST; ++ ++ ++typedef enum _RT_USB_WVALUE { ++ RT_USB_RESET_MASK = 1, ++ RT_USB_SLEEP_MASK = 2, ++ RT_USB_USB_HRCPWM = 3, ++ RT_USB_LDO = 4, ++ RT_USB_BOOT_TYPE = 5 ++} RT_USB_WVALUE; ++ ++ ++//BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn); ++//BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data); ++//BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index); ++//BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength); ++ ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/wifi.h b/drivers/net/wireless/rtl818x/rtl8189/include/wifi.h +new file mode 100644 +index 00000000..39f46186 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/wifi.h +@@ -0,0 +1,1263 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _WIFI_H_ ++#define _WIFI_H_ ++ ++#include ++ ++#ifdef BIT ++//#error "BIT define occurred earlier elsewhere!\n" ++#undef BIT ++#endif ++#define BIT(x) (1 << (x)) ++ ++ ++#define WLAN_ETHHDR_LEN 14 ++#define WLAN_ETHADDR_LEN 6 ++#define WLAN_IEEE_OUI_LEN 3 ++#define WLAN_ADDR_LEN 6 ++#define WLAN_CRC_LEN 4 ++#define WLAN_BSSID_LEN 6 ++#define WLAN_BSS_TS_LEN 8 ++#define WLAN_HDR_A3_LEN 24 ++#define WLAN_HDR_A4_LEN 30 ++#define WLAN_HDR_A3_QOS_LEN 26 ++#define WLAN_HDR_A4_QOS_LEN 32 ++#define WLAN_SSID_MAXLEN 32 ++#define WLAN_DATA_MAXLEN 2312 ++ ++#define WLAN_A3_PN_OFFSET 24 ++#define WLAN_A4_PN_OFFSET 30 ++ ++#define WLAN_MIN_ETHFRM_LEN 60 ++#define WLAN_MAX_ETHFRM_LEN 1514 ++#define WLAN_ETHHDR_LEN 14 ++ ++#define P80211CAPTURE_VERSION 0x80211001 ++ ++// This value is tested by WiFi 11n Test Plan 5.2.3. ++// This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. ++#define WiFiNavUpperUs 30000 // 30 ms ++ ++#ifdef GREEN_HILL ++#pragma pack(1) ++#endif ++ ++enum WIFI_FRAME_TYPE { ++ WIFI_MGT_TYPE = (0), ++ WIFI_CTRL_TYPE = (BIT(2)), ++ WIFI_DATA_TYPE = (BIT(3)), ++ WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), //!< QoS Data ++}; ++ ++enum WIFI_FRAME_SUBTYPE { ++ ++ // below is for mgt frame ++ WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), ++ WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), ++ WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), ++ WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), ++ WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), ++ WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), ++ WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), ++ WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), ++ ++ // below is for control frame ++ WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), ++ WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), ++ WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), ++ WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), ++ WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), ++ WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), ++ ++ // below is for data frame ++ WIFI_DATA = (0 | WIFI_DATA_TYPE), ++ WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), ++ WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), ++ WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), ++ WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), ++ WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), ++}; ++ ++enum WIFI_REASON_CODE { ++ _RSON_RESERVED_ = 0, ++ _RSON_UNSPECIFIED_ = 1, ++ _RSON_AUTH_NO_LONGER_VALID_ = 2, ++ _RSON_DEAUTH_STA_LEAVING_ = 3, ++ _RSON_INACTIVITY_ = 4, ++ _RSON_UNABLE_HANDLE_ = 5, ++ _RSON_CLS2_ = 6, ++ _RSON_CLS3_ = 7, ++ _RSON_DISAOC_STA_LEAVING_ = 8, ++ _RSON_ASOC_NOT_AUTH_ = 9, ++ ++ // WPA reason ++ _RSON_INVALID_IE_ = 13, ++ _RSON_MIC_FAILURE_ = 14, ++ _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, ++ _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, ++ _RSON_DIFF_IE_ = 17, ++ _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, ++ _RSON_UNICST_CIPHER_NOT_VALID_ = 19, ++ _RSON_AKMP_NOT_VALID_ = 20, ++ _RSON_UNSUPPORT_RSNE_VER_ = 21, ++ _RSON_INVALID_RSNE_CAP_ = 22, ++ _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, ++ ++ //belowing are Realtek definition ++ _RSON_PMK_NOT_AVAILABLE_ = 24, ++ _RSON_TDLS_TEAR_TOOFAR_ = 25, ++ _RSON_TDLS_TEAR_UN_RSN_ = 26, ++}; ++ ++/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */ ++#if 0 ++#define WLAN_REASON_UNSPECIFIED 1 ++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 ++#define WLAN_REASON_DEAUTH_LEAVING 3 ++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 ++#define WLAN_REASON_DISASSOC_AP_BUSY 5 ++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 ++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 ++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 ++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 ++#endif ++/* IEEE 802.11h */ ++#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 ++#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 ++#if 0 ++/* IEEE 802.11i */ ++#define WLAN_REASON_INVALID_IE 13 ++#define WLAN_REASON_MICHAEL_MIC_FAILURE 14 ++#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 ++#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 ++#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 ++#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 ++#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 ++#define WLAN_REASON_AKMP_NOT_VALID 20 ++#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 ++#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 ++#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 ++#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 ++#endif ++ ++enum WIFI_STATUS_CODE { ++ _STATS_SUCCESSFUL_ = 0, ++ _STATS_FAILURE_ = 1, ++ _STATS_CAP_FAIL_ = 10, ++ _STATS_NO_ASOC_ = 11, ++ _STATS_OTHER_ = 12, ++ _STATS_NO_SUPP_ALG_ = 13, ++ _STATS_OUT_OF_AUTH_SEQ_ = 14, ++ _STATS_CHALLENGE_FAIL_ = 15, ++ _STATS_AUTH_TIMEOUT_ = 16, ++ _STATS_UNABLE_HANDLE_STA_ = 17, ++ _STATS_RATE_FAIL_ = 18, ++}; ++ ++/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */ ++#if 0 ++#define WLAN_STATUS_SUCCESS 0 ++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 ++#define WLAN_STATUS_CAPS_UNSUPPORTED 10 ++#define WLAN_STATUS_REASSOC_NO_ASSOC 11 ++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 ++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 ++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 ++#define WLAN_STATUS_CHALLENGE_FAIL 15 ++#define WLAN_STATUS_AUTH_TIMEOUT 16 ++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 ++#define WLAN_STATUS_ASSOC_DENIED_RATES 18 ++#endif ++//entended ++/* IEEE 802.11b */ ++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 ++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 ++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 ++/* IEEE 802.11h */ ++#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22 ++#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23 ++#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24 ++/* IEEE 802.11g */ ++#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25 ++#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26 ++#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27 ++/* IEEE 802.11w */ ++#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30 ++#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31 ++/* IEEE 802.11i */ ++#define WLAN_STATUS_INVALID_IE 40 ++#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41 ++#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42 ++#define WLAN_STATUS_AKMP_NOT_VALID 43 ++#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44 ++#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45 ++#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46 ++#define WLAN_STATUS_TS_NOT_CREATED 47 ++#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48 ++#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49 ++#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50 ++#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51 ++/* IEEE 802.11r */ ++#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52 ++#define WLAN_STATUS_INVALID_PMKID 53 ++#define WLAN_STATUS_INVALID_MDIE 54 ++#define WLAN_STATUS_INVALID_FTIE 55 ++ ++ ++enum WIFI_REG_DOMAIN { ++ DOMAIN_FCC = 1, ++ DOMAIN_IC = 2, ++ DOMAIN_ETSI = 3, ++ DOMAIN_SPAIN = 4, ++ DOMAIN_FRANCE = 5, ++ DOMAIN_MKK = 6, ++ DOMAIN_ISRAEL = 7, ++ DOMAIN_MKK1 = 8, ++ DOMAIN_MKK2 = 9, ++ DOMAIN_MKK3 = 10, ++ DOMAIN_MAX ++}; ++ ++#define _TO_DS_ BIT(8) ++#define _FROM_DS_ BIT(9) ++#define _MORE_FRAG_ BIT(10) ++#define _RETRY_ BIT(11) ++#define _PWRMGT_ BIT(12) ++#define _MORE_DATA_ BIT(13) ++#define _PRIVACY_ BIT(14) ++#define _ORDER_ BIT(15) ++ ++#define SetToDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \ ++ } while(0) ++ ++#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0) ++ ++#define ClearToDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \ ++ } while(0) ++ ++#define SetFrDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \ ++ } while(0) ++ ++#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0) ++ ++#define ClearFrDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ ++ } while(0) ++ ++#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) ++ ++ ++#define SetMFrag(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ ++ } while(0) ++ ++#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0) ++ ++#define ClearMFrag(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \ ++ } while(0) ++ ++#define SetRetry(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \ ++ } while(0) ++ ++#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0) ++ ++#define ClearRetry(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \ ++ } while(0) ++ ++#define SetPwrMgt(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \ ++ } while(0) ++ ++#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0) ++ ++#define ClearPwrMgt(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \ ++ } while(0) ++ ++#define SetMData(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \ ++ } while(0) ++ ++#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0) ++ ++#define ClearMData(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \ ++ } while(0) ++ ++#define SetPrivacy(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \ ++ } while(0) ++ ++#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0) ++ ++#define ClearPrivacy(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \ ++ } while(0) ++ ++ ++#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) ++ ++#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2))) ++ ++#define SetFrameType(pbuf,type) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \ ++ *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ ++ } while(0) ++ ++#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) ++ ++#define SetFrameSubType(pbuf,type) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ ++ } while(0) ++ ++#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) ++ ++#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) ++ ++#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22))) ++ ++#define SetFragNum(pbuf, num) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ ++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ ++ cpu_to_le16(0x0f & (num)); \ ++ } while(0) ++ ++#define SetSeqNum(pbuf, num) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ ++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \ ++ le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ ++ } while(0) ++ ++#define SetDuration(pbuf, dur) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ ++ } while(0) ++ ++ ++#define SetPriority(pbuf, tid) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ ++ } while(0) ++ ++#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) ++ ++#define SetEOSP(pbuf, eosp) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (eosp & 1) << 4); \ ++ } while(0) ++ ++#define SetAckpolicy(pbuf, ack) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (ack & 3) << 5); \ ++ } while(0) ++ ++#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) ++ ++#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) ++ ++#define SetAMsdu(pbuf, amsdu) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (amsdu & 1) << 7); \ ++ } while(0) ++ ++#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) ++ ++#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1)|GetFrDs(pbuf))==3?30:24))) & 0x000f) ++ ++#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) ++ ++#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) ++ ++#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) ++ ++#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) ++ ++#define MacAddr_isBcst(addr) \ ++( \ ++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ ++ (addr[2] == 0xff) && (addr[3] == 0xff) && \ ++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ ++) ++ ++__inline static int IS_MCAST(unsigned char *da) ++{ ++ if ((*da) & 0x01) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++ ++__inline static unsigned char * get_da(unsigned char *pframe) ++{ ++ unsigned char *da; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ da = GetAddr1Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ da = GetAddr1Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ da = GetAddr3Ptr(pframe); ++ break; ++ default: // ToDs=1, FromDs=1 ++ da = GetAddr3Ptr(pframe); ++ break; ++ } ++ ++ return da; ++} ++ ++ ++__inline static unsigned char * get_sa(unsigned char *pframe) ++{ ++ unsigned char *sa; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ sa = GetAddr3Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ default: // ToDs=1, FromDs=1 ++ sa = GetAddr4Ptr(pframe); ++ break; ++ } ++ ++ return sa; ++} ++ ++__inline static unsigned char * get_hdr_bssid(unsigned char *pframe) ++{ ++ unsigned char *sa; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ sa = GetAddr3Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ sa = GetAddr1Ptr(pframe); ++ break; ++ case 0x03: // ToDs=1, FromDs=1 ++ sa = GetAddr1Ptr(pframe); ++ break; ++ default: ++ sa =NULL; //??????? ++ break; ++ } ++ ++ return sa; ++} ++ ++ ++__inline static int IsFrameTypeCtrl(unsigned char *pframe) ++{ ++ if(WIFI_CTRL_TYPE == GetFrameType(pframe)) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++/*----------------------------------------------------------------------------- ++ Below is for the security related definition ++------------------------------------------------------------------------------*/ ++#define _RESERVED_FRAME_TYPE_ 0 ++#define _SKB_FRAME_TYPE_ 2 ++#define _PRE_ALLOCMEM_ 1 ++#define _PRE_ALLOCHDR_ 3 ++#define _PRE_ALLOCLLCHDR_ 4 ++#define _PRE_ALLOCICVHDR_ 5 ++#define _PRE_ALLOCMICHDR_ 6 ++ ++#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A)?16:10) ++#define _ACKCTSLNG_ 14 //14 bytes long, including crclng ++#define _CRCLNG_ 4 ++ ++#define _ASOCREQ_IE_OFFSET_ 4 // excluding wlan_hdr ++#define _ASOCRSP_IE_OFFSET_ 6 ++#define _REASOCREQ_IE_OFFSET_ 10 ++#define _REASOCRSP_IE_OFFSET_ 6 ++#define _PROBEREQ_IE_OFFSET_ 0 ++#define _PROBERSP_IE_OFFSET_ 12 ++#define _AUTH_IE_OFFSET_ 6 ++#define _DEAUTH_IE_OFFSET_ 0 ++#define _BEACON_IE_OFFSET_ 12 ++#define _PUBLIC_ACTION_IE_OFFSET_ 8 ++ ++#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ ++ ++#define _SSID_IE_ 0 ++#define _SUPPORTEDRATES_IE_ 1 ++#define _DSSET_IE_ 3 ++#define _TIM_IE_ 5 ++#define _IBSS_PARA_IE_ 6 ++#define _COUNTRY_IE_ 7 ++#define _CHLGETXT_IE_ 16 ++#define _SUPPORTED_CH_IE_ 36 ++#define _CH_SWTICH_ANNOUNCE_ 37 //Secondary Channel Offset ++#define _RSN_IE_2_ 48 ++#define _SSN_IE_1_ 221 ++#define _ERPINFO_IE_ 42 ++#define _EXT_SUPPORTEDRATES_IE_ 50 ++ ++#define _HT_CAPABILITY_IE_ 45 ++#define _FTIE_ 55 ++#define _TIMEOUT_ITVL_IE_ 56 ++#define _SRC_IE_ 59 ++#define _HT_EXTRA_INFO_IE_ 61 ++#define _HT_ADD_INFO_IE_ 61 //_HT_EXTRA_INFO_IE_ ++#define _WAPI_IE_ 68 ++ ++ ++#define EID_BSSCoexistence 72 // 20/40 BSS Coexistence ++#define EID_BSSIntolerantChlReport 73 ++#define _RIC_Descriptor_IE_ 75 ++#ifdef CONFIG_IEEE80211W ++#define _MME_IE_ 76 //802.11w Management MIC element ++#endif //CONFIG_IEEE80211W ++#define _LINK_ID_IE_ 101 ++#define _CH_SWITCH_TIMING_ 104 ++#define _PTI_BUFFER_STATUS_ 106 ++#define _EXT_CAP_IE_ 127 ++#define _VENDOR_SPECIFIC_IE_ 221 ++ ++#define _RESERVED47_ 47 ++ ++/* --------------------------------------------------------------------------- ++ Below is the fixed elements... ++-----------------------------------------------------------------------------*/ ++#define _AUTH_ALGM_NUM_ 2 ++#define _AUTH_SEQ_NUM_ 2 ++#define _BEACON_ITERVAL_ 2 ++#define _CAPABILITY_ 2 ++#define _CURRENT_APADDR_ 6 ++#define _LISTEN_INTERVAL_ 2 ++#define _RSON_CODE_ 2 ++#define _ASOC_ID_ 2 ++#define _STATUS_CODE_ 2 ++#define _TIMESTAMP_ 8 ++ ++#define AUTH_ODD_TO 0 ++#define AUTH_EVEN_TO 1 ++ ++#define WLAN_ETHCONV_ENCAP 1 ++#define WLAN_ETHCONV_RFC1042 2 ++#define WLAN_ETHCONV_8021h 3 ++ ++#define cap_ESS BIT(0) ++#define cap_IBSS BIT(1) ++#define cap_CFPollable BIT(2) ++#define cap_CFRequest BIT(3) ++#define cap_Privacy BIT(4) ++#define cap_ShortPremble BIT(5) ++#define cap_PBCC BIT(6) ++#define cap_ChAgility BIT(7) ++#define cap_SpecMgmt BIT(8) ++#define cap_QoS BIT(9) ++#define cap_ShortSlot BIT(10) ++ ++/*----------------------------------------------------------------------------- ++ Below is the definition for 802.11i / 802.1x ++------------------------------------------------------------------------------*/ ++#define _IEEE8021X_MGT_ 1 // WPA ++#define _IEEE8021X_PSK_ 2 // WPA with pre-shared key ++ ++/* ++#define _NO_PRIVACY_ 0 ++#define _WEP_40_PRIVACY_ 1 ++#define _TKIP_PRIVACY_ 2 ++#define _WRAP_PRIVACY_ 3 ++#define _CCMP_PRIVACY_ 4 ++#define _WEP_104_PRIVACY_ 5 ++#define _WEP_WPA_MIXED_PRIVACY_ 6 // WEP + WPA ++*/ ++ ++#ifdef CONFIG_IEEE80211W ++#define _MME_IE_LENGTH_ 18 ++#endif //CONFIG_IEEE80211W ++/*----------------------------------------------------------------------------- ++ Below is the definition for WMM ++------------------------------------------------------------------------------*/ ++#define _WMM_IE_Length_ 7 // for WMM STA ++#define _WMM_Para_Element_Length_ 24 ++ ++ ++/*----------------------------------------------------------------------------- ++ Below is the definition for 802.11n ++------------------------------------------------------------------------------*/ ++ ++//#ifdef CONFIG_80211N_HT ++ ++#define SetOrderBit(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ ++ } while(0) ++ ++#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) ++ ++ ++/** ++ * struct rtw_ieee80211_bar - HT Block Ack Request ++ * ++ * This structure refers to "HT BlockAckReq" as ++ * described in 802.11n draft section 7.2.1.7.1 ++ */ ++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) ++struct rtw_ieee80211_bar { ++ unsigned short frame_control; ++ unsigned short duration; ++ unsigned char ra[6]; ++ unsigned char ta[6]; ++ unsigned short control; ++ unsigned short start_seq_num; ++} __attribute__((packed)); ++ #endif ++ ++/* 802.11 BAR control masks */ ++#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 ++#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 ++ ++ ++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) || defined(PLATFORM_FREEBSD) ++ ++ ++ ++ /** ++ * struct rtw_ieee80211_ht_cap - HT capabilities ++ * ++ * This structure refers to "HT capabilities element" as ++ * described in 802.11n draft section 7.3.2.52 ++ */ ++ ++struct rtw_ieee80211_ht_cap { ++ unsigned short cap_info; ++ unsigned char ampdu_params_info; ++ unsigned char supp_mcs_set[16]; ++ unsigned short extended_ht_cap_info; ++ unsigned int tx_BF_cap_info; ++ unsigned char antenna_selection_info; ++} __attribute__ ((packed)); ++ ++/** ++ * struct rtw_ieee80211_ht_cap - HT additional information ++ * ++ * This structure refers to "HT information element" as ++ * described in 802.11n draft section 7.3.2.53 ++ */ ++struct ieee80211_ht_addt_info { ++ unsigned char control_chan; ++ unsigned char ht_param; ++ unsigned short operation_mode; ++ unsigned short stbc_param; ++ unsigned char basic_set[16]; ++} __attribute__ ((packed)); ++ ++ ++struct HT_caps_element ++{ ++ union ++ { ++ struct ++ { ++ unsigned short HT_caps_info; ++ unsigned char AMPDU_para; ++ unsigned char MCS_rate[16]; ++ unsigned short HT_ext_caps; ++ unsigned int Beamforming_caps; ++ unsigned char ASEL_caps; ++ } HT_cap_element; ++ unsigned char HT_cap[26]; ++ }u; ++} __attribute__ ((packed)); ++ ++struct HT_info_element ++{ ++ unsigned char primary_channel; ++ unsigned char infos[5]; ++ unsigned char MCS_rate[16]; ++} __attribute__ ((packed)); ++ ++struct AC_param ++{ ++ unsigned char ACI_AIFSN; ++ unsigned char CW; ++ unsigned short TXOP_limit; ++} __attribute__ ((packed)); ++ ++struct WMM_para_element ++{ ++ unsigned char QoS_info; ++ unsigned char reserved; ++ struct AC_param ac_param[4]; ++} __attribute__ ((packed)); ++ ++struct ADDBA_request ++{ ++ unsigned char dialog_token; ++ unsigned short BA_para_set; ++ unsigned short BA_timeout_value; ++ unsigned short BA_starting_seqctrl; ++} __attribute__ ((packed)); ++ ++ ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct rtw_ieee80211_ht_cap { ++ unsigned short cap_info; ++ unsigned char ampdu_params_info; ++ unsigned char supp_mcs_set[16]; ++ unsigned short extended_ht_cap_info; ++ unsigned int tx_BF_cap_info; ++ unsigned char antenna_selection_info; ++}; ++ ++ ++struct ieee80211_ht_addt_info { ++ unsigned char control_chan; ++ unsigned char ht_param; ++ unsigned short operation_mode; ++ unsigned short stbc_param; ++ unsigned char basic_set[16]; ++}; ++ ++struct HT_caps_element ++{ ++ union ++ { ++ struct ++ { ++ unsigned short HT_caps_info; ++ unsigned char AMPDU_para; ++ unsigned char MCS_rate[16]; ++ unsigned short HT_ext_caps; ++ unsigned int Beamforming_caps; ++ unsigned char ASEL_caps; ++ } HT_cap_element; ++ unsigned char HT_cap[26]; ++ }; ++}; ++ ++struct HT_info_element ++{ ++ unsigned char primary_channel; ++ unsigned char infos[5]; ++ unsigned char MCS_rate[16]; ++}; ++ ++struct AC_param ++{ ++ unsigned char ACI_AIFSN; ++ unsigned char CW; ++ unsigned short TXOP_limit; ++}; ++ ++struct WMM_para_element ++{ ++ unsigned char QoS_info; ++ unsigned char reserved; ++ struct AC_param ac_param[4]; ++}; ++ ++struct ADDBA_request ++{ ++ unsigned char dialog_token; ++ unsigned short BA_para_set; ++ unsigned short BA_timeout_value; ++ unsigned short BA_starting_seqctrl; ++}; ++ ++ ++#pragma pack() ++ ++#endif ++ ++typedef enum _HT_CAP_AMPDU_FACTOR { ++ MAX_AMPDU_FACTOR_8K = 0, ++ MAX_AMPDU_FACTOR_16K = 1, ++ MAX_AMPDU_FACTOR_32K = 2, ++ MAX_AMPDU_FACTOR_64K = 3, ++}HT_CAP_AMPDU_FACTOR; ++ ++/* 802.11n HT capabilities masks */ ++#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 ++#define IEEE80211_HT_CAP_SM_PS 0x000C ++#define IEEE80211_HT_CAP_GRN_FLD 0x0010 ++#define IEEE80211_HT_CAP_SGI_20 0x0020 ++#define IEEE80211_HT_CAP_SGI_40 0x0040 ++#define IEEE80211_HT_CAP_TX_STBC 0x0080 ++#define IEEE80211_HT_CAP_RX_STBC 0x0300 ++#define IEEE80211_HT_CAP_DELAY_BA 0x0400 ++#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 ++#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 ++/* 802.11n HT capability AMPDU settings */ ++#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 ++#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C ++/* 802.11n HT capability MSC set */ ++#define IEEE80211_SUPP_MCS_SET_UEQM 4 ++#define IEEE80211_HT_CAP_MAX_STREAMS 4 ++#define IEEE80211_SUPP_MCS_SET_LEN 10 ++/* maximum streams the spec allows */ ++#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 ++#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 ++#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C ++#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 ++/* 802.11n HT IE masks */ ++#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 ++#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 ++#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 ++#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 ++#define IEEE80211_HT_IE_CHA_WIDTH 0x04 ++#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 ++#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 ++#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 ++ ++/* block-ack parameters */ ++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 ++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C ++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 ++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 ++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 ++ ++/* ++ * A-PMDU buffer sizes ++ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) ++ */ ++#define IEEE80211_MIN_AMPDU_BUF 0x8 ++#define IEEE80211_MAX_AMPDU_BUF 0x40 ++ ++ ++/* Spatial Multiplexing Power Save Modes */ ++#define WLAN_HT_CAP_SM_PS_STATIC 0 ++#define WLAN_HT_CAP_SM_PS_DYNAMIC 1 ++#define WLAN_HT_CAP_SM_PS_INVALID 2 ++#define WLAN_HT_CAP_SM_PS_DISABLED 3 ++ ++ ++#define OP_MODE_PURE 0 ++#define OP_MODE_MAY_BE_LEGACY_STAS 1 ++#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 ++#define OP_MODE_MIXED 3 ++ ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) ++#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) ++#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) ++#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) ++#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) ++ ++#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ ++ ((u16) (0x0001 | 0x0002)) ++#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 ++#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) ++#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) ++#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) ++ ++#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) ++#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) ++#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) ++#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) ++#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) ++#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) ++ ++ ++ ++//#endif ++ ++// ===============WPS Section=============== ++// For WPSv1.0 ++#define WPSOUI 0x0050f204 ++// WPS attribute ID ++#define WPS_ATTR_VER1 0x104A ++#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 ++#define WPS_ATTR_RESP_TYPE 0x103B ++#define WPS_ATTR_UUID_E 0x1047 ++#define WPS_ATTR_MANUFACTURER 0x1021 ++#define WPS_ATTR_MODEL_NAME 0x1023 ++#define WPS_ATTR_MODEL_NUMBER 0x1024 ++#define WPS_ATTR_SERIAL_NUMBER 0x1042 ++#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 ++#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 ++#define WPS_ATTR_DEVICE_NAME 0x1011 ++#define WPS_ATTR_CONF_METHOD 0x1008 ++#define WPS_ATTR_RF_BANDS 0x103C ++#define WPS_ATTR_DEVICE_PWID 0x1012 ++#define WPS_ATTR_REQUEST_TYPE 0x103A ++#define WPS_ATTR_ASSOCIATION_STATE 0x1002 ++#define WPS_ATTR_CONFIG_ERROR 0x1009 ++#define WPS_ATTR_VENDOR_EXT 0x1049 ++#define WPS_ATTR_SELECTED_REGISTRAR 0x1041 ++ ++// Value of WPS attribute "WPS_ATTR_DEVICE_NAME ++#define WPS_MAX_DEVICE_NAME_LEN 32 ++ ++// Value of WPS Request Type Attribute ++#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 ++#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 ++#define WPS_REQ_TYPE_REGISTRAR 0x02 ++#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 ++ ++// Value of WPS Response Type Attribute ++#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 ++#define WPS_RESPONSE_TYPE_8021X 0x01 ++#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 ++#define WPS_RESPONSE_TYPE_AP 0x03 ++ ++// Value of WPS WiFi Simple Configuration State Attribute ++#define WPS_WSC_STATE_NOT_CONFIG 0x01 ++#define WPS_WSC_STATE_CONFIG 0x02 ++ ++// Value of WPS Version Attribute ++#define WPS_VERSION_1 0x10 ++ ++// Value of WPS Configuration Method Attribute ++#define WPS_CONFIG_METHOD_FLASH 0x0001 ++#define WPS_CONFIG_METHOD_ETHERNET 0x0002 ++#define WPS_CONFIG_METHOD_LABEL 0x0004 ++#define WPS_CONFIG_METHOD_DISPLAY 0x0008 ++#define WPS_CONFIG_METHOD_E_NFC 0x0010 ++#define WPS_CONFIG_METHOD_I_NFC 0x0020 ++#define WPS_CONFIG_METHOD_NFC 0x0040 ++#define WPS_CONFIG_METHOD_PBC 0x0080 ++#define WPS_CONFIG_METHOD_KEYPAD 0x0100 ++#define WPS_CONFIG_METHOD_VPBC 0x0280 ++#define WPS_CONFIG_METHOD_PPBC 0x0480 ++#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 ++#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 ++ ++// Value of Category ID of WPS Primary Device Type Attribute ++#define WPS_PDT_CID_DISPLAYS 0x0007 ++#define WPS_PDT_CID_MULIT_MEDIA 0x0008 ++#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA ++ ++// Value of Sub Category ID of WPS Primary Device Type Attribute ++#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 ++#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER ++ ++// Value of Device Password ID ++#define WPS_DPID_PIN 0x0000 ++#define WPS_DPID_USER_SPEC 0x0001 ++#define WPS_DPID_MACHINE_SPEC 0x0002 ++#define WPS_DPID_REKEY 0x0003 ++#define WPS_DPID_PBC 0x0004 ++#define WPS_DPID_REGISTRAR_SPEC 0x0005 ++ ++// Value of WPS RF Bands Attribute ++#define WPS_RF_BANDS_2_4_GHZ 0x01 ++#define WPS_RF_BANDS_5_GHZ 0x02 ++ ++// Value of WPS Association State Attribute ++#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 ++#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 ++#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 ++#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 ++#define WPS_ASSOC_STATE_IP_FAILURE 0x04 ++ ++// =====================P2P Section===================== ++// For P2P ++#define P2POUI 0x506F9A09 ++ ++// P2P Attribute ID ++#define P2P_ATTR_STATUS 0x00 ++#define P2P_ATTR_MINOR_REASON_CODE 0x01 ++#define P2P_ATTR_CAPABILITY 0x02 ++#define P2P_ATTR_DEVICE_ID 0x03 ++#define P2P_ATTR_GO_INTENT 0x04 ++#define P2P_ATTR_CONF_TIMEOUT 0x05 ++#define P2P_ATTR_LISTEN_CH 0x06 ++#define P2P_ATTR_GROUP_BSSID 0x07 ++#define P2P_ATTR_EX_LISTEN_TIMING 0x08 ++#define P2P_ATTR_INTENTED_IF_ADDR 0x09 ++#define P2P_ATTR_MANAGEABILITY 0x0A ++#define P2P_ATTR_CH_LIST 0x0B ++#define P2P_ATTR_NOA 0x0C ++#define P2P_ATTR_DEVICE_INFO 0x0D ++#define P2P_ATTR_GROUP_INFO 0x0E ++#define P2P_ATTR_GROUP_ID 0x0F ++#define P2P_ATTR_INTERFACE 0x10 ++#define P2P_ATTR_OPERATING_CH 0x11 ++#define P2P_ATTR_INVITATION_FLAGS 0x12 ++ ++// Value of Status Attribute ++#define P2P_STATUS_SUCCESS 0x00 ++#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 ++#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 ++#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 ++#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 ++#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 ++#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 ++#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 ++#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 ++#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 ++#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A ++#define P2P_STATUS_FAIL_USER_REJECT 0x0B ++ ++// Value of Inviation Flags Attribute ++#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) ++ ++#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ ++ P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ ++ P2P_DEVCAP_CONCURRENT_OPERATION | \ ++ P2P_DEVCAP_INVITATION_PROC) ++ ++#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) ++ ++// Value of Device Capability Bitmap ++#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) ++#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) ++#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) ++#define P2P_DEVCAP_INFRA_MANAGED BIT(3) ++#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) ++#define P2P_DEVCAP_INVITATION_PROC BIT(5) ++ ++// Value of Group Capability Bitmap ++#define P2P_GRPCAP_GO BIT(0) ++#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) ++#define P2P_GRPCAP_GROUP_LIMIT BIT(2) ++#define P2P_GRPCAP_INTRABSS BIT(3) ++#define P2P_GRPCAP_CROSS_CONN BIT(4) ++#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) ++#define P2P_GRPCAP_GROUP_FORMATION BIT(6) ++ ++// P2P Public Action Frame ( Management Frame ) ++#define P2P_PUB_ACTION_ACTION 0x09 ++ ++// P2P Public Action Frame Type ++#define P2P_GO_NEGO_REQ 0 ++#define P2P_GO_NEGO_RESP 1 ++#define P2P_GO_NEGO_CONF 2 ++#define P2P_INVIT_REQ 3 ++#define P2P_INVIT_RESP 4 ++#define P2P_DEVDISC_REQ 5 ++#define P2P_DEVDISC_RESP 6 ++#define P2P_PROVISION_DISC_REQ 7 ++#define P2P_PROVISION_DISC_RESP 8 ++ ++// P2P Action Frame Type ++#define P2P_NOTICE_OF_ABSENCE 0 ++#define P2P_PRESENCE_REQUEST 1 ++#define P2P_PRESENCE_RESPONSE 2 ++#define P2P_GO_DISC_REQUEST 3 ++ ++ ++#define P2P_MAX_PERSISTENT_GROUP_NUM 10 ++ ++#define P2P_PROVISIONING_SCAN_CNT 3 ++ ++#define P2P_WILDCARD_SSID_LEN 7 ++ ++#define P2P_FINDPHASE_EX_NONE 0 // default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase ++#define P2P_FINDPHASE_EX_FULL 1 // used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase ++#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) ++#define P2P_FINDPHASE_EX_MAX 4 ++#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX ++ ++#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request ++#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode ++#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response ++#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode ++#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms ++#define P2P_INVITE_TIMEOUT 5000 // 5 seconds timeout for sending the invitation request ++#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 // 3 seconds timeout for sending the invitation request under concurrent mode ++#define P2P_RESET_SCAN_CH 25000 // 25 seconds timeout to reset the scan channel ( based on channel plan ) ++#define P2P_MAX_INTENT 15 ++ ++#define P2P_MAX_NOA_NUM 2 ++ ++// WPS Configuration Method ++#define WPS_CM_NONE 0x0000 ++#define WPS_CM_LABEL 0x0004 ++#define WPS_CM_DISPLYA 0x0008 ++#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 ++#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 ++#define WPS_CM_NFC_INTERFACE 0x0040 ++#define WPS_CM_PUSH_BUTTON 0x0080 ++#define WPS_CM_KEYPAD 0x0100 ++#define WPS_CM_SW_PUHS_BUTTON 0x0280 ++#define WPS_CM_HW_PUHS_BUTTON 0x0480 ++#define WPS_CM_SW_DISPLAY_PIN 0x2008 ++#define WPS_CM_LCD_DISPLAY_PIN 0x4008 ++ ++enum P2P_ROLE { ++ P2P_ROLE_DISABLE = 0, ++ P2P_ROLE_DEVICE = 1, ++ P2P_ROLE_CLIENT = 2, ++ P2P_ROLE_GO = 3 ++}; ++ ++enum P2P_STATE { ++ P2P_STATE_NONE = 0, // P2P disable ++ P2P_STATE_IDLE = 1, // P2P had enabled and do nothing ++ P2P_STATE_LISTEN = 2, // In pure listen state ++ P2P_STATE_SCAN = 3, // In scan phase ++ P2P_STATE_FIND_PHASE_LISTEN = 4, // In the listen state of find phase ++ P2P_STATE_FIND_PHASE_SEARCH = 5, // In the search state of find phase ++ P2P_STATE_TX_PROVISION_DIS_REQ = 6, // In P2P provisioning discovery ++ P2P_STATE_RX_PROVISION_DIS_RSP = 7, ++ P2P_STATE_RX_PROVISION_DIS_REQ = 8, ++ P2P_STATE_GONEGO_ING = 9, // Doing the group owner negoitation handshake ++ P2P_STATE_GONEGO_OK = 10, // finish the group negoitation handshake with success ++ P2P_STATE_GONEGO_FAIL = 11, // finish the group negoitation handshake with failure ++ P2P_STATE_RECV_INVITE_REQ_MATCH = 12, // receiving the P2P Inviation request and match with the profile. ++ P2P_STATE_PROVISIONING_ING = 13, // Doing the P2P WPS ++ P2P_STATE_PROVISIONING_DONE = 14, // Finish the P2P WPS ++ P2P_STATE_TX_INVITE_REQ = 15, // Transmit the P2P Invitation request ++ P2P_STATE_RX_INVITE_RESP_OK = 16, // Receiving the P2P Invitation response ++ P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, // receiving the P2P Inviation request and dismatch with the profile. ++ P2P_STATE_RECV_INVITE_REQ_GO = 18, // receiving the P2P Inviation request and this wifi is GO. ++ P2P_STATE_RECV_INVITE_REQ_JOIN = 19, // receiving the P2P Inviation request to join an existing P2P Group. ++ P2P_STATE_RX_INVITE_RESP_FAIL = 20, // recveing the P2P Inviation response with failure ++ P2P_STATE_RX_INFOR_NOREADY = 21, // receiving p2p negoitation response with information is not available ++ P2P_STATE_TX_INFOR_NOREADY = 22, // sending p2p negoitation response with information is not available ++}; ++ ++enum P2P_WPSINFO { ++ P2P_NO_WPSINFO = 0, ++ P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, ++ P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, ++ P2P_GOT_WPSINFO_PBC = 3, ++}; ++ ++#define P2P_PRIVATE_IOCTL_SET_LEN 64 ++ ++enum P2P_PROTO_WK_ID ++{ ++ P2P_FIND_PHASE_WK = 0, ++ P2P_RESTORE_STATE_WK = 1, ++ P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, ++ P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, ++ P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, ++ P2P_AP_P2P_CH_SWITCH_PROCESS_WK =5, ++ P2P_RO_CH_WK = 6, ++}; ++ ++#ifdef CONFIG_P2P_PS ++enum P2P_PS_STATE ++{ ++ P2P_PS_DISABLE = 0, ++ P2P_PS_ENABLE = 1, ++ P2P_PS_SCAN = 2, ++ P2P_PS_SCAN_DONE = 3, ++ P2P_PS_ALLSTASLEEP = 4, // for P2P GO ++}; ++ ++enum P2P_PS_MODE ++{ ++ P2P_PS_NONE = 0, ++ P2P_PS_CTWINDOW = 1, ++ P2P_PS_NOA = 2, ++ P2P_PS_MIX = 3, // CTWindow and NoA ++}; ++#endif // CONFIG_P2P_PS ++ ++// =====================WFD Section===================== ++// For Wi-Fi Display ++#define WFD_ATTR_DEVICE_INFO 0x00 ++#define WFD_ATTR_ASSOC_BSSID 0x01 ++#define WFD_ATTR_COUPLED_SINK_INFO 0x06 ++#define WFD_ATTR_LOCAL_IP_ADDR 0x08 ++#define WFD_ATTR_SESSION_INFO 0x09 ++#define WFD_ATTR_ALTER_MAC 0x0a ++ ++// For WFD Device Information Attribute ++#define WFD_DEVINFO_SOURCE 0x0000 ++#define WFD_DEVINFO_PSINK 0x0001 ++#define WFD_DEVINFO_SSINK 0x0002 ++#define WFD_DEVINFO_DUAL 0x0003 ++ ++#define WFD_DEVINFO_SESSION_AVAIL 0x0010 ++#define WFD_DEVINFO_WSD 0x0040 ++#define WFD_DEVINFO_PC_TDLS 0x0080 ++#define WFD_DEVINFO_HDCP_SUPPORT 0x0100 ++ ++#ifdef CONFIG_TX_MCAST2UNI ++#define IP_MCAST_MAC(mac) ((mac[0]==0x01)&&(mac[1]==0x00)&&(mac[2]==0x5e)) ++#define ICMPV6_MCAST_MAC(mac) ((mac[0]==0x33)&&(mac[1]==0x33)&&(mac[2]!=0xff)) ++#endif // CONFIG_TX_MCAST2UNI ++ ++ ++ ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef IW_AUTH_WAPI_VERSION_1 ++#define IW_AUTH_WAPI_VERSION_1 0x00000008 ++#endif ++#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK ++#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 ++#endif ++#ifndef IW_AUTH_WAPI_ENABLED ++#define IW_AUTH_WAPI_ENABLED 0x20 ++#endif ++#ifndef IW_ENCODE_ALG_SM4 ++#define IW_ENCODE_ALG_SM4 0x20 ++#endif ++#endif ++ ++#endif // _WIFI_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/wlan_bssdef.h b/drivers/net/wireless/rtl818x/rtl8189/include/wlan_bssdef.h +new file mode 100644 +index 00000000..dac17a05 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/wlan_bssdef.h +@@ -0,0 +1,741 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __WLAN_BSSDEF_H__ ++#define __WLAN_BSSDEF_H__ ++ ++ ++#define MAX_IE_SZ 768 ++ ++ ++#ifdef PLATFORM_LINUX ++ ++#define NDIS_802_11_LENGTH_SSID 32 ++#define NDIS_802_11_LENGTH_RATES 8 ++#define NDIS_802_11_LENGTH_RATES_EX 16 ++ ++typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; ++typedef long NDIS_802_11_RSSI; // in dBm ++typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates ++typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates ++ ++ ++typedef ULONG NDIS_802_11_KEY_INDEX; ++typedef unsigned long long NDIS_802_11_KEY_RSC; ++ ++ ++typedef struct _NDIS_802_11_SSID ++{ ++ ULONG SsidLength; ++ UCHAR Ssid[32]; ++} NDIS_802_11_SSID, *PNDIS_802_11_SSID; ++ ++typedef enum _NDIS_802_11_NETWORK_TYPE ++{ ++ Ndis802_11FH, ++ Ndis802_11DS, ++ Ndis802_11OFDM5, ++ Ndis802_11OFDM24, ++ Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; ++ ++typedef struct _NDIS_802_11_CONFIGURATION_FH ++{ ++ ULONG Length; // Length of structure ++ ULONG HopPattern; // As defined by 802.11, MSB set ++ ULONG HopSet; // to one if non-802.11 ++ ULONG DwellTime; // units are Kusec ++} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; ++ ++ ++/* ++ FW will only save the channel number in DSConfig. ++ ODI Handler will convert the channel number to freq. number. ++*/ ++typedef struct _NDIS_802_11_CONFIGURATION ++{ ++ ULONG Length; // Length of structure ++ ULONG BeaconPeriod; // units are Kusec ++ ULONG ATIMWindow; // units are Kusec ++ ULONG DSConfig; // Frequency, units are kHz ++ NDIS_802_11_CONFIGURATION_FH FHConfig; ++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; ++ ++ ++ ++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE ++{ ++ Ndis802_11IBSS, ++ Ndis802_11Infrastructure, ++ Ndis802_11AutoUnknown, ++ Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound ++ Ndis802_11APMode ++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; ++ ++ ++ ++ ++ ++typedef struct _NDIS_802_11_FIXED_IEs ++{ ++ UCHAR Timestamp[8]; ++ USHORT BeaconInterval; ++ USHORT Capabilities; ++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; ++ ++ ++ ++typedef struct _NDIS_802_11_VARIABLE_IEs ++{ ++ UCHAR ElementID; ++ UCHAR Length; ++ UCHAR data[1]; ++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; ++ ++ ++ ++/* ++ ++ ++ ++Length is the 4 bytes multiples of the sume of ++ sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) +++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) +++ sizeof (NDIS_802_11_RATES_EX) + IELength ++ ++Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the ++partial sum. ++ ++*/ ++#if 0 ++typedef struct _NDIS_WLAN_BSSID_EX ++{ ++ ULONG Length; ++ NDIS_802_11_MAC_ADDRESS MacAddress; ++ UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; ++ NDIS_802_11_SSID Ssid; ++ ULONG Privacy; ++ NDIS_802_11_RSSI Rssi; ++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; ++ NDIS_802_11_CONFIGURATION Configuration; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; ++ NDIS_802_11_RATES_EX SupportedRates; ++ ULONG IELength; ++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) ++} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; ++ ++ ++typedef struct _NDIS_802_11_BSSID_LIST_EX ++{ ++ ULONG NumberOfItems; ++ NDIS_WLAN_BSSID_EX Bssid[1]; ++} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; ++#endif ++ ++typedef enum _NDIS_802_11_AUTHENTICATION_MODE ++{ ++ Ndis802_11AuthModeOpen, ++ Ndis802_11AuthModeShared, ++ Ndis802_11AuthModeAutoSwitch, ++ Ndis802_11AuthModeWPA, ++ Ndis802_11AuthModeWPAPSK, ++ Ndis802_11AuthModeWPANone, ++ Ndis802_11AuthModeWAPI, ++ Ndis802_11AuthModeMax // Not a real mode, defined as upper bound ++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; ++ ++typedef enum _NDIS_802_11_WEP_STATUS ++{ ++ Ndis802_11WEPEnabled, ++ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, ++ Ndis802_11WEPDisabled, ++ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, ++ Ndis802_11WEPKeyAbsent, ++ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, ++ Ndis802_11WEPNotSupported, ++ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, ++ Ndis802_11Encryption2Enabled, ++ Ndis802_11Encryption2KeyAbsent, ++ Ndis802_11Encryption3Enabled, ++ Ndis802_11Encryption3KeyAbsent, ++ Ndis802_11_EncrypteionWAPI ++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, ++ NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; ++ ++ ++#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 ++#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 ++ ++#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_RESFI_STATUSCODE 2 ++#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 ++ ++typedef struct _NDIS_802_11_AI_REQFI ++{ ++ USHORT Capabilities; ++ USHORT ListenInterval; ++ NDIS_802_11_MAC_ADDRESS CurrentAPAddress; ++} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; ++ ++typedef struct _NDIS_802_11_AI_RESFI ++{ ++ USHORT Capabilities; ++ USHORT StatusCode; ++ USHORT AssociationId; ++} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; ++ ++typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION ++{ ++ ULONG Length; ++ USHORT AvailableRequestFixedIEs; ++ NDIS_802_11_AI_REQFI RequestFixedIEs; ++ ULONG RequestIELength; ++ ULONG OffsetRequestIEs; ++ USHORT AvailableResponseFixedIEs; ++ NDIS_802_11_AI_RESFI ResponseFixedIEs; ++ ULONG ResponseIELength; ++ ULONG OffsetResponseIEs; ++} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; ++ ++typedef enum _NDIS_802_11_RELOAD_DEFAULTS ++{ ++ Ndis802_11ReloadWEPKeys ++} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; ++ ++ ++// Key mapping keys require a BSSID ++typedef struct _NDIS_802_11_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ ULONG KeyLength; // length of key in bytes ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ NDIS_802_11_KEY_RSC KeyRSC; ++ UCHAR KeyMaterial[32]; // variable length depending on above field ++} NDIS_802_11_KEY, *PNDIS_802_11_KEY; ++ ++typedef struct _NDIS_802_11_REMOVE_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ NDIS_802_11_MAC_ADDRESS BSSID; ++} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; ++ ++typedef struct _NDIS_802_11_WEP ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys ++ ULONG KeyLength; // length of key in bytes ++ UCHAR KeyMaterial[16];// variable length depending on above field ++} NDIS_802_11_WEP, *PNDIS_802_11_WEP; ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST ++{ ++ ULONG Length; // Length of structure ++ NDIS_802_11_MAC_ADDRESS Bssid; ++ ULONG Flags; ++} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; ++ ++typedef enum _NDIS_802_11_STATUS_TYPE ++{ ++ Ndis802_11StatusType_Authentication, ++ Ndis802_11StatusType_MediaStreamMode, ++ Ndis802_11StatusType_PMKID_CandidateList, ++ Ndis802_11StatusTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; ++ ++typedef struct _NDIS_802_11_STATUS_INDICATION ++{ ++ NDIS_802_11_STATUS_TYPE StatusType; ++} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; ++ ++// mask for authentication/integrity fields ++#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f ++#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 ++#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 ++#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 ++#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E ++ ++// MIC check time, 60 seconds. ++#define MIC_CHECK_TIME 60000000 ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_EVENT ++{ ++ NDIS_802_11_STATUS_INDICATION Status; ++ NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; ++} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; ++ ++typedef struct _NDIS_802_11_TEST ++{ ++ ULONG Length; ++ ULONG Type; ++ union ++ { ++ NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; ++ NDIS_802_11_RSSI RssiTrigger; ++ }tt; ++} NDIS_802_11_TEST, *PNDIS_802_11_TEST; ++ ++ ++#endif //end of #ifdef PLATFORM_LINUX ++ ++#ifdef PLATFORM_FREEBSD ++ ++#define NDIS_802_11_LENGTH_SSID 32 ++#define NDIS_802_11_LENGTH_RATES 8 ++#define NDIS_802_11_LENGTH_RATES_EX 16 ++ ++typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; ++typedef long NDIS_802_11_RSSI; // in dBm ++typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates ++typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates ++ ++ ++typedef ULONG NDIS_802_11_KEY_INDEX; ++typedef unsigned long long NDIS_802_11_KEY_RSC; ++ ++ ++typedef struct _NDIS_802_11_SSID ++{ ++ ULONG SsidLength; ++ UCHAR Ssid[32]; ++} NDIS_802_11_SSID, *PNDIS_802_11_SSID; ++ ++typedef enum _NDIS_802_11_NETWORK_TYPE ++{ ++ Ndis802_11FH, ++ Ndis802_11DS, ++ Ndis802_11OFDM5, ++ Ndis802_11OFDM24, ++ Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; ++ ++typedef struct _NDIS_802_11_CONFIGURATION_FH ++{ ++ ULONG Length; // Length of structure ++ ULONG HopPattern; // As defined by 802.11, MSB set ++ ULONG HopSet; // to one if non-802.11 ++ ULONG DwellTime; // units are Kusec ++} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; ++ ++ ++/* ++ FW will only save the channel number in DSConfig. ++ ODI Handler will convert the channel number to freq. number. ++*/ ++typedef struct _NDIS_802_11_CONFIGURATION ++{ ++ ULONG Length; // Length of structure ++ ULONG BeaconPeriod; // units are Kusec ++ ULONG ATIMWindow; // units are Kusec ++ ULONG DSConfig; // Frequency, units are kHz ++ NDIS_802_11_CONFIGURATION_FH FHConfig; ++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; ++ ++ ++ ++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE ++{ ++ Ndis802_11IBSS, ++ Ndis802_11Infrastructure, ++ Ndis802_11AutoUnknown, ++ Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound ++ Ndis802_11APMode ++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; ++ ++ ++ ++ ++ ++typedef struct _NDIS_802_11_FIXED_IEs ++{ ++ UCHAR Timestamp[8]; ++ USHORT BeaconInterval; ++ USHORT Capabilities; ++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; ++ ++ ++ ++typedef struct _NDIS_802_11_VARIABLE_IEs ++{ ++ UCHAR ElementID; ++ UCHAR Length; ++ UCHAR data[1]; ++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; ++ ++ ++ ++/* ++ ++ ++ ++Length is the 4 bytes multiples of the sume of ++ sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) +++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) +++ sizeof (NDIS_802_11_RATES_EX) + IELength ++ ++Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the ++partial sum. ++ ++*/ ++#if 0 ++typedef struct _NDIS_WLAN_BSSID_EX ++{ ++ ULONG Length; ++ NDIS_802_11_MAC_ADDRESS MacAddress; ++ UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; ++ NDIS_802_11_SSID Ssid; ++ ULONG Privacy; ++ NDIS_802_11_RSSI Rssi; ++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; ++ NDIS_802_11_CONFIGURATION Configuration; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; ++ NDIS_802_11_RATES_EX SupportedRates; ++ ULONG IELength; ++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) ++} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; ++ ++ ++typedef struct _NDIS_802_11_BSSID_LIST_EX ++{ ++ ULONG NumberOfItems; ++ NDIS_WLAN_BSSID_EX Bssid[1]; ++} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; ++#endif ++ ++typedef enum _NDIS_802_11_AUTHENTICATION_MODE ++{ ++ Ndis802_11AuthModeOpen, ++ Ndis802_11AuthModeShared, ++ Ndis802_11AuthModeAutoSwitch, ++ Ndis802_11AuthModeWPA, ++ Ndis802_11AuthModeWPAPSK, ++ Ndis802_11AuthModeWPANone, ++ Ndis802_11AuthModeMax // Not a real mode, defined as upper bound ++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; ++ ++typedef enum _NDIS_802_11_WEP_STATUS ++{ ++ Ndis802_11WEPEnabled, ++ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, ++ Ndis802_11WEPDisabled, ++ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, ++ Ndis802_11WEPKeyAbsent, ++ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, ++ Ndis802_11WEPNotSupported, ++ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, ++ Ndis802_11Encryption2Enabled, ++ Ndis802_11Encryption2KeyAbsent, ++ Ndis802_11Encryption3Enabled, ++ Ndis802_11Encryption3KeyAbsent ++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, ++ NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; ++ ++ ++#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 ++#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 ++ ++#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_RESFI_STATUSCODE 2 ++#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 ++ ++typedef struct _NDIS_802_11_AI_REQFI ++{ ++ USHORT Capabilities; ++ USHORT ListenInterval; ++ NDIS_802_11_MAC_ADDRESS CurrentAPAddress; ++} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; ++ ++typedef struct _NDIS_802_11_AI_RESFI ++{ ++ USHORT Capabilities; ++ USHORT StatusCode; ++ USHORT AssociationId; ++} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; ++ ++typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION ++{ ++ ULONG Length; ++ USHORT AvailableRequestFixedIEs; ++ NDIS_802_11_AI_REQFI RequestFixedIEs; ++ ULONG RequestIELength; ++ ULONG OffsetRequestIEs; ++ USHORT AvailableResponseFixedIEs; ++ NDIS_802_11_AI_RESFI ResponseFixedIEs; ++ ULONG ResponseIELength; ++ ULONG OffsetResponseIEs; ++} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; ++ ++typedef enum _NDIS_802_11_RELOAD_DEFAULTS ++{ ++ Ndis802_11ReloadWEPKeys ++} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; ++ ++ ++// Key mapping keys require a BSSID ++typedef struct _NDIS_802_11_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ ULONG KeyLength; // length of key in bytes ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ NDIS_802_11_KEY_RSC KeyRSC; ++ UCHAR KeyMaterial[32]; // variable length depending on above field ++} NDIS_802_11_KEY, *PNDIS_802_11_KEY; ++ ++typedef struct _NDIS_802_11_REMOVE_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ NDIS_802_11_MAC_ADDRESS BSSID; ++} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; ++ ++typedef struct _NDIS_802_11_WEP ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys ++ ULONG KeyLength; // length of key in bytes ++ UCHAR KeyMaterial[16];// variable length depending on above field ++} NDIS_802_11_WEP, *PNDIS_802_11_WEP; ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST ++{ ++ ULONG Length; // Length of structure ++ NDIS_802_11_MAC_ADDRESS Bssid; ++ ULONG Flags; ++} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; ++ ++typedef enum _NDIS_802_11_STATUS_TYPE ++{ ++ Ndis802_11StatusType_Authentication, ++ Ndis802_11StatusType_MediaStreamMode, ++ Ndis802_11StatusType_PMKID_CandidateList, ++ Ndis802_11StatusTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; ++ ++typedef struct _NDIS_802_11_STATUS_INDICATION ++{ ++ NDIS_802_11_STATUS_TYPE StatusType; ++} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; ++ ++// mask for authentication/integrity fields ++#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f ++#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 ++#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 ++#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 ++#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E ++ ++// MIC check time, 60 seconds. ++#define MIC_CHECK_TIME 60000000 ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_EVENT ++{ ++ NDIS_802_11_STATUS_INDICATION Status; ++ NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; ++} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; ++ ++typedef struct _NDIS_802_11_TEST ++{ ++ ULONG Length; ++ ULONG Type; ++ union ++ { ++ NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; ++ NDIS_802_11_RSSI RssiTrigger; ++ }tt; ++} NDIS_802_11_TEST, *PNDIS_802_11_TEST; ++ ++ ++#endif //PLATFORM_FREEBSD ++#ifndef Ndis802_11APMode ++#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) ++#endif ++ ++typedef struct _WLAN_PHY_INFO ++{ ++ u8 SignalStrength;//(in percentage) ++ u8 SignalQuality;//(in percentage) ++ u8 Optimum_antenna; //for Antenna diversity ++ u8 Reserved_0; ++}WLAN_PHY_INFO,*PWLAN_PHY_INFO; ++ ++typedef struct _WLAN_BCN_INFO ++{ ++ /* these infor get from rtw_get_encrypt_info when ++ * * translate scan to UI */ ++ u8 encryp_protocol;//ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI ++ int group_cipher; //WPA/WPA2 group cipher ++ int pairwise_cipher;////WPA/WPA2/WEP pairwise cipher ++ int is_8021x; ++ ++ /* bwmode 20/40 and ch_offset UP/LOW */ ++ unsigned short ht_cap_info; ++ unsigned char ht_info_infos_0; ++}WLAN_BCN_INFO,*PWLAN_BCN_INFO; ++ ++/* temporally add #pragma pack for structure alignment issue of ++* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() ++*/ ++#ifdef PLATFORM_WINDOWS ++#pragma pack(push) ++#pragma pack(1) ++#endif ++typedef struct _WLAN_BSSID_EX ++{ ++ ULONG Length; ++ NDIS_802_11_MAC_ADDRESS MacAddress; ++ UCHAR Reserved[2];//[0]: IS beacon frame ++ NDIS_802_11_SSID Ssid; ++ ULONG Privacy; ++ NDIS_802_11_RSSI Rssi;//(in dBM,raw data ,get from PHY) ++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; ++ NDIS_802_11_CONFIGURATION Configuration; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; ++ NDIS_802_11_RATES_EX SupportedRates; ++ WLAN_PHY_INFO PhyInfo; ++ ULONG IELength; ++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) ++} ++#ifndef PLATFORM_WINDOWS ++__attribute__((packed)) ++#endif ++WLAN_BSSID_EX, *PWLAN_BSSID_EX; ++#ifdef PLATFORM_WINDOWS ++#pragma pack(pop) ++#endif ++ ++__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss) ++{ ++#if 0 ++ uint t_len; ++ ++ t_len = sizeof (ULONG) ++ + sizeof (NDIS_802_11_MAC_ADDRESS) ++ + 2 ++ + sizeof (NDIS_802_11_SSID) ++ + sizeof (ULONG) ++ + sizeof (NDIS_802_11_RSSI) ++ + sizeof (NDIS_802_11_NETWORK_TYPE) ++ + sizeof (NDIS_802_11_CONFIGURATION) ++ + sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) ++ + sizeof (NDIS_802_11_RATES_EX) ++ //all new member add here ++ + sizeof(WLAN_PHY_INFO) ++ //all new member add here ++ + sizeof (ULONG) ++ + bss->IELength; ++ return t_len; ++#else ++ return (sizeof(WLAN_BSSID_EX) -MAX_IE_SZ + bss->IELength); ++#endif ++} ++ ++struct wlan_network { ++ _list list; ++ int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G ++ int fixed; // set to fixed when not to be removed as site-surveying ++ unsigned long last_scanned; //timestamp for the network ++ int aid; //will only be valid when a BSS is joinned. ++ int join_res; ++ WLAN_BSSID_EX network; //must be the last item ++ WLAN_BCN_INFO BcnInfo; ++#ifdef PLATFORM_WINDOWS ++ unsigned char iebuf[MAX_IE_SZ]; ++#endif ++ ++}; ++ ++enum VRTL_CARRIER_SENSE ++{ ++ DISABLE_VCS, ++ ENABLE_VCS, ++ AUTO_VCS ++}; ++ ++enum VCS_TYPE ++{ ++ NONE_VCS, ++ RTS_CTS, ++ CTS_TO_SELF ++}; ++ ++ ++ ++ ++#define PWR_CAM 0 ++#define PWR_MINPS 1 ++#define PWR_MAXPS 2 ++#define PWR_UAPSD 3 ++#define PWR_VOIP 4 ++ ++ ++enum UAPSD_MAX_SP ++{ ++ NO_LIMIT, ++ TWO_MSDU, ++ FOUR_MSDU, ++ SIX_MSDU ++}; ++ ++ ++//john ++#define NUM_PRE_AUTH_KEY 16 ++#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY ++ ++/* ++* WPA2 ++*/ ++ ++#ifndef PLATFORM_OS_CE ++typedef struct _PMKID_CANDIDATE { ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ ULONG Flags; ++} PMKID_CANDIDATE, *PPMKID_CANDIDATE; ++ ++typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST ++{ ++ ULONG Version; // Version of the structure ++ ULONG NumCandidates; // No. of pmkid candidates ++ PMKID_CANDIDATE CandidateList[1]; ++} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST; ++ ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION ++{ ++ NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported; ++ NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported; ++ ++} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION; ++ ++typedef struct _NDIS_802_11_CAPABILITY ++{ ++ ULONG Length; ++ ULONG Version; ++ ULONG NoOfPMKIDs; ++ ULONG NoOfAuthEncryptPairsSupported; ++ NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1]; ++ ++} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY; ++#endif ++ ++ ++#endif //#ifndef WLAN_BSSDEF_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/include/xmit_osdep.h b/drivers/net/wireless/rtl818x/rtl8189/include/xmit_osdep.h +new file mode 100644 +index 00000000..090a4475 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/include/xmit_osdep.h +@@ -0,0 +1,99 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __XMIT_OSDEP_H_ ++#define __XMIT_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++struct pkt_file { ++ _pkt *pkt; ++ SIZE_T pkt_len; //the remainder length of the open_file ++ _buffer *cur_buffer; ++ u8 *buf_start; ++ u8 *cur_addr; ++ SIZE_T buf_len; ++}; ++ ++#ifdef PLATFORM_WINDOWS ++ ++#ifdef PLATFORM_OS_XP ++#ifdef CONFIG_USB_HCI ++#include ++#include ++#include ++#endif ++#endif ++ ++#ifdef CONFIG_GSPI_HCI ++#define NR_XMITFRAME 64 ++#else ++#define NR_XMITFRAME 128 ++#endif ++ ++#define ETH_ALEN 6 ++ ++extern NDIS_STATUS rtw_xmit_entry( ++IN _nic_hdl cnxt, ++IN NDIS_PACKET *pkt, ++IN UINT flags ++); ++ ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++#define NR_XMITFRAME 256 ++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); ++extern void rtw_xmit_entry_wrap (struct ifnet * pifp); ++#endif //PLATFORM_FREEBSD ++ ++#ifdef PLATFORM_LINUX ++ ++#define NR_XMITFRAME 256 ++ ++struct xmit_priv; ++struct pkt_attrib; ++struct sta_xmit_priv; ++struct xmit_frame; ++struct xmit_buf; ++ ++extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); ++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); ++ ++#endif ++ ++void rtw_os_xmit_schedule(_adapter *padapter); ++ ++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz); ++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz); ++ ++extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); ++ ++extern uint rtw_remainder_len(struct pkt_file *pfile); ++extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); ++extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen); ++extern sint rtw_endofpktfile (struct pkt_file *pfile); ++ ++extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); ++extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); ++ ++#endif //__XMIT_OSDEP_H_ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/make_drv b/drivers/net/wireless/rtl818x/rtl8189/make_drv +new file mode 100644 +index 00000000..c61ef0b7 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/make_drv +@@ -0,0 +1,238 @@ ++#!/bin/bash ++#======================================== ++# Common functions ++#======================================== ++intf_usb() ++{ ++ sed -i '/CONFIG_USB_HCI = /c\CONFIG_USB_HCI = y' Makefile ++ sed -i '/CONFIG_PCI_HCI = /c\CONFIG_PCI_HCI = n' Makefile ++ sed -i '/CONFIG_SDIO_HCI = /c\CONFIG_SDIO_HCI = n' Makefile ++ sed -i '/CONFIG_GSPI_HCI = /c\CONFIG_GSPI_HCI = n' Makefile ++} ++intf_pcie() ++{ ++ sed -i '/CONFIG_USB_HCI = /c\CONFIG_USB_HCI = n' Makefile ++ sed -i '/CONFIG_PCI_HCI = /c\CONFIG_PCI_HCI = y' Makefile ++ sed -i '/CONFIG_SDIO_HCI = /c\CONFIG_SDIO_HCI = n' Makefile ++ sed -i '/CONFIG_GSPI_HCI = /c\CONFIG_GSPI_HCI = n' Makefile ++} ++intf_sdio() ++{ ++ sed -i '/CONFIG_USB_HCI = /c\CONFIG_USB_HCI = n' Makefile ++ sed -i '/CONFIG_PCI_HCI = /c\CONFIG_PCI_HCI = n' Makefile ++ sed -i '/CONFIG_SDIO_HCI = /c\CONFIG_SDIO_HCI = y' Makefile ++ sed -i '/CONFIG_GSPI_HCI = /c\CONFIG_GSPI_HCI = n' Makefile ++} ++ ++nic_8192c() ++{ ++ sed -i '/CONFIG_RTL8192C = /c\CONFIG_RTL8192C = y' Makefile ++ sed -i '/CONFIG_RTL8192D = /c\CONFIG_RTL8192D = n' Makefile ++ sed -i '/CONFIG_RTL8723A = /c\CONFIG_RTL8723A = n' Makefile ++ sed -i '/CONFIG_RTL8188E = /c\CONFIG_RTL8188E = n' Makefile ++} ++nic_8192d() ++{ ++ sed -i '/CONFIG_RTL8192C = /c\CONFIG_RTL8192C = n' Makefile ++ sed -i '/CONFIG_RTL8192D = /c\CONFIG_RTL8192D = y' Makefile ++ sed -i '/CONFIG_RTL8723A = /c\CONFIG_RTL8723A = n' Makefile ++ sed -i '/CONFIG_RTL8188E = /c\CONFIG_RTL8188E = n' Makefile ++} ++nic_8723a(){ ++ sed -i '/CONFIG_RTL8192C = /c\CONFIG_RTL8192C = n' Makefile ++ sed -i '/CONFIG_RTL8192D = /c\CONFIG_RTL8192D = n' Makefile ++ sed -i '/CONFIG_RTL8723A = /c\CONFIG_RTL8723A = y' Makefile ++ sed -i '/CONFIG_RTL8188E = /c\CONFIG_RTL8188E = n' Makefile ++} ++nic_8188e(){ ++ sed -i '/CONFIG_RTL8192C = /c\CONFIG_RTL8192C = n' Makefile ++ sed -i '/CONFIG_RTL8192D = /c\CONFIG_RTL8192D = n' Makefile ++ sed -i '/CONFIG_RTL8723A = /c\CONFIG_RTL8723A = n' Makefile ++ sed -i '/CONFIG_RTL8188E = /c\CONFIG_RTL8188E = y' Makefile ++} ++ch_obj_cu() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8192CU) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8192CU = m' Makefile ++ ++ cp -f Kconfig_rtl8192c_usb_linux Kconfig ++} ++ ++ch_obj_ce() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8192CE) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8192CE = m' Makefile ++ ++ cp -f Kconfig_rtl8192c_pci_linux Kconfig ++} ++ ++ch_obj_du() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8192DU) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8192DU = m' Makefile ++ ++ cp -f Kconfig_rtl8192d_usb_linux Kconfig ++} ++ ++ch_obj_de() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8192DE) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8192DE = m' Makefile ++ ++ cp -f Kconfig_rtl8192d_pci_linux Kconfig ++} ++ ++ch_obj_as() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8723AS) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8723AS = m' Makefile ++ ++# sed -i '/CONFIG_POWER_SAVING = /c\CONFIG_POWER_SAVING = y' Makefile ++ ++ cp -f Kconfig_rtl8723a_sdio_linux Kconfig ++} ++ ++ch_obj_au() ++{ ++ sed -i '/obj-$(CONFIG_RTL/ c obj-$(CONFIG_RTL8723AS-VAU) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/ c export CONFIG_RTL8723AS-VAU = m' Makefile ++ ++# sed -i '/CONFIG_POWER_SAVING = /c\CONFIG_POWER_SAVING = n' Makefile ++ ++ cp -f Kconfig_rtl8723a_usb_linux Kconfig ++} ++ ++ch_obj_es() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8189ES) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8189ES = m' Makefile ++ ++ cp -f Kconfig_rtl8189e_sdio_linux Kconfig ++} ++ ++ch_obj_eu() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8188EU) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8188EU = m' Makefile ++ ++ cp -f Kconfig_rtl8188e_usb_linux Kconfig ++} ++ ++ch_obj_ee() ++{ ++ sed -i '/obj-$(CONFIG_RTL/c\obj-$(CONFIG_RTL8188EE) := $(MODULE_NAME).o' Makefile ++ sed -i '/export CONFIG_RTL/c\export CONFIG_RTL8188EE = m' Makefile ++ ++ cp -f Kconfig_rtl8188e_pci_linux Kconfig ++} ++ ++get_svn_revision() ++{ ++ if [ -z "$svn_rev" ] && [ -f .svn/entries ]; then ++ svn_rev=`sed -n '11 s/^\([0-9][0-9]*\)$/\1/p' .svn/entries` ++ fi ++ if [ -z "$svn_rev" ]; then ++ svn_rev="xxxx" ++ fi ++} ++ ++#======================================== ++# Sub functions ++#======================================== ++ ++add_version_file() ++{ ++ defversion="#define DRIVERVERSION\t\"$postfix\"" ++ echo -e $defversion > include/rtw_version.h ++} ++ ++conf_driver() ++{ ++ sed -i '/CONFIG_AUTOCFG_CP = /c\CONFIG_AUTOCFG_CP = y' Makefile ++ if [ -f include/rtw_version.h ]; then ++ echo "rtw_version.h has existed!" ++ else ++ add_version_file ++ fi ++} ++ ++#======================================== ++# Main Script Start From Here ++#======================================== ++ ++if [ ! -f include/rtw_version.h ]; then ++ # Make Version string ++ if [ -z "$2" ]; then ++ get_svn_revision ++ version="v4.1.3_"$svn_rev ++ datestr=$(date +%Y%m%d) ++ postfix=$version.$datestr ++ else ++ postfix=$2 ++ fi ++fi ++ ++if [ $# -eq 1 ]; then ++ card=$1 ++ echo "You have selected $card" ++else ++ # Select NIC type ++ echo "Please select card type(1/2):" ++ select card in RTL8188eus RTL8189es; ++ do ++ echo "You have selected $card" ++ break ++ done ++fi ++ ++# Make ++case "$card" in ++ [Rr][Tt][Ll]8192[Cc][Uu]) ++ conf_driver; ++ nic_8192c; ++ intf_usb; ++ ch_obj_cu;; ++ [Rr][Tt][Ll]8192[Cc][Ee]) ++ conf_driver; ++ nic_8192c; ++ intf_pcie; ++ ch_obj_ce;; ++ [Rr][Tt][Ll]8192[Dd][Uu]) ++ conf_driver; ++ nic_8192d; ++ intf_usb; ++ ch_obj_du;; ++ [Rr][Tt][Ll]8192[Dd][Ee]) ++ conf_driver; ++ nic_8192d; ++ intf_pcie; ++ ch_obj_de;; ++ [Rr][Tt][Ll]8723[Aa][Ss]) ++ conf_driver; ++ nic_8723a; ++ intf_sdio; ++ ch_obj_as;; ++ [Rr][Tt][Ll]8723[Aa][Ss]-[Vv][Aa][Uu]) ++ conf_driver; ++ nic_8723a; ++ intf_usb; ++ ch_obj_au;; ++ [Rr][Tt][Ll]8189[Ee][Ss]) ++ conf_driver; ++ nic_8188e; ++ intf_sdio; ++ ch_obj_es;; ++ [Rr][Tt][Ll]8188[Ee][Uu][Ss]) ++ conf_driver; ++ nic_8188e; ++ intf_usb; ++ ch_obj_eu;; ++ [Rr][Tt][Ll]8188[Ee][Ee]) ++ conf_driver; ++ nic_8188e; ++ intf_pcie; ++ ch_obj_ee;; ++ *) ++ echo "Unknown NIC type" ++ ;; ++esac +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/custom_gpio_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/custom_gpio_linux.c +new file mode 100644 +index 00000000..eaf2e14e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/custom_gpio_linux.c +@@ -0,0 +1,210 @@ ++/****************************************************************************** ++ * Customer code to add GPIO control during WLAN start/stop ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#include "osdep_service.h" ++#include "drv_types.h" ++#include "custom_gpio.h" ++ ++#ifdef CONFIG_PLATFORM_SPRD ++ ++//gspi func & GPIO define ++#include //0915 ++#include ++ ++#if !(defined ANDROID_2X) ++ ++#ifdef CONFIG_RTL8188E ++#include ++#include ++#endif // CONFIG_RTL8188E ++ ++#ifndef GPIO_WIFI_POWER ++#define GPIO_WIFI_POWER -1 ++#endif // !GPIO_WIFI_POWER ++ ++#ifndef GPIO_WIFI_RESET ++#define GPIO_WIFI_RESET -1 ++#endif // !GPIO_WIFI_RESET ++ ++#ifndef GPIO_WIFI_PWDN ++#define GPIO_WIFI_PWDN -1 ++#endif // !GPIO_WIFI_RESET ++#ifdef CONFIG_GSPI_HCI ++extern unsigned int oob_irq; ++#endif // CONFIG_GSPI_HCI ++ ++#ifdef CONFIG_SDIO_HCI ++extern int rtw_mp_mode; ++#else // !CONFIG_SDIO_HCI ++#endif // !CONFIG_SDIO_HCI ++ ++int rtw_wifi_gpio_init(void) ++{ ++#ifdef CONFIG_GSPI_HCI ++ if (GPIO_WIFI_IRQ > 0) { ++ gpio_request(GPIO_WIFI_IRQ, "oob_irq"); ++ gpio_direction_input(GPIO_WIFI_IRQ); ++ ++ oob_irq = gpio_to_irq(GPIO_WIFI_IRQ); ++ ++ DBG_8192C("%s oob_irq:%d\n", __func__, oob_irq); ++ } ++#endif ++ ++ if (GPIO_WIFI_RESET > 0) ++ gpio_request(GPIO_WIFI_RESET , "wifi_rst"); ++ ++ return 0; ++} ++ ++int rtw_wifi_gpio_deinit(void) ++{ ++#ifdef CONFIG_GSPI_HCI ++ if (GPIO_WIFI_IRQ > 0) { ++ gpio_free(GPIO_WIFI_IRQ); ++#endif ++ if (GPIO_WIFI_RESET > 0) ++ gpio_free(GPIO_WIFI_RESET ); ++ ++ return 0; ++} ++ ++/* Customer function to control hw specific wlan gpios */ ++void rtw_wifi_gpio_wlan_ctrl(int onoff) ++{ ++ switch (onoff) { ++ case WLAN_PWDN_OFF: ++ DBG_8192C("%s: call customer specific GPIO(%d) to set wifi power down pin to 0\n", ++ __FUNCTION__, GPIO_WIFI_RESET); ++ ++ if (GPIO_WIFI_RESET > 0) ++ gpio_direction_output(GPIO_WIFI_RESET , 0); ++ break; ++ ++ case WLAN_PWDN_ON: ++ DBG_8192C("%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\n", ++ __FUNCTION__, GPIO_WIFI_RESET); ++ ++ if (GPIO_WIFI_RESET > 0) ++ gpio_direction_output(GPIO_WIFI_RESET , 1); ++ break; ++ ++ case WLAN_POWER_OFF: ++ DBG_8192C("%s: call customer specific GPIO to turn off wifi power\n", ++ __FUNCTION__); ++ break; ++ case WLAN_POWER_ON: ++ DBG_8192C("%s: call customer specific GPIO to turn on wifi power\n", ++ __FUNCTION__); ++ break; ++ } ++} ++#else //ANDROID_2X ++//gspi func & GPIO define ++#include //0915 ++#include ++#ifdef CONFIG_RTL8188E ++extern int sprd_3rdparty_gpio_wifi_power; ++#endif ++extern int sprd_3rdparty_gpio_wifi_pwd; ++#ifdef CONFIG_RTL8723A ++extern int sprd_3rdparty_gpio_bt_reset; ++#endif ++ ++int rtw_wifi_gpio_init(void) ++{ ++#ifdef CONFIG_RTL8723A ++ if (sprd_3rdparty_gpio_bt_reset > 0) ++ gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1); ++#endif ++ ++ return 0; ++} ++ ++int rtw_wifi_gpio_deinit(void) ++{ ++ return 0; ++} ++ ++/* Customer function to control hw specific wlan gpios */ ++void rtw_wifi_gpio_wlan_ctrl(int onoff) ++{ ++ switch (onoff) { ++ case WLAN_PWDN_OFF: ++ DBG_8192C("%s: call customer specific GPIO to set wifi power down pin to 0\n", ++ __FUNCTION__); ++ if (sprd_3rdparty_gpio_wifi_pwd > 0) ++ gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0); ++ break; ++ ++ case WLAN_PWDN_ON: ++ DBG_8192C("%s: callc customer specific GPIO to set wifi power down pin to 1\n", ++ __FUNCTION__); ++ if (sprd_3rdparty_gpio_wifi_pwd > 0) ++ gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1); ++ break; ++ ++ case WLAN_POWER_OFF: ++ DBG_8192C("%s: call customer specific GPIO to turn off wifi power\n", ++ __FUNCTION__); ++#ifdef CONFIG_RTL8188E ++ if (sprd_3rdparty_gpio_wifi_power > 0) ++ gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0); ++#endif ++ break; ++ case WLAN_POWER_ON: ++ DBG_8192C("%s: call customer specific GPIO to turn on wifi power\n", ++ __FUNCTION__); ++#ifdef CONFIG_RTL8188E ++ if (sprd_3rdparty_gpio_wifi_power > 0) ++ gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1); ++#endif ++ ++ case WLAN_BT_PWDN_OFF: ++ DBG_8192C("%s: call customer specific GPIO to set bt power down pin to 0\n", ++ __FUNCTION__); ++#ifdef CONFIG_RTL8723A ++ if (sprd_3rdparty_gpio_bt_reset > 0) ++ gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0); ++#endif ++ break; ++ ++ case WLAN_BT_PWDN_ON: ++ DBG_8192C("%s: callc customer specific GPIO to set bt power down pin to 1\n", ++ __FUNCTION__); ++#ifdef CONFIG_RTL8723A ++ if (sprd_3rdparty_gpio_bt_reset > 0) ++ gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1); ++#endif ++ break; ++ break; ++ } ++} ++#endif //ANDROID_2X ++#else //CONFIG_PLATFORM_SPRD ++int rtw_wifi_gpio_init(void) ++{ ++ return 0; ++} ++ ++void rtw_wifi_gpio_wlan_ctrl(int onoff) ++{ ++} ++#endif //CONFIG_PLATFORM_SPRD +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_intf.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_intf.c +new file mode 100644 +index 00000000..aa08f2b1 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_intf.c +@@ -0,0 +1,945 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_GSPI_HCI ++#error "CONFIG_GSPI_HCI should be on!\n" ++#endif ++ ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_RTL8723A ++#include ++#include ++#include ++#endif ++ ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++ ++#include ++#include ++#include ++ ++#include ++ ++ ++extern char* ifname; ++ ++typedef struct _driver_priv { ++ int drv_registered; ++} drv_priv, *pdrv_priv; ++ ++unsigned int oob_irq; ++static drv_priv drvpriv = { ++ ++}; ++ ++static void decide_chip_type_by_device_id(PADAPTER padapter) ++{ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ ++#if defined(CONFIG_RTL8723A) ++ padapter->chip_type = RTL8723A; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8723AS; ++#elif defined(CONFIG_RTL8188E) ++ padapter->chip_type = RTL8188E; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8188ES; ++#endif ++} ++ ++static irqreturn_t spi_interrupt_thread(int irq, void *data) ++{ ++ struct dvobj_priv *dvobj; ++ PGSPI_DATA pgspi_data; ++ ++ ++ dvobj = (struct dvobj_priv*)data; ++ pgspi_data = &dvobj->intf_data; ++ ++ //spi_int_hdl(padapter); ++ if (pgspi_data->priv_wq) ++ queue_delayed_work(pgspi_data->priv_wq, &pgspi_data->irq_work, 0); ++ ++ return IRQ_HANDLED; ++} ++ ++static u8 gspi_alloc_irq(struct dvobj_priv *dvobj) ++{ ++ PGSPI_DATA pgspi_data; ++ struct spi_device *spi; ++ int err; ++ ++ ++ pgspi_data = &dvobj->intf_data; ++ spi = pgspi_data->func; ++ ++ err = request_irq(oob_irq, spi_interrupt_thread, ++ IRQF_TRIGGER_FALLING,//IRQF_TRIGGER_HIGH;//|IRQF_ONESHOT, ++ DRV_NAME, dvobj); ++ //err = request_threaded_irq(oob_irq, NULL, spi_interrupt_thread, ++ // IRQF_TRIGGER_FALLING, ++ // DRV_NAME, dvobj); ++ if (err < 0) { ++ DBG_871X("Oops: can't allocate irq %d err:%d\n", oob_irq, err); ++ goto exit; ++ } ++ enable_irq_wake(oob_irq); ++ disable_irq(oob_irq); ++ ++exit: ++ return err?_FAIL:_SUCCESS; ++} ++ ++static u8 gspi_init(struct dvobj_priv *dvobj) ++{ ++ PGSPI_DATA pgspi_data; ++ int err = 0; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+gspi_init\n")); ++ ++ if (NULL == dvobj) { ++ DBG_8192C(KERN_ERR "%s: driver object is NULL!\n", __func__); ++ err = -1; ++ goto exit; ++ } ++ ++ pgspi_data = &dvobj->intf_data; ++ ++ pgspi_data->block_transfer_len = 512; ++ pgspi_data->tx_block_mode = 0; ++ pgspi_data->rx_block_mode = 0; ++ ++exit: ++ _func_exit_; ++ ++ if (err) return _FAIL; ++ return _SUCCESS; ++} ++ ++static void gspi_deinit(struct dvobj_priv *dvobj) ++{ ++ PGSPI_DATA pgspi_data; ++ struct spi_device *spi; ++ int err; ++ ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+gspi_deinit\n")); ++ ++ if (NULL == dvobj) { ++ DBG_8192C(KERN_ERR "%s: driver object is NULL!\n", __FUNCTION__); ++ return; ++ } ++ ++ pgspi_data = &dvobj->intf_data; ++ spi = pgspi_data->func; ++ ++ if (spi) { ++ free_irq(oob_irq, dvobj); ++ } ++} ++ ++static struct dvobj_priv *gspi_dvobj_init(struct spi_device *spi) ++{ ++ int status = _FAIL; ++ struct dvobj_priv *dvobj = NULL; ++ PGSPI_DATA pgspi; ++ ++_func_enter_; ++ ++ dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj)); ++ if (NULL == dvobj) { ++ goto exit; ++ } ++ ++ _rtw_mutex_init(&dvobj->hw_init_mutex); ++ _rtw_mutex_init(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_init(&dvobj->setch_mutex); ++ _rtw_mutex_init(&dvobj->setbw_mutex); ++ dvobj->processing_dev_remove = _FALSE; ++ //spi init ++ /* This is the only SPI value that we need to set here, the rest ++ * comes from the board-peripherals file */ ++ spi->bits_per_word = 32; ++ spi->max_speed_hz = 48 * 1000 * 1000; ++ //here mode 0 and 3 all ok, ++ //3 can run under 48M clock when SPI_CTL4 bit14 IS_FST set to 1 ++ //0 can run under 24M clock, but can run under 48M when SPI_CTL4 bit14 IS_FST set to 1 and Ctl0_reg[1:0] set to 3. ++ spi->mode = SPI_MODE_3; ++ spi_setup(spi); ++ ++#if 1 ++ //DBG_8192C("set spi ==========================%d \n", spi_setup(spi)); ++ ++ DBG_871X("%s, mode = %d \n", __func__, spi->mode); ++ DBG_871X("%s, bit_per_word = %d \n", __func__, spi->bits_per_word); ++ DBG_871X("%s, speed = %d \n", __func__, spi->max_speed_hz); ++ DBG_871X("%s, chip_select = %d \n", __func__, spi->chip_select); ++ DBG_871X("%s, controller_data = %d \n", __func__, *(int *)spi->controller_data); ++ DBG_871X("%s, irq= %d \n", __func__, oob_irq); ++#endif ++ ++ spi_set_drvdata(spi, dvobj); ++ pgspi = &dvobj->intf_data; ++ pgspi->func = spi; ++ ++ if (gspi_init(dvobj) != _SUCCESS) { ++ DBG_871X("%s: initialize GSPI Failed!\n", __FUNCTION__); ++ goto free_dvobj; ++ } ++ rtw_reset_continual_io_error(dvobj); ++ status = _SUCCESS; ++ ++free_dvobj: ++ if (status != _SUCCESS && dvobj) { ++ spi_set_drvdata(spi, NULL); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ dvobj = NULL; ++ } ++ ++exit: ++_func_exit_; ++ ++ return dvobj; ++} ++ ++static void gspi_dvobj_deinit(struct spi_device *spi) ++{ ++ struct dvobj_priv *dvobj = spi_get_drvdata(spi); ++ ++_func_enter_; ++ ++ spi_set_drvdata(spi, NULL); ++ if (dvobj) { ++ gspi_deinit(dvobj); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ } ++ ++_func_exit_; ++} ++ ++static void spi_irq_work(void *data) ++{ ++ struct delayed_work *dwork; ++ PGSPI_DATA pgspi; ++ struct dvobj_priv *dvobj; ++ ++ ++ dwork = container_of(data, struct delayed_work, work); ++ pgspi = container_of(dwork, GSPI_DATA, irq_work); ++ ++ dvobj = spi_get_drvdata(pgspi->func); ++ if (!dvobj->if1) { ++ DBG_871X("%s if1 == NULL !!\n", __FUNCTION__); ++ return; ++ } ++ spi_int_hdl(dvobj->if1); ++} ++ ++static void gspi_intf_start(PADAPTER padapter) ++{ ++ PGSPI_DATA pgspi; ++ ++ ++ if (padapter == NULL) { ++ DBG_871X(KERN_ERR "%s: padapter is NULL!\n", __FUNCTION__); ++ return; ++ } ++ ++ pgspi = &adapter_to_dvobj(padapter)->intf_data; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ pgspi->priv_wq = alloc_workqueue("spi_wq", 0, 0); ++#else ++ pgspi->priv_wq = create_workqueue("spi_wq"); ++#endif ++ INIT_DELAYED_WORK(&pgspi->irq_work, (void*)spi_irq_work); ++ ++ enable_irq(oob_irq); ++ //hal dep ++ rtw_hal_enable_interrupt(padapter); ++} ++ ++static void gspi_intf_stop(PADAPTER padapter) ++{ ++ PGSPI_DATA pgspi; ++ ++ ++ if (padapter == NULL) { ++ DBG_871X(KERN_ERR "%s: padapter is NULL!\n", __FUNCTION__); ++ return; ++ } ++ ++ pgspi = &adapter_to_dvobj(padapter)->intf_data; ++ ++ if (pgspi->priv_wq) { ++ cancel_delayed_work_sync(&pgspi->irq_work); ++ flush_workqueue(pgspi->priv_wq); ++ destroy_workqueue(pgspi->priv_wq); ++ pgspi->priv_wq = NULL; ++ } ++ ++ //hal dep ++ rtw_hal_disable_interrupt(padapter); ++ disable_irq(oob_irq); ++} ++ ++/* ++ * Do deinit job corresponding to netdev_open() ++ */ ++void rtw_dev_unload(PADAPTER padapter) ++{ ++ struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_dev_unload\n")); ++ ++ padapter->bDriverStopped = _TRUE; ++ #ifdef CONFIG_XMIT_ACK ++ if (padapter->xmitpriv.ack_tx) ++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); ++ #endif ++ ++ if (padapter->bup == _TRUE) ++ { ++#if 0 ++ if (padapter->intf_stop) ++ padapter->intf_stop(padapter); ++#else ++ gspi_intf_stop(padapter); ++#endif ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop intf complete!\n")); ++ ++ if (!adapter_to_pwrctl(padapter)->bInternalAutoSuspend) ++ rtw_stop_drv_threads(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop thread complete!\n")); ++ ++ if (padapter->bSurpriseRemoved == _FALSE) ++ { ++#ifdef CONFIG_WOWLAN ++ if (adapter_to_pwrctl(padapter)->bSupportRemoteWakeup == _TRUE) { ++ DBG_871X("%s bSupportRemoteWakeup==_TRUE do not run rtw_hal_deinit()\n",__FUNCTION__); ++ } ++ else ++#endif ++ { ++ rtw_hal_deinit(padapter); ++ } ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: deinit hal complelt!\n")); ++ ++ padapter->bup = _FALSE; ++ } ++ else { ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("rtw_dev_unload: bup==_FALSE\n")); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-rtw_dev_unload\n")); ++} ++ ++static PADAPTER rtw_gspi_if1_init(struct dvobj_priv *dvobj) ++{ ++ int status = _FAIL; ++ struct net_device *pnetdev; ++ PADAPTER padapter = NULL; ++ ++ ++ padapter = (PADAPTER)rtw_zvmalloc(sizeof(*padapter)); ++ if (NULL == padapter) { ++ goto exit; ++ } ++ ++ padapter->dvobj = dvobj; ++ dvobj->if1 = padapter; ++ ++ padapter->bDriverStopped = _TRUE; ++ ++ dvobj->padapters[dvobj->iface_nums++] = padapter; ++ padapter->iface_id = IFACE_ID0; ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) ++ //set adapter_type/iface type for primary padapter ++ padapter->isprimary = _TRUE; ++ padapter->adapter_type = PRIMARY_ADAPTER; ++ #ifndef CONFIG_HWPORT_SWAP ++ padapter->iface_type = IFACE_PORT0; ++ #else ++ padapter->iface_type = IFACE_PORT1; ++ #endif ++#endif ++ ++ padapter->interface_type = RTW_GSPI; ++ decide_chip_type_by_device_id(padapter); ++ ++ //3 1. init network device data ++ pnetdev = rtw_init_netdev(padapter); ++ if (!pnetdev) ++ goto free_adapter; ++ ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj)); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)); ++#endif ++ ++ ++ //3 3. init driver special setting, interface, OS and hardware relative ++ //4 3.1 set hardware operation functions ++ hal_set_hal_ops(padapter); ++ ++ ++ //3 5. initialize Chip version ++ padapter->intf_start = &gspi_intf_start; ++ padapter->intf_stop = &gspi_intf_stop; ++ ++ if (rtw_init_io_priv(padapter, spi_set_intf_ops) == _FAIL) ++ { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ++ ("rtw_drv_init: Can't init io_priv\n")); ++ goto free_hal_data; ++ } ++ ++ { ++ u32 ret = 0; ++ DBG_8192C("read start:\n"); ++ //spi_write8_endian(padapter, SPI_LOCAL_OFFSET | 0xF0, 0x01, 1); ++ rtw_write8(padapter, SPI_LOCAL_OFFSET | 0xF0, 0x03); ++ ret = rtw_read32(padapter, SPI_LOCAL_OFFSET | 0xF0); ++ DBG_8192C("read end 0xF0 read32:%x:\n", ret); ++ DBG_8192C("read end 0xF0 read8:%x:\n", rtw_read8(padapter, SPI_LOCAL_OFFSET | 0xF0)); ++ ++ } ++ ++ rtw_hal_read_chip_version(padapter); ++ ++ rtw_hal_chip_configure(padapter); ++ ++ ++ //3 6. read efuse/eeprom data ++ rtw_hal_read_chip_info(padapter); ++ ++ ++ //3 7. init driver common data ++ if (rtw_init_drv_sw(padapter) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ++ ("rtw_drv_init: Initialize driver software resource Failed!\n")); ++ goto free_hal_data; ++ } ++ ++ ++ //3 8. get WLan MAC address ++ // set mac addr ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr); ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n" ++ ,padapter->bDriverStopped ++ ,padapter->bSurpriseRemoved ++ ,padapter->bup ++ ,padapter->hw_init_completed ++ ); ++ ++ status = _SUCCESS; ++ ++free_hal_data: ++ if (status != _SUCCESS && padapter->HalData) ++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData))); ++ ++free_wdev: ++ if (status != _SUCCESS) { ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++ rtw_wdev_free(padapter->rtw_wdev); ++ #endif ++ } ++ ++free_adapter: ++ if (status != _SUCCESS) { ++ if (pnetdev) ++ rtw_free_netdev(pnetdev); ++ else if (padapter) ++ rtw_vmfree((u8*)padapter, sizeof(*padapter)); ++ padapter = NULL; ++ } ++ ++exit: ++ return padapter; ++} ++ ++static void rtw_gspi_if1_deinit(PADAPTER if1) ++{ ++ struct net_device *pnetdev = if1->pnetdev; ++ struct mlme_priv *pmlmepriv = &if1->mlmepriv; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) ++ rtw_disassoc_cmd(if1, 0, _FALSE); ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(if1); ++ #ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(if1); ++#endif ++#endif ++/* ++ if(if1->DriverState != DRIVER_DISAPPEAR) { ++ if(pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++ } ++*/ ++ rtw_cancel_all_timer(if1); ++ ++ rtw_dev_unload(if1); ++ DBG_871X("+r871xu_dev_remove, hw_init_completed=%d\n", if1->hw_init_completed); ++ ++ rtw_handle_dualmac(if1, 0); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if (if1->rtw_wdev) ++ { ++ //rtw_wdev_unregister(if1->rtw_wdev); ++ rtw_wdev_free(if1->rtw_wdev); ++ } ++#endif ++ ++ rtw_free_drv_sw(if1); ++ ++ if(pnetdev) ++ rtw_free_netdev(pnetdev); ++} ++ ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++ */ ++static int /*__devinit*/ rtw_drv_probe(struct spi_device *spi) ++{ ++ int status = _FAIL; ++ struct dvobj_priv *dvobj; ++ struct net_device *pnetdev; ++ PADAPTER if1 = NULL, if2 = NULL; ++ ++ ++ DBG_8192C("RTW: %s line:%d", __FUNCTION__, __LINE__); ++ ++ if ((dvobj = gspi_dvobj_init(spi)) == NULL) { ++ DBG_871X("%s: Initialize device object priv Failed!\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ if ((if1 = rtw_gspi_if1_init(dvobj)) == NULL) { ++ DBG_871X("rtw_init_primary_adapter Failed!\n"); ++ goto free_dvobj; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ((if2 = rtw_drv_if2_init(if1, NULL, spi_set_intf_ops)) == NULL) { ++ goto free_if1; ++ } ++#endif ++ ++ //dev_alloc_name && register_netdev ++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) { ++ goto free_if2; ++ } ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(if1); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(if1->pnetdev); ++#endif ++ ++ if (gspi_alloc_irq(dvobj) != _SUCCESS) ++ goto free_if2; ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++ if(ui_pid[1]!=0) { ++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]); ++ rtw_signal_process(ui_pid[1], SIGUSR2); ++ } ++#endif ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ ++ status = _SUCCESS; ++ ++free_if2: ++ if (status != _SUCCESS && if2) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(if2); ++ rtw_drv_if2_free(if2); ++ #endif ++ } ++ ++free_if1: ++ if (status != _SUCCESS && if1) { ++ rtw_gspi_if1_deinit(if1); ++ } ++ ++free_dvobj: ++ if (status != _SUCCESS) ++ gspi_dvobj_deinit(spi); ++ ++exit: ++ return status == _SUCCESS?0:-ENODEV; ++} ++extern void rtw_unregister_netdevs(struct dvobj_priv *dvobj); ++static int /*__devexit*/ rtw_dev_remove(struct spi_device *spi) ++{ ++ struct dvobj_priv *dvobj = spi_get_drvdata(spi); ++ PADAPTER padapter = dvobj->if1; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_dev_remove\n")); ++ ++ dvobj->processing_dev_remove = _TRUE; ++ rtw_unregister_netdevs(dvobj); ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(dvobj_to_pwrctl(dvobj)); ++#endif ++ ++ rtw_pm_set_ips(padapter, IPS_NONE); ++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); ++ ++ LeaveAllPowerSaveMode(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(dvobj->if2); ++#endif ++ ++ rtw_gspi_if1_deinit(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_free(dvobj->if2); ++#endif ++ ++ gspi_dvobj_deinit(spi); ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-rtw_dev_remove\n")); ++ ++_func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_gspi_suspend(struct spi_device *spi, pm_message_t mesg) ++{ ++ struct dvobj_priv *dvobj = spi_get_drvdata(spi); ++ PADAPTER padapter = dvobj->if1; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ int ret = 0; ++ ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ pwrpriv->bInSuspend = _TRUE; ++ ++ while (pwrpriv->bips_processing == _TRUE) ++ rtw_msleep_os(1); ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("%s bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", __FUNCTION__ ++ ,padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto exit; ++ } ++ ++ rtw_cancel_all_timer(padapter); ++ LeaveAllPowerSaveMode(padapter); ++ ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++#ifdef CONFIG_WOWLAN ++ pwrpriv->bSupportRemoteWakeup=_TRUE; ++#else ++ //s2. ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ ++ rtw_set_roaming(padapter, 1); ++ } ++#endif ++ ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_dev_unload(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ rtw_indicate_disconnect(padapter); ++ ++ // interface deinit ++ gspi_deinit(dvobj); ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: deinit GSPI complete!\n", __FUNCTION__)); ++ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF); ++ rtw_mdelay_os(1); ++exit: ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ return ret; ++} ++ ++extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); ++int rtw_resume_process(_adapter *padapter) ++{ ++ struct net_device *pnetdev; ++ struct pwrctrl_priv *pwrpriv; ++ u8 is_pwrlock_hold_by_caller; ++ u8 is_directly_called_by_auto_resume; ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON); ++ rtw_mdelay_os(1); ++ ++ { ++ u32 ret = 0; ++ DBG_8192C("read start:\n"); ++ //spi_write8_endian(padapter, SPI_LOCAL_OFFSET | 0xF0, 0x01, 1); ++ rtw_write8(padapter, SPI_LOCAL_OFFSET | 0xF0, 0x03); ++ ret = rtw_read32(padapter, SPI_LOCAL_OFFSET | 0xF0); ++ DBG_8192C("read end 0xF0 read32:%x:\n", ret); ++ DBG_8192C("read end 0xF0 read8:%x:\n", rtw_read8(padapter, SPI_LOCAL_OFFSET | 0xF0)); ++ ++ } ++ ++ if (padapter) { ++ pnetdev = padapter->pnetdev; ++ pwrpriv = adapter_to_pwrctl(padapter); ++ } else { ++ ret = -1; ++ goto exit; ++ } ++ ++ // interface init ++ if (gspi_init(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ rtw_hal_disable_interrupt(padapter); ++ if (gspi_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: gspi_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) { ++ ret = -1; ++ goto exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ ++ if( padapter->pid[1]!=0) { ++ DBG_871X("pid[1]:%d\n",padapter->pid[1]); ++ rtw_signal_process(padapter->pid[1], SIGUSR2); ++ } ++ ++ #ifdef CONFIG_LAYER2_ROAMING_RESUME ++ rtw_roaming(padapter, NULL); ++ #endif ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++exit: ++ pwrpriv->bInSuspend = _FALSE; ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_gspi_resume(struct spi_device *spi) ++{ ++ struct dvobj_priv *dvobj = spi_get_drvdata(spi); ++ PADAPTER padapter = dvobj->if1; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); ++ int ret = 0; ++ ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if(pwrpriv->bInternalAutoSuspend ){ ++ ret = rtw_resume_process(padapter); ++ } else { ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_resume_in_workqueue(pwrpriv); ++#else ++ if(rtw_is_earlysuspend_registered(pwrpriv)) { ++ /* jeff: bypass resume here, do in late_resume */ ++ rtw_set_do_late_resume(pwrpriv, _TRUE); ++ } else { ++ ret = rtw_resume_process(padapter); ++ } ++#endif /* CONFIG_RESUME_IN_WORKQUEUE */ ++ } ++ ++ DBG_871X("<======== %s return %d\n", __FUNCTION__, ret); ++ return ret; ++ ++} ++ ++ ++static struct spi_driver rtw_spi_drv = { ++ .probe = rtw_drv_probe, ++ .remove = rtw_dev_remove, ++ .suspend = rtw_gspi_suspend, ++ .resume = rtw_gspi_resume, ++ .driver = { ++ .name = "wlan_spi", ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ } ++ ++}; ++ ++static int __init rtw_drv_entry(void) ++{ ++ int ret; ++ ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_drv_entry\n")); ++ DBG_8192C("RTW: rtw_drv_entry enter\n"); ++ ++ rtw_suspend_lock_init(); ++ ++ drvpriv.drv_registered = _TRUE; ++ ++ rtw_wifi_gpio_init(); ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON); ++ ret = spi_register_driver(&rtw_spi_drv); ++ ++ DBG_8192C("RTW: rtw_drv_entry exit %d\n", ret); ++ ++ return 0; ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_drv_halt\n")); ++ DBG_8192C("RTW: rtw_drv_halt enter\n"); ++ ++ drvpriv.drv_registered = _FALSE; ++ ++ spi_unregister_driver(&rtw_spi_drv); ++ ++ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF); ++ rtw_wifi_gpio_deinit(); ++ ++ rtw_suspend_lock_uninit(); ++ DBG_8192C("RTW: rtw_drv_halt enter\n"); ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-rtw_drv_halt\n")); ++ ++ rtw_mstat_dump(); ++} ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_ops_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_ops_linux.c +new file mode 100644 +index 00000000..8600f059 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/gspi_ops_linux.c +@@ -0,0 +1,432 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#define _GSPI_OPS_LINUX_C_ ++ ++#include ++#include ++ ++#include "rtl8723a_hal.h" ++#include "rtl8723a_spec.h" ++#include "gspi_ops.h" ++ ++int spi_send_msg(PADAPTER Adapter, struct spi_transfer xfers[], u32 IoAction) ++{ ++ struct dvobj_priv *psddev; ++ struct spi_device *spi; ++ struct spi_message msg; ++ int ret = 1; ++ ++ if (Adapter == NULL) { ++ DBG_8192C(KERN_ERR "%s: padapter is NULL!\n", __func__); ++ return 1; ++ } ++ ++ psddev = adapter_to_dvobj(Adapter); ++ spi = psddev->intf_data.func; ++ ++ spi_message_init(&msg); ++ spi_message_add_tail(&xfers[0], &msg); ++ spi_message_add_tail(&xfers[1], &msg); ++ spi_message_add_tail(&xfers[2], &msg); ++ ret = spi_sync(spi, &msg); ++ if (ret) { ++ DBG_8192C("%s: FAIL!\n", __func__); ++ } ++ ++ return ret; ++} ++ ++int addr_convert(u32 addr) ++{ ++ u32 domain_id = 0 ; ++ u32 temp_addr = addr&0xffff0000; ++ ++ if (temp_addr == 0 ) { ++ domain_id = WLAN_IOREG_DOMAIN; ++ return domain_id; ++ } ++ ++ switch (temp_addr) { ++ case SPI_LOCAL_OFFSET: ++ domain_id = SPI_LOCAL_DOMAIN; ++ break; ++ case WLAN_IOREG_OFFSET: ++ domain_id = WLAN_IOREG_DOMAIN; ++ break; ++ case FW_FIFO_OFFSET: ++ domain_id = FW_FIFO_DOMAIN; ++ break; ++ case TX_HIQ_OFFSET: ++ domain_id = TX_HIQ_DOMAIN; ++ break; ++ case TX_MIQ_OFFSET: ++ domain_id = TX_MIQ_DOMAIN; ++ break; ++ case TX_LOQ_OFFSET: ++ domain_id = TX_LOQ_DOMAIN; ++ break; ++ case RX_RXOFF_OFFSET: ++ domain_id = RX_RXFIFO_DOMAIN; ++ break; ++ default: ++ break; ++ } ++ //sys_mib.Spi_Transation_record.domain_id =domain_id; ++ return domain_id; ++} ++ ++static u32 buf_endian_reverse(u32 src) ++{ ++ return (((src&0x000000ff)<<24)|((src&0x0000ff00)<<8)| ++ ((src&0x00ff0000)>>8)|((src&0xff000000)>>24)); ++} ++ ++void spi_get_status_info(ADAPTER* Adapter, unsigned char *status) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = GET_STATUS_PUB_PAGE_NUM(status); ++ pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX] = GET_STATUS_HI_PAGE_NUM(status); ++ pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX] = GET_STATUS_MID_PAGE_NUM(status); ++ pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = GET_STATUS_LOW_PAGE_NUM(status); ++ ++ //DBG_8192C("%s: Free page for HIQ(%#x),MIDQ(%#x),LOWQ(%#x),PUBQ(%#x)\n", ++ // __FUNCTION__, ++ // pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX], ++ // pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX], ++ // pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX], ++ // pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]); ++} ++ ++int spi_read_write_reg(PADAPTER pAdapter, int write_flag, u32 addr, char * buf, int len, u32 eddien) ++{ ++ int fun = 1, domain_id = 0x0; //LOCAL ++ unsigned int cmd = 0 ; ++ int byte_en = 0 ;//,i = 0 ; ++ int ret = 0; ++ unsigned char status[8] = {0}; ++ unsigned int data_tmp = 0; ++ //u32 force_bigendian = !eddien; ++ u32 force_bigendian = eddien; ++ ++ if (len!=1 && len!=2 && len != 4) { ++ return -1; ++ } ++ ++ domain_id = addr_convert(addr); ++ ++ addr &= 0x7fff; ++ len &= 0xff; ++ if (write_flag) //write register ++ { ++ int remainder = addr % 4; ++ u32 val32 = *(u32 *)buf; ++ switch(len) { ++ case 1: ++ byte_en = (0x1 << remainder); ++ data_tmp = (val32& 0xff)<< (remainder*8); ++ break; ++ case 2: ++ byte_en = (0x3 << remainder); ++ data_tmp = (val32 & 0xffff)<< (remainder*8); ++ break; ++ case 4: ++ byte_en = 0xf; ++ data_tmp = val32 & 0xffffffff; ++ break; ++ default: ++ byte_en = 0xf; ++ data_tmp = val32 & 0xffffffff; ++ break; ++ } ++ } ++ else //read register ++ { ++ switch(len) { ++ case 1: ++ byte_en = 0x1; ++ break; ++ case 2: ++ byte_en = 0x3; ++ break; ++ case 4: ++ byte_en = 0xf; ++ break; ++ default: ++ byte_en = 0xf; ++ break; ++ } ++ } ++ ++ //addr = 0xF0 4byte: 0x2800f00f ++ REG_LEN_FORMAT(&cmd, byte_en); ++ REG_ADDR_FORMAT(&cmd, (addr&0xfffffffc)); ++ REG_DOMAIN_ID_FORMAT(&cmd, domain_id); ++ REG_FUN_FORMAT(&cmd, fun); ++ REG_RW_FORMAT(&cmd, write_flag); ++ ++ //DBG_8192C("spi_read_write_reg cmd1: %x, data_tmp is %x\n",cmd, data_tmp); ++ ++ if (force_bigendian) { ++ cmd = buf_endian_reverse(cmd); ++ } ++ ++ //io is one by one, so we do not need fwps_lock here ++ //rtw_spin_lock(&padapter->halpriv.fwps_lock); ++ //padapter->io_fifo_processing = _TRUE; ++ if (!write_flag && (domain_id!= RX_RXFIFO_DOMAIN)) { ++ u32 read_data = 0; ++ struct spi_transfer xfers[3]; ++ _rtw_memset(xfers, 0x00, 3*sizeof(struct spi_transfer)); ++ _rtw_memset(buf, 0x0, len); ++ ++ xfers[0].tx_buf = &cmd; ++ xfers[0].len = 4; ++ ++ xfers[1].rx_buf = status; ++ xfers[1].len = 8; ++ ++ xfers[2].rx_buf = &read_data; ++ xfers[2].len = 4; ++ ++ //DBG_8192C("spi_read_write_reg: read_data is %x\n", read_data); ++ ret = spi_send_msg(pAdapter, xfers, 0); ++ if (ret) { ++ DBG_8192C(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, ret, addr); ++ read_data = 0; ++ _rtw_memset(status, 0, 8); ++ } ++ ++ //DBG_8192C("spi_read_write_reg: read_data is %x\n", read_data); ++ read_data = EF4Byte(read_data); ++ //add for 8810 ++#ifdef CONFIG_BIG_ENDIAN ++ if (!force_bigendian) ++ read_data = buf_endian_reverse(read_data); ++#else ++ if (force_bigendian) ++ read_data = buf_endian_reverse(read_data); ++#endif ++ *(u32*)buf = read_data; ++ //DBG_8192C("spi_read_write_reg: read: buf is %x %x %x %x\n", buf[0], buf[1], buf[2], buf[3]); ++ } else if (write_flag ) { ++ struct spi_transfer xfers[3]; ++ _rtw_memset(xfers, 0x00, 3*sizeof(struct spi_transfer)); ++ ++ xfers[0].tx_buf = &cmd; ++ xfers[0].len = 4; ++ ++ xfers[1].tx_buf = &data_tmp; ++ xfers[1].len = 4; ++ ++ xfers[2].rx_buf = status; ++ xfers[2].len = 8; ++ ++ //DBG_8192C("spi_read_write_reg data_tmp 111: %x\n",data_tmp); ++#ifdef CONFIG_BIG_ENDIAN ++ if (!force_bigendian) ++ data_tmp = buf_endian_reverse(data_tmp); ++#else ++ if (force_bigendian) ++ data_tmp = buf_endian_reverse(data_tmp); ++#endif ++ ret = spi_send_msg(pAdapter, xfers, 0); ++ if (ret) { ++ DBG_8192C(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, ret, addr); ++ _rtw_memset(status, 0, 8); ++ } ++ } ++ ++ //padapter->io_fifo_processing = _FALSE; ++ ++ spi_get_status_info(pAdapter, (unsigned char*)status); ++ ++ return ret; ++} ++ ++u8 spi_read8(ADAPTER *Adapter, unsigned int addr, s32 *err) ++{ ++ unsigned int ret = 0; ++ int val32 = 0 , remainder = 0 ; ++ s32 _err = 0; ++ ++ _err = spi_read_write_reg(Adapter,0,addr&0xFFFFFFFC,(char *)&ret,4,0); ++ remainder = addr % 4; ++ val32 = ret; ++ val32 = (val32& (0xff<< (remainder<<3)))>>(remainder<<3); ++ ++ if (err) ++ *err = _err; ++ ++ return (u8)val32; ++ ++} ++ ++u16 spi_read16(ADAPTER *Adapter, u32 addr, s32 *err) ++{ ++ unsigned int ret = 0; ++ int val32 = 0 , remainder = 0 ; ++ s32 _err = 0; ++ ++ _err = spi_read_write_reg(Adapter,0,addr&0xFFFFFFFC,(char *)&ret,4,0); ++ remainder = addr % 4; ++ val32 = ret; ++ val32 = (val32& (0xffff<< (remainder<<3)))>>(remainder<<3); ++ ++ if (err) ++ *err = _err; ++ ++ return (u16)val32; ++} ++ ++u32 spi_read32(ADAPTER *Adapter, u32 addr, s32 *err) ++{ ++ unsigned int ret = 0; ++ s32 _err = 0; ++ ++ _err = spi_read_write_reg(Adapter,0,addr&0xFFFFFFFC,(char *)&ret,4,0); ++ if (err) ++ *err = _err; ++ ++ return ret; ++} ++ ++void spi_write8(ADAPTER *Adapter, u32 addr, u8 buf, s32 *err) ++{ ++ int ret = 0; ++ ++ ret = spi_read_write_reg(Adapter,1,addr,(char *)&buf,1,0); ++ if (err) ++ *err = ret; ++} ++ ++void spi_write16(ADAPTER *Adapter, u32 addr, u16 buf, s32 *err) ++{ ++ int ret = 0; ++ ++ ret = spi_read_write_reg(Adapter,1,addr,(char *)&buf,2,0); ++ if (err) ++ *err = ret; ++} ++ ++void spi_write32(ADAPTER *Adapter, u32 addr, u32 buf, s32 *err) ++{ ++ int ret = 0; ++ ++ ret = spi_read_write_reg(Adapter, 1,addr,(char *)&buf,4,0); ++ if (err) ++ *err = ret; ++} ++ ++unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big) ++{ ++ int ret = 0; ++ ++ ret = spi_read_write_reg(Adapter,1,addr,(char *)&buf,1, big); ++ return ret; ++} ++ ++void spi_write_tx_fifo(ADAPTER *Adapter, u8 *buf, int len, u32 fifo) ++{ ++ int fun =1; //TX_HIQ_FIFO ++ unsigned int cmd = 0; ++ unsigned char status[8]; ++ u8 more_data = 0; ++ int ret = 0; ++ ++ struct spi_transfer xfers[3]; ++ _rtw_memset(xfers, 0x00, 3*sizeof(struct spi_transfer)); ++ ++ xfers[0].tx_buf = &cmd; ++ xfers[0].len = 4; ++ ++ xfers[1].tx_buf = buf; ++ xfers[1].len = len;//len/4; ++ ++ xfers[2].rx_buf = status; ++ xfers[2].len = 8; ++ ++_func_enter_; ++ ++ FIFO_LEN_FORMAT(&cmd, len); //TX Agg len ++ FIFO_DOMAIN_ID_FORMAT(&cmd, fifo); ++ FIFO_FUN_FORMAT(&cmd, fun); ++ FIFO_RW_FORMAT(&cmd, (unsigned int)1); //write ++ ++ _rtw_memset(status, 0x00, 8); ++ ++ ret = spi_send_msg(Adapter, xfers, 1); ++ if (ret) { ++ DBG_8192C("%s: FAIL!(%d)\n", __func__, ret); ++ _rtw_memset(status, 0, 8); ++ } ++ ++ spi_get_status_info(Adapter, status); ++ ++ more_data = GET_STATUS_HISR_LOW8BIT(status) & BIT(0); ++ //if(more_data) { ++ // rtw_queue_delayed_work(Adapter->recv_wq, &Adapter->recv_work, 0, (void*)Adapter); ++ //} ++ ++_func_exit_; ++ ++ return; ++} ++ ++int spi_read_rx_fifo(ADAPTER *Adapter, unsigned char *buf, int len, struct spi_more_data *pmore_data) ++{ ++ int fun =1, domain_id = 0x1f; //RX_FIFO ++ unsigned int cmd = 0; ++ unsigned char status[8]; ++ int ret = 0; ++ struct spi_transfer xfers[3]; ++ ++ _rtw_memset(xfers, 0x00, 3*sizeof(struct spi_transfer)); ++ ++ xfers[0].tx_buf = &cmd; ++ xfers[0].len = 4; ++ ++ xfers[1].rx_buf = buf; ++ xfers[1].len = len; ++ ++ xfers[2].rx_buf = status; ++ xfers[2].len = 8; ++ ++ FIFO_LEN_FORMAT(&cmd, len); //TX Agg len ++ FIFO_DOMAIN_ID_FORMAT(&cmd, domain_id); ++ FIFO_FUN_FORMAT(&cmd, fun); ++ FIFO_RW_FORMAT(&cmd, 0); //read ++ ++ _rtw_memset(status, 0x00, 8); ++ _rtw_memset(buf, 0x0, len); ++ ++ ret = spi_send_msg(Adapter, xfers, 1); ++ if (ret) { ++ DBG_8192C(KERN_ERR "%s: FAIL!(%d)\n", __func__, ret); ++ _rtw_memset(status, 0x00, 8); ++ _rtw_memset(buf, 0x0, len); ++ return _FAIL; ++ } ++ ++ spi_get_status_info(Adapter, (unsigned char*)status); ++ pmore_data->more_data = GET_STATUS_HISR_LOW8BIT(status) & BIT(0); ++ pmore_data->len = GET_STATUS_RX_LENGTH(status); ++ ++ return _SUCCESS; ++} +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_cfg80211.c +new file mode 100644 +index 00000000..da7c494c +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_cfg80211.c +@@ -0,0 +1,5776 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IOCTL_CFG80211_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ ++#include "ioctl_cfg80211.h" ++ ++#define RTW_MAX_MGMT_TX_CNT (8) ++ ++#define RTW_SCAN_IE_LEN_MAX 2304 ++#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 65535 //ms ++#define RTW_MAX_NUM_PMKIDS 4 ++ ++#define RTW_CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */ ++ ++ ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ ++#ifndef WLAN_CIPHER_SUITE_SMS4 ++#define WLAN_CIPHER_SUITE_SMS4 0x00147201 ++#endif ++ ++#ifndef WLAN_AKM_SUITE_WAPI_PSK ++#define WLAN_AKM_SUITE_WAPI_PSK 0x000FAC04 ++#endif ++ ++#ifndef WLAN_AKM_SUITE_WAPI_CERT ++#define WLAN_AKM_SUITE_WAPI_CERT 0x000FAC12 ++#endif ++ ++#ifndef NL80211_WAPI_VERSION_1 ++#define NL80211_WAPI_VERSION_1 (1 << 2) ++#endif ++ ++#endif ++ ++ ++ ++static const u32 rtw_cipher_suites[] = { ++ WLAN_CIPHER_SUITE_WEP40, ++ WLAN_CIPHER_SUITE_WEP104, ++ WLAN_CIPHER_SUITE_TKIP, ++ WLAN_CIPHER_SUITE_CCMP, ++#ifdef CONFIG_IEEE80211W ++ WLAN_CIPHER_SUITE_AES_CMAC, ++#endif //CONFIG_IEEE80211W ++}; ++ ++#define RATETAB_ENT(_rate, _rateid, _flags) \ ++ { \ ++ .bitrate = (_rate), \ ++ .hw_value = (_rateid), \ ++ .flags = (_flags), \ ++ } ++ ++#define CHAN2G(_channel, _freq, _flags) { \ ++ .band = IEEE80211_BAND_2GHZ, \ ++ .center_freq = (_freq), \ ++ .hw_value = (_channel), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++ ++#define CHAN5G(_channel, _flags) { \ ++ .band = IEEE80211_BAND_5GHZ, \ ++ .center_freq = 5000 + (5 * (_channel)), \ ++ .hw_value = (_channel), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++ ++static struct ieee80211_rate rtw_rates[] = { ++ RATETAB_ENT(10, 0x1, 0), ++ RATETAB_ENT(20, 0x2, 0), ++ RATETAB_ENT(55, 0x4, 0), ++ RATETAB_ENT(110, 0x8, 0), ++ RATETAB_ENT(60, 0x10, 0), ++ RATETAB_ENT(90, 0x20, 0), ++ RATETAB_ENT(120, 0x40, 0), ++ RATETAB_ENT(180, 0x80, 0), ++ RATETAB_ENT(240, 0x100, 0), ++ RATETAB_ENT(360, 0x200, 0), ++ RATETAB_ENT(480, 0x400, 0), ++ RATETAB_ENT(540, 0x800, 0), ++}; ++ ++#define rtw_a_rates (rtw_rates + 4) ++#define RTW_A_RATES_NUM 8 ++#define rtw_g_rates (rtw_rates + 0) ++#define RTW_G_RATES_NUM 12 ++ ++#define RTW_2G_CHANNELS_NUM 14 ++#define RTW_5G_CHANNELS_NUM 37 ++ ++static struct ieee80211_channel rtw_2ghz_channels[] = { ++ CHAN2G(1, 2412, 0), ++ CHAN2G(2, 2417, 0), ++ CHAN2G(3, 2422, 0), ++ CHAN2G(4, 2427, 0), ++ CHAN2G(5, 2432, 0), ++ CHAN2G(6, 2437, 0), ++ CHAN2G(7, 2442, 0), ++ CHAN2G(8, 2447, 0), ++ CHAN2G(9, 2452, 0), ++ CHAN2G(10, 2457, 0), ++ CHAN2G(11, 2462, 0), ++ CHAN2G(12, 2467, 0), ++ CHAN2G(13, 2472, 0), ++ CHAN2G(14, 2484, 0), ++}; ++ ++static struct ieee80211_channel rtw_5ghz_a_channels[] = { ++ CHAN5G(34, 0), CHAN5G(36, 0), ++ CHAN5G(38, 0), CHAN5G(40, 0), ++ CHAN5G(42, 0), CHAN5G(44, 0), ++ CHAN5G(46, 0), CHAN5G(48, 0), ++ CHAN5G(52, 0), CHAN5G(56, 0), ++ CHAN5G(60, 0), CHAN5G(64, 0), ++ CHAN5G(100, 0), CHAN5G(104, 0), ++ CHAN5G(108, 0), CHAN5G(112, 0), ++ CHAN5G(116, 0), CHAN5G(120, 0), ++ CHAN5G(124, 0), CHAN5G(128, 0), ++ CHAN5G(132, 0), CHAN5G(136, 0), ++ CHAN5G(140, 0), CHAN5G(149, 0), ++ CHAN5G(153, 0), CHAN5G(157, 0), ++ CHAN5G(161, 0), CHAN5G(165, 0), ++ CHAN5G(184, 0), CHAN5G(188, 0), ++ CHAN5G(192, 0), CHAN5G(196, 0), ++ CHAN5G(200, 0), CHAN5G(204, 0), ++ CHAN5G(208, 0), CHAN5G(212, 0), ++ CHAN5G(216, 0), ++}; ++ ++ ++void rtw_2g_channels_init(struct ieee80211_channel *channels) ++{ ++ _rtw_memcpy((void*)channels, (void*)rtw_2ghz_channels, ++ sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM ++ ); ++} ++ ++void rtw_5g_channels_init(struct ieee80211_channel *channels) ++{ ++ _rtw_memcpy((void*)channels, (void*)rtw_5ghz_a_channels, ++ sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM ++ ); ++} ++ ++void rtw_2g_rates_init(struct ieee80211_rate *rates) ++{ ++ _rtw_memcpy(rates, rtw_g_rates, ++ sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM ++ ); ++} ++ ++void rtw_5g_rates_init(struct ieee80211_rate *rates) ++{ ++ _rtw_memcpy(rates, rtw_a_rates, ++ sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM ++ ); ++} ++ ++struct ieee80211_supported_band *rtw_spt_band_alloc( ++ enum ieee80211_band band ++ ) ++{ ++ struct ieee80211_supported_band *spt_band = NULL; ++ int n_channels, n_bitrates; ++ ++ if(band == IEEE80211_BAND_2GHZ) ++ { ++ n_channels = RTW_2G_CHANNELS_NUM; ++ n_bitrates = RTW_G_RATES_NUM; ++ } ++ else if(band == IEEE80211_BAND_5GHZ) ++ { ++ n_channels = RTW_5G_CHANNELS_NUM; ++ n_bitrates = RTW_A_RATES_NUM; ++ } ++ else ++ { ++ goto exit; ++ } ++ ++ spt_band = (struct ieee80211_supported_band *)rtw_zmalloc( ++ sizeof(struct ieee80211_supported_band) ++ + sizeof(struct ieee80211_channel)*n_channels ++ + sizeof(struct ieee80211_rate)*n_bitrates ++ ); ++ if(!spt_band) ++ goto exit; ++ ++ spt_band->channels = (struct ieee80211_channel*)(((u8*)spt_band)+sizeof(struct ieee80211_supported_band)); ++ spt_band->bitrates= (struct ieee80211_rate*)(((u8*)spt_band->channels)+sizeof(struct ieee80211_channel)*n_channels); ++ spt_band->band = band; ++ spt_band->n_channels = n_channels; ++ spt_band->n_bitrates = n_bitrates; ++ ++ if(band == IEEE80211_BAND_2GHZ) ++ { ++ rtw_2g_channels_init(spt_band->channels); ++ rtw_2g_rates_init(spt_band->bitrates); ++ } ++ else if(band == IEEE80211_BAND_5GHZ) ++ { ++ rtw_5g_channels_init(spt_band->channels); ++ rtw_5g_rates_init(spt_band->bitrates); ++ } ++ ++ //spt_band.ht_cap ++ ++exit: ++ ++ return spt_band; ++} ++ ++void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) ++{ ++ u32 size; ++ ++ if(!spt_band) ++ return; ++ ++ if(spt_band->band == IEEE80211_BAND_2GHZ) ++ { ++ size = sizeof(struct ieee80211_supported_band) ++ + sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM ++ + sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM; ++ } ++ else if(spt_band->band == IEEE80211_BAND_5GHZ) ++ { ++ size = sizeof(struct ieee80211_supported_band) ++ + sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM ++ + sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM; ++ } ++ else ++ { ++ ++ } ++ rtw_mfree((u8*)spt_band, size); ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++static const struct ieee80211_txrx_stypes ++rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = { ++ [NL80211_IFTYPE_ADHOC] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_STATION] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) ++ }, ++ [NL80211_IFTYPE_AP] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_AP_VLAN] = { ++ /* copy AP */ ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_P2P_CLIENT] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) ++ }, ++ [NL80211_IFTYPE_P2P_GO] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++}; ++#endif ++ ++static int rtw_ieee80211_channel_to_frequency(int chan, int band) ++{ ++ /* see 802.11 17.3.8.3.2 and Annex J ++ * there are overlapping channel numbers in 5GHz and 2GHz bands */ ++ ++ if (band == IEEE80211_BAND_5GHZ) { ++ if (chan >= 182 && chan <= 196) ++ return 4000 + chan * 5; ++ else ++ return 5000 + chan * 5; ++ } else { /* IEEE80211_BAND_2GHZ */ ++ if (chan == 14) ++ return 2484; ++ else if (chan < 14) ++ return 2407 + chan * 5; ++ else ++ return 0; /* not supported */ ++ } ++} ++ ++#define MAX_BSSINFO_LEN 1000 ++struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork) ++{ ++ struct ieee80211_channel *notify_channel; ++ struct cfg80211_bss *bss = NULL; ++ //struct ieee80211_supported_band *band; ++ u16 channel; ++ u32 freq; ++ u64 notify_timestamp; ++ u16 notify_capability; ++ u16 notify_interval; ++ u8 *notify_ie; ++ size_t notify_ielen; ++ s32 notify_signal; ++ u8 buf[MAX_BSSINFO_LEN], *pbuf; ++ size_t len,bssinf_len=0; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ struct wireless_dev *wdev = padapter->rtw_wdev; ++ struct wiphy *wiphy = wdev->wiphy; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ++ //DBG_8192C("%s\n", __func__); ++ ++ bssinf_len = pnetwork->network.IELength+sizeof (struct rtw_ieee80211_hdr_3addr); ++ if(bssinf_len > MAX_BSSINFO_LEN){ ++ DBG_871X("%s IE Length too long > %d byte \n",__FUNCTION__,MAX_BSSINFO_LEN); ++ goto exit; ++ } ++ ++ //To reduce PBC Overlap rate ++ //_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ if(wdev_to_priv(wdev)->scan_request != NULL) ++ { ++ u8 *psr=NULL, sr = 0; ++ NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid; ++ struct cfg80211_scan_request *request = wdev_to_priv(wdev)->scan_request; ++ struct cfg80211_ssid *ssids = request->ssids; ++ u32 wpsielen=0; ++ u8 *wpsie=NULL; ++ ++ wpsie = rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen); ++ ++ if(wpsie && wpsielen>0) ++ psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); ++ ++ if (sr != 0) ++ { ++ if(request->n_ssids == 1 && request->n_channels == 1) // it means under processing WPS ++ { ++ DBG_8192C("ssid=%s, len=%d\n", pssid->Ssid, pssid->SsidLength); ++ ++ if (ssids[0].ssid_len == 0) { ++ } ++ else if(pssid->SsidLength == ssids[0].ssid_len && ++ _rtw_memcmp(pssid->Ssid, ssids[0].ssid, ssids[0].ssid_len)) ++ { ++ DBG_871X("%s, got sr and ssid match!\n", __func__); ++ } ++ else ++ { ++ if(psr !=NULL) ++ *psr = 0; //clear sr ++ ++#if 0 ++ WLAN_BSSID_EX *pselect_network = &pnetwork->network; ++ struct cfg80211_bss *pselect_bss = NULL; ++ struct ieee80211_channel *notify_channel = NULL; ++ u32 freq; ++ ++ DBG_871X("%s, got sr, but ssid mismatch, to remove this bss\n", __func__); ++ ++ if (pselect_network->Configuration.DSConfig <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(pselect_network->Configuration.DSConfig, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(pselect_network->Configuration.DSConfig, IEEE80211_BAND_5GHZ); ++ ++ notify_channel = ieee80211_get_channel(wiphy, freq); ++ pselect_bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/, ++ pselect_network->MacAddress, pselect_network->Ssid.Ssid, ++ pselect_network->Ssid.SsidLength, 0/*WLAN_CAPABILITY_ESS*/, ++ 0/*WLAN_CAPABILITY_ESS*/); ++ ++ if(pselect_bss) ++ { ++ DBG_871X("%s, got bss for cfg80211 for unlinking bss\n", __func__); ++ ++ cfg80211_unlink_bss(wiphy, pselect_bss); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) ++ cfg80211_put_bss(wiphy, pselect_bss); ++#else ++ cfg80211_put_bss(pselect_bss); ++#endif ++ ++ } ++ ++ goto exit; ++#endif ++ } ++ } ++ } ++ } ++ //_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ ++ channel = pnetwork->network.Configuration.DSConfig; ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++ notify_channel = ieee80211_get_channel(wiphy, freq); ++ ++ //rtw_get_timestampe_from_ie() ++ notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */ ++ ++ notify_interval = le16_to_cpu(*(u16*)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs)); ++ notify_capability = le16_to_cpu(*(u16*)rtw_get_capability_from_ie(pnetwork->network.IEs)); ++ ++ ++ notify_ie = pnetwork->network.IEs+_FIXED_IE_LENGTH_; ++ notify_ielen = pnetwork->network.IELength-_FIXED_IE_LENGTH_; ++ ++ //We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) ++ if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && ++ is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { ++ notify_signal = 100*translate_percentage_to_dbm(padapter->recvpriv.signal_strength);//dbm ++ } else { ++ notify_signal = 100*translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm ++ } ++ ++ #if 0 ++ DBG_8192C("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress)); ++ DBG_8192C("Channel: %d(%d)\n", channel, freq); ++ DBG_8192C("Capability: %X\n", notify_capability); ++ DBG_8192C("Beacon interval: %d\n", notify_interval); ++ DBG_8192C("Signal: %d\n", notify_signal); ++ DBG_8192C("notify_timestamp: %#018llx\n", notify_timestamp); ++ #endif ++ ++ pbuf = buf; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf; ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ ++ if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ SetFrameSubType(pbuf, WIFI_BEACON); ++ } else { ++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ SetFrameSubType(pbuf, WIFI_PROBERSP); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN); ++ ++ ++ pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); ++ len = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ _rtw_memcpy(pbuf, pnetwork->network.IEs, pnetwork->network.IELength); ++ len += pnetwork->network.IELength; ++ ++ //#ifdef CONFIG_P2P ++ //if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL)) ++ //{ ++ // DBG_8192C("%s, got p2p_ie\n", __func__); ++ //} ++ //#endif ++ ++ ++#if 1 ++ bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)buf, ++ len, notify_signal, GFP_ATOMIC); ++#else ++ ++ bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress, ++ notify_timestamp, notify_capability, notify_interval, notify_ie, ++ notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/); ++#endif ++ ++ if (unlikely(!bss)) { ++ DBG_8192C(FUNC_ADPT_FMT" bss NULL\n", FUNC_ADPT_ARG(padapter)); ++ goto exit; ++ } ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) ++#ifndef COMPAT_KERNEL_RELEASE ++ //patch for cfg80211, update beacon ies to information_elements ++ if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON ++ ++ if(bss->len_information_elements != bss->len_beacon_ies) ++ { ++ bss->information_elements = bss->beacon_ies; ++ bss->len_information_elements = bss->len_beacon_ies; ++ } ++ } ++#endif //COMPAT_KERNEL_RELEASE ++#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) ++ ++/* ++ { ++ if( bss->information_elements == bss->proberesp_ies) ++ { ++ if( bss->len_information_elements != bss->len_proberesp_ies) ++ { ++ DBG_8192C("error!, len_information_elements != bss->len_proberesp_ies\n"); ++ } ++ ++ } ++ else if(bss->len_information_elements < bss->len_beacon_ies) ++ { ++ bss->information_elements = bss->beacon_ies; ++ bss->len_information_elements = bss->len_beacon_ies; ++ } ++ } ++*/ ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) ++ cfg80211_put_bss(wiphy, bss); ++#else ++ cfg80211_put_bss(bss); ++#endif ++ ++exit: ++ return bss; ++ ++} ++ ++/* ++ Check the given bss is valid by kernel API cfg80211_get_bss() ++ @padapter : the given adapter ++ ++ return _TRUE if bss is valid, _FALSE for not found. ++*/ ++int rtw_cfg80211_check_bss(_adapter *padapter) ++{ ++ WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); ++ struct cfg80211_bss *bss = NULL; ++ struct ieee80211_channel *notify_channel = NULL; ++ u32 freq; ++ ++ if (!(pnetwork) || !(padapter->rtw_wdev)) ++ return _FALSE; ++ ++ if (pnetwork->Configuration.DSConfig <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(pnetwork->Configuration.DSConfig, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(pnetwork->Configuration.DSConfig, IEEE80211_BAND_5GHZ); ++ ++ notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq); ++ bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel, ++ pnetwork->MacAddress, pnetwork->Ssid.Ssid, ++ pnetwork->Ssid.SsidLength, ++ WLAN_CAPABILITY_ESS, WLAN_CAPABILITY_ESS); ++ ++ return (bss!=NULL); ++} ++ ++void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct cfg80211_bss *bss = NULL; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ if (pwdev->iftype != NL80211_IFTYPE_ADHOC) ++ { ++ return; ++ } ++ ++ if (!rtw_cfg80211_check_bss(padapter)) { ++ WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); ++ struct wlan_network *scanned = pmlmepriv->cur_network_scanned; ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE) ++ { ++ ++ _rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX)); ++ if(cur_network) ++ { ++ if (!rtw_cfg80211_inform_bss(padapter,cur_network)) ++ DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); ++ else ++ DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); ++ } ++ else ++ { ++ DBG_871X("cur_network is not exist!!!\n"); ++ return ; ++ } ++ } ++ else ++ { ++ if(scanned == NULL) ++ rtw_warn_on(1); ++ ++ if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE ++ && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ++ ) { ++ if (!rtw_cfg80211_inform_bss(padapter,scanned)) { ++ DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); ++ } else { ++ //DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); ++ } ++ } else { ++ DBG_871X("scanned & pnetwork compare fail\n"); ++ rtw_warn_on(1); ++ } ++ } ++ ++ if (!rtw_cfg80211_check_bss(padapter)) ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); ++ } ++ //notify cfg80211 that device joined an IBSS ++ cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); ++} ++ ++void rtw_cfg80211_indicate_connect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif ++ struct cfg80211_bss *bss = NULL; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ if (pwdev->iftype != NL80211_IFTYPE_STATION ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT ++ #endif ++ ) { ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ return; ++ ++#ifdef CONFIG_P2P ++ if(pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ } ++ } ++#endif //CONFIG_P2P ++ ++ { ++ WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); ++ struct wlan_network *scanned = pmlmepriv->cur_network_scanned; ++ ++ //DBG_871X(FUNC_ADPT_FMT" BSS not found\n", FUNC_ADPT_ARG(padapter)); ++ ++ if(scanned == NULL) { ++ rtw_warn_on(1); ++ goto check_bss; ++ } ++ ++ if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ++ && _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE ++ ) { ++ if (!rtw_cfg80211_inform_bss(padapter,scanned)) { ++ DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); ++ } else { ++ //DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); ++ } ++ } else { ++ DBG_871X("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n", ++ scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress), ++ pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress) ++ ); ++ rtw_warn_on(1); ++ } ++ } ++ ++check_bss: ++ if (!rtw_cfg80211_check_bss(padapter)) ++ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if (rtw_to_roaming(padapter) > 0) { ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) ++ struct wiphy *wiphy = pwdev->wiphy; ++ struct ieee80211_channel *notify_channel; ++ u32 freq; ++ u16 channel = cur_network->network.Configuration.DSConfig; ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++ notify_channel = ieee80211_get_channel(wiphy, freq); ++ #endif ++ ++ DBG_871X(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); ++ cfg80211_roamed(padapter->pnetdev ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) ++ , notify_channel ++ #endif ++ , cur_network->network.MacAddress ++ , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2 ++ , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2 ++ , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6 ++ , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6 ++ , GFP_ATOMIC); ++ } ++ else ++ #endif ++ { ++ DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state); ++ cfg80211_connect_result(padapter->pnetdev, cur_network->network.MacAddress ++ , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2 ++ , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2 ++ , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6 ++ , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6 ++ , WLAN_STATUS_SUCCESS, GFP_ATOMIC); ++ DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state); ++ } ++} ++ ++void rtw_cfg80211_indicate_disconnect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++ if (pwdev->iftype != NL80211_IFTYPE_STATION ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT ++ #endif ++ ) { ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ return; ++ ++#ifdef CONFIG_P2P ++ if( pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ ++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ } ++ } ++#endif //CONFIG_P2P ++ ++ if (!padapter->mlmepriv.not_indic_disco) { ++ DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state); ++ ++ if(pwdev->sme_state==CFG80211_SME_CONNECTING) ++ cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, ++ WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC/*GFP_KERNEL*/); ++ else if(pwdev->sme_state==CFG80211_SME_CONNECTED) ++ cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); ++ //else ++ //DBG_8192C("pwdev->sme_state=%d\n", pwdev->sme_state); ++ ++ DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state); ++ } ++} ++ ++ ++#ifdef CONFIG_AP_MODE ++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ++ ++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; ++ ++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); ++ ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++ ++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) ++{ ++ u8 keylen; ++ struct cmd_obj* pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv); ++ int res=_SUCCESS; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ psetkeyparm->keyid=(u8)keyid; ++ if (is_wep_enc(alg)) ++ padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); ++ ++ psetkeyparm->algorithm = alg; ++ ++ psetkeyparm->set_tx = 1; ++ ++ switch(alg) ++ { ++ case _WEP40_: ++ keylen = 5; ++ break; ++ case _WEP104_: ++ keylen = 13; ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ case _AES_: ++ keylen = 16; ++ default: ++ keylen = 16; ++ } ++ ++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++ return res; ++ ++ ++} ++ ++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid) ++{ ++ u8 alg; ++ ++ switch(keylen) ++ { ++ case 5: ++ alg =_WEP40_; ++ break; ++ case 13: ++ alg =_WEP104_; ++ break; ++ default: ++ alg =_NO_PRIVACY_; ++ } ++ ++ return set_group_key(padapter, key, alg, keyid); ++ ++} ++ ++static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ struct sta_info *psta = NULL, *pbcmc_sta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ //sizeof(struct ieee_param) = 64 bytes; ++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(!psta) ++ { ++ //ret = -EINVAL; ++ DBG_8192C("rtw_set_encryption(), sta has already been removed or never been added\n"); ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) ++ { ++ //todo:clear default encryption keys ++ ++ DBG_8192C("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); ++ ++ goto exit; ++ } ++ ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) ++ { ++ DBG_8192C("r871x_set_encryption, crypt.alg = WEP\n"); ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ DBG_8192C("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); ++ ++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ } ++ ++ if (psecuritypriv->bWepDefaultKeyIdxSet == 0) ++ { ++ //wep default key has not been set, so use this key index as default key. ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_; ++ ++ if(wep_key_len == 13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_; ++ } ++ ++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; ++ } ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; ++ ++ set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx); ++ ++ goto exit; ++ ++ } ++ ++ ++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key ++ { ++ if(param->u.crypt.set_tx == 0) //group key ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set group_key, WEP\n", __FUNCTION__); ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set group_key, TKIP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ DBG_8192C("%s, set group_key, CCMP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ DBG_8192C("%s, set group_key, none\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x ++ { ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ if(param->u.crypt.set_tx ==1) //pairwise key ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, WEP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psta->dot118021XPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, TKIP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _TKIP_; ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ ++ DBG_8192C("%s, set pairwise key, CCMP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _AES_; ++ } ++ else ++ { ++ DBG_8192C("%s, set pairwise key, none\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _NO_PRIVACY_; ++ } ++ ++ set_pairwise_key(padapter, psta); ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ psta->bpairwise_key_installed = _TRUE; ++ ++ } ++ else//group key??? ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++#endif ++ ++static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++ DBG_8192C("%s\n", __func__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS ++#ifdef CONFIG_IEEE80211W ++ && param->u.crypt.idx > BIP_MAX_KEYID ++#endif //CONFIG_IEEE80211W ++ ) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } else { ++#ifdef CONFIG_WAPI_SUPPORT ++ if (strcmp(param->u.crypt.alg, "SMS4")) ++#endif ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); ++ DBG_8192C("wpa_set_encryption, crypt.alg = WEP\n"); ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (psecuritypriv->bWepDefaultKeyIdxSet == 0) ++ { ++ //wep default key has not been set, so use this key index as default key. ++ ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ ++ if(wep_key_len==13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; ++ } ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; ++ ++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0,_TRUE); ++ ++ goto exit; ++ } ++ ++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x ++ { ++ struct sta_info * psta,*pbcmc_sta; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ ++ //DBG_8192C("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X \n", __func__); ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ DBG_8192C("%s, : Obtain Sta_info fail \n", __func__); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ psta->ieee8021x_blocked = _FALSE; ++ ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ if(param->u.crypt.set_tx ==1)//pairwise key ++ { ++ ++ DBG_8192C("%s, : param->u.crypt.set_tx ==1 \n", __func__); ++ ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key ++ { ++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ padapter->securitypriv.busetkipkey=_FALSE; ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ } ++ ++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); ++ DBG_871X(" ~~~~set sta key:unicastkey\n"); ++ ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE, _TRUE); ++ } ++ else//group key ++ { ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); ++ padapter->securitypriv.binstallGrpkey = _TRUE; ++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ DBG_871X(" ~~~~set sta key:groupkey\n"); ++ ++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->adapter_type == PRIMARY_ADAPTER) ++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1,_TRUE); ++ else ++ DBG_871X_LEVEL(_drv_always_, "second interface do not set cam.\n"); ++#else ++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1,_TRUE); ++#endif ++ } ++#ifdef CONFIG_IEEE80211W ++ else if(strcmp(param->u.crypt.alg, "BIP") == 0) ++ { ++ int no; ++ //DBG_871X("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); ++ //save the IGTK key, length 16 bytes ++ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ /*DBG_871X("IGTK key below:\n"); ++ for(no=0;no<16;no++) ++ printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); ++ DBG_871X("\n");*/ ++ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; ++ padapter->securitypriv.binstallBIPkey = _TRUE; ++ DBG_871X(" ~~~~set sta key:IGKT\n"); ++ } ++#endif //CONFIG_IEEE80211W ++ ++#ifdef CONFIG_P2P ++ if(pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); ++ } ++ } ++#endif //CONFIG_P2P ++ ++ } ++ } ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta==NULL) ++ { ++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ } ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode ++ { ++ } ++ } ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if (strcmp(param->u.crypt.alg, "SMS4") == 0) ++ { ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ PRT_WAPI_STA_INFO pWapiSta; ++ u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ ++ if(param->u.crypt.set_tx == 1) ++ { ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(_rtw_memcmp(pWapiSta->PeerMacAddr,param->sta_addr,6)) ++ { ++ _rtw_memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ ++ pWapiSta->wapiUsk.bSet = true; ++ _rtw_memcpy(pWapiSta->wapiUsk.dataKey,param->u.crypt.key,16); ++ _rtw_memcpy(pWapiSta->wapiUsk.micKey,param->u.crypt.key+16,16); ++ pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; ++ pWapiSta->wapiUsk.bTxEnable = true; ++ ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPN,WapiAEPNInitialValueSrc,16); ++ pWapiSta->wapiUskUpdate.bTxEnable = false; ++ pWapiSta->wapiUskUpdate.bSet = false; ++ ++ if (psecuritypriv->sw_encrypt== false || psecuritypriv->sw_decrypt == false) ++ { ++ //set unicast key for ASUE ++ rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); ++ } ++ } ++ } ++ } ++ else ++ { ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(_rtw_memcmp(pWapiSta->PeerMacAddr,get_bssid(pmlmepriv),6)) ++ { ++ pWapiSta->wapiMsk.bSet = true; ++ _rtw_memcpy(pWapiSta->wapiMsk.dataKey,param->u.crypt.key,16); ++ _rtw_memcpy(pWapiSta->wapiMsk.micKey,param->u.crypt.key+16,16); ++ pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; ++ pWapiSta->wapiMsk.bTxEnable = false; ++ if(!pWapiSta->bSetkeyOk) ++ pWapiSta->bSetkeyOk = true; ++ pWapiSta->bAuthenticateInProgress = false; ++ ++ _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); ++ ++ if (psecuritypriv->sw_decrypt == false) ++ { ++ //set rx broadcast key for ASUE ++ rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); ++ } ++ } ++ ++ } ++ } ++ } ++#endif ++ ++ ++exit: ++ ++ DBG_8192C("%s, ret=%d\n", __func__, ret); ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ u8 key_index, bool pairwise, const u8 *mac_addr, ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr, ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ struct key_params *params) ++{ ++ char *alg_name; ++ u32 param_len; ++ struct ieee_param *param = NULL; ++ int ret=0; ++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy); ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ DBG_871X(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); ++ DBG_871X("cipher=0x%x\n", params->cipher); ++ DBG_871X("key_len=0x%x\n", params->key_len); ++ DBG_871X("seq_len=0x%x\n", params->seq_len); ++ DBG_871X("key_index=%d\n", key_index); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ DBG_871X("pairwise=%d\n", pairwise); ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ ++ param_len = sizeof(struct ieee_param) + params->key_len; ++ param = (struct ieee_param *)rtw_malloc(param_len); ++ if (param == NULL) ++ return -1; ++ ++ _rtw_memset(param, 0, param_len); ++ ++ param->cmd = IEEE_CMD_SET_ENCRYPTION; ++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); ++ ++ switch (params->cipher) { ++ case IW_AUTH_CIPHER_NONE: ++ //todo: remove key ++ //remove = 1; ++ alg_name = "none"; ++ break; ++ case WLAN_CIPHER_SUITE_WEP40: ++ case WLAN_CIPHER_SUITE_WEP104: ++ alg_name = "WEP"; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ alg_name = "TKIP"; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ alg_name = "CCMP"; ++ break; ++#ifdef CONFIG_IEEE80211W ++ case WLAN_CIPHER_SUITE_AES_CMAC: ++ alg_name = "BIP"; ++ break; ++#endif //CONFIG_IEEE80211W ++#ifdef CONFIG_WAPI_SUPPORT ++ case WLAN_CIPHER_SUITE_SMS4: ++ alg_name= "SMS4"; ++ if(pairwise == NL80211_KEYTYPE_PAIRWISE) { ++ if (key_index != 0 && key_index != 1) { ++ ret = -ENOTSUPP; ++ goto addkey_end; ++ } ++ _rtw_memcpy((void*)param->sta_addr, (void*)mac_addr, ETH_ALEN); ++ } else { ++ DBG_871X("mac_addr is null \n"); ++ } ++ DBG_871X("rtw_wx_set_enc_ext: SMS4 case \n"); ++ break; ++#endif ++ ++ default: ++ ret = -ENOTSUPP; ++ goto addkey_end; ++ } ++ ++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); ++ ++ ++ if (!mac_addr || is_broadcast_ether_addr(mac_addr)) ++ { ++ param->u.crypt.set_tx = 0; //for wpa/wpa2 group key ++ } else { ++ param->u.crypt.set_tx = 1; //for wpa/wpa2 pairwise key ++ } ++ ++ ++ //param->u.crypt.idx = key_index - 1; ++ param->u.crypt.idx = key_index; ++ ++ if (params->seq_len && params->seq) ++ { ++ _rtw_memcpy(param->u.crypt.seq, params->seq, params->seq_len); ++ } ++ ++ if(params->key_len && params->key) ++ { ++ param->u.crypt.key_len = params->key_len; ++ _rtw_memcpy(param->u.crypt.key, params->key, params->key_len); ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ ret = rtw_cfg80211_set_encryption(ndev, param, param_len); ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_AP_MODE ++ if(mac_addr) ++ _rtw_memcpy(param->sta_addr, (void*)mac_addr, ETH_ALEN); ++ ++ ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); ++#endif ++ } ++ else ++ { ++ DBG_8192C("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); ++ ++ } ++ ++addkey_end: ++ if(param) ++ { ++ rtw_mfree((u8*)param, param_len); ++ } ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ u8 key_index, bool pairwise, const u8 *mac_addr, ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr, ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ void *cookie, ++ void (*callback)(void *cookie, ++ struct key_params*)) ++{ ++#if 0 ++ struct iwm_priv *iwm = ndev_to_iwm(ndev); ++ struct iwm_key *key = &iwm->keys[key_index]; ++ struct key_params params; ++ ++ IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index); ++ ++ memset(¶ms, 0, sizeof(params)); ++ ++ params.cipher = key->cipher; ++ params.key_len = key->key_len; ++ params.seq_len = key->seq_len; ++ params.seq = key->seq; ++ params.key = key->key; ++ ++ callback(cookie, ¶ms); ++ ++ return key->key_len ? 0 : -ENOENT; ++#endif ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ return 0; ++} ++ ++static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ u8 key_index, bool pairwise, const u8 *mac_addr) ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr) ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ DBG_871X(FUNC_NDEV_FMT" key_index=%d\n", FUNC_NDEV_ARG(ndev), key_index); ++ ++ if (key_index == psecuritypriv->dot11PrivacyKeyIndex) ++ { ++ //clear the flag of wep default key set. ++ psecuritypriv->bWepDefaultKeyIdxSet = 0; ++ } ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, ++ struct net_device *ndev, u8 key_index ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ , bool unicast, bool multicast ++ #endif ++ ) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ DBG_871X(FUNC_NDEV_FMT" key_index=%d" ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ ", unicast=%d, multicast=%d" ++ #endif ++ ".\n", FUNC_NDEV_ARG(ndev), key_index ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ , unicast, multicast ++ #endif ++ ); ++ ++ if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) //set wep default key ++ { ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++ psecuritypriv->dot11PrivacyKeyIndex = key_index; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if (psecuritypriv->dot11DefKeylen[key_index] == 13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ psecuritypriv->bWepDefaultKeyIdxSet = 1; //set the flag to represent that wep default key has been set ++ } ++ ++ return 0; ++ ++} ++ ++static int cfg80211_rtw_get_station(struct wiphy *wiphy, ++ struct net_device *ndev, ++ u8 *mac, struct station_info *sinfo) ++{ ++ int ret = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ sinfo->filled = 0; ++ ++ if (!mac) { ++ DBG_871X(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac); ++ ret = -ENOENT; ++ goto exit; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, mac); ++ if (psta == NULL) { ++ DBG_8192C("%s, sta_info is null\n", __func__); ++ ret = -ENOENT; ++ goto exit; ++ } ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); ++#endif ++ ++ //for infra./P2PClient mode ++ if( check_fwstate(pmlmepriv, WIFI_STATION_STATE) ++ && check_fwstate(pmlmepriv, _FW_LINKED) ++ ) ++ { ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ ++ if (_rtw_memcmp(mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) { ++ DBG_871X("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress)); ++ ret = -ENOENT; ++ goto exit; ++ } ++ ++ sinfo->filled |= STATION_INFO_SIGNAL; ++ sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); ++ ++ sinfo->filled |= STATION_INFO_TX_BITRATE; ++ sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter); ++ ++ sinfo->filled |= STATION_INFO_RX_PACKETS; ++ sinfo->rx_packets = sta_rx_data_pkts(psta); ++ ++ sinfo->filled |= STATION_INFO_TX_PACKETS; ++ sinfo->tx_packets = psta->sta_stats.tx_pkts; ++ ++ } ++ ++ //for Ad-Hoc/AP mode ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ++ ||check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ++ ||check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ && check_fwstate(pmlmepriv, _FW_LINKED) ++ ) ++ { ++ //TODO: should acquire station info... ++ } ++ ++exit: ++ return ret; ++} ++ ++extern int netdev_open(struct net_device *pnetdev); ++#ifdef CONFIG_CONCURRENT_MODE ++extern int netdev_if2_open(struct net_device *pnetdev); ++#endif ++ ++/* ++enum nl80211_iftype { ++ NL80211_IFTYPE_UNSPECIFIED, ++ NL80211_IFTYPE_ADHOC, //1 ++ NL80211_IFTYPE_STATION, //2 ++ NL80211_IFTYPE_AP, //3 ++ NL80211_IFTYPE_AP_VLAN, ++ NL80211_IFTYPE_WDS, ++ NL80211_IFTYPE_MONITOR, //6 ++ NL80211_IFTYPE_MESH_POINT, ++ NL80211_IFTYPE_P2P_CLIENT, //8 ++ NL80211_IFTYPE_P2P_GO, //9 ++ //keep last ++ NUM_NL80211_IFTYPES, ++ NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1 ++}; ++*/ ++static int cfg80211_rtw_change_iface(struct wiphy *wiphy, ++ struct net_device *ndev, ++ enum nl80211_iftype type, u32 *flags, ++ struct vif_params *params) ++{ ++ enum nl80211_iftype old_type; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy); ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif ++ int ret = 0; ++ u8 change = _FALSE; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ if(adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) ++ { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->adapter_type == SECONDARY_ADAPTER) ++ { ++ DBG_871X(FUNC_NDEV_FMT" call netdev_if2_open\n", FUNC_NDEV_ARG(ndev)); ++ if(netdev_if2_open(ndev) != 0) { ++ ret= -EPERM; ++ goto exit; ++ } ++ } ++ else if(padapter->adapter_type == PRIMARY_ADAPTER) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ DBG_871X(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev)); ++ if(netdev_open(ndev) != 0) { ++ ret= -EPERM; ++ goto exit; ++ } ++ } ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ old_type = rtw_wdev->iftype; ++ DBG_871X(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n", ++ FUNC_NDEV_ARG(ndev), old_type, type); ++ ++ if(old_type != type) ++ { ++ change = _TRUE; ++ pmlmeext->action_public_rxseq = 0xffff; ++ pmlmeext->action_public_dialog_token = 0xff; ++ } ++ ++ switch (type) { ++ case NL80211_IFTYPE_ADHOC: ++ networkType = Ndis802_11IBSS; ++ break; ++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) ++ case NL80211_IFTYPE_P2P_CLIENT: ++#endif ++ case NL80211_IFTYPE_STATION: ++ networkType = Ndis802_11Infrastructure; ++ #ifdef CONFIG_P2P ++ if(pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(change && rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ //it means remove GO and change mode from AP(GO) to station(P2P DEVICE) ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ ++ DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ } ++ } ++ #endif //CONFIG_P2P ++ break; ++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) ++ case NL80211_IFTYPE_P2P_GO: ++#endif ++ case NL80211_IFTYPE_AP: ++ networkType = Ndis802_11APMode; ++ #ifdef CONFIG_P2P ++ if(pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(change && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ //it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO) ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ #endif //CONFIG_P2P ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ rtw_wdev->iftype = type; ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE) ++ { ++ rtw_wdev->iftype = old_type; ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ rtw_setopmode_cmd(padapter, networkType,_TRUE); ++ ++exit: ++ ++ return ret; ++} ++ ++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ if(pwdev_priv->scan_request != NULL) ++ { ++ //struct cfg80211_scan_request *scan_request = pwdev_priv->scan_request; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s with scan req\n", __FUNCTION__); ++ #endif ++ ++ //avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); ++ //if(scan_request == wiphy_to_dev(scan_request->wiphy)->scan_req) ++ if(pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy) ++ { ++ DBG_8192C("error wiphy compare\n"); ++ } ++ else ++ { ++ cfg80211_scan_done(pwdev_priv->scan_request, aborted); ++ } ++ ++ pwdev_priv->scan_request = NULL; ++ ++ } else { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s without scan req\n", __FUNCTION__); ++ #endif ++ } ++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++} ++ ++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ sint wait_status; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s\n", __func__); ++#endif ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //report network only if the current channel set contains the channel to which this network belongs ++ if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 ++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) ++ ) ++ { ++ //ev=translate_scan(padapter, a, pnetwork, ev, stop); ++ rtw_cfg80211_inform_bss(padapter, pnetwork); ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ //call this after other things have been done ++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), _FALSE); ++} ++ ++static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 *p2p_ie; ++ u32 wfd_ielen = 0; ++ u8 *wfd_ie; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_req_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(pmlmepriv->wps_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_req_ie_len; ++ pmlmepriv->wps_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); ++ pmlmepriv->wps_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_probe_req_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_probe_req_ie_len = wps_ielen; ++ } ++ ++ //buf += wps_ielen; ++ //len -= wps_ielen; ++ ++ #ifdef CONFIG_P2P ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ struct wifidirect_info *wdinfo = &padapter->wdinfo; ++ u32 attr_contentlen = 0; ++ u8 listen_ch_attr[5]; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_req_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_probe_req_ie_len; ++ pmlmepriv->p2p_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len); ++ pmlmepriv->p2p_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_probe_req_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_probe_req_ie_len = p2p_ielen; ++ ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8*)listen_ch_attr, (uint*) &attr_contentlen) ++ && attr_contentlen == 5) ++ { ++ if (wdinfo->listen_channel != listen_ch_attr[4]) { ++ DBG_871X(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n", ++ FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2], ++ listen_ch_attr[3], listen_ch_attr[4]); ++ wdinfo->listen_channel = listen_ch_attr[4]; ++ } ++ } ++ } ++ #endif //CONFIG_P2P ++ ++ //buf += p2p_ielen; ++ //len -= p2p_ielen; ++ ++ #ifdef CONFIG_WFD ++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen)) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_req_wfd_ielen=%d\n", wfd_ielen); ++ #endif ++ ++ if(pmlmepriv->wfd_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->wfd_probe_req_ie_len; ++ pmlmepriv->wfd_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wfd_probe_req_ie, free_len); ++ pmlmepriv->wfd_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->wfd_probe_req_ie = rtw_malloc(wfd_ielen); ++ if ( pmlmepriv->wfd_probe_req_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len); ++ } ++ #endif //CONFIG_WFD ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_scan(struct wiphy *wiphy ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) ++ , struct net_device *ndev ++ #endif ++ , struct cfg80211_scan_request *request) ++{ ++ int i; ++ u8 _status = _FALSE; ++ int ret = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++ struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; ++ _irqL irqL; ++ u8 *wps_ie=NULL; ++ uint wps_ielen=0; ++ u8 *p2p_ie=NULL; ++ uint p2p_ielen=0; ++ u8 survey_times=3; ++ u8 survey_times_for_one_ch=6; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct cfg80211_ssid *ssids = request->ssids; ++ int social_channel = 0, j = 0; ++ bool need_indicate_scan_done = _FALSE; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = NULL; ++ struct mlme_priv *pbuddy_mlmepriv = NULL; ++#endif //CONFIG_CONCURRENT_MODE ++ ++//#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++//#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->pbuddy_adapter) { ++ pbuddy_adapter = padapter->pbuddy_adapter; ++ pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++ } ++#endif //CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_MP_INCLUDED ++if (padapter->registrypriv.mp_mode == 1) ++{ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ret = -EPERM; ++ goto exit; ++ } ++} ++#endif ++ ++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ pwdev_priv->scan_request = request; ++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s under WIFI_AP_STATE\n", __FUNCTION__); ++#endif ++ ++ if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS|_FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); ++ ++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) ++ { ++ DBG_8192C("AP mode process WPS \n"); ++ } ++ ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ } ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ #ifdef CONFIG_P2P ++ if( pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(ssids->ssid != NULL ++ && _rtw_memcmp(ssids->ssid, "DIRECT-", 7) ++ && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) ++ ) ++ { ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE; ++ } ++ else ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++ #endif ++ } ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ ++ if(request->n_channels == 3 && ++ request->channels[0]->hw_value == 1 && ++ request->channels[1]->hw_value == 6 && ++ request->channels[2]->hw_value == 11 ++ ) ++ { ++ social_channel = 1; ++ } ++ } ++ } ++ #endif //CONFIG_P2P ++ ++ if(request->ie && request->ie_len>0) ++ { ++ rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len ); ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); ++ ret = -EBUSY; ++ goto check_need_indicate_scan_done; ++ } ++ ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) ++ { ++ DBG_8192C("%s, bBusyTraffic == _TRUE\n", __func__); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ if (rtw_is_scan_deny(padapter)){ ++ DBG_871X(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pbuddy_mlmepriv && (pbuddy_mlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) ++ { ++ DBG_8192C("%s, bBusyTraffic == _TRUE at buddy_intf\n", __func__); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ if (check_buddy_fwstate(padapter, ++ _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) ++ { ++ if(check_buddy_fwstate(padapter, _FW_UNDER_SURVEY)) ++ { ++ DBG_8192C("scanning_via_buddy_intf\n"); ++ pmlmepriv->scanning_via_buddy_intf = _TRUE; ++ } ++ ++ DBG_8192C("buddy_intf's mlme state:0x%x\n", pbuddy_mlmepriv->fw_state); ++ ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ if( pwdinfo->driver_interface == DRIVER_CFG80211 ) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ if(social_channel == 0) ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); ++ else ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST); ++ } ++ } ++#endif //CONFIG_P2P ++ ++ ++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); ++ //parsing request ssids, n_ssids ++ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); ++ #endif ++ _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); ++ ssid[i].SsidLength = ssids[i].ssid_len; ++ } ++ ++ /* parsing channels, n_channels */ ++ _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel)*RTW_CHANNEL_SCAN_AMOUNT); ++ for (i=0;in_channels && ichannels[i])); ++ #endif ++ ch[i].hw_value = request->channels[i]->hw_value; ++ ch[i].flags = request->channels[i]->flags; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ if (request->n_channels == 1) { ++ for(i=1;in_channels <= 4) { ++ for(j=request->n_channels-1;j>=0;j--) ++ for(i=0;in_channels); ++ } else { ++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, NULL, 0); ++ } ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ if(_status == _FALSE) ++ { ++ ret = -1; ++ } ++ ++check_need_indicate_scan_done: ++ if(need_indicate_scan_done) ++ rtw_cfg80211_surveydone_event_callback(padapter); ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ ++ if (changed & WIPHY_PARAM_RTS_THRESHOLD && ++ (iwm->conf.rts_threshold != wiphy->rts_threshold)) { ++ int ret; ++ ++ iwm->conf.rts_threshold = wiphy->rts_threshold; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, ++ CFG_RTS_THRESHOLD, ++ iwm->conf.rts_threshold); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (changed & WIPHY_PARAM_FRAG_THRESHOLD && ++ (iwm->conf.frag_threshold != wiphy->frag_threshold)) { ++ int ret; ++ ++ iwm->conf.frag_threshold = wiphy->frag_threshold; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX, ++ CFG_FRAG_THRESHOLD, ++ iwm->conf.frag_threshold); ++ if (ret < 0) ++ return ret; ++ } ++#endif ++ DBG_8192C("%s\n", __func__); ++ return 0; ++} ++ ++ ++ ++static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version) ++{ ++ DBG_8192C("%s, wpa_version=%d\n", __func__, wpa_version); ++ ++ if (!wpa_version) { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ return 0; ++ } ++ ++ ++ if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2)) ++ { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK; ++ } ++ ++/* ++ if (wpa_version & NL80211_WPA_VERSION_2) ++ { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; ++ } ++*/ ++ ++ return 0; ++ ++} ++ ++static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv, ++ enum nl80211_auth_type sme_auth_type) ++{ ++ DBG_8192C("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type); ++ ++ ++ switch (sme_auth_type) { ++ case NL80211_AUTHTYPE_AUTOMATIC: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++ ++ break; ++ case NL80211_AUTHTYPE_OPEN_SYSTEM: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++ ++ if(psecuritypriv->ndisauthtype>Ndis802_11AuthModeWPA) ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI) ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; ++#endif ++ ++ break; ++ case NL80211_AUTHTYPE_SHARED_KEY: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++ ++ break; ++ default: ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++ //return -ENOTSUPP; ++ } ++ ++ return 0; ++ ++} ++ ++static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast) ++{ ++ u32 ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ ++ u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm : ++ &psecuritypriv->dot118021XGrpPrivacy; ++ ++ DBG_8192C("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher); ++ ++ ++ if (!cipher) { ++ *profile_cipher = _NO_PRIVACY_; ++ psecuritypriv->ndisencryptstatus = ndisencryptstatus; ++ return 0; ++ } ++ ++ switch (cipher) { ++ case IW_AUTH_CIPHER_NONE: ++ *profile_cipher = _NO_PRIVACY_; ++ ndisencryptstatus = Ndis802_11EncryptionDisabled; ++#ifdef CONFIG_WAPI_SUPPORT ++ if(psecuritypriv->dot11PrivacyAlgrthm ==_SMS4_ ) ++ { ++ *profile_cipher = _SMS4_; ++ } ++#endif ++ break; ++ case WLAN_CIPHER_SUITE_WEP40: ++ *profile_cipher = _WEP40_; ++ ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ *profile_cipher = _WEP104_; ++ ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ *profile_cipher = _TKIP_; ++ ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ *profile_cipher = _AES_; ++ ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++#ifdef CONFIG_WAPI_SUPPORT ++ case WLAN_CIPHER_SUITE_SMS4: ++ *profile_cipher = _SMS4_; ++ ndisencryptstatus = Ndis802_11_EncrypteionWAPI; ++ break; ++#endif ++ default: ++ DBG_8192C("Unsupported cipher: 0x%x\n", cipher); ++ return -ENOTSUPP; ++ } ++ ++ if(ucast) ++ { ++ psecuritypriv->ndisencryptstatus = ndisencryptstatus; ++ ++ //if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) ++ // psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; ++ } ++ ++ return 0; ++} ++ ++static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt) ++{ ++ DBG_8192C("%s, key_mgt=0x%x\n", __func__, key_mgt); ++ ++ if (key_mgt == WLAN_AKM_SUITE_8021X) ++ //*auth_type = UMAC_AUTH_TYPE_8021X; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ else if (key_mgt == WLAN_AKM_SUITE_PSK) { ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ } ++#ifdef CONFIG_WAPI_SUPPORT ++ else if(key_mgt ==WLAN_AKM_SUITE_WAPI_PSK){ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; ++ } ++ else if(key_mgt ==WLAN_AKM_SUITE_WAPI_CERT){ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; ++ } ++#endif ++ ++ ++ else { ++ DBG_8192C("Invalid key mgt: 0x%x\n", key_mgt); ++ //return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) ++{ ++ u8 *buf=NULL, *pos=NULL; ++ u32 left; ++ int group_cipher = 0, pairwise_cipher = 0; ++ int ret = 0; ++ int wpa_ielen=0; ++ int wpa2_ielen=0; ++ u8 *pwpa, *pwpa2; ++ u8 null_addr[]= {0,0,0,0,0,0}; ++ ++ if (pie == NULL || !ielen) { ++ /* Treat this as normal case, but need to clear WIFI_UNDER_WPS */ ++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ goto exit; ++ } ++ ++ if (ielen > MAX_WPA_IE_LEN+MAX_WPS_IE_LEN+MAX_P2P_IE_LEN) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ buf = rtw_zmalloc(ielen); ++ if (buf == NULL){ ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memcpy(buf, pie , ielen); ++ ++ //dump ++ { ++ int i; ++ DBG_8192C("set wpa_ie(length:%zu):\n", ielen); ++ for(i=0;i0) ++ { ++ if(rtw_parse_wpa_ie(pwpa, wpa_ielen+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen+2); ++ ++ DBG_8192C("got wpa_ie, wpa_ielen:%u\n", wpa_ielen); ++ } ++ } ++ ++ pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen); ++ if(pwpa2 && wpa2_ielen>0) ++ { ++ if(rtw_parse_wpa2_ie(pwpa2, wpa2_ielen+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen+2); ++ ++ DBG_8192C("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen); ++ } ++ } ++ ++ if (group_cipher == 0) ++ { ++ group_cipher = WPA_CIPHER_NONE; ++ } ++ if (pairwise_cipher == 0) ++ { ++ pairwise_cipher = WPA_CIPHER_NONE; ++ } ++ ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ {/* handle wps_ie */ ++ uint wps_ielen; ++ u8 *wps_ie; ++ ++ wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen); ++ if (wps_ie && wps_ielen > 0) { ++ DBG_8192C("got wps_ie, wps_ielen:%u\n", wps_ielen); ++ padapter->securitypriv.wps_ie_len = wps_ielensecuritypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len); ++ set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ } else { ++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ } ++ } ++ ++ #ifdef CONFIG_P2P ++ {//check p2p_ie for assoc req; ++ uint p2p_ielen=0; ++ u8 *p2p_ie; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if((p2p_ie=rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_assoc_req_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_assoc_req_ie_len; ++ pmlmepriv->p2p_assoc_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len); ++ pmlmepriv->p2p_assoc_req_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_assoc_req_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ _rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen; ++ } ++ } ++ #endif //CONFIG_P2P ++ ++ #ifdef CONFIG_WFD ++ {//check wfd_ie for assoc req; ++ uint wfd_ielen=0; ++ u8 *wfd_ie; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if(rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen)) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen); ++ #endif ++ ++ if(pmlmepriv->wfd_assoc_req_ie) ++ { ++ u32 free_len = pmlmepriv->wfd_assoc_req_ie_len; ++ pmlmepriv->wfd_assoc_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wfd_assoc_req_ie, free_len); ++ pmlmepriv->wfd_assoc_req_ie = NULL; ++ } ++ ++ pmlmepriv->wfd_assoc_req_ie = rtw_malloc(wfd_ielen); ++ if ( pmlmepriv->wfd_assoc_req_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ goto exit; ++ } ++ rtw_get_wfd_ie(buf, ielen, pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len); ++ } ++ } ++ #endif //CONFIG_WFD ++ ++ //TKIP and AES disallow multicast packets until installing group key ++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ ++ || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ ++ || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) ++ //WPS open need to enable multicast ++ //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) ++ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", ++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); ++ ++exit: ++ if (buf) ++ rtw_mfree(buf, ielen); ++ if (ret) ++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ return ret; ++} ++ ++static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_ibss_params *params) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ NDIS_802_11_SSID ndis_ssid; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int ret=0; ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ ret = -EPERM; ++ goto exit; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING) == _TRUE) { ++ DBG_8192C("%s, but buddy_intf is under linking\n", __FUNCTION__); ++ ret = -EINVAL; ++ goto exit; ++ } ++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY) == _TRUE) { ++ rtw_scan_abort(padapter->pbuddy_adapter); ++ } ++#endif //CONFIG_CONCURRENT_MODE ++ ++ if (!params->ssid || !params->ssid_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (params->ssid_len > IW_ESSID_MAX_SIZE){ ++ ++ ret= -E2BIG; ++ goto exit; ++ } ++ ++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ ndis_ssid.SsidLength = params->ssid_len; ++ _rtw_memcpy(ndis_ssid.Ssid, params->ssid, params->ssid_len); ++ ++ //DBG_8192C("ssid=%s, len=%zu\n", ndis_ssid.Ssid, params->ssid_len); ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ ++ ret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM); ++ rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype); ++ ++ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) ++ { ++ ret = -1; ++ goto exit; ++ } ++ ++exit: ++ return ret; ++} ++ ++static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ ++ if (iwm->umac_profile_active) ++ return iwm_invalidate_mlme_profile(iwm); ++#endif ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ return 0; ++} ++ ++static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_connect_params *sme) ++{ ++ int ret=0; ++ _irqL irqL; ++ _list *phead; ++ struct wlan_network *pnetwork = NULL; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ NDIS_802_11_SSID ndis_ssid; ++ u8 *dst_ssid, *src_ssid; ++ u8 *dst_bssid, *src_bssid; ++ //u8 matched_by_bssid=_FALSE; ++ //u8 matched_by_ssid=_FALSE; ++ u8 matched=_FALSE; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ _queue *queue = &pmlmepriv->scanned_queue; ++ ++ padapter->mlmepriv.not_indic_disco = _TRUE; ++ ++ DBG_871X("=>"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ DBG_871X("privacy=%d, key=%p, key_len=%d, key_idx=%d\n", ++ sme->privacy, sme->key, sme->key_len, sme->key_idx); ++ ++ ++ if(wdev_to_priv(padapter->rtw_wdev)->block == _TRUE) ++ { ++ ret = -EBUSY; ++ DBG_871X("%s wdev_priv.block is set\n", __FUNCTION__); ++ goto exit; ++ } ++ ++#ifdef CONFIG_PLATFORM_MSTAR ++ printk("MStar Android!\n"); ++ if((wdev_to_priv(padapter->rtw_wdev))->bandroid_scan == _FALSE) ++ { ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++#endif //CONFIG_P2P ++ { ++ ret = -EBUSY; ++ printk("Android hasn't attached yet!\n"); ++ goto exit; ++ } ++ } ++#endif ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ ret = -EPERM; ++ goto exit; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING) == _TRUE) { ++ DBG_8192C("%s, but buddy_intf is under linking\n", __FUNCTION__); ++ ret = -EINVAL; ++ goto exit; ++ } ++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY) == _TRUE) { ++ rtw_scan_abort(padapter->pbuddy_adapter); ++ } ++#endif ++ ++ if (!sme->ssid || !sme->ssid_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (sme->ssid_len > IW_ESSID_MAX_SIZE){ ++ ++ ret= -E2BIG; ++ goto exit; ++ } ++ ++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ ndis_ssid.SsidLength = sme->ssid_len; ++ _rtw_memcpy(ndis_ssid.Ssid, sme->ssid, sme->ssid_len); ++ ++ DBG_8192C("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len); ++ ++ ++ if (sme->bssid) ++ DBG_8192C("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid)); ++ ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ ret = -EBUSY; ++ DBG_8192C("%s, fw_state=0x%x, goto exit\n", __FUNCTION__, pmlmepriv->fw_state); ++ goto exit; ++ } ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ rtw_scan_abort(padapter); ++ } ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ padapter->wapiInfo.bWapiEnable = false; ++#endif ++ ++ ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions); ++ if (ret < 0) ++ goto exit; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) ++ { ++ padapter->wapiInfo.bWapiEnable = true; ++ padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; ++ padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; ++ } ++#endif ++ ++ ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type); ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI) ++ padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm; ++#endif ++ ++ ++ if (ret < 0) ++ goto exit; ++ ++ DBG_8192C("%s, ie_len=%zu\n", __func__, sme->ie_len); ++ ++ ret = rtw_cfg80211_set_wpa_ie(padapter, sme->ie, sme->ie_len); ++ if (ret < 0) ++ goto exit; ++ ++ if (sme->crypto.n_ciphers_pairwise) { ++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE); ++ if (ret < 0) ++ goto exit; ++ } ++ ++ //For WEP Shared auth ++ if((psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Shared ++ || psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Auto) && sme->key ++ ) ++ { ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ DBG_871X("%s(): Shared/Auto WEP\n",__FUNCTION__); ++ ++ wep_key_idx = sme->key_idx; ++ wep_key_len = sme->key_len; ++ ++ if (sme->key_idx > WEP_KEYS) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ DBG_871X(" wpa_set_encryption: pwep allocate fail !!!\n"); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ if(wep_key_len==13) ++ { ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ } ++ } ++ else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ pwep->KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength); ++ ++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) ++ { ++ ret = -EOPNOTSUPP ; ++ } ++ ++ if (pwep) { ++ rtw_mfree((u8 *)pwep,wep_total_len); ++ } ++ ++ if(ret < 0) ++ goto exit; ++ } ++ ++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE); ++ if (ret < 0) ++ return ret; ++ ++ if (sme->crypto.n_akm_suites) { ++ ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]); ++ if (ret < 0) ++ goto exit; ++ } ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if(sme->crypto.akm_suites[0] ==WLAN_AKM_SUITE_WAPI_PSK){ ++ padapter->wapiInfo.bWapiPSK = true; ++ } ++ else if(sme->crypto.akm_suites[0] ==WLAN_AKM_SUITE_WAPI_CERT){ ++ padapter->wapiInfo.bWapiPSK = false; ++ } ++#endif ++ ++ authmode = psecuritypriv->ndisauthtype; ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ ++ //rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ ++ if (rtw_set_802_11_connect(padapter, sme->bssid, &ndis_ssid) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ ++ DBG_8192C("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->dot118021XGrpPrivacy); ++ ++exit: ++ ++ DBG_8192C("<=%s, ret %d\n",__FUNCTION__, ret); ++ ++ padapter->mlmepriv.not_indic_disco = _FALSE; ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, ++ u16 reason_code) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ padapter->mlmepriv.not_indic_disco = _TRUE; ++ ++ rtw_set_roaming(padapter, 0); ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) ++ { ++ rtw_scan_abort(padapter); ++ LeaveAllPowerSaveMode(padapter); ++ rtw_disassoc_cmd(padapter, 500, _FALSE); ++ ++ DBG_871X("%s...call rtw_indicate_disconnect\n", __FUNCTION__); ++ ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ ++ padapter->mlmepriv.not_indic_disco = _FALSE; ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) ++ struct wireless_dev *wdev, ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) || defined(COMPAT_KERNEL_RELEASE) ++ enum nl80211_tx_power_setting type, int mbm) ++#else ++ enum tx_power_setting type, int dbm) ++#endif ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ int ret; ++ ++ switch (type) { ++ case NL80211_TX_POWER_AUTOMATIC: ++ return 0; ++ case NL80211_TX_POWER_FIXED: ++ if (mbm < 0 || (mbm % 100)) ++ return -EOPNOTSUPP; ++ ++ if (!test_bit(IWM_STATUS_READY, &iwm->status)) ++ return 0; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, ++ CFG_TX_PWR_LIMIT_USR, ++ MBM_TO_DBM(mbm) * 2); ++ if (ret < 0) ++ return ret; ++ ++ return iwm_tx_power_trigger(iwm); ++ default: ++ IWM_ERR(iwm, "Unsupported power type: %d\n", type); ++ return -EOPNOTSUPP; ++ } ++#endif ++ DBG_8192C("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) ++ struct wireless_dev *wdev, ++#endif ++ int *dbm) ++{ ++ //_adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ DBG_8192C("%s\n", __func__); ++ ++ *dbm = (12); ++ ++ return 0; ++} ++ ++inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter) ++{ ++ struct rtw_wdev_priv *rtw_wdev_priv = wdev_to_priv(adapter->rtw_wdev); ++ return rtw_wdev_priv->power_mgmt; ++} ++ ++static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, ++ struct net_device *ndev, ++ bool enabled, int timeout) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct rtw_wdev_priv *rtw_wdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++ DBG_871X(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev), ++ enabled, timeout); ++ ++ rtw_wdev_priv->power_mgmt = enabled; ++ ++ #ifdef CONFIG_LPS ++ if (!enabled) ++ LPS_Leave(padapter); ++ #endif ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev, ++ struct cfg80211_pmksa *pmksa) ++{ ++ u8 index,blInserted = _FALSE; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev)); ++ ++ if ( _rtw_memcmp( pmksa->bssid, strZeroMacAddress, ETH_ALEN ) == _TRUE ) ++ { ++ return -EINVAL; ++ } ++ ++ blInserted = _FALSE; ++ ++ //overwrite PMKID ++ for(index=0 ; indexPMKIDList[index].Bssid, pmksa->bssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => rewrite with new PMKID. ++ DBG_871X(FUNC_NDEV_FMT" BSSID exists in the PMKList.\n", FUNC_NDEV_ARG(netdev)); ++ ++ _rtw_memcpy( psecuritypriv->PMKIDList[index].PMKID, pmksa->pmkid, WLAN_PMKID_LEN); ++ psecuritypriv->PMKIDList[index].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex = index+1; ++ blInserted = _TRUE; ++ break; ++ } ++ } ++ ++ if(!blInserted) ++ { ++ // Find a new entry ++ DBG_871X(FUNC_NDEV_FMT" Use the new entry index = %d for this PMKID.\n", ++ FUNC_NDEV_ARG(netdev), psecuritypriv->PMKIDIndex ); ++ ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, pmksa->bssid, ETH_ALEN); ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pmksa->pmkid, WLAN_PMKID_LEN); ++ ++ psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex++ ; ++ if(psecuritypriv->PMKIDIndex==16) ++ { ++ psecuritypriv->PMKIDIndex =0; ++ } ++ } ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev, ++ struct cfg80211_pmksa *pmksa) ++{ ++ u8 index, bMatched = _FALSE; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev)); ++ ++ for(index=0 ; indexPMKIDList[index].Bssid, pmksa->bssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => Remove this PMKID information and reset it. ++ _rtw_memset( psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN ); ++ _rtw_memset( psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN ); ++ psecuritypriv->PMKIDList[index].bUsed = _FALSE; ++ bMatched = _TRUE; ++ break; ++ } ++ } ++ ++ if(_FALSE == bMatched) ++ { ++ DBG_871X(FUNC_NDEV_FMT" do not have matched BSSID\n" ++ , FUNC_NDEV_ARG(netdev)); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(netdev)); ++ ++ _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ psecuritypriv->PMKIDIndex = 0; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_AP_MODE ++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ s32 freq; ++ int channel; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct net_device *ndev = padapter->pnetdev; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) ++ { ++ struct station_info sinfo; ++ u8 ie_offset; ++ if (GetFrameSubType(pmgmt_frame) == WIFI_ASSOCREQ) ++ ie_offset = _ASOCREQ_IE_OFFSET_; ++ else // WIFI_REASSOCREQ ++ ie_offset = _REASOCREQ_IE_OFFSET_; ++ ++ sinfo.filled = 0; ++ sinfo.filled = STATION_INFO_ASSOC_REQ_IES; ++ sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset; ++ sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset; ++ cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); ++ } ++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ ++ channel = pmlmeext->cur_channel; ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++ #ifdef COMPAT_KERNEL_RELEASE ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); ++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); ++ #else //COMPAT_KERNEL_RELEASE ++ { ++ //to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() ++ #ifndef CONFIG_PLATFORM_MSTAR ++ pwdev->iftype = NL80211_IFTYPE_STATION; ++ #endif //CONFIG_PLATFORM_MSTAR ++ DBG_8192C("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype); ++ rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len); ++ DBG_8192C("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype); ++ pwdev->iftype = NL80211_IFTYPE_AP; ++ //cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++ } ++ #endif //COMPAT_KERNEL_RELEASE ++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ ++ ++} ++ ++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) ++{ ++ s32 freq; ++ int channel; ++ u8 *pmgmt_frame; ++ uint frame_len; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ u8 mgmt_buf[128] = {0}; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct net_device *ndev = padapter->pnetdev; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) ++ cfg80211_del_sta(ndev, da, GFP_ATOMIC); ++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ ++ channel = pmlmeext->cur_channel; ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++ pmgmt_frame = mgmt_buf; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ //_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ //_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pmgmt_frame, WIFI_DEAUTH); ++ ++ pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); ++ frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ reason = cpu_to_le16(reason); ++ pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); ++ ++ #ifdef COMPAT_KERNEL_RELEASE ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); ++ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); ++ #else //COMPAT_KERNEL_RELEASE ++ cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); ++ //cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); ++ #endif //COMPAT_KERNEL_RELEASE ++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ ++} ++ ++static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) ++{ ++ int ret = 0; ++ ++ DBG_8192C("%s\n", __func__); ++ ++ return ret; ++} ++ ++static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) ++{ ++ int ret = 0; ++ ++ DBG_8192C("%s\n", __func__); ++ ++ return ret; ++} ++ ++static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev) ++{ ++ int ret = 0; ++ int rtap_len; ++ int qos_len = 0; ++ int dot11_hdr_len = 24; ++ int snap_len = 6; ++ unsigned char *pdata; ++ u16 frame_ctl; ++ unsigned char src_mac_addr[6]; ++ unsigned char dst_mac_addr[6]; ++ struct ieee80211_hdr *dot11_hdr; ++ struct ieee80211_radiotap_header *rtap_hdr; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ if (skb) ++ rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); ++ ++ if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) ++ goto fail; ++ ++ rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; ++ if (unlikely(rtap_hdr->it_version)) ++ goto fail; ++ ++ rtap_len = ieee80211_get_radiotap_len(skb->data); ++ if (unlikely(skb->len < rtap_len)) ++ goto fail; ++ ++ if(rtap_len != 14) ++ { ++ DBG_8192C("radiotap len (should be 14): %d\n", rtap_len); ++ goto fail; ++ } ++ ++ /* Skip the ratio tap header */ ++ skb_pull(skb, rtap_len); ++ ++ dot11_hdr = (struct ieee80211_hdr *)skb->data; ++ frame_ctl = le16_to_cpu(dot11_hdr->frame_control); ++ /* Check if the QoS bit is set */ ++ if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { ++ /* Check if this ia a Wireless Distribution System (WDS) frame ++ * which has 4 MAC addresses ++ */ ++ if (dot11_hdr->frame_control & 0x0080) ++ qos_len = 2; ++ if ((dot11_hdr->frame_control & 0x0300) == 0x0300) ++ dot11_hdr_len += 6; ++ ++ memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr)); ++ memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr)); ++ ++ /* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for ++ * for two MAC addresses ++ */ ++ skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2); ++ pdata = (unsigned char*)skb->data; ++ memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); ++ memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); ++ ++ DBG_8192C("should be eapol packet\n"); ++ ++ /* Use the real net device to transmit the packet */ ++ ret = _rtw_xmit_entry(skb, padapter->pnetdev); ++ ++ return ret; ++ ++ } ++ else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)) ++ == (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION) ++ ) ++ { ++ //only for action frames ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ //u8 category, action, OUI_Subtype, dialogToken=0; ++ //unsigned char *frame_body; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ u8 *buf = skb->data; ++ u32 len = skb->len; ++ u8 category, action; ++ int type = -1; ++ ++ if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { ++ DBG_8192C(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev), ++ le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); ++ goto fail; ++ } ++ ++ DBG_8192C("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n", ++ MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev)); ++ #ifdef CONFIG_P2P ++ if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0) ++ goto dump; ++ #endif ++ if (category == RTW_WLAN_CATEGORY_PUBLIC) ++ DBG_871X("RTW_Tx:%s\n", action_public_str(action)); ++ else ++ DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action); ++ ++dump: ++ //starting alloc mgmt frame to dump it ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto fail; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ ++ _rtw_memcpy(pframe, (void*)buf, len); ++ #ifdef CONFIG_WFD ++ if (type >= 0) ++ { ++ struct wifi_display_info *pwfd_info; ++ ++ pwfd_info = padapter->wdinfo.wfd_info; ++ ++ if ( _TRUE == pwfd_info->wfd_enable ) ++ { ++ rtw_append_wfd_ie( padapter, pframe, &len ); ++ } ++ } ++ #endif // CONFIG_WFD ++ pattrib->pktlen = len; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ //update seq number ++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr); ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ pmlmeext->mgnt_seq++; ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ } ++ else ++ { ++ DBG_8192C("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)); ++ } ++ ++ ++fail: ++ ++ dev_kfree_skb(skb); ++ ++ return 0; ++ ++} ++ ++static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev) ++{ ++ DBG_8192C("%s\n", __func__); ++} ++ ++static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ int ret = 0; ++ ++ DBG_8192C("%s\n", __func__); ++ ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtw_cfg80211_monitor_if_ops = { ++ .ndo_open = rtw_cfg80211_monitor_if_open, ++ .ndo_stop = rtw_cfg80211_monitor_if_close, ++ .ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry, ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) ++ .ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list, ++ #endif ++ .ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address, ++}; ++#endif ++ ++static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev) ++{ ++ int ret = 0; ++ struct net_device* mon_ndev = NULL; ++ struct wireless_dev* mon_wdev = NULL; ++ struct rtw_netdev_priv_indicator *pnpi; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++ if (!name ) { ++ DBG_871X(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter)); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (pwdev_priv->pmon_ndev) { ++ DBG_871X(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n", ++ FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev)); ++ ret = -EBUSY; ++ goto out; ++ } ++ ++ mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++ if (!mon_ndev) { ++ DBG_871X(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter)); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; ++ strncpy(mon_ndev->name, name, IFNAMSIZ); ++ mon_ndev->name[IFNAMSIZ - 1] = 0; ++ mon_ndev->destructor = rtw_ndev_destructor; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; ++#else ++ mon_ndev->open = rtw_cfg80211_monitor_if_open; ++ mon_ndev->stop = rtw_cfg80211_monitor_if_close; ++ mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry; ++ mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address; ++#endif ++ ++ pnpi = netdev_priv(mon_ndev); ++ pnpi->priv = padapter; ++ pnpi->sizeof_priv = sizeof(_adapter); ++ ++ /* wdev */ ++ mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); ++ if (!mon_wdev) { ++ DBG_871X(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter)); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ mon_wdev->wiphy = padapter->rtw_wdev->wiphy; ++ mon_wdev->netdev = mon_ndev; ++ mon_wdev->iftype = NL80211_IFTYPE_MONITOR; ++ mon_ndev->ieee80211_ptr = mon_wdev; ++ ++ ret = register_netdevice(mon_ndev); ++ if (ret) { ++ goto out; ++ } ++ ++ *ndev = pwdev_priv->pmon_ndev = mon_ndev; ++ _rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ+1); ++ ++out: ++ if (ret && mon_wdev) { ++ rtw_mfree((u8*)mon_wdev, sizeof(struct wireless_dev)); ++ mon_wdev = NULL; ++ } ++ ++ if (ret && mon_ndev) { ++ free_netdev(mon_ndev); ++ *ndev = mon_ndev = NULL; ++ } ++ ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++static struct wireless_dev * ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++static struct net_device * ++#else ++static int ++#endif ++ cfg80211_rtw_add_virtual_intf( ++ struct wiphy *wiphy, ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) ++ const char *name, ++ #else ++ char *name, ++ #endif ++ enum nl80211_iftype type, u32 *flags, struct vif_params *params) ++{ ++ int ret = 0; ++ struct net_device* ndev = NULL; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ DBG_871X(FUNC_ADPT_FMT " wiphy:%s, name:%s, type:%d\n", ++ FUNC_ADPT_ARG(padapter), wiphy_name(wiphy), name, type); ++ ++ switch (type) { ++ case NL80211_IFTYPE_ADHOC: ++ case NL80211_IFTYPE_AP_VLAN: ++ case NL80211_IFTYPE_WDS: ++ case NL80211_IFTYPE_MESH_POINT: ++ ret = -ENODEV; ++ break; ++ case NL80211_IFTYPE_MONITOR: ++ ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev); ++ break; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ case NL80211_IFTYPE_P2P_CLIENT: ++#endif ++ case NL80211_IFTYPE_STATION: ++ ret = -ENODEV; ++ break; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ case NL80211_IFTYPE_P2P_GO: ++#endif ++ case NL80211_IFTYPE_AP: ++ ret = -ENODEV; ++ break; ++ default: ++ ret = -ENODEV; ++ DBG_871X("Unsupported interface type\n"); ++ break; ++ } ++ ++ DBG_871X(FUNC_ADPT_FMT" ndev:%p, ret:%d\n", FUNC_ADPT_ARG(padapter), ndev, ret); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ return ndev ? ndev->ieee80211_ptr : ERR_PTR(ret); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ return ndev ? ndev : ERR_PTR(ret); ++#else ++ return ret; ++#endif ++} ++ ++static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ struct wireless_dev *wdev ++#else ++ struct net_device *ndev ++#endif ++) ++{ ++ struct rtw_wdev_priv *pwdev_priv = (struct rtw_wdev_priv *)wiphy_priv(wiphy); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ struct net_device *ndev; ++ ndev = wdev ? wdev->netdev : NULL; ++#endif ++ ++ if (!ndev) ++ goto exit; ++ ++ unregister_netdevice(ndev); ++ ++ if (ndev == pwdev_priv->pmon_ndev) { ++ pwdev_priv->pmon_ndev = NULL; ++ pwdev_priv->ifname_mon[0] = '\0'; ++ DBG_871X(FUNC_NDEV_FMT" remove monitor interface\n", FUNC_NDEV_ARG(ndev)); ++ } ++ ++exit: ++ return 0; ++} ++ ++static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len) ++{ ++ int ret=0; ++ u8 *pbuf = NULL; ++ uint len, wps_ielen=0; ++ uint p2p_ielen=0; ++ u8 *p2p_ie; ++ u8 got_p2p_ie = _FALSE; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++ DBG_8192C("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ if(head_len<24) ++ return -EINVAL; ++ ++ ++ pbuf = rtw_zmalloc(head_len+tail_len); ++ if(!pbuf) ++ return -ENOMEM; ++ ++ ++ //_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); ++ ++ //if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) ++ // pstapriv->max_num_sta = NUM_STA; ++ ++ ++ _rtw_memcpy(pbuf, (void *)head+24, head_len-24);// 24=beacon header len. ++ _rtw_memcpy(pbuf+head_len-24, (void *)tail, tail_len); ++ ++ len = head_len+tail_len-24; ++ ++ //check wps ie if inclued ++ if(rtw_get_wps_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &wps_ielen)) ++ DBG_8192C("add bcn, wps_ielen=%d\n", wps_ielen); ++ ++#ifdef CONFIG_P2P ++ //check p2p ie if inclued ++ if( adapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ { ++ //check p2p if enable ++ if(rtw_get_p2p_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &p2p_ielen)) ++ { ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct wifidirect_info *pwdinfo= &(adapter->wdinfo); ++ ++ DBG_8192C("got p2p_ie, len=%d\n", p2p_ielen); ++ got_p2p_ie = _TRUE; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ DBG_8192C("Enable P2P function for the first time\n"); ++ rtw_p2p_enable(adapter, P2P_ROLE_GO); ++ wdev_to_priv(adapter->rtw_wdev)->p2p_enabled = _TRUE; ++ } ++ else ++ { ++ DBG_8192C("enter GO Mode, p2p_ielen=%d\n", p2p_ielen); ++ ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 15; ++ } ++ } ++ } ++#endif // CONFIG_P2P ++ ++ /* pbss_network->IEs will not include p2p_ie, wfd ie */ ++ rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4); ++ rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4); ++ ++ if (rtw_check_beacon_data(adapter, pbuf, len) == _SUCCESS) ++ { ++#ifdef CONFIG_P2P ++ //check p2p if enable ++ if(got_p2p_ie == _TRUE) ++ { ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct wifidirect_info *pwdinfo= &(adapter->wdinfo); ++ pwdinfo->operating_channel = pmlmeext->cur_channel; ++ } ++#endif //CONFIG_P2P ++ ret = 0; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ ++ rtw_mfree(pbuf, head_len+tail_len); ++ ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) ++static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, ++ struct beacon_parameters *info) ++{ ++ int ret=0; ++ _adapter *adapter = wiphy_to_adapter(wiphy); ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, ++ struct beacon_parameters *info) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ cfg80211_rtw_add_beacon(wiphy, ndev, info); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return 0; ++} ++#else ++static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_ap_settings *settings) ++{ ++ int ret = 0; ++ _adapter *adapter = wiphy_to_adapter(wiphy); ++ ++ DBG_871X(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), ++ settings->hidden_ssid, settings->auth_type); ++ ++ ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, ++ settings->beacon.tail, settings->beacon.tail_len); ++ ++ adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid; ++ ++ if (settings->ssid && settings->ssid_len) { ++ WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network; ++ WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network; ++ ++ if(0) ++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter), ++ settings->ssid, settings->ssid_len, ++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); ++ ++ _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len); ++ pbss_network->Ssid.SsidLength = settings->ssid_len; ++ _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len); ++ pbss_network_ext->Ssid.SsidLength = settings->ssid_len; ++ ++ if(0) ++ DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), ++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, ++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); ++ } ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_beacon_data *info) ++{ ++ int ret = 0; ++ _adapter *adapter = wiphy_to_adapter(wiphy); ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ return 0; ++} ++ ++#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) ++ ++static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, ++ u8 *mac, struct station_parameters *params) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev, ++ u8 *mac) ++{ ++ int ret=0; ++ _irqL irqL; ++ _list *phead, *plist; ++ u8 updated; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("+"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ DBG_8192C("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__); ++ return -EINVAL; ++ } ++ ++ ++ if(!mac) ++ { ++ DBG_8192C("flush all sta, and cam_entry\n"); ++ ++ flush_all_cam_entry(padapter); //clear CAM ++ ++ ret = rtw_sta_flush(padapter); ++ ++ return ret; ++ } ++ ++ ++ DBG_8192C("free sta macaddr =" MAC_FMT "\n", MAC_ARG(mac)); ++ ++ if (mac[0] == 0xff && mac[1] == 0xff && ++ mac[2] == 0xff && mac[3] == 0xff && ++ mac[4] == 0xff && mac[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //check asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(mac, psta->hwaddr, ETH_ALEN)) ++ { ++ if(psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) ++ { ++ DBG_8192C("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); ++ } ++ else ++ { ++ DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid); ++ ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ psta = NULL; ++ ++ break; ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ associated_clients_update(padapter, updated); ++ ++ DBG_871X("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev, ++ u8 *mac, struct station_parameters *params) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev, ++ int idx, u8 *mac, struct station_info *sinfo) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ //TODO: dump scanned queue ++ ++ return -ENOENT; ++} ++ ++static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, ++ struct bss_parameters *params) ++{ ++ u8 i; ++ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++/* ++ DBG_8192C("use_cts_prot=%d\n", params->use_cts_prot); ++ DBG_8192C("use_short_preamble=%d\n", params->use_short_preamble); ++ DBG_8192C("use_short_slot_time=%d\n", params->use_short_slot_time); ++ DBG_8192C("ap_isolate=%d\n", params->ap_isolate); ++ ++ DBG_8192C("basic_rates_len=%d\n", params->basic_rates_len); ++ for(i=0; ibasic_rates_len; i++) ++ { ++ DBG_8192C("basic_rates=%d\n", params->basic_rates[i]); ++ ++ } ++*/ ++ return 0; ++ ++} ++ ++static int cfg80211_rtw_set_channel(struct wiphy *wiphy ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ , struct net_device *ndev ++ #endif ++ , struct ieee80211_channel *chan, enum nl80211_channel_type channel_type) ++{ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ #endif ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_auth_request *req) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_assoc_request *req) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++ return 0; ++} ++#endif //CONFIG_AP_MODE ++ ++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ int type; ++ s32 freq; ++ int channel; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ u8 category, action; ++ ++ channel = rtw_get_oper_ch(padapter); ++ ++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); ++ #ifdef CONFIG_P2P ++ type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); ++ if (type >= 0) ++ goto indicate; ++ #endif ++ rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); ++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); ++ ++indicate: ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#endif ++} ++ ++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ int type; ++ s32 freq; ++ int channel; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ u8 category, action; ++ ++ channel = rtw_get_oper_ch(padapter); ++ ++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); ++ #ifdef CONFIG_P2P ++ type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); ++ if (type >= 0) { ++ switch (type) { ++ case P2P_GO_NEGO_CONF: ++ case P2P_PROVISION_DISC_RESP: ++ case P2P_INVIT_RESP: ++ rtw_set_scan_deny(padapter, 2000); ++ rtw_clear_scan_deny(padapter); ++ } ++ goto indicate; ++ } ++ #endif ++ rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); ++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); ++ ++indicate: ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#endif ++} ++ ++void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg) ++{ ++ s32 freq; ++ int channel; ++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(adapter->rtw_wdev); ++ u8 category, action; ++ ++ channel = rtw_get_oper_ch(adapter); ++ ++ rtw_action_frame_parse(frame, frame_len, &category, &action); ++ ++ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); ++ if (msg) ++ DBG_871X("RTW_Rx:%s\n", msg); ++ else ++ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ else ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); ++#endif ++ ++} ++ ++#ifdef CONFIG_P2P ++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) ++{ ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++ u8 wpsie[ 255 ] = { 0x00 }, p2p_ie[ 255 ] = { 0x00 }; ++ uint p2p_ielen = 0; ++ uint wpsielen = 0; ++ u32 devinfo_contentlen = 0; ++ u8 devinfo_content[64] = { 0x00 }; ++ u16 capability = 0; ++ uint capability_len = 0; ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = 1; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_REQ; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ ++ //prepare for building provision_request frame ++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN); ++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN); ++ ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ ++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); ++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ switch(wps_devicepassword_id) ++ { ++ case WPS_DPID_PIN: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; ++ break; ++ case WPS_DPID_USER_SPEC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; ++ break; ++ case WPS_DPID_MACHINE_SPEC: ++ break; ++ case WPS_DPID_REKEY: ++ break; ++ case WPS_DPID_PBC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ break; ++ case WPS_DPID_REGISTRAR_SPEC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; ++ break; ++ default: ++ break; ++ } ++ ++ ++ if ( rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen ) ) ++ { ++ ++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen); ++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&capability, &capability_len); ++ ++ } ++ ++ ++ //start to build provision_request frame ++ _rtw_memset(wpsie, 0, sizeof(wpsie)); ++ _rtw_memset(p2p_ie, 0, sizeof(p2p_ie)); ++ p2p_ielen = 0; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //build_prov_disc_request_p2p_ie ++ // P2P OUI ++ p2pielen = 0; ++ p2p_ie[ p2pielen++ ] = 0x50; ++ p2p_ie[ p2pielen++ ] = 0x6F; ++ p2p_ie[ p2pielen++ ] = 0x9A; ++ p2p_ie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110301 ++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Device Info ++ // 3. Group ID ( When joining an operating P2P Group ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2p_ie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Group Capability Bitmap, 1 byte ++ _rtw_memcpy(p2p_ie + p2pielen, &capability, 2); ++ p2pielen += 2; ++ ++ ++ // Device Info ATTR ++ // Type: ++ p2p_ie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen); ++ p2pielen += devinfo_contentlen; ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen); ++ //p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); ++ //pframe += p2pielen; ++ pattrib->pktlen += p2p_ielen; ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ //dump_mgntframe(padapter, pmgntframe); ++ if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) ++ DBG_8192C("%s, ack to\n", __func__); ++ ++ //if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) ++ //{ ++ // DBG_8192C("waiting for p2p peer key-in PIN CODE\n"); ++ // rtw_msleep_os(15000); // 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. ++ //} ++ ++} ++ ++static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ struct wireless_dev *wdev, ++#else ++ struct net_device *ndev, ++#endif ++ struct ieee80211_channel * channel, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++ enum nl80211_channel_type channel_type, ++#endif ++ unsigned int duration, u64 *cookie) ++{ ++ s32 err = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); ++ u8 ready_on_channel = _FALSE; ++ ++ DBG_871X(FUNC_ADPT_FMT" ch:%u duration:%d\n", FUNC_ADPT_ARG(padapter), remain_ch, duration); ++ ++ if(pcfg80211_wdinfo->is_ro_ch == _TRUE) ++ { ++ DBG_8192C("%s, cancel ro ch timer\n", __func__); ++ ++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); ++#endif //CONFIG_CONCURRENT_MODE ++ ++ p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); ++ } ++ ++ pcfg80211_wdinfo->is_ro_ch = _TRUE; ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++ pcfg80211_wdinfo->remain_on_ch_type= channel_type; ++ #endif ++ pcfg80211_wdinfo->remain_on_ch_cookie= *cookie; ++ ++ rtw_scan_abort(padapter); ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ rtw_scan_abort(padapter->pbuddy_adapter); ++#endif //CONFIG_CONCURRENT_MODE ++ ++ //if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE; ++ padapter->wdinfo.listen_channel = remain_ch; ++ } ++ else ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ } ++ ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ ++ ++ if(duration < 400) ++ duration = duration*3;//extend from exper. ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(check_buddy_fwstate(padapter, _FW_LINKED) && ++ (durationext_listen_interval)) ++ { ++ duration = duration + pwdinfo->ext_listen_interval; ++ } ++#endif ++ ++ pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); ++ ++ if(rtw_ch_set_search_ch(pmlmeext->channel_set, remain_ch) >= 0) { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) ++ { ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ if(remain_ch != pbuddy_mlmeext->cur_channel) ++ { ++ if(ATOMIC_READ(&pwdev_priv->switch_ch_to)==1 || ++ (remain_ch != pmlmeext->cur_channel)) ++ { ++ DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__); ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); ++ ++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); ++ ++ DBG_8192C("%s, set switch ch timer, duration=%d\n", __func__, duration-pwdinfo->ext_listen_interval); ++ _set_timer(&pwdinfo->ap_p2p_switch_timer, duration-pwdinfo->ext_listen_interval); ++ } ++ } ++ ++ ready_on_channel = _TRUE; ++ //pmlmeext->cur_channel = remain_ch; ++ //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ }else ++#endif //CONFIG_CONCURRENT_MODE ++ if(remain_ch != rtw_get_oper_ch(padapter) ) ++ { ++ ready_on_channel = _TRUE; ++ //pmlmeext->cur_channel = remain_ch; ++ //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ } else { ++ DBG_871X("%s remain_ch:%u not in channel plan!!!!\n", __FUNCTION__, remain_ch); ++ } ++ ++ ++ //call this after other things have been done ++#ifdef CONFIG_CONCURRENT_MODE ++ if(ATOMIC_READ(&pwdev_priv->ro_ch_to)==1 || ++ (remain_ch != rtw_get_oper_ch(padapter))) ++ { ++ u8 co_channel = 0xff; ++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 0); ++#endif ++ ++ if(ready_on_channel == _TRUE) ++ { ++ if ( !check_fwstate(&padapter->mlmepriv, _FW_LINKED ) ) ++ { ++ pmlmeext->cur_channel = remain_ch; ++ ++ ++ set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ } ++ DBG_8192C("%s, set ro ch timer, duration=%d\n", __func__, duration); ++ _set_timer( &pcfg80211_wdinfo->remain_on_ch_timer, duration); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ } ++#endif ++ ++ rtw_cfg80211_ready_on_channel(padapter, *cookie, channel, channel_type, duration, GFP_KERNEL); ++ ++exit: ++ if (err) ++ pcfg80211_wdinfo->is_ro_ch = _FALSE; ++ ++ return err; ++} ++ ++static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ struct wireless_dev *wdev, ++#else ++ struct net_device *ndev, ++#endif ++ u64 cookie) ++{ ++ s32 err = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ ++ DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); ++ ++ if (pcfg80211_wdinfo->is_ro_ch == _TRUE) { ++ DBG_8192C("%s, cancel ro ch timer\n", __func__); ++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++ #ifdef CONFIG_CONCURRENT_MODE ++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); ++ #endif ++ p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); ++ } ++ ++ #if 0 ++ // Disable P2P Listen State ++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info)); ++ } ++ } ++ else ++ #endif ++ { ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ } ++ pcfg80211_wdinfo->is_ro_ch = _FALSE; ++ ++ return err; ++} ++ ++#endif //CONFIG_P2P ++ ++static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, size_t len) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ int ret = _FAIL; ++ bool ack = _TRUE; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ //struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ rtw_set_scan_deny(padapter, 1000); ++ ++ rtw_scan_abort(padapter); ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ rtw_scan_abort(padapter->pbuddy_adapter); ++ #endif /* CONFIG_CONCURRENT_MODE */ ++ ++ if (padapter->cfg80211_wdinfo.is_ro_ch == _TRUE) { ++ //DBG_8192C("%s, cancel ro ch timer\n", __func__); ++ //_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++ //padapter->cfg80211_wdinfo.is_ro_ch = _FALSE; ++ #ifdef CONFIG_CONCURRENT_MODE ++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) ++ { ++ DBG_8192C("%s, extend ro ch time\n", __func__); ++ _set_timer( &padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period); ++ } ++ #endif //CONFIG_CONCURRENT_MODE ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, _FW_LINKED )) { ++ u8 co_channel=0xff; ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ co_channel = rtw_get_oper_ch(padapter); ++ ++ if (tx_ch != pbuddy_mlmeext->cur_channel) { ++ ++ u16 ext_listen_period; ++ ++ if (ATOMIC_READ(&pwdev_priv->switch_ch_to)==1) { ++ DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__); ++ issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); ++ ++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); ++ ++ //DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period); ++ //_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); ++ } ++ ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED )) ++ { ++ ext_listen_period = 500;// 500ms ++ } ++ else ++ { ++ ext_listen_period = pwdinfo->ext_listen_period; ++ } ++ ++ DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); ++ _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period); ++ ++ } ++ ++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) ++ pmlmeext->cur_channel = tx_ch; ++ ++ if (tx_ch != co_channel) ++ set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ }else ++#endif //CONFIG_CONCURRENT_MODE ++ //if (tx_ch != pmlmeext->cur_channel) { ++ if(tx_ch != rtw_get_oper_ch(padapter)) { ++ if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) ++ pmlmeext->cur_channel = tx_ch; ++ set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++ //starting alloc mgmt frame to dump it ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ //ret = -ENOMEM; ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ ++ _rtw_memcpy(pframe, (void*)buf, len); ++ pattrib->pktlen = len; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ //update seq number ++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr); ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ pmlmeext->mgnt_seq++; ++ ++#ifdef CONFIG_WFD ++ { ++ struct wifi_display_info *pwfd_info; ++ ++ pwfd_info = padapter->wdinfo.wfd_info; ++ ++ if ( _TRUE == pwfd_info->wfd_enable ) ++ { ++ rtw_append_wfd_ie( padapter, pframe, &pattrib->pktlen ); ++ } ++ } ++#endif // CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) ++ { ++ ack = _FALSE; ++ ret = _FAIL; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ack == _FAIL\n", __func__); ++ #endif ++ } ++ else ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ack=%d, ok!\n", __func__, ack); ++ #endif ++ ret = _SUCCESS; ++ } ++ ++exit: ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ret=%d\n", __func__, ret); ++ #endif ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) ++ struct wireless_dev *wdev, ++#else ++ struct net_device *ndev, ++#endif ++ struct ieee80211_channel *chan, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ bool offchan, ++#endif ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++ enum nl80211_channel_type channel_type, ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ bool channel_type_valid, ++ #endif ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ unsigned int wait, ++#endif ++ const u8 *buf, size_t len, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) ++ bool no_cck, ++#endif ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) ++ bool dont_wait_for_ack, ++#endif ++ u64 *cookie) ++{ ++ _adapter *padapter = (_adapter *)wiphy_to_adapter(wiphy); ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ int ret = 0; ++ int tx_ret; ++ u32 dump_limit = RTW_MAX_MGMT_TX_CNT; ++ u32 dump_cnt = 0; ++ bool ack = _TRUE; ++ u8 tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); ++ u8 category, action; ++ int type = (-1); ++ u32 start = rtw_get_current_time(); ++ ++ /* cookie generation */ ++ *cookie = (unsigned long) buf; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X(FUNC_ADPT_FMT" len=%zu, ch=%d" ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++ ", ch_type=%d" ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ ", channel_type_valid=%d" ++ #endif ++ #endif ++ "\n", FUNC_ADPT_ARG(padapter), ++ len, tx_ch ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) ++ , channel_type ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ , channel_type_valid ++ #endif ++ #endif ++ ); ++#endif /* CONFIG_DEBUG_CFG80211 */ ++ ++ /* indicate ack before issue frame to avoid racing with rsp frame */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ rtw_cfg80211_mgmt_tx_status(padapter, *cookie, buf, len, ack, GFP_KERNEL); ++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) ++ cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL); ++#endif ++ ++ if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { ++ DBG_8192C(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter), ++ le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); ++ goto exit; ++ } ++ ++ DBG_8192C("RTW_Tx:tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf))); ++ #ifdef CONFIG_P2P ++ if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0) { ++ goto dump; ++ } ++ #endif ++ if (category == RTW_WLAN_CATEGORY_PUBLIC) ++ DBG_871X("RTW_Tx:%s\n", action_public_str(action)); ++ else ++ DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action); ++ ++dump: ++ do { ++ dump_cnt++; ++ tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len); ++ } while (dump_cnt < dump_limit && tx_ret != _SUCCESS); ++ ++ if (tx_ret != _SUCCESS || dump_cnt > 1) { ++ DBG_871X(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter), ++ tx_ret==_SUCCESS?"OK":"FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); ++ } ++ ++ switch (type) { ++ case P2P_GO_NEGO_CONF: ++ rtw_clear_scan_deny(padapter); ++ break; ++ case P2P_INVIT_RESP: ++ if (pwdev_priv->invit_info.flags & BIT(0) ++ && pwdev_priv->invit_info.status == 0) ++ { ++ DBG_871X(FUNC_ADPT_FMT" agree with invitation of persistent group\n", ++ FUNC_ADPT_ARG(padapter)); ++ rtw_set_scan_deny(padapter, 5000); ++ rtw_pwr_wakeup_ex(padapter, 5000); ++ rtw_clear_scan_deny(padapter); ++ } ++ break; ++ } ++ ++exit: ++ return ret; ++} ++ ++static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) ++ struct wireless_dev *wdev, ++#else ++ struct net_device *ndev, ++#endif ++ u16 frame_type, bool reg) ++{ ++ _adapter *adapter = wiphy_to_adapter(wiphy); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter), ++ frame_type, reg); ++#endif ++ ++ if (frame_type != (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ)) ++ return; ++ ++ return; ++} ++ ++static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 wps_oui[8]={0x0,0x50,0xf2,0x04}; ++ u8 *p2p_ie; ++ u32 wfd_ielen = 0; ++ u8 *wfd_ie; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ DBG_871X(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len); ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("bcn_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ u32 free_len = pmlmepriv->wps_beacon_ie_len; ++ pmlmepriv->wps_beacon_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_beacon_ie, free_len); ++ pmlmepriv->wps_beacon_ie = NULL; ++ } ++ ++ pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_beacon_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_beacon_ie_len = wps_ielen; ++ ++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); ++ ++ } ++ ++ //buf += wps_ielen; ++ //len -= wps_ielen; ++ ++ #ifdef CONFIG_P2P ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("bcn_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_beacon_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_beacon_ie_len; ++ pmlmepriv->p2p_beacon_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len); ++ pmlmepriv->p2p_beacon_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_beacon_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_beacon_ie_len = p2p_ielen; ++ ++ } ++ #endif //CONFIG_P2P ++ ++ //buf += p2p_ielen; ++ //len -= p2p_ielen; ++ ++ #ifdef CONFIG_WFD ++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen)) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("bcn_wfd_ielen=%d\n", wfd_ielen); ++ #endif ++ ++ if(pmlmepriv->wfd_beacon_ie) ++ { ++ u32 free_len = pmlmepriv->wfd_beacon_ie_len; ++ pmlmepriv->wfd_beacon_ie_len = 0; ++ rtw_mfree(pmlmepriv->wfd_beacon_ie, free_len); ++ pmlmepriv->wfd_beacon_ie = NULL; ++ } ++ ++ pmlmepriv->wfd_beacon_ie = rtw_malloc(wfd_ielen); ++ if ( pmlmepriv->wfd_beacon_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len); ++ } ++ #endif //CONFIG_WFD ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 *p2p_ie; ++ u32 wfd_ielen = 0; ++ u8 *wfd_ie; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ uint attr_contentlen = 0; ++ u16 uconfig_method, *puconfig_method = NULL; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_resp_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) ++ { ++ u8 sr = 0; ++ rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); ++ ++ if (sr != 0) ++ { ++ DBG_871X("%s, got sr\n", __func__); ++ } ++ else ++ { ++ DBG_8192C("GO mode process WPS under site-survey, sr no set\n"); ++ return ret; ++ } ++ } ++ ++ if(pmlmepriv->wps_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_resp_ie_len; ++ pmlmepriv->wps_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len); ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_probe_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ //add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode ++ if ( (puconfig_method = (u16*)rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen)) != NULL ) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ //printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); ++ #endif ++ ++ uconfig_method = WPS_CM_PUSH_BUTTON; ++ uconfig_method = cpu_to_be16( uconfig_method ); ++ ++ *puconfig_method |= uconfig_method; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_probe_resp_ie_len = wps_ielen; ++ ++ } ++ ++ //buf += wps_ielen; ++ //len -= wps_ielen; ++ ++ #ifdef CONFIG_P2P ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ u8 is_GO = _FALSE; ++ u32 attr_contentlen = 0; ++ u16 cap_attr=0; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_resp_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ //Check P2P Capability ATTR ++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) ++ { ++ u8 grp_cap=0; ++ //DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); ++ cap_attr = le16_to_cpu(cap_attr); ++ grp_cap = (u8)((cap_attr >> 8)&0xff); ++ ++ is_GO = (grp_cap&BIT(0)) ? _TRUE:_FALSE; ++ ++ if(is_GO) ++ DBG_8192C("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap); ++ } ++ ++ ++ if(is_GO == _FALSE) ++ { ++ if(pmlmepriv->p2p_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_probe_resp_ie_len; ++ pmlmepriv->p2p_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len); ++ pmlmepriv->p2p_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_probe_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen; ++ } ++ else ++ { ++ if(pmlmepriv->p2p_go_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len; ++ pmlmepriv->p2p_go_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len); ++ pmlmepriv->p2p_go_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_go_probe_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen; ++ } ++ ++ } ++ #endif //CONFIG_P2P ++ ++ //buf += p2p_ielen; ++ //len -= p2p_ielen; ++ ++ #ifdef CONFIG_WFD ++ if(rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen)) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("probe_resp_wfd_ielen=%d\n", wfd_ielen); ++ #endif ++ ++ if(pmlmepriv->wfd_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->wfd_probe_resp_ie_len; ++ pmlmepriv->wfd_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->wfd_probe_resp_ie, free_len); ++ pmlmepriv->wfd_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->wfd_probe_resp_ie = rtw_malloc(wfd_ielen); ++ if ( pmlmepriv->wfd_probe_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ rtw_get_wfd_ie(buf, len, pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len); ++ } ++ #endif //CONFIG_WFD ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ DBG_8192C("%s, ielen=%d\n", __func__, len); ++ ++ if(len>0) ++ { ++ if(pmlmepriv->wps_assoc_resp_ie) ++ { ++ u32 free_len = pmlmepriv->wps_assoc_resp_ie_len; ++ pmlmepriv->wps_assoc_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len); ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ } ++ ++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(len); ++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, buf, len); ++ pmlmepriv->wps_assoc_resp_ie_len = len; ++ } ++ ++ return ret; ++ ++} ++ ++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, ++ int type) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u32 p2p_ielen = 0; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_8192C("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if( (rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen>0)) ++ #ifdef CONFIG_P2P ++ || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen>0)) ++ #endif ++ ) ++ { ++ if (net != NULL) ++ { ++ switch (type) ++ { ++ case 0x1: //BEACON ++ ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len); ++ break; ++ case 0x2: //PROBE_RESP ++ ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); ++ break; ++ case 0x4: //ASSOC_RESP ++ ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++static struct cfg80211_ops rtw_cfg80211_ops = { ++ .change_virtual_intf = cfg80211_rtw_change_iface, ++ .add_key = cfg80211_rtw_add_key, ++ .get_key = cfg80211_rtw_get_key, ++ .del_key = cfg80211_rtw_del_key, ++ .set_default_key = cfg80211_rtw_set_default_key, ++ .get_station = cfg80211_rtw_get_station, ++ .scan = cfg80211_rtw_scan, ++ .set_wiphy_params = cfg80211_rtw_set_wiphy_params, ++ .connect = cfg80211_rtw_connect, ++ .disconnect = cfg80211_rtw_disconnect, ++ .join_ibss = cfg80211_rtw_join_ibss, ++ .leave_ibss = cfg80211_rtw_leave_ibss, ++ .set_tx_power = cfg80211_rtw_set_txpower, ++ .get_tx_power = cfg80211_rtw_get_txpower, ++ .set_power_mgmt = cfg80211_rtw_set_power_mgmt, ++ .set_pmksa = cfg80211_rtw_set_pmksa, ++ .del_pmksa = cfg80211_rtw_del_pmksa, ++ .flush_pmksa = cfg80211_rtw_flush_pmksa, ++ ++#ifdef CONFIG_AP_MODE ++ .add_virtual_intf = cfg80211_rtw_add_virtual_intf, ++ .del_virtual_intf = cfg80211_rtw_del_virtual_intf, ++ ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) ++ .add_beacon = cfg80211_rtw_add_beacon, ++ .set_beacon = cfg80211_rtw_set_beacon, ++ .del_beacon = cfg80211_rtw_del_beacon, ++ #else ++ .start_ap = cfg80211_rtw_start_ap, ++ .change_beacon = cfg80211_rtw_change_beacon, ++ .stop_ap = cfg80211_rtw_stop_ap, ++ #endif ++ ++ .add_station = cfg80211_rtw_add_station, ++ .del_station = cfg80211_rtw_del_station, ++ .change_station = cfg80211_rtw_change_station, ++ .dump_station = cfg80211_rtw_dump_station, ++ .change_bss = cfg80211_rtw_change_bss, ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) ++ .set_channel = cfg80211_rtw_set_channel, ++ #endif ++ //.auth = cfg80211_rtw_auth, ++ //.assoc = cfg80211_rtw_assoc, ++#endif //CONFIG_AP_MODE ++ ++#ifdef CONFIG_P2P ++ .remain_on_channel = cfg80211_rtw_remain_on_channel, ++ .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel, ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++ .mgmt_tx = cfg80211_rtw_mgmt_tx, ++ .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register, ++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) ++ .action = cfg80211_rtw_mgmt_tx, ++#endif ++}; ++ ++static void rtw_cfg80211_init_ht_capab(struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band, u8 rf_type) ++{ ++ ++#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */ ++#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */ ++ ++ ht_cap->ht_supported = _TRUE; ++ ++ ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; ++ ++ /* ++ *Maximum length of AMPDU that the STA can receive. ++ *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets) ++ */ ++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; ++ ++ /*Minimum MPDU start spacing , */ ++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; ++ ++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; ++ ++ /* ++ *hw->wiphy->bands[IEEE80211_BAND_2GHZ] ++ *base on ant_num ++ *rx_mask: RX mask ++ *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7 ++ *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15 ++ *if rx_ant >=3 rx_mask[2]=0xff; ++ *if BW_40 rx_mask[4]=0x01; ++ *highest supported RX rate ++ */ ++ if(rf_type == RF_1T1R) ++ { ++ ht_cap->mcs.rx_mask[0] = 0xFF; ++ ht_cap->mcs.rx_mask[1] = 0x00; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7; ++ } ++ else if((rf_type == RF_1T2R) || (rf_type==RF_2T2R)) ++ { ++ ht_cap->mcs.rx_mask[0] = 0xFF; ++ ht_cap->mcs.rx_mask[1] = 0xFF; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15; ++ } ++ else ++ { ++ DBG_8192C("%s, error rf_type=%d\n", __func__, rf_type); ++ } ++ ++} ++ ++void rtw_cfg80211_init_wiphy(_adapter *padapter) ++{ ++ u8 rf_type; ++ struct ieee80211_supported_band *bands; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct wiphy *wiphy = pwdev->wiphy; ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ DBG_8192C("%s:rf_type=%d\n", __func__, rf_type); ++ ++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */ ++ { ++ bands = wiphy->bands[IEEE80211_BAND_2GHZ]; ++ if(bands) ++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_2GHZ, rf_type); ++ } ++ ++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */ ++ { ++ bands = wiphy->bands[IEEE80211_BAND_5GHZ]; ++ if(bands) ++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_5GHZ, rf_type); ++ } ++} ++ ++/* ++struct ieee80211_iface_limit rtw_limits[] = { ++ { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) ++ | BIT(NL80211_IFTYPE_ADHOC) ++#ifdef CONFIG_AP_MODE ++ | BIT(NL80211_IFTYPE_AP) ++#endif ++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) ++ | BIT(NL80211_IFTYPE_P2P_CLIENT) ++ | BIT(NL80211_IFTYPE_P2P_GO) ++#endif ++ }, ++ {.max = 1, .types = BIT(NL80211_IFTYPE_MONITOR)}, ++}; ++ ++struct ieee80211_iface_combination rtw_combinations = { ++ .limits = rtw_limits, ++ .n_limits = ARRAY_SIZE(rtw_limits), ++ .max_interfaces = 2, ++ .num_different_channels = 1, ++}; ++*/ ++ ++static void rtw_cfg80211_preinit_wiphy(_adapter *padapter, struct wiphy *wiphy) ++{ ++ ++ wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; ++ ++ wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT; ++ wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX; ++ wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) ++ wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION; ++#endif ++ ++ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) ++ | BIT(NL80211_IFTYPE_ADHOC) ++#ifdef CONFIG_AP_MODE ++ | BIT(NL80211_IFTYPE_AP) ++ | BIT(NL80211_IFTYPE_MONITOR) ++#endif ++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) ++ | BIT(NL80211_IFTYPE_P2P_CLIENT) ++ | BIT(NL80211_IFTYPE_P2P_GO) ++#endif ++ ; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) ++#ifdef CONFIG_AP_MODE ++ wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; ++#endif //CONFIG_AP_MODE ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) ++ wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); ++#endif ++ ++ /* ++ wiphy->iface_combinations = &rtw_combinations; ++ wiphy->n_iface_combinations = 1; ++ */ ++ ++ wiphy->cipher_suites = rtw_cipher_suites; ++ wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); ++ ++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */ ++ wiphy->bands[IEEE80211_BAND_2GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_2GHZ); ++ /* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */ ++ wiphy->bands[IEEE80211_BAND_5GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_5GHZ); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) && LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)) ++ wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS; ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) ++ wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; ++ wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; ++#endif ++ ++ if(padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE) ++ wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT; ++ else ++ wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; ++} ++ ++int rtw_wdev_alloc(_adapter *padapter, struct device *dev) ++{ ++ int ret = 0; ++ struct wiphy *wiphy; ++ struct wireless_dev *wdev; ++ struct rtw_wdev_priv *pwdev_priv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++ DBG_8192C("%s(padapter=%p)\n", __func__, padapter); ++ ++ /* wiphy */ ++ wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wdev_priv)); ++ if (!wiphy) { ++ DBG_8192C("Couldn't allocate wiphy device\n"); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ set_wiphy_dev(wiphy, dev); ++ rtw_cfg80211_preinit_wiphy(padapter, wiphy); ++ ++ ret = wiphy_register(wiphy); ++ if (ret < 0) { ++ DBG_8192C("Couldn't register wiphy device\n"); ++ goto free_wiphy; ++ } ++ ++ /* wdev */ ++ wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); ++ if (!wdev) { ++ DBG_8192C("Couldn't allocate wireless device\n"); ++ ret = -ENOMEM; ++ goto unregister_wiphy; ++ } ++ wdev->wiphy = wiphy; ++ wdev->netdev = pnetdev; ++ //wdev->iftype = NL80211_IFTYPE_STATION; ++ wdev->iftype = NL80211_IFTYPE_MONITOR; // for rtw_setopmode_cmd() in cfg80211_rtw_change_iface() ++ padapter->rtw_wdev = wdev; ++ pnetdev->ieee80211_ptr = wdev; ++ ++ //init pwdev_priv ++ pwdev_priv = wdev_to_priv(wdev); ++ pwdev_priv->rtw_wdev = wdev; ++ pwdev_priv->pmon_ndev = NULL; ++ pwdev_priv->ifname_mon[0] = '\0'; ++ pwdev_priv->padapter = padapter; ++ pwdev_priv->scan_request = NULL; ++ _rtw_spinlock_init(&pwdev_priv->scan_req_lock); ++ ++ pwdev_priv->p2p_enabled = _FALSE; ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ rtw_wdev_invit_info_init(&pwdev_priv->invit_info); ++ rtw_wdev_nego_info_init(&pwdev_priv->nego_info); ++ ++ pwdev_priv->bandroid_scan = _FALSE; ++ ++ if(padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE) ++ pwdev_priv->power_mgmt = _TRUE; ++ else ++ pwdev_priv->power_mgmt = _FALSE; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); ++ ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); ++#endif ++ ++ return ret; ++ ++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev)); ++unregister_wiphy: ++ wiphy_unregister(wiphy); ++ free_wiphy: ++ wiphy_free(wiphy); ++exit: ++ return ret; ++ ++} ++ ++void rtw_wdev_free(struct wireless_dev *wdev) ++{ ++ struct rtw_wdev_priv *pwdev_priv; ++ ++ DBG_8192C("%s(wdev=%p)\n", __func__, wdev); ++ ++ if (!wdev) ++ return; ++ ++ pwdev_priv = wdev_to_priv(wdev); ++ ++ rtw_spt_band_free(wdev->wiphy->bands[IEEE80211_BAND_2GHZ]); ++ rtw_spt_band_free(wdev->wiphy->bands[IEEE80211_BAND_5GHZ]); ++ ++ wiphy_free(wdev->wiphy); ++ ++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev)); ++} ++ ++void rtw_wdev_unregister(struct wireless_dev *wdev) ++{ ++ struct rtw_wdev_priv *pwdev_priv; ++ ++ DBG_8192C("%s(wdev=%p)\n", __func__, wdev); ++ ++ if (!wdev) ++ return; ++ ++ pwdev_priv = wdev_to_priv(wdev); ++ ++ rtw_cfg80211_indicate_scan_done(pwdev_priv, _TRUE); ++ ++ if (pwdev_priv->pmon_ndev) { ++ DBG_8192C("%s, unregister monitor interface\n", __func__); ++ unregister_netdev(pwdev_priv->pmon_ndev); ++ } ++ ++ wiphy_unregister(wdev->wiphy); ++} ++ ++#endif //CONFIG_IOCTL_CFG80211 ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_linux.c +new file mode 100644 +index 00000000..d76facb6 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/ioctl_linux.c +@@ -0,0 +1,14216 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IOCTL_LINUX_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#ifdef CONFIG_MP_INCLUDED ++#include ++//#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif //CONFIG_USB_HCI ++#include ++ ++#ifdef CONFIG_MP_INCLUDED ++#include ++#endif //#ifdef CONFIG_MP_INCLUDED ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#include ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++#ifdef CONFIG_GSPI_HCI ++#include ++#endif ++ ++#ifdef CONFIG_RTL8723A ++//extern u8 _InitPowerOn(PADAPTER padapter); ++//extern s32 rtl8723a_FirmwareDownload(PADAPTER padapter); ++extern s32 FillH2CCmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++#define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e) ++#define iwe_stream_add_point(a, b, c, d, e) iwe_stream_add_point(b, c, d, e) ++#endif ++ ++ ++#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 ++ ++#define SCAN_ITEM_SIZE 768 ++#define MAX_CUSTOM_LEN 64 ++#define RATE_COUNT 4 ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++extern int ui_pid[3]; ++#endif ++ ++// combo scan ++#define WEXT_CSCAN_AMOUNT 9 ++#define WEXT_CSCAN_BUF_LEN 360 ++#define WEXT_CSCAN_HEADER "CSCAN S\x01\x00\x00S\x00" ++#define WEXT_CSCAN_HEADER_SIZE 12 ++#define WEXT_CSCAN_SSID_SECTION 'S' ++#define WEXT_CSCAN_CHANNEL_SECTION 'C' ++#define WEXT_CSCAN_NPROBE_SECTION 'N' ++#define WEXT_CSCAN_ACTV_DWELL_SECTION 'A' ++#define WEXT_CSCAN_PASV_DWELL_SECTION 'P' ++#define WEXT_CSCAN_HOME_DWELL_SECTION 'H' ++#define WEXT_CSCAN_TYPE_SECTION 'T' ++ ++ ++extern u8 key_2char2num(u8 hch, u8 lch); ++extern u8 str_2char2num(u8 hch, u8 lch); ++extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); ++ ++u32 rtw_rates[] = {1000000,2000000,5500000,11000000, ++ 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000}; ++ ++static const char * const iw_operation_mode[] = ++{ ++ "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" ++}; ++ ++static int hex2num_i(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return c - '0'; ++ if (c >= 'a' && c <= 'f') ++ return c - 'a' + 10; ++ if (c >= 'A' && c <= 'F') ++ return c - 'A' + 10; ++ return -1; ++} ++ ++static int hex2byte_i(const char *hex) ++{ ++ int a, b; ++ a = hex2num_i(*hex++); ++ if (a < 0) ++ return -1; ++ b = hex2num_i(*hex++); ++ if (b < 0) ++ return -1; ++ return (a << 4) | b; ++} ++ ++/** ++ * hwaddr_aton - Convert ASCII string to MAC address ++ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") ++ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) ++ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) ++ */ ++static int hwaddr_aton_i(const char *txt, u8 *addr) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ int a, b; ++ ++ a = hex2num_i(*txt++); ++ if (a < 0) ++ return -1; ++ b = hex2num_i(*txt++); ++ if (b < 0) ++ return -1; ++ *addr++ = (a << 4) | b; ++ if (i < 5 && *txt++ != ':') ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void indicate_wx_custom_event(_adapter *padapter, char *msg) ++{ ++ u8 *buff, *p; ++ union iwreq_data wrqu; ++ ++ if (strlen(msg) > IW_CUSTOM_MAX) { ++ DBG_871X("%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\n", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX); ++ return; ++ } ++ ++ buff = rtw_zmalloc(IW_CUSTOM_MAX+1); ++ if(!buff) ++ return; ++ ++ _rtw_memcpy(buff, msg, strlen(msg)); ++ ++ _rtw_memset(&wrqu,0,sizeof(wrqu)); ++ wrqu.data.length = strlen(msg); ++ ++ DBG_871X("%s %s\n", __FUNCTION__, buff); ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff); ++#endif ++ ++ rtw_mfree(buff, IW_CUSTOM_MAX+1); ++ ++} ++ ++ ++static void request_wps_pbc_event(_adapter *padapter) ++{ ++ u8 *buff, *p; ++ union iwreq_data wrqu; ++ ++ ++ buff = rtw_malloc(IW_CUSTOM_MAX); ++ if(!buff) ++ return; ++ ++ _rtw_memset(buff, 0, IW_CUSTOM_MAX); ++ ++ p=buff; ++ ++ p+=sprintf(p, "WPS_PBC_START.request=TRUE"); ++ ++ _rtw_memset(&wrqu,0,sizeof(wrqu)); ++ ++ wrqu.data.length = p-buff; ++ ++ wrqu.data.length = (wrqu.data.lengthpnetdev, IWEVCUSTOM, &wrqu, buff); ++#endif ++ ++ if(buff) ++ { ++ rtw_mfree(buff, IW_CUSTOM_MAX); ++ } ++ ++} ++ ++ ++void indicate_wx_scan_complete_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ //DBG_871X("+rtw_indicate_wx_scan_complete_event\n"); ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL); ++#endif ++} ++ ++ ++void rtw_indicate_wx_assoc_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ wrqu.ap_addr.sa_family = ARPHRD_ETHER; ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) ++ _rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN); ++ else ++ _rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN); ++ ++ DBG_871X_LEVEL(_drv_always_, "assoc success\n"); ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); ++#endif ++} ++ ++void rtw_indicate_wx_disassoc_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ wrqu.ap_addr.sa_family = ARPHRD_ETHER; ++ _rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); ++ ++#ifndef CONFIG_IOCTL_CFG80211 ++ DBG_871X_LEVEL(_drv_always_, "indicate disassoc\n"); ++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); ++#endif ++} ++ ++/* ++uint rtw_is_cckrates_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ i++; ++ } ++ ++ return _FALSE; ++} ++ ++uint rtw_is_cckratesonly_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ return _FALSE; ++ i++; ++ } ++ ++ return _TRUE; ++} ++*/ ++ ++static char *translate_scan(_adapter *padapter, ++ struct iw_request_info* info, struct wlan_network *pnetwork, ++ char *start, char *stop) ++{ ++ struct iw_event iwe; ++ u16 cap; ++ u32 ht_ielen = 0; ++ char custom[MAX_CUSTOM_LEN]; ++ char *p; ++ u16 max_rate=0, rate, ht_cap=_FALSE; ++ u32 i = 0; ++ char *current_val; ++ long rssi; ++ u8 bw_40MHz=0, short_GI=0; ++ u16 mcs_rate=0; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_P2P ++#ifdef CONFIG_WFD ++ if ( SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type ) ++ { ++ ++ } ++ else if ( ( SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type ) || ++ ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type ) ) ++#endif // CONFIG_WFD ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ u32 blnGotP2PIE = _FALSE; ++ ++ // User is doing the P2P device discovery ++ // The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. ++ // If not, the driver should ignore this AP and go to the next AP. ++ ++ // Verifying the SSID ++ if ( _rtw_memcmp( pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ) ) ++ { ++ u32 p2pielen = 0; ++ ++ if (pnetwork->network.Reserved[0] == 2) { // Probe Request ++ // Verifying the P2P IE ++ if ( rtw_get_p2p_ie( pnetwork->network.IEs, pnetwork->network.IELength, NULL, &p2pielen) ) ++ { ++ blnGotP2PIE = _TRUE; ++ } ++ } else { // Beacon or Probe Respones ++ // Verifying the P2P IE ++ if ( rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen) ) ++ { ++ blnGotP2PIE = _TRUE; ++ } ++ } ++ } ++ ++ if ( blnGotP2PIE == _FALSE ) ++ { ++ return start; ++ } ++ ++ } ++ } ++ ++#ifdef CONFIG_WFD ++ if ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type ) ++ { ++ u32 blnGotWFD = _FALSE; ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ uint wfd_ielen = 0; ++ ++ if ( rtw_get_wfd_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, wfd_ie, &wfd_ielen, pnetwork->network.Reserved[0]) ) ++ { ++ u8 wfd_devinfo[ 6 ] = { 0x00 }; ++ uint wfd_devlen = 6; ++ ++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen) ) ++ { ++ if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK ) ++ { ++ // the first two bits will indicate the WFD device type ++ if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_SOURCE ) ++ { ++ // If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. ++ blnGotWFD = _TRUE; ++ } ++ } ++ else if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE ) ++ { ++ // the first two bits will indicate the WFD device type ++ if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_PSINK ) ++ { ++ // If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. ++ // Todo: How about the SSink?! ++ blnGotWFD = _TRUE; ++ } ++ } ++ } ++ } ++ ++ if ( blnGotWFD == _FALSE ) ++ { ++ return start; ++ } ++ } ++#endif // CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ /* AP MAC address */ ++ iwe.cmd = SIOCGIWAP; ++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN); ++ ++ /* Add the ESSID */ ++ iwe.cmd = SIOCGIWESSID; ++ iwe.u.data.flags = 1; ++ iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); ++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); ++ ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-12); ++ ++ if(p && ht_ielen>0) ++ { ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ ht_cap = _TRUE; ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); ++ bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; ++ short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; ++ } ++ ++ /* Add the protocol name */ ++ iwe.cmd = SIOCGIWNAME; ++ if ((rtw_is_cckratesonly_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); ++ } ++ else if ((rtw_is_cckrates_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg"); ++ } ++ else ++ { ++ if(pnetwork->network.Configuration.DSConfig > 14) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); ++ } ++ else ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); ++ } ++ } ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN); ++ ++ /* Add mode */ ++ iwe.cmd = SIOCGIWMODE; ++ _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); ++ ++ ++ cap = le16_to_cpu(cap); ++ ++ if(cap & (WLAN_CAPABILITY_IBSS |WLAN_CAPABILITY_BSS)){ ++ if (cap & WLAN_CAPABILITY_BSS) ++ iwe.u.mode = IW_MODE_MASTER; ++ else ++ iwe.u.mode = IW_MODE_ADHOC; ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN); ++ } ++ ++ if(pnetwork->network.Configuration.DSConfig<1 /*|| pnetwork->network.Configuration.DSConfig>14*/) ++ pnetwork->network.Configuration.DSConfig = 1; ++ ++ /* Add frequency/channel */ ++ iwe.cmd = SIOCGIWFREQ; ++ iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; ++ iwe.u.freq.e = 1; ++ iwe.u.freq.i = pnetwork->network.Configuration.DSConfig; ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN); ++ ++ /* Add encryption capability */ ++ iwe.cmd = SIOCGIWENCODE; ++ if (cap & WLAN_CAPABILITY_PRIVACY) ++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; ++ else ++ iwe.u.data.flags = IW_ENCODE_DISABLED; ++ iwe.u.data.length = 0; ++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); ++ ++ /*Add basic and extended rates */ ++ max_rate = 0; ++ p = custom; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); ++ while(pnetwork->network.SupportedRates[i]!=0) ++ { ++ rate = pnetwork->network.SupportedRates[i]&0x7F; ++ if (rate > max_rate) ++ max_rate = rate; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), ++ "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); ++ i++; ++ } ++ ++ if(ht_cap == _TRUE) ++ { ++ if(mcs_rate&0x8000)//MCS15 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); ++ ++ } ++ else if(mcs_rate&0x0080)//MCS7 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++ else//default MCS7 ++ { ++ //DBG_871X("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++ ++ max_rate = max_rate*2;//Mbps/2; ++ } ++ ++ iwe.cmd = SIOCGIWRATE; ++ iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; ++ iwe.u.bitrate.value = max_rate * 500000; ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN); ++ ++ //parsing WPA/WPA2 IE ++ { ++ u8 buf[MAX_WPA_IE_LEN]; ++ u8 wpa_ie[255],rsn_ie[255]; ++ u16 wpa_len=0,rsn_len=0; ++ u8 *p; ++ sint out_len=0; ++ out_len=rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,rsn_ie,&rsn_len,wpa_ie,&wpa_len); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); ++ ++ if (wpa_len > 0) ++ { ++ p=buf; ++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN); ++ p += sprintf(p, "wpa_ie="); ++ for (i = 0; i < wpa_len; i++) { ++ p += sprintf(p, "%02x", wpa_ie[i]); ++ } ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++ start = iwe_stream_add_point(info, start, stop, &iwe,buf); ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = wpa_len; ++ start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie); ++ } ++ if (rsn_len > 0) ++ { ++ p = buf; ++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN); ++ p += sprintf(p, "rsn_ie="); ++ for (i = 0; i < rsn_len; i++) { ++ p += sprintf(p, "%02x", rsn_ie[i]); ++ } ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++ start = iwe_stream_add_point(info, start, stop, &iwe,buf); ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = rsn_len; ++ start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie); ++ } ++ } ++ ++ { //parsing WPS IE ++ uint cnt = 0,total_ielen; ++ u8 *wpsie_ptr=NULL; ++ uint wps_ielen = 0; ++ ++ u8 *ie_ptr = pnetwork->network.IEs +_FIXED_IE_LENGTH_; ++ total_ielen= pnetwork->network.IELength - _FIXED_IE_LENGTH_; ++ ++ if (pnetwork->network.Reserved[0] == 2) // Probe Request ++ { ++ ie_ptr = pnetwork->network.IEs; ++ total_ielen = pnetwork->network.IELength; ++ } ++ else // Beacon or Probe Respones ++ { ++ ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; ++ total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; ++ } ++ ++ while(cnt < total_ielen) ++ { ++ if(rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen>2)) ++ { ++ wpsie_ptr = &ie_ptr[cnt]; ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = (u16)wps_ielen; ++ start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr); ++ } ++ cnt+=ie_ptr[cnt+1]+2; //goto next ++ } ++ } ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ { ++ sint out_len_wapi=0; ++ /* here use static for stack size */ ++ static u8 buf_wapi[MAX_WAPI_IE_LEN]; ++ static u8 wapi_ie[MAX_WAPI_IE_LEN]; ++ u16 wapi_len=0; ++ u16 i; ++ ++ _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN); ++ _rtw_memset(wapi_ie, 0, MAX_WAPI_IE_LEN); ++ ++ out_len_wapi=rtw_get_wapi_ie(pnetwork->network.IEs ,pnetwork->network.IELength,wapi_ie,&wapi_len); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wapi_len=%d \n",wapi_len)); ++ ++ DBG_871X("rtw_wx_get_scan: %s ",pnetwork->network.Ssid.Ssid); ++ DBG_871X("rtw_wx_get_scan: ssid = %d ",wapi_len); ++ ++ ++ if (wapi_len > 0) ++ { ++ p=buf_wapi; ++ _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN); ++ p += sprintf(p, "wapi_ie="); ++ for (i = 0; i < wapi_len; i++) { ++ p += sprintf(p, "%02x", wapi_ie[i]); ++ } ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf_wapi); ++ start = iwe_stream_add_point(info, start, stop, &iwe,buf_wapi); ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = wapi_len; ++ start = iwe_stream_add_point(info, start, stop, &iwe, wapi_ie); ++ } ++ } ++#endif //CONFIG_WAPI_SUPPORT ++ ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 ss, sq; ++ ++ /* Add quality statistics */ ++ iwe.cmd = IWEVQUAL; ++ iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED | IW_QUAL_NOISE_INVALID ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ | IW_QUAL_DBM ++ #endif ++ ; ++ ++ if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && ++ is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { ++ ss = padapter->recvpriv.signal_strength; ++ sq = padapter->recvpriv.signal_qual; ++ } else { ++ ss = pnetwork->network.PhyInfo.SignalStrength; ++ sq = pnetwork->network.PhyInfo.SignalQuality; ++ } ++ ++ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ iwe.u.qual.level = (u8) translate_percentage_to_dbm(ss);//dbm ++ #else ++ iwe.u.qual.level = (u8)ss;//% ++ #ifdef CONFIG_BT_COEXIST ++ BT_SignalCompensation(padapter, &iwe.u.qual.level, NULL); ++ #endif // CONFIG_BT_COEXIST ++ #endif ++ ++ iwe.u.qual.qual = (u8)sq; // signal quality ++ ++ #ifdef CONFIG_PLATFORM_ROCKCHIPS ++ iwe.u.qual.noise = -100; // noise level suggest by zhf@rockchips ++ #else ++ iwe.u.qual.noise = 0; // noise level ++ #endif //CONFIG_PLATFORM_ROCKCHIPS ++ ++ //DBG_871X("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN); ++} ++ ++ { ++ u8 buf[MAX_WPA_IE_LEN]; ++ u8 * p,*pos; ++ int len; ++ p = buf; ++ pos = pnetwork->network.Reserved; ++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN); ++ p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++ start = iwe_stream_add_point(info, start, stop, &iwe, buf); ++ } ++ ++ return start; ++} ++ ++static int wpa_set_auth_algs(struct net_device *dev, u32 value) ++{ ++ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); ++ int ret = 0; ++ ++ if ((value & AUTH_ALG_SHARED_KEY)&&(value & AUTH_ALG_OPEN_SYSTEM)) ++ { ++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n",value); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++ } ++ else if (value & AUTH_ALG_SHARED_KEY) ++ { ++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY [value:0x%x]\n",value); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; ++#endif ++ } ++ else if(value & AUTH_ALG_OPEN_SYSTEM) ++ { ++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n"); ++ //padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ if(padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) ++ { ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++#endif ++ } ++ ++ } ++ else if(value & AUTH_ALG_LEAP) ++ { ++ DBG_871X("wpa_set_auth_algs, AUTH_ALG_LEAP\n"); ++ } ++ else ++ { ++ DBG_871X("wpa_set_auth_algs, error!\n"); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ ++ if (param->u.crypt.idx >= WEP_KEYS ++#ifdef CONFIG_IEEE80211W ++ && param->u.crypt.idx > BIP_MAX_KEYID ++#endif //CONFIG_IEEE80211W ++ ) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++#ifdef CONFIG_WAPI_SUPPORT ++ if (strcmp(param->u.crypt.alg, "SMS4")) ++#endif ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); ++ DBG_871X("wpa_set_encryption, crypt.alg = WEP\n"); ++ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(1)wep_key_idx=%d\n", wep_key_idx)); ++ DBG_871X("(1)wep_key_idx=%d\n", wep_key_idx); ++ ++ if (wep_key_idx > WEP_KEYS) ++ return -EINVAL; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(2)wep_key_idx=%d\n", wep_key_idx)); ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,(" wpa_set_encryption: pwep allocate fail !!!\n")); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ if(wep_key_len==13) ++ { ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ } ++ } ++ else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ pwep->KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_871X("wep, set_tx=1\n"); ++ ++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) ++ { ++ ret = -EOPNOTSUPP ; ++ } ++ } ++ else ++ { ++ DBG_871X("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to fw/cam ++ ++ if (wep_key_idx >= WEP_KEYS) { ++ ret = -EOPNOTSUPP ; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0,_TRUE); ++ } ++ ++ goto exit; ++ } ++ ++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x ++ { ++ struct sta_info * psta,*pbcmc_sta; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ psta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ if(param->u.crypt.set_tx ==1)//pairwise key ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key ++ { ++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ padapter->securitypriv.busetkipkey=_FALSE; ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ } ++ ++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); ++ DBG_871X(" ~~~~set sta key:unicastkey\n"); ++ ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE, _TRUE); ++ } ++ else//group key ++ { ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ printk("[%s] GTK key_len=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.alg, param->u.crypt.key_len); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ //only TKIP group key need to install this ++ if(param->u.crypt.key_len > 16) ++ { ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); ++ } ++ padapter->securitypriv.binstallGrpkey = _TRUE; ++ //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ DBG_871X(" ~~~~set sta key:groupkey\n"); ++ ++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1,_TRUE); ++ } ++#ifdef CONFIG_IEEE80211W ++ else if(strcmp(param->u.crypt.alg, "BIP") == 0) ++ { ++ int no; ++ //printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); ++ //save the IGTK key, length 16 bytes ++ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ /*printk("IGTK key below:\n"); ++ for(no=0;no<16;no++) ++ printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); ++ printk("\n");*/ ++ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; ++ padapter->securitypriv.binstallBIPkey = _TRUE; ++ DBG_871X(" ~~~~set sta key:IGKT\n"); ++ } ++#endif //CONFIG_IEEE80211W ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); ++ } ++#endif //CONFIG_P2P ++ ++ } ++ } ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta==NULL) ++ { ++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ } ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode ++ { ++ } ++ } ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if (strcmp(param->u.crypt.alg, "SMS4") == 0) ++ { ++ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; ++ PRT_WAPI_STA_INFO pWapiSta; ++ u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; ++ ++ if(param->u.crypt.set_tx == 1) ++ { ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(_rtw_memcmp(pWapiSta->PeerMacAddr,param->sta_addr,6)) ++ { ++ _rtw_memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); ++ ++ pWapiSta->wapiUsk.bSet = true; ++ _rtw_memcpy(pWapiSta->wapiUsk.dataKey,param->u.crypt.key,16); ++ _rtw_memcpy(pWapiSta->wapiUsk.micKey,param->u.crypt.key+16,16); ++ pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; ++ pWapiSta->wapiUsk.bTxEnable = true; ++ ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); ++ _rtw_memcpy(pWapiSta->lastRxUnicastPN,WapiAEPNInitialValueSrc,16); ++ pWapiSta->wapiUskUpdate.bTxEnable = false; ++ pWapiSta->wapiUskUpdate.bSet = false; ++ ++ if (psecuritypriv->sw_encrypt== false || psecuritypriv->sw_decrypt == false) ++ { ++ //set unicast key for ASUE ++ rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); ++ } ++ } ++ } ++ } ++ else ++ { ++ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { ++ if(_rtw_memcmp(pWapiSta->PeerMacAddr,get_bssid(pmlmepriv),6)) ++ { ++ pWapiSta->wapiMsk.bSet = true; ++ _rtw_memcpy(pWapiSta->wapiMsk.dataKey,param->u.crypt.key,16); ++ _rtw_memcpy(pWapiSta->wapiMsk.micKey,param->u.crypt.key+16,16); ++ pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; ++ pWapiSta->wapiMsk.bTxEnable = false; ++ if(!pWapiSta->bSetkeyOk) ++ pWapiSta->bSetkeyOk = true; ++ pWapiSta->bAuthenticateInProgress = false; ++ ++ _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); ++ ++ if (psecuritypriv->sw_decrypt == false) ++ { ++ //set rx broadcast key for ASUE ++ rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); ++ } ++ } ++ ++ } ++ } ++ } ++#endif ++ ++exit: ++ ++ if (pwep) { ++ rtw_mfree((u8 *)pwep, wep_total_len); ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) ++{ ++ u8 *buf=NULL, *pos=NULL; ++ u32 left; ++ int group_cipher = 0, pairwise_cipher = 0; ++ int ret = 0; ++ u8 null_addr[]= {0,0,0,0,0,0}; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++ if((ielen > MAX_WPA_IE_LEN) || (pie == NULL)){ ++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ if(pie == NULL) ++ return ret; ++ else ++ return -EINVAL; ++ } ++ ++ if(ielen) ++ { ++ buf = rtw_zmalloc(ielen); ++ if (buf == NULL){ ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memcpy(buf, pie , ielen); ++ ++ //dump ++ { ++ int i; ++ DBG_871X("\n wpa_ie(length:%d):\n", ielen); ++ for(i=0;i= RSN_SELECTOR_LEN){ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ } ++ else if (left > 0){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much \n", left)); ++ ret =-1; ++ goto exit; ++ } ++#endif ++ ++ if(rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); ++ } ++ ++ if(rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); ++ } ++ ++ if (group_cipher == 0) ++ { ++ group_cipher = WPA_CIPHER_NONE; ++ } ++ if (pairwise_cipher == 0) ++ { ++ pairwise_cipher = WPA_CIPHER_NONE; ++ } ++ ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ {//set wps_ie ++ u16 cnt = 0; ++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ while( cnt < ielen ) ++ { ++ eid = buf[cnt]; ++ ++ if((eid==_VENDOR_SPECIFIC_IE_)&&(_rtw_memcmp(&buf[cnt+2], wps_oui, 4)==_TRUE)) ++ { ++ DBG_871X("SET WPS_IE\n"); ++ ++ padapter->securitypriv.wps_ie_len = ( (buf[cnt+1]+2) < (MAX_WPA_IE_LEN<<2)) ? (buf[cnt+1]+2):(MAX_WPA_IE_LEN<<2); ++ ++ _rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len); ++ ++ set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); ++ } ++#endif //CONFIG_P2P ++ cnt += buf[cnt+1]+2; ++ ++ break; ++ } else { ++ cnt += buf[cnt+1]+2; //goto next ++ } ++ } ++ } ++ } ++ ++ //TKIP and AES disallow multicast packets until installing group key ++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ ++ || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ ++ || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) ++ //WPS open need to enable multicast ++ //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) ++ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", ++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); ++ ++exit: ++ ++ if (buf) rtw_mfree(buf, ielen); ++ ++ return ret; ++} ++ ++static int rtw_wx_get_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u16 cap; ++ u32 ht_ielen = 0; ++ char *p; ++ u8 ht_cap=_FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ NDIS_802_11_RATES_EX* prates = NULL; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("cmd_code=%x\n", info->cmd)); ++ ++ _func_enter_; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12); ++ if(p && ht_ielen>0) ++ { ++ ht_cap = _TRUE; ++ } ++ ++ prates = &pcur_bss->SupportedRates; ++ ++ if (rtw_is_cckratesonly_included((u8*)prates) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); ++ } ++ else if ((rtw_is_cckrates_included((u8*)prates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); ++ } ++ else ++ { ++ if(pcur_bss->Configuration.DSConfig > 14) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a"); ++ } ++ else ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); ++ } ++ } ++ } ++ else ++ { ++ //prates = &padapter->registrypriv.dev_network.SupportedRates; ++ //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); ++ snprintf(wrqu->name, IFNAMSIZ, "unassociated"); ++ } ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_freq(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_wx_set_freq\n")); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_get_freq(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ //wrqu->freq.m = ieee80211_wlan_frequencies[pcur_bss->Configuration.DSConfig-1] * 100000; ++ wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000; ++ wrqu->freq.e = 1; ++ wrqu->freq.i = pcur_bss->Configuration.DSConfig; ++ ++ } ++ else{ ++ wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000; ++ wrqu->freq.e = 1; ++ wrqu->freq.i = padapter->mlmeextpriv.cur_channel; ++ } ++ ++ return 0; ++} ++ ++static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; ++ int ret = 0; ++ ++ _func_enter_; ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ switch(wrqu->mode) ++ { ++ case IW_MODE_AUTO: ++ networkType = Ndis802_11AutoUnknown; ++ DBG_871X("set_mode = IW_MODE_AUTO\n"); ++ break; ++ case IW_MODE_ADHOC: ++ networkType = Ndis802_11IBSS; ++ DBG_871X("set_mode = IW_MODE_ADHOC\n"); ++ break; ++ case IW_MODE_MASTER: ++ networkType = Ndis802_11APMode; ++ DBG_871X("set_mode = IW_MODE_MASTER\n"); ++ //rtw_setopmode_cmd(padapter, networkType,_TRUE); ++ break; ++ case IW_MODE_INFRA: ++ networkType = Ndis802_11Infrastructure; ++ DBG_871X("set_mode = IW_MODE_INFRA\n"); ++ break; ++ ++ default : ++ ret = -EINVAL;; ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("\n Mode: %s is not supported \n", iw_operation_mode[wrqu->mode])); ++ goto exit; ++ } ++ ++/* ++ if(Ndis802_11APMode == networkType) ++ { ++ rtw_setopmode_cmd(padapter, networkType,_TRUE); ++ } ++ else ++ { ++ rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown,_TRUE); ++ } ++*/ ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE){ ++ ++ ret = -EPERM; ++ goto exit; ++ ++ } ++ ++ rtw_setopmode_cmd(padapter, networkType,_TRUE); ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_get_mode \n")); ++ ++ _func_enter_; ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ wrqu->mode = IW_MODE_INFRA; ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ ++ { ++ wrqu->mode = IW_MODE_ADHOC; ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ wrqu->mode = IW_MODE_MASTER; ++ } ++ else ++ { ++ wrqu->mode = IW_MODE_AUTO; ++ } ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++ ++static int rtw_wx_set_pmkid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 j,blInserted = _FALSE; ++ int intReturn = _FALSE; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra; ++ u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; ++ u8 strIssueBssid[ ETH_ALEN ] = { 0x00 }; ++ ++/* ++ struct iw_pmksa ++ { ++ __u32 cmd; ++ struct sockaddr bssid; ++ __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16 ++ } ++ There are the BSSID information in the bssid.sa_data array. ++ If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information. ++ If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver. ++ If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver. ++ */ ++ ++ _rtw_memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); ++ if ( pPMK->cmd == IW_PMKSA_ADD ) ++ { ++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n" ); ++ if ( _rtw_memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN ) == _TRUE ) ++ { ++ return( intReturn ); ++ } ++ else ++ { ++ intReturn = _TRUE; ++ } ++ blInserted = _FALSE; ++ ++ //overwrite PMKID ++ for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => rewrite with new PMKID. ++ ++ DBG_871X( "[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n" ); ++ ++ _rtw_memcpy( psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); ++ psecuritypriv->PMKIDList[ j ].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex = j+1; ++ blInserted = _TRUE; ++ break; ++ } ++ } ++ ++ if(!blInserted) ++ { ++ // Find a new entry ++ DBG_871X( "[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n", ++ psecuritypriv->PMKIDIndex ); ++ ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); ++ ++ psecuritypriv->PMKIDList[ psecuritypriv->PMKIDIndex ].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex++ ; ++ if(psecuritypriv->PMKIDIndex==16) ++ { ++ psecuritypriv->PMKIDIndex =0; ++ } ++ } ++ } ++ else if ( pPMK->cmd == IW_PMKSA_REMOVE ) ++ { ++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n" ); ++ intReturn = _TRUE; ++ for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => Remove this PMKID information and reset it. ++ _rtw_memset( psecuritypriv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN ); ++ psecuritypriv->PMKIDList[ j ].bUsed = _FALSE; ++ break; ++ } ++ } ++ } ++ else if ( pPMK->cmd == IW_PMKSA_FLUSH ) ++ { ++ DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n" ); ++ _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ psecuritypriv->PMKIDIndex = 0; ++ intReturn = _TRUE; ++ } ++ return( intReturn ); ++} ++ ++static int rtw_wx_get_sens(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ #ifdef CONFIG_PLATFORM_ROCKCHIPS ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ /* ++ * 20110311 Commented by Jeff ++ * For rockchip platform's wpa_driver_wext_get_rssi ++ */ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ //wrqu->sens.value=-padapter->recvpriv.signal_strength; ++ wrqu->sens.value=-padapter->recvpriv.rssi; ++ //DBG_871X("%s: %d\n", __FUNCTION__, wrqu->sens.value); ++ wrqu->sens.fixed = 0; /* no auto select */ ++ } else ++ #endif ++ { ++ wrqu->sens.value = 0; ++ wrqu->sens.fixed = 0; /* no auto select */ ++ wrqu->sens.disabled = 1; ++ } ++ return 0; ++} ++ ++static int rtw_wx_get_range(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct iw_range *range = (struct iw_range *)extra; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ u16 val; ++ int i; ++ ++ _func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_range. cmd_code=%x\n", info->cmd)); ++ ++ wrqu->data.length = sizeof(*range); ++ _rtw_memset(range, 0, sizeof(*range)); ++ ++ /* Let's try to keep this struct in the same order as in ++ * linux/include/wireless.h ++ */ ++ ++ /* TODO: See what values we can set, and remove the ones we can't ++ * set, or fill them with some default data. ++ */ ++ ++ /* ~5 Mb/s real (802.11b) */ ++ range->throughput = 5 * 1000 * 1000; ++ ++ // TODO: Not used in 802.11b? ++// range->min_nwid; /* Minimal NWID we are able to set */ ++ // TODO: Not used in 802.11b? ++// range->max_nwid; /* Maximal NWID we are able to set */ ++ ++ /* Old Frequency (backward compat - moved lower ) */ ++// range->old_num_channels; ++// range->old_num_frequency; ++// range->old_freq[6]; /* Filler to keep "version" at the same offset */ ++ ++ /* signal level threshold range */ ++ ++ //percent values between 0 and 100. ++ range->max_qual.qual = 100; ++ range->max_qual.level = 100; ++ range->max_qual.noise = 100; ++ range->max_qual.updated = 7; /* Updated all three */ ++ ++ ++ range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ ++ /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ ++ range->avg_qual.level = 20 + -98; ++ range->avg_qual.noise = 0; ++ range->avg_qual.updated = 7; /* Updated all three */ ++ ++ range->num_bitrates = RATE_COUNT; ++ ++ for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) { ++ range->bitrate[i] = rtw_rates[i]; ++ } ++ ++ range->min_frag = MIN_FRAG_THRESHOLD; ++ range->max_frag = MAX_FRAG_THRESHOLD; ++ ++ range->pm_capa = 0; ++ ++ range->we_version_compiled = WIRELESS_EXT; ++ range->we_version_source = 16; ++ ++// range->retry_capa; /* What retry options are supported */ ++// range->retry_flags; /* How to decode max/min retry limit */ ++// range->r_time_flags; /* How to decode max/min retry life */ ++// range->min_retry; /* Minimal number of retries */ ++// range->max_retry; /* Maximal number of retries */ ++// range->min_r_time; /* Minimal retry lifetime */ ++// range->max_r_time; /* Maximal retry lifetime */ ++ ++ for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { ++ ++ // Include only legal frequencies for some countries ++ if(pmlmeext->channel_set[i].ChannelNum != 0) ++ { ++ range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; ++ range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; ++ range->freq[val].e = 1; ++ val++; ++ } ++ ++ if (val == IW_MAX_FREQUENCIES) ++ break; ++ } ++ ++ range->num_channels = val; ++ range->num_frequency = val; ++ ++// Commented by Albert 2009/10/13 ++// The following code will proivde the security capability to network manager. ++// If the driver doesn't provide this capability to network manager, ++// the WPA/WPA2 routers can't be choosen in the network manager. ++ ++/* ++#define IW_SCAN_CAPA_NONE 0x00 ++#define IW_SCAN_CAPA_ESSID 0x01 ++#define IW_SCAN_CAPA_BSSID 0x02 ++#define IW_SCAN_CAPA_CHANNEL 0x04 ++#define IW_SCAN_CAPA_MODE 0x08 ++#define IW_SCAN_CAPA_RATE 0x10 ++#define IW_SCAN_CAPA_TYPE 0x20 ++#define IW_SCAN_CAPA_TIME 0x40 ++*/ ++ ++#if WIRELESS_EXT > 17 ++ range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| ++ IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; ++#endif ++ ++#ifdef IW_SCAN_CAPA_ESSID //WIRELESS_EXT > 21 ++ range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID| ++ IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE; ++#endif ++ ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++//set bssid flow ++//s1. rtw_set_802_11_infrastructure_mode() ++//s2. rtw_set_802_11_authentication_mode() ++//s3. set_802_11_encryption_mode() ++//s4. rtw_set_802_11_bssid() ++static int rtw_wx_set_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ _irqL irqL; ++ uint ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sockaddr *temp = (struct sockaddr *)awrq; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _list *phead; ++ u8 *dst_bssid, *src_bssid; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ ++ _func_enter_; ++/* ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->iface_type > PRIMARY_IFACE) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++*/ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_871X("set bssid, but buddy_intf is under scanning or linking\n"); ++ ++ ret = -EINVAL; ++ ++ goto exit; ++ } ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE) ++ { ++ DBG_871X("set bssid, but buddy_intf is under scanning or linking\n"); ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) ++ { ++ ret= -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++ ++ if (temp->sa_family != ARPHRD_ETHER){ ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ authmode = padapter->securitypriv.ndisauthtype; ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ pmlmepriv->pscanned = get_next(phead); ++ ++ while (1) ++ { ++ ++ if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) ++ { ++#if 0 ++ ret = -EINVAL; ++ goto exit; ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ rtw_set_802_11_bssid(padapter, temp->sa_data); ++ goto exit; ++ } ++ else ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ dst_bssid = pnetwork->network.MacAddress; ++ ++ src_bssid = temp->sa_data; ++ ++ if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) ++ { ++ if(!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) ++ { ++ ret = -1; ++ _exit_critical_bh(&queue->lock, &irqL); ++ goto exit; ++ } ++ ++ break; ++ } ++ ++ } ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ wrqu->ap_addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_wap\n")); ++ ++ _func_enter_; ++ ++ if ( ((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) || ++ ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || ++ ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE) ) ++ { ++ ++ _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN); ++ } ++ else ++ { ++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); ++ } ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_set_mlme(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++#if 0 ++/* SIOCSIWMLME data */ ++struct iw_mlme ++{ ++ __u16 cmd; /* IW_MLME_* */ ++ __u16 reason_code; ++ struct sockaddr addr; ++}; ++#endif ++ ++ int ret=0; ++ u16 reason; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_mlme *mlme = (struct iw_mlme *) extra; ++ ++ ++ if(mlme==NULL) ++ return -1; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ reason = cpu_to_le16(mlme->reason_code); ++ ++ ++ DBG_871X("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason); ++ ++ ++ switch (mlme->cmd) ++ { ++ case IW_MLME_DEAUTH: ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ break; ++ ++ case IW_MLME_DISASSOC: ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return ret; ++} ++ ++static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u8 _status = _FALSE; ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++ _irqL irqL; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_set_scan\n")); ++ ++_func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++/* ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->iface_type > PRIMARY_IFACE) ++ { ++ ret = -1; ++ goto exit; ++ } ++#endif ++*/ ++ ++#ifdef CONFIG_MP_INCLUDED ++if (padapter->registrypriv.mp_mode == 1) ++{ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ret = -1; ++ goto exit; ++ } ++} ++#endif ++ if(_FAIL == rtw_pwr_wakeup(padapter)) ++ { ++ ret= -1; ++ goto exit; ++ } ++ ++ if(padapter->bDriverStopped){ ++ DBG_871X("bDriverStopped=%d\n", padapter->bDriverStopped); ++ ret= -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -1; ++ goto exit; ++ } ++ ++ // When Busy Traffic, driver do not site survey. So driver return success. ++ // wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. ++ // modify by thomas 2011-02-22. ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE ++#ifdef CONFIG_CONCURRENT_MODE ++ || rtw_get_buddy_bBusyTraffic(padapter) == _TRUE ++#endif //CONFIG_CONCURRENT_MODE ++ ) ++ { ++ indicate_wx_scan_complete_event(padapter); ++ goto exit; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ indicate_wx_scan_complete_event(padapter); ++ goto exit; ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ { ++ u32 curr_time, delta_time; ++ ++ // under DHCP(Special packet) ++ curr_time = rtw_get_current_time(); ++ delta_time = curr_time - adapter_to_pwrctl(padapter)->DelayLPSLastTimeStamp; ++ delta_time = rtw_systime_to_ms(delta_time); ++ if (delta_time < 500) // 500ms ++ { ++ DBG_871X("%s: send DHCP pkt before %d ms, Skip scan\n", __FUNCTION__, delta_time); ++ ret = -1; ++ goto exit; ++ } ++ } ++#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, ++ _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) ++ { ++ if(check_buddy_fwstate(padapter, _FW_UNDER_SURVEY)) ++ { ++ DBG_871X("scanning_via_buddy_intf\n"); ++ pmlmepriv->scanning_via_buddy_intf = _TRUE; ++ } ++ ++ indicate_wx_scan_complete_event(padapter); ++ ++ goto exit; ++ } ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE) ++ { ++ indicate_wx_scan_complete_event(padapter); ++ goto exit; ++ } ++#endif ++ ++// Mareded by Albert 20101103 ++// For the DMP WiFi Display project, the driver won't to scan because ++// the pmlmepriv->scan_interval is always equal to 3. ++// So, the wpa_supplicant won't find out the WPS SoftAP. ++ ++/* ++ if(pmlmepriv->scan_interval>10) ++ pmlmepriv->scan_interval = 0; ++ ++ if(pmlmepriv->scan_interval > 0) ++ { ++ DBG_871X("scan done\n"); ++ ret = 0; ++ goto exit; ++ } ++ ++*/ ++#ifdef CONFIG_P2P ++ if ( pwdinfo->p2p_state != P2P_STATE_NONE ) ++ { ++ rtw_p2p_set_pre_state( pwdinfo, rtw_p2p_state( pwdinfo ) ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL); ++ rtw_free_network_queue(padapter, _TRUE); ++ } ++#endif //CONFIG_P2P ++ ++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); ++ ++#if WIRELESS_EXT >= 17 ++ if (wrqu->data.length == sizeof(struct iw_scan_req)) ++ { ++ struct iw_scan_req *req = (struct iw_scan_req *)extra; ++ ++ if (wrqu->data.flags & IW_SCAN_THIS_ESSID) ++ { ++ int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); ++ ++ _rtw_memcpy(ssid[0].Ssid, req->essid, len); ++ ssid[0].SsidLength = len; ++ ++ DBG_871X("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ _status = rtw_sitesurvey_cmd(padapter, ssid, 1, NULL, 0); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ } ++ else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) ++ { ++ DBG_871X("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); ++ } ++ ++ } ++ else ++#endif ++ ++ if( wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE ++ && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE ++ ) ++ { ++ int len = wrqu->data.length -WEXT_CSCAN_HEADER_SIZE; ++ char *pos = extra+WEXT_CSCAN_HEADER_SIZE; ++ char section; ++ char sec_len; ++ int ssid_index = 0; ++ ++ //DBG_871X("%s COMBO_SCAN header is recognized\n", __FUNCTION__); ++ ++ while(len >= 1) { ++ section = *(pos++); len-=1; ++ ++ switch(section) { ++ case WEXT_CSCAN_SSID_SECTION: ++ //DBG_871X("WEXT_CSCAN_SSID_SECTION\n"); ++ if(len < 1) { ++ len = 0; ++ break; ++ } ++ ++ sec_len = *(pos++); len-=1; ++ ++ if(sec_len>0 && sec_len<=len) { ++ ssid[ssid_index].SsidLength = sec_len; ++ _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); ++ //DBG_871X("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ ++ // , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); ++ ssid_index++; ++ } ++ ++ pos+=sec_len; len-=sec_len; ++ break; ++ ++ ++ case WEXT_CSCAN_CHANNEL_SECTION: ++ //DBG_871X("WEXT_CSCAN_CHANNEL_SECTION\n"); ++ pos+=1; len-=1; ++ break; ++ case WEXT_CSCAN_ACTV_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_PASV_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_PASV_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_HOME_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_HOME_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_TYPE_SECTION: ++ //DBG_871X("WEXT_CSCAN_TYPE_SECTION\n"); ++ pos+=1; len-=1; ++ break; ++ #if 0 ++ case WEXT_CSCAN_NPROBE_SECTION: ++ DBG_871X("WEXT_CSCAN_NPROBE_SECTION\n"); ++ break; ++ #endif ++ ++ default: ++ //DBG_871X("Unknown CSCAN section %c\n", section); ++ len = 0; // stop parsing ++ } ++ //DBG_871X("len:%d\n", len); ++ ++ } ++ ++ //jeff: it has still some scan paramater to parse, we only do this now... ++ _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT); ++ ++ } else ++ ++ { ++ _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0); ++ } ++ ++ if(_status == _FALSE) ++ ret = -1; ++ ++exit: ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ char *ev = extra; ++ char *stop = ev + wrqu->data.length; ++ u32 ret = 0; ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ sint wait_status; ++#ifdef CONFIG_CONCURRENT_MODE ++ //PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++#endif ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan\n")); ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_, (" Start of Query SIOCGIWSCAN .\n")); ++ ++ _func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++ ++/* ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->iface_type > PRIMARY_IFACE) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++*/ ++ if(adapter_to_pwrctl(padapter)->brfoffbyhw && padapter->bDriverStopped) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ // P2P is enabled ++ if ( padapter->chip_type == RTL8192D ) ++ wait_for_surveydone = 300; // Because the 8192du supports more channels. ++ else ++ wait_for_surveydone = 200; ++ } ++ else ++ { ++ // P2P is disabled ++ wait_for_surveydone = 100; ++ } ++#else ++ { ++ wait_for_surveydone = 100; ++ } ++#endif //CONFIG_P2P ++ ++/* ++#ifdef CONFIG_CONCURRENT_MODE ++ if(pmlmepriv->scanning_via_buddy_intf == _TRUE) ++ { ++ pmlmepriv->scanning_via_buddy_intf = _FALSE;//reset ++ ++ // change pointers to buddy interface ++ padapter = pbuddy_adapter; ++ pmlmepriv = pbuddy_mlmepriv; ++ queue = &(pbuddy_mlmepriv->scanned_queue); ++ ++ } ++#endif // CONFIG_CONCURRENT_MODE ++*/ ++#if 1 // Wireless Extension use EAGAIN to try ++ wait_status = _FW_UNDER_SURVEY ++#ifndef CONFIG_ANDROID ++ | _FW_UNDER_LINKING ++#endif ++ ; ++ ++ while (check_fwstate(pmlmepriv, wait_status) == _TRUE) ++ { ++ return -EAGAIN; ++ } ++#else ++ wait_status = _FW_UNDER_SURVEY ++ #ifndef CONFIG_ANDROID ++ |_FW_UNDER_LINKING ++ #endif ++ ; ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ while(dc_check_fwstate(padapter, wait_status)== _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > wait_for_surveydone ) ++ break; ++ } ++#endif // CONFIG_DUALMAC_CONCURRENT ++ ++ while(check_fwstate(pmlmepriv, wait_status) == _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > wait_for_surveydone ) ++ break; ++ } ++#endif ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ if((stop - ev) < SCAN_ITEM_SIZE) { ++ ret = -E2BIG; ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //report network only if the current channel set contains the channel to which this network belongs ++ if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 ++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) ++ ) ++ { ++ ev=translate_scan(padapter, a, pnetwork, ev, stop); ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ wrqu->data.length = ev-extra; ++ wrqu->data.flags = 0; ++ ++exit: ++ ++ _func_exit_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++ return ret ; ++ ++} ++ ++//set ssid flow ++//s1. rtw_set_802_11_infrastructure_mode() ++//s2. set_802_11_authenticaion_mode() ++//s3. set_802_11_encryption_mode() ++//s4. rtw_set_802_11_ssid() ++static int rtw_wx_set_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _queue *queue = &pmlmepriv->scanned_queue; ++ _list *phead; ++ s8 status = _TRUE; ++ struct wlan_network *pnetwork = NULL; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ NDIS_802_11_SSID ndis_ssid; ++ u8 *dst_ssid, *src_ssid; ++ ++ uint ret = 0, len; ++ ++ _func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++ ++/* ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->iface_type > PRIMARY_IFACE) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++*/ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_871X("set ssid, but buddy_intf is under scanning or linking\n"); ++ ++ ret = -EINVAL; ++ ++ goto exit; ++ } ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ if (dc_check_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING)== _TRUE) ++ { ++ DBG_871X("set bssid, but buddy_intf is under scanning or linking\n"); ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("+rtw_wx_set_essid: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); ++ if(_FAIL == rtw_pwr_wakeup(padapter)) ++ { ++ ret = -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++#if WIRELESS_EXT <= 20 ++ if ((wrqu->essid.length-1) > IW_ESSID_MAX_SIZE){ ++#else ++ if (wrqu->essid.length > IW_ESSID_MAX_SIZE){ ++#endif ++ ret= -E2BIG; ++ goto exit; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ ret = -1; ++ goto exit; ++ } ++ ++ authmode = padapter->securitypriv.ndisauthtype; ++ DBG_871X("=>%s\n",__FUNCTION__); ++ if (wrqu->essid.flags && wrqu->essid.length) ++ { ++ // Commented by Albert 20100519 ++ // We got the codes in "set_info" function of iwconfig source code. ++ // ========================================= ++ // wrq.u.essid.length = strlen(essid) + 1; ++ // if(we_kernel_version > 20) ++ // wrq.u.essid.length--; ++ // ========================================= ++ // That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. ++#if WIRELESS_EXT <= 20 ++ len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE; ++#else ++ len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE; ++#endif ++ ++ if( wrqu->essid.length != 33 ) ++ DBG_871X("ssid=%s, len=%d\n", extra, wrqu->essid.length); ++ ++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ ndis_ssid.SsidLength = len; ++ _rtw_memcpy(ndis_ssid.Ssid, extra, len); ++ src_ssid = ndis_ssid.Ssid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_essid: ssid=[%s]\n", src_ssid)); ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ pmlmepriv->pscanned = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) ++ { ++#if 0 ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ rtw_set_802_11_ssid(padapter, &ndis_ssid); ++ ++ goto exit; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("rtw_wx_set_ssid(): scanned_queue is empty\n")); ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_, ++ ("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n")); ++ ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ dst_ssid = pnetwork->network.Ssid.Ssid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_wx_set_essid: dst_ssid=%s\n", ++ pnetwork->network.Ssid.Ssid)); ++ ++ if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && ++ (pnetwork->network.Ssid.SsidLength==ndis_ssid.SsidLength)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_wx_set_essid: find match, set infra mode\n")); ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) ++ continue; ++ } ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) ++ { ++ ret = -1; ++ _exit_critical_bh(&queue->lock, &irqL); ++ goto exit; ++ } ++ ++ break; ++ } ++ } ++ _exit_critical_bh(&queue->lock, &irqL); ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("set ssid: set_802_11_auth. mode=%d\n", authmode)); ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++ DBG_871X("<=%s, ret %d\n",__FUNCTION__, ret); ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u32 len,ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_essid\n")); ++ ++ _func_enter_; ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ len = pcur_bss->Ssid.SsidLength; ++ ++ wrqu->essid.length = len; ++ ++ _rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len); ++ ++ wrqu->essid.flags = 1; ++ } ++ else ++ { ++ ret = -1; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_set_rate(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int i, ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 datarates[NumRates]; ++ u32 target_rate = wrqu->bitrate.value; ++ u32 fixed = wrqu->bitrate.fixed; ++ u32 ratevalue = 0; ++ u8 mpdatarate[NumRates]={11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff}; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_set_rate \n")); ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("target_rate = %d, fixed = %d\n",target_rate,fixed)); ++ ++ if(target_rate == -1){ ++ ratevalue = 11; ++ goto set_rate; ++ } ++ target_rate = target_rate/100000; ++ ++ switch(target_rate){ ++ case 10: ++ ratevalue = 0; ++ break; ++ case 20: ++ ratevalue = 1; ++ break; ++ case 55: ++ ratevalue = 2; ++ break; ++ case 60: ++ ratevalue = 3; ++ break; ++ case 90: ++ ratevalue = 4; ++ break; ++ case 110: ++ ratevalue = 5; ++ break; ++ case 120: ++ ratevalue = 6; ++ break; ++ case 180: ++ ratevalue = 7; ++ break; ++ case 240: ++ ratevalue = 8; ++ break; ++ case 360: ++ ratevalue = 9; ++ break; ++ case 480: ++ ratevalue = 10; ++ break; ++ case 540: ++ ratevalue = 11; ++ break; ++ default: ++ ratevalue = 11; ++ break; ++ } ++ ++set_rate: ++ ++ for(i=0; ibitrate.fixed = 0; /* no auto select */ ++ wrqu->bitrate.value = max_rate * 100000; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_rts(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ if (wrqu->rts.disabled) ++ padapter->registrypriv.rts_thresh = 2347; ++ else { ++ if (wrqu->rts.value < 0 || ++ wrqu->rts.value > 2347) ++ return -EINVAL; ++ ++ padapter->registrypriv.rts_thresh = wrqu->rts.value; ++ } ++ ++ DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_get_rts(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); ++ ++ wrqu->rts.value = padapter->registrypriv.rts_thresh; ++ wrqu->rts.fixed = 0; /* no auto select */ ++ //wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ if (wrqu->frag.disabled) ++ padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD; ++ else { ++ if (wrqu->frag.value < MIN_FRAG_THRESHOLD || ++ wrqu->frag.value > MAX_FRAG_THRESHOLD) ++ return -EINVAL; ++ ++ padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1; ++ } ++ ++ DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_get_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); ++ ++ wrqu->frag.value = padapter->xmitpriv.frag_len; ++ wrqu->frag.fixed = 0; /* no auto select */ ++ //wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_get_retry(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ ++ wrqu->retry.value = 7; ++ wrqu->retry.fixed = 0; /* no auto select */ ++ wrqu->retry.disabled = 1; ++ ++ return 0; ++ ++} ++ ++#if 0 ++#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ ++#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ ++#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ ++#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ ++#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ ++#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ ++#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ ++#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ ++#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ ++/* ++iwconfig wlan0 key on -> flags = 0x6001 -> maybe it means auto ++iwconfig wlan0 key off -> flags = 0x8800 ++iwconfig wlan0 key open -> flags = 0x2800 ++iwconfig wlan0 key open 1234567890 -> flags = 0x2000 ++iwconfig wlan0 key restricted -> flags = 0x4800 ++iwconfig wlan0 key open [3] 1234567890 -> flags = 0x2003 ++iwconfig wlan0 key restricted [2] 1234567890 -> flags = 0x4002 ++iwconfig wlan0 key open [3] -> flags = 0x2803 ++iwconfig wlan0 key restricted [2] -> flags = 0x4802 ++*/ ++#endif ++ ++static int rtw_wx_set_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ u32 key, ret = 0; ++ u32 keyindex_provided; ++ NDIS_802_11_WEP wep; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ ++ struct iw_point *erq = &(wrqu->encoding); ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ DBG_871X("+rtw_wx_set_enc, flags=0x%x\n", erq->flags); ++ ++ _rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP)); ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ ++ _func_enter_; ++ ++ if (erq->flags & IW_ENCODE_DISABLED) ++ { ++ DBG_871X("EncryptionDisabled\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ ++ goto exit; ++ } ++ ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ keyindex_provided = 1; ++ } ++ else ++ { ++ keyindex_provided = 0; ++ key = padapter->securitypriv.dot11PrivacyKeyIndex; ++ DBG_871X("rtw_wx_set_enc, key=%d\n", key); ++ } ++ ++ //set authentication mode ++ if(erq->flags & IW_ENCODE_OPEN) ++ { ++ DBG_871X("rtw_wx_set_enc():IW_ENCODE_OPEN\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; ++#endif ++ ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ else if(erq->flags & IW_ENCODE_RESTRICTED) ++ { ++ DBG_871X("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Shared; ++#endif ++ ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ authmode = Ndis802_11AuthModeShared; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ else ++ { ++ DBG_871X("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags); ++ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ ++ wep.KeyIndex = key; ++ if (erq->length > 0) ++ { ++ wep.KeyLength = erq->length <= 5 ? 5 : 13; ++ ++ wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ } ++ else ++ { ++ wep.KeyLength = 0 ; ++ ++ if(keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0). ++ { ++ padapter->securitypriv.dot11PrivacyKeyIndex = key; ++ ++ DBG_871X("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]); ++ ++ switch(padapter->securitypriv.dot11DefKeylen[key]) ++ { ++ case 5: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ break; ++ case 13: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ break; ++ default: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ break; ++ } ++ ++ goto exit; ++ ++ } ++ ++ } ++ ++ wep.KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength); ++ ++ if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) { ++ if(rf_on == pwrpriv->rf_pwrstate ) ++ ret = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ uint key, ret =0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *erq = &(wrqu->encoding); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ _func_enter_; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) ++ { ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) ++ { ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ return 0; ++ } ++ } ++ ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ } else ++ { ++ key = padapter->securitypriv.dot11PrivacyKeyIndex; ++ } ++ ++ erq->flags = key + 1; ++ ++ //if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) ++ //{ ++ // erq->flags |= IW_ENCODE_OPEN; ++ //} ++ ++ switch(padapter->securitypriv.ndisencryptstatus) ++ { ++ case Ndis802_11EncryptionNotSupported: ++ case Ndis802_11EncryptionDisabled: ++ ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ ++ break; ++ ++ case Ndis802_11Encryption1Enabled: ++ ++ erq->length = padapter->securitypriv.dot11DefKeylen[key]; ++ ++ if(erq->length) ++ { ++ _rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]); ++ ++ erq->flags |= IW_ENCODE_ENABLED; ++ ++ if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) ++ { ++ erq->flags |= IW_ENCODE_OPEN; ++ } ++ else if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared) ++ { ++ erq->flags |= IW_ENCODE_RESTRICTED; ++ } ++ } ++ else ++ { ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ } ++ ++ break; ++ ++ case Ndis802_11Encryption2Enabled: ++ case Ndis802_11Encryption3Enabled: ++ ++ erq->length = 16; ++ erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY); ++ ++ break; ++ ++ default: ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ ++ break; ++ ++ } ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_power(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ wrqu->power.value = 0; ++ wrqu->power.fixed = 0; /* no auto select */ ++ wrqu->power.disabled = 1; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_set_gen_ie(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length); ++ ++ return ret; ++} ++ ++static int rtw_wx_set_auth(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_param *param = (struct iw_param*)&(wrqu->param); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 value = param->value; ++ int ret = 0; ++ ++ switch (param->flags & IW_AUTH_INDEX) { ++ ++ case IW_AUTH_WPA_VERSION: ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef CONFIG_IOCTL_CFG80211 ++ padapter->wapiInfo.bWapiEnable = false; ++ if(value == IW_AUTH_WAPI_VERSION_1) ++ { ++ padapter->wapiInfo.bWapiEnable = true; ++ psecuritypriv->dot11PrivacyAlgrthm = _SMS4_; ++ psecuritypriv->dot118021XGrpPrivacy = _SMS4_; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; ++ pmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm; ++ padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; ++ padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; ++ } ++#endif ++#endif ++ break; ++ case IW_AUTH_CIPHER_PAIRWISE: ++ ++ break; ++ case IW_AUTH_CIPHER_GROUP: ++ ++ break; ++ case IW_AUTH_KEY_MGMT: ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef CONFIG_IOCTL_CFG80211 ++ DBG_871X("rtw_wx_set_auth: IW_AUTH_KEY_MGMT case \n"); ++ if(value == IW_AUTH_KEY_MGMT_WAPI_PSK) ++ padapter->wapiInfo.bWapiPSK = true; ++ else ++ padapter->wapiInfo.bWapiPSK = false; ++ DBG_871X("rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d \n",padapter->wapiInfo.bWapiPSK); ++#endif ++#endif ++ /* ++ * ??? does not use these parameters ++ */ ++ break; ++ ++ case IW_AUTH_TKIP_COUNTERMEASURES: ++ { ++ if ( param->value ) ++ { // wpa_supplicant is enabling the tkip countermeasure. ++ padapter->securitypriv.btkip_countermeasure = _TRUE; ++ } ++ else ++ { // wpa_supplicant is disabling the tkip countermeasure. ++ padapter->securitypriv.btkip_countermeasure = _FALSE; ++ } ++ break; ++ } ++ case IW_AUTH_DROP_UNENCRYPTED: ++ { ++ /* HACK: ++ * ++ * wpa_supplicant calls set_wpa_enabled when the driver ++ * is loaded and unloaded, regardless of if WPA is being ++ * used. No other calls are made which can be used to ++ * determine if encryption will be used or not prior to ++ * association being expected. If encryption is not being ++ * used, drop_unencrypted is set to false, else true -- we ++ * can use this to determine if the CAP_PRIVACY_ON bit should ++ * be set. ++ */ ++ ++ if(padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) ++ { ++ break;//it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, ++ // then it needn't reset it; ++ } ++ ++ if(param->value){ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeOpen; ++ } ++ ++ break; ++ } ++ ++ case IW_AUTH_80211_AUTH_ALG: ++ ++ #if defined(CONFIG_ANDROID) || 1 ++ /* ++ * It's the starting point of a link layer connection using wpa_supplicant ++ */ ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { ++ LeaveAllPowerSaveMode(padapter); ++ rtw_disassoc_cmd(padapter, 500, _FALSE); ++ DBG_871X("%s...call rtw_indicate_disconnect\n ",__FUNCTION__); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ #endif ++ ++ ++ ret = wpa_set_auth_algs(dev, (u32)param->value); ++ ++ break; ++ ++ case IW_AUTH_WPA_ENABLED: ++ ++ //if(param->value) ++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; //802.1x ++ //else ++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;//open system ++ ++ //_disassociate(priv); ++ ++ break; ++ ++ case IW_AUTH_RX_UNENCRYPTED_EAPOL: ++ //ieee->ieee802_1x = param->value; ++ break; ++ ++ case IW_AUTH_PRIVACY_INVOKED: ++ //ieee->privacy_invoked = param->value; ++ break; ++ ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef CONFIG_IOCTL_CFG80211 ++ case IW_AUTH_WAPI_ENABLED: ++ break; ++#endif ++#endif ++ ++ default: ++ return -EOPNOTSUPP; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_set_enc_ext(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ char *alg_name; ++ u32 param_len; ++ struct ieee_param *param = NULL; ++ struct iw_point *pencoding = &wrqu->encoding; ++ struct iw_encode_ext *pext = (struct iw_encode_ext *)extra; ++ int ret=0; ++ ++ param_len = sizeof(struct ieee_param) + pext->key_len; ++ param = (struct ieee_param *)rtw_malloc(param_len); ++ if (param == NULL) ++ return -1; ++ ++ _rtw_memset(param, 0, param_len); ++ ++ param->cmd = IEEE_CMD_SET_ENCRYPTION; ++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); ++ ++ ++ switch (pext->alg) { ++ case IW_ENCODE_ALG_NONE: ++ //todo: remove key ++ //remove = 1; ++ alg_name = "none"; ++ break; ++ case IW_ENCODE_ALG_WEP: ++ alg_name = "WEP"; ++ break; ++ case IW_ENCODE_ALG_TKIP: ++ alg_name = "TKIP"; ++ break; ++ case IW_ENCODE_ALG_CCMP: ++ alg_name = "CCMP"; ++ break; ++#ifdef CONFIG_IEEE80211W ++ case IW_ENCODE_ALG_AES_CMAC: ++ alg_name = "BIP"; ++ break; ++#endif //CONFIG_IEEE80211W ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef CONFIG_IOCTL_CFG80211 ++ case IW_ENCODE_ALG_SM4: ++ alg_name= "SMS4"; ++ _rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN); ++ DBG_871X("rtw_wx_set_enc_ext: SMS4 case \n"); ++ break; ++#endif ++#endif ++ default: ++ return -1; ++ } ++ ++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); ++ ++ if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) ++ { ++ param->u.crypt.set_tx = 1; ++ } ++ ++ /* cliW: WEP does not have group key ++ * just not checking GROUP key setting ++ */ ++ if ((pext->alg != IW_ENCODE_ALG_WEP) && ++ ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) ++#ifdef CONFIG_IEEE80211W ++ || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC) ++#endif //CONFIG_IEEE80211W ++ )) ++ { ++ param->u.crypt.set_tx = 0; ++ } ++ ++ param->u.crypt.idx = (pencoding->flags&0x00FF) -1 ; ++ ++ if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) ++ { ++#ifdef CONFIG_WAPI_SUPPORT ++#ifndef CONFIG_IOCTL_CFG80211 ++ if(pext->alg == IW_ENCODE_ALG_SM4) ++ _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16); ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_WAPI_SUPPORT ++ _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8); ++ } ++ ++ if(pext->key_len) ++ { ++ param->u.crypt.key_len = pext->key_len; ++ //_rtw_memcpy(param + 1, pext + 1, pext->key_len); ++ _rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len); ++ } ++ ++ if (pencoding->flags & IW_ENCODE_DISABLED) ++ { ++ //todo: remove key ++ //remove = 1; ++ } ++ ++ ret = wpa_set_encryption(dev, param, param_len); ++ ++ if(param) ++ { ++ rtw_mfree((u8*)param, param_len); ++ } ++ ++ return ret; ++} ++ ++ ++static int rtw_wx_get_nick(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ //struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ if(extra) ++ { ++ wrqu->data.length = 14; ++ wrqu->data.flags = 1; ++ _rtw_memcpy(extra, "", 14); ++ } ++ ++ //rtw_signal_process(pid, SIGUSR1); //for test ++ ++ //dump debug info here ++/* ++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, and 8021x ++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. ++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key ++ u32 ndisauthtype; ++ u32 ndisencryptstatus; ++*/ ++ ++ //DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", ++ // psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ // psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ ++ //DBG_871X("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); ++ //DBG_871X("auth_type=0x%x\n", psecuritypriv->ndisauthtype); ++ //DBG_871X("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); ++ ++#if 0 ++ DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); ++ DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); ++ DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); ++ DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); ++ DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); ++ ++ DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); ++ ++ ++ DBG_871X("\n"); ++ ++ DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); ++ DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); ++ ++ DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); ++ ++ DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); ++ ++ DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); ++ DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); ++ ++ DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); ++ DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); ++ DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); ++ DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); ++#endif ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_read32(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter; ++ struct iw_point *p; ++ u16 len; ++ u32 addr; ++ u32 data32; ++ u32 bytes; ++ u8 *ptmp; ++ ++ ++ padapter = (PADAPTER)rtw_netdev_priv(dev); ++ p = &wrqu->data; ++ len = p->length; ++ ptmp = (u8*)rtw_malloc(len); ++ if (NULL == ptmp) ++ return -ENOMEM; ++ ++ if (copy_from_user(ptmp, p->pointer, len)) { ++ rtw_mfree(ptmp, len); ++ return -EFAULT; ++ } ++ ++ bytes = 0; ++ addr = 0; ++ sscanf(ptmp, "%d,%x", &bytes, &addr); ++ ++ switch (bytes) { ++ case 1: ++ data32 = rtw_read8(padapter, addr); ++ sprintf(extra, "0x%02X", data32); ++ break; ++ case 2: ++ data32 = rtw_read16(padapter, addr); ++ sprintf(extra, "0x%04X", data32); ++ break; ++ case 4: ++ data32 = rtw_read32(padapter, addr); ++ sprintf(extra, "0x%08X", data32); ++ break; ++ default: ++ DBG_871X(KERN_INFO "%s: usage> read [bytes],[address(hex)]\n", __func__); ++ return -EINVAL; ++ } ++ DBG_871X(KERN_INFO "%s: addr=0x%08X data=%s\n", __func__, addr, extra); ++ ++ rtw_mfree(ptmp, len); ++ ++ return 0; ++} ++ ++static int rtw_wx_write32(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); ++ ++ u32 addr; ++ u32 data32; ++ u32 bytes; ++ ++ ++ bytes = 0; ++ addr = 0; ++ data32 = 0; ++ sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32); ++ ++ switch (bytes) { ++ case 1: ++ rtw_write8(padapter, addr, (u8)data32); ++ DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32); ++ break; ++ case 2: ++ rtw_write16(padapter, addr, (u16)data32); ++ DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32); ++ break; ++ case 4: ++ rtw_write32(padapter, addr, data32); ++ DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32); ++ break; ++ default: ++ DBG_871X(KERN_INFO "%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtw_wx_read_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u32 path, addr, data32; ++ ++ ++ path = *(u32*)extra; ++ addr = *((u32*)extra + 1); ++ data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF); ++// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); ++ /* ++ * IMPORTANT!! ++ * Only when wireless private ioctl is at odd order, ++ * "extra" would be copied to user space. ++ */ ++ sprintf(extra, "0x%05x", data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u32 path, addr, data32; ++ ++ ++ path = *(u32*)extra; ++ addr = *((u32*)extra + 1); ++ data32 = *((u32*)extra + 2); ++// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); ++ rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ return -1; ++} ++ ++static int dummy(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ //DBG_871X("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); ++ ++ return -1; ++ ++} ++ ++static int rtw_wx_set_channel_plan(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ extern int rtw_channel_plan; ++ u8 channel_plan_req = (u8) (*((int *)wrqu)); ++ ++ #if 0 ++ rtw_channel_plan = (int)wrqu->data.pointer; ++ pregistrypriv->channel_plan = rtw_channel_plan; ++ pmlmepriv->ChannelPlan = pregistrypriv->channel_plan; ++ #endif ++ ++ if( _SUCCESS == rtw_set_chplan_cmd(padapter, channel_plan_req, 1) ) { ++ DBG_871X("%s set channel_plan = 0x%02X\n", __func__, pmlmepriv->ChannelPlan); ++ } else ++ return -EPERM; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ++ ("WLAN IOCTL: cmd_code=%x, fwstate=0x%x\n", ++ a->cmd, get_fwstate(pmlmepriv))); ++#endif ++ return 0; ++} ++ ++static int rtw_wx_get_sensitivity(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *buf) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ // Modified by Albert 20110914 ++ // This is in dbm format for MTK platform. ++ wrqu->qual.level = padapter->recvpriv.rssi; ++ DBG_871X(" level = %u\n", wrqu->qual.level ); ++#endif ++ return 0; ++} ++ ++static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length); ++#else ++ return 0; ++#endif ++} ++ ++/* ++typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++*/ ++/* ++ * For all data larger than 16 octets, we need to use a ++ * pointer to memory allocated in user space. ++ */ ++static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ #if 0 ++struct iw_point ++{ ++ void __user *pointer; /* Pointer to the data (in user space) */ ++ __u16 length; /* number of fields or size in bytes */ ++ __u16 flags; /* Optional params */ ++}; ++ #endif ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ u8 res; ++ struct drvext_handler *phandler; ++ struct drvext_oidparam *poidparam; ++ int ret; ++ u16 len; ++ u8 *pparmbuf, bset; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *p = &wrqu->data; ++ ++ if( (!p->length) || (!p->pointer)){ ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ bset = (u8)(p->flags&0xFFFF); ++ len = p->length; ++ pparmbuf = (u8*)rtw_malloc(len); ++ if (pparmbuf == NULL){ ++ ret = -ENOMEM; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ if(bset)//set info ++ { ++ if (copy_from_user(pparmbuf, p->pointer,len)) { ++ rtw_mfree(pparmbuf, len); ++ ret = -EFAULT; ++ goto _rtw_drvext_hdl_exit; ++ } ++ } ++ else//query info ++ { ++ ++ } ++ ++ ++ // ++ poidparam = (struct drvext_oidparam *)pparmbuf; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("drvext set oid subcode [%d], len[%d], InformationBufferLength[%d]\r\n", ++ poidparam->subcode, poidparam->len, len)); ++ ++ ++ //check subcode ++ if ( poidparam->subcode >= MAX_DRVEXT_HANDLERS) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext handlers\r\n")); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ if ( poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext subcodes\r\n")); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ phandler = drvextoidhandlers + poidparam->subcode; ++ ++ if (poidparam->len != phandler->parmsize) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext param size %d vs %d\r\n", ++ poidparam->len , phandler->parmsize)); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data); ++ ++ if(res==0) ++ { ++ ret = 0; ++ ++ if (bset == 0x00) {//query info ++ //_rtw_memcpy(p->pointer, pparmbuf, len); ++ if (copy_to_user(p->pointer, pparmbuf, len)) ++ ret = -EFAULT; ++ } ++ } ++ else ++ ret = -EFAULT; ++ ++ ++_rtw_drvext_hdl_exit: ++ ++ return ret; ++ ++#endif ++ ++ return 0; ++ ++} ++ ++static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) ++{ ++ pRW_Reg RegRWStruct; ++ struct rf_reg_param *prfreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ switch(id) ++ { ++ case GEN_MP_IOCTL_SUBCODE(MP_START): ++ DBG_871X("871x_driver is only for normal mode, can't enter mp mode\n"); ++ break; ++ case GEN_MP_IOCTL_SUBCODE(READ_REG): ++ RegRWStruct = (pRW_Reg)pdata; ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset); ++ break; ++ case 2: ++ RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset); ++ break; ++ case 4: ++ RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset); ++ break; ++ default: ++ break; ++ } ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(WRITE_REG): ++ RegRWStruct = (pRW_Reg)pdata; ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value); ++ break; ++ case 2: ++ rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value); ++ break; ++ case 4: ++ rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value); ++ break; ++ default: ++ break; ++ } ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(READ_RF_REG): ++ ++ prfreg = (struct rf_reg_param *)pdata; ++ ++ path = (u8)prfreg->path; ++ offset = (u8)prfreg->offset; ++ ++ value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff); ++ ++ prfreg->value = value; ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG): ++ ++ prfreg = (struct rf_reg_param *)pdata; ++ ++ path = (u8)prfreg->path; ++ offset = (u8)prfreg->offset; ++ value = prfreg->value; ++ ++ rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value); ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO): ++ DBG_871X("==> trigger gpio 0\n"); ++ rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0); ++ break; ++#ifdef CONFIG_BT_COEXIST ++ case GEN_MP_IOCTL_SUBCODE(SET_DM_BT): ++ DBG_871X("==> set dm_bt_coexist:%x\n",*(u8 *)pdata); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata); ++ break; ++ case GEN_MP_IOCTL_SUBCODE(DEL_BA): ++ DBG_871X("==> delete ba:%x\n",*(u8 *)pdata); ++ rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata); ++ break; ++#endif ++#ifdef DBG_CONFIG_ERROR_DETECT ++ case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS): ++ *pdata = rtw_hal_sreset_get_wifi_status(padapter); ++ break; ++#endif ++ ++ default: ++ break; ++ } ++ ++} ++ ++static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ u32 BytesRead, BytesWritten, BytesNeeded; ++ struct oid_par_priv oid_par; ++ struct mp_ioctl_handler *phandler; ++ struct mp_ioctl_param *poidparam; ++ uint status=0; ++ u16 len; ++ u8 *pparmbuf = NULL, bset; ++ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); ++ struct iw_point *p = &wrqu->data; ++ ++ //DBG_871X("+rtw_mp_ioctl_hdl\n"); ++ ++ //mutex_lock(&ioctl_mutex); ++ ++ if ((!p->length) || (!p->pointer)) { ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ pparmbuf = NULL; ++ bset = (u8)(p->flags & 0xFFFF); ++ len = p->length; ++ pparmbuf = (u8*)rtw_malloc(len); ++ if (pparmbuf == NULL){ ++ ret = -ENOMEM; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ if (copy_from_user(pparmbuf, p->pointer, len)) { ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ poidparam = (struct mp_ioctl_param *)pparmbuf; ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_mp_ioctl_hdl: subcode [%d], len[%d], buffer_len[%d]\r\n", ++ poidparam->subcode, poidparam->len, len)); ++ ++ if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n")); ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ //DBG_871X("%s: %d\n", __func__, poidparam->subcode); ++#ifdef CONFIG_MP_INCLUDED ++if (padapter->registrypriv.mp_mode == 1) ++{ ++ phandler = mp_ioctl_hdl + poidparam->subcode; ++ ++ if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ++ ("no matching drvext param size %d vs %d\r\n", ++ poidparam->len, phandler->paramsize)); ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ if (phandler->handler) ++ { ++ oid_par.adapter_context = padapter; ++ oid_par.oid = phandler->oid; ++ oid_par.information_buf = poidparam->data; ++ oid_par.information_buf_len = poidparam->len; ++ oid_par.dbg = 0; ++ ++ BytesWritten = 0; ++ BytesNeeded = 0; ++ ++ if (bset) { ++ oid_par.bytes_rw = &BytesRead; ++ oid_par.bytes_needed = &BytesNeeded; ++ oid_par.type_of_oid = SET_OID; ++ } else { ++ oid_par.bytes_rw = &BytesWritten; ++ oid_par.bytes_needed = &BytesNeeded; ++ oid_par.type_of_oid = QUERY_OID; ++ } ++ ++ status = phandler->handler(&oid_par); ++ ++ //todo:check status, BytesNeeded, etc. ++ } ++ else { ++ DBG_871X("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n", ++ poidparam->subcode, phandler->oid, phandler->handler); ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++} ++else ++#endif ++{ ++ rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len); ++} ++ ++ if (bset == 0x00) {//query info ++ if (copy_to_user(p->pointer, pparmbuf, len)) ++ ret = -EFAULT; ++ } ++ ++ if (status) { ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++_rtw_mp_ioctl_hdl_exit: ++ ++ if (pparmbuf) ++ rtw_mfree(pparmbuf, len); ++ ++ //mutex_unlock(&ioctl_mutex); ++ ++ return ret; ++} ++ ++static int rtw_get_ap_info(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int bssid_match, ret = 0; ++ u32 cnt=0, wpa_ielen; ++ _irqL irqL; ++ _list *plist, *phead; ++ unsigned char *pbuf; ++ u8 bssid[ETH_ALEN]; ++ char data[32]; ++ struct wlan_network *pnetwork = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct iw_point *pdata = &wrqu->data; ++ ++ DBG_871X("+rtw_get_aplist_info\n"); ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ while((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))) == _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > 100) ++ break; ++ } ++ ++ ++ //pdata->length = 0;//? ++ pdata->flags = 0; ++ if(pdata->length>=32) ++ { ++ if(copy_from_user(data, pdata->pointer, 32)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //if(hwaddr_aton_i(pdata->pointer, bssid)) ++ if(hwaddr_aton_i(data, bssid)) ++ { ++ DBG_871X("Invalid BSSID '%s'.\n", (u8*)data); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return -EINVAL; ++ } ++ ++ ++ if(_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)//BSSID match, then check if supporting wpa/wpa2 ++ { ++ DBG_871X("BSSID:" MAC_FMT "\n", MAC_ARG(bssid)); ++ ++ pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ if(pbuf && (wpa_ielen>0)) ++ { ++ pdata->flags = 1; ++ break; ++ } ++ ++ pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ if(pbuf && (wpa_ielen>0)) ++ { ++ pdata->flags = 2; ++ break; ++ } ++ ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if(pdata->length>=34) ++ { ++ if(copy_to_user((u8*)pdata->pointer+32, (u8*)&pdata->flags, 1)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_set_pid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ int *pdata = (int *)wrqu; ++ int selector; ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ selector = *pdata; ++ if(selector < 3 && selector >=0) { ++ padapter->pid[selector] = *(pdata+1); ++ #ifdef CONFIG_GLOBAL_UI_PID ++ ui_pid[selector] = *(pdata+1); ++ #endif ++ DBG_871X("%s set pid[%d]=%d\n", __FUNCTION__, selector ,padapter->pid[selector]); ++ } ++ else ++ DBG_871X("%s selector %d error\n", __FUNCTION__, selector); ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_wps_start(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ u32 u32wps_start = 0; ++ unsigned int uintRet = 0; ++ ++ uintRet = copy_from_user( ( void* ) &u32wps_start, pdata->pointer, 4 ); ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ if ( u32wps_start == 0 ) ++ { ++ u32wps_start = *extra; ++ } ++ ++ DBG_871X( "[%s] wps_start = %d\n", __FUNCTION__, u32wps_start ); ++ ++ if ( u32wps_start == 1 ) // WPS Start ++ { ++ rtw_led_control(padapter, LED_CTL_START_WPS); ++ } ++ else if ( u32wps_start == 2 ) // WPS Stop because of wps success ++ { ++ rtw_led_control(padapter, LED_CTL_STOP_WPS); ++ } ++ else if ( u32wps_start == 3 ) // WPS Stop because of wps fail ++ { ++ rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL); ++ } ++ ++#ifdef CONFIG_INTEL_WIDI ++ process_intel_widi_wps_status(padapter, u32wps_start); ++#endif //CONFIG_INTEL_WIDI ++ ++exit: ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_P2P ++static int rtw_wext_p2p_enable(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ enum P2P_ROLE init_role = P2P_ROLE_DISABLE; ++ ++ if(*extra == '0' ) ++ init_role = P2P_ROLE_DISABLE; ++ else if(*extra == '1') ++ init_role = P2P_ROLE_DEVICE; ++ else if(*extra == '2') ++ init_role = P2P_ROLE_CLIENT; ++ else if(*extra == '3') ++ init_role = P2P_ROLE_GO; ++ ++ if(_FAIL == rtw_p2p_enable(padapter, init_role)) ++ { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ //set channel/bandwidth ++ if(init_role != P2P_ROLE_DISABLE) ++ { ++ u8 channel, ch_offset; ++ u16 bwmode; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) ++ { ++ // Stay at the listen state and wait for discovery. ++ channel = pwdinfo->listen_channel; ++ pwdinfo->operating_channel = pwdinfo->listen_channel; ++ ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ bwmode = HT_CHANNEL_WIDTH_20; ++ } ++#ifdef CONFIG_CONCURRENT_MODE ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++ ++ _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval ); ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel; ++ // How about the ch_offset and bwmode ?? ++ } ++ else ++ { ++ pwdinfo->operating_channel = pwdinfo->listen_channel; ++ } ++ ++ channel = pbuddy_mlmeext->cur_channel; ++ ch_offset = pbuddy_mlmeext->cur_ch_offset; ++ bwmode = pbuddy_mlmeext->cur_bwmode; ++ } ++#endif ++ else ++ { ++ pwdinfo->operating_channel = pmlmeext->cur_channel; ++ ++ channel = pwdinfo->operating_channel; ++ ch_offset = pmlmeext->cur_ch_offset; ++ bwmode = pmlmeext->cur_bwmode; ++ } ++ ++ set_channel_bwmode(padapter, channel, ch_offset, bwmode); ++ } ++ ++exit: ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ DBG_871X( "[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen( extra ) ); ++ _rtw_memcpy( pwdinfo->nego_ssid, extra, strlen( extra ) ); ++ pwdinfo->nego_ssidlen = strlen( extra ); ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_set_intent(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 intent = pwdinfo->intent; ++ ++ extra[ wrqu->data.length ] = 0x00; ++ ++ intent = rtw_atoi( extra ); ++ ++ if ( intent <= 15 ) ++ { ++ pwdinfo->intent= intent; ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_871X( "[%s] intent = %d\n", __FUNCTION__, intent); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_listen_ch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 listen_ch = pwdinfo->listen_channel; // Listen channel number ++ ++ extra[ wrqu->data.length ] = 0x00; ++ listen_ch = rtw_atoi( extra ); ++ ++ if ( ( listen_ch == 1 ) || ( listen_ch == 6 ) || ( listen_ch == 11 ) ) ++ { ++ pwdinfo->listen_channel = listen_ch; ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_871X( "[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel ); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_op_ch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++// Commented by Albert 20110524 ++// This function is used to set the operating channel if the driver will become the group owner ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 op_ch = pwdinfo->operating_channel; // Operating channel number ++ ++ extra[ wrqu->data.length ] = 0x00; ++ ++ op_ch = ( u8 ) rtw_atoi( extra ); ++ if ( op_ch > 0 ) ++ { ++ pwdinfo->operating_channel = op_ch; ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_871X( "[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel ); ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_profilefound(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ // Comment by Albert 2010/10/13 ++ // Input data format: ++ // Ex: 0 ++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID ++ // 0 => Reflush the profile record list. ++ // 1 => Add the profile list ++ // XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) ++ // YY => SSID Length ++ // SSID => SSID for persistence group ++ ++ DBG_871X( "[%s] In value = %s, len = %d \n", __FUNCTION__, extra, wrqu->data.length -1); ++ ++ ++ // The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ if ( extra[ 0 ] == '0' ) ++ { ++ // Remove all the profile information of wifidirect_info structure. ++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); ++ pwdinfo->profileindex = 0; ++ } ++ else ++ { ++ if ( pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM ) ++ { ++ ret = -1; ++ } ++ else ++ { ++ int jj, kk; ++ ++ // Add this profile information into pwdinfo->profileinfo ++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID ++ for( jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ pwdinfo->profileinfo[ pwdinfo->profileindex ].peermac[ jj ] = key_2char2num(extra[ kk ], extra[ kk+ 1 ]); ++ } ++ ++ //pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[ 19 ] - '0' ); ++ //_rtw_memcpy( pwdinfo->profileinfo[ pwdinfo->profileindex ].ssid, &extra[ 20 ], pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen ); ++ pwdinfo->profileindex++; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_setDN(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); ++ _rtw_memcpy( pwdinfo->device_name, extra, wrqu->data.length - 1 ); ++ pwdinfo->device_name_len = wrqu->data.length - 1; ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_status(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif ++ ++ if ( padapter->bShowGetP2PState ) ++ { ++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ } ++ ++ // Commented by Albert 2010/10/12 ++ // Because of the output size limitation, I had removed the "Role" information. ++ // About the "Role" information, we will use the new private IOCTL to get the "Role" information. ++ sprintf( extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo) ); ++ wrqu->data.length = strlen( extra ); ++ ++ return ret; ++ ++} ++ ++// Commented by Albert 20110520 ++// This function will return the config method description ++// This config method description will show us which config method the remote P2P device is intented to use ++// by sending the provisioning discovery request frame. ++ ++static int rtw_p2p_get_req_cm(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_role(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ ++ sprintf( extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo) ); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ ++ sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_peer_devaddr(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); ++ sprintf( extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ], ++ pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ], ++ pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]); ++ sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", ++ pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ], ++ pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ], ++ pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_groupid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", ++ pwdinfo->groupid_info.go_device_addr[ 0 ], pwdinfo->groupid_info.go_device_addr[ 1 ], ++ pwdinfo->groupid_info.go_device_addr[ 2 ], pwdinfo->groupid_info.go_device_addr[ 3 ], ++ pwdinfo->groupid_info.go_device_addr[ 4 ], pwdinfo->groupid_info.go_device_addr[ 5 ], ++ pwdinfo->groupid_info.ssid); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_op_ch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X( "[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel); ++ ++ sprintf( extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel ); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++inline static void macstr2num(u8 *dst, u8 *src) ++{ ++ int jj, kk; ++ for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) ++ { ++ dst[jj] = key_2char2num(src[kk], src[kk + 1]); ++ } ++} ++ ++static int rtw_p2p_get_wps_configmethod(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra, char *subcmd) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 peerMAC[ETH_ALEN] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list * plist,*phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u16 attr_content = 0; ++ uint attr_contentlen = 0; ++ u8 attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; ++ ++ // Commented by Albert 20110727 ++ // The input data is the MAC address which the application wants to know its WPS config method. ++ // After knowing its WPS config method, the application can decide the config method for provisioning discovery. ++ // Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); ++ ++ macstr2num(peerMAC, subcmd); ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) ++ { ++ u8 *wpsie; ++ uint wpsie_len = 0; ++ ++ // The mac address is matched. ++ ++ if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) ++ { ++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen); ++ if (attr_contentlen) ++ { ++ attr_content = be16_to_cpu(attr_content); ++ sprintf(attr_content_str, "\n\nM=%.4d", attr_content); ++ blnMatch = 1; ++ } ++ } ++ ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if (!blnMatch) ++ { ++ sprintf(attr_content_str, "\n\nM=0000"); ++ } ++ ++ wrqu->data.length = strlen(attr_content_str); ++ _rtw_memcpy(extra, attr_content_str, wrqu->data.length); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_WFD ++static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ DBG_871X( "[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ ++ sprintf( extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ DBG_871X( "[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); ++ ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc ); ++ DBG_871X( "[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc ); ++ ++ wrqu->data.length = strlen( extra ); ++ pwdinfo->wfd_info->wfd_pc = _FALSE; // Reset the WFD preferred connection to P2P ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail ); ++ DBG_871X( "[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail ); ++ ++ wrqu->data.length = strlen( extra ); ++ pwdinfo->wfd_info->peer_session_avail = _TRUE; // Reset the WFD session available ++ return ret; ++ ++} ++ ++#endif // CONFIG_WFD ++ ++static int rtw_p2p_get_go_device_address(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra, char *subcmd) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 peerMAC[ETH_ALEN] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ u8 attr_content[100] = { 0x00 }; ++ u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; ++ ++ // Commented by Albert 20121209 ++ // The input data is the GO's interface address which the application wants to know its device address. ++ // Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); ++ ++ macstr2num(peerMAC, subcmd); ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) ++ { ++ // Commented by Albert 2011/05/18 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if ((p2pie = rtw_get_p2p_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &p2pielen, pnetwork->network.Reserved[0]))) ++ { ++ while (p2pie) ++ { ++ // The P2P Device ID attribute is included in the Beacon frame. ++ // The P2P Device Info attribute is included in the probe response frame. ++ ++ _rtw_memset(attr_content, 0x00, 100); ++ if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) ++ { ++ // Handle the P2P Device ID attribute of Beacon first ++ blnMatch = 1; ++ break; ++ ++ } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) ++ { ++ // Handle the P2P Device Info attribute of probe response ++ blnMatch = 1; ++ break; ++ } ++ ++ //Get the next P2P IE ++ p2pie = rtw_get_p2p_ie(p2pie + p2pielen, pnetwork->network.IELength - 12 - (p2pie - &pnetwork->network.IEs[12] + p2pielen), NULL, &p2pielen); ++ } ++ } ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if (!blnMatch) ++ { ++ sprintf(go_devadd_str, "\n\ndev_add=NULL"); ++ } else ++ { ++ sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X", ++ attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); ++ } ++ ++ wrqu->data.length = strlen(go_devadd_str); ++ _rtw_memcpy(extra, go_devadd_str, wrqu->data.length); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_device_type(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra, char *subcmd) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 peerMAC[ETH_ALEN] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u8 dev_type[8] = { 0x00 }; ++ uint dev_type_len = 0; ++ u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; // +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer ++ ++ // Commented by Albert 20121209 ++ // The input data is the MAC address which the application wants to know its device type. ++ // Such user interface could know the device type. ++ // Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); ++ ++ macstr2num(peerMAC, subcmd); ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) ++ { ++ u8 *wpsie; ++ uint wpsie_len = 0; ++ ++ // The mac address is matched. ++ ++ if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) ++ { ++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len); ++ if (dev_type_len) ++ { ++ u16 type = 0; ++ ++ _rtw_memcpy(&type, dev_type, 2); ++ type = be16_to_cpu(type); ++ sprintf(dev_type_str, "\n\nN=%.2d", type); ++ blnMatch = 1; ++ } ++ } ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if (!blnMatch) ++ { ++ sprintf(dev_type_str, "\n\nN=00"); ++ } ++ ++ wrqu->data.length = strlen(dev_type_str); ++ _rtw_memcpy(extra, dev_type_str, wrqu->data.length); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_device_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra, char *subcmd) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 peerMAC[ETH_ALEN] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 }; ++ uint dev_len = 0; ++ u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; ++ ++ // Commented by Albert 20121225 ++ // The input data is the MAC address which the application wants to know its device name. ++ // Such user interface could show peer device's device name instead of ssid. ++ // Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); ++ ++ macstr2num(peerMAC, subcmd); ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) ++ { ++ u8 *wpsie; ++ uint wpsie_len = 0; ++ ++ // The mac address is matched. ++ ++ if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) ++ { ++ rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len); ++ if (dev_len) ++ { ++ sprintf(dev_name_str, "\n\nN=%s", dev_name); ++ blnMatch = 1; ++ } ++ } ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if (!blnMatch) ++ { ++ sprintf(dev_name_str, "\n\nN=0000"); ++ } ++ ++ wrqu->data.length = strlen(dev_name_str); ++ _rtw_memcpy(extra, dev_name_str, wrqu->data.length); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_invitation_procedure(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra, char *subcmd) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 peerMAC[ETH_ALEN] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ u8 attr_content[2] = { 0x00 }; ++ u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; ++ ++ // Commented by Ouden 20121226 ++ // The application wants to know P2P initation procedure is support or not. ++ // Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); ++ ++ macstr2num(peerMAC, subcmd); ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) ++ { ++ // Commented by Albert 20121226 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if ((p2pie = rtw_get_p2p_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &p2pielen, pnetwork->network.Reserved[0]))) ++ { ++ while (p2pie) ++ { ++ //_rtw_memset( attr_content, 0x00, 2); ++ if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) ++ { ++ // Handle the P2P capability attribute ++ blnMatch = 1; ++ break; ++ ++ } ++ ++ //Get the next P2P IE ++ p2pie = rtw_get_p2p_ie(p2pie + p2pielen, pnetwork->network.IELength - 12 - (p2pie - &pnetwork->network.IEs[12] + p2pielen), NULL, &p2pielen); ++ } ++ } ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if (!blnMatch) ++ { ++ sprintf(inv_proc_str, "\nIP=-1"); ++ } else ++ { ++ if (attr_content[0] && 0x20) ++ { ++ sprintf(inv_proc_str, "\nIP=1"); ++ } else ++ { ++ sprintf(inv_proc_str, "\nIP=0"); ++ } ++ } ++ ++ wrqu->data.length = strlen(inv_proc_str); ++ _rtw_memcpy(extra, inv_proc_str, wrqu->data.length); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_connect(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif // CONFIG_CONCURRENT_MODE ++ ++ // Commented by Albert 20110304 ++ // The input data contains two informations. ++ // 1. First information is the MAC address which wants to formate with ++ // 2. Second information is the WPS PINCode or "pbc" string for push button method ++ // Format: 00:E0:4C:00:00:05 ++ // Format: 00:E0:4C:00:00:05 ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if ( pwdinfo->p2p_state == P2P_STATE_NONE ) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO ) ++ { ++ return -1; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( uintPeerChannel ) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++ ++ pwdinfo->nego_req_info.peer_channel_num[ 0 ] = uintPeerChannel; ++ _rtw_memcpy( pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN ); ++ pwdinfo->nego_req_info.benable = _TRUE; ++ ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ if ( rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK ) ++ { ++ // Restore to the listen state if the current p2p state is not nego OK ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN ); ++ } ++ ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ // Have to enter the power saving with the AP ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ DBG_871X( "[%s] Start PreTx Procedure!\n", __FUNCTION__ ); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT ); ++ } ++ else ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT ); ++ } ++#else ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT ); ++#endif // CONFIG_CONCURRENT_MODE ++ ++ } ++ else ++ { ++ DBG_871X( "[%s] Not Found in Scanning Queue~\n", __FUNCTION__ ); ++ ret = -1; ++ } ++exit: ++ return ret; ++} ++ ++static int rtw_p2p_invite_req(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++ u8 attr_content[50] = { 0x00 }, _status = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ _irqL irqL; ++ struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif // CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_WFD ++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; ++#endif // CONFIG_WFD ++ ++ // Commented by Albert 20120321 ++ // The input data contains two informations. ++ // 1. First information is the P2P device address which you want to send to. ++ // 2. Second information is the group id which combines with GO's mac address, space and GO's ssid. ++ // Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" ++ // Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if ( wrqu->data.length <= 37 ) ++ { ++ DBG_871X( "[%s] Wrong format!\n", __FUNCTION__ ); ++ return ret; ++ } ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ else ++ { ++ // Reset the content of struct tx_invite_req_info ++ pinvite_req_info->benable = _FALSE; ++ _rtw_memset( pinvite_req_info->go_bssid, 0x00, ETH_ALEN ); ++ _rtw_memset( pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN ); ++ pinvite_req_info->ssidlen = 0x00; ++ pinvite_req_info->operating_ch = pwdinfo->operating_channel; ++ _rtw_memset( pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN ); ++ pinvite_req_info->token = 3; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ pinvite_req_info->peer_macaddr[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ // Commented by Albert 2011/05/18 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if ( (p2pie=rtw_get_p2p_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &p2pielen, pnetwork->network.Reserved[0]))) ++ { ++ // The P2P Device ID attribute is included in the Beacon frame. ++ // The P2P Device Info attribute is included in the probe response frame. ++ ++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device ID attribute of Beacon first ++ if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device Info attribute of probe response ++ if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++#ifdef CONFIG_WFD ++ if ( uintPeerChannel ) ++ { ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ uint wfd_ielen = 0; ++ ++ if ( rtw_get_wfd_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, wfd_ie, &wfd_ielen, pnetwork->network.Reserved[0]) ) ++ { ++ u8 wfd_devinfo[ 6 ] = { 0x00 }; ++ uint wfd_devlen = 6; ++ ++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); ++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) ) ++ { ++ u16 wfd_devinfo_field = 0; ++ ++ // Commented by Albert 20120319 ++ // The first two bytes are the WFD device information field of WFD device information subelement. ++ // In big endian format. ++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); ++ if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL ) ++ { ++ pwfd_info->peer_session_avail = _TRUE; ++ } ++ else ++ { ++ pwfd_info->peer_session_avail = _FALSE; ++ } ++ } ++ } ++ ++ if ( _FALSE == pwfd_info->peer_session_avail ) ++ { ++ DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ ); ++ goto exit; ++ } ++ } ++#endif // CONFIG_WFD ++ ++ if ( uintPeerChannel ) ++ { ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ ++ // Store the GO's bssid ++ for( jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ pinvite_req_info->go_bssid[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ // Store the GO's ssid ++ pinvite_req_info->ssidlen = wrqu->data.length - 36; ++ _rtw_memcpy( pinvite_req_info->go_ssid, &extra[ 36 ], (u32) pinvite_req_info->ssidlen ); ++ pinvite_req_info->benable = _TRUE; ++ pinvite_req_info->peer_ch = uintPeerChannel; ++ ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ // Have to enter the power saving with the AP ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); ++ } ++ else ++ { ++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++#else ++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++#endif ++ ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT ); ++ } ++ else ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT ); ++ } ++#else ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT ); ++#endif // CONFIG_CONCURRENT_MODE ++ ++ ++ } ++ else ++ { ++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); ++ } ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_persistent(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++ u8 attr_content[50] = { 0x00 }, _status = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ _irqL irqL; ++ struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif // CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_WFD ++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; ++#endif // CONFIG_WFD ++ ++ // Commented by Albert 20120328 ++ // The input data is 0 or 1 ++ // 0: disable persistent group functionality ++ // 1: enable persistent group founctionality ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ else ++ { ++ if ( extra[ 0 ] == '0' ) // Disable the persistent group function. ++ { ++ pwdinfo->persistent_supported = _FALSE; ++ } ++ else if ( extra[ 0 ] == '1' ) // Enable the persistent group function. ++ { ++ pwdinfo->persistent_supported = _TRUE; ++ } ++ else ++ { ++ pwdinfo->persistent_supported = _FALSE; ++ } ++ } ++ printk( "[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported ); ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int hexstr2bin(const char *hex, u8 *buf, size_t len) ++{ ++ size_t i; ++ int a; ++ const char *ipos = hex; ++ u8 *opos = buf; ++ ++ for (i = 0; i < len; i++) { ++ a = hex2byte_i(ipos); ++ if (a < 0) ++ return -1; ++ *opos++ = a; ++ ipos += 2; ++ } ++ return 0; ++} ++ ++static int uuid_str2bin(const char *str, u8 *bin) ++{ ++ const char *pos; ++ u8 *opos; ++ ++ pos = str; ++ opos = bin; ++ ++ if (hexstr2bin(pos, opos, 4)) ++ return -1; ++ pos += 8; ++ opos += 4; ++ ++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) ++ return -1; ++ pos += 4; ++ opos += 2; ++ ++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) ++ return -1; ++ pos += 4; ++ opos += 2; ++ ++ if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) ++ return -1; ++ pos += 4; ++ opos += 2; ++ ++ if (*pos++ != '-' || hexstr2bin(pos, opos, 6)) ++ return -1; ++ ++ return 0; ++} ++ ++static int rtw_p2p_set_wps_uuid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ ++ DBG_871X("[%s] data = %s\n", __FUNCTION__, extra); ++ ++ if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0)) ++ { ++ pwdinfo->external_uuid = 1; ++ } else { ++ pwdinfo->external_uuid = 0; ++ ret = -EINVAL; ++ } ++ ++ return ret; ++ ++} ++#ifdef CONFIG_WFD ++static int rtw_p2p_set_pc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 attr_content[50] = { 0x00 }, _status = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ _irqL irqL; ++ uint uintPeerChannel = 0; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif // CONFIG_CONCURRENT_MODE ++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; ++ ++ // Commented by Albert 20120512 ++ // 1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) ++ // Format: 00:E0:4C:00:00:05 ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ // Commented by Albert 2011/05/18 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if ( (p2pie=rtw_get_p2p_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &p2pielen, pnetwork->network.Reserved[0]))) ++ { ++ // The P2P Device ID attribute is included in the Beacon frame. ++ // The P2P Device Info attribute is included in the probe response frame. ++ printk( "[%s] Got P2P IE\n", __FUNCTION__ ); ++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device ID attribute of Beacon first ++ printk( "[%s] P2P_ATTR_DEVICE_ID \n", __FUNCTION__ ); ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device Info attribute of probe response ++ printk( "[%s] P2P_ATTR_DEVICE_INFO \n", __FUNCTION__ ); ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ printk( "[%s] channel = %d\n", __FUNCTION__, uintPeerChannel ); ++ ++ if ( uintPeerChannel ) ++ { ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ uint wfd_ielen = 0; ++ ++ if ( rtw_get_wfd_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, wfd_ie, &wfd_ielen, pnetwork->network.Reserved[0]) ) ++ { ++ u8 wfd_devinfo[ 6 ] = { 0x00 }; ++ uint wfd_devlen = 6; ++ ++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); ++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) ) ++ { ++ u16 wfd_devinfo_field = 0; ++ ++ // Commented by Albert 20120319 ++ // The first two bytes are the WFD device information field of WFD device information subelement. ++ // In big endian format. ++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); ++ if ( wfd_devinfo_field & WFD_DEVINFO_PC_TDLS ) ++ { ++ pwfd_info->wfd_pc = _TRUE; ++ } ++ else ++ { ++ pwfd_info->wfd_pc = _FALSE; ++ } ++ } ++ } ++ } ++ else ++ { ++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_wfd_device_type(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; ++ ++ // Commented by Albert 20120328 ++ // The input data is 0 or 1 ++ // 0: specify to Miracast source device ++ // 1 or others: specify to Miracast sink device (display device) ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if ( extra[ 0 ] == '0' ) // Set to Miracast source device. ++ { ++ pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE; ++ } ++ else // Set to Miracast sink device. ++ { ++ pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_scan_result_type(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; ++ ++ // Commented by Albert 20120328 ++ // The input data is 0 , 1 , 2 ++ // 0: when the P2P is enabled, the scan result will return all the found P2P device. ++ // 1: when the P2P is enabled, the scan result will return all the found P2P device and AP. ++ // 2: when the P2P is enabled, the scan result will show up the found Miracast devices base on... ++ // It will show up all the Miracast source device if this device is sink. ++ // It will show up all the Miracast sink device if this device is source. ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if ( extra[ 0 ] == '0' ) ++ { ++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY; ++ } ++ else if ( extra[ 0 ] == '1' ) ++ { ++ pwfd_info->scan_result_type = SCAN_RESULT_ALL; ++ } ++ else if ( extra[ 0 ] == '2' ) ++ { ++ pwfd_info->scan_result_type = SCAN_RESULT_WFD_TYPE; ++ } ++ else ++ { ++ pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY; ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_wfd_enable(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++// Commented by Kurt 20121206 ++// This function is used to set wfd enabled ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ if(*extra == '0' ) ++ pwdinfo->wfd_info->wfd_enable = _FALSE; ++ else if(*extra == '1') ++ pwdinfo->wfd_info->wfd_enable = _TRUE; ++ ++ DBG_871X( "[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable ); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_driver_iface(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++// Commented by Kurt 20121206 ++// This function is used to set driver iface is WEXT or CFG80211 ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ if(*extra == '1' ) ++ { ++ pwdinfo->driver_interface = DRIVER_WEXT; ++ DBG_871X( "[%s] driver_interface = WEXT\n", __FUNCTION__); ++ } ++ else if(*extra == '2') ++ { ++ pwdinfo->driver_interface = DRIVER_CFG80211; ++ DBG_871X( "[%s] driver_interface = CFG80211\n", __FUNCTION__); ++ } ++ ++ return ret; ++ ++} ++ ++// To set the WFD session available to enable or disable ++static int rtw_p2p_set_sa(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if( 0 ) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ else ++ { ++ if ( extra[ 0 ] == '0' ) // Disable the session available. ++ { ++ pwdinfo->session_available = _FALSE; ++ } ++ else if ( extra[ 0 ] == '1' ) // Enable the session available. ++ { ++ pwdinfo->session_available = _TRUE; ++ } ++ else ++ { ++ pwdinfo->session_available = _FALSE; ++ } ++ } ++ printk( "[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available ); ++ ++exit: ++ ++ return ret; ++ ++} ++#endif // CONFIG_WFD ++ ++static int rtw_p2p_prov_disc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++ u8 attr_content[100] = { 0x00 }, _status = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ _irqL irqL; ++ u8 ie_offset; ++#ifdef CONFIG_CONCURRENT_MODE ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; ++ struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; ++#endif // CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_WFD ++ struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; ++#endif // CONFIG_WFD ++ ++ // Commented by Albert 20110301 ++ // The input data contains two informations. ++ // 1. First information is the MAC address which wants to issue the provisioning discovery request frame. ++ // 2. Second information is the WPS configuration method which wants to discovery ++ // Format: 00:E0:4C:00:00:05_display ++ // Format: 00:E0:4C:00:00:05_keypad ++ // Format: 00:E0:4C:00:00:05_pbc ++ // Format: 00:E0:4C:00:00:05_label ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if ( pwdinfo->p2p_state == P2P_STATE_NONE ) ++ { ++ DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ else ++ { ++#ifdef CONFIG_INTEL_WIDI ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE){ ++ DBG_871X( "[%s] WiFi is under survey!\n", __FUNCTION__ ); ++ return ret; ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++ // Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. ++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN ); ++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN ); ++ _rtw_memset( &pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof( NDIS_802_11_SSID ) ); ++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 0 ] = 0; ++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 1 ] = 0; ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ if ( _rtw_memcmp( &extra[ 18 ], "display", 7 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "keypad", 7 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "pbc", 3 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "label", 5 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; ++ } ++ else ++ { ++ DBG_871X( "[%s] Unknown WPS config methodn", __FUNCTION__ ); ++ return( ret ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ if( uintPeerChannel != 0 ) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ // Commented by Albert 2011/05/18 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if (pnetwork->network.Reserved[0] == 2) { // Probe Request ++ ie_offset = 0; ++ } else { // Beacon or Probe Respones ++ ie_offset = 12; ++ } ++ if ( (p2pie=rtw_get_p2p_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &p2pielen, pnetwork->network.Reserved[0]))) ++ { ++ while ( p2pie ) ++ { ++ // The P2P Device ID attribute is included in the Beacon frame. ++ // The P2P Device Info attribute is included in the probe response frame. ++ ++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device ID attribute of Beacon first ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device Info attribute of probe response ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ ++ //Get the next P2P IE ++ p2pie = rtw_get_p2p_ie(p2pie+p2pielen, pnetwork->network.IELength - ie_offset -(p2pie -&pnetwork->network.IEs[ie_offset] + p2pielen), NULL, &p2pielen); ++ } ++ } ++ ++#ifdef CONFIG_INTEL_WIDI ++ // Some Intel WiDi source may not provide P2P IE, ++ // so we could only compare mac addr by 802.11 Source Address ++ if( pmlmepriv->widi_state == INTEL_WIDI_STATE_WFD_CONNECTION ++ && uintPeerChannel == 0 ) ++ { ++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( uintPeerChannel ) ++ { ++#ifdef CONFIG_WFD ++ { ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ uint wfd_ielen = 0; ++ ++ if ( rtw_get_wfd_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, wfd_ie, &wfd_ielen, pnetwork->network.Reserved[0]) ) ++ { ++ u8 wfd_devinfo[ 6 ] = { 0x00 }; ++ uint wfd_devlen = 6; ++ ++ DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); ++ if ( rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, wfd_devinfo, &wfd_devlen ) ) ++ { ++ u16 wfd_devinfo_field = 0; ++ ++ // Commented by Albert 20120319 ++ // The first two bytes are the WFD device information field of WFD device information subelement. ++ // In big endian format. ++ wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); ++ if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL ) ++ { ++ pwfd_info->peer_session_avail = _TRUE; ++ } ++ else ++ { ++ pwfd_info->peer_session_avail = _FALSE; ++ } ++ } ++ } ++ ++ if ( _FALSE == pwfd_info->peer_session_avail ) ++ { ++ DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ ); ++ goto exit; ++ } ++ } ++#endif // CONFIG_WFD ++ ++ DBG_871X( "[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel ); ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); ++ } ++#endif // CONFIG_CONCURRENT_MODE ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN ); ++ pwdinfo->tx_prov_disc_info.peer_channel_num[0] = ( u16 ) uintPeerChannel; ++ pwdinfo->tx_prov_disc_info.benable = _TRUE; ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) ++ { ++ _rtw_memcpy( &pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof( NDIS_802_11_SSID ) ); ++ } ++ else if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); ++ pwdinfo->tx_prov_disc_info.ssid.SsidLength= P2P_WILDCARD_SSID_LEN; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ // Have to enter the power saving with the AP ++ set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); ++ ++ issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); ++ } ++ else ++ { ++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++#else ++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++#endif ++ ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT ); ++ } ++ else ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++ } ++#else ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++#endif // CONFIG_CONCURRENT_MODE ++ ++ } ++ else ++ { ++ DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); ++#ifdef CONFIG_INTEL_WIDI ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); ++ rtw_free_network_queue(padapter, _TRUE); ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++#endif //CONFIG_INTEL_WIDI ++ } ++exit: ++ ++ return ret; ++ ++} ++ ++// Added by Albert 20110328 ++// This function is used to inform the driver the user had specified the pin code value or pbc ++// to application. ++ ++static int rtw_p2p_got_wpsinfo(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); ++ // Added by Albert 20110328 ++ // if the input data is P2P_NO_WPSINFO -> reset the wpsinfo ++ // if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. ++ // if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. ++ // if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC ++ ++ if ( *extra == '0' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++ } ++ else if ( *extra == '1' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN; ++ } ++ else if ( *extra == '2' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN; ++ } ++ else if ( *extra == '3' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC; ++ } ++ else ++ { ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++ } ++ ++ return ret; ++ ++} ++ ++#endif //CONFIG_P2P ++ ++static int rtw_p2p_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++#ifdef CONFIG_P2P ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ ++ if ( _rtw_memcmp( extra, "enable=", 7 ) ) ++ { ++ rtw_wext_p2p_enable( dev, info, wrqu, &extra[7] ); ++ } ++ else if ( _rtw_memcmp( extra, "setDN=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_p2p_setDN( dev, info, wrqu, &extra[6] ); ++ } ++ else if ( _rtw_memcmp( extra, "profilefound=", 13 ) ) ++ { ++ wrqu->data.length -= 13; ++ rtw_p2p_profilefound( dev, info, wrqu, &extra[13] ); ++ } ++ else if ( _rtw_memcmp( extra, "prov_disc=", 10 ) ) ++ { ++ wrqu->data.length -= 10; ++ rtw_p2p_prov_disc( dev, info, wrqu, &extra[10] ); ++ } ++ else if ( _rtw_memcmp( extra, "nego=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_p2p_connect( dev, info, wrqu, &extra[5] ); ++ } ++ else if ( _rtw_memcmp( extra, "intent=", 7 ) ) ++ { ++ // Commented by Albert 2011/03/23 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease 7 + 1 ++ wrqu->data.length -= 8; ++ rtw_p2p_set_intent( dev, info, wrqu, &extra[7] ); ++ } ++ else if ( _rtw_memcmp( extra, "ssid=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_p2p_set_go_nego_ssid( dev, info, wrqu, &extra[5] ); ++ } ++ else if ( _rtw_memcmp( extra, "got_wpsinfo=", 12 ) ) ++ { ++ wrqu->data.length -= 12; ++ rtw_p2p_got_wpsinfo( dev, info, wrqu, &extra[12] ); ++ } ++ else if ( _rtw_memcmp( extra, "listen_ch=", 10 ) ) ++ { ++ // Commented by Albert 2011/05/24 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease (10 + 1) ++ wrqu->data.length -= 11; ++ rtw_p2p_set_listen_ch( dev, info, wrqu, &extra[10] ); ++ } ++ else if ( _rtw_memcmp( extra, "op_ch=", 6 ) ) ++ { ++ // Commented by Albert 2011/05/24 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease (6 + 1) ++ wrqu->data.length -= 7; ++ rtw_p2p_set_op_ch( dev, info, wrqu, &extra[6] ); ++ } ++ else if ( _rtw_memcmp( extra, "invite=", 7 ) ) ++ { ++ wrqu->data.length -= 8; ++ rtw_p2p_invite_req( dev, info, wrqu, &extra[7] ); ++ } ++ else if ( _rtw_memcmp( extra, "persistent=", 11 ) ) ++ { ++ wrqu->data.length -= 11; ++ rtw_p2p_set_persistent( dev, info, wrqu, &extra[11] ); ++ } ++ else if ( _rtw_memcmp ( extra, "uuid=", 5) ) ++ { ++ wrqu->data.length -= 5; ++ ret = rtw_p2p_set_wps_uuid( dev, info, wrqu, &extra[5] ); ++ } ++#ifdef CONFIG_WFD ++ else if ( _rtw_memcmp( extra, "sa=", 3 ) ) ++ { ++ // sa: WFD Session Available information ++ wrqu->data.length -= 3; ++ rtw_p2p_set_sa( dev, info, wrqu, &extra[3] ); ++ } ++ else if ( _rtw_memcmp( extra, "pc=", 3 ) ) ++ { ++ // pc: WFD Preferred Connection ++ wrqu->data.length -= 3; ++ rtw_p2p_set_pc( dev, info, wrqu, &extra[3] ); ++ } ++ else if ( _rtw_memcmp( extra, "wfd_type=", 9 ) ) ++ { ++ // Specify this device is Mircast source or sink ++ wrqu->data.length -= 9; ++ rtw_p2p_set_wfd_device_type( dev, info, wrqu, &extra[9] ); ++ } ++ else if ( _rtw_memcmp( extra, "scan_type=", 10 ) ) ++ { ++ wrqu->data.length -= 10; ++ rtw_p2p_set_scan_result_type( dev, info, wrqu, &extra[10] ); ++ } ++ else if ( _rtw_memcmp( extra, "wfd_enable=", 11 ) ) ++ { ++ wrqu->data.length -= 11; ++ rtw_p2p_set_wfd_enable( dev, info, wrqu, &extra[11] ); ++ } ++ else if ( _rtw_memcmp( extra, "driver_iface=", 13 ) ) ++ { ++ wrqu->data.length -= 13; ++ rtw_p2p_set_driver_iface( dev, info, wrqu, &extra[13] ); ++ } ++#endif //CONFIG_WFD ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_P2P ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if ( padapter->bShowGetP2PState ) ++ { ++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); ++ } ++ ++ if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) ) ++ { ++ rtw_p2p_get_status( dev, info, wrqu, extra ); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "role", 4 ) ) ++ { ++ rtw_p2p_get_role( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_ifa", 8 ) ) ++ { ++ rtw_p2p_get_peer_ifaddr( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "req_cm", 6 ) ) ++ { ++ rtw_p2p_get_req_cm( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_deva", 9 ) ) ++ { ++ // Get the P2P device address when receiving the provision discovery request frame. ++ rtw_p2p_get_peer_devaddr( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "group_id", 8 ) ) ++ { ++ rtw_p2p_get_groupid( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "inv_peer_deva", 13 ) ) ++ { ++ // Get the P2P device address when receiving the P2P Invitation request frame. ++ rtw_p2p_get_peer_devaddr_by_invitation( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "op_ch", 5 ) ) ++ { ++ rtw_p2p_get_op_ch( dev, info, wrqu, extra); ++ } ++#ifdef CONFIG_WFD ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_port", 9 ) ) ++ { ++ rtw_p2p_get_peer_wfd_port( dev, info, wrqu, extra ); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "wfd_sa", 6 ) ) ++ { ++ rtw_p2p_get_peer_wfd_session_available( dev, info, wrqu, extra ); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "wfd_pc", 6 ) ) ++ { ++ rtw_p2p_get_peer_wfd_preferred_connection( dev, info, wrqu, extra ); ++ } ++#endif // CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get2(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_P2P ++ ++ int length = wrqu->data.length; ++ char *buffer = (u8 *)rtw_malloc(length); ++ ++ if (buffer == NULL) ++ { ++ ret = -ENOMEM; ++ goto bad; ++ } ++ ++ if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) ++ { ++ ret - EFAULT; ++ goto bad; ++ } ++ ++ DBG_871X("[%s] buffer = %s\n", __FUNCTION__, buffer); ++ ++ if (_rtw_memcmp(buffer, "wpsCM=", 6)) ++ { ++ ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]); ++ } else if (_rtw_memcmp(buffer, "devN=", 5)) ++ { ++ ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]); ++ } else if (_rtw_memcmp(buffer, "dev_type=", 9)) ++ { ++ ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]); ++ } else if (_rtw_memcmp(buffer, "go_devadd=", 10)) ++ { ++ ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]); ++ } else if (_rtw_memcmp(buffer, "InvProc=", 8)) ++ { ++ ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]); ++ } else ++ { ++ snprintf(extra, sizeof("Command not found."), "Command not found."); ++ wrqu->data.length = strlen(extra); ++ } ++ ++bad: ++ if (buffer) ++ { ++ rtw_mfree(buffer, length); ++ } ++ ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++static int rtw_cta_test_start(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ DBG_871X("%s %s\n", __func__, extra); ++ if (!strcmp(extra, "1")) ++ padapter->in_cta_test = 1; ++ else ++ padapter->in_cta_test = 0; ++ ++ if(padapter->in_cta_test) ++ { ++ u32 v = rtw_read32(padapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(padapter, REG_RCR, v); ++ DBG_871X("enable RCR_ADF\n"); ++ } ++ else ++ { ++ u32 v = rtw_read32(padapter, REG_RCR); ++ v |= RCR_CBSSID_DATA | RCR_CBSSID_BCN ;//| RCR_ADF ++ rtw_write32(padapter, REG_RCR, v); ++ DBG_871X("disable RCR_ADF\n"); ++ } ++ return ret; ++} ++ ++ ++extern int rtw_change_ifname(_adapter *padapter, const char *ifname); ++static int rtw_rereg_nd_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; ++ char new_ifname[IFNAMSIZ]; ++ ++ if(rereg_priv->old_ifname[0] == 0) { ++ char *reg_ifname; ++#ifdef CONFIG_CONCURRENT_MODE ++ if (padapter->isprimary) ++ reg_ifname = padapter->registrypriv.ifname; ++ else ++#endif ++ reg_ifname = padapter->registrypriv.if2name; ++ ++ strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); ++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0; ++ } ++ ++ //DBG_871X("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); ++ if(wrqu->data.length > IFNAMSIZ) ++ return -EFAULT; ++ ++ if ( copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ) ) { ++ return -EFAULT; ++ } ++ ++ if( 0 == strcmp(rereg_priv->old_ifname, new_ifname) ) { ++ return ret; ++ } ++ ++ DBG_871X("%s new_ifname:%s\n", __FUNCTION__, new_ifname); ++ if( 0 != (ret = rtw_change_ifname(padapter, new_ifname)) ) { ++ goto exit; ++ } ++ ++ if(_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { ++ padapter->ledpriv.bRegUseLed= rereg_priv->old_bRegUseLed; ++ rtw_hal_sw_led_init(padapter); ++ /* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */ ++ } ++ ++ strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); ++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0; ++ ++ if(_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) { ++ ++ DBG_871X("%s disable\n", __FUNCTION__); ++ // free network queue for Android's timming issue ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ // close led ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; ++ padapter->ledpriv.bRegUseLed= _FALSE; ++ rtw_hal_sw_led_deinit(padapter); ++ ++ /* ++ // the interface is being "disabled", we can do deeper IPS ++ rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); ++ rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); ++ */ ++ } ++exit: ++ return ret; ++ ++} ++ ++#if 0 ++void mac_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_871X("\n======= MAC REG =======\n"); ++ for(i=0x0;i<0x300;i+=4) ++ { ++ if(j%4==1) DBG_871X("0x%02x",i); ++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_871X("\n"); ++ } ++ for(i=0x400;i<0x800;i+=4) ++ { ++ if(j%4==1) DBG_871X("0x%02x",i); ++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_871X("\n"); ++ } ++} ++void bb_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_871X("\n======= BB REG =======\n"); ++ for(i=0x800;i<0x1000;i+=4) ++ { ++ if(j%4==1) DBG_871X("0x%02x",i); ++ ++ DBG_871X(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_871X("\n"); ++ } ++} ++void rf_reg_dump(_adapter *padapter) ++{ ++ int i,j=1,path; ++ u32 value; ++ DBG_871X("\n======= RF REG =======\n"); ++ for(path=0;path<2;path++) ++ { ++ DBG_871X("\nRF_Path(%x)\n",path); ++ for(i=0;i<0x100;i++) ++ { ++ value = PHY_QueryRFReg(padapter, (RF_RADIO_PATH_E)path,i, bMaskDWord); ++ if(j%4==1) DBG_871X("0x%02x ",i); ++ DBG_871X(" 0x%08x ",value); ++ if((j++)%4==0) DBG_871X("\n"); ++ } ++ } ++} ++ ++#endif ++ ++void mac_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ printk("\n======= MAC REG =======\n"); ++ for(i=0x0;i<0x300;i+=4) ++ { ++ if(j%4==1) printk("0x%02x",i); ++ printk(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) printk("\n"); ++ } ++ for(i=0x400;i<0x800;i+=4) ++ { ++ if(j%4==1) printk("0x%02x",i); ++ printk(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) printk("\n"); ++ } ++} ++void bb_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ printk("\n======= BB REG =======\n"); ++ for(i=0x800;i<0x1000;i+=4) ++ { ++ if(j%4==1) printk("0x%02x",i); ++ ++ printk(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) printk("\n"); ++ } ++} ++void rf_reg_dump(_adapter *padapter) ++{ ++ int i,j=1,path; ++ u32 value; ++ u8 rf_type,path_nums = 0; ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ printk("\n======= RF REG =======\n"); ++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) ++ path_nums = 1; ++ else ++ path_nums = 2; ++ ++ for(path=0;path ++#endif ++static int rtw_dbg_port(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ int ret = 0; ++ u8 major_cmd, minor_cmd; ++ u16 arg; ++ u32 extra_arg, *pdata, val32; ++ struct sta_info *psta; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++ pdata = (u32*)&wrqu->data; ++ ++ val32 = *pdata; ++ arg = (u16)(val32&0x0000ffff); ++ major_cmd = (u8)(val32>>24); ++ minor_cmd = (u8)((val32>>16)&0x00ff); ++ ++ extra_arg = *(pdata+1); ++ ++ switch(major_cmd) ++ { ++ case 0x70://read_reg ++ switch(minor_cmd) ++ { ++ case 1: ++ DBG_871X("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); ++ break; ++ case 2: ++ DBG_871X("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); ++ break; ++ case 4: ++ DBG_871X("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); ++ break; ++ } ++ break; ++ case 0x71://write_reg ++ switch(minor_cmd) ++ { ++ case 1: ++ rtw_write8(padapter, arg, extra_arg); ++ DBG_871X("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); ++ break; ++ case 2: ++ rtw_write16(padapter, arg, extra_arg); ++ DBG_871X("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); ++ break; ++ case 4: ++ rtw_write32(padapter, arg, extra_arg); ++ DBG_871X("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); ++ break; ++ } ++ break; ++ case 0x72://read_bb ++ DBG_871X("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); ++ break; ++ case 0x73://write_bb ++ rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg); ++ DBG_871X("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); ++ break; ++ case 0x74://read_rf ++ DBG_871X("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg,rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); ++ break; ++ case 0x75://write_rf ++ rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg); ++ DBG_871X("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); ++ break; ++ ++ case 0x76: ++ switch(minor_cmd) ++ { ++ case 0x00: //normal mode, ++ padapter->recvpriv.is_signal_dbg = 0; ++ break; ++ case 0x01: //dbg mode ++ padapter->recvpriv.is_signal_dbg = 1; ++ extra_arg = extra_arg>100?100:extra_arg; ++ extra_arg = extra_arg<0?0:extra_arg; ++ padapter->recvpriv.signal_strength_dbg=extra_arg; ++ break; ++ } ++ break; ++ case 0x78: //IOL test ++ switch(minor_cmd) ++ { ++ #ifdef CONFIG_IOL ++ case 0x04: //LLT table initialization test ++ { ++ u8 page_boundary = 0xf9; ++ { ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary); ++ ++ ++ if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500,0) ) ++ ret = -EPERM; ++ } ++ } ++ break; ++ case 0x05: //blink LED test ++ { ++ u16 reg = 0x4c; ++ u32 blink_num = 50; ++ u32 blink_delay_ms = 200; ++ int i; ++ ++ { ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ for(i=0;inetwork.MacAddress ++ , WLAN_REASON_EXPIRATION_CHK); ++ break; ++ case 0x7F: ++ switch(minor_cmd) ++ { ++ case 0x0: ++ DBG_871X("fwstate=0x%x\n", get_fwstate(pmlmepriv)); ++ break; ++ case 0x01: ++ DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", ++ psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ break; ++ case 0x02: ++ DBG_871X("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); ++ break; ++ case 0x03: ++ DBG_871X("qos_option=%d\n", pmlmepriv->qospriv.qos_option); ++#ifdef CONFIG_80211N_HT ++ DBG_871X("ht_option=%d\n", pmlmepriv->htpriv.ht_option); ++#endif //CONFIG_80211N_HT ++ break; ++ case 0x04: ++ DBG_871X("cur_ch=%d\n", pmlmeext->cur_channel); ++ DBG_871X("cur_bw=%d\n", pmlmeext->cur_bwmode); ++ DBG_871X("cur_ch_off=%d\n", pmlmeext->cur_ch_offset); ++ break; ++ case 0x05: ++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(psta) ++ { ++ int i; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++ DBG_871X("SSID=%s\n", cur_network->network.Ssid.Ssid); ++ DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ DBG_871X("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++#ifdef CONFIG_80211N_HT ++ DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ DBG_871X("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++#endif //CONFIG_80211N_HT ++ ++ for(i=0;i<16;i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ if(preorder_ctrl->enable) ++ { ++ DBG_871X("tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ else ++ { ++ DBG_871X("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); ++ } ++ break; ++ case 0x06: ++ { ++ u32 ODMFlag; ++ rtw_hal_get_hwreg(padapter, HW_VAR_DM_FLAG, (u8*)(&ODMFlag)); ++ DBG_871X("(B)DMFlag=0x%x, arg=0x%x\n", ODMFlag, arg); ++ ODMFlag = (u32)(0x0f&arg); ++ DBG_871X("(A)DMFlag=0x%x\n", ODMFlag); ++ rtw_hal_set_hwreg(padapter, HW_VAR_DM_FLAG, (u8 *)(&ODMFlag)); ++ } ++ break; ++ case 0x07: ++ DBG_871X("bSurpriseRemoved=%d, bDriverStopped=%d\n", ++ padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ break; ++ case 0x08: ++ { ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ DBG_871X("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" ++ ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" ++ ", free_recvframe_cnt=%d\n", ++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, ++ pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, ++ precvpriv->free_recvframe_cnt); ++ #ifdef CONFIG_USB_HCI ++ DBG_871X("rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt); ++ #endif ++ } ++ break; ++ case 0x09: ++ { ++ int i, j; ++ _list *plist, *phead; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++#ifdef CONFIG_AP_MODE ++ DBG_871X("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); ++#endif ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ if(extra_arg == psta->aid) ++ { ++ DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++#ifdef CONFIG_80211N_HT ++ DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ DBG_871X("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++#endif //CONFIG_80211N_HT ++ ++#ifdef CONFIG_AP_MODE ++ DBG_871X("capability=0x%x\n", psta->capability); ++ DBG_871X("flags=0x%x\n", psta->flags); ++ DBG_871X("wpa_psk=0x%x\n", psta->wpa_psk); ++ DBG_871X("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); ++ DBG_871X("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); ++ DBG_871X("qos_info=0x%x\n", psta->qos_info); ++#endif ++ DBG_871X("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); ++ ++ ++ ++ for(j=0;j<16;j++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[j]; ++ if(preorder_ctrl->enable) ++ { ++ DBG_871X("tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ } ++ break; ++ case 0x0a: ++ { ++ #ifdef DBG_TRX_STA_PKTS ++ int i, j; ++ _list *plist, *phead; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ if(arg == 0xff){ ++ psta->rx_bk_cnt =0; ++ psta->rx_be_cnt =0; ++ psta->rx_vo_cnt =0; ++ psta->rx_vi_cnt =0; ++ psta->tx_bk_cnt =0; ++ psta->tx_be_cnt =0; ++ psta->tx_vo_cnt =0; ++ psta->tx_vi_cnt =0; ++ } ++ else{ ++ if(extra_arg == psta->mac_id) ++ { ++ DBG_871X("=== sta's macaddr:" MAC_FMT "===\n", MAC_ARG(psta->hwaddr)); ++ DBG_871X("rx_bk_cnt =%d\n", psta->rx_bk_cnt); ++ DBG_871X("rx_be_cnt =%d\n", psta->rx_be_cnt); ++ DBG_871X("rx_vo_cnt =%d\n", psta->rx_vo_cnt); ++ DBG_871X("rx_vi_cnt =%d\n\n", psta->rx_vi_cnt); ++ ++ DBG_871X("tx_bk_cnt =%d\n", psta->tx_bk_cnt); ++ DBG_871X("tx_be_cnt =%d\n", psta->tx_be_cnt); ++ DBG_871X("tx_vo_cnt =%d\n", psta->tx_vo_cnt); ++ DBG_871X("tx_vi_cnt =%dn\n", psta->tx_vi_cnt); ++ } ++ } ++ ++ } ++ } ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ #endif ++ } ++ break; ++ ++ case 0x0c://dump rx/tx packet ++ { ++ if(arg == 0){ ++ DBG_871X("dump rx packet (%d)\n",extra_arg); ++ //pHalData->bDumpRxPkt =extra_arg; ++ rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); ++ } ++ else if(arg==1){ ++ DBG_871X("dump tx packet (%d)\n",extra_arg); ++ rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); ++ } ++ } ++ break; ++#if 0 ++ case 0x0d://dump cam ++ { ++ //u8 entry = (u8) extra_arg; ++ u8 entry=0; ++ //dump cam ++ for(entry=0;entry<32;entry++) ++ read_cam(padapter,entry); ++ } ++ break; ++#endif ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ case 0x0f: ++ { ++ if(extra_arg == 0){ ++ DBG_871X("###### silent reset test.......#####\n"); ++ rtw_hal_sreset_reset(padapter); ++ } else { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ psrtpriv->dbg_trigger_point = extra_arg; ++ } ++ ++ } ++ break; ++ case 0x15: ++ { ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ DBG_871X("==>silent resete cnts:%d\n",pwrpriv->ips_enter_cnts); ++ } ++ break; ++ ++ #endif ++ ++ case 0x10:// driver version display ++ DBG_871X("rtw driver version=%s\n", DRIVERVERSION); ++ break; ++ case 0x11: ++ { ++ DBG_871X("turn %s Rx RSSI display function\n",(extra_arg==1)?"on":"off"); ++ padapter->bRxRSSIDisplay = extra_arg; ++ rtw_hal_set_def_var(padapter, HW_DEF_FA_CNT_DUMP, &(padapter->bRxRSSIDisplay)); ++ } ++ break; ++ case 0x12: //set rx_stbc ++ { ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ // 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g ++ //default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ ++ if( pregpriv && (extra_arg == 0 || extra_arg == 1|| extra_arg == 2 || extra_arg == 3)) ++ { ++ pregpriv->rx_stbc= extra_arg; ++ DBG_871X("set rx_stbc=%d\n",pregpriv->rx_stbc); ++ } ++ else ++ DBG_871X("get rx_stbc=%d\n",pregpriv->rx_stbc); ++ ++ } ++ break; ++ case 0x13: //set ampdu_enable ++ { ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ // 0: disable, 0x1:enable (but wifi_spec should be 0), 0x2: force enable (don't care wifi_spec) ++ if( pregpriv && extra_arg >= 0 && extra_arg < 3 ) ++ { ++ pregpriv->ampdu_enable= extra_arg; ++ DBG_871X("set ampdu_enable=%d\n",pregpriv->ampdu_enable); ++ } ++ else ++ DBG_871X("get ampdu_enable=%d\n",pregpriv->ampdu_enable); ++ ++ } ++ break; ++ case 0x14: //get wifi_spec ++ { ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ DBG_871X("get wifi_spec=%d\n",pregpriv->wifi_spec); ++ ++ } ++ break; ++ case 0x16: ++ { ++ if(arg == 0xff){ ++ rtw_odm_dbg_comp_msg(padapter); ++ } ++ else{ ++ u64 dbg_comp = (u64)extra_arg; ++ rtw_odm_dbg_comp_set(padapter, dbg_comp); ++ } ++ } ++ break; ++#ifdef DBG_FIXED_CHAN ++ case 0x17: ++ { ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ printk("===> Fixed channel to %d \n",extra_arg); ++ pmlmeext->fixed_chan = extra_arg; ++ ++ } ++ break; ++#endif ++ case 0x20: ++ { ++ rtw_hal_get_hwreg(padapter, HW_VAR_READ_LLT_TAB,(u8 *)&extra_arg); ++ } ++ break; ++ case 0x23: ++ { ++ DBG_871X("turn %s the bNotifyChannelChange Variable\n",(extra_arg==1)?"on":"off"); ++ padapter->bNotifyChannelChange = extra_arg; ++ break; ++ } ++ case 0x24: ++ { ++#ifdef CONFIG_P2P ++ DBG_871X("turn %s the bShowGetP2PState Variable\n",(extra_arg==1)?"on":"off"); ++ padapter->bShowGetP2PState = extra_arg; ++#endif // CONFIG_P2P ++ break; ++ } ++ case 0xaa: ++ { ++ if(extra_arg> 0x13) extra_arg = 0xFF; ++ DBG_871X("chang data rate to :0x%02x\n",extra_arg); ++ padapter->fix_rate = extra_arg; ++ } ++ break; ++ case 0xdd://registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg ++ { ++ if(extra_arg==0){ ++ mac_reg_dump(padapter); ++ } ++ else if(extra_arg==1){ ++ bb_reg_dump(padapter); ++ } ++ else if(extra_arg==2){ ++ rf_reg_dump(padapter); ++ } ++ ++ } ++ break; ++ ++ case 0xee://turn on/off dynamic funcs ++ { ++ u32 odm_flag; ++ ++ if(0xf==extra_arg){ ++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC,&odm_flag); ++ DBG_871X(" === DMFlag(0x%08x) === \n",odm_flag); ++ DBG_871X("extra_arg = 0 - disable all dynamic func \n"); ++ DBG_871X("extra_arg = 1 - disable DIG- BIT(0)\n"); ++ DBG_871X("extra_arg = 2 - disable High power - BIT(1)\n"); ++ DBG_871X("extra_arg = 3 - disable tx power tracking - BIT(2)\n"); ++ DBG_871X("extra_arg = 4 - disable BT coexistence - BIT(3)\n"); ++ DBG_871X("extra_arg = 5 - disable antenna diversity - BIT(4)\n"); ++ DBG_871X("extra_arg = 6 - enable all dynamic func \n"); ++ } ++ else{ ++ /* extra_arg = 0 - disable all dynamic func ++ extra_arg = 1 - disable DIG ++ extra_arg = 2 - disable tx power tracking ++ extra_arg = 3 - turn on all dynamic func ++ */ ++ rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &(extra_arg)); ++ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC,&odm_flag); ++ DBG_871X(" === DMFlag(0x%08x) === \n",odm_flag); ++ } ++ } ++ break; ++ ++ case 0xfd: ++ rtw_write8(padapter, 0xc50, arg); ++ DBG_871X("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); ++ rtw_write8(padapter, 0xc58, arg); ++ DBG_871X("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); ++ break; ++ case 0xfe: ++ DBG_871X("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); ++ DBG_871X("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); ++ break; ++ case 0xff: ++ { ++ DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); ++ DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); ++ DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); ++ DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); ++ DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); ++ ++ DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); ++ ++ ++ DBG_871X("\n"); ++ ++ DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); ++ DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); ++ ++ DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); ++ ++ DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); ++ ++ DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); ++ DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); ++ ++ DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); ++ DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); ++ DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); ++ DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); ++ } ++ break; ++ } ++ break; ++ default: ++ DBG_871X("error dbg cmd!\n"); ++ break; ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int wpa_set_param(struct net_device *dev, u8 name, u32 value) ++{ ++ uint ret=0; ++ u32 flags; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ switch (name){ ++ case IEEE_PARAM_WPA_ENABLED: ++ ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; //802.1x ++ ++ //ret = ieee80211_wpa_enable(ieee, value); ++ ++ switch((value)&0xff) ++ { ++ case 1 : //WPA ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; //WPA_PSK ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case 2: //WPA2 ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; //WPA2_PSK ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("wpa_set_param:padapter->securitypriv.ndisauthtype=%d\n", padapter->securitypriv.ndisauthtype)); ++ ++ break; ++ ++ case IEEE_PARAM_TKIP_COUNTERMEASURES: ++ //ieee->tkip_countermeasures=value; ++ break; ++ ++ case IEEE_PARAM_DROP_UNENCRYPTED: ++ { ++ /* HACK: ++ * ++ * wpa_supplicant calls set_wpa_enabled when the driver ++ * is loaded and unloaded, regardless of if WPA is being ++ * used. No other calls are made which can be used to ++ * determine if encryption will be used or not prior to ++ * association being expected. If encryption is not being ++ * used, drop_unencrypted is set to false, else true -- we ++ * can use this to determine if the CAP_PRIVACY_ON bit should ++ * be set. ++ */ ++ ++#if 0 ++ struct ieee80211_security sec = { ++ .flags = SEC_ENABLED, ++ .enabled = value, ++ }; ++ ieee->drop_unencrypted = value; ++ /* We only change SEC_LEVEL for open mode. Others ++ * are set by ipw_wpa_set_encryption. ++ */ ++ if (!value) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_0; ++ } ++ else { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; ++ } ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++#endif ++ break; ++ ++ } ++ case IEEE_PARAM_PRIVACY_INVOKED: ++ ++ //ieee->privacy_invoked=value; ++ ++ break; ++ ++ case IEEE_PARAM_AUTH_ALGS: ++ ++ ret = wpa_set_auth_algs(dev, value); ++ ++ break; ++ ++ case IEEE_PARAM_IEEE_802_1X: ++ ++ //ieee->ieee802_1x=value; ++ ++ break; ++ ++ case IEEE_PARAM_WPAX_SELECT: ++ ++ // added for WPA2 mixed mode ++ //DBG_871X(KERN_WARNING "------------------------>wpax value = %x\n", value); ++ /* ++ spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); ++ ieee->wpax_type_set = 1; ++ ieee->wpax_type_notify = value; ++ spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); ++ */ ++ ++ break; ++ ++ default: ++ ++ ++ ++ ret = -EOPNOTSUPP; ++ ++ ++ break; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ switch (command) ++ { ++ case IEEE_MLME_STA_DEAUTH: ++ ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ case IEEE_MLME_STA_DISASSOC: ++ ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) ++{ ++ struct ieee_param *param; ++ uint ret=0; ++ ++ //down(&ieee->wx_sem); ++ ++ if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ param = (struct ieee_param *)rtw_malloc(p->length); ++ if (param == NULL) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ if (copy_from_user(param, p->pointer, p->length)) ++ { ++ rtw_mfree((u8*)param, p->length); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ switch (param->cmd) { ++ ++ case IEEE_CMD_SET_WPA_PARAM: ++ ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); ++ break; ++ ++ case IEEE_CMD_SET_WPA_IE: ++ //ret = wpa_set_wpa_ie(dev, param, p->length); ++ ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char*)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); ++ break; ++ ++ case IEEE_CMD_SET_ENCRYPTION: ++ ret = wpa_set_encryption(dev, param, p->length); ++ break; ++ ++ case IEEE_CMD_MLME: ++ ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); ++ break; ++ ++ default: ++ DBG_871X("Unknown WPA supplicant request: %d\n", param->cmd); ++ ret = -EOPNOTSUPP; ++ break; ++ ++ } ++ ++ if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ++ ret = -EFAULT; ++ ++ rtw_mfree((u8 *)param, p->length); ++ ++out: ++ ++ //up(&ieee->wx_sem); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_AP_MODE ++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ++ ++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; ++ ++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); ++ ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++ ++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) ++{ ++ u8 keylen; ++ struct cmd_obj* pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv); ++ int res=_SUCCESS; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ psetkeyparm->keyid=(u8)keyid; ++ if (is_wep_enc(alg)) ++ padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); ++ psetkeyparm->algorithm = alg; ++ ++ psetkeyparm->set_tx = 1; ++ ++ switch(alg) ++ { ++ case _WEP40_: ++ keylen = 5; ++ break; ++ case _WEP104_: ++ keylen = 13; ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ case _AES_: ++ keylen = 16; ++ default: ++ keylen = 16; ++ } ++ ++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++ return res; ++ ++ ++} ++ ++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid) ++{ ++ u8 alg; ++ ++ switch(keylen) ++ { ++ case 5: ++ alg =_WEP40_; ++ break; ++ case 13: ++ alg =_WEP104_; ++ break; ++ default: ++ alg =_NO_PRIVACY_; ++ } ++ ++ return set_group_key(padapter, key, alg, keyid); ++ ++} ++ ++ ++static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ struct sta_info *psta = NULL, *pbcmc_sta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ //sizeof(struct ieee_param) = 64 bytes; ++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(!psta) ++ { ++ //ret = -EINVAL; ++ DBG_871X("rtw_set_encryption(), sta has already been removed or never been added\n"); ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) ++ { ++ //todo:clear default encryption keys ++ ++ DBG_871X("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); ++ ++ goto exit; ++ } ++ ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) ++ { ++ DBG_871X("r871x_set_encryption, crypt.alg = WEP\n"); ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ DBG_871X("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); ++ ++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *)rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ DBG_871X(" r871x_set_encryption: pwep allocate fail !!!\n"); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_871X("wep, set_tx=1\n"); ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_; ++ ++ if(pwep->KeyLength==13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_; ++ } ++ ++ ++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ ++ } ++ else ++ { ++ DBG_871X("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ ++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key ++ { ++ if(param->u.crypt.set_tx ==1) ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_871X("%s, set group_key, WEP\n", __FUNCTION__); ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_871X("%s, set group_key, TKIP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ DBG_871X("%s, set group_key, CCMP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ DBG_871X("%s, set group_key, none\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x ++ { ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ if(param->u.crypt.set_tx ==1) ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_871X("%s, set pairwise key, WEP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psta->dot118021XPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_871X("%s, set pairwise key, TKIP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _TKIP_; ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ ++ DBG_871X("%s, set pairwise key, CCMP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _AES_; ++ } ++ else ++ { ++ DBG_871X("%s, set pairwise key, none\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _NO_PRIVACY_; ++ } ++ ++ set_pairwise_key(padapter, psta); ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ } ++ else//group key??? ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++ if(pwep) ++ { ++ rtw_mfree((u8 *)pwep, wep_total_len); ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ unsigned char *pbuf = param->u.bcn_ie.buf; ++ ++ ++ DBG_871X("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); ++ ++ if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) ++ pstapriv->max_num_sta = NUM_STA; ++ ++ ++ if(rtw_check_beacon_data(padapter, pbuf, (len-12-2)) == _SUCCESS)// 12 = param header, 2:no packed ++ ret = 0; ++ else ++ ret = -EINVAL; ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_hostapd_sta_flush(struct net_device *dev) ++{ ++ //_irqL irqL; ++ //_list *phead, *plist; ++ int ret=0; ++ //struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ flush_all_cam_entry(padapter); //clear CAM ++ ++ ret = rtw_sta_flush(padapter); ++ ++ return ret; ++ ++} ++ ++static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) ++{ ++ _irqL irqL; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++/* ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ DBG_871X("rtw_add_sta(), free has been added psta=%p\n", psta); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ psta = NULL; ++ } ++*/ ++ //psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ int flags = param->u.add_sta.flags; ++ ++ //DBG_871X("rtw_add_sta(), init sta's variables, psta=%p\n", psta); ++ ++ psta->aid = param->u.add_sta.aid;//aid=1~2007 ++ ++ _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); ++ ++ ++ //check wmm cap. ++ if(WLAN_STA_WME&flags) ++ psta->qos_option = 1; ++ else ++ psta->qos_option = 0; ++ ++ if(pmlmepriv->qospriv.qos_option == 0) ++ psta->qos_option = 0; ++ ++ ++#ifdef CONFIG_80211N_HT ++ //chec 802.11n ht cap. ++ if(WLAN_STA_HT&flags) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ psta->qos_option = 1; ++ _rtw_memcpy((void*)&psta->htpriv.ht_cap, (void*)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); ++ } ++ else ++ { ++ psta->htpriv.ht_option = _FALSE; ++ } ++ ++ if(pmlmepriv->htpriv.ht_option == _FALSE) ++ psta->htpriv.ht_option = _FALSE; ++#endif ++ ++ ++ update_sta_info_apmode(padapter, psta); ++ ++ ++ } ++ else ++ { ++ ret = -ENOMEM; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) ++{ ++ _irqL irqL; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ u8 updated; ++ ++ //DBG_871X("free psta=%p, aid=%d\n", psta, psta->aid); ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ pstapriv->asoc_list_cnt--; ++ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING); ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ associated_clients_update(padapter, updated); ++ ++ psta = NULL; ++ ++ } ++ else ++ { ++ DBG_871X("rtw_del_sta(), sta has already been removed or never been added\n"); ++ ++ //ret = -1; ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; ++ struct sta_data *psta_data = (struct sta_data *)param_ex->data; ++ ++ DBG_871X("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && ++ param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && ++ param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); ++ if(psta) ++ { ++#if 0 ++ struct { ++ u16 aid; ++ u16 capability; ++ int flags; ++ u32 sta_set; ++ u8 tx_supp_rates[16]; ++ u32 tx_supp_rates_len; ++ struct rtw_ieee80211_ht_cap ht_cap; ++ u64 rx_pkts; ++ u64 rx_bytes; ++ u64 rx_drops; ++ u64 tx_pkts; ++ u64 tx_bytes; ++ u64 tx_drops; ++ } get_sta; ++#endif ++ psta_data->aid = (u16)psta->aid; ++ psta_data->capability = psta->capability; ++ psta_data->flags = psta->flags; ++ ++/* ++ nonerp_set : BIT(0) ++ no_short_slot_time_set : BIT(1) ++ no_short_preamble_set : BIT(2) ++ no_ht_gf_set : BIT(3) ++ no_ht_set : BIT(4) ++ ht_20mhz_set : BIT(5) ++*/ ++ ++ psta_data->sta_set =((psta->nonerp_set) | ++ (psta->no_short_slot_time_set <<1) | ++ (psta->no_short_preamble_set <<2) | ++ (psta->no_ht_gf_set <<3) | ++ (psta->no_ht_set <<4) | ++ (psta->ht_20mhz_set <<5)); ++ ++ psta_data->tx_supp_rates_len = psta->bssratelen; ++ _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); ++#ifdef CONFIG_80211N_HT ++ _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); ++#endif //CONFIG_80211N_HT ++ psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; ++ psta_data->rx_bytes = psta->sta_stats.rx_bytes; ++ psta_data->rx_drops = psta->sta_stats.rx_drops; ++ ++ psta_data->tx_pkts = psta->sta_stats.tx_pkts; ++ psta_data->tx_bytes = psta->sta_stats.tx_bytes; ++ psta_data->tx_drops = psta->sta_stats.tx_drops; ++ ++ ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) ++{ ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ if((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) ++ { ++ int wpa_ie_len; ++ int copy_len; ++ ++ wpa_ie_len = psta->wpa_ie[1]; ++ ++ copy_len = ((wpa_ie_len+2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)):(wpa_ie_len+2); ++ ++ param->u.wpa_ie.len = copy_len; ++ ++ _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); ++ } ++ else ++ { ++ //ret = -1; ++ DBG_871X("sta's wpa_ie is NONE\n"); ++ } ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ unsigned char wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int ie_len; ++ ++ DBG_871X("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); ++ pmlmepriv->wps_beacon_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_beacon_ie_len = ie_len; ++ if ( pmlmepriv->wps_beacon_ie == NULL) { ++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); ++ ++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int ie_len; ++ ++ DBG_871X("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_probe_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_probe_resp_ie_len = ie_len; ++ if ( pmlmepriv->wps_probe_resp_ie == NULL) { ++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int ie_len; ++ ++ DBG_871X("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_assoc_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_assoc_resp_ie_len = ie_len; ++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) { ++ DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *mlmepriv = &(adapter->mlmepriv); ++ struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); ++ struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); ++ int ie_len; ++ u8 *ssid_ie; ++ char ssid[NDIS_802_11_LENGTH_SSID + 1]; ++ sint ssid_len; ++ u8 ignore_broadcast_ssid; ++ ++ if(check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EPERM; ++ ++ if (param->u.bcn_ie.reserved[0] != 0xea) ++ return -EINVAL; ++ ++ mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1]; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len); ++ ++ if (ssid_ie && ssid_len) { ++ WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network; ++ WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network; ++ ++ _rtw_memcpy(ssid, ssid_ie+2, ssid_len); ++ ssid[ssid_len>NDIS_802_11_LENGTH_SSID?NDIS_802_11_LENGTH_SSID:ssid_len] = 0x0; ++ ++ if(0) ++ DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), ++ ssid, ssid_len, ++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, ++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); ++ ++ _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); ++ pbss_network->Ssid.SsidLength = ssid_len; ++ _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len); ++ pbss_network_ext->Ssid.SsidLength = ssid_len; ++ ++ if(0) ++ DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), ++ pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, ++ pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); ++ } ++ ++ DBG_871X(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), ++ ignore_broadcast_ssid, ssid, ssid_len); ++ ++ return ret; ++} ++ ++static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ ret = rtw_acl_remove_sta(padapter, param->sta_addr); ++ ++ return ret; ++ ++} ++ ++static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ ret = rtw_acl_add_sta(padapter, param->sta_addr); ++ ++ return ret; ++ ++} ++ ++static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ rtw_set_macaddr_acl(padapter, param->u.mlme.command); ++ ++ return ret; ++} ++ ++static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) ++{ ++ struct ieee_param *param; ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ /* ++ * this function is expect to call in master mode, which allows no power saving ++ * so, we just check hw_init_completed ++ */ ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -EPERM; ++ goto out; ++ } ++ ++ ++ //if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ if(!p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ param = (struct ieee_param *)rtw_malloc(p->length); ++ if (param == NULL) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ if (copy_from_user(param, p->pointer, p->length)) ++ { ++ rtw_mfree((u8*)param, p->length); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ //DBG_871X("%s, cmd=%d\n", __FUNCTION__, param->cmd); ++ ++ switch (param->cmd) ++ { ++ case RTL871X_HOSTAPD_FLUSH: ++ ++ ret = rtw_hostapd_sta_flush(dev); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_ADD_STA: ++ ++ ret = rtw_add_sta(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_REMOVE_STA: ++ ++ ret = rtw_del_sta(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_BEACON: ++ ++ ret = rtw_set_beacon(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_SET_ENCRYPTION: ++ ++ ret = rtw_set_encryption(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_GET_WPAIE_STA: ++ ++ ret = rtw_get_sta_wpaie(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_BEACON: ++ ++ ret = rtw_set_wps_beacon(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: ++ ++ ret = rtw_set_wps_probe_resp(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: ++ ++ ret = rtw_set_wps_assoc_resp(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_HIDDEN_SSID: ++ ++ ret = rtw_set_hidden_ssid(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_GET_INFO_STA: ++ ++ ret = rtw_ioctl_get_sta_data(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_MACADDR_ACL: ++ ++ ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_ACL_ADD_STA: ++ ++ ret = rtw_ioctl_acl_add_sta(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_ACL_REMOVE_STA: ++ ++ ret = rtw_ioctl_acl_remove_sta(dev, param, p->length); ++ ++ break; ++ ++ default: ++ DBG_871X("Unknown hostapd request: %d\n", param->cmd); ++ ret = -EOPNOTSUPP; ++ break; ++ ++ } ++ ++ if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ++ ret = -EFAULT; ++ ++ ++ rtw_mfree((u8 *)param, p->length); ++ ++out: ++ ++ return ret; ++ ++} ++#endif ++ ++#include ++static int rtw_wx_set_priv(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ ++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ char *ext_dbg; ++#endif ++ ++ int ret = 0; ++ int len = 0; ++ char *ext; ++ int i; ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *dwrq = (struct iw_point*)awrq; ++ ++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ("+rtw_wx_set_priv\n")); ++ if(dwrq->length == 0) ++ return -EFAULT; ++ ++ len = dwrq->length; ++ if (!(ext = rtw_vmalloc(len))) ++ return -ENOMEM; ++ ++ if (copy_from_user(ext, dwrq->pointer, len)) { ++ rtw_vmfree(ext, len); ++ return -EFAULT; ++ } ++ ++ ++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ++ // ("rtw_wx_set_priv: %s req=%s\n", ++ // dev->name, ext)); ++ ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ if (!(ext_dbg = rtw_vmalloc(len))) ++ { ++ rtw_vmfree(ext, len); ++ return -ENOMEM; ++ } ++ ++ _rtw_memcpy(ext_dbg, ext, len); ++ #endif ++ ++ //added for wps2.0 @20110524 ++ if(dwrq->flags == 0x8766 && len > 8) ++ { ++ u32 cp_sz; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 *probereq_wpsie = ext; ++ int probereq_wpsie_len = len; ++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ if((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && ++ (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) ==_TRUE)) ++ { ++ cp_sz = probereq_wpsie_len>MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN:probereq_wpsie_len; ++ ++ //_rtw_memcpy(pmlmepriv->probereq_wpsie, probereq_wpsie, cp_sz); ++ //pmlmepriv->probereq_wpsie_len = cp_sz; ++ if(pmlmepriv->wps_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_req_ie_len; ++ pmlmepriv->wps_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); ++ pmlmepriv->wps_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz); ++ if ( pmlmepriv->wps_probe_req_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ ret = -EINVAL; ++ goto FREE_EXT; ++ ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz); ++ pmlmepriv->wps_probe_req_ie_len = cp_sz; ++ ++ } ++ ++ goto FREE_EXT; ++ ++ } ++ ++ if( len >= WEXT_CSCAN_HEADER_SIZE ++ && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE ++ ){ ++ ret = rtw_wx_set_scan(dev, info, awrq, ext); ++ goto FREE_EXT; ++ } ++ ++#ifdef CONFIG_ANDROID ++ //DBG_871X("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); ++ ++ i = rtw_android_cmdstr_to_num(ext); ++ ++ switch(i) { ++ case ANDROID_WIFI_CMD_START : ++ indicate_wx_custom_event(padapter, "START"); ++ break; ++ case ANDROID_WIFI_CMD_STOP : ++ indicate_wx_custom_event(padapter, "STOP"); ++ break; ++ case ANDROID_WIFI_CMD_RSSI : ++ { ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); ++ } else { ++ sprintf(ext, "OK"); ++ } ++ } ++ break; ++ case ANDROID_WIFI_CMD_LINKSPEED : ++ { ++ u16 mbps = rtw_get_cur_max_rate(padapter)/10; ++ sprintf(ext, "LINKSPEED %d", mbps); ++ } ++ break; ++ case ANDROID_WIFI_CMD_MACADDR : ++ sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr)); ++ break; ++ case ANDROID_WIFI_CMD_SCAN_ACTIVE : ++ { ++ //rtw_set_scan_mode(padapter, SCAN_ACTIVE); ++ sprintf(ext, "OK"); ++ } ++ break; ++ case ANDROID_WIFI_CMD_SCAN_PASSIVE : ++ { ++ //rtw_set_scan_mode(padapter, SCAN_PASSIVE); ++ sprintf(ext, "OK"); ++ } ++ break; ++ ++ case ANDROID_WIFI_CMD_COUNTRY : ++ { ++ char country_code[10]; ++ sscanf(ext, "%*s %s", country_code); ++ rtw_set_country(padapter, country_code); ++ sprintf(ext, "OK"); ++ } ++ break; ++ default : ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ DBG_871X("%s: %s unknowned req=%s\n", __FUNCTION__, ++ dev->name, ext_dbg); ++ #endif ++ ++ sprintf(ext, "OK"); ++ ++ } ++ ++ if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext)+1)) ) ) ++ ret = -EFAULT; ++ ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ DBG_871X("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__, ++ dev->name, ext_dbg ,ext, dwrq->length, (u16)(strlen(ext)+1)); ++ #endif ++#endif //end of CONFIG_ANDROID ++ ++ ++FREE_EXT: ++ ++ rtw_vmfree(ext, len); ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ rtw_vmfree(ext_dbg, len); ++ #endif ++ ++ //DBG_871X("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", ++ // dev->name, ret); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_WOWLAN ++static int rtw_wowlan_ctrl(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct wowlan_ioctl_param poidparam; ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct sta_info *psta = NULL; ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++ poidparam.subcode = 0; ++ ++ DBG_871X("+rtw_wowlan_ctrl: %s\n", extra); ++ ++ if(pwrctrlpriv->bSupportRemoteWakeup==_FALSE){ ++ ret = -EPERM; ++ DBG_871X("+rtw_wowlan_ctrl: Device didn't support the remote wakeup!!\n"); ++ goto _rtw_wowlan_ctrl_exit_free; ++ } ++ ++ if (!check_fwstate(pmlmepriv, _FW_LINKED) && ++ check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { ++ DBG_871X("[%s] WARNING: Please Connect With AP First!!\n", __func__); ++ goto _rtw_wowlan_ctrl_exit_free; ++ } ++ ++ if (_rtw_memcmp( extra, "enable", 6 )) { ++ ++ while (pwrctrlpriv->bips_processing == _TRUE) ++ rtw_msleep_os(1); ++ ++ rtw_cancel_all_timer(padapter); ++ ++ padapter->bDriverStopped = _TRUE; //for stop thread ++ rtw_stop_drv_threads(padapter); ++ padapter->bDriverStopped = _FALSE; //for 32k command ++ ++#ifdef CONFIG_LPS ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif ++ rtw_hal_disable_interrupt(padapter); // It need wait for leaving 32K. ++ ++ // 2.1 clean interupt ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ poidparam.subcode = WOWLAN_ENABLE; ++ ++ rtw_hal_set_hwreg(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ } else if (_rtw_memcmp( extra, "disable", 6 )) { ++#ifdef CONFIG_LPS ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif //CONFIG_LPS ++ pwrctrlpriv->bFwCurrentInPSMode = _FALSE; ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ poidparam.subcode = WOWLAN_DISABLE; ++ ++ rtw_hal_set_hwreg(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ if (psta) { ++ set_sta_rate(padapter, psta); ++ } ++ ++ padapter->bDriverStopped = _FALSE; ++ DBG_871X("%s: wowmode resuming, DriverStopped:%d\n", __func__, padapter->bDriverStopped); ++ rtw_start_drv_threads(padapter); ++ ++ rtw_hal_enable_interrupt(padapter); ++ ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ pwrctrlpriv->bips_processing = _FALSE; ++ rtw_set_pwr_state_check_timer(pwrctrlpriv); ++ ++ } else { ++ DBG_871X("[%s] Invalid Parameter.\n", __func__); ++ goto _rtw_wowlan_ctrl_exit_free; ++ } ++ //mutex_lock(&ioctl_mutex); ++_rtw_wowlan_ctrl_exit_free: ++ DBG_871X("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); ++ DBG_871X_LEVEL(_drv_always_, "%s in %d ms\n", __func__, ++ rtw_get_passing_time_ms(start_time)); ++_rtw_wowlan_ctrl_exit: ++ return ret; ++} ++#endif //CONFIG_WOWLAN ++ ++static int rtw_pm_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ unsigned mode = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ ++ if ( _rtw_memcmp( extra, "lps=", 4 ) ) ++ { ++ sscanf(extra+4, "%u", &mode); ++ ret = rtw_pm_set_lps(padapter,mode); ++ } ++ else if ( _rtw_memcmp( extra, "ips=", 4 ) ) ++ { ++ sscanf(extra+4, "%u", &mode); ++ ret = rtw_pm_set_ips(padapter,mode); ++ } ++ else{ ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static int rtw_mp_efuse_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ++ PEFUSE_HAL pEfuseHal; ++ struct iw_point *wrqu; ++ ++ u8 *PROMContent = pEEPROM->efuse_eeprom_data; ++ struct pwrctrl_priv *pwrctrlpriv ; ++ ++ u8 *data = NULL; ++ u8 *rawdata = NULL; ++ char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00}; ++ u8 ips_mode,lps_mode; ++ u16 i=0, j=0, mapLen=0, addr=0, cnts=0; ++ u16 max_available_size=0, raw_cursize=0, raw_maxsize=0; ++ int err; ++ #ifdef CONFIG_IOL ++ u8 org_fw_iol = padapter->registrypriv.fw_iol;// 0:Disable, 1:enable, 2:by usb speed ++ #endif ++ ++ wrqu = (struct iw_point*)wdata; ++ pwrctrlpriv = adapter_to_pwrctl(padapter); ++ pEfuseHal = &pHalData->EfuseHal; ++ ++ err = 0; ++ data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); ++ if (data == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); ++ if (rawdata == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ { ++ err = -EFAULT; ++ goto exit; ++ } ++ #ifdef CONFIG_LPS ++ lps_mode = pwrctrlpriv->power_mgnt;//keep org value ++ rtw_pm_set_lps(padapter,PS_MODE_ACTIVE); ++ #endif ++ ++ #ifdef CONFIG_IPS ++ ips_mode = pwrctrlpriv->ips_mode;//keep org value ++ rtw_pm_set_ips(padapter,IPS_NONE); ++ #endif ++ ++ pch = extra; ++ DBG_871X("%s: in=%s\n", __FUNCTION__, extra); ++ ++ i = 0; ++ //mac 16 "00e04c871200" rmap,00,2 ++ while ((token = strsep(&pch, ",")) != NULL) ++ { ++ if (i > 2) break; ++ tmp[i] = token; ++ i++; ++ } ++ #ifdef CONFIG_IOL ++ padapter->registrypriv.fw_iol = 0;// 0:Disable, 1:enable, 2:by usb speed ++ #endif ++ ++ if(strcmp(tmp[0], "status") == 0){ ++ sprintf(extra, "Load File efuse=%s,Load File MAC=%s",(pEEPROM->bloadfile_fail_flag? "FAIL" : "OK"),(pEEPROM->bloadmac_fail_flag? "FAIL" : "OK")); ++ ++ goto exit; ++ } ++ else if (strcmp(tmp[0], "drvmap") == 0) ++ { ++ mapLen = EFUSE_MAP_SIZE; ++ ++ sprintf(extra, "\n"); ++ for (i = 0; i < EFUSE_MAP_SIZE; i += 16) ++ { ++// DBG_871X("0x%02x\t", i); ++ sprintf(extra, "%s0x%02x\t", extra, i); ++ for (j=0; j<8; j++) { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, PROMContent[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra, "%s\t", extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, PROMContent[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra,"%s\n",extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0], "realmap") == 0) ++ { ++ mapLen = EFUSE_MAP_SIZE; ++ if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) ++ { ++ DBG_871X("%s: read realmap Fail!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("OFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "\n"); ++ for (i = 0; i < EFUSE_MAP_SIZE; i += 16) ++ { ++// DBG_871X("0x%02x\t", i); ++ sprintf(extra, "%s0x%02x\t", extra, i); ++ for (j=0; j<8; j++) { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseInitMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra, "%s\t", extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseInitMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra,"%s\n",extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0], "rmap") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ // rmap addr cnts ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); ++ ++ cnts = simple_strtoul(tmp[2], &ptmp, 10); ++ if (cnts == 0) ++ { ++ DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if ((addr + cnts) > max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_read error!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("%s: data={", __FUNCTION__); ++ *extra = 0; ++ for (i=0; i max_available_size) { ++ DBG_871X("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_read error!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("%s: MAC address={", __FUNCTION__); ++ *extra = 0; ++ for (i=0; i max_available_size) ++ { ++ DBG_871X("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_access error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("%s: {VID,PID}={", __FUNCTION__); ++ *extra = 0; ++ for (i=0; iBTEfuseInitMap) == _FAIL) ++ { ++ DBG_871X("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("OFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "\n"); ++ for (i=0; i<512; i+=16) // set 512 because the iwpriv's extra size have limit 0x7FF ++ { ++// DBG_871X("0x%03x\t", i); ++ sprintf(extra, "%s0x%03x\t", extra, i); ++ for (j=0; j<8; j++) { ++// DBG_871X("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra,"%s\t",extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra, "%s\n", extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0],"btbmap") == 0) ++ { ++ mapLen = EFUSE_BT_MAX_MAP_LEN; ++ if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) ++ { ++ DBG_871X("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++// DBG_871X("OFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "\n"); ++ for (i=512; i<1024 ; i+=16) ++ { ++// DBG_871X("0x%03x\t", i); ++ sprintf(extra, "%s0x%03x\t", extra, i); ++ for (j=0; j<8; j++) ++ { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra,"%s\t",extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", data[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra, "%s\n", extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0],"btrmap") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ // rmap addr cnts ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ ++ cnts = simple_strtoul(tmp[2], &ptmp, 10); ++ if (cnts == 0) ++ { ++ DBG_871X("%s: btrmap Fail!! cnts error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if ((addr + cnts) > max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_871X("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ *extra = 0; ++// DBG_871X("%s: bt efuse data={", __FUNCTION__); ++ for (i=0; ifakeBTEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra, "%s\t", extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra, "%s\n", extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0],"btbfake") == 0) ++ { ++// DBG_871X("OFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "\n"); ++ for (i=512; i<1024; i+=16) ++ { ++// DBG_871X("0x%03x\t", i); ++ sprintf(extra, "%s0x%03x\t", extra, i); ++ for (j=0; j<8; j++) { ++// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra, "%s\t", extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra, "%s\n", extra); ++ } ++// DBG_871X("\n"); ++ } ++ else if (strcmp(tmp[0],"wlrfkmap")== 0) ++ { ++// DBG_871X("OFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "\n"); ++ for (i=0; ifakeEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\t"); ++ sprintf(extra, "%s\t", extra); ++ for (; j<16; j++) { ++// DBG_871X("%02X ", pEfuseHal->fakeEfuseModifiedMap[i+j]); ++ sprintf(extra, "%s %02X", extra, pEfuseHal->fakeEfuseModifiedMap[i+j]); ++ } ++// DBG_871X("\n"); ++ sprintf(extra, "%s\n", extra); ++ } ++// DBG_871X("\n"); ++ ++ } ++ else if (strcmp(tmp[0],"wlrfkrmap")== 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ // rmap addr cnts ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); ++ ++ cnts = simple_strtoul(tmp[2], &ptmp, 10); ++ if (cnts == 0) ++ { ++ DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ ++ // DBG_871X("%s: data={", __FUNCTION__); ++ *extra = 0; ++ for (i=0; ifakeEfuseModifiedMap[addr+i]); ++ sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[addr+i]); ++ } ++ } ++ else if (strcmp(tmp[0],"btrfkrmap")== 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ // rmap addr cnts ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); ++ ++ cnts = simple_strtoul(tmp[2], &ptmp, 10); ++ if (cnts == 0) ++ { ++ DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); ++ err = -EINVAL; ++ goto exit; ++ } ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ ++ // DBG_871X("%s: data={", __FUNCTION__); ++ *extra = 0; ++ for (i=0; ifakeBTEfuseModifiedMap[addr+i]); ++ sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[addr+i]); ++ } ++ } ++ else ++ { ++ sprintf(extra, "Command not found!"); ++ } ++ ++exit: ++ if (data) ++ rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN); ++ if (rawdata) ++ rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN); ++ if (!err) ++ wrqu->length = strlen(extra); ++ ++ #ifdef CONFIG_IPS ++ rtw_pm_set_ips(padapter, ips_mode); ++ #endif ++ #ifdef CONFIG_LPS ++ rtw_pm_set_lps(padapter, lps_mode); ++ #endif ++ #ifdef CONFIG_IOL ++ padapter->registrypriv.fw_iol = org_fw_iol;// 0:Disable, 1:enable, 2:by usb speed ++ #endif ++ return err; ++} ++ ++static int rtw_mp_efuse_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu; ++ PADAPTER padapter; ++ struct pwrctrl_priv *pwrctrlpriv ; ++ PHAL_DATA_TYPE pHalData; ++ PEFUSE_HAL pEfuseHal; ++ ++ u8 ips_mode,lps_mode; ++ u32 i, jj, kk; ++ u8 *setdata = NULL; ++ u8 *ShadowMapBT = NULL; ++ u8 *ShadowMapWiFi = NULL; ++ u8 *setrawdata = NULL; ++ char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00}; ++ u16 addr=0, cnts=0, max_available_size=0; ++ int err; ++ ++ ++ wrqu = (struct iw_point*)wdata; ++ padapter = rtw_netdev_priv(dev); ++ pwrctrlpriv = adapter_to_pwrctl(padapter); ++ pHalData = GET_HAL_DATA(padapter); ++ pEfuseHal = &pHalData->EfuseHal; ++ err = 0; ++ setdata = rtw_zmalloc(1024); ++ if (setdata == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN); ++ if (ShadowMapBT == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ShadowMapWiFi = rtw_malloc(EFUSE_MAP_SIZE); ++ if (ShadowMapWiFi == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ setrawdata = rtw_malloc(EFUSE_MAX_SIZE); ++ if (setrawdata == NULL) ++ { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ #ifdef CONFIG_LPS ++ lps_mode = pwrctrlpriv->power_mgnt;//keep org value ++ rtw_pm_set_lps(padapter,PS_MODE_ACTIVE); ++ #endif ++ ++ #ifdef CONFIG_IPS ++ ips_mode = pwrctrlpriv->ips_mode;//keep org value ++ rtw_pm_set_ips(padapter,IPS_NONE); ++ #endif ++ ++ pch = extra; ++ DBG_871X("%s: in=%s\n", __FUNCTION__, extra); ++ ++ i = 0; ++ while ((token = strsep(&pch, ",")) != NULL) ++ { ++ if (i > 2) break; ++ tmp[i] = token; ++ i++; ++ } ++ ++ // tmp[0],[1],[2] ++ // wmap,addr,00e04c871200 ++ if (strcmp(tmp[0], "wmap") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ addr &= 0xFFF; ++ ++ cnts = strlen(tmp[2]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: map data=%s\n", __FUNCTION__, tmp[2]); ++ ++ for (jj=0, kk=0; jj max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "wraw") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ addr = simple_strtoul( tmp[1], &ptmp, 16 ); ++ addr &= 0xFFF; ++ ++ cnts = strlen(tmp[2]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: raw data=%s\n", __FUNCTION__, tmp[2]); ++ ++ for (jj=0, kk=0; jj 6) ++ { ++ DBG_871X("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); ++ ++ for (jj=0, kk=0; jj max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "vidpid") == 0) ++ { ++ if (tmp[1]==NULL) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ // pidvid,da0b7881 ++ #ifdef CONFIG_RTL8192C ++ addr = 0x0a; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ addr = 0x0c; ++ #endif ++ #ifdef CONFIG_RTL8723A ++ addr = EEPROM_VID_8723AU; ++ #endif ++ #ifdef CONFIG_RTL8188E ++ #ifdef CONFIG_USB_HCI ++ addr = EEPROM_VID_88EE; ++ #endif ++ #ifdef CONFIG_PCI_HCI ++ addr = EEPROM_VID_88EE; ++ #endif ++ #endif //#ifdef CONFIG_RTL8188E ++ cnts = strlen(tmp[1]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]); ++ ++ for (jj=0, kk=0; jj max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "wldumpfake") == 0) ++ { ++ if (rtw_efuse_map_read(padapter, 0, EFUSE_MAP_SIZE, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS) { ++ DBG_871X("%s: WiFi hw efuse dump to Fake map success \n", __FUNCTION__); ++ } else { ++ DBG_871X("%s: WiFi hw efuse dump to Fake map Fail \n", __FUNCTION__); ++ err = -EFAULT; ++ } ++ } ++ else if (strcmp(tmp[0], "btwmap") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ addr &= 0xFFF; ++ ++ cnts = strlen(tmp[2]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: BT data=%s\n", __FUNCTION__, tmp[2]); ++ ++ for (jj=0, kk=0; jj max_available_size) ++ { ++ DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) ++ { ++ DBG_871X("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "btwfake") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ addr &= 0xFFF; ++ ++ cnts = strlen(tmp[2]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]); ++ ++ for (jj=0, kk=0; jjfakeBTEfuseModifiedMap[addr+jj] = key_2char2num(tmp[2][kk], tmp[2][kk+1]); ++ } ++ } ++ else if (strcmp(tmp[0], "btdumpfake") == 0) ++ { ++ if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS) { ++ DBG_871X("%s: BT read all map success\n", __FUNCTION__); ++ } else { ++ DBG_871X("%s: BT read all map Fail!\n", __FUNCTION__); ++ err = -EFAULT; ++ } ++ } ++ else if (strcmp(tmp[0], "btfk2map") == 0) ++ { ++ _rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if (max_available_size < 1) ++ { ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) ++ { ++ DBG_871X("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "wlfk2map") == 0) ++ { ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if (max_available_size < 1) ++ { ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ if (rtw_efuse_map_write(padapter, 0x00, EFUSE_MAP_SIZE, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) ++ { ++ DBG_871X("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__); ++ err = -EFAULT; ++ goto exit; ++ } ++ } ++ else if (strcmp(tmp[0], "wlwfake") == 0) ++ { ++ if ((tmp[1]==NULL) || (tmp[2]==NULL)) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ addr &= 0xFFF; ++ ++ cnts = strlen(tmp[2]); ++ if (cnts%2) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ cnts /= 2; ++ if (cnts == 0) ++ { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]); ++ ++ for (jj=0, kk=0; jjfakeEfuseModifiedMap[addr+jj] = key_2char2num(tmp[2][kk], tmp[2][kk+1]); ++ } ++ } ++ ++exit: ++ if (setdata) ++ rtw_mfree(setdata, 1024); ++ if (ShadowMapBT) ++ rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN); ++ if (ShadowMapWiFi) ++ rtw_mfree(ShadowMapWiFi, EFUSE_MAP_SIZE); ++ if (setrawdata) ++ rtw_mfree(setrawdata, EFUSE_MAX_SIZE); ++ ++ #ifdef CONFIG_IPS ++ rtw_pm_set_ips(padapter, ips_mode); ++ #endif ++ #ifdef CONFIG_LPS ++ rtw_pm_set_lps(padapter, lps_mode); ++ #endif ++ ++ return err; ++} ++ ++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++/* ++ * Input Format: %s,%d,%d ++ * %s is width, could be ++ * "b" for 1 byte ++ * "w" for WORD (2 bytes) ++ * "dw" for DWORD (4 bytes) ++ * 1st %d is address(offset) ++ * 2st %d is data to write ++ */ ++static int rtw_mp_write_reg(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char *pch, *pnext, *ptmp; ++ char *width_str; ++ char width; ++ u32 addr, data; ++ int ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ char input[wrqu->length]; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ pch = input; ++ ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ width_str = pch; ++ ++ pch = pnext + 1; ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ addr = simple_strtoul(pch, &ptmp, 16); ++ if (addr > 0x3FFF) return -EINVAL; ++ ++ pch = pnext + 1; ++ if ((pch - extra) >= wrqu->length) return -EINVAL; ++ data = simple_strtoul(pch, &ptmp, 16); ++ ++ ret = 0; ++ width = width_str[0]; ++ switch (width) { ++ case 'b': ++ // 1 byte ++ if (data > 0xFF) { ++ ret = -EINVAL; ++ break; ++ } ++ rtw_write8(padapter, addr, data); ++ break; ++ case 'w': ++ // 2 bytes ++ if (data > 0xFFFF) { ++ ret = -EINVAL; ++ break; ++ } ++ rtw_write16(padapter, addr, data); ++ break; ++ case 'd': ++ // 4 bytes ++ rtw_write32(padapter, addr, data); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++/* ++ * Input Format: %s,%d ++ * %s is width, could be ++ * "b" for 1 byte ++ * "w" for WORD (2 bytes) ++ * "dw" for DWORD (4 bytes) ++ * %d is address(offset) ++ * ++ * Return: ++ * %d for data readed ++ */ ++static int rtw_mp_read_reg(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char input[wrqu->length]; ++ char *pch, *pnext, *ptmp; ++ char *width_str; ++ char width; ++ char data[20],tmp[20]; ++ u32 addr; ++ //u32 *data = (u32*)extra; ++ u32 ret, i=0, j=0, strtout=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (wrqu->length > 128) ++ return -EFAULT; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ _rtw_memset(data, 0, 20); ++ _rtw_memset(tmp, 0, 20); ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ pch = input; ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ width_str = pch; ++ ++ pch = pnext + 1; ++ if ((pch - input) >= wrqu->length) return -EINVAL; ++ ++ addr = simple_strtoul(pch, &ptmp, 16); ++ if (addr > 0x3FFF) return -EINVAL; ++ ++ ret = 0; ++ width = width_str[0]; ++ switch (width) ++ { ++ case 'b': ++ // 1 byte ++ // *(u8*)data = rtw_read8(padapter, addr); ++ sprintf(extra, "%d\n", rtw_read8(padapter, addr)); ++ wrqu->length = strlen(extra); ++ break; ++ case 'w': ++ // 2 bytes ++ //*(u16*)data = rtw_read16(padapter, addr); ++ sprintf(data, "%04x\n", rtw_read16(padapter, addr)); ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ if ( data[i] != '\0' ) ++ tmp[j] = data[i]; ++ ++ j++; ++ } ++ pch = tmp; ++ DBG_871X("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ if (!pnext) ++ break; ++ ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtout = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtout ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = 7; ++ break; ++ case 'd': ++ // 4 bytes ++ //*data = rtw_read32(padapter, addr); ++ sprintf(data, "%08x", rtw_read32(padapter, addr)); ++ //add read data format blank ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ if ( data[i] != '\0' ) ++ tmp[j] = data[i]; ++ ++ j++; ++ } ++ pch = tmp; ++ DBG_871X("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ if (!pnext) ++ break; ++ ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtout = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtout ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = strlen(extra); ++ break; ++ ++ default: ++ wrqu->length = 0; ++ ret = -EINVAL; ++ break; ++ ++ } ++ ++ return ret; ++} ++ ++/* ++ * Input Format: %d,%x,%x ++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS ++ * 1st %x is address(offset) ++ * 2st %x is data to write ++ */ ++ static int rtw_mp_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++/*static int rtw_mp_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++*/ ++ u32 path, addr, data; ++ int ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ char input[wrqu->length]; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ ++ ret = sscanf(input, "%d,%x,%x", &path, &addr, &data); ++ if (ret < 3) return -EINVAL; ++ ++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL; ++ if (addr > 0xFF) return -EINVAL; ++ if (data > 0xFFFFF) return -EINVAL; ++ ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ write_rfreg(padapter, path, addr, data); ++ ++ sprintf(extra, "write_rf completed \n"); ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++/* ++ * Input Format: %d,%x ++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS ++ * %x is address(offset) ++ * ++ * Return: ++ * %d for data readed ++ */ ++static int rtw_mp_read_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char input[wrqu->length]; ++ char *pch, *pnext, *ptmp; ++ char data[20],tmp[20]; ++ //u32 *data = (u32*)extra; ++ u32 path, addr; ++ u32 ret,i=0 ,j=0,strtou=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (wrqu->length > 128) return -EFAULT; ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ ret = sscanf(input, "%d,%x", &path, &addr); ++ if (ret < 2) return -EINVAL; ++ ++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL; ++ if (addr > 0xFF) return -EINVAL; ++ ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ //*data = read_rfreg(padapter, path, addr); ++ sprintf(data, "%08x", read_rfreg(padapter, path, addr)); ++ //add read data format blank ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ tmp[j] = data[i]; ++ j++; ++ } ++ pch = tmp; ++ DBG_871X("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtou = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtou ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_start(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 val8; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++#ifdef CONFIG_BT_COEXIST ++ PBT30Info pBTInfo; ++ PBT_MGNT pBtMgnt; ++ ++ pBTInfo = GET_BT_INFO(padapter); ++ pBtMgnt = &pBTInfo->BtMgnt; ++#endif ++ if(padapter->registrypriv.mp_mode ==0) ++ { ++ #ifdef CONFIG_RTL8723A ++ DBG_871X("_rtw_mp_xmit_priv for Download BT patch FW\n"); ++ _rtw_mp_xmit_priv(&padapter->xmitpriv); ++ #endif ++ ++ padapter->registrypriv.mp_mode =1; ++ rtw_pm_set_ips(padapter,IPS_NONE); ++ LeaveAllPowerSaveMode(padapter); ++ MPT_InitializeAdapter(padapter, 1); ++#ifdef CONFIG_BT_COEXIST ++ pHalData->bt_coexist.BluetoothCoexist = 0; ++ pBtMgnt->ExtConfig.bManualControl = _TRUE; ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); ++ BT_HaltProcess(padapter); ++ DBG_871X("Set disable BT_COEXIST\n"); ++ //padapter->registrypriv.mp_mode =0; ++ //pHalFunc->hal_init(padapter); ++ //padapter->registrypriv.mp_mode =1; ++ // Force to switch Antenna to WiFi ++ rtw_write16(padapter, 0x870, 0x300); ++ rtw_write16(padapter, 0x860, 0x110); ++#endif ++ } ++ ++ if (padapter->registrypriv.mp_mode == 0) ++ return -EPERM; ++ ++ if (padapter->mppriv.mode == MP_OFF) { ++ if (mp_start_test(padapter) == _FAIL) ++ return -EPERM; ++ padapter->mppriv.mode = MP_ON; ++ MPT_PwrCtlDM(padapter,0); ++ } ++ ++ return 0; ++} ++ ++static int rtw_mp_stop(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if(padapter->registrypriv.mp_mode ==1) ++ { ++ MPT_DeInitAdapter(padapter); ++ padapter->registrypriv.mp_mode=0; ++ DBG_871X("rtw_mp_stop -> registrypriv.mp_mode=%d ",padapter->registrypriv.mp_mode); ++ ++ if (padapter->mppriv.mode != MP_OFF) { ++ //mp_stop_test(padapter); ++ padapter->mppriv.mode = MP_OFF; ++ } ++ } ++ ++ return 0; ++} ++ ++extern int wifirate2_ratetbl_inx(unsigned char rate); ++ ++static int rtw_mp_rate(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 rate = MPT_RATE_1M; ++ u8 input[wrqu->length]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ rate = rtw_atoi(input); ++ sprintf( extra, "Set data rate to %d" , rate ); ++ ++ if(rate <= 0x7f) ++ rate = wifirate2_ratetbl_inx( (u8)rate); ++ else ++ rate =(rate-0x80+MPT_RATE_MCS0); ++ ++ //DBG_871X("%s: rate=%d\n", __func__, rate); ++ ++ if (rate >= MPT_RATE_LAST ) ++ return -EINVAL; ++ ++ padapter->mppriv.rateidx = rate; ++ Hal_SetDataRate(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_channel(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ u32 channel = 1; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ channel = rtw_atoi(input); ++ //DBG_871X("%s: channel=%d\n", __func__, channel); ++ sprintf( extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel ); ++ ++ padapter->mppriv.channel = channel; ++ Hal_SetChannel(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_bandwidth(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 bandwidth=0, sg=0; ++ //u8 buffer[40]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ //if (copy_from_user(buffer, (void*)wrqu->data.pointer, wrqu->data.length)) ++ // return -EFAULT; ++ ++ //DBG_871X("%s:iwpriv in=%s\n", __func__, extra); ++ ++ sscanf(extra, "40M=%d,shortGI=%d", &bandwidth, &sg); ++ ++ if (bandwidth != HT_CHANNEL_WIDTH_40) ++ bandwidth = HT_CHANNEL_WIDTH_20; ++ ++ //DBG_871X("%s: bw=%d sg=%d \n", __func__, bandwidth , sg); ++ ++ padapter->mppriv.bandwidth = (u8)bandwidth; ++ padapter->mppriv.preamble = sg; ++ ++ SetBandwidth(padapter); ++ ++ return 0; ++} ++ ++static int rtw_mp_txpower(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 idx_a=0,idx_b=0,MsetPower=1; ++ u8 input[wrqu->length]; ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ MsetPower = strncmp(input, "off", 3); ++ sscanf(input,"patha=%d,pathb=%d",&idx_a,&idx_b); ++ //DBG_871X("%s: tx_pwr_idx_a=%x b=%x\n", __func__, idx_a, idx_b); ++ if(MsetPower==0) ++ { ++ padapter->mppriv.bSetTxPower = 0; ++ sprintf( extra, "MP Set power off"); ++ } ++ else ++ { ++ sprintf( extra, "Set power level path_A:%d path_B:%d", idx_a , idx_b ); ++ padapter->mppriv.txpoweridx = (u8)idx_a; ++ padapter->mppriv.txpoweridx_b = (u8)idx_b; ++ padapter->mppriv.bSetTxPower = 1; ++ Hal_SetAntennaPathPower(padapter); ++ } ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_ant_tx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 i; ++ u8 input[wrqu->length]; ++ u16 antenna = 0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ //DBG_871X("%s: input=%s\n", __func__, input); ++ ++ sprintf( extra, "switch Tx antenna to %s", input ); ++ ++ for (i=0; i < strlen(input); i++) ++ { ++ switch(input[i]) ++ { ++ case 'a' : ++ antenna|=ANTENNA_A; ++ break; ++ case 'b': ++ antenna|=ANTENNA_B; ++ break; ++ } ++ } ++ //antenna |= BIT(extra[i]-'a'); ++ //DBG_871X("%s: antenna=0x%x\n", __func__, antenna); ++ padapter->mppriv.antenna_tx = antenna; ++ //DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx); ++ ++ Hal_SetAntenna(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_ant_rx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 i; ++ u16 antenna = 0; ++ u8 input[wrqu->length]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ //DBG_871X("%s: input=%s\n", __func__, input); ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ sprintf( extra, "switch Rx antenna to %s", input ); ++ ++ for (i=0; i < strlen(input); i++) { ++ ++ switch( input[i] ) ++ { ++ case 'a' : ++ antenna|=ANTENNA_A; ++ break; ++ case 'b': ++ antenna|=ANTENNA_B; ++ break; ++ } ++ } ++ ++ //DBG_871X("%s: antenna=0x%x\n", __func__, antenna); ++ padapter->mppriv.antenna_rx = antenna; ++ //DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx); ++ Hal_SetAntenna(padapter); ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_ctx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 pkTx = 1, countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1; ++ u32 bStartTest = 1; ++ u32 count = 0; ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ pmp_priv = &padapter->mppriv; ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_871X("%s: in=%s\n", __func__, extra); ++ ++ countPkTx = strncmp(extra, "count=", 5); // strncmp TRUE is 0 ++ cotuTx = strncmp(extra, "background", 20); ++ CarrSprTx = strncmp(extra, "background,cs", 20); ++ scTx = strncmp(extra, "background,sc", 20); ++ sgleTx = strncmp(extra, "background,stone", 20); ++ pkTx = strncmp(extra, "background,pkt", 20); ++ stop = strncmp(extra, "stop", 4); ++ sscanf(extra, "count=%d,pkt", &count); ++ ++ //DBG_871X("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop); ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ ++ if (stop == 0) { ++ bStartTest = 0; // To set Stop ++ pmp_priv->tx.stop = 1; ++ sprintf( extra, "Stop continuous Tx"); ++ } else { ++ bStartTest = 1; ++ if (pmp_priv->mode != MP_ON) { ++ if (pmp_priv->tx.stop != 1) { ++ DBG_871X("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode); ++ return -EFAULT; ++ } ++ } ++ } ++ ++ if (pkTx == 0 || countPkTx == 0) ++ pmp_priv->mode = MP_PACKET_TX; ++ if (sgleTx == 0) ++ pmp_priv->mode = MP_SINGLE_TONE_TX; ++ if (cotuTx == 0) ++ pmp_priv->mode = MP_CONTINUOUS_TX; ++ if (CarrSprTx == 0) ++ pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; ++ if (scTx == 0) ++ pmp_priv->mode = MP_SINGLE_CARRIER_TX; ++ ++ switch (pmp_priv->mode) ++ { ++ case MP_PACKET_TX: ++ ++ //DBG_871X("%s:pkTx %d\n", __func__,bStartTest); ++ if (bStartTest == 0) ++ { ++ pmp_priv->tx.stop = 1; ++ pmp_priv->mode = MP_ON; ++ sprintf( extra, "Stop continuous Tx"); ++ } ++ else if (pmp_priv->tx.stop == 1) ++ { ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 count=%u,\n",count); ++ //DBG_871X("%s:countPkTx %d\n", __func__,count); ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = count; ++ pmp_priv->tx.payload = 2; ++ pattrib = &pmp_priv->tx.attrib; ++ pattrib->pktlen = 1500; ++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); ++ SetPacketTx(padapter); ++ } ++ else { ++ //DBG_871X("%s: pkTx not stop\n", __func__); ++ return -EFAULT; ++ } ++ wrqu->length = strlen(extra); ++ return 0; ++ ++ case MP_SINGLE_TONE_TX: ++ //DBG_871X("%s: sgleTx %d \n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ } ++ Hal_SetSingleToneTx(padapter, (u8)bStartTest); ++ break; ++ ++ case MP_CONTINUOUS_TX: ++ //DBG_871X("%s: cotuTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ } ++ Hal_SetContinuousTx(padapter, (u8)bStartTest); ++ break; ++ ++ case MP_CARRIER_SUPPRISSION_TX: ++ //DBG_871X("%s: CarrSprTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ if( pmp_priv->rateidx <= MPT_RATE_11M ) ++ { ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ Hal_SetCarrierSuppressionTx(padapter, (u8)bStartTest); ++ }else ++ sprintf( extra, "Specify carrier suppression but not CCK rate"); ++ } ++ break; ++ ++ case MP_SINGLE_CARRIER_TX: ++ //DBG_871X("%s: scTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ } ++ Hal_SetSingleCarrierTx(padapter, (u8)bStartTest); ++ break; ++ ++ default: ++ //DBG_871X("%s:No Match MP_MODE\n", __func__); ++ sprintf( extra, "Error! Continuous-Tx is not on-going."); ++ return -EFAULT; ++ } ++ ++ if ( bStartTest==1 && pmp_priv->mode != MP_ON) { ++ struct mp_priv *pmp_priv = &padapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ //DBG_871X("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(padapter); ++ } else { ++ pmp_priv->mode = MP_ON; ++ } ++ ++ wrqu->length = strlen(extra); ++ return 0; ++} ++ ++ ++static int rtw_mp_disable_bt_coexist(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++ ++ u8 input[wrqu->data.length]; ++ u32 bt_coexist; ++ ++#ifdef CONFIG_BT_COEXIST ++ PBT30Info pBTInfo; ++ PBT_MGNT pBtMgnt; ++ ++ pBTInfo = GET_BT_INFO(padapter); ++ pBtMgnt = &pBTInfo->BtMgnt; ++#endif ++ if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) ++ return -EFAULT; ++ ++ bt_coexist = rtw_atoi(input); ++ ++ if( bt_coexist == 0 ) ++ { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n")); ++ DBG_871X("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n"); ++#ifdef CONFIG_BT_COEXIST ++ pHalData->bt_coexist.BluetoothCoexist = 0; ++ pBtMgnt->ExtConfig.bManualControl = _TRUE; ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); ++ BT_HaltProcess(padapter); ++#if 1 ++ padapter->registrypriv.mp_mode=0; ++ pHalFunc->hal_init(padapter); ++ padapter->registrypriv.mp_mode=1; ++#endif ++ // Force to switch Antenna to WiFi ++ rtw_write16(padapter, 0x870, 0x300); ++ rtw_write16(padapter, 0x860, 0x110); ++#endif ++ //BT_SetManualControl(pAdapter, TRUE); ++ } ++ else ++ { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("Set OID_RT_SET_DISABLE_BT_COEXIST: enable BT_COEXIST\n")); ++#ifdef CONFIG_BT_COEXIST ++ pBtMgnt->ExtConfig.bManualControl = _FALSE; ++#endif ++ //BT_SetManualControl(pAdapter, FALSE); ++ } ++ ++ return 0; ++} ++ ++ ++static int rtw_mp_arx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 bStartRx=0,bStopRx=0,bQueryPhy=0,bQueryMac=0; ++ u32 cckok=0,cckcrc=0,ofdmok=0,ofdmcrc=0,htok=0,htcrc=0,OFDM_FA=0,CCK_FA=0,DropPacket=0,vht_ok=0,vht_err=0; ++ u8 input[wrqu->length]; ++ u32 mac_cck_ok=0, mac_ofdm_ok=0, mac_ht_ok=0, mac_vht_ok=0; ++ u32 mac_cck_err=0, mac_ofdm_err=0, mac_ht_err=0, mac_vht_err=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_871X("%s: %s\n", __func__, input); ++ ++ bStartRx = (strncmp(input, "start", 5)==0)?1:0; // strncmp TRUE is 0 ++ bStopRx = (strncmp(input, "stop", 5)==0)?1:0; // strncmp TRUE is 0 ++ bQueryPhy = (strncmp(input, "phy", 3)==0)?1:0; // strncmp TRUE is 0 ++ bQueryMac = (strncmp(input, "mac", 3)==0)?1:0; // strncmp TRUE is 0 ++ ++ if(bStartRx) ++ { ++ sprintf( extra, "start"); ++ SetPacketRx(padapter, bStartRx); ++ } ++ else if(bStopRx) ++ { ++ SetPacketRx(padapter, 0); ++ sprintf( extra, "Received packet OK:%d CRC error:%d",padapter->mppriv.rx_pktcount,padapter->mppriv.rx_crcerrpktcount); ++ } ++ else if(bQueryPhy) ++ { ++ ++ //if (IS_HARDWARE_TYPE_JAGUAR(padapter)) ++ #ifdef CONFIG_RTL8188A ++ { ++ cckok = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF); // [13:0] ++ ofdmok = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF); // [13:0] ++ htok = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF); // [13:0] ++ vht_ok = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF); // [13:0] ++ ++ cckcrc = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF0000); // [29:16] ++ ofdmcrc = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF0000); // [29:16] ++ htcrc = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF0000); // [29:16] ++ vht_err = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF0000); // [29:16] ++ } ++ #else ++ { ++ cckok = PHY_QueryBBReg(padapter, 0xF88, bMaskDWord); ++ ofdmok = PHY_QueryBBReg(padapter, 0xF94, bMaskLWord); ++ htok = PHY_QueryBBReg(padapter, 0xF90, bMaskLWord); ++ vht_ok = 0; ++ ++ cckcrc = PHY_QueryBBReg(padapter, 0xF84, bMaskDWord); ++ ofdmcrc = PHY_QueryBBReg(padapter, 0xF94, bMaskHWord); ++ htcrc = PHY_QueryBBReg(padapter, 0xF90, bMaskHWord); ++ vht_err = 0; ++ } ++ #endif ++ CCK_FA=(rtw_read8(padapter, 0xa5b )<<8 ) | (rtw_read8(padapter, 0xa5c)); ++ sprintf( extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d",cckok+ofdmok+htok+vht_ok,cckcrc+ofdmcrc+htcrc+vht_err,OFDM_FA+CCK_FA); ++ } ++ else if(bQueryMac) ++ { ++ ++ // for 8723A ++ { ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x3); ++ mac_cck_ok = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x0); ++ mac_ofdm_ok = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x6); ++ mac_ht_ok = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ mac_vht_ok = 0; ++ ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x4); ++ mac_cck_err = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x1); ++ mac_ofdm_err = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ PHY_SetMacReg(padapter, 0x664, BIT28|BIT29|BIT30|BIT31, 0x7); ++ mac_ht_err = PHY_QueryMacReg(padapter, 0x664, bMaskLWord); // [15:0] ++ mac_vht_err = 0; ++ //Mac_DropPacket ++ rtw_write32(padapter, 0x664, (rtw_read32(padapter, 0x0664)& 0x0FFFFFFF)| Mac_DropPacket); ++ DropPacket = rtw_read32(padapter, 0x664)& 0x0000FFFF; ++ } ++ ++ sprintf( extra, "Mac Received packet OK: %d , CRC error: %d , FA Counter: %d , Drop Packets: %d\n", ++ mac_cck_ok+mac_ofdm_ok+mac_ht_ok+mac_vht_ok,mac_cck_err+mac_ofdm_err+mac_ht_err+mac_vht_err,OFDM_FA+CCK_FA,DropPacket); ++ } ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_trx_query(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 txok,txfail,rxok,rxfail; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ //if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) ++ // return -EFAULT; ++ ++ txok=padapter->mppriv.tx.sended; ++ txfail=0; ++ rxok = padapter->mppriv.rx_pktcount; ++ rxfail = padapter->mppriv.rx_crcerrpktcount; ++ ++ _rtw_memset(extra, '\0', 128); ++ ++ sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ", txok, txfail,rxok,rxfail); ++ ++ wrqu->length=strlen(extra)+1; ++ ++ return 0; ++} ++ ++static int rtw_mp_pwrtrk(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 enable; ++ u32 thermal; ++ s32 ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ _rtw_memset(extra, 0, wrqu->length); ++ ++ enable = 1; ++ if (wrqu->length > 1) { // not empty string ++ if (strncmp(input, "stop", 4) == 0) ++ { ++ enable = 0; ++ sprintf(extra, "mp tx power tracking stop"); ++ } ++ else if (sscanf(input, "ther=%d", &thermal)) { ++ ret = Hal_SetThermalMeter(padapter, (u8)thermal); ++ if (ret == _FAIL) return -EPERM; ++ sprintf(extra, "mp tx power tracking start,target value=%d ok ",thermal); ++ }else { ++ return -EINVAL; ++ } ++ } ++ ++ ret = Hal_SetPowerTracking(padapter, enable); ++ if (ret == _FAIL) return -EPERM; ++ ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_psd(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ strcpy(extra,input); ++ ++ wrqu->length = mp_query_psd(padapter, extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_thermal(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 val; ++ u16 bwrite=1; ++ ++ #if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) ++ u16 addr=EEPROM_THERMAL_METER; ++ #endif ++ #ifdef CONFIG_RTL8723A ++ u16 addr=EEPROM_THERMAL_METER_8723A; ++ #endif ++ #if defined(CONFIG_RTL8188E) ++ u16 addr=EEPROM_THERMAL_METER_88E; ++ #endif ++ ++ u16 cnt=1; ++ u16 max_available_size=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ //DBG_871X("print extra %s \n",extra); ++ ++ bwrite = strncmp(extra, "write", 6); // strncmp TRUE is 0 ++ ++ Hal_GetThermalMeter(padapter, &val); ++ ++ if( bwrite == 0 ) ++ { ++ //DBG_871X("to write val:%d",val); ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if( 2 > max_available_size ) ++ { ++ DBG_871X("no available efuse!\n"); ++ return -EFAULT; ++ } ++ if ( rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL ) ++ { ++ DBG_871X("rtw_efuse_map_write error \n"); ++ return -EFAULT; ++ } ++ else ++ { ++ sprintf(extra, " efuse write ok :%d", val); ++ } ++ } ++ else ++ { ++ sprintf(extra, "%d", val); ++ } ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_reset_stats(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ pmp_priv = &padapter->mppriv; ++ ++ pmp_priv->tx.sended = 0; ++ pmp_priv->tx_pktcount = 0; ++ pmp_priv->rx_pktcount = 0; ++ pmp_priv->rx_crcerrpktcount = 0; ++ ++ //reset phy counter ++ write_bbreg(padapter,0xf14,BIT16,0x1); ++ rtw_msleep_os(10); ++ write_bbreg(padapter,0xf14,BIT16,0x0); ++ //reset mac counter ++ PHY_SetMacReg(padapter, 0x664, BIT27, 0x1); ++ PHY_SetMacReg(padapter, 0x664, BIT27, 0x0); ++ return 0; ++} ++ ++static int rtw_mp_dump(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 value,i,j=1,path; ++ u8 input[wrqu->length]; ++ u8 rf_type,path_nums = 0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ ++ pmp_priv = &padapter->mppriv; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ if ( strncmp(input, "all", 4)==0 ) ++ { ++ printk("\n======= MAC REG =======\n"); ++ for ( i=0x0;i<0x300;i+=4 ) ++ { ++ if(j%4==1) printk("0x%02x ",i); ++ printk(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) printk("\n"); ++ } ++ for( i=0x400;i<0x1000;i+=4 ) ++ { ++ if(j%4==1) DBG_871X("0x%02x",i); ++ printk(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) printk("\n"); ++ } ++ ++ i,j=1; ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ bb_reg_dump(padapter); ++ rf_reg_dump(padapter); ++ /* ++ printk("\n======= RF REG =======\n"); ++ if(( RF_1T2R == rf_type ) ||( RF_1T1R ==rf_type )) ++ path_nums = 1; ++ else ++ path_nums = 2; ++ ++ for(path=0;pathlength]; ++ u32 valxcap; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_871X("%s:iwpriv in=%s\n", __func__, input); ++ ++ sscanf(input, "xcap=%d", &valxcap); ++ ++ Hal_ProSetCrystalCap( padapter , valxcap ); ++ ++ sprintf( extra, "Set xcap=%d",valxcap ); ++ wrqu->length = strlen(extra) + 1; ++ ++return 0; ++ ++} ++ ++static int rtw_mp_SetRFPath(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ char input[wrqu->data.length]; ++ u8 bMain=1,bTurnoff=1; ++ ++ if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) ++ return -EFAULT; ++ DBG_871X("%s:iwpriv in=%s\n", __func__, input); ++ ++ bMain = strncmp(input, "1", 2); // strncmp TRUE is 0 ++ bTurnoff = strncmp(input, "0", 3); // strncmp TRUE is 0 ++ ++ if(bMain==0) ++ { ++ MP_PHY_SetRFPathSwitch(padapter,_TRUE); ++ DBG_871X("%s:PHY_SetRFPathSwitch=TRUE\n", __func__); ++ } ++ else if(bTurnoff==0) ++ { ++ MP_PHY_SetRFPathSwitch(padapter,_FALSE); ++ DBG_871X("%s:PHY_SetRFPathSwitch=FALSE\n", __func__); ++ } ++ ++ return 0; ++} ++ ++static int rtw_mp_QueryDrv(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ char input[wrqu->data.length]; ++ u8 qAutoLoad=1; ++ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); ++ ++ if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) ++ return -EFAULT; ++ DBG_871X("%s:iwpriv in=%s\n", __func__, input); ++ ++ qAutoLoad = strncmp(input, "autoload", 8); // strncmp TRUE is 0 ++ ++ if(qAutoLoad==0) ++ { ++ DBG_871X("%s:qAutoLoad\n", __func__); ++ ++ if(pEEPROM->bautoload_fail_flag) ++ sprintf(extra, "fail"); ++ else ++ sprintf(extra, "ok"); ++ } ++ wrqu->data.length = strlen(extra) + 1; ++ return 0; ++} ++ ++/* update Tx AGC offset */ ++static int rtw_mp_antBdiff(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ ++ ++ // MPT_ProSetTxAGCOffset ++ return 0; ++} ++ ++ ++static int rtw_mp_PwrCtlDM(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ u8 bstart=1; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ bstart = strncmp(input, "start", 5); // strncmp TRUE is 0 ++ if(bstart==0){ ++ sprintf(extra, "PwrCtlDM start \n"); ++ MPT_PwrCtlDM(padapter,1); ++ }else{ ++ sprintf(extra, "PwrCtlDM stop \n"); ++ MPT_PwrCtlDM(padapter,0); ++ } ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_RTL8723A ++ ++/* update Tx AGC offset */ ++static int rtw_mp_SetBT(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++ ++ BT_REQ_CMD BtReq; ++ PMPT_CONTEXT pMptCtx=&(padapter->mppriv.MptCtx); ++ PBT_RSP_CMD pBtRsp=(PBT_RSP_CMD)&pMptCtx->mptOutBuf[0]; ++ char input[128]; ++ char *pch, *ptmp, *token, *tmp[2]={0x00,0x00}; ++ u8 setdata[100]; ++ u8 resetbt=0x00; ++ u8 H2cSetbtmac[6]; ++ ++ u16 testmode=1,ready=1,trxparam=1,setgen=1,getgen=1,testctrl=1,testbt=1,readtherm=1,setbtmac=1; ++ u32 i,ii,jj,kk,cnts,status; ++ PRT_FIRMWARE_8723A pBTFirmware = NULL; ++ ++ if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) ++ return -EFAULT; ++ if(strlen(extra)<1) return -EFAULT; ++ ++ DBG_871X("%s:iwpriv in=%s\n", __func__, extra); ++ ready = strncmp(extra, "ready", 5); ++ testmode = strncmp(extra, "testmode", 8); // strncmp TRUE is 0 ++ trxparam = strncmp(extra, "trxparam", 8); ++ setgen = strncmp(extra, "setgen", 6); ++ getgen = strncmp(extra, "getgen", 6); ++ testctrl = strncmp(extra, "testctrl", 8); ++ testbt = strncmp(extra, "testbt", 6); ++ readtherm = strncmp(extra, "readtherm", 9); ++ setbtmac = strncmp(extra, "setbtmac", 8); ++ ++ if ( strncmp(extra, "dlfw", 4) == 0) ++ { ++ padapter->registrypriv.mp_mode =0; ++ pHalFunc->hal_init(padapter); ++ padapter->registrypriv.mp_mode =1; ++ MPT_PwrCtlDM(padapter,0); ++ rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc)| 0x00000004)); ++ rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b)& 0xFFFFFFEF)); ++ rtw_msleep_os(600); ++ //rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE)); ++ rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b)| 0x00000010)); ++ rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc)& 0xFFFFFFFB)); ++ rtw_msleep_os(1200); ++ ++ DBG_871X("padapter->bBTFWReady == _FALSE rtl8723a_FirmwareDownload !\n"); ++ status = rtl8723a_FirmwareDownload(padapter); ++ #if 0 ++ FillH2CCmd(padapter, 0x32, 1, &resetbt); ++ rtw_msleep_os(1000); ++ ++ if(padapter->bBTFWReady == _FALSE && padapter->registrypriv.mp_mode == 1) ++ { ++ //pMptCtx->h2cReqNum=0; ++ DBG_871X("padapter->bBTFWReady == _FALSE rtl8723a_FirmwareDownload !\n"); ++ status = rtl8723a_FirmwareDownload(padapter); ++ } ++ else ++ { ++ pBTFirmware = (PRT_FIRMWARE_8723A)rtw_zmalloc(sizeof(RT_FIRMWARE_8723A)); ++ DBG_871X("rtl8723a_FirmwareDownload go to FirmwareDownloadBT !\n"); ++ FirmwareDownloadBT(padapter, pBTFirmware); ++ if (pBTFirmware) ++ rtw_mfree((u8*)pBTFirmware, sizeof(RT_FIRMWARE_8723A)); ++ } ++ #endif ++ DBG_871X("Wait for FirmwareDownloadBT fw boot!\n"); ++ rtw_msleep_os(1000); ++ _rtw_memset(extra,'\0', wrqu->data.length); ++ BtReq.opCodeVer=1; ++ BtReq.OpCode=0; ++ BtReq.paraLength=0; ++ mptbt_BtControlProcess(padapter,&BtReq); ++ rtw_msleep_os(100); ++ for (i=4; imptOutLen; i++) ++ { ++ DBG_8192C("FirmwareDownloadBT ready = 0x%x ", pMptCtx->mptOutBuf[i]); ++ if( (pMptCtx->mptOutBuf[i]==0x00) && (pMptCtx->mptOutBuf[i+1]==0x00)) ++ { ++ sprintf(extra, "download FW Fail.\n"); ++ } ++ else ++ { ++ sprintf(extra, "download FW OK.\n"); ++ goto exit; ++ } ++ } ++ ++ goto exit; ++ } ++ ++ if ( strncmp(extra, "down", 4) == 0){ ++ DBG_871X("SetBT down for to hal_init !\n"); ++ mp_stop_test(padapter); ++ pHalFunc->hal_init(padapter); ++ mp_start_test(padapter); ++ MPT_PwrCtlDM(padapter,0); ++ rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc)| 0x00000004)); ++ rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b)& 0xFFFFFFEF)); ++ rtw_msleep_os(600); ++ //rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE)); ++ rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b)| 0x00000010)); ++ rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc)& 0xFFFFFFFB)); ++ rtw_msleep_os(1200); ++ goto exit; ++ } ++ if ( strncmp(extra, "disable", 4) == 0){ ++ DBG_871X("SetBT enable !\n"); ++ rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFB)); ++ rtw_msleep_os(500); ++ goto exit; ++ } ++ if ( strncmp(extra, "enable", 4) == 0){ ++ DBG_871X("SetBT disable !\n"); ++ rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)| 0x00000004)); ++ rtw_msleep_os(500); ++ goto exit; ++ } ++ ++ if( ready!=0 && testmode!=0 && trxparam!=0 && setgen!=0 && getgen!=0 && testctrl!=0 && testbt!=0 && readtherm!=0 &&setbtmac!=0) ++ return -EFAULT; ++ ++ if( testbt==0 ) ++ { ++ BtReq.opCodeVer=1; ++ BtReq.OpCode=6; ++ BtReq.paraLength=cnts/2; ++ goto todo; ++ } ++ if( ready==0 ) ++ { ++ BtReq.opCodeVer=1; ++ BtReq.OpCode=0; ++ BtReq.paraLength=0; ++ goto todo; ++ } ++ ++ DBG_871X("%s:after strncmp\n", __func__); ++ pch = extra; ++ i = 0; ++ while ((token = strsep(&pch, ",")) != NULL) ++ { ++ if (i > 1) break; ++ tmp[i] = token; ++ i++; ++ } ++ ++ if ((tmp[0]==NULL) && (tmp[1]==NULL)) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ cnts = strlen(tmp[1]); ++ if (cnts<1) return -EFAULT; ++ ++ DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); ++ DBG_871X("%s: data=%s\n", __FUNCTION__, tmp[1]); ++ ++ for (jj=0, kk=0; jjdata.length); ++ ++ mptbt_BtControlProcess(padapter,&BtReq); ++ ++ if(readtherm==0){ ++ sprintf(extra,"BT thermal="); ++ for (i=4; imptOutLen; i++) ++ { ++ if( (pMptCtx->mptOutBuf[i]==0x00) && (pMptCtx->mptOutBuf[i+1]==0x00)) ++ goto exit; ++ DBG_8192C("0x%x ", pMptCtx->mptOutBuf[i]); ++ sprintf(extra, "%s %d ", extra, pMptCtx->mptOutBuf[i]); ++ } ++ }else{ ++ for (i=4; imptOutLen; i++) ++ { ++ DBG_8192C("0x%x ", pMptCtx->mptOutBuf[i]); ++ sprintf(extra, "%s 0x%x ", extra, pMptCtx->mptOutBuf[i]); ++ } ++ } ++ ++exit: ++ wrqu->data.length = strlen(extra) + 1; ++ ++return status; ++ ++} ++ ++#endif //#ifdef CONFIG_RTL8723A ++ ++static int rtw_mp_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ u32 subcmd = wrqu->flags; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (padapter == NULL) ++ { ++ return -ENETDOWN; ++ } ++ ++ if((padapter->bup == _FALSE )||(padapter->hw_init_completed == _FALSE)) ++ { ++ DBG_871X(" %s fail =>(padapter->bup == _FALSE )||(padapter->hw_init_completed == _FALSE) \n",__FUNCTION__); ++ return -ENETDOWN; ++ } ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ DBG_871X("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE) \n",__FUNCTION__); ++ return -ENETDOWN; ++ } ++ ++ //_rtw_memset(extra, 0x00, IW_PRIV_SIZE_MASK); ++ ++ if (extra == NULL) ++ { ++ wrqu->length = 0; ++ return -EIO; ++ } ++ ++ switch(subcmd) ++ { ++ case MP_START: ++ DBG_871X("set case mp_start \n"); ++ rtw_mp_start (dev,info,wrqu,extra); ++ break; ++ ++ case MP_STOP: ++ DBG_871X("set case mp_stop \n"); ++ rtw_mp_stop (dev,info,wrqu,extra); ++ break; ++ ++ case MP_BANDWIDTH: ++ DBG_871X("set case mp_bandwidth \n"); ++ rtw_mp_bandwidth (dev,info,wrqu,extra); ++ break; ++ ++ case MP_RESET_STATS: ++ DBG_871X("set case MP_RESET_STATS \n"); ++ rtw_mp_reset_stats (dev,info,wrqu,extra); ++ break; ++ case MP_SetRFPathSwh: ++ DBG_871X("set MP_SetRFPathSwitch \n"); ++ rtw_mp_SetRFPath (dev,info,wdata,extra); ++ break; ++ case CTA_TEST: ++ DBG_871X("set CTA_TEST\n"); ++ rtw_cta_test_start (dev, info, wdata, extra); ++ break; ++ case MP_DISABLE_BT_COEXIST: ++ DBG_871X("set case MP_DISABLE_BT_COEXIST \n"); ++ rtw_mp_disable_bt_coexist(dev, info, wdata, extra); ++ break; ++#ifdef CONFIG_WOWLAN ++ case MP_WOW_ENABLE: ++ DBG_871X("set case MP_WOW_ENABLE: %s \n", extra); ++ rtw_wowlan_ctrl(dev, info, wdata, extra); ++ break; ++#endif ++ } ++ ++ ++ return 0; ++} ++ ++ ++static int rtw_mp_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ u32 subcmd = wrqu->flags; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ //DBG_871X("in mp_get extra= %s \n",extra); ++ ++ if (padapter == NULL) ++ { ++ return -ENETDOWN; ++ } ++ if (extra == NULL) ++ { ++ wrqu->length = 0; ++ return -EIO; ++ } ++ ++ switch(subcmd) ++ { ++ case WRITE_REG : ++ rtw_mp_write_reg (dev,info,wrqu,extra); ++ break; ++ ++ case WRITE_RF: ++ rtw_mp_write_rf (dev,info,wrqu,extra); ++ break; ++ ++ case MP_PHYPARA: ++ DBG_871X("mp_get MP_PHYPARA \n"); ++ rtw_mp_phypara(dev,info,wrqu,extra); ++ break; ++ ++ case MP_CHANNEL: ++ DBG_871X("set case mp_channel \n"); ++ rtw_mp_channel (dev,info,wrqu,extra); ++ break; ++ ++ case READ_REG: ++ DBG_871X("mp_get READ_REG \n"); ++ rtw_mp_read_reg (dev,info,wrqu,extra); ++ break; ++ case READ_RF: ++ DBG_871X("mp_get READ_RF \n"); ++ rtw_mp_read_rf (dev,info,wrqu,extra); ++ break; ++ ++ case MP_RATE: ++ DBG_871X("set case mp_rate \n"); ++ rtw_mp_rate (dev,info,wrqu,extra); ++ break; ++ ++ case MP_TXPOWER: ++ DBG_871X("set case MP_TXPOWER \n"); ++ rtw_mp_txpower (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ANT_TX: ++ DBG_871X("set case MP_ANT_TX \n"); ++ rtw_mp_ant_tx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ANT_RX: ++ DBG_871X("set case MP_ANT_RX \n"); ++ rtw_mp_ant_rx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_QUERY: ++ //DBG_871X("mp_get mp_query MP_QUERY \n"); ++ rtw_mp_trx_query(dev,info,wrqu,extra); ++ break; ++ ++ case MP_CTX: ++ DBG_871X("set case MP_CTX \n"); ++ rtw_mp_ctx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ARX: ++ DBG_871X("set case MP_ARX \n"); ++ rtw_mp_arx (dev,info,wrqu,extra); ++ break; ++ ++ case EFUSE_GET: ++ DBG_871X("efuse get EFUSE_GET \n"); ++ rtw_mp_efuse_get(dev,info,wdata,extra); ++ break; ++ ++ case MP_DUMP: ++ DBG_871X("set case MP_DUMP \n"); ++ rtw_mp_dump (dev,info,wrqu,extra); ++ break; ++ case MP_PSD: ++ DBG_871X("set case MP_PSD \n"); ++ rtw_mp_psd (dev,info,wrqu,extra); ++ break; ++ case MP_THER: ++ DBG_871X("set case MP_THER \n"); ++ rtw_mp_thermal (dev,info,wrqu,extra); ++ break; ++ case MP_PwrCtlDM: ++ DBG_871X("set MP_PwrCtlDM\n"); ++ rtw_mp_PwrCtlDM (dev,info,wrqu,extra); ++ break; ++ case MP_QueryDrvStats: ++ DBG_871X("mp_get MP_QueryDrvStats \n"); ++ rtw_mp_QueryDrv (dev,info,wdata,extra); ++ break; ++ case MP_PWRTRK: ++ DBG_871X("set case MP_PWRTRK \n"); ++ rtw_mp_pwrtrk (dev,info,wrqu,extra); ++ break; ++ case EFUSE_SET: ++ DBG_871X("set case efuse set \n"); ++ rtw_mp_efuse_set (dev,info,wdata,extra); ++ break; ++ ++#ifdef CONFIG_RTL8723A ++ case MP_SetBT: ++ DBG_871X("set MP_SetBT \n"); ++ rtw_mp_SetBT (dev,info,wdata,extra); ++ break; ++#endif ++ ++ } ++ ++ rtw_msleep_os(10); //delay 5ms for sending pkt before exit adb shell operation ++return 0; ++} ++ ++#endif //#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++static int rtw_wfd_tdls_enable(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ if ( extra[ 0 ] == '0' ) ++ { ++ padapter->wdinfo.wfd_tdls_enable = 0; ++ } ++ else ++ { ++ padapter->wdinfo.wfd_tdls_enable = 1; ++ } ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_weaksec(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ u8 i, j; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ if ( extra[ 0 ] == '0' ) ++ { ++ padapter->wdinfo.wfd_tdls_weaksec = 0; ++ } ++ else ++ { ++ padapter->wdinfo.wfd_tdls_weaksec = 1; ++ } ++#endif ++ ++ return ret; ++} ++ ++ ++static int rtw_tdls_enable(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ _irqL irqL; ++ _list *plist, *phead; ++ s32 index; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 tdls_sta[NUM_STA][ETH_ALEN]; ++ u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; ++ ++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ _rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta)); ++ ++ if ( extra[ 0 ] == '0' ) ++ { ++ ptdlsinfo->enable = 0; ++ ++ if(pstapriv->asoc_sta_count==1) ++ return ret; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ for(index=0; index< NUM_STA; index++) ++ { ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); ++ ++ plist = get_next(plist); ++ ++ if(psta->tdls_sta_state != TDLS_STATE_NONE) ++ { ++ _rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN); ++ } ++ } ++ } ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(index=0; index< NUM_STA; index++) ++ { ++ if( !_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN) ) ++ { ++ printk("issue tear down to "MAC_FMT"\n", MAC_ARG(tdls_sta[index])); ++ issue_tdls_teardown(padapter, tdls_sta[index]); ++ } ++ } ++ rtw_tdls_cmd(padapter, myid(&(padapter->eeprompriv)), TDLS_RS_RCR); ++ rtw_reset_tdls_info(padapter); ++ } ++ else if ( extra[ 0 ] == '1' ) ++ { ++ ptdlsinfo->enable = 1; ++ } ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_setup(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ u8 i, j; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 mac_addr[ETH_ALEN]; ++ ++#ifdef CONFIG_WFD ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif // CONFIG_WFD ++ ++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++#ifdef CONFIG_WFD ++ if ( _AES_ != padapter->securitypriv.dot11PrivacyAlgrthm ) ++ { ++ // Weak Security situation with AP. ++ if ( 0 == pwdinfo->wfd_tdls_weaksec ) ++ { ++ // Can't send the tdls setup request out!! ++ DBG_871X( "[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__ ); ++ } ++ else ++ { ++ issue_tdls_setup_req(padapter, mac_addr); ++ } ++ } ++ else ++#endif // CONFIG_WFD ++ { ++ issue_tdls_setup_req(padapter, mac_addr); ++ } ++#endif ++ ++ return ret; ++} ++ ++static int rtw_tdls_teardown(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ u8 i,j; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sta_info *ptdls_sta = NULL; ++ u8 mac_addr[ETH_ALEN]; ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), mac_addr); ++ ++ if(ptdls_sta != NULL) ++ { ++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_UN_RSN_; ++ issue_tdls_teardown(padapter, mac_addr); ++ } ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_discovery(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ issue_tdls_dis_req(padapter, NULL); ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_ch_switch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ if( ptdls_sta == NULL ) ++ return ret; ++ ptdlsinfo->ch_sensing=1; ++ ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_INIT_CH_SEN); ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_pson(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 1); ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_psoff(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0); ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_setip(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; ++ u8 i=0, j=0, k=0, tag=0, ip[3] = { 0xff }, *ptr = extra; ++ ++ printk( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1 ); ++ ++ ++ while( i < 4 ) ++ { ++ for( j=0; j < 4; j++) ++ { ++ if( *( extra + j + tag ) == '.' || *( extra + j + tag ) == '\0' ) ++ { ++ if( j == 1 ) ++ pwfd_info->ip_address[i]=convert_ip_addr( '0', '0', *(extra+(j-1)+tag)); ++ if( j == 2 ) ++ pwfd_info->ip_address[i]=convert_ip_addr( '0', *(extra+(j-2)+tag), *(extra+(j-1)+tag)); ++ if( j == 3 ) ++ pwfd_info->ip_address[i]=convert_ip_addr( *(extra+(j-3)+tag), *(extra+(j-2)+tag), *(extra+(j-1)+tag)); ++ ++ tag += j + 1; ++ break; ++ } ++ } ++ i++; ++ } ++ ++ printk( "[%s] Set IP = %u.%u.%u.%u \n", __FUNCTION__, ++ ptdlsinfo->wfd_info->ip_address[0], ptdlsinfo->wfd_info->ip_address[1], ++ ptdlsinfo->wfd_info->ip_address[2], ptdlsinfo->wfd_info->ip_address[3] ++ ); ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_getip(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; ++ ++ printk( "[%s]\n", __FUNCTION__); ++ ++ sprintf( extra, "\n\n%u.%u.%u.%u\n", ++ pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], ++ pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3] ++ ); ++ ++ printk( "[%s] IP=%u.%u.%u.%u\n", __FUNCTION__, ++ pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], ++ pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3] ++ ); ++ ++ wrqu->data.length = strlen( extra ); ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls_getport(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; ++ ++ printk( "[%s]\n", __FUNCTION__); ++ ++ sprintf( extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport ); ++ printk( "[%s] remote port = %d\n", __FUNCTION__, pwfd_info->peer_rtsp_ctrlport ); ++ ++ wrqu->data.length = strlen( extra ); ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++ ++} ++ ++//WFDTDLS, for sigma test ++static int rtw_tdls_dis_result(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; ++ ++ printk( "[%s]\n", __FUNCTION__); ++ ++ if(ptdlsinfo->dev_discovered == 1 ) ++ { ++ sprintf( extra, "\n\nDis=1\n" ); ++ ptdlsinfo->dev_discovered = 0; ++ } ++ ++ wrqu->data.length = strlen( extra ); ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++ ++} ++ ++//WFDTDLS, for sigma test ++static int rtw_wfd_tdls_status(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_WFD ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; ++ ++ printk( "[%s]\n", __FUNCTION__); ++ ++ if(ptdlsinfo->setup_state == TDLS_LINKED_STATE ) ++ { ++ sprintf( extra, "\n\nStatus=1\n" ); ++ } ++ else ++ { ++ sprintf( extra, "\n\nStatus=0\n" ); ++ } ++ ++ wrqu->data.length = strlen( extra ); ++ ++#endif //CONFIG_WFD ++#endif //CONFIG_TDLS ++ ++ return ret; ++ ++} ++ ++static int rtw_tdls_ch_switch_off(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ ptdls_sta->tdls_sta_state |= TDLS_SW_OFF_STATE; ++/* ++ if((ptdls_sta->tdls_sta_state & TDLS_AT_OFF_CH_STATE) && (ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE)){ ++ pmlmeinfo->tdls_candidate_ch= pmlmeext->cur_channel; ++ issue_tdls_ch_switch_req(padapter, mac_addr); ++ DBG_871X("issue tdls ch switch req back to base channel\n"); ++ } ++*/ ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++static int rtw_tdls(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ // WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! ++ if ( _rtw_memcmp( extra, "wfdenable=", 10 ) ) ++ { ++ wrqu->data.length -=10; ++ rtw_wfd_tdls_enable( dev, info, wrqu, &extra[10] ); ++ return ret; ++ } ++ else if ( _rtw_memcmp( extra, "weaksec=", 8 ) ) ++ { ++ wrqu->data.length -=8; ++ rtw_tdls_weaksec( dev, info, wrqu, &extra[8] ); ++ return ret; ++ } ++ else if ( _rtw_memcmp( extra, "tdlsenable=", 11 ) ) ++ { ++ wrqu->data.length -=11; ++ rtw_tdls_enable( dev, info, wrqu, &extra[11] ); ++ return ret; ++ } ++ ++ if( padapter->tdlsinfo.enable == 0 ) ++ { ++ printk("tdls haven't enabled\n"); ++ return 0; ++ } ++ ++ if ( _rtw_memcmp( extra, "setup=", 6 ) ) ++ { ++ wrqu->data.length -=6; ++ rtw_tdls_setup( dev, info, wrqu, &extra[6] ); ++ } ++ else if (_rtw_memcmp( extra, "tear=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_tdls_teardown( dev, info, wrqu, &extra[5] ); ++ } ++ else if (_rtw_memcmp( extra, "dis=", 4 ) ) ++ { ++ wrqu->data.length -= 4; ++ rtw_tdls_discovery( dev, info, wrqu, &extra[4] ); ++ } ++ else if (_rtw_memcmp( extra, "sw=", 3 ) ) ++ { ++ wrqu->data.length -= 3; ++ rtw_tdls_ch_switch( dev, info, wrqu, &extra[3] ); ++ } ++ else if (_rtw_memcmp( extra, "swoff=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_tdls_ch_switch_off( dev, info, wrqu, &extra[6] ); ++ } ++ else if (_rtw_memcmp( extra, "pson=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_tdls_pson( dev, info, wrqu, &extra[5] ); ++ } ++ else if (_rtw_memcmp( extra, "psoff=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_tdls_psoff( dev, info, wrqu, &extra[6] ); ++ } ++#ifdef CONFIG_WFD ++ else if (_rtw_memcmp( extra, "setip=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_tdls_setip( dev, info, wrqu, &extra[6] ); ++ } ++ else if (_rtw_memcmp( extra, "tprobe=", 6 ) ) ++ { ++ issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev)); ++ } ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_TDLS ++ ++ return ret; ++} ++ ++ ++static int rtw_tdls_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_WFD ++ ++ DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); ++ ++ if ( _rtw_memcmp( wrqu->data.pointer, "ip", 2 ) ) ++ { ++ rtw_tdls_getip( dev, info, wrqu, extra ); ++ } ++ if ( _rtw_memcmp( wrqu->data.pointer, "port", 4 ) ) ++ { ++ rtw_tdls_getport( dev, info, wrqu, extra ); ++ } ++ //WFDTDLS, for sigma test ++ if ( _rtw_memcmp( wrqu->data.pointer, "dis", 3 ) ) ++ { ++ rtw_tdls_dis_result( dev, info, wrqu, extra ); ++ } ++ if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) ) ++ { ++ rtw_wfd_tdls_status( dev, info, wrqu, extra ); ++ } ++ ++#endif //CONFIG_WFD ++ ++ return ret; ++} ++ ++ ++ ++ ++ ++#ifdef CONFIG_INTEL_WIDI ++static int rtw_widi_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ process_intel_widi_cmd(padapter, extra); ++ ++ return ret; ++} ++ ++static int rtw_widi_set_probe_request(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ u8 *pbuf = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ pbuf = rtw_malloc(sizeof(l2_msg_t)); ++ if(pbuf) ++ { ++ copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length); ++ //_rtw_memcpy(pbuf, wrqu->data.pointer, wrqu->data.length); ++ ++ if( wrqu->data.flags == 0 ) ++ intel_widi_wk_cmd(padapter, INTEL_WIDI_ISSUE_PROB_WK, pbuf); ++ else if( wrqu->data.flags == 1 ) ++ rtw_set_wfd_rds_sink_info( padapter, (l2_msg_t *)pbuf ); ++ } ++ return ret; ++} ++#endif // CONFIG_INTEL_WIDI ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++ ++#ifdef CONFIG_RTL8723A ++extern void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++#define cal_txdesc_chksum rtl8723a_cal_txdesc_chksum ++extern void rtl8723a_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); ++#define fill_default_txdesc rtl8723a_fill_default_txdesc ++#elif defined(CONFIG_RTL8188E) ++#include ++extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum ++#ifdef CONFIG_SDIO_HCI ++extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); ++#define fill_default_txdesc rtl8188es_fill_default_txdesc ++#endif // CONFIG_SDIO_HCI ++#endif // CONFIG_RTL8188E ++ ++static s32 initLoopback(PADAPTER padapter) ++{ ++ PLOOPBACKDATA ploopback; ++ ++ ++ if (padapter->ploopback == NULL) { ++ ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA)); ++ if (ploopback == NULL) return -ENOMEM; ++ ++ _rtw_init_sema(&ploopback->sema, 0); ++ ploopback->bstop = _TRUE; ++ ploopback->cnt = 0; ++ ploopback->size = 300; ++ _rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg)); ++ ++ padapter->ploopback = ploopback; ++ } ++ ++ return 0; ++} ++ ++static void freeLoopback(PADAPTER padapter) ++{ ++ PLOOPBACKDATA ploopback; ++ ++ ++ ploopback = padapter->ploopback; ++ if (ploopback) { ++ rtw_mfree((u8*)ploopback, sizeof(LOOPBACKDATA)); ++ padapter->ploopback = NULL; ++ } ++} ++ ++static s32 initpseudoadhoc(PADAPTER padapter) ++{ ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; ++ s32 err; ++ ++ networkType = Ndis802_11IBSS; ++ err = rtw_set_802_11_infrastructure_mode(padapter, networkType); ++ if (err == _FALSE) return _FAIL; ++ ++ err = rtw_setopmode_cmd(padapter, networkType,_TRUE); ++ if (err == _FAIL) return _FAIL; ++ ++ return _SUCCESS; ++} ++ ++static s32 createpseudoadhoc(PADAPTER padapter) ++{ ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ struct mlme_priv *pmlmepriv; ++ NDIS_802_11_SSID *passoc_ssid; ++ WLAN_BSSID_EX *pdev_network; ++ u8 *pibss; ++ u8 ssid[] = "pseduo_ad-hoc"; ++ s32 err; ++ _irqL irqL; ++ ++ ++ pmlmepriv = &padapter->mlmepriv; ++ ++ authmode = Ndis802_11AuthModeOpen; ++ err = rtw_set_802_11_authentication_mode(padapter, authmode); ++ if (err == _FALSE) return _FAIL; ++ ++ passoc_ssid = &pmlmepriv->assoc_ssid; ++ _rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ passoc_ssid->SsidLength = sizeof(ssid) - 1; ++ _rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength); ++ ++ pdev_network = &padapter->registrypriv.dev_network; ++ pibss = padapter->registrypriv.dev_network.MacAddress; ++ _rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(padapter); ++ rtw_generate_random_ibss(pibss); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++#if 0 ++ err = rtw_createbss_cmd(padapter); ++ if (err == _FAIL) return _FAIL; ++#else ++{ ++ struct wlan_network *pcur_network; ++ struct sta_info *psta; ++ ++ //3 create a new psta ++ pcur_network = &pmlmepriv->cur_network; ++ ++ //clear psta in the cur_network, if any ++ psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); ++ if (psta) rtw_free_stainfo(padapter, psta); ++ ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pibss); ++ if (psta == NULL) return _FAIL; ++ ++ //3 join psudo AdHoc ++ pcur_network->join_res = 1; ++ pcur_network->aid = psta->aid = 1; ++ _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network)); ++ ++ // set msr to WIFI_FW_ADHOC_STATE ++#if 0 ++ Set_NETYPE0_MSR(padapter, WIFI_FW_ADHOC_STATE); ++#else ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(padapter, MSR); ++ val8 &= 0xFC; // clear NETYPE0 ++ val8 |= WIFI_FW_ADHOC_STATE & 0x3; ++ rtw_write8(padapter, MSR, val8); ++ } ++#endif ++} ++#endif ++ ++ return _SUCCESS; ++} ++ ++static struct xmit_frame* createloopbackpkt(PADAPTER padapter, u32 size) ++{ ++ struct xmit_priv *pxmitpriv; ++ struct xmit_frame *pframe; ++ struct xmit_buf *pxmitbuf; ++ struct pkt_attrib *pattrib; ++ struct tx_desc *desc; ++ u8 *pkt_start, *pkt_end, *ptr; ++ struct rtw_ieee80211_hdr *hdr; ++ s32 bmcast; ++ _irqL irqL; ++ ++ ++ if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ) return NULL; ++ ++ pxmitpriv = &padapter->xmitpriv; ++ pframe = NULL; ++ ++ //2 1. allocate xmit frame ++ pframe = rtw_alloc_xmitframe(pxmitpriv); ++ if (pframe == NULL) return NULL; ++ pframe->padapter = padapter; ++ ++ //2 2. allocate xmit buffer ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ if (pxmitbuf == NULL) { ++ rtw_free_xmitframe(pxmitpriv, pframe); ++ return NULL; ++ } ++ ++ pframe->pxmitbuf = pxmitbuf; ++ pframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pframe; ++ ++ //2 3. update_attrib() ++ pattrib = &pframe->attrib; ++ ++ // init xmitframe attribute ++ _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); ++ ++ pattrib->ether_type = 0x8723; ++ _rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++// pattrib->pctrl = 0; ++// pattrib->dhcp_pkt = 0; ++// pattrib->pktlen = 0; ++ pattrib->ack_policy = 0; ++// pattrib->pkt_hdrlen = ETH_HLEN; ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA; ++ pattrib->priority = 0; ++ pattrib->qsel = pattrib->priority; ++// do_queue_select(padapter, pattrib); ++ pattrib->nr_frags = 1; ++ pattrib->encrypt = 0; ++ pattrib->bswenc = _FALSE; ++ pattrib->qos_en = _FALSE; ++ ++ bmcast = IS_MCAST(pattrib->ra); ++ if (bmcast) { ++ pattrib->mac_id = 1; ++ pattrib->psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ pattrib->mac_id = 0; ++ pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ } ++ ++ pattrib->pktlen = size; ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; ++ ++ //2 4. fill TX descriptor ++ desc = (struct tx_desc*)pframe->buf_addr; ++ _rtw_memset(desc, 0, TXDESC_SIZE); ++ ++ fill_default_txdesc(pframe, (u8*)desc); ++ ++ // Hw set sequence number ++ ((PTXDESC)desc)->hwseq_en = 0; // HWSEQ_EN, 0:disable, 1:enable ++// ((PTXDESC)desc)->hwseq_sel = 0; // HWSEQ_SEL ++ ++ ((PTXDESC)desc)->disdatafb = 1; ++ ++ // convert to little endian ++ desc->txdw0 = cpu_to_le32(desc->txdw0); ++ desc->txdw1 = cpu_to_le32(desc->txdw1); ++ desc->txdw2 = cpu_to_le32(desc->txdw2); ++ desc->txdw3 = cpu_to_le32(desc->txdw3); ++ desc->txdw4 = cpu_to_le32(desc->txdw4); ++ desc->txdw5 = cpu_to_le32(desc->txdw5); ++ desc->txdw6 = cpu_to_le32(desc->txdw6); ++ desc->txdw7 = cpu_to_le32(desc->txdw7); ++#ifdef CONFIG_PCI_HCI ++ desc->txdw8 = cpu_to_le32(desc->txdw8); ++ desc->txdw9 = cpu_to_le32(desc->txdw9); ++ desc->txdw10 = cpu_to_le32(desc->txdw10); ++ desc->txdw11 = cpu_to_le32(desc->txdw11); ++ desc->txdw12 = cpu_to_le32(desc->txdw12); ++ desc->txdw13 = cpu_to_le32(desc->txdw13); ++ desc->txdw14 = cpu_to_le32(desc->txdw14); ++ desc->txdw15 = cpu_to_le32(desc->txdw15); ++#endif ++ ++ cal_txdesc_chksum(desc); ++ ++ //2 5. coalesce ++ pkt_start = pframe->buf_addr + TXDESC_SIZE; ++ pkt_end = pkt_start + pattrib->last_txcmdsz; ++ ++ //3 5.1. make wlan header, make_wlanhdr() ++ hdr = (struct rtw_ieee80211_hdr *)pkt_start; ++ SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); ++ _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA ++ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA ++ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID ++ ++ //3 5.2. make payload ++ ptr = pkt_start + pattrib->hdrlen; ++ get_random_bytes(ptr, pkt_end - ptr); ++ ++ pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; ++ pxmitbuf->ptail += pxmitbuf->len; ++ ++ return pframe; ++} ++ ++static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) ++{ ++ struct xmit_priv *pxmitpriv; ++ struct xmit_buf *pxmitbuf; ++ ++ ++ pxmitpriv = &padapter->xmitpriv; ++ pxmitbuf = pframe->pxmitbuf; ++ ++ rtw_free_xmitframe(pxmitpriv, pframe); ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++} ++ ++static void printdata(u8 *pbuf, u32 len) ++{ ++ u32 i, val; ++ ++ ++ for (i = 0; (i+4) <= len; i+=4) { ++ printk("%08X", *(u32*)(pbuf + i)); ++ if ((i+4) & 0x1F) printk(" "); ++ else printk("\n"); ++ } ++ ++ if (i < len) ++ { ++#ifdef CONFIG_BIG_ENDIAN ++ for (; i < len, i++) ++ printk("%02X", pbuf+i); ++#else // CONFIG_LITTLE_ENDIAN ++#if 0 ++ val = 0; ++ _rtw_memcpy(&val, pbuf + i, len - i); ++ printk("%8X", val); ++#else ++ u8 str[9]; ++ u8 n; ++ val = 0; ++ n = len - i; ++ _rtw_memcpy(&val, pbuf+i, n); ++ sprintf(str, "%08X", val); ++ n = (4 - n) * 2; ++ printk("%8s", str+n); ++#endif ++#endif // CONFIG_LITTLE_ENDIAN ++ } ++ printk("\n"); ++} ++ ++static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) ++{ ++ PHAL_DATA_TYPE phal; ++ struct recv_stat *prxstat; ++ struct recv_stat report; ++ PRXREPORT prxreport; ++ u32 drvinfosize; ++ u32 rxpktsize; ++ u8 fcssize; ++ u8 ret = _FALSE; ++ ++ prxstat = (struct recv_stat*)rxbuf; ++ report.rxdw0 = le32_to_cpu(prxstat->rxdw0); ++ report.rxdw1 = le32_to_cpu(prxstat->rxdw1); ++ report.rxdw2 = le32_to_cpu(prxstat->rxdw2); ++ report.rxdw3 = le32_to_cpu(prxstat->rxdw3); ++ report.rxdw4 = le32_to_cpu(prxstat->rxdw4); ++ report.rxdw5 = le32_to_cpu(prxstat->rxdw5); ++ ++ prxreport = (PRXREPORT)&report; ++ drvinfosize = prxreport->drvinfosize << 3; ++ rxpktsize = prxreport->pktlen; ++ ++ phal = GET_HAL_DATA(padapter); ++ if (phal->ReceiveConfig & RCR_APPFCS) fcssize = IEEE80211_FCS_LEN; ++ else fcssize = 0; ++ ++ if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) { ++ DBG_8192C("%s: ERROR! size not match tx/rx=%d/%d !\n", ++ __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize); ++ ret = _FALSE; ++ } else { ++ ret = _rtw_memcmp(txbuf + TXDESC_SIZE,\ ++ rxbuf + RXDESC_SIZE + drvinfosize,\ ++ txsz - TXDESC_SIZE); ++ if (ret == _FALSE) { ++ DBG_8192C("%s: ERROR! pkt content mismatch!\n", __func__); ++ } ++ } ++ ++ if (ret == _FALSE) ++ { ++ DBG_8192C("\n%s: TX PKT total=%d, desc=%d, content=%d\n", ++ __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE); ++ DBG_8192C("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE); ++ printdata(txbuf, TXDESC_SIZE); ++ DBG_8192C("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE); ++ printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE); ++ ++ DBG_8192C("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n", ++ __func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize); ++ if (rxpktsize != 0) ++ { ++ DBG_8192C("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE); ++ printdata(rxbuf, RXDESC_SIZE); ++ DBG_8192C("%s: RX drvinfo size=%d\n", __func__, drvinfosize); ++ printdata(rxbuf + RXDESC_SIZE, drvinfosize); ++ DBG_8192C("%s: RX content size=%d\n", __func__, rxpktsize); ++ printdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize); ++ } else { ++ DBG_8192C("%s: RX data size=%d\n", __func__, rxsz); ++ printdata(rxbuf, rxsz); ++ } ++ } ++ ++ return ret; ++} ++ ++thread_return lbk_thread(thread_context context) ++{ ++ s32 err; ++ PADAPTER padapter; ++ PLOOPBACKDATA ploopback; ++ struct xmit_frame *pxmitframe; ++ u32 cnt, ok, fail, headerlen; ++ u32 pktsize; ++ u32 ff_hwaddr; ++ ++ ++ padapter = (PADAPTER)context; ++ ploopback = padapter->ploopback; ++ if (ploopback == NULL) return -1; ++ cnt = 0; ++ ok = 0; ++ fail = 0; ++ ++ daemonize("%s", "RTW_LBK_THREAD"); ++ allow_signal(SIGTERM); ++ ++ do { ++ if (ploopback->size == 0) { ++ get_random_bytes(&pktsize, 4); ++ pktsize = (pktsize % 1535) + 1; // 1~1535 ++ } else ++ pktsize = ploopback->size; ++ ++ pxmitframe = createloopbackpkt(padapter, pktsize); ++ if (pxmitframe == NULL) { ++ sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!"); ++ break; ++ } ++ ++ ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz; ++ _rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize); ++ ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); ++ cnt++; ++ DBG_8192C("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize); ++ pxmitframe->pxmitbuf->pdata = ploopback->txbuf; ++ rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf); ++ ++ // wait for rx pkt ++ _rtw_down_sema(&ploopback->sema); ++ ++ err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize); ++ if (err == _TRUE) ++ ok++; ++ else ++ fail++; ++ ++ ploopback->txsize = 0; ++ _rtw_memset(ploopback->txbuf, 0, 0x8000); ++ ploopback->rxsize = 0; ++ _rtw_memset(ploopback->rxbuf, 0, 0x8000); ++ ++ freeloopbackpkt(padapter, pxmitframe); ++ pxmitframe = NULL; ++ ++ if (signal_pending(current)) { ++ flush_signals(current); ++ } ++ ++ if ((ploopback->bstop == _TRUE) || ++ ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) ++ { ++ u32 ok_rate, fail_rate, all; ++ all = cnt; ++ ok_rate = (ok*100)/all; ++ fail_rate = (fail*100)/all; ++ sprintf(ploopback->msg,\ ++ "loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)",\ ++ ok_rate, ok, all, fail_rate, fail, all); ++ break; ++ } ++ } while (1); ++ ++ ploopback->bstop = _TRUE; ++ ++ thread_exit(); ++} ++ ++static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8* pmsg) ++{ ++ PLOOPBACKDATA ploopback; ++ u32 len; ++ s32 err; ++ ++ ++ ploopback = padapter->ploopback; ++ ++ if (ploopback) ++ { ++ if (ploopback->bstop == _FALSE) { ++ ploopback->bstop = _TRUE; ++ _rtw_up_sema(&ploopback->sema); ++ } ++ len = 0; ++ do { ++ len = strlen(ploopback->msg); ++ if (len) break; ++ rtw_msleep_os(1); ++ } while (1); ++ _rtw_memcpy(pmsg, ploopback->msg, len+1); ++ freeLoopback(padapter); ++ ++ return; ++ } ++ ++ // disable dynamic algorithm ++ { ++ u32 DMFlag = DYNAMIC_FUNC_DISABLE; ++ rtw_hal_get_hwreg(padapter, HW_VAR_DM_FLAG, (u8*)&DMFlag); ++ } ++ ++ // create pseudo ad-hoc connection ++ err = initpseudoadhoc(padapter); ++ if (err == _FAIL) { ++ sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!"); ++ return; ++ } ++ ++ err = createpseudoadhoc(padapter); ++ if (err == _FAIL) { ++ sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!"); ++ return; ++ } ++ ++ err = initLoopback(padapter); ++ if (err) { ++ sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err); ++ return; ++ } ++ ++ ploopback = padapter->ploopback; ++ ++ ploopback->bstop = _FALSE; ++ ploopback->cnt = cnt; ++ ploopback->size = size; ++ ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD"); ++ if (IS_ERR(padapter->lbkthread)) ++ { ++ freeLoopback(padapter); ++ sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt); ++ return; ++ } ++ ++ sprintf(pmsg, "loopback start! cnt=%d", cnt); ++} ++#endif // CONFIG_MAC_LOOPBACK_DRIVER ++ ++static int rtw_test( ++ struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u32 len; ++ u8 *pbuf, *pch; ++ char *ptmp; ++ u8 *delim = ","; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ DBG_871X("+%s\n", __func__); ++ len = wrqu->data.length; ++ ++ pbuf = (u8*)rtw_zmalloc(len); ++ if (pbuf == NULL) { ++ DBG_871X("%s: no memory!\n", __func__); ++ return -ENOMEM; ++ } ++ ++ if (copy_from_user(pbuf, wrqu->data.pointer, len)) { ++ rtw_mfree(pbuf, len); ++ DBG_871X("%s: copy from user fail!\n", __func__); ++ return -EFAULT; ++ } ++ DBG_871X("%s: string=\"%s\"\n", __func__, pbuf); ++ ++ ptmp = (char*)pbuf; ++ pch = strsep(&ptmp, delim); ++ if ((pch == NULL) || (strlen(pch) == 0)) { ++ rtw_mfree(pbuf, len); ++ DBG_871X("%s: parameter error(level 1)!\n", __func__); ++ return -EFAULT; ++ } ++ ++#ifdef CONFIG_MAC_LOOPBACK_DRIVER ++ if (strcmp(pch, "loopback") == 0) ++ { ++ s32 cnt = 0; ++ u32 size = 64; ++ ++ pch = strsep(&ptmp, delim); ++ if ((pch == NULL) || (strlen(pch) == 0)) { ++ rtw_mfree(pbuf, len); ++ DBG_871X("%s: parameter error(level 2)!\n", __func__); ++ return -EFAULT; ++ } ++ ++ sscanf(pch, "%d", &cnt); ++ DBG_871X("%s: loopback cnt=%d\n", __func__, cnt); ++ ++ pch = strsep(&ptmp, delim); ++ if ((pch == NULL) || (strlen(pch) == 0)) { ++ rtw_mfree(pbuf, len); ++ DBG_871X("%s: parameter error(level 2)!\n", __func__); ++ return -EFAULT; ++ } ++ ++ sscanf(pch, "%d", &size); ++ DBG_871X("%s: loopback size=%d\n", __func__, size); ++ ++ loopbackTest(padapter, cnt, size, extra); ++ wrqu->data.length = strlen(extra) + 1; ++ ++ rtw_mfree(pbuf, len); ++ return 0; ++ } ++#endif ++ ++#ifdef CONFIG_RTL8723A ++#if 0 ++ if (strcmp(pch, "poweron") == 0) ++ { ++ s32 ret; ++ ++ ret = _InitPowerOn(padapter); ++ DBG_871X("%s: power on %s\n", __func__, (_FAIL==ret) ? "FAIL!":"OK."); ++ sprintf(extra, "Power ON %s", (_FAIL==ret) ? "FAIL!":"OK."); ++ wrqu->data.length = strlen(extra) + 1; ++ ++ rtw_mfree(pbuf, len); ++ return 0; ++ } ++ ++ if (strcmp(pch, "dlfw") == 0) ++ { ++ s32 ret; ++ ++ ret = rtl8723a_FirmwareDownload(padapter); ++ DBG_871X("%s: download FW %s\n", __func__, (_FAIL==ret) ? "FAIL!":"OK."); ++ sprintf(extra, "download FW %s", (_FAIL==ret) ? "FAIL!":"OK."); ++ wrqu->data.length = strlen(extra) + 1; ++ ++ rtw_mfree(pbuf, len); ++ return 0; ++ } ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++#define GET_BT_INFO(padapter) (&GET_HAL_DATA(padapter)->BtInfo) ++ ++ if (strcmp(pch, "btdbg") == 0) ++ { ++ DBG_8192C("===== BT debug information Start =====\n"); ++ DBG_8192C("WIFI status=\n"); ++ DBG_8192C("BT status=\n"); ++ DBG_8192C("BT profile=\n"); ++ DBG_8192C("WIFI RSSI=%d\n", GET_HAL_DATA(padapter)->dmpriv.UndecoratedSmoothedPWDB); ++ DBG_8192C("BT RSSI=\n"); ++ DBG_8192C("coex mechanism=\n"); ++ DBG_8192C("BT counter TX/RX=/\n"); ++ DBG_8192C("0x880=0x%08x\n", rtw_read32(padapter, 0x880)); ++ DBG_8192C("0x6c0=0x%08x\n", rtw_read32(padapter, 0x6c0)); ++ DBG_8192C("0x6c4=0x%08x\n", rtw_read32(padapter, 0x6c4)); ++ DBG_8192C("0x6c8=0x%08x\n", rtw_read32(padapter, 0x6c8)); ++ DBG_8192C("0x6cc=0x%08x\n", rtw_read32(padapter, 0x6cc)); ++ DBG_8192C("0x778=0x%08x\n", rtw_read32(padapter, 0x778)); ++ DBG_8192C("0xc50=0x%08x\n", rtw_read32(padapter, 0xc50)); ++ BT_DisplayBtCoexInfo(padapter); ++ DBG_8192C("===== BT debug information End =====\n"); ++ } ++ ++ if (strcmp(pch, "bton") == 0) ++ { ++ PBT30Info pBTInfo = GET_BT_INFO(padapter); ++ PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt; ++ ++ pBtMgnt->ExtConfig.bManualControl = _FALSE; ++ } ++ ++ if (strcmp(pch, "btoff") == 0) ++ { ++ PBT30Info pBTInfo = GET_BT_INFO(padapter); ++ PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt; ++ ++ pBtMgnt->ExtConfig.bManualControl = _TRUE; ++ } ++#endif // CONFIG_BT_COEXIST ++ ++ if (strcmp(pch, "h2c") == 0) ++ { ++ u8 param[6]; ++ u8 count = 0; ++ u32 tmp; ++ u8 i; ++ u32 pos; ++ s32 ret; ++ ++ ++ do { ++ pch = strsep(&ptmp, delim); ++ if ((pch == NULL) || (strlen(pch) == 0)) ++ break; ++ ++ sscanf(pch, "%x", &tmp); ++ param[count++] = (u8)tmp; ++ } while (count < 6); ++ ++ if (count == 0) { ++ rtw_mfree(pbuf, len); ++ DBG_8192C("%s: parameter error(level 2)!\n", __func__); ++ return -EFAULT; ++ } ++ ++ ret = FillH2CCmd(padapter, param[0], count-1, ¶m[1]); ++ ++ pos = sprintf(extra, "H2C ID=%x content=", param[0]); ++ for (i=0; idata.length = strlen(extra) + 1; ++ } ++#endif // CONFIG_RTL8723A ++ ++ rtw_mfree(pbuf, len); ++ return 0; ++} ++ ++static iw_handler rtw_handlers[] = ++{ ++ NULL, /* SIOCSIWCOMMIT */ ++ rtw_wx_get_name, /* SIOCGIWNAME */ ++ dummy, /* SIOCSIWNWID */ ++ dummy, /* SIOCGIWNWID */ ++ rtw_wx_set_freq, /* SIOCSIWFREQ */ ++ rtw_wx_get_freq, /* SIOCGIWFREQ */ ++ rtw_wx_set_mode, /* SIOCSIWMODE */ ++ rtw_wx_get_mode, /* SIOCGIWMODE */ ++ dummy, /* SIOCSIWSENS */ ++ rtw_wx_get_sens, /* SIOCGIWSENS */ ++ NULL, /* SIOCSIWRANGE */ ++ rtw_wx_get_range, /* SIOCGIWRANGE */ ++ rtw_wx_set_priv, /* SIOCSIWPRIV */ ++ NULL, /* SIOCGIWPRIV */ ++ NULL, /* SIOCSIWSTATS */ ++ NULL, /* SIOCGIWSTATS */ ++ dummy, /* SIOCSIWSPY */ ++ dummy, /* SIOCGIWSPY */ ++ NULL, /* SIOCGIWTHRSPY */ ++ NULL, /* SIOCWIWTHRSPY */ ++ rtw_wx_set_wap, /* SIOCSIWAP */ ++ rtw_wx_get_wap, /* SIOCGIWAP */ ++ rtw_wx_set_mlme, /* request MLME operation; uses struct iw_mlme */ ++ dummy, /* SIOCGIWAPLIST -- depricated */ ++ rtw_wx_set_scan, /* SIOCSIWSCAN */ ++ rtw_wx_get_scan, /* SIOCGIWSCAN */ ++ rtw_wx_set_essid, /* SIOCSIWESSID */ ++ rtw_wx_get_essid, /* SIOCGIWESSID */ ++ dummy, /* SIOCSIWNICKN */ ++ rtw_wx_get_nick, /* SIOCGIWNICKN */ ++ NULL, /* -- hole -- */ ++ NULL, /* -- hole -- */ ++ rtw_wx_set_rate, /* SIOCSIWRATE */ ++ rtw_wx_get_rate, /* SIOCGIWRATE */ ++ rtw_wx_set_rts, /* SIOCSIWRTS */ ++ rtw_wx_get_rts, /* SIOCGIWRTS */ ++ rtw_wx_set_frag, /* SIOCSIWFRAG */ ++ rtw_wx_get_frag, /* SIOCGIWFRAG */ ++ dummy, /* SIOCSIWTXPOW */ ++ dummy, /* SIOCGIWTXPOW */ ++ dummy, /* SIOCSIWRETRY */ ++ rtw_wx_get_retry, /* SIOCGIWRETRY */ ++ rtw_wx_set_enc, /* SIOCSIWENCODE */ ++ rtw_wx_get_enc, /* SIOCGIWENCODE */ ++ dummy, /* SIOCSIWPOWER */ ++ rtw_wx_get_power, /* SIOCGIWPOWER */ ++ NULL, /*---hole---*/ ++ NULL, /*---hole---*/ ++ rtw_wx_set_gen_ie, /* SIOCSIWGENIE */ ++ NULL, /* SIOCGWGENIE */ ++ rtw_wx_set_auth, /* SIOCSIWAUTH */ ++ NULL, /* SIOCGIWAUTH */ ++ rtw_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ ++ NULL, /* SIOCGIWENCODEEXT */ ++ rtw_wx_set_pmkid, /* SIOCSIWPMKSA */ ++ NULL, /*---hole---*/ ++}; ++ ++#if 0 ++//defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++static const struct iw_priv_args rtw_private_args[] = ++{ ++ { SIOCIWFIRSTPRIV + 0x00, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set ++ { SIOCIWFIRSTPRIV + 0x01, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get ++/* --- sub-ioctls definitions --- */ ++ { MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, //set ++ { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get ++ { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, //set ++ { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get ++ { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, //set ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get ++ { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"}, ++ { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, ++ { WRITE_REG, IW_PRIV_TYPE_CHAR | 1024, 0,"write_reg"},//set ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL" }, ++ { WRITE_RF, IW_PRIV_TYPE_CHAR | 1024, 0,"write_rf"},//set ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, ++ { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set" }, ++ { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, ++ { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_pwrtrk"}, ++ { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, ++ { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl ++ { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_setrfpath" }, ++ ++#ifdef CONFIG_RTL8723A ++ { MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" }, ++#endif ++ ++ { SIOCIWFIRSTPRIV + 0x02, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "test"},//set ++}; ++ ++ ++static iw_handler rtw_private_handler[] = ++{ ++ rtw_mp_set, ++ rtw_mp_get, ++}; ++ ++#else // not inlucde MP ++ ++static const struct iw_priv_args rtw_private_args[] = { ++ { ++ SIOCIWFIRSTPRIV + 0x0, ++ IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x1, ++ IW_PRIV_TYPE_CHAR | 0x7FF, ++ IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x4, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x5, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x6, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start" ++ }, ++//for PLATFORM_MT53XX ++ { ++ SIOCIWFIRSTPRIV + 0x7, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x8, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x9, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie" ++ }, ++ ++//for RTK_DMP_PLATFORM ++ { ++ SIOCIWFIRSTPRIV + 0xA, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan" ++ }, ++ ++ { ++ SIOCIWFIRSTPRIV + 0xB, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0xC, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0xD, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x10, ++ IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x11, ++ IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x13, ++ IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x14, ++ IW_PRIV_TYPE_CHAR | 64, 0, "tdls" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x15, ++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | P2P_PRIVATE_IOCTL_SET_LEN , "tdls_get" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x16, ++ IW_PRIV_TYPE_CHAR | 64, 0, "pm_set" ++ }, ++ ++ {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, ++ ++ {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set"}, ++ {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"}, ++ { ++ SIOCIWFIRSTPRIV + 0x1D, ++ IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test" ++ }, ++ ++#ifdef CONFIG_INTEL_WIDI ++ { ++ SIOCIWFIRSTPRIV + 0x1E, ++ IW_PRIV_TYPE_CHAR | 1024, 0, "widi_set" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x1F, ++ IW_PRIV_TYPE_CHAR | 128, 0, "widi_prob_req" ++ }, ++#endif // CONFIG_INTEL_WIDI ++ ++#ifdef CONFIG_MP_INCLUDED ++ ++ { SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set ++ { SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get ++/* --- sub-ioctls definitions --- */ ++ ++ { MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, //set ++ { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get ++ { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, //set ++ { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get ++ { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, //set ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get ++ { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"}, ++ { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get ++ { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, ++ { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, ++ { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, ++ { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, ++ { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, ++ { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, ++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, ++ { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, ++ { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, ++ { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, ++ { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, ++ { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, ++ { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, ++ { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, ++ { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_pwrtrk"}, ++ { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, ++ { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl ++ { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_setrfpath" }, ++ { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, ++#ifdef CONFIG_RTL8723A ++ { MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" }, ++ { MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"}, ++#endif ++ { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, ++#endif ++#ifdef CONFIG_WOWLAN ++ { MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_enable" }, //set ++#endif ++}; ++ ++static iw_handler rtw_private_handler[] = ++{ ++ rtw_wx_write32, //0x00 ++ rtw_wx_read32, //0x01 ++ rtw_drvext_hdl, //0x02 ++ rtw_mp_ioctl_hdl, //0x03 ++ ++// for MM DTV platform ++ rtw_get_ap_info, //0x04 ++ ++ rtw_set_pid, //0x05 ++ rtw_wps_start, //0x06 ++ ++// for PLATFORM_MT53XX ++ rtw_wx_get_sensitivity, //0x07 ++ rtw_wx_set_mtk_wps_probe_ie, //0x08 ++ rtw_wx_set_mtk_wps_ie, //0x09 ++ ++// for RTK_DMP_PLATFORM ++// Set Channel depend on the country code ++ rtw_wx_set_channel_plan, //0x0A ++ ++ rtw_dbg_port, //0x0B ++ rtw_wx_write_rf, //0x0C ++ rtw_wx_read_rf, //0x0D ++ ++#ifndef CONFIG_MP_INCLUDED ++ rtw_wx_priv_null, //0x0E ++ rtw_wx_priv_null, //0x0F ++#else ++ rtw_mp_set, //0x0E ++ rtw_mp_get, //0x0F ++#endif ++ rtw_p2p_set, //0x10 ++ rtw_p2p_get, //0x11 ++ NULL, //0x12 ++ rtw_p2p_get2, //0x13 ++ ++ rtw_tdls, //0x14 ++ rtw_tdls_get, //0x15 ++ ++ rtw_pm_set, //0x16 ++ rtw_wx_priv_null, //0x17 ++ rtw_rereg_nd_name, //0x18 ++ rtw_wx_priv_null, //0x19 ++ ++ rtw_mp_efuse_set, //0x1A ++ rtw_mp_efuse_get, //0x1B ++ NULL, // 0x1C is reserved for hostapd ++ rtw_test, // 0x1D ++#ifdef CONFIG_INTEL_WIDI ++ rtw_widi_set, //0x1E ++ rtw_widi_set_probe_request, //0x1F ++#endif // CONFIG_INTEL_WIDI ++}; ++ ++#endif // #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++#if WIRELESS_EXT >= 17 ++static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_statistics *piwstats=&padapter->iwstats; ++ int tmp_level = 0; ++ int tmp_qual = 0; ++ int tmp_noise = 0; ++ ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) ++ { ++ piwstats->qual.qual = 0; ++ piwstats->qual.level = 0; ++ piwstats->qual.noise = 0; ++ //DBG_871X("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); ++ } ++ else{ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); ++ #else ++ tmp_level = padapter->recvpriv.signal_strength; ++ #ifdef CONFIG_BT_COEXIST ++ { ++ u8 signal = (u8)tmp_level; ++ BT_SignalCompensation(padapter, &signal, NULL); ++ tmp_level= signal; ++ } ++ #endif // CONFIG_BT_COEXIST ++ #endif ++ ++ tmp_qual = padapter->recvpriv.signal_qual; ++ tmp_noise =padapter->recvpriv.noise; ++ //DBG_871X("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); ++ ++ piwstats->qual.level = tmp_level; ++ piwstats->qual.qual = tmp_qual; ++ piwstats->qual.noise = tmp_noise; ++ } ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) ++ piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;//|IW_QUAL_DBM; ++#else ++#ifdef RTK_DMP_PLATFORM ++ //IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. ++ //remove this flag for show percentage 0~100 ++ piwstats->qual.updated = 0x07; ++#else ++ piwstats->qual.updated = 0x0f; ++#endif ++#endif ++ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM; ++ #endif ++ ++ return &padapter->iwstats; ++} ++#endif ++ ++#ifdef CONFIG_WIRELESS_EXT ++struct iw_handler_def rtw_handlers_def = ++{ ++ .standard = rtw_handlers, ++ .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler), ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)) || defined(CONFIG_WEXT_PRIV) ++ .private = rtw_private_handler, ++ .private_args = (struct iw_priv_args *)rtw_private_args, ++ .num_private = sizeof(rtw_private_handler) / sizeof(iw_handler), ++ .num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args), ++#endif ++#if WIRELESS_EXT >= 17 ++ .get_wireless_stats = rtw_get_wireless_stats, ++#endif ++}; ++#endif ++ ++// copy from net/wireless/wext.c start ++/* ---------------------------------------------------------------- */ ++/* ++ * Calculate size of private arguments ++ */ ++static const char iw_priv_type_size[] = { ++ 0, /* IW_PRIV_TYPE_NONE */ ++ 1, /* IW_PRIV_TYPE_BYTE */ ++ 1, /* IW_PRIV_TYPE_CHAR */ ++ 0, /* Not defined */ ++ sizeof(__u32), /* IW_PRIV_TYPE_INT */ ++ sizeof(struct iw_freq), /* IW_PRIV_TYPE_FLOAT */ ++ sizeof(struct sockaddr), /* IW_PRIV_TYPE_ADDR */ ++ 0, /* Not defined */ ++}; ++ ++static int get_priv_size(__u16 args) ++{ ++ int num = args & IW_PRIV_SIZE_MASK; ++ int type = (args & IW_PRIV_TYPE_MASK) >> 12; ++ ++ return num * iw_priv_type_size[type]; ++} ++// copy from net/wireless/wext.c end ++ ++static int rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data) ++{ ++ int err = 0; ++ u8 *input = NULL; ++ u32 input_len = 0; ++ const char delim[] = " "; ++ u8 *output = NULL; ++ u32 output_len = 0; ++ u32 count = 0; ++ u8 *buffer= NULL; ++ u32 buffer_len = 0; ++ char *ptr = NULL; ++ u8 cmdname[17] = {0}; // IFNAMSIZ+1 ++ u32 cmdlen; ++ s32 len; ++ u8 *extra = NULL; ++ u32 extra_size = 0; ++ ++ s32 k; ++ const iw_handler *priv; /* Private ioctl */ ++ const struct iw_priv_args *priv_args; /* Private ioctl description */ ++ u32 num_priv; /* Number of ioctl */ ++ u32 num_priv_args; /* Number of descriptions */ ++ iw_handler handler; ++ int temp; ++ int subcmd = 0; /* sub-ioctl index */ ++ int offset = 0; /* Space for sub-ioctl index */ ++ ++ union iwreq_data wdata; ++ ++ ++ _rtw_memcpy(&wdata, wrq_data, sizeof(wdata)); ++ ++ input_len = wdata.data.length; ++ input = rtw_zmalloc(input_len); ++ if (NULL == input) ++ return -ENOMEM; ++ if (copy_from_user(input, wdata.data.pointer, input_len)) { ++ err = -EFAULT; ++ goto exit; ++ } ++ ptr = input; ++ len = input_len; ++ ++ sscanf(ptr, "%16s", cmdname); ++ cmdlen = strlen(cmdname); ++ DBG_8192C("%s: cmd=%s\n", __func__, cmdname); ++ ++ // skip command string ++ if (cmdlen > 0) ++ cmdlen += 1; // skip one space ++ ptr += cmdlen; ++ len -= cmdlen; ++ DBG_8192C("%s: parameters=%s\n", __func__, ptr); ++ ++ priv = rtw_private_handler; ++ priv_args = rtw_private_args; ++ num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler); ++ num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args); ++ ++ if (num_priv_args == 0) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ /* Search the correct ioctl */ ++ k = -1; ++ while((++k < num_priv_args) && strcmp(priv_args[k].name, cmdname)); ++ ++ /* If not found... */ ++ if (k == num_priv_args) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ /* Watch out for sub-ioctls ! */ ++ if (priv_args[k].cmd < SIOCDEVPRIVATE) ++ { ++ int j = -1; ++ ++ /* Find the matching *real* ioctl */ ++ while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') || ++ (priv_args[j].set_args != priv_args[k].set_args) || ++ (priv_args[j].get_args != priv_args[k].get_args))); ++ ++ /* If not found... */ ++ if (j == num_priv_args) { ++ err = -EINVAL; ++ goto exit; ++ } ++ ++ /* Save sub-ioctl number */ ++ subcmd = priv_args[k].cmd; ++ /* Reserve one int (simplify alignment issues) */ ++ offset = sizeof(__u32); ++ /* Use real ioctl definition from now on */ ++ k = j; ++ } ++ ++ buffer = rtw_zmalloc(4096); ++ if (NULL == buffer) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ /* If we have to set some data */ ++ if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && ++ (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) ++ { ++ u8 *str; ++ ++ switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) ++ { ++ case IW_PRIV_TYPE_BYTE: ++ /* Fetch args */ ++ count = 0; ++ do { ++ str = strsep(&ptr, delim); ++ if (NULL == str) break; ++ sscanf(str, "%i", &temp); ++ buffer[count++] = (u8)temp; ++ } while (1); ++ buffer_len = count; ++ ++ /* Number of args to fetch */ ++ wdata.data.length = count; ++ if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) ++ wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; ++ ++ break; ++ ++ case IW_PRIV_TYPE_INT: ++ /* Fetch args */ ++ count = 0; ++ do { ++ str = strsep(&ptr, delim); ++ if (NULL == str) break; ++ sscanf(str, "%i", &temp); ++ ((s32*)buffer)[count++] = (s32)temp; ++ } while (1); ++ buffer_len = count * sizeof(s32); ++ ++ /* Number of args to fetch */ ++ wdata.data.length = count; ++ if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) ++ wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; ++ ++ break; ++ ++ case IW_PRIV_TYPE_CHAR: ++ if (len > 0) ++ { ++ /* Size of the string to fetch */ ++ wdata.data.length = len; ++ if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) ++ wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; ++ ++ /* Fetch string */ ++ _rtw_memcpy(buffer, ptr, wdata.data.length); ++ } ++ else ++ { ++ wdata.data.length = 1; ++ buffer[0] = '\0'; ++ } ++ buffer_len = wdata.data.length; ++ break; ++ ++ default: ++ DBG_8192C("%s: Not yet implemented...\n", __func__); ++ err = -1; ++ goto exit; ++ } ++ ++ if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && ++ (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) ++ { ++ DBG_8192C("%s: The command %s needs exactly %d argument(s)...\n", ++ __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); ++ err = -EINVAL; ++ goto exit; ++ } ++ } /* if args to set */ ++ else ++ { ++ wdata.data.length = 0L; ++ } ++ ++ /* Those two tests are important. They define how the driver ++ * will have to handle the data */ ++ if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && ++ ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) ++ { ++ /* First case : all SET args fit within wrq */ ++ if (offset) ++ wdata.mode = subcmd; ++ _rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset); ++ } ++ else ++ { ++ if ((priv_args[k].set_args == 0) && ++ (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && ++ (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) ++ { ++ /* Second case : no SET args, GET args fit within wrq */ ++ if (offset) ++ wdata.mode = subcmd; ++ } ++ else ++ { ++ /* Third case : args won't fit in wrq, or variable number of args */ ++ if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) { ++ err = -EFAULT; ++ goto exit; ++ } ++ wdata.data.flags = subcmd; ++ } ++ } ++ ++ rtw_mfree(input, input_len); ++ input = NULL; ++ ++ extra_size = 0; ++ if (IW_IS_SET(priv_args[k].cmd)) ++ { ++ /* Size of set arguments */ ++ extra_size = get_priv_size(priv_args[k].set_args); ++ ++ /* Does it fits in iwr ? */ ++ if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && ++ ((extra_size + offset) <= IFNAMSIZ)) ++ extra_size = 0; ++ } else { ++ /* Size of get arguments */ ++ extra_size = get_priv_size(priv_args[k].get_args); ++ ++ /* Does it fits in iwr ? */ ++ if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && ++ (extra_size <= IFNAMSIZ)) ++ extra_size = 0; ++ } ++ ++ if (extra_size == 0) { ++ extra = (u8*)&wdata; ++ rtw_mfree(buffer, 4096); ++ buffer = NULL; ++ } else ++ extra = buffer; ++ ++ handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV]; ++ err = handler(dev, NULL, &wdata, extra); ++ ++ /* If we have to get some data */ ++ if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) && ++ (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) ++ { ++ int j; ++ int n = 0; /* number of args */ ++ u8 str[20] = {0}; ++ ++ /* Check where is the returned data */ ++ if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && ++ (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) ++ n = priv_args[k].get_args & IW_PRIV_SIZE_MASK; ++ else ++ n = wdata.data.length; ++ ++ output = rtw_zmalloc(4096); ++ if (NULL == output) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) ++ { ++ case IW_PRIV_TYPE_BYTE: ++ /* Display args */ ++ for (j = 0; j < n; j++) ++ { ++ sprintf(str, "%d ", extra[j]); ++ len = strlen(str); ++ output_len = strlen(output); ++ if ((output_len + len + 1) > 4096) { ++ err = -E2BIG; ++ goto exit; ++ } ++ _rtw_memcpy(output+output_len, str, len); ++ } ++ break; ++ ++ case IW_PRIV_TYPE_INT: ++ /* Display args */ ++ for (j = 0; j < n; j++) ++ { ++ sprintf(str, "%d ", ((__s32*)extra)[j]); ++ len = strlen(str); ++ output_len = strlen(output); ++ if ((output_len + len + 1) > 4096) { ++ err = -E2BIG; ++ goto exit; ++ } ++ _rtw_memcpy(output+output_len, str, len); ++ } ++ break; ++ ++ case IW_PRIV_TYPE_CHAR: ++ /* Display args */ ++ _rtw_memcpy(output, extra, n); ++ break; ++ ++ default: ++ DBG_8192C("%s: Not yet implemented...\n", __func__); ++ err = -1; ++ goto exit; ++ } ++ ++ output_len = strlen(output) + 1; ++ wrq_data->data.length = output_len; ++ if (copy_to_user(wrq_data->data.pointer, output, output_len)) { ++ err = -EFAULT; ++ goto exit; ++ } ++ } /* if args to set */ ++ else ++ { ++ wrq_data->data.length = 0; ++ } ++ ++exit: ++ if (input) ++ rtw_mfree(input, input_len); ++ if (buffer) ++ rtw_mfree(buffer, 4096); ++ if (output) ++ rtw_mfree(output, 4096); ++ ++ return err; ++} ++ ++#include ++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct iwreq *wrq = (struct iwreq *)rq; ++ int ret=0; ++ ++ switch (cmd) ++ { ++ case RTL_IOCTL_WPA_SUPPLICANT: ++ ret = wpa_supplicant_ioctl(dev, &wrq->u.data); ++ break; ++#ifdef CONFIG_AP_MODE ++ case RTL_IOCTL_HOSTAPD: ++ ret = rtw_hostapd_ioctl(dev, &wrq->u.data); ++ break; ++#ifdef CONFIG_NO_WIRELESS_HANDLERS ++ case SIOCSIWMODE: ++ ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL); ++ break; ++#endif ++#endif // CONFIG_AP_MODE ++ case SIOCDEVPRIVATE: ++ ret = rtw_ioctl_wext_private(dev, &wrq->u); ++ break; ++ case (SIOCDEVPRIVATE+1): ++ ret = rtw_android_priv_cmd(dev, rq, cmd); ++ break; ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ return ret; ++} +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/mlme_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/mlme_linux.c +new file mode 100644 +index 00000000..58c466bb +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/mlme_linux.c +@@ -0,0 +1,620 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _MLME_OSDEP_C_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef RTK_DMP_PLATFORM ++void Linkup_workitem_callback(struct work_struct *work) ++{ ++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem); ++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkup_workitem_callback\n")); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP); ++#endif ++ ++_func_exit_; ++} ++ ++void Linkdown_workitem_callback(struct work_struct *work) ++{ ++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem); ++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkdown_workitem_callback\n")); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN); ++#endif ++ ++_func_exit_; ++} ++#endif ++ ++ ++/* ++void sitesurvey_ctrl_handler(void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ ++ _sitesurvey_ctrl_handler(adapter); ++ ++ _set_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer, 3000); ++} ++*/ ++ ++void rtw_join_timeout_handler (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ _rtw_join_timeout_handler(adapter); ++} ++ ++ ++void _rtw_scan_timeout_handler (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ rtw_scan_timeout_handler(adapter); ++} ++ ++ ++void _dynamic_check_timer_handlder (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++/* remove for MP power tracking DM. ++#if (MP_DRIVER == 1) ++if (adapter->registrypriv.mp_mode == 1) ++ return; ++#endif ++*/ ++ rtw_dynamic_check_timer_handlder(adapter); ++ ++ _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); ++} ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++void _rtw_set_scan_deny_timer_hdl(void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ rtw_set_scan_deny_timer_hdl(adapter); ++} ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++void _rtw_event_polling_timer_hdl(void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ ++ rtw_event_polling_timer_hdl(adapter); ++ ++ _set_timer(&adapter->mlmepriv.event_polling_timer, 200); ++} ++#endif ++ ++void rtw_init_mlme_timer(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _init_timer(&(pmlmepriv->assoc_timer), padapter->pnetdev, rtw_join_timeout_handler, padapter); ++ //_init_timer(&(pmlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer), padapter->pnetdev, sitesurvey_ctrl_handler, padapter); ++ _init_timer(&(pmlmepriv->scan_to_timer), padapter->pnetdev, _rtw_scan_timeout_handler, padapter); ++ ++ _init_timer(&(pmlmepriv->dynamic_chk_timer), padapter->pnetdev, _dynamic_check_timer_handlder, padapter); ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _init_timer(&(pmlmepriv->set_scan_deny_timer), padapter->pnetdev, _rtw_set_scan_deny_timer_hdl, padapter); ++ #endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ _init_timer(&(pmlmepriv->event_polling_timer), padapter->pnetdev, _rtw_event_polling_timer_hdl, padapter); ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter); ++ _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter); ++#endif ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ if (padapter->HalFunc.hal_init_checkbthang_workqueue) ++ padapter->HalFunc.hal_init_checkbthang_workqueue(padapter); ++#endif ++} ++ ++extern void rtw_indicate_wx_assoc_event(_adapter *padapter); ++extern void rtw_indicate_wx_disassoc_event(_adapter *padapter); ++ ++void rtw_os_indicate_connect(_adapter *adapter) ++{ ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++_func_enter_; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) ++ { ++ rtw_cfg80211_ibss_indicate_connect(adapter); ++ } ++ else ++ rtw_cfg80211_indicate_connect(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ rtw_indicate_wx_assoc_event(adapter); ++ netif_carrier_on(adapter->pnetdev); ++ ++ if(adapter->pid[2] !=0) ++ rtw_signal_process(adapter->pid[2], SIGALRM); ++ ++#ifdef RTK_DMP_PLATFORM ++ _set_workitem(&adapter->mlmepriv.Linkup_workitem); ++#endif ++ ++_func_exit_; ++ ++} ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted) ++{ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), aborted); ++#endif ++ indicate_wx_scan_complete_event(padapter); ++} ++ ++static RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; ++void rtw_reset_securitypriv( _adapter *adapter ) ++{ ++ u8 backupPMKIDIndex = 0; ++ u8 backupTKIPCountermeasure = 0x00; ++ u32 backupTKIPcountermeasure_time = 0; ++ // add for CONFIG_IEEE80211W, none 11w also can use ++ _irqL irqL; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ ++ _enter_critical_bh(&adapter->security_key_mutex, &irqL); ++ ++ if(adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)//802.1x ++ { ++ // Added by Albert 2009/02/18 ++ // We have to backup the PMK information for WiFi PMK Caching test item. ++ // ++ // Backup the btkip_countermeasure information. ++ // When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. ++ ++ _rtw_memset( &backupPMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ ++ _rtw_memcpy( &backupPMKIDList[ 0 ], &adapter->securitypriv.PMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; ++ backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; ++ backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; ++#ifdef CONFIG_IEEE80211W ++ //reset RX BIP packet number ++ pmlmeext->mgnt_80211w_IPN_rx = 0; ++#endif //CONFIG_IEEE80211W ++ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof (struct security_priv)); ++ //_init_timer(&(adapter->securitypriv.tkip_timer),adapter->pnetdev, rtw_use_tkipkey_handler, adapter); ++ ++ // Added by Albert 2009/02/18 ++ // Restore the PMK information to securitypriv structure for the following connection. ++ _rtw_memcpy( &adapter->securitypriv.PMKIDList[ 0 ], &backupPMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ adapter->securitypriv.PMKIDIndex = backupPMKIDIndex; ++ adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure; ++ adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time; ++ ++ adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; ++ adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; ++ ++ } ++ else //reset values in securitypriv ++ { ++ //if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) ++ //{ ++ struct security_priv *psec_priv=&adapter->securitypriv; ++ ++ psec_priv->dot11AuthAlgrthm =dot11AuthAlgrthm_Open; //open system ++ psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ psec_priv->dot11PrivacyKeyIndex = 0; ++ ++ psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psec_priv->dot118021XGrpKeyid = 1; ++ ++ psec_priv->ndisauthtype = Ndis802_11AuthModeOpen; ++ psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled; ++ //} ++ } ++ // add for CONFIG_IEEE80211W, none 11w also can use ++ _exit_critical_bh(&adapter->security_key_mutex, &irqL); ++} ++ ++void rtw_os_indicate_disconnect( _adapter *adapter ) ++{ ++ //RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; ++ ++_func_enter_; ++ ++ netif_carrier_off(adapter->pnetdev); // Do it first for tx broadcast pkt after disconnection issue! ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_disconnect(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ rtw_indicate_wx_disassoc_event(adapter); ++ ++#ifdef RTK_DMP_PLATFORM ++ _set_workitem(&adapter->mlmepriv.Linkdown_workitem); ++#endif ++ //modify for CONFIG_IEEE80211W, none 11w also can use the same command ++ rtw_reset_securitypriv_cmd(adapter); ++ ++_func_exit_; ++ ++} ++ ++void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie) ++{ ++ uint len; ++ u8 *buff,*p,i; ++ union iwreq_data wrqu; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+rtw_report_sec_ie, authmode=%d\n", authmode)); ++ ++ buff = NULL; ++ if(authmode==_WPA_IE_ID_) ++ { ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("rtw_report_sec_ie, authmode=%d\n", authmode)); ++ ++ buff = rtw_malloc(IW_CUSTOM_MAX); ++ ++ _rtw_memset(buff,0,IW_CUSTOM_MAX); ++ ++ p=buff; ++ ++ p+=sprintf(p,"ASSOCINFO(ReqIEs="); ++ ++ len = sec_ie[1]+2; ++ len = (len < IW_CUSTOM_MAX) ? len:IW_CUSTOM_MAX; ++ ++ for(i=0;ipnetdev,IWEVCUSTOM,&wrqu,buff); ++#endif ++ ++ if(buff) ++ rtw_mfree(buff, IW_CUSTOM_MAX); ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void _survey_timer_hdl (void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ ++ survey_timer_hdl(padapter); ++} ++ ++void _link_timer_hdl (void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ link_timer_hdl(padapter); ++} ++ ++void _addba_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *psta = (struct sta_info *)FunctionContext; ++ addba_timer_hdl(psta); ++} ++ ++#ifdef CONFIG_IEEE80211W ++void _sa_query_timer_hdl (void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ sa_query_timer_hdl(padapter); ++} ++#endif //CONFIG_IEEE80211W ++ ++void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ ++ _init_timer(&psta->addba_retry_timer, padapter->pnetdev, _addba_timer_hdl, psta); ++} ++ ++/* ++void _reauth_timer_hdl(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ reauth_timer_hdl(padapter); ++} ++ ++void _reassoc_timer_hdl(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ reassoc_timer_hdl(padapter); ++} ++*/ ++ ++void init_mlme_ext_timer(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ _init_timer(&pmlmeext->survey_timer, padapter->pnetdev, _survey_timer_hdl, padapter); ++ _init_timer(&pmlmeext->link_timer, padapter->pnetdev, _link_timer_hdl, padapter); ++#ifdef CONFIG_IEEE80211W ++ _init_timer(&pmlmeext->sa_query_timer, padapter->pnetdev, _sa_query_timer_hdl, padapter); ++#endif //CONFIG_IEEE80211W ++ //_init_timer(&pmlmeext->ADDBA_timer, padapter->pnetdev, _addba_timer_hdl, padapter); ++ ++ //_init_timer(&pmlmeext->reauth_timer, padapter->pnetdev, _reauth_timer_hdl, padapter); ++ //_init_timer(&pmlmeext->reassoc_timer, padapter->pnetdev, _reassoc_timer_hdl, padapter); ++} ++ ++#ifdef CONFIG_AP_MODE ++ ++void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) ++{ ++ union iwreq_data wrqu; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(psta==NULL) ++ return; ++ ++ if(psta->aid > NUM_STA) ++ return; ++ ++ if(pstapriv->sta_aid[psta->aid - 1] != psta) ++ return; ++ ++ ++ wrqu.addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); ++ ++ DBG_871X("+rtw_indicate_sta_assoc_event\n"); ++ ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL); ++#endif ++ ++} ++ ++void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) ++{ ++ union iwreq_data wrqu; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(psta==NULL) ++ return; ++ ++ if(psta->aid > NUM_STA) ++ return; ++ ++ if(pstapriv->sta_aid[psta->aid - 1] != psta) ++ return; ++ ++ ++ wrqu.addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); ++ ++ DBG_871X("+rtw_indicate_sta_disassoc_event\n"); ++ ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL); ++#endif ++ ++} ++ ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ ++static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ _adapter *padapter = (_adapter *)phostapdpriv->padapter; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb); ++} ++ ++static int mgnt_netdev_open(struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ ++ DBG_871X("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr)); ++ ++ ++ init_usb_anchor(&phostapdpriv->anchored); ++ ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ ++ ++ netif_carrier_on(pnetdev); ++ ++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100);//only excluding beacon ++ ++ return 0; ++} ++static int mgnt_netdev_close(struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ usb_kill_anchored_urbs(&phostapdpriv->anchored); ++ ++ netif_carrier_off(pnetdev); ++ ++ if (!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_stop_queue(pnetdev); ++ ++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); ++ ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtl871x_mgnt_netdev_ops = { ++ .ndo_open = mgnt_netdev_open, ++ .ndo_stop = mgnt_netdev_close, ++ .ndo_start_xmit = mgnt_xmit_entry, ++ //.ndo_set_mac_address = r871x_net_set_mac_address, ++ //.ndo_get_stats = r871x_net_get_stats, ++ //.ndo_do_ioctl = r871x_mp_ioctl, ++}; ++#endif ++ ++int hostapd_mode_init(_adapter *padapter) ++{ ++ unsigned char mac[ETH_ALEN]; ++ struct hostapd_priv *phostapdpriv; ++ struct net_device *pnetdev; ++ ++ pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv)); ++ if (!pnetdev) ++ return -ENOMEM; ++ ++ //SET_MODULE_OWNER(pnetdev); ++ ether_setup(pnetdev); ++ ++ //pnetdev->type = ARPHRD_IEEE80211; ++ ++ phostapdpriv = rtw_netdev_priv(pnetdev); ++ phostapdpriv->pmgnt_netdev = pnetdev; ++ phostapdpriv->padapter= padapter; ++ padapter->phostapdpriv = phostapdpriv; ++ ++ //pnetdev->init = NULL; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ ++ DBG_871X("register rtl871x_mgnt_netdev_ops to netdev_ops\n"); ++ ++ pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops; ++ ++#else ++ ++ pnetdev->open = mgnt_netdev_open; ++ ++ pnetdev->stop = mgnt_netdev_close; ++ ++ pnetdev->hard_start_xmit = mgnt_xmit_entry; ++ ++ //pnetdev->set_mac_address = r871x_net_set_mac_address; ++ ++ //pnetdev->get_stats = r871x_net_get_stats; ++ ++ //pnetdev->do_ioctl = r871x_mp_ioctl; ++ ++#endif ++ ++ pnetdev->watchdog_timeo = HZ; /* 1 second timeout */ ++ ++ //pnetdev->wireless_handlers = NULL; ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ pnetdev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++ ++ ++ if(dev_alloc_name(pnetdev,"mgnt.wlan%d") < 0) ++ { ++ DBG_871X("hostapd_mode_init(): dev_alloc_name, fail! \n"); ++ } ++ ++ ++ //SET_NETDEV_DEV(pnetdev, pintfpriv->udev); ++ ++ ++ mac[0]=0x00; ++ mac[1]=0xe0; ++ mac[2]=0x4c; ++ mac[3]=0x87; ++ mac[4]=0x11; ++ mac[5]=0x12; ++ ++ _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN); ++ ++ ++ netif_carrier_off(pnetdev); ++ ++ ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) ++ { ++ DBG_871X("hostapd_mode_init(): register_netdev fail!\n"); ++ ++ if(pnetdev) ++ { ++ rtw_free_netdev(pnetdev); ++ } ++ } ++ ++ return 0; ++ ++} ++ ++void hostapd_mode_unload(_adapter *padapter) ++{ ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pnetdev = phostapdpriv->pmgnt_netdev; ++ ++ unregister_netdev(pnetdev); ++ rtw_free_netdev(pnetdev); ++ ++} ++ ++#endif ++#endif ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/os_intfs.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/os_intfs.c +new file mode 100644 +index 00000000..255d2b8d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/os_intfs.c +@@ -0,0 +1,2986 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _OS_INTFS_C_ ++ ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++#ifdef CONFIG_BR_EXT ++#include ++#endif //CONFIG_BR_EXT ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++#ifdef CONFIG_RTL8723A ++#define RF_GAIN_OFFSET_ON BIT0 ++#define REG_RF_BB_GAIN_OFFSET 0x7f ++#define RF_GAIN_OFFSET_MASK 0xfffff ++#else ++#define RF_GAIN_OFFSET_ON BIT4 ++#define REG_RF_BB_GAIN_OFFSET 0x55 ++#define RF_GAIN_OFFSET_MASK 0xfffff ++#endif //CONFIG_RTL8723A ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); ++MODULE_AUTHOR("Realtek Semiconductor Corp."); ++MODULE_VERSION(DRIVERVERSION); ++ ++/* module param defaults */ ++int rtw_chip_version = 0x00; ++int rtw_rfintfs = HWPI; ++int rtw_lbkmode = 0;//RTL8712_AIR_TRX; ++ ++ ++int rtw_network_mode = Ndis802_11IBSS;//Ndis802_11Infrastructure;//infra, ad-hoc, auto ++//NDIS_802_11_SSID ssid; ++int rtw_channel = 1;//ad-hoc support requirement ++int rtw_wireless_mode = WIRELESS_11BG_24N; ++int rtw_vrtl_carrier_sense = AUTO_VCS; ++int rtw_vcs_type = RTS_CTS;//* ++int rtw_rts_thresh = 2347;//* ++int rtw_frag_thresh = 2346;//* ++int rtw_preamble = PREAMBLE_LONG;//long, short, auto ++int rtw_scan_mode = 1;//active, passive ++int rtw_adhoc_tx_pwr = 1; ++int rtw_soft_ap = 0; ++//int smart_ps = 1; ++#ifdef CONFIG_POWER_SAVING ++int rtw_power_mgnt = 1; ++#ifdef CONFIG_IPS_LEVEL_2 ++int rtw_ips_mode = IPS_LEVEL_2; ++#else ++int rtw_ips_mode = IPS_NORMAL; ++#endif ++#else ++int rtw_power_mgnt = PS_MODE_ACTIVE; ++int rtw_ips_mode = IPS_NONE; ++#endif ++ ++int rtw_smart_ps = 2; ++ ++#ifdef CONFIG_TX_EARLY_MODE ++int rtw_early_mode=1; ++#endif ++module_param(rtw_ips_mode, int, 0644); ++MODULE_PARM_DESC(rtw_ips_mode,"The default IPS mode"); ++ ++int rtw_radio_enable = 1; ++int rtw_long_retry_lmt = 7; ++int rtw_short_retry_lmt = 7; ++int rtw_busy_thresh = 40; ++//int qos_enable = 0; //* ++int rtw_ack_policy = NORMAL_ACK; ++ ++int rtw_mp_mode = 0; ++ ++int rtw_software_encrypt = 0; ++int rtw_software_decrypt = 0; ++ ++int rtw_acm_method = 0;// 0:By SW 1:By HW. ++ ++int rtw_wmm_enable = 1;// default is set to enable the wmm. ++int rtw_uapsd_enable = 0; ++int rtw_uapsd_max_sp = NO_LIMIT; ++int rtw_uapsd_acbk_en = 0; ++int rtw_uapsd_acbe_en = 0; ++int rtw_uapsd_acvi_en = 0; ++int rtw_uapsd_acvo_en = 0; ++ ++#ifdef CONFIG_80211N_HT ++int rtw_ht_enable = 1; ++int rtw_cbw40_enable = 3; // 0 :diable, bit(0): enable 2.4g, bit(1): enable 5g ++int rtw_ampdu_enable = 1;//for enable tx_ampdu ++int rtw_rx_stbc = 1;// 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ ++int rtw_ampdu_amsdu = 0;// 0: disabled, 1:enabled, 2:auto ++#endif ++ ++int rtw_lowrate_two_xmit = 1;//Use 2 path Tx to transmit MCS0~7 and legacy mode ++ ++//int rf_config = RF_1T2R; // 1T2R ++int rtw_rf_config = RF_819X_MAX_TYPE; //auto ++int rtw_low_power = 0; ++#ifdef CONFIG_WIFI_TEST ++int rtw_wifi_spec = 1;//for wifi test ++#else ++int rtw_wifi_spec = 0; ++#endif ++int rtw_channel_plan = RT_CHANNEL_DOMAIN_MAX; ++ ++#ifdef CONFIG_BT_COEXIST ++int rtw_btcoex_enable = 1; ++int rtw_bt_iso = 2;// 0:Low, 1:High, 2:From Efuse ++int rtw_bt_sco = 3;// 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy ++int rtw_bt_ampdu =1 ;// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. ++#endif ++ ++int rtw_AcceptAddbaReq = _TRUE;// 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. ++ ++int rtw_antdiv_cfg = 2; // 0:OFF , 1:ON, 2:decide by Efuse config ++int rtw_antdiv_type = 0 ; //0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) ++ ++ ++#ifdef CONFIG_USB_AUTOSUSPEND ++int rtw_enusbss = 1;//0:disable,1:enable ++#else ++int rtw_enusbss = 0;//0:disable,1:enable ++#endif ++ ++int rtw_hwpdn_mode=2;//0:disable,1:enable,2: by EFUSE config ++ ++#ifdef CONFIG_HW_PWRP_DETECTION ++int rtw_hwpwrp_detect = 1; ++#else ++int rtw_hwpwrp_detect = 0; //HW power ping detect 0:disable , 1:enable ++#endif ++ ++#ifdef CONFIG_USB_HCI ++int rtw_hw_wps_pbc = 1; ++#else ++int rtw_hw_wps_pbc = 0; ++#endif ++ ++#ifdef CONFIG_TX_MCAST2UNI ++int rtw_mc2u_disable = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++int rtw_dmsp = 0; ++#endif // CONFIG_DUALMAC_CONCURRENT ++ ++#ifdef CONFIG_80211D ++int rtw_80211d = 0; ++#endif ++ ++#ifdef CONFIG_REGULATORY_CTRL ++int rtw_regulatory_id =2; ++#else ++int rtw_regulatory_id = 0xff;// Regulatory tab id, 0xff = follow efuse's setting ++#endif ++module_param(rtw_regulatory_id, int, 0644); ++ ++ ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++int rtw_force_ant = 2;//0 :normal, 1:Main ant, 2:Aux ant ++int rtw_force_igi =0;//0 :normal ++module_param(rtw_force_ant, int, 0644); ++module_param(rtw_force_igi, int, 0644); ++#endif ++ ++#ifdef CONFIG_QOS_OPTIMIZATION ++int rtw_qos_opt_enable=1;//0: disable,1:enable ++#else ++int rtw_qos_opt_enable=0;//0: disable,1:enable ++#endif ++module_param(rtw_qos_opt_enable,int,0644); ++ ++char* ifname = "wlan%d"; ++module_param(ifname, charp, 0644); ++MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); ++ ++char* if2name = "wlan%d"; ++module_param(if2name, charp, 0644); ++MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); ++ ++char* rtw_initmac = 0; // temp mac address if users want to use instead of the mac address in Efuse ++ ++module_param(rtw_initmac, charp, 0644); ++module_param(rtw_channel_plan, int, 0644); ++module_param(rtw_chip_version, int, 0644); ++module_param(rtw_rfintfs, int, 0644); ++module_param(rtw_lbkmode, int, 0644); ++module_param(rtw_network_mode, int, 0644); ++module_param(rtw_channel, int, 0644); ++module_param(rtw_mp_mode, int, 0644); ++module_param(rtw_wmm_enable, int, 0644); ++module_param(rtw_vrtl_carrier_sense, int, 0644); ++module_param(rtw_vcs_type, int, 0644); ++module_param(rtw_busy_thresh, int, 0644); ++#ifdef CONFIG_80211N_HT ++module_param(rtw_ht_enable, int, 0644); ++module_param(rtw_cbw40_enable, int, 0644); ++module_param(rtw_ampdu_enable, int, 0644); ++module_param(rtw_rx_stbc, int, 0644); ++module_param(rtw_ampdu_amsdu, int, 0644); ++#endif ++ ++module_param(rtw_lowrate_two_xmit, int, 0644); ++ ++module_param(rtw_rf_config, int, 0644); ++module_param(rtw_power_mgnt, int, 0644); ++module_param(rtw_smart_ps, int, 0644); ++module_param(rtw_low_power, int, 0644); ++module_param(rtw_wifi_spec, int, 0644); ++ ++module_param(rtw_antdiv_cfg, int, 0644); ++module_param(rtw_antdiv_type, int, 0644); ++ ++module_param(rtw_enusbss, int, 0644); ++module_param(rtw_hwpdn_mode, int, 0644); ++module_param(rtw_hwpwrp_detect, int, 0644); ++ ++module_param(rtw_hw_wps_pbc, int, 0644); ++ ++#ifdef CONFIG_TX_EARLY_MODE ++module_param(rtw_early_mode, int, 0644); ++#endif ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++char *rtw_adaptor_info_caching_file_path= "/data/misc/wifi/rtw_cache"; ++module_param(rtw_adaptor_info_caching_file_path, charp, 0644); ++MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file"); ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++ ++#ifdef CONFIG_LAYER2_ROAMING ++uint rtw_max_roaming_times=2; ++module_param(rtw_max_roaming_times, uint, 0644); ++MODULE_PARM_DESC(rtw_max_roaming_times,"The max roaming times to try"); ++#endif //CONFIG_LAYER2_ROAMING ++ ++#ifdef CONFIG_IOL ++int rtw_fw_iol=1;// 0:Disable, 1:enable, 2:by usb speed ++module_param(rtw_fw_iol, int, 0644); ++MODULE_PARM_DESC(rtw_fw_iol,"FW IOL"); ++#endif //CONFIG_IOL ++ ++#ifdef CONFIG_FILE_FWIMG ++char *rtw_fw_file_path= ""; ++module_param(rtw_fw_file_path, charp, 0644); ++MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image"); ++#endif //CONFIG_FILE_FWIMG ++ ++#ifdef CONFIG_TX_MCAST2UNI ++module_param(rtw_mc2u_disable, int, 0644); ++#endif // CONFIG_TX_MCAST2UNI ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++module_param(rtw_dmsp, int, 0644); ++#endif // CONFIG_DUALMAC_CONCURRENT ++ ++#ifdef CONFIG_80211D ++module_param(rtw_80211d, int, 0644); ++MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++module_param(rtw_btcoex_enable, int, 0644); ++MODULE_PARM_DESC(rtw_btcoex_enable, "Enable BT co-existence mechanism"); ++#endif ++ ++uint rtw_notch_filter = RTW_NOTCH_FILTER; ++module_param(rtw_notch_filter, uint, 0644); ++MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); ++ ++static uint loadparam(PADAPTER padapter, _nic_hdl pnetdev); ++int _netdev_open(struct net_device *pnetdev); ++int netdev_open (struct net_device *pnetdev); ++static int netdev_close (struct net_device *pnetdev); ++ ++//#ifdef RTK_DMP_PLATFORM ++#ifdef CONFIG_PROC_DEBUG ++#define RTL8192C_PROC_NAME "rtl819xC" ++#define RTL8192D_PROC_NAME "rtl819xD" ++static char rtw_proc_name[IFNAMSIZ]; ++static struct proc_dir_entry *rtw_proc = NULL; ++static int rtw_proc_cnt = 0; ++ ++#define RTW_PROC_NAME DRV_NAME ++ ++void rtw_proc_init_one(struct net_device *dev) ++{ ++ struct proc_dir_entry *dir_dev = NULL; ++ struct proc_dir_entry *entry=NULL; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ u8 rf_type; ++ ++ if(rtw_proc == NULL) ++ { ++ if(padapter->chip_type == RTL8188C_8192C) ++ { ++ _rtw_memcpy(rtw_proc_name, RTL8192C_PROC_NAME, sizeof(RTL8192C_PROC_NAME)); ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++ _rtw_memcpy(rtw_proc_name, RTL8192D_PROC_NAME, sizeof(RTL8192D_PROC_NAME)); ++ } ++ else if(padapter->chip_type == RTL8723A) ++ { ++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME)); ++ } ++ else if(padapter->chip_type == RTL8188E) ++ { ++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME)); ++ } ++ else ++ { ++ _rtw_memcpy(rtw_proc_name, RTW_PROC_NAME, sizeof(RTW_PROC_NAME)); ++ } ++ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, proc_net); ++#else ++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, init_net.proc_net); ++#endif ++ if (rtw_proc == NULL) { ++ DBG_871X(KERN_ERR "Unable to create rtw_proc directory\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ver_info", S_IFREG | S_IRUGO, rtw_proc, proc_get_drv_version, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++#ifdef DBG_MEM_ALLOC ++ entry = create_proc_read_entry("mstat", S_IFREG | S_IRUGO, ++ rtw_proc, proc_get_mstat, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif /* DBG_MEM_ALLOC */ ++ } ++ ++ ++ ++ if(padapter->dir_dev == NULL) ++ { ++ padapter->dir_dev = create_proc_entry(dev->name, ++ S_IFDIR | S_IRUGO | S_IXUGO, ++ rtw_proc); ++ ++ dir_dev = padapter->dir_dev; ++ ++ if(dir_dev==NULL) ++ { ++ if(rtw_proc_cnt == 0) ++ { ++ if(rtw_proc){ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(rtw_proc_name, proc_net); ++#else ++ remove_proc_entry(rtw_proc_name, init_net.proc_net); ++#endif ++ rtw_proc = NULL; ++ } ++ } ++ ++ DBG_871X("Unable to create dir_dev directory\n"); ++ return; ++ } ++ } ++ else ++ { ++ return; ++ } ++ ++ rtw_proc_cnt++; ++ ++ entry = create_proc_read_entry("write_reg", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_write_reg, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_write_reg; ++ ++ entry = create_proc_read_entry("read_reg", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_read_reg, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_read_reg; ++ ++ ++ entry = create_proc_read_entry("fwstate", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_fwstate, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("sec_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_sec_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("mlmext_state", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_mlmext_state, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("qos_option", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_qos_option, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ht_option", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ht_option, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("rf_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ap_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ap_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("adapter_state", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_adapter_state, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("trx_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_trx_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("mac_reg_dump1", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_mac_reg_dump1, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("mac_reg_dump2", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_mac_reg_dump2, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("mac_reg_dump3", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_mac_reg_dump3, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("bb_reg_dump1", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_bb_reg_dump1, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("bb_reg_dump2", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_bb_reg_dump2, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("bb_reg_dump3", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_bb_reg_dump3, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("rf_reg_dump1", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_reg_dump1, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("rf_reg_dump2", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_reg_dump2, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) { ++ entry = create_proc_read_entry("rf_reg_dump3", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_reg_dump3, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("rf_reg_dump4", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_reg_dump4, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ } ++ ++#ifdef CONFIG_AP_MODE ++ ++ entry = create_proc_read_entry("all_sta_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_all_sta_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ entry = create_proc_read_entry("_malloc_cnt", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_malloc_cnt, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ entry = create_proc_read_entry("best_channel", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_best_channel, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_best_channel; ++#endif ++ ++ entry = create_proc_read_entry("rx_signal", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rx_signal, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_rx_signal; ++#ifdef CONFIG_80211N_HT ++ entry = create_proc_read_entry("ht_enable", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ht_enable, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_ht_enable; ++ ++ entry = create_proc_read_entry("cbw40_enable", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_cbw40_enable, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_cbw40_enable; ++ ++ entry = create_proc_read_entry("ampdu_enable", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ampdu_enable, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_ampdu_enable; ++ ++ entry = create_proc_read_entry("rx_stbc", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rx_stbc, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_rx_stbc; ++#endif //CONFIG_80211N_HT ++ ++ entry = create_proc_read_entry("path_rssi", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_two_path_rssi, dev); ++ ++ ++ entry = create_proc_read_entry("rssi_disp", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rssi_disp, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_rssi_disp; ++#ifdef CONFIG_BT_COEXIST ++ entry = create_proc_read_entry("btcoex_dbg", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_btcoex_dbg, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_btcoex_dbg; ++#endif /*CONFIG_BT_COEXIST*/ ++ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ entry = create_proc_read_entry("sreset", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_sreset, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_sreset; ++#endif /* DBG_CONFIG_ERROR_DETECT */ ++ ++ /* for odm */ ++ { ++ struct proc_dir_entry *dir_odm = NULL; ++ ++ if (padapter->dir_odm == NULL) { ++ padapter->dir_odm = create_proc_entry( ++ "odm", S_IFDIR | S_IRUGO | S_IXUGO, dir_dev); ++ ++ dir_odm = padapter->dir_odm; ++ ++ if(dir_odm==NULL) { ++ DBG_871X("Unable to create dir_odm directory\n"); ++ return; ++ } ++ } ++ else ++ { ++ return; ++ } ++ ++ entry = create_proc_read_entry("dbg_comp", S_IFREG | S_IRUGO, ++ dir_odm, proc_get_odm_dbg_comp, dev); ++ if (!entry) { ++ rtw_warn_on(1); ++ return; ++ } ++ entry->write_proc = proc_set_odm_dbg_comp; ++ ++ entry = create_proc_read_entry("dbg_level", S_IFREG | S_IRUGO, ++ dir_odm, proc_get_odm_dbg_level, dev); ++ if (!entry) { ++ rtw_warn_on(1); ++ return; ++ } ++ entry->write_proc = proc_set_odm_dbg_level; ++ ++ entry = create_proc_read_entry("adaptivity", S_IFREG | S_IRUGO, ++ dir_odm, proc_get_odm_adaptivity, dev); ++ if (!entry) { ++ rtw_warn_on(1); ++ return; ++ } ++ entry->write_proc = proc_set_odm_adaptivity; ++ } ++} ++ ++void rtw_proc_remove_one(struct net_device *dev) ++{ ++ struct proc_dir_entry *dir_dev = NULL; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ u8 rf_type; ++ ++ dir_dev = padapter->dir_dev; ++ padapter->dir_dev = NULL; ++ ++ if (dir_dev) { ++ ++ remove_proc_entry("write_reg", dir_dev); ++ remove_proc_entry("read_reg", dir_dev); ++ remove_proc_entry("fwstate", dir_dev); ++ remove_proc_entry("sec_info", dir_dev); ++ remove_proc_entry("mlmext_state", dir_dev); ++ remove_proc_entry("qos_option", dir_dev); ++ remove_proc_entry("ht_option", dir_dev); ++ remove_proc_entry("rf_info", dir_dev); ++ remove_proc_entry("ap_info", dir_dev); ++ remove_proc_entry("adapter_state", dir_dev); ++ remove_proc_entry("trx_info", dir_dev); ++ ++ remove_proc_entry("mac_reg_dump1", dir_dev); ++ remove_proc_entry("mac_reg_dump2", dir_dev); ++ remove_proc_entry("mac_reg_dump3", dir_dev); ++ remove_proc_entry("bb_reg_dump1", dir_dev); ++ remove_proc_entry("bb_reg_dump2", dir_dev); ++ remove_proc_entry("bb_reg_dump3", dir_dev); ++ remove_proc_entry("rf_reg_dump1", dir_dev); ++ remove_proc_entry("rf_reg_dump2", dir_dev); ++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) { ++ remove_proc_entry("rf_reg_dump3", dir_dev); ++ remove_proc_entry("rf_reg_dump4", dir_dev); ++ } ++#ifdef CONFIG_AP_MODE ++ remove_proc_entry("all_sta_info", dir_dev); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ remove_proc_entry("_malloc_cnt", dir_dev); ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ remove_proc_entry("best_channel", dir_dev); ++#endif ++ remove_proc_entry("rx_signal", dir_dev); ++#ifdef CONFIG_80211N_HT ++ remove_proc_entry("cbw40_enable", dir_dev); ++ ++ remove_proc_entry("ht_enable", dir_dev); ++ ++ remove_proc_entry("ampdu_enable", dir_dev); ++ ++ remove_proc_entry("rx_stbc", dir_dev); ++#endif //CONFIG_80211N_HT ++ remove_proc_entry("path_rssi", dir_dev); ++ ++ remove_proc_entry("rssi_disp", dir_dev); ++ ++#ifdef CONFIG_BT_COEXIST ++ remove_proc_entry("btcoex_dbg", dir_dev); ++#endif //CONFIG_BT_COEXIST ++ ++#if defined(DBG_CONFIG_ERROR_DETECT) ++ remove_proc_entry("sreset", dir_dev); ++#endif /* DBG_CONFIG_ERROR_DETECT */ ++ ++ /* for odm */ ++ { ++ struct proc_dir_entry *dir_odm = NULL; ++ dir_odm = padapter->dir_odm; ++ padapter->dir_odm = NULL; ++ ++ if (dir_odm) { ++ remove_proc_entry("dbg_comp", dir_odm); ++ remove_proc_entry("dbg_level", dir_odm); ++ remove_proc_entry("adaptivity", dir_odm); ++ ++ remove_proc_entry("odm", dir_dev); ++ } ++ } ++ ++ remove_proc_entry(dev->name, rtw_proc); ++ dir_dev = NULL; ++ ++ } ++ else ++ { ++ return; ++ } ++ ++ rtw_proc_cnt--; ++ ++ if(rtw_proc_cnt == 0) ++ { ++ if(rtw_proc){ ++ remove_proc_entry("ver_info", rtw_proc); ++ #ifdef DBG_MEM_ALLOC ++ remove_proc_entry("mstat", rtw_proc); ++ #endif /* DBG_MEM_ALLOC */ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(rtw_proc_name, proc_net); ++#else ++ remove_proc_entry(rtw_proc_name, init_net.proc_net); ++#endif ++ rtw_proc = NULL; ++ } ++ } ++} ++#endif ++ ++uint loadparam( _adapter *padapter, _nic_hdl pnetdev); ++uint loadparam( _adapter *padapter, _nic_hdl pnetdev) ++{ ++ ++ uint status = _SUCCESS; ++ struct registry_priv *registry_par = &padapter->registrypriv; ++ ++_func_enter_; ++ ++ registry_par->chip_version = (u8)rtw_chip_version; ++ registry_par->rfintfs = (u8)rtw_rfintfs; ++ registry_par->lbkmode = (u8)rtw_lbkmode; ++ //registry_par->hci = (u8)hci; ++ registry_par->network_mode = (u8)rtw_network_mode; ++ ++ _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); ++ registry_par->ssid.SsidLength = 3; ++ ++ registry_par->channel = (u8)rtw_channel; ++ registry_par->wireless_mode = (u8)rtw_wireless_mode; ++ registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; ++ registry_par->vcs_type = (u8)rtw_vcs_type; ++ registry_par->rts_thresh=(u16)rtw_rts_thresh; ++ registry_par->frag_thresh=(u16)rtw_frag_thresh; ++ registry_par->preamble = (u8)rtw_preamble; ++ registry_par->scan_mode = (u8)rtw_scan_mode; ++ registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr; ++ registry_par->soft_ap= (u8)rtw_soft_ap; ++ registry_par->smart_ps = (u8)rtw_smart_ps; ++ registry_par->power_mgnt = (u8)rtw_power_mgnt; ++ registry_par->ips_mode = (u8)rtw_ips_mode; ++ registry_par->radio_enable = (u8)rtw_radio_enable; ++ registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; ++ registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; ++ registry_par->busy_thresh = (u16)rtw_busy_thresh; ++ //registry_par->qos_enable = (u8)rtw_qos_enable; ++ registry_par->ack_policy = (u8)rtw_ack_policy; ++ registry_par->mp_mode = (u8)rtw_mp_mode; ++ registry_par->software_encrypt = (u8)rtw_software_encrypt; ++ registry_par->software_decrypt = (u8)rtw_software_decrypt; ++ ++ registry_par->acm_method = (u8)rtw_acm_method; ++ ++ //UAPSD ++ registry_par->wmm_enable = (u8)rtw_wmm_enable; ++ registry_par->uapsd_enable = (u8)rtw_uapsd_enable; ++ registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; ++ registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; ++ registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; ++ registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; ++ registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; ++ ++#ifdef CONFIG_80211N_HT ++ registry_par->ht_enable = (u8)rtw_ht_enable; ++ registry_par->cbw40_enable = (u8)rtw_cbw40_enable; ++ registry_par->ampdu_enable = (u8)rtw_ampdu_enable; ++ registry_par->rx_stbc = (u8)rtw_rx_stbc; ++ registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu; ++#endif ++#ifdef CONFIG_TX_EARLY_MODE ++ registry_par->early_mode = (u8)rtw_early_mode; ++#endif ++ registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit; ++ registry_par->rf_config = (u8)rtw_rf_config; ++ registry_par->low_power = (u8)rtw_low_power; ++ ++ ++ registry_par->wifi_spec = (u8)rtw_wifi_spec; ++ ++ registry_par->channel_plan = (u8)rtw_channel_plan; ++ ++#ifdef CONFIG_BT_COEXIST ++ registry_par->btcoex = (u8)rtw_btcoex_enable; ++ registry_par->bt_iso = (u8)rtw_bt_iso; ++ registry_par->bt_sco = (u8)rtw_bt_sco; ++ registry_par->bt_ampdu = (u8)rtw_bt_ampdu; ++#endif ++ ++ registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; ++ ++ registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; ++ registry_par->antdiv_type = (u8)rtw_antdiv_type; ++ ++#ifdef CONFIG_AUTOSUSPEND ++ registry_par->usbss_enable = (u8)rtw_enusbss;//0:disable,1:enable ++#endif ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;//0:disable,1:enable,2:by EFUSE config ++ registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;//0:disable,1:enable ++#endif ++ ++ registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable; ++ registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; ++ ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path); ++ registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX-1]=0; ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ registry_par->max_roaming_times = (u8)rtw_max_roaming_times; ++#ifdef CONFIG_INTEL_WIDI ++ registry_par->max_roaming_times = (u8)rtw_max_roaming_times + 2; ++#endif // CONFIG_INTEL_WIDI ++#endif ++ ++#ifdef CONFIG_IOL ++ registry_par->fw_iol = rtw_fw_iol; ++#endif ++ ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ registry_par->dmsp= (u8)rtw_dmsp; ++#endif ++ ++#ifdef CONFIG_80211D ++ registry_par->enable80211d = (u8)rtw_80211d; ++#endif ++ ++ snprintf(registry_par->ifname, 16, "%s", ifname); ++ snprintf(registry_par->if2name, 16, "%s", if2name); ++ ++ registry_par->notch_filter = (u8)rtw_notch_filter; ++ ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ registry_par->force_ant = (u8)rtw_force_ant; ++ registry_par->force_igi = (u8)rtw_force_igi; ++#endif ++ registry_par->regulatory_tid = (u8)rtw_regulatory_id; ++ ++ ++_func_exit_; ++ ++ return status; ++} ++ ++static int rtw_net_set_mac_address(struct net_device *pnetdev, void *p) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct sockaddr *addr = p; ++ ++ if(padapter->bup == _FALSE) ++ { ++ //DBG_871X("r8711_net_set_mac_address(), MAC=%x:%x:%x:%x:%x:%x\n", addr->sa_data[0], addr->sa_data[1], addr->sa_data[2], addr->sa_data[3], ++ //addr->sa_data[4], addr->sa_data[5]); ++ _rtw_memcpy(padapter->eeprompriv.mac_addr, addr->sa_data, ETH_ALEN); ++ //_rtw_memcpy(pnetdev->dev_addr, addr->sa_data, ETH_ALEN); ++ //padapter->bset_hwaddr = _TRUE; ++ } ++ ++ return 0; ++} ++ ++static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct recv_priv *precvpriv = &(padapter->recvpriv); ++ ++ padapter->stats.tx_packets = pxmitpriv->tx_pkts;//pxmitpriv->tx_pkts++; ++ padapter->stats.rx_packets = precvpriv->rx_pkts;//precvpriv->rx_pkts++; ++ padapter->stats.tx_dropped = pxmitpriv->tx_drop; ++ padapter->stats.rx_dropped = precvpriv->rx_drop; ++ padapter->stats.tx_bytes = pxmitpriv->tx_bytes; ++ padapter->stats.rx_bytes = precvpriv->rx_bytes; ++ ++ return &padapter->stats; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++/* ++ * AC to queue mapping ++ * ++ * AC_VO -> queue 0 ++ * AC_VI -> queue 1 ++ * AC_BE -> queue 2 ++ * AC_BK -> queue 3 ++ */ ++static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 }; ++ ++/* Given a data frame determine the 802.1p/1d tag to use. */ ++unsigned int rtw_classify8021d(struct sk_buff *skb) ++{ ++ unsigned int dscp; ++ ++ /* skb->priority values from 256->263 are magic values to ++ * directly indicate a specific 802.1d priority. This is used ++ * to allow 802.1d priority to be passed directly in from VLAN ++ * tags, etc. ++ */ ++ if (skb->priority >= 256 && skb->priority <= 263) ++ return skb->priority - 256; ++ ++ switch (skb->protocol) { ++ case htons(ETH_P_IP): ++ dscp = ip_hdr(skb)->tos & 0xfc; ++ break; ++ default: ++ return 0; ++ } ++ ++ return dscp >> 5; ++} ++ ++static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb) ++{ ++ _adapter *padapter = rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ skb->priority = rtw_classify8021d(skb); ++ ++ if(pmlmepriv->acm_mask != 0) ++ { ++ skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority); ++ } ++ ++ return rtw_1d_to_queue[skb->priority]; ++} ++ ++u16 rtw_recv_select_queue(struct sk_buff *skb) ++{ ++ struct iphdr *piphdr; ++ unsigned int dscp; ++ u16 eth_type; ++ u32 priority; ++ u8 *pdata = skb->data; ++ ++ _rtw_memcpy(ð_type, pdata+(ETH_ALEN<<1), 2); ++ ++ switch (eth_type) { ++ case htons(ETH_P_IP): ++ ++ piphdr = (struct iphdr *)(pdata+ETH_HLEN); ++ ++ dscp = piphdr->tos & 0xfc; ++ ++ priority = dscp >> 5; ++ ++ break; ++ default: ++ priority = 0; ++ } ++ ++ return rtw_1d_to_queue[priority]; ++ ++} ++ ++#endif ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtw_netdev_ops = { ++ .ndo_open = netdev_open, ++ .ndo_stop = netdev_close, ++ .ndo_start_xmit = rtw_xmit_entry, ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ .ndo_select_queue = rtw_select_queue, ++#endif ++ .ndo_set_mac_address = rtw_net_set_mac_address, ++ .ndo_get_stats = rtw_net_get_stats, ++ .ndo_do_ioctl = rtw_ioctl, ++}; ++#endif ++ ++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) ++{ ++ _adapter *padapter = rtw_netdev_priv(pnetdev); ++ ++#ifdef CONFIG_EASY_REPLACEMENT ++ struct net_device *TargetNetdev = NULL; ++ _adapter *TargetAdapter = NULL; ++ struct net *devnet = NULL; ++ ++ if(padapter->bDongle == 1) ++ { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ TargetNetdev = dev_get_by_name("wlan0"); ++#else ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = pnetdev->nd_net; ++ #else ++ devnet = dev_net(pnetdev); ++ #endif ++ TargetNetdev = dev_get_by_name(devnet, "wlan0"); ++#endif ++ if(TargetNetdev) { ++ DBG_871X("Force onboard module driver disappear !!!\n"); ++ TargetAdapter = rtw_netdev_priv(TargetNetdev); ++ TargetAdapter->DriverState = DRIVER_DISAPPEAR; ++ ++ padapter->pid[0] = TargetAdapter->pid[0]; ++ padapter->pid[1] = TargetAdapter->pid[1]; ++ padapter->pid[2] = TargetAdapter->pid[2]; ++ ++ dev_put(TargetNetdev); ++ unregister_netdev(TargetNetdev); ++ ++ if(TargetAdapter->chip_type == padapter->chip_type) ++ rtw_proc_remove_one(TargetNetdev); ++ ++ padapter->DriverState = DRIVER_REPLACE_DONGLE; ++ } ++ } ++#endif ++ ++ if(dev_alloc_name(pnetdev, ifname) < 0) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("dev_alloc_name, fail! \n")); ++ } ++ ++ netif_carrier_off(pnetdev); ++ //rtw_netif_stop_queue(pnetdev); ++ ++ return 0; ++} ++ ++struct net_device *rtw_init_netdev(_adapter *old_padapter) ++{ ++ _adapter *padapter; ++ struct net_device *pnetdev; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+init_net_dev\n")); ++ ++ if(old_padapter != NULL) ++ pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter); ++ else ++ pnetdev = rtw_alloc_etherdev(sizeof(_adapter)); ++ ++ if (!pnetdev) ++ return NULL; ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ padapter->pnetdev = pnetdev; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ SET_MODULE_OWNER(pnetdev); ++#endif ++ ++ //pnetdev->init = NULL; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ DBG_871X("register rtw_netdev_ops to netdev_ops\n"); ++ pnetdev->netdev_ops = &rtw_netdev_ops; ++#else ++ pnetdev->open = netdev_open; ++ pnetdev->stop = netdev_close; ++ pnetdev->hard_start_xmit = rtw_xmit_entry; ++ pnetdev->set_mac_address = rtw_net_set_mac_address; ++ pnetdev->get_stats = rtw_net_get_stats; ++ pnetdev->do_ioctl = rtw_ioctl; ++#endif ++ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ pnetdev->features |= NETIF_F_IP_CSUM; ++#endif ++ //pnetdev->tx_timeout = NULL; ++ pnetdev->watchdog_timeo = HZ*3; /* 3 second timeout */ ++#ifdef CONFIG_WIRELESS_EXT ++ pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def; ++#endif ++ ++#ifdef WIRELESS_SPY ++ //priv->wireless_data.spy_data = &priv->spy_data; ++ //pnetdev->wireless_data = &priv->wireless_data; ++#endif ++ ++ //step 2. ++ loadparam(padapter, pnetdev); ++ ++ return pnetdev; ++ ++} ++ ++u32 rtw_start_drv_threads(_adapter *padapter) ++{ ++ u32 _status = _SUCCESS; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_start_drv_threads\n")); ++#ifdef CONFIG_XMIT_THREAD_MODE ++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) ++ if(padapter->adapter_type == PRIMARY_ADAPTER){ ++#endif ++ padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); ++ if(IS_ERR(padapter->xmitThread)) ++ _status = _FAIL; ++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) ++ } ++#endif // CONFIG_SDIO_HCI+CONFIG_CONCURRENT_MODE ++#endif ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); ++ if(IS_ERR(padapter->recvThread)) ++ _status = _FAIL; ++#endif ++ ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->isprimary == _TRUE) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); ++ if(IS_ERR(padapter->cmdThread)) ++ _status = _FAIL; ++ else ++ _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); //wait for cmd_thread to run ++ } ++ ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); ++ if(IS_ERR(padapter->evtThread)) ++ _status = _FAIL; ++#endif ++ ++ rtw_hal_start_thread(padapter); ++ return _status; ++ ++} ++ ++void rtw_unregister_netdevs(struct dvobj_priv *dvobj) ++{ ++ int i; ++ _adapter *padapter = NULL; ++ ++ for(i=0;iiface_nums;i++) ++ { ++ struct net_device *pnetdev = NULL; ++ ++ padapter = dvobj->padapters[i]; ++ ++ if (padapter == NULL) ++ continue; ++ ++ pnetdev = padapter->pnetdev; ++ ++ if((padapter->DriverState != DRIVER_DISAPPEAR) && pnetdev) { ++ ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++#endif ++ ++ } ++ ++} ++ ++ ++void rtw_stop_drv_threads (_adapter *padapter) ++{ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_stop_drv_threads\n")); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->isprimary == _TRUE) ++#endif //CONFIG_CONCURRENT_MODE ++ { ++ rtw_stop_cmd_thread(padapter); ++ } ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _rtw_up_sema(&padapter->evtpriv.evt_notify); ++ if(padapter->evtThread){ ++ _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema); ++ } ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++ // Below is to termindate tx_thread... ++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) ++ // Only wake-up primary adapter ++ if(padapter->adapter_type == PRIMARY_ADAPTER) ++#endif //SDIO_HCI + CONCURRENT ++ { ++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema); ++ _rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema); ++ } ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt: rtw_xmit_thread can be terminated ! \n")); ++#endif ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ // Below is to termindate rx_thread... ++ _rtw_up_sema(&padapter->recvpriv.recv_sema); ++ _rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt:recv_thread can be terminated! \n")); ++#endif ++ ++ rtw_hal_stop_thread(padapter); ++} ++ ++u8 rtw_init_default_value(_adapter *padapter); ++u8 rtw_init_default_value(_adapter *padapter) ++{ ++ u8 ret = _SUCCESS; ++ struct registry_priv* pregistrypriv = &padapter->registrypriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ //xmit_priv ++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; ++ pxmitpriv->vcs = pregistrypriv->vcs_type; ++ pxmitpriv->vcs_type = pregistrypriv->vcs_type; ++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; ++ pxmitpriv->frag_len = pregistrypriv->frag_thresh; ++ ++ ++ ++ //recv_priv ++ ++ ++ //mlme_priv ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ pmlmepriv->scan_mode = SCAN_ACTIVE; ++ ++ //qos_priv ++ //pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable; ++ ++ //ht_priv ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->htpriv.ampdu_enable = _FALSE;//set to disabled ++#endif ++ ++ //security_priv ++ //rtw_get_encrypt_decrypt_from_registrypriv(padapter); ++ psecuritypriv->binstallGrpkey = _FAIL; ++ psecuritypriv->sw_encrypt=pregistrypriv->software_encrypt; ++ psecuritypriv->sw_decrypt=pregistrypriv->software_decrypt; ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system ++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ ++ psecuritypriv->dot11PrivacyKeyIndex = 0; ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psecuritypriv->dot118021XGrpKeyid = 1; ++ ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled; ++ ++ ++ //pwrctrl_priv ++ ++ ++ //registry_priv ++ rtw_init_registrypriv_dev_network(padapter); ++ rtw_update_registrypriv_dev_network(padapter); ++ ++ ++ //hal_priv ++ rtw_hal_def_value_init(padapter); ++ ++ //misc. ++ padapter->bReadPortCancel = _FALSE; ++ padapter->bWritePortCancel = _FALSE; ++ padapter->bRxRSSIDisplay = 0; ++ padapter->bNotifyChannelChange = 0; ++#ifdef CONFIG_P2P ++ padapter->bShowGetP2PState = 1; ++#endif ++ ++ return ret; ++} ++ ++u8 rtw_reset_drv_sw(_adapter *padapter) ++{ ++ u8 ret8=_SUCCESS; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++ //hal_priv ++ rtw_hal_def_value_init(padapter); ++ padapter->bReadPortCancel = _FALSE; ++ padapter->bWritePortCancel = _FALSE; ++ padapter->bRxRSSIDisplay = 0; ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ ++ padapter->xmitpriv.tx_pkts = 0; ++ padapter->recvpriv.rx_pkts = 0; ++ ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY |_FW_UNDER_LINKING); ++ ++#ifdef CONFIG_AUTOSUSPEND ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ adapter_to_dvobj(padapter)->pusbdev->autosuspend_disabled = 1;//autosuspend disabled by the user ++ #endif ++#endif ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ rtw_hal_sreset_reset_value(padapter); ++#endif ++ pwrctrlpriv->pwr_state_check_cnts = 0; ++ ++ //mlmeextpriv ++ padapter->mlmeextpriv.sitesurvey_res.state= SCAN_DISABLE; ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ ++ return ret8; ++} ++ ++ ++u8 rtw_init_drv_sw(_adapter *padapter) ++{ ++ ++ u8 ret8=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_init_drv_sw\n")); ++ ++ if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init cmd_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ padapter->cmdpriv.padapter=padapter; ++ ++ if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init evt_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ ++ if (rtw_init_mlme_priv(padapter) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_P2P ++ rtw_init_wifidirect_timers(padapter); ++ init_wifidirect_info(padapter, P2P_ROLE_DISABLE); ++ reset_global_wifidirect_info(padapter); ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_init_cfg80211_wifidirect_info(padapter); ++ #endif ++#ifdef CONFIG_WFD ++ if(rtw_init_wifi_display_info(padapter) == _FAIL) ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init init_wifi_display_info\n")); ++#endif ++#endif /* CONFIG_P2P */ ++ ++ if(init_mlme_ext_priv(padapter) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_ext_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_TDLS ++ if(rtw_init_tdls_info(padapter) == _FAIL) ++ { ++ DBG_871X("Can't rtw_init_tdls_info\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++#endif //CONFIG_TDLS ++ ++ if(_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_xmit_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ if(_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_recv_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ // add for CONFIG_IEEE80211W, none 11w also can use ++ _rtw_spinlock_init(&padapter->security_key_mutex); ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); ++ ++ //_init_timer(&(padapter->securitypriv.tkip_timer), padapter->pifp, rtw_use_tkipkey_handler, padapter); ++ ++ if(_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_sta_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ padapter->stapriv.padapter = padapter; ++ padapter->setband = GHZ24_50; ++ padapter->fix_rate = 0xFF; ++ rtw_init_bcmc_stainfo(padapter); ++ ++ rtw_init_pwrctrl_priv(padapter); ++ ++ //_rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv));//move to mlme_priv ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (init_mp_priv(padapter) == _FAIL) { ++ DBG_871X("%s: initialize MP private data Fail!\n", __func__); ++ } ++#endif ++ ++ ret8 = rtw_init_default_value(padapter); ++ ++ rtw_hal_dm_init(padapter); ++ rtw_hal_sw_led_init(padapter); ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ rtw_hal_sreset_init(padapter); ++#endif ++ ++#ifdef CONFIG_INTEL_WIDI ++ if(rtw_init_intel_widi(padapter) == _FAIL) ++ { ++ DBG_871X("Can't rtw_init_intel_widi\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++#endif //CONFIG_INTEL_WIDI ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ padapter->WapiSupport = true; //set true temp, will revise according to Efuse or Registry value later. ++ rtw_wapi_init(padapter); ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ _rtw_spinlock_init(&padapter->br_ext_lock); ++#endif // CONFIG_BR_EXT ++ ++exit: ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_init_drv_sw\n")); ++ ++ _func_exit_; ++ ++ return ret8; ++ ++} ++ ++#ifdef CONFIG_WOWLAN ++void rtw_cancel_dynamic_chk_timer(_adapter *padapter) ++{ ++ _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel dynamic_chk_timer! \n")); ++} ++#endif ++ ++void rtw_cancel_all_timer(_adapter *padapter) ++{ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_cancel_all_timer\n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel association timer complete! \n")); ++ ++ //_cancel_timer_ex(&padapter->securitypriv.tkip_timer); ++ //RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel tkip_timer! \n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel scan_to_timer! \n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel dynamic_chk_timer! \n")); ++ ++ // cancel sw led timer ++ rtw_hal_sw_led_deinit(padapter); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel DeInitSwLeds! \n")); ++ ++ _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++#ifdef CONFIG_P2P ++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++#endif //CONFIG_P2P ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer); ++ rtw_clear_scan_deny(padapter); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel set_scan_deny_timer! \n")); ++#endif ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); ++#endif ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ _cancel_timer_ex(&padapter->mlmepriv.event_polling_timer); ++#endif ++ ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ if (padapter->HalFunc.hal_cancel_checkbthang_workqueue) ++ padapter->HalFunc.hal_cancel_checkbthang_workqueue(padapter); ++#endif ++ //cancel dm timer ++ rtw_hal_dm_deinit(padapter); ++ ++} ++ ++u8 rtw_free_drv_sw(_adapter *padapter) ++{ ++ struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("==>rtw_free_drv_sw")); ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_free(padapter); ++#endif ++ ++ //we can call rtw_p2p_enable here, but: ++ // 1. rtw_p2p_enable may have IO operation ++ // 2. rtw_p2p_enable is bundled with wext interface ++ #ifdef CONFIG_P2P ++ { ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++#ifdef CONFIG_CONCURRENT_MODE ++ _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); ++#endif // CONFIG_CONCURRENT_MODE ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ } ++ } ++ #endif ++ // add for CONFIG_IEEE80211W, none 11w also can use ++ _rtw_spinlock_free(&padapter->security_key_mutex); ++ ++#ifdef CONFIG_BR_EXT ++ _rtw_spinlock_free(&padapter->br_ext_lock); ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_INTEL_WIDI ++ rtw_free_intel_widi(padapter); ++#endif //CONFIG_INTEL_WIDI ++ ++ free_mlme_ext_priv(&padapter->mlmeextpriv); ++ ++#ifdef CONFIG_TDLS ++ //rtw_free_tdls_info(&padapter->tdlsinfo); ++#endif //CONFIG_TDLS ++ ++ rtw_free_cmd_priv(&padapter->cmdpriv); ++ ++ rtw_free_evt_priv(&padapter->evtpriv); ++ ++ rtw_free_mlme_priv(&padapter->mlmepriv); ++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) ++ if (padapter->HalFunc.hal_free_checkbthang_workqueue) ++ padapter->HalFunc.hal_free_checkbthang_workqueue(padapter); ++#endif ++ //free_io_queue(padapter); ++ ++ _rtw_free_xmit_priv(&padapter->xmitpriv); ++ ++ _rtw_free_sta_priv(&padapter->stapriv); //will free bcmc_stainfo here ++ ++ _rtw_free_recv_priv(&padapter->recvpriv); ++ ++ rtw_free_pwrctrl_priv(padapter); ++ ++ //rtw_mfree((void *)padapter, sizeof (padapter)); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ free_drvext(&padapter->drvextpriv); ++#endif ++ ++ rtw_hal_free_data(padapter); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("<==rtw_free_drv_sw\n")); ++ ++ //free the old_pnetdev ++ if(padapter->rereg_nd_name_priv.old_pnetdev) { ++ free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); ++ padapter->rereg_nd_name_priv.old_pnetdev = NULL; ++ } ++ ++ // clear pbuddy_adapter to avoid access wrong pointer. ++ if(padapter->pbuddy_adapter != NULL) { ++ padapter->pbuddy_adapter->pbuddy_adapter = NULL; ++ } ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_free_drv_sw\n")); ++ ++ return _SUCCESS; ++ ++} ++ ++#ifdef CONFIG_CONCURRENT_MODE ++int _netdev_if2_open(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ _adapter *primary_padapter = padapter->pbuddy_adapter; ++ ++ DBG_871X("+871x_drv - if2_open, bup=%d\n", padapter->bup); ++ ++ if(primary_padapter->bup == _FALSE || primary_padapter->hw_init_completed == _FALSE) ++ { ++ _netdev_open(primary_padapter->pnetdev); ++ } ++ ++ if(padapter->bup == _FALSE && primary_padapter->bup == _TRUE && ++ primary_padapter->hw_init_completed == _TRUE) ++ { ++ int i; ++ ++ padapter->bDriverStopped = _FALSE; ++ padapter->bSurpriseRemoved = _FALSE; ++ padapter->bCardDisableWOHSM = _FALSE; ++ ++ padapter->bFWReady = primary_padapter->bFWReady; ++ ++ //if (init_mlme_ext_priv(padapter) == _FAIL) ++ // goto netdev_if2_open_error; ++ ++ ++ if(rtw_start_drv_threads(padapter) == _FAIL) ++ { ++ goto netdev_if2_open_error; ++ } ++ ++ ++ if(padapter->intf_start) ++ { ++ padapter->intf_start(padapter); ++ } ++ ++ rtw_proc_init_one(pnetdev); ++ ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_init_wiphy(padapter); ++#endif ++ ++ padapter->bup = _TRUE; ++ ++ } ++ ++ padapter->net_closed = _FALSE; ++ ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ ++ DBG_871X("-871x_drv - if2_open, bup=%d\n", padapter->bup); ++ return 0; ++ ++netdev_if2_open_error: ++ ++ padapter->bup = _FALSE; ++ ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ ++ return (-1); ++ ++} ++ ++int netdev_if2_open(struct net_device *pnetdev) ++{ ++ int ret; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); ++ ret = _netdev_if2_open(pnetdev); ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); ++ return ret; ++} ++ ++static int netdev_if2_close(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ ++ padapter->net_closed = _TRUE; ++ ++ if(pnetdev) ++ { ++ if (!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_scan_abort(padapter); ++ wdev_to_priv(padapter->rtw_wdev)->bandroid_scan = _FALSE; ++#endif ++ ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtw_netdev_if2_ops = { ++ .ndo_open = netdev_if2_open, ++ .ndo_stop = netdev_if2_close, ++ .ndo_start_xmit = rtw_xmit_entry, ++ .ndo_set_mac_address = rtw_net_set_mac_address, ++ .ndo_get_stats = rtw_net_get_stats, ++ .ndo_do_ioctl = rtw_ioctl, ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ .ndo_select_queue = rtw_select_queue, ++#endif ++}; ++#endif ++ ++ ++#ifdef CONFIG_USB_HCI ++ #include ++#endif ++#ifdef CONFIG_SDIO_HCI ++ #include ++#endif ++_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops)) ++{ ++ int res = _FAIL; ++ struct net_device *pnetdev = NULL; ++ _adapter *padapter = NULL; ++ struct dvobj_priv *pdvobjpriv; ++ u8 mac[ETH_ALEN]; ++ ++ /****** init netdev ******/ ++ pnetdev = rtw_init_netdev(NULL); ++ if (!pnetdev) ++ goto error_rtw_drv_if2_init; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ DBG_871X("register rtw_netdev_if2_ops to netdev_ops\n"); ++ pnetdev->netdev_ops = &rtw_netdev_if2_ops; ++#else ++ pnetdev->open = netdev_if2_open; ++ pnetdev->stop = netdev_if2_close; ++#endif ++ ++#ifdef CONFIG_NO_WIRELESS_HANDLERS ++ pnetdev->wireless_handlers = NULL; ++#endif ++ ++ /****** init adapter ******/ ++ padapter = rtw_netdev_priv(pnetdev); ++ _rtw_memcpy(padapter, primary_padapter, sizeof(_adapter)); ++ ++ // ++ padapter->bup = _FALSE; ++ padapter->net_closed = _TRUE; ++ padapter->hw_init_completed = _FALSE; ++ padapter->dir_dev = NULL; ++ padapter->dir_odm = NULL; ++ ++ //set adapter_type/iface type ++ padapter->isprimary = _FALSE; ++ padapter->adapter_type = SECONDARY_ADAPTER; ++ padapter->pbuddy_adapter = primary_padapter; ++ padapter->iface_id = IFACE_ID1; ++#ifndef CONFIG_HWPORT_SWAP //Port0 -> Pri , Port1 -> Sec ++ padapter->iface_type = IFACE_PORT1; ++#else ++ padapter->iface_type = IFACE_PORT0; ++#endif //CONFIG_HWPORT_SWAP ++ // ++ padapter->pnetdev = pnetdev; ++ ++ /****** setup dvobj ******/ ++ pdvobjpriv = adapter_to_dvobj(padapter); ++ pdvobjpriv->if2 = padapter; ++ pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter; ++ ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(pdvobjpriv)); ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_alloc(padapter, dvobj_to_dev(pdvobjpriv)); ++ #endif //CONFIG_IOCTL_CFG80211 ++ ++ //set interface_type/chip_type/HardwareType ++ padapter->interface_type = primary_padapter->interface_type; ++ padapter->chip_type = primary_padapter->chip_type; ++ padapter->HardwareType = primary_padapter->HardwareType; ++ ++ //step 2. hook HalFunc, allocate HalData ++ hal_set_hal_ops(padapter); ++ ++ padapter->HalFunc.inirp_init = NULL; ++ padapter->HalFunc.inirp_deinit = NULL; ++ ++ // ++ padapter->intf_start = primary_padapter->intf_start; ++ padapter->intf_stop = primary_padapter->intf_stop; ++ ++ //step init_io_priv ++ if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n")); ++ } ++ ++ //step read_chip_version ++ rtw_hal_read_chip_version(padapter); ++ ++ //step usb endpoint mapping ++ rtw_hal_chip_configure(padapter); ++ ++ ++ //init drv data ++ if(rtw_init_drv_sw(padapter)!= _SUCCESS) ++ goto error_rtw_drv_if2_init; ++ ++ //get mac address from primary_padapter ++ _rtw_memcpy(mac, primary_padapter->eeprompriv.mac_addr, ETH_ALEN); ++ ++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) && ++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) || ++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) && ++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0))) ++ { ++ mac[0] = 0x00; ++ mac[1] = 0xe0; ++ mac[2] = 0x4c; ++ mac[3] = 0x87; ++ mac[4] = 0x11; ++ mac[5] = 0x22; ++ } ++ else ++ { ++ //If the BIT1 is 0, the address is universally administered. ++ //If it is 1, the address is locally administered ++ mac[0] |= BIT(1); // locally administered ++ ++ } ++ ++ _rtw_memcpy(padapter->eeprompriv.mac_addr, mac, ETH_ALEN); ++#ifdef CONFIG_P2P ++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr); ++#endif ++ primary_padapter->pbuddy_adapter = padapter; ++ ++ res = _SUCCESS; ++ ++ return padapter; ++ ++ ++error_rtw_drv_if2_init: ++ ++ if(padapter) ++ rtw_free_drv_sw(padapter); ++ ++ if (pnetdev) ++ rtw_free_netdev(pnetdev); ++ ++ return NULL; ++ ++} ++ ++void rtw_drv_if2_free(_adapter *if2) ++{ ++ _adapter *padapter = if2; ++ struct net_device *pnetdev = NULL; ++ ++ if (padapter == NULL) ++ return; ++ ++ pnetdev = padapter->pnetdev; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_free(padapter->rtw_wdev); ++#endif /* CONFIG_IOCTL_CFG80211 */ ++ ++ ++ rtw_free_drv_sw(padapter); ++ ++ rtw_free_netdev(pnetdev); ++ ++} ++ ++void rtw_drv_if2_stop(_adapter *if2) ++{ ++ _adapter *padapter = if2; ++ //struct net_device *pnetdev = NULL; ++ ++ if (padapter == NULL) ++ return; ++/* ++ pnetdev = padapter->pnetdev; ++ ++ if (pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++*/ ++ rtw_cancel_all_timer(padapter); ++ ++ if (padapter->bup == _TRUE) { ++ padapter->bDriverStopped = _TRUE; ++ #ifdef CONFIG_XMIT_ACK ++ if (padapter->xmitpriv.ack_tx) ++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); ++ #endif ++ ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ rtw_stop_drv_threads(padapter); ++ ++ padapter->bup = _FALSE; ++ } ++/* ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++ #endif ++*/ ++} ++#endif //end of CONFIG_CONCURRENT_MODE ++ ++#ifdef CONFIG_BR_EXT ++void netdev_br_init(struct net_device *netdev) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ //struct net_bridge *br = netdev->br_port->br;//->dev->dev_addr; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if (netdev->br_port) ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if (rcu_dereference(adapter->pnetdev->rx_handler_data)) ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ { ++ struct net_device *br_netdev; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ br_netdev = dev_get_by_name(CONFIG_BR_EXT_BRNAME); ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ struct net *devnet = NULL; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = netdev->nd_net; ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = dev_net(netdev); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ ++ br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ ++ if (br_netdev) { ++ memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN); ++ dev_put(br_netdev); ++ } else ++ DBG_871X("%s()-%d: dev_get_by_name(%s) failed!", __FUNCTION__, __LINE__, CONFIG_BR_EXT_BRNAME); ++ } ++ ++ adapter->ethBrExtInfo.addPPPoETag = 1; ++ } ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++} ++#endif //CONFIG_BR_EXT ++ ++static int _rtw_drv_register_netdev(_adapter *padapter, char *name) ++{ ++ int ret = _SUCCESS; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++ /* alloc netdev name */ ++ rtw_init_netdev_name(pnetdev, name); ++ ++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) { ++ DBG_871X(FUNC_NDEV_FMT "Failed!\n", FUNC_NDEV_ARG(pnetdev)); ++ ret = _FAIL; ++ goto error_register_netdev; ++ } ++ ++ DBG_871X("%s, MAC Address (if%d) = " MAC_FMT "\n", __FUNCTION__, (padapter->iface_id+1), MAC_ARG(pnetdev->dev_addr)); ++ ++ return ret; ++ ++error_register_netdev: ++ ++ if(padapter->iface_id > IFACE_ID0) ++ { ++ rtw_free_drv_sw(padapter); ++ ++ rtw_free_netdev(pnetdev); ++ } ++ ++ return ret; ++} ++ ++int rtw_drv_register_netdev(_adapter *if1) ++{ ++ int i, status = _SUCCESS; ++ struct dvobj_priv *dvobj = if1->dvobj; ++ ++ if(dvobj->iface_nums < IFACE_ID_MAX) ++ { ++ for(i=0; iiface_nums; i++) ++ { ++ _adapter *padapter = dvobj->padapters[i]; ++ ++ if(padapter) ++ { ++ char *name; ++ ++ if(padapter->iface_id == IFACE_ID0) ++ name = if1->registrypriv.ifname; ++ else if(padapter->iface_id == IFACE_ID1) ++ name = if1->registrypriv.if2name; ++ else ++ name = "wlan%d"; ++ ++ if((status = _rtw_drv_register_netdev(padapter, name)) != _SUCCESS) { ++ break; ++ } ++ } ++ } ++ } ++ ++ return status; ++} ++ ++int _netdev_open(struct net_device *pnetdev) ++{ ++ uint status; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - dev_open\n")); ++ DBG_871X("+871x_drv - drv_open, bup=%d\n", padapter->bup); ++ ++ if(pwrctrlpriv->ps_flag == _TRUE){ ++ padapter->net_closed = _FALSE; ++ goto netdev_open_normal_process; ++ } ++ ++ if(padapter->bup == _FALSE) ++ { ++ padapter->bDriverStopped = _FALSE; ++ padapter->bSurpriseRemoved = _FALSE; ++ padapter->bCardDisableWOHSM = _FALSE; ++ ++ status = rtw_hal_init(padapter); ++ if (status ==_FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("rtl871x_hal_init(): Can't init h/w!\n")); ++ goto netdev_open_error; ++ } ++ ++ DBG_871X("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++ rtw_bb_rf_gain_offset(padapter); ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++ status=rtw_start_drv_threads(padapter); ++ if(status ==_FAIL) ++ { ++ DBG_871X("Initialize driver software resource Failed!\n"); ++ goto netdev_open_error; ++ } ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ init_drvext(padapter); ++#endif ++ ++ if(padapter->intf_start) ++ { ++ padapter->intf_start(padapter); ++ } ++ ++#ifndef RTK_DMP_PLATFORM ++ rtw_proc_init_one(pnetdev); ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_init_wiphy(padapter); ++#endif ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ padapter->bup = _TRUE; ++ ++ pwrctrlpriv->bips_processing = _FALSE; ++ } ++ padapter->net_closed = _FALSE; ++ ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ ++#ifdef CONFIG_DETECT_C2H_BY_POLLING ++ _set_timer(&padapter->mlmepriv.event_polling_timer, 200); ++#endif ++ ++ rtw_set_pwr_state_check_timer(pwrctrlpriv); ++ ++ //netif_carrier_on(pnetdev);//call this func when rtw_joinbss_event_callback return success ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ ++#ifdef CONFIG_BR_EXT ++ netdev_br_init(pnetdev); ++#endif // CONFIG_BR_EXT ++ ++netdev_open_normal_process: ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ { ++ _adapter *sec_adapter = padapter->pbuddy_adapter; ++ if(sec_adapter && (sec_adapter->bup == _FALSE)) ++ _netdev_if2_open(sec_adapter->pnetdev); ++ } ++ #endif ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - dev_open\n")); ++ DBG_871X("-871x_drv - drv_open, bup=%d\n", padapter->bup); ++ ++ return 0; ++ ++netdev_open_error: ++ ++ padapter->bup = _FALSE; ++ ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("-871x_drv - dev_open, fail!\n")); ++ DBG_871X("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); ++ ++ return (-1); ++ ++} ++ ++int netdev_open(struct net_device *pnetdev) ++{ ++ int ret; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ ++ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); ++ ret = _netdev_open(pnetdev); ++ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_IPS ++int ips_netdrv_open(_adapter *padapter) ++{ ++ int status = _SUCCESS; ++ padapter->net_closed = _FALSE; ++ DBG_871X("===> %s.........\n",__FUNCTION__); ++ ++ ++ padapter->bDriverStopped = _FALSE; ++ padapter->bCardDisableWOHSM = _FALSE; ++ //padapter->bup = _TRUE; ++ ++ status = rtw_hal_init(padapter); ++ if (status ==_FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("ips_netdrv_open(): Can't init h/w!\n")); ++ goto netdev_open_error; ++ } ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++ rtw_bb_rf_gain_offset(padapter); ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++ if(padapter->intf_start) ++ { ++ padapter->intf_start(padapter); ++ } ++ ++ rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer,5000); ++ ++ return _SUCCESS; ++ ++netdev_open_error: ++ //padapter->bup = _FALSE; ++ DBG_871X("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup); ++ ++ return _FAIL; ++} ++ ++ ++int rtw_ips_pwr_up(_adapter *padapter) ++{ ++ int result; ++ u32 start_time = rtw_get_current_time(); ++ DBG_871X("===> rtw_ips_pwr_up..............\n"); ++ rtw_reset_drv_sw(padapter); ++ ++ result = ips_netdrv_open(padapter); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ DBG_871X("<=== rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time)); ++ return result; ++ ++} ++ ++void rtw_ips_pwr_down(_adapter *padapter) ++{ ++ u32 start_time = rtw_get_current_time(); ++ DBG_871X("===> rtw_ips_pwr_down...................\n"); ++ ++ padapter->bCardDisableWOHSM = _TRUE; ++ padapter->net_closed = _TRUE; ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_ips_dev_unload(padapter); ++ padapter->bCardDisableWOHSM = _FALSE; ++ DBG_871X("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); ++} ++#endif ++void rtw_ips_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ DBG_871X("====> %s...\n",__FUNCTION__); ++ ++ rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0); ++ ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ rtw_hal_deinit(padapter); ++ } ++ ++} ++ ++#ifdef CONFIG_RF_GAIN_OFFSET ++void rtw_bb_rf_gain_offset(_adapter *padapter) ++{ ++ u8 value = padapter->eeprompriv.EEPROMRFGainOffset; ++ u8 tmp = 0x3e; ++ u32 res; ++ ++ DBG_871X("+%s value: 0x%02x+\n", __func__, value); ++ ++ if (value & RF_GAIN_OFFSET_ON) { ++ //DBG_871X("Offset RF Gain.\n"); ++ //DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal=0x%x\n",padapter->eeprompriv.EEPROMRFGainVal); ++ if(padapter->eeprompriv.EEPROMRFGainVal != 0xff){ ++#ifdef CONFIG_RTL8723A ++ res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0xd, 0xffffffff); ++ //DBG_871X("Offset RF Gain. reg 0xd=0x%x\n",res); ++ res &= 0xfff87fff; ++ ++ res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; ++ //DBG_871X("Offset RF Gain. reg 0xd=0x%x\n",res); ++ ++ rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); ++ ++ res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0xe, 0xffffffff); ++ DBG_871X("Offset RF Gain. reg 0xe=0x%x\n",res); ++ res &= 0xfffffff0; ++ ++ res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f); ++ //DBG_871X("Offset RF Gain. reg 0xe=0x%x\n",res); ++ ++ rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); ++#else ++ res = rtw_hal_read_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, 0xffffffff); ++ DBG_871X("REG_RF_BB_GAIN_OFFSET=%x \n",res); ++ res &= 0xfff87fff; ++ res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; ++ DBG_871X("write REG_RF_BB_GAIN_OFFSET=%x \n",res); ++ rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); ++#endif ++ } ++ else ++ { ++ //DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal=0x%x != 0xff, didn't run Kfree\n",padapter->eeprompriv.EEPROMRFGainVal); ++ } ++ } else { ++ //DBG_871X("Using the default RF gain.\n"); ++ } ++ ++} ++#endif //CONFIG_RF_GAIN_OFFSET ++ ++int pm_netdev_open(struct net_device *pnetdev,u8 bnormal) ++{ ++ int status; ++ ++ ++ if (_TRUE == bnormal) ++ status = netdev_open(pnetdev); ++#ifdef CONFIG_IPS ++ else ++ status = (_SUCCESS == ips_netdrv_open((_adapter *)rtw_netdev_priv(pnetdev)))?(0):(-1); ++#endif ++ ++ return status; ++} ++ ++static int netdev_close(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - drv_close\n")); ++ ++ if(adapter_to_pwrctl(padapter)->bInternalAutoSuspend == _TRUE) ++ { ++ //rtw_pwr_wakeup(padapter); ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off) ++ adapter_to_pwrctl(padapter)->ps_flag = _TRUE; ++ } ++ padapter->net_closed = _TRUE; ++ ++/* if(!padapter->hw_init_completed) ++ { ++ DBG_871X("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed); ++ ++ padapter->bDriverStopped = _TRUE; ++ ++ rtw_dev_unload(padapter); ++ } ++ else*/ ++ if(adapter_to_pwrctl(padapter)->rf_pwrstate == rf_on){ ++ DBG_871X("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed); ++ ++ //s1. ++ if(pnetdev) ++ { ++ if (!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++#ifndef CONFIG_ANDROID ++ //s2. ++ LeaveAllPowerSaveMode(padapter); ++ rtw_disassoc_cmd(padapter, 500, _FALSE); ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ //s2-4. ++ rtw_free_network_queue(padapter,_TRUE); ++#endif ++ // Close LED ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ } ++ ++#ifdef CONFIG_BR_EXT ++ //if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) ++ { ++ //void nat25_db_cleanup(_adapter *priv); ++ nat25_db_cleanup(padapter); ++ } ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_P2P ++ rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_scan_abort(padapter); ++ wdev_to_priv(padapter->rtw_wdev)->bandroid_scan = _FALSE; ++ padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; //set this at the end ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ rtw_wapi_disable_tx(padapter); ++#endif ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - drv_close\n")); ++ DBG_871X("-871x_drv - drv_close, bup=%d\n", padapter->bup); ++ ++ return 0; ++ ++} ++ ++void rtw_ndev_destructor(struct net_device *ndev) ++{ ++ DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if (ndev->ieee80211_ptr) ++ rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev)); ++#endif ++ free_netdev(ndev); ++} ++ ++#ifdef CONFIG_ARP_KEEP_ALIVE ++struct route_info { ++ struct in_addr dst_addr; ++ struct in_addr src_addr; ++ struct in_addr gateway; ++ unsigned int dev_index; ++}; ++ ++static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info) ++{ ++ struct rtmsg *rt_msg; ++ struct rtattr *rt_attr; ++ int rt_len; ++ ++ rt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr); ++ if ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN)) ++ return; ++ ++ rt_attr = (struct rtattr *) RTM_RTA(rt_msg); ++ rt_len = RTM_PAYLOAD(nl_hdr); ++ ++ for (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) ++ { ++ switch (rt_attr->rta_type) { ++ case RTA_OIF: ++ rt_info->dev_index = *(int *) RTA_DATA(rt_attr); ++ break; ++ case RTA_GATEWAY: ++ rt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr); ++ break; ++ case RTA_PREFSRC: ++ rt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr); ++ break; ++ case RTA_DST: ++ rt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr); ++ break; ++ } ++ } ++} ++ ++static int route_dump(u32 *gw_addr ,int* gw_index) ++{ ++ int err = 0; ++ struct socket *sock; ++ struct { ++ struct nlmsghdr nlh; ++ struct rtgenmsg g; ++ } req; ++ struct msghdr msg; ++ struct iovec iov; ++ struct sockaddr_nl nladdr; ++ mm_segment_t oldfs; ++ char *pg; ++ int size = 0; ++ ++ err = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock); ++ if (err) ++ { ++ printk( ": Could not create a datagram socket, error = %d\n", -ENXIO); ++ return err; ++ } ++ ++ memset(&nladdr, 0, sizeof(nladdr)); ++ nladdr.nl_family = AF_NETLINK; ++ ++ req.nlh.nlmsg_len = sizeof(req); ++ req.nlh.nlmsg_type = RTM_GETROUTE; ++ req.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST; ++ req.nlh.nlmsg_pid = 0; ++ req.g.rtgen_family = AF_INET; ++ ++ iov.iov_base = &req; ++ iov.iov_len = sizeof(req); ++ ++ msg.msg_name = &nladdr; ++ msg.msg_namelen = sizeof(nladdr); ++ msg.msg_iov = &iov; ++ msg.msg_iovlen = 1; ++ msg.msg_control = NULL; ++ msg.msg_controllen = 0; ++ msg.msg_flags = MSG_DONTWAIT; ++ ++ oldfs = get_fs(); set_fs(KERNEL_DS); ++ err = sock_sendmsg(sock, &msg, sizeof(req)); ++ set_fs(oldfs); ++ ++ if (size < 0) ++ goto out_sock; ++ ++ pg = (char *) __get_free_page(GFP_KERNEL); ++ if (pg == NULL) { ++ err = -ENOMEM; ++ goto out_sock; ++ } ++ ++#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) ++restart: ++#endif ++ ++ for (;;) ++ { ++ struct nlmsghdr *h; ++ ++ iov.iov_base = pg; ++ iov.iov_len = PAGE_SIZE; ++ ++ oldfs = get_fs(); set_fs(KERNEL_DS); ++ err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT); ++ set_fs(oldfs); ++ ++ if (err < 0) ++ goto out_sock_pg; ++ ++ if (msg.msg_flags & MSG_TRUNC) { ++ err = -ENOBUFS; ++ goto out_sock_pg; ++ } ++ ++ h = (struct nlmsghdr*) pg; ++ ++ while (NLMSG_OK(h, err)) ++ { ++ struct route_info rt_info; ++ if (h->nlmsg_type == NLMSG_DONE) { ++ err = 0; ++ goto done; ++ } ++ ++ if (h->nlmsg_type == NLMSG_ERROR) { ++ struct nlmsgerr *errm = (struct nlmsgerr*) NLMSG_DATA(h); ++ err = errm->error; ++ printk( "NLMSG error: %d\n", errm->error); ++ goto done; ++ } ++ ++ if (h->nlmsg_type == RTM_GETROUTE) ++ { ++ printk( "RTM_GETROUTE: NLMSG: %d\n", h->nlmsg_type); ++ } ++ if (h->nlmsg_type != RTM_NEWROUTE) { ++ printk( "NLMSG: %d\n", h->nlmsg_type); ++ err = -EINVAL; ++ goto done; ++ } ++ ++ memset(&rt_info, 0, sizeof(struct route_info)); ++ parse_routes(h, &rt_info); ++ if(!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) ++ { ++ *gw_addr = rt_info.gateway.s_addr; ++ *gw_index = rt_info.dev_index; ++ ++ } ++ h = NLMSG_NEXT(h, err); ++ } ++ ++ if (err) ++ { ++ printk( "!!!Remnant of size %d %d %d\n", err, h->nlmsg_len, h->nlmsg_type); ++ err = -EINVAL; ++ break; ++ } ++ } ++ ++done: ++#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) ++ if (!err && req.g.rtgen_family == AF_INET) { ++ req.g.rtgen_family = AF_INET6; ++ ++ iov.iov_base = &req; ++ iov.iov_len = sizeof(req); ++ ++ msg.msg_name = &nladdr; ++ msg.msg_namelen = sizeof(nladdr); ++ msg.msg_iov = &iov; ++ msg.msg_iovlen = 1; ++ msg.msg_control = NULL; ++ msg.msg_controllen = 0; ++ msg.msg_flags=MSG_DONTWAIT; ++ ++ oldfs = get_fs(); set_fs(KERNEL_DS); ++ err = sock_sendmsg(sock, &msg, sizeof(req)); ++ set_fs(oldfs); ++ ++ if (err > 0) ++ goto restart; ++ } ++#endif ++ ++out_sock_pg: ++ free_page((unsigned long) pg); ++ ++out_sock: ++ sock_release(sock); ++ return err; ++} ++ ++static int arp_query(unsigned char *haddr, u32 paddr, ++ struct net_device *dev) ++{ ++ struct neighbour *neighbor_entry; ++ int ret = 0; ++ ++ neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev); ++ ++ if (neighbor_entry != NULL) { ++ neighbor_entry->used = jiffies; ++ if (neighbor_entry->nud_state & NUD_VALID) { ++ _rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len); ++ ret = 1; ++ } ++ neigh_release(neighbor_entry); ++ } ++ return ret; ++} ++ ++static int get_defaultgw(u32 *ip_addr ,char mac[]) ++{ ++ int gw_index = 0; // oif device index ++ struct net_device *gw_dev = NULL; //oif device ++ ++ route_dump(ip_addr, &gw_index); ++ ++ if( !(*ip_addr) || !gw_index ) ++ { ++ //DBG_871X("No default GW \n"); ++ return -1; ++ } ++ ++ gw_dev = dev_get_by_index(&init_net, gw_index); ++ ++ if(gw_dev == NULL) ++ { ++ //DBG_871X("get Oif Device Fail \n"); ++ return -1; ++ } ++ ++ if(!arp_query(mac, *ip_addr, gw_dev)) ++ { ++ //DBG_871X( "arp query failed\n"); ++ dev_put(gw_dev); ++ return -1; ++ ++ } ++ dev_put(gw_dev); ++ ++ return 0; ++} ++ ++int rtw_gw_addr_query(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u32 gw_addr = 0; // default gw address ++ unsigned char gw_mac[32] = {0}; // default gw mac ++ int i; ++ int res; ++ ++ res = get_defaultgw(&gw_addr, gw_mac); ++ if(!res) ++ { ++ pmlmepriv->gw_ip[0] = gw_addr&0xff; ++ pmlmepriv->gw_ip[1] = (gw_addr&0xff00)>>8; ++ pmlmepriv->gw_ip[2] = (gw_addr&0xff0000)>>16; ++ pmlmepriv->gw_ip[3] = (gw_addr&0xff000000)>>24; ++ _rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, 6); ++ DBG_871X("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr)); ++ DBG_871X("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip)); ++ } ++ else ++ { ++ //DBG_871X("Get Gateway IP/MAC fail!\n"); ++ } ++ ++ return res; ++} ++#endif ++ ++int rtw_suspend_free_assoc_resource(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif ++ DBG_871X("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); ++ ++ rtw_cancel_all_timer(padapter); ++ if(pnetdev){ ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++ #ifdef CONFIG_LAYER2_ROAMING_RESUME ++#ifdef CONFIG_P2P ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++#else ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) ++#endif ++ { ++ DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ rtw_set_roaming(padapter, 1); ++ } ++ #endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) ++ { ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++ } ++ #ifdef CONFIG_AP_MODE ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ rtw_sta_flush(padapter); ++ } ++ #endif ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) ){ ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ } ++ ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++#ifdef CONFIG_AUTOSUSPEND ++ if(is_primary_adapter(padapter) && (!adapter_to_pwrctl(padapter)->bInternalAutoSuspend )) ++#endif ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ DBG_871X("==> "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); ++ return 0; ++} ++extern void rtw_dev_unload(_adapter *padapter); ++int rtw_suspend_common(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ int ret = 0; ++ _func_enter_; ++ LeaveAllPowerSaveMode(padapter); ++ ++ rtw_suspend_free_assoc_resource(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)){ ++ rtw_suspend_free_assoc_resource(padapter->pbuddy_adapter); ++ } ++#endif ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)){ ++ rtw_dev_unload(padapter->pbuddy_adapter); ++ } ++#endif ++ rtw_dev_unload(padapter); ++ ++exit: ++ ++ _func_exit_; ++ return ret; ++} ++ ++int rtw_resume_common(_adapter *padapter) ++{ ++ int ret = 0; ++ struct net_device *pnetdev= padapter->pnetdev; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ ++ _func_enter_; ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ rtw_reset_drv_sw(padapter->pbuddy_adapter); ++ #endif ++ ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) { ++ DBG_871X("%s ==> pm_netdev_open failed \n",__FUNCTION__); ++ ret = -1; ++ return ret; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)){ ++ pnetdev = padapter->pbuddy_adapter->pnetdev; ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ } ++ #endif ++ ++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ ++ #ifdef CONFIG_LAYER2_ROAMING_RESUME ++ rtw_roaming(padapter, NULL); ++ #endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ rtw_ap_restore_network(padapter); ++ } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } else { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } ++ ++ #ifdef CONFIG_CONCURRENT_MODE ++ if(rtw_buddy_adapter_up(padapter)) ++ { ++ mlmepriv = &padapter->pbuddy_adapter->mlmepriv; ++ if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ ++ #ifdef CONFIG_LAYER2_ROAMING_RESUME ++ rtw_roaming(padapter->pbuddy_adapter, NULL); ++ #endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ rtw_ap_restore_network(padapter->pbuddy_adapter); ++ } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } else { ++ DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); ++ } ++ } ++ #endif ++ ++ _func_exit_; ++ return ret; ++} +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_intf.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_intf.c +new file mode 100644 +index 00000000..4d00d304 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_intf.c +@@ -0,0 +1,2001 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_PCI_HCI ++ ++#error "CONFIG_PCI_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifdef CONFIG_80211N_HT ++extern int rtw_ht_enable; ++extern int rtw_cbw40_enable; ++extern int rtw_ampdu_enable;//for enable tx_ampdu ++#endif ++ ++#ifdef CONFIG_PM ++extern int pm_netdev_open(struct net_device *pnetdev); ++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state); ++static int rtw_resume(struct pci_dev *pdev); ++#endif ++ ++ ++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid); ++static void rtw_dev_remove(struct pci_dev *pdev); ++ ++static struct specific_device_id specific_device_id_tbl[] = { ++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {} ++}; ++ ++struct pci_device_id rtw_pci_id_tbl[] = { ++#ifdef CONFIG_RTL8188E ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8179)}, ++#endif ++#ifdef CONFIG_RTL8192C ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8191)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8178)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8177)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8176)}, ++#endif ++#ifdef CONFIG_RTL8192D ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8193)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x002B)}, ++#endif ++ {}, ++}; ++ ++struct pci_drv_priv { ++ struct pci_driver rtw_pci_drv; ++ int drv_registered; ++}; ++ ++ ++static struct pci_drv_priv pci_drvpriv = { ++ .rtw_pci_drv.name = (char*)DRV_NAME, ++ .rtw_pci_drv.probe = rtw_drv_init, ++ .rtw_pci_drv.remove = rtw_dev_remove, ++ .rtw_pci_drv.id_table = rtw_pci_id_tbl, ++#ifdef CONFIG_PM ++ .rtw_pci_drv.suspend = rtw_suspend, ++ .rtw_pci_drv.resume = rtw_resume, ++#else ++ .rtw_pci_drv.suspend = NULL, ++ .rtw_pci_drv.resume = NULL, ++#endif ++}; ++ ++ ++MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl); ++ ++ ++static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { ++ INTEL_VENDOR_ID, ++ ATI_VENDOR_ID, ++ AMD_VENDOR_ID, ++ SIS_VENDOR_ID ++}; ++ ++static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ u8 bresult = _SUCCESS; ++ int error; ++ ++ value |= 0x40; ++ ++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x80, value); ++ ++ if(error != 0) ++ { ++ bresult = _FALSE; ++ DBG_871X("rtw_pci_platform_switch_device_pci_aspm error (%d)\n",error); ++ } ++ ++ return bresult; ++} ++ ++// ++// When we set 0x01 to enable clk request. Set 0x0 to disable clk req. ++// ++static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ u8 buffer, bresult = _SUCCESS; ++ int error; ++ ++ buffer = value; ++ ++ if(!padapter->hw_init_completed) ++ return bresult; ++ ++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, value); ++ ++ if(error != 0) ++ { ++ bresult = _FALSE; ++ DBG_871X("rtw_pci_switch_clk_req error (%d)\n",error); ++ } ++ ++ return bresult; ++} ++ ++#if 0 ++//Description: ++//Disable RTL8192SE ASPM & Disable Pci Bridge ASPM ++void rtw_pci_disable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u32 pcicfg_addrport = 0; ++ u8 num4bytes; ++ u8 linkctrl_reg; ++ u16 pcibridge_linkctrlreg, aspmlevel = 0; ++ ++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ // if it is not intel bus then don't enable ASPM. ++ if ((pcipriv->busnumber == 0xff ++ && pcipriv->devnumber == 0xff ++ && pcipriv->funcnumber == 0xff) ++ || (pcipriv->pcibridge_busnum == 0xff ++ && pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { ++ DBG_871X("%s(): Disable ASPM. Recognize the Bus of PCI(Bridge) as UNKNOWN.\n", __func__); ++ } ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ rtw_pci_switch_clk_req(padapter, 0x0); ++ } ++ ++ { ++ // Suggested by SD1 for promising device will in L0 state after an I/O. ++ u8 tmp_u1b; ++ ++ pci_read_config_byte(pdvobjpriv->ppcidev, 0x80, &tmp_u1b); ++ } ++ ++ // Retrieve original configuration settings. ++ linkctrl_reg = pcipriv->linkctrl_reg; ++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg; ++ ++ // Set corresponding value. ++ aspmlevel |= BIT(0) | BIT(1); ++ linkctrl_reg &= ~aspmlevel; ++ pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg); ++ rtw_udelay_os(50); ++ ++ //When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ if ((pcipriv->busnumber == 0xff && ++ pcipriv->devnumber == 0xff && ++ pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && ++ pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ //Do Nothing!! ++ } ++ else ++ { ++ //4 //Disable Pci Bridge ASPM ++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) | ++ (pcipriv->pcibridge_devnum << 11) | ++ (pcipriv->pcibridge_funcnum << 8) | (1 << 31); ++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4; ++ ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg); ++ ++ DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg); ++ ++ rtw_udelay_os(50); ++ } ++} ++ ++//[ASPM] ++//Description: ++// Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving ++// We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM ++// or the system will show bluescreen. ++void rtw_pci_enable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u16 aspmlevel = 0; ++ u32 pcicfg_addrport = 0; ++ u8 num4bytes; ++ u8 u_pcibridge_aspmsetting = 0; ++ u8 u_device_aspmsetting = 0; ++ ++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ // if it is not intel bus then don't enable ASPM. ++ ++ if ((pcipriv->busnumber == 0xff ++ && pcipriv->devnumber == 0xff ++ && pcipriv->funcnumber == 0xff) ++ || (pcipriv->pcibridge_busnum == 0xff ++ && pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++ //4 Enable Pci Bridge ASPM ++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) ++ | (pcipriv->pcibridge_devnum << 11) ++ | (pcipriv->pcibridge_funcnum << 8) | (1 << 31); ++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4; ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ ++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg | pdvobjpriv->const_hostpci_aspm_setting; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS) ++ u_pcibridge_aspmsetting &= ~BIT(0); ++ ++ NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting); ++ ++ DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), ++ u_pcibridge_aspmsetting); ++ ++ rtw_udelay_os(50); ++ ++ // Get ASPM level (with/without Clock Req) ++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting; ++ u_device_aspmsetting = pcipriv->linkctrl_reg; ++ u_device_aspmsetting |= aspmlevel; ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); //(priv->linkctrl_reg | ASPMLevel)); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ } ++ ++ rtw_udelay_os(50); ++} ++ ++// ++//Description: ++//To get link control field by searching from PCIe capability lists. ++// ++static u8 ++rtw_get_link_control_field(_adapter *padapter, u8 busnum, u8 devnum, ++ u8 funcnum) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct rt_pci_capabilities_header capability_hdr; ++ u8 capability_offset, num4bytes; ++ u32 pcicfg_addrport = 0; ++ u8 linkctrl_reg; ++ u8 status = _FALSE; ++ ++ //If busnum, devnum, funcnum are set to 0xff. ++ if (busnum == 0xff && devnum == 0xff && funcnum == 0xff) { ++ DBG_871X("GetLinkControlField(): Fail to find PCIe Capability\n"); ++ return _FALSE; ++ } ++ ++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31); ++ ++ //2PCIeCap ++ ++ // The device supports capability lists. Find the capabilities. ++ num4bytes = 0x34 / 4; ++ //get capability_offset ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUchar(PCI_CONF_DATA, &capability_offset); ++ ++ // Loop through the capabilities in search of the power management capability. ++ // The list is NULL-terminated, so the last offset will always be zero. ++ ++ while (capability_offset != 0) { ++ // First find the number of 4 Byte. ++ num4bytes = capability_offset / 4; ++ ++ // Read the header of the capability at this offset. If the retrieved capability is not ++ // the power management capability that we are looking for, follow the link to the ++ // next capability and continue looping. ++ ++ //4 get capability_hdr ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUshort(PCI_CONF_DATA, (u16 *) & capability_hdr); ++ ++ // Found the PCI express capability ++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS) ++ { ++ break; ++ } ++ else ++ { ++ // This is some other capability. Keep looking for the PCI express capability. ++ capability_offset = capability_hdr.next; ++ } ++ } ++ ++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS) // ++ { ++ num4bytes = (capability_offset + 0x10) / 4; ++ ++ //4 Read Link Control Register ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUchar(PCI_CONF_DATA, &linkctrl_reg); ++ ++ pcipriv->pcibridge_pciehdr_offset = capability_offset; ++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg; ++ ++ status = _TRUE; ++ } ++ else ++ { ++ // We didn't find a PCIe capability. ++ DBG_871X("GetLinkControlField(): Cannot Find PCIe Capability\n"); ++ } ++ ++ return status; ++} ++ ++// ++//Description: ++//To get PCI bus infomation and return busnum, devnum, and funcnum about ++//the bus(bridge) which the device binds. ++// ++static u8 ++rtw_get_pci_bus_info(_adapter *padapter, ++ u16 vendorid, ++ u16 deviceid, ++ u8 irql, u8 basecode, u8 subclass, u8 filed19val, ++ u8 * busnum, u8 * devnum, u8 * funcnum) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ u8 busnum_idx, devicenum_idx, functionnum_idx; ++ u32 pcicfg_addrport = 0; ++ u32 dev_venid = 0, classcode, field19, headertype; ++ u16 venId, devId; ++ u8 basec, subc, irqline; ++ u16 regoffset; ++ u8 b_singlefunc = _FALSE; ++ u8 b_bridgechk = _FALSE; ++ ++ *busnum = 0xFF; ++ *devnum = 0xFF; ++ *funcnum = 0xFF; ++ ++ //DBG_871X("==============>vendorid:%x,deviceid:%x,irql:%x\n", vendorid,deviceid,irql); ++ if ((basecode == PCI_CLASS_BRIDGE_DEV) && ++ (subclass == PCI_SUBCLASS_BR_PCI_TO_PCI) ++ && (filed19val == U1DONTCARE)) ++ b_bridgechk = _TRUE; ++ ++ // perform a complete pci bus scan operation ++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255 ++ { ++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32 ++ { ++ b_singlefunc = _FALSE; ++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8 ++ { ++ // ++ // We have to skip redundant Bus scan to prevent unexpected system hang ++ // if single function is present in this device. ++ // 2009.02.26. ++ // ++ if (functionnum_idx == 0) { ++ //4 get header type (DWORD #3) ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype); ++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7]. ++ if (headertype == 0) //Single function ++ b_singlefunc = _TRUE; ++ } ++ else ++ {//By pass the following scan process. ++ if (b_singlefunc == _TRUE) ++ break; ++ } ++ ++ // Set access enable control. ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ ++ //4 // Get vendorid/ deviceid ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid); ++ ++ // if data port is full of 1s, no device is present ++ // some broken boards return 0 if a slot is empty: ++ if (dev_venid == 0xFFFFFFFF || dev_venid == 0) ++ continue; //PCI_INVALID_VENDORID ++ ++ // 4 // Get irql ++ regoffset = 0x3C; ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ NdisRawReadPortUchar((PCI_CONF_DATA +(regoffset & 0x3)), &irqline); ++ ++ venId = (u16) (dev_venid >> 0) & 0xFFFF; ++ devId = (u16) (dev_venid >> 16) & 0xFFFF; ++ ++ // Check Vendor ID ++ if (!b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE)) ++ continue; ++ ++ // Check Device ID ++ if (!b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE)) ++ continue; ++ ++ // Check irql ++ if (!b_bridgechk && (irqline != irql) && (irql != U1DONTCARE)) ++ continue; ++ ++ //4 get Class Code ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode); ++ classcode = classcode >> 8; ++ ++ basec = (u8) (classcode >> 16) & 0xFF; ++ subc = (u8) (classcode >> 8) & 0xFF; ++ if (b_bridgechk && (venId != vendorid) && (basec == basecode) && (subc == subclass)) ++ return _TRUE; ++ ++ // Check Vendor ID ++ if (b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE)) ++ continue; ++ ++ // Check Device ID ++ if (b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE)) ++ continue; ++ ++ // Check irql ++ if (b_bridgechk && (irqline != irql) && (irql != U1DONTCARE)) ++ continue; ++ ++ //4 get field 0x19 value (DWORD #6) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19); ++ field19 = (field19 >> 8) & 0xFF; ++ ++ //4 Matching Class Code and filed19. ++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) { ++ *busnum = busnum_idx; ++ *devnum = devicenum_idx; ++ *funcnum = functionnum_idx; ++ ++ DBG_871X("GetPciBusInfo(): Find Device(%X:%X) bus=%d dev=%d, func=%d\n", ++ vendorid, deviceid, busnum_idx, devicenum_idx, functionnum_idx); ++ return _TRUE; ++ } ++ } ++ } ++ } ++ ++ DBG_871X("GetPciBusInfo(): Cannot Find Device(%X:%X:%X)\n", vendorid, deviceid, dev_venid); ++ ++ return _FALSE; ++} ++ ++static u8 ++rtw_get_pci_brideg_info(_adapter *padapter, ++ u8 basecode, ++ u8 subclass, ++ u8 filed19val, u8 * busnum, u8 * devnum, ++ u8 * funcnum, u16 * vendorid, u16 * deviceid) ++{ ++ u8 busnum_idx, devicenum_idx, functionnum_idx; ++ u32 pcicfg_addrport = 0; ++ u32 dev_venid, classcode, field19, headertype; ++ u16 venId, devId; ++ u8 basec, subc, irqline; ++ u16 regoffset; ++ u8 b_singlefunc = _FALSE; ++ ++ *busnum = 0xFF; ++ *devnum = 0xFF; ++ *funcnum = 0xFF; ++ ++ // perform a complete pci bus scan operation ++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255 ++ { ++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32 ++ { ++ b_singlefunc = _FALSE; ++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8 ++ { ++ // ++ // We have to skip redundant Bus scan to prevent unexpected system hang ++ // if single function is present in this device. ++ // 2009.02.26. ++ // ++ if (functionnum_idx == 0) ++ { ++ //4 get header type (DWORD #3) ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , pcicfg_addrport + (3 << 2)); ++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA, &headertype); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype); ++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7]. ++ if (headertype == 0) //Single function ++ b_singlefunc = _TRUE; ++ } ++ else ++ {//By pass the following scan process. ++ if (b_singlefunc == _TRUE) ++ break; ++ } ++ ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ ++ //4 // Get vendorid/ deviceid ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid); ++ ++ //4 Get irql ++ regoffset = 0x3C; ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ NdisRawReadPortUchar((PCI_CONF_DATA + (regoffset & 0x3)), &irqline); ++ ++ venId = (u16) (dev_venid >> 0) & 0xFFFF; ++ devId = (u16) (dev_venid >> 16) & 0xFFFF; ++ ++ //4 get Class Code ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode); ++ classcode = classcode >> 8; ++ ++ basec = (u8) (classcode >> 16) & 0xFF; ++ subc = (u8) (classcode >> 8) & 0xFF; ++ ++ //4 get field 0x19 value (DWORD #6) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19); ++ field19 = (field19 >> 8) & 0xFF; ++ ++ //4 Matching Class Code and filed19. ++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) { ++ *busnum = busnum_idx; ++ *devnum = devicenum_idx; ++ *funcnum = functionnum_idx; ++ *vendorid = venId; ++ *deviceid = devId; ++ ++ DBG_871X("GetPciBridegInfo : Find Device(%X:%X) bus=%d dev=%d, func=%d\n", ++ venId, devId, busnum_idx, devicenum_idx, functionnum_idx); ++ ++ return _TRUE; ++ } ++ } ++ } ++ } ++ ++ DBG_871X("GetPciBridegInfo(): Cannot Find PciBridge for Device\n"); ++ ++ return _FALSE; ++} // end of GetPciBridegInfo ++ ++// ++//Description: ++//To find specific bridge information. ++// ++static void rtw_find_bridge_info(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 pcibridge_busnum = 0xff; ++ u8 pcibridge_devnum = 0xff; ++ u8 pcibridge_funcnum = 0xff; ++ u16 pcibridge_vendorid = 0xff; ++ u16 pcibridge_deviceid = 0xff; ++ u8 tmp = 0; ++ ++ rtw_get_pci_brideg_info(padapter, ++ PCI_CLASS_BRIDGE_DEV, ++ PCI_SUBCLASS_BR_PCI_TO_PCI, ++ pcipriv->busnumber, ++ &pcibridge_busnum, ++ &pcibridge_devnum, &pcibridge_funcnum, ++ &pcibridge_vendorid, &pcibridge_deviceid); ++ ++ // match the array of vendor id and regonize which chipset is used. ++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; ++ ++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { ++ if (pcibridge_vendorid == pcibridge_vendors[tmp]) { ++ pcipriv->pcibridge_vendor = tmp; ++ DBG_871X("Pci Bridge Vendor is found index: %d\n", tmp); ++ break; ++ } ++ } ++ DBG_871X("Pci Bridge Vendor is %x\n", pcibridge_vendors[tmp]); ++ ++ // Update corresponding PCI bus info. ++ pcipriv->pcibridge_busnum = pcibridge_busnum; ++ pcipriv->pcibridge_devnum = pcibridge_devnum; ++ pcipriv->pcibridge_funcnum = pcibridge_funcnum; ++ pcipriv->pcibridge_vendorid = pcibridge_vendorid; ++ pcipriv->pcibridge_deviceid = pcibridge_deviceid; ++ ++} ++ ++static u8 ++rtw_get_amd_l1_patch(_adapter *padapter, u8 busnum, u8 devnum, ++ u8 funcnum) ++{ ++ u8 status = _FALSE; ++ u8 offset_e0; ++ unsigned offset_e4; ++ u32 pcicfg_addrport = 0; ++ ++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31); ++ ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0); ++ NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0); ++ ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0); ++ NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0); ++ ++ if (offset_e0 == 0xA0) ++ { ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4); ++ //DbgPrint("Offset E4 %x\n", offset_e4); ++ if (offset_e4 & BIT(23)) ++ status = _TRUE; ++ } ++ ++ return status; ++} ++#else ++/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ ++void rtw_pci_disable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 linkctrl_reg; ++ u16 pcibridge_linkctrlreg; ++ u16 aspmlevel = 0; ++ ++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM. ++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23. ++ if(pdvobjpriv->const_pci_aspm == 0) ++ return; ++ ++ if(!padapter->hw_init_completed) ++ return; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s(): PCI(Bridge) UNKNOWN.\n", __FUNCTION__)); ++ return; ++ } ++ ++ linkctrl_reg = pcipriv->linkctrl_reg; ++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg; ++ ++ // Set corresponding value. ++ aspmlevel |= BIT(0) | BIT(1); ++ linkctrl_reg &=~aspmlevel; ++ pcibridge_linkctrlreg &=~aspmlevel; ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ rtw_pci_switch_clk_req(padapter, 0x0); ++ } ++ ++ { ++ /*for promising device will in L0 state after an I/O.*/ ++ u8 tmp_u1b; ++ pci_read_config_byte(pdev, 0x80, &tmp_u1b); ++ } ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg); ++ rtw_udelay_os(50); ++ ++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, ++ // we do not execute any action and return. Added by tynli. ++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) ) ++ { ++ // Do Nothing!! ++ } ++ else ++ { ++ /*Disable Pci Bridge ASPM*/ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ //NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg); ++ pci_write_config_byte(bridge_pdev, pcipriv->pcibridge_pciehdr_offset + 0x10, pcibridge_linkctrlreg); ++ ++ DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg); ++ ++ rtw_udelay_os(50); ++ } ++ ++} ++ ++/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for ++power saving We should follow the sequence to enable ++RTL8192SE first then enable Pci Bridge ASPM ++or the system will show bluescreen.*/ ++void rtw_pci_enable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u16 aspmlevel = 0; ++ u8 u_pcibridge_aspmsetting = 0; ++ u8 u_device_aspmsetting = 0; ++ u32 u_device_aspmsupportsetting = 0; ++ ++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM. ++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23. ++ if(pdvobjpriv->const_pci_aspm == 0) ++ return; ++ ++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, ++ // we do not execute any action and return. Added by tynli. ++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) ) ++ { ++ DBG_871X("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++//Get Bridge ASPM Support ++//not to enable bridge aspm if bridge does not support ++//Added by sherry 20100803 ++ if (IS_HARDWARE_TYPE_8192DE(padapter)) ++ { ++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11)|(pcipriv->pcibridge_funcnum << 8)|(1 << 31); ++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x0C)/4; ++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); ++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA,&uDeviceASPMSupportSetting); ++ pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x0C), &u_device_aspmsupportsetting); ++ DBG_871X("rtw_pci_enable_aspm(): Bridge ASPM support %x \n",u_device_aspmsupportsetting); ++ if(((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) ++ { ++ if(pdvobjpriv->const_devicepci_aspm_setting == 3) ++ { ++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n"); ++ return; ++ } ++ else if(pdvobjpriv->const_devicepci_aspm_setting == 2) ++ { ++ if((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) ++ { ++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L1 \n"); ++ return; ++ } ++ } ++ else if(pdvobjpriv->const_devicepci_aspm_setting == 1) ++ { ++ if((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) ++ { ++ DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0s \n"); ++ return; ++ } ++ ++ } ++ } ++ else ++ { ++ DBG_871X("rtw_pci_enable_aspm(): Bridge support L0s and L1 \n"); ++ } ++ } ++ ++ ++ /*Enable Pci Bridge ASPM*/ ++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11) |(pcipriv->pcibridge_funcnum << 8)|(1 << 31); ++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x10)/4; ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, PciCfgAddrPort + (Num4Bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ ++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg; ++ u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS ) ++ u_pcibridge_aspmsetting &= ~BIT(0); // for intel host 42 device 43 ++ ++ //NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting); ++ pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x10), u_pcibridge_aspmsetting); ++ ++ DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), ++ u_pcibridge_aspmsetting); ++ ++ rtw_udelay_os(50); ++ ++ /*Get ASPM level (with/without Clock Req)*/ ++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting; ++ u_device_aspmsetting = pcipriv->linkctrl_reg; ++ u_device_aspmsetting |= aspmlevel; // device 43 ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ } ++ ++ rtw_udelay_os(50); ++} ++ ++static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv) ++{ ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ u8 status = _FALSE; ++ u8 offset_e0; ++ u32 offset_e4; ++ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0); ++ //NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0); ++ pci_write_config_byte(bridge_pdev, 0xE0, 0xA0); ++ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0); ++ //NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0); ++ pci_read_config_byte(bridge_pdev, 0xE0, &offset_e0); ++ ++ if (offset_e0 == 0xA0) { ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4); ++ //NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4); ++ pci_read_config_dword(bridge_pdev, 0xE4, &offset_e4); ++ if (offset_e4 & BIT(23)) ++ status = _TRUE; ++ } ++ ++ return status; ++} ++ ++static void rtw_pci_get_linkcontrol_field(struct dvobj_priv *pdvobjpriv) ++{ ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ u8 capabilityoffset = pcipriv->pcibridge_pciehdr_offset; ++ u8 linkctrl_reg; ++ ++ /*Read Link Control Register*/ ++ pci_read_config_byte(bridge_pdev, capabilityoffset + PCI_EXP_LNKCTL, &linkctrl_reg); ++ ++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg; ++} ++#endif ++ ++static void rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *pdvobjpriv) ++{ ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 tmp; ++ int pos; ++ u8 linkctrl_reg; ++ ++ //Link Control Register ++ pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg); ++ pcipriv->linkctrl_reg = linkctrl_reg; ++ ++ //DBG_871X("Link Control Register = %x\n", pcipriv->linkctrl_reg); ++ ++ pci_read_config_byte(pdev, 0x98, &tmp); ++ tmp |= BIT(4); ++ pci_write_config_byte(pdev, 0x98, tmp); ++ ++ //tmp = 0x17; ++ //pci_write_config_byte(pdev, 0x70f, tmp); ++} ++ ++// ++// Update PCI dependent default settings. ++// ++static void rtw_pci_update_default_setting(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); ++ ++ //reset pPSC->reg_rfps_level & priv->b_support_aspm ++ pwrpriv->reg_rfps_level = 0; ++ pwrpriv->b_support_aspm = 0; ++ ++ // Dynamic Mechanism, ++ //rtw_hal_set_def_var(pAdapter, HAL_DEF_INIT_GAIN, &(pDevice->InitGainState)); ++ ++ // Update PCI ASPM setting ++ pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; ++ switch (pdvobjpriv->const_pci_aspm) { ++ case 0: // No ASPM ++ break; ++ ++ case 1: // ASPM dynamically enabled/disable. ++ pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; ++ break; ++ ++ case 2: // ASPM with Clock Req dynamically enabled/disable. ++ pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ break; ++ ++ case 3: // Always enable ASPM and Clock Req from initialization to halt. ++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); ++ pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ break; ++ ++ case 4: // Always enable ASPM without Clock Req from initialization to halt. ++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; ++ break; ++ } ++ ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; ++ ++ // Update Radio OFF setting ++ switch (pdvobjpriv->const_hwsw_rfoff_d3) { ++ case 1: ++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; ++ break; ++ ++ case 2: ++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; ++ break; ++ ++ case 3: ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; ++ break; ++ } ++ ++ // Update Rx 2R setting ++ //pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); ++ ++ // ++ // Set HW definition to determine if it supports ASPM. ++ // ++ switch (pdvobjpriv->const_support_pciaspm) { ++ case 0: // Not support ASPM. ++ { ++ u8 b_support_aspm = _FALSE; ++ pwrpriv->b_support_aspm = b_support_aspm; ++ } ++ break; ++ ++ case 1: // Support ASPM. ++ { ++ u8 b_support_aspm = _TRUE; ++ u8 b_support_backdoor = _TRUE; ++ ++ pwrpriv->b_support_aspm = b_support_aspm; ++ ++ /*if(pAdapter->MgntInfo.CustomerID == RT_CID_TOSHIBA && ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD && ++ !pcipriv->amd_l1_patch) ++ b_support_backdoor = _FALSE;*/ ++ ++ pwrpriv->b_support_backdoor = b_support_backdoor; ++ } ++ break; ++ ++ case 2: // Set by Chipset. ++ // ASPM value set by chipset. ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { ++ u8 b_support_aspm = _TRUE; ++ pwrpriv->b_support_aspm = b_support_aspm; ++ } ++ break; ++ ++ default: ++ // Do nothing. Set when finding the chipset. ++ break; ++ } ++} ++ ++static void rtw_pci_initialize_adapter_common(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ ++ rtw_pci_update_default_setting(padapter); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { ++ // Always enable ASPM & Clock Req. ++ rtw_pci_enable_aspm(padapter); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM); ++ } ++ ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++#define rtw_pci_interrupt(x,y,z) rtw_pci_interrupt(x,y) ++#endif ++ ++static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs) ++{ ++ struct dvobj_priv *dvobj = (struct dvobj_priv *)priv; ++ _adapter *adapter = dvobj->if1; ++ ++ if (dvobj->irq_enabled == 0) { ++ return IRQ_HANDLED; ++ } ++ ++ if(rtw_hal_interrupt_handler(adapter) == _FAIL) ++ return IRQ_HANDLED; ++ //return IRQ_NONE; ++ ++ return IRQ_HANDLED; ++} ++ ++#ifdef RTK_DMP_PLATFORM ++#define pci_iounmap(x,y) iounmap(y) ++#endif ++ ++int pci_alloc_irq(struct dvobj_priv *dvobj) ++{ ++ int err; ++ struct pci_dev *pdev = dvobj->ppcidev; ++ ++#if defined(IRQF_SHARED) ++ err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj); ++#else ++ err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj); ++#endif ++ if (err) { ++ DBG_871X("Error allocating IRQ %d",pdev->irq); ++ } else { ++ dvobj->irq_alloc = 1; ++ DBG_871X("Request_irq OK, IRQ %d\n",pdev->irq); ++ } ++ ++ return err?_FAIL:_SUCCESS; ++} ++ ++static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev) ++{ ++ int err; ++ u32 status = _FAIL; ++ struct dvobj_priv *dvobj = NULL; ++ struct pci_priv *pcipriv = NULL; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ unsigned long pmem_start, pmem_len, pmem_flags; ++ u8 tmp; ++ ++_func_enter_; ++ ++ if ((dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj))) == NULL) { ++ goto exit; ++ } ++ dvobj->ppcidev = pdev; ++ pcipriv = &(dvobj->pcipriv); ++ pci_set_drvdata(pdev, dvobj); ++ ++ _rtw_mutex_init(&dvobj->hw_init_mutex); ++ _rtw_mutex_init(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_init(&dvobj->setch_mutex); ++ _rtw_mutex_init(&dvobj->setbw_mutex); ++ ++ dvobj->processing_dev_remove = _FALSE; ++ if ( (err = pci_enable_device(pdev)) != 0) { ++ DBG_871X(KERN_ERR "%s : Cannot enable new PCI device\n", pci_name(pdev)); ++ goto free_dvobj; ++ } ++ ++#ifdef CONFIG_64BIT_DMA ++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { ++ DBG_871X("RTL819xCE: Using 64bit DMA\n"); ++ if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) != 0) { ++ DBG_871X(KERN_ERR "Unable to obtain 64bit DMA for consistent allocations\n"); ++ goto disable_picdev; ++ } ++ dvobj->bdma64 = _TRUE; ++ } else ++#endif ++ { ++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { ++ if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { ++ DBG_871X(KERN_ERR "Unable to obtain 32bit DMA for consistent allocations\n"); ++ goto disable_picdev; ++ } ++ } ++ } ++ ++ pci_set_master(pdev); ++ ++ if ((err = pci_request_regions(pdev, DRV_NAME)) != 0) { ++ DBG_871X(KERN_ERR "Can't obtain PCI resources\n"); ++ goto disable_picdev; ++ } ++ //MEM map ++ pmem_start = pci_resource_start(pdev, 2); ++ pmem_len = pci_resource_len(pdev, 2); ++ pmem_flags = pci_resource_flags(pdev, 2); ++ ++#ifdef RTK_DMP_PLATFORM ++ dvobj->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len); ++#else ++ dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, 2, pmem_len); /* shared mem start */ ++#endif ++ if (dvobj->pci_mem_start == 0) { ++ DBG_871X(KERN_ERR "Can't map PCI mem\n"); ++ goto release_regions; ++ } ++ ++ DBG_871X("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", ++ pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start); ++ ++ // Disable Clk Request */ ++ pci_write_config_byte(pdev, 0x81, 0); ++ // leave D3 mode */ ++ pci_write_config_byte(pdev, 0x44, 0); ++ pci_write_config_byte(pdev, 0x04, 0x06); ++ pci_write_config_byte(pdev, 0x04, 0x07); ++ ++#if 1 ++ /*find bus info*/ ++ pcipriv->busnumber = pdev->bus->number; ++ pcipriv->devnumber = PCI_SLOT(pdev->devfn); ++ pcipriv->funcnumber = PCI_FUNC(pdev->devfn); ++ ++ /*find bridge info*/ ++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; ++ if(bridge_pdev){ ++ pcipriv->pcibridge_vendorid = bridge_pdev->vendor; ++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { ++ if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { ++ pcipriv->pcibridge_vendor = tmp; ++ DBG_871X("Pci Bridge Vendor is found index: %d, %x\n", tmp, pcibridge_vendors[tmp]); ++ break; ++ } ++ } ++ } ++ ++ //if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) { ++ if(bridge_pdev){ ++ pcipriv->pcibridge_busnum = bridge_pdev->bus->number; ++ pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn); ++ pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) ++ pcipriv->pcibridge_pciehdr_offset = pci_find_capability(bridge_pdev, PCI_CAP_ID_EXP); ++#else ++ pcipriv->pcibridge_pciehdr_offset = bridge_pdev->pcie_cap; ++#endif ++ ++ rtw_pci_get_linkcontrol_field(dvobj); ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) { ++ pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj); ++ } ++ } ++#else ++ // ++ // Find bridge related info. ++ // ++ rtw_get_pci_bus_info(padapter, ++ pdev->vendor, ++ pdev->device, ++ (u8) pdvobjpriv->irqline, ++ 0x02, 0x80, U1DONTCARE, ++ &pcipriv->busnumber, ++ &pcipriv->devnumber, ++ &pcipriv->funcnumber); ++ ++ rtw_find_bridge_info(padapter); ++ ++ if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) { ++ rtw_get_link_control_field(padapter, ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum); ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) { ++ pcipriv->amd_l1_patch = ++ rtw_get_amd_l1_patch(padapter, ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum); ++ } ++ } ++#endif ++ ++ // ++ // Allow the hardware to look at PCI config information. ++ // ++ rtw_pci_parse_configuration(pdev, dvobj); ++ ++ DBG_871X("pcidev busnumber:devnumber:funcnumber:" ++ "vendor:link_ctl %d:%d:%d:%x:%x\n", ++ pcipriv->busnumber, ++ pcipriv->devnumber, ++ pcipriv->funcnumber, ++ pdev->vendor, ++ pcipriv->linkctrl_reg); ++ ++ DBG_871X("pci_bridge busnumber:devnumber:funcnumber:vendor:" ++ "pcie_cap:link_ctl_reg: %d:%d:%d:%x:%x:%x:%x\n", ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ pcibridge_vendors[pcipriv->pcibridge_vendor], ++ pcipriv->pcibridge_pciehdr_offset, ++ pcipriv->pcibridge_linkctrlreg, ++ pcipriv->amd_l1_patch); ++ ++ status = _SUCCESS; ++ ++iounmap: ++ if (status != _SUCCESS && dvobj->pci_mem_start != 0) { ++ pci_iounmap(pdev, (void *)dvobj->pci_mem_start); ++ dvobj->pci_mem_start = 0; ++ } ++release_regions: ++ if (status != _SUCCESS) ++ pci_release_regions(pdev); ++disable_picdev: ++ if (status != _SUCCESS) ++ pci_disable_device(pdev); ++free_dvobj: ++ if (status != _SUCCESS && dvobj) { ++ pci_set_drvdata(pdev, NULL); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ dvobj = NULL; ++ } ++exit: ++_func_exit_; ++ return dvobj; ++} ++ ++ ++static void pci_dvobj_deinit(struct pci_dev *pdev) ++{ ++ struct dvobj_priv *dvobj = pci_get_drvdata(pdev); ++_func_enter_; ++ ++ pci_set_drvdata(pdev, NULL); ++ if (dvobj) { ++ if (dvobj->irq_alloc) { ++ free_irq(pdev->irq, dvobj); ++ dvobj->irq_alloc = 0; ++ } ++ ++ if (dvobj->pci_mem_start != 0) { ++ pci_iounmap(pdev, (void *)dvobj->pci_mem_start); ++ dvobj->pci_mem_start = 0; ++ } ++ ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ } ++ ++ pci_release_regions(pdev); ++ pci_disable_device(pdev); ++ ++_func_exit_; ++} ++ ++ ++static void decide_chip_type_by_pci_device_id(_adapter *padapter, struct pci_dev *pdev) ++{ ++ u16 venderid, deviceid, irqline; ++ u8 revisionid; ++ struct dvobj_priv *pdvobjpriv=adapter_to_dvobj(padapter); ++ ++ ++ venderid = pdev->vendor; ++ deviceid = pdev->device; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &revisionid); // PCI_REVISION_ID 0x08 ++#else ++ revisionid = pdev->revision; ++#endif ++ pci_read_config_word(pdev, PCI_INTERRUPT_LINE, &irqline); // PCI_INTERRUPT_LINE 0x3c ++ pdvobjpriv->irqline = irqline; ++ ++ ++ // ++ // Decide hardware type here. ++ // ++ if( deviceid == HAL_HW_PCI_8185_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8188_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8198_DEVICE_ID) ++ { ++ DBG_871X("Adapter (8185/8185B) is found- VendorID/DeviceID=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType=HARDWARE_TYPE_RTL8185; ++ } ++ else if (deviceid == HAL_HW_PCI_8190_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0045_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0046_DEVICE_ID || ++ deviceid == HAL_HW_PCI_DLINK_DEVICE_ID) ++ { ++ DBG_871X("Adapter(8190 PCI) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8190P; ++ } ++ else if (deviceid == HAL_HW_PCI_8192_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0044_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0047_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8192SE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8174_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8173_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8172_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8171_DEVICE_ID) ++ { ++ // 8192e and and 8192se may have the same device ID 8192. However, their Revision ++ // ID is different ++ // Added for 92DE. We deferentiate it from SVID,SDID. ++ if( pdev->subsystem_vendor == 0x10EC && pdev->subsystem_device == 0xE020){ ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++ DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid); ++ }else{ ++ switch (revisionid) { ++ case HAL_HW_PCI_REVISION_ID_8192PCIE: ++ DBG_871X("Adapter(8192 PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192E; ++ break; ++ case HAL_HW_PCI_REVISION_ID_8192SE: ++ DBG_871X("Adapter(8192SE) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE; ++ break; ++ default: ++ DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE; ++ break; ++ } ++ } ++ } ++ else if(deviceid==HAL_HW_PCI_8723E_DEVICE_ID ) ++ {//RTL8723E may have the same device ID with RTL8192CET ++ padapter->HardwareType = HARDWARE_TYPE_RTL8723AE; ++ DBG_871X("Adapter(8723 PCI-E) is found - VendorID/DeviceID=%x/%x\n", venderid, deviceid); ++ } ++ else if (deviceid == HAL_HW_PCI_8192CET_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8192CE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8191CE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8188CE_DEVICE_ID) ++ { ++ DBG_871X("Adapter(8192C PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE; ++ } ++ else if (deviceid == HAL_HW_PCI_8192DE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_002B_DEVICE_ID ){ ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++ DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid); ++ } ++ else if (deviceid == HAL_HW_PCI_8188EE_DEVICE_ID){ ++ padapter->HardwareType = HARDWARE_TYPE_RTL8188EE; ++ padapter->chip_type = RTL8188E; ++ DBG_871X("Adapter(8188EE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid); ++ } ++ ++ else ++ { ++ DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ //padapter->HardwareType = HAL_DEFAULT_HARDWARE_TYPE; ++ } ++ ++ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ ++ //TODO: ++#ifdef CONFIG_RTL8192C ++ padapter->chip_type = RTL8188C_8192C; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE; ++#endif ++#ifdef CONFIG_RTL8192D ++ pdvobjpriv->InterfaceNumber = revisionid; ++ ++ padapter->chip_type = RTL8192D; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++#endif ++ ++} ++ ++static void pci_intf_start(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_start\n")); ++ DBG_871X("+pci_intf_start\n"); ++ ++ //Enable hw interrupt ++ rtw_hal_enable_interrupt(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_start\n")); ++ DBG_871X("-pci_intf_start\n"); ++} ++ ++static void pci_intf_stop(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_stop\n")); ++ ++ //Disable hw interrupt ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //device still exists, so driver can do i/o operation ++ rtw_hal_disable_interrupt(padapter); ++ tasklet_disable(&(padapter->recvpriv.recv_tasklet)); ++ tasklet_disable(&(padapter->recvpriv.irq_prepare_beacon_tasklet)); ++ tasklet_disable(&(padapter->xmitpriv.xmit_tasklet)); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ /* This function only be called at driver removing. disable buddy_adapter too ++ don't disable interrupt of buddy_adapter because it is same as primary. ++ */ ++ if (padapter->pbuddy_adapter){ ++ tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.recv_tasklet)); ++ tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.irq_prepare_beacon_tasklet)); ++ tasklet_disable(&(padapter->pbuddy_adapter->xmitpriv.xmit_tasklet)); ++ } ++#endif ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("pci_intf_stop: SurpriseRemoved==_FALSE\n")); ++ } ++ else ++ { ++ // Clear irq_enabled to prevent handle interrupt function. ++ adapter_to_dvobj(padapter)->irq_enabled = 0; ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_stop\n")); ++ ++} ++ ++ ++void rtw_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n")); ++ ++ if(padapter->bup == _TRUE) ++ { ++ DBG_871X("+rtw_dev_unload\n"); ++ ++ padapter->bDriverStopped = _TRUE; ++ #ifdef CONFIG_XMIT_ACK ++ if (padapter->xmitpriv.ack_tx) ++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); ++ #endif ++ ++ //s3. ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s4. ++ rtw_stop_drv_threads(padapter); ++ ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ DBG_871X("r871x_dev_unload()->rtl871x_hal_deinit()\n"); ++ rtw_hal_deinit(padapter); ++ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ padapter->bup = _FALSE; ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" )); ++ } ++ ++ DBG_871X("-rtw_dev_unload\n"); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n")); ++ ++} ++ ++static void disable_ht_for_spec_devid(const struct pci_device_id *pdid) ++{ ++#ifdef CONFIG_80211N_HT ++ u16 vid, pid; ++ u32 flags; ++ int i; ++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id); ++ ++ for(i=0; ivendor==vid) && (pdid->device==pid) && (flags&SPEC_DEV_ID_DISABLE_HT)) ++ { ++ rtw_ht_enable = 0; ++ rtw_cbw40_enable = 0; ++ rtw_ampdu_enable = 0; ++ } ++ ++ } ++#endif ++} ++ ++#ifdef CONFIG_PM ++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ _func_enter_; ++ ++ ++ _func_exit_; ++ return 0; ++} ++ ++static int rtw_resume(struct pci_dev *pdev) ++{ ++ _func_enter_; ++ ++ ++ _func_exit_; ++ ++ return 0; ++} ++#endif ++ ++_adapter *rtw_pci_if1_init(struct dvobj_priv * dvobj, struct pci_dev *pdev, const struct pci_device_id *pdid) ++{ ++ _adapter *padapter = NULL; ++ struct net_device *pnetdev = NULL; ++ int status = _FAIL; ++ ++ if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) { ++ goto exit; ++ } ++ padapter->dvobj = dvobj; ++ dvobj->if1 = padapter; ++ ++ padapter->bDriverStopped=_TRUE; ++ ++ dvobj->padapters[dvobj->iface_nums++] = padapter; ++ padapter->iface_id = IFACE_ID0; ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) ++ //set adapter_type/iface type for primary padapter ++ padapter->isprimary = _TRUE; ++ padapter->adapter_type = PRIMARY_ADAPTER; ++ #ifndef CONFIG_HWPORT_SWAP ++ padapter->iface_type = IFACE_PORT0; ++ #else ++ padapter->iface_type = IFACE_PORT1; ++ #endif ++#endif ++ ++ #ifndef RTW_DVOBJ_CHIP_HW_TYPE ++ //step 1-1., decide the chip_type via vid/pid ++ padapter->interface_type = RTW_PCIE; ++ decide_chip_type_by_pci_device_id(padapter, pdev); ++ #endif ++ ++ if((pnetdev = rtw_init_netdev(padapter)) == NULL) { ++ goto free_adapter; ++ } ++ ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj)); ++ #endif ++ if (dvobj->bdma64) ++ pnetdev->features |= NETIF_F_HIGHDMA; ++ pnetdev->irq = pdev->irq; ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)) != 0) { ++ goto free_adapter; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ ++ //step 2. hook HalFunc, allocate HalData ++ hal_set_hal_ops(padapter); ++ ++ ++ //step 3. ++ padapter->intf_start=&pci_intf_start; ++ padapter->intf_stop=&pci_intf_stop; ++ ++ ++ //.2 ++ rtw_init_io_priv(padapter, pci_set_intf_ops); ++ ++ //.3 ++ rtw_hal_read_chip_version(padapter); ++ ++ //.4 ++ rtw_hal_chip_configure(padapter); ++ ++ ++ //step 4. read efuse/eeprom data and get mac_addr ++ rtw_hal_read_chip_info(padapter); ++ ++ //step 5. ++ if(rtw_init_drv_sw(padapter) ==_FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto free_hal_data; ++ } ++ ++ if(rtw_hal_inirp_init(padapter) ==_FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize PCI desc ring Failed!\n")); ++ goto free_hal_data; ++ } ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr); ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ //step 6. Init pci related configuration ++ rtw_pci_initialize_adapter_common(padapter); ++ ++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n" ++ ,padapter->bDriverStopped ++ ,padapter->bSurpriseRemoved ++ ,padapter->bup ++ ,padapter->hw_init_completed ++ ); ++ ++ status = _SUCCESS; ++ ++free_hal_data: ++ if(status != _SUCCESS && padapter->HalData) ++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData))); ++ ++free_wdev: ++ if(status != _SUCCESS) { ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++ rtw_wdev_free(padapter->rtw_wdev); ++ #endif ++ } ++ ++free_adapter: ++ if (status != _SUCCESS) { ++ if (pnetdev) ++ rtw_free_netdev(pnetdev); ++ else if (padapter) ++ rtw_vmfree((u8*)padapter, sizeof(*padapter)); ++ padapter = NULL; ++ } ++exit: ++ return padapter; ++} ++ ++static void rtw_pci_if1_deinit(_adapter *if1) ++{ ++ struct net_device *pnetdev = if1->pnetdev; ++ struct mlme_priv *pmlmepriv= &if1->mlmepriv; ++ ++ // padapter->intf_stop(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ rtw_disassoc_cmd(if1, 0, _FALSE); ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(if1); ++ #ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(if1); ++ #endif ++#endif ++ ++ if (if1->DriverState != DRIVER_DISAPPEAR) { ++ if(pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++ } ++ ++ rtw_cancel_all_timer(if1); ++#ifdef CONFIG_WOWLAN ++ adapter_to_pwrctl(if1)->wowlan_mode=_FALSE; ++#endif //CONFIG_WOWLAN ++ rtw_dev_unload(if1); ++ ++ DBG_871X("%s, hw_init_completed=%d\n", __func__, if1->hw_init_completed); ++ ++ //s6. ++ rtw_handle_dualmac(if1, 0); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(if1->rtw_wdev) ++ { ++ rtw_wdev_unregister(if1->rtw_wdev); ++ rtw_wdev_free(if1->rtw_wdev); ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ rtw_hal_inirp_deinit(if1); ++ rtw_free_drv_sw(if1); ++ ++ if(pnetdev) ++ rtw_free_netdev(pnetdev); ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link down\n"); ++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); ++#endif ++} ++ ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++*/ ++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid) ++{ ++ int i, err = -ENODEV; ++ ++ int status; ++ _adapter *if1 = NULL, *if2 = NULL; ++ struct dvobj_priv *dvobj; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); ++ //DBG_871X("+rtw_drv_init\n"); ++ ++ //step 0. ++ disable_ht_for_spec_devid(pdid); ++ ++ /* Initialize dvobj_priv */ ++ if ((dvobj = pci_dvobj_init(pdev)) == NULL) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); ++ goto exit; ++ } ++ ++ /* Initialize if1 */ ++ if ((if1 = rtw_pci_if1_init(dvobj, pdev, pdid)) == NULL) { ++ DBG_871X("rtw_pci_if1_init Failed!\n"); ++ goto free_dvobj; ++ } ++ ++ /* Initialize if2 */ ++#ifdef CONFIG_CONCURRENT_MODE ++ if((if2 = rtw_drv_if2_init(if1, pci_set_intf_ops)) == NULL) { ++ goto free_if1; ++ } ++#endif ++ ++ //dev_alloc_name && register_netdev ++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) { ++ goto free_if2; ++ } ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(if1); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(if1->pnetdev); ++#endif ++ ++ /* alloc irq */ ++ if (pci_alloc_irq(dvobj) != _SUCCESS) ++ goto free_if2; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ //DBG_871X("-871x_drv - drv_init, success!\n"); ++ ++ status = _SUCCESS; ++ ++free_if2: ++ if(status != _SUCCESS && if2) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(if2); ++ rtw_drv_if2_free(if2); ++ #endif ++ } ++free_if1: ++ if (status != _SUCCESS && if1) { ++ rtw_pci_if1_deinit(if1); ++ } ++free_dvobj: ++ if (status != _SUCCESS) ++ pci_dvobj_deinit(pdev); ++exit: ++ return status == _SUCCESS?0:-ENODEV; ++} ++ ++extern void rtw_unregister_netdevs(struct dvobj_priv *dvobj); ++/* ++ * dev_remove() - our device is being removed ++*/ ++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both ++static void rtw_dev_remove(struct pci_dev *pdev) ++{ ++ struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev); ++ _adapter *padapter = pdvobjpriv->if1; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++_func_exit_; ++ ++ DBG_871X("+rtw_dev_remove\n"); ++ ++ pdvobjpriv->processing_dev_remove = _TRUE; ++ rtw_unregister_netdevs(pdvobjpriv); ++ ++ if (unlikely(!padapter)) { ++ return; ++ } ++ ++ #if 0 ++#ifdef RTK_DMP_PLATFORM ++ padapter->bSurpriseRemoved = _FALSE; // always trate as device exists ++ // this will let the driver to disable it's interrupt ++#else ++ if(pci_drvpriv.drv_registered == _TRUE) ++ { ++ //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ /*else ++ { ++ //DBG_871X("r871xu_dev_remove():module removed\n"); ++ padapter->hw_init_completed = _FALSE; ++ }*/ ++#endif ++ #endif ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(dvobj_to_pwrctl(pdvobjpriv)); ++#endif ++ ++ rtw_pm_set_ips(padapter, IPS_NONE); ++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); ++ ++ LeaveAllPowerSaveMode(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(pdvobjpriv->if2); ++#endif ++ ++ rtw_pci_if1_deinit(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_free(pdvobjpriv->if2); ++#endif ++ ++ pci_dvobj_deinit(pdev); ++ ++ DBG_871X("-r871xu_dev_remove, done\n"); ++ ++_func_exit_; ++ return; ++} ++ ++ ++static int __init rtw_drv_entry(void) ++{ ++ int ret = 0; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n")); ++ DBG_871X("rtw driver version=%s\n", DRIVERVERSION); ++ DBG_871X("Build at: %s %s\n", __DATE__, __TIME__); ++ pci_drvpriv.drv_registered = _TRUE; ++ ++ rtw_suspend_lock_init(); ++ ++ ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv); ++ if (ret) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, (": No device found\n")); ++ } ++ ++ return ret; ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n")); ++ DBG_871X("+rtw_drv_halt\n"); ++ ++ pci_drvpriv.drv_registered = _FALSE; ++ ++ pci_unregister_driver(&pci_drvpriv.rtw_pci_drv); ++ ++ rtw_suspend_lock_uninit(); ++ ++ DBG_871X("-rtw_drv_halt\n"); ++ ++ rtw_mstat_dump(); ++} ++ ++ ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_ops_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_ops_linux.c +new file mode 100644 +index 00000000..12c6c683 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/pci_ops_linux.c +@@ -0,0 +1,24 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#define _PCI_OPS_LINUX_C_ ++ ++#include ++ ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/recv_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/recv_linux.c +new file mode 100644 +index 00000000..bb6de8a9 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/recv_linux.c +@@ -0,0 +1,512 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RECV_OSDEP_C_ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++//init os related resource in struct recv_priv ++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) ++{ ++ int res=_SUCCESS; ++ ++ return res; ++} ++ ++//alloc os related resource in union recv_frame ++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) ++{ ++ int res=_SUCCESS; ++ ++ precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; ++ ++ return res; ++ ++} ++ ++//free os related resource in union recv_frame ++void rtw_os_recv_resource_free(struct recv_priv *precvpriv) ++{ ++ sint i; ++ union recv_frame *precvframe; ++ precvframe = (union recv_frame*) precvpriv->precv_frame_buf; ++ ++ for(i=0; i < NR_RECVFRAME; i++) ++ { ++ if(precvframe->u.hdr.pkt) ++ { ++ rtw_skb_free(precvframe->u.hdr.pkt);//free skb by driver ++ precvframe->u.hdr.pkt = NULL; ++ } ++ precvframe++; ++ } ++ ++} ++ ++ ++//alloc os related resource in struct recv_buf ++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ int res=_SUCCESS; ++ ++#ifdef CONFIG_USB_HCI ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ precvbuf->irp_pending = _FALSE; ++ precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL); ++ if(precvbuf->purb == NULL){ ++ res = _FAIL; ++ } ++ ++ precvbuf->pskb = NULL; ++ ++ precvbuf->reuse = _FALSE; ++ ++ precvbuf->pallocated_buf = precvbuf->pbuf = NULL; ++ ++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL; ++ ++ precvbuf->transfer_len = 0; ++ ++ precvbuf->len = 0; ++ ++ #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr); ++ precvbuf->pbuf = precvbuf->pallocated_buf; ++ if(precvbuf->pallocated_buf == NULL) ++ return _FAIL; ++ #endif //CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++#endif //CONFIG_USB_HCI ++ ++ return res; ++} ++ ++//free os related resource in struct recv_buf ++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ int ret = _SUCCESS; ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr); ++ precvbuf->pallocated_buf = NULL; ++ precvbuf->dma_transfer_addr = 0; ++ ++#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ if(precvbuf->purb) ++ { ++ //usb_kill_urb(precvbuf->purb); ++ usb_free_urb(precvbuf->purb); ++ } ++ ++#endif //CONFIG_USB_HCI ++ ++ ++ if(precvbuf->pskb) ++ rtw_skb_free(precvbuf->pskb); ++ ++ ++ return ret; ++ ++} ++ ++void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup) ++{ ++#ifdef CONFIG_IOCTL_CFG80211 ++ enum nl80211_key_type key_type; ++#endif ++ union iwreq_data wrqu; ++ struct iw_michaelmicfailure ev; ++ struct mlme_priv* pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ u32 cur_time = 0; ++ ++ if( psecuritypriv->last_mic_err_time == 0 ) ++ { ++ psecuritypriv->last_mic_err_time = rtw_get_current_time(); ++ } ++ else ++ { ++ cur_time = rtw_get_current_time(); ++ ++ if( cur_time - psecuritypriv->last_mic_err_time < 60*HZ ) ++ { ++ psecuritypriv->btkip_countermeasure = _TRUE; ++ psecuritypriv->last_mic_err_time = 0; ++ psecuritypriv->btkip_countermeasure_time = cur_time; ++ } ++ else ++ { ++ psecuritypriv->last_mic_err_time = rtw_get_current_time(); ++ } ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( bgroup ) ++ { ++ key_type |= NL80211_KEYTYPE_GROUP; ++ } ++ else ++ { ++ key_type |= NL80211_KEYTYPE_PAIRWISE; ++ } ++ ++ cfg80211_michael_mic_failure(padapter->pnetdev, (u8 *)&pmlmepriv->assoc_bssid[ 0 ], key_type, -1, ++ NULL, GFP_ATOMIC); ++#endif ++ ++ _rtw_memset( &ev, 0x00, sizeof( ev ) ); ++ if ( bgroup ) ++ { ++ ev.flags |= IW_MICFAILURE_GROUP; ++ } ++ else ++ { ++ ev.flags |= IW_MICFAILURE_PAIRWISE; ++ } ++ ++ ev.src_addr.sa_family = ARPHRD_ETHER; ++ _rtw_memcpy( ev.src_addr.sa_data, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ ++ _rtw_memset( &wrqu, 0x00, sizeof( wrqu ) ); ++ wrqu.data.length = sizeof( ev ); ++ ++#ifndef CONFIG_IOCTL_CFG80211 ++ wireless_send_event( padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char*) &ev ); ++#endif ++} ++ ++void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_HOSTAPD_MLME ++ _pkt *skb; ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; ++ ++ RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("+rtw_hostapd_mlme_rx\n")); ++ ++ skb = precv_frame->u.hdr.pkt; ++ ++ if (skb == NULL) ++ return; ++ ++ skb->data = precv_frame->u.hdr.rx_data; ++ skb->tail = precv_frame->u.hdr.rx_tail; ++ skb->len = precv_frame->u.hdr.len; ++ ++ //pskb_copy = rtw_skb_copy(skb); ++// if(skb == NULL) goto _exit; ++ ++ skb->dev = pmgnt_netdev; ++ skb->ip_summed = CHECKSUM_NONE; ++ skb->pkt_type = PACKET_OTHERHOST; ++ //skb->protocol = __constant_htons(0x0019); /*ETH_P_80211_RAW*/ ++ skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/ ++ ++ //DBG_871X("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); ++ ++ //skb->mac.raw = skb->data; ++ skb_reset_mac_header(skb); ++ ++ //skb_pull(skb, 24); ++ _rtw_memset(skb->cb, 0, sizeof(skb->cb)); ++ ++ rtw_netif_rx(pmgnt_netdev, skb); ++ ++ precv_frame->u.hdr.pkt = NULL; // set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() ++#endif ++} ++ ++int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct recv_priv *precvpriv; ++ _queue *pfree_recv_queue; ++ _pkt *skb; ++ struct mlme_priv*pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ void *br_port = NULL; ++#endif ++ ++_func_enter_; ++ ++ precvpriv = &(padapter->recvpriv); ++ pfree_recv_queue = &(precvpriv->free_recv_queue); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS) ++ { ++ goto _recv_indicatepkt_drop; ++ } ++#endif ++ ++#ifdef CONFIG_WAPI_SUPPORT ++ if (rtw_wapi_check_for_drop(padapter,precv_frame)) ++ { ++ WAPI_TRACE(WAPI_ERR, "%s(): Rx Reorder Drop case!!\n", __FUNCTION__); ++ goto _recv_indicatepkt_drop; ++ } ++#endif ++ ++ skb = precv_frame->u.hdr.pkt; ++ if(skb == NULL) ++ { ++ RT_TRACE(_module_recv_osdep_c_,_drv_err_,("rtw_recv_indicatepkt():skb==NULL something wrong!!!!\n")); ++ goto _recv_indicatepkt_drop; ++ } ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():skb != NULL !!!\n")); ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():precv_frame->u.hdr.rx_head=%p precv_frame->hdr.rx_data=%p\n", precv_frame->u.hdr.rx_head, precv_frame->u.hdr.rx_data)); ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("precv_frame->hdr.rx_tail=%p precv_frame->u.hdr.rx_end=%p precv_frame->hdr.len=%d \n", precv_frame->u.hdr.rx_tail, precv_frame->u.hdr.rx_end, precv_frame->u.hdr.len)); ++ ++ skb->data = precv_frame->u.hdr.rx_data; ++ ++ skb_set_tail_pointer(skb, precv_frame->u.hdr.len); ++ ++ skb->len = precv_frame->u.hdr.len; ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb->tail, skb->end, skb->len)); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _pkt *pskb2=NULL; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ int bmcast = IS_MCAST(pattrib->dst); ++ ++ //DBG_871X("bmcast=%d\n", bmcast); ++ ++ if(_rtw_memcmp(pattrib->dst, myid(&padapter->eeprompriv), ETH_ALEN)==_FALSE) ++ { ++ //DBG_871X("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); ++ ++ if(bmcast) ++ { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ pskb2 = rtw_skb_clone(skb); ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ } ++ ++ if(psta) ++ { ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ ++ //DBG_871X("directly forwarding to the rtw_xmit_entry\n"); ++ ++ //skb->ip_summed = CHECKSUM_NONE; ++ skb->dev = pnetdev; ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ skb_set_queue_mapping(skb, rtw_recv_select_queue(skb)); ++#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35) ++ ++ _rtw_xmit_entry(skb, pnetdev); ++ ++ if(bmcast) ++ skb = pskb2; ++ else ++ goto _recv_indicatepkt_end; ++ } ++ ++ ++ } ++ else// to APself ++ { ++ //DBG_871X("to APSelf\n"); ++ } ++ } ++ ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); ++ if (nat25_handle_frame(padapter, skb) == -1) { ++ //priv->ext_stats.rx_data_drops++; ++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); ++ //return FAIL; ++#if 1 ++ // bypass this frame to upper layer!! ++#else ++ goto _recv_indicatepkt_drop; ++#endif ++ } ++ } ++ ++#endif // CONFIG_BR_EXT ++ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ //DBG_871X("CHECKSUM_UNNECESSARY \n"); ++ } else { ++ skb->ip_summed = CHECKSUM_NONE; ++ //DBG_871X("CHECKSUM_NONE(%d, %d) \n", pattrib->tcpchk_valid, pattrib->tcp_chkrpt); ++ } ++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ ++ ++ skb->ip_summed = CHECKSUM_NONE; ++ ++#endif ++ ++ skb->dev = padapter->pnetdev; ++ skb->protocol = eth_type_trans(skb, padapter->pnetdev); ++ ++ #ifdef DBG_TRX_STA_PKTS ++ { ++ ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ int bmcast = IS_MCAST(pattrib->dst); ++ ++ if(bmcast) ++ { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ } ++ if(psta) ++ { ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ psta->rx_bk_cnt++; ++ break; ++ case 4: ++ case 5: ++ psta->rx_vi_cnt++; ++ break; ++ case 6: ++ case 7: ++ psta->rx_vo_cnt++; ++ break; ++ case 0: ++ case 3: ++ default: ++ psta->rx_be_cnt++; ++ break; ++ } ++ } ++ } ++ #endif ++ ++ rtw_netif_rx(padapter->pnetdev, skb); ++ ++_recv_indicatepkt_end: ++ ++ precv_frame->u.hdr.pkt = NULL; // pointers to NULL before rtw_free_recvframe() ++ ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n rtw_recv_indicatepkt :after rtw_netif_rx!!!!\n")); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++_recv_indicatepkt_drop: ++ ++ //enqueue back to free_recv_queue ++ if(precv_frame) ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ ++ return _FAIL; ++ ++_func_exit_; ++ ++} ++ ++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++#ifdef CONFIG_USB_HCI ++ ++ precvbuf->ref_cnt--; ++ ++ //free skb in recv_buf ++ rtw_skb_free(precvbuf->pskb); ++ ++ precvbuf->pskb = NULL; ++ precvbuf->reuse = _FALSE; ++ ++ if(precvbuf->irp_pending == _FALSE) ++ { ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ ++ ++#endif ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ precvbuf->pskb = NULL; ++#endif ++ ++} ++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext); ++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext) ++{ ++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext; ++ rtw_reordering_ctrl_timeout_handler(preorder_ctrl); ++} ++ ++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) ++{ ++ _adapter *padapter = preorder_ctrl->padapter; ++ ++ _init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter->pnetdev, _rtw_reordering_ctrl_timeout_handler, preorder_ctrl); ++ ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/rtw_android.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/rtw_android.c +new file mode 100644 +index 00000000..201aead2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/rtw_android.c +@@ -0,0 +1,844 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_GPIO_WAKEUP ++#include ++#endif ++ ++#include ++ ++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) ++#include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++#include ++#else ++#include ++#endif ++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ ++ ++#ifdef CONFIG_GPIO_WAKEUP ++#include ++#include ++#endif ++ ++const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { ++ "START", ++ "STOP", ++ "SCAN-ACTIVE", ++ "SCAN-PASSIVE", ++ "RSSI", ++ "LINKSPEED", ++ "RXFILTER-START", ++ "RXFILTER-STOP", ++ "RXFILTER-ADD", ++ "RXFILTER-REMOVE", ++ "BTCOEXSCAN-START", ++ "BTCOEXSCAN-STOP", ++ "BTCOEXMODE", ++ "SETSUSPENDOPT", ++ "P2P_DEV_ADDR", ++ "SETFWPATH", ++ "SETBAND", ++ "GETBAND", ++ "COUNTRY", ++ "P2P_SET_NOA", ++ "P2P_GET_NOA", ++ "P2P_SET_PS", ++ "SET_AP_WPS_P2P_IE", ++#ifdef PNO_SUPPORT ++ "PNOSSIDCLR", ++ "PNOSETUP ", ++ "PNOFORCE", ++ "PNODEBUG", ++#endif ++ ++ "MACADDR", ++ ++ "BLOCK", ++ "WFD-ENABLE", ++ "WFD-DISABLE", ++ "WFD-SET-TCPPORT", ++ "WFD-SET-MAXTPUT", ++ "WFD-SET-DEVTYPE", ++}; ++ ++#ifdef PNO_SUPPORT ++#define PNO_TLV_PREFIX 'S' ++#define PNO_TLV_VERSION '1' ++#define PNO_TLV_SUBVERSION '2' ++#define PNO_TLV_RESERVED '0' ++#define PNO_TLV_TYPE_SSID_IE 'S' ++#define PNO_TLV_TYPE_TIME 'T' ++#define PNO_TLV_FREQ_REPEAT 'R' ++#define PNO_TLV_FREQ_EXPO_MAX 'M' ++ ++typedef struct cmd_tlv { ++ char prefix; ++ char version; ++ char subver; ++ char reserved; ++} cmd_tlv_t; ++#endif /* PNO_SUPPORT */ ++ ++typedef struct android_wifi_priv_cmd { ++ ++#ifdef CONFIG_COMPAT ++ compat_uptr_t buf; ++#else ++ char *buf; ++#endif ++ ++ int used_len; ++ int total_len; ++} android_wifi_priv_cmd; ++ ++/** ++ * Local (static) functions and variables ++ */ ++ ++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first ++ * time (only) in dhd_open, subsequential wifi on will be handled by ++ * wl_android_wifi_on ++ */ ++static int g_wifi_on = _TRUE; ++ ++unsigned int oob_irq; ++ ++#ifdef PNO_SUPPORT ++static int wl_android_set_pno_setup(struct net_device *dev, char *command, int total_len) ++{ ++ wlc_ssid_t ssids_local[MAX_PFN_LIST_COUNT]; ++ int res = -1; ++ int nssid = 0; ++ cmd_tlv_t *cmd_tlv_temp; ++ char *str_ptr; ++ int tlv_size_left; ++ int pno_time = 0; ++ int pno_repeat = 0; ++ int pno_freq_expo_max = 0; ++ ++#ifdef PNO_SET_DEBUG ++ int i; ++ char pno_in_example[] = { ++ 'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ', ++ 'S', '1', '2', '0', ++ 'S', ++ 0x05, ++ 'd', 'l', 'i', 'n', 'k', ++ 'S', ++ 0x04, ++ 'G', 'O', 'O', 'G', ++ 'T', ++ '0', 'B', ++ 'R', ++ '2', ++ 'M', ++ '2', ++ 0x00 ++ }; ++#endif /* PNO_SET_DEBUG */ ++ ++ DHD_INFO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len)); ++ ++ if (total_len < (strlen(CMD_PNOSETUP_SET) + sizeof(cmd_tlv_t))) { ++ DBG_871X("%s argument=%d less min size\n", __FUNCTION__, total_len); ++ goto exit_proc; ++ } ++ ++#ifdef PNO_SET_DEBUG ++ memcpy(command, pno_in_example, sizeof(pno_in_example)); ++ for (i = 0; i < sizeof(pno_in_example); i++) ++ printf("%02X ", command[i]); ++ printf("\n"); ++ total_len = sizeof(pno_in_example); ++#endif ++ ++ str_ptr = command + strlen(CMD_PNOSETUP_SET); ++ tlv_size_left = total_len - strlen(CMD_PNOSETUP_SET); ++ ++ cmd_tlv_temp = (cmd_tlv_t *)str_ptr; ++ memset(ssids_local, 0, sizeof(ssids_local)); ++ ++ if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) && ++ (cmd_tlv_temp->version == PNO_TLV_VERSION) && ++ (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) { ++ ++ str_ptr += sizeof(cmd_tlv_t); ++ tlv_size_left -= sizeof(cmd_tlv_t); ++ ++ if ((nssid = wl_iw_parse_ssid_list_tlv(&str_ptr, ssids_local, ++ MAX_PFN_LIST_COUNT, &tlv_size_left)) <= 0) { ++ DBG_871X("SSID is not presented or corrupted ret=%d\n", nssid); ++ goto exit_proc; ++ } else { ++ if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) { ++ DBG_871X("%s scan duration corrupted field size %d\n", ++ __FUNCTION__, tlv_size_left); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_time = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s: pno_time=%d\n", __FUNCTION__, pno_time)); ++ ++ if (str_ptr[0] != 0) { ++ if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) { ++ DBG_871X("%s pno repeat : corrupted field\n", ++ __FUNCTION__); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat)); ++ if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) { ++ DBG_871X("%s FREQ_EXPO_MAX corrupted field size\n", ++ __FUNCTION__); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s: pno_freq_expo_max=%d\n", ++ __FUNCTION__, pno_freq_expo_max)); ++ } ++ } ++ } else { ++ DBG_871X("%s get wrong TLV command\n", __FUNCTION__); ++ goto exit_proc; ++ } ++ ++ res = dhd_dev_pno_set(dev, ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max); ++ ++exit_proc: ++ return res; ++} ++#endif /* PNO_SUPPORT */ ++ ++int rtw_android_cmdstr_to_num(char *cmdstr) ++{ ++ int cmd_num; ++ for(cmd_num=0 ; cmd_nummlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ int bytes_written = 0; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d", ++ pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); ++ } ++ ++ return bytes_written; ++} ++ ++int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ int bytes_written = 0; ++ u16 link_speed = 0; ++ ++ link_speed = rtw_get_cur_max_rate(padapter)/10; ++ bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed); ++ ++ return bytes_written; ++} ++ ++int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ int bytes_written = 0; ++ ++ bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr)); ++ return bytes_written; ++} ++ ++int rtw_android_set_country(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1; ++ int ret = _FAIL; ++ ++ ret = rtw_set_country(adapter, country_code); ++ ++ return (ret==_SUCCESS)?0:-1; ++} ++ ++int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len) ++{ ++ int bytes_written = 0; ++ ++ //We use the same address as our HW MAC address ++ _rtw_memcpy(command, net->dev_addr, ETH_ALEN); ++ ++ bytes_written = ETH_ALEN; ++ return bytes_written; ++} ++ ++int rtw_android_set_block(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1; ++ ++ #ifdef CONFIG_IOCTL_CFG80211 ++ wdev_to_priv(adapter->rtw_wdev)->block = (*block_value=='0')?_FALSE:_TRUE; ++ #endif ++ ++ return 0; ++} ++ ++int get_int_from_command( char* pcmd ) ++{ ++ int i = 0; ++ ++ for( i = 0; i < strlen( pcmd ); i++ ) ++ { ++ if ( pcmd[ i ] == '=' ) ++ { ++ // Skip the '=' and space characters. ++ i += 2; ++ break; ++ } ++ } ++ return ( rtw_atoi( pcmd + i ) ); ++} ++ ++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) ++{ ++ int ret = 0; ++ char *command = NULL; ++ int cmd_num; ++ int bytes_written = 0; ++ android_wifi_priv_cmd priv_cmd; ++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net); ++#ifdef CONFIG_WFD ++ struct wifi_display_info *pwfd_info; ++#endif ++ ++ rtw_lock_suspend(); ++ ++ if (!ifr->ifr_data) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ //DBG_871X("%s priv_cmd.buf=%p priv_cmd.total_len=%d priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len); ++ command = rtw_zmalloc(priv_cmd.total_len); ++ if (!command) ++ { ++ DBG_871X("%s: failed to allocate memory\n", __FUNCTION__); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)){ ++ DBG_871X("%s: failed to access memory\n", __FUNCTION__); ++ ret = -EFAULT; ++ goto exit; ++ } ++ if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ DBG_871X("%s: Android private cmd \"%s\" on %s\n" ++ , __FUNCTION__, command, ifr->ifr_name); ++ ++ cmd_num = rtw_android_cmdstr_to_num(command); ++ ++ switch(cmd_num) { ++ case ANDROID_WIFI_CMD_START: ++ //bytes_written = wl_android_wifi_on(net); ++ goto response; ++ case ANDROID_WIFI_CMD_SETFWPATH: ++ goto response; ++ } ++ ++ if (!g_wifi_on) { ++ DBG_871X("%s: Ignore private cmd \"%s\" - iface %s is down\n" ++ ,__FUNCTION__, command, ifr->ifr_name); ++ ret = 0; ++ goto exit; ++ } ++ ++ switch(cmd_num) { ++ ++ case ANDROID_WIFI_CMD_STOP: ++ //bytes_written = wl_android_wifi_off(net); ++ break; ++ ++ case ANDROID_WIFI_CMD_SCAN_ACTIVE: ++ //rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); ++#ifdef CONFIG_PLATFORM_MSTAR ++#ifdef CONFIG_IOCTL_CFG80211 ++ (wdev_to_priv(net->ieee80211_ptr))->bandroid_scan = _TRUE; ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_PLATFORM_MSTAR ++ break; ++ case ANDROID_WIFI_CMD_SCAN_PASSIVE: ++ //rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); ++ break; ++ ++ case ANDROID_WIFI_CMD_RSSI: ++ bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_LINKSPEED: ++ bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_MACADDR: ++ bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_BLOCK: ++ bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_RXFILTER_START: ++ //bytes_written = net_os_set_packet_filter(net, 1); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_STOP: ++ //bytes_written = net_os_set_packet_filter(net, 0); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_ADD: ++ //int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; ++ //bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_REMOVE: ++ //int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; ++ //bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); ++ break; ++ ++ case ANDROID_WIFI_CMD_BTCOEXSCAN_START: ++ /* TBD: BTCOEXSCAN-START */ ++ break; ++ case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP: ++ /* TBD: BTCOEXSCAN-STOP */ ++ break; ++ case ANDROID_WIFI_CMD_BTCOEXMODE: ++ #if 0 ++ uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0'; ++ if (mode == 1) ++ net_os_set_packet_filter(net, 0); /* DHCP starts */ ++ else ++ net_os_set_packet_filter(net, 1); /* DHCP ends */ ++#ifdef WL_CFG80211 ++ bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command); ++#endif ++ #endif ++ break; ++ ++ case ANDROID_WIFI_CMD_SETSUSPENDOPT: ++ //bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_SETBAND: ++ { ++ uint band = *(command + strlen("SETBAND") + 1) - '0'; ++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net); ++ ++ if (padapter->chip_type == RTL8192D) ++ padapter->setband = band; ++ ++ break; ++ } ++ case ANDROID_WIFI_CMD_GETBAND: ++ //bytes_written = wl_android_get_band(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_COUNTRY: ++ bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len); ++ break; ++ ++#ifdef PNO_SUPPORT ++ case ANDROID_WIFI_CMD_PNOSSIDCLR_SET: ++ //bytes_written = dhd_dev_pno_reset(net); ++ break; ++ case ANDROID_WIFI_CMD_PNOSETUP_SET: ++ //bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_PNOENABLE_SET: ++ //uint pfn_enabled = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0'; ++ //bytes_written = dhd_dev_pno_enable(net, pfn_enabled); ++ break; ++#endif ++ ++ case ANDROID_WIFI_CMD_P2P_DEV_ADDR: ++ bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_P2P_SET_NOA: ++ //int skip = strlen(CMD_P2P_SET_NOA) + 1; ++ //bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); ++ break; ++ case ANDROID_WIFI_CMD_P2P_GET_NOA: ++ //bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_P2P_SET_PS: ++ //int skip = strlen(CMD_P2P_SET_PS) + 1; ++ //bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); ++ break; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: ++ { ++ int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3; ++ bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0'); ++ break; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_WFD ++ case ANDROID_WIFI_CMD_WFD_ENABLE: ++ { ++ // Commented by Albert 2012/07/24 ++ // We can enable the WFD function by using the following command: ++ // wpa_cli driver wfd-enable ++ ++ pwfd_info = &padapter->wfd_info; ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ pwfd_info->wfd_enable = _TRUE; ++ break; ++ } ++ ++ case ANDROID_WIFI_CMD_WFD_DISABLE: ++ { ++ // Commented by Albert 2012/07/24 ++ // We can disable the WFD function by using the following command: ++ // wpa_cli driver wfd-disable ++ ++ pwfd_info = &padapter->wfd_info; ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ pwfd_info->wfd_enable = _FALSE; ++ break; ++ } ++ case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: ++ { ++ // Commented by Albert 2012/07/24 ++ // We can set the tcp port number by using the following command: ++ // wpa_cli driver wfd-set-tcpport = 554 ++ ++ pwfd_info = &padapter->wfd_info; ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ pwfd_info->rtsp_ctrlport = ( u16 ) get_int_from_command( priv_cmd.buf ); ++ break; ++ } ++ case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: ++ { ++ break; ++ } ++ case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: ++ { ++ // Commented by Albert 2012/08/28 ++ // Specify the WFD device type ( WFD source/primary sink ) ++ ++ struct wifi_display_info *pwfd_info; ++ _adapter* padapter = ( _adapter * ) rtw_netdev_priv(net); ++ ++ pwfd_info = &padapter->wfd_info; ++ if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) ++ { ++ pwfd_info->wfd_device_type = ( u8 ) get_int_from_command( priv_cmd.buf ); ++ ++ pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL; ++ } ++ break; ++ } ++#endif ++ default: ++ DBG_871X("Unknown PRIVATE command %s - ignored\n", command); ++ snprintf(command, 3, "OK"); ++ bytes_written = strlen("OK"); ++ } ++ ++response: ++ if (bytes_written >= 0) { ++ if ((bytes_written == 0) && (priv_cmd.total_len > 0)) ++ command[0] = '\0'; ++ if (bytes_written >= priv_cmd.total_len) { ++ DBG_871X("%s: bytes_written = %d\n", __FUNCTION__, bytes_written); ++ bytes_written = priv_cmd.total_len; ++ } else { ++ bytes_written++; ++ } ++ priv_cmd.used_len = bytes_written; ++ if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) { ++ DBG_871X("%s: failed to copy data to user buffer\n", __FUNCTION__); ++ ret = -EFAULT; ++ } ++ } ++ else { ++ ret = bytes_written; ++ } ++ ++exit: ++ rtw_unlock_suspend(); ++ if (command) { ++ rtw_mfree(command, priv_cmd.total_len); ++ } ++ ++ return ret; ++} ++ ++ ++/** ++ * Functions for Android WiFi card detection ++ */ ++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) ++ ++static int g_wifidev_registered = 0; ++static struct semaphore wifi_control_sem; ++static struct wifi_platform_data *wifi_control_data = NULL; ++static struct resource *wifi_irqres = NULL; ++ ++static int wifi_add_dev(void); ++static void wifi_del_dev(void); ++ ++int rtw_android_wifictrl_func_add(void) ++{ ++ int ret = 0; ++ sema_init(&wifi_control_sem, 0); ++ ++ ret = wifi_add_dev(); ++ if (ret) { ++ DBG_871X("%s: platform_driver_register failed\n", __FUNCTION__); ++ return ret; ++ } ++ g_wifidev_registered = 1; ++ ++ /* Waiting callback after platform_driver_register is done or exit with error */ ++ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) { ++ ret = -EINVAL; ++ DBG_871X("%s: platform_driver_register timeout\n", __FUNCTION__); ++ } ++ ++ return ret; ++} ++ ++void rtw_android_wifictrl_func_del(void) ++{ ++ if (g_wifidev_registered) ++ { ++ wifi_del_dev(); ++ g_wifidev_registered = 0; ++ } ++} ++ ++void *wl_android_prealloc(int section, unsigned long size) ++{ ++ void *alloc_ptr = NULL; ++ if (wifi_control_data && wifi_control_data->mem_prealloc) { ++ alloc_ptr = wifi_control_data->mem_prealloc(section, size); ++ if (alloc_ptr) { ++ DBG_871X("success alloc section %d\n", section); ++ if (size != 0L) ++ memset(alloc_ptr, 0, size); ++ return alloc_ptr; ++ } ++ } ++ ++ DBG_871X("can't alloc section %d\n", section); ++ return NULL; ++} ++ ++int wifi_get_irq_number(unsigned long *irq_flags_ptr) ++{ ++ if (wifi_irqres) { ++ *irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK; ++ return (int)wifi_irqres->start; ++ } ++#ifdef CUSTOM_OOB_GPIO_NUM ++ return CUSTOM_OOB_GPIO_NUM; ++#else ++ return -1; ++#endif ++} ++ ++int wifi_set_power(int on, unsigned long msec) ++{ ++ DBG_871X("%s = %d\n", __FUNCTION__, on); ++ if (wifi_control_data && wifi_control_data->set_power) { ++ wifi_control_data->set_power(on); ++ } ++ if (msec) ++ msleep(msec); ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++int wifi_get_mac_addr(unsigned char *buf) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ if (!buf) ++ return -EINVAL; ++ if (wifi_control_data && wifi_control_data->get_mac_addr) { ++ return wifi_control_data->get_mac_addr(buf); ++ } ++ return -EOPNOTSUPP; ++} ++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE) ++void *wifi_get_country_code(char *ccode) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ if (!ccode) ++ return NULL; ++ if (wifi_control_data && wifi_control_data->get_country_code) { ++ return wifi_control_data->get_country_code(ccode); ++ } ++ return NULL; ++} ++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */ ++ ++static int wifi_set_carddetect(int on) ++{ ++ DBG_871X("%s = %d\n", __FUNCTION__, on); ++ if (wifi_control_data && wifi_control_data->set_carddetect) { ++ wifi_control_data->set_carddetect(on); ++ } ++ return 0; ++} ++ ++static int wifi_probe(struct platform_device *pdev) ++{ ++ struct wifi_platform_data *wifi_ctrl = ++ (struct wifi_platform_data *)(pdev->dev.platform_data); ++ int wifi_wake_gpio = 0; ++ ++ DBG_871X("## %s\n", __FUNCTION__); ++ wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq"); ++ ++ if (wifi_irqres == NULL) ++ wifi_irqres = platform_get_resource_byname(pdev, ++ IORESOURCE_IRQ, "bcm4329_wlan_irq"); ++ else ++ wifi_wake_gpio = wifi_irqres->start; ++ ++#ifdef CONFIG_GPIO_WAKEUP ++ printk("%s: gpio:%d wifi_wake_gpio:%d\n", __func__, ++ wifi_irqres->start, wifi_wake_gpio); ++ ++ if (wifi_wake_gpio > 0) { ++ gpio_request(wifi_wake_gpio, "oob_irq"); ++ gpio_direction_input(wifi_wake_gpio); ++ oob_irq = gpio_to_irq(wifi_wake_gpio); ++ printk("%s oob_irq:%d\n", __func__, oob_irq); ++ } ++#endif ++ wifi_control_data = wifi_ctrl; ++ ++ wifi_set_power(1, 0); /* Power On */ ++ wifi_set_carddetect(1); /* CardDetect (0->1) */ ++ ++ up(&wifi_control_sem); ++ return 0; ++} ++ ++static int wifi_remove(struct platform_device *pdev) ++{ ++ struct wifi_platform_data *wifi_ctrl = ++ (struct wifi_platform_data *)(pdev->dev.platform_data); ++ ++ DBG_871X("## %s\n", __FUNCTION__); ++ wifi_control_data = wifi_ctrl; ++ ++ wifi_set_power(0, 0); /* Power Off */ ++ wifi_set_carddetect(0); /* CardDetect (1->0) */ ++ ++ up(&wifi_control_sem); ++ return 0; ++} ++ ++static int wifi_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ DBG_871X("##> %s\n", __FUNCTION__); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) ++ bcmsdh_oob_intr_set(0); ++#endif ++ return 0; ++} ++ ++static int wifi_resume(struct platform_device *pdev) ++{ ++ DBG_871X("##> %s\n", __FUNCTION__); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) ++ if (dhd_os_check_if_up(bcmsdh_get_drvdata())) ++ bcmsdh_oob_intr_set(1); ++#endif ++ return 0; ++} ++ ++/* temporarily use these two */ ++static struct platform_driver wifi_device = { ++ .probe = wifi_probe, ++ .remove = wifi_remove, ++ .suspend = wifi_suspend, ++ .resume = wifi_resume, ++ .driver = { ++ .name = "bcmdhd_wlan", ++ } ++}; ++ ++static struct platform_driver wifi_device_legacy = { ++ .probe = wifi_probe, ++ .remove = wifi_remove, ++ .suspend = wifi_suspend, ++ .resume = wifi_resume, ++ .driver = { ++ .name = "bcm4329_wlan", ++ } ++}; ++ ++static int wifi_add_dev(void) ++{ ++ DBG_871X("## Calling platform_driver_register\n"); ++ platform_driver_register(&wifi_device); ++ platform_driver_register(&wifi_device_legacy); ++ return 0; ++} ++ ++static void wifi_del_dev(void) ++{ ++ DBG_871X("## Unregister platform_driver_register\n"); ++ platform_driver_unregister(&wifi_device); ++ platform_driver_unregister(&wifi_device_legacy); ++} ++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_intf.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_intf.c +new file mode 100644 +index 00000000..d6a4698e +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_intf.c +@@ -0,0 +1,1972 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_SDIO_HCI ++#error "CONFIG_SDIO_HCI shall be on!\n" ++#endif ++ ++#include ++#include ++ ++#if defined(CONFIG_WOWLAN) || defined(CONFIG_PLATFORM_SPRD) ++#include ++#include ++#endif ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#include ++#endif // CONFIG_PLATFORM_SPRD ++ ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifdef CONFIG_PM_RUNTIME ++#include ++#endif ++#endif ++ ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++#if defined(CONFIG_MMC_SUNXI_POWER_CONTROL) ++ ++#ifdef CONFIG_WITS_EVB_V13 ++#define SDIOID 0 ++#else ++#define SDIOID (CONFIG_CHIP_ID==1123 ? 3 : 1) ++#endif ++ ++#define SUNXI_SDIO_WIFI_NUM_RTL8189ES 10 ++extern void sunximmc_rescan_card(unsigned id, unsigned insert); ++extern int mmc_pm_get_mod_type(void); ++extern int mmc_pm_gpio_ctrl(char* name, int level); ++/* ++* rtl8189es_shdn = port:PH09<1><0> ++* rtl8189es_wakeup = port:PH10<1><1> ++* rtl8189es_vdd_en = port:PH11<1><0> ++* rtl8189es_vcc_en = port:PH12<1><0> ++*/ ++ ++int rtl8189es_sdio_powerup(void) ++{ ++ mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 1); ++ udelay(100); ++ mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 1); ++ udelay(50); ++ mmc_pm_gpio_ctrl("rtl8189es_shdn", 1); ++ return 0; ++} ++int rtl8189es_sdio_poweroff(void) ++{ ++ mmc_pm_gpio_ctrl("rtl8189es_shdn", 0); ++ mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 0); ++ mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 0); ++ return 0; ++} ++#endif //defined(CONFIG_MMC_SUNXI_POWER_CONTROL) ++#endif //CONFIG_PLATFORM_ARM_SUNxI ++ ++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++#ifdef CONFIG_MMC ++#include ++static unsigned sdc_id = 0; ++extern void sw_mci_rescan_card(unsigned id, unsigned insert); ++extern int wifi_pm_get_mod_type(void); ++extern void wifi_pm_power(int on); ++#endif //CONFIG_MMC ++#endif //#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++ ++#ifndef dev_to_sdio_func ++#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev) ++#endif ++ ++#ifdef CONFIG_WOWLAN ++static struct mmc_host *mmc_host = NULL; ++#endif ++ ++static const struct sdio_device_id sdio_ids[] = { ++#ifdef CONFIG_RTL8723A ++ { SDIO_DEVICE(0x024c, 0x8723) }, ++#endif //CONFIG_RTL8723A ++ ++#ifdef CONFIG_RTL8188E ++ { SDIO_DEVICE(0x024c, 0x8179) }, ++#endif //CONFIG_RTL8188E ++ ++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) /* temporarily add this to accept all sdio wlan id */ ++ { SDIO_DEVICE_CLASS(SDIO_CLASS_WLAN) }, ++#endif ++// { /* end: all zeroes */ }, ++}; ++ ++static int rtw_drv_init(struct sdio_func *func, const struct sdio_device_id *id); ++static void rtw_dev_remove(struct sdio_func *func); ++static int rtw_sdio_resume(struct device *dev); ++static int rtw_sdio_suspend(struct device *dev); ++#ifdef CONFIG_PM_RUNTIME ++static void rtw_start_runtime(struct sdio_func *func); ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)) ++static const struct dev_pm_ops rtw_sdio_pm_ops = { ++ .suspend = rtw_sdio_suspend, ++ .resume = rtw_sdio_resume, ++}; ++#endif ++ ++struct sdio_drv_priv { ++ struct sdio_driver r871xs_drv; ++ int drv_registered; ++}; ++ ++static struct sdio_drv_priv sdio_drvpriv = { ++ .r871xs_drv.probe = rtw_drv_init, ++ .r871xs_drv.remove = rtw_dev_remove, ++ .r871xs_drv.name = (char*)DRV_NAME, ++ .r871xs_drv.id_table = sdio_ids, ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)) ++ .r871xs_drv.drv = { ++ .pm = &rtw_sdio_pm_ops, ++ } ++ #endif ++}; ++ ++static void sd_sync_int_hdl(struct sdio_func *func) ++{ ++ struct dvobj_priv *psdpriv; ++ ++ ++ psdpriv = sdio_get_drvdata(func); ++ ++ if (!psdpriv->if1) { ++ DBG_871X("%s if1 == NULL\n", __func__); ++ return; ++ } ++ ++ rtw_sdio_set_irq_thd(psdpriv, current); ++ sd_int_hdl(psdpriv->if1); ++ rtw_sdio_set_irq_thd(psdpriv, NULL); ++} ++ ++int sdio_alloc_irq(struct dvobj_priv *dvobj) ++{ ++ PSDIO_DATA psdio_data; ++ struct sdio_func *func; ++ int err; ++ ++ psdio_data = &dvobj->intf_data; ++ func = psdio_data->func; ++ ++ sdio_claim_host(func); ++ ++ err = sdio_claim_irq(func, &sd_sync_int_hdl); ++ if (err) ++ printk(KERN_CRIT "%s: sdio_claim_irq FAIL(%d)!\n", __func__, err); ++ else ++ dvobj->irq_alloc = 1; ++ ++ sdio_release_host(func); ++ ++ return err?_FAIL:_SUCCESS; ++} ++ ++void sdio_free_irq(struct dvobj_priv *dvobj) ++{ ++ PSDIO_DATA psdio_data; ++ struct sdio_func *func; ++ int err; ++ ++ if (dvobj->irq_alloc) { ++ psdio_data = &dvobj->intf_data; ++ func = psdio_data->func; ++ ++ if (func) { ++ sdio_claim_host(func); ++ err = sdio_release_irq(func); ++ if (err) ++ DBG_871X_LEVEL(_drv_err_,"%s: sdio_release_irq FAIL(%d)!\n", __func__, err); ++ sdio_release_host(func); ++ } ++ dvobj->irq_alloc = 0; ++ } ++} ++ ++#ifdef CONFIG_GPIO_WAKEUP ++extern unsigned int oob_irq; ++static irqreturn_t gpio_hostwakeup_irq_thread(int irq, void *data) ++{ ++ PADAPTER padapter = (PADAPTER)data; ++ DBG_871X_LEVEL(_drv_always_, "gpio_hostwakeup_irq_thread\n"); ++ /* Disable interrupt before calling handler */ ++ //disable_irq_nosync(oob_irq); ++ rtw_lock_suspend_timeout(HZ/2); ++ return IRQ_HANDLED; ++} ++ ++static u8 gpio_hostwakeup_alloc_irq(PADAPTER padapter) ++{ ++ int err; ++ if (oob_irq == 0) ++ return _FAIL; ++ /* dont set it IRQF_TRIGGER_LOW, or wowlan */ ++ /* power is high after suspend */ ++ /* and failing can prevent can not sleep issue if */ ++ /* wifi gpio12 pin is not linked with CPU */ ++ err = request_threaded_irq(oob_irq, gpio_hostwakeup_irq_thread, NULL, ++ //IRQF_TRIGGER_LOW | IRQF_ONESHOT, ++ IRQF_TRIGGER_FALLING, ++ "rtw_wifi_gpio_wakeup", padapter); ++ if (err < 0) { ++ DBG_871X("Oops: can't allocate gpio irq %d err:%d\n", oob_irq, err); ++ return _FALSE; ++ } else { ++ DBG_871X("allocate gpio irq %d ok\n", oob_irq); ++} ++ ++ enable_irq_wake(oob_irq); ++ return _SUCCESS; ++} ++ ++static void gpio_hostwakeup_free_irq(PADAPTER padapter) ++{ ++ if (oob_irq == 0) ++ return; ++ disable_irq_wake(oob_irq); ++ free_irq(oob_irq, padapter); ++} ++#endif ++ ++static u32 sdio_init(struct dvobj_priv *dvobj) ++{ ++ PSDIO_DATA psdio_data; ++ struct sdio_func *func; ++ int err; ++ ++_func_enter_; ++ ++ psdio_data = &dvobj->intf_data; ++ func = psdio_data->func; ++ ++ //3 1. init SDIO bus ++ sdio_claim_host(func); ++ ++ err = sdio_enable_func(func); ++ if (err) { ++ DBG_8192C(KERN_CRIT "%s: sdio_enable_func FAIL(%d)!\n", __func__, err); ++ goto release; ++ } ++ ++ err = sdio_set_block_size(func, 512); ++ if (err) { ++ DBG_8192C(KERN_CRIT "%s: sdio_set_block_size FAIL(%d)!\n", __func__, err); ++ goto release; ++ } ++ psdio_data->block_transfer_len = 512; ++ psdio_data->tx_block_mode = 1; ++ psdio_data->rx_block_mode = 1; ++ ++release: ++ sdio_release_host(func); ++ ++exit: ++_func_exit_; ++ ++ if (err) return _FAIL; ++ return _SUCCESS; ++} ++ ++static void sdio_deinit(struct dvobj_priv *dvobj) ++{ ++ struct sdio_func *func; ++ int err; ++ ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+sdio_deinit\n")); ++ ++ func = dvobj->intf_data.func; ++ ++ if (func) { ++ sdio_claim_host(func); ++ err = sdio_disable_func(func); ++ if (err) ++ DBG_8192C(KERN_ERR "%s: sdio_disable_func(%d)\n", __func__, err); ++ ++ if (dvobj->irq_alloc) { ++ err = sdio_release_irq(func); ++ if (err) ++ DBG_8192C(KERN_ERR "%s: sdio_release_irq(%d)\n", __func__, err); ++ } ++ ++ sdio_release_host(func); ++ } ++} ++static struct dvobj_priv *sdio_dvobj_init(struct sdio_func *func) ++{ ++ int status = _FAIL; ++ struct dvobj_priv *dvobj = NULL; ++ PSDIO_DATA psdio; ++_func_enter_; ++ ++ if ((dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj))) == NULL) { ++ goto exit; ++ } ++ ++ _rtw_mutex_init(&dvobj->hw_init_mutex); ++ _rtw_mutex_init(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_init(&dvobj->setch_mutex); ++ _rtw_mutex_init(&dvobj->setbw_mutex); ++ ++ sdio_set_drvdata(func, dvobj); ++ dvobj->processing_dev_remove = _FALSE; ++ ++#ifdef CONFIG_WOWLAN ++ sdio_claim_host(func); ++ mmc_host = func->card->host; ++ sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); ++ sdio_release_host(func); ++#endif ++ ++ psdio = &dvobj->intf_data; ++ psdio->func = func; ++ ++ if (sdio_init(dvobj) != _SUCCESS) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!\n", __FUNCTION__)); ++ goto free_dvobj; ++ } ++ rtw_reset_continual_io_error(dvobj); ++ status = _SUCCESS; ++ ++free_dvobj: ++ if (status != _SUCCESS && dvobj) { ++ sdio_set_drvdata(func, NULL); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ dvobj = NULL; ++ } ++exit: ++_func_exit_; ++ return dvobj; ++} ++ ++static void sdio_dvobj_deinit(struct sdio_func *func) ++{ ++ struct dvobj_priv *dvobj = sdio_get_drvdata(func); ++_func_enter_; ++ ++ sdio_set_drvdata(func, NULL); ++ if (dvobj) { ++ sdio_deinit(dvobj); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ } ++ ++_func_exit_; ++ return; ++} ++static void decide_chip_type_by_device_id(PADAPTER padapter, u32 id) ++{ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ ++#if 0 ++ switch (id) ++ { ++ case 0x8723: ++ padapter->chip_type = RTL8723A; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8723AS; ++ break; ++ case 0x8179: ++ padapter->chip_type = RTL8188E; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8188ES; ++ break; ++ } ++#else ++#if defined(CONFIG_RTL8723A) ++ padapter->chip_type = RTL8723A; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8723AS; ++#elif defined(CONFIG_RTL8188E) ++ padapter->chip_type = RTL8188E; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8188ES; ++#endif ++#endif ++} ++ ++static void sd_intf_start(PADAPTER padapter) ++{ ++ if (padapter == NULL) { ++ DBG_8192C(KERN_ERR "%s: padapter is NULL!\n", __func__); ++ return; ++ } ++ ++ // hal dep ++ rtw_hal_enable_interrupt(padapter); ++} ++ ++static void sd_intf_stop(PADAPTER padapter) ++{ ++ if (padapter == NULL) { ++ DBG_8192C(KERN_ERR "%s: padapter is NULL!\n", __func__); ++ return; ++ } ++ ++ // hal dep ++ rtw_hal_disable_interrupt(padapter); ++} ++ ++/* ++ * Do deinit job corresponding to netdev_open() ++ */ ++void rtw_dev_unload(PADAPTER padapter) ++{ ++ struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_dev_unload\n")); ++ ++ padapter->bDriverStopped = _TRUE; ++ #ifdef CONFIG_XMIT_ACK ++ if (padapter->xmitpriv.ack_tx) ++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); ++ #endif ++ ++ if (padapter->bup == _TRUE) ++ { ++ // stop TX ++// val8 = 0xFF; ++// rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE,&val8); ++ ++#if 0 ++ if (padapter->intf_stop) ++ padapter->intf_stop(padapter); ++#else ++ sd_intf_stop(padapter); ++#endif ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop intf complete!\n")); ++ ++ if (!pwrctl->bInternalAutoSuspend) ++ rtw_stop_drv_threads(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop thread complete!\n")); ++ ++ if (padapter->bSurpriseRemoved == _FALSE) ++ { ++#ifdef CONFIG_WOWLAN ++ if (pwrctl->bSupportRemoteWakeup == _TRUE && ++ pwrctl->wowlan_mode ==_TRUE) { ++ DBG_871X_LEVEL(_drv_always_, "%s bSupportRemoteWakeup==_TRUE do not run rtw_hal_deinit()\n",__FUNCTION__); ++ } ++ else ++#endif ++ { ++ //amy modify 20120221 for power seq is different between driver open and ips ++ rtw_hal_deinit(padapter); ++ } ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: deinit hal complelt!\n")); ++ ++ padapter->bup = _FALSE; ++ } ++ else { ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("rtw_dev_unload: bup==_FALSE\n")); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-rtw_dev_unload\n")); ++} ++ ++_adapter *rtw_sdio_if1_init(struct dvobj_priv *dvobj, const struct sdio_device_id *pdid) ++{ ++ int status = _FAIL; ++ struct net_device *pnetdev; ++ PADAPTER padapter = NULL; ++ ++ if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) { ++ goto exit; ++ } ++ padapter->dvobj = dvobj; ++ dvobj->if1 = padapter; ++ ++ padapter->bDriverStopped=_TRUE; ++ ++ dvobj->padapters[dvobj->iface_nums++] = padapter; ++ padapter->iface_id = IFACE_ID0; ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) ++ //set adapter_type/iface type for primary padapter ++ padapter->isprimary = _TRUE; ++ padapter->adapter_type = PRIMARY_ADAPTER; ++ #ifndef CONFIG_HWPORT_SWAP ++ padapter->iface_type = IFACE_PORT0; ++ #else ++ padapter->iface_type = IFACE_PORT1; ++ #endif ++#endif ++ ++ padapter->interface_type = RTW_SDIO; ++ decide_chip_type_by_device_id(padapter, (u32)pdid->device); ++ ++ //3 1. init network device data ++ pnetdev = rtw_init_netdev(padapter); ++ if (!pnetdev) ++ goto free_adapter; ++ ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj)); ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)); ++#endif ++ ++ //3 3. init driver special setting, interface, OS and hardware relative ++ ++ //4 3.1 set hardware operation functions ++ hal_set_hal_ops(padapter); ++ ++ ++ //3 5. initialize Chip version ++ padapter->intf_start = &sd_intf_start; ++ padapter->intf_stop = &sd_intf_stop; ++ ++ if (rtw_init_io_priv(padapter, sdio_set_intf_ops) == _FAIL) ++ { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ++ ("rtw_drv_init: Can't init io_priv\n")); ++ goto free_hal_data; ++ } ++ ++ rtw_hal_read_chip_version(padapter); ++ ++ rtw_hal_chip_configure(padapter); ++ ++ ++ //3 6. read efuse/eeprom data ++ rtw_hal_read_chip_info(padapter); ++ ++ //3 7. init driver common data ++ if (rtw_init_drv_sw(padapter) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ++ ("rtw_drv_init: Initialize driver software resource Failed!\n")); ++ goto free_hal_data; ++ } ++ ++ //3 8. get WLan MAC address ++ // set mac addr ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++#ifdef CONFIG_P2P ++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr); ++#endif ++ rtw_hal_disable_interrupt(padapter); ++ ++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n" ++ ,padapter->bDriverStopped ++ ,padapter->bSurpriseRemoved ++ ,padapter->bup ++ ,padapter->hw_init_completed ++ ); ++ ++ status = _SUCCESS; ++ ++free_hal_data: ++ if(status != _SUCCESS && padapter->HalData) ++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData))); ++ ++free_wdev: ++ if(status != _SUCCESS) { ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++ rtw_wdev_free(padapter->rtw_wdev); ++ #endif ++ } ++ ++free_adapter: ++ if (status != _SUCCESS) { ++ if (pnetdev) ++ rtw_free_netdev(pnetdev); ++ else if (padapter) ++ rtw_vmfree((u8*)padapter, sizeof(*padapter)); ++ padapter = NULL; ++ } ++exit: ++ return padapter; ++} ++ ++static void rtw_sdio_if1_deinit(_adapter *if1) ++{ ++ struct net_device *pnetdev = if1->pnetdev; ++ struct mlme_priv *pmlmepriv= &if1->mlmepriv; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ rtw_disassoc_cmd(if1, 0, _FALSE); ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(if1); ++ #ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(if1); ++ #endif ++#endif ++ ++#ifdef CONFIG_GPIO_WAKEUP ++ gpio_hostwakeup_free_irq(if1); ++#endif ++/* ++ if(if1->DriverState != DRIVER_DISAPPEAR) { ++ if(pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++ } ++*/ ++ rtw_cancel_all_timer(if1); ++ ++#ifdef CONFIG_WOWLAN ++ adapter_to_pwrctl(if1)->wowlan_mode=_FALSE; ++ DBG_871X_LEVEL(_drv_always_, "%s wowlan_mode:%d\n", __func__, adapter_to_pwrctl(if1)->wowlan_mode); ++#endif //CONFIG_WOWLAN ++ ++ rtw_dev_unload(if1); ++ DBG_871X("+r871xu_dev_remove, hw_init_completed=%d\n", if1->hw_init_completed); ++ ++ rtw_handle_dualmac(if1, 0); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if (if1->rtw_wdev) ++ { ++ //rtw_wdev_unregister(if1->rtw_wdev); ++ rtw_wdev_free(if1->rtw_wdev); ++ } ++#endif ++ ++ rtw_free_drv_sw(if1); ++ ++ if(pnetdev) ++ rtw_free_netdev(pnetdev); ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link down\n"); ++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); ++#endif ++ ++} ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifdef CONFIG_PM_RUNTIME ++#include ++static void rtw_start_runtime(struct sdio_func *func) ++{ ++ unsigned long flags; ++ struct mmc_card *card = func->card; ++ struct mmc_host *host = card->host; ++ ++ DBG_871X("%s \n", __func__); ++ ++ pm_runtime_no_callbacks(&func->dev); ++ pm_suspend_ignore_children(&func->dev, true); ++ pm_runtime_set_autosuspend_delay(&func->dev, 50); ++ pm_runtime_use_autosuspend(&func->dev); ++ pm_runtime_put_autosuspend(&func->dev); ++} ++#endif ++#endif ++ ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++ */ ++static int rtw_drv_init( ++ struct sdio_func *func, ++ const struct sdio_device_id *id) ++{ ++ int status = _FAIL; ++ struct net_device *pnetdev; ++ PADAPTER if1 = NULL, if2 = NULL; ++ struct dvobj_priv *dvobj; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_info_, ++ ("+rtw_drv_init: vendor=0x%04x device=0x%04x class=0x%02x\n", ++ func->vendor, func->device, func->class)); ++ ++ if ((dvobj = sdio_dvobj_init(func)) == NULL) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); ++ goto exit; ++ } ++ ++ if ((if1 = rtw_sdio_if1_init(dvobj, id)) == NULL) { ++ DBG_871X("rtw_init_primary_adapter Failed!\n"); ++ goto free_dvobj; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if ((if2 = rtw_drv_if2_init(if1, sdio_set_intf_ops)) == NULL) { ++ goto free_if1; ++ } ++#endif ++ ++ //dev_alloc_name && register_netdev ++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) { ++ goto free_if2; ++ } ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(if1); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(if1->pnetdev); ++#endif ++ ++ if (sdio_alloc_irq(dvobj) != _SUCCESS) ++ goto free_if2; ++ ++#ifdef CONFIG_GPIO_WAKEUP ++ gpio_hostwakeup_alloc_irq(if1); ++#endif ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++ if(ui_pid[1]!=0) { ++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]); ++ rtw_signal_process(ui_pid[1], SIGUSR2); ++ } ++#endif ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifdef CONFIG_PM_RUNTIME ++ rtw_start_runtime(func); ++#endif ++#endif ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ ++ status = _SUCCESS; ++ ++free_if2: ++ if(status != _SUCCESS && if2) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(if2); ++ rtw_drv_if2_free(if2); ++ #endif ++ } ++free_if1: ++ if (status != _SUCCESS && if1) { ++ rtw_sdio_if1_deinit(if1); ++ } ++free_dvobj: ++ if (status != _SUCCESS) ++ sdio_dvobj_deinit(func); ++exit: ++ return status == _SUCCESS?0:-ENODEV; ++} ++extern void rtw_unregister_netdevs(struct dvobj_priv *dvobj); ++static void rtw_dev_remove(struct sdio_func *func) ++{ ++ struct dvobj_priv *dvobj = sdio_get_drvdata(func); ++ PADAPTER padapter = dvobj->if1; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_dev_remove\n")); ++ ++ dvobj->processing_dev_remove = _TRUE; ++ rtw_unregister_netdevs(dvobj); ++ ++ if (padapter->bSurpriseRemoved == _FALSE) { ++ int err; ++ ++ /* test surprise remove */ ++ sdio_claim_host(func); ++ sdio_readb(func, 0, &err); ++ sdio_release_host(func); ++ if (err == -ENOMEDIUM) { ++ padapter->bSurpriseRemoved = _TRUE; ++ DBG_871X(KERN_NOTICE "%s: device had been removed!\n", __func__); ++ } ++ } ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ MPT_DeInitAdapter(padapter); ++#endif ++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(dvobj_to_pwrctl(dvobj)); ++#endif ++ ++ rtw_pm_set_ips(padapter, IPS_NONE); ++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); ++ ++ LeaveAllPowerSaveMode(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(dvobj->if2); ++#endif ++ ++ rtw_sdio_if1_deinit(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_free(dvobj->if2); ++#endif ++ ++ sdio_dvobj_deinit(func); ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-rtw_dev_remove\n")); ++ ++_func_exit_; ++} ++ ++#if 1 ++ ++#ifdef CONFIG_WOWLAN ++static int rtw_suspend_wow(_adapter *padapter) ++{ ++ _adapter *pbuddy_adapter = padapter->pbuddy_adapter; ++ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++ int ret = 0; ++ ++ struct wowlan_ioctl_param poidparam; ++ u8 ps_mode; ++ ++ _func_enter_; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) ++ pwrpriv->wowlan_mode = _TRUE; ++ else ++ pwrpriv->wowlan_mode = _FALSE; ++ ++ rtw_cancel_all_timer(padapter); ++ ++ if (pwrpriv->wowlan_mode == _TRUE) { ++ // 1. stop thread ++ padapter->bDriverStopped = _TRUE; //for stop thread ++ rtw_stop_drv_threads(padapter); ++ padapter->bDriverStopped = _FALSE; //for 32k command ++#ifdef CONFIG_POWER_SAVING ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif ++ // 2. disable interrupt ++ rtw_hal_disable_interrupt(padapter); // It need wait for leaving 32K. ++ ++ // 2.1 clean interupt ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ // 2.2 free irq ++ sdio_free_irq(adapter_to_dvobj(padapter)); ++ } ++ else { ++ LeaveAllPowerSaveMode(padapter); ++ } ++ ++ if(pnetdev){ ++ if(pwrpriv->wowlan_mode == _TRUE) { ++ rtw_netif_stop_queue(pnetdev); ++ } else { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ } ++ ++ DBG_871X("wowlan_mode: %d\n", pwrpriv->wowlan_mode); ++ ++ if ((pwrpriv->bSupportRemoteWakeup == _TRUE) && ++ (pwrpriv->wowlan_mode == _TRUE)) { ++ poidparam.subcode = WOWLAN_ENABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ } else { ++ //s2-1. issue rtw_disassoc_cmd to fw ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++ } ++ ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) ) ++ { ++ DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ ++ if (pwrpriv->wowlan_mode != _TRUE) ++ rtw_set_roaming(padapter, 1); ++ else ++ rtw_set_roaming(padapter, 0); ++ } ++#endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ if (pwrpriv->wowlan_mode == _FALSE) ++ { ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_dev_unload(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)){ ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_survey\n", __func__); ++ rtw_indicate_scan_done(padapter, 1); ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)){ ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_linking\n", __func__); ++ rtw_indicate_disconnect(padapter); ++ } ++ ++ sdio_deinit(adapter_to_dvobj(padapter)); ++ } ++ else ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: wowmode suspending\n", __func__); ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_survey\n", __func__); ++ rtw_indicate_scan_done(padapter, 1); ++ clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++#ifdef CONFIG_POWER_SAVING ++ rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0); ++#endif ++ } ++ ++exit: ++ ++ _func_exit_; ++ return ret; ++} ++#endif //#ifdef CONFIG_WOWLAN ++ ++static int rtw_sdio_suspend(struct device *dev) ++{ ++ struct sdio_func *func =dev_to_sdio_func(dev); ++ struct dvobj_priv *psdpriv = sdio_get_drvdata(func); ++ _adapter *padapter = psdpriv->if1; ++ ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ int ret = 0; ++#ifdef CONFIG_PLATFORM_SPRD ++ u32 value; ++#endif // CONFIG_PLATFORM_SPRD ++ ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "sdio suspend start\n"); ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ pwrpriv->bInSuspend = _TRUE; ++ ++#if (!(defined ANDROID_2X) && (defined CONFIG_PLATFORM_SPRD)) ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { ++ //we should not suspend softap, bcm also do like this ++ DBG_871X("%s should not suspend hw and system in AP mode\n",__FUNCTION__); ++ goto exit; ++ } ++#endif ++ ++ while (pwrpriv->bips_processing == _TRUE) ++ rtw_msleep_os(1); ++ ++#ifdef CONFIG_IOL_READ_EFUSE_MAP ++ if(!padapter->bup){ ++ u8 bMacPwrCtrlOn = _FALSE; ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if(bMacPwrCtrlOn) ++ rtw_hal_power_off(padapter); ++ } ++#endif ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("%s bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", __FUNCTION__ ++ ,padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto exit; ++ } ++ ++ ++#ifdef CONFIG_WOWLAN ++ rtw_suspend_wow(padapter); ++#else ++ rtw_suspend_common(padapter); ++#endif ++ ++ // interface deinit ++ sdio_deinit(adapter_to_dvobj(padapter)); ++ ++ DBG_871X_LEVEL(_drv_always_, "sdio suspend success in %d ms\n", ++ rtw_get_passing_time_ms(start_time)); ++ ++exit: ++ ++#ifdef CONFIG_MMC_PM_KEEP_POWER ++ //Android 4.0 don't support WIFI close power ++ //or power down or clock will close after wifi resume, ++ //this is sprd's bug in Android 4.0, but sprd don't ++ //want to fix it. ++ //we have test power under 8723as, power consumption is ok ++ if (func) { ++ mmc_pm_flag_t pm_flag = 0; ++ pm_flag = sdio_get_host_pm_caps(func); ++ DBG_871X("cmd: %s: suspend: PM flag = 0x%x\n", sdio_func_id(func), pm_flag); ++ if (!(pm_flag & MMC_PM_KEEP_POWER)) { ++ DBG_871X("%s: cannot remain alive while host is suspended\n", sdio_func_id(func)); ++ return -ENOSYS; ++ } else { ++ DBG_871X("cmd: suspend with MMC_PM_KEEP_POWER\n"); ++ sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); ++ } ++ } ++#endif ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifndef CONFIG_WOWLAN ++#ifdef CONFIG_RTL8188E ++#ifdef ANDROID_2X ++ /* ++ * Pull down wifi power pin here ++ * Pull up wifi power pin before sdio resume. ++ */ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF); ++#endif // ANDROID_2X ++#endif // CONFIG_RTL8188E ++#endif // CONFIG_WOWLAN ++#endif // CONFIG_PLATFORM_SPRD ++ ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ return ret; ++} ++ ++ ++#else ++static int rtw_sdio_suspend(struct device *dev) ++{ ++ struct sdio_func *func =dev_to_sdio_func(dev); ++ struct dvobj_priv *psdpriv = sdio_get_drvdata(func); ++ _adapter *padapter = psdpriv->if1; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ int ret = 0; ++#ifdef CONFIG_PLATFORM_SPRD ++ u32 value; ++#endif // CONFIG_PLATFORM_SPRD ++ ++#ifdef CONFIG_WOWLAN ++ struct wowlan_ioctl_param poidparam; ++ u8 ps_mode; ++#endif //CONFIG_WOWLAN ++ ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "sdio suspend start\n"); ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ pwrpriv->bInSuspend = _TRUE; ++ ++#if (!(defined ANDROID_2X) && (defined CONFIG_PLATFORM_SPRD)) ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { ++ //we should not suspend softap, bcm also do like this ++ DBG_871X("%s should not suspend hw and system in AP mode\n",__FUNCTION__); ++ goto exit; ++ } ++#endif ++ ++#ifdef CONFIG_WOWLAN ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) ++ pwrpriv->wowlan_mode = _TRUE; ++ else ++ pwrpriv->wowlan_mode = _FALSE; ++#endif ++ ++ //pwrpriv->bInSuspend = _TRUE; ++ ++ while (pwrpriv->bips_processing == _TRUE) ++ rtw_msleep_os(1); ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("%s bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", __FUNCTION__ ++ ,padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto exit; ++ } ++ ++ rtw_cancel_all_timer(padapter); ++ ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_mode == _TRUE) { ++ // 1. stop thread ++ padapter->bDriverStopped = _TRUE; //for stop thread ++ rtw_stop_drv_threads(padapter); ++ padapter->bDriverStopped = _FALSE; //for 32k command ++#ifdef CONFIG_POWER_SAVING ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif ++ // 2. disable interrupt ++ rtw_hal_disable_interrupt(padapter); // It need wait for leaving 32K. ++ ++ // 2.1 clean interupt ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ // 2.2 free irq ++ sdio_free_irq(adapter_to_dvobj(padapter)); ++ } else { ++ LeaveAllPowerSaveMode(padapter); ++ } ++ ++ if(pnetdev){ ++ if(pwrpriv->wowlan_mode == _TRUE) { ++ rtw_netif_stop_queue(pnetdev); ++ } else { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ } ++ ++ DBG_871X("wowlan_mode: %d\n", pwrpriv->wowlan_mode); ++ ++ if ((pwrpriv->bSupportRemoteWakeup == _TRUE) && ++ (pwrpriv->wowlan_mode == _TRUE)) { ++ poidparam.subcode = WOWLAN_ENABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ } else { ++ //s2-1. issue rtw_disassoc_cmd to fw ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++ } ++#else // !CONFIG_WOWLAN ++ LeaveAllPowerSaveMode(padapter); ++ ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++#endif // !CONFIG_WOWLAN ++ ++ //for power down during suspend, need leave ips mode before entering power down. ++ //pwrpriv->bInSuspend = _TRUE; ++ ++ //padapter->net_closed = _TRUE; ++ //s1. ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_mode != _TRUE) ++ rtw_set_roaming(padapter, 1); ++ else ++ rtw_set_roaming(padapter, 0); ++#else //CONFIG_WOWLAN ++ rtw_set_roaming(padapter, 1); ++#endif // !CONFIG_WOWLAN ++ } ++#endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_mode == _FALSE) ++ { ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_dev_unload(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)){ ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_survey\n", __func__); ++ rtw_indicate_scan_done(padapter, 1); ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)){ ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_linking\n", __func__); ++ rtw_indicate_disconnect(padapter); ++ } ++ ++ sdio_deinit(adapter_to_dvobj(padapter)); ++ } ++ else ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: wowmode suspending\n", __func__); ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ { ++ DBG_871X_LEVEL(_drv_always_, "%s: fw_under_survey\n", __func__); ++ rtw_indicate_scan_done(padapter, 1); ++ clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++#ifdef CONFIG_POWER_SAVING ++ rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0); ++#endif ++ } ++#else ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_dev_unload(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ rtw_indicate_disconnect(padapter); ++ ++ // interface deinit ++ sdio_deinit(adapter_to_dvobj(padapter)); ++#endif ++ DBG_871X_LEVEL(_drv_always_, "sdio suspend success in %d ms\n", ++ rtw_get_passing_time_ms(start_time)); ++ ++exit: ++ ++//#if (defined CONFIG_WOWLAN) || (!(defined ANDROID_2X) && (defined CONFIG_PLATFORM_SPRD)) ++#if (defined CONFIG_WOWLAN) ++#if (!(defined ANDROID_2X)) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34)) ++ //Android 4.0 don't support WIFI close power ++ //or power down or clock will close after wifi resume, ++ //this is sprd's bug in Android 4.0, but sprd don't ++ //want to fix it. ++ //we have test power under 8723as, power consumption is ok ++ if (func) { ++ mmc_pm_flag_t pm_flag = 0; ++ pm_flag = sdio_get_host_pm_caps(func); ++ DBG_871X("cmd: %s: suspend: PM flag = 0x%x\n", sdio_func_id(func), pm_flag); ++ if (!(pm_flag & MMC_PM_KEEP_POWER)) { ++ DBG_871X("%s: cannot remain alive while host is suspended\n", sdio_func_id(func)); ++ return -ENOSYS; ++ } else { ++ DBG_871X("cmd: suspend with MMC_PM_KEEP_POWER\n"); ++ sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); ++ } ++ } ++#endif ++#endif ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifndef CONFIG_WOWLAN ++#ifdef CONFIG_RTL8188E ++#ifdef ANDROID_2X ++ /* ++ * Pull down wifi power pin here ++ * Pull up wifi power pin before sdio resume. ++ */ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF); ++#endif // ANDROID_2X ++#endif // CONFIG_RTL8188E ++#endif // CONFIG_WOWLAN ++#endif // CONFIG_PLATFORM_SPRD ++ ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ return ret; ++} ++#endif ++extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); ++ ++#if 1 ++#ifdef CONFIG_WOWLAN ++int rtw_resume_process_wow(_adapter *padapter) ++{ ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ int ret = 0; ++ ++ u32 value = 0; ++ struct wowlan_ioctl_param poidparam; ++ struct sta_info *psta = NULL; ++ ++ _func_enter_; ++ ++ if (pwrpriv->wowlan_mode == _FALSE){ ++ ++ // interface init ++ if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) { ++ ret = -1; ++ goto exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ } ++ else //pwrpriv->wowlan_mode == _TRUE ++ { ++ ++#ifdef CONFIG_POWER_SAVING ++#ifdef CONFIG_LPS ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif //CONFIG_LPS ++#endif ++ ++ pwrpriv->bFwCurrentInPSMode = _FALSE; ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ //Disable WOW, set H2C command ++ poidparam.subcode=WOWLAN_DISABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ if (psta) { ++ set_sta_rate(padapter, psta); ++ } ++ ++ padapter->bDriverStopped = _FALSE; ++ ++ DBG_871X("%s: wowmode resuming, DriverStopped:%d\n", __func__, padapter->bDriverStopped); ++ rtw_start_drv_threads(padapter); ++ ++ rtw_hal_enable_interrupt(padapter); ++ ++ // start netif queue ++ if(pnetdev) { ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ } ++ } ++ ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ ++ if (pwrpriv->wowlan_wake_reason == FWDecisionDisconnect || ++ pwrpriv->wowlan_wake_reason == Rx_DisAssoc || ++ pwrpriv->wowlan_wake_reason == Rx_DeAuth) { ++ ++ DBG_871X("%s: disconnect reason: %02x\n", __func__, ++ pwrpriv->wowlan_wake_reason); ++ rtw_indicate_disconnect(padapter); ++ rtw_sta_media_status_rpt(padapter, rtw_get_stainfo(&padapter->stapriv, ++ get_bssid(&padapter->mlmepriv)), 0); ++ rtw_free_assoc_resources(padapter, 1); ++ } else { ++ DBG_871X("%s: do roaming\n", __func__); ++ rtw_roaming(padapter, NULL); ++ } ++ ++#endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ if (pwrpriv->wowlan_wake_reason == Rx_GTK || ++ pwrpriv->wowlan_wake_reason == Rx_DisAssoc || ++ pwrpriv->wowlan_wake_reason == Rx_DeAuth) { ++ DBG_871X("%s: set ext wake lock\n", __func__); ++ rtw_lock_ext_suspend_timeout(1500); ++ } ++ ++ if (pwrpriv->wowlan_mode == _TRUE) { ++ pwrpriv->bips_processing = _FALSE; ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ pwrpriv->bips_processing = _FALSE; ++ rtw_unlock_suspend(); ++ } else { ++ DBG_871X_LEVEL(_drv_always_, "do not reset timer\n"); ++ } ++ ++ pwrpriv->wowlan_mode =_FALSE; ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++} ++#endif //CONFIG_WOWLAN ++ ++int rtw_resume_process_normal(_adapter *padapter) ++{ ++ struct net_device *pnetdev= padapter->pnetdev; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct mlme_priv *mlmepriv = &padapter->mlmepriv; ++ int ret = 0; ++ ++ _func_enter_; ++ // interface init ++ if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ rtw_hal_disable_interrupt(padapter); ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ if(rtw_resume_common(padapter)!= 0) { ++ DBG_871X("%s rtw_resume_common failed\n",__FUNCTION__); ++ goto exit; ++ } ++ _func_exit_; ++exit: ++ return ret; ++} ++ ++int rtw_resume_process(_adapter *padapter) ++{ ++ struct net_device *pnetdev; ++ struct pwrctrl_priv *pwrpriv = NULL; ++ ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "sdio resume start\n"); ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if (padapter) { ++ pnetdev = padapter->pnetdev; ++ pwrpriv = adapter_to_pwrctl(padapter); ++ } else { ++ ret = -1; ++ goto exit; ++ } ++ ++#ifdef CONFIG_WOWLAN ++ rtw_resume_process_wow( padapter); ++#else //!CONFIG_WOWLAN ++ rtw_resume_process_normal( padapter); ++#endif ++ ++ if( padapter->pid[1]!=0) { ++ DBG_871X("pid[1]:%d\n",padapter->pid[1]); ++ rtw_signal_process(padapter->pid[1], SIGUSR2); ++ } ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++exit: ++ if (pwrpriv) ++ pwrpriv->bInSuspend = _FALSE; ++ DBG_871X_LEVEL(_drv_always_, "sdio resume ret:%d in %d ms\n", ret, ++ rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ ++ return ret; ++} ++#else ++int rtw_resume_process(_adapter *padapter) ++{ ++ struct net_device *pnetdev; ++ struct pwrctrl_priv *pwrpriv = NULL; ++ u8 is_pwrlock_hold_by_caller; ++ u8 is_directly_called_by_auto_resume; ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++#ifdef CONFIG_WOWLAN ++ u32 value = 0; ++ struct wowlan_ioctl_param poidparam; ++ struct sta_info *psta = NULL; ++#endif // CONFIG_WOWLAN ++ ++ _func_enter_; ++ ++ DBG_871X_LEVEL(_drv_always_, "sdio resume start\n"); ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if (padapter) { ++ pnetdev = padapter->pnetdev; ++ pwrpriv = adapter_to_pwrctl(padapter); ++ } else { ++ ret = -1; ++ goto exit; ++ } ++ ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_mode == _FALSE){ ++ ++ // interface init ++ if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) { ++ ret = -1; ++ goto exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ } else { ++ ++#ifdef CONFIG_POWER_SAVING ++#ifdef CONFIG_LPS ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0); ++#endif //CONFIG_LPS ++#endif ++ ++ pwrpriv->bFwCurrentInPSMode = _FALSE; ++ ++ rtw_hal_disable_interrupt(padapter); ++ ++ if (padapter->HalFunc.clear_interrupt) ++ padapter->HalFunc.clear_interrupt(padapter); ++ ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ //Disable WOW, set H2C command ++ poidparam.subcode=WOWLAN_DISABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ if (psta) { ++ set_sta_rate(padapter, psta); ++ } ++ ++ padapter->bDriverStopped = _FALSE; ++ ++ DBG_871X("%s: wowmode resuming, DriverStopped:%d\n", __func__, padapter->bDriverStopped); ++ rtw_start_drv_threads(padapter); ++ ++ rtw_hal_enable_interrupt(padapter); ++ ++ // start netif queue ++ if(pnetdev) { ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ } ++ } ++#else //!CONFIG_WOWLAN ++ ++ // interface init ++ if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ rtw_hal_disable_interrupt(padapter); ++ if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) ++ { ++ ret = -1; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); ++ goto exit; ++ } ++ ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) { ++ ret = -1; ++ goto exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++#endif ++ if( padapter->pid[1]!=0) { ++ DBG_871X("pid[1]:%d\n",padapter->pid[1]); ++ rtw_signal_process(padapter->pid[1], SIGUSR2); ++ } ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_wake_reason == FWDecisionDisconnect || ++ pwrpriv->wowlan_wake_reason == Rx_DisAssoc || ++ pwrpriv->wowlan_wake_reason == Rx_DeAuth) { ++ ++ DBG_871X("%s: disconnect reason: %02x\n", __func__, ++ pwrpriv->wowlan_wake_reason); ++ rtw_indicate_disconnect(padapter); ++ rtw_sta_media_status_rpt(padapter, rtw_get_stainfo(&padapter->stapriv, ++ get_bssid(&padapter->mlmepriv)), 0); ++ rtw_free_assoc_resources(padapter, 1); ++ } else { ++ DBG_871X("%s: do roaming\n", __func__); ++ rtw_roaming(padapter, NULL); ++ } ++#else ++ rtw_roaming(padapter, NULL); ++#endif //CONFOG_WOWLAN ++#endif //CONFIG_LAYER2_ROAMING_RESUME ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++#ifdef CONFIG_WOWLAN ++ if (pwrpriv->wowlan_wake_reason == Rx_GTK || ++ pwrpriv->wowlan_wake_reason == Rx_DisAssoc || ++ pwrpriv->wowlan_wake_reason == Rx_DeAuth) { ++ DBG_871X("%s: set ext wake lock\n", __func__); ++ rtw_lock_ext_suspend_timeout(1500); ++ } ++ ++ if (pwrpriv->wowlan_mode == _TRUE) { ++ pwrpriv->bips_processing = _FALSE; ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ pwrpriv->bips_processing = _FALSE; ++ rtw_unlock_suspend(); ++ } else { ++ DBG_871X_LEVEL(_drv_always_, "do not reset timer\n"); ++ } ++ ++ pwrpriv->wowlan_mode =_FALSE; ++#endif //CONFIG_WOWLAN ++ ++exit: ++ if (pwrpriv) ++ pwrpriv->bInSuspend = _FALSE; ++ DBG_871X_LEVEL(_drv_always_, "sdio resume ret:%d in %d ms\n", ret, ++ rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ ++ return ret; ++} ++#endif ++ ++ ++static int rtw_sdio_resume(struct device *dev) ++{ ++ struct sdio_func *func =dev_to_sdio_func(dev); ++ struct dvobj_priv *psdpriv = sdio_get_drvdata(func); ++ _adapter *padapter = psdpriv->if1; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); ++ int ret = 0; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if(pwrpriv->bInternalAutoSuspend ){ ++ ret = rtw_resume_process(padapter); ++ } else { ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_resume_in_workqueue(pwrpriv); ++#else ++ if (rtw_is_earlysuspend_registered(pwrpriv) ++ #ifdef CONFIG_WOWLAN ++ && !pwrpriv->wowlan_mode ++ #endif /* CONFIG_WOWLAN */ ++ ) { ++ /* jeff: bypass resume here, do in late_resume */ ++ rtw_set_do_late_resume(pwrpriv, _TRUE); ++ } else { ++ rtw_set_do_late_resume(pwrpriv, _FALSE); ++ #ifdef CONFIG_WOWLAN ++ //rtw_lock_suspend_timeout(4000); ++ rtw_lock_suspend(); ++ #endif ++ ret = rtw_resume_process(padapter); ++ } ++#endif /* CONFIG_RESUME_IN_WORKQUEUE */ ++ } ++ ++ DBG_871X("<======== %s return %d\n", __FUNCTION__, ret); ++ return ret; ++ ++} ++ ++ ++ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++extern int console_suspend_enabled; ++#endif ++ ++ ++#ifdef CONFIG_PLATFORM_SPRD ++extern void sdhci_bus_scan(void); ++#ifndef ANDROID_2X ++extern int sdhci_device_attached(void); ++#endif ++#endif // CONFIG_PLATFORM_SPRD ++ ++static int __init rtw_drv_entry(void) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++/*depends on sunxi power control */ ++#if defined CONFIG_MMC_SUNXI_POWER_CONTROL ++ unsigned int mod_sel = mmc_pm_get_mod_type(); ++ ++ if(mod_sel == SUNXI_SDIO_WIFI_NUM_RTL8189ES) ++ { ++ rtl8189es_sdio_powerup(); ++ sunximmc_rescan_card(SDIOID, 1); ++ DBG_8192C("[rtl8189es] %s: power up, rescan card.\n", __FUNCTION__); ++ } ++ else ++ { ++ ret = -1; ++ DBG_8192C("[rtl8189es] %s: mod_sel = %d is incorrect.\n", __FUNCTION__, mod_sel); ++ } ++#endif // defined CONFIG_MMC_SUNXI_POWER_CONTROL ++ if(ret != 0) ++ goto exit; ++ ++#endif //CONFIG_PLATFORM_ARM_SUNxI ++ ++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++#ifdef CONFIG_MMC ++ script_item_value_type_e type; ++ script_item_u item; ++ ++ unsigned int mod_sel = wifi_pm_get_mod_type(); ++ ++ type = script_get_item("wifi_para", "wifi_sdc_id", &item); ++ if (SCIRPT_ITEM_VALUE_TYPE_INT != type) ++ { ++ DBG_871X("ERR: script_get_item wifi_sdc_id failed\n"); ++ ret = -1; ++ } ++ else ++ { ++ sdc_id = item.val; ++ DBG_871X("----- %s sdc_id: %d, mod_sel: %d\n", __FUNCTION__, sdc_id, mod_sel); ++ wifi_pm_power(1); ++ mdelay(10); ++ sw_mci_rescan_card(sdc_id, 1); ++ DBG_871X("[rtw_sdio] %s: power up, rescan card.\n", __FUNCTION__); ++ } ++#endif //CONFIG_MMC ++ if(ret != 0) ++ goto exit; ++ ++#endif //#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++ ++ DBG_871X_LEVEL(_drv_always_, "module init start version:"DRIVERVERSION"\n"); ++ ++// DBG_871X(KERN_INFO "+%s", __func__); ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+rtw_drv_entry\n")); ++ DBG_871X(DRV_NAME " driver version=%s\n", DRIVERVERSION); ++ DBG_871X("build time: %s %s\n", __DATE__, __TIME__); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++ //console_suspend_enabled=0; ++#endif ++ ++#ifdef CONFIG_PLATFORM_SPRD ++ rtw_wifi_gpio_init(); ++ ++#ifdef ANDROID_2X ++#ifdef CONFIG_RTL8188E ++ rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_ON); ++#endif //CONFIG_RTL8188E ++#endif //ANDROID_2X ++ ++ /* Pull up pwd pin, make wifi leave power down mode. */ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON); ++ ++#if defined(CONFIG_RTL8723A) && (MP_DRIVER == 1) ++ // Pull up BT reset pin. ++ rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON); ++#endif ++ rtw_mdelay_os(5); ++ ++ sdhci_bus_scan(); ++#if (defined ANDROID_2X) ++ rtw_mdelay_os(200); ++#endif //ANDROID_2X ++ ++#endif // CONFIG_PLATFORM_SPRD ++ ++ rtw_suspend_lock_init(); ++ ++ ++ sdio_drvpriv.drv_registered = _TRUE; ++ ++ ret = sdio_register_driver(&sdio_drvpriv.r871xs_drv); ++ ++exit: ++ DBG_871X_LEVEL(_drv_always_, "module init ret=%d\n", ret); ++ ++ rtw_android_wifictrl_func_add(); ++ ++ return ret; ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ DBG_871X_LEVEL(_drv_always_, "module exit start\n"); ++ ++ rtw_android_wifictrl_func_del(); ++ sdio_drvpriv.drv_registered = _FALSE; ++ ++ sdio_unregister_driver(&sdio_drvpriv.r871xs_drv); ++ ++#ifdef CONFIG_PLATFORM_SPRD ++ /* Pull down pwd pin, make wifi enter power down mode. */ ++ rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF); ++ rtw_mdelay_os(5); ++ rtw_wifi_gpio_deinit(); ++ ++#ifdef ANDROID_2X ++#ifdef CONFIG_RTL8188E ++ rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF); ++#endif // CONFIG_RTL8188E ++#endif // ANDROID_2X ++ ++#endif // CONFIG_PLATFORM_SPRD ++ ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++#if defined(CONFIG_MMC_SUNXI_POWER_CONTROL) ++ sunximmc_rescan_card(SDIOID, 0); ++#ifdef CONFIG_RTL8188E ++ rtl8189es_sdio_poweroff(); ++ DBG_8192C("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__); ++#endif //CONFIG_RTL8188E ++#endif //defined(CONFIG_MMC_SUNXI_POWER_CONTROL) ++#endif //CONFIG_PLATFORM_ARM_SUNxI ++ ++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++#ifdef CONFIG_MMC ++ wifi_pm_power(0); ++ sw_mci_rescan_card(sdc_id, 0); ++ printk("[rtl8723as] %s: remove card, power off.\n", __FUNCTION__); ++#endif //CONFIG_MMC ++#endif //#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) ++ rtw_suspend_lock_uninit(); ++ DBG_871X_LEVEL(_drv_always_, "module exit success\n"); ++ ++ rtw_mstat_dump(); ++} ++ ++ ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_ops_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_ops_linux.c +new file mode 100644 +index 00000000..4a107892 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/sdio_ops_linux.c +@@ -0,0 +1,912 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#define _SDIO_OPS_LINUX_C_ ++ ++#include ++ ++#include ++ ++static bool rtw_sdio_claim_host_needed(struct sdio_func *func) ++{ ++ struct dvobj_priv *dvobj = sdio_get_drvdata(func); ++ PSDIO_DATA sdio_data = &dvobj->intf_data; ++ ++ if (sdio_data->sys_sdio_irq_thd && sdio_data->sys_sdio_irq_thd == current) ++ return _FALSE; ++ return _TRUE; ++} ++ ++inline void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl) ++{ ++ PSDIO_DATA sdio_data = &dvobj->intf_data; ++ ++ sdio_data->sys_sdio_irq_thd = thd_hdl; ++} ++ ++u8 sd_f0_read8(struct intf_hdl *pintfhdl,u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u8 v=0; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ v = sdio_f0_readb(func, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); ++ ++_func_exit_; ++ ++ return v; ++} ++ ++void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ sdio_f0_writeb(func, v, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v); ++ ++_func_exit_; ++} ++ ++/* ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ int err=0, i; ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ ++ for (i = 0; i < cnt; i++) { ++ pdata[i] = sdio_readb(func, addr+i, &err); ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr+i); ++ break; ++ } ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++/* ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ int err=0, i; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ err = _sd_cmd52_read(pintfhdl, addr, cnt, pdata); ++ if (claim_needed) ++ sdio_release_host(func); ++ ++_func_exit_; ++ ++ return err; ++} ++ ++/* ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ int err=0, i; ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved)!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ ++ for (i = 0; i < cnt; i++) { ++ sdio_writeb(func, pdata[i], addr+i, &err); ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr+i, pdata[i]); ++ break; ++ } ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++/* ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ int err=0, i; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ err = _sd_cmd52_write(pintfhdl, addr, cnt, pdata); ++ if (claim_needed) ++ sdio_release_host(func); ++ ++_func_exit_; ++ ++ return err; ++} ++ ++u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u8 v=0; ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved)!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ ++ v = sdio_readb(func, addr, err); ++ ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); ++ ++_func_exit_; ++ ++ return v; ++} ++ ++u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u8 v; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ v = sdio_readb(func, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); ++ ++_func_exit_; ++ ++ return v; ++} ++ ++u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u16 v=0; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ v = sdio_readw(func, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); ++ ++_func_exit_; ++ ++ return v; ++} ++ ++u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u32 v=0; ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ ++ v = sdio_readl(func, addr, err); ++ ++ if (err && *err) ++ { ++ int i; ++ ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v); ++ ++ *err = 0; ++ for(i=0; ibSurpriseRemoved = _TRUE; ++ } ++ ++ if(rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ ++ } ++ } ++ ++ if (i==SD_IO_TRY_CNT) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ else ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ ++ } ++ ++_func_exit_; ++ ++ return v; ++} ++ ++u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ u32 v=0; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return v; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ v = sdio_readl(func, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ ++ if (err && *err) ++ { ++ int i; ++ ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v); ++ ++ *err = 0; ++ for(i=0; ibSurpriseRemoved = _TRUE; ++ } ++ ++ if(rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ } ++ } ++ ++ if (i==SD_IO_TRY_CNT) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ else ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ ++ } ++ ++_func_exit_; ++ ++ return v; ++} ++ ++void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return ; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ sdio_writeb(func, v, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v); ++ ++_func_exit_; ++} ++ ++void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return ; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ sdio_writew(func, v, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ if (err && *err) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%04x\n", __func__, *err, addr, v); ++ ++_func_exit_; ++} ++ ++void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return ; ++ } ++ ++ func = psdio->func; ++ ++ sdio_writel(func, v, addr, err); ++ ++ if (err && *err) ++ { ++ int i; ++ ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v); ++ ++ *err = 0; ++ for(i=0; ibSurpriseRemoved = _TRUE; ++ } ++ ++ if(rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ } ++ } ++ ++ if (i==SD_IO_TRY_CNT) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ else ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ ++ } ++ ++_func_exit_; ++} ++ ++void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ struct sdio_func *func; ++ bool claim_needed; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved)!!!\n",__FUNCTION__); ++ return ; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ sdio_writel(func, v, addr, err); ++ if (claim_needed) ++ sdio_release_host(func); ++ ++ if (err && *err) ++ { ++ int i; ++ ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v); ++ ++ *err = 0; ++ for(i=0; ibSurpriseRemoved = _TRUE; ++ } ++ ++ if(rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ } ++ } ++ ++ if (i==SD_IO_TRY_CNT) ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ else ++ DBG_871X(KERN_ERR "%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i); ++ } ++ ++_func_exit_; ++} ++ ++/* ++ * Use CMD53 to read data from SDIO device. ++ * This function MUST be called after sdio_claim_host() or ++ * in SDIO ISR(host had been claimed). ++ * ++ * Parameters: ++ * psdio pointer of SDIO_DATA ++ * addr address to read ++ * cnt amount to read ++ * pdata pointer to put data, this should be a "DMA:able scratch buffer"! ++ * ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ int err= -EPERM; ++ struct sdio_func *func; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ ++ if (unlikely((cnt==1) || (cnt==2))) ++ { ++ int i; ++ u8 *pbuf = (u8*)pdata; ++ ++ for (i = 0; i < cnt; i++) ++ { ++ *(pbuf+i) = sdio_readb(func, addr+i, &err); ++ ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr); ++ break; ++ } ++ } ++ return err; ++ } ++ ++ err = sdio_memcpy_fromio(func, pdata, addr, cnt); ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL(%d)! ADDR=%#x Size=%d\n", __func__, err, addr, cnt); ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++/* ++ * Use CMD53 to read data from SDIO device. ++ * ++ * Parameters: ++ * psdio pointer of SDIO_DATA ++ * addr address to read ++ * cnt amount to read ++ * pdata pointer to put data, this should be a "DMA:able scratch buffer"! ++ * ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 sd_read(struct intf_hdl * pintfhdl, u32 addr, u32 cnt, void *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ bool claim_needed; ++ s32 err= -EPERM; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ err = _sd_read(pintfhdl, addr, cnt, pdata); ++ if (claim_needed) ++ sdio_release_host(func); ++_func_exit_; ++ return err; ++} ++ ++/* ++ * Use CMD53 to write data to SDIO device. ++ * This function MUST be called after sdio_claim_host() or ++ * in SDIO ISR(host had been claimed). ++ * ++ * Parameters: ++ * psdio pointer of SDIO_DATA ++ * addr address to write ++ * cnt amount to write ++ * pdata data pointer, this should be a "DMA:able scratch buffer"! ++ * ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ u32 size; ++ s32 err=-EPERM; ++ ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++// size = sdio_align_size(func, cnt); ++ ++ if (unlikely((cnt==1) || (cnt==2))) ++ { ++ int i; ++ u8 *pbuf = (u8*)pdata; ++ ++ for (i = 0; i < cnt; i++) ++ { ++ sdio_writeb(func, *(pbuf+i), addr+i, &err); ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr, *(pbuf+i)); ++ break; ++ } ++ } ++ ++ return err; ++ } ++ ++ size = cnt; ++ err = sdio_memcpy_toio(func, addr, pdata, size); ++ if (err) { ++ DBG_871X(KERN_ERR "%s: FAIL(%d)! ADDR=%#x Size=%d(%d)\n", __func__, err, addr, cnt, size); ++ } ++ ++_func_exit_; ++ ++ return err; ++} ++ ++/* ++ * Use CMD53 to write data to SDIO device. ++ * ++ * Parameters: ++ * psdio pointer of SDIO_DATA ++ * addr address to write ++ * cnt amount to write ++ * pdata data pointer, this should be a "DMA:able scratch buffer"! ++ * ++ * Return: ++ * 0 Success ++ * others Fail ++ */ ++s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) ++{ ++ PADAPTER padapter; ++ struct dvobj_priv *psdiodev; ++ PSDIO_DATA psdio; ++ ++ struct sdio_func *func; ++ bool claim_needed; ++ s32 err=-EPERM; ++_func_enter_; ++ padapter = pintfhdl->padapter; ++ psdiodev = pintfhdl->pintf_dev; ++ psdio = &psdiodev->intf_data; ++ ++ if(padapter->bSurpriseRemoved){ ++ //DBG_871X(" %s (padapter->bSurpriseRemoved )!!!\n",__FUNCTION__); ++ return err; ++ } ++ ++ func = psdio->func; ++ claim_needed = rtw_sdio_claim_host_needed(func); ++ ++ if (claim_needed) ++ sdio_claim_host(func); ++ err = _sd_write(pintfhdl, addr, cnt, pdata); ++ if (claim_needed) ++ sdio_release_host(func); ++_func_exit_; ++ return err; ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_intf.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_intf.c +new file mode 100644 +index 00000000..d3f6dd2d +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_intf.c +@@ -0,0 +1,2142 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifndef CONFIG_USB_HCI ++ ++#error "CONFIG_USB_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++#include ++#ifdef CONFIG_PLATFORM_RTK_DMP ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifdef CONFIG_80211N_HT ++extern int rtw_ht_enable; ++extern int rtw_cbw40_enable; ++extern int rtw_ampdu_enable;//for enable tx_ampdu ++#endif ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++int ui_pid[3] = {0, 0, 0}; ++#endif ++ ++ ++extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); ++static int rtw_suspend(struct usb_interface *intf, pm_message_t message); ++static int rtw_resume(struct usb_interface *intf); ++int rtw_resume_process(_adapter *padapter); ++ ++ ++static int rtw_drv_init(struct usb_interface *pusb_intf,const struct usb_device_id *pdid); ++static void rtw_dev_remove(struct usb_interface *pusb_intf); ++ ++static void rtw_dev_shutdown(struct device *dev) ++{ ++ struct usb_interface *usb_intf = container_of(dev, struct usb_interface, dev); ++ struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf); ++ _adapter *adapter = dvobj->if1; ++ int i; ++ ++ DBG_871X("%s\n", __func__); ++ ++ for (i = 0; iiface_nums; i++) { ++ adapter = dvobj->padapters[i]; ++ adapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ ATOMIC_SET(&dvobj->continual_io_error, MAX_CONTINUAL_IO_ERR+1); ++} ++ ++#if (LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,23)) ++/* Some useful macros to use to create struct usb_device_id */ ++ #define USB_DEVICE_ID_MATCH_VENDOR 0x0001 ++ #define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 ++ #define USB_DEVICE_ID_MATCH_DEV_LO 0x0004 ++ #define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 ++ #define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010 ++ #define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020 ++ #define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040 ++ #define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 ++ #define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 ++ #define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 ++ #define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400 ++ ++ ++#define USB_DEVICE_ID_MATCH_INT_INFO \ ++ (USB_DEVICE_ID_MATCH_INT_CLASS | \ ++ USB_DEVICE_ID_MATCH_INT_SUBCLASS | \ ++ USB_DEVICE_ID_MATCH_INT_PROTOCOL) ++ ++ ++#define USB_DEVICE_AND_INTERFACE_INFO(vend, prod, cl, sc, pr) \ ++ .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ ++ | USB_DEVICE_ID_MATCH_DEVICE, \ ++ .idVendor = (vend), \ ++ .idProduct = (prod), \ ++ .bInterfaceClass = (cl), \ ++ .bInterfaceSubClass = (sc), \ ++ .bInterfaceProtocol = (pr) ++ ++ /** ++ * USB_VENDOR_AND_INTERFACE_INFO - describe a specific usb vendor with a class of usb interfaces ++ * @vend: the 16 bit USB Vendor ID ++ * @cl: bInterfaceClass value ++ * @sc: bInterfaceSubClass value ++ * @pr: bInterfaceProtocol value ++ * ++ * This macro is used to create a struct usb_device_id that matches a ++ * specific vendor with a specific class of interfaces. ++ * ++ * This is especially useful when explicitly matching devices that have ++ * vendor specific bDeviceClass values, but standards-compliant interfaces. ++ */ ++#define USB_VENDOR_AND_INTERFACE_INFO(vend, cl, sc, pr) \ ++ .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ ++ | USB_DEVICE_ID_MATCH_VENDOR, \ ++ .idVendor = (vend), \ ++ .bInterfaceClass = (cl), \ ++ .bInterfaceSubClass = (sc), \ ++ .bInterfaceProtocol = (pr) ++ ++/* ----------------------------------------------------------------------- */ ++#endif ++ ++#define USB_VENDER_ID_REALTEK 0x0BDA ++ ++/* DID_USB_v916_20130116 */ ++#define RTL8192C_USB_IDS \ ++ /*=== Realtek demoboard ===*/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191)},/* Default ID */ \ ++ /****** 8188CUS ********/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8176)},/* 8188cu 1*1 dongole */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170)},/* 8188CE-VAU USB minCard */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817E)},/* 8188CE-VAU USB minCard */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817A)},/* 8188cu Slim Solo */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817B)},/* 8188cu Slim Combo */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817D)},/* 8188RU High-power USB Dongle */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754)},/* 8188 Combo for BC4 */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817F)},/* 8188RU */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x818A)},/* RTL8188CUS-VL */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x018A)},/* RTL8188CTV */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x17C0)}, /* RTK demoboard - USB-N10E */ \ ++ /****** 8192CUS ********/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177)},/* 8191cu 1*2 */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8178)},/* 8192cu 2*2 */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817C)},/* 8192CE-VAU USB minCard */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191)},/* 8192CU 2*2 */ \ ++ {USB_DEVICE(0x1058, 0x0631)},/* Alpha, 8192CU */ \ ++ /*=== Customer ID ===*/ \ ++ /****** 8188CUS Dongle ********/ \ ++ {USB_DEVICE(0x2019, 0xED17)},/* PCI - Edimax */ \ ++ {USB_DEVICE(0x0DF6, 0x0052)},/* Sitecom - Edimax */ \ ++ {USB_DEVICE(0x7392, 0x7811)},/* Edimax - Edimax */ \ ++ {USB_DEVICE(0x07B8, 0x8189)},/* Abocom - Abocom */ \ ++ {USB_DEVICE(0x0EB0, 0x9071)},/* NO Brand - Etop */ \ ++ {USB_DEVICE(0x06F8, 0xE033)},/* Hercules - Edimax */ \ ++ {USB_DEVICE(0x103C, 0x1629)},/* HP - Lite-On ,8188CUS Slim Combo */ \ ++ {USB_DEVICE(0x2001, 0x3308)},/* D-Link - Alpha */ \ ++ {USB_DEVICE(0x050D, 0x1102)},/* Belkin - Edimax */ \ ++ {USB_DEVICE(0x2019, 0xAB2A)},/* Planex - Abocom */ \ ++ {USB_DEVICE(0x20F4, 0x648B)},/* TRENDnet - Cameo */ \ ++ {USB_DEVICE(0x4855, 0x0090)},/* - Feixun */ \ ++ {USB_DEVICE(0x13D3, 0x3357)},/* - AzureWave */ \ ++ {USB_DEVICE(0x0DF6, 0x005C)},/* Sitecom - Edimax */ \ ++ {USB_DEVICE(0x0BDA, 0x5088)},/* Thinkware - CC&C */ \ ++ {USB_DEVICE(0x4856, 0x0091)},/* NetweeN - Feixun */ \ ++ {USB_DEVICE(0x0846, 0x9041)}, /* Netgear - Cameo */ \ ++ {USB_DEVICE(0x2019, 0x4902)},/* Planex - Etop */ \ ++ {USB_DEVICE(0x2019, 0xAB2E)},/* SW-WF02-AD15 -Abocom */ \ ++ {USB_DEVICE(0x2001, 0x330B)}, /* D-LINK - T&W */ \ ++ {USB_DEVICE(0xCDAB, 0x8010)}, /* - - compare */ \ ++ {USB_DEVICE(0x0B05, 0x17BA)}, /* ASUS - Edimax */ \ ++ {USB_DEVICE(0x0BDA, 0x1E1E)}, /* Intel - - */ \ ++ {USB_DEVICE(0x04BB, 0x094c)}, /* I-O DATA - Edimax */ \ ++ /****** 8188CTV ********/ \ ++ {USB_DEVICE(0xCDAB, 0x8011)}, /* - - compare */ \ ++ {USB_DEVICE(0x0BDA, 0x0A8A)}, /* Sony - Foxconn */ \ ++ /****** 8188 RU ********/ \ ++ {USB_DEVICE(0x0BDA, 0x317F)},/* Netcore,Netcore */ \ ++ /****** 8188CE-VAU ********/ \ ++ {USB_DEVICE(0x13D3, 0x3359)},/* - Azwave */ \ ++ {USB_DEVICE(0x13D3, 0x3358)},/* - Azwave */ \ ++ /****** 8188CUS Slim Solo********/ \ ++ {USB_DEVICE(0x04F2, 0xAFF7)},/* XAVI - XAVI */ \ ++ {USB_DEVICE(0x04F2, 0xAFF9)},/* XAVI - XAVI */ \ ++ {USB_DEVICE(0x04F2, 0xAFFA)},/* XAVI - XAVI */ \ ++ /****** 8188CUS Slim Combo ********/ \ ++ {USB_DEVICE(0x04F2, 0xAFF8)},/* XAVI - XAVI */ \ ++ {USB_DEVICE(0x04F2, 0xAFFB)},/* XAVI - XAVI */ \ ++ {USB_DEVICE(0x04F2, 0xAFFC)},/* XAVI - XAVI */ \ ++ {USB_DEVICE(0x2019, 0x1201)},/* Planex - Vencer */ \ ++ /****** 8192CUS Dongle ********/ \ ++ {USB_DEVICE(0x2001, 0x3307)},/* D-Link - Cameo */ \ ++ {USB_DEVICE(0x2001, 0x330A)},/* D-Link - Alpha */ \ ++ {USB_DEVICE(0x2001, 0x3309)},/* D-Link - Alpha */ \ ++ {USB_DEVICE(0x0586, 0x341F)},/* Zyxel - Abocom */ \ ++ {USB_DEVICE(0x7392, 0x7822)},/* Edimax - Edimax */ \ ++ {USB_DEVICE(0x2019, 0xAB2B)},/* Planex - Abocom */ \ ++ {USB_DEVICE(0x07B8, 0x8178)},/* Abocom - Abocom */ \ ++ {USB_DEVICE(0x07AA, 0x0056)},/* ATKK - Gemtek */ \ ++ {USB_DEVICE(0x4855, 0x0091)},/* - Feixun */ \ ++ {USB_DEVICE(0x050D, 0x2102)},/* Belkin - Sercomm */ \ ++ {USB_DEVICE(0x050D, 0x2103)},/* Belkin - Edimax */ \ ++ {USB_DEVICE(0x20F4, 0x624D)},/* TRENDnet */ \ ++ {USB_DEVICE(0x0DF6, 0x0061)},/* Sitecom - Edimax */ \ ++ {USB_DEVICE(0x0B05, 0x17AB)},/* ASUS - Edimax */ \ ++ {USB_DEVICE(0x0846, 0x9021)},/* Netgear - Sercomm */ \ ++ {USB_DEVICE(0x0846, 0xF001)}, /* Netgear - Sercomm */ \ ++ {USB_DEVICE(0x0E66, 0x0019)},/* Hawking,Edimax */ \ ++ {USB_DEVICE(0x0E66, 0x0020)}, /* Hawking - Edimax */ \ ++ {USB_DEVICE(0x050D, 0x1004)}, /* Belkin - Edimax */ \ ++ {USB_DEVICE(0x0BDA, 0x2E2E)}, /* Intel - - */ \ ++ {USB_DEVICE(0x2357, 0x0100)}, /* TP-Link - TP-Link */ \ ++ {USB_DEVICE(0x06F8, 0xE035)}, /* Hercules - Edimax */ \ ++ {USB_DEVICE(0x04BB, 0x0950)}, /* IO-DATA - Edimax */ \ ++ {USB_DEVICE(0x0DF6, 0x0070)}, /* Sitecom - Edimax */ \ ++ {USB_DEVICE(0x0789, 0x016D)}, /* LOGITEC - Edimax */ \ ++ /****** 8192CE-VAU ********/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8186)},/* Intel-Xavi( Azwave) */ ++ ++#define RTL8192D_USB_IDS \ ++ /*=== Realtek demoboard ===*/ \ ++ /****** 8192DU ********/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8193)},/* 8192DU-VC */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8194)},/* 8192DU-VS */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8111)},/* Realtek 5G dongle for WiFi Display */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0193)},/* 8192DE-VAU */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8171)},/* 8192DU-VC */ \ ++ /*=== Customer ID ===*/ \ ++ /****** 8192DU-VC ********/ \ ++ {USB_DEVICE(0x2019, 0xAB2C)},/* PCI - Abocm */ \ ++ {USB_DEVICE(0x2019, 0x4903)},/* PCI - ETOP */ \ ++ {USB_DEVICE(0x2019, 0x4904)},/* PCI - ETOP */ \ ++ {USB_DEVICE(0x07B8, 0x8193)},/* Abocom - Abocom */ \ ++ /****** 8192DU-VS ********/ \ ++ {USB_DEVICE(0x20F4, 0x664B)}, /* TRENDnet - Cameo */ \ ++ {USB_DEVICE(0x04DD, 0x954F)}, /* Sharp */ \ ++ {USB_DEVICE(0x04DD, 0x96A6)}, /* Sharp */ \ ++ {USB_DEVICE(0x050D, 0x110A)}, /* Belkin - Edimax */ \ ++ {USB_DEVICE(0x050D, 0x1105)}, /* Belkin - Edimax */ \ ++ {USB_DEVICE(0x050D, 0x120A)}, /* Belkin - Edimax */ \ ++ {USB_DEVICE(0x1668, 0x8102)}, /* - */ \ ++ {USB_DEVICE(0x0BDA, 0xE194)}, /* - Edimax */ \ ++ /****** 8192DU-WiFi Display Dongle ********/ \ ++ {USB_DEVICE(0x2019, 0xAB2D)},/* Planex - Abocom ,5G dongle for WiFi Display */ ++ ++#define RTL8723A_USB_IDS \ ++ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x8724,0xff,0xff,0xff)}, /* 8723AU 1*1 */ \ ++ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x1724,0xff,0xff,0xff)}, /* 8723AU 1*1 */ \ ++ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x0724,0xff,0xff,0xff)}, /* 8723AU 1*1 */ ++ ++#define RTL8188E_USB_IDS \ ++ /*=== Realtek demoboard ===*/ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8179)}, /* 8188EUS */ \ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0179)}, /* 8188ETV */ \ ++ /*=== Customer ID ===*/ \ ++ /****** 8188EUS ********/ \ ++ {USB_DEVICE(0x07B8, 0x8179)}, /* Abocom - Abocom */ ++ ++#ifndef CONFIG_RTL8192C ++ #undef RTL8192C_USB_IDS ++ #define RTL8192C_USB_IDS ++#endif ++#ifndef CONFIG_RTL8192D ++ #undef RTL8192D_USB_IDS ++ #define RTL8192D_USB_IDS ++#endif ++#ifndef CONFIG_RTL8723A ++ #undef RTL8723A_USB_IDS ++ #define RTL8723A_USB_IDS ++#endif ++#ifndef CONFIG_RTL8188E ++ #undef RTL8188E_USB_IDS ++ #define RTL8188E_USB_IDS ++#endif ++ ++static struct usb_device_id rtw_usb_id_tbl[] ={ ++ RTL8192C_USB_IDS ++ RTL8192D_USB_IDS ++ RTL8723A_USB_IDS ++ RTL8188E_USB_IDS ++ {} /* Terminating entry */ ++}; ++MODULE_DEVICE_TABLE(usb, rtw_usb_id_tbl); ++ ++int const rtw_usb_id_len = sizeof(rtw_usb_id_tbl) / sizeof(struct usb_device_id); ++ ++static struct specific_device_id specific_device_id_tbl[] = { ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8177, .flags=SPEC_DEV_ID_DISABLE_HT},//8188cu 1*1 dongole, (b/g mode only) ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x817E, .flags=SPEC_DEV_ID_DISABLE_HT},//8188CE-VAU USB minCard (b/g mode only) ++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3359, .flags=SPEC_DEV_ID_DISABLE_HT},//Russian customer -Azwave (8188CE-VAU g mode) ++#ifdef RTK_DMP_PLATFORM ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8111, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // Realtek 5G dongle for WiFi Display ++ {.idVendor=0x2019, .idProduct=0xAB2D, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // PCI-Abocom 5G dongle for WiFi Display ++#endif /* RTK_DMP_PLATFORM */ ++ {} ++}; ++ ++struct rtw_usb_drv { ++ struct usb_driver usbdrv; ++ int drv_registered; ++}; ++ ++#ifdef CONFIG_RTL8192C ++static struct usb_device_id rtl8192c_usb_id_tbl[] ={ ++ RTL8192C_USB_IDS ++ {} /* Terminating entry */ ++}; ++ ++struct rtw_usb_drv rtl8192c_usb_drv = { ++ .usbdrv.name = (char*)"rtl8192cu", ++ .usbdrv.probe = rtw_drv_init, ++ .usbdrv.disconnect = rtw_dev_remove, ++ .usbdrv.id_table = rtl8192c_usb_id_tbl, ++ .usbdrv.suspend = rtw_suspend, ++ .usbdrv.resume = rtw_resume, ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++ .usbdrv.reset_resume = rtw_resume, ++ #endif ++ #ifdef CONFIG_AUTOSUSPEND ++ .usbdrv.supports_autosuspend = 1, ++ #endif ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) ++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown, ++ #else ++ .usbdrv.driver.shutdown = rtw_dev_shutdown, ++ #endif ++}; ++ ++static struct rtw_usb_drv *usb_drv = &rtl8192c_usb_drv; ++#endif /* CONFIG_RTL8192C */ ++ ++#ifdef CONFIG_RTL8192D ++static struct usb_device_id rtl8192d_usb_id_tbl[] ={ ++ RTL8192D_USB_IDS ++ {} /* Terminating entry */ ++}; ++ ++struct rtw_usb_drv rtl8192d_usb_drv = { ++ .usbdrv.name = (char*)"rtl8192du", ++ .usbdrv.probe = rtw_drv_init, ++ .usbdrv.disconnect = rtw_dev_remove, ++ .usbdrv.id_table = rtl8192d_usb_id_tbl, ++ .usbdrv.suspend = rtw_suspend, ++ .usbdrv.resume = rtw_resume, ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++ .usbdrv.reset_resume = rtw_resume, ++ #endif ++ #ifdef CONFIG_AUTOSUSPEND ++ .usbdrv.supports_autosuspend = 1, ++ #endif ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) ++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown, ++ #else ++ .usbdrv.driver.shutdown = rtw_dev_shutdown, ++ #endif ++}; ++static struct rtw_usb_drv *usb_drv = &rtl8192d_usb_drv; ++#endif /* CONFIG_RTL8192D */ ++ ++#ifdef CONFIG_RTL8723A ++static struct usb_device_id rtl8723a_usb_id_tbl[] ={ ++ RTL8723A_USB_IDS ++ {} /* Terminating entry */ ++}; ++ ++struct rtw_usb_drv rtl8723a_usb_drv = { ++ .usbdrv.name = (char*)"rtl8723au", ++ .usbdrv.probe = rtw_drv_init, ++ .usbdrv.disconnect = rtw_dev_remove, ++ .usbdrv.id_table = rtl8723a_usb_id_tbl, ++ .usbdrv.suspend = rtw_suspend, ++ .usbdrv.resume = rtw_resume, ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++ .usbdrv.reset_resume = rtw_resume, ++ #endif ++ #ifdef CONFIG_AUTOSUSPEND ++ .usbdrv.supports_autosuspend = 1, ++ #endif ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) ++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown, ++ #else ++ .usbdrv.driver.shutdown = rtw_dev_shutdown, ++ #endif ++}; ++ ++static struct rtw_usb_drv *usb_drv = &rtl8723a_usb_drv; ++#endif /* CONFIG_RTL8723A */ ++ ++#ifdef CONFIG_RTL8188E ++static struct usb_device_id rtl8188e_usb_id_tbl[] ={ ++ RTL8188E_USB_IDS ++ {} /* Terminating entry */ ++}; ++ ++struct rtw_usb_drv rtl8188e_usb_drv = { ++ .usbdrv.name = (char*)"rtl8188eu", ++ .usbdrv.probe = rtw_drv_init, ++ .usbdrv.disconnect = rtw_dev_remove, ++ .usbdrv.id_table = rtl8188e_usb_id_tbl, ++ .usbdrv.suspend = rtw_suspend, ++ .usbdrv.resume = rtw_resume, ++ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++ .usbdrv.reset_resume = rtw_resume, ++ #endif ++ #ifdef CONFIG_AUTOSUSPEND ++ .usbdrv.supports_autosuspend = 1, ++ #endif ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) ++ .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown, ++ #else ++ .usbdrv.driver.shutdown = rtw_dev_shutdown, ++ #endif ++}; ++ ++static struct rtw_usb_drv *usb_drv = &rtl8188e_usb_drv; ++#endif /* CONFIG_RTL8188E */ ++ ++static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN); ++} ++ ++static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); ++} ++ ++static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT); ++} ++ ++static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK); ++} ++ ++static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_in(epd)); ++} ++ ++static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_out(epd)); ++} ++ ++static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_int(epd) && RT_usb_endpoint_dir_in(epd)); ++} ++ ++static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) ++{ ++ return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; ++} ++ ++static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) ++{ ++ u8 rst = _SUCCESS; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _rtw_mutex_init(&dvobj->usb_vendor_req_mutex); ++ #endif ++ ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ dvobj->usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE); ++ if (dvobj->usb_alloc_vendor_req_buf == NULL) { ++ DBG_871X("alloc usb_vendor_req_buf failed... /n"); ++ rst = _FAIL; ++ goto exit; ++ } ++ dvobj->usb_vendor_req_buf = ++ (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf ), ALIGNMENT_UNIT); ++exit: ++ #endif ++ ++ return rst; ++ ++} ++ ++static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) ++{ ++ u8 rst = _SUCCESS; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ if(dvobj->usb_vendor_req_buf) ++ rtw_mfree(dvobj->usb_alloc_vendor_req_buf, MAX_USB_IO_CTL_SIZE); ++ #endif ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _rtw_mutex_free(&dvobj->usb_vendor_req_mutex); ++ #endif ++ ++ return rst; ++} ++ ++static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf) ++{ ++ int i; ++ u8 val8; ++ int status = _FAIL; ++ struct dvobj_priv *pdvobjpriv; ++ struct usb_device_descriptor *pdev_desc; ++ struct usb_host_config *phost_conf; ++ struct usb_config_descriptor *pconf_desc; ++ struct usb_host_interface *phost_iface; ++ struct usb_interface_descriptor *piface_desc; ++ struct usb_host_endpoint *phost_endp; ++ struct usb_endpoint_descriptor *pendp_desc; ++ struct usb_device *pusbd; ++ ++_func_enter_; ++ ++ if ((pdvobjpriv = (struct dvobj_priv*)rtw_zmalloc(sizeof(*pdvobjpriv))) == NULL) { ++ goto exit; ++ } ++ ++ _rtw_mutex_init(&pdvobjpriv->hw_init_mutex); ++ _rtw_mutex_init(&pdvobjpriv->h2c_fwcmd_mutex); ++ _rtw_mutex_init(&pdvobjpriv->setch_mutex); ++ _rtw_mutex_init(&pdvobjpriv->setbw_mutex); ++ pdvobjpriv->processing_dev_remove = _FALSE; ++ ++ pdvobjpriv->pusbintf = usb_intf ; ++ pusbd = pdvobjpriv->pusbdev = interface_to_usbdev(usb_intf); ++ usb_set_intfdata(usb_intf, pdvobjpriv); ++ ++ pdvobjpriv->RtNumInPipes = 0; ++ pdvobjpriv->RtNumOutPipes = 0; ++ ++ //padapter->EepromAddressSize = 6; ++ //pdvobjpriv->nr_endpoint = 6; ++ ++ pdev_desc = &pusbd->descriptor; ++ ++#if 0 ++ DBG_871X("\n8712_usb_device_descriptor:\n"); ++ DBG_871X("bLength=%x\n", pdev_desc->bLength); ++ DBG_871X("bDescriptorType=%x\n", pdev_desc->bDescriptorType); ++ DBG_871X("bcdUSB=%x\n", pdev_desc->bcdUSB); ++ DBG_871X("bDeviceClass=%x\n", pdev_desc->bDeviceClass); ++ DBG_871X("bDeviceSubClass=%x\n", pdev_desc->bDeviceSubClass); ++ DBG_871X("bDeviceProtocol=%x\n", pdev_desc->bDeviceProtocol); ++ DBG_871X("bMaxPacketSize0=%x\n", pdev_desc->bMaxPacketSize0); ++ DBG_871X("idVendor=%x\n", pdev_desc->idVendor); ++ DBG_871X("idProduct=%x\n", pdev_desc->idProduct); ++ DBG_871X("bcdDevice=%x\n", pdev_desc->bcdDevice); ++ DBG_871X("iManufacturer=%x\n", pdev_desc->iManufacturer); ++ DBG_871X("iProduct=%x\n", pdev_desc->iProduct); ++ DBG_871X("iSerialNumber=%x\n", pdev_desc->iSerialNumber); ++ DBG_871X("bNumConfigurations=%x\n", pdev_desc->bNumConfigurations); ++#endif ++ ++ phost_conf = pusbd->actconfig; ++ pconf_desc = &phost_conf->desc; ++ ++#if 0 ++ DBG_871X("\n8712_usb_configuration_descriptor:\n"); ++ DBG_871X("bLength=%x\n", pconf_desc->bLength); ++ DBG_871X("bDescriptorType=%x\n", pconf_desc->bDescriptorType); ++ DBG_871X("wTotalLength=%x\n", pconf_desc->wTotalLength); ++ DBG_871X("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces); ++ DBG_871X("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue); ++ DBG_871X("iConfiguration=%x\n", pconf_desc->iConfiguration); ++ DBG_871X("bmAttributes=%x\n", pconf_desc->bmAttributes); ++ DBG_871X("bMaxPower=%x\n", pconf_desc->bMaxPower); ++#endif ++ ++ //DBG_871X("\n/****** num of altsetting = (%d) ******/\n", pusb_interface->num_altsetting); ++ ++ phost_iface = &usb_intf->altsetting[0]; ++ piface_desc = &phost_iface->desc; ++ ++#if 0 ++ DBG_871X("\n8712_usb_interface_descriptor:\n"); ++ DBG_871X("bLength=%x\n", piface_desc->bLength); ++ DBG_871X("bDescriptorType=%x\n", piface_desc->bDescriptorType); ++ DBG_871X("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber); ++ DBG_871X("bAlternateSetting=%x\n", piface_desc->bAlternateSetting); ++ DBG_871X("bNumEndpoints=%x\n", piface_desc->bNumEndpoints); ++ DBG_871X("bInterfaceClass=%x\n", piface_desc->bInterfaceClass); ++ DBG_871X("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass); ++ DBG_871X("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol); ++ DBG_871X("iInterface=%x\n", piface_desc->iInterface); ++#endif ++ ++ pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces; ++ pdvobjpriv->InterfaceNumber = piface_desc->bInterfaceNumber; ++ pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints; ++ ++ //DBG_871X("\ndump usb_endpoint_descriptor:\n"); ++ ++ for (i = 0; i < pdvobjpriv->nr_endpoint; i++) ++ { ++ phost_endp = phost_iface->endpoint + i; ++ if (phost_endp) ++ { ++ pendp_desc = &phost_endp->desc; ++ ++ DBG_871X("\nusb_endpoint_descriptor(%d):\n", i); ++ DBG_871X("bLength=%x\n",pendp_desc->bLength); ++ DBG_871X("bDescriptorType=%x\n",pendp_desc->bDescriptorType); ++ DBG_871X("bEndpointAddress=%x\n",pendp_desc->bEndpointAddress); ++ //DBG_871X("bmAttributes=%x\n",pendp_desc->bmAttributes); ++ DBG_871X("wMaxPacketSize=%d\n",le16_to_cpu(pendp_desc->wMaxPacketSize)); ++ DBG_871X("bInterval=%x\n",pendp_desc->bInterval); ++ //DBG_871X("bRefresh=%x\n",pendp_desc->bRefresh); ++ //DBG_871X("bSynchAddress=%x\n",pendp_desc->bSynchAddress); ++ ++ if (RT_usb_endpoint_is_bulk_in(pendp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc)); ++ pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); ++ pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_int_in(pendp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(pendp_desc),pendp_desc->bInterval); ++ pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); ++ pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_bulk_out(pendp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(pendp_desc)); ++ pdvobjpriv->RtOutPipe[pdvobjpriv->RtNumOutPipes] = RT_usb_endpoint_num(pendp_desc); ++ pdvobjpriv->RtNumOutPipes++; ++ } ++ pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc); ++ } ++ } ++ ++ DBG_871X("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); ++ ++ if (pusbd->speed == USB_SPEED_HIGH) { ++ pdvobjpriv->ishighspeed = _TRUE; ++ DBG_871X("USB_SPEED_HIGH\n"); ++ } else { ++ pdvobjpriv->ishighspeed = _FALSE; ++ DBG_871X("NON USB_SPEED_HIGH\n"); ++ } ++ ++ if (rtw_init_intf_priv(pdvobjpriv) == _FAIL) { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't INIT rtw_init_intf_priv\n")); ++ goto free_dvobj; ++ } ++ ++ //.3 misc ++ _rtw_init_sema(&(pdvobjpriv->usb_suspend_sema), 0); ++ rtw_reset_continual_io_error(pdvobjpriv); ++ ++ usb_get_dev(pusbd); ++ ++ status = _SUCCESS; ++ ++free_dvobj: ++ if (status != _SUCCESS && pdvobjpriv) { ++ usb_set_intfdata(usb_intf, NULL); ++ _rtw_mutex_free(&pdvobjpriv->hw_init_mutex); ++ _rtw_mutex_free(&pdvobjpriv->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&pdvobjpriv->setch_mutex); ++ _rtw_mutex_free(&pdvobjpriv->setbw_mutex); ++ rtw_mfree((u8*)pdvobjpriv, sizeof(*pdvobjpriv)); ++ pdvobjpriv = NULL; ++ } ++exit: ++_func_exit_; ++ return pdvobjpriv; ++} ++ ++static void usb_dvobj_deinit(struct usb_interface *usb_intf) ++{ ++ struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf); ++ ++_func_enter_; ++ ++ usb_set_intfdata(usb_intf, NULL); ++ if (dvobj) { ++ //Modify condition for 92DU DMDP 2010.11.18, by Thomas ++ if ((dvobj->NumInterfaces != 2 && dvobj->NumInterfaces != 3) ++ || (dvobj->InterfaceNumber == 1)) { ++ if (interface_to_usbdev(usb_intf)->state != USB_STATE_NOTATTACHED) { ++ //If we didn't unplug usb dongle and remove/insert modlue, driver fails on sitesurvey for the first time when device is up . ++ //Reset usb port for sitesurvey fail issue. 2009.8.13, by Thomas ++ DBG_871X("usb attached..., try to reset usb device\n"); ++ usb_reset_device(interface_to_usbdev(usb_intf)); ++ } ++ } ++ rtw_deinit_intf_priv(dvobj); ++ _rtw_mutex_free(&dvobj->hw_init_mutex); ++ _rtw_mutex_free(&dvobj->h2c_fwcmd_mutex); ++ _rtw_mutex_free(&dvobj->setch_mutex); ++ _rtw_mutex_free(&dvobj->setbw_mutex); ++ rtw_mfree((u8*)dvobj, sizeof(*dvobj)); ++ } ++ ++ //DBG_871X("%s %d\n", __func__, ATOMIC_READ(&usb_intf->dev.kobj.kref.refcount)); ++ usb_put_dev(interface_to_usbdev(usb_intf)); ++ ++_func_exit_; ++} ++ ++static void decide_chip_type_by_usb_device_id(_adapter *padapter, const struct usb_device_id *pdid) ++{ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ hal_set_hw_type(padapter); ++} ++ ++static void usb_intf_start(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_start\n")); ++ ++ rtw_hal_inirp_init(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_start\n")); ++ ++} ++ ++static void usb_intf_stop(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_stop\n")); ++ ++ //disabel_hw_interrupt ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //device still exists, so driver can do i/o operation ++ //TODO: ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("SurpriseRemoved==_FALSE\n")); ++ } ++ ++ //cancel in irp ++ rtw_hal_inirp_deinit(padapter); ++ ++ //cancel out irp ++ rtw_write_port_cancel(padapter); ++ ++ //todo:cancel other irps ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_stop\n")); ++ ++} ++ ++void rtw_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ u8 val8; ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n")); ++ ++ if(padapter->bup == _TRUE) ++ { ++ DBG_871X("===> rtw_dev_unload\n"); ++ ++ padapter->bDriverStopped = _TRUE; ++ #ifdef CONFIG_XMIT_ACK ++ if (padapter->xmitpriv.ack_tx) ++ rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); ++ #endif ++ ++ //s3. ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s4. ++ if(!adapter_to_pwrctl(padapter)->bInternalAutoSuspend ) ++ rtw_stop_drv_threads(padapter); ++ ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //DBG_871X("r871x_dev_unload()->rtl871x_hal_deinit()\n"); ++#ifdef CONFIG_WOWLAN ++ if((adapter_to_pwrctl(padapter)->bSupportRemoteWakeup==_TRUE)&&(adapter_to_pwrctl(padapter)->wowlan_mode==_TRUE)){ ++ DBG_871X("%s bSupportWakeOnWlan==_TRUE do not run rtw_hal_deinit()\n",__FUNCTION__); ++ } ++ else ++#endif //CONFIG_WOWLAN ++ { ++ rtw_hal_deinit(padapter); ++ } ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ padapter->bup = _FALSE; ++#ifdef CONFIG_WOWLAN ++ padapter->hw_init_completed=_FALSE; ++#endif //CONFIG_WOWLAN ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" )); ++ } ++ ++ DBG_871X("<=== rtw_dev_unload\n"); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n")); ++ ++} ++ ++static void process_spec_devid(const struct usb_device_id *pdid) ++{ ++ u16 vid, pid; ++ u32 flags; ++ int i; ++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id); ++ ++ for(i=0; iidVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_DISABLE_HT)) ++ { ++ rtw_ht_enable = 0; ++ rtw_cbw40_enable = 0; ++ rtw_ampdu_enable = 0; ++ } ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ // Change the ifname to wlan10 when PC side WFD dongle plugin on DMP platform. ++ // It is used to distinguish between normal and PC-side wifi dongle/module. ++ if((pdid->idVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_ASSIGN_IFNAME)) ++ { ++ extern char* ifname; ++ strncpy(ifname, "wlan10", 6); ++ //DBG_871X("%s()-%d: ifname=%s, vid=%04X, pid=%04X\n", __FUNCTION__, __LINE__, ifname, vid, pid); ++ } ++#endif /* RTK_DMP_PLATFORM */ ++ ++ } ++} ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++int rtw_hw_suspend(_adapter *padapter ) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++ _func_enter_; ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", ++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto error_exit; ++ } ++ ++ if(padapter)//system suspend ++ { ++ LeaveAllPowerSaveMode(padapter); ++ ++ DBG_871X("==> rtw_hw_suspend\n"); ++ _enter_pwrlock(&pwrpriv->lock); ++ pwrpriv->bips_processing = _TRUE; ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++ //s2. ++ rtw_disassoc_cmd(padapter, 500, _FALSE); ++ ++ //s2-2. indicate disconnect to os ++ //rtw_indicate_disconnect(padapter); ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ { ++ _clr_fwstate_(pmlmepriv, _FW_LINKED); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ rtw_os_indicate_disconnect(padapter); ++ ++ #ifdef CONFIG_LPS ++ //donnot enqueue cmd ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0); ++ #endif ++ } ++ ++ } ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter,_TRUE); ++ #ifdef CONFIG_IPS ++ rtw_ips_dev_unload(padapter); ++ #endif ++ pwrpriv->rf_pwrstate = rf_off; ++ pwrpriv->bips_processing = _FALSE; ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ } ++ else ++ goto error_exit; ++ ++ _func_exit_; ++ return 0; ++ ++error_exit: ++ DBG_871X("%s, failed \n",__FUNCTION__); ++ return (-1); ++ ++} ++ ++int rtw_hw_resume(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++ _func_enter_; ++ ++ if(padapter)//system resume ++ { ++ DBG_871X("==> rtw_hw_resume\n"); ++ _enter_pwrlock(&pwrpriv->lock); ++ pwrpriv->bips_processing = _TRUE; ++ rtw_reset_drv_sw(padapter); ++ ++ if(pm_netdev_open(pnetdev,_FALSE) != 0) ++ { ++ _exit_pwrlock(&pwrpriv->lock); ++ goto error_exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ ++ if(!rtw_netif_queue_stopped(pnetdev)) ++ rtw_netif_start_queue(pnetdev); ++ else ++ rtw_netif_wake_queue(pnetdev); ++ ++ pwrpriv->bkeepfwalive = _FALSE; ++ pwrpriv->brfoffbyhw = _FALSE; ++ ++ pwrpriv->rf_pwrstate = rf_on; ++ pwrpriv->bips_processing = _FALSE; ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ } ++ else ++ { ++ goto error_exit; ++ } ++ ++ _func_exit_; ++ ++ return 0; ++error_exit: ++ DBG_871X("%s, Open net dev failed \n",__FUNCTION__); ++ return (-1); ++} ++#endif ++ ++#if 1 ++#ifdef CONFIG_WOWLAN ++static void rtw_suspend_wow(_adapter *padapter) ++{ ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++ struct wowlan_ioctl_param poidparam; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) ++ pwrpriv->wowlan_mode = _TRUE; ++ else ++ pwrpriv->wowlan_mode = _FALSE; ++ ++ rtw_cancel_all_timer(padapter); ++ LeaveAllPowerSaveMode(padapter); ++ ++ rtw_stop_cmd_thread(padapter); ++ ++ ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++ if(pwrpriv->bSupportRemoteWakeup==_TRUE && pwrpriv->wowlan_mode==_TRUE){ ++ //set H2C command ++ poidparam.subcode=WOWLAN_ENABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ } ++ else ++ { ++ //s2. ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++ } ++ ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)&& rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ //DBG_871X("%s:%d assoc_ssid:%s\n", __FUNCTION__, __LINE__, pmlmepriv->assoc_ssid.Ssid); ++ DBG_871X("%s:%d %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, __LINE__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ ++ rtw_set_roaming(padapter, 1); ++ } ++#endif ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++#ifdef CONFIG_AUTOSUSPEND ++ if(!pwrpriv->bInternalAutoSuspend ) ++#endif ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_dev_unload(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ //if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ // rtw_indicate_disconnect(padapter); ++ ++} ++#endif ++static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) ++{ ++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); ++ _adapter *padapter = dvobj->if1; ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); ++ struct usb_device *usb_dev = interface_to_usbdev(pusb_intf); ++ ++ ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ ++#ifdef CONFIG_IOL_READ_EFUSE_MAP ++ if(!padapter->bup){ ++ u8 bMacPwrCtrlOn = _FALSE; ++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); ++ if(bMacPwrCtrlOn) ++ rtw_hal_power_off(padapter); ++ } ++#endif ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", ++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto exit; ++ } ++ ++ if(pwrpriv->bInternalAutoSuspend ) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ // The FW command register update must after MAC and FW init ready. ++ if((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable )) ++ { ++ u8 bOpen = _TRUE; ++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); ++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_TRUE ,500);//note fw to support hw power down ping detect ++ } ++ #endif ++ #endif ++ } ++ ++ pwrpriv->bInSuspend = _TRUE; ++ ++ _enter_pwrlock(&pwrpriv->lock); ++#ifdef CONFIG_WOWLAN ++ rtw_suspend_wow(padapter); ++#else ++ rtw_suspend_common(padapter); ++#endif ++ ++#ifdef CONFIG_AUTOSUSPEND ++ pwrpriv->rf_pwrstate = rf_off; ++ pwrpriv->bips_processing = _FALSE; ++#endif ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ ++exit: ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ return ret; ++} ++#else ++static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) ++{ ++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); ++ _adapter *padapter = dvobj->if1; ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); ++ struct usb_device *usb_dev = interface_to_usbdev(pusb_intf); ++#ifdef CONFIG_WOWLAN ++ struct wowlan_ioctl_param poidparam; ++#endif // CONFIG_WOWLAN ++ ++ int ret = 0; ++ u32 start_time = rtw_get_current_time(); ++ ++ _func_enter_; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++#ifdef CONFIG_WOWLAN ++ if (check_fwstate(pmlmepriv, _FW_LINKED)) ++ pwrpriv->wowlan_mode = _TRUE; ++ else ++ pwrpriv->wowlan_mode = _FALSE; ++#endif ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_871X("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", ++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto exit; ++ } ++ ++ if(pwrpriv->bInternalAutoSuspend ) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ // The FW command register update must after MAC and FW init ready. ++ if((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable )) ++ { ++ u8 bOpen = _TRUE; ++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); ++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_TRUE ,500);//note fw to support hw power down ping detect ++ } ++ #endif ++ #endif ++ } ++ pwrpriv->bInSuspend = _TRUE; ++ rtw_cancel_all_timer(padapter); ++ LeaveAllPowerSaveMode(padapter); ++ ++ rtw_stop_cmd_thread(padapter); ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ rtw_netif_stop_queue(pnetdev); ++ } ++ ++#ifdef CONFIG_WOWLAN ++ if(pwrpriv->bSupportRemoteWakeup==_TRUE && pwrpriv->wowlan_mode==_TRUE){ ++ //set H2C command ++ poidparam.subcode=WOWLAN_ENABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ } ++ else ++#else ++ { ++ //s2. ++ rtw_disassoc_cmd(padapter, 0, _FALSE); ++ } ++#endif //CONFIG_WOWLAN ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ //DBG_871X("%s:%d assoc_ssid:%s\n", __FUNCTION__, __LINE__, pmlmepriv->assoc_ssid.Ssid); ++ DBG_871X("%s:%d %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, __LINE__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ ++ rtw_set_roaming(padapter, 1); ++ } ++#endif ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++#ifdef CONFIG_AUTOSUSPEND ++ if(!pwrpriv->bInternalAutoSuspend ) ++#endif ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_dev_unload(padapter); ++#ifdef CONFIG_AUTOSUSPEND ++ pwrpriv->rf_pwrstate = rf_off; ++ pwrpriv->bips_processing = _FALSE; ++#endif ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ rtw_indicate_disconnect(padapter); ++ ++exit: ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ return ret; ++} ++ ++#endif ++static int rtw_resume(struct usb_interface *pusb_intf) ++{ ++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); ++ _adapter *padapter = dvobj->if1; ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); ++ int ret = 0; ++ ++ if(pwrpriv->bInternalAutoSuspend ){ ++ ret = rtw_resume_process(padapter); ++ } else { ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_resume_in_workqueue(pwrpriv); ++#else ++ if (rtw_is_earlysuspend_registered(pwrpriv) ++ #ifdef CONFIG_WOWLAN ++ && !pwrpriv->wowlan_mode ++ #endif /* CONFIG_WOWLAN */ ++ ) { ++ /* jeff: bypass resume here, do in late_resume */ ++ rtw_set_do_late_resume(pwrpriv, _TRUE); ++ } else { ++ ret = rtw_resume_process(padapter); ++ } ++#endif /* CONFIG_RESUME_IN_WORKQUEUE */ ++ } ++ ++ return ret; ++ ++} ++ ++int rtw_resume_process(_adapter *padapter) ++{ ++ struct net_device *pnetdev; ++ struct pwrctrl_priv *pwrpriv; ++ int ret = -1; ++ u32 start_time = rtw_get_current_time(); ++#ifdef CONFIG_BT_COEXIST ++ u8 pm_cnt; ++#endif //#ifdef CONFIG_BT_COEXIST ++ _func_enter_; ++ ++ DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if(padapter) { ++ pnetdev= padapter->pnetdev; ++ pwrpriv = adapter_to_pwrctl(padapter); ++ } else { ++ goto exit; ++ } ++ ++ _enter_pwrlock(&pwrpriv->lock); ++#ifdef CONFIG_BT_COEXIST ++#ifdef CONFIG_AUTOSUSPEND ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_871X("%s...pm_usage_cnt(%d) pwrpriv->bAutoResume=%x. ....\n",__func__,atomic_read(&(adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt)),pwrpriv->bAutoResume); ++ pm_cnt=atomic_read(&(adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt)); ++ #else ++ DBG_871X("...pm_usage_cnt(%d).....\n", adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt); ++ pm_cnt = adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt; ++ #endif ++ ++ DBG_871X("pwrpriv->bAutoResume (%x)\n",pwrpriv->bAutoResume ); ++ if( _TRUE == pwrpriv->bAutoResume ){ ++ pwrpriv->bInternalAutoSuspend = _FALSE; ++ pwrpriv->bAutoResume=_FALSE; ++ DBG_871X("pwrpriv->bAutoResume (%x) pwrpriv->bInternalAutoSuspend(%x)\n",pwrpriv->bAutoResume,pwrpriv->bInternalAutoSuspend ); ++ ++ } ++#endif //#ifdef CONFIG_AUTOSUSPEND ++#endif //#ifdef CONFIG_BT_COEXIST ++ ++ ++ if(rtw_resume_common(padapter)!= 0) { ++ DBG_871X("%s rtw_resume_common failed\n",__FUNCTION__); ++ _exit_pwrlock(&pwrpriv->lock); ++ goto exit; ++ } ++ ++#ifdef CONFIG_AUTOSUSPEND ++ if(pwrpriv->bInternalAutoSuspend ) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ // The FW command register update must after MAC and FW init ready. ++ if((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable )) ++ { ++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_FALSE ,500);//note fw to support hw power down ping detect ++ u8 bOpen = _FALSE; ++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); ++ } ++ #endif ++ #endif ++#ifdef CONFIG_BT_COEXIST ++ DBG_871X("pwrpriv->bAutoResume (%x)\n",pwrpriv->bAutoResume ); ++ if( _TRUE == pwrpriv->bAutoResume ){ ++ pwrpriv->bInternalAutoSuspend = _FALSE; ++ pwrpriv->bAutoResume=_FALSE; ++ DBG_871X("pwrpriv->bAutoResume (%x) pwrpriv->bInternalAutoSuspend(%x)\n",pwrpriv->bAutoResume,pwrpriv->bInternalAutoSuspend ); ++ } ++ ++#else //#ifdef CONFIG_BT_COEXIST ++ pwrpriv->bInternalAutoSuspend = _FALSE; ++#endif //#ifdef CONFIG_BT_COEXIST ++ pwrpriv->brfoffbyhw = _FALSE; ++ } ++#endif ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ if( padapter->pid[1]!=0) { ++ DBG_871X("pid[1]:%d\n",padapter->pid[1]); ++ rtw_signal_process(padapter->pid[1], SIGUSR2); ++ } ++ ++ ret = 0; ++exit: ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++ pwrpriv->bInSuspend = _FALSE; ++ DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ ++ , ret, rtw_get_passing_time_ms(start_time)); ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++#ifdef CONFIG_AUTOSUSPEND ++void autosuspend_enter(_adapter* padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); ++ ++ DBG_871X("==>autosuspend_enter...........\n"); ++ ++ pwrpriv->bInternalAutoSuspend = _TRUE; ++ pwrpriv->bips_processing = _TRUE; ++ ++ if(rf_off == pwrpriv->change_rfpwrstate ) ++ { ++#ifndef CONFIG_BT_COEXIST ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_enable_autosuspend(dvobj->pusbdev); ++ #else ++ dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ usb_autopm_put_interface(dvobj->pusbintf); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_enable(dvobj->pusbintf); ++ #else ++ usb_autosuspend_device(dvobj->pusbdev, 1); ++ #endif ++#else //#ifndef CONFIG_BT_COEXIST ++ if(1==pwrpriv->autopm_cnt){ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_enable_autosuspend(dvobj->pusbdev); ++ #else ++ dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ usb_autopm_put_interface(dvobj->pusbintf); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_enable(dvobj->pusbintf); ++ #else ++ usb_autosuspend_device(dvobj->pusbdev, 1); ++ #endif ++ pwrpriv->autopm_cnt --; ++ } ++ else ++ DBG_871X("0!=pwrpriv->autopm_cnt[%d] didn't usb_autopm_put_interface\n", pwrpriv->autopm_cnt); ++ ++#endif //#ifndef CONFIG_BT_COEXIST ++ } ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); ++ #else ++ DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); ++ #endif ++ ++} ++int autoresume_enter(_adapter* padapter) ++{ ++ int result = _SUCCESS; ++ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); ++ ++ DBG_871X("====> autoresume_enter \n"); ++ ++ if(rf_off == pwrpriv->rf_pwrstate ) ++ { ++ pwrpriv->ps_flag = _FALSE; ++#ifndef CONFIG_BT_COEXIST ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ if (usb_autopm_get_interface(dvobj->pusbintf) < 0) ++ { ++ DBG_871X( "can't get autopm: %d\n", result); ++ result = _FAIL; ++ goto error_exit; ++ } ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_disable(dvobj->pusbintf); ++ #else ++ usb_autoresume_device(dvobj->pusbdev, 1); ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); ++ #else ++ DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); ++ #endif ++#else //#ifndef CONFIG_BT_COEXIST ++ pwrpriv->bAutoResume=_TRUE; ++ if(0==pwrpriv->autopm_cnt){ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ if (usb_autopm_get_interface(dvobj->pusbintf) < 0) ++ { ++ DBG_871X( "can't get autopm: %d\n", result); ++ result = _FAIL; ++ goto error_exit; ++ } ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_disable(dvobj->pusbintf); ++ #else ++ usb_autoresume_device(dvobj->pusbdev, 1); ++ #endif ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); ++ #else ++ DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); ++ #endif ++ pwrpriv->autopm_cnt++; ++ } ++ else ++ DBG_871X("0!=pwrpriv->autopm_cnt[%d] didn't usb_autopm_get_interface\n",pwrpriv->autopm_cnt); ++#endif //#ifndef CONFIG_BT_COEXIST ++ } ++ DBG_871X("<==== autoresume_enter \n"); ++error_exit: ++ ++ return result; ++} ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++extern void rtd2885_wlan_netlink_sendMsg(char *action_string, char *name); ++#endif ++ ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++#include ++extern int sw_usb_disable_hcd(__u32 usbc_no); ++extern int sw_usb_enable_hcd(__u32 usbc_no); ++static int usb_wifi_host = 2; ++#endif ++ ++#ifdef CONFIG_PLATFORM_ARM_SUN6I ++#include ++extern int sw_usb_disable_hcd(__u32 usbc_no); ++extern int sw_usb_enable_hcd(__u32 usbc_no); ++extern void wifi_pm_power(int on); ++static script_item_u item; ++#endif ++ ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++*/ ++ ++_adapter *rtw_sw_export = NULL; ++ ++_adapter *rtw_usb_if1_init(struct dvobj_priv *dvobj, ++ struct usb_interface *pusb_intf, const struct usb_device_id *pdid) ++{ ++ _adapter *padapter = NULL; ++ struct net_device *pnetdev = NULL; ++ int status = _FAIL; ++ ++ if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) { ++ goto exit; ++ } ++ padapter->dvobj = dvobj; ++ dvobj->if1 = padapter; ++ ++ padapter->bDriverStopped=_TRUE; ++ ++ dvobj->padapters[dvobj->iface_nums++] = padapter; ++ padapter->iface_id = IFACE_ID0; ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) ++ //set adapter_type/iface type for primary padapter ++ padapter->isprimary = _TRUE; ++ padapter->adapter_type = PRIMARY_ADAPTER; ++ #ifndef CONFIG_HWPORT_SWAP ++ padapter->iface_type = IFACE_PORT0; ++ #else ++ padapter->iface_type = IFACE_PORT1; ++ #endif ++#endif ++ ++ #ifndef RTW_DVOBJ_CHIP_HW_TYPE ++ //step 1-1., decide the chip_type via vid/pid ++ padapter->interface_type = RTW_USB; ++ decide_chip_type_by_usb_device_id(padapter, pdid); ++ #endif ++ ++ if (rtw_handle_dualmac(padapter, 1) != _SUCCESS) ++ goto free_adapter; ++ ++ if((pnetdev = rtw_init_netdev(padapter)) == NULL) { ++ goto handle_dualmac; ++ } ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj)); ++ padapter = rtw_netdev_priv(pnetdev); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)) != 0) { ++ goto handle_dualmac; ++ } ++#endif ++ ++ ++ //step 2. hook HalFunc, allocate HalData ++ hal_set_hal_ops(padapter); ++ ++ padapter->intf_start=&usb_intf_start; ++ padapter->intf_stop=&usb_intf_stop; ++ ++ //step init_io_priv ++ rtw_init_io_priv(padapter, usb_set_intf_ops); ++ ++ //step read_chip_version ++ rtw_hal_read_chip_version(padapter); ++ ++ //step usb endpoint mapping ++ rtw_hal_chip_configure(padapter); ++ ++ //step read efuse/eeprom data and get mac_addr ++ rtw_hal_read_chip_info(padapter); ++ ++ //step 5. ++ if(rtw_init_drv_sw(padapter) ==_FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto free_hal_data; ++ } ++ ++#ifdef CONFIG_PM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ if(adapter_to_pwrctl(padapter)->bSupportRemoteWakeup) ++ { ++ dvobj->pusbdev->do_remote_wakeup=1; ++ pusb_intf->needs_remote_wakeup = 1; ++ device_init_wakeup(&pusb_intf->dev, 1); ++ DBG_871X("\n pwrctrlpriv.bSupportRemoteWakeup~~~~~~\n"); ++ DBG_871X("\n pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n",device_may_wakeup(&pusb_intf->dev)); ++ } ++#endif ++#endif ++ ++#ifdef CONFIG_AUTOSUSPEND ++ if( padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE ) ++ { ++ if(padapter->registrypriv.usbss_enable ){ /* autosuspend (2s delay) */ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38)) ++ dvobj->pusbdev->dev.power.autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time ++ #else ++ dvobj->pusbdev->autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_enable_autosuspend(dvobj->pusbdev); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ padapter->bDisableAutosuspend = dvobj->pusbdev->autosuspend_disabled ; ++ dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user ++ #endif ++ ++ //usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf );//init pm_usage_cnt ,let it start from 1 ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,atomic_read(&(dvobj->pusbintf ->pm_usage_cnt))); ++ #else ++ DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,dvobj->pusbintf ->pm_usage_cnt); ++ #endif ++ } ++ } ++#endif ++ //2012-07-11 Move here to prevent the 8723AS-VAU BT auto suspend influence ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ if (usb_autopm_get_interface(pusb_intf) < 0) ++ { ++ DBG_871X( "can't get autopm: \n"); ++ } ++ #endif ++#ifdef CONFIG_BT_COEXIST ++ adapter_to_pwrctl(padapter)->autopm_cnt=1; ++#endif ++ ++ // set mac addr ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++ rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr); ++ ++ DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n" ++ , padapter->bDriverStopped ++ , padapter->bSurpriseRemoved ++ , padapter->bup ++ , padapter->hw_init_completed ++ ); ++ ++ status = _SUCCESS; ++ ++free_hal_data: ++ if(status != _SUCCESS && padapter->HalData) ++ rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData))); ++free_wdev: ++ if(status != _SUCCESS) { ++ #ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_unregister(padapter->rtw_wdev); ++ rtw_wdev_free(padapter->rtw_wdev); ++ #endif ++ } ++handle_dualmac: ++ if (status != _SUCCESS) ++ rtw_handle_dualmac(padapter, 0); ++free_adapter: ++ if (status != _SUCCESS) { ++ if (pnetdev) ++ rtw_free_netdev(pnetdev); ++ else if (padapter) ++ rtw_vmfree((u8*)padapter, sizeof(*padapter)); ++ padapter = NULL; ++ } ++exit: ++ return padapter; ++} ++ ++static void rtw_usb_if1_deinit(_adapter *if1) ++{ ++ struct net_device *pnetdev = if1->pnetdev; ++ struct mlme_priv *pmlmepriv= &if1->mlmepriv; ++ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(if1); ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ rtw_disassoc_cmd(if1, 0, _FALSE); ++ ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(if1); ++ #ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(if1); ++ #endif ++#endif ++/* ++ if(if1->DriverState != DRIVER_DISAPPEAR) { ++ if(pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++ rtw_proc_remove_one(pnetdev); ++ } ++ } ++*/ ++ rtw_cancel_all_timer(if1); ++ ++#ifdef CONFIG_WOWLAN ++ pwrctl->wowlan_mode=_FALSE; ++#endif //CONFIG_WOWLAN ++ ++ rtw_dev_unload(if1); ++ ++ DBG_871X("+r871xu_dev_remove, hw_init_completed=%d\n", if1->hw_init_completed); ++ ++ rtw_handle_dualmac(if1, 0); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(if1->rtw_wdev) ++ { ++ //rtw_wdev_unregister(if1->rtw_wdev); ++ rtw_wdev_free(if1->rtw_wdev); ++ } ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++ if(1 == pwrctl->autopm_cnt){ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ usb_autopm_put_interface(adapter_to_dvobj(if1)->pusbintf); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_enable(adapter_to_dvobj(if1)->pusbintf); ++ #else ++ usb_autosuspend_device(adapter_to_dvobj(if1)->pusbdev, 1); ++ #endif ++ pwrctl->autopm_cnt --; ++ } ++#endif ++ ++ rtw_free_drv_sw(if1); ++ ++ if(pnetdev) ++ rtw_free_netdev(pnetdev); ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link down\n"); ++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); ++#endif ++ ++} ++ ++static void dump_usb_interface(struct usb_interface *usb_intf) ++{ ++ int i; ++ u8 val8; ++ ++ struct usb_device *udev = interface_to_usbdev(usb_intf); ++ struct usb_device_descriptor *dev_desc = &udev->descriptor; ++ ++ struct usb_host_config *act_conf = udev->actconfig; ++ struct usb_config_descriptor *act_conf_desc = &act_conf->desc; ++ ++ struct usb_host_interface *host_iface; ++ struct usb_interface_descriptor *iface_desc; ++ struct usb_host_endpoint *host_endp; ++ struct usb_endpoint_descriptor *endp_desc; ++ ++#if 1 /* The usb device this usb interface belongs to */ ++ DBG_871X("usb_interface:%p, usb_device:%p(num:%d, path:%s), usb_device_descriptor:%p\n", usb_intf, udev, udev->devnum, udev->devpath, dev_desc); ++ DBG_871X("bLength:%u\n", dev_desc->bLength); ++ DBG_871X("bDescriptorType:0x%02x\n", dev_desc->bDescriptorType); ++ DBG_871X("bcdUSB:0x%04x\n", le16_to_cpu(dev_desc->bcdUSB)); ++ DBG_871X("bDeviceClass:0x%02x\n", dev_desc->bDeviceClass); ++ DBG_871X("bDeviceSubClass:0x%02x\n", dev_desc->bDeviceSubClass); ++ DBG_871X("bDeviceProtocol:0x%02x\n", dev_desc->bDeviceProtocol); ++ DBG_871X("bMaxPacketSize0:%u\n", dev_desc->bMaxPacketSize0); ++ DBG_871X("idVendor:0x%04x\n", le16_to_cpu(dev_desc->idVendor)); ++ DBG_871X("idProduct:0x%04x\n", le16_to_cpu(dev_desc->idProduct)); ++ DBG_871X("bcdDevice:0x%04x\n", le16_to_cpu(dev_desc->bcdDevice)); ++ DBG_871X("iManufacturer:0x02%x\n", dev_desc->iManufacturer); ++ DBG_871X("iProduct:0x%02x\n", dev_desc->iProduct); ++ DBG_871X("iSerialNumber:0x%02x\n", dev_desc->iSerialNumber); ++ DBG_871X("bNumConfigurations:%u\n", dev_desc->bNumConfigurations); ++#endif ++ ++ ++#if 1 /* The acting usb_config_descriptor */ ++ DBG_871X("\nact_conf_desc:%p\n", act_conf_desc); ++ DBG_871X("bLength:%u\n", act_conf_desc->bLength); ++ DBG_871X("bDescriptorType:0x%02x\n", act_conf_desc->bDescriptorType); ++ DBG_871X("wTotalLength:%u\n", le16_to_cpu(act_conf_desc->wTotalLength)); ++ DBG_871X("bNumInterfaces:%u\n", act_conf_desc->bNumInterfaces); ++ DBG_871X("bConfigurationValue:0x%02x\n", act_conf_desc->bConfigurationValue); ++ DBG_871X("iConfiguration:0x%02x\n", act_conf_desc->iConfiguration); ++ DBG_871X("bmAttributes:0x%02x\n", act_conf_desc->bmAttributes); ++ DBG_871X("bMaxPower=%u\n", act_conf_desc->bMaxPower); ++#endif ++ ++ ++ DBG_871X("****** num of altsetting = (%d) ******/\n", usb_intf->num_altsetting); ++ /* Get he host side alternate setting (the current alternate setting) for this interface*/ ++ host_iface = usb_intf->cur_altsetting; ++ iface_desc = &host_iface->desc; ++ ++#if 1 /* The current alternate setting*/ ++ DBG_871X("\nusb_interface_descriptor:%p:\n", iface_desc); ++ DBG_871X("bLength:%u\n", iface_desc->bLength); ++ DBG_871X("bDescriptorType:0x%02x\n", iface_desc->bDescriptorType); ++ DBG_871X("bInterfaceNumber:0x%02x\n", iface_desc->bInterfaceNumber); ++ DBG_871X("bAlternateSetting=%x\n", iface_desc->bAlternateSetting); ++ DBG_871X("bNumEndpoints=%x\n", iface_desc->bNumEndpoints); ++ DBG_871X("bInterfaceClass=%x\n", iface_desc->bInterfaceClass); ++ DBG_871X("bInterfaceSubClass=%x\n", iface_desc->bInterfaceSubClass); ++ DBG_871X("bInterfaceProtocol=%x\n", iface_desc->bInterfaceProtocol); ++ DBG_871X("iInterface=%x\n", iface_desc->iInterface); ++#endif ++ ++ ++#if 1 ++ //DBG_871X("\ndump usb_endpoint_descriptor:\n"); ++ ++ for (i = 0; i < iface_desc->bNumEndpoints; i++) ++ { ++ host_endp = host_iface->endpoint + i; ++ if (host_endp) ++ { ++ endp_desc = &host_endp->desc; ++ ++ DBG_871X("\nusb_endpoint_descriptor(%d):\n", i); ++ DBG_871X("bLength=%x\n",endp_desc->bLength); ++ DBG_871X("bDescriptorType=%x\n",endp_desc->bDescriptorType); ++ DBG_871X("bEndpointAddress=%x\n",endp_desc->bEndpointAddress); ++ DBG_871X("bmAttributes=%x\n",endp_desc->bmAttributes); ++ DBG_871X("wMaxPacketSize=%x\n",endp_desc->wMaxPacketSize); ++ DBG_871X("wMaxPacketSize=%x\n",le16_to_cpu(endp_desc->wMaxPacketSize)); ++ DBG_871X("bInterval=%x\n",endp_desc->bInterval); ++ //DBG_871X("bRefresh=%x\n",pendp_desc->bRefresh); ++ //DBG_871X("bSynchAddress=%x\n",pendp_desc->bSynchAddress); ++ ++ if (RT_usb_endpoint_is_bulk_in(endp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(endp_desc)); ++ //pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_int_in(endp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(endp_desc),endp_desc->bInterval); ++ //pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_bulk_out(endp_desc)) ++ { ++ DBG_871X("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(endp_desc)); ++ //pdvobjpriv->RtNumOutPipes++; ++ } ++ //pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc); ++ } ++ } ++ ++ //DBG_871X("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); ++#endif ++ ++ if (udev->speed == USB_SPEED_HIGH) ++ DBG_871X("USB_SPEED_HIGH\n"); ++ else ++ DBG_871X("NON USB_SPEED_HIGH\n"); ++ ++} ++ ++ ++static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) ++{ ++ int i; ++ _adapter *if1 = NULL, *if2 = NULL; ++ int status; ++ struct dvobj_priv *dvobj; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); ++ //DBG_871X("+rtw_drv_init\n"); ++ ++ //step 0. ++ process_spec_devid(pdid); ++ ++ /* Initialize dvobj_priv */ ++ if ((dvobj = usb_dvobj_init(pusb_intf)) == NULL) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); ++ goto exit; ++ } ++ ++ #ifdef RTW_DVOBJ_CHIP_HW_TYPE ++ decide_chip_type_by_usb_device_id(dvobj, pdid); ++ #endif ++ ++ if ((if1 = rtw_usb_if1_init(dvobj, pusb_intf, pdid)) == NULL) { ++ DBG_871X("rtw_init_primary_adapter Failed!\n"); ++ goto free_dvobj; ++ } ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if((if2 = rtw_drv_if2_init(if1, usb_set_intf_ops)) == NULL) { ++ goto free_if1; ++ } ++#endif ++ ++#ifdef CONFIG_INTEL_PROXIM ++ rtw_sw_export=if1; ++#endif ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++ if(ui_pid[1]!=0) { ++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]); ++ rtw_signal_process(ui_pid[1], SIGUSR2); ++ } ++#endif ++ ++ //dev_alloc_name && register_netdev ++ if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) { ++ goto free_if2; ++ } ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(if1); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_871X("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(if1->pnetdev); ++#endif ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ ++ status = _SUCCESS; ++ ++free_if2: ++ if(status != _SUCCESS && if2) { ++ #ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(if2); ++ rtw_drv_if2_free(if2); ++ #endif ++ } ++free_if1: ++ if (status != _SUCCESS && if1) { ++ rtw_usb_if1_deinit(if1); ++ } ++free_dvobj: ++ if (status != _SUCCESS) ++ usb_dvobj_deinit(pusb_intf); ++exit: ++ return status == _SUCCESS?0:-ENODEV; ++} ++extern void rtw_unregister_netdevs(struct dvobj_priv *dvobj); ++/* ++ * dev_remove() - our device is being removed ++*/ ++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both ++static void rtw_dev_remove(struct usb_interface *pusb_intf) ++{ ++ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); ++ _adapter *padapter = dvobj->if1; ++ struct net_device *pnetdev = padapter->pnetdev; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ DBG_871X("+rtw_dev_remove\n"); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+dev_remove()\n")); ++ dvobj->processing_dev_remove = _TRUE; ++ rtw_unregister_netdevs(dvobj); ++ ++ if(usb_drv->drv_registered == _TRUE) ++ { ++ //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ /*else ++ { ++ //DBG_871X("r871xu_dev_remove():module removed\n"); ++ padapter->hw_init_completed = _FALSE; ++ }*/ ++#ifdef CONFIG_MP_INCLUDED ++ if (padapter->registrypriv.mp_mode == 1) ++ MPT_DeInitAdapter(padapter); ++#endif ++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(dvobj_to_pwrctl(dvobj)); ++#endif ++ ++ rtw_pm_set_ips(padapter, IPS_NONE); ++ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); ++ ++ LeaveAllPowerSaveMode(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_stop(dvobj->if2); ++#endif ++ ++ rtw_usb_if1_deinit(padapter); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ rtw_drv_if2_free(dvobj->if2); ++#endif ++ ++ usb_dvobj_deinit(pusb_intf); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-dev_remove()\n")); ++ DBG_871X("-r871xu_dev_remove, done\n"); ++ ++ ++#ifdef CONFIG_INTEL_PROXIM ++ rtw_sw_export=NULL; ++#endif ++ ++_func_exit_; ++ ++ return; ++ ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++extern int console_suspend_enabled; ++#endif ++ ++static int __init rtw_drv_entry(void) ++{ ++#ifdef CONFIG_PLATFORM_RTK_DMP ++ u32 tmp; ++ tmp=readl((volatile unsigned int*)0xb801a608); ++ tmp &= 0xffffff00; ++ tmp |= 0x55; ++ writel(tmp,(volatile unsigned int*)0xb801a608);//write dummy register for 1055 ++#endif ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++#ifndef CONFIG_RTL8723A ++ int ret = 0; ++ /* ----------get usb_wifi_usbc_num------------- */ ++ ret = script_parser_fetch("usb_wifi_para", "usb_wifi_usbc_num", (int *)&usb_wifi_host, 64); ++ if(ret != 0){ ++ DBG_8192C("ERR: script_parser_fetch usb_wifi_usbc_num failed\n"); ++ ret = -ENOMEM; ++ return ret; ++ } ++ DBG_8192C("sw_usb_enable_hcd: usbc_num = %d\n", usb_wifi_host); ++ sw_usb_enable_hcd(usb_wifi_host); ++#endif //CONFIG_RTL8723A ++#endif //CONFIG_PLATFORM_ARM_SUNxI ++ ++#if defined CONFIG_PLATFORM_ARM_SUN6I ++ script_item_value_type_e type; ++ ++ type = script_get_item("wifi_para", "wifi_usbc_id", &item); ++ if(SCIRPT_ITEM_VALUE_TYPE_INT != type){ ++ printk("ERR: script_get_item wifi_usbc_id failed\n"); ++ return -ENOMEM; ++ } ++ ++ printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val); ++ wifi_pm_power(1); ++ mdelay(10); ++ ++ #ifndef CONFIG_RTL8723A ++ sw_usb_enable_hcd(item.val); ++ #endif ++#endif // defined CONFIG_PLATFORM_ARM_SUN6I && !(defined CONFIG_RTL8723A) ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n")); ++ ++ DBG_871X(DRV_NAME " driver version=%s\n", DRIVERVERSION); ++ DBG_871X("build time: %s %s\n", __DATE__, __TIME__); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++ //console_suspend_enabled=0; ++#endif ++ ++ rtw_suspend_lock_init(); ++ ++ usb_drv->drv_registered = _TRUE; ++ return usb_register(&usb_drv->usbdrv); ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n")); ++ DBG_871X("+rtw_drv_halt\n"); ++ ++ usb_drv->drv_registered = _FALSE; ++ usb_deregister(&usb_drv->usbdrv); ++ ++#ifdef CONFIG_PLATFORM_ARM_SUNxI ++#ifndef CONFIG_RTL8723A ++ DBG_8192C("sw_usb_disable_hcd: usbc_num = %d\n", usb_wifi_host); ++ sw_usb_disable_hcd(usb_wifi_host); ++#endif //ifndef CONFIG_RTL8723A ++#endif //CONFIG_PLATFORM_ARM_SUNxI ++ ++#if defined CONFIG_PLATFORM_ARM_SUN6I ++ #ifndef CONFIG_RTL8723A ++ sw_usb_disable_hcd(item.val); ++ #endif ++ wifi_pm_power(0); ++#endif // defined CONFIG_PLATFORM_ARM_SUN6I && !(defined CONFIG_RTL8723A) ++ ++ rtw_suspend_lock_uninit(); ++ DBG_871X("-rtw_drv_halt\n"); ++ ++ rtw_mstat_dump(); ++} ++ ++ ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); ++ ++#ifdef CONFIG_INTEL_PROXIM ++_adapter *rtw_usb_get_sw_pointer(void) ++{ ++ return rtw_sw_export; ++} ++EXPORT_SYMBOL(rtw_usb_get_sw_pointer); ++#endif //CONFIG_INTEL_PROXIM ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_ops_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_ops_linux.c +new file mode 100644 +index 00000000..db754644 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/usb_ops_linux.c +@@ -0,0 +1,698 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ *******************************************************************************/ ++#define _USB_OPS_LINUX_C_ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *regs) ++{ ++ if (urb) { ++ if (urb->context) { ++ rtw_mfree(urb->context); ++ } ++ usb_free_urb(urb); ++ } ++} ++ ++static int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, ++ u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ int rc; ++ unsigned int pipe; ++ u8 reqtype; ++ struct usb_ctrlrequest *dr; ++ struct urb *urb; ++ struct rtl819x_async_write_data { ++ u8 data[VENDOR_CMD_MAX_DATA_LEN]; ++ struct usb_ctrlrequest dr; ++ } *buf; ++ ++ ++ if (requesttype == VENDOR_READ) { ++ pipe = usb_rcvctrlpipe(udev, 0);//read_in ++ reqtype = REALTEK_USB_VENQT_READ; ++ } ++ else { ++ pipe = usb_sndctrlpipe(udev, 0);//write_out ++ reqtype = REALTEK_USB_VENQT_WRITE; ++ } ++ ++ buf = (struct rtl819x_async_write_data *)rtw_zmalloc(sizeof(*buf)); ++ if (!buf) { ++ rc = -ENOMEM; ++ goto exit; ++ } ++ ++ urb = usb_alloc_urb(0, GFP_ATOMIC); ++ if (!urb) { ++ rtw_mfree((u8*)buf, sizeof(*buf)); ++ rc = -ENOMEM; ++ goto exit; ++ } ++ ++ dr = &buf->dr; ++ ++ dr->bRequestType = reqtype; ++ dr->bRequest = request; ++ dr->wValue = cpu_to_le16(value); ++ dr->wIndex = cpu_to_le16(index); ++ dr->wLength = cpu_to_le16(len); ++ ++ _rtw_memcpy(buf, pdata, len); ++ ++ usb_fill_control_urb(urb, udev, pipe, (unsigned char *)dr, buf, len, ++ _usbctrl_vendorreq_async_callback, buf); ++ ++ rc = usb_submit_urb(urb, GFP_ATOMIC); ++ if (rc < 0) { ++ rtw_mfree((u8*)buf, sizeof(*buf)); ++ usb_free_urb(urb); ++ } ++ ++exit: ++ return rc; ++} ++ ++int usb_write_async(struct usb_device *udev, u32 addr, void *pdata, u16 len) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ ++ int ret; ++ ++ requesttype = VENDOR_WRITE;//write_out ++ request = REALTEK_USB_VENQT_CMD_REQ; ++ index = REALTEK_USB_VENQT_CMD_IDX;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ ++ ret = _usbctrl_vendorreq_async_write(udev, request, wvalue, index, pdata, len, requesttype); ++ ++ return ret; ++} ++ ++int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ++{ ++ u8 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = val; ++ ret = usb_write_async(udev, addr, &data, 1); ++ _func_exit_; ++ ++ return ret; ++} ++ ++int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ++{ ++ u16 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = val; ++ ret = usb_write_async(udev, addr, &data, 2); ++ _func_exit_; ++ ++ return ret; ++} ++ ++int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ++{ ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = val; ++ ret = usb_write_async(udev, addr, &data, 4); ++ _func_exit_; ++ ++ return ret; ++} ++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ ++ ++unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr) ++{ ++ unsigned int pipe=0, ep_num=0; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++ if (addr == RECV_BULK_IN_ADDR) { ++ pipe=usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe[0]); ++ ++ } else if (addr == RECV_INT_IN_ADDR) { ++ pipe=usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe[1]); ++ ++ } else if (addr < HW_QUEUE_ENTRY) { ++ ep_num = pdvobj->Queue2Pipe[addr]; ++ pipe = usb_sndbulkpipe(pusbd, ep_num); ++ } ++ ++ return pipe; ++} ++ ++struct zero_bulkout_context{ ++ void *pbuf; ++ void *purb; ++ void *pirp; ++ void *padapter; ++}; ++ ++static void usb_bulkout_zero_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)purb->context; ++ ++ //DBG_8192C("+usb_bulkout_zero_complete\n"); ++ ++ if(pcontext) ++ { ++ if(pcontext->pbuf) ++ { ++ rtw_mfree(pcontext->pbuf, sizeof(int)); ++ } ++ ++ if(pcontext->purb && (pcontext->purb==purb)) ++ { ++ usb_free_urb(pcontext->purb); ++ } ++ ++ ++ rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context)); ++ } ++ ++ ++} ++ ++static u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ int pipe, status, len; ++ u32 ret; ++ unsigned char *pbuf; ++ struct zero_bulkout_context *pcontext; ++ PURB purb = NULL; ++ _adapter *padapter = (_adapter *)pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++ //DBG_871X("%s\n", __func__); ++ ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx)) ++ { ++ return _FAIL; ++ } ++ ++ ++ pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context)); ++ ++ pbuf = (unsigned char *)rtw_zmalloc(sizeof(int)); ++ purb = usb_alloc_urb(0, GFP_ATOMIC); ++ ++ len = 0; ++ pcontext->pbuf = pbuf; ++ pcontext->purb = purb; ++ pcontext->pirp = NULL; ++ pcontext->padapter = padapter; ++ ++ ++ //translate DMA FIFO addr to pipehandle ++ //pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ pbuf, ++ len, ++ usb_bulkout_zero_complete, ++ pcontext);//context is pcontext ++ ++ status = usb_submit_urb(purb, GFP_ATOMIC); ++ ++ if (!status) ++ { ++ ret= _SUCCESS; ++ } ++ else ++ { ++ ret= _FAIL; ++ } ++ ++ ++ return _SUCCESS; ++ ++} ++ ++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ ++} ++ ++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ ++} ++ ++ ++void usb_read_port_cancel(struct intf_hdl *pintfhdl) ++{ ++ int i; ++ struct recv_buf *precvbuf; ++ _adapter *padapter = pintfhdl->padapter; ++ precvbuf = (struct recv_buf *)padapter->recvpriv.precv_buf; ++ ++ DBG_871X("%s\n", __func__); ++ ++ padapter->bReadPortCancel = _TRUE; ++ ++ for (i=0; i < NR_RECVBUFF ; i++) { ++ ++ precvbuf->reuse = _TRUE; ++ if (precvbuf->purb) { ++ //DBG_8192C("usb_read_port_cancel : usb_kill_urb \n"); ++ usb_kill_urb(precvbuf->purb); ++ } ++ precvbuf++; ++ } ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ usb_kill_urb(padapter->recvpriv.int_in_urb); ++#endif ++} ++ ++static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ _irqL irqL; ++ int i; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context; ++ //struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; ++ //_adapter *padapter = pxmitframe->padapter; ++ _adapter *padapter = pxmitbuf->padapter; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ //struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++_func_enter_; ++ ++ switch(pxmitbuf->flags) ++ { ++ case VO_QUEUE_INX: ++ pxmitpriv->voq_cnt--; ++ break; ++ case VI_QUEUE_INX: ++ pxmitpriv->viq_cnt--; ++ break; ++ case BE_QUEUE_INX: ++ pxmitpriv->beq_cnt--; ++ break; ++ case BK_QUEUE_INX: ++ pxmitpriv->bkq_cnt--; ++ break; ++ case HIGH_QUEUE_INX: ++#ifdef CONFIG_AP_MODE ++ rtw_chk_hi_queue_cmd(padapter); ++#endif ++ break; ++ default: ++ break; ++ } ++ ++ ++/* ++ _enter_critical(&pxmitpriv->lock, &irqL); ++ ++ pxmitpriv->txirp_cnt--; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ pxmitpriv->bkq_cnt--; ++ //DBG_8192C("pxmitpriv->bkq_cnt=%d\n", pxmitpriv->bkq_cnt); ++ break; ++ case 4: ++ case 5: ++ pxmitpriv->viq_cnt--; ++ //DBG_8192C("pxmitpriv->viq_cnt=%d\n", pxmitpriv->viq_cnt); ++ break; ++ case 6: ++ case 7: ++ pxmitpriv->voq_cnt--; ++ //DBG_8192C("pxmitpriv->voq_cnt=%d\n", pxmitpriv->voq_cnt); ++ break; ++ case 0: ++ case 3: ++ default: ++ pxmitpriv->beq_cnt--; ++ //DBG_8192C("pxmitpriv->beq_cnt=%d\n", pxmitpriv->beq_cnt); ++ break; ++ ++ } ++ ++ _exit_critical(&pxmitpriv->lock, &irqL); ++ ++ ++ if(pxmitpriv->txirp_cnt==0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); ++ _rtw_up_sema(&(pxmitpriv->tx_retevt)); ++ } ++*/ ++ //rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped ||padapter->bWritePortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ DBG_8192C("%s(): TX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bWritePortCancel(%d) pxmitbuf->ext_tag(%x) \n", ++ __FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel,pxmitbuf->ext_tag); ++ ++ goto check_completion; ++ } ++ ++ ++ if (purb->status==0) { ++ ++ } else { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ DBG_871X("###=> urb_write_port_complete status(%d)\n",purb->status); ++ if((purb->status==-EPIPE)||(purb->status==-EPROTO)) ++ { ++ //usb_clear_halt(pusbdev, purb->pipe); ++ //msleep(10); ++ sreset_set_wifi_error_status(padapter, USB_WRITE_PORT_FAIL); ++ } else if (purb->status == -EINPROGRESS) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: EINPROGESS\n")); ++ goto check_completion; ++ ++ } else if (purb->status == -ENOENT) { ++ DBG_871X("%s: -ENOENT\n", __func__); ++ goto check_completion; ++ ++ } else if (purb->status == -ECONNRESET) { ++ DBG_871X("%s: -ECONNRESET\n", __func__); ++ goto check_completion; ++ ++ } else if (purb->status == -ESHUTDOWN) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: ESHUTDOWN\n")); ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped=TRUE\n")); ++ ++ goto check_completion; ++ } ++ else ++ { ++ padapter->bSurpriseRemoved=_TRUE; ++ DBG_8192C("bSurpriseRemoved=TRUE\n"); ++ //rtl8192cu_trigger_gpio_0(padapter); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bSurpriseRemoved=TRUE\n")); ++ ++ goto check_completion; ++ } ++ } ++ ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time(); ++ } ++ #endif ++ ++check_completion: ++ _enter_critical(&pxmitpriv->lock_sctx, &irqL); ++ rtw_sctx_done_err(&pxmitbuf->sctx, ++ purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); ++ _exit_critical(&pxmitpriv->lock_sctx, &irqL); ++ ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ ++ //if(rtw_txframes_pending(padapter)) ++ { ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ } ++ ++_func_exit_; ++ ++} ++ ++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ _irqL irqL; ++ unsigned int pipe; ++ int status; ++ u32 ret = _FAIL, bwritezero = _FALSE; ++ PURB purb = NULL; ++ _adapter *padapter = (_adapter *)pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)wmem; ++ struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port\n")); ++ ++ if ((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx)) { ++ #ifdef DBG_TX ++ DBG_871X(" DBG_TX %s:%d bDriverStopped%d, bSurpriseRemoved:%d, pnp_bstop_trx:%d\n",__FUNCTION__, __LINE__ ++ ,padapter->bDriverStopped, padapter->bSurpriseRemoved, dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx ); ++ #endif ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_TX_DENY); ++ goto exit; ++ } ++ ++ _enter_critical(&pxmitpriv->lock, &irqL); ++ ++ switch(addr) ++ { ++ case VO_QUEUE_INX: ++ pxmitpriv->voq_cnt++; ++ pxmitbuf->flags = VO_QUEUE_INX; ++ break; ++ case VI_QUEUE_INX: ++ pxmitpriv->viq_cnt++; ++ pxmitbuf->flags = VI_QUEUE_INX; ++ break; ++ case BE_QUEUE_INX: ++ pxmitpriv->beq_cnt++; ++ pxmitbuf->flags = BE_QUEUE_INX; ++ break; ++ case BK_QUEUE_INX: ++ pxmitpriv->bkq_cnt++; ++ pxmitbuf->flags = BK_QUEUE_INX; ++ break; ++ case HIGH_QUEUE_INX: ++ pxmitbuf->flags = HIGH_QUEUE_INX; ++ break; ++ default: ++ pxmitbuf->flags = MGT_QUEUE_INX; ++ break; ++ } ++ ++ _exit_critical(&pxmitpriv->lock, &irqL); ++ ++ #ifdef DBG_TRX_STA_PKTS ++ { ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ int bmcast = IS_MCAST(pattrib->dst); ++ u8 agg_num = 1; ++ ++ #ifdef CONFIG_USB_HCI ++ #ifdef CONFIG_USB_TX_AGGREGATION ++ if(pxmitframe->agg_num>1) ++ agg_num = pxmitframe->agg_num; ++ #endif ++ #endif ++ ++ #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ if(pxmitframe->agg_num>1) ++ agg_num = pxmitframe->agg_num; ++ #endif ++ ++ if(bmcast) ++ { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ } ++ if(psta) ++ { ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ psta->tx_bk_cnt += agg_num; ++ break; ++ case 4: ++ case 5: ++ psta->tx_vi_cnt += agg_num; ++ break; ++ case 6: ++ case 7: ++ psta->tx_vo_cnt += agg_num; ++ break; ++ case 0: ++ case 3: ++ default: ++ psta->tx_be_cnt += agg_num; ++ break; ++ } ++ } ++ } ++ #endif ++ ++ purb = pxmitbuf->pxmit_urb[0]; ++ ++#if 0 ++ if(pdvobj->ishighspeed) ++ { ++ if(cnt> 0 && cnt%512 == 0) ++ { ++ //DBG_8192C("ishighspeed, cnt=%d\n", cnt); ++ bwritezero = _TRUE; ++ } ++ } ++ else ++ { ++ if(cnt > 0 && cnt%64 == 0) ++ { ++ //DBG_8192C("cnt=%d\n", cnt); ++ bwritezero = _TRUE; ++ } ++ } ++#endif ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++#ifdef CONFIG_REDUCE_USB_TX_INT ++ if ( (pxmitpriv->free_xmitbuf_cnt%NR_XMITBUFF == 0) ++ || (pxmitbuf->ext_tag == _TRUE) ) ++ { ++ purb->transfer_flags &= (~URB_NO_INTERRUPT); ++ } else { ++ purb->transfer_flags |= URB_NO_INTERRUPT; ++ //DBG_8192C("URB_NO_INTERRUPT "); ++ } ++#endif ++ ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ pxmitframe->buf_addr, //= pxmitbuf->pbuf ++ cnt, ++ usb_write_port_complete, ++ pxmitbuf);//context is pxmitbuf ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ purb->transfer_dma = pxmitbuf->dma_transfer_addr; ++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ purb->transfer_flags |= URB_ZERO_PACKET; ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++#if 0 ++ if (bwritezero) ++ { ++ purb->transfer_flags |= URB_ZERO_PACKET; ++ } ++#endif ++ ++ status = usb_submit_urb(purb, GFP_ATOMIC); ++ if (!status) { ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.last_tx_time = rtw_get_current_time(); ++ } ++ #endif ++ } else { ++ rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR); ++ DBG_871X("usb_write_port, status=%d\n", status); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port(): usb_submit_urb, status=%x\n", status)); ++ ++ switch (status) { ++ case -ENODEV: ++ padapter->bDriverStopped=_TRUE; ++ break; ++ default: ++ break; ++ } ++ goto exit; ++ } ++ ++ ret= _SUCCESS; ++ ++// Commented by Albert 2009/10/13 ++// We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. ++/* ++ if(bwritezero == _TRUE) ++ { ++ usb_bulkout_zero(pintfhdl, addr); ++ } ++*/ ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("-usb_write_port\n")); ++ ++exit: ++ if (ret != _SUCCESS) ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++_func_exit_; ++ return ret; ++ ++} ++ ++void usb_write_port_cancel(struct intf_hdl *pintfhdl) ++{ ++ int i, j; ++ _adapter *padapter = pintfhdl->padapter; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmitbuf; ++ ++ DBG_871X("%s \n", __func__); ++ ++ padapter->bWritePortCancel = _TRUE; ++ ++ for (i=0; ipxmit_urb[j]) { ++ usb_kill_urb(pxmitbuf->pxmit_urb[j]); ++ } ++ } ++ pxmitbuf++; ++ } ++ ++ pxmitbuf = (struct xmit_buf*)padapter->xmitpriv.pxmit_extbuf; ++ for (i = 0; i < NR_XMIT_EXTBUFF; i++) { ++ for (j=0; j<8; j++) { ++ if(pxmitbuf->pxmit_urb[j]) { ++ usb_kill_urb(pxmitbuf->pxmit_urb[j]); ++ } ++ } ++ pxmitbuf++; ++ } ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/xmit_linux.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/xmit_linux.c +new file mode 100644 +index 00000000..979066d8 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/linux/xmit_linux.c +@@ -0,0 +1,456 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _XMIT_OSDEP_C_ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++uint rtw_remainder_len(struct pkt_file *pfile) ++{ ++ return (pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start))); ++} ++ ++void _rtw_open_pktfile (_pkt *pktptr, struct pkt_file *pfile) ++{ ++_func_enter_; ++ ++ pfile->pkt = pktptr; ++ pfile->cur_addr = pfile->buf_start = pktptr->data; ++ pfile->pkt_len = pfile->buf_len = pktptr->len; ++ ++ pfile->cur_buffer = pfile->buf_start ; ++ ++_func_exit_; ++} ++ ++uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen) ++{ ++ uint len = 0; ++ ++_func_enter_; ++ ++ len = rtw_remainder_len(pfile); ++ len = (rlen > len)? len: rlen; ++ ++ if(rmem) ++ skb_copy_bits(pfile->pkt, pfile->buf_len-pfile->pkt_len, rmem, len); ++ ++ pfile->cur_addr += len; ++ pfile->pkt_len -= len; ++ ++_func_exit_; ++ ++ return len; ++} ++ ++sint rtw_endofpktfile(struct pkt_file *pfile) ++{ ++_func_enter_; ++ ++ if (pfile->pkt_len == 0) { ++_func_exit_; ++ return _TRUE; ++ } ++ ++_func_exit_; ++ ++ return _FALSE; ++} ++ ++void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) ++{ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ struct sk_buff *skb = (struct sk_buff *)pkt; ++ pattrib->hw_tcp_csum = 0; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ if (skb_shinfo(skb)->nr_frags == 0) ++ { ++ const struct iphdr *ip = ip_hdr(skb); ++ if (ip->protocol == IPPROTO_TCP) { ++ // TCP checksum offload by HW ++ DBG_871X("CHECKSUM_PARTIAL TCP\n"); ++ pattrib->hw_tcp_csum = 1; ++ //skb_checksum_help(skb); ++ } else if (ip->protocol == IPPROTO_UDP) { ++ //DBG_871X("CHECKSUM_PARTIAL UDP\n"); ++#if 1 ++ skb_checksum_help(skb); ++#else ++ // Set UDP checksum = 0 to skip checksum check ++ struct udphdr *udp = skb_transport_header(skb); ++ udp->check = 0; ++#endif ++ } else { ++ DBG_871X("%s-%d TCP CSUM offload Error!!\n", __FUNCTION__, __LINE__); ++ WARN_ON(1); /* we need a WARN() */ ++ } ++ } ++ else { // IP fragmentation case ++ DBG_871X("%s-%d nr_frags != 0, using skb_checksum_help(skb);!!\n", __FUNCTION__, __LINE__); ++ skb_checksum_help(skb); ++ } ++ } ++#endif ++ ++} ++ ++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz) ++{ ++#ifdef CONFIG_USB_HCI ++ int i; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr); ++ pxmitbuf->pbuf = pxmitbuf->pallocated_buf; ++ if(pxmitbuf->pallocated_buf == NULL) ++ return _FAIL; ++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ return _FAIL; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++ pxmitbuf->dma_transfer_addr = 0; ++ ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ for(i=0; i<8; i++) ++ { ++ pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL); ++ if(pxmitbuf->pxmit_urb[i] == NULL) ++ { ++ DBG_871X("pxmitbuf->pxmit_urb[i]==NULL"); ++ return _FAIL; ++ } ++ ++ } ++#endif ++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ return _FAIL; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++#endif ++ ++ return _SUCCESS; ++} ++ ++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz) ++{ ++#ifdef CONFIG_USB_HCI ++ int i; ++ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ ++ for(i=0; i<8; i++) ++ { ++ if(pxmitbuf->pxmit_urb[i]) ++ { ++ //usb_kill_urb(pxmitbuf->pxmit_urb[i]); ++ usb_free_urb(pxmitbuf->pxmit_urb[i]); ++ } ++ } ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr); ++ pxmitbuf->pallocated_buf = NULL; ++ pxmitbuf->dma_transfer_addr = 0; ++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ if(pxmitbuf->pallocated_buf) ++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++#endif ++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ if(pxmitbuf->pallocated_buf) ++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz); ++#endif ++} ++ ++#define WMM_XMIT_THRESHOLD (NR_XMITFRAME*2/5) ++ ++void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ u16 queue; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ queue = skb_get_queue_mapping(pkt); ++ if (padapter->registrypriv.wifi_spec) { ++ if(__netif_subqueue_stopped(padapter->pnetdev, queue) && ++ (pxmitpriv->hwxmits[queue].accnt < WMM_XMIT_THRESHOLD)) ++ { ++ netif_wake_subqueue(padapter->pnetdev, queue); ++ } ++ } else { ++ if(__netif_subqueue_stopped(padapter->pnetdev, queue)) ++ netif_wake_subqueue(padapter->pnetdev, queue); ++ } ++#else ++ if (netif_queue_stopped(padapter->pnetdev)) ++ netif_wake_queue(padapter->pnetdev); ++#endif ++ ++ rtw_skb_free(pkt); ++} ++ ++void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe) ++{ ++ if(pxframe->pkt) ++ rtw_os_pkt_complete(padapter, pxframe->pkt); ++ ++ pxframe->pkt = NULL; ++} ++ ++void rtw_os_xmit_schedule(_adapter *padapter) ++{ ++ _adapter *pri_adapter = padapter; ++ ++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) ++ if(!padapter) ++ return; ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if(padapter->adapter_type > PRIMARY_ADAPTER) ++ pri_adapter = padapter->pbuddy_adapter; ++#endif ++ ++ if (_rtw_queue_empty(&pri_adapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) ++ _rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema); ++ ++ ++#else ++ _irqL irqL; ++ struct xmit_priv *pxmitpriv; ++ ++ if(!padapter) ++ return; ++ ++ pxmitpriv = &padapter->xmitpriv; ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if(rtw_txframes_pending(padapter)) ++ { ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ } ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++#endif ++} ++ ++static void rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ u16 queue; ++ ++ queue = skb_get_queue_mapping(pkt); ++ if (padapter->registrypriv.wifi_spec) { ++ /* No free space for Tx, tx_worker is too slow */ ++ if (pxmitpriv->hwxmits[queue].accnt > WMM_XMIT_THRESHOLD) { ++ //DBG_871X("%s(): stop netif_subqueue[%d]\n", __FUNCTION__, queue); ++ netif_stop_subqueue(padapter->pnetdev, queue); ++ } ++ } else { ++ if(pxmitpriv->free_xmitframe_cnt<=4) { ++ if (!netif_tx_queue_stopped(netdev_get_tx_queue(padapter->pnetdev, queue))) ++ netif_stop_subqueue(padapter->pnetdev, queue); ++ } ++ } ++#else ++ if(pxmitpriv->free_xmitframe_cnt<=4) ++ { ++ if (!rtw_netif_queue_stopped(padapter->pnetdev)) ++ rtw_netif_stop_queue(padapter->pnetdev); ++ } ++#endif ++} ++ ++#ifdef CONFIG_TX_MCAST2UNI ++int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sk_buff *newskb; ++ struct sta_info *psta = NULL; ++ u8 chk_alive_num = 0; ++ char chk_alive_list[NUM_STA]; ++ u8 bc_addr[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ u8 null_addr[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ int i; ++ s32 res; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //free sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { ++ int stainfo_offset; ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ plist = get_next(plist); ++ ++ stainfo_offset = rtw_stainfo_offset(pstapriv, psta); ++ if (stainfo_offset_valid(stainfo_offset)) { ++ chk_alive_list[chk_alive_num++] = stainfo_offset; ++ } ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ for (i = 0; i < chk_alive_num; i++) { ++ psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); ++ if(!(psta->state &_FW_LINKED)) ++ continue; ++ ++ /* avoid come from STA1 and send back STA1 */ ++ if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE ++ || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE ++ || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE ++ ) ++ continue; ++ ++ newskb = rtw_skb_copy(skb); ++ ++ if (newskb) { ++ _rtw_memcpy(newskb->data, psta->hwaddr, 6); ++ res = rtw_xmit(padapter, &newskb); ++ if (res < 0) { ++ DBG_871X("%s()-%d: rtw_xmit() return error!\n", __FUNCTION__, __LINE__); ++ pxmitpriv->tx_drop++; ++ rtw_skb_free(newskb); ++ } else ++ pxmitpriv->tx_pkts++; ++ } else { ++ DBG_871X("%s-%d: rtw_skb_copy() failed!\n", __FUNCTION__, __LINE__); ++ pxmitpriv->tx_drop++; ++ //rtw_skb_free(skb); ++ return _FALSE; // Caller shall tx this multicast frame via normal way. ++ } ++ } ++ ++ rtw_skb_free(skb); ++ return _TRUE; ++} ++#endif // CONFIG_TX_MCAST2UNI ++ ++ ++int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++#ifdef CONFIG_TX_MCAST2UNI ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ extern int rtw_mc2u_disable; ++#endif // CONFIG_TX_MCAST2UNI ++ s32 res = 0; ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ u16 queue; ++#endif ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("+xmit_enry\n")); ++ ++ if (rtw_if_up(padapter) == _FALSE) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit_entry: rtw_if_up fail\n")); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); ++ #endif ++ goto drop_packet; ++ } ++ ++ rtw_check_xmit_resource(padapter, pkt); ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ if ( !rtw_mc2u_disable ++ && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE ++ && ( IP_MCAST_MAC(pkt->data) ++ || ICMPV6_MCAST_MAC(pkt->data) ) ++ && (padapter->registrypriv.wifi_spec == 0) ++ ) ++ { ++ if ( pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME/4) ) { ++ res = rtw_mlcst2unicst(padapter, pkt); ++ if (res == _TRUE) { ++ goto exit; ++ } ++ } else { ++ //DBG_871X("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); ++ //DBG_871X("!m2u ); ++ } ++ } ++#endif // CONFIG_TX_MCAST2UNI ++ ++ res = rtw_xmit(padapter, &pkt); ++ if (res < 0) { ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); ++ #endif ++ goto drop_packet; ++ } ++ ++ pxmitpriv->tx_pkts++; ++ RT_TRACE(_module_xmit_osdep_c_, _drv_info_, ("rtw_xmit_entry: tx_pkts=%d\n", (u32)pxmitpriv->tx_pkts)); ++ goto exit; ++ ++drop_packet: ++ pxmitpriv->tx_drop++; ++ rtw_skb_free(pkt); ++ RT_TRACE(_module_xmit_osdep_c_, _drv_notice_, ("rtw_xmit_entry: drop, tx_drop=%d\n", (u32)pxmitpriv->tx_drop)); ++ ++exit: ++ ++_func_exit_; ++ ++ return 0; ++} ++ ++int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) ++{ ++ if (pkt) ++ rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize); ++ return _rtw_xmit_entry(pkt, pnetdev); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/os_dep/osdep_service.c b/drivers/net/wireless/rtl818x/rtl8189/os_dep/osdep_service.c +new file mode 100644 +index 00000000..ac86e4d2 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/os_dep/osdep_service.c +@@ -0,0 +1,2335 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _OSDEP_SERVICE_C_ ++ ++#include ++#include ++#include ++#include ++#ifdef PLATFORM_LINUX ++#include ++#endif ++#ifdef PLATFORM_FREEBSD ++#include ++#include ++#endif /* PLATFORM_FREEBSD */ ++#ifdef RTK_DMP_PLATFORM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++#include ++#endif ++#endif ++ ++#define RT_TAG '1178' ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++#include ++atomic_t _malloc_cnt = ATOMIC_INIT(0); ++atomic_t _malloc_size = ATOMIC_INIT(0); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ ++#if defined(PLATFORM_LINUX) ++/* ++* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE ++* @return: one of RTW_STATUS_CODE ++*/ ++inline int RTW_STATUS_CODE(int error_code){ ++ if(error_code >=0) ++ return _SUCCESS; ++ ++ switch(error_code) { ++ //case -ETIMEDOUT: ++ // return RTW_STATUS_TIMEDOUT; ++ default: ++ return _FAIL; ++ } ++} ++#else ++inline int RTW_STATUS_CODE(int error_code){ ++ return error_code; ++} ++#endif ++ ++u32 rtw_atoi(u8* s) ++{ ++ ++ int num=0,flag=0; ++ int i; ++ for(i=0;i<=strlen(s);i++) ++ { ++ if(s[i] >= '0' && s[i] <= '9') ++ num = num * 10 + s[i] -'0'; ++ else if(s[0] == '-' && i==0) ++ flag =1; ++ else ++ break; ++ } ++ ++ if(flag == 1) ++ num = num * -1; ++ ++ return(num); ++ ++} ++ ++inline u8* _rtw_vmalloc(u32 sz) ++{ ++ u8 *pbuf; ++#ifdef PLATFORM_LINUX ++ pbuf = vmalloc(sz); ++#endif ++#ifdef PLATFORM_FREEBSD ++ pbuf = malloc(sz,M_DEVBUF,M_NOWAIT); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ if ( pbuf != NULL) { ++ atomic_inc(&_malloc_cnt); ++ atomic_add(sz, &_malloc_size); ++ } ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ return pbuf; ++} ++ ++inline u8* _rtw_zvmalloc(u32 sz) ++{ ++ u8 *pbuf; ++#ifdef PLATFORM_LINUX ++ pbuf = _rtw_vmalloc(sz); ++ if (pbuf != NULL) ++ memset(pbuf, 0, sz); ++#endif ++#ifdef PLATFORM_FREEBSD ++ pbuf = malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT); ++#endif ++#ifdef PLATFORM_WINDOWS ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++ if (pbuf != NULL) ++ NdisFillMemory(pbuf, sz, 0); ++#endif ++ ++ return pbuf; ++} ++ ++inline void _rtw_vmfree(u8 *pbuf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ vfree(pbuf); ++#endif ++#ifdef PLATFORM_FREEBSD ++ free(pbuf,M_DEVBUF); ++#endif ++#ifdef PLATFORM_WINDOWS ++ NdisFreeMemory(pbuf,sz, 0); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ atomic_dec(&_malloc_cnt); ++ atomic_sub(sz, &_malloc_size); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++} ++ ++u8* _rtw_malloc(u32 sz) ++{ ++ ++ u8 *pbuf=NULL; ++ ++#ifdef PLATFORM_LINUX ++#ifdef RTK_DMP_PLATFORM ++ if(sz > 0x4000) ++ pbuf = (u8 *)dvr_malloc(sz); ++ else ++#endif ++ pbuf = kmalloc(sz,in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ pbuf = malloc(sz,M_DEVBUF,M_NOWAIT); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ if ( pbuf != NULL) { ++ atomic_inc(&_malloc_cnt); ++ atomic_add(sz, &_malloc_size); ++ } ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ return pbuf; ++ ++} ++ ++ ++u8* _rtw_zmalloc(u32 sz) ++{ ++#ifdef PLATFORM_FREEBSD ++ return malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT); ++#else // PLATFORM_FREEBSD ++ u8 *pbuf = _rtw_malloc(sz); ++ ++ if (pbuf != NULL) { ++ ++#ifdef PLATFORM_LINUX ++ memset(pbuf, 0, sz); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisFillMemory(pbuf, sz, 0); ++#endif ++ ++ } ++ ++ return pbuf; ++#endif // PLATFORM_FREEBSD ++} ++ ++void _rtw_mfree(u8 *pbuf, u32 sz) ++{ ++ ++#ifdef PLATFORM_LINUX ++#ifdef RTK_DMP_PLATFORM ++ if(sz > 0x4000) ++ dvr_free(pbuf); ++ else ++#endif ++ kfree(pbuf); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ free(pbuf,M_DEVBUF); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisFreeMemory(pbuf,sz, 0); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ atomic_dec(&_malloc_cnt); ++ atomic_sub(sz, &_malloc_size); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++} ++ ++#ifdef PLATFORM_FREEBSD ++//review again ++struct sk_buff * dev_alloc_skb(unsigned int size) ++{ ++ struct sk_buff *skb=NULL; ++ u8 *data=NULL; ++ ++ //skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); // for skb->len, etc. ++ skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff)); ++ if(!skb) ++ goto out; ++ data = _rtw_malloc(size); ++ if(!data) ++ goto nodata; ++ ++ skb->head = (unsigned char*)data; ++ skb->data = (unsigned char*)data; ++ skb->tail = (unsigned char*)data; ++ skb->end = (unsigned char*)data + size; ++ skb->len = 0; ++ //printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); ++ ++out: ++ return skb; ++nodata: ++ _rtw_mfree((u8 *)skb, sizeof(struct sk_buff)); ++ skb = NULL; ++goto out; ++ ++} ++ ++void dev_kfree_skb_any(struct sk_buff *skb) ++{ ++ //printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); ++ if(skb->head) ++ _rtw_mfree(skb->head, 0); ++ //printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); ++ if(skb) ++ _rtw_mfree((u8 *)skb, 0); ++} ++struct sk_buff *skb_clone(const struct sk_buff *skb) ++{ ++ return NULL; ++} ++ ++#endif /* PLATFORM_FREEBSD */ ++ ++inline struct sk_buff *_rtw_skb_alloc(u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ return dev_alloc_skb(sz); ++#endif /* PLATFORM_FREEBSD */ ++} ++ ++inline void _rtw_skb_free(struct sk_buff *skb) ++{ ++ dev_kfree_skb_any(skb); ++} ++ ++inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) ++{ ++#ifdef PLATFORM_LINUX ++ return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ return NULL; ++#endif /* PLATFORM_FREEBSD */ ++} ++ ++inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) ++{ ++#ifdef PLATFORM_LINUX ++ return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ return skb_clone(skb); ++#endif /* PLATFORM_FREEBSD */ ++} ++ ++inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) ++{ ++#ifdef PLATFORM_LINUX ++ skb->dev = ndev; ++ return netif_rx(skb); ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ return (*ndev->if_input)(ndev, skb); ++#endif /* PLATFORM_FREEBSD */ ++} ++ ++void _rtw_skb_queue_purge(struct sk_buff_head *list) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = skb_dequeue(list)) != NULL) ++ _rtw_skb_free(skb); ++} ++ ++#ifdef CONFIG_USB_HCI ++inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma) ++{ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); ++#else ++ return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); ++#endif ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ return (malloc(size, M_USBDEV, M_NOWAIT | M_ZERO)); ++#endif /* PLATFORM_FREEBSD */ ++} ++inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma) ++{ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ usb_free_coherent(dev, size, addr, dma); ++#else ++ usb_buffer_free(dev, size, addr, dma); ++#endif ++#endif /* PLATFORM_LINUX */ ++ ++#ifdef PLATFORM_FREEBSD ++ free(addr, M_USBDEV); ++#endif /* PLATFORM_FREEBSD */ ++} ++#endif /* CONFIG_USB_HCI */ ++ ++#ifdef DBG_MEM_ALLOC ++ ++struct rtw_mem_stat { ++ ATOMIC_T alloc; // the memory bytes we allocate currently ++ ATOMIC_T peak; // the peak memory bytes we allocate ++ ATOMIC_T alloc_cnt; // the alloc count for alloc currently ++ ATOMIC_T alloc_err_cnt; // the error times we fail to allocate memory ++}; ++ ++struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)]; ++struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)]; ++ ++char *MSTAT_TYPE_str[] = { ++ "VIR", ++ "PHY", ++ "SKB", ++ "USB", ++}; ++ ++char *MSTAT_FUNC_str[] = { ++ "UNSP", ++ "IO", ++ "TXIO", ++ "RXIO", ++ "TX", ++ "RX", ++}; ++ ++int _rtw_mstat_dump(char *buf, int len) ++{ ++ int cnt = 0; ++ int i; ++ int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)]; ++ int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)]; ++ ++ int vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err; ++ int tx_alloc, tx_peak, tx_alloc_err, rx_alloc, rx_peak, rx_alloc_err; ++ ++ for(i=0;i 5000) { ++ // rtw_mstat_dump(); ++ update_time=rtw_get_current_time(); ++ //} ++} ++ ++ ++ ++inline u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ u8 *p; ++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_vmalloc((sz)); ++ ++ rtw_mstat_update( ++ flags ++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ u8 *p; ++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_zvmalloc((sz)); ++ ++ rtw_mstat_update( ++ flags ++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz)); ++ ++ _rtw_vmfree((pbuf), (sz)); ++ ++ rtw_mstat_update( ++ flags ++ , MSTAT_FREE ++ , sz ++ ); ++} ++ ++inline u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ u8 *p; ++ ++ //if(sz>=153 && sz<=306) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ //if((sz)>4096) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_malloc((sz)); ++ ++ rtw_mstat_update( ++ flags ++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ u8 *p; ++ ++ //if(sz>=153 && sz<=306) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ //if((sz)>4096) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p = _rtw_zmalloc((sz)); ++ ++ rtw_mstat_update( ++ flags ++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) ++{ ++ //if(sz>=153 && sz<=306) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ //if((sz)>4096) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz)); ++ ++ _rtw_mfree((pbuf), (sz)); ++ ++ rtw_mstat_update( ++ flags ++ , MSTAT_FREE ++ , sz ++ ); ++} ++ ++inline struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line) ++{ ++ struct sk_buff *skb; ++ unsigned int truesize = 0; ++ ++ skb = _rtw_skb_alloc(size); ++ ++ if(skb) ++ truesize = skb->truesize; ++ ++ if(!skb || truesize < size /*|| size > 4096*/) ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize); ++ ++ rtw_mstat_update( ++ flags ++ , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , truesize ++ ); ++ ++ return skb; ++} ++ ++inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) ++{ ++ unsigned int truesize = skb->truesize; ++ ++ //if(truesize > 4096) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); ++ ++ _rtw_skb_free(skb); ++ ++ rtw_mstat_update( ++ flags ++ , MSTAT_FREE ++ , truesize ++ ); ++} ++ ++inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line) ++{ ++ struct sk_buff *skb_cp; ++ unsigned int truesize = skb->truesize; ++ unsigned int cp_truesize = 0; ++ ++ skb_cp = _rtw_skb_copy(skb); ++ if(skb_cp) ++ cp_truesize = skb_cp->truesize; ++ ++ if(!skb_cp || cp_truesize != truesize /*||cp_truesize > 4096*/) ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize); ++ ++ rtw_mstat_update( ++ flags ++ , skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , truesize ++ ); ++ ++ return skb_cp; ++} ++ ++inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line) ++{ ++ struct sk_buff *skb_cl; ++ unsigned int truesize = skb->truesize; ++ unsigned int cl_truesize = 0; ++ ++ skb_cl = _rtw_skb_clone(skb); ++ if(skb_cl) ++ cl_truesize = skb_cl->truesize; ++ ++ if(!skb_cl || cl_truesize != truesize /*|| cl_truesize > 4096*/) ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize); ++ ++ rtw_mstat_update( ++ flags ++ , skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , truesize ++ ); ++ ++ return skb_cl; ++} ++ ++inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) ++{ ++ int ret; ++ unsigned int truesize = skb->truesize; ++ ++ //if(truesize > 4096) ++ // DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); ++ ++ ret = _rtw_netif_rx(ndev, skb); ++ ++ rtw_mstat_update( ++ flags ++ , MSTAT_FREE ++ , truesize ++ ); ++ ++ return ret; ++} ++ ++inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = skb_dequeue(list)) != NULL) ++ dbg_rtw_skb_free(skb, flags, func, line); ++} ++ ++#ifdef CONFIG_USB_HCI ++inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line) ++{ ++ void *p; ++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, size); ++ ++ p = _rtw_usb_buffer_alloc(dev, size, dma); ++ ++ rtw_mstat_update( ++ flags ++ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL ++ , size ++ ); ++ ++ return p; ++} ++ ++inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line) ++{ ++ //DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, size); ++ ++ _rtw_usb_buffer_free(dev, size, addr, dma); ++ ++ rtw_mstat_update( ++ flags ++ , MSTAT_FREE ++ , size ++ ); ++} ++#endif /* CONFIG_USB_HCI */ ++#endif /* DBG_MEM_ALLOC */ ++ ++void* rtw_malloc2d(int h, int w, int size) ++{ ++ int j; ++ ++ void **a = (void **) rtw_zmalloc( h*sizeof(void *) + h*w*size ); ++ if(a == NULL) ++ { ++ DBG_871X("%s: alloc memory fail!\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ for( j=0; jprev = pnew; ++ pnew->next = pnext; ++ pnew->prev = pprev; ++ pprev->next = pnew; ++} ++#endif /* PLATFORM_FREEBSD */ ++ ++void _rtw_init_listhead(_list *list) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ INIT_LIST_HEAD(list); ++ ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++ list->next = list; ++ list->prev = list; ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisInitializeListHead(list); ++ ++#endif ++ ++} ++ ++ ++/* ++For the following list_xxx operations, ++caller must guarantee the atomic context. ++Otherwise, there will be racing condition. ++*/ ++u32 rtw_is_list_empty(_list *phead) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ if (list_empty(phead)) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ ++ if (phead->next == phead) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++ if (IsListEmpty(phead)) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++ ++ ++} ++ ++void rtw_list_insert_head(_list *plist, _list *phead) ++{ ++ ++#ifdef PLATFORM_LINUX ++ list_add(plist, phead); ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++ __list_add(plist, phead, phead->next); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ InsertHeadList(phead, plist); ++#endif ++} ++ ++void rtw_list_insert_tail(_list *plist, _list *phead) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ list_add_tail(plist, phead); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ ++ __list_add(plist, phead->prev, phead); ++ ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ InsertTailList(phead, plist); ++ ++#endif ++ ++} ++ ++ ++/* ++ ++Caller must check if the list is empty before calling rtw_list_delete ++ ++*/ ++ ++ ++void _rtw_init_sema(_sema *sema, int init_val) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ sema_init(sema, init_val); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ sema_init(sema, init_val, "rtw_drv"); ++#endif ++#ifdef PLATFORM_OS_XP ++ ++ KeInitializeSemaphore(sema, init_val, SEMA_UPBND); // count=0; ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ if(*sema == NULL) ++ *sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL); ++#endif ++ ++} ++ ++void _rtw_free_sema(_sema *sema) ++{ ++#ifdef PLATFORM_FREEBSD ++ sema_destroy(sema); ++#endif ++#ifdef PLATFORM_OS_CE ++ CloseHandle(*sema); ++#endif ++ ++} ++ ++void _rtw_up_sema(_sema *sema) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ up(sema); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ sema_post(sema); ++#endif ++#ifdef PLATFORM_OS_XP ++ ++ KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1, FALSE ); ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ ReleaseSemaphore(*sema, 1, NULL ); ++#endif ++} ++ ++u32 _rtw_down_sema(_sema *sema) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ if (down_interruptible(sema)) ++ return _FAIL; ++ else ++ return _SUCCESS; ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ sema_wait(sema); ++ return _SUCCESS; ++#endif ++#ifdef PLATFORM_OS_XP ++ ++ if(STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL)) ++ return _SUCCESS; ++ else ++ return _FAIL; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ if(WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE )) ++ return _SUCCESS; ++ else ++ return _FAIL; ++#endif ++} ++ ++ ++ ++void _rtw_mutex_init(_mutex *pmutex) ++{ ++#ifdef PLATFORM_LINUX ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_init(pmutex); ++#else ++ init_MUTEX(pmutex); ++#endif ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_init(pmutex, "", NULL, MTX_DEF|MTX_RECURSE); ++#endif ++#ifdef PLATFORM_OS_XP ++ ++ KeInitializeMutex(pmutex, 0); ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ *pmutex = CreateMutex( NULL, _FALSE, NULL); ++#endif ++} ++ ++void _rtw_mutex_free(_mutex *pmutex); ++void _rtw_mutex_free(_mutex *pmutex) ++{ ++#ifdef PLATFORM_LINUX ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_destroy(pmutex); ++#else ++#endif ++ ++#ifdef PLATFORM_FREEBSD ++ sema_destroy(pmutex); ++#endif ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ ++#endif ++} ++ ++void _rtw_spinlock_init(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock_init(plock); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_init(plock, "", NULL, MTX_DEF|MTX_RECURSE); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAllocateSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinlock_free(_lock *plock) ++{ ++#ifdef PLATFORM_FREEBSD ++ mtx_destroy(plock); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisFreeSpinLock(plock); ++ ++#endif ++ ++} ++#ifdef PLATFORM_FREEBSD ++extern PADAPTER prtw_lock; ++ ++void rtw_mtx_lock(_lock *plock){ ++ if(prtw_lock){ ++ mtx_lock(&prtw_lock->glock); ++ } ++ else{ ++ printf("%s prtw_lock==NULL",__FUNCTION__); ++ } ++} ++void rtw_mtx_unlock(_lock *plock){ ++ if(prtw_lock){ ++ mtx_unlock(&prtw_lock->glock); ++ } ++ else{ ++ printf("%s prtw_lock==NULL",__FUNCTION__); ++ } ++ ++} ++#endif //PLATFORM_FREEBSD ++ ++ ++void _rtw_spinlock(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock(plock); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_lock(plock); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAcquireSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinunlock(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_unlock(plock); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_unlock(plock); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisReleaseSpinLock(plock); ++ ++#endif ++} ++ ++ ++void _rtw_spinlock_ex(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock(plock); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_lock(plock); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisDprAcquireSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinunlock_ex(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_unlock(plock); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ mtx_unlock(plock); ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisDprReleaseSpinLock(plock); ++ ++#endif ++} ++ ++ ++ ++void _rtw_init_queue(_queue *pqueue) ++{ ++ ++ _rtw_init_listhead(&(pqueue->queue)); ++ ++ _rtw_spinlock_init(&(pqueue->lock)); ++ ++} ++ ++u32 _rtw_queue_empty(_queue *pqueue) ++{ ++ return (rtw_is_list_empty(&(pqueue->queue))); ++} ++ ++ ++u32 rtw_end_of_queue_search(_list *head, _list *plist) ++{ ++ if (head == plist) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++ ++u32 rtw_get_current_time(void) ++{ ++ ++#ifdef PLATFORM_LINUX ++ return jiffies; ++#endif ++#ifdef PLATFORM_FREEBSD ++ struct timeval tvp; ++ getmicrotime(&tvp); ++ return tvp.tv_sec; ++#endif ++#ifdef PLATFORM_WINDOWS ++ LARGE_INTEGER SystemTime; ++ NdisGetCurrentSystemTime(&SystemTime); ++ return (u32)(SystemTime.LowPart);// count of 100-nanosecond intervals ++#endif ++} ++ ++inline u32 rtw_systime_to_ms(u32 systime) ++{ ++#ifdef PLATFORM_LINUX ++ return systime * 1000 / HZ; ++#endif ++#ifdef PLATFORM_FREEBSD ++ return systime * 1000; ++#endif ++#ifdef PLATFORM_WINDOWS ++ return systime / 10000 ; ++#endif ++} ++ ++inline u32 rtw_ms_to_systime(u32 ms) ++{ ++#ifdef PLATFORM_LINUX ++ return ms * HZ / 1000; ++#endif ++#ifdef PLATFORM_FREEBSD ++ return ms /1000; ++#endif ++#ifdef PLATFORM_WINDOWS ++ return ms * 10000 ; ++#endif ++} ++ ++// the input parameter start use the same unit as returned by rtw_get_current_time ++inline s32 rtw_get_passing_time_ms(u32 start) ++{ ++#ifdef PLATFORM_LINUX ++ return rtw_systime_to_ms(jiffies-start); ++#endif ++#ifdef PLATFORM_FREEBSD ++ return rtw_systime_to_ms(rtw_get_current_time()); ++#endif ++#ifdef PLATFORM_WINDOWS ++ LARGE_INTEGER SystemTime; ++ NdisGetCurrentSystemTime(&SystemTime); ++ return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ; ++#endif ++} ++ ++inline s32 rtw_get_time_interval_ms(u32 start, u32 end) ++{ ++#ifdef PLATFORM_LINUX ++ return rtw_systime_to_ms(end-start); ++#endif ++#ifdef PLATFORM_FREEBSD ++ return rtw_systime_to_ms(rtw_get_current_time()); ++#endif ++#ifdef PLATFORM_WINDOWS ++ return rtw_systime_to_ms(end-start); ++#endif ++} ++ ++ ++void rtw_sleep_schedulable(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ u32 delta; ++ ++ delta = (ms * HZ)/1000;//(ms) ++ if (delta == 0) { ++ delta = 1;// 1 ms ++ } ++ set_current_state(TASK_INTERRUPTIBLE); ++ if (schedule_timeout(delta) != 0) { ++ return ; ++ } ++ return; ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ DELAY(ms*1000); ++ return ; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++} ++ ++ ++void rtw_msleep_os(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ msleep((unsigned int)ms); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ //Delay for delay microseconds ++ DELAY(ms*1000); ++ return ; ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void rtw_usleep_os(int us) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ // msleep((unsigned int)us); ++ if ( 1 < (us/1000) ) ++ msleep(1); ++ else ++ msleep( (us/1000) + 1); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ //Delay for delay microseconds ++ DELAY(us); ++ ++ return ; ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(us); //(us) ++ ++#endif ++ ++ ++} ++ ++ ++#ifdef DBG_DELAY_OS ++void _rtw_mdelay_os(int ms, const char *func, const int line) ++{ ++ #if 0 ++ if(ms>10) ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); ++ rtw_msleep_os(ms); ++ return; ++ #endif ++ ++ ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); ++ ++#if defined(PLATFORM_LINUX) ++ ++ mdelay((unsigned long)ms); ++ ++#elif defined(PLATFORM_WINDOWS) ++ ++ NdisStallExecution(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void _rtw_udelay_os(int us, const char *func, const int line) ++{ ++ ++ #if 0 ++ if(us > 1000) { ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); ++ rtw_usleep_os(us); ++ return; ++ } ++ #endif ++ ++ ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); ++ ++ ++#if defined(PLATFORM_LINUX) ++ ++ udelay((unsigned long)us); ++ ++#elif defined(PLATFORM_WINDOWS) ++ ++ NdisStallExecution(us); //(us) ++ ++#endif ++ ++} ++#else ++void rtw_mdelay_os(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ mdelay((unsigned long)ms); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ DELAY(ms*1000); ++ return ; ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisStallExecution(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void rtw_udelay_os(int us) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ udelay((unsigned long)us); ++ ++#endif ++#ifdef PLATFORM_FREEBSD ++ //Delay for delay microseconds ++ DELAY(us); ++ return ; ++#endif ++#ifdef PLATFORM_WINDOWS ++ ++ NdisStallExecution(us); //(us) ++ ++#endif ++ ++} ++#endif ++ ++void rtw_yield_os() ++{ ++#ifdef PLATFORM_LINUX ++ yield(); ++#endif ++#ifdef PLATFORM_FREEBSD ++ yield(); ++#endif ++#ifdef PLATFORM_WINDOWS ++ SwitchToThread(); ++#endif ++} ++ ++#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" ++#define RTW_SUSPEND_EXT_LOCK_NAME "rtw_wifi_ext" ++ ++ ++#ifdef CONFIG_WAKELOCK ++static struct wake_lock rtw_suspend_lock; ++static struct wake_lock rtw_suspend_ext_lock; ++#elif defined(CONFIG_ANDROID_POWER) ++static android_suspend_lock_t rtw_suspend_lock ={ ++ .name = RTW_SUSPEND_LOCK_NAME ++}; ++static android_suspend_lock_t rtw_suspend_ext_lock ={ ++ .name = RTW_SUSPEND_EXT_LOCK_NAME ++}; ++#endif ++ ++inline void rtw_suspend_lock_init() ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); ++ wake_lock_init(&rtw_suspend_ext_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_EXT_LOCK_NAME); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_init_suspend_lock(&rtw_suspend_lock); ++ android_init_suspend_ext_lock(&rtw_suspend_ext_lock); ++ #endif ++} ++ ++inline void rtw_suspend_lock_uninit() ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_destroy(&rtw_suspend_lock); ++ wake_lock_destroy(&rtw_suspend_ext_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_uninit_suspend_lock(&rtw_suspend_lock); ++ android_uninit_suspend_lock(&rtw_suspend_ext_lock); ++ #endif ++} ++ ++inline void rtw_lock_suspend() ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock(&rtw_suspend_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_lock_suspend(&rtw_suspend_lock); ++ #endif ++ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); ++ #endif ++} ++ ++inline void rtw_unlock_suspend() ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_unlock(&rtw_suspend_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_unlock_suspend(&rtw_suspend_lock); ++ #endif ++ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); ++ #endif ++} ++ ++inline void rtw_lock_suspend_timeout(u32 timeout_ms) ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); ++ #endif ++} ++ ++inline void rtw_lock_ext_suspend_timeout(u32 timeout_ms) ++{ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_timeout(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_lock_suspend_auto_expire(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); ++ #endif ++} ++ ++inline void ATOMIC_SET(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_set(v,i); ++ #elif defined(PLATFORM_WINDOWS) ++ *v=i;// other choice???? ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_set_int(v,i); ++ #endif ++} ++ ++inline int ATOMIC_READ(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_read(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return *v; // other choice???? ++ #elif defined(PLATFORM_FREEBSD) ++ return atomic_load_acq_32(v); ++ #endif ++} ++ ++inline void ATOMIC_ADD(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_add(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedAdd(v,i); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_add_int(v,i); ++ #endif ++} ++inline void ATOMIC_SUB(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_sub(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedAdd(v,-i); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_subtract_int(v,i); ++ #endif ++} ++ ++inline void ATOMIC_INC(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_inc(v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedIncrement(v); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_add_int(v,1); ++ #endif ++} ++ ++inline void ATOMIC_DEC(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_dec(v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedDecrement(v); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_subtract_int(v,1); ++ #endif ++} ++ ++inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_add_return(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedAdd(v,i); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_add_int(v,i); ++ return atomic_load_acq_32(v); ++ #endif ++} ++ ++inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_sub_return(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedAdd(v,-i); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_subtract_int(v,i); ++ return atomic_load_acq_32(v); ++ #endif ++} ++ ++inline int ATOMIC_INC_RETURN(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_inc_return(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedIncrement(v); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_add_int(v,1); ++ return atomic_load_acq_32(v); ++ #endif ++} ++ ++inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_dec_return(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedDecrement(v); ++ #elif defined(PLATFORM_FREEBSD) ++ atomic_subtract_int(v,1); ++ return atomic_load_acq_32(v); ++ #endif ++} ++ ++ ++#ifdef PLATFORM_LINUX ++/* ++* Open a file with the specific @param path, @param flag, @param mode ++* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success ++* @param path the path of the file to open ++* @param flag file operation flags, please refer to linux document ++* @param mode please refer to linux document ++* @return Linux specific error code ++*/ ++static int openFile(struct file **fpp, char *path, int flag, int mode) ++{ ++ struct file *fp; ++ ++ fp=filp_open(path, flag, mode); ++ if(IS_ERR(fp)) { ++ *fpp=NULL; ++ return PTR_ERR(fp); ++ } ++ else { ++ *fpp=fp; ++ return 0; ++ } ++} ++ ++/* ++* Close the file with the specific @param fp ++* @param fp the pointer of struct file to close ++* @return always 0 ++*/ ++static int closeFile(struct file *fp) ++{ ++ filp_close(fp,NULL); ++ return 0; ++} ++ ++static int readFile(struct file *fp,char *buf,int len) ++{ ++ int rlen=0, sum=0; ++ ++ if (!fp->f_op || !fp->f_op->read) ++ return -EPERM; ++ ++ while(sumf_op->read(fp,buf+sum,len-sum, &fp->f_pos); ++ if(rlen>0) ++ sum+=rlen; ++ else if(0 != rlen) ++ return rlen; ++ else ++ break; ++ } ++ ++ return sum; ++ ++} ++ ++static int writeFile(struct file *fp,char *buf,int len) ++{ ++ int wlen=0, sum=0; ++ ++ if (!fp->f_op || !fp->f_op->write) ++ return -EPERM; ++ ++ while(sumf_op->write(fp,buf+sum,len-sum, &fp->f_pos); ++ if(wlen>0) ++ sum+=wlen; ++ else if(0 != wlen) ++ return wlen; ++ else ++ break; ++ } ++ ++ return sum; ++ ++} ++ ++/* ++* Test if the specifi @param path is a file and readable ++* @param path the path of the file to test ++* @return Linux specific error code ++*/ ++static int isFileReadable(char *path) ++{ ++ struct file *fp; ++ int ret = 0; ++ mm_segment_t oldfs; ++ char buf; ++ ++ fp=filp_open(path, O_RDONLY, 0); ++ if(IS_ERR(fp)) { ++ ret = PTR_ERR(fp); ++ } ++ else { ++ oldfs = get_fs(); set_fs(get_ds()); ++ ++ if(1!=readFile(fp, &buf, 1)) ++ ret = PTR_ERR(fp); ++ ++ set_fs(oldfs); ++ filp_close(fp,NULL); ++ } ++ return ret; ++} ++ ++/* ++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most ++* @param path the path of the file to open and read ++* @param buf the starting address of the buffer to store file content ++* @param sz how many bytes to read at most ++* @return the byte we've read, or Linux specific error code ++*/ ++static int retriveFromFile(char *path, u8* buf, u32 sz) ++{ ++ int ret =-1; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && buf) { ++ if( 0 == (ret=openFile(&fp,path, O_RDONLY, 0)) ){ ++ DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); ++ ++ oldfs = get_fs(); set_fs(get_ds()); ++ ret=readFile(fp, buf, sz); ++ set_fs(oldfs); ++ closeFile(fp); ++ ++ DBG_871X("%s readFile, ret:%d\n",__FUNCTION__, ret); ++ ++ } else { ++ DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); ++ } ++ } else { ++ DBG_871X("%s NULL pointer\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/* ++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file ++* @param path the path of the file to open and write ++* @param buf the starting address of the data to write into file ++* @param sz how many bytes to write at most ++* @return the byte we've written, or Linux specific error code ++*/ ++static int storeToFile(char *path, u8* buf, u32 sz) ++{ ++ int ret =0; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && buf) { ++ if( 0 == (ret=openFile(&fp, path, O_CREAT|O_WRONLY, 0666)) ) { ++ DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); ++ ++ oldfs = get_fs(); set_fs(get_ds()); ++ ret=writeFile(fp, buf, sz); ++ set_fs(oldfs); ++ closeFile(fp); ++ ++ DBG_871X("%s writeFile, ret:%d\n",__FUNCTION__, ret); ++ ++ } else { ++ DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); ++ } ++ } else { ++ DBG_871X("%s NULL pointer\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++#endif //PLATFORM_LINUX ++ ++/* ++* Test if the specifi @param path is a file and readable ++* @param path the path of the file to test ++* @return _TRUE or _FALSE ++*/ ++int rtw_is_file_readable(char *path) ++{ ++#ifdef PLATFORM_LINUX ++ if(isFileReadable(path) == 0) ++ return _TRUE; ++ else ++ return _FALSE; ++#else ++ //Todo... ++ return _FALSE; ++#endif ++} ++ ++/* ++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most ++* @param path the path of the file to open and read ++* @param buf the starting address of the buffer to store file content ++* @param sz how many bytes to read at most ++* @return the byte we've read ++*/ ++int rtw_retrive_from_file(char *path, u8* buf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ int ret =retriveFromFile(path, buf, sz); ++ return ret>=0?ret:0; ++#else ++ //Todo... ++ return 0; ++#endif ++} ++ ++/* ++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file ++* @param path the path of the file to open and write ++* @param buf the starting address of the data to write into file ++* @param sz how many bytes to write at most ++* @return the byte we've written ++*/ ++int rtw_store_to_file(char *path, u8* buf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ int ret =storeToFile(path, buf, sz); ++ return ret>=0?ret:0; ++#else ++ //Todo... ++ return 0; ++#endif ++} ++ ++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR ++#ifdef PLATFORM_LINUX ++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) ++{ ++ struct net_device *pnetdev; ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); ++#else ++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++#endif ++ if (!pnetdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(pnetdev); ++ pnpi->priv=old_priv; ++ pnpi->sizeof_priv=sizeof_priv; ++ ++RETURN: ++ return pnetdev; ++} ++ ++struct net_device *rtw_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *pnetdev; ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++ pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); ++#else ++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++#endif ++ if (!pnetdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(pnetdev); ++ ++ pnpi->priv = rtw_zvmalloc(sizeof_priv); ++ if (!pnpi->priv) { ++ free_netdev(pnetdev); ++ pnetdev = NULL; ++ goto RETURN; ++ } ++ ++ pnpi->sizeof_priv=sizeof_priv; ++RETURN: ++ return pnetdev; ++} ++ ++void rtw_free_netdev(struct net_device * netdev) ++{ ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++ if(!netdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(netdev); ++ ++ if(!pnpi->priv) ++ goto RETURN; ++ ++ rtw_vmfree(pnpi->priv, pnpi->sizeof_priv); ++ free_netdev(netdev); ++ ++RETURN: ++ return; ++} ++ ++/* ++* Jeff: this function should be called under ioctl (rtnl_lock is accquired) while ++* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ++*/ ++int rtw_change_ifname(_adapter *padapter, const char *ifname) ++{ ++ struct net_device *pnetdev; ++ struct net_device *cur_pnetdev = padapter->pnetdev; ++ struct rereg_nd_name_data *rereg_priv; ++ int ret; ++ ++ if(!padapter) ++ goto error; ++ ++ rereg_priv = &padapter->rereg_nd_name_priv; ++ ++ //free the old_pnetdev ++ if(rereg_priv->old_pnetdev) { ++ free_netdev(rereg_priv->old_pnetdev); ++ rereg_priv->old_pnetdev = NULL; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++ if(!rtnl_is_locked()) ++ unregister_netdev(cur_pnetdev); ++ else ++#endif ++ unregister_netdevice(cur_pnetdev); ++ ++ rtw_proc_remove_one(cur_pnetdev); ++ ++ rereg_priv->old_pnetdev=cur_pnetdev; ++ ++ pnetdev = rtw_init_netdev(padapter); ++ if (!pnetdev) { ++ ret = -1; ++ goto error; ++ } ++ ++ SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter))); ++ ++ rtw_init_netdev_name(pnetdev, ifname); ++ ++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++ if(!rtnl_is_locked()) ++ ret = register_netdev(pnetdev); ++ else ++#endif ++ ret = register_netdevice(pnetdev); ++ ++ if ( ret != 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); ++ goto error; ++ } ++ ++ rtw_proc_init_one(pnetdev); ++ ++ return 0; ++ ++error: ++ ++ return -1; ++ ++} ++#endif ++#endif //MEM_ALLOC_REFINE_ADAPTOR ++ ++#ifdef PLATFORM_FREEBSD ++/* ++ * Copy a buffer from userspace and write into kernel address ++ * space. ++ * ++ * This emulation just calls the FreeBSD copyin function (to ++ * copy data from user space buffer into a kernel space buffer) ++ * and is designed to be used with the above io_write_wrapper. ++ * ++ * This function should return the number of bytes not copied. ++ * I.e. success results in a zero value. ++ * Negative error values are not returned. ++ */ ++unsigned long ++copy_from_user(void *to, const void *from, unsigned long n) ++{ ++ if ( copyin(from, to, n) != 0 ) { ++ /* Any errors will be treated as a failure ++ to copy any of the requested bytes */ ++ return n; ++ } ++ ++ return 0; ++} ++ ++unsigned long ++copy_to_user(void *to, const void *from, unsigned long n) ++{ ++ if ( copyout(from, to, n) != 0 ) { ++ /* Any errors will be treated as a failure ++ to copy any of the requested bytes */ ++ return n; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * The usb_register and usb_deregister functions are used to register ++ * usb drivers with the usb subsystem. In this compatibility layer ++ * emulation a list of drivers (struct usb_driver) is maintained ++ * and is used for probing/attaching etc. ++ * ++ * usb_register and usb_deregister simply call these functions. ++ */ ++int ++usb_register(struct usb_driver *driver) ++{ ++ rtw_usb_linux_register(driver); ++ return 0; ++} ++ ++ ++int ++usb_deregister(struct usb_driver *driver) ++{ ++ rtw_usb_linux_deregister(driver); ++ return 0; ++} ++ ++void module_init_exit_wrapper(void *arg) ++{ ++ int (*func)(void) = arg; ++ func(); ++ return; ++} ++ ++#endif //PLATFORM_FREEBSD ++ ++#ifdef CONFIG_PLATFORM_SPRD ++#ifdef do_div ++#undef do_div ++#endif ++#include ++#endif ++ ++u64 rtw_modular64(u64 x, u64 y) ++{ ++#ifdef PLATFORM_LINUX ++ return do_div(x, y); ++#elif defined(PLATFORM_WINDOWS) ++ return (x % y); ++#elif defined(PLATFORM_FREEBSD) ++ return (x %y); ++#endif ++} ++ ++u64 rtw_division64(u64 x, u64 y) ++{ ++#ifdef PLATFORM_LINUX ++ do_div(x, y); ++ return x; ++#elif defined(PLATFORM_WINDOWS) ++ return (x / y); ++#elif defined(PLATFORM_FREEBSD) ++ return (x / y); ++#endif ++} ++ ++void rtw_buf_free(u8 **buf, u32 *buf_len) ++{ ++ u32 ori_len; ++ ++ if (!buf || !buf_len) ++ return; ++ ++ ori_len = *buf_len; ++ ++ if (*buf) { ++ u32 tmp_buf_len = *buf_len; ++ *buf_len = 0; ++ rtw_mfree(*buf, tmp_buf_len); ++ *buf = NULL; ++ } ++} ++ ++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len) ++{ ++ u32 ori_len = 0, dup_len = 0; ++ u8 *ori = NULL; ++ u8 *dup = NULL; ++ ++ if (!buf || !buf_len) ++ return; ++ ++ if (!src || !src_len) ++ goto keep_ori; ++ ++ /* duplicate src */ ++ dup = rtw_malloc(src_len); ++ if (dup) { ++ dup_len = src_len; ++ _rtw_memcpy(dup, src, dup_len); ++ } ++ ++keep_ori: ++ ori = *buf; ++ ori_len = *buf_len; ++ ++ /* replace buf with dup */ ++ *buf_len = 0; ++ *buf = dup; ++ *buf_len = dup_len; ++ ++ /* free ori */ ++ if (ori && ori_len > 0) ++ rtw_mfree(ori, ori_len); ++} ++ ++ ++/** ++ * rtw_cbuf_full - test if cbuf is full ++ * @cbuf: pointer of struct rtw_cbuf ++ * ++ * Returns: _TRUE if cbuf is full ++ */ ++inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf) ++{ ++ return (cbuf->write == cbuf->read-1)? _TRUE : _FALSE; ++} ++ ++/** ++ * rtw_cbuf_empty - test if cbuf is empty ++ * @cbuf: pointer of struct rtw_cbuf ++ * ++ * Returns: _TRUE if cbuf is empty ++ */ ++inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf) ++{ ++ return (cbuf->write == cbuf->read)? _TRUE : _FALSE; ++} ++ ++/** ++ * rtw_cbuf_push - push a pointer into cbuf ++ * @cbuf: pointer of struct rtw_cbuf ++ * @buf: pointer to push in ++ * ++ * Lock free operation, be careful of the use scheme ++ * Returns: _TRUE push success ++ */ ++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf) ++{ ++ if (rtw_cbuf_full(cbuf)) ++ return _FAIL; ++ ++ if (0) ++ DBG_871X("%s on %u\n", __func__, cbuf->write); ++ cbuf->bufs[cbuf->write] = buf; ++ cbuf->write = (cbuf->write+1)%cbuf->size; ++ ++ return _SUCCESS; ++} ++ ++/** ++ * rtw_cbuf_pop - pop a pointer from cbuf ++ * @cbuf: pointer of struct rtw_cbuf ++ * ++ * Lock free operation, be careful of the use scheme ++ * Returns: pointer popped out ++ */ ++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf) ++{ ++ void *buf; ++ if (rtw_cbuf_empty(cbuf)) ++ return NULL; ++ ++ if (0) ++ DBG_871X("%s on %u\n", __func__, cbuf->read); ++ buf = cbuf->bufs[cbuf->read]; ++ cbuf->read = (cbuf->read+1)%cbuf->size; ++ ++ return buf; ++} ++ ++/** ++ * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization ++ * @size: size of pointer ++ * ++ * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure ++ */ ++struct rtw_cbuf *rtw_cbuf_alloc(u32 size) ++{ ++ struct rtw_cbuf *cbuf; ++ ++ cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void*)*size); ++ ++ if (cbuf) { ++ cbuf->write = cbuf->read = 0; ++ cbuf->size = size; ++ } ++ ++ return cbuf; ++} ++ ++/** ++ * rtw_cbuf_free - free the given rtw_cbuf ++ * @cbuf: pointer of struct rtw_cbuf to free ++ */ ++void rtw_cbuf_free(struct rtw_cbuf *cbuf) ++{ ++ rtw_mfree((u8*)cbuf, sizeof(*cbuf) + sizeof(void*)*cbuf->size); ++} ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/runwpa b/drivers/net/wireless/rtl818x/rtl8189/runwpa +new file mode 100644 +index 00000000..f825e8bd +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/runwpa +@@ -0,0 +1,20 @@ ++#!/bin/bash ++ ++if [ "`which iwconfig`" = "" ] ; then ++ echo "WARNING:Wireless tool not exist!" ++ echo " Please install it!" ++ exit ++else ++ if [ `uname -r | cut -d. -f2` -eq 4 ]; then ++ wpa_supplicant -D ipw -c wpa1.conf -i wlan0 ++ else ++ if [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt 18 ] ; then ++ wpa_supplicant -D ipw -c wpa1.conf -i wlan0 ++ else ++ wpa_supplicant -D wext -c wpa1.conf -i wlan0 ++ fi ++ ++ fi ++fi ++ ++ +diff --git a/drivers/net/wireless/rtl818x/rtl8189/wlan0dhcp b/drivers/net/wireless/rtl818x/rtl8189/wlan0dhcp +new file mode 100644 +index 00000000..60433829 +--- /dev/null ++++ b/drivers/net/wireless/rtl818x/rtl8189/wlan0dhcp +@@ -0,0 +1,16 @@ ++#!/bin/bash ++ ++var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'` ++ ++kill $var0 ++cp ifcfg-wlan0 /etc/sysconfig/network-scripts/ ++ ++dhclient wlan0 ++ ++var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'` ++ ++ ++rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0 ++ ++echo "get ip: $var1" ++ +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index 8c8377d5..8f99de1a 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1087,4 +1087,26 @@ config RTC_DRV_LOONGSON1 + This driver can also be built as a module. If so, the module + will be called rtc-ls1x. + ++config RTC_DRV_GOKE ++ tristate "goke ipc RTC" ++ depends on GK_RTC ++ help ++ RTC (Realtime Clock) driver for goke ipc. ++choice ++ prompt "Select RTC clock" ++ depends on RTC_DRV_GOKE ++ default CLOCK_24M ++ help ++ Select board base on goke ipc ++ ++config CLOCK_32K ++ bool "32k HZ" ++ help ++ Select Goke goke ipc RTC CLOCK 32k ++ ++config CLOCK_24M ++ bool "24M HZ" ++ help ++ Select Goke goke ipc RTC CLOCK 24M ++endchoice + endif # RTC_CLASS +diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile +index 727ae778..61936a30 100644 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -111,3 +111,7 @@ obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o + obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o + obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o + obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o ++ifdef CONFIG_RTC_DRV_GOKE ++obj-$(CONFIG_GK_RTC_V1_00) += rtc-gk_v1_00.o ++endif ++ +diff --git a/drivers/rtc/rtc-gk_v1_00.c b/drivers/rtc/rtc-gk_v1_00.c +new file mode 100644 +index 00000000..6b0db1ab +--- /dev/null ++++ b/drivers/rtc/rtc-gk_v1_00.c +@@ -0,0 +1,320 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ADDR_SHIFT 2 ++ ++#define PWRMGR_BASE GK_VA_PMU_RTC ++ ++#define MCU_RTC_BASE (PWRMGR_BASE + (0x0000 << ADDR_SHIFT)) ++#define MCU_SYS_BASE (PWRMGR_BASE + (0x2800 << ADDR_SHIFT)) ++ ++/* System configure 17 register */ ++#define SYS_REG_CFG17 (MCU_SYS_BASE + (0x0011 << ADDR_SHIFT)) ++#define CFG17_RTC_CLK_SEL_32K (1<<0) ++#define CFG17_RTC_CLK_SEL_24M (0<<0) ++#define CFG17_RTC_SOFT_RESET (1<<1) ++ ++/********************************/ ++/* RTC Register List */ ++/********************************/ ++#define RTC_SYS_CONFIG (MCU_RTC_BASE + (0x00 << ADDR_SHIFT)) ++#define RTC_IRQ_ENABLE (1<<5) ++#define RTC_PAUSE_ENABLE (1<<4) ++#define RTC_STOP_ENABLE (1<<3) ++#define RTC_ENABLE (1<<0) ++ ++#define RTC_P_SCALER_DIV0 (MCU_RTC_BASE + (0x01 << ADDR_SHIFT)) ++#define RTC_P_SCALER_DIV1 (MCU_RTC_BASE + (0x02 << ADDR_SHIFT)) ++#define RTC_P_SCALER_DIV2 (MCU_RTC_BASE + (0x03 << ADDR_SHIFT)) ++#define RTC_P_SCALER_DIV3 (MCU_RTC_BASE + (0x04 << ADDR_SHIFT)) ++ ++#define RTC_PRE_LOAD_HOUR (MCU_RTC_BASE + (0x05 << ADDR_SHIFT)) ++#define RTC_PRE_LOAD_MIN (MCU_RTC_BASE + (0x06 << ADDR_SHIFT)) ++#define RTC_PRE_LOAD_SEC (MCU_RTC_BASE + (0x07 << ADDR_SHIFT)) ++ ++#define RTC_IRQ_CLEAR (MCU_RTC_BASE + (0x08 << ADDR_SHIFT)) ++#define RTC_IRQ_CLR (1<<0) ++ ++#define RTC_PRE_LOAD_DAY_L (MCU_RTC_BASE + (0x09 << ADDR_SHIFT)) ++#define RTC_PRE_LOAD_DAY_H (MCU_RTC_BASE + (0x0A << ADDR_SHIFT)) ++ ++#define RTC_IRQ_STATUS (MCU_RTC_BASE + (0x1A << ADDR_SHIFT)) ++#define RTC_IRQ_GEN (1<<0) ++ ++#define RTC_HOUR_VALUE (MCU_RTC_BASE + (0x1D << ADDR_SHIFT)) ++#define RTC_MIN_VALUE (MCU_RTC_BASE + (0x1C << ADDR_SHIFT)) ++#define RTC_SEC_VALUE (MCU_RTC_BASE + (0x1B << ADDR_SHIFT)) ++ ++#define RTC_DAY_L_VALUE (MCU_RTC_BASE + (0x1E << ADDR_SHIFT)) ++#define RTC_DAY_H_VALUE (MCU_RTC_BASE + (0x1F << ADDR_SHIFT)) ++ ++static unsigned short gk_rtc_get_day(void); ++ ++static void gk_rtc_set_clock(void) ++{ ++#ifdef CONFIG_CLOCK_32K ++ // 32.768KHz clock ++ gk_mcu_writel( SYS_REG_CFG17, CFG17_RTC_CLK_SEL_32K); ++ gk_mcu_writel( RTC_P_SCALER_DIV3, 0x00); ++ gk_mcu_writel( RTC_P_SCALER_DIV2, 0x00); ++ gk_mcu_writel( RTC_P_SCALER_DIV1, 0x7f); ++ gk_mcu_writel( RTC_P_SCALER_DIV0, 0xff); ++#endif ++ ++#ifdef CONFIG_CLOCK_24M ++ gk_mcu_writel( SYS_REG_CFG17, CFG17_RTC_CLK_SEL_24M); ++ gk_mcu_writel( RTC_P_SCALER_DIV3, 0x01); ++ gk_mcu_writel( RTC_P_SCALER_DIV2, 0x6e); ++ gk_mcu_writel( RTC_P_SCALER_DIV1, 0x35); ++ gk_mcu_writel( RTC_P_SCALER_DIV0, 0xff); ++#endif ++} ++ ++static void gk_rtc_stop(void) ++{ ++ /* clear out the hardware. */ ++ gk_mcu_writel( RTC_SYS_CONFIG, 9); ++ ++} ++ ++static void gk_rtc_reset(void) ++{ ++ unsigned char syscfg17; ++ ++ // config ++ gk_mcu_writel( RTC_SYS_CONFIG, 0x0); ++ gk_mcu_writel( RTC_SYS_CONFIG, (RTC_IRQ_ENABLE | RTC_ENABLE)); ++ ++ //reset rtc ++ syscfg17 = gk_mcu_readl( SYS_REG_CFG17); ++ syscfg17 |= CFG17_RTC_SOFT_RESET; ++ gk_mcu_writel( SYS_REG_CFG17, syscfg17); ++} ++ ++static void gk_rtc_start(void) ++{ ++ unsigned char syscfg17; ++ ++ gk_rtc_set_clock(); ++ printk("rtc start...\n"); ++ //if(gk_rtc_get_day() != 0) return; ++ ++ // config ++ gk_mcu_writel( RTC_SYS_CONFIG, 0x0); ++ gk_mcu_writel( RTC_SYS_CONFIG, (RTC_ENABLE)); ++ ++ syscfg17 = gk_mcu_readl( SYS_REG_CFG17); ++ syscfg17 |= CFG17_RTC_SOFT_RESET; ++ gk_mcu_writel( SYS_REG_CFG17, syscfg17); ++} ++ ++static unsigned short gk_rtc_get_day(void) ++{ ++ unsigned char dayh; ++ unsigned char dayl; ++ ++ dayh = gk_mcu_readl(RTC_DAY_H_VALUE); ++ dayl = gk_mcu_readl(RTC_DAY_L_VALUE); ++ ++ //printk("read day = %d - %d \n", dayh, dayl); ++ ++ return (((unsigned short)dayh << 8)|(unsigned short)dayl); ++} ++ ++static unsigned long gk_rtc_get_time(void) ++{ ++ int h,m,s; ++ ++ h = gk_mcu_readl(RTC_HOUR_VALUE); ++ m = gk_mcu_readl(RTC_MIN_VALUE ); ++ s = gk_mcu_readl(RTC_SEC_VALUE ); ++ ++ //printk("read time: h=%d m=%d s=%d \n", h, m, s); ++ ++ return (unsigned long)((h*3600) + m*60 + s); ++} ++ ++static void gk_rtc_set_day(unsigned short day) ++{ ++ unsigned char dayh; ++ unsigned char dayl; ++ ++ dayh = ((day >> 8) & 0xff); ++ dayl = ((day >> 0) & 0xff); ++ ++ //printk("set dayh=%d dayl=%d \n", dayh, dayl); ++ ++ gk_mcu_writel(RTC_PRE_LOAD_DAY_H, dayh); ++ gk_mcu_writel(RTC_PRE_LOAD_DAY_L, dayl); ++} ++ ++static void gk_rtc_write_time(unsigned char hour, unsigned char min, unsigned char sec) ++{ ++ //printk("set time: h=%d m=%d s=%d \n", hour, min, sec); ++ gk_mcu_writel(RTC_PRE_LOAD_HOUR, hour); ++ gk_mcu_writel(RTC_PRE_LOAD_MIN, min); ++ gk_mcu_writel(RTC_PRE_LOAD_SEC, sec); ++} ++ ++static int gk_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ unsigned long t; ++ unsigned short day; ++ unsigned long sec; ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_config(GPIO_12, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_config(GPIO_12, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++#endif ++ day = gk_rtc_get_day(); ++ sec = gk_rtc_get_time(); ++ ++ t = day * 3600 * 24 + sec; ++ printk("os read tm: t=%ld \n", t); ++ rtc_time_to_tm(t, tm); ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // release pmu controller & reset pmu ++ gk_mcu_writel(GK_VA_PMU + 0xA05C, PMU_ALWAYS_RUNNING); ++ gk_mcu_writel(GK_VA_PMU + 0xA02C, 0xB2); // 1011 0010 ++ gk_mcu_writel(GK_VA_PMU + 0xA02C, 0x63); // 0110 0011 ++#endif ++ return rtc_valid_tm(tm); ++} ++ ++static int gk_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ unsigned long t; ++ unsigned short day; ++ unsigned long left; ++ unsigned char h,m,s; ++ ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // get pmu controller ++ gk_gpio_config(GPIO_12, GPIO_TYPE_OUTPUT_1); ++ msleep(1); ++ gk_gpio_config(GPIO_12, GPIO_TYPE_OUTPUT_0); ++ msleep(1); ++#endif ++ rtc_tm_to_time(tm, &t); ++ ++ day = t / (3600*24); ++ left = t % (3600*24); ++ ++ h = left / 3600; ++ left = left % 3600; ++ ++ m = left /60; ++ s = left % 60; ++ ++ printk("os set time: day=%d h=%d m=%d s=%d t=%ld\n", day, h, m, s, t); ++ ++ gk_rtc_stop(); ++ gk_rtc_set_day(day); ++ gk_rtc_write_time(h, m, s); ++ // Steven Yu: use start replace reset. ++ //gk_rtc_reset(); ++ gk_rtc_start(); ++ ++#ifdef CONFIG_PMU_ALWAYS_RUNNING ++ // release pmu controller & reset pmu ++ gk_mcu_writel(GK_VA_PMU + 0xA05C, PMU_ALWAYS_RUNNING); ++ gk_mcu_writel(GK_VA_PMU + 0xA02C, 0xB2); // 1011 0010 ++ gk_mcu_writel(GK_VA_PMU + 0xA02C, 0x63); // 0110 0011 ++#endif ++ return 0; ++} ++ ++static struct rtc_class_ops gk_rtc_ops = ++{ ++ .read_time = gk_rtc_read_time, ++ .set_time = gk_rtc_set_time, ++}; ++ ++ ++ ++static int __devinit gk_rtc_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtcdev; ++ ++ int ret; ++ ++ ++ printk("rtc base: 0x%x \n", MCU_RTC_BASE); ++ ++ //gk_rtc_stop(); ++ ++ // Steven Yu: do not reset rtc, otherwise the time would be reset or stop. ++ // start rtc in gk_rtc_set_time ++ //gk_rtc_start(); ++ ++ rtcdev = rtc_device_register("gk-rtc", &pdev->dev, &gk_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtcdev)) ++ { ++ ret = PTR_ERR(rtcdev); ++ goto out_err; ++ } ++ ++ platform_set_drvdata(pdev, rtcdev); ++ ++ return 0; ++ ++out_err: ++ return ret; ++} ++ ++static int __devexit gk_rtc_remove(struct platform_device *pdev) ++{ ++ struct rtc_device *rtcdev = platform_get_drvdata(pdev); ++ ++ rtc_device_unregister(rtcdev); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++MODULE_ALIAS("platform:gk_rtc"); ++static struct platform_driver gk_rtc_driver = ++{ ++ .remove = __devexit_p(gk_rtc_remove), ++ .driver = ++ { ++ .name = "gk-rtc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init gk_rtc_init(void) ++{ ++ printk("gk rtc init...\n"); ++ return platform_driver_probe(&gk_rtc_driver, gk_rtc_probe); ++} ++module_init(gk_rtc_init); ++ ++static void __exit gk_rtc_exit(void) ++{ ++ platform_driver_unregister(&gk_rtc_driver); ++} ++module_exit(gk_rtc_exit); ++ ++MODULE_AUTHOR("louis "); ++MODULE_DESCRIPTION("driver for gk internal RTC"); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 00c02403..995da67f 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -452,6 +452,12 @@ config SPI_TLE62X0 + # Add new SPI protocol masters in alphabetical order above this line + # + ++config SPI_GOKE ++ tristate "GOKE IPC SPI Controller" ++ depends on GK_SPI ++ help ++ This selects a driver for the GOKE SPI Controller. ++ + endif # SPI_MASTER + + # (slave support would go here) +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 9d75d219..ac2a9e64 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -10,6 +10,9 @@ obj-$(CONFIG_SPI_MASTER) += spi.o + obj-$(CONFIG_SPI_SPIDEV) += spidev.o + + # SPI master controller drivers (bus) ++ifdef CONFIG_SPI_GOKE ++obj-$(CONFIG_GK_SPI_V1_00) += spi-goke_v1_00.o ++endif + obj-$(CONFIG_SPI_ALTERA) += spi-altera.o + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o + obj-$(CONFIG_SPI_ATH79) += spi-ath79.o +diff --git a/drivers/spi/spi-goke_v1_00.c b/drivers/spi/spi-goke_v1_00.c +new file mode 100644 +index 00000000..87ecd6bb +--- /dev/null ++++ b/drivers/spi/spi-goke_v1_00.c +@@ -0,0 +1,1479 @@ ++/* ++ * linux/drivers/spi/spi_goke_v1_00.c ++ * ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SPI_USE_IRQ 1 ++#define SPI_DUMP_DATA 0 ++/*============================Global Variables================================*/ ++extern void v6_dma_flush_range(unsigned long start, unsigned long end); ++extern void v6_flush_kern_cache_all(void); ++ ++struct gk_spi { ++ u32 regbase; ++ struct gk_spi_platform_info *pinfo; ++ ++ int irq; ++ struct tasklet_struct tasklet; ++ ++ spinlock_t lock; ++ struct list_head queue; ++ u32 idle; ++ u32 shutdown; ++ ++ struct spi_device *c_dev; ++ struct spi_message *c_msg; ++ struct spi_transfer *c_xfer; ++ ++ u8 rw_mode, bpw, chip_select; ++ u32 ridx, widx, len; ++}; ++ ++struct gk_spi_private { ++ struct spi_device *spi; ++ struct mutex mtx; ++ spinlock_t lock; ++}; ++ ++static struct { ++ int cs_num; ++ struct gk_spi_private *data; ++} gk_spi_private_devices[SPI_MASTER_INSTANCES]; ++ ++static void gk_spi_handle_message(struct gk_spi *); ++static void gk_spi_prepare_message(struct gk_spi *); ++static void gk_spi_prepare_transfer(struct gk_spi *); ++static void gk_spi_finish_transfer(struct gk_spi *); ++static void gk_spi_finish_message(struct gk_spi *); ++static void gk_spi_start_transfer(struct gk_spi *); ++/*============================SPI Bus Driver==================================*/ ++static int gk_spi_setup(struct spi_device *spi) ++{ ++ return 0; ++} ++ ++static void gk_spi_cleanup(struct spi_device *spi) ++{ ++ return; ++} ++ ++static inline void gk_spi_chipselect(struct gk_spi *priv, int is_active) ++{ ++#if SPI_USE_IRQ ++ gk_spi_writel(priv->regbase + SPI_SER_OFFSET, is_active); ++#endif ++#if 1 ++ if(priv->c_dev) ++ { ++ gk_gpio_set_out(priv->pinfo->cs_pins[0], ++ (priv->c_dev->mode & SPI_CS_HIGH) ? GPIO_HIGH : GPIO_LOW); ++ } ++#endif ++} ++ ++static int gk_spi_stop(struct gk_spi *priv) ++{ ++ gk_spi_readl(priv->regbase + SPI_ICR_OFFSET); ++ gk_spi_readl(priv->regbase + SPI_ISR_OFFSET); ++ gk_spi_chipselect(priv, 0); ++ gk_spi_writel(priv->regbase + SPI_SSIENR_OFFSET, 0); ++ ++ return 0; ++} ++ ++static void gk_spi_start_transfer(struct gk_spi *priv) ++{ ++ void *wbuf,*rbuf; ++ u32 widx, ridx, len; ++ u32 xfer_len; ++ u8 cs_id; ++ u16 i, tmp; ++ ++ wbuf = (void *)priv->c_xfer->tx_buf; ++ rbuf = (void *)priv->c_xfer->rx_buf; ++ len = priv->len; ++ cs_id = priv->c_dev->chip_select; ++ widx = priv->widx; ++ ridx = priv->ridx; ++ //printk("=====[%s %d] %08x %d\n",__func__, __LINE__, priv->regbase, priv->pinfo->cs_pins[0]); ++ ++ /* Feed data into FIFO */ ++ switch (priv->rw_mode) ++ { ++ case SPI_WRITE_ONLY: ++ xfer_len = len - widx; ++#if SPI_USE_IRQ ++ if (xfer_len > priv->pinfo->fifo_entries) ++ xfer_len = priv->pinfo->fifo_entries; ++ gk_spi_chipselect(priv, 1 << cs_id); ++ gk_spi_writel(priv->regbase + SPI_RXFTLR_OFFSET, xfer_len); ++ gk_spi_writel(priv->regbase + SPI_TXFTLR_OFFSET, xfer_len); ++ if (priv->bpw <= 8) ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] W-%d\n",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)wbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ } ++ else ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ } ++#else ++ gk_spi_chipselect(priv, 1 << cs_id); ++ /* Fill the TX FIFO up with the data to be sent */ ++ if (xfer_len < priv->pinfo->fifo_entries) ++ { ++ len = xfer_len; ++ } ++ else ++ { ++ len = priv->pinfo->fifo_entries; ++ } ++ if (priv->bpw <= 8) ++ { ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] W-%d\n",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)wbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ for(i = 0; i < len; i++) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ridx++; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ridx++; ++ len++; ++ } ++ }; ++ } ++ else ++ { ++ for(i = 0; i < len; i++) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ ridx++; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ ridx++; ++ len++; ++ } ++ }; ++ } ++ gk_spi_chipselect(priv, 0); ++#endif ++ break; ++ ++ case SPI_WRITE_READ: ++ xfer_len = len - widx; ++#if SPI_USE_IRQ ++ if (xfer_len > priv->pinfo->fifo_entries) ++ xfer_len = priv->pinfo->fifo_entries; ++ ++ gk_spi_chipselect(priv, 1 << cs_id); ++ gk_spi_writel(priv->regbase + SPI_RXFTLR_OFFSET, xfer_len); ++ gk_spi_writel(priv->regbase + SPI_TXFTLR_OFFSET, xfer_len); ++ if (priv->bpw <= 8) ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] W-%d:",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)wbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ } ++ else ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ } ++#else ++ gk_spi_chipselect(priv, 1 << cs_id); ++ if (xfer_len < priv->pinfo->fifo_entries) ++ { ++ len = xfer_len; ++ } ++ else ++ { ++ len = priv->pinfo->fifo_entries; ++ } ++ if (priv->bpw <= 8) ++ { ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] W-%d:",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)wbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ /* Fill the TX FIFO up with the data to be sent */ ++ for(i = 0; i < len; i++) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u8 *)rbuf)[ridx++] = tmp & 0xff; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, tmp); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u8 *)rbuf)[ridx++] = tmp & 0xff; ++ len++; ++ } ++ }; ++ v6_dma_flush_range(rbuf, rbuf+xfer_len); ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] R-%d:",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)rbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ } ++ else ++ { ++ /* Fill the TX FIFO up with the data to be sent */ ++ for(i = 0; i < len; i++) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ ((u16 *)rbuf)[ridx++] = tmp; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ tmp = ((u16 *)wbuf)[widx++]; ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, tmp); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u16 *)rbuf)[ridx++] = tmp; ++ len++; ++ } ++ }; ++ v6_dma_flush_range(rbuf, rbuf+xfer_len); ++ } ++#endif ++ break; ++ ++ case SPI_READ_ONLY: ++ xfer_len = len - ridx; ++#if SPI_USE_IRQ ++ if (xfer_len > priv->pinfo->fifo_entries) ++ xfer_len = priv->pinfo->fifo_entries; ++ ++ gk_spi_chipselect(priv, 1 << cs_id); ++ gk_spi_writel(priv->regbase + SPI_RXFTLR_OFFSET, xfer_len); ++ gk_spi_writel(priv->regbase + SPI_TXFTLR_OFFSET, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, SPI_DUMMY_DATA); ++#else ++ gk_spi_chipselect(priv, 1 << cs_id); ++ if (xfer_len < priv->pinfo->fifo_entries) ++ { ++ len = xfer_len; ++ } ++ else ++ { ++ len = priv->pinfo->fifo_entries; ++ } ++ ++ if (priv->bpw <= 8) ++ { ++ /* Fill the TX FIFO up with the data to be sent */ ++ for(i = 0; i < len; i++) ++ { ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, SPI_DUMMY_DATA); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u8 *)rbuf)[ridx++] = tmp & 0xff; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ tmp = ((u8 *)wbuf)[widx++]; ++ gk_spi_writeb(priv->regbase + SPI_DR_OFFSET, SPI_DUMMY_DATA); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u8 *)rbuf)[ridx++] = tmp & 0xff; ++ len++; ++ } ++ }; ++ v6_dma_flush_range(rbuf, rbuf+xfer_len); ++ } ++ else ++ { ++ /* Fill the TX FIFO up with the data to be sent */ ++ for(i = 0; i < len; i++) ++ { ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, SPI_DUMMY_DATA); ++ } ++ while (len < xfer_len) ++ { ++ // read data first ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ ((u16 *)rbuf)[ridx++] = tmp; ++ } ++ // FIFO not full ++ tmp = gk_spi_readb(priv->regbase + SPI_TXFLR_OFFSET); ++ if (tmp < (priv->pinfo->fifo_entries/2)) ++ { ++ gk_spi_writew(priv->regbase + SPI_DR_OFFSET, SPI_DUMMY_DATA); ++ len++; ++ } ++ }; ++ // remain data ++ len = ridx - priv->ridx; ++ while (len < xfer_len) ++ { ++ // read data ++ tmp = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (tmp) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u16 *)rbuf)[ridx++] = tmp; ++ len++; ++ } ++ }; ++ v6_dma_flush_range(rbuf, rbuf+xfer_len); ++ } ++ gk_spi_chipselect(priv, 0); ++#endif ++ break; ++ ++ default: ++ break; ++ } ++ ++ priv->widx = widx; ++#if SPI_USE_IRQ ++ enable_irq(priv->irq); ++#else ++ priv->ridx = ridx; ++ gk_spi_finish_transfer(priv); ++#endif ++ return; ++} ++ ++static void gk_spi_tasklet(unsigned long data) ++{ ++ struct gk_spi *priv = (struct gk_spi *)data; ++ void *rbuf; ++ u32 widx, ridx, len; ++ u32 rxflr, xfer_len; ++ u32 status; ++ u16 i, tmp; ++ u32 finish_transfer; ++ ++ /* Wait until SPI idle */ ++ status = gk_spi_readl(priv->regbase + SPI_SR_OFFSET); ++ if (status & 0x1) ++ { ++ /* Transfer is still in progress */ ++ for (i = 0; i < MAX_QUERY_TIMES; i++) ++ { ++ status = gk_spi_readl(priv->regbase + SPI_SR_OFFSET); ++ if (!(status & 0x1)) ++ break; ++ } ++ if (status & 0x1) ++ { ++ tasklet_schedule(&priv->tasklet); ++ return; ++ } ++ } ++ ++ rbuf = (void *)priv->c_xfer->rx_buf; ++ len = priv->len; ++ widx = priv->widx; ++ ridx = priv->ridx; ++ ++ /* Fetch data from FIFO */ ++ switch (priv->rw_mode) ++ { ++ case SPI_WRITE_ONLY: ++ rxflr = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ ++ if (priv->bpw <= 8) ++ { ++ for(i = 0; i < rxflr; i++) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ } ++ } ++ else ++ { ++ for(i = 0; i < rxflr; i++) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ } ++ } ++ ++ break; ++ case SPI_READ_ONLY: ++ case SPI_WRITE_READ: ++ xfer_len = len - ridx; ++ rxflr = gk_spi_readb(priv->regbase + SPI_RXFLR_OFFSET); ++ if (xfer_len > rxflr) ++ { ++ xfer_len = rxflr; ++ } ++ ++ if(priv->bpw <= 8) ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = gk_spi_readb(priv->regbase + SPI_DR_OFFSET); ++ ((u8 *)rbuf)[ridx++] = tmp & 0xff; ++ } ++#if SPI_DUMP_DATA ++ printk("=====[%s %d] R-%d:",__func__, __LINE__, xfer_len); ++ for(i = 0; i < xfer_len; i++) ++ { ++ printk("%02x ", ((u8*)rbuf)[i]); ++ } ++ printk("\n"); ++#endif ++ } ++ else ++ { ++ for(i = 0; i < xfer_len; i++) ++ { ++ tmp = gk_spi_readw(priv->regbase + SPI_DR_OFFSET); ++ ((u16 *)rbuf)[ridx++] = tmp; ++ } ++ } ++ //v6_dma_flush_range(&rbuf[priv->ridx], &rbuf[ridx-1]); ++ priv->ridx = ridx; ++ break; ++ ++ default: ++ break; ++ } ++ ++ /* Check whether the current transfer ends */ ++ finish_transfer = 0; ++ switch (priv->rw_mode) ++ { ++ case SPI_WRITE_ONLY: ++ if (widx == len) ++ { ++ finish_transfer = 1; ++ } ++ break; ++ ++ case SPI_READ_ONLY: ++ if (ridx == len) ++ { ++ finish_transfer = 1; ++ } ++ break; ++ ++ case SPI_WRITE_READ: ++ if (ridx == len && widx == len) ++ { ++ finish_transfer = 1; ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ /* End transfer or continue filling FIFO */ ++ if (finish_transfer) ++ { ++ gk_spi_finish_transfer(priv); ++ enable_irq(priv->irq); ++ } ++ else ++ { ++ gk_spi_start_transfer(priv); ++ } ++} ++ ++static void gk_spi_prepare_transfer(struct gk_spi *priv) ++{ ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ struct gk_spi_cs_config cs_config; ++ u32 ctrlr0; ++ void *wbuf, *rbuf; ++ msg = priv->c_msg; ++ ++ spin_lock(&priv->lock); ++ //if (priv->c_xfer == NULL) ++ { ++ xfer = list_entry(priv->c_msg->transfers.next, struct spi_transfer, transfer_list); ++ } ++ //else ++ { ++ // xfer = list_entry(priv->c_xfer->transfer_list.next, struct spi_transfer, transfer_list); ++ ++ } ++ priv->c_xfer = xfer; ++ //printk("=====[%s %d] %d\n",__func__, __LINE__, priv->c_xfer->speed_hz); ++ list_del(priv->c_msg->transfers.next); ++ spin_unlock(&priv->lock); ++ ++ wbuf = (void *)xfer->tx_buf; ++ rbuf = (void *)xfer->rx_buf; ++ ++ if (priv->bpw <= 8) ++ priv->len = xfer->len; ++ else ++ priv->len = xfer->len >> 1; ++ priv->widx = 0; ++ priv->ridx = 0; ++ if (wbuf && !rbuf) ++ priv->rw_mode = SPI_WRITE_ONLY; ++ if ( !wbuf && rbuf) ++ priv->rw_mode = SPI_READ_ONLY; ++ if (wbuf && rbuf) ++ priv->rw_mode = SPI_WRITE_READ; ++ ++ ctrlr0 = gk_spi_readl(priv->regbase + SPI_CTRLR0_OFFSET); ++ ctrlr0 &= 0xfffff4ff; ++ /* Always use write & read mode due to I1 changes */ ++ ctrlr0 |= (SPI_WRITE_READ << 8); ++ if (priv->c_dev->mode & SPI_LOOP) ++ ctrlr0 |= (0x1 << 11); ++ ++ gk_spi_writel(priv->regbase + SPI_CTRLR0_OFFSET, ctrlr0); ++ ++ if (!priv->chip_select) { ++ cs_config.bus_id = priv->c_dev->master->bus_num; ++ cs_config.cs_id = priv->c_dev->chip_select; ++ cs_config.cs_num = priv->c_dev->master->num_chipselect; ++ cs_config.cs_pins = priv->pinfo->cs_pins; ++ //priv->pinfo->cs_activate(&cs_config); ++ priv->chip_select = 1; ++ } ++ ++ disable_irq_nosync(priv->irq); ++ gk_spi_writel(priv->regbase + SPI_IMR_OFFSET, SPI_TXEIS_MASK); ++ gk_spi_writel(priv->regbase + SPI_SSIENR_OFFSET, 1); ++ gk_spi_chipselect(priv, 0); ++} ++ ++static void gk_spi_finish_transfer(struct gk_spi *priv) ++{ ++ if (priv->c_xfer->cs_change) { ++ struct gk_spi_cs_config cs_config; ++ ++ cs_config.bus_id = priv->c_dev->master->bus_num; ++ cs_config.cs_id = priv->c_msg->spi->chip_select; ++ cs_config.cs_num = priv->c_dev->master->num_chipselect; ++ cs_config.cs_pins = priv->pinfo->cs_pins; ++ ++ priv->pinfo->cs_deactivate(&cs_config); ++ priv->chip_select = 0; ++ } ++ ++ gk_spi_stop(priv); ++ ++ //if (list_is_last(&priv->c_xfer->transfer_list, &priv->c_msg->transfers)) { ++ if (list_empty(&priv->c_msg->transfers)) { ++ gk_spi_finish_message(priv); ++ } ++ else ++ { ++ gk_spi_prepare_transfer(priv); ++ gk_spi_start_transfer(priv); ++ } ++} ++ ++static void gk_spi_finish_message(struct gk_spi *priv) ++{ ++ struct spi_message *msg; ++ unsigned long flags; ++ u32 message_pending; ++ ++ if (priv->chip_select) ++ { ++ struct gk_spi_cs_config cs_config; ++ ++ cs_config.bus_id = priv->c_dev->master->bus_num; ++ cs_config.cs_id = priv->c_msg->spi->chip_select; ++ cs_config.cs_num = priv->c_dev->master->num_chipselect; ++ cs_config.cs_pins = priv->pinfo->cs_pins; ++ ++ priv->pinfo->cs_deactivate(&cs_config); ++ priv->chip_select = 0; ++ } ++ if(priv->c_xfer->rx_buf) ++ { ++ spin_lock(&priv->lock); ++ v6_flush_kern_cache_all(); ++ //v6_dma_flush_range(&priv->c_xfer->rx_buf[0], &priv->c_xfer->rx_buf[priv->c_xfer->len]); ++ spin_unlock(&priv->lock); ++ } ++ msg = priv->c_msg; ++ msg->actual_length = priv->c_xfer->len; ++ msg->status = 0; ++ ++ /* Next Message */ ++ spin_lock_irqsave(&priv->lock, flags); ++ list_del_init(&msg->queue); ++ if (!list_empty(&priv->queue)) ++ { ++ message_pending = 1; ++ } ++ else ++ { ++ message_pending = 0; ++ priv->idle = 1; ++ priv->c_msg = NULL; ++ priv->c_xfer = NULL; ++ } ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (message_pending) ++ { ++ gk_spi_handle_message(priv); ++ } ++ if(priv->c_xfer && priv->c_xfer->rx_buf && priv->c_xfer->len) { ++ v6_dma_flush_range((unsigned long)priv->c_xfer->rx_buf, ++ (u32)priv->c_xfer->rx_buf+priv->c_xfer->len); ++ } ++ msg->complete(msg->context); ++} ++ ++static void gk_spi_handle_message(struct gk_spi *priv) ++{ ++ gk_spi_prepare_message(priv); ++ gk_spi_prepare_transfer(priv); ++ gk_spi_start_transfer(priv); ++} ++ ++static void gk_spi_prepare_message(struct gk_spi *priv) ++{ ++ u32 ctrlr0, ssi_clk, sckdv; ++ struct spi_message *msg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ msg = list_entry(priv->queue.next, struct spi_message, queue); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ctrlr0 = gk_spi_readl(priv->regbase + SPI_CTRLR0_OFFSET); ++ ++ if (msg->spi->bits_per_word < 4) ++ msg->spi->bits_per_word = 4; ++ if (msg->spi->bits_per_word > 16) ++ msg->spi->bits_per_word = 16; ++ priv->bpw = msg->spi->bits_per_word; ++ ++ ctrlr0 &= 0xfffffff0; ++ ctrlr0 |= (priv->bpw - 1); ++ ++ ctrlr0 &= (~((1 << 6) | (1 << 7))); ++ ctrlr0 |= ((msg->spi->mode & (SPI_CPHA | SPI_CPOL)) << 6); ++ if (msg->spi->mode & SPI_LOOP) { ++ ctrlr0 |= 0x00000800; ++ } ++ gk_spi_writel(priv->regbase + SPI_CTRLR0_OFFSET, ctrlr0); ++ ++ //printk("=====[%s %d] %d\n",__func__, __LINE__, priv->c_xfer->speed_hz); ++ ssi_clk = priv->pinfo->get_ssi_freq_hz(); ++ if(msg->spi->max_speed_hz == 0 || msg->spi->max_speed_hz > ssi_clk) ++ msg->spi->max_speed_hz = ssi_clk; ++ ++ sckdv = (u16)(((ssi_clk / msg->spi->max_speed_hz) + 0x01) & 0xfffe); ++ gk_spi_writel(priv->regbase + SPI_BAUDR_OFFSET, sckdv); ++ //gk_spi_writel(priv->regbase + SPI_BAUDR_OFFSET, 0x02); ++ ++ priv->chip_select = 0; ++ priv->c_dev = msg->spi; ++ priv->c_msg = msg; ++} ++ ++static int gk_spi_main_entry(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct gk_spi *priv; ++ struct spi_transfer *xfer; ++ unsigned long flags; ++ u32 shut_down, bus_idle; ++ ++ priv = spi_master_get_devdata(spi->master); ++ spin_lock_irqsave(&priv->lock, flags); ++ shut_down = priv->shutdown; ++ spin_unlock_irqrestore(&priv->lock, flags); ++ if (shut_down) { ++ return -ESHUTDOWN; ++ } ++ ++ /* Validation */ ++ if (list_empty(&msg->transfers) || !spi->max_speed_hz) { ++ return -EINVAL; ++ } ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (!xfer->tx_buf && !xfer->rx_buf) { ++ return -EINVAL; ++ } ++ ++ if (spi->bits_per_word > 8 && (xfer->len & 0x1)) { ++ return -EINVAL; ++ } ++ } ++ ++ /* Queue Message */ ++ msg->status = -EINPROGRESS; ++ msg->actual_length = 0; ++ spin_lock_irqsave(&priv->lock, flags); ++ list_add_tail(&msg->queue, &priv->queue); ++ if (priv->idle) { ++ priv->idle = 0; ++ bus_idle = 1; ++ } else { ++ bus_idle = 0; ++ } ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ /* Handle message right away if bus is idle */ ++ if (bus_idle) { ++ gk_spi_handle_message(priv); ++ } ++ ++ return 0; ++} ++ ++static int gk_spi_inithw(struct gk_spi *priv) ++{ ++ u16 sckdv, i; ++ u32 ctrlr0, ssi_freq; ++ ++ /* Set PLL */ ++ if (priv->pinfo->rct_set_ssi_pll) ++ priv->pinfo->rct_set_ssi_pll(); ++ ++ /* Disable SPI */ ++ gk_spi_stop(priv); ++ ++ /* Config Chip Select Pins */ ++ for (i = 0; i < priv->pinfo->cs_num; i++) { ++ if (priv->pinfo->cs_pins[i] < 0) { ++ continue; ++ } ++ ++ gk_gpio_set_out(priv->pinfo->cs_pins[i], GPIO_HIGH); ++ } ++ ++ /* Initial Register Settings */ ++ ctrlr0 = (( SPI_CFS << 12) | (SPI_WRITE_ONLY << 8) | (SPI_SCPOL << 7) | ++ (SPI_SCPH << 6) | (SPI_FRF << 4) | (SPI_DFS)); ++ gk_spi_writel(priv->regbase + SPI_CTRLR0_OFFSET, ctrlr0); ++ ++ ssi_freq = priv->pinfo->get_ssi_freq_hz(); ++ sckdv = (u16)(((ssi_freq / SPI_BAUD_RATE) + 0x01) & 0xfffe); ++ gk_spi_writel(priv->regbase + SPI_BAUDR_OFFSET, sckdv); ++ ++ gk_spi_writel(priv->regbase + SPI_TXFTLR_OFFSET, 0); ++ gk_spi_writel(priv->regbase + SPI_RXFTLR_OFFSET, 1); ++ gk_spi_writel(priv->regbase + SPI_SER_OFFSET, 1); ++ return 0; ++} ++ ++static irqreturn_t gk_spi_isr(int irq, void *dev_data) ++{ ++ struct gk_spi *priv = dev_data; ++ if (gk_spi_readl(priv->regbase + SPI_ISR_OFFSET)) { ++ disable_irq_nosync(priv->irq); ++ ++ gk_spi_tasklet((unsigned long)priv); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int __devinit gk_spi_probe(struct platform_device *pdev) ++{ ++ struct gk_spi *priv; ++ struct gk_spi_private *ps; ++ struct spi_master *master; ++ struct spi_device *spidev; ++ struct resource *res; ++ struct gk_spi_platform_info *pinfo; ++ int i, irq, errorCode; ++ ++ gk_rct_writel(GK_VA_RCT + 0x0030, 0x01); ++ //gk_rct_writel(GK_VA_RCT + 0x00A0, 0x01); ++ /* Get IRQ NO. */ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ ++ /* Get Platform Info */ ++ pinfo = (struct gk_spi_platform_info *)pdev->dev.platform_data; ++ if (!pinfo) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ if (pinfo->cs_num && !pinfo->cs_pins) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ if (!pinfo->cs_activate || !pinfo->cs_deactivate) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ if (!pinfo->get_ssi_freq_hz) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ ++ /* Get Base Address */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ errorCode = -EINVAL; ++ goto gk_spi_probe_exit3; ++ } ++ ++ /* Alocate Master */ ++ master = spi_alloc_master(&pdev->dev, sizeof *priv); ++ if (!master) { ++ errorCode = -ENOMEM; ++ goto gk_spi_probe_exit3; ++ } ++ ++ /* Initalize Device Data */ ++ master->bus_num = pdev->id; ++ master->num_chipselect = pinfo->cs_num; ++ master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH; ++ master->setup = gk_spi_setup; ++ master->transfer = gk_spi_main_entry; ++ master->cleanup = gk_spi_cleanup; ++ platform_set_drvdata(pdev, master); ++ priv = spi_master_get_devdata(master); ++ priv->regbase = (u32)res->start; ++ priv->irq = irq; ++ priv->pinfo = pinfo; ++ tasklet_init(&priv->tasklet, gk_spi_tasklet, (unsigned long)priv); ++ INIT_LIST_HEAD(&priv->queue); ++ priv->idle = 1; ++ priv->c_dev = NULL; ++ priv->c_msg = NULL; ++ priv->c_xfer = NULL; ++ priv->shutdown = 0; ++ spin_lock_init(&priv->lock); ++ priv->bpw = 16; ++ ++ /* Inittialize Hardware*/ ++ gk_spi_inithw(priv); ++ ++ /* Request IRQ */ ++ errorCode = request_irq(irq, gk_spi_isr, IRQF_TRIGGER_HIGH, ++ dev_name(&pdev->dev), priv); ++ if (errorCode) ++ goto gk_spi_probe_exit2; ++ else ++ dev_info(&pdev->dev, "gk SPI Controller %d created \n", pdev->id); ++ ++ /* Register Master */ ++ errorCode = spi_register_master(master); ++ if (errorCode) ++ goto gk_spi_probe_exit1; ++ ++ /* Allocate Private Devices */ ++ ps = (struct gk_spi_private *)kmalloc(master->num_chipselect * \ ++ sizeof(struct gk_spi_private), GFP_KERNEL); ++ if (!ps) { ++ errorCode = -ENOMEM; ++ goto gk_spi_probe_exit3; ++ } ++ spidev = (struct spi_device *)kmalloc(master->num_chipselect * \ ++ sizeof(struct spi_device), GFP_KERNEL); ++ if (!spidev) { ++ errorCode = -ENOMEM; ++ kfree(ps); ++ goto gk_spi_probe_exit3; ++ } ++ ++ for (i = 0; i < master->num_chipselect; i++) { ++ ps[i].spi = spidev + i; ++ ps[i].spi->master = master; ++ mutex_init(&ps[i].mtx); ++ spin_lock_init(&ps[i].lock); ++ } ++ gk_spi_private_devices[master->bus_num].cs_num = master->num_chipselect; ++ gk_spi_private_devices[master->bus_num].data = ps; ++ goto gk_spi_probe_exit3; ++ ++gk_spi_probe_exit1: ++ free_irq(irq, priv); ++ ++gk_spi_probe_exit2: ++ tasklet_kill(&priv->tasklet); ++ spi_master_put(master); ++ ++gk_spi_probe_exit3: ++ return errorCode; ++} ++ ++static int __devexit gk_spi_remove(struct platform_device *pdev) ++{ ++ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct gk_spi *priv = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ priv->shutdown = 1; ++ spin_unlock_irqrestore(&priv->lock, flags); ++ tasklet_kill(&priv->tasklet); ++ free_irq(priv->irq, priv); ++ gk_spi_stop(priv); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ list_for_each_entry(msg, &priv->queue, queue) ++ { ++ msg->status = -ESHUTDOWN; ++ msg->complete(msg->context); ++ } ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ spi_unregister_master(master); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int gk_spi_suspend_noirq(struct device *dev) ++{ ++ int errorCode = 0; ++ struct spi_master *master; ++ struct gk_spi *priv; ++ struct platform_device *pdev; ++ ++ pdev = to_platform_device(dev); ++ master = platform_get_drvdata(pdev); ++ priv = spi_master_get_devdata(master); ++ ++ if (priv) ++ { ++ //disable_irq(priv->irq); ++ gk_spi_stop(priv); ++ } ++ else ++ { ++ dev_err(&pdev->dev, "Cannot find valid pinfo\n"); ++ errorCode = -ENXIO; ++ } ++ ++ dev_dbg(&pdev->dev, "%s\n", __func__); ++ ++ return errorCode; ++} ++ ++static int gk_spi_resume_noirq(struct device *dev) ++{ ++ int errorCode = 0; ++ struct spi_master *master; ++ struct gk_spi *priv; ++ struct platform_device *pdev; ++ ++ pdev = to_platform_device(dev); ++ master = platform_get_drvdata(pdev); ++ priv = spi_master_get_devdata(master); ++ if (priv) ++ { ++ gk_spi_inithw(priv); ++ //enable_irq(priv->irq); ++ } ++ else ++ { ++ dev_err(&pdev->dev, "Cannot find valid pinfo\n"); ++ errorCode = -ENXIO; ++ } ++ ++ dev_dbg(&pdev->dev, "%s\n", __func__); ++ ++ return errorCode; ++} ++ ++static const struct dev_pm_ops gk_spi_dev_pm_ops = { ++ .suspend_noirq = gk_spi_suspend_noirq, ++ .resume_noirq = gk_spi_resume_noirq, ++}; ++#endif ++ ++static struct platform_driver gk_spi_driver = { ++ .probe = gk_spi_probe, ++ .remove = __devexit_p(gk_spi_remove), ++ .driver = { ++ .name = "spi", ++ .owner = THIS_MODULE, ++#ifdef CONFIG_PM ++ .pm = &gk_spi_dev_pm_ops, ++#endif ++ }, ++}; ++ ++static int __init gk_spi_init(void) ++{ ++ return platform_driver_register(&gk_spi_driver); ++} ++ ++static void __exit gk_spi_exit(void) ++{ ++ platform_driver_unregister(&gk_spi_driver); ++} ++ ++subsys_initcall(gk_spi_init); ++module_exit(gk_spi_exit); ++ ++MODULE_DESCRIPTION("GOKE SPI Driver"); ++MODULE_LICENSE("GPL"); ++ ++ ++/*=================Utilities for Non-GPL Use==================================*/ ++static void gk_spi_complete(void *arg) ++{ ++ complete(arg); ++} ++ ++int gk_spi_write(gk_spi_cfg_t *spi_cfg, gk_spi_write_t *spi_write) ++{ ++ u8 bus_id, cs_id, cs_num; ++ unsigned long flags; ++ int errorCode; ++ struct gk_spi_private *ps; ++ struct spi_device *spi; ++ struct spi_message msg; ++ struct spi_transfer xfer; ++ ++ DECLARE_COMPLETION_ONSTACK(done); ++ ++ /* Validate Input Args */ ++ if (!spi_cfg || !spi_write) ++ return -EINVAL; ++ ++ bus_id = spi_write->bus_id; ++ cs_id = spi_write->cs_id; ++ cs_num = gk_spi_private_devices[bus_id].cs_num; ++ ps = gk_spi_private_devices[bus_id].data; ++ ++ if (bus_id >= SPI_MASTER_INSTANCES || cs_id >= cs_num ++ || !spi_write->buffer || !spi_write->n_size) ++ return -EINVAL; ++ ++ /* Transfer */ ++ memset(&xfer, 0, sizeof(struct spi_transfer)); ++ xfer.tx_buf = spi_write->buffer; ++ xfer.len = spi_write->n_size; ++ xfer.cs_change = spi_cfg->cs_change; ++ ++ /* Message */ ++ memset(&msg, 0, sizeof(struct spi_message)); ++ INIT_LIST_HEAD(&msg.transfers); ++ list_add_tail(&xfer.transfer_list, &msg.transfers); ++ msg.complete = gk_spi_complete; ++ msg.context = &done; ++ spi = ps[cs_id].spi; ++ msg.spi = spi; ++ ++ mutex_lock(&ps[cs_id].mtx); ++ ++ /* Config */ ++ spi->chip_select = cs_id; ++ spi->mode = spi_cfg->spi_mode; ++ spi->mode &= ~SPI_LOOP; ++ spi->bits_per_word = spi_cfg->cfs_dfs; ++ spi->max_speed_hz = spi_cfg->baud_rate; ++ ++ /* Wait */ ++ spin_lock_irqsave(&ps[cs_id].lock, flags); ++ errorCode = spi->master->transfer(spi, &msg); ++ spin_unlock_irqrestore(&ps[cs_id].lock, flags); ++ if (!errorCode) ++ wait_for_completion(&done); ++ ++ mutex_unlock(&ps[cs_id].mtx); ++ ++ return errorCode; ++} ++EXPORT_SYMBOL(gk_spi_write); ++ ++int gk_spi_read(gk_spi_cfg_t *spi_cfg, gk_spi_read_t *spi_read) ++{ ++ u8 bus_id, cs_id, cs_num; ++ unsigned long flags; ++ int errorCode; ++ struct gk_spi_private *ps; ++ struct spi_device *spi; ++ struct spi_message msg; ++ struct spi_transfer xfer; ++ ++ DECLARE_COMPLETION_ONSTACK(done); ++ ++ /* Validate Input Args */ ++ if (!spi_cfg || !spi_read) ++ return -EINVAL; ++ ++ bus_id = spi_read->bus_id; ++ cs_id = spi_read->cs_id; ++ cs_num = gk_spi_private_devices[bus_id].cs_num; ++ ps = gk_spi_private_devices[bus_id].data; ++ if (bus_id >= SPI_MASTER_INSTANCES || cs_id >= cs_num ++ || !spi_read->buffer || !spi_read->n_size) ++ return -EINVAL; ++ ++ /* Transfer */ ++ memset(&xfer, 0, sizeof(struct spi_transfer)); ++ xfer.rx_buf = spi_read->buffer; ++ xfer.len = spi_read->n_size; ++ xfer.cs_change = spi_cfg->cs_change; ++ ++ /* Message */ ++ memset(&msg, 0, sizeof(struct spi_message)); ++ INIT_LIST_HEAD(&msg.transfers); ++ list_add_tail(&xfer.transfer_list, &msg.transfers); ++ msg.complete = gk_spi_complete; ++ msg.context = &done; ++ spi = ps[cs_id].spi; ++ msg.spi = spi; ++ ++ mutex_lock(&ps[cs_id].mtx); ++ ++ /* Config */ ++ spi->chip_select = cs_id; ++ spi->mode = spi_cfg->spi_mode; ++ spi->mode &= ~SPI_LOOP; ++ spi->bits_per_word = spi_cfg->cfs_dfs; ++ spi->max_speed_hz = spi_cfg->baud_rate; ++ ++ /* Wait */ ++ spin_lock_irqsave(&ps[cs_id].lock, flags); ++ errorCode = spi->master->transfer(spi, &msg); ++ spin_unlock_irqrestore(&ps[cs_id].lock, flags); ++ if (!errorCode) ++ wait_for_completion(&done); ++ ++ mutex_unlock(&ps[cs_id].mtx); ++ ++ return errorCode; ++} ++EXPORT_SYMBOL(gk_spi_read); ++ ++int gk_spi_write_then_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_then_read_t *spi_write_then_read) ++{ ++ u8 bus_id, cs_id, cs_num, *buf; ++ u16 size; ++ unsigned long flags; ++ int errorCode; ++ struct gk_spi_private *ps; ++ struct spi_device *spi; ++ struct spi_message msg; ++ struct spi_transfer xfer; ++ ++ DECLARE_COMPLETION_ONSTACK(done); ++ ++ /* Validate Input Args */ ++ if (!spi_cfg || !spi_write_then_read) ++ return -EINVAL; ++ ++ bus_id = spi_write_then_read->bus_id; ++ cs_id = spi_write_then_read->cs_id; ++ cs_num = gk_spi_private_devices[bus_id].cs_num; ++ ps = gk_spi_private_devices[bus_id].data; ++ ++ if (bus_id >= SPI_MASTER_INSTANCES || cs_id >= cs_num ++ || !spi_write_then_read->w_buffer || !spi_write_then_read->w_size ++ || !spi_write_then_read->r_buffer || !spi_write_then_read->r_size) ++ return -EINVAL; ++ ++ /* Prepare Buffer */ ++ size = spi_write_then_read->w_size + spi_write_then_read->r_size; ++ buf = (u8 *)kmalloc(size, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ memcpy(buf, spi_write_then_read->w_buffer, spi_write_then_read->w_size); ++ memset(buf + spi_write_then_read->w_size, SPI_DUMMY_DATA, ++ spi_write_then_read->r_size); ++ ++ /* Transfer */ ++ memset(&xfer, 0, sizeof(struct spi_transfer)); ++ xfer.tx_buf = buf; ++ xfer.rx_buf = buf; ++ xfer.len = size; ++ xfer.cs_change = spi_cfg->cs_change; ++ ++ /* Message */ ++ memset(&msg, 0, sizeof(struct spi_message)); ++ INIT_LIST_HEAD(&msg.transfers); ++ list_add_tail(&xfer.transfer_list, &msg.transfers); ++ msg.complete = gk_spi_complete; ++ msg.context = &done; ++ spi = ps[cs_id].spi; ++ msg.spi = spi; ++ ++ mutex_lock(&ps[cs_id].mtx); ++ ++ /* Config */ ++ spi->chip_select = cs_id; ++ spi->mode = spi_cfg->spi_mode; ++ spi->mode &= ~SPI_LOOP; ++ spi->bits_per_word = spi_cfg->cfs_dfs; ++ spi->max_speed_hz = spi_cfg->baud_rate; ++ ++ /* Wait */ ++ spin_lock_irqsave(&ps[cs_id].lock, flags); ++ errorCode = spi->master->transfer(spi, &msg); ++ spin_unlock_irqrestore(&ps[cs_id].lock, flags); ++ if (!errorCode) ++ wait_for_completion(&done); ++ ++ mutex_unlock(&ps[cs_id].mtx); ++ ++ /* Free Buffer */ ++ memcpy(spi_write_then_read->r_buffer, buf + spi_write_then_read->w_size, ++ spi_write_then_read->r_size); ++ kfree(buf); ++ ++ return errorCode; ++} ++EXPORT_SYMBOL(gk_spi_write_then_read); ++ ++int gk_spi_write_and_read(gk_spi_cfg_t *spi_cfg, ++ gk_spi_write_and_read_t *spi_write_and_read) ++{ ++ u8 bus_id, cs_id, cs_num; ++ unsigned long flags; ++ int errorCode; ++ struct gk_spi_private *ps; ++ struct spi_device *spi; ++ struct spi_message msg; ++ struct spi_transfer xfer; ++ ++ DECLARE_COMPLETION_ONSTACK(done); ++ ++ /* Validate Input Args */ ++ if (!spi_cfg || !spi_write_and_read) ++ return -EINVAL; ++ ++ bus_id = spi_write_and_read->bus_id; ++ cs_id = spi_write_and_read->cs_id; ++ cs_num = gk_spi_private_devices[bus_id].cs_num; ++ ps = gk_spi_private_devices[bus_id].data; ++ ++ if (bus_id >= SPI_MASTER_INSTANCES || cs_id >= cs_num ++ || !spi_write_and_read->w_buffer|| !spi_write_and_read->r_buffer ++ || !spi_write_and_read->n_size) ++ return -EINVAL; ++ ++ /* Transfer */ ++ memset(&xfer, 0, sizeof(struct spi_transfer)); ++ xfer.tx_buf = spi_write_and_read->w_buffer; ++ xfer.rx_buf = spi_write_and_read->r_buffer; ++ xfer.len = spi_write_and_read->n_size; ++ xfer.cs_change = spi_cfg->cs_change; ++ ++ /* Message */ ++ memset(&msg, 0, sizeof(struct spi_message)); ++ INIT_LIST_HEAD(&msg.transfers); ++ list_add_tail(&xfer.transfer_list, &msg.transfers); ++ msg.complete = gk_spi_complete; ++ msg.context = &done; ++ spi = ps[cs_id].spi; ++ msg.spi = spi; ++ ++ mutex_lock(&ps[cs_id].mtx); ++ ++ /* Config */ ++ spi->chip_select = cs_id; ++ spi->mode = spi_cfg->spi_mode; ++ spi->mode &= ~SPI_LOOP; ++ spi->bits_per_word = spi_cfg->cfs_dfs; ++ spi->max_speed_hz = spi_cfg->baud_rate; ++ ++ /* Wait */ ++ spin_lock_irqsave(&ps[cs_id].lock, flags); ++ errorCode = spi->master->transfer(spi, &msg); ++ spin_unlock_irqrestore(&ps[cs_id].lock, flags); ++ if (!errorCode) ++ wait_for_completion(&done); ++ ++ mutex_unlock(&ps[cs_id].mtx); ++ ++ return errorCode; ++} ++EXPORT_SYMBOL(gk_spi_write_and_read); ++ ++ +diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig +index 3b2eaad1..dac6dec5 100644 +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -9,6 +9,22 @@ source "drivers/tty/serial/8250/Kconfig" + + comment "Non-8250 serial port support" + ++config SERIAL_GOKE ++ tristate "Goke ipc Soc serial port support" ++ depends on GK_UART ++ select SERIAL_CORE ++ help ++ If you have a machine based on an Goke ipc Soc you ++ can enable its onboard serial ports by enabling this option. ++ ++config SERIAL_GOKE_CONSOLE ++ bool "Console on Goke ipc SoC serial port" ++ depends on SERIAL_GOKE=y ++ select SERIAL_CORE_CONSOLE ++ help ++ If you have enabled the serial port on the Goke ipc Soc ++ you can make it the console by answering Y to this option. ++ + config SERIAL_AMBA_PL010 + tristate "ARM AMBA PL010 serial port support" + depends on ARM_AMBA && (BROKEN || !ARCH_VERSATILE) +diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile +index 7257c5d8..f408ea26 100644 +--- a/drivers/tty/serial/Makefile ++++ b/drivers/tty/serial/Makefile +@@ -79,3 +79,6 @@ obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o + obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o + obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o + obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o ++ifdef CONFIG_SERIAL_GOKE ++obj-$(CONFIG_GK_UART_V1_00) += gk_sio_v1_00.o ++endif +diff --git a/drivers/tty/serial/gk_sio_v1_00.c b/drivers/tty/serial/gk_sio_v1_00.c +new file mode 100644 +index 00000000..d7023bfa +--- /dev/null ++++ b/drivers/tty/serial/gk_sio_v1_00.c +@@ -0,0 +1,837 @@ ++/* ++ * drivers/tty/serial/gk_sio_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#if defined(CONFIG_SERIAL_GOKE_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#define SUPPORT_SYSRQ ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* ==========================================================================*/ ++static void __serial_gk_enable_ms(struct uart_port *port) ++{ ++ gk_uart_setbitsl((unsigned int)port->membase + UART_IE_OFFSET, UART_IE_EDSSI); ++} ++ ++static void __serial_gk_disable_ms(struct uart_port *port) ++{ ++ gk_uart_clrbitsl((unsigned int)port->membase + UART_IE_OFFSET, UART_IE_EDSSI); ++} ++ ++static inline void wait_for_tx(struct uart_port *port) ++{ ++ u32 ls; ++ ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ while ((ls & UART_LS_TEMT) != UART_LS_TEMT) { ++ cpu_relax(); ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ } ++} ++ ++static inline void wait_for_rx(struct uart_port *port) ++{ ++ u32 ls; ++ ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ while ((ls & UART_LS_DR) != UART_LS_DR) { ++ cpu_relax(); ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ } ++} ++ ++/* ==========================================================================*/ ++static inline void serial_gk_receive_chars(struct uart_port *port, ++ u32 tmo) ++{ ++ struct tty_struct *tty = port->state->port.tty; ++ u32 ch; ++ u32 flag; ++ int max_count; ++ u32 ls; ++ ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ max_count = port->fifosize; ++ ++ do { ++ flag = TTY_NORMAL; ++ if (unlikely(ls & (UART_LS_BI | UART_LS_PE | ++ UART_LS_FE | UART_LS_OE))) { ++ if (ls & UART_LS_BI) { ++ ls &= ~(UART_LS_FE | UART_LS_PE); ++ port->icount.brk++; ++ ++ if (uart_handle_break(port)) ++ goto ignore_char; ++ } ++ if (ls & UART_LS_FE) ++ port->icount.frame++; ++ if (ls & UART_LS_PE) ++ port->icount.parity++; ++ if (ls & UART_LS_OE) ++ port->icount.overrun++; ++ ++ ls &= port->read_status_mask; ++ ++ if (ls & UART_LS_BI) ++ flag = TTY_BREAK; ++ else if (ls & UART_LS_FE) ++ flag = TTY_FRAME; ++ else if (ls & UART_LS_PE) ++ flag = TTY_PARITY; ++ else if (ls & UART_LS_OE) ++ flag = TTY_OVERRUN; ++ ++ if (ls & UART_LS_OE) { ++ printk(KERN_DEBUG "%s: OVERFLOW\n", __FUNCTION__); ++ } ++ } ++ ++ if (likely(ls & UART_LS_DR)) { ++ ch = gk_uart_readl((unsigned int)port->membase + UART_RB_OFFSET); ++ port->icount.rx++; ++ tmo = 0; ++ ++ if (uart_handle_sysrq_char(port, ch)) ++ goto ignore_char; ++ ++ uart_insert_char(port, ls, UART_LS_OE, ch, flag); ++ } else { ++ if (tmo) { ++ ch = gk_uart_readl((unsigned int)port->membase + UART_RB_OFFSET); ++ printk(KERN_DEBUG "False TMO get %d\n", ch); ++ } ++ } ++ ++ignore_char: ++ ls = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ } while ((ls & UART_LS_DR) && (max_count-- > 0)); ++ ++ spin_unlock(&port->lock); ++ tty_flip_buffer_push(tty); ++ spin_lock(&port->lock); ++} ++ ++static void serial_gk_transmit_chars(struct uart_port *port) ++{ ++ struct circ_buf *xmit = &port->state->xmit; ++ int count; ++ struct gk_uart_port_info *port_info; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ if (port->x_char) { ++ gk_uart_writeb((unsigned int)port->membase + UART_TH_OFFSET, port->x_char); ++ port->icount.tx++; ++ port->x_char = 0; ++ return; ++ } ++ ++ if (uart_tx_stopped(port) || uart_circ_empty(xmit)) { ++ port_info->stop_tx(port->membase); ++ return; ++ } ++ ++ count = port->fifosize; ++ while (count-- > 0) { ++ gk_uart_writeb((unsigned int)port->membase + UART_TH_OFFSET, ++ xmit->buf[xmit->tail]); ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ port->icount.tx++; ++ if (uart_circ_empty(xmit)) ++ break; ++ } ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(port); ++ if (uart_circ_empty(xmit)) ++ port_info->stop_tx(port->membase); ++} ++ ++static inline void serial_gk_check_modem_status(struct uart_port *port) ++{ ++ struct gk_uart_port_info *port_info; ++ u32 ms; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ if (port_info->get_ms) { ++ ms = port_info->get_ms(port->membase); ++ ++ if (ms & UART_MS_RI) ++ port->icount.rng++; ++ if (ms & UART_MS_DSR) ++ port->icount.dsr++; ++ if (ms & UART_MS_DCTS) ++ uart_handle_cts_change(port, (ms & UART_MS_CTS)); ++ if (ms & UART_MS_DDCD) ++ uart_handle_dcd_change(port, (ms & UART_MS_DCD)); ++ ++ wake_up_interruptible(&port->state->port.delta_msr_wait); ++ } ++} ++ ++static irqreturn_t serial_gk_irq(int irq, void *dev_id) ++{ ++ struct uart_port *port = dev_id; ++ int rval = IRQ_HANDLED; ++ u32 ii; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&port->lock, flags); ++ ++ ii = gk_uart_readl((unsigned int)port->membase + UART_II_OFFSET); ++ switch (ii & 0x0F) { ++ case UART_II_MODEM_STATUS_CHANGED: ++ serial_gk_check_modem_status(port); ++ break; ++ ++ case UART_II_THR_EMPTY: ++ serial_gk_transmit_chars(port); ++ break; ++ ++ case UART_II_RCV_STATUS: ++ case UART_II_RCV_DATA_AVAIL: ++ serial_gk_receive_chars(port, 0); ++ break; ++ case UART_II_CHAR_TIMEOUT: ++ serial_gk_receive_chars(port, 1); ++ break; ++ ++ case UART_II_NO_INT_PENDING: ++ default: ++ printk(KERN_DEBUG "%s: 0x%x\n", __FUNCTION__, ii); ++ rval = IRQ_NONE; ++ break; ++ } ++ ++ spin_unlock_irqrestore(&port->lock, flags); ++ ++ return rval; ++} ++ ++/* ==========================================================================*/ ++static void serial_gk_enable_ms(struct uart_port *port) ++{ ++ __serial_gk_enable_ms(port); ++} ++ ++static void serial_gk_start_tx(struct uart_port *port) ++{ ++ gk_uart_setbitsl((unsigned int)port->membase + UART_IE_OFFSET, UART_IE_ETBEI); ++} ++ ++static void serial_gk_stop_tx(struct uart_port *port) ++{ ++ struct gk_uart_port_info *port_info; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ port_info->stop_tx(port->membase); ++} ++ ++static void serial_gk_stop_rx(struct uart_port *port) ++{ ++ gk_uart_clrbitsl((unsigned int)port->membase + UART_IE_OFFSET, UART_IE_ERBFI); ++} ++ ++static unsigned int serial_gk_tx_empty(struct uart_port *port) ++{ ++ unsigned long flags; ++ unsigned int lsr; ++ ++ spin_lock_irqsave(&port->lock, flags); ++ lsr = gk_uart_readl((unsigned int)port->membase + UART_LS_OFFSET); ++ spin_unlock_irqrestore(&port->lock, flags); ++ ++ return ((lsr & (UART_LS_TEMT | UART_LS_THRE)) == ++ (UART_LS_TEMT | UART_LS_THRE)) ? TIOCSER_TEMT : 0; ++} ++ ++static unsigned int serial_gk_get_mctrl(struct uart_port *port) ++{ ++ unsigned int mctrl = 0; ++ struct gk_uart_port_info *port_info; ++ u32 ms; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ if (port_info->get_ms) { ++ ms = port_info->get_ms(port->membase); ++ ++ if (ms & UART_MS_CTS) ++ mctrl |= TIOCM_CTS; ++ if (ms & UART_MS_DSR) ++ mctrl |= TIOCM_DSR; ++ if (ms & UART_MS_RI) ++ mctrl |= TIOCM_RI; ++ if (ms & UART_MS_DCD) ++ mctrl |= TIOCM_CD; ++ } ++ ++ return mctrl; ++} ++ ++static void serial_gk_set_mctrl(struct uart_port *port, ++ unsigned int mctrl) ++{ ++ struct gk_uart_port_info *port_info; ++ u32 mcr; ++ u32 mcr_new = 0; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ if (port_info->get_ms) { ++ mcr = gk_uart_readl((unsigned int)port->membase + UART_MC_OFFSET); ++ ++ if (mctrl & TIOCM_DTR) ++ mcr_new |= UART_MC_DTR; ++ if (mctrl & TIOCM_RTS) ++ mcr_new |= UART_MC_RTS; ++ if (mctrl & TIOCM_OUT1) ++ mcr_new |= UART_MC_OUT1; ++ if (mctrl & TIOCM_OUT2) ++ mcr_new |= UART_MC_OUT2; ++ if (mctrl & TIOCM_LOOP) ++ mcr_new |= UART_MC_LB; ++ ++ mcr_new |= port_info->mcr; ++ if (mcr_new != mcr) { ++ if ((mcr & UART_MC_AFCE) == UART_MC_AFCE) { ++ mcr &= ~UART_MC_AFCE; ++ gk_uart_writel((unsigned int)port->membase + UART_MC_OFFSET, ++ mcr); ++ } ++ gk_uart_writel((unsigned int)port->membase + UART_MC_OFFSET, mcr_new); ++ } ++ } ++} ++ ++static void serial_gk_break_ctl(struct uart_port *port, int break_state) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&port->lock, flags); ++ if (break_state != 0) ++ gk_uart_setbitsl((unsigned int)(unsigned int)port->membase + UART_LC_OFFSET, UART_LC_BRK); ++ else ++ gk_uart_clrbitsl((unsigned int)(unsigned int)port->membase + UART_LC_OFFSET, UART_LC_BRK); ++ spin_unlock_irqrestore(&port->lock, flags); ++} ++ ++static int serial_gk_startup(struct uart_port *port) ++{ ++ int retval = 0; ++ struct gk_uart_port_info *port_info; ++ unsigned long flags; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ spin_lock_irqsave(&port->lock, flags); ++ gk_uart_setbitsl((unsigned int)port->membase + UART_SRR_OFFSET, 0x00); ++ gk_uart_writel((unsigned int)port->membase + UART_IE_OFFSET, port_info->ier | ++ UART_IE_PTIME); ++ gk_uart_writel((unsigned int)port->membase + UART_FC_OFFSET, (port_info->fcr | ++ UART_FC_XMITR | UART_FC_RCVRR)); ++ gk_uart_writel((unsigned int)port->membase + UART_IE_OFFSET, port_info->ier); ++ spin_unlock_irqrestore(&port->lock, flags); ++ ++ //printk("%s[001] port->irq=%d\n", __FUNCTION__, port->irq); ++ retval = request_irq(port->irq, serial_gk_irq, ++ IRQF_TRIGGER_HIGH, dev_name(port->dev), port); ++ ++ //printk("%s[002] retval = %d\n", __FUNCTION__, retval); ++ ++ return retval; ++} ++ ++static void serial_gk_shutdown(struct uart_port *port) ++{ ++ unsigned long flags; ++ ++ free_irq(port->irq, port); ++ ++ spin_lock_irqsave(&port->lock, flags); ++ gk_uart_clrbitsl((unsigned int)port->membase + UART_LC_OFFSET, UART_LC_BRK); ++ gk_uart_setbitsl((unsigned int)port->membase + UART_SRR_OFFSET, 0x01); ++ spin_unlock_irqrestore(&port->lock, flags); ++} ++ ++static void serial_gk_set_termios(struct uart_port *port, ++ struct ktermios *termios, struct ktermios *old) ++{ ++ struct gk_uart_port_info *port_info; ++ unsigned int baud, quot; ++ u32 lc = 0x0; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ ++ port->uartclk = port_info->get_pll(); ++ switch (termios->c_cflag & CSIZE) { ++ case CS5: ++ lc |= UART_LC_CLS_5_BITS; ++ break; ++ case CS6: ++ lc |= UART_LC_CLS_6_BITS; ++ break; ++ case CS7: ++ lc |= UART_LC_CLS_7_BITS; ++ break; ++ case CS8: ++ default: ++ lc |= UART_LC_CLS_8_BITS; ++ break; ++ } ++ ++ if (termios->c_cflag & CSTOPB) ++ lc |= UART_LC_STOP_2BIT; ++ else ++ lc |= UART_LC_STOP_1BIT; ++ ++ if (termios->c_cflag & PARENB) { ++ if (termios->c_cflag & PARODD) ++ lc |= (UART_LC_PEN | UART_LC_ODD_PARITY); ++ else ++ lc |= (UART_LC_PEN | UART_LC_EVEN_PARITY); ++ } ++ ++ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); ++ quot = uart_get_divisor(port, baud); ++ ++ disable_irq(port->irq); ++ uart_update_timeout(port, termios->c_cflag, baud); ++ ++ port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; ++ if (termios->c_iflag & INPCK) ++ port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; ++ if (termios->c_iflag & (BRKINT | PARMRK)) ++ port->read_status_mask |= UART_LSR_BI; ++ ++ port->ignore_status_mask = 0; ++ if (termios->c_iflag & IGNPAR) ++ port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; ++ if (termios->c_iflag & IGNBRK) { ++ port->ignore_status_mask |= UART_LSR_BI; ++ if (termios->c_iflag & IGNPAR) ++ port->ignore_status_mask |= UART_LSR_OE; ++ } ++ if ((termios->c_cflag & CREAD) == 0) ++ port->ignore_status_mask |= UART_LSR_DR; ++ ++ if ((termios->c_cflag & CRTSCTS) == 0) ++ port_info->mcr &= ~UART_MC_AFCE; ++ else ++ port_info->mcr |= UART_MC_AFCE; ++ ++ gk_uart_writel((unsigned int)port->membase + UART_LC_OFFSET, UART_LC_DLAB); ++ ++#if 1 ++{ ++ u32 clk = GK_UART_FREQ; ++ u16 dl; ++ ++ dl = clk * 10 / baud / 16; ++ if (dl % 10 >= 5) ++ dl = (dl / 10) + 1; ++ else ++ dl = (dl / 10); ++ ++ gk_uart_writel((unsigned int)port->membase + UART_DLL_OFFSET, dl & 0xff); ++ gk_uart_writel((unsigned int)port->membase + UART_DLH_OFFSET, (dl >> 8) & 0xff); ++} ++#else ++ gk_uart_writel((unsigned int)port->membase + UART_DLL_OFFSET, quot & 0xff); ++ gk_uart_writel((unsigned int)port->membase + UART_DLH_OFFSET, (quot >> 8) & 0xff); ++#endif ++ ++ gk_uart_writel((unsigned int)port->membase + UART_LC_OFFSET, lc); ++ if (UART_ENABLE_MS(port, termios->c_cflag)) ++ __serial_gk_enable_ms(port); ++ else ++ __serial_gk_disable_ms(port); ++ serial_gk_set_mctrl(port, port->mctrl); ++ ++ enable_irq(port->irq); ++} ++ ++static void serial_gk_pm(struct uart_port *port, ++ unsigned int state, unsigned int oldstate) ++{ ++} ++ ++static void serial_gk_release_port(struct uart_port *port) ++{ ++} ++ ++static int serial_gk_request_port(struct uart_port *port) ++{ ++ return 0; ++} ++ ++static void serial_gk_config_port(struct uart_port *port, int flags) ++{ ++} ++ ++static int serial_gk_verify_port(struct uart_port *port, ++ struct serial_struct *ser) ++{ ++ int retval = 0; ++ ++ if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00) ++ retval = -EINVAL; ++ if (port->irq != ser->irq) ++ retval = -EINVAL; ++ if (ser->io_type != SERIAL_IO_MEM) ++ retval = -EINVAL; ++ ++ return retval; ++} ++ ++static const char *serial_gk_type(struct uart_port *port) ++{ ++ return "gkuart"; ++} ++ ++#ifdef CONFIG_CONSOLE_POLL ++static void serial_gk_poll_put_char(struct uart_port *port, ++ unsigned char chr) ++{ ++ struct gk_uart_port_info *port_info; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ if (!port->suspended) { ++ wait_for_tx(port); ++ gk_uart_writeb((unsigned int)port->membase + UART_TH_OFFSET, chr); ++ } ++} ++ ++static int serial_gk_poll_get_char(struct uart_port *port) ++{ ++ struct gk_uart_port_info *port_info; ++ ++ port_info = (struct gk_uart_port_info *)(port->private_data); ++ if (!port->suspended) { ++ wait_for_rx(port); ++ return gk_uart_readl((unsigned int)port->membase + UART_RB_OFFSET); ++ } ++ return 0; ++} ++#endif ++ ++struct uart_ops serial_gk_pops = { ++ .tx_empty = serial_gk_tx_empty, ++ .set_mctrl = serial_gk_set_mctrl, ++ .get_mctrl = serial_gk_get_mctrl, ++ .stop_tx = serial_gk_stop_tx, ++ .start_tx = serial_gk_start_tx, ++ .stop_rx = serial_gk_stop_rx, ++ .enable_ms = serial_gk_enable_ms, ++ .break_ctl = serial_gk_break_ctl, ++ .startup = serial_gk_startup, ++ .shutdown = serial_gk_shutdown, ++ .set_termios = serial_gk_set_termios, ++ .pm = serial_gk_pm, ++ .type = serial_gk_type, ++ .release_port = serial_gk_release_port, ++ .request_port = serial_gk_request_port, ++ .config_port = serial_gk_config_port, ++ .verify_port = serial_gk_verify_port, ++#ifdef CONFIG_CONSOLE_POLL ++ .poll_put_char = serial_gk_poll_put_char, ++ .poll_get_char = serial_gk_poll_get_char, ++#endif ++}; ++ ++/* ==========================================================================*/ ++#if defined(CONFIG_SERIAL_GOKE_CONSOLE) ++static struct uart_driver serial_gk_reg; ++ ++static void serial_gk_console_putchar(struct uart_port *port, int ch) ++{ ++ wait_for_tx(port); ++ gk_uart_writel((unsigned int)port->membase + UART_TH_OFFSET, ch); ++} ++ ++static void serial_gk_console_write(struct console *co, ++ const char *s, unsigned int count) ++{ ++ u32 ie; ++ struct uart_port *port; ++ unsigned long flags; ++ int locked = 1; ++ ++ port = (struct uart_port *)( ++ gk_uart_ports.port[co->index].port); ++ ++ if (!port->suspended) { ++ local_irq_save(flags); ++ if (port->sysrq) { ++ locked = 0; ++ } else if (oops_in_progress) { ++ locked = spin_trylock(&port->lock); ++ } else { ++ spin_lock(&port->lock); ++ locked = 1; ++ } ++ ++ ie = gk_uart_readl((unsigned int)port->membase + UART_IE_OFFSET); ++ gk_uart_writel((unsigned int)port->membase + UART_IE_OFFSET, ++ ie & ~UART_IE_ETBEI); ++ ++ uart_console_write(port, s, count, ++ serial_gk_console_putchar); ++ ++ wait_for_tx(port); ++ gk_uart_writel((unsigned int)port->membase + UART_IE_OFFSET, ie); ++ ++ if (locked) ++ spin_unlock(&port->lock); ++ local_irq_restore(flags); ++ } ++} ++ ++static int __init serial_gk_console_setup(struct console *co, ++ char *options) ++{ ++ struct uart_port *port; ++ int baud = 115200; ++ int bits = 8; ++ int parity = 'n'; ++ int flow = 'n'; ++ ++ if (co->index < 0 || co->index >= gk_uart_ports.total_port_num) ++ co->index = 0; ++ ++#ifdef KE_DEBUG ++ printk("[serial_gk_console_setup]index = %d\n", co->index); ++#endif ++ ++ port = (struct uart_port *)(gk_uart_ports.port[co->index].port); ++ ++ if(gk_uart_ports.port[co->index].set_pll != NULL) ++ { ++ gk_uart_ports.port[co->index].set_pll(); ++ } ++ ++ port->uartclk = gk_uart_ports.port[co->index].get_pll(); ++ port->ops = &serial_gk_pops; ++ port->private_data = &(gk_uart_ports.port[co->index]); ++ port->line = co->index; ++ ++ if (options) ++ uart_parse_options(options, &baud, &parity, &bits, &flow); ++ ++ return uart_set_options(port, co, baud, parity, bits, flow); ++} ++ ++static struct console serial_gk_console = { ++ .name = "ttySGK", ++ .write = serial_gk_console_write, ++ .device = uart_console_device, ++ .setup = serial_gk_console_setup, ++ .flags = CON_PRINTBUFFER, ++ .index = -1, ++ .data = &serial_gk_reg, ++}; ++ ++static int __init serial_gk_console_init(void) ++{ ++ if (serial_gk_reg.nr == -1) ++ serial_gk_reg.nr = gk_uart_ports.total_port_num; ++ ++#ifdef KE_DEBUG ++ printk("gk_console_init start!\n"); ++#endif ++ ++ register_console(&serial_gk_console); ++ ++#ifdef KE_DEBUG ++ printk("gk_console_init End!\n"); ++#endif ++ ++ return 0; ++} ++ ++console_initcall(serial_gk_console_init); ++ ++#define GK_CONSOLE &serial_gk_console ++#else ++#define GK_CONSOLE NULL ++#endif ++ ++/* ==========================================================================*/ ++static struct uart_driver serial_gk_reg = { ++ .owner = THIS_MODULE, ++ .driver_name = "uart", ++ .dev_name = "ttySGK", ++ .major = 204,//TTY_MAJOR, ++ .minor = 18,//64, ++ .nr = UART_INSTANCES, ++ .cons = GK_CONSOLE, ++}; ++ ++static int serial_gk_probe(struct platform_device *pdev) ++{ ++ int retval = 0; ++ struct gk_uart_platform_info *pinfo; ++ struct uart_port *port; ++ ++ printk(KERN_DEBUG "%s: entry\n", __FUNCTION__); ++ ++ pinfo = (struct gk_uart_platform_info *)pdev->dev.platform_data; ++ if (pinfo == NULL) { ++ dev_err(&pdev->dev, "Can't get UART platform data!\n"); ++ retval = -ENXIO; ++ goto serial_gk_probe_exit; ++ } ++ ++ if ((pdev->id < 0) || (pdev->id >= pinfo->total_port_num)) { ++ dev_err(&pdev->dev, "Wrong UART ID %d!\n", pdev->id); ++ retval = -ENXIO; ++ goto serial_gk_probe_exit; ++ } ++ ++ port = (struct uart_port *)(pinfo->port[pdev->id].port); ++ if(pinfo->port[pdev->id].set_pll != NULL) ++ { ++ pinfo->port[pdev->id].set_pll(); ++ } ++ port->uartclk = pinfo->port[pdev->id].get_pll(); ++ port->ops = &serial_gk_pops; ++ port->dev = &pdev->dev; ++ port->private_data = &(pinfo->port[pdev->id]); ++ port->line = pdev->id; ++ ++ retval = uart_add_one_port(&serial_gk_reg, port); ++ if (retval) { ++ dev_err(&pdev->dev, ++ "uart_add_one_port %d fail %d!\n", ++ pdev->id, retval); ++ goto serial_gk_probe_unregister_driver; ++ } else { ++ pinfo->registed_port_num++; ++ } ++ ++ printk(KERN_DEBUG "%s: succeed!\n", __FUNCTION__); ++ ++ goto serial_gk_probe_exit; ++ ++serial_gk_probe_unregister_driver: ++ if (pinfo->registed_port_num == 0) ++ uart_unregister_driver(&serial_gk_reg); ++ ++serial_gk_probe_exit: ++ return retval; ++} ++ ++static int serial_gk_remove(struct platform_device *pdev) ++{ ++ int retval = 0; ++ struct gk_uart_platform_info *pinfo; ++ struct uart_port *port; ++ ++ pinfo = (struct gk_uart_platform_info *)pdev->dev.platform_data; ++ ++ if (pinfo) { ++ port = (struct uart_port *)(pinfo->port[pdev->id].port); ++ retval = uart_remove_one_port(&serial_gk_reg, port); ++ if (retval) { ++ dev_err(&pdev->dev, ++ "uart_remove_one_port %d fail %d!\n", ++ pdev->id, retval); ++ } else { ++ pinfo->registed_port_num--; ++ } ++ ++ if (pinfo->registed_port_num == 0) ++ uart_unregister_driver(&serial_gk_reg); ++ ++ dev_notice(&pdev->dev, "Remove GK UART.\n"); ++ } ++ ++ return retval; ++} ++ ++static struct platform_driver serial_gk_driver = { ++ .probe = serial_gk_probe, ++ .remove = serial_gk_remove, ++ .driver = { ++ .name = "uart", ++ }, ++}; ++ ++int __init serial_gk_init(void) ++{ ++ int ret; ++ ++ printk(KERN_DEBUG "Serial: gk_uart driver\n"); ++ ++ ret = uart_register_driver(&serial_gk_reg); ++ if (ret == 0) ++ { ++ //printk("%s[001] ret=0x%x\n", __FUNCTION__, ret); ++ ret = platform_driver_register(&serial_gk_driver); ++ if (ret) ++ { ++ printk(KERN_ERR "Serial: gk_uart driver register f!\n"); ++ uart_unregister_driver(&serial_gk_reg); ++ } ++ } ++ ++ return ret; ++ ++} ++ ++void __exit serial_gk_exit(void) ++{ ++ platform_driver_unregister(&serial_gk_driver); ++} ++ ++module_init(serial_gk_init); ++module_exit(serial_gk_exit); ++ ++MODULE_DESCRIPTION("GOKE GK SoC UART driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:gk-uart"); +diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c +index e411f186..25bc1d6e 100644 +--- a/drivers/usb/class/cdc-acm.c ++++ b/drivers/usb/class/cdc-acm.c +@@ -123,13 +123,23 @@ static void acm_release_minor(struct acm *acm) + static int acm_ctrl_msg(struct acm *acm, int request, int value, + void *buf, int len) + { +- int retval = usb_control_msg(acm->dev, usb_sndctrlpipe(acm->dev, 0), ++ int retval; ++ ++ retval = usb_autopm_get_interface(acm->control); ++ if (retval) ++ return retval; ++ ++ retval = usb_control_msg(acm->dev, usb_sndctrlpipe(acm->dev, 0), + request, USB_RT_ACM, value, + acm->control->altsetting[0].desc.bInterfaceNumber, + buf, len, 5000); ++ + dev_dbg(&acm->control->dev, + "%s - rq 0x%02x, val %#x, len %#x, result %d\n", + __func__, request, value, len, retval); ++ ++ usb_autopm_put_interface(acm->control); ++ + return retval < 0 ? retval : 0; + } + +@@ -234,12 +244,9 @@ static int acm_write_start(struct acm *acm, int wbn) + acm->susp_count); + usb_autopm_get_interface_async(acm->control); + if (acm->susp_count) { +- if (!acm->delayed_wb) +- acm->delayed_wb = wb; +- else +- usb_autopm_put_interface_async(acm->control); ++ usb_anchor_urb(wb->urb, &acm->delayed); + spin_unlock_irqrestore(&acm->write_lock, flags); +- return 0; /* A white lie */ ++ return 0; + } + usb_mark_last_busy(acm->dev); + +@@ -535,6 +542,7 @@ static int acm_port_activate(struct tty_port *port, struct tty_struct *tty) + { + struct acm *acm = container_of(port, struct acm, port); + int retval = -ENODEV; ++ int i; + + dev_dbg(&acm->control->dev, "%s\n", __func__); + +@@ -583,6 +591,8 @@ static int acm_port_activate(struct tty_port *port, struct tty_struct *tty) + return 0; + + error_submit_read_urbs: ++ for (i = 0; i < acm->rx_buflimit; i++) ++ usb_kill_urb(acm->read_urbs[i]); + acm->ctrlout = 0; + acm_set_control(acm, acm->ctrlout); + error_set_control: +@@ -610,21 +620,35 @@ static void acm_port_destruct(struct tty_port *port) + static void acm_port_shutdown(struct tty_port *port) + { + struct acm *acm = container_of(port, struct acm, port); ++ struct urb *urb; ++ struct acm_wb *wb; + int i; ++ int pm_err; + + dev_dbg(&acm->control->dev, "%s\n", __func__); + + mutex_lock(&acm->mutex); + if (!acm->disconnected) { +- usb_autopm_get_interface(acm->control); ++ pm_err = usb_autopm_get_interface(acm->control); + acm_set_control(acm, acm->ctrlout = 0); ++ ++ for (;;) { ++ urb = usb_get_from_anchor(&acm->delayed); ++ if (!urb) ++ break; ++ wb = urb->context; ++ wb->use = 0; ++ usb_autopm_put_interface_async(acm->control); ++ } ++ + usb_kill_urb(acm->ctrlurb); + for (i = 0; i < ACM_NW; i++) + usb_kill_urb(acm->wb[i].urb); + for (i = 0; i < acm->rx_buflimit; i++) + usb_kill_urb(acm->read_urbs[i]); + acm->control->needs_remote_wakeup = 0; +- usb_autopm_put_interface(acm->control); ++ if (!pm_err) ++ usb_autopm_put_interface(acm->control); + } + mutex_unlock(&acm->mutex); + } +@@ -886,11 +910,12 @@ static void acm_tty_set_termios(struct tty_struct *tty, + /* FIXME: Needs to clear unsupported bits in the termios */ + acm->clocal = ((termios->c_cflag & CLOCAL) != 0); + +- if (!newline.dwDTERate) { ++ if (C_BAUD(tty) == B0) { + newline.dwDTERate = acm->line.dwDTERate; + newctrl &= ~ACM_CTRL_DTR; +- } else ++ } else if (termios_old && (termios_old->c_cflag & CBAUD) == B0) { + newctrl |= ACM_CTRL_DTR; ++ } + + if (newctrl != acm->ctrlout) + acm_set_control(acm, acm->ctrlout = newctrl); +@@ -983,6 +1008,7 @@ static int acm_probe(struct usb_interface *intf, + unsigned long quirks; + int num_rx_buf; + int i; ++ unsigned int elength = 0; + int combined_interfaces = 0; + + /* normal quirks */ +@@ -1018,6 +1044,12 @@ static int acm_probe(struct usb_interface *intf, + } + + while (buflen > 0) { ++ elength = buffer[0]; ++ if (!elength) { ++ dev_err(&intf->dev, "skipping garbage byte\n"); ++ elength = 1; ++ goto next_desc; ++ } + if (buffer[1] != USB_DT_CS_INTERFACE) { + dev_err(&intf->dev, "skipping garbage\n"); + goto next_desc; +@@ -1025,6 +1057,8 @@ static int acm_probe(struct usb_interface *intf, + + switch (buffer[2]) { + case USB_CDC_UNION_TYPE: /* we've found it */ ++ if (elength < sizeof(struct usb_cdc_union_desc)) ++ goto next_desc; + if (union_header) { + dev_err(&intf->dev, "More than one " + "union descriptor, skipping ...\n"); +@@ -1033,31 +1067,38 @@ static int acm_probe(struct usb_interface *intf, + union_header = (struct usb_cdc_union_desc *)buffer; + break; + case USB_CDC_COUNTRY_TYPE: /* export through sysfs*/ ++ if (elength < sizeof(struct usb_cdc_country_functional_desc)) ++ goto next_desc; + cfd = (struct usb_cdc_country_functional_desc *)buffer; + break; + case USB_CDC_HEADER_TYPE: /* maybe check version */ + break; /* for now we ignore it */ + case USB_CDC_ACM_TYPE: ++ if (elength < 4) ++ goto next_desc; + ac_management_function = buffer[3]; + break; + case USB_CDC_CALL_MANAGEMENT_TYPE: ++ if (elength < 5) ++ goto next_desc; + call_management_function = buffer[3]; + call_interface_num = buffer[4]; + if ( (quirks & NOT_A_MODEM) == 0 && (call_management_function & 3) != 3) + dev_err(&intf->dev, "This device cannot do calls on its own. It is not a modem.\n"); + break; + default: +- /* there are LOTS more CDC descriptors that ++ /* ++ * there are LOTS more CDC descriptors that + * could legitimately be found here. + */ + dev_dbg(&intf->dev, "Ignoring descriptor: " +- "type %02x, length %d\n", +- buffer[2], buffer[0]); ++ "type %02x, length %ud\n", ++ buffer[2], elength); + break; + } + next_desc: +- buflen -= buffer[0]; +- buffer += buffer[0]; ++ buflen -= elength; ++ buffer += elength; + } + + if (!union_header) { +@@ -1083,10 +1124,11 @@ next_desc: + } else { + control_interface = usb_ifnum_to_if(usb_dev, union_header->bMasterInterface0); + data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = union_header->bSlaveInterface0)); +- if (!control_interface || !data_interface) { +- dev_dbg(&intf->dev, "no interfaces\n"); +- return -ENODEV; +- } ++ } ++ ++ if (!control_interface || !data_interface) { ++ dev_dbg(&intf->dev, "no interfaces\n"); ++ return -ENODEV; + } + + if (data_interface_num != call_interface_num) +@@ -1211,6 +1253,7 @@ made_compressed_probe: + acm->bInterval = epread->bInterval; + tty_port_init(&acm->port); + acm->port.ops = &acm_port_ops; ++ init_usb_anchor(&acm->delayed); + + buf = usb_alloc_coherent(usb_dev, ctrlsize, GFP_KERNEL, &acm->ctrl_dma); + if (!buf) { +@@ -1403,6 +1446,7 @@ static void acm_disconnect(struct usb_interface *intf) + &dev_attr_wCountryCodes); + device_remove_file(&acm->control->dev, + &dev_attr_iCountryCodeRelDate); ++ kfree(acm->country_codes); + } + device_remove_file(&acm->control->dev, &dev_attr_bmCapabilities); + usb_set_intfdata(acm->control, NULL); +@@ -1441,18 +1485,15 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message) + struct acm *acm = usb_get_intfdata(intf); + int cnt; + ++ spin_lock_irq(&acm->read_lock); ++ spin_lock(&acm->write_lock); + if (PMSG_IS_AUTO(message)) { +- int b; +- +- spin_lock_irq(&acm->write_lock); +- b = acm->transmitting; +- spin_unlock_irq(&acm->write_lock); +- if (b) ++ if (acm->transmitting) { ++ spin_unlock(&acm->write_lock); ++ spin_unlock_irq(&acm->read_lock); + return -EBUSY; ++ } + } +- +- spin_lock_irq(&acm->read_lock); +- spin_lock(&acm->write_lock); + cnt = acm->susp_count++; + spin_unlock(&acm->write_lock); + spin_unlock_irq(&acm->read_lock); +@@ -1460,8 +1501,7 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message) + if (cnt) + return 0; + +- if (test_bit(ASYNCB_INITIALIZED, &acm->port.flags)) +- stop_data_traffic(acm); ++ stop_data_traffic(acm); + + return 0; + } +@@ -1469,29 +1509,24 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message) + static int acm_resume(struct usb_interface *intf) + { + struct acm *acm = usb_get_intfdata(intf); +- struct acm_wb *wb; ++ struct urb *urb; + int rv = 0; +- int cnt; + + spin_lock_irq(&acm->read_lock); +- acm->susp_count -= 1; +- cnt = acm->susp_count; +- spin_unlock_irq(&acm->read_lock); ++ spin_lock(&acm->write_lock); + +- if (cnt) +- return 0; ++ if (--acm->susp_count) ++ goto out; + + if (test_bit(ASYNCB_INITIALIZED, &acm->port.flags)) { +- rv = usb_submit_urb(acm->ctrlurb, GFP_NOIO); +- +- spin_lock_irq(&acm->write_lock); +- if (acm->delayed_wb) { +- wb = acm->delayed_wb; +- acm->delayed_wb = NULL; +- spin_unlock_irq(&acm->write_lock); +- acm_start_wb(acm, wb); +- } else { +- spin_unlock_irq(&acm->write_lock); ++ rv = usb_submit_urb(acm->ctrlurb, GFP_ATOMIC); ++ ++ for (;;) { ++ urb = usb_get_from_anchor(&acm->delayed); ++ if (!urb) ++ break; ++ ++ acm_start_wb(acm, urb->context); + } + + /* +@@ -1499,12 +1534,14 @@ static int acm_resume(struct usb_interface *intf) + * do the write path at all cost + */ + if (rv < 0) +- goto err_out; ++ goto out; + +- rv = acm_submit_read_urbs(acm, GFP_NOIO); ++ rv = acm_submit_read_urbs(acm, GFP_ATOMIC); + } ++out: ++ spin_unlock(&acm->write_lock); ++ spin_unlock_irq(&acm->read_lock); + +-err_out: + return rv; + } + +@@ -1542,6 +1579,8 @@ static int acm_reset_resume(struct usb_interface *intf) + + static const struct usb_device_id acm_ids[] = { + /* quirky and broken devices */ ++ { USB_DEVICE(0x17ef, 0x7000), /* Lenovo USB modem */ ++ .driver_info = NO_UNION_NORMAL, },/* has no union descriptor */ + { USB_DEVICE(0x0870, 0x0001), /* Metricom GS Modem */ + .driver_info = NO_UNION_NORMAL, /* has no union descriptor */ + }, +@@ -1581,17 +1620,32 @@ static const struct usb_device_id acm_ids[] = { + { USB_DEVICE(0x0572, 0x1328), /* Shiro / Aztech USB MODEM UM-3100 */ + .driver_info = NO_UNION_NORMAL, /* has no union descriptor */ + }, ++ { USB_DEVICE(0x2184, 0x001c) }, /* GW Instek AFG-2225 */ + { USB_DEVICE(0x22b8, 0x6425), /* Motorola MOTOMAGX phones */ + }, + /* Motorola H24 HSPA module: */ + { USB_DEVICE(0x22b8, 0x2d91) }, /* modem */ +- { USB_DEVICE(0x22b8, 0x2d92) }, /* modem + diagnostics */ +- { USB_DEVICE(0x22b8, 0x2d93) }, /* modem + AT port */ +- { USB_DEVICE(0x22b8, 0x2d95) }, /* modem + AT port + diagnostics */ +- { USB_DEVICE(0x22b8, 0x2d96) }, /* modem + NMEA */ +- { USB_DEVICE(0x22b8, 0x2d97) }, /* modem + diagnostics + NMEA */ +- { USB_DEVICE(0x22b8, 0x2d99) }, /* modem + AT port + NMEA */ +- { USB_DEVICE(0x22b8, 0x2d9a) }, /* modem + AT port + diagnostics + NMEA */ ++ { USB_DEVICE(0x22b8, 0x2d92), /* modem + diagnostics */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d93), /* modem + AT port */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d95), /* modem + AT port + diagnostics */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d96), /* modem + NMEA */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d97), /* modem + diagnostics + NMEA */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d99), /* modem + AT port + NMEA */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, ++ { USB_DEVICE(0x22b8, 0x2d9a), /* modem + AT port + diagnostics + NMEA */ ++ .driver_info = NO_UNION_NORMAL, /* handle only modem interface */ ++ }, + + { USB_DEVICE(0x0572, 0x1329), /* Hummingbird huc56s (Conexant) */ + .driver_info = NO_UNION_NORMAL, /* union descriptor misplaced on +diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h +index 35ef887b..96147806 100644 +--- a/drivers/usb/class/cdc-acm.h ++++ b/drivers/usb/class/cdc-acm.h +@@ -117,7 +117,7 @@ struct acm { + unsigned int throttled:1; /* actually throttled */ + unsigned int throttle_req:1; /* throttle requested */ + u8 bInterval; +- struct acm_wb *delayed_wb; /* write queued for a device about to be woken */ ++ struct usb_anchor delayed; /* writes queued for a device about to be woken */ + }; + + #define CDC_DATA_INTERFACE_TYPE 0x0a +diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c +index 9dd51f7f..e5fa34e5 100644 +--- a/drivers/usb/class/cdc-wdm.c ++++ b/drivers/usb/class/cdc-wdm.c +@@ -233,6 +233,7 @@ skip_error: + static void wdm_int_callback(struct urb *urb) + { + int rv = 0; ++ int responding; + int status = urb->status; + struct wdm_device *desc; + struct usb_cdc_notification *dr; +@@ -286,8 +287,8 @@ static void wdm_int_callback(struct urb *urb) + + spin_lock(&desc->iuspin); + clear_bit(WDM_READ, &desc->flags); +- set_bit(WDM_RESPONDING, &desc->flags); +- if (!test_bit(WDM_DISCONNECTING, &desc->flags) ++ responding = test_and_set_bit(WDM_RESPONDING, &desc->flags); ++ if (!responding && !test_bit(WDM_DISCONNECTING, &desc->flags) + && !test_bit(WDM_SUSPENDING, &desc->flags)) { + rv = usb_submit_urb(desc->response, GFP_ATOMIC); + dev_dbg(&desc->intf->dev, "%s: usb_submit_urb %d", +@@ -687,16 +688,20 @@ static void wdm_rxwork(struct work_struct *work) + { + struct wdm_device *desc = container_of(work, struct wdm_device, rxwork); + unsigned long flags; +- int rv; ++ int rv = 0; ++ int responding; + + spin_lock_irqsave(&desc->iuspin, flags); + if (test_bit(WDM_DISCONNECTING, &desc->flags)) { + spin_unlock_irqrestore(&desc->iuspin, flags); + } else { ++ responding = test_and_set_bit(WDM_RESPONDING, &desc->flags); + spin_unlock_irqrestore(&desc->iuspin, flags); +- rv = usb_submit_urb(desc->response, GFP_KERNEL); ++ if (!responding) ++ rv = usb_submit_urb(desc->response, GFP_KERNEL); + if (rv < 0 && rv != -EPERM) { + spin_lock_irqsave(&desc->iuspin, flags); ++ clear_bit(WDM_RESPONDING, &desc->flags); + if (!test_bit(WDM_DISCONNECTING, &desc->flags)) + schedule_work(&desc->rxwork); + spin_unlock_irqrestore(&desc->iuspin, flags); +@@ -817,13 +822,11 @@ static int wdm_manage_power(struct usb_interface *intf, int on) + { + /* need autopm_get/put here to ensure the usbcore sees the new value */ + int rv = usb_autopm_get_interface(intf); +- if (rv < 0) +- goto err; + + intf->needs_remote_wakeup = on; +- usb_autopm_put_interface(intf); +-err: +- return rv; ++ if (!rv) ++ usb_autopm_put_interface(intf); ++ return 0; + } + + static int wdm_probe(struct usb_interface *intf, const struct usb_device_id *id) +diff --git a/drivers/usb/core/buffer.c b/drivers/usb/core/buffer.c +index b0585e62..19fa68a7 100644 +--- a/drivers/usb/core/buffer.c ++++ b/drivers/usb/core/buffer.c +@@ -22,17 +22,25 @@ + */ + + /* FIXME tune these based on pool statistics ... */ +-static const size_t pool_max[HCD_BUFFER_POOLS] = { +- /* platforms without dma-friendly caches might need to +- * prevent cacheline sharing... +- */ +- 32, +- 128, +- 512, +- PAGE_SIZE / 2 +- /* bigger --> allocate pages */ ++static size_t pool_max[HCD_BUFFER_POOLS] = { ++ 32, 128, 512, 2048, + }; + ++void __init usb_init_pool_max(void) ++{ ++ /* ++ * The pool_max values must never be smaller than ++ * ARCH_KMALLOC_MINALIGN. ++ */ ++ if (ARCH_KMALLOC_MINALIGN <= 32) ++ ; /* Original value is okay */ ++ else if (ARCH_KMALLOC_MINALIGN <= 64) ++ pool_max[0] = 64; ++ else if (ARCH_KMALLOC_MINALIGN <= 128) ++ pool_max[0] = 0; /* Don't use this pool */ ++ else ++ BUILD_BUG(); /* We don't allow this */ ++} + + /* SETUP primitives */ + +diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c +index f4bdd0ce..f19646ef 100644 +--- a/drivers/usb/core/config.c ++++ b/drivers/usb/core/config.c +@@ -201,6 +201,17 @@ static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum, + if (n == 0) + n = 9; /* 32 ms = 2^(9-1) uframes */ + j = 16; ++ ++ /* ++ * Adjust bInterval for quirked devices. ++ * This quirk fixes bIntervals reported in ++ * linear microframes. ++ */ ++ if (to_usb_device(ddev)->quirks & ++ USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL) { ++ n = clamp(fls(d->bInterval), i, j); ++ i = j = n; ++ } + break; + default: /* USB_SPEED_FULL or _LOW */ + /* For low-speed, 10 ms is the official minimum. +@@ -424,7 +435,8 @@ static int usb_parse_configuration(struct usb_device *dev, int cfgidx, + + memcpy(&config->desc, buffer, USB_DT_CONFIG_SIZE); + if (config->desc.bDescriptorType != USB_DT_CONFIG || +- config->desc.bLength < USB_DT_CONFIG_SIZE) { ++ config->desc.bLength < USB_DT_CONFIG_SIZE || ++ config->desc.bLength > size) { + dev_err(ddev, "invalid descriptor for config index %d: " + "type = 0x%X, length = %d\n", cfgidx, + config->desc.bDescriptorType, config->desc.bLength); +@@ -665,8 +677,6 @@ int usb_get_configuration(struct usb_device *dev) + struct usb_config_descriptor *desc; + + cfgno = 0; +- if (dev->authorized == 0) /* Not really an error */ +- goto out_not_authorized; + result = -ENOMEM; + if (ncfg > USB_MAXCONFIG) { + dev_warn(ddev, "too many configurations: %d, " +@@ -748,7 +758,6 @@ int usb_get_configuration(struct usb_device *dev) + + err: + kfree(desc); +-out_not_authorized: + dev->descriptor.bNumConfigurations = cfgno; + err2: + if (result == -ENOMEM) +diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c +index 404413b0..d2ae3d94 100644 +--- a/drivers/usb/core/devio.c ++++ b/drivers/usb/core/devio.c +@@ -444,6 +444,7 @@ static void async_completed(struct urb *urb) + as->status = urb->status; + signr = as->signr; + if (signr) { ++ memset(&sinfo, 0, sizeof(sinfo)); + sinfo.si_signo = as->signr; + sinfo.si_errno = as->status; + sinfo.si_code = SI_ASYNCIO; +@@ -681,7 +682,25 @@ static int check_ctrlrecip(struct dev_state *ps, unsigned int requesttype, + index &= 0xff; + switch (requesttype & USB_RECIP_MASK) { + case USB_RECIP_ENDPOINT: ++ if ((index & ~USB_DIR_IN) == 0) ++ return 0; + ret = findintfep(ps->dev, index); ++ if (ret < 0) { ++ /* ++ * Some not fully compliant Win apps seem to get ++ * index wrong and have the endpoint number here ++ * rather than the endpoint address (with the ++ * correct direction). Win does let this through, ++ * so we'll not reject it here but leave it to ++ * the device to not break KVM. But we warn. ++ */ ++ ret = findintfep(ps->dev, index ^ 0x80); ++ if (ret >= 0) ++ dev_info(&ps->dev->dev, ++ "%s: process %i (%s) requesting ep %02x but needs %02x\n", ++ __func__, task_pid_nr(current), ++ current->comm, index, index ^ 0x80); ++ } + if (ret >= 0) + ret = checkintf(ps, ret); + break; +@@ -2073,6 +2092,7 @@ static void usbdev_remove(struct usb_device *udev) + wake_up_all(&ps->wait); + list_del_init(&ps->list); + if (ps->discsignr) { ++ memset(&sinfo, 0, sizeof(sinfo)); + sinfo.si_signo = ps->discsignr; + sinfo.si_errno = EPIPE; + sinfo.si_code = SI_ASYNCIO; +diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c +index 9a56635d..621ea00f 100644 +--- a/drivers/usb/core/driver.c ++++ b/drivers/usb/core/driver.c +@@ -530,22 +530,10 @@ int usb_match_device(struct usb_device *dev, const struct usb_device_id *id) + } + + /* returns 0 if no match, 1 if match */ +-int usb_match_one_id(struct usb_interface *interface, +- const struct usb_device_id *id) ++int usb_match_one_id_intf(struct usb_device *dev, ++ struct usb_host_interface *intf, ++ const struct usb_device_id *id) + { +- struct usb_host_interface *intf; +- struct usb_device *dev; +- +- /* proc_connectinfo in devio.c may call us with id == NULL. */ +- if (id == NULL) +- return 0; +- +- intf = interface->cur_altsetting; +- dev = interface_to_usbdev(interface); +- +- if (!usb_match_device(dev, id)) +- return 0; +- + /* The interface class, subclass, and protocol should never be + * checked for a match if the device class is Vendor Specific, + * unless the match record specifies the Vendor ID. */ +@@ -570,6 +558,26 @@ int usb_match_one_id(struct usb_interface *interface, + + return 1; + } ++ ++/* returns 0 if no match, 1 if match */ ++int usb_match_one_id(struct usb_interface *interface, ++ const struct usb_device_id *id) ++{ ++ struct usb_host_interface *intf; ++ struct usb_device *dev; ++ ++ /* proc_connectinfo in devio.c may call us with id == NULL. */ ++ if (id == NULL) ++ return 0; ++ ++ intf = interface->cur_altsetting; ++ dev = interface_to_usbdev(interface); ++ ++ if (!usb_match_device(dev, id)) ++ return 0; ++ ++ return usb_match_one_id_intf(dev, intf, id); ++} + EXPORT_SYMBOL_GPL(usb_match_one_id); + + /** +@@ -906,8 +914,7 @@ EXPORT_SYMBOL_GPL(usb_deregister); + * it doesn't support pre_reset/post_reset/reset_resume or + * because it doesn't support suspend/resume. + * +- * The caller must hold @intf's device's lock, but not its pm_mutex +- * and not @intf->dev.sem. ++ * The caller must hold @intf's device's lock, but not @intf's lock. + */ + void usb_forced_unbind_intf(struct usb_interface *intf) + { +@@ -920,16 +927,37 @@ void usb_forced_unbind_intf(struct usb_interface *intf) + intf->needs_binding = 1; + } + ++/* ++ * Unbind drivers for @udev's marked interfaces. These interfaces have ++ * the needs_binding flag set, for example by usb_resume_interface(). ++ * ++ * The caller must hold @udev's device lock. ++ */ ++static void unbind_marked_interfaces(struct usb_device *udev) ++{ ++ struct usb_host_config *config; ++ int i; ++ struct usb_interface *intf; ++ ++ config = udev->actconfig; ++ if (config) { ++ for (i = 0; i < config->desc.bNumInterfaces; ++i) { ++ intf = config->interface[i]; ++ if (intf->dev.driver && intf->needs_binding) ++ usb_forced_unbind_intf(intf); ++ } ++ } ++} ++ + /* Delayed forced unbinding of a USB interface driver and scan + * for rebinding. + * +- * The caller must hold @intf's device's lock, but not its pm_mutex +- * and not @intf->dev.sem. ++ * The caller must hold @intf's device's lock, but not @intf's lock. + * + * Note: Rebinds will be skipped if a system sleep transition is in + * progress and the PM "complete" callback hasn't occurred yet. + */ +-void usb_rebind_intf(struct usb_interface *intf) ++static void usb_rebind_intf(struct usb_interface *intf) + { + int rc; + +@@ -946,68 +974,66 @@ void usb_rebind_intf(struct usb_interface *intf) + } + } + +-#ifdef CONFIG_PM +- +-/* Unbind drivers for @udev's interfaces that don't support suspend/resume +- * There is no check for reset_resume here because it can be determined +- * only during resume whether reset_resume is needed. ++/* ++ * Rebind drivers to @udev's marked interfaces. These interfaces have ++ * the needs_binding flag set. + * + * The caller must hold @udev's device lock. + */ +-static void unbind_no_pm_drivers_interfaces(struct usb_device *udev) ++static void rebind_marked_interfaces(struct usb_device *udev) + { + struct usb_host_config *config; + int i; + struct usb_interface *intf; +- struct usb_driver *drv; + + config = udev->actconfig; + if (config) { + for (i = 0; i < config->desc.bNumInterfaces; ++i) { + intf = config->interface[i]; +- +- if (intf->dev.driver) { +- drv = to_usb_driver(intf->dev.driver); +- if (!drv->suspend || !drv->resume) +- usb_forced_unbind_intf(intf); +- } ++ if (intf->needs_binding) ++ usb_rebind_intf(intf); + } + } + } + +-/* Unbind drivers for @udev's interfaces that failed to support reset-resume. +- * These interfaces have the needs_binding flag set by usb_resume_interface(). ++/* ++ * Unbind all of @udev's marked interfaces and then rebind all of them. ++ * This ordering is necessary because some drivers claim several interfaces ++ * when they are first probed. + * + * The caller must hold @udev's device lock. + */ +-static void unbind_no_reset_resume_drivers_interfaces(struct usb_device *udev) ++void usb_unbind_and_rebind_marked_interfaces(struct usb_device *udev) + { +- struct usb_host_config *config; +- int i; +- struct usb_interface *intf; +- +- config = udev->actconfig; +- if (config) { +- for (i = 0; i < config->desc.bNumInterfaces; ++i) { +- intf = config->interface[i]; +- if (intf->dev.driver && intf->needs_binding) +- usb_forced_unbind_intf(intf); +- } +- } ++ unbind_marked_interfaces(udev); ++ rebind_marked_interfaces(udev); + } + +-static void do_rebind_interfaces(struct usb_device *udev) ++#ifdef CONFIG_PM ++ ++/* Unbind drivers for @udev's interfaces that don't support suspend/resume ++ * There is no check for reset_resume here because it can be determined ++ * only during resume whether reset_resume is needed. ++ * ++ * The caller must hold @udev's device lock. ++ */ ++static void unbind_no_pm_drivers_interfaces(struct usb_device *udev) + { + struct usb_host_config *config; + int i; + struct usb_interface *intf; ++ struct usb_driver *drv; + + config = udev->actconfig; + if (config) { + for (i = 0; i < config->desc.bNumInterfaces; ++i) { + intf = config->interface[i]; +- if (intf->needs_binding) +- usb_rebind_intf(intf); ++ ++ if (intf->dev.driver) { ++ drv = to_usb_driver(intf->dev.driver); ++ if (!drv->suspend || !drv->resume) ++ usb_forced_unbind_intf(intf); ++ } + } + } + } +@@ -1325,7 +1351,7 @@ int usb_resume_complete(struct device *dev) + * whose needs_binding flag is set + */ + if (udev->state != USB_STATE_NOTATTACHED) +- do_rebind_interfaces(udev); ++ rebind_marked_interfaces(udev); + return 0; + } + +@@ -1347,7 +1373,7 @@ int usb_resume(struct device *dev, pm_message_t msg) + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); +- unbind_no_reset_resume_drivers_interfaces(udev); ++ unbind_marked_interfaces(udev); + } + + /* Avoid PM error messages for devices disconnected while suspended +@@ -1660,6 +1686,18 @@ static int autosuspend_check(struct usb_device *udev) + dev_dbg(&udev->dev, "remote wakeup needed for autosuspend\n"); + return -EOPNOTSUPP; + } ++ ++ /* ++ * If the device is a direct child of the root hub and the HCD ++ * doesn't handle wakeup requests, don't allow autosuspend when ++ * wakeup is needed. ++ */ ++ if (w && udev->parent == udev->bus->root_hub && ++ bus_to_hcd(udev->bus)->cant_recv_wakeups) { ++ dev_dbg(&udev->dev, "HCD doesn't handle wakeup requests\n"); ++ return -EOPNOTSUPP; ++ } ++ + udev->do_remote_wakeup = w; + return 0; + } +@@ -1682,10 +1720,13 @@ int usb_runtime_suspend(struct device *dev) + if (status == -EAGAIN || status == -EBUSY) + usb_mark_last_busy(udev); + +- /* The PM core reacts badly unless the return code is 0, +- * -EAGAIN, or -EBUSY, so always return -EBUSY on an error. ++ /* ++ * The PM core reacts badly unless the return code is 0, ++ * -EAGAIN, or -EBUSY, so always return -EBUSY on an error ++ * (except for root hubs, because they don't suspend through ++ * an upstream port like other USB devices). + */ +- if (status != 0) ++ if (status != 0 && udev->parent) + return -EBUSY; + return status; + } +diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c +index 2b487d47..50ebe6cf 100644 +--- a/drivers/usb/core/hcd-pci.c ++++ b/drivers/usb/core/hcd-pci.c +@@ -71,7 +71,7 @@ static void companion_common(struct pci_dev *pdev, struct usb_hcd *hcd, + continue; + + companion_hcd = pci_get_drvdata(companion); +- if (!companion_hcd) ++ if (!companion_hcd || !companion_hcd->self.root_hub) + continue; + + /* For SET_HS_COMPANION, store a pointer to the EHCI bus in +diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c +index e2cc8df3..f1d0e3ca 100644 +--- a/drivers/usb/core/hcd.c ++++ b/drivers/usb/core/hcd.c +@@ -1528,6 +1528,7 @@ static int unlink1(struct usb_hcd *hcd, struct urb *urb, int status) + int usb_hcd_unlink_urb (struct urb *urb, int status) + { + struct usb_hcd *hcd; ++ struct usb_device *udev = urb->dev; + int retval = -EIDRM; + unsigned long flags; + +@@ -1539,20 +1540,19 @@ int usb_hcd_unlink_urb (struct urb *urb, int status) + spin_lock_irqsave(&hcd_urb_unlink_lock, flags); + if (atomic_read(&urb->use_count) > 0) { + retval = 0; +- usb_get_dev(urb->dev); ++ usb_get_dev(udev); + } + spin_unlock_irqrestore(&hcd_urb_unlink_lock, flags); + if (retval == 0) { + hcd = bus_to_hcd(urb->dev->bus); + retval = unlink1(hcd, urb, status); +- usb_put_dev(urb->dev); ++ if (retval == 0) ++ retval = -EINPROGRESS; ++ else if (retval != -EIDRM && retval != -EBUSY) ++ dev_dbg(&udev->dev, "hcd_unlink_urb %p fail %d\n", ++ urb, retval); ++ usb_put_dev(udev); + } +- +- if (retval == 0) +- retval = -EINPROGRESS; +- else if (retval != -EIDRM && retval != -EBUSY) +- dev_dbg(&urb->dev->dev, "hcd_unlink_urb %p fail %d\n", +- urb, retval); + return retval; + } + +@@ -1882,6 +1882,8 @@ int usb_alloc_streams(struct usb_interface *interface, + return -EINVAL; + if (dev->speed != USB_SPEED_SUPER) + return -EINVAL; ++ if (dev->state < USB_STATE_CONFIGURED) ++ return -ENODEV; + + /* Streams only apply to bulk endpoints. */ + for (i = 0; i < num_eps; i++) +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +index 49b139c1..4a4df38f 100644 +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -488,6 +488,15 @@ resubmit: + static inline int + hub_clear_tt_buffer (struct usb_device *hdev, u16 devinfo, u16 tt) + { ++ /* Need to clear both directions for control ep */ ++ if (((devinfo >> 11) & USB_ENDPOINT_XFERTYPE_MASK) == ++ USB_ENDPOINT_XFER_CONTROL) { ++ int status = usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ HUB_CLEAR_TT_BUFFER, USB_RT_PORT, ++ devinfo ^ 0x8000, tt, NULL, 0, 1000); ++ if (status) ++ return status; ++ } + return usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), + HUB_CLEAR_TT_BUFFER, USB_RT_PORT, devinfo, + tt, NULL, 0, 1000); +@@ -911,6 +920,11 @@ static void hub_activate(struct usb_hub *hub, enum hub_activation_type type) + clear_port_feature(hub->hdev, port1, + USB_PORT_FEAT_C_ENABLE); + } ++ if (portchange & USB_PORT_STAT_C_RESET) { ++ need_debounce_delay = true; ++ clear_port_feature(hub->hdev, port1, ++ USB_PORT_FEAT_C_RESET); ++ } + if ((portchange & USB_PORT_STAT_C_BH_RESET) && + hub_is_superspeed(hub->hdev)) { + need_debounce_delay = true; +@@ -1326,6 +1340,7 @@ static int hub_configure(struct usb_hub *hub, + return 0; + + fail: ++ hdev->maxchild = 0; + dev_err (hub_dev, "config failed, %s (err %d)\n", + message, ret); + /* hub_disconnect() frees urb and descriptor */ +@@ -1386,8 +1401,19 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id) + desc = intf->cur_altsetting; + hdev = interface_to_usbdev(intf); + +- /* Hubs have proper suspend/resume support. */ +- usb_enable_autosuspend(hdev); ++ /* ++ * Hubs have proper suspend/resume support, except for root hubs ++ * where the controller driver doesn't have bus_suspend and ++ * bus_resume methods. ++ */ ++ if (hdev->parent) { /* normal device */ ++ usb_enable_autosuspend(hdev); ++ } else { /* root hub */ ++ const struct hc_driver *drv = bus_to_hcd(hdev->bus)->driver; ++ ++ if (drv->bus_suspend && drv->bus_resume) ++ usb_enable_autosuspend(hdev); ++ } + + if (hdev->level == MAX_TOPO_LEVEL) { + dev_err(&intf->dev, +@@ -1612,8 +1638,10 @@ void usb_set_device_state(struct usb_device *udev, + || new_state == USB_STATE_SUSPENDED) + ; /* No change to wakeup settings */ + else if (new_state == USB_STATE_CONFIGURED) +- wakeup = udev->actconfig->desc.bmAttributes +- & USB_CONFIG_ATT_WAKEUP; ++ wakeup = (udev->quirks & ++ USB_QUIRK_IGNORE_REMOTE_WAKEUP) ? 0 : ++ udev->actconfig->desc.bmAttributes & ++ USB_CONFIG_ATT_WAKEUP; + else + wakeup = 0; + } +@@ -1675,12 +1703,12 @@ static void choose_devnum(struct usb_device *udev) + * bus->devnum_next. */ + devnum = find_next_zero_bit(bus->devmap.devicemap, 128, + bus->devnum_next); +- if (devnum >= 128) ++ if (devnum >= 127) + devnum = find_next_zero_bit(bus->devmap.devicemap, + 128, 1); +- bus->devnum_next = ( devnum >= 127 ? 1 : devnum + 1); ++ bus->devnum_next = ( devnum >= 126 ? 1 : devnum + 1); + } +- if (devnum < 128) { ++ if (devnum < 127) { + set_bit(devnum, bus->devmap.devicemap); + udev->devnum = devnum; + } +@@ -1906,24 +1934,23 @@ static int usb_enumerate_device(struct usb_device *udev) + if (err < 0) { + dev_err(&udev->dev, "can't read configurations, error %d\n", + err); +- goto fail; ++ return err; + } + } +- if (udev->wusb == 1 && udev->authorized == 0) { +- udev->product = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- udev->manufacturer = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- udev->serial = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- } +- else { +- /* read the standard strings and cache them if present */ +- udev->product = usb_cache_string(udev, udev->descriptor.iProduct); +- udev->manufacturer = usb_cache_string(udev, +- udev->descriptor.iManufacturer); +- udev->serial = usb_cache_string(udev, udev->descriptor.iSerialNumber); +- } ++ ++ /* read the standard strings and cache them if present */ ++ udev->product = usb_cache_string(udev, udev->descriptor.iProduct); ++ udev->manufacturer = usb_cache_string(udev, ++ udev->descriptor.iManufacturer); ++ udev->serial = usb_cache_string(udev, udev->descriptor.iSerialNumber); ++ + err = usb_enumerate_device_otg(udev); +-fail: +- return err; ++ if (err < 0) ++ return err; ++ ++ usb_detect_interface_quirks(udev); ++ ++ return 0; + } + + static void set_usb_port_removable(struct usb_device *udev) +@@ -2074,16 +2101,6 @@ int usb_deauthorize_device(struct usb_device *usb_dev) + usb_dev->authorized = 0; + usb_set_configuration(usb_dev, -1); + +- kfree(usb_dev->product); +- usb_dev->product = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- kfree(usb_dev->manufacturer); +- usb_dev->manufacturer = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- kfree(usb_dev->serial); +- usb_dev->serial = kstrdup("n/a (unauthorized)", GFP_KERNEL); +- +- usb_destroy_configuration(usb_dev); +- usb_dev->descriptor.bNumConfigurations = 0; +- + out_unauthorized: + usb_unlock_device(usb_dev); + return 0; +@@ -2111,17 +2128,7 @@ int usb_authorize_device(struct usb_device *usb_dev) + goto error_device_descriptor; + } + +- kfree(usb_dev->product); +- usb_dev->product = NULL; +- kfree(usb_dev->manufacturer); +- usb_dev->manufacturer = NULL; +- kfree(usb_dev->serial); +- usb_dev->serial = NULL; +- + usb_dev->authorized = 1; +- result = usb_enumerate_device(usb_dev); +- if (result < 0) +- goto error_enumerate; + /* Choose and set the configuration. This registers the interfaces + * with the driver core and lets interface drivers bind to them. + */ +@@ -2137,7 +2144,6 @@ int usb_authorize_device(struct usb_device *usb_dev) + } + dev_info(&usb_dev->dev, "authorized to connect\n"); + +-error_enumerate: + error_device_descriptor: + usb_autosuspend_device(usb_dev); + error_autoresume: +@@ -3095,8 +3101,13 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, + retval = hub_port_reset(hub, port1, udev, delay, false); + if (retval < 0) /* error or disconnect */ + goto fail; ++#if 0 ++ //add by liming for usb controler bug, otherwise the usb enumeration error ++ retval = hub_port_reset(hub, port1, udev, delay, false); ++ if (retval < 0) /* error or disconnect */ ++ goto fail; + /* success, speed is known */ +- ++#endif + retval = -ENODEV; + + if (oldspeed != USB_SPEED_UNKNOWN && oldspeed != udev->speed) { +@@ -3213,6 +3224,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, + buf->bMaxPacketSize0; + kfree(buf); + ++#if 0 + retval = hub_port_reset(hub, port1, udev, delay, false); + if (retval < 0) /* error or disconnect */ + goto fail; +@@ -3222,6 +3234,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, + retval = -ENODEV; + goto fail; + } ++#endif + if (r) { + dev_err(&udev->dev, + "device descriptor read/64, error %d\n", +@@ -3355,6 +3368,9 @@ check_highspeed (struct usb_hub *hub, struct usb_device *udev, int port1) + struct usb_qualifier_descriptor *qual; + int status; + ++ if (udev->quirks & USB_QUIRK_DEVICE_QUALIFIER) ++ return; ++ + qual = kmalloc (sizeof *qual, GFP_KERNEL); + if (qual == NULL) + return; +@@ -3725,9 +3741,10 @@ static void hub_events(void) + + hub = list_entry(tmp, struct usb_hub, event_list); + kref_get(&hub->kref); ++ hdev = hub->hdev; ++ usb_get_dev(hdev); + spin_unlock_irq(&hub_event_lock); + +- hdev = hub->hdev; + hub_dev = hub->intfdev; + intf = to_usb_interface(hub_dev); + dev_dbg(hub_dev, "state %d ports %d chg %04x evt %04x\n", +@@ -3881,7 +3898,9 @@ static void hub_events(void) + hub->hdev->children[i - 1]; + + dev_dbg(hub_dev, "warm reset port %d\n", i); +- if (!udev) { ++ if (!udev || ++ !(portstatus & USB_PORT_STAT_CONNECTION) || ++ udev->state == USB_STATE_NOTATTACHED) { + status = hub_port_reset(hub, i, + NULL, HUB_BH_RESET_TIME, + true); +@@ -3891,8 +3910,8 @@ static void hub_events(void) + usb_lock_device(udev); + status = usb_reset_device(udev); + usb_unlock_device(udev); ++ connect_change = 0; + } +- connect_change = 0; + } + + if (connect_change) +@@ -3940,6 +3959,7 @@ static void hub_events(void) + usb_autopm_put_interface(intf); + loop_disconnected: + usb_unlock_device(hdev); ++ usb_put_dev(hdev); + kref_put(&hub->kref, hub_release); + + } /* end while (1) */ +@@ -4149,6 +4169,12 @@ static int usb_reset_and_verify_device(struct usb_device *udev) + } + parent_hub = hdev_to_hub(parent_hdev); + ++ /* Disable USB2 hardware LPM. ++ * It will be re-enabled by the enumeration process. ++ */ ++ if (udev->usb2_hw_lpm_enabled == 1) ++ usb_set_usb2_hardware_lpm(udev, 0); ++ + set_bit(port1, parent_hub->busy_bits); + for (i = 0; i < SET_CONFIG_TRIES; ++i) { + +@@ -4312,10 +4338,11 @@ int usb_reset_device(struct usb_device *udev) + else if (cintf->condition == + USB_INTERFACE_BOUND) + rebind = 1; ++ if (rebind) ++ cintf->needs_binding = 1; + } +- if (ret == 0 && rebind) +- usb_rebind_intf(cintf); + } ++ usb_unbind_and_rebind_marked_interfaces(udev); + } + + usb_autosuspend_device(udev); +diff --git a/drivers/usb/core/otg_whitelist.h b/drivers/usb/core/otg_whitelist.h +index e8cdce57..2753cec6 100644 +--- a/drivers/usb/core/otg_whitelist.h ++++ b/drivers/usb/core/otg_whitelist.h +@@ -59,6 +59,11 @@ static int is_targeted(struct usb_device *dev) + le16_to_cpu(dev->descriptor.idProduct) == 0xbadd)) + return 0; + ++ /* OTG PET device is always targeted (see OTG 2.0 ECN 6.4.2) */ ++ if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a && ++ le16_to_cpu(dev->descriptor.idProduct) == 0x0200)) ++ return 1; ++ + /* NOTE: can't use usb_match_id() since interface caches + * aren't set up yet. this is cut/paste from that code. + */ +diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c +index 8b2a9d83..9fac46d4 100644 +--- a/drivers/usb/core/quirks.c ++++ b/drivers/usb/core/quirks.c +@@ -15,17 +15,22 @@ + #include + #include "usb.h" + +-/* List of quirky USB devices. Please keep this list ordered by: ++/* Lists of quirky USB devices, split in device quirks and interface quirks. ++ * Device quirks are applied at the very beginning of the enumeration process, ++ * right after reading the device descriptor. They can thus only match on device ++ * information. ++ * ++ * Interface quirks are applied after reading all the configuration descriptors. ++ * They can match on both device and interface information. ++ * ++ * Note that the DELAY_INIT and HONOR_BNUMINTERFACES quirks do not make sense as ++ * interface quirks, as they only influence the enumeration process which is run ++ * before processing the interface quirks. ++ * ++ * Please keep the lists ordered by: + * 1) Vendor ID + * 2) Product ID + * 3) Class ID +- * +- * as we want specific devices to be overridden first, and only after that, any +- * class specific quirks. +- * +- * Right now the logic aborts if it finds a valid device in the table, we might +- * want to change that in the future if it turns out that a whole class of +- * devices is broken... + */ + static const struct usb_device_id usb_quirk_list[] = { + /* CBM - Flash disk */ +@@ -38,53 +43,29 @@ static const struct usb_device_id usb_quirk_list[] = { + /* Creative SB Audigy 2 NX */ + { USB_DEVICE(0x041e, 0x3020), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C200 */ +- { USB_DEVICE(0x046d, 0x0802), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam C250 */ +- { USB_DEVICE(0x046d, 0x0804), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam C300 */ +- { USB_DEVICE(0x046d, 0x0805), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam B/C500 */ +- { USB_DEVICE(0x046d, 0x0807), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam C600 */ +- { USB_DEVICE(0x046d, 0x0808), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam Pro 9000 */ +- { USB_DEVICE(0x046d, 0x0809), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam C905 */ +- { USB_DEVICE(0x046d, 0x080a), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Webcam C210 */ +- { USB_DEVICE(0x046d, 0x0819), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Microsoft Wireless Laser Mouse 6000 Receiver */ ++ { USB_DEVICE(0x045e, 0x00e1), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C260 */ +- { USB_DEVICE(0x046d, 0x081a), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Microsoft LifeCam-VX700 v2.0 */ ++ { USB_DEVICE(0x045e, 0x0770), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C310 */ +- { USB_DEVICE(0x046d, 0x081b), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam Fusion */ ++ { USB_DEVICE(0x046d, 0x08c1), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C910 */ +- { USB_DEVICE(0x046d, 0x0821), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam Orbit MP */ ++ { USB_DEVICE(0x046d, 0x08c2), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C160 */ +- { USB_DEVICE(0x046d, 0x0824), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam Pro for Notebook */ ++ { USB_DEVICE(0x046d, 0x08c3), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Webcam C270 */ +- { USB_DEVICE(0x046d, 0x0825), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam Pro 5000 */ ++ { USB_DEVICE(0x046d, 0x08c5), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Quickcam Pro 9000 */ +- { USB_DEVICE(0x046d, 0x0990), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam OEM Dell Notebook */ ++ { USB_DEVICE(0x046d, 0x08c6), .driver_info = USB_QUIRK_RESET_RESUME }, + +- /* Logitech Quickcam E3500 */ +- { USB_DEVICE(0x046d, 0x09a4), .driver_info = USB_QUIRK_RESET_RESUME }, +- +- /* Logitech Quickcam Vision Pro */ +- { USB_DEVICE(0x046d, 0x09a6), .driver_info = USB_QUIRK_RESET_RESUME }, ++ /* Logitech Quickcam OEM Cisco VT Camera II */ ++ { USB_DEVICE(0x046d, 0x08c7), .driver_info = USB_QUIRK_RESET_RESUME }, + + /* Logitech Harmony 700-series */ + { USB_DEVICE(0x046d, 0xc122), .driver_info = USB_QUIRK_DELAY_INIT }, +@@ -100,16 +81,34 @@ static const struct usb_device_id usb_quirk_list[] = { + { USB_DEVICE(0x04d8, 0x000c), .driver_info = + USB_QUIRK_CONFIG_INTF_STRINGS }, + ++ /* CarrolTouch 4000U */ ++ { USB_DEVICE(0x04e7, 0x0009), .driver_info = USB_QUIRK_RESET_RESUME }, ++ ++ /* CarrolTouch 4500U */ ++ { USB_DEVICE(0x04e7, 0x0030), .driver_info = USB_QUIRK_RESET_RESUME }, ++ + /* Samsung Android phone modem - ID conflict with SPH-I500 */ + { USB_DEVICE(0x04e8, 0x6601), .driver_info = + USB_QUIRK_CONFIG_INTF_STRINGS }, + ++ { USB_DEVICE(0x04f3, 0x009b), .driver_info = ++ USB_QUIRK_DEVICE_QUALIFIER }, ++ ++ { USB_DEVICE(0x04f3, 0x016f), .driver_info = ++ USB_QUIRK_DEVICE_QUALIFIER }, ++ + /* Roland SC-8820 */ + { USB_DEVICE(0x0582, 0x0007), .driver_info = USB_QUIRK_RESET_RESUME }, + + /* Edirol SD-20 */ + { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME }, + ++ /* Alcor Micro Corp. Hub */ ++ { USB_DEVICE(0x058f, 0x9254), .driver_info = USB_QUIRK_RESET_RESUME }, ++ ++ /* MicroTouch Systems touchscreen */ ++ { USB_DEVICE(0x0596, 0x051e), .driver_info = USB_QUIRK_RESET_RESUME }, ++ + /* appletouch */ + { USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME }, + +@@ -143,6 +142,9 @@ static const struct usb_device_id usb_quirk_list[] = { + /* Broadcom BCM92035DGROM BT dongle */ + { USB_DEVICE(0x0a5c, 0x2021), .driver_info = USB_QUIRK_RESET_RESUME }, + ++ /* MAYA44USB sound device */ ++ { USB_DEVICE(0x0a92, 0x0091), .driver_info = USB_QUIRK_RESET_RESUME }, ++ + /* Action Semiconductor flash disk */ + { USB_DEVICE(0x10d6, 0x2200), .driver_info = + USB_QUIRK_STRING_FETCH_255 }, +@@ -150,6 +152,10 @@ static const struct usb_device_id usb_quirk_list[] = { + /* SKYMEDI USB_DRIVE */ + { USB_DEVICE(0x1516, 0x8628), .driver_info = USB_QUIRK_RESET_RESUME }, + ++ /* Razer - Razer Blade Keyboard */ ++ { USB_DEVICE(0x1532, 0x0116), .driver_info = ++ USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL }, ++ + /* BUILDWIN Photo Frame */ + { USB_DEVICE(0x1908, 0x1315), .driver_info = + USB_QUIRK_HONOR_BNUMINTERFACES }, +@@ -160,16 +166,65 @@ static const struct usb_device_id usb_quirk_list[] = { + { } /* terminating entry must be last */ + }; + +-static const struct usb_device_id *find_id(struct usb_device *udev) ++static const struct usb_device_id usb_interface_quirk_list[] = { ++ /* Logitech UVC Cameras */ ++ { USB_VENDOR_AND_INTERFACE_INFO(0x046d, USB_CLASS_VIDEO, 1, 0), ++ .driver_info = USB_QUIRK_RESET_RESUME }, ++ ++ /* ASUS Base Station(T100) */ ++ { USB_DEVICE(0x0b05, 0x17e0), .driver_info = ++ USB_QUIRK_IGNORE_REMOTE_WAKEUP }, ++ ++ /* Protocol and OTG Electrical Test Device */ ++ { USB_DEVICE(0x1a0a, 0x0200), .driver_info = ++ USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL }, ++ ++ { } /* terminating entry must be last */ ++}; ++ ++static bool usb_match_any_interface(struct usb_device *udev, ++ const struct usb_device_id *id) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < udev->descriptor.bNumConfigurations; ++i) { ++ struct usb_host_config *cfg = &udev->config[i]; ++ unsigned int j; ++ ++ for (j = 0; j < cfg->desc.bNumInterfaces; ++j) { ++ struct usb_interface_cache *cache; ++ struct usb_host_interface *intf; ++ ++ cache = cfg->intf_cache[j]; ++ if (cache->num_altsetting == 0) ++ continue; ++ ++ intf = &cache->altsetting[0]; ++ if (usb_match_one_id_intf(udev, intf, id)) ++ return true; ++ } ++ } ++ ++ return false; ++} ++ ++static u32 __usb_detect_quirks(struct usb_device *udev, ++ const struct usb_device_id *id) + { +- const struct usb_device_id *id = usb_quirk_list; ++ u32 quirks = 0; ++ ++ for (; id->match_flags; id++) { ++ if (!usb_match_device(udev, id)) ++ continue; + +- for (; id->idVendor || id->bDeviceClass || id->bInterfaceClass || +- id->driver_info; id++) { +- if (usb_match_device(udev, id)) +- return id; ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_INT_INFO) && ++ !usb_match_any_interface(udev, id)) ++ continue; ++ ++ quirks |= (u32)(id->driver_info); + } +- return NULL; ++ ++ return quirks; + } + + /* +@@ -177,14 +232,10 @@ static const struct usb_device_id *find_id(struct usb_device *udev) + */ + void usb_detect_quirks(struct usb_device *udev) + { +- const struct usb_device_id *id = usb_quirk_list; +- +- id = find_id(udev); +- if (id) +- udev->quirks = (u32)(id->driver_info); ++ udev->quirks = __usb_detect_quirks(udev, usb_quirk_list); + if (udev->quirks) + dev_dbg(&udev->dev, "USB quirks for this device: %x\n", +- udev->quirks); ++ udev->quirks); + + /* For the present, all devices default to USB-PERSIST enabled */ + #if 0 /* was: #ifdef CONFIG_PM */ +@@ -201,3 +252,16 @@ void usb_detect_quirks(struct usb_device *udev) + udev->persist_enabled = 1; + #endif /* CONFIG_PM */ + } ++ ++void usb_detect_interface_quirks(struct usb_device *udev) ++{ ++ u32 quirks; ++ ++ quirks = __usb_detect_quirks(udev, usb_interface_quirk_list); ++ if (quirks == 0) ++ return; ++ ++ dev_dbg(&udev->dev, "USB interface quirks for this device: %x\n", ++ quirks); ++ udev->quirks |= quirks; ++} +diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c +index c74ba7bb..89669608 100644 +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -1010,6 +1010,7 @@ static int __init usb_init(void) + pr_info("%s: USB support disabled\n", usbcore_name); + return 0; + } ++ usb_init_pool_max(); + + retval = usb_debugfs_init(); + if (retval) +diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h +index 71648dcb..645278fb 100644 +--- a/drivers/usb/core/usb.h ++++ b/drivers/usb/core/usb.h +@@ -24,6 +24,7 @@ extern void usb_disable_device(struct usb_device *dev, int skip_ep0); + extern int usb_deauthorize_device(struct usb_device *); + extern int usb_authorize_device(struct usb_device *); + extern void usb_detect_quirks(struct usb_device *udev); ++extern void usb_detect_interface_quirks(struct usb_device *udev); + extern int usb_remove_device(struct usb_device *udev); + + extern int usb_get_device_descriptor(struct usb_device *dev, +@@ -35,10 +36,13 @@ extern int usb_set_configuration(struct usb_device *dev, int configuration); + extern int usb_choose_configuration(struct usb_device *udev); + + extern void usb_kick_khubd(struct usb_device *dev); ++extern int usb_match_one_id_intf(struct usb_device *dev, ++ struct usb_host_interface *intf, ++ const struct usb_device_id *id); + extern int usb_match_device(struct usb_device *dev, + const struct usb_device_id *id); + extern void usb_forced_unbind_intf(struct usb_interface *intf); +-extern void usb_rebind_intf(struct usb_interface *intf); ++extern void usb_unbind_and_rebind_marked_interfaces(struct usb_device *udev); + + extern int usb_hub_claim_port(struct usb_device *hdev, unsigned port, + void *owner); +diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig +index f70cab3b..0d11047b 100644 +--- a/drivers/usb/musb/Kconfig ++++ b/drivers/usb/musb/Kconfig +@@ -7,7 +7,7 @@ + config USB_MUSB_HDRC + tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' + depends on USB && USB_GADGET +- select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN) ++ select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN || GK_MUSB) + select TWL4030_USB if MACH_OMAP_3430SDP + select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA + select USB_OTG_UTILS +@@ -32,8 +32,8 @@ config USB_MUSB_HDRC + + if USB_MUSB_HDRC + +-choice +- prompt "Platform Glue Layer" ++#choice ++# prompt "Platform Glue Layer" + + config USB_MUSB_DAVINCI + tristate "DaVinci" +@@ -45,6 +45,50 @@ config USB_MUSB_DA8XX + + config USB_MUSB_TUSB6010 + tristate "TUSB6010" ++ ++config USB_MUSB_GK ++ boolean "GK MUSB support" ++ depends on USB_MUSB_HDRC && !USB_MUSB_SOC ++ depends on GK_MUSB ++ help ++ Say Y here if your system has a dual role high speed USB ++ controller based on the Mentor Graphics silicon IP. ++ ++if USB_MUSB_GK ++choice ++ prompt "GK USB work mode" ++ default GK_USB_HOST_MODE if USB_MUSB_GK ++ help ++ Slect GK USB work mode between HOST and SLAVE. ++ ++config GK_USB_HOST_MODE ++ bool "USB-MASTER mode" ++ depends on USB_MUSB_GK ++ help ++ GK USB work in HOST mode. ++ ++config GK_USB_SLAVE_MODE ++ bool "USB-SALVE mode" ++ depends on USB_MUSB_GK ++ help ++ GK USB work in SLAVE mode. ++ ++config GK_USB_OTG_MODE ++ bool "GK USB OTG mode" ++ depends on USB_MUSB_GK ++ select USB_OTG_WHITELIST ++ help ++ GK USB OTG mode. ++endchoice ++ ++if GK_USB_OTG_MODE ++config GK_USB_OTG_GPIO ++ int "USB OTG PIN" ++ help ++ GK UUSB OTG pin. ++endif #GK_OTG ++ ++endif #USB_MUSB_GK + + config USB_MUSB_OMAP2PLUS + tristate "OMAP2430 and onwards" +@@ -62,12 +106,12 @@ config USB_MUSB_UX500 + tristate "U8500 and U5500" + depends on (ARCH_U8500 && AB8500_USB) + +-endchoice ++#endchoice + + choice + prompt 'MUSB DMA mode' + default USB_UX500_DMA if USB_MUSB_UX500 +- default USB_INVENTRA_DMA if USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN ++ default USB_INVENTRA_DMA if USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_GK + default USB_TI_CPPI_DMA if USB_MUSB_DAVINCI + default USB_TUSB_OMAP_DMA if USB_MUSB_TUSB6010 + default MUSB_PIO_ONLY if USB_MUSB_TUSB6010 || USB_MUSB_DA8XX || USB_MUSB_AM35X +@@ -83,8 +127,8 @@ config USB_UX500_DMA + Enable DMA transfers on UX500 platforms. + + config USB_INVENTRA_DMA +- bool 'Inventra' +- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN ++ bool 'use inventra DMA' ++ depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_GK + help + Enable DMA transfers using Mentor's engine. + +diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile +index 88bfb9de..16aad307 100644 +--- a/drivers/usb/musb/Makefile ++++ b/drivers/usb/musb/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o + obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o + obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o + obj-$(CONFIG_USB_MUSB_UX500) += ux500.o ++obj-$(CONFIG_USB_MUSB_GK) += gk_usb.o + + # the kconfig must guarantee that only one of the + # possible I/O schemes will be enabled at a time ... +diff --git a/drivers/usb/musb/gk_usb.c b/drivers/usb/musb/gk_usb.c +new file mode 100644 +index 00000000..61730077 +--- /dev/null ++++ b/drivers/usb/musb/gk_usb.c +@@ -0,0 +1,548 @@ ++/* ++ * drivers/usb/gk_usb.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2014-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++ ++#include "musb_core.h" ++#include "gk_usb.h" ++ ++ ++static struct timer_list musb_idle_timer; ++static struct musb *the_musb; ++ ++ ++struct gk_glue { ++ struct device *dev; ++ struct platform_device *musb; ++}; ++ ++#define USB_PHY_BASE (GK_VA_USB_PHY) ++#define USB_PHY_REG(x) (USB_PHY_BASE + (x)) ++ ++#define REG_USB_PHY_UTMI0 USB_PHY_REG(0x000) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_01 USB_PHY_REG(0x004) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_02 USB_PHY_REG(0x008) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_03 USB_PHY_REG(0x00C) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_04 USB_PHY_REG(0x010) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_05 USB_PHY_REG(0x014) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_06 USB_PHY_REG(0x018) /* read/write */ ++#define REG_USB_PHY_UTMI_STATUS USB_PHY_REG(0x01C) /* read */ ++#define REG_USB_PHY_UTMI_REG_08 USB_PHY_REG(0x020) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_09 USB_PHY_REG(0x024) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_0A USB_PHY_REG(0x028) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_0B USB_PHY_REG(0x02C) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_0C USB_PHY_REG(0x030) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_10 USB_PHY_REG(0x040) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_11 USB_PHY_REG(0x044) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_12 USB_PHY_REG(0x048) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_13 USB_PHY_REG(0x04C) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_14 USB_PHY_REG(0x050) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_15 USB_PHY_REG(0x054) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_16 USB_PHY_REG(0x058) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_17 USB_PHY_REG(0x05C) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_18 USB_PHY_REG(0x060) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_19 USB_PHY_REG(0x064) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_1A USB_PHY_REG(0x068) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_1B USB_PHY_REG(0x06C) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_1C USB_PHY_REG(0x070) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_1D USB_PHY_REG(0x074) /* read/write */ ++#define REG_USB_PHY_UTMI_REG_1E USB_PHY_REG(0x078) /* read/write */ ++ ++#define REG_UTMI_BASE GK_VA_USB_PHY ++#define REG_PLL_POWER_CONTROL (GK_VA_RCT + 0x0050) /* read/write */ ++ ++//#define USB_AHB_W(addr, value) *(volatile unsigned long*)(addr) = (value) ++//#define USB_AHB_R(addr, value) value = *(volatile unsigned long*)(addr) ++#ifdef CONFIG_GK_USB_OTG_MODE ++static int usb_ctrl_init(void); ++#endif ++ ++void GH_PLL_set_POWER_CONTROL_usb(u8 data) ++{ ++ GH_PLL_POWER_CONTROL_S d; ++ d.all = gk_usb_readl(REG_PLL_POWER_CONTROL); ++ //d.all = *(volatile u32 *)REG_PLL_POWER_CONTROL; ++ d.bitc.usb = data; ++ gk_usb_writel(REG_PLL_POWER_CONTROL, d.all); ++ //*(volatile u32 *)REG_PLL_POWER_CONTROL = d.all; ++} ++ ++void GH_USB_PHY_init(void) ++{ ++ gk_usb_writew(REG_USB_PHY_UTMI0, ((u16)0x0000ff05)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_01, ((u16)0x00009080)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_02, ((u16)0x00003000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_03, ((u16)0x00003020)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_04, ((u16)0x00000483)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_05, ((u16)0x00008044)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_06, ((u16)0x000000c0)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_08, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_09, ((u16)0x000000ff)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_0A, ((u16)0x0000000b)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_0B, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_0C, ((u16)0x000023cc)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_10, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_11, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_12, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_13, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_14, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_15, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_16, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_17, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_18, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_19, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_1A, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_1B, ((u16)0x00000001)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_1C, ((u16)0x00002801)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_1D, ((u16)0x00000000)); ++ gk_usb_writew(REG_USB_PHY_UTMI_REG_1E, ((u16)0x00000000)); ++} ++ ++int gk_usb_phy_init(void) ++{ ++ u32 value = 0; ++ struct gk_gpio_io_info usb_gpio_conf; ++ GH_USB_PHY_init(); ++ printk("musb phy Begin initial sequence ...\n"); ++ ++ usb_gpio_conf.gpio_id = gk_all_gpio_cfg.usb_host; ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ usb_gpio_conf.active_level = GPIO_HIGH; ++#elif defined(CONFIG_GK_USB_SLAVE_MODE) ++ usb_gpio_conf.active_level = GPIO_LOW; ++#elif defined(CONFIG_GK_USB_OTG_MODE) ++ usb_gpio_conf.active_level = GPIO_HIGH; ++#endif ++ usb_gpio_conf.active_delay = 1; ++ ++ gk_set_gpio_output(&usb_gpio_conf, 1); ++ mdelay(20);//100ms ++ ++#if defined(CONFIG_GK_MUSB_CON_V1_10) ++ value = gk_usb_readl(GK_VA_AHB_GREG + 0x8); ++ printk(KERN_DEBUG "val=0x%x\n", value); ++ value &= ~0x00000008; //08->disbale handle ++ value |= 0x00000003; //00->burst8 01->burst16 02->burst32 03->burst64 ++ gk_usb_writel((GK_VA_AHB_GREG + 0x8), value); ++ value = gk_usb_readl(GK_VA_AHB_GREG + 0x8); ++#endif ++ //USB_AHB_R(0x70170050, value); ++ //USB_AHB_W(0x70170050, value | 0x02); ++ //PHY reset ++ GH_PLL_set_POWER_CONTROL_usb(1); ++ GH_PLL_set_POWER_CONTROL_usb(0); ++ mdelay(20); ++ GH_PLL_set_POWER_CONTROL_usb(1); ++ mdelay(10); ++ // init phy ++ //init UTMI ++ gk_usb_writel((REG_UTMI_BASE+(0x04<<2)), 0x0000040f); ++ gk_usb_writel((REG_UTMI_BASE+(0x10<<2)), 0x00008051); ++ gk_usb_writel((REG_UTMI_BASE+(0x11<<2)), 0x00005080); ++ gk_usb_writel((REG_UTMI_BASE+(0x11<<2)), 0x00005090); ++ gk_usb_writel((REG_UTMI_BASE+(0x00<<2)), 0x00006bc3); ++ gk_usb_writel((REG_UTMI_BASE+(0x0A<<2)), 0x00003403); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x00<<2)), 0x000069c3); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x11<<2)), 0x00005080); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x00<<2)), 0x00000001); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x1e<<2)), 0x00000001); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x1e<<2)), 0x00000000); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x03<<2)), 0x00000023); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x03<<2)), 0x00000020); ++ gk_usb_writel((REG_UTMI_BASE+(0x0a<<2)), 0x00000003); ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ gk_usb_writel((REG_UTMI_BASE+(0x0a<<2)), 0x00000103); ++#elif defined(CONFIG_GK_USB_OTG_MODE) ++ if (!gk_gpio_get(CONFIG_GK_USB_OTG_GPIO)) ++ { ++ gk_usb_writel((REG_UTMI_BASE+(0x0a<<2)), 0x00000103); ++ } ++ else ++ { ++ gk_usb_writel((REG_UTMI_BASE+(0x0a<<2)), 0x0000010B); ++ } ++#elif defined(CONFIG_GK_USB_SLAVE_MODE) ++ gk_usb_writel((REG_UTMI_BASE+(0x0a<<2)), 0x0000010B); ++#endif ++ mdelay(10); ++ ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x03<<2)), 0x00000023); ++ mdelay(20); ++ gk_usb_writel((REG_UTMI_BASE+(0x03<<2)), 0x00000020); ++ mdelay(20); ++ ++ //reset USB controller ++ gk_rct_writel(GK_VA_RCT + 0x0088, 0x6CC36011); ++ mdelay(20); ++ gk_rct_writel(GK_VA_RCT + 0x0088, 0x4CC36011); ++ mdelay(20); ++ ++ return 0; ++} ++ ++ ++/*************************************************************************/ ++ ++static void gk_musb_enable(struct musb *musb) ++{ ++ ++} ++ ++static void gk_musb_disable(struct musb *musb) ++{ ++ void __iomem *pBase = musb->ctrl_base; ++ ++ gk_musb_writew((unsigned int)pBase, 0x06, 0x00); ++ gk_musb_writew((unsigned int)pBase, 0x08, 0x00); ++ gk_musb_writeb((unsigned int)pBase, 0x0B, 0x00); ++} ++ ++static int gk_musb_set_mode(struct musb *musb, u8 musb_mode) ++{ ++ return 0; ++} ++ ++static void gk_musb_try_idle(struct musb *musb, unsigned long timeout) ++{ ++ ++} ++ ++/* ++ * Updates cable VBUS status. Caller must take care of locking. ++ */ ++static int gk_musb_vbus_status(struct musb *musb) ++{ ++ int ret = 0; ++ ++ ++ return ret; ++} ++ ++static void gk_musb_set_vbus(struct musb *musb, int is_on) ++{ ++ ++} ++ ++static void musb_do_idle(unsigned long _musb) ++{ ++ ++} ++ ++ ++static int gk_musb_init(struct musb *musb) ++{ ++ struct platform_device *pdev; ++ ++ usb_nop_xceiv_register(); ++ musb->xceiv = usb_get_transceiver(); ++ //printk("musb xceiv = 0x%x \n", (uint32_t)musb->xceiv); ++ if (!musb->xceiv) ++ return -ENODEV; ++ ++ ++ //musb->isr = gk_musb_interrupt; ++ ++ pdev = to_platform_device(musb->controller); ++ ++ setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); ++ ++ printk("gk musb init end...\n"); ++ ++ return 0; ++} ++ ++static int gk_musb_exit(struct musb *musb) ++{ ++ del_timer_sync(&musb_idle_timer); ++ the_musb = NULL; ++ ++ if (musb->board_set_power) ++ musb->board_set_power(0); ++ ++ usb_put_transceiver(musb->xceiv); ++ usb_nop_xceiv_unregister(); ++ return 0; ++} ++ ++static const struct musb_platform_ops gk_ops = { ++ .init = gk_musb_init, ++ .exit = gk_musb_exit, ++ ++ .enable = gk_musb_enable, ++ .disable = gk_musb_disable, ++ ++ .set_mode = gk_musb_set_mode, ++ .try_idle = gk_musb_try_idle, ++ ++ .vbus_status= gk_musb_vbus_status, ++ .set_vbus = gk_musb_set_vbus, ++}; ++ ++static int gk_probe(struct platform_device *pdev) ++{ ++ int ret = -ENOMEM; ++ struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; ++ struct platform_device *musb; ++ struct gk_glue *glue; ++ ++ gk_usb_phy_init(); ++ glue = kzalloc(sizeof(*glue), GFP_KERNEL); ++ if (!glue) { ++ dev_err(&pdev->dev, "failed to allocate glue context\n"); ++ goto err0; ++ } ++ ++ musb = platform_device_alloc("musb-hdrc", -1); ++ if (!musb) { ++ dev_err(&pdev->dev, "failed to allocate musb device\n"); ++ goto err1; ++ } ++ ++ musb->dev.parent = &pdev->dev; ++ musb->dev.dma_mask = &gk_dmamask; ++ musb->dev.coherent_dma_mask = gk_dmamask; ++ ++ glue->dev = &pdev->dev; ++ glue->musb = musb; ++ ++ pdata->platform_ops = &gk_ops; ++ ++ platform_set_drvdata(pdev, glue); ++ ++ ret = platform_device_add_resources(musb, pdev->resource, ++ pdev->num_resources); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to add resources\n"); ++ goto err2; ++ } ++ ++ ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to add platform_data\n"); ++ goto err2; ++ } ++ ++ ret = platform_device_add(musb); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register musb device\n"); ++ goto err1; ++ } ++ printk("platform add gk musb...\n"); ++ ++ ++ return 0; ++ ++err2: ++ platform_device_put(musb); ++ ++err1: ++ kfree(glue); ++ ++err0: ++ return ret; ++} ++ ++static int gk_remove(struct platform_device *pdev) ++{ ++ struct gk_glue *glue = platform_get_drvdata(pdev); ++ ++ platform_device_del(glue->musb); ++ platform_device_put(glue->musb); ++ pdev->resource[0].parent = NULL; ++ pdev->resource[0].sibling = NULL; ++ pdev->resource[0].child = NULL; ++ pdev->resource[1].parent = NULL; ++ pdev->resource[1].sibling = NULL; ++ pdev->resource[1].child = NULL; ++ kfree(glue); ++ ++ return 0; ++} ++ ++static struct platform_driver gk_driver = { ++ .probe = gk_probe, ++ .remove = gk_remove, ++ .driver = { ++ .name = "musb-gk", ++ }, ++}; ++ ++static int __init gk_init(void) ++{ ++#ifdef CONFIG_GK_USB_OTG_MODE ++ usb_ctrl_init(); ++#endif ++ return platform_driver_register(&gk_driver); ++} ++module_init(gk_init); ++ ++static void __exit gk_exit(void) ++{ ++ platform_driver_unregister(&gk_driver); ++} ++module_exit(gk_exit); ++ ++#ifdef CONFIG_GK_USB_OTG_MODE ++static struct semaphore sema_usb_ctrl; ++static u32 usb_ctrl_mode; ++extern void set_usb_unregister(void); ++extern void set_usb_master(void); ++extern void set_usb_slave(void); ++ ++void set_usb_phy_unregister(void) ++{ ++ platform_driver_unregister(&gk_driver); ++} ++EXPORT_SYMBOL(set_usb_phy_unregister); ++ ++void set_usb_phy_master(void) ++{ ++ struct gk_gpio_io_info usb_gpio_conf; ++ usb_gpio_conf.gpio_id = gk_all_gpio_cfg.usb_host; ++ usb_gpio_conf.active_level = GPIO_HIGH; ++ usb_gpio_conf.active_delay = 1; ++ ++ gk_set_gpio_output(&usb_gpio_conf, 1); ++ ++ mdelay(10); ++ ++ platform_driver_register(&gk_driver); ++ ++} ++EXPORT_SYMBOL(set_usb_phy_master); ++ ++void set_usb_phy_slave(void) ++{ ++ struct gk_gpio_io_info usb_gpio_conf; ++ usb_gpio_conf.gpio_id = gk_all_gpio_cfg.usb_host; ++ usb_gpio_conf.active_level = GPIO_LOW; ++ usb_gpio_conf.active_delay = 1; ++ ++ gk_set_gpio_output(&usb_gpio_conf, 1); ++ ++ mdelay(10); ++ ++ platform_driver_register(&gk_driver); ++} ++ ++EXPORT_SYMBOL(set_usb_phy_slave); ++ ++static irqreturn_t usb_ctrl_irq_handle(int irq, void *dummy) ++{ ++ printk("usb_ctrl_irq_handle\n"); ++ printk("irq : %d\n", gk_gpio_get(CONFIG_GK_USB_OTG_GPIO)); ++ ++ if (gk_gpio_get(CONFIG_GK_USB_OTG_GPIO)) ++ { ++ usb_ctrl_mode = 1; ++ } ++ else ++ { ++ usb_ctrl_mode = 0; ++ } ++ ++ mdelay(1); ++ ++ up(&sema_usb_ctrl); ++} ++ ++static void usb_ctrl_task(struct task_struct *p) ++{ ++ while(1) ++ { ++ down(&sema_usb_ctrl); ++ if (usb_ctrl_mode == 1) ++ { ++ printk("usb entry slave mode\n"); ++ set_usb_unregister(); ++ set_usb_phy_unregister(); ++ ++ set_usb_phy_slave(); ++ set_usb_slave(); ++ } ++ else ++ { ++ printk("usb entry master mode\n"); ++ set_usb_unregister(); ++ set_usb_phy_unregister(); ++ ++ set_usb_phy_master(); ++ set_usb_master(); ++ } ++ } ++} ++ ++static int usb_ctrl_init(void) ++{ ++ static struct gk_gpio_irq_info usb_ctrl_irq; ++#if 0 ++ static struct gk_gpio_io_info usb_ctrl_io; ++ usb_ctrl_io.gpio_id = CONFIG_GK_USB_OTG_GPIO; ++ usb_ctrl_io.active_level = 1; ++ usb_ctrl_io.active_delay = 10; ++ ++ printk("GPIO%d : %d\n", CONFIG_GK_USB_OTG_GPIO, gk_get_gpio_input(&usb_ctrl_io)); ++#endif ++ ++ usb_ctrl_irq.pin = CONFIG_GK_USB_OTG_GPIO; ++ usb_ctrl_irq.type = IRQ_TYPE_EDGE_BOTH; ++ usb_ctrl_irq.handler = usb_ctrl_irq_handle; ++ ++ sema_init(&sema_usb_ctrl, 0); ++ if (gk_gpio_get(CONFIG_GK_USB_OTG_GPIO)) ++ { ++ usb_ctrl_mode = 1; ++ } ++ else ++ { ++ usb_ctrl_mode = 0; ++ } ++ ++ kernel_thread(usb_ctrl_task, NULL, 0); ++ gk_gpio_request_irq(&usb_ctrl_irq); ++} ++#endif ++ ++MODULE_DESCRIPTION("GOKE MUSB driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL v2"); ++ +diff --git a/drivers/usb/musb/gk_usb.h b/drivers/usb/musb/gk_usb.h +new file mode 100644 +index 00000000..84469718 +--- /dev/null ++++ b/drivers/usb/musb/gk_usb.h +@@ -0,0 +1,31 @@ ++/* ++ * Copyright (C) 2015 by GOKE LIMITED ++ * ++ * The Inventra Controller Driver for Linux is free software; you ++ * can redistribute it and/or modify it under the terms of the GNU ++ * General Public License version 2 as published by the Free Software ++ * Foundation. ++ */ ++ ++#ifndef __GK_USB_H__ ++#define __GK_USB_H__ ++ ++#include ++ ++ ++typedef union { /* PLL_POWER_CONTROL */ ++ u32 all; ++ struct { ++ u32 unkown1 : 1; ++ u32 usb : 1; ++ u32 unkown2 : 30; ++ } bitc; ++} GH_PLL_POWER_CONTROL_S; ++ ++ ++ ++int gk_usb_phy_init(void); ++ ++ ++ ++#endif /* __GK_USB_H__ */ +diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c +index a2b4008d..71eb2feb 100644 +--- a/drivers/usb/musb/musb_core.c ++++ b/drivers/usb/musb/musb_core.c +@@ -100,6 +100,8 @@ + #include + #include + ++#include ++ + #include "musb_core.h" + + #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) +@@ -226,84 +228,50 @@ static struct usb_phy_io_ops musb_ulpi_access = { + + #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) + ++u32 get_epnum_from_fifo(u32 fifo) ++{ ++ return (fifo-GK_VA_USB-0x400)/MUSB_FIFO_EP_OFFSET; ++} ++ + /* + * Load an endpoint's FIFO + */ + void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) + { +- struct musb *musb = hw_ep->musb; ++ //struct musb *musb = hw_ep->musb; + void __iomem *fifo = hw_ep->fifo; ++ int i; ++ u32 fifo_addr; + +- prefetch((u8 *)src); +- +- dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", +- 'T', hw_ep->epnum, fifo, len, src); +- +- /* we can't assume unaligned reads work */ +- if (likely((0x01 & (unsigned long) src) == 0)) { +- u16 index = 0; +- +- /* best case is 32bit-aligned source address */ +- if ((0x02 & (unsigned long) src) == 0) { +- if (len >= 4) { +- writesl(fifo, src + index, len >> 2); +- index += len & ~0x03; +- } +- if (len & 0x02) { +- musb_writew(fifo, 0, *(u16 *)&src[index]); +- index += 2; +- } +- } else { +- if (len >= 2) { +- writesw(fifo, src + index, len >> 1); +- index += len & ~0x01; +- } +- } +- if (len & 0x01) +- musb_writeb(fifo, 0, src[index]); +- } else { +- /* byte aligned */ +- writesb(fifo, src, len); ++ fifo_addr = get_epnum_from_fifo((u32)fifo)*4+0x20+GK_VA_USB; ++ fifo = (void __iomem *)fifo_addr; ++ for (i = 0; i < len; i++) { ++ musb_writeb(fifo, 0, src[i]); + } + } + ++ + #if !defined(CONFIG_USB_MUSB_AM35X) + /* + * Unload an endpoint's FIFO + */ + void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) + { +- struct musb *musb = hw_ep->musb; ++ //struct musb *musb = hw_ep->musb; + void __iomem *fifo = hw_ep->fifo; + +- dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", +- 'R', hw_ep->epnum, fifo, len, dst); ++ //printk("%cX ep%d fifo %p count %d buf %p\n", ++ // 'R', hw_ep->epnum, fifo, len, dst); + +- /* we can't assume unaligned writes work */ +- if (likely((0x01 & (unsigned long) dst) == 0)) { +- u16 index = 0; ++ int i; ++ u32 fifo_addr; + +- /* best case is 32bit-aligned destination address */ +- if ((0x02 & (unsigned long) dst) == 0) { +- if (len >= 4) { +- readsl(fifo, dst, len >> 2); +- index = len & ~0x03; +- } +- if (len & 0x02) { +- *(u16 *)&dst[index] = musb_readw(fifo, 0); +- index += 2; +- } +- } else { +- if (len >= 2) { +- readsw(fifo, dst, len >> 1); +- index = len & ~0x01; +- } +- } +- if (len & 0x01) +- dst[index] = musb_readb(fifo, 0); +- } else { +- /* byte aligned */ +- readsb(fifo, dst, len); ++ fifo_addr = get_epnum_from_fifo((u32)fifo)*4+0x20+GK_VA_USB; ++ ++ fifo=(void __iomem *)fifo_addr; ++ ++ for (i = 0; i < len; i++) { ++ dst[i] = musb_readb(fifo, 0); + } + } + #endif +@@ -1497,7 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) + /*-------------------------------------------------------------------------*/ + + #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ +- defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) ++ defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \ ++ defined(CONFIG_GK_MUSB) + + static irqreturn_t generic_interrupt(int irq, void *__hci) + { +@@ -1544,24 +1513,39 @@ irqreturn_t musb_interrupt(struct musb *musb) + (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", + musb->int_usb, musb->int_tx, musb->int_rx); + +- /* the core can interrupt us for multiple reasons; docs have +- * a generic interrupt flowchart to follow ++ /** ++ * According to Mentor Graphics' documentation, flowchart on page 98, ++ * IRQ should be handled as follows: ++ * ++ * . Resume IRQ ++ * . Session Request IRQ ++ * . VBUS Error IRQ ++ * . Suspend IRQ ++ * . Connect IRQ ++ * . Disconnect IRQ ++ * . Reset/Babble IRQ ++ * . SOF IRQ (we're not using this one) ++ * . Endpoint 0 IRQ ++ * . TX Endpoints ++ * . RX Endpoints ++ * ++ * We will be following that flowchart in order to avoid any problems ++ * that might arise with internal Finite State Machine. + */ ++ + if (musb->int_usb) + retval |= musb_stage0_irq(musb, musb->int_usb, + devctl, power); + +- /* "stage 1" is handling endpoint irqs */ +- +- /* handle endpoint 0 first */ + if (musb->int_tx & 1) { +- if (devctl & MUSB_DEVCTL_HM) ++ if (is_host_active(musb)) + retval |= musb_h_ep0_irq(musb); + else + retval |= musb_g_ep0_irq(musb); + } + +- /* RX on endpoints 1-15 */ ++ ++ /* RX on endpoints 1-15 */ + reg = musb->int_rx >> 1; + ep_num = 1; + while (reg) { +@@ -1569,12 +1553,14 @@ irqreturn_t musb_interrupt(struct musb *musb) + /* musb_ep_select(musb->mregs, ep_num); */ + /* REVISIT just retval = ep->rx_irq(...) */ + retval = IRQ_HANDLED; +- if (devctl & MUSB_DEVCTL_HM) { +- if (is_host_capable()) +- musb_host_rx(musb, ep_num); +- } else { +- if (is_peripheral_capable()) +- musb_g_rx(musb, ep_num); ++ if (is_host_active(musb)) ++ { ++ //printk("IM,R\n"); ++ musb_host_rx(musb, ep_num); ++ } ++ else ++ { ++ musb_g_rx(musb, ep_num); + } + } + +@@ -1582,20 +1568,23 @@ irqreturn_t musb_interrupt(struct musb *musb) + ep_num++; + } + +- /* TX on endpoints 1-15 */ +- reg = musb->int_tx >> 1; +- ep_num = 1; ++ ++/* TX on endpoints 1-15 */ ++ reg = musb->int_tx >> 1; ++ ep_num = 1; + while (reg) { + if (reg & 1) { + /* musb_ep_select(musb->mregs, ep_num); */ + /* REVISIT just retval |= ep->tx_irq(...) */ + retval = IRQ_HANDLED; +- if (devctl & MUSB_DEVCTL_HM) { +- if (is_host_capable()) +- musb_host_tx(musb, ep_num); +- } else { +- if (is_peripheral_capable()) +- musb_g_tx(musb, ep_num); ++ if (is_host_active(musb)) ++ { ++ //printk(" IM,T\n"); ++ musb_host_tx(musb, ep_num); ++ } ++ else ++ { ++ musb_g_tx(musb, ep_num); + } + } + reg >>= 1; +@@ -1642,6 +1631,7 @@ void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) + } else { + /* receive */ + if (devctl & MUSB_DEVCTL_HM) { ++ //printk("rxdmaint\n"); + if (is_host_capable()) + musb_host_rx(musb, epnum); + } else { +@@ -1860,9 +1850,13 @@ static void musb_free(struct musb *musb) + dma_controller_destroy(c); + } + +- kfree(musb); ++ // use usb_put_hcd replace kfree(musb) ++ usb_put_hcd(musb_to_hcd(musb)); ++ printk("musb_free\n"); ++ //kfree(musb); + } + ++ + /* + * Perform generic per-controller initialization. + * +@@ -1899,7 +1893,20 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) + pm_runtime_enable(musb->controller); + + spin_lock_init(&musb->lock); +- musb->board_mode = plat->mode; ++ ++#if defined(CONFIG_GK_USB_OTG_MODE) ++ if (!gk_gpio_get(CONFIG_GK_USB_OTG_GPIO)) ++ { ++ musb->board_mode = MUSB_HOST; ++ } ++ else ++ { ++ musb->board_mode = MUSB_PERIPHERAL; ++ } ++#else ++ musb->board_mode = plat->mode; ++#endif ++ + musb->board_set_power = plat->set_power; + musb->min_power = plat->min_power; + musb->ops = plat->platform_ops; +@@ -1937,7 +1944,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) + if (use_dma && dev->dma_mask) { + struct dma_controller *c; + +- c = dma_controller_create(musb, musb->mregs); ++ c = dma_controller_create_non_init(musb, musb->mregs); + musb->dma_controller = c; + if (c) + (void) c->start(c); +@@ -1964,7 +1971,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) + INIT_WORK(&musb->irq_work, musb_irq_work); + + /* attach to the IRQ */ +- if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { ++ if (request_irq(nIrq, musb->isr, IRQF_SHARED | IRQF_TRIGGER_HIGH, dev_name(dev), musb)) { + dev_err(dev, "request_irq %d failed!\n", nIrq); + status = -ENODEV; + goto fail3; +@@ -1997,6 +2004,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) + } + } + ++ + /* For the host-only role, we can activate right away. + * (We expect the ID pin to be forcibly grounded!!) + * Otherwise, wait till the gadget driver hooks up. +@@ -2110,28 +2118,32 @@ static int __devinit musb_probe(struct platform_device *pdev) + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!iomem || irq <= 0) + return -ENODEV; +- ++#if 0 + base = ioremap(iomem->start, resource_size(iomem)); + if (!base) { + dev_err(dev, "ioremap failed\n"); + return -ENOMEM; + } ++#else ++ base = (void __iomem *)iomem->start; ++#endif + + #ifndef CONFIG_MUSB_PIO_ONLY + /* clobbered by use_dma=n */ + orig_dma_mask = dev->dma_mask; + #endif + status = musb_init_controller(dev, irq, base); ++#if 0 + if (status < 0) + iounmap(base); +- ++#endif + return status; + } + + static int __devexit musb_remove(struct platform_device *pdev) + { + struct musb *musb = dev_to_musb(&pdev->dev); +- void __iomem *ctrl_base = musb->ctrl_base; ++ //void __iomem *ctrl_base = musb->ctrl_base; + + /* this gets called on rmmod. + * - Host mode: host may still be active +@@ -2142,7 +2154,7 @@ static int __devexit musb_remove(struct platform_device *pdev) + musb_shutdown(pdev); + + musb_free(musb); +- iounmap(ctrl_base); ++ //iounmap(ctrl_base); + device_init_wakeup(&pdev->dev, 0); + #ifndef CONFIG_MUSB_PIO_ONLY + pdev->dev.dma_mask = orig_dma_mask; +@@ -2411,3 +2423,28 @@ static void __exit musb_cleanup(void) + platform_driver_unregister(&musb_driver); + } + module_exit(musb_cleanup); ++ ++#ifdef CONFIG_GK_USB_OTG_MODE ++void set_usb_unregister(void) ++{ ++ platform_driver_unregister(&musb_driver); ++} ++EXPORT_SYMBOL(set_usb_unregister); ++ ++void set_usb_master(void) ++{ ++ platform_driver_register(&musb_driver); ++ ++ mdelay(10); ++} ++EXPORT_SYMBOL(set_usb_master); ++ ++void set_usb_slave(void) ++{ ++ platform_driver_register(&musb_driver); ++ ++ mdelay(10); ++} ++EXPORT_SYMBOL(set_usb_slave); ++#endif ++ +diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h +index f4a40f00..95f06fea 100644 +--- a/drivers/usb/musb/musb_core.h ++++ b/drivers/usb/musb/musb_core.h +@@ -517,6 +517,7 @@ static inline int musb_read_fifosize(struct musb *musb, + hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4); + hw_ep->is_shared_fifo = false; + } ++ //printk("epnum %d tx %d rx %d\n",epnum,hw_ep->max_packet_sz_tx ,hw_ep->max_packet_sz_rx); + + return 0; + } +diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h +index 3a97c4e2..2b8c0d45 100644 +--- a/drivers/usb/musb/musb_dma.h ++++ b/drivers/usb/musb/musb_dma.h +@@ -129,6 +129,8 @@ struct dma_channel { + size_t actual_len; + enum dma_channel_status status; + bool desired_mode; ++ ++ struct musb_hw_ep *hw_ep; + }; + + /* +@@ -181,6 +183,9 @@ extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit); + extern struct dma_controller *__init + dma_controller_create(struct musb *, void __iomem *); + ++extern struct dma_controller * ++dma_controller_create_non_init(struct musb *musb, void __iomem *base); ++ + extern void dma_controller_destroy(struct dma_controller *); + + #endif /* __MUSB_DMA_H__ */ +diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c +index 95918dac..04e34520 100644 +--- a/drivers/usb/musb/musb_gadget.c ++++ b/drivers/usb/musb/musb_gadget.c +@@ -244,8 +244,9 @@ static void nuke(struct musb_ep *ep, const int status) + musb_writew(epio, MUSB_RXCSR, + 0 | MUSB_RXCSR_FLUSHFIFO); + } +- ++#if defined(CONFIG_GK_MUSB_CON_V1_10) + value = c->channel_abort(ep->dma); ++#endif + dev_dbg(musb->controller, "%s: abort DMA --> %d\n", + ep->name, value); + c->channel_release(ep->dma); +@@ -358,29 +359,65 @@ static void txstate(struct musb *musb, struct musb_request *req) + csr); + + #ifndef CONFIG_MUSB_PIO_ONLY +- if (is_buffer_mapped(req)) { ++ if ((is_buffer_mapped(req))&&(request->length>=max_ep_writesize(musb, musb_ep))) { + struct dma_controller *c = musb->dma_controller; +- size_t request_size; +- +- /* setup DMA, then program endpoint CSR */ +- request_size = min_t(size_t, request->length - request->actual, +- musb_ep->dma->max_len); +- ++ size_t request_size = 0; ++ ++ if((request->length - request->actual>=musb_ep->packet_sz) ++ &&(musb_ep->type!=USB_ENDPOINT_XFER_ISOC)) ++ { ++#if defined(CONFIG_GK_MUSB_CON_V1_10) ++ musb_ep->dma->desired_mode = 1; ++#elif defined(CONFIG_GK_MUSB_CON_V1_00) ++ musb_ep->dma->desired_mode = 0; ++#endif ++ } ++ else ++ { ++ musb_ep->dma->desired_mode = 0; ++ //printk("mod=0\n"); ++ } ++ if(musb_ep->dma->desired_mode == 0) ++ { ++ request_size = min(request->length - request->actual,(unsigned)musb_ep->packet_sz); ++ } ++ else ++ { ++ request_size = min(request->length - request->actual, ++ musb_ep->dma->max_len); ++ } + use_dma = (request->dma != DMA_ADDR_INVALID); + + /* MUSB_TXCSR_P_ISO is still set correctly */ + + #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) + { +- if (request_size < musb_ep->packet_sz) +- musb_ep->dma->desired_mode = 0; ++ u16 csr_tx; ++ csr_tx = musb_readw(epio, MUSB_TXCSR); ++ if (musb_ep->dma->desired_mode==0) ++ { ++ //musb_ep->dma->desired_mode = 0; ++ csr_tx &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); ++ csr_tx |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ ++ } + else +- musb_ep->dma->desired_mode = 1; +- +- use_dma = use_dma && c->channel_program( ++ { ++ //musb_ep->dma->desired_mode = 1; ++ //printk("lsk:csr_tx=0x%x\n",csr_tx); ++ //csr_tx &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); ++ csr_tx |= MUSB_TXCSR_AUTOSET; ++ csr_tx &=~MUSB_TXCSR_DMAENAB; ++ musb_writew(epio, MUSB_TXCSR, csr_tx); ++ csr_tx |= MUSB_TXCSR_DMAMODE; ++ musb_writew(epio, MUSB_TXCSR, csr_tx); ++ csr_tx |= MUSB_TXCSR_DMAENAB; ++ } ++ musb_writew(epio, MUSB_TXCSR, csr_tx); ++ use_dma = use_dma && musb_ep->dma && c->channel_program( + musb_ep->dma, musb_ep->packet_sz, + musb_ep->dma->desired_mode, + request->dma + request->actual, request_size); ++#if 0 + if (use_dma) { + if (musb_ep->dma->desired_mode == 0) { + /* +@@ -401,6 +438,15 @@ static void txstate(struct musb *musb, struct musb_request *req) + csr |= (MUSB_TXCSR_DMAENAB + | MUSB_TXCSR_DMAMODE + | MUSB_TXCSR_MODE); ++ /* ++ * Enable Autoset according to table ++ * below ++ * bulk_split hb_mult Autoset_Enable ++ * 0 0 Yes(Normal) ++ * 0 >0 No(High BW ISO) ++ * 1 0 Yes(HS bulk) ++ * 1 >0 Yes(FS bulk) ++ */ + if (!musb_ep->hb_mult) + csr |= MUSB_TXCSR_AUTOSET; + } +@@ -408,6 +454,7 @@ static void txstate(struct musb *musb, struct musb_request *req) + + musb_writew(epio, MUSB_TXCSR, csr); + } ++#endif + } + + #elif defined(CONFIG_USB_TI_CPPI_DMA) +@@ -463,7 +510,11 @@ static void txstate(struct musb *musb, struct musb_request *req) + + musb_write_fifo(musb_ep->hw_ep, fifo_count, + (u8 *) (request->buf + request->actual)); ++#if defined(CONFIG_USB_INVENTRA_DMA) ++ musb_ep->dma->actual_len=fifo_count; ++#else + request->actual += fifo_count; ++#endif + csr |= MUSB_TXCSR_TXPKTRDY; + csr &= ~MUSB_TXCSR_P_UNDERRUN; + musb_writew(epio, MUSB_TXCSR, csr); +@@ -532,15 +583,15 @@ void musb_g_tx(struct musb *musb, u8 epnum) + + if (request) { + u8 is_dma = 0; +- +- if (dma && (csr & MUSB_TXCSR_DMAENAB)) { ++ //if (dma && (csr & MUSB_TXCSR_DMAENAB)) { ++ if (dma) { + is_dma = 1; +- csr |= MUSB_TXCSR_P_WZC_BITS; +- csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | +- MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); +- musb_writew(epio, MUSB_TXCSR, csr); ++ //csr |= MUSB_TXCSR_P_WZC_BITS; ++ //csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | ++ // MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); ++ //musb_writew(epio, MUSB_TXCSR, csr); + /* Ensure writebuffer is empty. */ +- csr = musb_readw(epio, MUSB_TXCSR); ++ //csr = musb_readw(epio, MUSB_TXCSR); + request->actual += musb_ep->dma->actual_len; + dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", + epnum, csr, musb_ep->dma->actual_len, request); +@@ -550,6 +601,7 @@ void musb_g_tx(struct musb *musb, u8 epnum) + * First, maybe a terminating short packet. Some DMA + * engines might handle this by themselves. + */ ++#if 0 + if ((request->zero && request->length + && (request->length % musb_ep->packet_sz == 0) + && (request->actual == request->length)) +@@ -571,7 +623,7 @@ void musb_g_tx(struct musb *musb, u8 epnum) + | MUSB_TXCSR_TXPKTRDY); + request->zero = 0; + } +- ++#endif + if (request->actual == request->length) { + musb_g_giveback(musb_ep, request, 0); + /* +@@ -649,13 +701,13 @@ static void rxstate(struct musb *musb, struct musb_request *req) + musb_ep = &hw_ep->ep_out; + + len = musb_ep->packet_sz; +- ++#if defined(CONFIG_GK_MUSB_CON_V1_10) + /* We shouldn't get here while DMA is active, but we do... */ + if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { + dev_dbg(musb->controller, "DMA pending...\n"); + return; + } +- ++#endif + if (csr & MUSB_RXCSR_P_SENDSTALL) { + dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", + musb_ep->end_point.name, csr); +@@ -697,13 +749,23 @@ static void rxstate(struct musb *musb, struct musb_request *req) + * is set. Currently short_not_ok flag is set only from + * file_storage and f_mass_storage drivers + */ +- +- if (request->short_not_ok && len == musb_ep->packet_sz) ++ //if (request->short_not_ok && len == musb_ep->packet_sz) ++ if((len == musb_ep->packet_sz) ++ &&(request->actual+musb_ep->packet_sz<=request->length) ++ &&(musb_ep->type!=USB_ENDPOINT_XFER_ISOC)) ++ { ++#if defined(CONFIG_GK_MUSB_CON_V1_10) + use_mode_1 = 1; ++#elif defined(CONFIG_GK_MUSB_CON_V1_00) ++ use_mode_1 = 0; ++#endif ++ } + else + use_mode_1 = 0; + + if (request->actual < request->length) { ++ ++#if defined(CONFIG_GK_MUSB_CON_V1_10) + #ifdef CONFIG_USB_INVENTRA_DMA + if (is_buffer_mapped(req)) { + struct dma_controller *c; +@@ -712,7 +774,6 @@ static void rxstate(struct musb *musb, struct musb_request *req) + + c = musb->dma_controller; + channel = musb_ep->dma; +- + /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in + * mode 0 only. So we do not get endpoint interrupts due to DMA + * completion. We only get interrupts from DMA controller. +@@ -748,14 +809,17 @@ static void rxstate(struct musb *musb, struct musb_request *req) + */ + musb_writew(epio, MUSB_RXCSR, + csr | MUSB_RXCSR_DMAMODE); +- musb_writew(epio, MUSB_RXCSR, csr); ++ //musb_writew(epio, MUSB_RXCSR, csr); + + } else { + if (!musb_ep->hb_mult && + musb_ep->hw_ep->rx_double_buffered) + csr |= MUSB_RXCSR_AUTOCLEAR; +- csr |= MUSB_RXCSR_DMAENAB; ++ csr &= ~MUSB_RXCSR_DMAENAB; ++ csr &= ~MUSB_RXCSR_DMAMODE; + musb_writew(epio, MUSB_RXCSR, csr); ++ csr |= MUSB_RXCSR_DMAENAB; ++ musb_writew(epio, MUSB_RXCSR, csr); + } + + if (request->actual < request->length) { +@@ -830,7 +894,7 @@ static void rxstate(struct musb *musb, struct musb_request *req) + return; + } + #endif /* Mentor's DMA */ +- ++#endif + fifo_count = request->length - request->actual; + dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", + musb_ep->end_point.name, +@@ -920,7 +984,10 @@ void musb_g_rx(struct musb *musb, u8 epnum) + + csr = musb_readw(epio, MUSB_RXCSR); + dma = is_dma_capable() ? musb_ep->dma : NULL; +- ++ // for gk7101 ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++ dma = NULL; ++#endif + dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, + csr, dma ? " (dma)" : "", request); + +@@ -944,14 +1011,14 @@ void musb_g_rx(struct musb *musb, u8 epnum) + /* REVISIT not necessarily an error */ + dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); + } +- ++#if defined(CONFIG_GK_MUSB_CON_V1_10) + if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { + /* "should not happen"; likely RXPKTRDY pending for DMA */ + dev_dbg(musb->controller, "%s busy, csr %04x\n", + musb_ep->end_point.name, csr); + return; + } +- ++#endif + if (dma && (csr & MUSB_RXCSR_DMAENAB)) { + csr &= ~(MUSB_RXCSR_AUTOCLEAR + | MUSB_RXCSR_DMAENAB +@@ -1100,11 +1167,15 @@ static int musb_gadget_enable(struct usb_ep *ep, + /* Set TXMAXP with the FIFO size of the endpoint + * to disable double buffering mode. + */ +- if (musb->double_buffer_not_ok) ++ if (musb->double_buffer_not_ok) { + musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); +- else ++ } else { ++ //if (can_bulk_split(musb, musb_ep->type)) ++ //musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / ++ //musb_ep->packet_sz) - 1; + musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz + | (musb_ep->hb_mult << 11)); ++ } + + csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; + if (musb_readw(regs, MUSB_TXCSR) +@@ -1167,12 +1238,24 @@ static int musb_gadget_enable(struct usb_ep *ep, + /* NOTE: all the I/O code _should_ work fine without DMA, in case + * for some reason you run out of channels here. + */ +- if (is_dma_capable() && musb->dma_controller) { +- struct dma_controller *c = musb->dma_controller; +- +- musb_ep->dma = c->channel_alloc(c, hw_ep, +- (desc->bEndpointAddress & USB_DIR_IN)); +- } else ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++ if(usb_endpoint_dir_in(desc)) ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++ if(1) ++#endif ++ { ++ if (is_dma_capable() && musb->dma_controller) { ++ struct dma_controller *c = musb->dma_controller; ++ ++ musb_ep->dma = c->channel_alloc(c, hw_ep, ++ usb_endpoint_dir_in(desc)); ++ if (usb_endpoint_dir_in(desc)) ++ hw_ep->tx_channel = musb_ep->dma; ++ else ++ hw_ep->rx_channel = musb_ep->dma; ++ musb_ep->dma->hw_ep = hw_ep; ++ } ++ }else + musb_ep->dma = NULL; + + musb_ep->desc = desc; +@@ -1834,12 +1917,12 @@ static inline void __devinit musb_g_init_endpoints(struct musb *musb) + init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); + count++; + } else { +- if (hw_ep->max_packet_sz_tx) { ++ if ((epnum&0x01)&&(hw_ep->max_packet_sz_tx)) { + init_peripheral_ep(musb, &hw_ep->ep_in, + epnum, 1); + count++; + } +- if (hw_ep->max_packet_sz_rx) { ++ else if (hw_ep->max_packet_sz_rx) { + init_peripheral_ep(musb, &hw_ep->ep_out, + epnum, 0); + count++; +diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c +index ef8d7448..79b84fb0 100644 +--- a/drivers/usb/musb/musb_host.c ++++ b/drivers/usb/musb/musb_host.c +@@ -42,7 +42,9 @@ + #include + #include + #include +- ++#include ++#include ++#include + #include "musb_core.h" + #include "musb_host.h" + +@@ -97,13 +99,37 @@ + */ + + ++ ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++#define USE_M0 1 ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++#define USE_M1 1 ++//#define USE_M0 1 ++#endif ++ ++typedef struct ++{ ++ unsigned long size; ++ dma_addr_t phy_addr; ++ dma_addr_t phy_valid_addr; ++ void *vm_addr; ++ void *vm_valid_addr; ++} dma_buf_t; ++ ++dma_buf_t dma_buf_tx,dma_buf_rx; ++ ++static unsigned char dma_en = 0; ++ + static void musb_ep_program(struct musb *musb, u8 epnum, +- struct urb *urb, int is_out, +- u8 *buf, u32 offset, u32 len); ++ struct urb *urb, int is_out, ++ u8 *buf, u32 offset, u32 len); + + /* + * Clear TX fifo. Needed to avoid BABBLE errors. + */ ++/* ++ * modified for hardware bug by liming. ++ */ + static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) + { + struct musb *musb = ep->musb; +@@ -112,19 +138,20 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) + u16 lastcsr = 0; + int retries = 1000; + +- csr = musb_readw(epio, MUSB_TXCSR); +- while (csr & MUSB_TXCSR_FIFONOTEMPTY) { ++ csr = musb_readw(epio, MUSB_TXCSR); ++ while ((csr & MUSB_TXCSR_FIFONOTEMPTY)) { + if (csr != lastcsr) + dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); +- lastcsr = csr; +- csr |= MUSB_TXCSR_FLUSHFIFO; ++ lastcsr = csr; ++ csr &= ~MUSB_TXCSR_TXPKTRDY; ++ csr |= MUSB_TXCSR_FLUSHFIFO; + musb_writew(epio, MUSB_TXCSR, csr); + csr = musb_readw(epio, MUSB_TXCSR); + if (WARN(retries-- < 1, +- "Could not flush host TX%d fifo: csr: %04x\n", +- ep->epnum, csr)) ++ "Could not flush host TX%d fifo: csr: %04x\n", ++ ep->epnum, csr)) + return; +- mdelay(1); ++ udelay(1); + } + } + +@@ -132,7 +159,7 @@ static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) + { + void __iomem *epio = ep->regs; + u16 csr; +- int retries = 5; ++ int retries = 10; + + /* scrub any data left in the fifo */ + do { +@@ -141,11 +168,11 @@ static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) + break; + musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); + csr = musb_readw(epio, MUSB_TXCSR); +- udelay(10); ++ udelay(1); + } while (--retries); + + WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", +- ep->epnum, csr); ++ ep->epnum, csr); + + /* and reset for the next transfer */ + musb_writew(epio, MUSB_TXCSR, 0); +@@ -530,7 +557,6 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) + csr |= MUSB_RXCSR_H_REQPKT; + musb_writew(epio, MUSB_RXCSR, csr); + } +- + return done; + } + +@@ -605,17 +631,20 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) + ep->rx_reinit = 0; + } + +-static bool musb_tx_dma_program(struct dma_controller *dma, +- struct musb_hw_ep *hw_ep, struct musb_qh *qh, +- struct urb *urb, u32 offset, u32 length) ++static bool musb_tx_dma_program(struct musb *musb, ++ struct dma_controller *dma, ++ struct musb_hw_ep *hw_ep, ++ struct musb_qh *qh, ++ struct urb *urb, ++ u32 offset, ++ u32 length) + { + struct dma_channel *channel = hw_ep->tx_channel; + void __iomem *epio = hw_ep->regs; +- u16 pkt_size = qh->maxpacket; +- u16 csr; +- u8 mode; +- +-#ifdef CONFIG_USB_INVENTRA_DMA ++ u16 pkt_size = qh->maxpacket; ++ u16 csr; ++ u8 mode = 0; ++ + if (length > channel->max_len) + length = channel->max_len; + +@@ -633,37 +662,24 @@ static bool musb_tx_dma_program(struct dma_controller *dma, + } + channel->desired_mode = mode; + musb_writew(epio, MUSB_TXCSR, csr); +-#else +- if (!is_cppi_enabled() && !tusb_dma_omap()) +- return false; +- +- channel->actual_len = 0; +- +- /* +- * TX uses "RNDIS" mode automatically but needs help +- * to identify the zero-length-final-packet case. +- */ +- mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; +-#endif +- +- qh->segsize = length; +- +- /* +- * Ensure the data reaches to main memory before starting +- * DMA transfer +- */ +- wmb(); +- +- if (!dma->channel_program(channel, pkt_size, mode, +- urb->transfer_dma + offset, length)) { +- dma->channel_release(channel); +- hw_ep->tx_channel = NULL; + +- csr = musb_readw(epio, MUSB_TXCSR); +- csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); +- musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); +- return false; +- } ++ channel->hw_ep = hw_ep; ++ ++ if (!urb->align) { ++ //printk("cpy: dst : %p, src : %p, len : %d\n", dma_buf.vm_valid_addr, urb->transfer_dma + qh->offset, length); ++ if (!dma->channel_program(channel, pkt_size, mode, ++ dma_buf_tx.phy_valid_addr + qh->offset, ++ length)) { ++ printk("dma error 1 !!!"); ++ } ++ } else { ++ //wmb(); ++ if (!dma->channel_program(channel, pkt_size, mode, ++ urb->transfer_dma + qh->offset, ++ length)) { ++ printk("dma error 3 !!!"); ++ } ++ } + return true; + } + +@@ -676,7 +692,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + u8 *buf, u32 offset, u32 len) + { + struct dma_controller *dma_controller; +- struct dma_channel *dma_channel; ++ struct dma_channel *dma_channel = NULL; + u8 dma_ok; + void __iomem *mbase = musb->mregs; + struct musb_hw_ep *hw_ep = musb->endpoints + epnum; +@@ -694,20 +710,38 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + + musb_ep_select(mbase, epnum); + +- /* candidate for DMA? */ +- dma_controller = musb->dma_controller; +- if (is_dma_capable() && epnum && dma_controller) { +- dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; +- if (!dma_channel) { +- dma_channel = dma_controller->channel_alloc( +- dma_controller, hw_ep, is_out); +- if (is_out) +- hw_ep->tx_channel = dma_channel; +- else +- hw_ep->rx_channel = dma_channel; +- } +- } else +- dma_channel = NULL; ++ ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++ if (is_out) ++#endif ++ { ++ /* candidate for DMA? */ ++ dma_controller = musb->dma_controller; ++ if (is_dma_capable() && epnum && dma_controller) ++ { ++ dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; ++ if (!dma_channel) { ++ dma_channel = dma_controller->channel_alloc( ++ dma_controller, hw_ep, is_out); ++ if (is_out) ++ { ++ hw_ep->tx_channel = dma_channel; ++ } ++ else ++ { ++ hw_ep->rx_channel = dma_channel; ++ if((dma_channel_status(dma_channel) == MUSB_DMA_STATUS_BUSY)) ++ { ++ printk("dma busy use pio epnum rx%d\n",epnum); ++ dma_channel = NULL; ++ } ++ } ++ } ++ } ++ else ++ dma_channel = NULL; ++ } ++ + + /* make sure we clear DMAEnab, autoSet bits from previous run */ + +@@ -765,6 +799,17 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); + musb_write_txhubport(mbase, epnum, qh->h_port_reg); + /* FIXME if !epnum, do the same for RX ... */ ++ if(!epnum){ ++ musb_writeb(mbase, ++ MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR), ++ qh->addr_reg); ++ musb_writeb(mbase, ++ MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR), ++ qh->h_addr_reg); ++ musb_writeb(mbase, ++ MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT), ++ qh->h_port_reg); ++ } + } else + musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); + +@@ -790,15 +835,38 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + qh->type_reg); + } + +- if (can_bulk_split(musb, qh->type)) ++ if (can_bulk_split(musb, qh->type)) { + load_count = min((u32) hw_ep->max_packet_sz_tx, +- len); +- else ++ len); ++ } else { + load_count = min((u32) packet_sz, len); ++ hw_ep->max_packet_sz_tx = packet_sz; ++ } ++ ++ if (dma_channel && (urb->transfer_dma & 0x7)) { ++ memcpy(dma_buf_tx.vm_valid_addr, urb->transfer_buffer, len); ++ urb->align = 0; ++ //udelay(6); ++ } else { ++ urb->align = 1; ++ } ++ ++ wmb(); ++#if defined(USE_M0) ++ //musb dma mode0 ++ if (dma_channel && musb_tx_dma_program(musb, dma_controller, ++ hw_ep, qh, urb, offset, min((u32) hw_ep->max_packet_sz_tx, len))) { ++ ++ load_count = 0; ++ } ++#elif defined(USE_M1) ++ //musb dma mode1 ++ if (dma_channel && musb_tx_dma_program(musb, dma_controller, ++ hw_ep, qh, urb, offset, len)) { + +- if (dma_channel && musb_tx_dma_program(dma_controller, +- hw_ep, qh, urb, offset, len)) + load_count = 0; ++ } ++#endif + + if (load_count) { + /* PIO to load FIFO */ +@@ -838,13 +906,15 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + csr &= MUSB_RXCSR_DISNYET; + } + +- /* kick things off */ +- +- if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { ++ if ((len> qh->maxpacket)&&(dma_channel)&&(urb->transfer_flags & URB_SHORT_NOT_OK)&&(usb_pipebulk(urb->pipe))) { + /* Candidate for DMA */ + dma_channel->actual_len = 0L; + qh->segsize = len; +- ++ if (urb->transfer_flags & URB_SHORT_NOT_OK) ++ { ++ dma_en = 1; ++ musb_writew(mbase,0x300 + epnum*4,len/qh->maxpacket); ++ } + /* AUTOREQ is in a DMA register */ + musb_writew(hw_ep->regs, MUSB_RXCSR, csr); + csr = musb_readw(hw_ep->regs, MUSB_RXCSR); +@@ -853,22 +923,29 @@ static void musb_ep_program(struct musb *musb, u8 epnum, + * Unless caller treats short RX transfers as + * errors, we dare not queue multiple transfers. + */ +- dma_ok = dma_controller->channel_program(dma_channel, +- packet_sz, !(urb->transfer_flags & +- URB_SHORT_NOT_OK), +- urb->transfer_dma + offset, +- qh->segsize); ++ hw_ep->rx_channel->hw_ep = hw_ep; ++ ++ dma_ok = dma_controller->channel_program( ++ hw_ep->rx_channel, qh->maxpacket, ++ 1, urb->transfer_dma, len); ++ + if (!dma_ok) { + dma_controller->channel_release(dma_channel); + hw_ep->rx_channel = dma_channel = NULL; + } else +- csr |= MUSB_RXCSR_DMAENAB; ++ { ++ csr |= MUSB_RXCSR_DMAENAB; ++ ++ csr |= MUSB_RXCSR_DMAMODE; ++ csr |= MUSB_RXCSR_AUTOCLEAR; ++ csr |=MUSB_RXCSR_H_AUTOREQ; ++ } + } + + csr |= MUSB_RXCSR_H_REQPKT; + dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); + musb_writew(hw_ep->regs, MUSB_RXCSR, csr); +- csr = musb_readw(hw_ep->regs, MUSB_RXCSR); ++ csr = musb_readw(hw_ep->regs, MUSB_RXCSR); + } + } + +@@ -1089,8 +1166,10 @@ done: + */ + + #endif +- ++extern u8 usb_short_pack_flag; + /* Service a Tx-Available or dma completion irq for the endpoint */ ++ ++extern unsigned long time_1_start, time_1_end, time_1; + void musb_host_tx(struct musb *musb, u8 epnum) + { + int pipe; +@@ -1107,6 +1186,7 @@ void musb_host_tx(struct musb *musb, u8 epnum) + struct dma_channel *dma; + bool transfer_pending = false; + ++ + musb_ep_select(mbase, epnum); + tx_csr = musb_readw(epio, MUSB_TXCSR); + +@@ -1128,13 +1208,13 @@ void musb_host_tx(struct musb *musb, u8 epnum) + + /* stall; record URB status */ + status = -EPIPE; +- ++ printk("=============[%s %d]\n", __func__, __LINE__); + } else if (tx_csr & MUSB_TXCSR_H_ERROR) { + /* (NON-ISO) dma was disabled, fifo flushed */ + dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); + + status = -ETIMEDOUT; +- ++ printk("=============[%s %d]\n", __func__, __LINE__); + } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { + dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum); + +@@ -1150,12 +1230,14 @@ void musb_host_tx(struct musb *musb, u8 epnum) + musb_writew(epio, MUSB_TXCSR, + MUSB_TXCSR_H_WZC_BITS + | MUSB_TXCSR_TXPKTRDY); ++ printk("=============[%s %d]\n", __func__, __LINE__); + return; + } + + if (status) { + if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { + dma->status = MUSB_DMA_STATUS_CORE_ABORT; ++ printk("[%s %d]status-0x%08x-0x%08x\n", __func__, __LINE__, status, dma->status); + (void) musb->dma_controller->channel_abort(dma); + } + +@@ -1229,9 +1311,8 @@ void musb_host_tx(struct musb *musb, u8 epnum) + * too late (after TXPKTRDY was cleared by controller). + * Re-read TXCSR as we have spoiled its previous value. + */ +- tx_csr = musb_readw(epio, MUSB_TXCSR); ++ tx_csr = musb_readw(epio, MUSB_TXCSR); + } +- + /* + * We may get here from a DMA completion or TXPKTRDY interrupt. + * In any case, we must check the FIFO status here and bail out +@@ -1239,10 +1320,12 @@ void musb_host_tx(struct musb *musb, u8 epnum) + * "missed" TXPKTRDY interrupts and deal with double-buffered + * FIFO mode too... + */ ++ tx_csr = musb_readw(epio, MUSB_TXCSR); + if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { + dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " +- "CSR %04x\n", tx_csr); +- return; ++ "CSR %04x\n", tx_csr); ++ ++ return; + } + } + +@@ -1266,16 +1349,22 @@ void musb_host_tx(struct musb *musb, u8 epnum) + offset = d->offset; + length = d->length; + } +- } else if (dma && urb->transfer_buffer_length == qh->offset) { ++ } else if (dma && (urb->transfer_buffer_length == qh->offset)) { + done = true; + } else { + /* see if we need to send more data, or ZLP */ +- if (qh->segsize < qh->maxpacket) +- done = true; +- else if (qh->offset == urb->transfer_buffer_length +- && !(urb->transfer_flags +- & URB_ZERO_PACKET)) ++ if (!dma) { ++ if (qh->segsize < qh->maxpacket) { ++ done = true; ++ } ++ } ++ ++ if (qh->offset >= urb->transfer_buffer_length ++ && !(urb->transfer_flags ++ & URB_ZERO_PACKET)) { ++ + done = true; ++ } + if (!done) { + offset = qh->offset; + length = urb->transfer_buffer_length - offset; +@@ -1300,12 +1389,9 @@ void musb_host_tx(struct musb *musb, u8 epnum) + musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); + return; + } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { +- if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, +- offset, length)) { +- if (is_cppi_enabled() || tusb_dma_omap()) +- musb_h_tx_dma_start(hw_ep); +- return; +- } ++ musb_tx_dma_program(musb, musb->dma_controller, ++ hw_ep, qh, urb, ++ qh->offset, min((u32) hw_ep->max_packet_sz_tx, length)); + } else if (tx_csr & MUSB_TXCSR_DMAENAB) { + dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); + return; +@@ -1318,19 +1404,21 @@ void musb_host_tx(struct musb *musb, u8 epnum) + * (and presumably, FIFO is not half-full) we should write *two* + * packets before updating TXCSR; other docs disagree... + */ +- if (length > qh->maxpacket) +- length = qh->maxpacket; +- /* Unmap the buffer so that CPU can use it */ +- usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); +- musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); +- qh->segsize = length; +- +- musb_ep_select(mbase, epnum); +- musb_writew(epio, MUSB_TXCSR, +- MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); ++ if (!dma) { ++ if (length > qh->maxpacket) ++ length = qh->maxpacket; ++ ++ /* Unmap the buffer so that CPU can use it */ ++ usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); ++ musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); ++ ++ qh->segsize = length; ++ musb_ep_select(mbase, epnum); ++ musb_writew(epio, MUSB_TXCSR, ++ MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); ++ } + } + +- + #ifdef CONFIG_USB_INVENTRA_DMA + + /* Host side RX (IN) using Mentor DMA works as follows: +@@ -1418,6 +1506,8 @@ static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) + * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, + * and high-bandwidth IN transfer cases. + */ ++ ++ + void musb_host_rx(struct musb *musb, u8 epnum) + { + struct urb *urb; +@@ -1430,14 +1520,12 @@ void musb_host_rx(struct musb *musb, u8 epnum) + u16 rx_csr, val; + bool iso_err = false; + bool done = false; +- u32 status; +- struct dma_channel *dma; +- ++ u32 status = 0; ++ struct dma_channel *dma = NULL; ++ static int temp_dma_lenth = 0; + musb_ep_select(mbase, epnum); +- + urb = next_urb(qh); + dma = is_dma_capable() ? hw_ep->rx_channel : NULL; +- status = 0; + xfer_len = 0; + + rx_csr = musb_readw(epio, MUSB_RXCSR); +@@ -1464,18 +1552,15 @@ void musb_host_rx(struct musb *musb, u8 epnum) + * handled yet! */ + if (rx_csr & MUSB_RXCSR_H_RXSTALL) { + dev_dbg(musb->controller, "RX end %d STALL\n", epnum); +- + /* stall; record URB status */ + status = -EPIPE; + + } else if (rx_csr & MUSB_RXCSR_H_ERROR) { + dev_dbg(musb->controller, "end %d RX proto error\n", epnum); +- + status = -EPROTO; + musb_writeb(epio, MUSB_RXINTERVAL, 0); + + } else if (rx_csr & MUSB_RXCSR_DATAERROR) { +- + if (USB_ENDPOINT_XFER_ISOC != qh->type) { + dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); + +@@ -1524,11 +1609,17 @@ void musb_host_rx(struct musb *musb, u8 epnum) + goto finish; + } + +- if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { +- /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ +- ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); +- goto finish; +- } ++ if(dma_en == 0) ++ { ++ if((musb_readw(epio, MUSB_RXCOUNT) == 0) || (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) ++ { ++ //printk("dma busy use pio\n"); ++ dma = NULL; ++ } ++ } ++ ++ if(qh->maxpacket<512) ++ dma = NULL; + + /* thorough shutdown for now ... given more precise fault handling + * and better queueing support, we might keep a DMA pipeline going +@@ -1560,13 +1651,16 @@ void musb_host_rx(struct musb *musb, u8 epnum) + MUSB_RXCSR_H_WZC_BITS | rx_csr); + } + #endif +- if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { ++ if (dma && (dma_en == 1)) { ++ //printk("HRM\n"); ++ dma_en = 0; + xfer_len = dma->actual_len; + + val &= ~(MUSB_RXCSR_DMAENAB + | MUSB_RXCSR_H_AUTOREQ + | MUSB_RXCSR_AUTOCLEAR +- | MUSB_RXCSR_RXPKTRDY); ++ | MUSB_RXCSR_RXPKTRDY ++ |MUSB_RXCSR_DMAMODE); + musb_writew(hw_ep->regs, MUSB_RXCSR, val); + + #ifdef CONFIG_USB_INVENTRA_DMA +@@ -1592,9 +1686,18 @@ void musb_host_rx(struct musb *musb, u8 epnum) + done = (urb->actual_length + xfer_len >= + urb->transfer_buffer_length + || dma->actual_len < qh->maxpacket); +- } + ++ ++ } ++ if(urb->align == 0) ++ { ++ if (usb_pipeisoc(pipe)) ++ memcpy(urb->transfer_buffer + (urb->iso_frame_desc + qh->iso_idx)->offset ,dma_buf_rx.vm_valid_addr,temp_dma_lenth); ++ else ++ memcpy(urb->transfer_buffer + urb->actual_length ,dma_buf_rx.vm_valid_addr,temp_dma_lenth); ++ } + /* send IN token for next packet, without AUTOREQ */ ++ val = musb_readw(epio, MUSB_RXCSR); + if (!done) { + val |= MUSB_RXCSR_H_REQPKT; + musb_writew(epio, MUSB_RXCSR, +@@ -1616,7 +1719,7 @@ void musb_host_rx(struct musb *musb, u8 epnum) + + /* FIXME this is another "SHOULD NEVER HAPPEN" */ + +-/* SCRUB (RX) */ ++ /* SCRUB (RX) */ + /* do the proper sequence to abort the transfer */ + musb_ep_select(mbase, epnum); + val &= ~MUSB_RXCSR_H_REQPKT; +@@ -1632,6 +1735,7 @@ void musb_host_rx(struct musb *musb, u8 epnum) + int ret, length; + dma_addr_t buf; + ++ dma_en = 1; + rx_count = musb_readw(epio, MUSB_RXCOUNT); + + dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", +@@ -1671,26 +1775,7 @@ void musb_host_rx(struct musb *musb, u8 epnum) + buf = urb->transfer_dma + + urb->actual_length; + } +- +- dma->desired_mode = 0; +-#ifdef USE_MODE1 +- /* because of the issue below, mode 1 will +- * only rarely behave with correct semantics. +- */ +- if ((urb->transfer_flags & +- URB_SHORT_NOT_OK) +- && (urb->transfer_buffer_length - +- urb->actual_length) +- > qh->maxpacket) +- dma->desired_mode = 1; +- if (rx_count < hw_ep->max_packet_sz_rx) { +- length = rx_count; +- dma->desired_mode = 0; +- } else { +- length = urb->transfer_buffer_length; +- } +-#endif +- ++ + /* Disadvantage of using mode 1: + * It's basically usable only for mass storage class; essentially all + * other protocols also terminate transfers on short packets. +@@ -1707,32 +1792,35 @@ void musb_host_rx(struct musb *musb, u8 epnum) + * completed, you will find rxcount 0. Okay, so you might think why not + * wait for an interrupt when the pkt is recd. Well, you won't get any! + */ +- + val = musb_readw(epio, MUSB_RXCSR); + val &= ~MUSB_RXCSR_H_REQPKT; +- +- if (dma->desired_mode == 0) +- val &= ~MUSB_RXCSR_H_AUTOREQ; +- else +- val |= MUSB_RXCSR_H_AUTOREQ; ++ val &= ~MUSB_RXCSR_H_AUTOREQ; + val |= MUSB_RXCSR_DMAENAB; +- +- /* autoclear shouldn't be set in high bandwidth */ +- if (qh->hb_mult == 1) +- val |= MUSB_RXCSR_AUTOCLEAR; +- ++ qh->hb_mult = 0; ++ dma->desired_mode = 0; + musb_writew(epio, MUSB_RXCSR, + MUSB_RXCSR_H_WZC_BITS | val); +- ++ + /* REVISIT if when actual_length != 0, + * transfer_buffer_length needs to be + * adjusted first... + */ +- ret = c->channel_program( +- dma, qh->maxpacket, +- dma->desired_mode, buf, length); +- ++ hw_ep->rx_channel->hw_ep = hw_ep; ++ ++ if (buf & 0x7) ++ { ++ urb->align = 0; ++ temp_dma_lenth = length; ++ ret = c->channel_program(dma, qh->maxpacket,dma->desired_mode, dma_buf_rx.phy_valid_addr, length); ++ } ++ else ++ { ++ urb->align = 1; ++ ret = c->channel_program(dma, qh->maxpacket,dma->desired_mode, buf, length); ++ } ++ + if (!ret) { ++ printk("lsk:dma err\n"); + c->channel_release(dma); + hw_ep->rx_channel = NULL; + dma = NULL; +@@ -1756,6 +1844,7 @@ finish: + if (done) { + if (urb->status == -EINPROGRESS) + urb->status = status; ++ //printk("end urb %p\n",urb); + musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); + } + } +@@ -1765,19 +1854,22 @@ finish: + * host side hardware endpoint + direction; scheduling may activate + * that hardware endpoint. + */ ++int last_tx_epnum = 3; ++int last_rx_epnum = 0; ++int rx_cnt = 1; + static int musb_schedule( + struct musb *musb, + struct musb_qh *qh, + int is_in) + { +- int idle; +- int best_diff; +- int best_end, epnum; +- struct musb_hw_ep *hw_ep = NULL; +- struct list_head *head = NULL; +- u8 toggle; +- u8 txtype; +- struct urb *urb = next_urb(qh); ++ int idle; ++ int best_diff; ++ int best_end, epnum; ++ struct musb_hw_ep *hw_ep = NULL; ++ struct list_head *head = NULL; ++ u8 toggle; ++ u8 txtype; ++ struct urb *urb = next_urb(qh); + + /* use fixed hardware for control and bulk */ + if (qh->type == USB_ENDPOINT_XFER_CONTROL) { +@@ -1849,20 +1941,27 @@ static int musb_schedule( + else + head = &musb->out_bulk; + +- /* Enable bulk RX NAK timeout scheme when bulk requests are +- * multiplexed. This scheme doen't work in high speed to full ++ /* Enable bulk RX/TX NAK timeout scheme when bulk requests are ++ * multiplexed. This scheme does not work in high speed to full + * speed scenario as NAK interrupts are not coming from a + * full speed device connected to a high speed device. + * NAK timeout interval is 8 (128 uframe or 16ms) for HS and + * 4 (8 frame or 8ms) for FS device. + */ +- if (is_in && qh->dev) ++ if (qh->dev) + qh->intv_reg = + (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; + goto success; +- } else if (best_end < 0) { +- return -ENOSPC; +- } ++ } else if ((best_end > 0) && (qh->type == USB_ENDPOINT_XFER_BULK)) { ++ if (is_in) { ++ } else { ++ head = &musb->out_bulk; ++ } ++ } else { ++ if (best_end < 0) { ++ return -ENOSPC; ++ } ++ } + + idle = 1; + qh->mux = 0; +@@ -2254,8 +2353,29 @@ static int musb_h_start(struct usb_hcd *hcd) + /* NOTE: musb_start() is called when the hub driver turns + * on port power, or when (OTG) peripheral starts. + */ +- hcd->state = HC_STATE_RUNNING; ++ hcd->state = HC_STATE_RUNNING; + musb->port1_status = 0; ++ ++ dma_buf_tx.size = 1024*100; ++ dma_buf_tx.vm_addr = dma_alloc_coherent(NULL, dma_buf_tx.size, &dma_buf_tx.phy_addr, GFP_KERNEL); ++ //printk("vm : %p, phy : %p\n", dma_buf.vm_addr, dma_buf.phy_addr); ++ if (dma_buf_tx.vm_addr == NULL) { ++ printk("dma_buf alloc faild!\n"); ++ } else { ++ dma_buf_tx.phy_valid_addr = dma_buf_tx.phy_addr & 0xfffffff8; ++ dma_buf_tx.vm_valid_addr = (void *)((int)dma_buf_tx.vm_addr & 0xfffffff8); ++ } ++#if defined(CONFIG_GK_MUSB_CON_V1_10) ++ dma_buf_rx.size = 1024*100; ++ dma_buf_rx.vm_addr = dma_alloc_coherent(NULL, dma_buf_rx.size, &dma_buf_rx.phy_addr, GFP_KERNEL); ++ //printk("vm : %p, phy : %p\n", dma_buf.vm_addr, dma_buf.phy_addr); ++ if (dma_buf_rx.vm_addr == NULL) { ++ printk("dma_buf alloc faild!\n"); ++ } else { ++ dma_buf_rx.phy_valid_addr = dma_buf_rx.phy_addr & 0xfffffff8; ++ dma_buf_rx.vm_valid_addr = (void *)((int)dma_buf_rx.vm_addr & 0xfffffff8); ++ } ++#endif + return 0; + } + +@@ -2263,6 +2383,12 @@ static void musb_h_stop(struct usb_hcd *hcd) + { + musb_stop(hcd_to_musb(hcd)); + hcd->state = HC_STATE_HALT; ++ // Steven Yu: ++ // dma_buf.vm_addr alloced by dma_alloc_coherent, so must use dma_free_coherent to free. ++ dma_free_coherent(NULL, dma_buf_tx.size, dma_buf_tx.vm_addr, dma_buf_tx.phy_addr); ++#if defined(CONFIG_GK_MUSB_CON_V1_10) ++ dma_free_coherent(NULL, dma_buf_rx.size, dma_buf_rx.vm_addr, dma_buf_rx.phy_addr); ++#endif + } + + static int musb_bus_suspend(struct usb_hcd *hcd) +diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h +index 1d5eda26..f1be4284 100644 +--- a/drivers/usb/musb/musb_io.h ++++ b/drivers/usb/musb/musb_io.h +@@ -36,6 +36,10 @@ + #define __MUSB_LINUX_PLATFORM_ARCH_H__ + + #include ++#include ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ + + #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \ + && !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \ +@@ -60,19 +64,18 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len) + #ifndef CONFIG_BLACKFIN + + /* NOTE: these offsets are all in bytes */ ++static inline u16 musb_readw(const void __iomem *addr, unsigned int offset) ++ { return gk_musb_readw((unsigned int)addr, offset); } + +-static inline u16 musb_readw(const void __iomem *addr, unsigned offset) +- { return __raw_readw(addr + offset); } ++static inline u32 musb_readl(const void __iomem *addr, unsigned int offset) ++ { return gk_musb_readl((unsigned int)addr, offset); } + +-static inline u32 musb_readl(const void __iomem *addr, unsigned offset) +- { return __raw_readl(addr + offset); } + ++static inline void musb_writew(void __iomem *addr, unsigned int offset, u16 data) ++ { gk_musb_writew((unsigned int)addr, offset, data); } + +-static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data) +- { __raw_writew(data, addr + offset); } +- +-static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data) +- { __raw_writel(data, addr + offset); } ++static inline void musb_writel(void __iomem *addr, unsigned int offset, u32 data) ++ { gk_musb_writel((unsigned int)addr, offset, data); } + + + #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) +@@ -80,7 +83,7 @@ static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data) + /* + * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. + */ +-static inline u8 musb_readb(const void __iomem *addr, unsigned offset) ++static inline u8 musb_readb(const void __iomem *addr, unsigned int offset) + { + u16 tmp; + u8 val; +@@ -94,7 +97,7 @@ static inline u8 musb_readb(const void __iomem *addr, unsigned offset) + return val; + } + +-static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data) ++static inline void musb_writeb(void __iomem *addr, unsigned int offset, u8 data) + { + u16 tmp; + +@@ -110,10 +113,11 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data) + #else + + static inline u8 musb_readb(const void __iomem *addr, unsigned offset) +- { return __raw_readb(addr + offset); } ++ { return gk_musb_readb((unsigned int)addr, offset); } + + static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data) +- { __raw_writeb(data, addr + offset); } ++ { gk_musb_writeb((unsigned int)addr, offset, data); } ++ + + #endif /* CONFIG_USB_MUSB_TUSB6010 */ + +diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h +index 03f2655a..40f4bdf8 100644 +--- a/drivers/usb/musb/musb_regs.h ++++ b/drivers/usb/musb/musb_regs.h +@@ -213,9 +213,6 @@ + /* HUBADDR */ + #define MUSB_HUBADDR_MULTI_TT 0x80 + +- +-#ifndef CONFIG_BLACKFIN +- + /* + * Common USB registers + */ +@@ -234,13 +231,12 @@ + #define MUSB_TESTMODE 0x0F /* 8 bit */ + + /* Get offset for a given FIFO from musb->mregs */ +-#if defined(CONFIG_USB_MUSB_TUSB6010) || \ +- defined(CONFIG_USB_MUSB_TUSB6010_MODULE) +-#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20)) +-#else +-#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4)) ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++#define MUSB_FIFO_EP_OFFSET 0x8 ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++#define MUSB_FIFO_EP_OFFSET 0x40 //8 gk7101s/gk8601->0x40 + #endif +- ++#define MUSB_FIFO_OFFSET(epnum) (0x400 + ((epnum) * MUSB_FIFO_EP_OFFSET)) + /* + * Additional Control Registers + */ +@@ -296,14 +292,6 @@ + #define MUSB_FLAT_OFFSET(_epnum, _offset) \ + (0x100 + (0x10*(_epnum)) + (_offset)) + +-#if defined(CONFIG_USB_MUSB_TUSB6010) || \ +- defined(CONFIG_USB_MUSB_TUSB6010_MODULE) +-/* TUSB6010 EP0 configuration register is special */ +-#define MUSB_TUSB_OFFSET(_epnum, _offset) \ +- (0x10 + _offset) +-#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */ +-#endif +- + #define MUSB_TXCSR_MODE 0x2000 + + /* "bus control"/target registers, for host side multipoint (external hubs) */ +@@ -453,193 +441,4 @@ static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum) + return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT)); + } + +-#else /* CONFIG_BLACKFIN */ +- +-#define USB_BASE USB_FADDR +-#define USB_OFFSET(reg) (reg - USB_BASE) +- +-/* +- * Common USB registers +- */ +-#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */ +-#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */ +-#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */ +-#define MUSB_INTRRX USB_OFFSET(USB_INTRRX) +-#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE) +-#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE) +-#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */ +-#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */ +-#define MUSB_FRAME USB_OFFSET(USB_FRAME) +-#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */ +-#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */ +- +-/* Get offset for a given FIFO from musb->mregs */ +-#define MUSB_FIFO_OFFSET(epnum) \ +- (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8)) +- +-/* +- * Additional Control Registers +- */ +- +-#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */ +- +-#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */ +-#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */ +-#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */ +-#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */ +-#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */ +- +-/* Offsets to endpoint registers */ +-#define MUSB_TXMAXP 0x00 +-#define MUSB_TXCSR 0x04 +-#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ +-#define MUSB_RXMAXP 0x08 +-#define MUSB_RXCSR 0x0C +-#define MUSB_RXCOUNT 0x10 +-#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ +-#define MUSB_TXTYPE 0x14 +-#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ +-#define MUSB_TXINTERVAL 0x18 +-#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ +-#define MUSB_RXTYPE 0x1C +-#define MUSB_RXINTERVAL 0x20 +-#define MUSB_TXCOUNT 0x28 +- +-/* Offsets to endpoint registers in indexed model (using INDEX register) */ +-#define MUSB_INDEXED_OFFSET(_epnum, _offset) \ +- (0x40 + (_offset)) +- +-/* Offsets to endpoint registers in flat models */ +-#define MUSB_FLAT_OFFSET(_epnum, _offset) \ +- (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset)) +- +-/* Not implemented - HW has separate Tx/Rx FIFO */ +-#define MUSB_TXCSR_MODE 0x0000 +- +-static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) +-{ +-} +- +-static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off) +-{ +-} +- +-static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size) +-{ +-} +- +-static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off) +-{ +-} +- +-static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val) +-{ +-} +- +-static inline u8 musb_read_txfifosz(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u16 musb_read_txfifoadd(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u8 musb_read_rxfifosz(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u16 musb_read_rxfifoadd(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u8 musb_read_configdata(void __iomem *mbase) +-{ +- return 0; +-} +- +-static inline u16 musb_read_hwvers(void __iomem *mbase) +-{ +- /* +- * This register is invisible on Blackfin, actually the MUSB +- * RTL version of Blackfin is 1.9, so just harcode its value. +- */ +- return MUSB_HWVERS_1900; +-} +- +-static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase) +-{ +- return NULL; +-} +- +-static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, +- u8 qh_addr_req) +-{ +-} +- +-static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs, +- u8 qh_h_addr_reg) +-{ +-} +- +-static inline void musb_write_rxhubport(void __iomem *ep_target_regs, +- u8 qh_h_port_reg) +-{ +-} +- +-static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, +- u8 qh_addr_reg) +-{ +-} +- +-static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, +- u8 qh_addr_reg) +-{ +-} +- +-static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, +- u8 qh_h_port_reg) +-{ +-} +- +-static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum) +-{ +- return 0; +-} +- +-#endif /* CONFIG_BLACKFIN */ +- + #endif /* __MUSB_REGS_H__ */ +diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c +index 57a60858..021535b1 100644 +--- a/drivers/usb/musb/musbhsdma.c ++++ b/drivers/usb/musb/musbhsdma.c +@@ -30,352 +30,415 @@ + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ ++ ++#include + #include + #include + #include + #include ++#include ++#include + #include "musb_core.h" + #include "musbhsdma.h" + +-static int dma_controller_start(struct dma_controller *c) +-{ +- /* nothing to do */ +- return 0; +-} ++#include ++#include + +-static void dma_channel_release(struct dma_channel *channel); ++#if CONFIG_USB_MUSB_GK ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++#include ++#include ++#include + +-static int dma_controller_stop(struct dma_controller *c) +-{ +- struct musb_dma_controller *controller = container_of(c, +- struct musb_dma_controller, controller); +- struct musb *musb = controller->private_data; +- struct dma_channel *channel; +- u8 bit; + +- if (controller->used_channels != 0) { +- dev_err(musb->controller, +- "Stopping DMA controller while channel active\n"); ++#define SIZE_4M 0x00400000 /* 4M */ ++#define DMA_LONG_WORD_MASK 0x3 ++#define DMA_CHAN 3 ++#endif + +- for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { +- if (controller->used_channels & (1 << bit)) { +- channel = &controller->channel[bit].channel; +- dma_channel_release(channel); ++struct semaphore sema_trans; + +- if (!controller->used_channels) +- break; +- } +- } +- } ++unsigned long time_start, time_end, time; + +- return 0; +-} ++unsigned long time_1_start, time_1_end, time_1; + +-static struct dma_channel *dma_channel_allocate(struct dma_controller *c, +- struct musb_hw_ep *hw_ep, u8 transmit) +-{ +- struct musb_dma_controller *controller = container_of(c, +- struct musb_dma_controller, controller); +- struct musb_dma_channel *musb_channel = NULL; +- struct dma_channel *channel = NULL; +- u8 bit; +- +- for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { +- if (!(controller->used_channels & (1 << bit))) { +- controller->used_channels |= (1 << bit); +- musb_channel = &(controller->channel[bit]); +- musb_channel->controller = controller; +- musb_channel->idx = bit; +- musb_channel->epnum = hw_ep->epnum; +- musb_channel->transmit = transmit; +- channel = &(musb_channel->channel); +- channel->private_data = musb_channel; +- channel->status = MUSB_DMA_STATUS_FREE; +- channel->max_len = 0x100000; +- /* Tx => mode 1; Rx => mode 0 */ +- channel->desired_mode = transmit; +- channel->actual_len = 0; +- break; +- } +- } + +- return channel; +-} ++struct gk_dma_channel { ++ struct dma_channel channel; ++ struct gk_dma_controller *controller; ++ struct musb_hw_ep *hw_ep; ++ struct dma_chan *dma_chan; ++ unsigned int cur_len; ++ gk_dma_req_t req; ++ //dma_cookie_t cookie; ++ u8 ch_num; ++ u8 is_tx; ++ u8 is_allocated; ++ u16 max_packet_sz; ++ u16 short_packet; ++}; + +-static void dma_channel_release(struct dma_channel *channel) +-{ +- struct musb_dma_channel *musb_channel = channel->private_data; ++struct gk_dma_controller { ++ struct dma_controller controller; ++ struct gk_dma_channel rx_channel; ++ struct gk_dma_channel tx_channel; + +- channel->actual_len = 0; +- musb_channel->start_addr = 0; +- musb_channel->len = 0; ++ void *private_data; ++ void __iomem *base; + +- musb_channel->controller->used_channels &= +- ~(1 << musb_channel->idx); ++ u8 ch_num; ++ u8 is_tx; ++}; + +- channel->status = MUSB_DMA_STATUS_UNKNOWN; ++struct gk_dma_controller *controller_irq; ++struct gk_dma_controller *controller_irq_rx; ++u8 usb_short_pack_flag=0; ++ ++void gk_usb_dma_irq_tx(void *dev_id, u32 status) ++{ ++ u8 ep; ++ u8 *mbase; ++ u8 devctl; ++ struct gk_dma_channel *gk_channel; ++ struct gk_dma_controller *controller = NULL; ++ struct musb *musb = NULL; ++ unsigned long flags; ++ ++ controller = (struct gk_dma_controller *)controller_irq; ++ ++ if (controller == NULL) { ++ printk("ERROR : controller is null\n"); ++ return; ++ } ++ ++ musb = controller->private_data; ++ mbase = musb->mregs; ++ spin_lock_irqsave(&musb->lock, flags); ++ ++ gk_channel = &(controller->tx_channel); ++ gk_channel->channel.status = MUSB_DMA_STATUS_FREE; ++ devctl = musb_readb(mbase, MUSB_DEVCTL); ++ ep = gk_channel->hw_ep->epnum; ++ ++ //printk("d1t irq=0x%d\n",irq); ++ if (gk_channel->channel.desired_mode) ++ { ++ int offset = MUSB_EP_OFFSET(ep, MUSB_TXCSR); ++ u16 txcsr,tmp,flag; ++ //printk("d1t\n"); ++ /* ++ * The programming guide says that we ++ * must clear DMAENAB before DMAMODE. ++ */ ++ musb_ep_select(mbase, ep); ++ txcsr = musb_readw(mbase, offset); ++ tmp=txcsr; ++ flag=0; ++ if(tmp&(MUSB_TXCSR_TXPKTRDY|MUSB_TXCSR_FIFONOTEMPTY)) ++ { ++ //printk("d1t\n"); ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ txcsr &= ~(MUSB_TXCSR_DMAENAB ++ | MUSB_TXCSR_AUTOSET|MUSB_TXCSR_TXPKTRDY); ++ musb_writew(mbase, offset, txcsr|MUSB_TXCSR_H_WZC_BITS); ++ ++ txcsr &= ~(MUSB_TXCSR_DMAMODE|MUSB_TXCSR_TXPKTRDY); ++ musb_writew(mbase, offset, txcsr|MUSB_TXCSR_H_WZC_BITS); ++ tmp = musb_readw(mbase, offset); ++ #ifdef CONFIG_USB_INVENTRA_DMA ++ if((tmp&(MUSB_TXCSR_TXPKTRDY|MUSB_TXCSR_FIFONOTEMPTY))==0) ++ musb_dma_completion(musb,ep,1); ++ #endif ++#else ++ txcsr &= ~(MUSB_TXCSR_DMAENAB ++ | MUSB_TXCSR_AUTOSET|MUSB_TXCSR_TXPKTRDY); ++ musb_writew(mbase, offset, txcsr|MUSB_TXCSR_P_WZC_BITS); ++ ++ txcsr &= ~(MUSB_TXCSR_DMAMODE|MUSB_TXCSR_TXPKTRDY); ++ musb_writew(mbase, offset, txcsr|MUSB_TXCSR_P_WZC_BITS); ++ tmp = musb_readw(mbase, offset); ++ #ifdef CONFIG_USB_INVENTRA_DMA ++ if((tmp&(MUSB_TXCSR_TXPKTRDY|MUSB_TXCSR_FIFONOTEMPTY))==0) ++ musb_dma_completion(musb,ep,1); ++ #endif ++#endif ++ } ++ else ++ { ++ //printk("d0t\n"); ++ txcsr &= ~(MUSB_TXCSR_DMAENAB ++ | MUSB_TXCSR_AUTOSET); ++ musb_writew(mbase, offset, txcsr); ++ txcsr &= ~(MUSB_TXCSR_DMAMODE); ++ musb_writew(mbase, offset, txcsr); ++#ifdef CONFIG_USB_INVENTRA_DMA ++ usb_short_pack_flag=0; ++ if(gk_channel->short_packet) ++ { ++ txcsr |= MUSB_TXCSR_TXPKTRDY; ++#if defined(CONFIG_GK_USB_HOST_MODE) ++ musb_writew(mbase, offset, txcsr); ++#endif ++ usb_short_pack_flag=1; ++ gk_channel->short_packet=0; ++ } ++else ++ musb_dma_completion(musb,ep,1); ++#endif ++ } ++ } ++ else ++ { ++ int offset = MUSB_EP_OFFSET(ep, MUSB_TXCSR); ++ u16 txcsr; ++ //printk("0t\n"); ++ /* ++ * The programming guide says that we ++ * must clear DMAENAB before DMAMODE. ++ */ ++ musb_ep_select(mbase, ep); ++ txcsr = musb_readw(mbase, offset); ++ txcsr &= ~(MUSB_TXCSR_DMAENAB | ++ MUSB_TXCSR_DMAMODE | ++ MUSB_TXCSR_AUTOSET ); ++ txcsr |= MUSB_TXCSR_TXPKTRDY; ++ musb_writew(mbase, offset, txcsr); ++ } ++ ++ ++ spin_unlock_irqrestore(&musb->lock, flags); + } + +-static void configure_channel(struct dma_channel *channel, +- u16 packet_sz, u8 mode, +- dma_addr_t dma_addr, u32 len) ++void gk_usb_dma_irq_rx(void *dev_id, u32 status) + { +- struct musb_dma_channel *musb_channel = channel->private_data; +- struct musb_dma_controller *controller = musb_channel->controller; +- struct musb *musb = controller->private_data; +- void __iomem *mbase = controller->base; +- u8 bchannel = musb_channel->idx; +- u16 csr = 0; ++ u8 ep; ++ u8 *mbase; ++ u8 devctl; + +- dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", +- channel, packet_sz, dma_addr, len, mode); ++ struct gk_dma_channel *gk_channel; ++ struct gk_dma_controller *controller = NULL; ++ struct musb *musb = NULL; ++ unsigned long flags; ++ //printk("d1t irq=0x%d\n",status); + +- if (mode) { +- csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; +- BUG_ON(len < packet_sz); +- } +- csr |= MUSB_HSDMA_BURSTMODE_INCR16 +- << MUSB_HSDMA_BURSTMODE_SHIFT; +- +- csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) +- | (1 << MUSB_HSDMA_ENABLE_SHIFT) +- | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) +- | (musb_channel->transmit +- ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) +- : 0); +- +- /* address/count */ +- musb_write_hsdma_addr(mbase, bchannel, dma_addr); +- musb_write_hsdma_count(mbase, bchannel, len); +- +- /* control (this should start things) */ +- musb_writew(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), +- csr); +-} ++ controller = (struct gk_dma_controller *)controller_irq_rx; + +-static int dma_channel_program(struct dma_channel *channel, +- u16 packet_sz, u8 mode, +- dma_addr_t dma_addr, u32 len) +-{ +- struct musb_dma_channel *musb_channel = channel->private_data; +- struct musb_dma_controller *controller = musb_channel->controller; +- struct musb *musb = controller->private_data; ++ if (controller == NULL) { ++ printk("ERROR : controller is null\n"); ++ return; ++ } + +- dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", +- musb_channel->epnum, +- musb_channel->transmit ? "Tx" : "Rx", +- packet_sz, dma_addr, len, mode); ++ musb = controller->private_data; ++ mbase = musb->mregs; + +- BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || +- channel->status == MUSB_DMA_STATUS_BUSY); ++ spin_lock_irqsave(&musb->lock, flags); + +- /* Let targets check/tweak the arguments */ +- if (musb->ops->adjust_channel_params) { +- int ret = musb->ops->adjust_channel_params(channel, +- packet_sz, &mode, &dma_addr, &len); +- if (ret) +- return ret; +- } ++ gk_channel = &(controller->rx_channel) ; + +- /* +- * The DMA engine in RTL1.8 and above cannot handle +- * DMA addresses that are not aligned to a 4 byte boundary. +- * It ends up masking the last two bits of the address +- * programmed in DMA_ADDR. +- * +- * Fail such DMA transfers, so that the backup PIO mode +- * can carry out the transfer +- */ +- if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4)) +- return false; ++ gk_channel->channel.status = MUSB_DMA_STATUS_FREE; + +- channel->actual_len = 0; +- musb_channel->start_addr = dma_addr; +- musb_channel->len = len; +- musb_channel->max_packet_sz = packet_sz; +- channel->status = MUSB_DMA_STATUS_BUSY; ++ devctl = musb_readb(mbase, MUSB_DEVCTL); ++ ep = gk_channel->hw_ep->epnum; + +- configure_channel(channel, packet_sz, mode, dma_addr, len); ++#ifdef CONFIG_USB_INVENTRA_DMA ++ musb_dma_completion(musb,ep,0); ++#endif + +- return true; ++ spin_unlock_irqrestore(&musb->lock, flags); + } + +-static int dma_channel_abort(struct dma_channel *channel) ++static struct dma_channel *gk_dma_channel_allocate(struct dma_controller *c, ++ struct musb_hw_ep *hw_ep, u8 is_tx) + { +- struct musb_dma_channel *musb_channel = channel->private_data; +- void __iomem *mbase = musb_channel->controller->base; ++ struct gk_dma_controller *controller = container_of(c, ++ struct gk_dma_controller, controller); ++ struct gk_dma_channel *gk_channel = NULL; ++ static int dma_alloc_rx_init = 0,dma_alloc_tx_init = 0; + +- u8 bchannel = musb_channel->idx; +- int offset; +- u16 csr; ++ if (hw_ep->epnum == 0) { ++ return NULL; ++ } + +- if (channel->status == MUSB_DMA_STATUS_BUSY) { +- if (musb_channel->transmit) { +- offset = MUSB_EP_OFFSET(musb_channel->epnum, +- MUSB_TXCSR); +- +- /* +- * The programming guide says that we must clear +- * the DMAENAB bit before the DMAMODE bit... +- */ +- csr = musb_readw(mbase, offset); +- csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); +- musb_writew(mbase, offset, csr); +- csr &= ~MUSB_TXCSR_DMAMODE; +- musb_writew(mbase, offset, csr); +- } else { +- offset = MUSB_EP_OFFSET(musb_channel->epnum, +- MUSB_RXCSR); ++ gk_channel = is_tx ? &(controller->tx_channel) : &(controller->rx_channel) ; + +- csr = musb_readw(mbase, offset); +- csr &= ~(MUSB_RXCSR_AUTOCLEAR | +- MUSB_RXCSR_DMAENAB | +- MUSB_RXCSR_DMAMODE); +- musb_writew(mbase, offset, csr); +- } ++ /* Check if channel is already used. */ + +- musb_writew(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), +- 0); +- musb_write_hsdma_addr(mbase, bchannel, 0); +- musb_write_hsdma_count(mbase, bchannel, 0); +- channel->status = MUSB_DMA_STATUS_FREE; ++ controller->ch_num = hw_ep->epnum; ++ controller->is_tx = is_tx; ++ ++ gk_channel->hw_ep = hw_ep; ++ gk_channel->is_allocated = 1; ++ gk_channel->ch_num = hw_ep->epnum; ++ gk_channel->is_tx = is_tx; ++ ++ gk_channel->channel.private_data = gk_channel; ++ gk_channel->channel.max_len = SIZE_4M; ++ if(!is_tx && dma_alloc_rx_init == 0) ++ { ++ dma_alloc_rx_init = 1; ++ gk_channel->channel.status = MUSB_DMA_STATUS_FREE; ++ } ++ if(is_tx && dma_alloc_tx_init == 0) ++ { ++ dma_alloc_tx_init = 1; ++ gk_channel->channel.status = MUSB_DMA_STATUS_FREE; + } + +- return 0; ++ gk_channel->controller = controller; ++ ++ ++ ++ ++ return &(gk_channel->channel); + } + +-static irqreturn_t dma_controller_irq(int irq, void *private_data) ++static void gk_dma_channel_release(struct dma_channel *channel) + { +- struct musb_dma_controller *controller = private_data; +- struct musb *musb = controller->private_data; +- struct musb_dma_channel *musb_channel; +- struct dma_channel *channel; ++ struct gk_dma_channel *gk_channel = channel->private_data; + +- void __iomem *mbase = controller->base; ++ gk_channel->is_allocated = 0; ++ channel->status = MUSB_DMA_STATUS_FREE; ++ channel->actual_len = 0; + +- irqreturn_t retval = IRQ_NONE; ++} + +- unsigned long flags; ++static int gk_dma_channel_program(struct dma_channel *channel, ++ u16 packet_sz, u8 mode, ++ dma_addr_t dma_addr, u32 len) ++{ ++ struct gk_dma_channel *gk_channel = channel->private_data; ++ gk_dma_req_t *req = &gk_channel->req; ++ struct gk_dma_controller *controller = gk_channel->controller; ++ unsigned char trans_size = 0; + +- u8 bchannel; +- u8 int_hsdma; + +- u32 addr, count; +- u16 csr; ++ if(len <= 0) return false; ++ if(packet_sz & 0x3) return false; ++ if((int)dma_addr & 0x7) return false; + +- spin_lock_irqsave(&musb->lock, flags); ++ gk_channel->max_packet_sz = packet_sz; + +- int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); ++ channel->status = MUSB_DMA_STATUS_BUSY; ++ channel->desired_mode = mode; + +-#ifdef CONFIG_BLACKFIN +- /* Clear DMA interrupt flags */ +- musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); +-#endif ++ if ((len % 8) == 0) { ++ trans_size = 3; ++ } else if ((len % 4) == 0) { ++ trans_size = 2; ++ } else if ((len % 2) == 0) { ++ trans_size = 1; ++ } else { ++ trans_size = 0; ++ } + +- if (!int_hsdma) { +- dev_dbg(musb->controller, "spurious DMA irq\n"); ++ channel->actual_len = len; ++ controller->is_tx = gk_channel->is_tx; ++ gk_channel->hw_ep = channel->hw_ep; + +- for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { +- musb_channel = (struct musb_dma_channel *) +- &(controller->channel[bchannel]); +- channel = &musb_channel->channel; +- if (channel->status == MUSB_DMA_STATUS_BUSY) { +- count = musb_read_hsdma_count(mbase, bchannel); + +- if (count == 0) +- int_hsdma |= (1 << bchannel); +- } +- } + +- dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma); ++ if(controller->is_tx) ++ { ++ controller_irq = controller; ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++ req->dst = (u32)gk_channel->hw_ep->fifo - 0x90000000; ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++ req->dst = (u32)gk_virt_to_phys((u32)(gk_channel->hw_ep->fifo)); ++#endif ++ if((mode)&&(len%packet_sz)) ++ gk_channel->short_packet=1; ++ else ++ gk_channel->short_packet=0; ++ req->src = dma_addr; //ddr addr ++ req->xfr_count = len; ++ gk_dma_writel(DMA_CHAN_SRC_REG(DMA_CHAN_TX), req->src); ++ gk_dma_writel(DMA_CHAN_DST_REG(DMA_CHAN_TX), req->dst); ++#if defined(CONFIG_GK_MUSB_CON_V1_00) ++ gk_dma_writel(DMA_CHAN_CTR_REG(DMA_CHAN_TX), (0x98000000 | req->xfr_count | (trans_size << 22))); ++#elif defined(CONFIG_GK_MUSB_CON_V1_10) ++ gk_dma_writel(DMA_CHAN_CTR_REG(DMA_CHAN_TX), (0x9B000000 | req->xfr_count | (trans_size << 22))); ++#endif + +- if (!int_hsdma) +- goto done; + } ++ else ++ { ++ controller_irq_rx = controller; ++ req->src = (u32)gk_virt_to_phys((u32)(gk_channel->hw_ep->fifo)); ++ req->dst = dma_addr; //ddr addr ++ req->xfr_count = len; ++ gk_dma_writel(DMA_CHAN_DST_REG(DMA_CHAN_RX), req->dst); ++ gk_dma_writel(DMA_CHAN_SRC_REG(DMA_CHAN_RX), req->src); ++ gk_dma_writel(DMA_CHAN_CTR_REG(DMA_CHAN_RX), (0xab000000 | req->xfr_count | (trans_size << 22))); ++ } ++ ++ return true; ++} ++ ++static int gk_dma_channel_abort(struct dma_channel *channel) ++{ ++ struct gk_dma_channel *gk_channel = channel->private_data; ++ struct gk_dma_controller *controller = gk_channel->controller; ++ struct musb *musb = controller->private_data; ++ void __iomem *epio = musb->endpoints[gk_channel->hw_ep->epnum].regs; ++ u16 csr; ++ + +- for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { +- if (int_hsdma & (1 << bchannel)) { +- musb_channel = (struct musb_dma_channel *) +- &(controller->channel[bchannel]); +- channel = &musb_channel->channel; +- +- csr = musb_readw(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, +- MUSB_HSDMA_CONTROL)); +- +- if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { +- musb_channel->channel.status = +- MUSB_DMA_STATUS_BUS_ABORT; +- } else { +- u8 devctl; +- +- addr = musb_read_hsdma_addr(mbase, +- bchannel); +- channel->actual_len = addr +- - musb_channel->start_addr; +- +- dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", +- channel, musb_channel->start_addr, +- addr, channel->actual_len, +- musb_channel->len, +- (channel->actual_len +- < musb_channel->len) ? +- "=> reconfig 0" : "=> complete"); +- +- devctl = musb_readb(mbase, MUSB_DEVCTL); +- +- channel->status = MUSB_DMA_STATUS_FREE; +- +- /* completed */ +- if ((devctl & MUSB_DEVCTL_HM) +- && (musb_channel->transmit) +- && ((channel->desired_mode == 0) +- || (channel->actual_len & +- (musb_channel->max_packet_sz - 1))) +- ) { +- u8 epnum = musb_channel->epnum; +- int offset = MUSB_EP_OFFSET(epnum, +- MUSB_TXCSR); +- u16 txcsr; +- +- /* +- * The programming guide says that we +- * must clear DMAENAB before DMAMODE. +- */ +- musb_ep_select(mbase, epnum); +- txcsr = musb_readw(mbase, offset); +- txcsr &= ~(MUSB_TXCSR_DMAENAB +- | MUSB_TXCSR_AUTOSET); +- musb_writew(mbase, offset, txcsr); +- /* Send out the packet */ +- txcsr &= ~MUSB_TXCSR_DMAMODE; +- txcsr |= MUSB_TXCSR_TXPKTRDY; +- musb_writew(mbase, offset, txcsr); +- } +- musb_dma_completion(musb, musb_channel->epnum, +- musb_channel->transmit); +- } ++ printk( "dma abort channel=%d, is_tx=%d\n", ++ gk_channel->ch_num, gk_channel->is_tx); ++ if(gk_channel->is_tx) ++ { ++ printk("dma status=0x%x\n",gk_dma_readl(DMA_CHAN_STA_REG(DMA_CHAN_TX))); ++ } ++ else ++ printk("dma status=0x%x\n",gk_dma_readl(DMA_CHAN_STA_REG(DMA_CHAN_RX))); ++ if(channel->status == MUSB_DMA_STATUS_BUSY) { ++ if (gk_channel->is_tx) { ++ csr = musb_readw(epio, 0x10 + MUSB_TXCSR); ++ csr &= ~(MUSB_TXCSR_AUTOSET | ++ MUSB_TXCSR_DMAENAB); ++ musb_writew(epio, 0x10 + MUSB_TXCSR, csr); ++ csr &= ~MUSB_TXCSR_DMAMODE; ++ musb_writew(epio, 0x10 + MUSB_TXCSR, csr); ++ } else { ++ csr = musb_readw(epio, 0x10 + MUSB_RXCSR); ++ csr &= ~(MUSB_RXCSR_AUTOCLEAR | ++ MUSB_RXCSR_DMAENAB); ++ musb_writew(epio, 0x10 + MUSB_RXCSR, csr); ++ csr &= ~MUSB_RXCSR_DMAMODE; ++ musb_writew(epio, 0x10 + MUSB_RXCSR, csr); + } +- } ++ } ++ channel->status = MUSB_DMA_STATUS_FREE; + +- retval = IRQ_HANDLED; +-done: +- spin_unlock_irqrestore(&musb->lock, flags); +- return retval; ++ return 0; + } + +-void dma_controller_destroy(struct dma_controller *c) ++static int gk_dma_controller_stop(struct dma_controller *c) + { +- struct musb_dma_controller *controller = container_of(c, +- struct musb_dma_controller, controller); ++ struct gk_dma_controller *controller = container_of(c, ++ struct gk_dma_controller, controller); ++ struct dma_channel *channel; + +- if (!controller) +- return; + +- if (controller->irq) +- free_irq(controller->irq, c); ++ if(controller->is_tx) channel = &controller->tx_channel.channel; ++ else channel = &controller->rx_channel.channel; ++ ++ gk_dma_channel_release(channel); ++ ++ return 0; ++} ++ ++static int gk_dma_controller_start(struct dma_controller *c) ++{ ++ ++ return 0; ++} ++ ++void dma_controller_destroy(struct dma_controller *c) ++{ ++ struct gk_dma_controller *controller = container_of(c, ++ struct gk_dma_controller, controller); + + kfree(controller); + } +@@ -383,40 +446,85 @@ void dma_controller_destroy(struct dma_controller *c) + struct dma_controller *__init + dma_controller_create(struct musb *musb, void __iomem *base) + { +- struct musb_dma_controller *controller; +- struct device *dev = musb->controller; +- struct platform_device *pdev = to_platform_device(dev); +- int irq = platform_get_irq_byname(pdev, "dma"); +- +- if (irq == 0) { +- dev_err(dev, "No DMA interrupt line!\n"); +- return NULL; +- } ++ struct gk_dma_controller *controller; + + controller = kzalloc(sizeof(*controller), GFP_KERNEL); + if (!controller) + return NULL; + +- controller->channel_count = MUSB_HSDMA_CHANNELS; + controller->private_data = musb; ++ + controller->base = base; + +- controller->controller.start = dma_controller_start; +- controller->controller.stop = dma_controller_stop; +- controller->controller.channel_alloc = dma_channel_allocate; +- controller->controller.channel_release = dma_channel_release; +- controller->controller.channel_program = dma_channel_program; +- controller->controller.channel_abort = dma_channel_abort; ++ controller->controller.start = gk_dma_controller_start; ++ controller->controller.stop = gk_dma_controller_stop; ++ controller->controller.channel_alloc = gk_dma_channel_allocate; ++ controller->controller.channel_release = gk_dma_channel_release; ++ controller->controller.channel_program = gk_dma_channel_program; ++ controller->controller.channel_abort = gk_dma_channel_abort; ++ ++ printk("dma controller create ok\n"); ++ ++ return &controller->controller; ++} ++ ++struct dma_controller * ++dma_controller_create_non_init(struct musb *musb, void __iomem *base) ++{ + +- if (request_irq(irq, dma_controller_irq, 0, +- dev_name(musb->controller), &controller->controller)) { +- dev_err(dev, "request_irq %d failed!\n", irq); +- dma_controller_destroy(&controller->controller); ++ struct gk_dma_controller *controller; ++ int err; + ++ controller = kzalloc(sizeof(*controller), GFP_KERNEL); ++ if (!controller) + return NULL; ++ ++ controller->private_data = musb; ++ ++ controller->base = base; ++ ++ controller->controller.start = gk_dma_controller_start; ++ controller->controller.stop = gk_dma_controller_stop; ++ controller->controller.channel_alloc = gk_dma_channel_allocate; ++ controller->controller.channel_release = gk_dma_channel_release; ++ controller->controller.channel_program = gk_dma_channel_program; ++ controller->controller.channel_abort = gk_dma_channel_abort; ++ //controller->controller.is_compatible = gk_dma_is_compatible; ++ ++#if 0 ++ retval = request_irq(DMA_IRQ, gk_usb_dma_irq, ++ IRQ_TYPE_LEVEL_HIGH | SA_SHIRQ, "usb-dma", NULL); ++ if (retval) { ++ pr_err("%s: request_irq %d fail %d!\n", ++ __func__, DMA_IRQ, retval); + } ++#endif + +- controller->irq = irq; ++ //usb_dma_irq = gk_usb_dma_irq; ++#ifdef CONFIG_USB_INVENTRA_DMA ++ err = gk_dma_request_irq(DMA_CHAN_TX, ++ gk_usb_dma_irq_tx, NULL); ++ if (err < 0) ++ return NULL; ++ err = gk_dma_enable_irq(DMA_CHAN_TX, ++ gk_usb_dma_irq_tx); ++ if (err < 0) ++ return NULL; ++#if defined(CONFIG_GK_MUSB_CON_V1_10) ++ err = gk_dma_request_irq(DMA_CHAN_RX, ++ gk_usb_dma_irq_rx, NULL); ++ if (err < 0) ++ return NULL; ++ err = gk_dma_enable_irq(DMA_CHAN_RX, ++ gk_usb_dma_irq_rx); ++ if (err < 0) ++ return NULL; ++#endif ++ ++#endif ++ printk("dma_controller_create_non_init ok\n"); + + return &controller->controller; + } ++ ++ +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index a290be51..ad167e23 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -2349,6 +2349,16 @@ config FB_PRE_INIT_FB + Select this option if display contents should be inherited as set by + the bootloader. + ++config FB_GOKE ++ tristate "goke ipc Framebuffer support" ++ depends on FB && GK_FB ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_SYS_FOPS ++ help ++ Frame buffer driver for goke ipc. ++ + config FB_MSM + tristate "MSM Framebuffer support" + depends on FB && ARCH_MSM +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 9356add9..d7683036 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -138,6 +138,7 @@ obj-$(CONFIG_FB_SH_MOBILE_HDMI) += sh_mobile_hdmi.o + obj-$(CONFIG_FB_SH_MOBILE_MERAM) += sh_mobile_meram.o + obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o + obj-$(CONFIG_FB_OMAP) += omap/ ++obj-$(CONFIG_FB_GOKE) += goke/ + obj-y += omap2/ + obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o + obj-$(CONFIG_FB_CARMINE) += carminefb.o +diff --git a/drivers/video/goke/Makefile b/drivers/video/goke/Makefile +new file mode 100644 +index 00000000..e3ad8eea +--- /dev/null ++++ b/drivers/video/goke/Makefile +@@ -0,0 +1,20 @@ ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++# ++ ++ifdef CONFIG_FB_GOKE ++obj-$(CONFIG_GK_FB_V1_00) += gk_fb_v1_00.o ++endif ++ +diff --git a/drivers/video/goke/gk_fb_v1_00.c b/drivers/video/goke/gk_fb_v1_00.c +new file mode 100644 +index 00000000..836982ab +--- /dev/null ++++ b/drivers/video/goke/gk_fb_v1_00.c +@@ -0,0 +1,1267 @@ ++/* ++ * drivers/video/goke/gk_fb_v1_00.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include CONFIG_GK_CHIP_INCLUDE_FILE ++ ++/* video=gk_fb0:x,x, ++ ,[,,] */ ++ ++static const struct gk_fb_color_table_s { ++ enum gk_fb_color_format color_format; ++ int bits_per_pixel; ++ struct fb_bitfield red; ++ struct fb_bitfield green; ++ struct fb_bitfield blue; ++ struct fb_bitfield transp; ++} gk_fb_color_format_table[] = ++{ ++ { ++ .color_format = GK_FB_COLOR_CLUT_8BPP, ++ .bits_per_pixel = 8, ++ .red = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_RGB565, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 11, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 5, ++ .length = 6, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_BGR565, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 5, ++ .length = 6, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 11, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_AGBR4444, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 8, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 4, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 12, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_RGBA4444, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 12, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 8, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 4, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_BGRA4444, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 4, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 8, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 12, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ABGR4444, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 4, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 8, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 12, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ARGB4444, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 8, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 4, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 0, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 12, ++ .length = 4, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_AGBR1555, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 10, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 5, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 15, ++ .length = 1, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_GBR1555, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 10, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 5, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 0, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_RGBA5551, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 11, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 6, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 1, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 1, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_BGRA5551, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 1, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 6, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 11, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 1, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ABGR1555, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 5, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 10, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 15, ++ .length = 1, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ARGB1555, ++ .bits_per_pixel = 16, ++ .red = ++ { ++ .offset = 10, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 5, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 0, ++ .length = 5, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 15, ++ .length = 1, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_AGBR8888, ++ .bits_per_pixel = 32, ++ .red = ++ { ++ .offset = 0, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 16, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 8, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 24, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_RGBA8888, ++ .bits_per_pixel = 32, ++ .red = ++ { ++ .offset = 24, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 16, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 8, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_BGRA8888, ++ .bits_per_pixel = 32, ++ .red = ++ { ++ .offset = 8, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 16, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 24, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 0, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ABGR8888, ++ .bits_per_pixel = 32, ++ .red = ++ { ++ .offset = 0, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 8, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 16, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 24, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ }, ++ ++ { ++ .color_format = GK_FB_COLOR_ARGB8888, ++ .bits_per_pixel = 32, ++ .red = ++ { ++ .offset = 16, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .green = ++ { ++ .offset = 8, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .blue = ++ { ++ .offset = 0, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ .transp = ++ { ++ .offset = 24, ++ .length = 8, ++ .msb_right = 0, ++ }, ++ }, ++}; ++ ++/* ========================================================================== */ ++static int gk_fb_proc_read(char *page, char **start, ++ off_t off, int count, int *eof, void *data) ++{ ++ int len; ++ struct gk_platform_fb *gk_fb_data; ++ struct fb_info *info; ++ ++ gk_fb_data = (struct gk_platform_fb *)data; ++ info = gk_fb_data->proc_fb_info; ++ ++ *start = page + off; ++ wait_event_interruptible(gk_fb_data->proc_wait, ++ (gk_fb_data->proc_wait_flag > 0)); ++ gk_fb_data->proc_wait_flag = 0; ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, ++ gk_fb_data->proc_wait_flag); ++ len = sprintf(*start, "%04d %04d %04d %04d %04d %04d\n", ++ info->var.xres, info->var.yres, ++ info->fix.line_length, ++ info->var.xoffset, info->var.yoffset, ++ gk_fb_data->color_format); ++ ++ if (off + len > count) { ++ *eof = 1; ++ len = 0; ++ } ++ ++ return len; ++} ++ ++/* ========================================================================== */ ++static int gk_fb_setcmap(struct fb_cmap *cmap, struct fb_info *info) ++{ ++ int errorCode = 0; ++ struct gk_platform_fb *gk_fb_data; ++ int pos; ++ u16 *r, *g, *b, *t; ++ u8 *pclut_table, *pblend_table; ++ ++ if (cmap == &info->cmap) { ++ errorCode = 0; ++ goto gk_fb_setcmap_exit; ++ } ++ ++ if (cmap->start != 0 || cmap->len != 256) { ++ dev_dbg(info->device, ++ "%s: Incorrect parameters: start = %d, len = %d\n", ++ __func__, cmap->start, cmap->len); ++ errorCode = -1; ++ goto gk_fb_setcmap_exit; ++ } ++ ++ if (!cmap->red || !cmap->green || !cmap->blue) { ++ dev_dbg(info->device, "%s: Incorrect rgb pointers!\n", ++ __func__); ++ errorCode = -1; ++ goto gk_fb_setcmap_exit; ++ } ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ ++ mutex_lock(&gk_fb_data->lock); ++ ++ r = cmap->red; ++ g = cmap->green; ++ b = cmap->blue; ++ t = cmap->transp; ++ pclut_table = gk_fb_data->clut_table; ++ pblend_table = gk_fb_data->blend_table; ++ for (pos = 0; pos < 256; pos++) { ++ *pclut_table++ = *r++; ++ *pclut_table++ = *g++; ++ *pclut_table++ = *b++; ++ if (t) *pblend_table++ = *t++; ++ } ++ ++ if (gk_fb_data->setcmap) { ++ mutex_unlock(&gk_fb_data->lock); ++ errorCode = gk_fb_data->setcmap(cmap, info); ++ } else { ++ mutex_unlock(&gk_fb_data->lock); ++ } ++ ++gk_fb_setcmap_exit: ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, errorCode); ++ return errorCode; ++} ++ ++static int gk_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ int errorCode = 0; ++ struct gk_platform_fb *gk_fb_data; ++ u32 framesize = 0; ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ ++ mutex_lock(&gk_fb_data->lock); ++ if (gk_fb_data->check_var) { ++ errorCode = gk_fb_data->check_var(var, info); ++ } ++ mutex_unlock(&gk_fb_data->lock); ++ ++ if (var->xres_virtual * var->bits_per_pixel / 8 > info->fix.line_length) { ++ errorCode = -ENOMEM; ++ dev_err(info->device, "%s: xres_virtual[%d] too big [%d]!\n", ++ __func__, var->xres_virtual * var->bits_per_pixel / 8, ++ info->fix.line_length); ++ } ++ ++ framesize = info->fix.line_length * var->yres_virtual; ++ if (framesize > info->fix.smem_len) { ++ errorCode = -ENOMEM; ++ dev_err(info->device, "%s: framesize[%d] too big [%d]!\n", ++ __func__, framesize, info->fix.smem_len); ++ } ++ ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, errorCode); ++ ++ return errorCode; ++} ++ ++static int gk_fb_set_par(struct fb_info *info) ++{ ++ int errorCode = 0, i; ++ struct gk_platform_fb *gk_fb_data; ++ struct fb_var_screeninfo *pvar; ++ static struct fb_var_screeninfo *cur_var; ++ int res_changed = 0; ++ int color_format_changed = 0; ++ enum gk_fb_color_format new_color_format; ++ const struct gk_fb_color_table_s *pTable; ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ mutex_lock(&gk_fb_data->lock); ++ cur_var = &gk_fb_data->screen_var; ++ pvar = &info->var; ++ ++ if (!gk_fb_data->set_par) ++ goto gkfb_set_par_quick_exit; ++ ++ /* Resolution changed */ ++ if (pvar->xres != cur_var->xres || pvar->yres != cur_var->yres) { ++ res_changed = 1; ++ } ++ ++ /* Color format changed */ ++ if (pvar->bits_per_pixel != cur_var->bits_per_pixel || ++ pvar->red.offset != cur_var->red.offset || ++ pvar->red.length != cur_var->red.length || ++ pvar->red.msb_right != cur_var->red.msb_right || ++ pvar->green.offset != cur_var->green.offset || ++ pvar->green.length != cur_var->green.length || ++ pvar->green.msb_right != cur_var->green.msb_right || ++ pvar->blue.offset != cur_var->blue.offset || ++ pvar->blue.length != cur_var->blue.length || ++ pvar->blue.msb_right != cur_var->blue.msb_right || ++ pvar->transp.offset != cur_var->transp.offset || ++ pvar->transp.length != cur_var->transp.length || ++ pvar->transp.msb_right != cur_var->transp.msb_right) { ++ ++ color_format_changed = 1; ++ } ++ ++ if (!res_changed && !color_format_changed) ++ goto gkfb_set_par_quick_exit; ++ ++ /* Find color format */ ++ new_color_format = gk_fb_data->color_format; ++ pTable = gk_fb_color_format_table; ++ for (i = 0; i < ARRAY_SIZE(gk_fb_color_format_table); i++) { ++ if (pTable->bits_per_pixel == pvar->bits_per_pixel && ++ pTable->red.offset == pvar->red.offset && ++ pTable->red.length == pvar->red.length && ++ pTable->red.msb_right == pvar->red.msb_right && ++ pTable->green.offset == pvar->green.offset && ++ pTable->green.length == pvar->green.length && ++ pTable->green.msb_right == pvar->green.msb_right && ++ pTable->blue.offset == pvar->blue.offset && ++ pTable->blue.length == pvar->blue.length && ++ pTable->blue.msb_right == pvar->blue.msb_right && ++ pTable->transp.offset == pvar->transp.offset && ++ pTable->transp.length == pvar->transp.length && ++ pTable->transp.msb_right == pvar->transp.msb_right) { ++ ++ new_color_format = pTable->color_format; ++ break; ++ } ++ pTable++; ++ } ++ ++ gk_fb_data->color_format = new_color_format; ++ memcpy(cur_var, pvar, sizeof(*pvar)); ++ mutex_unlock(&gk_fb_data->lock); ++ ++ errorCode = gk_fb_data->set_par(info); ++ goto gkfb_set_par_normal_exit; ++ ++gkfb_set_par_quick_exit: ++ memcpy(cur_var, pvar, sizeof(*pvar)); ++ mutex_unlock(&gk_fb_data->lock); ++ ++gkfb_set_par_normal_exit: ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, errorCode); ++ ++ return errorCode; ++} ++ ++static int gk_fb_pan_display(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ int errorCode = 0; ++ struct gk_platform_fb *gk_fb_data; ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ ++ gk_fb_data->proc_wait_flag++; ++ wake_up(&(gk_fb_data->proc_wait)); ++ mutex_lock(&gk_fb_data->lock); ++ gk_fb_data->screen_var.xoffset = var->xoffset; ++ gk_fb_data->screen_var.yoffset = var->yoffset; ++ if (gk_fb_data->pan_display) { ++ errorCode = gk_fb_data->pan_display(var, info); ++ } ++ mutex_unlock(&gk_fb_data->lock); ++ ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, errorCode); ++ ++ return 0; ++} ++ ++static int gk_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) ++{ ++ unsigned long size = vma->vm_end - vma->vm_start; ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ if (offset + size > info->fix.smem_len) ++ return -EINVAL; ++ ++ offset += info->fix.smem_start; ++ if (remap_pfn_range(vma, vma->vm_start, offset >> PAGE_SHIFT, ++ size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ dev_dbg(info->device, "%s: P(0x%08lx)->V(0x%08lx), size = 0x%08lx.\n", ++ __func__, offset, vma->vm_start, size); ++ ++ return 0; ++} ++ ++static int gk_fb_blank(int blank_mode, struct fb_info *info) ++{ ++ int errorCode = 0; ++ struct gk_platform_fb *gk_fb_data; ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ ++ mutex_lock(&gk_fb_data->lock); ++ if (gk_fb_data->set_blank) { ++ errorCode = gk_fb_data->set_blank(blank_mode, info); ++ } ++ mutex_unlock(&gk_fb_data->lock); ++ ++ dev_dbg(info->device, "%s:%d %d.\n", __func__, __LINE__, errorCode); ++ ++ return errorCode; ++} ++ ++static struct fb_ops gk_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = gk_fb_check_var, ++ .fb_set_par = gk_fb_set_par, ++ .fb_pan_display = gk_fb_pan_display, ++ .fb_fillrect = sys_fillrect, ++ .fb_copyarea = sys_copyarea, ++ .fb_imageblit = sys_imageblit, ++ .fb_mmap = gk_fb_mmap, ++ .fb_setcmap = gk_fb_setcmap, ++ .fb_blank = gk_fb_blank, ++}; ++ ++static int __init gk_fb_setup(struct device *dev, char *options, ++ struct gk_platform_fb *gk_fb_data) ++{ ++ int retval = -1; ++ int ssret; ++ int cl_xres; ++ int cl_yres; ++ int cl_xvirtual; ++ int cl_yvirtual; ++ int cl_format; ++ int cl_cvs_buf; ++ unsigned int cl_prealloc_start; ++ unsigned int cl_prealloc_length; ++ ++ if (!options || !*options) { ++ goto gkfb_setup_exit; ++ } ++ ++ ssret = sscanf(options, "%dx%d,%dx%d,%d,%d,%x,%x", &cl_xres, &cl_yres, ++ &cl_xvirtual, &cl_yvirtual, &cl_format, &cl_cvs_buf, ++ &cl_prealloc_start, &cl_prealloc_length); ++ if (ssret == 6) { ++ gk_fb_data->screen_var.xres = cl_xres; ++ gk_fb_data->screen_var.yres = cl_yres; ++ gk_fb_data->screen_var.xres_virtual = cl_xvirtual; ++ gk_fb_data->screen_var.yres_virtual = cl_yvirtual; ++ gk_fb_data->color_format = cl_format; ++ gk_fb_data->conversion_buf.available = cl_cvs_buf; ++ dev_dbg(dev, "%dx%d,%dx%d,%d,%d\n", cl_xres, cl_yres, ++ cl_xvirtual, cl_yvirtual, cl_format, cl_cvs_buf); ++ retval = 0; ++ } else ++ if (ssret == 8) { ++ gk_fb_data->screen_var.xres = cl_xres; ++ gk_fb_data->screen_var.yres = cl_yres; ++ gk_fb_data->screen_var.xres_virtual = cl_xvirtual; ++ gk_fb_data->screen_var.yres_virtual = cl_yvirtual; ++ gk_fb_data->color_format = cl_format; ++ gk_fb_data->conversion_buf.available = cl_cvs_buf; ++ ++ gk_fb_data->screen_fix.smem_start = cl_prealloc_start; ++ gk_fb_data->screen_fix.smem_len = cl_prealloc_length; ++ gk_fb_data->use_prealloc = 1; ++ dev_dbg(dev, "%dx%d,%dx%d,%d,%d,%x,%x\n", cl_xres, cl_yres, ++ cl_xvirtual, cl_yvirtual, cl_format, cl_cvs_buf, ++ cl_prealloc_start, cl_prealloc_length); ++ retval = 0; ++ } else { ++ dev_err(dev, "Can not support %s@%d!\n", options, ssret); ++ } ++ ++gkfb_setup_exit: ++ return retval; ++} ++ ++static int __devinit gk_fb_probe(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ struct fb_info *info; ++ char fb_name[64]; ++ char *option; ++ struct gk_platform_fb *gk_fb_data = NULL; ++ u32 i; ++ u32 framesize; ++ u32 line_length; ++ ++//printk("gk framebuffer probe...\n"); ++ gk_fb_data = (struct gk_platform_fb *)pdev->dev.platform_data; ++ if (gk_fb_data == NULL) { ++ dev_err(&pdev->dev, "%s: gk_fb_data is NULL!\n", __func__); ++ errorCode = -ENODEV; ++ goto gkfb_probe_exit; ++ } ++//printk("gk framebuffer use_prealloc ... %d\n", gk_fb_data->use_prealloc); ++ if (gk_fb_data->use_prealloc) { ++ dev_info(&pdev->dev, "%s: use prealloc.\n", __func__); ++ } else { ++ snprintf(fb_name, sizeof(fb_name), "gk_fb%d", pdev->id); ++ if (fb_get_options(fb_name, &option)) { ++ errorCode = -ENODEV; ++ printk("gk framebuffer no options...\n"); ++ goto gkfb_probe_exit; ++ } ++ //printk("gk framebuffer setup...%s\n", option); ++ if (gk_fb_setup(&pdev->dev, option, gk_fb_data)) { ++ errorCode = -ENODEV; ++ goto gkfb_probe_exit; ++ } ++ } ++//printk("gk framebuffer alloc...\n"); ++ info = framebuffer_alloc(sizeof(gk_fb_data), &pdev->dev); ++ if (info == NULL) { ++ dev_err(&pdev->dev, "%s: framebuffer_alloc fail!\n", __func__); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_exit; ++ } ++ ++ mutex_lock(&gk_fb_data->lock); ++ ++ info->fbops = &gk_fb_ops; ++ info->par = gk_fb_data; ++ info->var = gk_fb_data->screen_var; ++ info->fix = gk_fb_data->screen_fix; ++ info->flags = FBINFO_FLAG_DEFAULT; ++ ++ /* Fill Color-related Variables */ ++ for (i = 0; i < ARRAY_SIZE(gk_fb_color_format_table); i++) { ++ if (gk_fb_color_format_table[i].color_format == ++ gk_fb_data->color_format) ++ break; ++ } ++ if (i < ARRAY_SIZE(gk_fb_color_format_table)) { ++ info->var.bits_per_pixel = ++ gk_fb_color_format_table[i].bits_per_pixel; ++ info->var.red = gk_fb_color_format_table[i].red; ++ info->var.green = gk_fb_color_format_table[i].green; ++ info->var.blue = gk_fb_color_format_table[i].blue; ++ info->var.transp = gk_fb_color_format_table[i].transp; ++ } ++ ++ /* Malloc Framebuffer Memory */ ++ line_length = (info->var.xres_virtual * ++ (info->var.bits_per_pixel / 8) + 31) & 0xffffffe0; ++ if (gk_fb_data->use_prealloc == 0) { ++ info->fix.line_length = line_length; ++ } else { ++ info->fix.line_length = ++ (line_length > gk_fb_data->prealloc_line_length) ? ++ line_length : gk_fb_data->prealloc_line_length; ++ } ++ framesize = info->fix.line_length * info->var.yres_virtual; ++ if (framesize % PAGE_SIZE) { ++ framesize /= PAGE_SIZE; ++ framesize++; ++ framesize *= PAGE_SIZE; ++ } ++ if (gk_fb_data->use_prealloc == 0) { ++ info->screen_base = kzalloc(framesize, GFP_KERNEL); ++ if (info->screen_base == NULL) { ++ dev_err(&pdev->dev, "%s(%d): Can't get fbmem!\n", ++ __func__, __LINE__); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } ++ if (gk_fb_data->conversion_buf.available) { ++ gk_fb_data->conversion_buf.ping_buf = ++ kzalloc(framesize, GFP_KERNEL); ++ if (gk_fb_data->conversion_buf.ping_buf == NULL) { ++ gk_fb_data->conversion_buf.available = 0; ++ dev_err(&pdev->dev, "%s(%d): Can't get fbmem!\n", ++ __func__, __LINE__); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } else { ++ gk_fb_data->conversion_buf.ping_buf_size ++ = framesize; ++ } ++ ++ gk_fb_data->conversion_buf.pong_buf = ++ kzalloc(framesize, GFP_KERNEL); ++ if (gk_fb_data->conversion_buf.pong_buf == NULL) { ++ gk_fb_data->conversion_buf.available = 0; ++ dev_err(&pdev->dev, "%s(%d): Can't get fbmem!\n", ++ __func__, __LINE__); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } else { ++ gk_fb_data->conversion_buf.pong_buf_size ++ = framesize; ++ } ++ } ++ info->fix.smem_start = virt_to_phys(info->screen_base); ++ info->fix.smem_len = framesize; ++ } else { ++ if ((info->fix.smem_start == 0) || ++ (info->fix.smem_len < framesize)) { ++ dev_err(&pdev->dev, "%s: prealloc[0x%08x < 0x%08x]!\n", ++ __func__, info->fix.smem_len, framesize); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } ++ ++ info->screen_base = (char __iomem *) ++ gk_phys_to_virt(info->fix.smem_start); ++ //memset(info->screen_base, 0, info->fix.smem_len); ++ ++ if (gk_fb_data->conversion_buf.available) { ++ if (info->fix.smem_len < 3 * framesize) { ++ gk_fb_data->conversion_buf.available = 0; ++ dev_err(&pdev->dev, ++ "%s: prealloc[0x%08x < 0x%08x]!\n", ++ __func__, info->fix.smem_len, ++ 3 * framesize); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } else { ++ gk_fb_data->conversion_buf.ping_buf = ++ info->screen_base + framesize; ++ gk_fb_data->conversion_buf.ping_buf_size = ++ framesize; ++ gk_fb_data->conversion_buf.ping_buf = ++ info->screen_base + framesize; ++ gk_fb_data->conversion_buf.ping_buf_size = ++ framesize; ++ } ++ } ++ } ++ ++ errorCode = fb_alloc_cmap(&info->cmap, 256, 1); ++ if (errorCode < 0) { ++ dev_err(&pdev->dev, "%s: fb_alloc_cmap fail!\n", __func__); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_release_framebuffer; ++ } ++ for (i = info->cmap.start; i < info->cmap.len; i++) { ++ info->cmap.red[i] = ++ gk_fb_data->clut_table[i * GK_CLUT_BYTES + 0]; ++ info->cmap.red[i] <<= 8; ++ info->cmap.green[i] = ++ gk_fb_data->clut_table[i * GK_CLUT_BYTES + 1]; ++ info->cmap.green[i] <<= 8; ++ info->cmap.blue[i] = ++ gk_fb_data->clut_table[i * GK_CLUT_BYTES + 2]; ++ info->cmap.blue[i] <<= 8; ++ if (info->cmap.transp) { ++ info->cmap.transp[i] = gk_fb_data->blend_table[i]; ++ info->cmap.transp[i] <<= 8; ++ } ++ } ++ ++ platform_set_drvdata(pdev, info); ++ gk_fb_data->fb_status = GK_FB_ACTIVE_MODE; ++ mutex_unlock(&gk_fb_data->lock); ++ ++ errorCode = register_framebuffer(info); ++ if (errorCode < 0) { ++ dev_err(&pdev->dev, "%s: register_framebuffer fail!\n", ++ __func__); ++ errorCode = -ENOMEM; ++ mutex_lock(&gk_fb_data->lock); ++ goto gkfb_probe_dealloc_cmap; ++ } ++ ++ gk_fb_data->proc_fb_info = info; ++ gk_fb_data->proc_file = create_proc_entry(dev_name(&pdev->dev), ++ S_IRUGO | S_IWUSR, get_gk_proc_dir()); ++ if (gk_fb_data->proc_file == NULL) { ++ dev_err(&pdev->dev, "Register %s failed!\n", ++ dev_name(&pdev->dev)); ++ errorCode = -ENOMEM; ++ goto gkfb_probe_unregister_framebuffer; ++ } else { ++ gk_fb_data->proc_file->read_proc = gk_fb_proc_read; ++ gk_fb_data->proc_file->data = gk_fb_data; ++ } ++ ++ mutex_lock(&gk_fb_data->lock); ++ gk_fb_data->screen_var = info->var; ++ gk_fb_data->screen_fix = info->fix; ++ mutex_unlock(&gk_fb_data->lock); ++ ++ dev_info(&pdev->dev, ++ "probe p[%dx%d] v[%dx%d] c[%d] b[%d] l[%d] @ [0x%08lx:0x%08x]!\n", ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, gk_fb_data->color_format, ++ gk_fb_data->conversion_buf.available, ++ info->fix.line_length, ++ info->fix.smem_start, info->fix.smem_len); ++ goto gkfb_probe_exit; ++ ++gkfb_probe_unregister_framebuffer: ++ unregister_framebuffer(info); ++ ++gkfb_probe_dealloc_cmap: ++ fb_dealloc_cmap(&info->cmap); ++ ++gkfb_probe_release_framebuffer: ++ framebuffer_release(info); ++ gk_fb_data->fb_status = GK_FB_STOP_MODE; ++ mutex_unlock(&gk_fb_data->lock); ++ ++gkfb_probe_exit: ++ return errorCode; ++} ++ ++static int __devexit gk_fb_remove(struct platform_device *pdev) ++{ ++ struct fb_info *info; ++ struct gk_platform_fb *gk_fb_data = NULL; ++ ++ info = platform_get_drvdata(pdev); ++ if (info) { ++ remove_proc_entry(dev_name(&pdev->dev), ++ get_gk_proc_dir()); ++ unregister_framebuffer(info); ++ ++ gk_fb_data = (struct gk_platform_fb *)info->par; ++ mutex_lock(&gk_fb_data->lock); ++ gk_fb_data->fb_status = GK_FB_STOP_MODE; ++ fb_dealloc_cmap(&info->cmap); ++ if (gk_fb_data->use_prealloc == 0) { ++ if (info->screen_base) { ++ kfree(info->screen_base); ++ } ++ if (gk_fb_data->conversion_buf.available) { ++ if (gk_fb_data->conversion_buf.ping_buf) { ++ kfree(gk_fb_data->conversion_buf.ping_buf); ++ } ++ if (gk_fb_data->conversion_buf.pong_buf) { ++ kfree(gk_fb_data->conversion_buf.pong_buf); ++ } ++ } ++ gk_fb_data->screen_fix.smem_start = 0; ++ gk_fb_data->screen_fix.smem_len = 0; ++ } ++ platform_set_drvdata(pdev, NULL); ++ framebuffer_release(info); ++ mutex_unlock(&gk_fb_data->lock); ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int gk_fb_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ int errorCode = 0; ++ ++ dev_dbg(&pdev->dev, "%s exit with %d @ %d\n", ++ __func__, errorCode, state.event); ++ ++ return errorCode; ++} ++ ++static int gk_fb_resume(struct platform_device *pdev) ++{ ++ int errorCode = 0; ++ ++ dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, errorCode); ++ ++ return errorCode; ++} ++#endif ++ ++static struct platform_driver gk_fb_driver = { ++ .probe = gk_fb_probe, ++ .remove = __devexit_p(gk_fb_remove), ++#ifdef CONFIG_PM ++ .suspend = gk_fb_suspend, ++ .resume = gk_fb_resume, ++#endif ++ .driver = { ++ .name = "gk-fb", ++ }, ++}; ++ ++static int __init gk_fb_init(void) ++{ ++ //printk("init gk framebuffer\n"); ++ return platform_driver_register(&gk_fb_driver); ++} ++ ++static void __exit gk_fb_exit(void) ++{ ++ platform_driver_unregister(&gk_fb_driver); ++} ++ ++module_init(gk_fb_init); ++module_exit(gk_fb_exit); ++ ++MODULE_DESCRIPTION("GK framebuffer driver"); ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig +index 37096246..3665ff67 100644 +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -84,6 +84,13 @@ config WM8350_WATCHDOG + + # ARM Architecture + ++config WATCHDOG_GOKE ++ tristate "goke ipc watchdog" ++ depends on GK_WDT ++ help ++ Watchdog timer embedded into goke ipc. This will reboot your ++ system when the timeout is reached. ++ + config ARM_SP805_WATCHDOG + tristate "ARM SP805 Watchdog" + depends on ARM_AMBA +diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile +index e8f479a1..930e6a8f 100644 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -53,6 +53,9 @@ obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o + obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o + obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o + obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o ++ifdef CONFIG_WATCHDOG_GOKE ++obj-$(CONFIG_GK_WDT_V1_00) += gk_wdt_v1_00.o ++endif + + # AVR32 Architecture + obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o +diff --git a/drivers/watchdog/gk_wdt_v1_00.c b/drivers/watchdog/gk_wdt_v1_00.c +new file mode 100644 +index 00000000..c6113cd6 +--- /dev/null ++++ b/drivers/watchdog/gk_wdt_v1_00.c +@@ -0,0 +1,540 @@ ++/* ++ * linux/drivers/watchdog/gk_wdt.c ++ * ++ * Author: Steven Yu, ++ * Copyright (C) 2012-2015, goke, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include /* for MODULE_ALIAS_MISCDEV */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define CONFIG_GK_WDT_ATBOOT (0) ++#define CONFIG_GK_WDT_TIMEOUT (15) ++ ++static bool nowayout = WATCHDOG_NOWAYOUT; ++static int tmr_margin = CONFIG_GK_WDT_TIMEOUT; ++static int tmr_atboot = CONFIG_GK_WDT_ATBOOT; ++static int soft_noboot; ++static int debug; ++ ++module_param(tmr_margin, int, 0); ++module_param(tmr_atboot, int, 0); ++module_param(nowayout, bool, 0); ++module_param(soft_noboot, int, 0); ++module_param(debug, int, 1); ++ ++MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" ++ __MODULE_STRING(CONFIG_GK_WDT_TIMEOUT) ")"); ++MODULE_PARM_DESC(tmr_atboot, ++ "Watchdog is started at boot time if set to 1, default=" ++ __MODULE_STRING(CONFIG_GK_WDT_ATBOOT)); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " ++ "0 to reboot (default 0)"); ++MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); ++ ++static DEFINE_SPINLOCK(wdt_lock); ++ ++static int init_mode = WDOG_CTR_RST_EN; //WDOG_CTR_INT_EN | WDOG_CTR_RST_EN ++module_param(init_mode, int, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(init_mode, "Watchdog mode: 0x2=reset, 0x4=irq"); ++ ++enum gk_wdt_state { ++ WDT_CLOSE_STATE_DISABLE, ++ WDT_CLOSE_STATE_ALLOW, ++}; ++struct gk_wdt_info ++{ ++ unsigned char __iomem *regbase; ++ ++ struct device *dev; ++ struct resource *mem; ++ unsigned int irq; ++ ++ enum gk_wdt_state state; ++ ++ unsigned int tmo; ++ unsigned int boot_tmo; ++ ++ struct watchdog_device *wdt_dev; ++ ++ unsigned int ctl_reg; ++ unsigned int init_mode; ++ unsigned int act_timeout; ++ ++}; ++ ++static struct gk_wdt_info *pwdtinfo = NULL; ++ ++ ++/* watchdog control routines */ ++ ++#define DBG(fmt, ...) \ ++do { \ ++ if (debug) \ ++ pr_info(fmt, ##__VA_ARGS__); \ ++} while (0) ++ ++/* functions */ ++static int gk_wdt_keepalive(struct watchdog_device *wdd) ++{ ++ struct gk_wdt_info *pinfo = pwdtinfo; ++ ++ spin_lock(&wdt_lock); ++ gk_wdt_writel((unsigned int)pinfo->regbase + WDOG_RELOAD_OFFSET, pinfo->tmo); ++ gk_wdt_writel((unsigned int)pinfo->regbase + WDOG_RESTART_OFFSET, WDT_RESTART_VAL); ++ spin_unlock(&wdt_lock); ++ ++ return 0; ++} ++ ++static void __gk_wdt_stop(struct gk_wdt_info *pinfo) ++{ ++ gk_wdt_writel((unsigned int)pinfo->regbase + WDOG_CONTROL_OFFSET, 0); ++ while((gk_wdt_readl((unsigned int)pinfo->regbase + WDOG_CONTROL_OFFSET) ++ & (WDOG_CTR_RST_EN|WDOG_CTR_INT_EN|WDOG_CTR_EN)) != 0); ++} ++ ++static int gk_wdt_stop(struct watchdog_device *wdd) ++{ ++ struct gk_wdt_info *pinfo = pwdtinfo; ++ ++ spin_lock(&wdt_lock); ++ __gk_wdt_stop(pinfo); ++ spin_unlock(&wdt_lock); ++ ++ return 0; ++} ++ ++static int __gk_wdt_start(struct gk_wdt_info *pinfo, u32 ctl_reg) ++{ ++ spin_lock(&wdt_lock); ++ ++ __gk_wdt_stop(pinfo); ++ ++ if (!ctl_reg) ++ ctl_reg = pinfo->init_mode | WDOG_CTR_EN; ++ ++ if ((ctl_reg & WDOG_CTR_RST_EN) == WDOG_CTR_RST_EN) ++ { ++ /* Clear the WDT_RST_L_REG to zero */ ++ //gk_writel(WDT_RST_L_REG, RCT_WDT_RESET_VAL); ++ ++ /* Clear software reset bit. */ ++ //gk_writel(SOFT_RESET_REG, 0x2); ++ } ++ ++ gk_wdt_writel(WDOG_CONTROL_REG, ctl_reg); ++ while(gk_wdt_tstbitsl(WDOG_CONTROL_REG, ctl_reg) != ctl_reg); ++ ++ spin_unlock(&wdt_lock); ++ ++ DBG("%s: ctl_reg=0x%08x\n", __func__, ctl_reg); ++ ++ return 0; ++ ++} ++ ++static int gk_wdt_start(struct watchdog_device *wdd) ++{ ++ struct gk_wdt_info *pinfo = pwdtinfo; ++ __gk_wdt_start(pinfo, 0); ++ return 0; ++} ++ ++static int gk_wdt_is_running(struct gk_wdt_info *pinfo) ++{ ++ return (gk_wdt_readl((unsigned int)pinfo->regbase + WDOG_CONTROL_OFFSET) & WDOG_CTR_EN); ++} ++ ++static int gk_wdt_set_heartbeat(struct watchdog_device *wdd, u32 timeout) ++{ ++ struct gk_wdt_info *pinfo = pwdtinfo; ++ ++ int errorCode = 0; ++ u32 freq; ++ u32 max_tmo; ++ ++ freq = get_apb_bus_freq_hz(); ++ if (freq) ++ max_tmo = 0xFFFFFFFF / freq; ++ else { ++ dev_err(pinfo->dev, "freq == 0 !\n"); ++ errorCode = -EPERM; ++ goto wdt_set_heartbeat_exit; ++ } ++ ++ if (timeout > max_tmo) { ++ dev_err(pinfo->dev, "max_tmo is %d, not %d.\n", max_tmo, timeout); ++ errorCode = -EINVAL; ++ goto wdt_set_heartbeat_exit; ++ } ++ ++ pinfo->tmo = timeout * freq; ++ pinfo->act_timeout = timeout; ++ gk_wdt_keepalive(wdd); ++ ++ DBG("%s: timeout=%d, freq=%u, count=0x%08x\n", __func__, timeout, freq, pinfo->tmo); ++ ++ wdd->timeout = timeout; ++ ++wdt_set_heartbeat_exit: ++ return errorCode; ++ ++} ++ ++static const struct watchdog_info gk_wdt_ident = { ++ .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE), ++ .firmware_version = 0, ++ .identity = "GK Watchdog", ++}; ++ ++static struct watchdog_ops gk_wdt_ops = { ++ .owner = THIS_MODULE, ++ .start = gk_wdt_start, ++ .stop = gk_wdt_stop, ++ .ping = gk_wdt_keepalive, ++ .set_timeout = gk_wdt_set_heartbeat, ++}; ++ ++static struct watchdog_device gk_wdd = { ++ .info = &gk_wdt_ident, ++ .ops = &gk_wdt_ops, ++}; ++ ++/* interrupt handler code */ ++static irqreturn_t gk_wdt_irq(int irqno, void *devid) ++{ ++ struct gk_wdt_info *pinfo; ++ ++ pinfo = (struct gk_wdt_info *)devid; ++ ++ /* clear the IRQ */ ++ gk_wdt_writel((unsigned int)pinfo->regbase + WDOG_CLR_TMO_OFFSET, 0x01); ++ ++ /* Update the timerout register(Feed something to a dog) */ ++ //gk_wdt_keepalive(pinfo); ++ ++ dev_info(pinfo->dev, "Watchdog timer expired!\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __devinit gk_wdt_probe(struct platform_device *pdev) ++{ ++ struct device *wdt_dev; ++ struct resource *wdt_irq; ++ struct resource *wdt_mem; ++ ++#if 1 ++ void __iomem *wdt_base; ++#endif ++ ++ struct gk_wdt_info *pinfo; ++ ++ unsigned int wtcon; ++ int started = 0; ++ int ret; ++ //int size; ++ ++ printk("[%s]: probe\n", __FUNCTION__); ++ ++ DBG("%s: probe=%p\n", __func__, pdev); ++ ++ wdt_dev = &pdev->dev; ++ ++ wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (wdt_mem == NULL) { ++ dev_err(wdt_dev, "Get WDT memory resource failed\n"); ++ return -ENOENT; ++ } ++ ++ wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (wdt_irq == NULL) { ++ dev_err(wdt_dev, "Get WDT irq resource failed\n"); ++ return -ENOENT; ++ } ++#if 0 ++ /* get the memory region for the watchdog timer */ ++ size = resource_size(wdt_mem); ++ if (!request_mem_region(wdt_mem->start, size, pdev->name)) { ++ dev_err(wdt_dev, "Failed to get WDT's memory region\n"); ++ return -EBUSY; ++ } ++ ++ wdt_base = ioremap(wdt_mem->start, size); ++ if (wdt_base == NULL) { ++ dev_err(wdt_dev, "failed to ioremap() region\n"); ++ ret = -EINVAL; ++ goto err_req; ++ } ++#else ++ wdt_base = (void __iomem*)wdt_mem->start; ++#endif ++ ++ DBG("probe: mapped wdt_base=%p\n", wdt_base); ++ printk("[%s]: probe mapped wdt_base=%p\n", __FUNCTION__, wdt_base); ++ ++ pinfo = kzalloc(sizeof(struct gk_wdt_info), GFP_KERNEL); ++ if (pinfo == NULL) { ++ dev_err(wdt_dev, "Out of memory!\n"); ++ ret = -ENOMEM; ++ goto err_map; ++ } ++ ++ pinfo->regbase = (unsigned char __iomem *)wdt_base; ++ pinfo->mem = wdt_mem; ++ pinfo->dev = &pdev->dev; ++ pinfo->irq = wdt_irq->start; ++ pinfo->wdt_dev = &gk_wdd; ++ pinfo->state = WDT_CLOSE_STATE_DISABLE; ++ pinfo->boot_tmo = gk_wdt_readl((unsigned int)pinfo->regbase + WDOG_TIMEOUT_OFFSET); ++ pinfo->init_mode = (init_mode & (WDOG_CTR_INT_EN | WDOG_CTR_RST_EN)); ++ platform_set_drvdata(pdev, pinfo); ++ pwdtinfo = pinfo; ++ ++ /* see if we can actually set the requested timer margin, and if ++ * not, try the default value */ ++ ++ if (gk_wdt_set_heartbeat(pinfo->wdt_dev, tmr_margin)) ++ { ++ started = gk_wdt_set_heartbeat(pinfo->wdt_dev, CONFIG_GK_WDT_TIMEOUT); ++ if (started == 0) ++ dev_info(wdt_dev, ++ "tmr_margin value out of range, default %d used\n", CONFIG_GK_WDT_TIMEOUT); ++ else ++ dev_info(wdt_dev, "default timer value is out of range, cannot start\n"); ++ } ++ ++ ret = request_irq(wdt_irq->start, gk_wdt_irq, IRQF_TRIGGER_RISING, dev_name(&pdev->dev), pinfo); ++ if (ret != 0) { ++ dev_err(wdt_dev, "failed to install irq (%d)\n", ret); ++ goto err_malloc; ++ } ++ ++ watchdog_set_nowayout(pinfo->wdt_dev, nowayout); ++ ++ ret = watchdog_register_device(pinfo->wdt_dev); ++ if (ret) { ++ dev_err(wdt_dev, "cannot register watchdog (%d)\n", ret); ++ goto err_irq; ++ } ++ ++ if (tmr_atboot && started == 0) ++ { ++ dev_info(wdt_dev, "starting watchdog timer\n"); ++ gk_wdt_start(pinfo->wdt_dev); ++ } ++ else if (!tmr_atboot) ++ { ++ /* if we're not enabling the watchdog, then ensure it is ++ * disabled if it has been left running from the bootloader ++ * or other source */ ++ ++ gk_wdt_stop(pinfo->wdt_dev); ++ } ++ ++ /* print out a statement of readiness */ ++ ++ wtcon = gk_wdt_readl((unsigned int)wdt_base + WDOG_CONTROL_OFFSET); ++ ++ ++ printk("watchdog %sactive, reset %sabled, irq %sabled\n", ++ (wtcon & WDOG_CTR_EN) ? "" : "in", ++ (wtcon & WDOG_CTR_RST_EN) ? "en" : "dis", ++ (wtcon & WDOG_CTR_INT_EN) ? "en" : "dis"); ++ ++ ++ return 0; ++ ++err_irq: ++ free_irq(wdt_irq->start, pdev); ++ ++err_malloc: ++ kfree(pinfo); ++ ++err_map: ++ //iounmap(wdt_base); ++ ++//err_req: ++ //release_mem_region(wdt_mem->start, size); ++ ++ return ret; ++ ++} ++ ++static int __devexit gk_wdt_remove(struct platform_device *pdev) ++{ ++ struct gk_wdt_info *pinfo; ++ struct resource *wdt_mem; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ if (pinfo) ++ { ++ watchdog_unregister_device(pinfo->wdt_dev); ++ gk_wdt_stop(pinfo->wdt_dev); ++ free_irq(pinfo->irq, pinfo); ++ platform_set_drvdata(pdev, NULL); ++ //iounmap((unsigned int)pinfo->regbase); ++ ++ wdt_mem = pinfo->mem; ++ //release_mem_region(wdt_mem->start, resource_size(wdt_mem)); ++ kfree(pinfo); ++ } ++ ++ dev_notice(&pdev->dev, ++ "Remove GK Media Processor Watch Dog Timer[%s].\n", ++ dev_name(&pdev->dev)); ++ ++ return 0; ++ ++} ++ ++static void gk_wdt_shutdown(struct platform_device *pdev) ++{ ++ struct gk_wdt_info *pinfo; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ if (pinfo) ++ gk_wdt_stop(pinfo->wdt_dev); ++ else ++ dev_err(&pdev->dev, "Cannot find valid pinfo\n"); ++ ++ dev_dbg(&pdev->dev, "%s exit.\n", __func__); ++} ++ ++#ifdef CONFIG_PM ++static int gk_wdt_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ struct gk_wdt_info *pinfo; ++ int errorCode = 0; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ if (pinfo) { ++ disable_irq(pinfo->irq); ++ pinfo->ctl_reg = gk_wdt_readl((unsigned int)pinfo->regbase + WDOG_CONTROL_OFFSET); ++ gk_wdt_stop(pinfo); ++ } else { ++ dev_err(&pdev->dev, "Cannot find valid pinfo\n"); ++ errorCode = -ENXIO; ++ } ++ ++ dev_dbg(&pdev->dev, "%s exit with %d @ %d\n", ++ __func__, errorCode, state.event); ++ ++ return errorCode; ++} ++ ++static int gk_wdt_resume(struct platform_device *pdev) ++{ ++ struct gk_wdt_info *pinfo; ++ int errorCode = 0; ++ ++ pinfo = platform_get_drvdata(pdev); ++ ++ if (pinfo) { ++ if (pinfo->ctl_reg) { ++ gk_wdt_set_heartbeat(pinfo, pinfo->act_timeout); ++ gk_wdt_start(pinfo->wdt_dev); ++ } ++ enable_irq(pinfo->irq); ++ } else { ++ dev_err(&pdev->dev, "Cannot find valid pinfo\n"); ++ errorCode = -ENXIO; ++ } ++ ++ dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, errorCode); ++ ++ return errorCode; ++} ++#endif ++ ++ ++#ifdef CONFIG_OF ++static const struct of_device_id gk_wdt_match[] = { ++ { .compatible = "goke,gk-wdt" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, gk_wdt_match); ++#else ++#define gk_wdt_match NULL ++#endif ++ ++static struct platform_driver gk_wdt_driver = { ++ .probe = gk_wdt_probe, ++ .remove = __devexit_p(gk_wdt_remove), ++ .shutdown = gk_wdt_shutdown, ++#ifdef CONFIG_PM ++ .suspend = gk_wdt_suspend, ++ .resume = gk_wdt_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "gk-wdt", ++ .of_match_table = gk_wdt_match, ++ }, ++}; ++ ++ ++static int __init gk_wdt_init(void) ++{ ++ pr_info("GK Watchdog Timer, (c) 2014 Goke Microelectronics\n"); ++ ++ printk("[%s]: init\n", __FUNCTION__); ++ ++ return platform_driver_register(&gk_wdt_driver); ++} ++ ++static void __exit gk_wdt_exit(void) ++{ ++ platform_driver_unregister(&gk_wdt_driver); ++} ++ ++module_init(gk_wdt_init); ++module_exit(gk_wdt_exit); ++ ++MODULE_AUTHOR("Goke Microelectronics Inc."); ++MODULE_DESCRIPTION("GK Watchdog Device Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gk-wdt"); +diff --git a/fs/Kconfig b/fs/Kconfig +index f95ae3a0..f19f3434 100644 +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -203,6 +203,7 @@ source "fs/hfsplus/Kconfig" + source "fs/befs/Kconfig" + source "fs/bfs/Kconfig" + source "fs/efs/Kconfig" ++source "fs/yaffs2/Kconfig" + source "fs/jffs2/Kconfig" + # UBIFS File system configuration + source "fs/ubifs/Kconfig" +diff --git a/fs/Makefile b/fs/Makefile +index 2fb97793..79b94ebe 100644 +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -125,3 +125,4 @@ obj-$(CONFIG_GFS2_FS) += gfs2/ + obj-y += exofs/ # Multiple modules + obj-$(CONFIG_CEPH_FS) += ceph/ + obj-$(CONFIG_PSTORE) += pstore/ ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ +diff --git a/fs/jffs2/debug.c b/fs/jffs2/debug.c +index 1090eb64..9797fadc 100644 +--- a/fs/jffs2/debug.c ++++ b/fs/jffs2/debug.c +@@ -264,13 +264,11 @@ void __jffs2_dbg_superblock_counts(struct jffs2_sb_info *c) + } + + #define check(sz) \ +-do { \ + if (sz != c->sz##_size) { \ + pr_warn("%s_size mismatch counted 0x%x, c->%s_size 0x%x\n", \ + #sz, sz, #sz, c->sz##_size); \ +- dump = 1; \ +- } \ +-} while (0) ++ dump = 1; \ ++ } + + check(free); + check(dirty); +diff --git a/fs/jffs2/file.c b/fs/jffs2/file.c +index 8608f877..fc4535d2 100644 +--- a/fs/jffs2/file.c ++++ b/fs/jffs2/file.c +@@ -138,39 +138,33 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, + struct page *pg; + struct inode *inode = mapping->host; + struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode); +- struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb); +- struct jffs2_raw_inode ri; +- uint32_t alloc_len = 0; + pgoff_t index = pos >> PAGE_CACHE_SHIFT; + uint32_t pageofs = index << PAGE_CACHE_SHIFT; + int ret = 0; + +- jffs2_dbg(1, "%s()\n", __func__); +- +- if (pageofs > inode->i_size) { +- ret = jffs2_reserve_space(c, sizeof(ri), &alloc_len, +- ALLOC_NORMAL, JFFS2_SUMMARY_INODE_SIZE); +- if (ret) +- return ret; +- } +- +- mutex_lock(&f->sem); + pg = grab_cache_page_write_begin(mapping, index, flags); +- if (!pg) { +- if (alloc_len) +- jffs2_complete_reservation(c); +- mutex_unlock(&f->sem); ++ if (!pg) + return -ENOMEM; +- } + *pagep = pg; + +- if (alloc_len) { ++ D1(printk(KERN_DEBUG "jffs2_write_begin()\n")); ++ ++ if (pageofs > inode->i_size) { + /* Make new hole frag from old EOF to new page */ ++ struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb); ++ struct jffs2_raw_inode ri; + struct jffs2_full_dnode *fn; ++ uint32_t alloc_len; + + jffs2_dbg(1, "Writing new hole frag 0x%x-0x%x between current EOF and new page\n", + (unsigned int)inode->i_size, pageofs); + ++ ret = jffs2_reserve_space(c, sizeof(ri), &alloc_len, ++ ALLOC_NORMAL, JFFS2_SUMMARY_INODE_SIZE); ++ if (ret) ++ goto out_page; ++ ++ mutex_lock(&f->sem); + memset(&ri, 0, sizeof(ri)); + + ri.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); +@@ -197,6 +191,7 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, + if (IS_ERR(fn)) { + ret = PTR_ERR(fn); + jffs2_complete_reservation(c); ++ mutex_unlock(&f->sem); + goto out_page; + } + ret = jffs2_add_full_dnode_to_inode(c, f, fn); +@@ -211,10 +206,12 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, + jffs2_mark_node_obsolete(c, fn->raw); + jffs2_free_full_dnode(fn); + jffs2_complete_reservation(c); ++ mutex_unlock(&f->sem); + goto out_page; + } + jffs2_complete_reservation(c); + inode->i_size = pageofs; ++ mutex_unlock(&f->sem); + } + + /* +@@ -223,18 +220,18 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, + * case of a short-copy. + */ + if (!PageUptodate(pg)) { ++ mutex_lock(&f->sem); + ret = jffs2_do_readpage_nolock(inode, pg); ++ mutex_unlock(&f->sem); + if (ret) + goto out_page; + } +- mutex_unlock(&f->sem); + jffs2_dbg(1, "end write_begin(). pg->flags %lx\n", pg->flags); + return ret; + + out_page: + unlock_page(pg); + page_cache_release(pg); +- mutex_unlock(&f->sem); + return ret; + } + +diff --git a/fs/jffs2/fs.c b/fs/jffs2/fs.c +index bb6f993e..a5499837 100644 +--- a/fs/jffs2/fs.c ++++ b/fs/jffs2/fs.c +@@ -585,6 +585,8 @@ int jffs2_do_fill_super(struct super_block *sb, void *data, int silent) + jffs2_start_garbage_collect_thread(c); + return 0; + ++ out_root_i: ++ iput(root_i); + out_root: + jffs2_free_ino_caches(c); + jffs2_free_raw_node_refs(c); +diff --git a/fs/jffs2/gc.c b/fs/jffs2/gc.c +index 5a2dec2b..ad271c70 100644 +--- a/fs/jffs2/gc.c ++++ b/fs/jffs2/gc.c +@@ -234,8 +234,8 @@ int jffs2_garbage_collect_pass(struct jffs2_sb_info *c) + return 0; + + jffs2_dbg(1, "No progress from erasing block; doing GC anyway\n"); +- mutex_lock(&c->alloc_sem); + spin_lock(&c->erase_completion_lock); ++ mutex_lock(&c->alloc_sem); + } + + /* First, work out which block we're garbage-collecting */ +diff --git a/fs/jffs2/nodemgmt.c b/fs/jffs2/nodemgmt.c +index ffa8f12c..6784d1e7 100644 +--- a/fs/jffs2/nodemgmt.c ++++ b/fs/jffs2/nodemgmt.c +@@ -375,16 +375,14 @@ static int jffs2_do_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, + spin_unlock(&c->erase_completion_lock); + + ret = jffs2_prealloc_raw_node_refs(c, jeb, 1); +- ++ if (ret) ++ return ret; + /* Just lock it again and continue. Nothing much can change because + we hold c->alloc_sem anyway. In fact, it's not entirely clear why + we hold c->erase_completion_lock in the majority of this function... + but that's a question for another (more caffeine-rich) day. */ + spin_lock(&c->erase_completion_lock); + +- if (ret) +- return ret; +- + waste = jeb->free_size; + jffs2_link_node_ref(c, jeb, + (jeb->offset + c->sector_size - waste) | REF_OBSOLETE, +diff --git a/fs/yaffs2/Kconfig b/fs/yaffs2/Kconfig +new file mode 100644 +index 00000000..408570fc +--- /dev/null ++++ b/fs/yaffs2/Kconfig +@@ -0,0 +1,171 @@ ++# ++# yaffs file system configurations ++# ++ ++config YAFFS_FS ++ tristate "yaffs2 file system support" ++ default n ++ depends on MTD_BLOCK ++ select YAFFS_YAFFS1 ++ select YAFFS_YAFFS2 ++ help ++ yaffs2, or Yet Another Flash File System, is a file system ++ optimised for NAND Flash chips. ++ ++ To compile the yaffs2 file system support as a module, choose M ++ here: the module will be called yaffs2. ++ ++ If unsure, say N. ++ ++ Further information on yaffs2 is available at ++ . ++ ++config YAFFS_YAFFS1 ++ bool "512 byte / page devices" ++ depends on YAFFS_FS ++ default y ++ help ++ Enable yaffs1 support -- yaffs for 512 byte / page devices ++ ++ Not needed for 2K-page devices. ++ ++ If unsure, say Y. ++ ++config YAFFS_9BYTE_TAGS ++ bool "Use older-style on-NAND data format with pageStatus byte" ++ depends on YAFFS_YAFFS1 ++ default n ++ help ++ ++ Older-style on-NAND data format has a "pageStatus" byte to record ++ chunk/page state. This byte is zero when the page is discarded. ++ Choose this option if you have existing on-NAND data using this ++ format that you need to continue to support. New data written ++ also uses the older-style format. Note: Use of this option ++ generally requires that MTD's oob layout be adjusted to use the ++ older-style format. See notes on tags formats and MTD versions ++ in yaffs_mtdif1.c. ++ ++ If unsure, say N. ++ ++config YAFFS_DOES_ECC ++ bool "Lets yaffs do its own ECC" ++ depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS ++ default n ++ help ++ This enables yaffs to use its own ECC functions instead of using ++ the ones from the generic MTD-NAND driver. ++ ++ If unsure, say N. ++ ++config YAFFS_ECC_WRONG_ORDER ++ bool "Use the same ecc byte order as Steven Hill's nand_ecc.c" ++ depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS ++ default n ++ help ++ This makes yaffs_ecc.c use the same ecc byte order as Steven ++ Hill's nand_ecc.c. If not set, then you get the same ecc byte ++ order as SmartMedia. ++ ++ If unsure, say N. ++ ++config YAFFS_YAFFS2 ++ bool "2048 byte (or larger) / page devices" ++ depends on YAFFS_FS ++ default y ++ help ++ Enable yaffs2 support -- yaffs for >= 2K bytes per page devices ++ ++ If unsure, say Y. ++ ++config YAFFS_AUTO_YAFFS2 ++ bool "Autoselect yaffs2 format" ++ depends on YAFFS_YAFFS2 ++ default y ++ help ++ Without this, you need to explicitely use yaffs2 as the file ++ system type. With this, you can say "yaffs" and yaffs or yaffs2 ++ will be used depending on the device page size (yaffs on ++ 512-byte page devices, yaffs2 on 2K page devices). ++ ++ If unsure, say Y. ++ ++config YAFFS_DISABLE_TAGS_ECC ++ bool "Disable yaffs from doing ECC on tags by default" ++ depends on YAFFS_FS && YAFFS_YAFFS2 ++ default n ++ help ++ This defaults yaffs to using its own ECC calculations on tags instead of ++ just relying on the MTD. ++ This behavior can also be overridden with tags_ecc_on and ++ tags_ecc_off mount options. ++ ++ If unsure, say N. ++ ++config YAFFS_ALWAYS_CHECK_CHUNK_ERASED ++ bool "Force chunk erase check" ++ depends on YAFFS_FS ++ default n ++ help ++ Normally yaffs only checks chunks before writing until an erased ++ chunk is found. This helps to detect any partially written ++ chunks that might have happened due to power loss. ++ ++ Enabling this forces on the test that chunks are erased in flash ++ before writing to them. This takes more time but is potentially ++ a bit more secure. ++ ++ Suggest setting Y during development and ironing out driver ++ issues etc. Suggest setting to N if you want faster writing. ++ ++ If unsure, say Y. ++ ++config YAFFS_EMPTY_LOST_AND_FOUND ++ bool "Empty lost and found on boot" ++ depends on YAFFS_FS ++ default n ++ help ++ If this is enabled then the contents of lost and found is ++ automatically dumped at mount. ++ ++ If unsure, say N. ++ ++config YAFFS_DISABLE_BLOCK_REFRESHING ++ bool "Disable yaffs2 block refreshing" ++ depends on YAFFS_FS ++ default n ++ help ++ If this is set, then block refreshing is disabled. ++ Block refreshing infrequently refreshes the oldest block in ++ a yaffs2 file system. This mechanism helps to refresh flash to ++ mitigate against data loss. This is particularly useful for MLC. ++ ++ If unsure, say N. ++ ++config YAFFS_DISABLE_BACKGROUND ++ bool "Disable yaffs2 background processing" ++ depends on YAFFS_FS ++ default n ++ help ++ If this is set, then background processing is disabled. ++ Background processing makes many foreground activities faster. ++ ++ If unsure, say N. ++ ++config YAFFS_DISABLE_BAD_BLOCK_MARKING ++ bool "Disable yaffs2 bad block marking" ++ depends on YAFFS_FS ++ default n ++ help ++ Useful during early flash bring up to prevent problems causing ++ lots of bad block marking. ++ ++ If unsure, say N. ++ ++config YAFFS_XATTR ++ bool "Enable yaffs2 xattr support" ++ depends on YAFFS_FS ++ default y ++ help ++ If this is set then yaffs2 will provide xattr support. ++ If unsure, say Y. +diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile +new file mode 100644 +index 00000000..f9a9fb1b +--- /dev/null ++++ b/fs/yaffs2/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for the linux YAFFS filesystem routines. ++# ++ ++obj-$(CONFIG_YAFFS_FS) += yaffs.o ++ ++yaffs-y := yaffs_ecc.o yaffs_vfs.o yaffs_guts.o yaffs_checkptrw.o ++yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o ++yaffs-y += yaffs_tagscompat.o yaffs_tagsmarshall.o ++yaffs-y += yaffs_mtdif.o ++yaffs-y += yaffs_nameval.o yaffs_attribs.o ++yaffs-y += yaffs_allocator.o ++yaffs-y += yaffs_yaffs1.o ++yaffs-y += yaffs_yaffs2.o ++yaffs-y += yaffs_bitmap.o ++yaffs-y += yaffs_summary.o ++yaffs-y += yaffs_verify.o ++ +diff --git a/fs/yaffs2/yaffs_allocator.c b/fs/yaffs2/yaffs_allocator.c +new file mode 100644 +index 00000000..c8f2861c +--- /dev/null ++++ b/fs/yaffs2/yaffs_allocator.c +@@ -0,0 +1,357 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_allocator.h" ++#include "yaffs_guts.h" ++#include "yaffs_trace.h" ++#include "yportenv.h" ++ ++/* ++ * Each entry in yaffs_tnode_list and yaffs_obj_list hold blocks ++ * of approx 100 objects that are themn allocated singly. ++ * This is basically a simplified slab allocator. ++ * ++ * We don't use the Linux slab allocator because slab does not allow ++ * us to dump all the objects in one hit when we do a umount and tear ++ * down all the tnodes and objects. slab requires that we first free ++ * the individual objects. ++ * ++ * Once yaffs has been mainlined I shall try to motivate for a change ++ * to slab to provide the extra features we need here. ++ */ ++ ++struct yaffs_tnode_list { ++ struct yaffs_tnode_list *next; ++ struct yaffs_tnode *tnodes; ++}; ++ ++struct yaffs_obj_list { ++ struct yaffs_obj_list *next; ++ struct yaffs_obj *objects; ++}; ++ ++struct yaffs_allocator { ++ int n_tnodes_created; ++ struct yaffs_tnode *free_tnodes; ++ int n_free_tnodes; ++ struct yaffs_tnode_list *alloc_tnode_list; ++ ++ int n_obj_created; ++ struct list_head free_objs; ++ int n_free_objects; ++ ++ struct yaffs_obj_list *allocated_obj_list; ++}; ++ ++static void yaffs_deinit_raw_tnodes(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator = ++ (struct yaffs_allocator *)dev->allocator; ++ struct yaffs_tnode_list *tmp; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ while (allocator->alloc_tnode_list) { ++ tmp = allocator->alloc_tnode_list->next; ++ ++ kfree(allocator->alloc_tnode_list->tnodes); ++ kfree(allocator->alloc_tnode_list); ++ allocator->alloc_tnode_list = tmp; ++ } ++ ++ allocator->free_tnodes = NULL; ++ allocator->n_free_tnodes = 0; ++ allocator->n_tnodes_created = 0; ++} ++ ++static void yaffs_init_raw_tnodes(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator = dev->allocator; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ allocator->alloc_tnode_list = NULL; ++ allocator->free_tnodes = NULL; ++ allocator->n_free_tnodes = 0; ++ allocator->n_tnodes_created = 0; ++} ++ ++static int yaffs_create_tnodes(struct yaffs_dev *dev, int n_tnodes) ++{ ++ struct yaffs_allocator *allocator = ++ (struct yaffs_allocator *)dev->allocator; ++ int i; ++ struct yaffs_tnode *new_tnodes; ++ u8 *mem; ++ struct yaffs_tnode *curr; ++ struct yaffs_tnode *next; ++ struct yaffs_tnode_list *tnl; ++ ++ if (!allocator) { ++ BUG(); ++ return YAFFS_FAIL; ++ } ++ ++ if (n_tnodes < 1) ++ return YAFFS_OK; ++ ++ /* make these things */ ++ new_tnodes = kmalloc(n_tnodes * dev->tnode_size, GFP_NOFS); ++ mem = (u8 *) new_tnodes; ++ ++ if (!new_tnodes) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs: Could not allocate Tnodes"); ++ return YAFFS_FAIL; ++ } ++ ++ /* New hookup for wide tnodes */ ++ for (i = 0; i < n_tnodes - 1; i++) { ++ curr = (struct yaffs_tnode *)&mem[i * dev->tnode_size]; ++ next = (struct yaffs_tnode *)&mem[(i + 1) * dev->tnode_size]; ++ curr->internal[0] = next; ++ } ++ ++ curr = (struct yaffs_tnode *)&mem[(n_tnodes - 1) * dev->tnode_size]; ++ curr->internal[0] = allocator->free_tnodes; ++ allocator->free_tnodes = (struct yaffs_tnode *)mem; ++ ++ allocator->n_free_tnodes += n_tnodes; ++ allocator->n_tnodes_created += n_tnodes; ++ ++ /* Now add this bunch of tnodes to a list for freeing up. ++ * NB If we can't add this to the management list it isn't fatal ++ * but it just means we can't free this bunch of tnodes later. ++ */ ++ tnl = kmalloc(sizeof(struct yaffs_tnode_list), GFP_NOFS); ++ if (!tnl) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "Could not add tnodes to management list"); ++ return YAFFS_FAIL; ++ } else { ++ tnl->tnodes = new_tnodes; ++ tnl->next = allocator->alloc_tnode_list; ++ allocator->alloc_tnode_list = tnl; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_ALLOCATE, "Tnodes added"); ++ ++ return YAFFS_OK; ++} ++ ++struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator = ++ (struct yaffs_allocator *)dev->allocator; ++ struct yaffs_tnode *tn = NULL; ++ ++ if (!allocator) { ++ BUG(); ++ return NULL; ++ } ++ ++ /* If there are none left make more */ ++ if (!allocator->free_tnodes) ++ yaffs_create_tnodes(dev, YAFFS_ALLOCATION_NTNODES); ++ ++ if (allocator->free_tnodes) { ++ tn = allocator->free_tnodes; ++ allocator->free_tnodes = allocator->free_tnodes->internal[0]; ++ allocator->n_free_tnodes--; ++ } ++ ++ return tn; ++} ++ ++/* FreeTnode frees up a tnode and puts it back on the free list */ ++void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) ++{ ++ struct yaffs_allocator *allocator = dev->allocator; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ if (tn) { ++ tn->internal[0] = allocator->free_tnodes; ++ allocator->free_tnodes = tn; ++ allocator->n_free_tnodes++; ++ } ++ dev->checkpoint_blocks_required = 0; /* force recalculation */ ++} ++ ++/*--------------- yaffs_obj alloaction ------------------------ ++ * ++ * Free yaffs_objs are stored in a list using obj->siblings. ++ * The blocks of allocated objects are stored in a linked list. ++ */ ++ ++static void yaffs_init_raw_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator = dev->allocator; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ allocator->allocated_obj_list = NULL; ++ INIT_LIST_HEAD(&allocator->free_objs); ++ allocator->n_free_objects = 0; ++} ++ ++static void yaffs_deinit_raw_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator = dev->allocator; ++ struct yaffs_obj_list *tmp; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ while (allocator->allocated_obj_list) { ++ tmp = allocator->allocated_obj_list->next; ++ kfree(allocator->allocated_obj_list->objects); ++ kfree(allocator->allocated_obj_list); ++ allocator->allocated_obj_list = tmp; ++ } ++ ++ INIT_LIST_HEAD(&allocator->free_objs); ++ allocator->n_free_objects = 0; ++ allocator->n_obj_created = 0; ++} ++ ++static int yaffs_create_free_objs(struct yaffs_dev *dev, int n_obj) ++{ ++ struct yaffs_allocator *allocator = dev->allocator; ++ int i; ++ struct yaffs_obj *new_objs; ++ struct yaffs_obj_list *list; ++ ++ if (!allocator) { ++ BUG(); ++ return YAFFS_FAIL; ++ } ++ ++ if (n_obj < 1) ++ return YAFFS_OK; ++ ++ /* make these things */ ++ new_objs = kmalloc(n_obj * sizeof(struct yaffs_obj), GFP_NOFS); ++ list = kmalloc(sizeof(struct yaffs_obj_list), GFP_NOFS); ++ ++ if (!new_objs || !list) { ++ kfree(new_objs); ++ new_objs = NULL; ++ kfree(list); ++ list = NULL; ++ yaffs_trace(YAFFS_TRACE_ALLOCATE, ++ "Could not allocate more objects"); ++ return YAFFS_FAIL; ++ } ++ ++ /* Hook them into the free list */ ++ for (i = 0; i < n_obj; i++) ++ list_add(&new_objs[i].siblings, &allocator->free_objs); ++ ++ allocator->n_free_objects += n_obj; ++ allocator->n_obj_created += n_obj; ++ ++ /* Now add this bunch of Objects to a list for freeing up. */ ++ ++ list->objects = new_objs; ++ list->next = allocator->allocated_obj_list; ++ allocator->allocated_obj_list = list; ++ ++ return YAFFS_OK; ++} ++ ++struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj = NULL; ++ struct list_head *lh; ++ struct yaffs_allocator *allocator = dev->allocator; ++ ++ if (!allocator) { ++ BUG(); ++ return obj; ++ } ++ ++ /* If there are none left make more */ ++ if (list_empty(&allocator->free_objs)) ++ yaffs_create_free_objs(dev, YAFFS_ALLOCATION_NOBJECTS); ++ ++ if (!list_empty(&allocator->free_objs)) { ++ lh = allocator->free_objs.next; ++ obj = list_entry(lh, struct yaffs_obj, siblings); ++ list_del_init(lh); ++ allocator->n_free_objects--; ++ } ++ ++ return obj; ++} ++ ++void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) ++{ ++ ++ struct yaffs_allocator *allocator = dev->allocator; ++ ++ if (!allocator) { ++ BUG(); ++ return; ++ } ++ ++ /* Link into the free list. */ ++ list_add(&obj->siblings, &allocator->free_objs); ++ allocator->n_free_objects++; ++} ++ ++void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) ++{ ++ ++ if (!dev->allocator) { ++ BUG(); ++ return; ++ } ++ ++ yaffs_deinit_raw_tnodes(dev); ++ yaffs_deinit_raw_objs(dev); ++ kfree(dev->allocator); ++ dev->allocator = NULL; ++} ++ ++void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_allocator *allocator; ++ ++ if (dev->allocator) { ++ BUG(); ++ return; ++ } ++ ++ allocator = kmalloc(sizeof(struct yaffs_allocator), GFP_NOFS); ++ if (allocator) { ++ dev->allocator = allocator; ++ yaffs_init_raw_tnodes(dev); ++ yaffs_init_raw_objs(dev); ++ } ++} ++ +diff --git a/fs/yaffs2/yaffs_allocator.h b/fs/yaffs2/yaffs_allocator.h +new file mode 100644 +index 00000000..a8cc3226 +--- /dev/null ++++ b/fs/yaffs2/yaffs_allocator.h +@@ -0,0 +1,30 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_ALLOCATOR_H__ ++#define __YAFFS_ALLOCATOR_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev); ++void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev); ++ ++struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev); ++void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn); ++ ++struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev); ++void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_attribs.c b/fs/yaffs2/yaffs_attribs.c +new file mode 100644 +index 00000000..3d778f22 +--- /dev/null ++++ b/fs/yaffs2/yaffs_attribs.c +@@ -0,0 +1,124 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_guts.h" ++#include "yaffs_attribs.h" ++ ++void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh) ++{ ++ obj->yst_uid = oh->yst_uid; ++ obj->yst_gid = oh->yst_gid; ++ obj->yst_atime = oh->yst_atime; ++ obj->yst_mtime = oh->yst_mtime; ++ obj->yst_ctime = oh->yst_ctime; ++ obj->yst_rdev = oh->yst_rdev; ++} ++ ++void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj) ++{ ++ oh->yst_uid = obj->yst_uid; ++ oh->yst_gid = obj->yst_gid; ++ oh->yst_atime = obj->yst_atime; ++ oh->yst_mtime = obj->yst_mtime; ++ oh->yst_ctime = obj->yst_ctime; ++ oh->yst_rdev = obj->yst_rdev; ++ ++} ++ ++void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c) ++{ ++ obj->yst_mtime = Y_CURRENT_TIME; ++ if (do_a) ++ obj->yst_atime = obj->yst_mtime; ++ if (do_c) ++ obj->yst_ctime = obj->yst_mtime; ++} ++ ++void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev) ++{ ++ yaffs_load_current_time(obj, 1, 1); ++ obj->yst_rdev = rdev; ++ obj->yst_uid = uid; ++ obj->yst_gid = gid; ++} ++ ++static loff_t yaffs_get_file_size(struct yaffs_obj *obj) ++{ ++ YCHAR *alias = NULL; ++ obj = yaffs_get_equivalent_obj(obj); ++ ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return obj->variant.file_variant.file_size; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ alias = obj->variant.symlink_variant.alias; ++ if (!alias) ++ return 0; ++ return strnlen(alias, YAFFS_MAX_ALIAS_LENGTH); ++ default: ++ return 0; ++ } ++} ++ ++int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr) ++{ ++ unsigned int valid = attr->ia_valid; ++ ++ if (valid & ATTR_MODE) ++ obj->yst_mode = attr->ia_mode; ++ if (valid & ATTR_UID) ++ obj->yst_uid = attr->ia_uid; ++ if (valid & ATTR_GID) ++ obj->yst_gid = attr->ia_gid; ++ ++ if (valid & ATTR_ATIME) ++ obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime); ++ if (valid & ATTR_CTIME) ++ obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime); ++ if (valid & ATTR_MTIME) ++ obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime); ++ ++ if (valid & ATTR_SIZE) ++ yaffs_resize_file(obj, attr->ia_size); ++ ++ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); ++ ++ return YAFFS_OK; ++ ++} ++ ++int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr) ++{ ++ unsigned int valid = 0; ++ ++ attr->ia_mode = obj->yst_mode; ++ valid |= ATTR_MODE; ++ attr->ia_uid = obj->yst_uid; ++ valid |= ATTR_UID; ++ attr->ia_gid = obj->yst_gid; ++ valid |= ATTR_GID; ++ ++ Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime; ++ valid |= ATTR_ATIME; ++ Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime; ++ valid |= ATTR_CTIME; ++ Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime; ++ valid |= ATTR_MTIME; ++ ++ attr->ia_size = yaffs_get_file_size(obj); ++ valid |= ATTR_SIZE; ++ ++ attr->ia_valid = valid; ++ ++ return YAFFS_OK; ++} +diff --git a/fs/yaffs2/yaffs_attribs.h b/fs/yaffs2/yaffs_attribs.h +new file mode 100644 +index 00000000..5b21b085 +--- /dev/null ++++ b/fs/yaffs2/yaffs_attribs.h +@@ -0,0 +1,28 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_ATTRIBS_H__ ++#define __YAFFS_ATTRIBS_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh); ++void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj); ++void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev); ++void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c); ++int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr); ++int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_bitmap.c b/fs/yaffs2/yaffs_bitmap.c +new file mode 100644 +index 00000000..4440e930 +--- /dev/null ++++ b/fs/yaffs2/yaffs_bitmap.c +@@ -0,0 +1,97 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_bitmap.h" ++#include "yaffs_trace.h" ++/* ++ * Chunk bitmap manipulations ++ */ ++ ++static inline u8 *yaffs_block_bits(struct yaffs_dev *dev, int blk) ++{ ++ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "BlockBits block %d is not valid", ++ blk); ++ BUG(); ++ } ++ return dev->chunk_bits + ++ (dev->chunk_bit_stride * (blk - dev->internal_start_block)); ++} ++ ++void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk) ++{ ++ if (blk < dev->internal_start_block || blk > dev->internal_end_block || ++ chunk < 0 || chunk >= dev->param.chunks_per_block) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "Chunk Id (%d:%d) invalid", ++ blk, chunk); ++ BUG(); ++ } ++} ++ ++void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ ++ memset(blk_bits, 0, dev->chunk_bit_stride); ++} ++ ++void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ ++ yaffs_verify_chunk_bit_id(dev, blk, chunk); ++ blk_bits[chunk / 8] &= ~(1 << (chunk & 7)); ++} ++ ++void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ ++ yaffs_verify_chunk_bit_id(dev, blk, chunk); ++ blk_bits[chunk / 8] |= (1 << (chunk & 7)); ++} ++ ++int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ ++ yaffs_verify_chunk_bit_id(dev, blk, chunk); ++ return (blk_bits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0; ++} ++ ++int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ int i; ++ ++ for (i = 0; i < dev->chunk_bit_stride; i++) { ++ if (*blk_bits) ++ return 1; ++ blk_bits++; ++ } ++ return 0; ++} ++ ++int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk) ++{ ++ u8 *blk_bits = yaffs_block_bits(dev, blk); ++ int i; ++ int n = 0; ++ ++ for (i = 0; i < dev->chunk_bit_stride; i++, blk_bits++) ++ n += hweight8(*blk_bits); ++ ++ return n; ++} +diff --git a/fs/yaffs2/yaffs_bitmap.h b/fs/yaffs2/yaffs_bitmap.h +new file mode 100644 +index 00000000..e26b37d8 +--- /dev/null ++++ b/fs/yaffs2/yaffs_bitmap.h +@@ -0,0 +1,33 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* ++ * Chunk bitmap manipulations ++ */ ++ ++#ifndef __YAFFS_BITMAP_H__ ++#define __YAFFS_BITMAP_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk); ++void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk); ++void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); ++void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); ++int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); ++int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk); ++int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_checkptrw.c b/fs/yaffs2/yaffs_checkptrw.c +new file mode 100644 +index 00000000..e739fb4a +--- /dev/null ++++ b/fs/yaffs2/yaffs_checkptrw.c +@@ -0,0 +1,474 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_checkptrw.h" ++#include "yaffs_getblockinfo.h" ++ ++struct yaffs_checkpt_chunk_hdr { ++ int version; ++ int seq; ++ u32 sum; ++ u32 xor; ++} ; ++ ++ ++static int apply_chunk_offset(struct yaffs_dev *dev, int chunk) ++{ ++ return chunk - dev->chunk_offset; ++} ++ ++static int apply_block_offset(struct yaffs_dev *dev, int block) ++{ ++ return block - dev->block_offset; ++} ++ ++static void yaffs2_checkpt_init_chunk_hdr(struct yaffs_dev *dev) ++{ ++ struct yaffs_checkpt_chunk_hdr hdr; ++ ++ hdr.version = YAFFS_CHECKPOINT_VERSION; ++ hdr.seq = dev->checkpt_page_seq; ++ hdr.sum = dev->checkpt_sum; ++ hdr.xor = dev->checkpt_xor; ++ ++ dev->checkpt_byte_offs = sizeof(hdr); ++ ++ memcpy(dev->checkpt_buffer, &hdr, sizeof(hdr)); ++} ++ ++static int yaffs2_checkpt_check_chunk_hdr(struct yaffs_dev *dev) ++{ ++ struct yaffs_checkpt_chunk_hdr hdr; ++ ++ memcpy(&hdr, dev->checkpt_buffer, sizeof(hdr)); ++ ++ dev->checkpt_byte_offs = sizeof(hdr); ++ ++ return hdr.version == YAFFS_CHECKPOINT_VERSION && ++ hdr.seq == dev->checkpt_page_seq && ++ hdr.sum == dev->checkpt_sum && ++ hdr.xor == dev->checkpt_xor; ++} ++ ++static int yaffs2_checkpt_space_ok(struct yaffs_dev *dev) ++{ ++ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "checkpt blocks_avail = %d", blocks_avail); ++ ++ return (blocks_avail <= 0) ? 0 : 1; ++} ++ ++static int yaffs_checkpt_erase(struct yaffs_dev *dev) ++{ ++ int i; ++ ++ if (!dev->drv.drv_erase_fn) ++ return 0; ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "checking blocks %d to %d", ++ dev->internal_start_block, dev->internal_end_block); ++ ++ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); ++ int offset_i = apply_block_offset(dev, i); ++ int result; ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "erasing checkpt block %d", i); ++ ++ dev->n_erasures++; ++ ++ result = dev->drv.drv_erase_fn(dev, offset_i); ++ if(result) { ++ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; ++ dev->n_erased_blocks++; ++ dev->n_free_chunks += ++ dev->param.chunks_per_block; ++ } else { ++ dev->drv.drv_mark_bad_fn(dev, offset_i); ++ bi->block_state = YAFFS_BLOCK_STATE_DEAD; ++ } ++ } ++ } ++ ++ dev->blocks_in_checkpt = 0; ++ ++ return 1; ++} ++ ++static void yaffs2_checkpt_find_erased_block(struct yaffs_dev *dev) ++{ ++ int i; ++ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "allocating checkpt block: erased %d reserved %d avail %d next %d ", ++ dev->n_erased_blocks, dev->param.n_reserved_blocks, ++ blocks_avail, dev->checkpt_next_block); ++ ++ if (dev->checkpt_next_block >= 0 && ++ dev->checkpt_next_block <= dev->internal_end_block && ++ blocks_avail > 0) { ++ ++ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; ++ i++) { ++ struct yaffs_block_info *bi; ++ ++ bi = yaffs_get_block_info(dev, i); ++ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { ++ dev->checkpt_next_block = i + 1; ++ dev->checkpt_cur_block = i; ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "allocating checkpt block %d", i); ++ return; ++ } ++ } ++ } ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, "out of checkpt blocks"); ++ ++ dev->checkpt_next_block = -1; ++ dev->checkpt_cur_block = -1; ++} ++ ++static void yaffs2_checkpt_find_block(struct yaffs_dev *dev) ++{ ++ int i; ++ struct yaffs_ext_tags tags; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "find next checkpt block: start: blocks %d next %d", ++ dev->blocks_in_checkpt, dev->checkpt_next_block); ++ ++ if (dev->blocks_in_checkpt < dev->checkpt_max_blocks) ++ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; ++ i++) { ++ int chunk = i * dev->param.chunks_per_block; ++ enum yaffs_block_state state; ++ u32 seq; ++ ++ dev->tagger.read_chunk_tags_fn(dev, ++ apply_chunk_offset(dev, chunk), ++ NULL, &tags); ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "find next checkpt block: search: block %d state %d oid %d seq %d eccr %d", ++ i, (int) state, ++ tags.obj_id, tags.seq_number, ++ tags.ecc_result); ++ ++ if (tags.seq_number != YAFFS_SEQUENCE_CHECKPOINT_DATA) ++ continue; ++ ++ dev->tagger.query_block_fn(dev, ++ apply_block_offset(dev, i), ++ &state, &seq); ++ if (state == YAFFS_BLOCK_STATE_DEAD) ++ continue; ++ ++ /* Right kind of block */ ++ dev->checkpt_next_block = tags.obj_id; ++ dev->checkpt_cur_block = i; ++ dev->checkpt_block_list[dev->blocks_in_checkpt] = i; ++ dev->blocks_in_checkpt++; ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "found checkpt block %d", i); ++ return; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, "found no more checkpt blocks"); ++ ++ dev->checkpt_next_block = -1; ++ dev->checkpt_cur_block = -1; ++} ++ ++int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing) ++{ ++ int i; ++ ++ dev->checkpt_open_write = writing; ++ ++ /* Got the functions we need? */ ++ if (!dev->tagger.write_chunk_tags_fn || ++ !dev->tagger.read_chunk_tags_fn || ++ !dev->drv.drv_erase_fn || ++ !dev->drv.drv_mark_bad_fn) ++ return 0; ++ ++ if (writing && !yaffs2_checkpt_space_ok(dev)) ++ return 0; ++ ++ if (!dev->checkpt_buffer) ++ dev->checkpt_buffer = ++ kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); ++ if (!dev->checkpt_buffer) ++ return 0; ++ ++ dev->checkpt_page_seq = 0; ++ dev->checkpt_byte_count = 0; ++ dev->checkpt_sum = 0; ++ dev->checkpt_xor = 0; ++ dev->checkpt_cur_block = -1; ++ dev->checkpt_cur_chunk = -1; ++ dev->checkpt_next_block = dev->internal_start_block; ++ ++ if (writing) { ++ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); ++ yaffs2_checkpt_init_chunk_hdr(dev); ++ return yaffs_checkpt_erase(dev); ++ } ++ ++ /* Opening for a read */ ++ /* Set to a value that will kick off a read */ ++ dev->checkpt_byte_offs = dev->data_bytes_per_chunk; ++ /* A checkpoint block list of 1 checkpoint block per 16 block is ++ * (hopefully) going to be way more than we need */ ++ dev->blocks_in_checkpt = 0; ++ dev->checkpt_max_blocks = ++ (dev->internal_end_block - dev->internal_start_block) / 16 + 2; ++ dev->checkpt_block_list = ++ kmalloc(sizeof(int) * dev->checkpt_max_blocks, GFP_NOFS); ++ ++ if (!dev->checkpt_block_list) ++ return 0; ++ ++ for (i = 0; i < dev->checkpt_max_blocks; i++) ++ dev->checkpt_block_list[i] = -1; ++ ++ return 1; ++} ++ ++int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum) ++{ ++ u32 composite_sum; ++ ++ composite_sum = (dev->checkpt_sum << 8) | (dev->checkpt_xor & 0xff); ++ *sum = composite_sum; ++ return 1; ++} ++ ++static int yaffs2_checkpt_flush_buffer(struct yaffs_dev *dev) ++{ ++ int chunk; ++ int offset_chunk; ++ struct yaffs_ext_tags tags; ++ ++ if (dev->checkpt_cur_block < 0) { ++ yaffs2_checkpt_find_erased_block(dev); ++ dev->checkpt_cur_chunk = 0; ++ } ++ ++ if (dev->checkpt_cur_block < 0) ++ return 0; ++ ++ tags.is_deleted = 0; ++ tags.obj_id = dev->checkpt_next_block; /* Hint to next place to look */ ++ tags.chunk_id = dev->checkpt_page_seq + 1; ++ tags.seq_number = YAFFS_SEQUENCE_CHECKPOINT_DATA; ++ tags.n_bytes = dev->data_bytes_per_chunk; ++ if (dev->checkpt_cur_chunk == 0) { ++ /* First chunk we write for the block? Set block state to ++ checkpoint */ ++ struct yaffs_block_info *bi = ++ yaffs_get_block_info(dev, dev->checkpt_cur_block); ++ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; ++ dev->blocks_in_checkpt++; ++ } ++ ++ chunk = ++ dev->checkpt_cur_block * dev->param.chunks_per_block + ++ dev->checkpt_cur_chunk; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "checkpoint wite buffer nand %d(%d:%d) objid %d chId %d", ++ chunk, dev->checkpt_cur_block, dev->checkpt_cur_chunk, ++ tags.obj_id, tags.chunk_id); ++ ++ offset_chunk = apply_chunk_offset(dev, chunk); ++ ++ dev->n_page_writes++; ++ ++ dev->tagger.write_chunk_tags_fn(dev, offset_chunk, ++ dev->checkpt_buffer, &tags); ++ dev->checkpt_page_seq++; ++ dev->checkpt_cur_chunk++; ++ if (dev->checkpt_cur_chunk >= dev->param.chunks_per_block) { ++ dev->checkpt_cur_chunk = 0; ++ dev->checkpt_cur_block = -1; ++ } ++ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); ++ ++ yaffs2_checkpt_init_chunk_hdr(dev); ++ ++ ++ return 1; ++} ++ ++int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes) ++{ ++ int i = 0; ++ int ok = 1; ++ u8 *data_bytes = (u8 *) data; ++ ++ if (!dev->checkpt_buffer) ++ return 0; ++ ++ if (!dev->checkpt_open_write) ++ return -1; ++ ++ while (i < n_bytes && ok) { ++ dev->checkpt_buffer[dev->checkpt_byte_offs] = *data_bytes; ++ dev->checkpt_sum += *data_bytes; ++ dev->checkpt_xor ^= *data_bytes; ++ ++ dev->checkpt_byte_offs++; ++ i++; ++ data_bytes++; ++ dev->checkpt_byte_count++; ++ ++ if (dev->checkpt_byte_offs < 0 || ++ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) ++ ok = yaffs2_checkpt_flush_buffer(dev); ++ } ++ ++ return i; ++} ++ ++int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes) ++{ ++ int i = 0; ++ int ok = 1; ++ struct yaffs_ext_tags tags; ++ int chunk; ++ int offset_chunk; ++ u8 *data_bytes = (u8 *) data; ++ ++ if (!dev->checkpt_buffer) ++ return 0; ++ ++ if (dev->checkpt_open_write) ++ return -1; ++ ++ while (i < n_bytes && ok) { ++ ++ if (dev->checkpt_byte_offs < 0 || ++ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) { ++ ++ if (dev->checkpt_cur_block < 0) { ++ yaffs2_checkpt_find_block(dev); ++ dev->checkpt_cur_chunk = 0; ++ } ++ ++ if (dev->checkpt_cur_block < 0) { ++ ok = 0; ++ break; ++ } ++ ++ chunk = dev->checkpt_cur_block * ++ dev->param.chunks_per_block + ++ dev->checkpt_cur_chunk; ++ ++ offset_chunk = apply_chunk_offset(dev, chunk); ++ dev->n_page_reads++; ++ ++ /* read in the next chunk */ ++ dev->tagger.read_chunk_tags_fn(dev, ++ offset_chunk, ++ dev->checkpt_buffer, ++ &tags); ++ ++ if (tags.chunk_id != (dev->checkpt_page_seq + 1) || ++ tags.ecc_result > YAFFS_ECC_RESULT_FIXED || ++ tags.seq_number != YAFFS_SEQUENCE_CHECKPOINT_DATA) { ++ ok = 0; ++ break; ++ } ++ if(!yaffs2_checkpt_check_chunk_hdr(dev)) { ++ ok = 0; ++ break; ++ } ++ ++ dev->checkpt_page_seq++; ++ dev->checkpt_cur_chunk++; ++ ++ if (dev->checkpt_cur_chunk >= ++ dev->param.chunks_per_block) ++ dev->checkpt_cur_block = -1; ++ ++ } ++ ++ *data_bytes = dev->checkpt_buffer[dev->checkpt_byte_offs]; ++ dev->checkpt_sum += *data_bytes; ++ dev->checkpt_xor ^= *data_bytes; ++ dev->checkpt_byte_offs++; ++ i++; ++ data_bytes++; ++ dev->checkpt_byte_count++; ++ } ++ ++ return i; ++} ++ ++int yaffs_checkpt_close(struct yaffs_dev *dev) ++{ ++ int i; ++ ++ if (dev->checkpt_open_write) { ++ if (dev->checkpt_byte_offs != ++ sizeof(sizeof(struct yaffs_checkpt_chunk_hdr))) ++ yaffs2_checkpt_flush_buffer(dev); ++ } else if (dev->checkpt_block_list) { ++ for (i = 0; ++ i < dev->blocks_in_checkpt && ++ dev->checkpt_block_list[i] >= 0; i++) { ++ int blk = dev->checkpt_block_list[i]; ++ struct yaffs_block_info *bi = NULL; ++ ++ if (dev->internal_start_block <= blk && ++ blk <= dev->internal_end_block) ++ bi = yaffs_get_block_info(dev, blk); ++ if (bi && bi->block_state == YAFFS_BLOCK_STATE_EMPTY) ++ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; ++ } ++ kfree(dev->checkpt_block_list); ++ dev->checkpt_block_list = NULL; ++ } ++ ++ dev->n_free_chunks -= ++ dev->blocks_in_checkpt * dev->param.chunks_per_block; ++ dev->n_erased_blocks -= dev->blocks_in_checkpt; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, "checkpoint byte count %d", ++ dev->checkpt_byte_count); ++ ++ if (dev->checkpt_buffer) { ++ /* free the buffer */ ++ kfree(dev->checkpt_buffer); ++ dev->checkpt_buffer = NULL; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev) ++{ ++ /* Erase the checkpoint data */ ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "checkpoint invalidate of %d blocks", ++ dev->blocks_in_checkpt); ++ ++ return yaffs_checkpt_erase(dev); ++} +diff --git a/fs/yaffs2/yaffs_checkptrw.h b/fs/yaffs2/yaffs_checkptrw.h +new file mode 100644 +index 00000000..cdbaba71 +--- /dev/null ++++ b/fs/yaffs2/yaffs_checkptrw.h +@@ -0,0 +1,33 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_CHECKPTRW_H__ ++#define __YAFFS_CHECKPTRW_H__ ++ ++#include "yaffs_guts.h" ++ ++int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing); ++ ++int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes); ++ ++int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes); ++ ++int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum); ++ ++int yaffs_checkpt_close(struct yaffs_dev *dev); ++ ++int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_ecc.c b/fs/yaffs2/yaffs_ecc.c +new file mode 100644 +index 00000000..9294107c +--- /dev/null ++++ b/fs/yaffs2/yaffs_ecc.c +@@ -0,0 +1,281 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * This code implements the ECC algorithm used in SmartMedia. ++ * ++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. ++ * The two unused bit are set to 1. ++ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two ++ * such ECC blocks are used on a 512-byte NAND page. ++ * ++ */ ++ ++#include "yportenv.h" ++ ++#include "yaffs_ecc.h" ++ ++/* Table generated by gen-ecc.c ++ * Using a table means we do not have to calculate p1..p4 and p1'..p4' ++ * for each byte of data. These are instead provided in a table in bits7..2. ++ * Bit 0 of each entry indicates whether the entry has an odd or even parity, ++ * and therefore this bytes influence on the line parity. ++ */ ++ ++static const unsigned char column_parity_table[] = { ++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, ++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, ++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, ++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, ++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, ++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, ++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, ++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, ++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, ++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, ++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, ++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, ++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, ++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, ++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, ++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, ++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, ++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, ++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, ++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, ++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, ++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, ++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, ++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, ++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, ++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, ++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, ++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, ++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, ++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, ++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, ++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, ++}; ++ ++ ++/* Calculate the ECC for a 256-byte block of data */ ++void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc) ++{ ++ unsigned int i; ++ unsigned char col_parity = 0; ++ unsigned char line_parity = 0; ++ unsigned char line_parity_prime = 0; ++ unsigned char t; ++ unsigned char b; ++ ++ for (i = 0; i < 256; i++) { ++ b = column_parity_table[*data++]; ++ col_parity ^= b; ++ ++ if (b & 0x01) { /* odd number of bits in the byte */ ++ line_parity ^= i; ++ line_parity_prime ^= ~i; ++ } ++ } ++ ++ ecc[2] = (~col_parity) | 0x03; ++ ++ t = 0; ++ if (line_parity & 0x80) ++ t |= 0x80; ++ if (line_parity_prime & 0x80) ++ t |= 0x40; ++ if (line_parity & 0x40) ++ t |= 0x20; ++ if (line_parity_prime & 0x40) ++ t |= 0x10; ++ if (line_parity & 0x20) ++ t |= 0x08; ++ if (line_parity_prime & 0x20) ++ t |= 0x04; ++ if (line_parity & 0x10) ++ t |= 0x02; ++ if (line_parity_prime & 0x10) ++ t |= 0x01; ++ ecc[1] = ~t; ++ ++ t = 0; ++ if (line_parity & 0x08) ++ t |= 0x80; ++ if (line_parity_prime & 0x08) ++ t |= 0x40; ++ if (line_parity & 0x04) ++ t |= 0x20; ++ if (line_parity_prime & 0x04) ++ t |= 0x10; ++ if (line_parity & 0x02) ++ t |= 0x08; ++ if (line_parity_prime & 0x02) ++ t |= 0x04; ++ if (line_parity & 0x01) ++ t |= 0x02; ++ if (line_parity_prime & 0x01) ++ t |= 0x01; ++ ecc[0] = ~t; ++ ++} ++ ++/* Correct the ECC on a 256 byte block of data */ ++ ++int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, ++ const unsigned char *test_ecc) ++{ ++ unsigned char d0, d1, d2; /* deltas */ ++ ++ d0 = read_ecc[0] ^ test_ecc[0]; ++ d1 = read_ecc[1] ^ test_ecc[1]; ++ d2 = read_ecc[2] ^ test_ecc[2]; ++ ++ if ((d0 | d1 | d2) == 0) ++ return 0; /* no error */ ++ ++ if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 && ++ ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 && ++ ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) { ++ /* Single bit (recoverable) error in data */ ++ ++ unsigned byte; ++ unsigned bit; ++ ++ bit = byte = 0; ++ ++ if (d1 & 0x80) ++ byte |= 0x80; ++ if (d1 & 0x20) ++ byte |= 0x40; ++ if (d1 & 0x08) ++ byte |= 0x20; ++ if (d1 & 0x02) ++ byte |= 0x10; ++ if (d0 & 0x80) ++ byte |= 0x08; ++ if (d0 & 0x20) ++ byte |= 0x04; ++ if (d0 & 0x08) ++ byte |= 0x02; ++ if (d0 & 0x02) ++ byte |= 0x01; ++ ++ if (d2 & 0x80) ++ bit |= 0x04; ++ if (d2 & 0x20) ++ bit |= 0x02; ++ if (d2 & 0x08) ++ bit |= 0x01; ++ ++ data[byte] ^= (1 << bit); ++ ++ return 1; /* Corrected the error */ ++ } ++ ++ if ((hweight8(d0) + hweight8(d1) + hweight8(d2)) == 1) { ++ /* Reccoverable error in ecc */ ++ ++ read_ecc[0] = test_ecc[0]; ++ read_ecc[1] = test_ecc[1]; ++ read_ecc[2] = test_ecc[2]; ++ ++ return 1; /* Corrected the error */ ++ } ++ ++ /* Unrecoverable error */ ++ ++ return -1; ++ ++} ++ ++/* ++ * ECCxxxOther does ECC calcs on arbitrary n bytes of data ++ */ ++void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, ++ struct yaffs_ecc_other *ecc_other) ++{ ++ unsigned int i; ++ unsigned char col_parity = 0; ++ unsigned line_parity = 0; ++ unsigned line_parity_prime = 0; ++ unsigned char b; ++ ++ for (i = 0; i < n_bytes; i++) { ++ b = column_parity_table[*data++]; ++ col_parity ^= b; ++ ++ if (b & 0x01) { ++ /* odd number of bits in the byte */ ++ line_parity ^= i; ++ line_parity_prime ^= ~i; ++ } ++ ++ } ++ ++ ecc_other->col_parity = (col_parity >> 2) & 0x3f; ++ ecc_other->line_parity = line_parity; ++ ecc_other->line_parity_prime = line_parity_prime; ++} ++ ++int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, ++ struct yaffs_ecc_other *read_ecc, ++ const struct yaffs_ecc_other *test_ecc) ++{ ++ unsigned char delta_col; /* column parity delta */ ++ unsigned delta_line; /* line parity delta */ ++ unsigned delta_line_prime; /* line parity delta */ ++ unsigned bit; ++ ++ delta_col = read_ecc->col_parity ^ test_ecc->col_parity; ++ delta_line = read_ecc->line_parity ^ test_ecc->line_parity; ++ delta_line_prime = ++ read_ecc->line_parity_prime ^ test_ecc->line_parity_prime; ++ ++ if ((delta_col | delta_line | delta_line_prime) == 0) ++ return 0; /* no error */ ++ ++ if (delta_line == ~delta_line_prime && ++ (((delta_col ^ (delta_col >> 1)) & 0x15) == 0x15)) { ++ /* Single bit (recoverable) error in data */ ++ ++ bit = 0; ++ ++ if (delta_col & 0x20) ++ bit |= 0x04; ++ if (delta_col & 0x08) ++ bit |= 0x02; ++ if (delta_col & 0x02) ++ bit |= 0x01; ++ ++ if (delta_line >= n_bytes) ++ return -1; ++ ++ data[delta_line] ^= (1 << bit); ++ ++ return 1; /* corrected */ ++ } ++ ++ if ((hweight32(delta_line) + ++ hweight32(delta_line_prime) + ++ hweight8(delta_col)) == 1) { ++ /* Reccoverable error in ecc */ ++ ++ *read_ecc = *test_ecc; ++ return 1; /* corrected */ ++ } ++ ++ /* Unrecoverable error */ ++ ++ return -1; ++} +diff --git a/fs/yaffs2/yaffs_ecc.h b/fs/yaffs2/yaffs_ecc.h +new file mode 100644 +index 00000000..17d47bd8 +--- /dev/null ++++ b/fs/yaffs2/yaffs_ecc.h +@@ -0,0 +1,44 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* ++ * This code implements the ECC algorithm used in SmartMedia. ++ * ++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. ++ * The two unused bit are set to 1. ++ * The ECC can correct single bit errors in a 256-byte page of data. ++ * Thus, two such ECC blocks are used on a 512-byte NAND page. ++ * ++ */ ++ ++#ifndef __YAFFS_ECC_H__ ++#define __YAFFS_ECC_H__ ++ ++struct yaffs_ecc_other { ++ unsigned char col_parity; ++ unsigned line_parity; ++ unsigned line_parity_prime; ++}; ++ ++void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc); ++int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, ++ const unsigned char *test_ecc); ++ ++void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, ++ struct yaffs_ecc_other *ecc); ++int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, ++ struct yaffs_ecc_other *read_ecc, ++ const struct yaffs_ecc_other *test_ecc); ++#endif +diff --git a/fs/yaffs2/yaffs_getblockinfo.h b/fs/yaffs2/yaffs_getblockinfo.h +new file mode 100644 +index 00000000..8fd0802b +--- /dev/null ++++ b/fs/yaffs2/yaffs_getblockinfo.h +@@ -0,0 +1,35 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_GETBLOCKINFO_H__ ++#define __YAFFS_GETBLOCKINFO_H__ ++ ++#include "yaffs_guts.h" ++#include "yaffs_trace.h" ++ ++/* Function to manipulate block info */ ++static inline struct yaffs_block_info *yaffs_get_block_info(struct yaffs_dev ++ *dev, int blk) ++{ ++ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>> yaffs: get_block_info block %d is not valid", ++ blk); ++ BUG(); ++ } ++ return &dev->block_info[blk - dev->internal_start_block]; ++} ++ ++#endif +diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c +new file mode 100644 +index 00000000..1de28173 +--- /dev/null ++++ b/fs/yaffs2/yaffs_guts.c +@@ -0,0 +1,5146 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yportenv.h" ++#include "yaffs_trace.h" ++ ++#include "yaffs_guts.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_tagscompat.h" ++#include "yaffs_tagsmarshall.h" ++#include "yaffs_nand.h" ++#include "yaffs_yaffs1.h" ++#include "yaffs_yaffs2.h" ++#include "yaffs_bitmap.h" ++#include "yaffs_verify.h" ++#include "yaffs_nand.h" ++#include "yaffs_packedtags2.h" ++#include "yaffs_nameval.h" ++#include "yaffs_allocator.h" ++#include "yaffs_attribs.h" ++#include "yaffs_summary.h" ++ ++/* Note YAFFS_GC_GOOD_ENOUGH must be <= YAFFS_GC_PASSIVE_THRESHOLD */ ++#define YAFFS_GC_GOOD_ENOUGH 2 ++#define YAFFS_GC_PASSIVE_THRESHOLD 4 ++ ++#include "yaffs_ecc.h" ++ ++/* Forward declarations */ ++ ++static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, ++ const u8 *buffer, int n_bytes, int use_reserve); ++ ++static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR *name, ++ int buffer_size); ++ ++/* Function to calculate chunk and offset */ ++ ++void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, ++ int *chunk_out, u32 *offset_out) ++{ ++ int chunk; ++ u32 offset; ++ ++ chunk = (u32) (addr >> dev->chunk_shift); ++ ++ if (dev->chunk_div == 1) { ++ /* easy power of 2 case */ ++ offset = (u32) (addr & dev->chunk_mask); ++ } else { ++ /* Non power-of-2 case */ ++ ++ loff_t chunk_base; ++ ++ chunk /= dev->chunk_div; ++ ++ chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk; ++ offset = (u32) (addr - chunk_base); ++ } ++ ++ *chunk_out = chunk; ++ *offset_out = offset; ++} ++ ++/* Function to return the number of shifts for a power of 2 greater than or ++ * equal to the given number ++ * Note we don't try to cater for all possible numbers and this does not have to ++ * be hellishly efficient. ++ */ ++ ++static inline u32 calc_shifts_ceiling(u32 x) ++{ ++ int extra_bits; ++ int shifts; ++ ++ shifts = extra_bits = 0; ++ ++ while (x > 1) { ++ if (x & 1) ++ extra_bits++; ++ x >>= 1; ++ shifts++; ++ } ++ ++ if (extra_bits) ++ shifts++; ++ ++ return shifts; ++} ++ ++/* Function to return the number of shifts to get a 1 in bit 0 ++ */ ++ ++static inline u32 calc_shifts(u32 x) ++{ ++ u32 shifts; ++ ++ shifts = 0; ++ ++ if (!x) ++ return 0; ++ ++ while (!(x & 1)) { ++ x >>= 1; ++ shifts++; ++ } ++ ++ return shifts; ++} ++ ++/* ++ * Temporary buffer manipulations. ++ */ ++ ++static int yaffs_init_tmp_buffers(struct yaffs_dev *dev) ++{ ++ int i; ++ u8 *buf = (u8 *) 1; ++ ++ memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer)); ++ ++ for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) { ++ dev->temp_buffer[i].in_use = 0; ++ buf = kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); ++ dev->temp_buffer[i].buffer = buf; ++ } ++ ++ return buf ? YAFFS_OK : YAFFS_FAIL; ++} ++ ++u8 *yaffs_get_temp_buffer(struct yaffs_dev * dev) ++{ ++ int i; ++ ++ dev->temp_in_use++; ++ if (dev->temp_in_use > dev->max_temp) ++ dev->max_temp = dev->temp_in_use; ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ if (dev->temp_buffer[i].in_use == 0) { ++ dev->temp_buffer[i].in_use = 1; ++ return dev->temp_buffer[i].buffer; ++ } ++ } ++ ++ yaffs_trace(YAFFS_TRACE_BUFFERS, "Out of temp buffers"); ++ /* ++ * If we got here then we have to allocate an unmanaged one ++ * This is not good. ++ */ ++ ++ dev->unmanaged_buffer_allocs++; ++ return kmalloc(dev->data_bytes_per_chunk, GFP_NOFS); ++ ++} ++ ++void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer) ++{ ++ int i; ++ ++ dev->temp_in_use--; ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ if (dev->temp_buffer[i].buffer == buffer) { ++ dev->temp_buffer[i].in_use = 0; ++ return; ++ } ++ } ++ ++ if (buffer) { ++ /* assume it is an unmanaged one. */ ++ yaffs_trace(YAFFS_TRACE_BUFFERS, ++ "Releasing unmanaged temp buffer"); ++ kfree(buffer); ++ dev->unmanaged_buffer_deallocs++; ++ } ++ ++} ++ ++/* ++ * Functions for robustisizing TODO ++ * ++ */ ++ ++static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, ++ const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ (void) dev; ++ (void) nand_chunk; ++ (void) data; ++ (void) tags; ++} ++ ++static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, ++ const struct yaffs_ext_tags *tags) ++{ ++ (void) dev; ++ (void) nand_chunk; ++ (void) tags; ++} ++ ++void yaffs_handle_chunk_error(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi) ++{ ++ if (!bi->gc_prioritise) { ++ bi->gc_prioritise = 1; ++ dev->has_pending_prioritised_gc = 1; ++ bi->chunk_error_strikes++; ++ ++ if (bi->chunk_error_strikes > 3) { ++ bi->needs_retiring = 1; /* Too many stikes, so retire */ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: Block struck out"); ++ ++ } ++ } ++} ++ ++static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, ++ int erased_ok) ++{ ++ int flash_block = nand_chunk / dev->param.chunks_per_block; ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); ++ ++ yaffs_handle_chunk_error(dev, bi); ++ ++ if (erased_ok) { ++ /* Was an actual write failure, ++ * so mark the block for retirement.*/ ++ bi->needs_retiring = 1; ++ yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ "**>> Block %d needs retiring", flash_block); ++ } ++ ++ /* Delete the chunk */ ++ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); ++ yaffs_skip_rest_of_block(dev); ++} ++ ++/* ++ * Verification code ++ */ ++ ++/* ++ * Simple hash function. Needs to have a reasonable spread ++ */ ++ ++static inline int yaffs_hash_fn(int n) ++{ ++ if (n < 0) ++ n = -n; ++ return n % YAFFS_NOBJECT_BUCKETS; ++} ++ ++/* ++ * Access functions to useful fake objects. ++ * Note that root might have a presence in NAND if permissions are set. ++ */ ++ ++struct yaffs_obj *yaffs_root(struct yaffs_dev *dev) ++{ ++ return dev->root_dir; ++} ++ ++struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev) ++{ ++ return dev->lost_n_found; ++} ++ ++/* ++ * Erased NAND checking functions ++ */ ++ ++int yaffs_check_ff(u8 *buffer, int n_bytes) ++{ ++ /* Horrible, slow implementation */ ++ while (n_bytes--) { ++ if (*buffer != 0xff) ++ return 0; ++ buffer++; ++ } ++ return 1; ++} ++ ++static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk) ++{ ++ int retval = YAFFS_OK; ++ u8 *data = yaffs_get_temp_buffer(dev); ++ struct yaffs_ext_tags tags; ++ int result; ++ ++ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); ++ ++ if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR) ++ retval = YAFFS_FAIL; ++ ++ if (!yaffs_check_ff(data, dev->data_bytes_per_chunk) || ++ tags.chunk_used) { ++ yaffs_trace(YAFFS_TRACE_NANDACCESS, ++ "Chunk %d not erased", nand_chunk); ++ retval = YAFFS_FAIL; ++ } ++ ++ yaffs_release_temp_buffer(dev, data); ++ ++ return retval; ++ ++} ++ ++static int yaffs_verify_chunk_written(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ int retval = YAFFS_OK; ++ struct yaffs_ext_tags temp_tags; ++ u8 *buffer = yaffs_get_temp_buffer(dev); ++ int result; ++ ++ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); ++ if (memcmp(buffer, data, dev->data_bytes_per_chunk) || ++ temp_tags.obj_id != tags->obj_id || ++ temp_tags.chunk_id != tags->chunk_id || ++ temp_tags.n_bytes != tags->n_bytes) ++ retval = YAFFS_FAIL; ++ ++ yaffs_release_temp_buffer(dev, buffer); ++ ++ return retval; ++} ++ ++ ++int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks) ++{ ++ int reserved_chunks; ++ int reserved_blocks = dev->param.n_reserved_blocks; ++ int checkpt_blocks; ++ ++ checkpt_blocks = yaffs_calc_checkpt_blocks_required(dev); ++ ++ reserved_chunks = ++ (reserved_blocks + checkpt_blocks) * dev->param.chunks_per_block; ++ ++ return (dev->n_free_chunks > (reserved_chunks + n_chunks)); ++} ++ ++static int yaffs_find_alloc_block(struct yaffs_dev *dev) ++{ ++ int i; ++ struct yaffs_block_info *bi; ++ ++ if (dev->n_erased_blocks < 1) { ++ /* Hoosterman we've got a problem. ++ * Can't get space to gc ++ */ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: no more erased blocks"); ++ ++ return -1; ++ } ++ ++ /* Find an empty block. */ ++ ++ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ dev->alloc_block_finder++; ++ if (dev->alloc_block_finder < dev->internal_start_block ++ || dev->alloc_block_finder > dev->internal_end_block) { ++ dev->alloc_block_finder = dev->internal_start_block; ++ } ++ ++ bi = yaffs_get_block_info(dev, dev->alloc_block_finder); ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { ++ bi->block_state = YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->seq_number++; ++ bi->seq_number = dev->seq_number; ++ dev->n_erased_blocks--; ++ yaffs_trace(YAFFS_TRACE_ALLOCATE, ++ "Allocated block %d, seq %d, %d left" , ++ dev->alloc_block_finder, dev->seq_number, ++ dev->n_erased_blocks); ++ return dev->alloc_block_finder; ++ } ++ } ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs tragedy: no more erased blocks, but there should have been %d", ++ dev->n_erased_blocks); ++ ++ return -1; ++} ++ ++static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, ++ struct yaffs_block_info **block_ptr) ++{ ++ int ret_val; ++ struct yaffs_block_info *bi; ++ ++ if (dev->alloc_block < 0) { ++ /* Get next block to allocate off */ ++ dev->alloc_block = yaffs_find_alloc_block(dev); ++ dev->alloc_page = 0; ++ } ++ ++ if (!use_reserver && !yaffs_check_alloc_available(dev, 1)) { ++ /* No space unless we're allowed to use the reserve. */ ++ return -1; ++ } ++ ++ if (dev->n_erased_blocks < dev->param.n_reserved_blocks ++ && dev->alloc_page == 0) ++ yaffs_trace(YAFFS_TRACE_ALLOCATE, "Allocating reserve"); ++ ++ /* Next page please.... */ ++ if (dev->alloc_block >= 0) { ++ bi = yaffs_get_block_info(dev, dev->alloc_block); ++ ++ ret_val = (dev->alloc_block * dev->param.chunks_per_block) + ++ dev->alloc_page; ++ bi->pages_in_use++; ++ yaffs_set_chunk_bit(dev, dev->alloc_block, dev->alloc_page); ++ ++ dev->alloc_page++; ++ ++ dev->n_free_chunks--; ++ ++ /* If the block is full set the state to full */ ++ if (dev->alloc_page >= dev->param.chunks_per_block) { ++ bi->block_state = YAFFS_BLOCK_STATE_FULL; ++ dev->alloc_block = -1; ++ } ++ ++ if (block_ptr) ++ *block_ptr = bi; ++ ++ return ret_val; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!"); ++ ++ return -1; ++} ++ ++static int yaffs_get_erased_chunks(struct yaffs_dev *dev) ++{ ++ int n; ++ ++ n = dev->n_erased_blocks * dev->param.chunks_per_block; ++ ++ if (dev->alloc_block > 0) ++ n += (dev->param.chunks_per_block - dev->alloc_page); ++ ++ return n; ++ ++} ++ ++/* ++ * yaffs_skip_rest_of_block() skips over the rest of the allocation block ++ * if we don't want to write to it. ++ */ ++void yaffs_skip_rest_of_block(struct yaffs_dev *dev) ++{ ++ struct yaffs_block_info *bi; ++ ++ if (dev->alloc_block > 0) { ++ bi = yaffs_get_block_info(dev, dev->alloc_block); ++ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { ++ bi->block_state = YAFFS_BLOCK_STATE_FULL; ++ dev->alloc_block = -1; ++ } ++ } ++} ++ ++static int yaffs_write_new_chunk(struct yaffs_dev *dev, ++ const u8 *data, ++ struct yaffs_ext_tags *tags, int use_reserver) ++{ ++ int attempts = 0; ++ int write_ok = 0; ++ int chunk; ++ ++ yaffs2_checkpt_invalidate(dev); ++ ++ do { ++ struct yaffs_block_info *bi = 0; ++ int erased_ok = 0; ++ ++ chunk = yaffs_alloc_chunk(dev, use_reserver, &bi); ++ if (chunk < 0) { ++ /* no space */ ++ break; ++ } ++ ++ /* First check this chunk is erased, if it needs ++ * checking. The checking policy (unless forced ++ * always on) is as follows: ++ * ++ * Check the first page we try to write in a block. ++ * If the check passes then we don't need to check any ++ * more. If the check fails, we check again... ++ * If the block has been erased, we don't need to check. ++ * ++ * However, if the block has been prioritised for gc, ++ * then we think there might be something odd about ++ * this block and stop using it. ++ * ++ * Rationale: We should only ever see chunks that have ++ * not been erased if there was a partially written ++ * chunk due to power loss. This checking policy should ++ * catch that case with very few checks and thus save a ++ * lot of checks that are most likely not needed. ++ * ++ * Mods to the above ++ * If an erase check fails or the write fails we skip the ++ * rest of the block. ++ */ ++ ++ /* let's give it a try */ ++ attempts++; ++ ++ if (dev->param.always_check_erased) ++ bi->skip_erased_check = 0; ++ ++ if (!bi->skip_erased_check) { ++ erased_ok = yaffs_check_chunk_erased(dev, chunk); ++ if (erased_ok != YAFFS_OK) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>> yaffs chunk %d was not erased", ++ chunk); ++ ++ /* If not erased, delete this one, ++ * skip rest of block and ++ * try another chunk */ ++ yaffs_chunk_del(dev, chunk, 1, __LINE__); ++ yaffs_skip_rest_of_block(dev); ++ continue; ++ } ++ } ++ ++ write_ok = yaffs_wr_chunk_tags_nand(dev, chunk, data, tags); ++ ++ if (!bi->skip_erased_check) ++ write_ok = ++ yaffs_verify_chunk_written(dev, chunk, data, tags); ++ ++ if (write_ok != YAFFS_OK) { ++ /* Clean up aborted write, skip to next block and ++ * try another chunk */ ++ yaffs_handle_chunk_wr_error(dev, chunk, erased_ok); ++ continue; ++ } ++ ++ bi->skip_erased_check = 1; ++ ++ /* Copy the data into the robustification buffer */ ++ yaffs_handle_chunk_wr_ok(dev, chunk, data, tags); ++ ++ } while (write_ok != YAFFS_OK && ++ (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts)); ++ ++ if (!write_ok) ++ chunk = -1; ++ ++ if (attempts > 1) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>> yaffs write required %d attempts", ++ attempts); ++ dev->n_retried_writes += (attempts - 1); ++ } ++ ++ return chunk; ++} ++ ++/* ++ * Block retiring for handling a broken block. ++ */ ++ ++static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block) ++{ ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); ++ ++ yaffs2_checkpt_invalidate(dev); ++ ++ yaffs2_clear_oldest_dirty_seq(dev, bi); ++ ++ if (yaffs_mark_bad(dev, flash_block) != YAFFS_OK) { ++ if (yaffs_erase_block(dev, flash_block) != YAFFS_OK) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: Failed to mark bad and erase block %d", ++ flash_block); ++ } else { ++ struct yaffs_ext_tags tags; ++ int chunk_id = ++ flash_block * dev->param.chunks_per_block; ++ ++ u8 *buffer = yaffs_get_temp_buffer(dev); ++ ++ memset(buffer, 0xff, dev->data_bytes_per_chunk); ++ memset(&tags, 0, sizeof(tags)); ++ tags.seq_number = YAFFS_SEQUENCE_BAD_BLOCK; ++ if (dev->tagger.write_chunk_tags_fn(dev, chunk_id - ++ dev->chunk_offset, ++ buffer, ++ &tags) != YAFFS_OK) ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: Failed to write bad block marker to block %d", ++ flash_block); ++ ++ yaffs_release_temp_buffer(dev, buffer); ++ } ++ } ++ ++ bi->block_state = YAFFS_BLOCK_STATE_DEAD; ++ bi->gc_prioritise = 0; ++ bi->needs_retiring = 0; ++ ++ dev->n_retired_blocks++; ++} ++ ++/*---------------- Name handling functions ------------*/ ++ ++static u16 yaffs_calc_name_sum(const YCHAR *name) ++{ ++ u16 sum = 0; ++ u16 i = 1; ++ ++ if (!name) ++ return 0; ++ ++ while ((*name) && i < (YAFFS_MAX_NAME_LENGTH / 2)) { ++ ++ /* 0x1f mask is case insensitive */ ++ sum += ((*name) & 0x1f) * i; ++ i++; ++ name++; ++ } ++ return sum; ++} ++ ++ ++void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name) ++{ ++ memset(obj->short_name, 0, sizeof(obj->short_name)); ++ ++ if (name && !name[0]) { ++ yaffs_fix_null_name(obj, obj->short_name, ++ YAFFS_SHORT_NAME_LENGTH); ++ name = obj->short_name; ++ } else if (name && ++ strnlen(name, YAFFS_SHORT_NAME_LENGTH + 1) <= ++ YAFFS_SHORT_NAME_LENGTH) { ++ strcpy(obj->short_name, name); ++ } ++ ++ obj->sum = yaffs_calc_name_sum(name); ++} ++ ++void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, ++ const struct yaffs_obj_hdr *oh) ++{ ++#ifdef CONFIG_YAFFS_AUTO_UNICODE ++ YCHAR tmp_name[YAFFS_MAX_NAME_LENGTH + 1]; ++ memset(tmp_name, 0, sizeof(tmp_name)); ++ yaffs_load_name_from_oh(obj->my_dev, tmp_name, oh->name, ++ YAFFS_MAX_NAME_LENGTH + 1); ++ yaffs_set_obj_name(obj, tmp_name); ++#else ++ yaffs_set_obj_name(obj, oh->name); ++#endif ++} ++ ++loff_t yaffs_max_file_size(struct yaffs_dev *dev) ++{ ++ if(sizeof(loff_t) < 8) ++ return YAFFS_MAX_FILE_SIZE_32; ++ else ++ return ((loff_t) YAFFS_MAX_CHUNK_ID) * dev->data_bytes_per_chunk; ++} ++ ++/*-------------------- TNODES ------------------- ++ ++ * List of spare tnodes ++ * The list is hooked together using the first pointer ++ * in the tnode. ++ */ ++ ++struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev) ++{ ++ struct yaffs_tnode *tn = yaffs_alloc_raw_tnode(dev); ++ ++ if (tn) { ++ memset(tn, 0, dev->tnode_size); ++ dev->n_tnodes++; ++ } ++ ++ dev->checkpoint_blocks_required = 0; /* force recalculation */ ++ ++ return tn; ++} ++ ++/* FreeTnode frees up a tnode and puts it back on the free list */ ++static void yaffs_free_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) ++{ ++ yaffs_free_raw_tnode(dev, tn); ++ dev->n_tnodes--; ++ dev->checkpoint_blocks_required = 0; /* force recalculation */ ++} ++ ++static void yaffs_deinit_tnodes_and_objs(struct yaffs_dev *dev) ++{ ++ yaffs_deinit_raw_tnodes_and_objs(dev); ++ dev->n_obj = 0; ++ dev->n_tnodes = 0; ++} ++ ++static void yaffs_load_tnode_0(struct yaffs_dev *dev, struct yaffs_tnode *tn, ++ unsigned pos, unsigned val) ++{ ++ u32 *map = (u32 *) tn; ++ u32 bit_in_map; ++ u32 bit_in_word; ++ u32 word_in_map; ++ u32 mask; ++ ++ pos &= YAFFS_TNODES_LEVEL0_MASK; ++ val >>= dev->chunk_grp_bits; ++ ++ bit_in_map = pos * dev->tnode_width; ++ word_in_map = bit_in_map / 32; ++ bit_in_word = bit_in_map & (32 - 1); ++ ++ mask = dev->tnode_mask << bit_in_word; ++ ++ map[word_in_map] &= ~mask; ++ map[word_in_map] |= (mask & (val << bit_in_word)); ++ ++ if (dev->tnode_width > (32 - bit_in_word)) { ++ bit_in_word = (32 - bit_in_word); ++ word_in_map++; ++ mask = ++ dev->tnode_mask >> bit_in_word; ++ map[word_in_map] &= ~mask; ++ map[word_in_map] |= (mask & (val >> bit_in_word)); ++ } ++} ++ ++u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, ++ unsigned pos) ++{ ++ u32 *map = (u32 *) tn; ++ u32 bit_in_map; ++ u32 bit_in_word; ++ u32 word_in_map; ++ u32 val; ++ ++ pos &= YAFFS_TNODES_LEVEL0_MASK; ++ ++ bit_in_map = pos * dev->tnode_width; ++ word_in_map = bit_in_map / 32; ++ bit_in_word = bit_in_map & (32 - 1); ++ ++ val = map[word_in_map] >> bit_in_word; ++ ++ if (dev->tnode_width > (32 - bit_in_word)) { ++ bit_in_word = (32 - bit_in_word); ++ word_in_map++; ++ val |= (map[word_in_map] << bit_in_word); ++ } ++ ++ val &= dev->tnode_mask; ++ val <<= dev->chunk_grp_bits; ++ ++ return val; ++} ++ ++/* ------------------- End of individual tnode manipulation -----------------*/ ++ ++/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------ ++ * The look up tree is represented by the top tnode and the number of top_level ++ * in the tree. 0 means only the level 0 tnode is in the tree. ++ */ ++ ++/* FindLevel0Tnode finds the level 0 tnode, if one exists. */ ++struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, ++ struct yaffs_file_var *file_struct, ++ u32 chunk_id) ++{ ++ struct yaffs_tnode *tn = file_struct->top; ++ u32 i; ++ int required_depth; ++ int level = file_struct->top_level; ++ ++ (void) dev; ++ ++ /* Check sane level and chunk Id */ ++ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) ++ return NULL; ++ ++ if (chunk_id > YAFFS_MAX_CHUNK_ID) ++ return NULL; ++ ++ /* First check we're tall enough (ie enough top_level) */ ++ ++ i = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; ++ required_depth = 0; ++ while (i) { ++ i >>= YAFFS_TNODES_INTERNAL_BITS; ++ required_depth++; ++ } ++ ++ if (required_depth > file_struct->top_level) ++ return NULL; /* Not tall enough, so we can't find it */ ++ ++ /* Traverse down to level 0 */ ++ while (level > 0 && tn) { ++ tn = tn->internal[(chunk_id >> ++ (YAFFS_TNODES_LEVEL0_BITS + ++ (level - 1) * ++ YAFFS_TNODES_INTERNAL_BITS)) & ++ YAFFS_TNODES_INTERNAL_MASK]; ++ level--; ++ } ++ ++ return tn; ++} ++ ++/* add_find_tnode_0 finds the level 0 tnode if it exists, ++ * otherwise first expands the tree. ++ * This happens in two steps: ++ * 1. If the tree isn't tall enough, then make it taller. ++ * 2. Scan down the tree towards the level 0 tnode adding tnodes if required. ++ * ++ * Used when modifying the tree. ++ * ++ * If the tn argument is NULL, then a fresh tnode will be added otherwise the ++ * specified tn will be plugged into the ttree. ++ */ ++ ++struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, ++ struct yaffs_file_var *file_struct, ++ u32 chunk_id, ++ struct yaffs_tnode *passed_tn) ++{ ++ int required_depth; ++ int i; ++ int l; ++ struct yaffs_tnode *tn; ++ u32 x; ++ ++ /* Check sane level and page Id */ ++ if (file_struct->top_level < 0 || ++ file_struct->top_level > YAFFS_TNODES_MAX_LEVEL) ++ return NULL; ++ ++ if (chunk_id > YAFFS_MAX_CHUNK_ID) ++ return NULL; ++ ++ /* First check we're tall enough (ie enough top_level) */ ++ ++ x = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; ++ required_depth = 0; ++ while (x) { ++ x >>= YAFFS_TNODES_INTERNAL_BITS; ++ required_depth++; ++ } ++ ++ if (required_depth > file_struct->top_level) { ++ /* Not tall enough, gotta make the tree taller */ ++ for (i = file_struct->top_level; i < required_depth; i++) { ++ ++ tn = yaffs_get_tnode(dev); ++ ++ if (tn) { ++ tn->internal[0] = file_struct->top; ++ file_struct->top = tn; ++ file_struct->top_level++; ++ } else { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs: no more tnodes"); ++ return NULL; ++ } ++ } ++ } ++ ++ /* Traverse down to level 0, adding anything we need */ ++ ++ l = file_struct->top_level; ++ tn = file_struct->top; ++ ++ if (l > 0) { ++ while (l > 0 && tn) { ++ x = (chunk_id >> ++ (YAFFS_TNODES_LEVEL0_BITS + ++ (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) & ++ YAFFS_TNODES_INTERNAL_MASK; ++ ++ if ((l > 1) && !tn->internal[x]) { ++ /* Add missing non-level-zero tnode */ ++ tn->internal[x] = yaffs_get_tnode(dev); ++ if (!tn->internal[x]) ++ return NULL; ++ } else if (l == 1) { ++ /* Looking from level 1 at level 0 */ ++ if (passed_tn) { ++ /* If we already have one, release it */ ++ if (tn->internal[x]) ++ yaffs_free_tnode(dev, ++ tn->internal[x]); ++ tn->internal[x] = passed_tn; ++ ++ } else if (!tn->internal[x]) { ++ /* Don't have one, none passed in */ ++ tn->internal[x] = yaffs_get_tnode(dev); ++ if (!tn->internal[x]) ++ return NULL; ++ } ++ } ++ ++ tn = tn->internal[x]; ++ l--; ++ } ++ } else { ++ /* top is level 0 */ ++ if (passed_tn) { ++ memcpy(tn, passed_tn, ++ (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8); ++ yaffs_free_tnode(dev, passed_tn); ++ } ++ } ++ ++ return tn; ++} ++ ++static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, ++ int chunk_obj) ++{ ++ return (tags->chunk_id == chunk_obj && ++ tags->obj_id == obj_id && ++ !tags->is_deleted) ? 1 : 0; ++ ++} ++ ++static int yaffs_find_chunk_in_group(struct yaffs_dev *dev, int the_chunk, ++ struct yaffs_ext_tags *tags, int obj_id, ++ int inode_chunk) ++{ ++ int j; ++ ++ for (j = 0; the_chunk && j < dev->chunk_grp_size; j++) { ++ if (yaffs_check_chunk_bit ++ (dev, the_chunk / dev->param.chunks_per_block, ++ the_chunk % dev->param.chunks_per_block)) { ++ ++ if (dev->chunk_grp_size == 1) ++ return the_chunk; ++ else { ++ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, ++ tags); ++ if (yaffs_tags_match(tags, ++ obj_id, inode_chunk)) { ++ /* found it; */ ++ return the_chunk; ++ } ++ } ++ } ++ the_chunk++; ++ } ++ return -1; ++} ++ ++int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, ++ struct yaffs_ext_tags *tags) ++{ ++ /*Get the Tnode, then get the level 0 offset chunk offset */ ++ struct yaffs_tnode *tn; ++ int the_chunk = -1; ++ struct yaffs_ext_tags local_tags; ++ int ret_val = -1; ++ struct yaffs_dev *dev = in->my_dev; ++ ++ if (!tags) { ++ /* Passed a NULL, so use our own tags space */ ++ tags = &local_tags; ++ } ++ ++ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); ++ ++ if (!tn) ++ return ret_val; ++ ++ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); ++ ++ ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, ++ inode_chunk); ++ return ret_val; ++} ++ ++static int yaffs_find_del_file_chunk(struct yaffs_obj *in, int inode_chunk, ++ struct yaffs_ext_tags *tags) ++{ ++ /* Get the Tnode, then get the level 0 offset chunk offset */ ++ struct yaffs_tnode *tn; ++ int the_chunk = -1; ++ struct yaffs_ext_tags local_tags; ++ struct yaffs_dev *dev = in->my_dev; ++ int ret_val = -1; ++ ++ if (!tags) { ++ /* Passed a NULL, so use our own tags space */ ++ tags = &local_tags; ++ } ++ ++ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); ++ ++ if (!tn) ++ return ret_val; ++ ++ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); ++ ++ ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, ++ inode_chunk); ++ ++ /* Delete the entry in the filestructure (if found) */ ++ if (ret_val != -1) ++ yaffs_load_tnode_0(dev, tn, inode_chunk, 0); ++ ++ return ret_val; ++} ++ ++int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, ++ int nand_chunk, int in_scan) ++{ ++ /* NB in_scan is zero unless scanning. ++ * For forward scanning, in_scan is > 0; ++ * for backward scanning in_scan is < 0 ++ * ++ * nand_chunk = 0 is a dummy insert to make sure the tnodes are there. ++ */ ++ ++ struct yaffs_tnode *tn; ++ struct yaffs_dev *dev = in->my_dev; ++ int existing_cunk; ++ struct yaffs_ext_tags existing_tags; ++ struct yaffs_ext_tags new_tags; ++ unsigned existing_serial, new_serial; ++ ++ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) { ++ /* Just ignore an attempt at putting a chunk into a non-file ++ * during scanning. ++ * If it is not during Scanning then something went wrong! ++ */ ++ if (!in_scan) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy:attempt to put data chunk into a non-file" ++ ); ++ BUG(); ++ } ++ ++ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); ++ return YAFFS_OK; ++ } ++ ++ tn = yaffs_add_find_tnode_0(dev, ++ &in->variant.file_variant, ++ inode_chunk, NULL); ++ if (!tn) ++ return YAFFS_FAIL; ++ ++ if (!nand_chunk) ++ /* Dummy insert, bail now */ ++ return YAFFS_OK; ++ ++ existing_cunk = yaffs_get_group_base(dev, tn, inode_chunk); ++ ++ if (in_scan != 0) { ++ /* If we're scanning then we need to test for duplicates ++ * NB This does not need to be efficient since it should only ++ * happen when the power fails during a write, then only one ++ * chunk should ever be affected. ++ * ++ * Correction for YAFFS2: This could happen quite a lot and we ++ * need to think about efficiency! TODO ++ * Update: For backward scanning we don't need to re-read tags ++ * so this is quite cheap. ++ */ ++ ++ if (existing_cunk > 0) { ++ /* NB Right now existing chunk will not be real ++ * chunk_id if the chunk group size > 1 ++ * thus we have to do a FindChunkInFile to get the ++ * real chunk id. ++ * ++ * We have a duplicate now we need to decide which ++ * one to use: ++ * ++ * Backwards scanning YAFFS2: The old one is what ++ * we use, dump the new one. ++ * YAFFS1: Get both sets of tags and compare serial ++ * numbers. ++ */ ++ ++ if (in_scan > 0) { ++ /* Only do this for forward scanning */ ++ yaffs_rd_chunk_tags_nand(dev, ++ nand_chunk, ++ NULL, &new_tags); ++ ++ /* Do a proper find */ ++ existing_cunk = ++ yaffs_find_chunk_in_file(in, inode_chunk, ++ &existing_tags); ++ } ++ ++ if (existing_cunk <= 0) { ++ /*Hoosterman - how did this happen? */ ++ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: existing chunk < 0 in scan" ++ ); ++ ++ } ++ ++ /* NB The deleted flags should be false, otherwise ++ * the chunks will not be loaded during a scan ++ */ ++ ++ if (in_scan > 0) { ++ new_serial = new_tags.serial_number; ++ existing_serial = existing_tags.serial_number; ++ } ++ ++ if ((in_scan > 0) && ++ (existing_cunk <= 0 || ++ ((existing_serial + 1) & 3) == new_serial)) { ++ /* Forward scanning. ++ * Use new ++ * Delete the old one and drop through to ++ * update the tnode ++ */ ++ yaffs_chunk_del(dev, existing_cunk, 1, ++ __LINE__); ++ } else { ++ /* Backward scanning or we want to use the ++ * existing one ++ * Delete the new one and return early so that ++ * the tnode isn't changed ++ */ ++ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); ++ return YAFFS_OK; ++ } ++ } ++ ++ } ++ ++ if (existing_cunk == 0) ++ in->n_data_chunks++; ++ ++ yaffs_load_tnode_0(dev, tn, inode_chunk, nand_chunk); ++ ++ return YAFFS_OK; ++} ++ ++static void yaffs_soft_del_chunk(struct yaffs_dev *dev, int chunk) ++{ ++ struct yaffs_block_info *the_block; ++ unsigned block_no; ++ ++ yaffs_trace(YAFFS_TRACE_DELETION, "soft delete chunk %d", chunk); ++ ++ block_no = chunk / dev->param.chunks_per_block; ++ the_block = yaffs_get_block_info(dev, block_no); ++ if (the_block) { ++ the_block->soft_del_pages++; ++ dev->n_free_chunks++; ++ yaffs2_update_oldest_dirty_seq(dev, block_no, the_block); ++ } ++} ++ ++/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all ++ * the chunks in the file. ++ * All soft deleting does is increment the block's softdelete count and pulls ++ * the chunk out of the tnode. ++ * Thus, essentially this is the same as DeleteWorker except that the chunks ++ * are soft deleted. ++ */ ++ ++static int yaffs_soft_del_worker(struct yaffs_obj *in, struct yaffs_tnode *tn, ++ u32 level, int chunk_offset) ++{ ++ int i; ++ int the_chunk; ++ int all_done = 1; ++ struct yaffs_dev *dev = in->my_dev; ++ ++ if (!tn) ++ return 1; ++ ++ if (level > 0) { ++ for (i = YAFFS_NTNODES_INTERNAL - 1; ++ all_done && i >= 0; ++ i--) { ++ if (tn->internal[i]) { ++ all_done = ++ yaffs_soft_del_worker(in, ++ tn->internal[i], ++ level - 1, ++ (chunk_offset << ++ YAFFS_TNODES_INTERNAL_BITS) ++ + i); ++ if (all_done) { ++ yaffs_free_tnode(dev, ++ tn->internal[i]); ++ tn->internal[i] = NULL; ++ } else { ++ /* Can this happen? */ ++ } ++ } ++ } ++ return (all_done) ? 1 : 0; ++ } ++ ++ /* level 0 */ ++ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) { ++ the_chunk = yaffs_get_group_base(dev, tn, i); ++ if (the_chunk) { ++ yaffs_soft_del_chunk(dev, the_chunk); ++ yaffs_load_tnode_0(dev, tn, i, 0); ++ } ++ } ++ return 1; ++} ++ ++static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev = obj->my_dev; ++ struct yaffs_obj *parent; ++ ++ yaffs_verify_obj_in_dir(obj); ++ parent = obj->parent; ++ ++ yaffs_verify_dir(parent); ++ ++ if (dev && dev->param.remove_obj_fn) ++ dev->param.remove_obj_fn(obj); ++ ++ list_del_init(&obj->siblings); ++ obj->parent = NULL; ++ ++ yaffs_verify_dir(parent); ++} ++ ++void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj) ++{ ++ if (!directory) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "tragedy: Trying to add an object to a null pointer directory" ++ ); ++ BUG(); ++ return; ++ } ++ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "tragedy: Trying to add an object to a non-directory" ++ ); ++ BUG(); ++ } ++ ++ if (obj->siblings.prev == NULL) { ++ /* Not initialised */ ++ BUG(); ++ } ++ ++ yaffs_verify_dir(directory); ++ ++ yaffs_remove_obj_from_dir(obj); ++ ++ /* Now add it */ ++ list_add(&obj->siblings, &directory->variant.dir_variant.children); ++ obj->parent = directory; ++ ++ if (directory == obj->my_dev->unlinked_dir ++ || directory == obj->my_dev->del_dir) { ++ obj->unlinked = 1; ++ obj->my_dev->n_unlinked_files++; ++ obj->rename_allowed = 0; ++ } ++ ++ yaffs_verify_dir(directory); ++ yaffs_verify_obj_in_dir(obj); ++} ++ ++static int yaffs_change_obj_name(struct yaffs_obj *obj, ++ struct yaffs_obj *new_dir, ++ const YCHAR *new_name, int force, int shadows) ++{ ++ int unlink_op; ++ int del_op; ++ struct yaffs_obj *existing_target; ++ ++ if (new_dir == NULL) ++ new_dir = obj->parent; /* use the old directory */ ++ ++ if (new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "tragedy: yaffs_change_obj_name: new_dir is not a directory" ++ ); ++ BUG(); ++ } ++ ++ unlink_op = (new_dir == obj->my_dev->unlinked_dir); ++ del_op = (new_dir == obj->my_dev->del_dir); ++ ++ existing_target = yaffs_find_by_name(new_dir, new_name); ++ ++ /* If the object is a file going into the unlinked directory, ++ * then it is OK to just stuff it in since duplicate names are OK. ++ * else only proceed if the new name does not exist and we're putting ++ * it into a directory. ++ */ ++ if (!(unlink_op || del_op || force || ++ shadows > 0 || !existing_target) || ++ new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) ++ return YAFFS_FAIL; ++ ++ yaffs_set_obj_name(obj, new_name); ++ obj->dirty = 1; ++ yaffs_add_obj_to_dir(new_dir, obj); ++ ++ if (unlink_op) ++ obj->unlinked = 1; ++ ++ /* If it is a deletion then we mark it as a shrink for gc */ ++ if (yaffs_update_oh(obj, new_name, 0, del_op, shadows, NULL) >= 0) ++ return YAFFS_OK; ++ ++ return YAFFS_FAIL; ++} ++ ++/*------------------------ Short Operations Cache ------------------------------ ++ * In many situations where there is no high level buffering a lot of ++ * reads might be short sequential reads, and a lot of writes may be short ++ * sequential writes. eg. scanning/writing a jpeg file. ++ * In these cases, a short read/write cache can provide a huge perfomance ++ * benefit with dumb-as-a-rock code. ++ * In Linux, the page cache provides read buffering and the short op cache ++ * provides write buffering. ++ * ++ * There are a small number (~10) of cache chunks per device so that we don't ++ * need a very intelligent search. ++ */ ++ ++static int yaffs_obj_cache_dirty(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev = obj->my_dev; ++ int i; ++ struct yaffs_cache *cache; ++ int n_caches = obj->my_dev->param.n_caches; ++ ++ for (i = 0; i < n_caches; i++) { ++ cache = &dev->cache[i]; ++ if (cache->object == obj && cache->dirty) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void yaffs_flush_file_cache(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev = obj->my_dev; ++ int lowest = -99; /* Stop compiler whining. */ ++ int i; ++ struct yaffs_cache *cache; ++ int chunk_written = 0; ++ int n_caches = obj->my_dev->param.n_caches; ++ ++ if (n_caches < 1) ++ return; ++ do { ++ cache = NULL; ++ ++ /* Find the lowest dirty chunk for this object */ ++ for (i = 0; i < n_caches; i++) { ++ if (dev->cache[i].object == obj && ++ dev->cache[i].dirty) { ++ if (!cache || ++ dev->cache[i].chunk_id < lowest) { ++ cache = &dev->cache[i]; ++ lowest = cache->chunk_id; ++ } ++ } ++ } ++ ++ if (cache && !cache->locked) { ++ /* Write it out and free it up */ ++ chunk_written = ++ yaffs_wr_data_obj(cache->object, ++ cache->chunk_id, ++ cache->data, ++ cache->n_bytes, 1); ++ cache->dirty = 0; ++ cache->object = NULL; ++ } ++ } while (cache && chunk_written > 0); ++ ++ if (cache) ++ /* Hoosterman, disk full while writing cache out. */ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: no space during cache write"); ++} ++ ++/*yaffs_flush_whole_cache(dev) ++ * ++ * ++ */ ++ ++void yaffs_flush_whole_cache(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj; ++ int n_caches = dev->param.n_caches; ++ int i; ++ ++ /* Find a dirty object in the cache and flush it... ++ * until there are no further dirty objects. ++ */ ++ do { ++ obj = NULL; ++ for (i = 0; i < n_caches && !obj; i++) { ++ if (dev->cache[i].object && dev->cache[i].dirty) ++ obj = dev->cache[i].object; ++ } ++ if (obj) ++ yaffs_flush_file_cache(obj); ++ } while (obj); ++ ++} ++ ++/* Grab us a cache chunk for use. ++ * First look for an empty one. ++ * Then look for the least recently used non-dirty one. ++ * Then look for the least recently used dirty one...., flush and look again. ++ */ ++static struct yaffs_cache *yaffs_grab_chunk_worker(struct yaffs_dev *dev) ++{ ++ int i; ++ ++ if (dev->param.n_caches > 0) { ++ for (i = 0; i < dev->param.n_caches; i++) { ++ if (!dev->cache[i].object) ++ return &dev->cache[i]; ++ } ++ } ++ return NULL; ++} ++ ++static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) ++{ ++ struct yaffs_cache *cache; ++ struct yaffs_obj *the_obj; ++ int usage; ++ int i; ++ int pushout; ++ ++ if (dev->param.n_caches < 1) ++ return NULL; ++ ++ /* Try find a non-dirty one... */ ++ ++ cache = yaffs_grab_chunk_worker(dev); ++ ++ if (!cache) { ++ /* They were all dirty, find the LRU object and flush ++ * its cache, then find again. ++ * NB what's here is not very accurate, ++ * we actually flush the object with the LRU chunk. ++ */ ++ ++ /* With locking we can't assume we can use entry zero, ++ * Set the_obj to a valid pointer for Coverity. */ ++ the_obj = dev->cache[0].object; ++ usage = -1; ++ cache = NULL; ++ pushout = -1; ++ ++ for (i = 0; i < dev->param.n_caches; i++) { ++ if (dev->cache[i].object && ++ !dev->cache[i].locked && ++ (dev->cache[i].last_use < usage || ++ !cache)) { ++ usage = dev->cache[i].last_use; ++ the_obj = dev->cache[i].object; ++ cache = &dev->cache[i]; ++ pushout = i; ++ } ++ } ++ ++ if (!cache || cache->dirty) { ++ /* Flush and try again */ ++ yaffs_flush_file_cache(the_obj); ++ cache = yaffs_grab_chunk_worker(dev); ++ } ++ } ++ return cache; ++} ++ ++/* Find a cached chunk */ ++static struct yaffs_cache *yaffs_find_chunk_cache(const struct yaffs_obj *obj, ++ int chunk_id) ++{ ++ struct yaffs_dev *dev = obj->my_dev; ++ int i; ++ ++ if (dev->param.n_caches < 1) ++ return NULL; ++ ++ for (i = 0; i < dev->param.n_caches; i++) { ++ if (dev->cache[i].object == obj && ++ dev->cache[i].chunk_id == chunk_id) { ++ dev->cache_hits++; ++ ++ return &dev->cache[i]; ++ } ++ } ++ return NULL; ++} ++ ++/* Mark the chunk for the least recently used algorithym */ ++static void yaffs_use_cache(struct yaffs_dev *dev, struct yaffs_cache *cache, ++ int is_write) ++{ ++ int i; ++ ++ if (dev->param.n_caches < 1) ++ return; ++ ++ if (dev->cache_last_use < 0 || ++ dev->cache_last_use > 100000000) { ++ /* Reset the cache usages */ ++ for (i = 1; i < dev->param.n_caches; i++) ++ dev->cache[i].last_use = 0; ++ ++ dev->cache_last_use = 0; ++ } ++ dev->cache_last_use++; ++ cache->last_use = dev->cache_last_use; ++ ++ if (is_write) ++ cache->dirty = 1; ++} ++ ++/* Invalidate a single cache page. ++ * Do this when a whole page gets written, ++ * ie the short cache for this page is no longer valid. ++ */ ++static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, int chunk_id) ++{ ++ struct yaffs_cache *cache; ++ ++ if (object->my_dev->param.n_caches > 0) { ++ cache = yaffs_find_chunk_cache(object, chunk_id); ++ ++ if (cache) ++ cache->object = NULL; ++ } ++} ++ ++/* Invalidate all the cache pages associated with this object ++ * Do this whenever ther file is deleted or resized. ++ */ ++static void yaffs_invalidate_whole_cache(struct yaffs_obj *in) ++{ ++ int i; ++ struct yaffs_dev *dev = in->my_dev; ++ ++ if (dev->param.n_caches > 0) { ++ /* Invalidate it. */ ++ for (i = 0; i < dev->param.n_caches; i++) { ++ if (dev->cache[i].object == in) ++ dev->cache[i].object = NULL; ++ } ++ } ++} ++ ++static void yaffs_unhash_obj(struct yaffs_obj *obj) ++{ ++ int bucket; ++ struct yaffs_dev *dev = obj->my_dev; ++ ++ /* If it is still linked into the bucket list, free from the list */ ++ if (!list_empty(&obj->hash_link)) { ++ list_del_init(&obj->hash_link); ++ bucket = yaffs_hash_fn(obj->obj_id); ++ dev->obj_bucket[bucket].count--; ++ } ++} ++ ++/* FreeObject frees up a Object and puts it back on the free list */ ++static void yaffs_free_obj(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev; ++ ++ if (!obj) { ++ BUG(); ++ return; ++ } ++ dev = obj->my_dev; ++ yaffs_trace(YAFFS_TRACE_OS, "FreeObject %p inode %p", ++ obj, obj->my_inode); ++ if (obj->parent) ++ BUG(); ++ if (!list_empty(&obj->siblings)) ++ BUG(); ++ ++ if (obj->my_inode) { ++ /* We're still hooked up to a cached inode. ++ * Don't delete now, but mark for later deletion ++ */ ++ obj->defered_free = 1; ++ return; ++ } ++ ++ yaffs_unhash_obj(obj); ++ ++ yaffs_free_raw_obj(dev, obj); ++ dev->n_obj--; ++ dev->checkpoint_blocks_required = 0; /* force recalculation */ ++} ++ ++void yaffs_handle_defered_free(struct yaffs_obj *obj) ++{ ++ if (obj->defered_free) ++ yaffs_free_obj(obj); ++} ++ ++static int yaffs_generic_obj_del(struct yaffs_obj *in) ++{ ++ /* Iinvalidate the file's data in the cache, without flushing. */ ++ yaffs_invalidate_whole_cache(in); ++ ++ if (in->my_dev->param.is_yaffs2 && in->parent != in->my_dev->del_dir) { ++ /* Move to unlinked directory so we have a deletion record */ ++ yaffs_change_obj_name(in, in->my_dev->del_dir, _Y("deleted"), 0, ++ 0); ++ } ++ ++ yaffs_remove_obj_from_dir(in); ++ yaffs_chunk_del(in->my_dev, in->hdr_chunk, 1, __LINE__); ++ in->hdr_chunk = 0; ++ ++ yaffs_free_obj(in); ++ return YAFFS_OK; ++ ++} ++ ++static void yaffs_soft_del_file(struct yaffs_obj *obj) ++{ ++ if (!obj->deleted || ++ obj->variant_type != YAFFS_OBJECT_TYPE_FILE || ++ obj->soft_del) ++ return; ++ ++ if (obj->n_data_chunks <= 0) { ++ /* Empty file with no duplicate object headers, ++ * just delete it immediately */ ++ yaffs_free_tnode(obj->my_dev, obj->variant.file_variant.top); ++ obj->variant.file_variant.top = NULL; ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "yaffs: Deleting empty file %d", ++ obj->obj_id); ++ yaffs_generic_obj_del(obj); ++ } else { ++ yaffs_soft_del_worker(obj, ++ obj->variant.file_variant.top, ++ obj->variant. ++ file_variant.top_level, 0); ++ obj->soft_del = 1; ++ } ++} ++ ++/* Pruning removes any part of the file structure tree that is beyond the ++ * bounds of the file (ie that does not point to chunks). ++ * ++ * A file should only get pruned when its size is reduced. ++ * ++ * Before pruning, the chunks must be pulled from the tree and the ++ * level 0 tnode entries must be zeroed out. ++ * Could also use this for file deletion, but that's probably better handled ++ * by a special case. ++ * ++ * This function is recursive. For levels > 0 the function is called again on ++ * any sub-tree. For level == 0 we just check if the sub-tree has data. ++ * If there is no data in a subtree then it is pruned. ++ */ ++ ++static struct yaffs_tnode *yaffs_prune_worker(struct yaffs_dev *dev, ++ struct yaffs_tnode *tn, u32 level, ++ int del0) ++{ ++ int i; ++ int has_data; ++ ++ if (!tn) ++ return tn; ++ ++ has_data = 0; ++ ++ if (level > 0) { ++ for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) { ++ if (tn->internal[i]) { ++ tn->internal[i] = ++ yaffs_prune_worker(dev, ++ tn->internal[i], ++ level - 1, ++ (i == 0) ? del0 : 1); ++ } ++ ++ if (tn->internal[i]) ++ has_data++; ++ } ++ } else { ++ int tnode_size_u32 = dev->tnode_size / sizeof(u32); ++ u32 *map = (u32 *) tn; ++ ++ for (i = 0; !has_data && i < tnode_size_u32; i++) { ++ if (map[i]) ++ has_data++; ++ } ++ } ++ ++ if (has_data == 0 && del0) { ++ /* Free and return NULL */ ++ yaffs_free_tnode(dev, tn); ++ tn = NULL; ++ } ++ return tn; ++} ++ ++static int yaffs_prune_tree(struct yaffs_dev *dev, ++ struct yaffs_file_var *file_struct) ++{ ++ int i; ++ int has_data; ++ int done = 0; ++ struct yaffs_tnode *tn; ++ ++ if (file_struct->top_level < 1) ++ return YAFFS_OK; ++ ++ file_struct->top = ++ yaffs_prune_worker(dev, file_struct->top, file_struct->top_level, 0); ++ ++ /* Now we have a tree with all the non-zero branches NULL but ++ * the height is the same as it was. ++ * Let's see if we can trim internal tnodes to shorten the tree. ++ * We can do this if only the 0th element in the tnode is in use ++ * (ie all the non-zero are NULL) ++ */ ++ ++ while (file_struct->top_level && !done) { ++ tn = file_struct->top; ++ ++ has_data = 0; ++ for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) { ++ if (tn->internal[i]) ++ has_data++; ++ } ++ ++ if (!has_data) { ++ file_struct->top = tn->internal[0]; ++ file_struct->top_level--; ++ yaffs_free_tnode(dev, tn); ++ } else { ++ done = 1; ++ } ++ } ++ ++ return YAFFS_OK; ++} ++ ++/*-------------------- End of File Structure functions.-------------------*/ ++ ++/* alloc_empty_obj gets us a clean Object.*/ ++static struct yaffs_obj *yaffs_alloc_empty_obj(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj = yaffs_alloc_raw_obj(dev); ++ ++ if (!obj) ++ return obj; ++ ++ dev->n_obj++; ++ ++ /* Now sweeten it up... */ ++ ++ memset(obj, 0, sizeof(struct yaffs_obj)); ++ obj->being_created = 1; ++ ++ obj->my_dev = dev; ++ obj->hdr_chunk = 0; ++ obj->variant_type = YAFFS_OBJECT_TYPE_UNKNOWN; ++ INIT_LIST_HEAD(&(obj->hard_links)); ++ INIT_LIST_HEAD(&(obj->hash_link)); ++ INIT_LIST_HEAD(&obj->siblings); ++ ++ /* Now make the directory sane */ ++ if (dev->root_dir) { ++ obj->parent = dev->root_dir; ++ list_add(&(obj->siblings), ++ &dev->root_dir->variant.dir_variant.children); ++ } ++ ++ /* Add it to the lost and found directory. ++ * NB Can't put root or lost-n-found in lost-n-found so ++ * check if lost-n-found exists first ++ */ ++ if (dev->lost_n_found) ++ yaffs_add_obj_to_dir(dev->lost_n_found, obj); ++ ++ obj->being_created = 0; ++ ++ dev->checkpoint_blocks_required = 0; /* force recalculation */ ++ ++ return obj; ++} ++ ++static int yaffs_find_nice_bucket(struct yaffs_dev *dev) ++{ ++ int i; ++ int l = 999; ++ int lowest = 999999; ++ ++ /* Search for the shortest list or one that ++ * isn't too long. ++ */ ++ ++ for (i = 0; i < 10 && lowest > 4; i++) { ++ dev->bucket_finder++; ++ dev->bucket_finder %= YAFFS_NOBJECT_BUCKETS; ++ if (dev->obj_bucket[dev->bucket_finder].count < lowest) { ++ lowest = dev->obj_bucket[dev->bucket_finder].count; ++ l = dev->bucket_finder; ++ } ++ } ++ ++ return l; ++} ++ ++static int yaffs_new_obj_id(struct yaffs_dev *dev) ++{ ++ int bucket = yaffs_find_nice_bucket(dev); ++ int found = 0; ++ struct list_head *i; ++ u32 n = (u32) bucket; ++ ++ /* Now find an object value that has not already been taken ++ * by scanning the list. ++ */ ++ ++ while (!found) { ++ found = 1; ++ n += YAFFS_NOBJECT_BUCKETS; ++ if (1 || dev->obj_bucket[bucket].count > 0) { ++ list_for_each(i, &dev->obj_bucket[bucket].list) { ++ /* If there is already one in the list */ ++ if (i && list_entry(i, struct yaffs_obj, ++ hash_link)->obj_id == n) { ++ found = 0; ++ } ++ } ++ } ++ } ++ return n; ++} ++ ++static void yaffs_hash_obj(struct yaffs_obj *in) ++{ ++ int bucket = yaffs_hash_fn(in->obj_id); ++ struct yaffs_dev *dev = in->my_dev; ++ ++ list_add(&in->hash_link, &dev->obj_bucket[bucket].list); ++ dev->obj_bucket[bucket].count++; ++} ++ ++struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number) ++{ ++ int bucket = yaffs_hash_fn(number); ++ struct list_head *i; ++ struct yaffs_obj *in; ++ ++ list_for_each(i, &dev->obj_bucket[bucket].list) { ++ /* Look if it is in the list */ ++ in = list_entry(i, struct yaffs_obj, hash_link); ++ if (in->obj_id == number) { ++ /* Don't show if it is defered free */ ++ if (in->defered_free) ++ return NULL; ++ return in; ++ } ++ } ++ ++ return NULL; ++} ++ ++static struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, ++ enum yaffs_obj_type type) ++{ ++ struct yaffs_obj *the_obj = NULL; ++ struct yaffs_tnode *tn = NULL; ++ ++ if (number < 0) ++ number = yaffs_new_obj_id(dev); ++ ++ if (type == YAFFS_OBJECT_TYPE_FILE) { ++ tn = yaffs_get_tnode(dev); ++ if (!tn) ++ return NULL; ++ } ++ ++ the_obj = yaffs_alloc_empty_obj(dev); ++ if (!the_obj) { ++ if (tn) ++ yaffs_free_tnode(dev, tn); ++ return NULL; ++ } ++ ++ the_obj->fake = 0; ++ the_obj->rename_allowed = 1; ++ the_obj->unlink_allowed = 1; ++ the_obj->obj_id = number; ++ yaffs_hash_obj(the_obj); ++ the_obj->variant_type = type; ++ yaffs_load_current_time(the_obj, 1, 1); ++ ++ switch (type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ the_obj->variant.file_variant.file_size = 0; ++ the_obj->variant.file_variant.scanned_size = 0; ++ the_obj->variant.file_variant.shrink_size = ++ yaffs_max_file_size(dev); ++ the_obj->variant.file_variant.top_level = 0; ++ the_obj->variant.file_variant.top = tn; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ INIT_LIST_HEAD(&the_obj->variant.dir_variant.children); ++ INIT_LIST_HEAD(&the_obj->variant.dir_variant.dirty); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* No action required */ ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* todo this should not happen */ ++ break; ++ } ++ return the_obj; ++} ++ ++static struct yaffs_obj *yaffs_create_fake_dir(struct yaffs_dev *dev, ++ int number, u32 mode) ++{ ++ ++ struct yaffs_obj *obj = ++ yaffs_new_obj(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY); ++ ++ if (!obj) ++ return NULL; ++ ++ obj->fake = 1; /* it is fake so it might not use NAND */ ++ obj->rename_allowed = 0; ++ obj->unlink_allowed = 0; ++ obj->deleted = 0; ++ obj->unlinked = 0; ++ obj->yst_mode = mode; ++ obj->my_dev = dev; ++ obj->hdr_chunk = 0; /* Not a valid chunk. */ ++ return obj; ++ ++} ++ ++ ++static void yaffs_init_tnodes_and_objs(struct yaffs_dev *dev) ++{ ++ int i; ++ ++ dev->n_obj = 0; ++ dev->n_tnodes = 0; ++ yaffs_init_raw_tnodes_and_objs(dev); ++ ++ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { ++ INIT_LIST_HEAD(&dev->obj_bucket[i].list); ++ dev->obj_bucket[i].count = 0; ++ } ++} ++ ++struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, ++ int number, ++ enum yaffs_obj_type type) ++{ ++ struct yaffs_obj *the_obj = NULL; ++ ++ if (number > 0) ++ the_obj = yaffs_find_by_number(dev, number); ++ ++ if (!the_obj) ++ the_obj = yaffs_new_obj(dev, number, type); ++ ++ return the_obj; ++ ++} ++ ++YCHAR *yaffs_clone_str(const YCHAR *str) ++{ ++ YCHAR *new_str = NULL; ++ int len; ++ ++ if (!str) ++ str = _Y(""); ++ ++ len = strnlen(str, YAFFS_MAX_ALIAS_LENGTH); ++ new_str = kmalloc((len + 1) * sizeof(YCHAR), GFP_NOFS); ++ if (new_str) { ++ strncpy(new_str, str, len); ++ new_str[len] = 0; ++ } ++ return new_str; ++ ++} ++/* ++ *yaffs_update_parent() handles fixing a directories mtime and ctime when a new ++ * link (ie. name) is created or deleted in the directory. ++ * ++ * ie. ++ * create dir/a : update dir's mtime/ctime ++ * rm dir/a: update dir's mtime/ctime ++ * modify dir/a: don't update dir's mtimme/ctime ++ * ++ * This can be handled immediately or defered. Defering helps reduce the number ++ * of updates when many files in a directory are changed within a brief period. ++ * ++ * If the directory updating is defered then yaffs_update_dirty_dirs must be ++ * called periodically. ++ */ ++ ++static void yaffs_update_parent(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev; ++ ++ if (!obj) ++ return; ++ dev = obj->my_dev; ++ obj->dirty = 1; ++ yaffs_load_current_time(obj, 0, 1); ++ if (dev->param.defered_dir_update) { ++ struct list_head *link = &obj->variant.dir_variant.dirty; ++ ++ if (list_empty(link)) { ++ list_add(link, &dev->dirty_dirs); ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, ++ "Added object %d to dirty directories", ++ obj->obj_id); ++ } ++ ++ } else { ++ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); ++ } ++} ++ ++void yaffs_update_dirty_dirs(struct yaffs_dev *dev) ++{ ++ struct list_head *link; ++ struct yaffs_obj *obj; ++ struct yaffs_dir_var *d_s; ++ union yaffs_obj_var *o_v; ++ ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update dirty directories"); ++ ++ while (!list_empty(&dev->dirty_dirs)) { ++ link = dev->dirty_dirs.next; ++ list_del_init(link); ++ ++ d_s = list_entry(link, struct yaffs_dir_var, dirty); ++ o_v = list_entry(d_s, union yaffs_obj_var, dir_variant); ++ obj = list_entry(o_v, struct yaffs_obj, variant); ++ ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update directory %d", ++ obj->obj_id); ++ ++ if (obj->dirty) ++ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); ++ } ++} ++ ++/* ++ * Mknod (create) a new object. ++ * equiv_obj only has meaning for a hard link; ++ * alias_str only has meaning for a symlink. ++ * rdev only has meaning for devices (a subset of special objects) ++ */ ++ ++static struct yaffs_obj *yaffs_create_obj(enum yaffs_obj_type type, ++ struct yaffs_obj *parent, ++ const YCHAR *name, ++ u32 mode, ++ u32 uid, ++ u32 gid, ++ struct yaffs_obj *equiv_obj, ++ const YCHAR *alias_str, u32 rdev) ++{ ++ struct yaffs_obj *in; ++ YCHAR *str = NULL; ++ struct yaffs_dev *dev = parent->my_dev; ++ ++ /* Check if the entry exists. ++ * If it does then fail the call since we don't want a dup. */ ++ if (yaffs_find_by_name(parent, name)) ++ return NULL; ++ ++ if (type == YAFFS_OBJECT_TYPE_SYMLINK) { ++ str = yaffs_clone_str(alias_str); ++ if (!str) ++ return NULL; ++ } ++ ++ in = yaffs_new_obj(dev, -1, type); ++ ++ if (!in) { ++ kfree(str); ++ return NULL; ++ } ++ ++ in->hdr_chunk = 0; ++ in->valid = 1; ++ in->variant_type = type; ++ ++ in->yst_mode = mode; ++ ++ yaffs_attribs_init(in, gid, uid, rdev); ++ ++ in->n_data_chunks = 0; ++ ++ yaffs_set_obj_name(in, name); ++ in->dirty = 1; ++ ++ yaffs_add_obj_to_dir(parent, in); ++ ++ in->my_dev = parent->my_dev; ++ ++ switch (type) { ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ in->variant.symlink_variant.alias = str; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ in->variant.hardlink_variant.equiv_obj = equiv_obj; ++ in->variant.hardlink_variant.equiv_id = equiv_obj->obj_id; ++ list_add(&in->hard_links, &equiv_obj->hard_links); ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* do nothing */ ++ break; ++ } ++ ++ if (yaffs_update_oh(in, name, 0, 0, 0, NULL) < 0) { ++ /* Could not create the object header, fail */ ++ yaffs_del_obj(in); ++ in = NULL; ++ } ++ ++ if (in) ++ yaffs_update_parent(parent); ++ ++ return in; ++} ++ ++struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid) ++{ ++ return yaffs_create_obj(YAFFS_OBJECT_TYPE_FILE, parent, name, mode, ++ uid, gid, NULL, NULL, 0); ++} ++ ++struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name, ++ u32 mode, u32 uid, u32 gid) ++{ ++ return yaffs_create_obj(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name, ++ mode, uid, gid, NULL, NULL, 0); ++} ++ ++struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid, u32 rdev) ++{ ++ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode, ++ uid, gid, NULL, NULL, rdev); ++} ++ ++struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid, const YCHAR *alias) ++{ ++ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode, ++ uid, gid, NULL, alias, 0); ++} ++ ++/* yaffs_link_obj returns the object id of the equivalent object.*/ ++struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, ++ struct yaffs_obj *equiv_obj) ++{ ++ /* Get the real object in case we were fed a hard link obj */ ++ equiv_obj = yaffs_get_equivalent_obj(equiv_obj); ++ ++ if (yaffs_create_obj(YAFFS_OBJECT_TYPE_HARDLINK, ++ parent, name, 0, 0, 0, ++ equiv_obj, NULL, 0)) ++ return equiv_obj; ++ ++ return NULL; ++ ++} ++ ++ ++ ++/*---------------------- Block Management and Page Allocation -------------*/ ++ ++static void yaffs_deinit_blocks(struct yaffs_dev *dev) ++{ ++ if (dev->block_info_alt && dev->block_info) ++ vfree(dev->block_info); ++ else ++ kfree(dev->block_info); ++ ++ dev->block_info_alt = 0; ++ ++ dev->block_info = NULL; ++ ++ if (dev->chunk_bits_alt && dev->chunk_bits) ++ vfree(dev->chunk_bits); ++ else ++ kfree(dev->chunk_bits); ++ dev->chunk_bits_alt = 0; ++ dev->chunk_bits = NULL; ++} ++ ++static int yaffs_init_blocks(struct yaffs_dev *dev) ++{ ++ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; ++ ++ dev->block_info = NULL; ++ dev->chunk_bits = NULL; ++ dev->alloc_block = -1; /* force it to get a new one */ ++ ++ /* If the first allocation strategy fails, thry the alternate one */ ++ dev->block_info = ++ kmalloc(n_blocks * sizeof(struct yaffs_block_info), GFP_NOFS); ++ if (!dev->block_info) { ++ dev->block_info = ++ vmalloc(n_blocks * sizeof(struct yaffs_block_info)); ++ dev->block_info_alt = 1; ++ } else { ++ dev->block_info_alt = 0; ++ } ++ ++ if (!dev->block_info) ++ goto alloc_error; ++ ++ /* Set up dynamic blockinfo stuff. Round up bytes. */ ++ dev->chunk_bit_stride = (dev->param.chunks_per_block + 7) / 8; ++ dev->chunk_bits = ++ kmalloc(dev->chunk_bit_stride * n_blocks, GFP_NOFS); ++ if (!dev->chunk_bits) { ++ dev->chunk_bits = ++ vmalloc(dev->chunk_bit_stride * n_blocks); ++ dev->chunk_bits_alt = 1; ++ } else { ++ dev->chunk_bits_alt = 0; ++ } ++ if (!dev->chunk_bits) ++ goto alloc_error; ++ ++ ++ memset(dev->block_info, 0, n_blocks * sizeof(struct yaffs_block_info)); ++ memset(dev->chunk_bits, 0, dev->chunk_bit_stride * n_blocks); ++ return YAFFS_OK; ++ ++alloc_error: ++ yaffs_deinit_blocks(dev); ++ return YAFFS_FAIL; ++} ++ ++ ++void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no) ++{ ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block_no); ++ int erased_ok = 0; ++ int i; ++ ++ /* If the block is still healthy erase it and mark as clean. ++ * If the block has had a data failure, then retire it. ++ */ ++ ++ yaffs_trace(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE, ++ "yaffs_block_became_dirty block %d state %d %s", ++ block_no, bi->block_state, ++ (bi->needs_retiring) ? "needs retiring" : ""); ++ ++ yaffs2_clear_oldest_dirty_seq(dev, bi); ++ ++ bi->block_state = YAFFS_BLOCK_STATE_DIRTY; ++ ++ /* If this is the block being garbage collected then stop gc'ing */ ++ if (block_no == dev->gc_block) ++ dev->gc_block = 0; ++ ++ /* If this block is currently the best candidate for gc ++ * then drop as a candidate */ ++ if (block_no == dev->gc_dirtiest) { ++ dev->gc_dirtiest = 0; ++ dev->gc_pages_in_use = 0; ++ } ++ ++ if (!bi->needs_retiring) { ++ yaffs2_checkpt_invalidate(dev); ++ erased_ok = yaffs_erase_block(dev, block_no); ++ if (!erased_ok) { ++ dev->n_erase_failures++; ++ yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ "**>> Erasure failed %d", block_no); ++ } ++ } ++ ++ /* Verify erasure if needed */ ++ if (erased_ok && ++ ((yaffs_trace_mask & YAFFS_TRACE_ERASE) || ++ !yaffs_skip_verification(dev))) { ++ for (i = 0; i < dev->param.chunks_per_block; i++) { ++ if (!yaffs_check_chunk_erased(dev, ++ block_no * dev->param.chunks_per_block + i)) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ ">>Block %d erasure supposedly OK, but chunk %d not erased", ++ block_no, i); ++ } ++ } ++ } ++ ++ if (!erased_ok) { ++ /* We lost a block of free space */ ++ dev->n_free_chunks -= dev->param.chunks_per_block; ++ yaffs_retire_block(dev, block_no); ++ yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ "**>> Block %d retired", block_no); ++ return; ++ } ++ ++ /* Clean it up... */ ++ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; ++ bi->seq_number = 0; ++ dev->n_erased_blocks++; ++ bi->pages_in_use = 0; ++ bi->soft_del_pages = 0; ++ bi->has_shrink_hdr = 0; ++ bi->skip_erased_check = 1; /* Clean, so no need to check */ ++ bi->gc_prioritise = 0; ++ bi->has_summary = 0; ++ ++ yaffs_clear_chunk_bits(dev, block_no); ++ ++ yaffs_trace(YAFFS_TRACE_ERASE, "Erased block %d", block_no); ++} ++ ++static inline int yaffs_gc_process_chunk(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi, ++ int old_chunk, u8 *buffer) ++{ ++ int new_chunk; ++ int mark_flash = 1; ++ struct yaffs_ext_tags tags; ++ struct yaffs_obj *object; ++ int matching_chunk; ++ int ret_val = YAFFS_OK; ++ ++ memset(&tags, 0, sizeof(tags)); ++ yaffs_rd_chunk_tags_nand(dev, old_chunk, ++ buffer, &tags); ++ object = yaffs_find_by_number(dev, tags.obj_id); ++ ++ yaffs_trace(YAFFS_TRACE_GC_DETAIL, ++ "Collecting chunk in block %d, %d %d %d ", ++ dev->gc_chunk, tags.obj_id, ++ tags.chunk_id, tags.n_bytes); ++ ++ if (object && !yaffs_skip_verification(dev)) { ++ if (tags.chunk_id == 0) ++ matching_chunk = ++ object->hdr_chunk; ++ else if (object->soft_del) ++ /* Defeat the test */ ++ matching_chunk = old_chunk; ++ else ++ matching_chunk = ++ yaffs_find_chunk_in_file ++ (object, tags.chunk_id, ++ NULL); ++ ++ if (old_chunk != matching_chunk) ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "gc: page in gc mismatch: %d %d %d %d", ++ old_chunk, ++ matching_chunk, ++ tags.obj_id, ++ tags.chunk_id); ++ } ++ ++ if (!object) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "page %d in gc has no object: %d %d %d ", ++ old_chunk, ++ tags.obj_id, tags.chunk_id, ++ tags.n_bytes); ++ } ++ ++ if (object && ++ object->deleted && ++ object->soft_del && tags.chunk_id != 0) { ++ /* Data chunk in a soft deleted file, ++ * throw it away. ++ * It's a soft deleted data chunk, ++ * No need to copy this, just forget ++ * about it and fix up the object. ++ */ ++ ++ /* Free chunks already includes ++ * softdeleted chunks, how ever this ++ * chunk is going to soon be really ++ * deleted which will increment free ++ * chunks. We have to decrement free ++ * chunks so this works out properly. ++ */ ++ dev->n_free_chunks--; ++ bi->soft_del_pages--; ++ ++ object->n_data_chunks--; ++ if (object->n_data_chunks <= 0) { ++ /* remeber to clean up obj */ ++ dev->gc_cleanup_list[dev->n_clean_ups] = tags.obj_id; ++ dev->n_clean_ups++; ++ } ++ mark_flash = 0; ++ } else if (object) { ++ /* It's either a data chunk in a live ++ * file or an ObjectHeader, so we're ++ * interested in it. ++ * NB Need to keep the ObjectHeaders of ++ * deleted files until the whole file ++ * has been deleted off ++ */ ++ tags.serial_number++; ++ dev->n_gc_copies++; ++ ++ if (tags.chunk_id == 0) { ++ /* It is an object Id, ++ * We need to nuke the ++ * shrinkheader flags since its ++ * work is done. ++ * Also need to clean up ++ * shadowing. ++ */ ++ struct yaffs_obj_hdr *oh; ++ oh = (struct yaffs_obj_hdr *) buffer; ++ ++ oh->is_shrink = 0; ++ tags.extra_is_shrink = 0; ++ oh->shadows_obj = 0; ++ oh->inband_shadowed_obj_id = 0; ++ tags.extra_shadows = 0; ++ ++ /* Update file size */ ++ if (object->variant_type == YAFFS_OBJECT_TYPE_FILE) { ++ yaffs_oh_size_load(oh, ++ object->variant.file_variant.file_size); ++ tags.extra_file_size = ++ object->variant.file_variant.file_size; ++ } ++ ++ yaffs_verify_oh(object, oh, &tags, 1); ++ new_chunk = ++ yaffs_write_new_chunk(dev, (u8 *) oh, &tags, 1); ++ } else { ++ new_chunk = ++ yaffs_write_new_chunk(dev, buffer, &tags, 1); ++ } ++ ++ if (new_chunk < 0) { ++ ret_val = YAFFS_FAIL; ++ } else { ++ ++ /* Now fix up the Tnodes etc. */ ++ ++ if (tags.chunk_id == 0) { ++ /* It's a header */ ++ object->hdr_chunk = new_chunk; ++ object->serial = tags.serial_number; ++ } else { ++ /* It's a data chunk */ ++ yaffs_put_chunk_in_file(object, tags.chunk_id, ++ new_chunk, 0); ++ } ++ } ++ } ++ if (ret_val == YAFFS_OK) ++ yaffs_chunk_del(dev, old_chunk, mark_flash, __LINE__); ++ return ret_val; ++} ++ ++static int yaffs_gc_block(struct yaffs_dev *dev, int block, int whole_block) ++{ ++ int old_chunk; ++ int ret_val = YAFFS_OK; ++ int i; ++ int is_checkpt_block; ++ int max_copies; ++ int chunks_before = yaffs_get_erased_chunks(dev); ++ int chunks_after; ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block); ++ ++ is_checkpt_block = (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT); ++ ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "Collecting block %d, in use %d, shrink %d, whole_block %d", ++ block, bi->pages_in_use, bi->has_shrink_hdr, ++ whole_block); ++ ++ /*yaffs_verify_free_chunks(dev); */ ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) ++ bi->block_state = YAFFS_BLOCK_STATE_COLLECTING; ++ ++ bi->has_shrink_hdr = 0; /* clear the flag so that the block can erase */ ++ ++ dev->gc_disable = 1; ++ ++ yaffs_summary_gc(dev, block); ++ ++ if (is_checkpt_block || !yaffs_still_some_chunks(dev, block)) { ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "Collecting block %d that has no chunks in use", ++ block); ++ yaffs_block_became_dirty(dev, block); ++ } else { ++ ++ u8 *buffer = yaffs_get_temp_buffer(dev); ++ ++ yaffs_verify_blk(dev, bi, block); ++ ++ max_copies = (whole_block) ? dev->param.chunks_per_block : 5; ++ old_chunk = block * dev->param.chunks_per_block + dev->gc_chunk; ++ ++ for (/* init already done */ ; ++ ret_val == YAFFS_OK && ++ dev->gc_chunk < dev->param.chunks_per_block && ++ (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) && ++ max_copies > 0; ++ dev->gc_chunk++, old_chunk++) { ++ if (yaffs_check_chunk_bit(dev, block, dev->gc_chunk)) { ++ /* Page is in use and might need to be copied */ ++ max_copies--; ++ ret_val = yaffs_gc_process_chunk(dev, bi, ++ old_chunk, buffer); ++ } ++ } ++ yaffs_release_temp_buffer(dev, buffer); ++ } ++ ++ yaffs_verify_collected_blk(dev, bi, block); ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { ++ /* ++ * The gc did not complete. Set block state back to FULL ++ * because checkpointing does not restore gc. ++ */ ++ bi->block_state = YAFFS_BLOCK_STATE_FULL; ++ } else { ++ /* The gc completed. */ ++ /* Do any required cleanups */ ++ for (i = 0; i < dev->n_clean_ups; i++) { ++ /* Time to delete the file too */ ++ struct yaffs_obj *object = ++ yaffs_find_by_number(dev, dev->gc_cleanup_list[i]); ++ if (object) { ++ yaffs_free_tnode(dev, ++ object->variant.file_variant.top); ++ object->variant.file_variant.top = NULL; ++ yaffs_trace(YAFFS_TRACE_GC, ++ "yaffs: About to finally delete object %d", ++ object->obj_id); ++ yaffs_generic_obj_del(object); ++ object->my_dev->n_deleted_files--; ++ } ++ ++ } ++ chunks_after = yaffs_get_erased_chunks(dev); ++ if (chunks_before >= chunks_after) ++ yaffs_trace(YAFFS_TRACE_GC, ++ "gc did not increase free chunks before %d after %d", ++ chunks_before, chunks_after); ++ dev->gc_block = 0; ++ dev->gc_chunk = 0; ++ dev->n_clean_ups = 0; ++ } ++ ++ dev->gc_disable = 0; ++ ++ return ret_val; ++} ++ ++/* ++ * find_gc_block() selects the dirtiest block (or close enough) ++ * for garbage collection. ++ */ ++ ++static unsigned yaffs_find_gc_block(struct yaffs_dev *dev, ++ int aggressive, int background) ++{ ++ int i; ++ int iterations; ++ unsigned selected = 0; ++ int prioritised = 0; ++ int prioritised_exist = 0; ++ struct yaffs_block_info *bi; ++ int threshold; ++ ++ /* First let's see if we need to grab a prioritised block */ ++ if (dev->has_pending_prioritised_gc && !aggressive) { ++ dev->gc_dirtiest = 0; ++ bi = dev->block_info; ++ for (i = dev->internal_start_block; ++ i <= dev->internal_end_block && !selected; i++) { ++ ++ if (bi->gc_prioritise) { ++ prioritised_exist = 1; ++ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && ++ yaffs_block_ok_for_gc(dev, bi)) { ++ selected = i; ++ prioritised = 1; ++ } ++ } ++ bi++; ++ } ++ ++ /* ++ * If there is a prioritised block and none was selected then ++ * this happened because there is at least one old dirty block ++ * gumming up the works. Let's gc the oldest dirty block. ++ */ ++ ++ if (prioritised_exist && ++ !selected && dev->oldest_dirty_block > 0) ++ selected = dev->oldest_dirty_block; ++ ++ if (!prioritised_exist) /* None found, so we can clear this */ ++ dev->has_pending_prioritised_gc = 0; ++ } ++ ++ /* If we're doing aggressive GC then we are happy to take a less-dirty ++ * block, and search harder. ++ * else (leasurely gc), then we only bother to do this if the ++ * block has only a few pages in use. ++ */ ++ ++ if (!selected) { ++ int pages_used; ++ int n_blocks = ++ dev->internal_end_block - dev->internal_start_block + 1; ++ if (aggressive) { ++ threshold = dev->param.chunks_per_block; ++ iterations = n_blocks; ++ } else { ++ int max_threshold; ++ ++ if (background) ++ max_threshold = dev->param.chunks_per_block / 2; ++ else ++ max_threshold = dev->param.chunks_per_block / 8; ++ ++ if (max_threshold < YAFFS_GC_PASSIVE_THRESHOLD) ++ max_threshold = YAFFS_GC_PASSIVE_THRESHOLD; ++ ++ threshold = background ? (dev->gc_not_done + 2) * 2 : 0; ++ if (threshold < YAFFS_GC_PASSIVE_THRESHOLD) ++ threshold = YAFFS_GC_PASSIVE_THRESHOLD; ++ if (threshold > max_threshold) ++ threshold = max_threshold; ++ ++ iterations = n_blocks / 16 + 1; ++ if (iterations > 100) ++ iterations = 100; ++ } ++ ++ for (i = 0; ++ i < iterations && ++ (dev->gc_dirtiest < 1 || ++ dev->gc_pages_in_use > YAFFS_GC_GOOD_ENOUGH); ++ i++) { ++ dev->gc_block_finder++; ++ if (dev->gc_block_finder < dev->internal_start_block || ++ dev->gc_block_finder > dev->internal_end_block) ++ dev->gc_block_finder = ++ dev->internal_start_block; ++ ++ bi = yaffs_get_block_info(dev, dev->gc_block_finder); ++ ++ pages_used = bi->pages_in_use - bi->soft_del_pages; ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && ++ pages_used < dev->param.chunks_per_block && ++ (dev->gc_dirtiest < 1 || ++ pages_used < dev->gc_pages_in_use) && ++ yaffs_block_ok_for_gc(dev, bi)) { ++ dev->gc_dirtiest = dev->gc_block_finder; ++ dev->gc_pages_in_use = pages_used; ++ } ++ } ++ ++ if (dev->gc_dirtiest > 0 && dev->gc_pages_in_use <= threshold) ++ selected = dev->gc_dirtiest; ++ } ++ ++ /* ++ * If nothing has been selected for a while, try the oldest dirty ++ * because that's gumming up the works. ++ */ ++ ++ if (!selected && dev->param.is_yaffs2 && ++ dev->gc_not_done >= (background ? 10 : 20)) { ++ yaffs2_find_oldest_dirty_seq(dev); ++ if (dev->oldest_dirty_block > 0) { ++ selected = dev->oldest_dirty_block; ++ dev->gc_dirtiest = selected; ++ dev->oldest_dirty_gc_count++; ++ bi = yaffs_get_block_info(dev, selected); ++ dev->gc_pages_in_use = ++ bi->pages_in_use - bi->soft_del_pages; ++ } else { ++ dev->gc_not_done = 0; ++ } ++ } ++ ++ if (selected) { ++ yaffs_trace(YAFFS_TRACE_GC, ++ "GC Selected block %d with %d free, prioritised:%d", ++ selected, ++ dev->param.chunks_per_block - dev->gc_pages_in_use, ++ prioritised); ++ ++ dev->n_gc_blocks++; ++ if (background) ++ dev->bg_gcs++; ++ ++ dev->gc_dirtiest = 0; ++ dev->gc_pages_in_use = 0; ++ dev->gc_not_done = 0; ++ if (dev->refresh_skip > 0) ++ dev->refresh_skip--; ++ } else { ++ dev->gc_not_done++; ++ yaffs_trace(YAFFS_TRACE_GC, ++ "GC none: finder %d skip %d threshold %d dirtiest %d using %d oldest %d%s", ++ dev->gc_block_finder, dev->gc_not_done, threshold, ++ dev->gc_dirtiest, dev->gc_pages_in_use, ++ dev->oldest_dirty_block, background ? " bg" : ""); ++ } ++ ++ return selected; ++} ++ ++/* New garbage collector ++ * If we're very low on erased blocks then we do aggressive garbage collection ++ * otherwise we do "leasurely" garbage collection. ++ * Aggressive gc looks further (whole array) and will accept less dirty blocks. ++ * Passive gc only inspects smaller areas and only accepts more dirty blocks. ++ * ++ * The idea is to help clear out space in a more spread-out manner. ++ * Dunno if it really does anything useful. ++ */ ++static int yaffs_check_gc(struct yaffs_dev *dev, int background) ++{ ++ int aggressive = 0; ++ int gc_ok = YAFFS_OK; ++ int max_tries = 0; ++ int min_erased; ++ int erased_chunks; ++ int checkpt_block_adjust; ++ ++ if (dev->param.gc_control_fn && ++ (dev->param.gc_control_fn(dev) & 1) == 0) ++ return YAFFS_OK; ++ ++ if (dev->gc_disable) ++ /* Bail out so we don't get recursive gc */ ++ return YAFFS_OK; ++ ++ /* This loop should pass the first time. ++ * Only loops here if the collection does not increase space. ++ */ ++ ++ do { ++ max_tries++; ++ ++ checkpt_block_adjust = yaffs_calc_checkpt_blocks_required(dev); ++ ++ min_erased = ++ dev->param.n_reserved_blocks + checkpt_block_adjust + 1; ++ erased_chunks = ++ dev->n_erased_blocks * dev->param.chunks_per_block; ++ ++ /* If we need a block soon then do aggressive gc. */ ++ if (dev->n_erased_blocks < min_erased) ++ aggressive = 1; ++ else { ++ if (!background ++ && erased_chunks > (dev->n_free_chunks / 4)) ++ break; ++ ++ if (dev->gc_skip > 20) ++ dev->gc_skip = 20; ++ if (erased_chunks < dev->n_free_chunks / 2 || ++ dev->gc_skip < 1 || background) ++ aggressive = 0; ++ else { ++ dev->gc_skip--; ++ break; ++ } ++ } ++ ++ dev->gc_skip = 5; ++ ++ /* If we don't already have a block being gc'd then see if we ++ * should start another */ ++ ++ if (dev->gc_block < 1 && !aggressive) { ++ dev->gc_block = yaffs2_find_refresh_block(dev); ++ dev->gc_chunk = 0; ++ dev->n_clean_ups = 0; ++ } ++ if (dev->gc_block < 1) { ++ dev->gc_block = ++ yaffs_find_gc_block(dev, aggressive, background); ++ dev->gc_chunk = 0; ++ dev->n_clean_ups = 0; ++ } ++ ++ if (dev->gc_block > 0) { ++ dev->all_gcs++; ++ if (!aggressive) ++ dev->passive_gc_count++; ++ ++ yaffs_trace(YAFFS_TRACE_GC, ++ "yaffs: GC n_erased_blocks %d aggressive %d", ++ dev->n_erased_blocks, aggressive); ++ ++ gc_ok = yaffs_gc_block(dev, dev->gc_block, aggressive); ++ } ++ ++ if (dev->n_erased_blocks < (dev->param.n_reserved_blocks) && ++ dev->gc_block > 0) { ++ yaffs_trace(YAFFS_TRACE_GC, ++ "yaffs: GC !!!no reclaim!!! n_erased_blocks %d after try %d block %d", ++ dev->n_erased_blocks, max_tries, ++ dev->gc_block); ++ } ++ } while ((dev->n_erased_blocks < dev->param.n_reserved_blocks) && ++ (dev->gc_block > 0) && (max_tries < 2)); ++ ++ return aggressive ? gc_ok : YAFFS_OK; ++} ++ ++/* ++ * yaffs_bg_gc() ++ * Garbage collects. Intended to be called from a background thread. ++ * Returns non-zero if at least half the free chunks are erased. ++ */ ++int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency) ++{ ++ int erased_chunks = dev->n_erased_blocks * dev->param.chunks_per_block; ++ ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, "Background gc %u", urgency); ++ ++ yaffs_check_gc(dev, 1); ++ return erased_chunks > dev->n_free_chunks / 2; ++} ++ ++/*-------------------- Data file manipulation -----------------*/ ++ ++static int yaffs_rd_data_obj(struct yaffs_obj *in, int inode_chunk, u8 * buffer) ++{ ++ int nand_chunk = yaffs_find_chunk_in_file(in, inode_chunk, NULL); ++ ++ if (nand_chunk >= 0) ++ return yaffs_rd_chunk_tags_nand(in->my_dev, nand_chunk, ++ buffer, NULL); ++ else { ++ yaffs_trace(YAFFS_TRACE_NANDACCESS, ++ "Chunk %d not found zero instead", ++ nand_chunk); ++ /* get sane (zero) data if you read a hole */ ++ memset(buffer, 0, in->my_dev->data_bytes_per_chunk); ++ return 0; ++ } ++ ++} ++ ++void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, ++ int lyn) ++{ ++ int block; ++ int page; ++ struct yaffs_ext_tags tags; ++ struct yaffs_block_info *bi; ++ ++ if (chunk_id <= 0) ++ return; ++ ++ dev->n_deletions++; ++ block = chunk_id / dev->param.chunks_per_block; ++ page = chunk_id % dev->param.chunks_per_block; ++ ++ if (!yaffs_check_chunk_bit(dev, block, page)) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Deleting invalid chunk %d", chunk_id); ++ ++ bi = yaffs_get_block_info(dev, block); ++ ++ yaffs2_update_oldest_dirty_seq(dev, block, bi); ++ ++ yaffs_trace(YAFFS_TRACE_DELETION, ++ "line %d delete of chunk %d", ++ lyn, chunk_id); ++ ++ if (!dev->param.is_yaffs2 && mark_flash && ++ bi->block_state != YAFFS_BLOCK_STATE_COLLECTING) { ++ ++ memset(&tags, 0, sizeof(tags)); ++ tags.is_deleted = 1; ++ yaffs_wr_chunk_tags_nand(dev, chunk_id, NULL, &tags); ++ yaffs_handle_chunk_update(dev, chunk_id, &tags); ++ } else { ++ dev->n_unmarked_deletions++; ++ } ++ ++ /* Pull out of the management area. ++ * If the whole block became dirty, this will kick off an erasure. ++ */ ++ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING || ++ bi->block_state == YAFFS_BLOCK_STATE_FULL || ++ bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || ++ bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { ++ dev->n_free_chunks++; ++ yaffs_clear_chunk_bit(dev, block, page); ++ bi->pages_in_use--; ++ ++ if (bi->pages_in_use == 0 && ++ !bi->has_shrink_hdr && ++ bi->block_state != YAFFS_BLOCK_STATE_ALLOCATING && ++ bi->block_state != YAFFS_BLOCK_STATE_NEEDS_SCAN) { ++ yaffs_block_became_dirty(dev, block); ++ } ++ } ++} ++ ++static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, ++ const u8 *buffer, int n_bytes, int use_reserve) ++{ ++ /* Find old chunk Need to do this to get serial number ++ * Write new one and patch into tree. ++ * Invalidate old tags. ++ */ ++ ++ int prev_chunk_id; ++ struct yaffs_ext_tags prev_tags; ++ int new_chunk_id; ++ struct yaffs_ext_tags new_tags; ++ struct yaffs_dev *dev = in->my_dev; ++ ++ yaffs_check_gc(dev, 0); ++ ++ /* Get the previous chunk at this location in the file if it exists. ++ * If it does not exist then put a zero into the tree. This creates ++ * the tnode now, rather than later when it is harder to clean up. ++ */ ++ prev_chunk_id = yaffs_find_chunk_in_file(in, inode_chunk, &prev_tags); ++ if (prev_chunk_id < 1 && ++ !yaffs_put_chunk_in_file(in, inode_chunk, 0, 0)) ++ return 0; ++ ++ /* Set up new tags */ ++ memset(&new_tags, 0, sizeof(new_tags)); ++ ++ new_tags.chunk_id = inode_chunk; ++ new_tags.obj_id = in->obj_id; ++ new_tags.serial_number = ++ (prev_chunk_id > 0) ? prev_tags.serial_number + 1 : 1; ++ new_tags.n_bytes = n_bytes; ++ ++ if (n_bytes < 1 || n_bytes > dev->param.total_bytes_per_chunk) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "Writing %d bytes to chunk!!!!!!!!!", ++ n_bytes); ++ BUG(); ++ } ++ ++ new_chunk_id = ++ yaffs_write_new_chunk(dev, buffer, &new_tags, use_reserve); ++ ++ if (new_chunk_id > 0) { ++ yaffs_put_chunk_in_file(in, inode_chunk, new_chunk_id, 0); ++ ++ if (prev_chunk_id > 0) ++ yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); ++ ++ yaffs_verify_file_sane(in); ++ } ++ return new_chunk_id; ++ ++} ++ ++ ++ ++static int yaffs_do_xattrib_mod(struct yaffs_obj *obj, int set, ++ const YCHAR *name, const void *value, int size, ++ int flags) ++{ ++ struct yaffs_xattr_mod xmod; ++ int result; ++ ++ xmod.set = set; ++ xmod.name = name; ++ xmod.data = value; ++ xmod.size = size; ++ xmod.flags = flags; ++ xmod.result = -ENOSPC; ++ ++ result = yaffs_update_oh(obj, NULL, 0, 0, 0, &xmod); ++ ++ if (result > 0) ++ return xmod.result; ++ else ++ return -ENOSPC; ++} ++ ++static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, ++ struct yaffs_xattr_mod *xmod) ++{ ++ int retval = 0; ++ int x_offs = sizeof(struct yaffs_obj_hdr); ++ struct yaffs_dev *dev = obj->my_dev; ++ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); ++ char *x_buffer = buffer + x_offs; ++ ++ if (xmod->set) ++ retval = ++ nval_set(x_buffer, x_size, xmod->name, xmod->data, ++ xmod->size, xmod->flags); ++ else ++ retval = nval_del(x_buffer, x_size, xmod->name); ++ ++ obj->has_xattr = nval_hasvalues(x_buffer, x_size); ++ obj->xattr_known = 1; ++ xmod->result = retval; ++ ++ return retval; ++} ++ ++static int yaffs_do_xattrib_fetch(struct yaffs_obj *obj, const YCHAR *name, ++ void *value, int size) ++{ ++ char *buffer = NULL; ++ int result; ++ struct yaffs_ext_tags tags; ++ struct yaffs_dev *dev = obj->my_dev; ++ int x_offs = sizeof(struct yaffs_obj_hdr); ++ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); ++ char *x_buffer; ++ int retval = 0; ++ ++ if (obj->hdr_chunk < 1) ++ return -ENODATA; ++ ++ /* If we know that the object has no xattribs then don't do all the ++ * reading and parsing. ++ */ ++ if (obj->xattr_known && !obj->has_xattr) { ++ if (name) ++ return -ENODATA; ++ else ++ return 0; ++ } ++ ++ buffer = (char *)yaffs_get_temp_buffer(dev); ++ if (!buffer) ++ return -ENOMEM; ++ ++ result = ++ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, (u8 *) buffer, &tags); ++ ++ if (result != YAFFS_OK) ++ retval = -ENOENT; ++ else { ++ x_buffer = buffer + x_offs; ++ ++ if (!obj->xattr_known) { ++ obj->has_xattr = nval_hasvalues(x_buffer, x_size); ++ obj->xattr_known = 1; ++ } ++ ++ if (name) ++ retval = nval_get(x_buffer, x_size, name, value, size); ++ else ++ retval = nval_list(x_buffer, x_size, value, size); ++ } ++ yaffs_release_temp_buffer(dev, (u8 *) buffer); ++ return retval; ++} ++ ++int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, ++ const void *value, int size, int flags) ++{ ++ return yaffs_do_xattrib_mod(obj, 1, name, value, size, flags); ++} ++ ++int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name) ++{ ++ return yaffs_do_xattrib_mod(obj, 0, name, NULL, 0, 0); ++} ++ ++int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, ++ int size) ++{ ++ return yaffs_do_xattrib_fetch(obj, name, value, size); ++} ++ ++int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size) ++{ ++ return yaffs_do_xattrib_fetch(obj, NULL, buffer, size); ++} ++ ++static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) ++{ ++ u8 *buf; ++ struct yaffs_obj_hdr *oh; ++ struct yaffs_dev *dev; ++ struct yaffs_ext_tags tags; ++ int result; ++ int alloc_failed = 0; ++ ++ if (!in || !in->lazy_loaded || in->hdr_chunk < 1) ++ return; ++ ++ dev = in->my_dev; ++ in->lazy_loaded = 0; ++ buf = yaffs_get_temp_buffer(dev); ++ ++ result = yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags); ++ oh = (struct yaffs_obj_hdr *)buf; ++ ++ in->yst_mode = oh->yst_mode; ++ yaffs_load_attribs(in, oh); ++ yaffs_set_obj_name_from_oh(in, oh); ++ ++ if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { ++ in->variant.symlink_variant.alias = ++ yaffs_clone_str(oh->alias); ++ if (!in->variant.symlink_variant.alias) ++ alloc_failed = 1; /* Not returned */ ++ } ++ yaffs_release_temp_buffer(dev, buf); ++} ++ ++static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR *name, ++ const YCHAR *oh_name, int buff_size) ++{ ++#ifdef CONFIG_YAFFS_AUTO_UNICODE ++ if (dev->param.auto_unicode) { ++ if (*oh_name) { ++ /* It is an ASCII name, do an ASCII to ++ * unicode conversion */ ++ const char *ascii_oh_name = (const char *)oh_name; ++ int n = buff_size - 1; ++ while (n > 0 && *ascii_oh_name) { ++ *name = *ascii_oh_name; ++ name++; ++ ascii_oh_name++; ++ n--; ++ } ++ } else { ++ strncpy(name, oh_name + 1, buff_size - 1); ++ } ++ } else { ++#else ++ (void) dev; ++ { ++#endif ++ strncpy(name, oh_name, buff_size - 1); ++ } ++} ++ ++static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name, ++ const YCHAR *name) ++{ ++#ifdef CONFIG_YAFFS_AUTO_UNICODE ++ ++ int is_ascii; ++ YCHAR *w; ++ ++ if (dev->param.auto_unicode) { ++ ++ is_ascii = 1; ++ w = name; ++ ++ /* Figure out if the name will fit in ascii character set */ ++ while (is_ascii && *w) { ++ if ((*w) & 0xff00) ++ is_ascii = 0; ++ w++; ++ } ++ ++ if (is_ascii) { ++ /* It is an ASCII name, so convert unicode to ascii */ ++ char *ascii_oh_name = (char *)oh_name; ++ int n = YAFFS_MAX_NAME_LENGTH - 1; ++ while (n > 0 && *name) { ++ *ascii_oh_name = *name; ++ name++; ++ ascii_oh_name++; ++ n--; ++ } ++ } else { ++ /* Unicode name, so save starting at the second YCHAR */ ++ *oh_name = 0; ++ strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2); ++ } ++ } else { ++#else ++ dev = dev; ++ { ++#endif ++ strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); ++ } ++} ++ ++/* UpdateObjectHeader updates the header on NAND for an object. ++ * If name is not NULL, then that new name is used. ++ */ ++int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force, ++ int is_shrink, int shadows, struct yaffs_xattr_mod *xmod) ++{ ++ ++ struct yaffs_block_info *bi; ++ struct yaffs_dev *dev = in->my_dev; ++ int prev_chunk_id; ++ int ret_val = 0; ++ int result = 0; ++ int new_chunk_id; ++ struct yaffs_ext_tags new_tags; ++ struct yaffs_ext_tags old_tags; ++ const YCHAR *alias = NULL; ++ u8 *buffer = NULL; ++ YCHAR old_name[YAFFS_MAX_NAME_LENGTH + 1]; ++ struct yaffs_obj_hdr *oh = NULL; ++ loff_t file_size = 0; ++ ++ strcpy(old_name, _Y("silly old name")); ++ ++ if (in->fake && in != dev->root_dir && !force && !xmod) ++ return ret_val; ++ ++ yaffs_check_gc(dev, 0); ++ yaffs_check_obj_details_loaded(in); ++ ++ buffer = yaffs_get_temp_buffer(in->my_dev); ++ oh = (struct yaffs_obj_hdr *)buffer; ++ ++ prev_chunk_id = in->hdr_chunk; ++ ++ if (prev_chunk_id > 0) { ++ result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, ++ buffer, &old_tags); ++ ++ yaffs_verify_oh(in, oh, &old_tags, 0); ++ memcpy(old_name, oh->name, sizeof(oh->name)); ++ memset(buffer, 0xff, sizeof(struct yaffs_obj_hdr)); ++ } else { ++ memset(buffer, 0xff, dev->data_bytes_per_chunk); ++ } ++ ++ oh->type = in->variant_type; ++ oh->yst_mode = in->yst_mode; ++ oh->shadows_obj = oh->inband_shadowed_obj_id = shadows; ++ ++ yaffs_load_attribs_oh(oh, in); ++ ++ if (in->parent) ++ oh->parent_obj_id = in->parent->obj_id; ++ else ++ oh->parent_obj_id = 0; ++ ++ if (name && *name) { ++ memset(oh->name, 0, sizeof(oh->name)); ++ yaffs_load_oh_from_name(dev, oh->name, name); ++ } else if (prev_chunk_id > 0) { ++ memcpy(oh->name, old_name, sizeof(oh->name)); ++ } else { ++ memset(oh->name, 0, sizeof(oh->name)); ++ } ++ ++ oh->is_shrink = is_shrink; ++ ++ switch (in->variant_type) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Should not happen */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ if (oh->parent_obj_id != YAFFS_OBJECTID_DELETED && ++ oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED) ++ file_size = in->variant.file_variant.file_size; ++ yaffs_oh_size_load(oh, file_size); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ oh->equiv_id = in->variant.hardlink_variant.equiv_id; ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ alias = in->variant.symlink_variant.alias; ++ if (!alias) ++ alias = _Y("no alias"); ++ strncpy(oh->alias, alias, YAFFS_MAX_ALIAS_LENGTH); ++ oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0; ++ break; ++ } ++ ++ /* process any xattrib modifications */ ++ if (xmod) ++ yaffs_apply_xattrib_mod(in, (char *)buffer, xmod); ++ ++ /* Tags */ ++ memset(&new_tags, 0, sizeof(new_tags)); ++ in->serial++; ++ new_tags.chunk_id = 0; ++ new_tags.obj_id = in->obj_id; ++ new_tags.serial_number = in->serial; ++ ++ /* Add extra info for file header */ ++ new_tags.extra_available = 1; ++ new_tags.extra_parent_id = oh->parent_obj_id; ++ new_tags.extra_file_size = file_size; ++ new_tags.extra_is_shrink = oh->is_shrink; ++ new_tags.extra_equiv_id = oh->equiv_id; ++ new_tags.extra_shadows = (oh->shadows_obj > 0) ? 1 : 0; ++ new_tags.extra_obj_type = in->variant_type; ++ yaffs_verify_oh(in, oh, &new_tags, 1); ++ ++ /* Create new chunk in NAND */ ++ new_chunk_id = ++ yaffs_write_new_chunk(dev, buffer, &new_tags, ++ (prev_chunk_id > 0) ? 1 : 0); ++ ++ if (buffer) ++ yaffs_release_temp_buffer(dev, buffer); ++ ++ if (new_chunk_id < 0) ++ return new_chunk_id; ++ ++ in->hdr_chunk = new_chunk_id; ++ ++ if (prev_chunk_id > 0) ++ yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); ++ ++ if (!yaffs_obj_cache_dirty(in)) ++ in->dirty = 0; ++ ++ /* If this was a shrink, then mark the block ++ * that the chunk lives on */ ++ if (is_shrink) { ++ bi = yaffs_get_block_info(in->my_dev, ++ new_chunk_id / ++ in->my_dev->param.chunks_per_block); ++ bi->has_shrink_hdr = 1; ++ } ++ ++ ++ return new_chunk_id; ++} ++ ++/*--------------------- File read/write ------------------------ ++ * Read and write have very similar structures. ++ * In general the read/write has three parts to it ++ * An incomplete chunk to start with (if the read/write is not chunk-aligned) ++ * Some complete chunks ++ * An incomplete chunk to end off with ++ * ++ * Curve-balls: the first chunk might also be the last chunk. ++ */ ++ ++int yaffs_file_rd(struct yaffs_obj *in, u8 * buffer, loff_t offset, int n_bytes) ++{ ++ int chunk; ++ u32 start; ++ int n_copy; ++ int n = n_bytes; ++ int n_done = 0; ++ struct yaffs_cache *cache; ++ struct yaffs_dev *dev; ++ ++ dev = in->my_dev; ++ ++ while (n > 0) { ++ yaffs_addr_to_chunk(dev, offset, &chunk, &start); ++ chunk++; ++ ++ /* OK now check for the curveball where the start and end are in ++ * the same chunk. ++ */ ++ if ((start + n) < dev->data_bytes_per_chunk) ++ n_copy = n; ++ else ++ n_copy = dev->data_bytes_per_chunk - start; ++ ++ cache = yaffs_find_chunk_cache(in, chunk); ++ ++ /* If the chunk is already in the cache or it is less than ++ * a whole chunk or we're using inband tags then use the cache ++ * (if there is caching) else bypass the cache. ++ */ ++ if (cache || n_copy != dev->data_bytes_per_chunk || ++ dev->param.inband_tags) { ++ if (dev->param.n_caches > 0) { ++ ++ /* If we can't find the data in the cache, ++ * then load it up. */ ++ ++ if (!cache) { ++ cache = ++ yaffs_grab_chunk_cache(in->my_dev); ++ cache->object = in; ++ cache->chunk_id = chunk; ++ cache->dirty = 0; ++ cache->locked = 0; ++ yaffs_rd_data_obj(in, chunk, ++ cache->data); ++ cache->n_bytes = 0; ++ } ++ ++ yaffs_use_cache(dev, cache, 0); ++ ++ cache->locked = 1; ++ ++ memcpy(buffer, &cache->data[start], n_copy); ++ ++ cache->locked = 0; ++ } else { ++ /* Read into the local buffer then copy.. */ ++ ++ u8 *local_buffer = ++ yaffs_get_temp_buffer(dev); ++ yaffs_rd_data_obj(in, chunk, local_buffer); ++ ++ memcpy(buffer, &local_buffer[start], n_copy); ++ ++ yaffs_release_temp_buffer(dev, local_buffer); ++ } ++ } else { ++ /* A full chunk. Read directly into the buffer. */ ++ yaffs_rd_data_obj(in, chunk, buffer); ++ } ++ n -= n_copy; ++ offset += n_copy; ++ buffer += n_copy; ++ n_done += n_copy; ++ } ++ return n_done; ++} ++ ++int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset, ++ int n_bytes, int write_through) ++{ ++ ++ int chunk; ++ u32 start; ++ int n_copy; ++ int n = n_bytes; ++ int n_done = 0; ++ int n_writeback; ++ loff_t start_write = offset; ++ int chunk_written = 0; ++ u32 n_bytes_read; ++ loff_t chunk_start; ++ struct yaffs_dev *dev; ++ ++ dev = in->my_dev; ++ ++ while (n > 0 && chunk_written >= 0) { ++ yaffs_addr_to_chunk(dev, offset, &chunk, &start); ++ ++ if (((loff_t)chunk) * ++ dev->data_bytes_per_chunk + start != offset || ++ start >= dev->data_bytes_per_chunk) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "AddrToChunk of offset %lld gives chunk %d start %d", ++ offset, chunk, start); ++ } ++ chunk++; /* File pos to chunk in file offset */ ++ ++ /* OK now check for the curveball where the start and end are in ++ * the same chunk. ++ */ ++ ++ if ((start + n) < dev->data_bytes_per_chunk) { ++ n_copy = n; ++ ++ /* Now calculate how many bytes to write back.... ++ * If we're overwriting and not writing to then end of ++ * file then we need to write back as much as was there ++ * before. ++ */ ++ ++ chunk_start = (((loff_t)(chunk - 1)) * ++ dev->data_bytes_per_chunk); ++ ++ if (chunk_start > in->variant.file_variant.file_size) ++ n_bytes_read = 0; /* Past end of file */ ++ else ++ n_bytes_read = ++ in->variant.file_variant.file_size - ++ chunk_start; ++ ++ if (n_bytes_read > dev->data_bytes_per_chunk) ++ n_bytes_read = dev->data_bytes_per_chunk; ++ ++ n_writeback = ++ (n_bytes_read > ++ (start + n)) ? n_bytes_read : (start + n); ++ ++ if (n_writeback < 0 || ++ n_writeback > dev->data_bytes_per_chunk) ++ BUG(); ++ ++ } else { ++ n_copy = dev->data_bytes_per_chunk - start; ++ n_writeback = dev->data_bytes_per_chunk; ++ } ++ ++ if (n_copy != dev->data_bytes_per_chunk || ++ !dev->param.cache_bypass_aligned || ++ dev->param.inband_tags) { ++ /* An incomplete start or end chunk (or maybe both ++ * start and end chunk), or we're using inband tags, ++ * or we're forcing writes through the cache, ++ * so we want to use the cache buffers. ++ */ ++ if (dev->param.n_caches > 0) { ++ struct yaffs_cache *cache; ++ ++ /* If we can't find the data in the cache, then ++ * load the cache */ ++ cache = yaffs_find_chunk_cache(in, chunk); ++ ++ if (!cache && ++ yaffs_check_alloc_available(dev, 1)) { ++ cache = yaffs_grab_chunk_cache(dev); ++ cache->object = in; ++ cache->chunk_id = chunk; ++ cache->dirty = 0; ++ cache->locked = 0; ++ yaffs_rd_data_obj(in, chunk, ++ cache->data); ++ } else if (cache && ++ !cache->dirty && ++ !yaffs_check_alloc_available(dev, ++ 1)) { ++ /* Drop the cache if it was a read cache ++ * item and no space check has been made ++ * for it. ++ */ ++ cache = NULL; ++ } ++ ++ if (cache) { ++ yaffs_use_cache(dev, cache, 1); ++ cache->locked = 1; ++ ++ memcpy(&cache->data[start], buffer, ++ n_copy); ++ ++ cache->locked = 0; ++ cache->n_bytes = n_writeback; ++ ++ if (write_through) { ++ chunk_written = ++ yaffs_wr_data_obj ++ (cache->object, ++ cache->chunk_id, ++ cache->data, ++ cache->n_bytes, 1); ++ cache->dirty = 0; ++ } ++ } else { ++ chunk_written = -1; /* fail write */ ++ } ++ } else { ++ /* An incomplete start or end chunk (or maybe ++ * both start and end chunk). Read into the ++ * local buffer then copy over and write back. ++ */ ++ ++ u8 *local_buffer = yaffs_get_temp_buffer(dev); ++ ++ yaffs_rd_data_obj(in, chunk, local_buffer); ++ memcpy(&local_buffer[start], buffer, n_copy); ++ ++ chunk_written = ++ yaffs_wr_data_obj(in, chunk, ++ local_buffer, ++ n_writeback, 0); ++ ++ yaffs_release_temp_buffer(dev, local_buffer); ++ } ++ } else { ++ /* A full chunk. Write directly from the buffer. */ ++ ++ chunk_written = ++ yaffs_wr_data_obj(in, chunk, buffer, ++ dev->data_bytes_per_chunk, 0); ++ ++ /* Since we've overwritten the cached data, ++ * we better invalidate it. */ ++ yaffs_invalidate_chunk_cache(in, chunk); ++ } ++ ++ if (chunk_written >= 0) { ++ n -= n_copy; ++ offset += n_copy; ++ buffer += n_copy; ++ n_done += n_copy; ++ } ++ } ++ ++ /* Update file object */ ++ ++ if ((start_write + n_done) > in->variant.file_variant.file_size) ++ in->variant.file_variant.file_size = (start_write + n_done); ++ ++ in->dirty = 1; ++ return n_done; ++} ++ ++int yaffs_wr_file(struct yaffs_obj *in, const u8 *buffer, loff_t offset, ++ int n_bytes, int write_through) ++{ ++ yaffs2_handle_hole(in, offset); ++ return yaffs_do_file_wr(in, buffer, offset, n_bytes, write_through); ++} ++ ++/* ---------------------- File resizing stuff ------------------ */ ++ ++static void yaffs_prune_chunks(struct yaffs_obj *in, loff_t new_size) ++{ ++ ++ struct yaffs_dev *dev = in->my_dev; ++ loff_t old_size = in->variant.file_variant.file_size; ++ int i; ++ int chunk_id; ++ u32 dummy; ++ int last_del; ++ int start_del; ++ ++ if (old_size > 0) ++ yaffs_addr_to_chunk(dev, old_size - 1, &last_del, &dummy); ++ else ++ last_del = 0; ++ ++ yaffs_addr_to_chunk(dev, new_size + dev->data_bytes_per_chunk - 1, ++ &start_del, &dummy); ++ last_del++; ++ start_del++; ++ ++ /* Delete backwards so that we don't end up with holes if ++ * power is lost part-way through the operation. ++ */ ++ for (i = last_del; i >= start_del; i--) { ++ /* NB this could be optimised somewhat, ++ * eg. could retrieve the tags and write them without ++ * using yaffs_chunk_del ++ */ ++ ++ chunk_id = yaffs_find_del_file_chunk(in, i, NULL); ++ ++ if (chunk_id < 1) ++ continue; ++ ++ if (chunk_id < ++ (dev->internal_start_block * dev->param.chunks_per_block) || ++ chunk_id >= ++ ((dev->internal_end_block + 1) * ++ dev->param.chunks_per_block)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Found daft chunk_id %d for %d", ++ chunk_id, i); ++ } else { ++ in->n_data_chunks--; ++ yaffs_chunk_del(dev, chunk_id, 1, __LINE__); ++ } ++ } ++} ++ ++void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size) ++{ ++ int new_full; ++ u32 new_partial; ++ struct yaffs_dev *dev = obj->my_dev; ++ ++ yaffs_addr_to_chunk(dev, new_size, &new_full, &new_partial); ++ ++ yaffs_prune_chunks(obj, new_size); ++ ++ if (new_partial != 0) { ++ int last_chunk = 1 + new_full; ++ u8 *local_buffer = yaffs_get_temp_buffer(dev); ++ ++ /* Rewrite the last chunk with its new size and zero pad */ ++ yaffs_rd_data_obj(obj, last_chunk, local_buffer); ++ memset(local_buffer + new_partial, 0, ++ dev->data_bytes_per_chunk - new_partial); ++ ++ yaffs_wr_data_obj(obj, last_chunk, local_buffer, ++ new_partial, 1); ++ ++ yaffs_release_temp_buffer(dev, local_buffer); ++ } ++ ++ obj->variant.file_variant.file_size = new_size; ++ ++ yaffs_prune_tree(dev, &obj->variant.file_variant); ++} ++ ++int yaffs_resize_file(struct yaffs_obj *in, loff_t new_size) ++{ ++ struct yaffs_dev *dev = in->my_dev; ++ loff_t old_size = in->variant.file_variant.file_size; ++ ++ yaffs_flush_file_cache(in); ++ yaffs_invalidate_whole_cache(in); ++ ++ yaffs_check_gc(dev, 0); ++ ++ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) ++ return YAFFS_FAIL; ++ ++ if (new_size == old_size) ++ return YAFFS_OK; ++ ++ if (new_size > old_size) { ++ yaffs2_handle_hole(in, new_size); ++ in->variant.file_variant.file_size = new_size; ++ } else { ++ /* new_size < old_size */ ++ yaffs_resize_file_down(in, new_size); ++ } ++ ++ /* Write a new object header to reflect the resize. ++ * show we've shrunk the file, if need be ++ * Do this only if the file is not in the deleted directories ++ * and is not shadowed. ++ */ ++ if (in->parent && ++ !in->is_shadowed && ++ in->parent->obj_id != YAFFS_OBJECTID_UNLINKED && ++ in->parent->obj_id != YAFFS_OBJECTID_DELETED) ++ yaffs_update_oh(in, NULL, 0, 0, 0, NULL); ++ ++ return YAFFS_OK; ++} ++ ++int yaffs_flush_file(struct yaffs_obj *in, int update_time, int data_sync) ++{ ++ if (!in->dirty) ++ return YAFFS_OK; ++ ++ yaffs_flush_file_cache(in); ++ ++ if (data_sync) ++ return YAFFS_OK; ++ ++ if (update_time) ++ yaffs_load_current_time(in, 0, 0); ++ ++ return (yaffs_update_oh(in, NULL, 0, 0, 0, NULL) >= 0) ? ++ YAFFS_OK : YAFFS_FAIL; ++} ++ ++ ++/* yaffs_del_file deletes the whole file data ++ * and the inode associated with the file. ++ * It does not delete the links associated with the file. ++ */ ++static int yaffs_unlink_file_if_needed(struct yaffs_obj *in) ++{ ++ int ret_val; ++ int del_now = 0; ++ struct yaffs_dev *dev = in->my_dev; ++ ++ if (!in->my_inode) ++ del_now = 1; ++ ++ if (del_now) { ++ ret_val = ++ yaffs_change_obj_name(in, in->my_dev->del_dir, ++ _Y("deleted"), 0, 0); ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "yaffs: immediate deletion of file %d", ++ in->obj_id); ++ in->deleted = 1; ++ in->my_dev->n_deleted_files++; ++ if (dev->param.disable_soft_del || dev->param.is_yaffs2) ++ yaffs_resize_file(in, 0); ++ yaffs_soft_del_file(in); ++ } else { ++ ret_val = ++ yaffs_change_obj_name(in, in->my_dev->unlinked_dir, ++ _Y("unlinked"), 0, 0); ++ } ++ return ret_val; ++} ++ ++static int yaffs_del_file(struct yaffs_obj *in) ++{ ++ int ret_val = YAFFS_OK; ++ int deleted; /* Need to cache value on stack if in is freed */ ++ struct yaffs_dev *dev = in->my_dev; ++ ++ if (dev->param.disable_soft_del || dev->param.is_yaffs2) ++ yaffs_resize_file(in, 0); ++ ++ if (in->n_data_chunks > 0) { ++ /* Use soft deletion if there is data in the file. ++ * That won't be the case if it has been resized to zero. ++ */ ++ if (!in->unlinked) ++ ret_val = yaffs_unlink_file_if_needed(in); ++ ++ deleted = in->deleted; ++ ++ if (ret_val == YAFFS_OK && in->unlinked && !in->deleted) { ++ in->deleted = 1; ++ deleted = 1; ++ in->my_dev->n_deleted_files++; ++ yaffs_soft_del_file(in); ++ } ++ return deleted ? YAFFS_OK : YAFFS_FAIL; ++ } else { ++ /* The file has no data chunks so we toss it immediately */ ++ yaffs_free_tnode(in->my_dev, in->variant.file_variant.top); ++ in->variant.file_variant.top = NULL; ++ yaffs_generic_obj_del(in); ++ ++ return YAFFS_OK; ++ } ++} ++ ++int yaffs_is_non_empty_dir(struct yaffs_obj *obj) ++{ ++ return (obj && ++ obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) && ++ !(list_empty(&obj->variant.dir_variant.children)); ++} ++ ++static int yaffs_del_dir(struct yaffs_obj *obj) ++{ ++ /* First check that the directory is empty. */ ++ if (yaffs_is_non_empty_dir(obj)) ++ return YAFFS_FAIL; ++ ++ return yaffs_generic_obj_del(obj); ++} ++ ++static int yaffs_del_symlink(struct yaffs_obj *in) ++{ ++ kfree(in->variant.symlink_variant.alias); ++ in->variant.symlink_variant.alias = NULL; ++ ++ return yaffs_generic_obj_del(in); ++} ++ ++static int yaffs_del_link(struct yaffs_obj *in) ++{ ++ /* remove this hardlink from the list associated with the equivalent ++ * object ++ */ ++ list_del_init(&in->hard_links); ++ return yaffs_generic_obj_del(in); ++} ++ ++int yaffs_del_obj(struct yaffs_obj *obj) ++{ ++ int ret_val = -1; ++ ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ ret_val = yaffs_del_file(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ if (!list_empty(&obj->variant.dir_variant.dirty)) { ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, ++ "Remove object %d from dirty directories", ++ obj->obj_id); ++ list_del_init(&obj->variant.dir_variant.dirty); ++ } ++ return yaffs_del_dir(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ ret_val = yaffs_del_symlink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ ret_val = yaffs_del_link(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ ret_val = yaffs_generic_obj_del(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ ret_val = 0; ++ break; /* should not happen. */ ++ } ++ return ret_val; ++} ++ ++ ++static void yaffs_empty_dir_to_dir(struct yaffs_obj *from_dir, ++ struct yaffs_obj *to_dir) ++{ ++ struct yaffs_obj *obj; ++ struct list_head *lh; ++ struct list_head *n; ++ ++ list_for_each_safe(lh, n, &from_dir->variant.dir_variant.children) { ++ obj = list_entry(lh, struct yaffs_obj, siblings); ++ yaffs_add_obj_to_dir(to_dir, obj); ++ } ++} ++ ++struct yaffs_obj *yaffs_retype_obj(struct yaffs_obj *obj, ++ enum yaffs_obj_type type) ++{ ++ /* Tear down the old variant */ ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ /* Nuke file data */ ++ yaffs_resize_file(obj, 0); ++ yaffs_free_tnode(obj->my_dev, obj->variant.file_variant.top); ++ obj->variant.file_variant.top = NULL; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Put the children in lost and found. */ ++ yaffs_empty_dir_to_dir(obj, obj->my_dev->lost_n_found); ++ if (!list_empty(&obj->variant.dir_variant.dirty)) ++ list_del_init(&obj->variant.dir_variant.dirty); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ /* Nuke symplink data */ ++ kfree(obj->variant.symlink_variant.alias); ++ obj->variant.symlink_variant.alias = NULL; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ list_del_init(&obj->hard_links); ++ break; ++ default: ++ break; ++ } ++ ++ memset(&obj->variant, 0, sizeof(obj->variant)); ++ ++ /*Set up new variant if the memset is not enough. */ ++ switch (type) { ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ INIT_LIST_HEAD(&obj->variant.dir_variant.children); ++ INIT_LIST_HEAD(&obj->variant.dir_variant.dirty); ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ default: ++ break; ++ } ++ ++ obj->variant_type = type; ++ ++ return obj; ++ ++} ++ ++static int yaffs_unlink_worker(struct yaffs_obj *obj) ++{ ++ int del_now = 0; ++ ++ if (!obj) ++ return YAFFS_FAIL; ++ ++ if (!obj->my_inode) ++ del_now = 1; ++ ++ yaffs_update_parent(obj->parent); ++ ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { ++ return yaffs_del_link(obj); ++ } else if (!list_empty(&obj->hard_links)) { ++ /* Curve ball: We're unlinking an object that has a hardlink. ++ * ++ * This problem arises because we are not strictly following ++ * The Linux link/inode model. ++ * ++ * We can't really delete the object. ++ * Instead, we do the following: ++ * - Select a hardlink. ++ * - Unhook it from the hard links ++ * - Move it from its parent directory so that the rename works. ++ * - Rename the object to the hardlink's name. ++ * - Delete the hardlink ++ */ ++ ++ struct yaffs_obj *hl; ++ struct yaffs_obj *parent; ++ int ret_val; ++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ hl = list_entry(obj->hard_links.next, struct yaffs_obj, ++ hard_links); ++ ++ yaffs_get_obj_name(hl, name, YAFFS_MAX_NAME_LENGTH + 1); ++ parent = hl->parent; ++ ++ list_del_init(&hl->hard_links); ++ ++ yaffs_add_obj_to_dir(obj->my_dev->unlinked_dir, hl); ++ ++ ret_val = yaffs_change_obj_name(obj, parent, name, 0, 0); ++ ++ if (ret_val == YAFFS_OK) ++ ret_val = yaffs_generic_obj_del(hl); ++ ++ return ret_val; ++ ++ } else if (del_now) { ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return yaffs_del_file(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ list_del_init(&obj->variant.dir_variant.dirty); ++ return yaffs_del_dir(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ return yaffs_del_symlink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ return yaffs_generic_obj_del(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ default: ++ return YAFFS_FAIL; ++ } ++ } else if (yaffs_is_non_empty_dir(obj)) { ++ return YAFFS_FAIL; ++ } else { ++ return yaffs_change_obj_name(obj, obj->my_dev->unlinked_dir, ++ _Y("unlinked"), 0, 0); ++ } ++} ++ ++static int yaffs_unlink_obj(struct yaffs_obj *obj) ++{ ++ if (obj && obj->unlink_allowed) ++ return yaffs_unlink_worker(obj); ++ ++ return YAFFS_FAIL; ++} ++ ++int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR *name) ++{ ++ struct yaffs_obj *obj; ++ ++ obj = yaffs_find_by_name(dir, name); ++ return yaffs_unlink_obj(obj); ++} ++ ++/* Note: ++ * If old_name is NULL then we take old_dir as the object to be renamed. ++ */ ++int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR *old_name, ++ struct yaffs_obj *new_dir, const YCHAR *new_name) ++{ ++ struct yaffs_obj *obj = NULL; ++ struct yaffs_obj *existing_target = NULL; ++ int force = 0; ++ int result; ++ struct yaffs_dev *dev; ++ ++ if (!old_dir || old_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ BUG(); ++ return YAFFS_FAIL; ++ } ++ if (!new_dir || new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ BUG(); ++ return YAFFS_FAIL; ++ } ++ ++ dev = old_dir->my_dev; ++ ++#ifdef CONFIG_YAFFS_CASE_INSENSITIVE ++ /* Special case for case insemsitive systems. ++ * While look-up is case insensitive, the name isn't. ++ * Therefore we might want to change x.txt to X.txt ++ */ ++ if (old_dir == new_dir && ++ old_name && new_name && ++ strcmp(old_name, new_name) == 0) ++ force = 1; ++#endif ++ ++ if (strnlen(new_name, YAFFS_MAX_NAME_LENGTH + 1) > ++ YAFFS_MAX_NAME_LENGTH) ++ /* ENAMETOOLONG */ ++ return YAFFS_FAIL; ++ ++ if (old_name) ++ obj = yaffs_find_by_name(old_dir, old_name); ++ else{ ++ obj = old_dir; ++ old_dir = obj->parent; ++ } ++ ++ if (obj && obj->rename_allowed) { ++ /* Now handle an existing target, if there is one */ ++ existing_target = yaffs_find_by_name(new_dir, new_name); ++ if (yaffs_is_non_empty_dir(existing_target)) { ++ return YAFFS_FAIL; /* ENOTEMPTY */ ++ } else if (existing_target && existing_target != obj) { ++ /* Nuke the target first, using shadowing, ++ * but only if it isn't the same object. ++ * ++ * Note we must disable gc here otherwise it can mess ++ * up the shadowing. ++ * ++ */ ++ dev->gc_disable = 1; ++ yaffs_change_obj_name(obj, new_dir, new_name, force, ++ existing_target->obj_id); ++ existing_target->is_shadowed = 1; ++ yaffs_unlink_obj(existing_target); ++ dev->gc_disable = 0; ++ } ++ ++ result = yaffs_change_obj_name(obj, new_dir, new_name, 1, 0); ++ ++ yaffs_update_parent(old_dir); ++ if (new_dir != old_dir) ++ yaffs_update_parent(new_dir); ++ ++ return result; ++ } ++ return YAFFS_FAIL; ++} ++ ++/*----------------------- Initialisation Scanning ---------------------- */ ++ ++void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, ++ int backward_scanning) ++{ ++ struct yaffs_obj *obj; ++ ++ if (backward_scanning) { ++ /* Handle YAFFS2 case (backward scanning) ++ * If the shadowed object exists then ignore. ++ */ ++ obj = yaffs_find_by_number(dev, obj_id); ++ if (obj) ++ return; ++ } ++ ++ /* Let's create it (if it does not exist) assuming it is a file so that ++ * it can do shrinking etc. ++ * We put it in unlinked dir to be cleaned up after the scanning ++ */ ++ obj = ++ yaffs_find_or_create_by_number(dev, obj_id, YAFFS_OBJECT_TYPE_FILE); ++ if (!obj) ++ return; ++ obj->is_shadowed = 1; ++ yaffs_add_obj_to_dir(dev->unlinked_dir, obj); ++ obj->variant.file_variant.shrink_size = 0; ++ obj->valid = 1; /* So that we don't read any other info. */ ++} ++ ++void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list) ++{ ++ struct list_head *lh; ++ struct list_head *save; ++ struct yaffs_obj *hl; ++ struct yaffs_obj *in; ++ ++ list_for_each_safe(lh, save, hard_list) { ++ hl = list_entry(lh, struct yaffs_obj, hard_links); ++ in = yaffs_find_by_number(dev, ++ hl->variant.hardlink_variant.equiv_id); ++ ++ if (in) { ++ /* Add the hardlink pointers */ ++ hl->variant.hardlink_variant.equiv_obj = in; ++ list_add(&hl->hard_links, &in->hard_links); ++ } else { ++ /* Todo Need to report/handle this better. ++ * Got a problem... hardlink to a non-existant object ++ */ ++ hl->variant.hardlink_variant.equiv_obj = NULL; ++ INIT_LIST_HEAD(&hl->hard_links); ++ } ++ } ++} ++ ++static void yaffs_strip_deleted_objs(struct yaffs_dev *dev) ++{ ++ /* ++ * Sort out state of unlinked and deleted objects after scanning. ++ */ ++ struct list_head *i; ++ struct list_head *n; ++ struct yaffs_obj *l; ++ ++ if (dev->read_only) ++ return; ++ ++ /* Soft delete all the unlinked files */ ++ list_for_each_safe(i, n, ++ &dev->unlinked_dir->variant.dir_variant.children) { ++ l = list_entry(i, struct yaffs_obj, siblings); ++ yaffs_del_obj(l); ++ } ++ ++ list_for_each_safe(i, n, &dev->del_dir->variant.dir_variant.children) { ++ l = list_entry(i, struct yaffs_obj, siblings); ++ yaffs_del_obj(l); ++ } ++} ++ ++/* ++ * This code iterates through all the objects making sure that they are rooted. ++ * Any unrooted objects are re-rooted in lost+found. ++ * An object needs to be in one of: ++ * - Directly under deleted, unlinked ++ * - Directly or indirectly under root. ++ * ++ * Note: ++ * This code assumes that we don't ever change the current relationships ++ * between directories: ++ * root_dir->parent == unlinked_dir->parent == del_dir->parent == NULL ++ * lost-n-found->parent == root_dir ++ * ++ * This fixes the problem where directories might have inadvertently been ++ * deleted leaving the object "hanging" without being rooted in the ++ * directory tree. ++ */ ++ ++static int yaffs_has_null_parent(struct yaffs_dev *dev, struct yaffs_obj *obj) ++{ ++ return (obj == dev->del_dir || ++ obj == dev->unlinked_dir || obj == dev->root_dir); ++} ++ ++static void yaffs_fix_hanging_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_obj *parent; ++ int i; ++ struct list_head *lh; ++ struct list_head *n; ++ int depth_limit; ++ int hanging; ++ ++ if (dev->read_only) ++ return; ++ ++ /* Iterate through the objects in each hash entry, ++ * looking at each object. ++ * Make sure it is rooted. ++ */ ++ ++ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { ++ list_for_each_safe(lh, n, &dev->obj_bucket[i].list) { ++ obj = list_entry(lh, struct yaffs_obj, hash_link); ++ parent = obj->parent; ++ ++ if (yaffs_has_null_parent(dev, obj)) { ++ /* These directories are not hanging */ ++ hanging = 0; ++ } else if (!parent || ++ parent->variant_type != ++ YAFFS_OBJECT_TYPE_DIRECTORY) { ++ hanging = 1; ++ } else if (yaffs_has_null_parent(dev, parent)) { ++ hanging = 0; ++ } else { ++ /* ++ * Need to follow the parent chain to ++ * see if it is hanging. ++ */ ++ hanging = 0; ++ depth_limit = 100; ++ ++ while (parent != dev->root_dir && ++ parent->parent && ++ parent->parent->variant_type == ++ YAFFS_OBJECT_TYPE_DIRECTORY && ++ depth_limit > 0) { ++ parent = parent->parent; ++ depth_limit--; ++ } ++ if (parent != dev->root_dir) ++ hanging = 1; ++ } ++ if (hanging) { ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "Hanging object %d moved to lost and found", ++ obj->obj_id); ++ yaffs_add_obj_to_dir(dev->lost_n_found, obj); ++ } ++ } ++ } ++} ++ ++/* ++ * Delete directory contents for cleaning up lost and found. ++ */ ++static void yaffs_del_dir_contents(struct yaffs_obj *dir) ++{ ++ struct yaffs_obj *obj; ++ struct list_head *lh; ++ struct list_head *n; ++ ++ if (dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) ++ BUG(); ++ ++ list_for_each_safe(lh, n, &dir->variant.dir_variant.children) { ++ obj = list_entry(lh, struct yaffs_obj, siblings); ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) ++ yaffs_del_dir_contents(obj); ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "Deleting lost_found object %d", ++ obj->obj_id); ++ yaffs_unlink_obj(obj); ++ } ++} ++ ++static void yaffs_empty_l_n_f(struct yaffs_dev *dev) ++{ ++ yaffs_del_dir_contents(dev->lost_n_found); ++} ++ ++ ++struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *directory, ++ const YCHAR *name) ++{ ++ int sum; ++ struct list_head *i; ++ YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1]; ++ struct yaffs_obj *l; ++ ++ if (!name) ++ return NULL; ++ ++ if (!directory) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "tragedy: yaffs_find_by_name: null pointer directory" ++ ); ++ BUG(); ++ return NULL; ++ } ++ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "tragedy: yaffs_find_by_name: non-directory" ++ ); ++ BUG(); ++ } ++ ++ sum = yaffs_calc_name_sum(name); ++ ++ list_for_each(i, &directory->variant.dir_variant.children) { ++ l = list_entry(i, struct yaffs_obj, siblings); ++ ++ if (l->parent != directory) ++ BUG(); ++ ++ yaffs_check_obj_details_loaded(l); ++ ++ /* Special case for lost-n-found */ ++ if (l->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { ++ if (!strcmp(name, YAFFS_LOSTNFOUND_NAME)) ++ return l; ++ } else if (l->sum == sum || l->hdr_chunk <= 0) { ++ /* LostnFound chunk called Objxxx ++ * Do a real check ++ */ ++ yaffs_get_obj_name(l, buffer, ++ YAFFS_MAX_NAME_LENGTH + 1); ++ if (!strncmp(name, buffer, YAFFS_MAX_NAME_LENGTH)) ++ return l; ++ } ++ } ++ return NULL; ++} ++ ++/* GetEquivalentObject dereferences any hard links to get to the ++ * actual object. ++ */ ++ ++struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj) ++{ ++ if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { ++ obj = obj->variant.hardlink_variant.equiv_obj; ++ yaffs_check_obj_details_loaded(obj); ++ } ++ return obj; ++} ++ ++/* ++ * A note or two on object names. ++ * * If the object name is missing, we then make one up in the form objnnn ++ * ++ * * ASCII names are stored in the object header's name field from byte zero ++ * * Unicode names are historically stored starting from byte zero. ++ * ++ * Then there are automatic Unicode names... ++ * The purpose of these is to save names in a way that can be read as ++ * ASCII or Unicode names as appropriate, thus allowing a Unicode and ASCII ++ * system to share files. ++ * ++ * These automatic unicode are stored slightly differently... ++ * - If the name can fit in the ASCII character space then they are saved as ++ * ascii names as per above. ++ * - If the name needs Unicode then the name is saved in Unicode ++ * starting at oh->name[1]. ++ ++ */ ++static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR *name, ++ int buffer_size) ++{ ++ /* Create an object name if we could not find one. */ ++ if (strnlen(name, YAFFS_MAX_NAME_LENGTH) == 0) { ++ YCHAR local_name[20]; ++ YCHAR num_string[20]; ++ YCHAR *x = &num_string[19]; ++ unsigned v = obj->obj_id; ++ num_string[19] = 0; ++ while (v > 0) { ++ x--; ++ *x = '0' + (v % 10); ++ v /= 10; ++ } ++ /* make up a name */ ++ strcpy(local_name, YAFFS_LOSTNFOUND_PREFIX); ++ strcat(local_name, x); ++ strncpy(name, local_name, buffer_size - 1); ++ } ++} ++ ++int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size) ++{ ++ memset(name, 0, buffer_size * sizeof(YCHAR)); ++ yaffs_check_obj_details_loaded(obj); ++ if (obj->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { ++ strncpy(name, YAFFS_LOSTNFOUND_NAME, buffer_size - 1); ++ } else if (obj->short_name[0]) { ++ strcpy(name, obj->short_name); ++ } else if (obj->hdr_chunk > 0) { ++ int result; ++ u8 *buffer = yaffs_get_temp_buffer(obj->my_dev); ++ ++ struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer; ++ ++ memset(buffer, 0, obj->my_dev->data_bytes_per_chunk); ++ ++ if (obj->hdr_chunk > 0) { ++ result = yaffs_rd_chunk_tags_nand(obj->my_dev, ++ obj->hdr_chunk, ++ buffer, NULL); ++ } ++ yaffs_load_name_from_oh(obj->my_dev, name, oh->name, ++ buffer_size); ++ ++ yaffs_release_temp_buffer(obj->my_dev, buffer); ++ } ++ ++ yaffs_fix_null_name(obj, name, buffer_size); ++ ++ return strnlen(name, YAFFS_MAX_NAME_LENGTH); ++} ++ ++loff_t yaffs_get_obj_length(struct yaffs_obj *obj) ++{ ++ /* Dereference any hard linking */ ++ obj = yaffs_get_equivalent_obj(obj); ++ ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) ++ return obj->variant.file_variant.file_size; ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { ++ if (!obj->variant.symlink_variant.alias) ++ return 0; ++ return strnlen(obj->variant.symlink_variant.alias, ++ YAFFS_MAX_ALIAS_LENGTH); ++ } else { ++ /* Only a directory should drop through to here */ ++ return obj->my_dev->data_bytes_per_chunk; ++ } ++} ++ ++int yaffs_get_obj_link_count(struct yaffs_obj *obj) ++{ ++ int count = 0; ++ struct list_head *i; ++ ++ if (!obj->unlinked) ++ count++; /* the object itself */ ++ ++ list_for_each(i, &obj->hard_links) ++ count++; /* add the hard links; */ ++ ++ return count; ++} ++ ++int yaffs_get_obj_inode(struct yaffs_obj *obj) ++{ ++ obj = yaffs_get_equivalent_obj(obj); ++ ++ return obj->obj_id; ++} ++ ++unsigned yaffs_get_obj_type(struct yaffs_obj *obj) ++{ ++ obj = yaffs_get_equivalent_obj(obj); ++ ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return DT_REG; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ return DT_DIR; ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ return DT_LNK; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ return DT_REG; ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ if (S_ISFIFO(obj->yst_mode)) ++ return DT_FIFO; ++ if (S_ISCHR(obj->yst_mode)) ++ return DT_CHR; ++ if (S_ISBLK(obj->yst_mode)) ++ return DT_BLK; ++ if (S_ISSOCK(obj->yst_mode)) ++ return DT_SOCK; ++ return DT_REG; ++ break; ++ default: ++ return DT_REG; ++ break; ++ } ++} ++ ++YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj) ++{ ++ obj = yaffs_get_equivalent_obj(obj); ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) ++ return yaffs_clone_str(obj->variant.symlink_variant.alias); ++ else ++ return yaffs_clone_str(_Y("")); ++} ++ ++/*--------------------------- Initialisation code -------------------------- */ ++ ++static int yaffs_check_dev_fns(struct yaffs_dev *dev) ++{ ++ struct yaffs_driver *drv = &dev->drv; ++ struct yaffs_tags_handler *tagger = &dev->tagger; ++ ++ /* Common functions, gotta have */ ++ if (!drv->drv_read_chunk_fn || ++ !drv->drv_write_chunk_fn || ++ !drv->drv_erase_fn) ++ return 0; ++ ++ if (dev->param.is_yaffs2 && ++ (!drv->drv_mark_bad_fn || !drv->drv_check_bad_fn)) ++ return 0; ++ ++ /* Install the default tags marshalling functions if needed. */ ++ yaffs_tags_compat_install(dev); ++ yaffs_tags_marshall_install(dev); ++ ++ /* Check we now have the marshalling functions required. */ ++ if (!tagger->write_chunk_tags_fn || ++ !tagger->read_chunk_tags_fn || ++ !tagger->query_block_fn || ++ !tagger->mark_bad_fn) ++ return 0; ++ ++ return 1; ++} ++ ++static int yaffs_create_initial_dir(struct yaffs_dev *dev) ++{ ++ /* Initialise the unlinked, deleted, root and lost+found directories */ ++ dev->lost_n_found = dev->root_dir = NULL; ++ dev->unlinked_dir = dev->del_dir = NULL; ++ dev->unlinked_dir = ++ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR); ++ dev->del_dir = ++ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_DELETED, S_IFDIR); ++ dev->root_dir = ++ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_ROOT, ++ YAFFS_ROOT_MODE | S_IFDIR); ++ dev->lost_n_found = ++ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_LOSTNFOUND, ++ YAFFS_LOSTNFOUND_MODE | S_IFDIR); ++ ++ if (dev->lost_n_found && dev->root_dir && dev->unlinked_dir ++ && dev->del_dir) { ++ yaffs_add_obj_to_dir(dev->root_dir, dev->lost_n_found); ++ return YAFFS_OK; ++ } ++ return YAFFS_FAIL; ++} ++ ++/* Low level init. ++ * Typically only used by yaffs_guts_initialise, but also used by the ++ * Low level yaffs driver tests. ++ */ ++ ++int yaffs_guts_ll_init(struct yaffs_dev *dev) ++{ ++ ++ ++ yaffs_trace(YAFFS_TRACE_TRACING, "yaffs: yaffs_ll_init()"); ++ ++ if (!dev) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: Need a device" ++ ); ++ return YAFFS_FAIL; ++ } ++ ++ if (dev->ll_init) ++ return YAFFS_OK; ++ ++ dev->internal_start_block = dev->param.start_block; ++ dev->internal_end_block = dev->param.end_block; ++ dev->block_offset = 0; ++ dev->chunk_offset = 0; ++ dev->n_free_chunks = 0; ++ ++ dev->gc_block = 0; ++ ++ if (dev->param.start_block == 0) { ++ dev->internal_start_block = dev->param.start_block + 1; ++ dev->internal_end_block = dev->param.end_block + 1; ++ dev->block_offset = 1; ++ dev->chunk_offset = dev->param.chunks_per_block; ++ } ++ ++ /* Check geometry parameters. */ ++ ++ if ((!dev->param.inband_tags && dev->param.is_yaffs2 && ++ dev->param.total_bytes_per_chunk < 1024) || ++ (!dev->param.is_yaffs2 && ++ dev->param.total_bytes_per_chunk < 512) || ++ (dev->param.inband_tags && !dev->param.is_yaffs2) || ++ dev->param.chunks_per_block < 2 || ++ dev->param.n_reserved_blocks < 2 || ++ dev->internal_start_block <= 0 || ++ dev->internal_end_block <= 0 || ++ dev->internal_end_block <= ++ (dev->internal_start_block + dev->param.n_reserved_blocks + 2) ++ ) { ++ /* otherwise it is too small */ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "NAND geometry problems: chunk size %d, type is yaffs%s, inband_tags %d ", ++ dev->param.total_bytes_per_chunk, ++ dev->param.is_yaffs2 ? "2" : "", ++ dev->param.inband_tags); ++ return YAFFS_FAIL; ++ } ++ ++ /* Sort out space for inband tags, if required */ ++ if (dev->param.inband_tags) ++ dev->data_bytes_per_chunk = ++ dev->param.total_bytes_per_chunk - ++ sizeof(struct yaffs_packed_tags2_tags_only); ++ else ++ dev->data_bytes_per_chunk = dev->param.total_bytes_per_chunk; ++ ++ /* Got the right mix of functions? */ ++ if (!yaffs_check_dev_fns(dev)) { ++ /* Function missing */ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "device function(s) missing or wrong"); ++ ++ return YAFFS_FAIL; ++ } ++ ++ if (yaffs_init_nand(dev) != YAFFS_OK) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "InitialiseNAND failed"); ++ return YAFFS_FAIL; ++ } ++ ++ return YAFFS_OK; ++} ++ ++ ++int yaffs_guts_format_dev(struct yaffs_dev *dev) ++{ ++ int i; ++ enum yaffs_block_state state; ++ u32 dummy; ++ ++ if(yaffs_guts_ll_init(dev) != YAFFS_OK) ++ return YAFFS_FAIL; ++ ++ if(dev->is_mounted) ++ return YAFFS_FAIL; ++ ++ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ yaffs_query_init_block_state(dev, i, &state, &dummy); ++ if (state != YAFFS_BLOCK_STATE_DEAD) ++ yaffs_erase_block(dev, i); ++ } ++ ++ return YAFFS_OK; ++} ++ ++ ++int yaffs_guts_initialise(struct yaffs_dev *dev) ++{ ++ int init_failed = 0; ++ unsigned x; ++ int bits; ++ ++ if(yaffs_guts_ll_init(dev) != YAFFS_OK) ++ return YAFFS_FAIL; ++ ++ if (dev->is_mounted) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "device already mounted"); ++ return YAFFS_FAIL; ++ } ++ ++ dev->is_mounted = 1; ++ ++ /* OK now calculate a few things for the device */ ++ ++ /* ++ * Calculate all the chunk size manipulation numbers: ++ */ ++ x = dev->data_bytes_per_chunk; ++ /* We always use dev->chunk_shift and dev->chunk_div */ ++ dev->chunk_shift = calc_shifts(x); ++ x >>= dev->chunk_shift; ++ dev->chunk_div = x; ++ /* We only use chunk mask if chunk_div is 1 */ ++ dev->chunk_mask = (1 << dev->chunk_shift) - 1; ++ ++ /* ++ * Calculate chunk_grp_bits. ++ * We need to find the next power of 2 > than internal_end_block ++ */ ++ ++ x = dev->param.chunks_per_block * (dev->internal_end_block + 1); ++ ++ bits = calc_shifts_ceiling(x); ++ ++ /* Set up tnode width if wide tnodes are enabled. */ ++ if (!dev->param.wide_tnodes_disabled) { ++ /* bits must be even so that we end up with 32-bit words */ ++ if (bits & 1) ++ bits++; ++ if (bits < 16) ++ dev->tnode_width = 16; ++ else ++ dev->tnode_width = bits; ++ } else { ++ dev->tnode_width = 16; ++ } ++ ++ dev->tnode_mask = (1 << dev->tnode_width) - 1; ++ ++ /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled), ++ * so if the bitwidth of the ++ * chunk range we're using is greater than 16 we need ++ * to figure out chunk shift and chunk_grp_size ++ */ ++ ++ if (bits <= dev->tnode_width) ++ dev->chunk_grp_bits = 0; ++ else ++ dev->chunk_grp_bits = bits - dev->tnode_width; ++ ++ dev->tnode_size = (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8; ++ if (dev->tnode_size < sizeof(struct yaffs_tnode)) ++ dev->tnode_size = sizeof(struct yaffs_tnode); ++ ++ dev->chunk_grp_size = 1 << dev->chunk_grp_bits; ++ ++ if (dev->param.chunks_per_block < dev->chunk_grp_size) { ++ /* We have a problem because the soft delete won't work if ++ * the chunk group size > chunks per block. ++ * This can be remedied by using larger "virtual blocks". ++ */ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "chunk group too large"); ++ ++ return YAFFS_FAIL; ++ } ++ ++ /* Finished verifying the device, continue with initialisation */ ++ ++ /* More device initialisation */ ++ dev->all_gcs = 0; ++ dev->passive_gc_count = 0; ++ dev->oldest_dirty_gc_count = 0; ++ dev->bg_gcs = 0; ++ dev->gc_block_finder = 0; ++ dev->buffered_block = -1; ++ dev->doing_buffered_block_rewrite = 0; ++ dev->n_deleted_files = 0; ++ dev->n_bg_deletions = 0; ++ dev->n_unlinked_files = 0; ++ dev->n_ecc_fixed = 0; ++ dev->n_ecc_unfixed = 0; ++ dev->n_tags_ecc_fixed = 0; ++ dev->n_tags_ecc_unfixed = 0; ++ dev->n_erase_failures = 0; ++ dev->n_erased_blocks = 0; ++ dev->gc_disable = 0; ++ dev->has_pending_prioritised_gc = 1; ++ /* Assume the worst for now, will get fixed on first GC */ ++ INIT_LIST_HEAD(&dev->dirty_dirs); ++ dev->oldest_dirty_seq = 0; ++ dev->oldest_dirty_block = 0; ++ ++ /* Initialise temporary buffers and caches. */ ++ if (!yaffs_init_tmp_buffers(dev)) ++ init_failed = 1; ++ ++ dev->cache = NULL; ++ dev->gc_cleanup_list = NULL; ++ ++ if (!init_failed && dev->param.n_caches > 0) { ++ int i; ++ void *buf; ++ int cache_bytes = ++ dev->param.n_caches * sizeof(struct yaffs_cache); ++ ++ if (dev->param.n_caches > YAFFS_MAX_SHORT_OP_CACHES) ++ dev->param.n_caches = YAFFS_MAX_SHORT_OP_CACHES; ++ ++ dev->cache = kmalloc(cache_bytes, GFP_NOFS); ++ ++ buf = (u8 *) dev->cache; ++ ++ if (dev->cache) ++ memset(dev->cache, 0, cache_bytes); ++ ++ for (i = 0; i < dev->param.n_caches && buf; i++) { ++ dev->cache[i].object = NULL; ++ dev->cache[i].last_use = 0; ++ dev->cache[i].dirty = 0; ++ dev->cache[i].data = buf = ++ kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); ++ } ++ if (!buf) ++ init_failed = 1; ++ ++ dev->cache_last_use = 0; ++ } ++ ++ dev->cache_hits = 0; ++ ++ if (!init_failed) { ++ dev->gc_cleanup_list = ++ kmalloc(dev->param.chunks_per_block * sizeof(u32), ++ GFP_NOFS); ++ if (!dev->gc_cleanup_list) ++ init_failed = 1; ++ } ++ ++ if (dev->param.is_yaffs2) ++ dev->param.use_header_file_size = 1; ++ ++ if (!init_failed && !yaffs_init_blocks(dev)) ++ init_failed = 1; ++ ++ yaffs_init_tnodes_and_objs(dev); ++ ++ if (!init_failed && !yaffs_create_initial_dir(dev)) ++ init_failed = 1; ++ ++ if (!init_failed && dev->param.is_yaffs2 && ++ !dev->param.disable_summary && ++ !yaffs_summary_init(dev)) ++ init_failed = 1; ++ ++ if (!init_failed) { ++ /* Now scan the flash. */ ++ if (dev->param.is_yaffs2) { ++ if (yaffs2_checkpt_restore(dev)) { ++ yaffs_check_obj_details_loaded(dev->root_dir); ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT | ++ YAFFS_TRACE_MOUNT, ++ "yaffs: restored from checkpoint" ++ ); ++ } else { ++ ++ /* Clean up the mess caused by an aborted ++ * checkpoint load then scan backwards. ++ */ ++ yaffs_deinit_blocks(dev); ++ ++ yaffs_deinit_tnodes_and_objs(dev); ++ ++ dev->n_erased_blocks = 0; ++ dev->n_free_chunks = 0; ++ dev->alloc_block = -1; ++ dev->alloc_page = -1; ++ dev->n_deleted_files = 0; ++ dev->n_unlinked_files = 0; ++ dev->n_bg_deletions = 0; ++ ++ if (!init_failed && !yaffs_init_blocks(dev)) ++ init_failed = 1; ++ ++ yaffs_init_tnodes_and_objs(dev); ++ ++ if (!init_failed ++ && !yaffs_create_initial_dir(dev)) ++ init_failed = 1; ++ ++ if (!init_failed && !yaffs2_scan_backwards(dev)) ++ init_failed = 1; ++ } ++ } else if (!yaffs1_scan(dev)) { ++ init_failed = 1; ++ } ++ ++ yaffs_strip_deleted_objs(dev); ++ yaffs_fix_hanging_objs(dev); ++ if (dev->param.empty_lost_n_found) ++ yaffs_empty_l_n_f(dev); ++ } ++ ++ if (init_failed) { ++ /* Clean up the mess */ ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "yaffs: yaffs_guts_initialise() aborted."); ++ ++ yaffs_deinitialise(dev); ++ return YAFFS_FAIL; ++ } ++ ++ /* Zero out stats */ ++ dev->n_page_reads = 0; ++ dev->n_page_writes = 0; ++ dev->n_erasures = 0; ++ dev->n_gc_copies = 0; ++ dev->n_retried_writes = 0; ++ ++ dev->n_retired_blocks = 0; ++ ++ yaffs_verify_free_chunks(dev); ++ yaffs_verify_blocks(dev); ++ ++ /* Clean up any aborted checkpoint data */ ++ if (!dev->is_checkpointed && dev->blocks_in_checkpt > 0) ++ yaffs2_checkpt_invalidate(dev); ++ ++ yaffs_trace(YAFFS_TRACE_TRACING, ++ "yaffs: yaffs_guts_initialise() done."); ++ return YAFFS_OK; ++} ++ ++void yaffs_deinitialise(struct yaffs_dev *dev) ++{ ++ if (dev->is_mounted) { ++ int i; ++ ++ yaffs_deinit_blocks(dev); ++ yaffs_deinit_tnodes_and_objs(dev); ++ yaffs_summary_deinit(dev); ++ ++ if (dev->param.n_caches > 0 && dev->cache) { ++ ++ for (i = 0; i < dev->param.n_caches; i++) { ++ kfree(dev->cache[i].data); ++ dev->cache[i].data = NULL; ++ } ++ ++ kfree(dev->cache); ++ dev->cache = NULL; ++ } ++ ++ kfree(dev->gc_cleanup_list); ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) ++ kfree(dev->temp_buffer[i].buffer); ++ ++ dev->is_mounted = 0; ++ ++ yaffs_deinit_nand(dev); ++ } ++} ++ ++int yaffs_count_free_chunks(struct yaffs_dev *dev) ++{ ++ int n_free = 0; ++ int b; ++ struct yaffs_block_info *blk; ++ ++ blk = dev->block_info; ++ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { ++ switch (blk->block_state) { ++ case YAFFS_BLOCK_STATE_EMPTY: ++ case YAFFS_BLOCK_STATE_ALLOCATING: ++ case YAFFS_BLOCK_STATE_COLLECTING: ++ case YAFFS_BLOCK_STATE_FULL: ++ n_free += ++ (dev->param.chunks_per_block - blk->pages_in_use + ++ blk->soft_del_pages); ++ break; ++ default: ++ break; ++ } ++ blk++; ++ } ++ return n_free; ++} ++ ++int yaffs_get_n_free_chunks(struct yaffs_dev *dev) ++{ ++ /* This is what we report to the outside world */ ++ int n_free; ++ int n_dirty_caches; ++ int blocks_for_checkpt; ++ int i; ++ ++ n_free = dev->n_free_chunks; ++ n_free += dev->n_deleted_files; ++ ++ /* Now count and subtract the number of dirty chunks in the cache. */ ++ ++ for (n_dirty_caches = 0, i = 0; i < dev->param.n_caches; i++) { ++ if (dev->cache[i].dirty) ++ n_dirty_caches++; ++ } ++ ++ n_free -= n_dirty_caches; ++ ++ n_free -= ++ ((dev->param.n_reserved_blocks + 1) * dev->param.chunks_per_block); ++ ++ /* Now figure checkpoint space and report that... */ ++ blocks_for_checkpt = yaffs_calc_checkpt_blocks_required(dev); ++ ++ n_free -= (blocks_for_checkpt * dev->param.chunks_per_block); ++ ++ if (n_free < 0) ++ n_free = 0; ++ ++ return n_free; ++} ++ ++ ++ ++/* ++ * Marshalling functions to get loff_t file sizes into and out of ++ * object headers. ++ */ ++void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize) ++{ ++ oh->file_size_low = (fsize & 0xFFFFFFFF); ++ oh->file_size_high = ((fsize >> 32) & 0xFFFFFFFF); ++} ++ ++loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh) ++{ ++ loff_t retval; ++ ++ if (sizeof(loff_t) >= 8 && ~(oh->file_size_high)) ++ retval = (((loff_t) oh->file_size_high) << 32) | ++ (((loff_t) oh->file_size_low) & 0xFFFFFFFF); ++ else ++ retval = (loff_t) oh->file_size_low; ++ ++ return retval; ++} ++ ++ ++void yaffs_count_blocks_by_state(struct yaffs_dev *dev, int bs[10]) ++{ ++ int i; ++ struct yaffs_block_info *bi; ++ int s; ++ ++ for(i = 0; i < 10; i++) ++ bs[i] = 0; ++ ++ for(i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ bi = yaffs_get_block_info(dev, i); ++ s = bi->block_state; ++ if(s > YAFFS_BLOCK_STATE_DEAD || s < YAFFS_BLOCK_STATE_UNKNOWN) ++ bs[0]++; ++ else ++ bs[s]++; ++ } ++} +diff --git a/fs/yaffs2/yaffs_guts.h b/fs/yaffs2/yaffs_guts.h +new file mode 100644 +index 00000000..77bc7e99 +--- /dev/null ++++ b/fs/yaffs2/yaffs_guts.h +@@ -0,0 +1,1007 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_GUTS_H__ ++#define __YAFFS_GUTS_H__ ++ ++#include "yportenv.h" ++ ++#define YAFFS_OK 1 ++#define YAFFS_FAIL 0 ++ ++/* Give us a Y=0x59, ++ * Give us an A=0x41, ++ * Give us an FF=0xff ++ * Give us an S=0x53 ++ * And what have we got... ++ */ ++#define YAFFS_MAGIC 0x5941ff53 ++ ++/* ++ * Tnodes form a tree with the tnodes in "levels" ++ * Levels greater than 0 hold 8 slots which point to other tnodes. ++ * Those at level 0 hold 16 slots which point to chunks in NAND. ++ * ++ * A maximum level of 8 thust supports files of size up to: ++ * ++ * 2^(3*MAX_LEVEL+4) ++ * ++ * Thus a max level of 8 supports files with up to 2^^28 chunks which gives ++ * a maximum file size of around 512Gbytees with 2k chunks. ++ */ ++#define YAFFS_NTNODES_LEVEL0 16 ++#define YAFFS_TNODES_LEVEL0_BITS 4 ++#define YAFFS_TNODES_LEVEL0_MASK 0xf ++ ++#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2) ++#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1) ++#define YAFFS_TNODES_INTERNAL_MASK 0x7 ++#define YAFFS_TNODES_MAX_LEVEL 8 ++#define YAFFS_TNODES_MAX_BITS (YAFFS_TNODES_LEVEL0_BITS + \ ++ YAFFS_TNODES_INTERNAL_BITS * \ ++ YAFFS_TNODES_MAX_LEVEL) ++#define YAFFS_MAX_CHUNK_ID ((1 << YAFFS_TNODES_MAX_BITS) - 1) ++ ++#define YAFFS_MAX_FILE_SIZE_32 0x7fffffff ++ ++/* Constants for YAFFS1 mode */ ++#define YAFFS_BYTES_PER_SPARE 16 ++#define YAFFS_BYTES_PER_CHUNK 512 ++#define YAFFS_CHUNK_SIZE_SHIFT 9 ++#define YAFFS_CHUNKS_PER_BLOCK 32 ++#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK) ++ ++#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 ++#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 ++ ++ ++ ++#define YAFFS_ALLOCATION_NOBJECTS 100 ++#define YAFFS_ALLOCATION_NTNODES 100 ++#define YAFFS_ALLOCATION_NLINKS 100 ++ ++#define YAFFS_NOBJECT_BUCKETS 256 ++ ++#define YAFFS_OBJECT_SPACE 0x40000 ++#define YAFFS_MAX_OBJECT_ID (YAFFS_OBJECT_SPACE - 1) ++ ++/* Binary data version stamps */ ++#define YAFFS_SUMMARY_VERSION 1 ++#define YAFFS_CHECKPOINT_VERSION 7 ++ ++#ifdef CONFIG_YAFFS_UNICODE ++#define YAFFS_MAX_NAME_LENGTH 127 ++#define YAFFS_MAX_ALIAS_LENGTH 79 ++#else ++#define YAFFS_MAX_NAME_LENGTH 255 ++#define YAFFS_MAX_ALIAS_LENGTH 159 ++#endif ++ ++#define YAFFS_SHORT_NAME_LENGTH 15 ++ ++/* Some special object ids for pseudo objects */ ++#define YAFFS_OBJECTID_ROOT 1 ++#define YAFFS_OBJECTID_LOSTNFOUND 2 ++#define YAFFS_OBJECTID_UNLINKED 3 ++#define YAFFS_OBJECTID_DELETED 4 ++ ++/* Fake object Id for summary data */ ++#define YAFFS_OBJECTID_SUMMARY 0x10 ++ ++/* Pseudo object ids for checkpointing */ ++#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20 ++#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21 ++ ++#define YAFFS_MAX_SHORT_OP_CACHES 20 ++ ++#define YAFFS_N_TEMP_BUFFERS 6 ++ ++/* We limit the number attempts at sucessfully saving a chunk of data. ++ * Small-page devices have 32 pages per block; large-page devices have 64. ++ * Default to something in the order of 5 to 10 blocks worth of chunks. ++ */ ++#define YAFFS_WR_ATTEMPTS (5*64) ++ ++/* Sequence numbers are used in YAFFS2 to determine block allocation order. ++ * The range is limited slightly to help distinguish bad numbers from good. ++ * This also allows us to perhaps in the future use special numbers for ++ * special purposes. ++ * EFFFFF00 allows the allocation of 8 blocks/second (~1Mbytes) for 15 years, ++ * and is a larger number than the lifetime of a 2GB device. ++ */ ++#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000 ++#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xefffff00 ++ ++/* Special sequence number for bad block that failed to be marked bad */ ++#define YAFFS_SEQUENCE_BAD_BLOCK 0xffff0000 ++ ++/* ChunkCache is used for short read/write operations.*/ ++struct yaffs_cache { ++ struct yaffs_obj *object; ++ int chunk_id; ++ int last_use; ++ int dirty; ++ int n_bytes; /* Only valid if the cache is dirty */ ++ int locked; /* Can't push out or flush while locked. */ ++ u8 *data; ++}; ++ ++/* yaffs1 tags structures in RAM ++ * NB This uses bitfield. Bitfields should not straddle a u32 boundary ++ * otherwise the structure size will get blown out. ++ */ ++ ++struct yaffs_tags { ++ u32 chunk_id:20; ++ u32 serial_number:2; ++ u32 n_bytes_lsb:10; ++ u32 obj_id:18; ++ u32 ecc:12; ++ u32 n_bytes_msb:2; ++}; ++ ++union yaffs_tags_union { ++ struct yaffs_tags as_tags; ++ u8 as_bytes[8]; ++}; ++ ++ ++/* Stuff used for extended tags in YAFFS2 */ ++ ++enum yaffs_ecc_result { ++ YAFFS_ECC_RESULT_UNKNOWN, ++ YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_ECC_RESULT_FIXED, ++ YAFFS_ECC_RESULT_UNFIXED ++}; ++ ++enum yaffs_obj_type { ++ YAFFS_OBJECT_TYPE_UNKNOWN, ++ YAFFS_OBJECT_TYPE_FILE, ++ YAFFS_OBJECT_TYPE_SYMLINK, ++ YAFFS_OBJECT_TYPE_DIRECTORY, ++ YAFFS_OBJECT_TYPE_HARDLINK, ++ YAFFS_OBJECT_TYPE_SPECIAL ++}; ++ ++#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL ++ ++struct yaffs_ext_tags { ++ unsigned chunk_used; /* Status of the chunk: used or unused */ ++ unsigned obj_id; /* If 0 this is not used */ ++ unsigned chunk_id; /* If 0 this is a header, else a data chunk */ ++ unsigned n_bytes; /* Only valid for data chunks */ ++ ++ /* The following stuff only has meaning when we read */ ++ enum yaffs_ecc_result ecc_result; ++ unsigned block_bad; ++ ++ /* YAFFS 1 stuff */ ++ unsigned is_deleted; /* The chunk is marked deleted */ ++ unsigned serial_number; /* Yaffs1 2-bit serial number */ ++ ++ /* YAFFS2 stuff */ ++ unsigned seq_number; /* The sequence number of this block */ ++ ++ /* Extra info if this is an object header (YAFFS2 only) */ ++ ++ unsigned extra_available; /* Extra info available if not zero */ ++ unsigned extra_parent_id; /* The parent object */ ++ unsigned extra_is_shrink; /* Is it a shrink header? */ ++ unsigned extra_shadows; /* Does this shadow another object? */ ++ ++ enum yaffs_obj_type extra_obj_type; /* What object type? */ ++ ++ loff_t extra_file_size; /* Length if it is a file */ ++ unsigned extra_equiv_id; /* Equivalent object for a hard link */ ++}; ++ ++/* Spare structure for YAFFS1 */ ++struct yaffs_spare { ++ u8 tb0; ++ u8 tb1; ++ u8 tb2; ++ u8 tb3; ++ u8 page_status; /* set to 0 to delete the chunk */ ++ u8 block_status; ++ u8 tb4; ++ u8 tb5; ++ u8 ecc1[3]; ++ u8 tb6; ++ u8 tb7; ++ u8 ecc2[3]; ++}; ++ ++/*Special structure for passing through to mtd */ ++struct yaffs_nand_spare { ++ struct yaffs_spare spare; ++ int eccres1; ++ int eccres2; ++}; ++ ++/* Block data in RAM */ ++ ++enum yaffs_block_state { ++ YAFFS_BLOCK_STATE_UNKNOWN = 0, ++ ++ YAFFS_BLOCK_STATE_SCANNING, ++ /* Being scanned */ ++ ++ YAFFS_BLOCK_STATE_NEEDS_SCAN, ++ /* The block might have something on it (ie it is allocating or full, ++ * perhaps empty) but it needs to be scanned to determine its true ++ * state. ++ * This state is only valid during scanning. ++ * NB We tolerate empty because the pre-scanner might be incapable of ++ * deciding ++ * However, if this state is returned on a YAFFS2 device, ++ * then we expect a sequence number ++ */ ++ ++ YAFFS_BLOCK_STATE_EMPTY, ++ /* This block is empty */ ++ ++ YAFFS_BLOCK_STATE_ALLOCATING, ++ /* This block is partially allocated. ++ * At least one page holds valid data. ++ * This is the one currently being used for page ++ * allocation. Should never be more than one of these. ++ * If a block is only partially allocated at mount it is treated as ++ * full. ++ */ ++ ++ YAFFS_BLOCK_STATE_FULL, ++ /* All the pages in this block have been allocated. ++ * If a block was only partially allocated when mounted we treat ++ * it as fully allocated. ++ */ ++ ++ YAFFS_BLOCK_STATE_DIRTY, ++ /* The block was full and now all chunks have been deleted. ++ * Erase me, reuse me. ++ */ ++ ++ YAFFS_BLOCK_STATE_CHECKPOINT, ++ /* This block is assigned to holding checkpoint data. */ ++ ++ YAFFS_BLOCK_STATE_COLLECTING, ++ /* This block is being garbage collected */ ++ ++ YAFFS_BLOCK_STATE_DEAD ++ /* This block has failed and is not in use */ ++}; ++ ++#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1) ++ ++struct yaffs_block_info { ++ ++ s32 soft_del_pages:10; /* number of soft deleted pages */ ++ s32 pages_in_use:10; /* number of pages in use */ ++ u32 block_state:4; /* One of the above block states. */ ++ /* NB use unsigned because enum is sometimes ++ * an int */ ++ u32 needs_retiring:1; /* Data has failed on this block, */ ++ /*need to get valid data off and retire*/ ++ u32 skip_erased_check:1;/* Skip the erased check on this block */ ++ u32 gc_prioritise:1; /* An ECC check or blank check has failed. ++ Block should be prioritised for GC */ ++ u32 chunk_error_strikes:3; /* How many times we've had ecc etc ++ failures on this block and tried to reuse it */ ++ u32 has_summary:1; /* The block has a summary */ ++ ++ u32 has_shrink_hdr:1; /* This block has at least one shrink header */ ++ u32 seq_number; /* block sequence number for yaffs2 */ ++ ++}; ++ ++/* -------------------------- Object structure -------------------------------*/ ++/* This is the object structure as stored on NAND */ ++ ++struct yaffs_obj_hdr { ++ enum yaffs_obj_type type; ++ ++ /* Apply to everything */ ++ int parent_obj_id; ++ u16 sum_no_longer_used; /* checksum of name. No longer used */ ++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ /* The following apply to all object types except for hard links */ ++ u32 yst_mode; /* protection */ ++ ++ u32 yst_uid; ++ u32 yst_gid; ++ u32 yst_atime; ++ u32 yst_mtime; ++ u32 yst_ctime; ++ ++ /* File size applies to files only */ ++ u32 file_size_low; ++ ++ /* Equivalent object id applies to hard links only. */ ++ int equiv_id; ++ ++ /* Alias is for symlinks only. */ ++ YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1]; ++ ++ u32 yst_rdev; /* stuff for block and char devices (major/min) */ ++ ++ u32 win_ctime[2]; ++ u32 win_atime[2]; ++ u32 win_mtime[2]; ++ ++ u32 inband_shadowed_obj_id; ++ u32 inband_is_shrink; ++ ++ u32 file_size_high; ++ u32 reserved[1]; ++ int shadows_obj; /* This object header shadows the ++ specified object if > 0 */ ++ ++ /* is_shrink applies to object headers written when wemake a hole. */ ++ u32 is_shrink; ++ ++}; ++ ++/*--------------------------- Tnode -------------------------- */ ++ ++struct yaffs_tnode { ++ struct yaffs_tnode *internal[YAFFS_NTNODES_INTERNAL]; ++}; ++ ++/*------------------------ Object -----------------------------*/ ++/* An object can be one of: ++ * - a directory (no data, has children links ++ * - a regular file (data.... not prunes :->). ++ * - a symlink [symbolic link] (the alias). ++ * - a hard link ++ */ ++ ++struct yaffs_file_var { ++ loff_t file_size; ++ loff_t scanned_size; ++ loff_t shrink_size; ++ int top_level; ++ struct yaffs_tnode *top; ++}; ++ ++struct yaffs_dir_var { ++ struct list_head children; /* list of child links */ ++ struct list_head dirty; /* Entry for list of dirty directories */ ++}; ++ ++struct yaffs_symlink_var { ++ YCHAR *alias; ++}; ++ ++struct yaffs_hardlink_var { ++ struct yaffs_obj *equiv_obj; ++ u32 equiv_id; ++}; ++ ++union yaffs_obj_var { ++ struct yaffs_file_var file_variant; ++ struct yaffs_dir_var dir_variant; ++ struct yaffs_symlink_var symlink_variant; ++ struct yaffs_hardlink_var hardlink_variant; ++}; ++ ++struct yaffs_obj { ++ u8 deleted:1; /* This should only apply to unlinked files. */ ++ u8 soft_del:1; /* it has also been soft deleted */ ++ u8 unlinked:1; /* An unlinked file.*/ ++ u8 fake:1; /* A fake object has no presence on NAND. */ ++ u8 rename_allowed:1; /* Some objects cannot be renamed. */ ++ u8 unlink_allowed:1; ++ u8 dirty:1; /* the object needs to be written to flash */ ++ u8 valid:1; /* When the file system is being loaded up, this ++ * object might be created before the data ++ * is available ++ * ie. file data chunks encountered before ++ * the header. ++ */ ++ u8 lazy_loaded:1; /* This object has been lazy loaded and ++ * is missing some detail */ ++ ++ u8 defered_free:1; /* Object is removed from NAND, but is ++ * still in the inode cache. ++ * Free of object is defered. ++ * until the inode is released. ++ */ ++ u8 being_created:1; /* This object is still being created ++ * so skip some verification checks. */ ++ u8 is_shadowed:1; /* This object is shadowed on the way ++ * to being renamed. */ ++ ++ u8 xattr_known:1; /* We know if this has object has xattribs ++ * or not. */ ++ u8 has_xattr:1; /* This object has xattribs. ++ * Only valid if xattr_known. */ ++ ++ u8 serial; /* serial number of chunk in NAND.*/ ++ u16 sum; /* sum of the name to speed searching */ ++ ++ struct yaffs_dev *my_dev; /* The device I'm on */ ++ ++ struct list_head hash_link; /* list of objects in hash bucket */ ++ ++ struct list_head hard_links; /* hard linked object chain*/ ++ ++ /* directory structure stuff */ ++ /* also used for linking up the free list */ ++ struct yaffs_obj *parent; ++ struct list_head siblings; ++ ++ /* Where's my object header in NAND? */ ++ int hdr_chunk; ++ ++ int n_data_chunks; /* Number of data chunks for this file. */ ++ ++ u32 obj_id; /* the object id value */ ++ ++ u32 yst_mode; ++ ++ YCHAR short_name[YAFFS_SHORT_NAME_LENGTH + 1]; ++ ++#ifdef CONFIG_YAFFS_WINCE ++ u32 win_ctime[2]; ++ u32 win_mtime[2]; ++ u32 win_atime[2]; ++#else ++ u32 yst_uid; ++ u32 yst_gid; ++ u32 yst_atime; ++ u32 yst_mtime; ++ u32 yst_ctime; ++#endif ++ ++ u32 yst_rdev; ++ ++ void *my_inode; ++ ++ enum yaffs_obj_type variant_type; ++ ++ union yaffs_obj_var variant; ++ ++}; ++ ++struct yaffs_obj_bucket { ++ struct list_head list; ++ int count; ++}; ++ ++/* yaffs_checkpt_obj holds the definition of an object as dumped ++ * by checkpointing. ++ */ ++ ++struct yaffs_checkpt_obj { ++ int struct_type; ++ u32 obj_id; ++ u32 parent_id; ++ int hdr_chunk; ++ enum yaffs_obj_type variant_type:3; ++ u8 deleted:1; ++ u8 soft_del:1; ++ u8 unlinked:1; ++ u8 fake:1; ++ u8 rename_allowed:1; ++ u8 unlink_allowed:1; ++ u8 serial; ++ int n_data_chunks; ++ loff_t size_or_equiv_obj; ++}; ++ ++/*--------------------- Temporary buffers ---------------- ++ * ++ * These are chunk-sized working buffers. Each device has a few. ++ */ ++ ++struct yaffs_buffer { ++ u8 *buffer; ++ int in_use; ++}; ++ ++/*----------------- Device ---------------------------------*/ ++ ++struct yaffs_param { ++ const YCHAR *name; ++ ++ /* ++ * Entry parameters set up way early. Yaffs sets up the rest. ++ * The structure should be zeroed out before use so that unused ++ * and default values are zero. ++ */ ++ ++ int inband_tags; /* Use unband tags */ ++ u32 total_bytes_per_chunk; /* Should be >= 512, does not need to ++ be a power of 2 */ ++ int chunks_per_block; /* does not need to be a power of 2 */ ++ int spare_bytes_per_chunk; /* spare area size */ ++ int start_block; /* Start block we're allowed to use */ ++ int end_block; /* End block we're allowed to use */ ++ int n_reserved_blocks; /* Tuneable so that we can reduce ++ * reserved blocks on NOR and RAM. */ ++ ++ int n_caches; /* If <= 0, then short op caching is disabled, ++ * else the number of short op caches. ++ */ ++ int cache_bypass_aligned; /* If non-zero then bypass the cache for ++ * aligned writes. ++ */ ++ ++ int use_nand_ecc; /* Flag to decide whether or not to use ++ * NAND driver ECC on data (yaffs1) */ ++ int tags_9bytes; /* Use 9 byte tags */ ++ int no_tags_ecc; /* Flag to decide whether or not to do ECC ++ * on packed tags (yaffs2) */ ++ ++ int is_yaffs2; /* Use yaffs2 mode on this device */ ++ ++ int empty_lost_n_found; /* Auto-empty lost+found directory on mount */ ++ ++ int refresh_period; /* How often to check for a block refresh */ ++ ++ /* Checkpoint control. Can be set before or after initialisation */ ++ u8 skip_checkpt_rd; ++ u8 skip_checkpt_wr; ++ ++ int enable_xattr; /* Enable xattribs */ ++ ++ int max_objects; /* ++ * Set to limit the number of objects created. ++ * 0 = no limit. ++ */ ++ ++ /* The remove_obj_fn function must be supplied by OS flavours that ++ * need it. ++ * yaffs direct uses it to implement the faster readdir. ++ * Linux uses it to protect the directory during unlocking. ++ */ ++ void (*remove_obj_fn) (struct yaffs_obj *obj); ++ ++ /* Callback to mark the superblock dirty */ ++ void (*sb_dirty_fn) (struct yaffs_dev *dev); ++ ++ /* Callback to control garbage collection. */ ++ unsigned (*gc_control_fn) (struct yaffs_dev *dev); ++ ++ /* Debug control flags. Don't use unless you know what you're doing */ ++ int use_header_file_size; /* Flag to determine if we should use ++ * file sizes from the header */ ++ int disable_lazy_load; /* Disable lazy loading on this device */ ++ int wide_tnodes_disabled; /* Set to disable wide tnodes */ ++ int disable_soft_del; /* yaffs 1 only: Set to disable the use of ++ * softdeletion. */ ++ ++ int defered_dir_update; /* Set to defer directory updates */ ++ ++#ifdef CONFIG_YAFFS_AUTO_UNICODE ++ int auto_unicode; ++#endif ++ int always_check_erased; /* Force chunk erased check always on */ ++ ++ int disable_summary; ++ int disable_bad_block_marking; ++ ++}; ++ ++struct yaffs_driver { ++ int (*drv_write_chunk_fn) (struct yaffs_dev *dev, int nand_chunk, ++ const u8 *data, int data_len, ++ const u8 *oob, int oob_len); ++ int (*drv_read_chunk_fn) (struct yaffs_dev *dev, int nand_chunk, ++ u8 *data, int data_len, ++ u8 *oob, int oob_len, ++ enum yaffs_ecc_result *ecc_result); ++ int (*drv_erase_fn) (struct yaffs_dev *dev, int block_no); ++ int (*drv_mark_bad_fn) (struct yaffs_dev *dev, int block_no); ++ int (*drv_check_bad_fn) (struct yaffs_dev *dev, int block_no); ++ int (*drv_initialise_fn) (struct yaffs_dev *dev); ++ int (*drv_deinitialise_fn) (struct yaffs_dev *dev); ++}; ++ ++struct yaffs_tags_handler { ++ int (*write_chunk_tags_fn) (struct yaffs_dev *dev, ++ int nand_chunk, const u8 *data, ++ const struct yaffs_ext_tags *tags); ++ int (*read_chunk_tags_fn) (struct yaffs_dev *dev, ++ int nand_chunk, u8 *data, ++ struct yaffs_ext_tags *tags); ++ ++ int (*query_block_fn) (struct yaffs_dev *dev, int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number); ++ int (*mark_bad_fn) (struct yaffs_dev *dev, int block_no); ++}; ++ ++struct yaffs_dev { ++ struct yaffs_param param; ++ struct yaffs_driver drv; ++ struct yaffs_tags_handler tagger; ++ ++ /* Context storage. Holds extra OS specific data for this device */ ++ ++ void *os_context; ++ void *driver_context; ++ ++ struct list_head dev_list; ++ ++ int ll_init; ++ /* Runtime parameters. Set up by YAFFS. */ ++ int data_bytes_per_chunk; ++ ++ /* Non-wide tnode stuff */ ++ u16 chunk_grp_bits; /* Number of bits that need to be resolved if ++ * the tnodes are not wide enough. ++ */ ++ u16 chunk_grp_size; /* == 2^^chunk_grp_bits */ ++ ++ /* Stuff to support wide tnodes */ ++ u32 tnode_width; ++ u32 tnode_mask; ++ u32 tnode_size; ++ ++ /* Stuff for figuring out file offset to chunk conversions */ ++ u32 chunk_shift; /* Shift value */ ++ u32 chunk_div; /* Divisor after shifting: 1 for 2^n sizes */ ++ u32 chunk_mask; /* Mask to use for power-of-2 case */ ++ ++ int is_mounted; ++ int read_only; ++ int is_checkpointed; ++ ++ /* Stuff to support block offsetting to support start block zero */ ++ int internal_start_block; ++ int internal_end_block; ++ int block_offset; ++ int chunk_offset; ++ ++ /* Runtime checkpointing stuff */ ++ int checkpt_page_seq; /* running sequence number of checkpt pages */ ++ int checkpt_byte_count; ++ int checkpt_byte_offs; ++ u8 *checkpt_buffer; ++ int checkpt_open_write; ++ int blocks_in_checkpt; ++ int checkpt_cur_chunk; ++ int checkpt_cur_block; ++ int checkpt_next_block; ++ int *checkpt_block_list; ++ int checkpt_max_blocks; ++ u32 checkpt_sum; ++ u32 checkpt_xor; ++ ++ int checkpoint_blocks_required; /* Number of blocks needed to store ++ * current checkpoint set */ ++ ++ /* Block Info */ ++ struct yaffs_block_info *block_info; ++ u8 *chunk_bits; /* bitmap of chunks in use */ ++ u8 block_info_alt:1; /* allocated using alternative alloc */ ++ u8 chunk_bits_alt:1; /* allocated using alternative alloc */ ++ int chunk_bit_stride; /* Number of bytes of chunk_bits per block. ++ * Must be consistent with chunks_per_block. ++ */ ++ ++ int n_erased_blocks; ++ int alloc_block; /* Current block being allocated off */ ++ u32 alloc_page; ++ int alloc_block_finder; /* Used to search for next allocation block */ ++ ++ /* Object and Tnode memory management */ ++ void *allocator; ++ int n_obj; ++ int n_tnodes; ++ ++ int n_hardlinks; ++ ++ struct yaffs_obj_bucket obj_bucket[YAFFS_NOBJECT_BUCKETS]; ++ u32 bucket_finder; ++ ++ int n_free_chunks; ++ ++ /* Garbage collection control */ ++ u32 *gc_cleanup_list; /* objects to delete at the end of a GC. */ ++ u32 n_clean_ups; ++ ++ unsigned has_pending_prioritised_gc; /* We think this device might ++ have pending prioritised gcs */ ++ unsigned gc_disable; ++ unsigned gc_block_finder; ++ unsigned gc_dirtiest; ++ unsigned gc_pages_in_use; ++ unsigned gc_not_done; ++ unsigned gc_block; ++ unsigned gc_chunk; ++ unsigned gc_skip; ++ struct yaffs_summary_tags *gc_sum_tags; ++ ++ /* Special directories */ ++ struct yaffs_obj *root_dir; ++ struct yaffs_obj *lost_n_found; ++ ++ int buffered_block; /* Which block is buffered here? */ ++ int doing_buffered_block_rewrite; ++ ++ struct yaffs_cache *cache; ++ int cache_last_use; ++ ++ /* Stuff for background deletion and unlinked files. */ ++ struct yaffs_obj *unlinked_dir; /* Directory where unlinked and deleted ++ files live. */ ++ struct yaffs_obj *del_dir; /* Directory where deleted objects are ++ sent to disappear. */ ++ struct yaffs_obj *unlinked_deletion; /* Current file being ++ background deleted. */ ++ int n_deleted_files; /* Count of files awaiting deletion; */ ++ int n_unlinked_files; /* Count of unlinked files. */ ++ int n_bg_deletions; /* Count of background deletions. */ ++ ++ /* Temporary buffer management */ ++ struct yaffs_buffer temp_buffer[YAFFS_N_TEMP_BUFFERS]; ++ int max_temp; ++ int temp_in_use; ++ int unmanaged_buffer_allocs; ++ int unmanaged_buffer_deallocs; ++ ++ /* yaffs2 runtime stuff */ ++ unsigned seq_number; /* Sequence number of currently ++ allocating block */ ++ unsigned oldest_dirty_seq; ++ unsigned oldest_dirty_block; ++ ++ /* Block refreshing */ ++ int refresh_skip; /* A skip down counter. ++ * Refresh happens when this gets to zero. */ ++ ++ /* Dirty directory handling */ ++ struct list_head dirty_dirs; /* List of dirty directories */ ++ ++ /* Summary */ ++ int chunks_per_summary; ++ struct yaffs_summary_tags *sum_tags; ++ ++ /* Statistics */ ++ u32 n_page_writes; ++ u32 n_page_reads; ++ u32 n_erasures; ++ u32 n_bad_queries; ++ u32 n_bad_markings; ++ u32 n_erase_failures; ++ u32 n_gc_copies; ++ u32 all_gcs; ++ u32 passive_gc_count; ++ u32 oldest_dirty_gc_count; ++ u32 n_gc_blocks; ++ u32 bg_gcs; ++ u32 n_retried_writes; ++ u32 n_retired_blocks; ++ u32 n_ecc_fixed; ++ u32 n_ecc_unfixed; ++ u32 n_tags_ecc_fixed; ++ u32 n_tags_ecc_unfixed; ++ u32 n_deletions; ++ u32 n_unmarked_deletions; ++ u32 refresh_count; ++ u32 cache_hits; ++ u32 tags_used; ++ u32 summary_used; ++ ++}; ++ ++/* The CheckpointDevice structure holds the device information that changes ++ *at runtime and must be preserved over unmount/mount cycles. ++ */ ++struct yaffs_checkpt_dev { ++ int struct_type; ++ int n_erased_blocks; ++ int alloc_block; /* Current block being allocated off */ ++ u32 alloc_page; ++ int n_free_chunks; ++ ++ int n_deleted_files; /* Count of files awaiting deletion; */ ++ int n_unlinked_files; /* Count of unlinked files. */ ++ int n_bg_deletions; /* Count of background deletions. */ ++ ++ /* yaffs2 runtime stuff */ ++ unsigned seq_number; /* Sequence number of currently ++ * allocating block */ ++ ++}; ++ ++struct yaffs_checkpt_validity { ++ int struct_type; ++ u32 magic; ++ u32 version; ++ u32 head; ++}; ++ ++struct yaffs_shadow_fixer { ++ int obj_id; ++ int shadowed_id; ++ struct yaffs_shadow_fixer *next; ++}; ++ ++/* Structure for doing xattr modifications */ ++struct yaffs_xattr_mod { ++ int set; /* If 0 then this is a deletion */ ++ const YCHAR *name; ++ const void *data; ++ int size; ++ int flags; ++ int result; ++}; ++ ++/*----------------------- YAFFS Functions -----------------------*/ ++ ++int yaffs_guts_initialise(struct yaffs_dev *dev); ++void yaffs_deinitialise(struct yaffs_dev *dev); ++ ++int yaffs_get_n_free_chunks(struct yaffs_dev *dev); ++ ++int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, ++ struct yaffs_obj *new_dir, const YCHAR * new_name); ++ ++int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name); ++int yaffs_del_obj(struct yaffs_obj *obj); ++struct yaffs_obj *yaffs_retype_obj(struct yaffs_obj *obj, ++ enum yaffs_obj_type type); ++ ++ ++int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size); ++loff_t yaffs_get_obj_length(struct yaffs_obj *obj); ++int yaffs_get_obj_inode(struct yaffs_obj *obj); ++unsigned yaffs_get_obj_type(struct yaffs_obj *obj); ++int yaffs_get_obj_link_count(struct yaffs_obj *obj); ++ ++/* File operations */ ++int yaffs_file_rd(struct yaffs_obj *obj, u8 * buffer, loff_t offset, ++ int n_bytes); ++int yaffs_wr_file(struct yaffs_obj *obj, const u8 * buffer, loff_t offset, ++ int n_bytes, int write_trhrough); ++int yaffs_resize_file(struct yaffs_obj *obj, loff_t new_size); ++ ++struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid); ++ ++int yaffs_flush_file(struct yaffs_obj *obj, int update_time, int data_sync); ++ ++/* Flushing and checkpointing */ ++void yaffs_flush_whole_cache(struct yaffs_dev *dev); ++ ++int yaffs_checkpoint_save(struct yaffs_dev *dev); ++int yaffs_checkpoint_restore(struct yaffs_dev *dev); ++ ++/* Directory operations */ ++struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name, ++ u32 mode, u32 uid, u32 gid); ++struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *the_dir, ++ const YCHAR *name); ++struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number); ++ ++/* Link operations */ ++struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR *name, ++ struct yaffs_obj *equiv_obj); ++ ++struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj); ++ ++/* Symlink operations */ ++struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid, const YCHAR *alias); ++YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj); ++ ++/* Special inodes (fifos, sockets and devices) */ ++struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, ++ const YCHAR *name, u32 mode, u32 uid, ++ u32 gid, u32 rdev); ++ ++int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR *name, ++ const void *value, int size, int flags); ++int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR *name, void *value, ++ int size); ++int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size); ++int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR *name); ++ ++/* Special directories */ ++struct yaffs_obj *yaffs_root(struct yaffs_dev *dev); ++struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev); ++ ++void yaffs_handle_defered_free(struct yaffs_obj *obj); ++ ++void yaffs_update_dirty_dirs(struct yaffs_dev *dev); ++ ++int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency); ++ ++/* Debug dump */ ++int yaffs_dump_obj(struct yaffs_obj *obj); ++ ++void yaffs_guts_test(struct yaffs_dev *dev); ++int yaffs_guts_ll_init(struct yaffs_dev *dev); ++ ++ ++/* A few useful functions to be used within the core files*/ ++void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, ++ int lyn); ++int yaffs_check_ff(u8 *buffer, int n_bytes); ++void yaffs_handle_chunk_error(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi); ++ ++u8 *yaffs_get_temp_buffer(struct yaffs_dev *dev); ++void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer); ++ ++struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, ++ int number, ++ enum yaffs_obj_type type); ++int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, ++ int nand_chunk, int in_scan); ++void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR *name); ++void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, ++ const struct yaffs_obj_hdr *oh); ++void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj); ++YCHAR *yaffs_clone_str(const YCHAR *str); ++void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list); ++void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no); ++int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, ++ int force, int is_shrink, int shadows, ++ struct yaffs_xattr_mod *xop); ++void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, ++ int backward_scanning); ++int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks); ++struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev); ++struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, ++ struct yaffs_file_var *file_struct, ++ u32 chunk_id, ++ struct yaffs_tnode *passed_tn); ++ ++int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset, ++ int n_bytes, int write_trhrough); ++void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size); ++void yaffs_skip_rest_of_block(struct yaffs_dev *dev); ++ ++int yaffs_count_free_chunks(struct yaffs_dev *dev); ++ ++struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, ++ struct yaffs_file_var *file_struct, ++ u32 chunk_id); ++ ++u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, ++ unsigned pos); ++ ++int yaffs_is_non_empty_dir(struct yaffs_obj *obj); ++ ++int yaffs_guts_format_dev(struct yaffs_dev *dev); ++ ++void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, ++ int *chunk_out, u32 *offset_out); ++/* ++ * Marshalling functions to get loff_t file sizes into aand out of ++ * object headers. ++ */ ++void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize); ++loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh); ++loff_t yaffs_max_file_size(struct yaffs_dev *dev); ++ ++/* ++ * Debug function to count number of blocks in each state ++ * NB Needs to be called with correct number of integers ++ */ ++ ++void yaffs_count_blocks_by_state(struct yaffs_dev *dev, int bs[10]); ++ ++int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, ++ struct yaffs_ext_tags *tags); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_linux.h b/fs/yaffs2/yaffs_linux.h +new file mode 100644 +index 00000000..c20ab14b +--- /dev/null ++++ b/fs/yaffs2/yaffs_linux.h +@@ -0,0 +1,48 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_LINUX_H__ ++#define __YAFFS_LINUX_H__ ++ ++#include "yportenv.h" ++ ++struct yaffs_linux_context { ++ struct list_head context_list; /* List of these we have mounted */ ++ struct yaffs_dev *dev; ++ struct super_block *super; ++ struct task_struct *bg_thread; /* Background thread for this device */ ++ int bg_running; ++ struct mutex gross_lock; /* Gross locking mutex*/ ++ u8 *spare_buffer; /* For mtdif2 use. Don't know the buffer size ++ * at compile time so we have to allocate it. ++ */ ++ struct list_head search_contexts; ++ struct task_struct *readdir_process; ++ unsigned mount_id; ++ int dirty; ++}; ++ ++#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context)) ++#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context)) ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++#define WRITE_SIZE_STR "writesize" ++#define WRITE_SIZE(mtd) ((mtd)->writesize) ++#else ++#define WRITE_SIZE_STR "oobblock" ++#define WRITE_SIZE(mtd) ((mtd)->oobblock) ++#endif ++ ++#endif +diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c +new file mode 100644 +index 00000000..7ae63c54 +--- /dev/null ++++ b/fs/yaffs2/yaffs_mtdif.c +@@ -0,0 +1,308 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yportenv.h" ++ ++#include "yaffs_mtdif.h" ++ ++#include "linux/mtd/mtd.h" ++#include "linux/types.h" ++#include "linux/time.h" ++#include "linux/mtd/nand.h" ++#include "linux/kernel.h" ++#include "linux/version.h" ++#include "linux/types.h" ++ ++#include "yaffs_trace.h" ++#include "yaffs_guts.h" ++#include "yaffs_linux.h" ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) ++#define MTD_OPS_AUTO_OOB MTD_OOB_AUTO ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) ++#define mtd_erase(m, ei) (m)->erase(m, ei) ++#define mtd_write_oob(m, addr, pops) (m)->write_oob(m, addr, pops) ++#define mtd_read_oob(m, addr, pops) (m)->read_oob(m, addr, pops) ++#define mtd_block_isbad(m, offs) (m)->block_isbad(m, offs) ++#define mtd_block_markbad(m, offs) (m)->block_markbad(m, offs) ++#endif ++ ++ ++ ++int nandmtd_erase_block(struct yaffs_dev *dev, int block_no) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ u32 addr = ++ ((loff_t) block_no) * dev->param.total_bytes_per_chunk * ++ dev->param.chunks_per_block; ++ struct erase_info ei; ++ int retval = 0; ++ ++ ei.mtd = mtd; ++ ei.addr = addr; ++ ei.len = dev->param.total_bytes_per_chunk * dev->param.chunks_per_block; ++ ei.time = 1000; ++ ei.retries = 2; ++ ei.callback = NULL; ++ ei.priv = (u_long) dev; ++ ++ retval = mtd_erase(mtd, &ei); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ ++ return YAFFS_FAIL; ++} ++ ++ ++static int yaffs_mtd_write(struct yaffs_dev *dev, int nand_chunk, ++ const u8 *data, int data_len, ++ const u8 *oob, int oob_len) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ loff_t addr; ++ struct mtd_oob_ops ops; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "yaffs_mtd_write(%p, %d, %p, %d, %p, %d)\n", ++ dev, nand_chunk, data, data_len, oob, oob_len); ++ ++ if (!data || !data_len) { ++ data = NULL; ++ data_len = 0; ++ } ++ ++ if (!oob || !oob_len) { ++ oob = NULL; ++ oob_len = 0; ++ } ++ ++ addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; ++ memset(&ops, 0, sizeof(ops)); ++ ops.mode = MTD_OPS_AUTO_OOB; ++ ops.len = (data) ? data_len : 0; ++ ops.ooblen = oob_len; ++ ops.datbuf = (u8 *)data; ++ ops.oobbuf = (u8 *)oob; ++ ++ retval = mtd_write_oob(mtd, addr, &ops); ++ if (retval) { ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "write_oob failed, chunk %d, mtd error %d", ++ nand_chunk, retval); ++ } ++ return retval ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++static int yaffs_mtd_read(struct yaffs_dev *dev, int nand_chunk, ++ u8 *data, int data_len, ++ u8 *oob, int oob_len, ++ enum yaffs_ecc_result *ecc_result) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ loff_t addr; ++ struct mtd_oob_ops ops; ++ int retval; ++ ++ addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; ++ memset(&ops, 0, sizeof(ops)); ++ ops.mode = MTD_OPS_AUTO_OOB; ++ ops.len = (data) ? data_len : 0; ++ ops.ooblen = oob_len; ++ ops.datbuf = data; ++ ops.oobbuf = oob; ++ ++#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20)) ++ /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug; ++ * help it out with ops.len = ops.ooblen when ops.datbuf == NULL. ++ */ ++ ops.len = (ops.datbuf) ? ops.len : ops.ooblen; ++#endif ++ /* Read page and oob using MTD. ++ * Check status and determine ECC result. ++ */ ++ retval = mtd_read_oob(mtd, addr, &ops); ++ if (retval) ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "read_oob failed, chunk %d, mtd error %d", ++ nand_chunk, retval); ++ ++ switch (retval) { ++ case 0: ++ /* no error */ ++ if(ecc_result) ++ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; ++ break; ++ ++ case -EUCLEAN: ++ /* MTD's ECC fixed the data */ ++ if(ecc_result) ++ *ecc_result = YAFFS_ECC_RESULT_FIXED; ++ dev->n_ecc_fixed++; ++ break; ++ ++ case -EBADMSG: ++ default: ++ /* MTD's ECC could not fix the data */ ++ dev->n_ecc_unfixed++; ++ if(ecc_result) ++ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; ++ return YAFFS_FAIL; ++ } ++ ++ return YAFFS_OK; ++} ++ ++static int yaffs_mtd_erase(struct yaffs_dev *dev, int block_no) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ ++ loff_t addr; ++ struct erase_info ei; ++ int retval = 0; ++ u32 block_size; ++ ++ block_size = dev->param.total_bytes_per_chunk * ++ dev->param.chunks_per_block; ++ addr = ((loff_t) block_no) * block_size; ++ ++ ei.mtd = mtd; ++ ei.addr = addr; ++ ei.len = block_size; ++ ei.time = 1000; ++ ei.retries = 2; ++ ei.callback = NULL; ++ ei.priv = (u_long) dev; ++ ++ retval = mtd_erase(mtd, &ei); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ ++ return YAFFS_FAIL; ++} ++ ++static int yaffs_mtd_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ int blocksize = dev->param.chunks_per_block * dev->param.total_bytes_per_chunk; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad", block_no); ++ ++ retval = mtd_block_markbad(mtd, (loff_t) blocksize * block_no); ++ return (retval) ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++static int yaffs_mtd_check_bad(struct yaffs_dev *dev, int block_no) ++{ ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ int blocksize = dev->param.chunks_per_block * dev->param.total_bytes_per_chunk; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "checking block %d bad", block_no); ++ ++ retval = mtd_block_isbad(mtd, (loff_t) blocksize * block_no); ++ return (retval) ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++static int yaffs_mtd_initialise(struct yaffs_dev *dev) ++{ ++ return YAFFS_OK; ++} ++ ++static int yaffs_mtd_deinitialise(struct yaffs_dev *dev) ++{ ++ return YAFFS_OK; ++} ++ ++ ++void yaffs_mtd_drv_install(struct yaffs_dev *dev) ++{ ++ struct yaffs_driver *drv = &dev->drv; ++ ++ drv->drv_write_chunk_fn = yaffs_mtd_write; ++ drv->drv_read_chunk_fn = yaffs_mtd_read; ++ drv->drv_erase_fn = yaffs_mtd_erase; ++ drv->drv_mark_bad_fn = yaffs_mtd_mark_bad; ++ drv->drv_check_bad_fn = yaffs_mtd_check_bad; ++ drv->drv_initialise_fn = yaffs_mtd_initialise; ++ drv->drv_deinitialise_fn = yaffs_mtd_deinitialise; ++} ++ ++ ++struct mtd_info * yaffs_get_mtd_device(dev_t sdev) ++{ ++ struct mtd_info *mtd; ++ ++ mtd = yaffs_get_mtd_device(sdev); ++ ++ /* Check it's an mtd device..... */ ++ if (MAJOR(sdev) != MTD_BLOCK_MAJOR) ++ return NULL; /* This isn't an mtd device */ ++ ++ /* Check it's NAND */ ++ if (mtd->type != MTD_NANDFLASH) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: MTD device is not NAND it's type %d", ++ mtd->type); ++ return NULL; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_OS, " %s %d", WRITE_SIZE_STR, WRITE_SIZE(mtd)); ++ yaffs_trace(YAFFS_TRACE_OS, " oobsize %d", mtd->oobsize); ++ yaffs_trace(YAFFS_TRACE_OS, " erasesize %d", mtd->erasesize); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) ++ yaffs_trace(YAFFS_TRACE_OS, " size %u", mtd->size); ++#else ++ yaffs_trace(YAFFS_TRACE_OS, " size %lld", mtd->size); ++#endif ++ ++ return mtd; ++} ++ ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) ++{ ++ if (yaffs_version == 2) { ++ if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || ++ mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) && ++ !inband_tags) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not have the right page sizes" ++ ); ++ return -1; ++ } ++ } else { ++ if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK || ++ mtd->oobsize != YAFFS_BYTES_PER_SPARE) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not support have the right page sizes" ++ ); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++ ++void yaffs_put_mtd_device(struct mtd_info *mtd) ++{ ++ if(mtd) ++ put_mtd_device(mtd); ++} +diff --git a/fs/yaffs2/yaffs_mtdif.h b/fs/yaffs2/yaffs_mtdif.h +new file mode 100644 +index 00000000..9cff224c +--- /dev/null ++++ b/fs/yaffs2/yaffs_mtdif.h +@@ -0,0 +1,25 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_MTDIF_H__ ++#define __YAFFS_MTDIF_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_mtd_drv_install(struct yaffs_dev *dev); ++struct mtd_info * yaffs_get_mtd_device(dev_t sdev); ++void yaffs_put_mtd_device(struct mtd_info *mtd); ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); ++#endif +diff --git a/fs/yaffs2/yaffs_nameval.c b/fs/yaffs2/yaffs_nameval.c +new file mode 100644 +index 00000000..4bdf4ed7 +--- /dev/null ++++ b/fs/yaffs2/yaffs_nameval.c +@@ -0,0 +1,208 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * This simple implementation of a name-value store assumes a small number of ++* values and fits into a small finite buffer. ++ * ++ * Each attribute is stored as a record: ++ * sizeof(int) bytes record size. ++ * strnlen+1 bytes name null terminated. ++ * nbytes value. ++ * ---------- ++ * total size stored in record size ++ * ++ * This code has not been tested with unicode yet. ++ */ ++ ++#include "yaffs_nameval.h" ++ ++#include "yportenv.h" ++ ++static int nval_find(const char *xb, int xb_size, const YCHAR *name, ++ int *exist_size) ++{ ++ int pos = 0; ++ int size; ++ ++ memcpy(&size, xb, sizeof(int)); ++ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { ++ if (!strncmp((YCHAR *) (xb + pos + sizeof(int)), ++ name, size)) { ++ if (exist_size) ++ *exist_size = size; ++ return pos; ++ } ++ pos += size; ++ if (pos < xb_size - sizeof(int)) ++ memcpy(&size, xb + pos, sizeof(int)); ++ else ++ size = 0; ++ } ++ if (exist_size) ++ *exist_size = 0; ++ return -ENODATA; ++} ++ ++static int nval_used(const char *xb, int xb_size) ++{ ++ int pos = 0; ++ int size; ++ ++ memcpy(&size, xb + pos, sizeof(int)); ++ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { ++ pos += size; ++ if (pos < xb_size - sizeof(int)) ++ memcpy(&size, xb + pos, sizeof(int)); ++ else ++ size = 0; ++ } ++ return pos; ++} ++ ++int nval_del(char *xb, int xb_size, const YCHAR *name) ++{ ++ int pos = nval_find(xb, xb_size, name, NULL); ++ int size; ++ ++ if (pos < 0 || pos >= xb_size) ++ return -ENODATA; ++ ++ /* Find size, shift rest over this record, ++ * then zero out the rest of buffer */ ++ memcpy(&size, xb + pos, sizeof(int)); ++ memcpy(xb + pos, xb + pos + size, xb_size - (pos + size)); ++ memset(xb + (xb_size - size), 0, size); ++ return 0; ++} ++ ++int nval_set(char *xb, int xb_size, const YCHAR *name, const char *buf, ++ int bsize, int flags) ++{ ++ int pos; ++ int namelen = strnlen(name, xb_size); ++ int reclen; ++ int size_exist = 0; ++ int space; ++ int start; ++ ++ pos = nval_find(xb, xb_size, name, &size_exist); ++ ++ if (flags & XATTR_CREATE && pos >= 0) ++ return -EEXIST; ++ if (flags & XATTR_REPLACE && pos < 0) ++ return -ENODATA; ++ ++ start = nval_used(xb, xb_size); ++ space = xb_size - start + size_exist; ++ ++ reclen = (sizeof(int) + namelen + 1 + bsize); ++ ++ if (reclen > space) ++ return -ENOSPC; ++ ++ if (pos >= 0) { ++ nval_del(xb, xb_size, name); ++ start = nval_used(xb, xb_size); ++ } ++ ++ pos = start; ++ ++ memcpy(xb + pos, &reclen, sizeof(int)); ++ pos += sizeof(int); ++ strncpy((YCHAR *) (xb + pos), name, reclen); ++ pos += (namelen + 1); ++ memcpy(xb + pos, buf, bsize); ++ return 0; ++} ++ ++int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, ++ int bsize) ++{ ++ int pos = nval_find(xb, xb_size, name, NULL); ++ int size; ++ ++ if (pos >= 0 && pos < xb_size) { ++ ++ memcpy(&size, xb + pos, sizeof(int)); ++ pos += sizeof(int); /* advance past record length */ ++ size -= sizeof(int); ++ ++ /* Advance over name string */ ++ while (xb[pos] && size > 0 && pos < xb_size) { ++ pos++; ++ size--; ++ } ++ /*Advance over NUL */ ++ pos++; ++ size--; ++ ++ /* If bsize is zero then this is a size query. ++ * Return the size, but don't copy. ++ */ ++ if (!bsize) ++ return size; ++ ++ if (size <= bsize) { ++ memcpy(buf, xb + pos, size); ++ return size; ++ } ++ } ++ if (pos >= 0) ++ return -ERANGE; ++ ++ return -ENODATA; ++} ++ ++int nval_list(const char *xb, int xb_size, char *buf, int bsize) ++{ ++ int pos = 0; ++ int size; ++ int name_len; ++ int ncopied = 0; ++ int filled = 0; ++ ++ memcpy(&size, xb + pos, sizeof(int)); ++ while (size > sizeof(int) && ++ size <= xb_size && ++ (pos + size) < xb_size && ++ !filled) { ++ pos += sizeof(int); ++ size -= sizeof(int); ++ name_len = strnlen((YCHAR *) (xb + pos), size); ++ if (ncopied + name_len + 1 < bsize) { ++ memcpy(buf, xb + pos, name_len * sizeof(YCHAR)); ++ buf += name_len; ++ *buf = '\0'; ++ buf++; ++ if (sizeof(YCHAR) > 1) { ++ *buf = '\0'; ++ buf++; ++ } ++ ncopied += (name_len + 1); ++ } else { ++ filled = 1; ++ } ++ pos += size; ++ if (pos < xb_size - sizeof(int)) ++ memcpy(&size, xb + pos, sizeof(int)); ++ else ++ size = 0; ++ } ++ return ncopied; ++} ++ ++int nval_hasvalues(const char *xb, int xb_size) ++{ ++ return nval_used(xb, xb_size) > 0; ++} +diff --git a/fs/yaffs2/yaffs_nameval.h b/fs/yaffs2/yaffs_nameval.h +new file mode 100644 +index 00000000..951e64f8 +--- /dev/null ++++ b/fs/yaffs2/yaffs_nameval.h +@@ -0,0 +1,28 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __NAMEVAL_H__ ++#define __NAMEVAL_H__ ++ ++#include "yportenv.h" ++ ++int nval_del(char *xb, int xb_size, const YCHAR * name); ++int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, ++ int bsize, int flags); ++int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, ++ int bsize); ++int nval_list(const char *xb, int xb_size, char *buf, int bsize); ++int nval_hasvalues(const char *xb, int xb_size); ++#endif +diff --git a/fs/yaffs2/yaffs_nand.c b/fs/yaffs2/yaffs_nand.c +new file mode 100644 +index 00000000..0d8499bd +--- /dev/null ++++ b/fs/yaffs2/yaffs_nand.c +@@ -0,0 +1,122 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_nand.h" ++#include "yaffs_tagscompat.h" ++ ++#include "yaffs_getblockinfo.h" ++#include "yaffs_summary.h" ++ ++static int apply_chunk_offset(struct yaffs_dev *dev, int chunk) ++{ ++ return chunk - dev->chunk_offset; ++} ++ ++int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, ++ u8 *buffer, struct yaffs_ext_tags *tags) ++{ ++ int result; ++ struct yaffs_ext_tags local_tags; ++ int flash_chunk = apply_chunk_offset(dev, nand_chunk); ++ ++ dev->n_page_reads++; ++ ++ /* If there are no tags provided use local tags. */ ++ if (!tags) ++ tags = &local_tags; ++ ++ result = dev->tagger.read_chunk_tags_fn(dev, flash_chunk, buffer, tags); ++ if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) { ++ ++ struct yaffs_block_info *bi; ++ bi = yaffs_get_block_info(dev, ++ nand_chunk / ++ dev->param.chunks_per_block); ++ yaffs_handle_chunk_error(dev, bi); ++ } ++ return result; ++} ++ ++int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *buffer, struct yaffs_ext_tags *tags) ++{ ++ int result; ++ int flash_chunk = apply_chunk_offset(dev, nand_chunk); ++ ++ dev->n_page_writes++; ++ ++ if (!tags) { ++ yaffs_trace(YAFFS_TRACE_ERROR, "Writing with no tags"); ++ BUG(); ++ return YAFFS_FAIL; ++ } ++ ++ tags->seq_number = dev->seq_number; ++ tags->chunk_used = 1; ++ yaffs_trace(YAFFS_TRACE_WRITE, ++ "Writing chunk %d tags %d %d", ++ nand_chunk, tags->obj_id, tags->chunk_id); ++ ++ result = dev->tagger.write_chunk_tags_fn(dev, flash_chunk, ++ buffer, tags); ++ ++ yaffs_summary_add(dev, tags, nand_chunk); ++ ++ return result; ++} ++ ++int yaffs_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ block_no -= dev->block_offset; ++ dev->n_bad_markings++; ++ ++ if (dev->param.disable_bad_block_marking) ++ return YAFFS_OK; ++ ++ return dev->tagger.mark_bad_fn(dev, block_no); ++} ++ ++ ++int yaffs_query_init_block_state(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ block_no -= dev->block_offset; ++ return dev->tagger.query_block_fn(dev, block_no, state, seq_number); ++} ++ ++int yaffs_erase_block(struct yaffs_dev *dev, int block_no) ++{ ++ int result; ++ ++ block_no -= dev->block_offset; ++ dev->n_erasures++; ++ result = dev->drv.drv_erase_fn(dev, block_no); ++ return result; ++} ++ ++int yaffs_init_nand(struct yaffs_dev *dev) ++{ ++ if (dev->drv.drv_initialise_fn) ++ return dev->drv.drv_initialise_fn(dev); ++ return YAFFS_OK; ++} ++ ++int yaffs_deinit_nand(struct yaffs_dev *dev) ++{ ++ if (dev->drv.drv_deinitialise_fn) ++ return dev->drv.drv_deinitialise_fn(dev); ++ return YAFFS_OK; ++} +diff --git a/fs/yaffs2/yaffs_nand.h b/fs/yaffs2/yaffs_nand.h +new file mode 100644 +index 00000000..804e97ad +--- /dev/null ++++ b/fs/yaffs2/yaffs_nand.h +@@ -0,0 +1,39 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_NAND_H__ ++#define __YAFFS_NAND_H__ ++#include "yaffs_guts.h" ++ ++int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, ++ u8 *buffer, struct yaffs_ext_tags *tags); ++ ++int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *buffer, struct yaffs_ext_tags *tags); ++ ++int yaffs_mark_bad(struct yaffs_dev *dev, int block_no); ++ ++int yaffs_query_init_block_state(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ unsigned *seq_number); ++ ++int yaffs_erase_block(struct yaffs_dev *dev, int flash_block); ++ ++int yaffs_init_nand(struct yaffs_dev *dev); ++int yaffs_deinit_nand(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_packedtags1.c b/fs/yaffs2/yaffs_packedtags1.c +new file mode 100644 +index 00000000..dd9a331d +--- /dev/null ++++ b/fs/yaffs2/yaffs_packedtags1.c +@@ -0,0 +1,56 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_packedtags1.h" ++#include "yportenv.h" ++ ++static const u8 all_ff[20] = { ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff ++}; ++ ++void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, ++ const struct yaffs_ext_tags *t) ++{ ++ pt->chunk_id = t->chunk_id; ++ pt->serial_number = t->serial_number; ++ pt->n_bytes = t->n_bytes; ++ pt->obj_id = t->obj_id; ++ pt->ecc = 0; ++ pt->deleted = (t->is_deleted) ? 0 : 1; ++ pt->unused_stuff = 0; ++ pt->should_be_ff = 0xffffffff; ++} ++ ++void yaffs_unpack_tags1(struct yaffs_ext_tags *t, ++ const struct yaffs_packed_tags1 *pt) ++{ ++ ++ if (memcmp(all_ff, pt, sizeof(struct yaffs_packed_tags1))) { ++ t->block_bad = 0; ++ if (pt->should_be_ff != 0xffffffff) ++ t->block_bad = 1; ++ t->chunk_used = 1; ++ t->obj_id = pt->obj_id; ++ t->chunk_id = pt->chunk_id; ++ t->n_bytes = pt->n_bytes; ++ t->ecc_result = YAFFS_ECC_RESULT_NO_ERROR; ++ t->is_deleted = (pt->deleted) ? 0 : 1; ++ t->serial_number = pt->serial_number; ++ } else { ++ memset(t, 0, sizeof(struct yaffs_ext_tags)); ++ } ++} +diff --git a/fs/yaffs2/yaffs_packedtags1.h b/fs/yaffs2/yaffs_packedtags1.h +new file mode 100644 +index 00000000..3015d58a +--- /dev/null ++++ b/fs/yaffs2/yaffs_packedtags1.h +@@ -0,0 +1,39 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ ++ ++#ifndef __YAFFS_PACKEDTAGS1_H__ ++#define __YAFFS_PACKEDTAGS1_H__ ++ ++#include "yaffs_guts.h" ++ ++struct yaffs_packed_tags1 { ++ u32 chunk_id:20; ++ u32 serial_number:2; ++ u32 n_bytes:10; ++ u32 obj_id:18; ++ u32 ecc:12; ++ u32 deleted:1; ++ u32 unused_stuff:1; ++ unsigned should_be_ff; ++ ++}; ++ ++void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, ++ const struct yaffs_ext_tags *t); ++void yaffs_unpack_tags1(struct yaffs_ext_tags *t, ++ const struct yaffs_packed_tags1 *pt); ++#endif +diff --git a/fs/yaffs2/yaffs_packedtags2.c b/fs/yaffs2/yaffs_packedtags2.c +new file mode 100644 +index 00000000..e1d18cc3 +--- /dev/null ++++ b/fs/yaffs2/yaffs_packedtags2.c +@@ -0,0 +1,197 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_packedtags2.h" ++#include "yportenv.h" ++#include "yaffs_trace.h" ++ ++/* This code packs a set of extended tags into a binary structure for ++ * NAND storage ++ */ ++ ++/* Some of the information is "extra" struff which can be packed in to ++ * speed scanning ++ * This is defined by having the EXTRA_HEADER_INFO_FLAG set. ++ */ ++ ++/* Extra flags applied to chunk_id */ ++ ++#define EXTRA_HEADER_INFO_FLAG 0x80000000 ++#define EXTRA_SHRINK_FLAG 0x40000000 ++#define EXTRA_SHADOWS_FLAG 0x20000000 ++#define EXTRA_SPARE_FLAGS 0x10000000 ++ ++#define ALL_EXTRA_FLAGS 0xf0000000 ++ ++/* Also, the top 4 bits of the object Id are set to the object type. */ ++#define EXTRA_OBJECT_TYPE_SHIFT (28) ++#define EXTRA_OBJECT_TYPE_MASK ((0x0f) << EXTRA_OBJECT_TYPE_SHIFT) ++ ++static void yaffs_dump_packed_tags2_tags_only( ++ const struct yaffs_packed_tags2_tags_only *ptt) ++{ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "packed tags obj %d chunk %d byte %d seq %d", ++ ptt->obj_id, ptt->chunk_id, ptt->n_bytes, ptt->seq_number); ++} ++ ++static void yaffs_dump_packed_tags2(const struct yaffs_packed_tags2 *pt) ++{ ++ yaffs_dump_packed_tags2_tags_only(&pt->t); ++} ++ ++static void yaffs_dump_tags2(const struct yaffs_ext_tags *t) ++{ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d", ++ t->ecc_result, t->block_bad, t->chunk_used, t->obj_id, ++ t->chunk_id, t->n_bytes, t->is_deleted, t->serial_number, ++ t->seq_number); ++ ++} ++ ++static int yaffs_check_tags_extra_packable(const struct yaffs_ext_tags *t) ++{ ++ if (t->chunk_id != 0 || !t->extra_available) ++ return 0; ++ ++ /* Check if the file size is too long to store */ ++ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE && ++ (t->extra_file_size >> 31) != 0) ++ return 0; ++ return 1; ++} ++ ++void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *ptt, ++ const struct yaffs_ext_tags *t) ++{ ++ ptt->chunk_id = t->chunk_id; ++ ptt->seq_number = t->seq_number; ++ ptt->n_bytes = t->n_bytes; ++ ptt->obj_id = t->obj_id; ++ ++ /* Only store extra tags for object headers. ++ * If it is a file then only store if the file size is short\ ++ * enough to fit. ++ */ ++ if (yaffs_check_tags_extra_packable(t)) { ++ /* Store the extra header info instead */ ++ /* We save the parent object in the chunk_id */ ++ ptt->chunk_id = EXTRA_HEADER_INFO_FLAG | t->extra_parent_id; ++ if (t->extra_is_shrink) ++ ptt->chunk_id |= EXTRA_SHRINK_FLAG; ++ if (t->extra_shadows) ++ ptt->chunk_id |= EXTRA_SHADOWS_FLAG; ++ ++ ptt->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; ++ ptt->obj_id |= (t->extra_obj_type << EXTRA_OBJECT_TYPE_SHIFT); ++ ++ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) ++ ptt->n_bytes = t->extra_equiv_id; ++ else if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE) ++ ptt->n_bytes = (unsigned) t->extra_file_size; ++ else ++ ptt->n_bytes = 0; ++ } ++ ++ yaffs_dump_packed_tags2_tags_only(ptt); ++ yaffs_dump_tags2(t); ++} ++ ++void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, ++ const struct yaffs_ext_tags *t, int tags_ecc) ++{ ++ yaffs_pack_tags2_tags_only(&pt->t, t); ++ ++ if (tags_ecc) ++ yaffs_ecc_calc_other((unsigned char *)&pt->t, ++ sizeof(struct yaffs_packed_tags2_tags_only), ++ &pt->ecc); ++} ++ ++void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, ++ struct yaffs_packed_tags2_tags_only *ptt) ++{ ++ memset(t, 0, sizeof(struct yaffs_ext_tags)); ++ ++ if (ptt->seq_number == 0xffffffff) ++ return; ++ ++ t->block_bad = 0; ++ t->chunk_used = 1; ++ t->obj_id = ptt->obj_id; ++ t->chunk_id = ptt->chunk_id; ++ t->n_bytes = ptt->n_bytes; ++ t->is_deleted = 0; ++ t->serial_number = 0; ++ t->seq_number = ptt->seq_number; ++ ++ /* Do extra header info stuff */ ++ if (ptt->chunk_id & EXTRA_HEADER_INFO_FLAG) { ++ t->chunk_id = 0; ++ t->n_bytes = 0; ++ ++ t->extra_available = 1; ++ t->extra_parent_id = ptt->chunk_id & (~(ALL_EXTRA_FLAGS)); ++ t->extra_is_shrink = ptt->chunk_id & EXTRA_SHRINK_FLAG ? 1 : 0; ++ t->extra_shadows = ptt->chunk_id & EXTRA_SHADOWS_FLAG ? 1 : 0; ++ t->extra_obj_type = ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT; ++ t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; ++ ++ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) ++ t->extra_equiv_id = ptt->n_bytes; ++ else ++ t->extra_file_size = ptt->n_bytes; ++ } ++ yaffs_dump_packed_tags2_tags_only(ptt); ++ yaffs_dump_tags2(t); ++} ++ ++void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, ++ int tags_ecc) ++{ ++ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_NO_ERROR; ++ ++ if (pt->t.seq_number != 0xffffffff && tags_ecc) { ++ /* Chunk is in use and we need to do ECC */ ++ ++ struct yaffs_ecc_other ecc; ++ int result; ++ yaffs_ecc_calc_other((unsigned char *)&pt->t, ++ sizeof(struct yaffs_packed_tags2_tags_only), ++ &ecc); ++ result = ++ yaffs_ecc_correct_other((unsigned char *)&pt->t, ++ sizeof(struct yaffs_packed_tags2_tags_only), ++ &pt->ecc, &ecc); ++ switch (result) { ++ case 0: ++ ecc_result = YAFFS_ECC_RESULT_NO_ERROR; ++ break; ++ case 1: ++ ecc_result = YAFFS_ECC_RESULT_FIXED; ++ break; ++ case -1: ++ ecc_result = YAFFS_ECC_RESULT_UNFIXED; ++ break; ++ default: ++ ecc_result = YAFFS_ECC_RESULT_UNKNOWN; ++ } ++ } ++ yaffs_unpack_tags2_tags_only(t, &pt->t); ++ ++ t->ecc_result = ecc_result; ++ ++ yaffs_dump_packed_tags2(pt); ++ yaffs_dump_tags2(t); ++} +diff --git a/fs/yaffs2/yaffs_packedtags2.h b/fs/yaffs2/yaffs_packedtags2.h +new file mode 100644 +index 00000000..675e7194 +--- /dev/null ++++ b/fs/yaffs2/yaffs_packedtags2.h +@@ -0,0 +1,47 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ ++ ++#ifndef __YAFFS_PACKEDTAGS2_H__ ++#define __YAFFS_PACKEDTAGS2_H__ ++ ++#include "yaffs_guts.h" ++#include "yaffs_ecc.h" ++ ++struct yaffs_packed_tags2_tags_only { ++ unsigned seq_number; ++ unsigned obj_id; ++ unsigned chunk_id; ++ unsigned n_bytes; ++}; ++ ++struct yaffs_packed_tags2 { ++ struct yaffs_packed_tags2_tags_only t; ++ struct yaffs_ecc_other ecc; ++}; ++ ++/* Full packed tags with ECC, used for oob tags */ ++void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, ++ const struct yaffs_ext_tags *t, int tags_ecc); ++void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, ++ int tags_ecc); ++ ++/* Only the tags part (no ECC for use with inband tags */ ++void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *pt, ++ const struct yaffs_ext_tags *t); ++void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, ++ struct yaffs_packed_tags2_tags_only *pt); ++#endif +diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c +new file mode 100644 +index 00000000..3c9e7232 +--- /dev/null ++++ b/fs/yaffs2/yaffs_summary.c +@@ -0,0 +1,312 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* Summaries write the useful part of the tags for the chunks in a block into an ++ * an array which is written to the last n chunks of the block. ++ * Reading the summaries gives all the tags for the block in one read. Much ++ * faster. ++ * ++ * Chunks holding summaries are marked with tags making it look like ++ * they are part of a fake file. ++ * ++ * The summary could also be used during gc. ++ * ++ */ ++ ++#include "yaffs_summary.h" ++#include "yaffs_packedtags2.h" ++#include "yaffs_nand.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_bitmap.h" ++ ++/* ++ * The summary is built up in an array of summary tags. ++ * This gets written to the last one or two (maybe more) chunks in a block. ++ * A summary header is written as the first part of each chunk of summary data. ++ * The summary header must match or the summary is rejected. ++ */ ++ ++/* Summary tags don't need the sequence number because that is redundant. */ ++struct yaffs_summary_tags { ++ unsigned obj_id; ++ unsigned chunk_id; ++ unsigned n_bytes; ++}; ++ ++/* Summary header */ ++struct yaffs_summary_header { ++ unsigned version; /* Must match current version */ ++ unsigned block; /* Must be this block */ ++ unsigned seq; /* Must be this sequence number */ ++ unsigned sum; /* Just add up all the bytes in the tags */ ++}; ++ ++ ++static void yaffs_summary_clear(struct yaffs_dev *dev) ++{ ++ if (!dev->sum_tags) ++ return; ++ memset(dev->sum_tags, 0, dev->chunks_per_summary * ++ sizeof(struct yaffs_summary_tags)); ++} ++ ++ ++void yaffs_summary_deinit(struct yaffs_dev *dev) ++{ ++ kfree(dev->sum_tags); ++ dev->sum_tags = NULL; ++ kfree(dev->gc_sum_tags); ++ dev->gc_sum_tags = NULL; ++ dev->chunks_per_summary = 0; ++} ++ ++int yaffs_summary_init(struct yaffs_dev *dev) ++{ ++ int sum_bytes; ++ int chunks_used; /* Number of chunks used by summary */ ++ int sum_tags_bytes; ++ ++ sum_bytes = dev->param.chunks_per_block * ++ sizeof(struct yaffs_summary_tags); ++ ++ chunks_used = (sum_bytes + dev->data_bytes_per_chunk - 1)/ ++ (dev->data_bytes_per_chunk - ++ sizeof(struct yaffs_summary_header)); ++ ++ dev->chunks_per_summary = dev->param.chunks_per_block - chunks_used; ++ sum_tags_bytes = sizeof(struct yaffs_summary_tags) * ++ dev->chunks_per_summary; ++ dev->sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS); ++ dev->gc_sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS); ++ if (!dev->sum_tags || !dev->gc_sum_tags) { ++ yaffs_summary_deinit(dev); ++ return YAFFS_FAIL; ++ } ++ ++ yaffs_summary_clear(dev); ++ ++ return YAFFS_OK; ++} ++ ++static unsigned yaffs_summary_sum(struct yaffs_dev *dev) ++{ ++ u8 *sum_buffer = (u8 *)dev->sum_tags; ++ int i; ++ unsigned sum = 0; ++ ++ i = sizeof(struct yaffs_summary_tags) * ++ dev->chunks_per_summary; ++ while (i > 0) { ++ sum += *sum_buffer; ++ sum_buffer++; ++ i--; ++ } ++ ++ return sum; ++} ++ ++static int yaffs_summary_write(struct yaffs_dev *dev, int blk) ++{ ++ struct yaffs_ext_tags tags; ++ u8 *buffer; ++ u8 *sum_buffer = (u8 *)dev->sum_tags; ++ int n_bytes; ++ int chunk_in_nand; ++ int chunk_in_block; ++ int result; ++ int this_tx; ++ struct yaffs_summary_header hdr; ++ int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr); ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); ++ ++ buffer = yaffs_get_temp_buffer(dev); ++ n_bytes = sizeof(struct yaffs_summary_tags) * ++ dev->chunks_per_summary; ++ memset(&tags, 0, sizeof(struct yaffs_ext_tags)); ++ tags.obj_id = YAFFS_OBJECTID_SUMMARY; ++ tags.chunk_id = 1; ++ chunk_in_block = dev->chunks_per_summary; ++ chunk_in_nand = dev->alloc_block * dev->param.chunks_per_block + ++ dev->chunks_per_summary; ++ hdr.version = YAFFS_SUMMARY_VERSION; ++ hdr.block = blk; ++ hdr.seq = bi->seq_number; ++ hdr.sum = yaffs_summary_sum(dev); ++ ++ do { ++ this_tx = n_bytes; ++ if (this_tx > sum_bytes_per_chunk) ++ this_tx = sum_bytes_per_chunk; ++ memcpy(buffer, &hdr, sizeof(hdr)); ++ memcpy(buffer + sizeof(hdr), sum_buffer, this_tx); ++ tags.n_bytes = this_tx + sizeof(hdr); ++ result = yaffs_wr_chunk_tags_nand(dev, chunk_in_nand, ++ buffer, &tags); ++ ++ if (result != YAFFS_OK) ++ break; ++ yaffs_set_chunk_bit(dev, blk, chunk_in_block); ++ bi->pages_in_use++; ++ dev->n_free_chunks--; ++ ++ n_bytes -= this_tx; ++ sum_buffer += this_tx; ++ chunk_in_nand++; ++ chunk_in_block++; ++ tags.chunk_id++; ++ } while (result == YAFFS_OK && n_bytes > 0); ++ yaffs_release_temp_buffer(dev, buffer); ++ ++ ++ if (result == YAFFS_OK) ++ bi->has_summary = 1; ++ ++ ++ return result; ++} ++ ++int yaffs_summary_read(struct yaffs_dev *dev, ++ struct yaffs_summary_tags *st, ++ int blk) ++{ ++ struct yaffs_ext_tags tags; ++ u8 *buffer; ++ u8 *sum_buffer = (u8 *)st; ++ int n_bytes; ++ int chunk_id; ++ int chunk_in_nand; ++ int chunk_in_block; ++ int result; ++ int this_tx; ++ struct yaffs_summary_header hdr; ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); ++ int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr); ++ int sum_tags_bytes; ++ ++ sum_tags_bytes = sizeof(struct yaffs_summary_tags) * ++ dev->chunks_per_summary; ++ buffer = yaffs_get_temp_buffer(dev); ++ n_bytes = sizeof(struct yaffs_summary_tags) * dev->chunks_per_summary; ++ chunk_in_block = dev->chunks_per_summary; ++ chunk_in_nand = blk * dev->param.chunks_per_block + ++ dev->chunks_per_summary; ++ chunk_id = 1; ++ do { ++ this_tx = n_bytes; ++ if (this_tx > sum_bytes_per_chunk) ++ this_tx = sum_bytes_per_chunk; ++ result = yaffs_rd_chunk_tags_nand(dev, chunk_in_nand, ++ buffer, &tags); ++ ++ if (tags.chunk_id != chunk_id || ++ tags.obj_id != YAFFS_OBJECTID_SUMMARY || ++ tags.chunk_used == 0 || ++ tags.ecc_result > YAFFS_ECC_RESULT_FIXED || ++ tags.n_bytes != (this_tx + sizeof(hdr))) ++ result = YAFFS_FAIL; ++ if (result != YAFFS_OK) ++ break; ++ ++ if (st == dev->sum_tags) { ++ /* If we're scanning then update the block info */ ++ yaffs_set_chunk_bit(dev, blk, chunk_in_block); ++ bi->pages_in_use++; ++ } ++ memcpy(&hdr, buffer, sizeof(hdr)); ++ memcpy(sum_buffer, buffer + sizeof(hdr), this_tx); ++ n_bytes -= this_tx; ++ sum_buffer += this_tx; ++ chunk_in_nand++; ++ chunk_in_block++; ++ chunk_id++; ++ } while (result == YAFFS_OK && n_bytes > 0); ++ yaffs_release_temp_buffer(dev, buffer); ++ ++ if (result == YAFFS_OK) { ++ /* Verify header */ ++ if (hdr.version != YAFFS_SUMMARY_VERSION || ++ hdr.seq != bi->seq_number || ++ hdr.sum != yaffs_summary_sum(dev)) ++ result = YAFFS_FAIL; ++ } ++ ++ if (st == dev->sum_tags && result == YAFFS_OK) ++ bi->has_summary = 1; ++ ++ return result; ++} ++ ++int yaffs_summary_add(struct yaffs_dev *dev, ++ struct yaffs_ext_tags *tags, ++ int chunk_in_nand) ++{ ++ struct yaffs_packed_tags2_tags_only tags_only; ++ struct yaffs_summary_tags *sum_tags; ++ int block_in_nand = chunk_in_nand / dev->param.chunks_per_block; ++ int chunk_in_block = chunk_in_nand % dev->param.chunks_per_block; ++ ++ if (!dev->sum_tags) ++ return YAFFS_OK; ++ ++ if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) { ++ yaffs_pack_tags2_tags_only(&tags_only, tags); ++ sum_tags = &dev->sum_tags[chunk_in_block]; ++ sum_tags->chunk_id = tags_only.chunk_id; ++ sum_tags->n_bytes = tags_only.n_bytes; ++ sum_tags->obj_id = tags_only.obj_id; ++ ++ if (chunk_in_block == dev->chunks_per_summary - 1) { ++ /* Time to write out the summary */ ++ yaffs_summary_write(dev, block_in_nand); ++ yaffs_summary_clear(dev); ++ yaffs_skip_rest_of_block(dev); ++ } ++ } ++ return YAFFS_OK; ++} ++ ++int yaffs_summary_fetch(struct yaffs_dev *dev, ++ struct yaffs_ext_tags *tags, ++ int chunk_in_block) ++{ ++ struct yaffs_packed_tags2_tags_only tags_only; ++ struct yaffs_summary_tags *sum_tags; ++ if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) { ++ sum_tags = &dev->sum_tags[chunk_in_block]; ++ tags_only.chunk_id = sum_tags->chunk_id; ++ tags_only.n_bytes = sum_tags->n_bytes; ++ tags_only.obj_id = sum_tags->obj_id; ++ yaffs_unpack_tags2_tags_only(tags, &tags_only); ++ return YAFFS_OK; ++ } ++ return YAFFS_FAIL; ++} ++ ++void yaffs_summary_gc(struct yaffs_dev *dev, int blk) ++{ ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); ++ int i; ++ ++ if (!bi->has_summary) ++ return; ++ ++ for (i = dev->chunks_per_summary; ++ i < dev->param.chunks_per_block; ++ i++) { ++ if (yaffs_check_chunk_bit(dev, blk, i)) { ++ yaffs_clear_chunk_bit(dev, blk, i); ++ bi->pages_in_use--; ++ dev->n_free_chunks++; ++ } ++ } ++} +diff --git a/fs/yaffs2/yaffs_summary.h b/fs/yaffs2/yaffs_summary.h +new file mode 100644 +index 00000000..be141d07 +--- /dev/null ++++ b/fs/yaffs2/yaffs_summary.h +@@ -0,0 +1,37 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_SUMMARY_H__ ++#define __YAFFS_SUMMARY_H__ ++ ++#include "yaffs_packedtags2.h" ++ ++ ++int yaffs_summary_init(struct yaffs_dev *dev); ++void yaffs_summary_deinit(struct yaffs_dev *dev); ++ ++int yaffs_summary_add(struct yaffs_dev *dev, ++ struct yaffs_ext_tags *tags, ++ int chunk_in_block); ++int yaffs_summary_fetch(struct yaffs_dev *dev, ++ struct yaffs_ext_tags *tags, ++ int chunk_in_block); ++int yaffs_summary_read(struct yaffs_dev *dev, ++ struct yaffs_summary_tags *st, ++ int blk); ++void yaffs_summary_gc(struct yaffs_dev *dev, int blk); ++ ++ ++#endif +diff --git a/fs/yaffs2/yaffs_tagscompat.c b/fs/yaffs2/yaffs_tagscompat.c +new file mode 100644 +index 00000000..092430be +--- /dev/null ++++ b/fs/yaffs2/yaffs_tagscompat.c +@@ -0,0 +1,381 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_guts.h" ++#include "yaffs_tagscompat.h" ++#include "yaffs_ecc.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_trace.h" ++ ++static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); ++ ++ ++/********** Tags ECC calculations *********/ ++ ++ ++void yaffs_calc_tags_ecc(struct yaffs_tags *tags) ++{ ++ /* Calculate an ecc */ ++ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; ++ unsigned i, j; ++ unsigned ecc = 0; ++ unsigned bit = 0; ++ ++ tags->ecc = 0; ++ ++ for (i = 0; i < 8; i++) { ++ for (j = 1; j & 0xff; j <<= 1) { ++ bit++; ++ if (b[i] & j) ++ ecc ^= bit; ++ } ++ } ++ tags->ecc = ecc; ++} ++ ++int yaffs_check_tags_ecc(struct yaffs_tags *tags) ++{ ++ unsigned ecc = tags->ecc; ++ ++ yaffs_calc_tags_ecc(tags); ++ ++ ecc ^= tags->ecc; ++ ++ if (ecc && ecc <= 64) { ++ /* TODO: Handle the failure better. Retire? */ ++ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; ++ ++ ecc--; ++ ++ b[ecc / 8] ^= (1 << (ecc & 7)); ++ ++ /* Now recvalc the ecc */ ++ yaffs_calc_tags_ecc(tags); ++ ++ return 1; /* recovered error */ ++ } else if (ecc) { ++ /* Wierd ecc failure value */ ++ /* TODO Need to do somethiong here */ ++ return -1; /* unrecovered error */ ++ } ++ return 0; ++} ++ ++/********** Tags **********/ ++ ++static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, ++ struct yaffs_tags *tags_ptr) ++{ ++ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; ++ ++ yaffs_calc_tags_ecc(tags_ptr); ++ ++ spare_ptr->tb0 = tu->as_bytes[0]; ++ spare_ptr->tb1 = tu->as_bytes[1]; ++ spare_ptr->tb2 = tu->as_bytes[2]; ++ spare_ptr->tb3 = tu->as_bytes[3]; ++ spare_ptr->tb4 = tu->as_bytes[4]; ++ spare_ptr->tb5 = tu->as_bytes[5]; ++ spare_ptr->tb6 = tu->as_bytes[6]; ++ spare_ptr->tb7 = tu->as_bytes[7]; ++} ++ ++static void yaffs_get_tags_from_spare(struct yaffs_dev *dev, ++ struct yaffs_spare *spare_ptr, ++ struct yaffs_tags *tags_ptr) ++{ ++ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; ++ int result; ++ ++ tu->as_bytes[0] = spare_ptr->tb0; ++ tu->as_bytes[1] = spare_ptr->tb1; ++ tu->as_bytes[2] = spare_ptr->tb2; ++ tu->as_bytes[3] = spare_ptr->tb3; ++ tu->as_bytes[4] = spare_ptr->tb4; ++ tu->as_bytes[5] = spare_ptr->tb5; ++ tu->as_bytes[6] = spare_ptr->tb6; ++ tu->as_bytes[7] = spare_ptr->tb7; ++ ++ result = yaffs_check_tags_ecc(tags_ptr); ++ if (result > 0) ++ dev->n_tags_ecc_fixed++; ++ else if (result < 0) ++ dev->n_tags_ecc_unfixed++; ++} ++ ++static void yaffs_spare_init(struct yaffs_spare *spare) ++{ ++ memset(spare, 0xff, sizeof(struct yaffs_spare)); ++} ++ ++static int yaffs_wr_nand(struct yaffs_dev *dev, ++ int nand_chunk, const u8 *data, ++ struct yaffs_spare *spare) ++{ ++ int data_size = dev->data_bytes_per_chunk; ++ ++ return dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, data_size, ++ (u8 *) spare, sizeof(*spare)); ++} ++ ++static int yaffs_rd_chunk_nand(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, ++ struct yaffs_spare *spare, ++ enum yaffs_ecc_result *ecc_result, ++ int correct_errors) ++{ ++ int ret_val; ++ struct yaffs_spare local_spare; ++ int data_size; ++ int spare_size; ++ int ecc_result1, ecc_result2; ++ u8 calc_ecc[3]; ++ ++ if (!spare) { ++ /* If we don't have a real spare, then we use a local one. */ ++ /* Need this for the calculation of the ecc */ ++ spare = &local_spare; ++ } ++ data_size = dev->data_bytes_per_chunk; ++ spare_size = sizeof(struct yaffs_spare); ++ ++ if (dev->param.use_nand_ecc) ++ return dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, data_size, ++ (u8 *) spare, spare_size, ++ ecc_result); ++ ++ ++ /* Handle the ECC at this level. */ ++ ++ ret_val = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, data_size, ++ (u8 *)spare, spare_size, ++ NULL); ++ if (!data || !correct_errors) ++ return ret_val; ++ ++ /* Do ECC correction if needed. */ ++ yaffs_ecc_calc(data, calc_ecc); ++ ecc_result1 = yaffs_ecc_correct(data, spare->ecc1, calc_ecc); ++ yaffs_ecc_calc(&data[256], calc_ecc); ++ ecc_result2 = yaffs_ecc_correct(&data[256], spare->ecc2, calc_ecc); ++ ++ if (ecc_result1 > 0) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>>yaffs ecc error fix performed on chunk %d:0", ++ nand_chunk); ++ dev->n_ecc_fixed++; ++ } else if (ecc_result1 < 0) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>>yaffs ecc error unfixed on chunk %d:0", ++ nand_chunk); ++ dev->n_ecc_unfixed++; ++ } ++ ++ if (ecc_result2 > 0) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>>yaffs ecc error fix performed on chunk %d:1", ++ nand_chunk); ++ dev->n_ecc_fixed++; ++ } else if (ecc_result2 < 0) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "**>>yaffs ecc error unfixed on chunk %d:1", ++ nand_chunk); ++ dev->n_ecc_unfixed++; ++ } ++ ++ if (ecc_result1 || ecc_result2) { ++ /* We had a data problem on this page */ ++ yaffs_handle_rd_data_error(dev, nand_chunk); ++ } ++ ++ if (ecc_result1 < 0 || ecc_result2 < 0) ++ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; ++ else if (ecc_result1 > 0 || ecc_result2 > 0) ++ *ecc_result = YAFFS_ECC_RESULT_FIXED; ++ else ++ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; ++ ++ return ret_val; ++} ++ ++/* ++ * Functions for robustisizing ++ */ ++ ++static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk) ++{ ++ int flash_block = nand_chunk / dev->param.chunks_per_block; ++ ++ /* Mark the block for retirement */ ++ yaffs_get_block_info(dev, flash_block + dev->block_offset)-> ++ needs_retiring = 1; ++ yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ "**>>Block %d marked for retirement", ++ flash_block); ++ ++ /* TODO: ++ * Just do a garbage collection on the affected block ++ * then retire the block ++ * NB recursion ++ */ ++} ++ ++static int yaffs_tags_compat_wr(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, const struct yaffs_ext_tags *ext_tags) ++{ ++ struct yaffs_spare spare; ++ struct yaffs_tags tags; ++ ++ yaffs_spare_init(&spare); ++ ++ if (ext_tags->is_deleted) ++ spare.page_status = 0; ++ else { ++ tags.obj_id = ext_tags->obj_id; ++ tags.chunk_id = ext_tags->chunk_id; ++ ++ tags.n_bytes_lsb = ext_tags->n_bytes & (1024 - 1); ++ ++ if (dev->data_bytes_per_chunk >= 1024) ++ tags.n_bytes_msb = (ext_tags->n_bytes >> 10) & 3; ++ else ++ tags.n_bytes_msb = 3; ++ ++ tags.serial_number = ext_tags->serial_number; ++ ++ if (!dev->param.use_nand_ecc && data) { ++ yaffs_ecc_calc(data, spare.ecc1); ++ yaffs_ecc_calc(&data[256], spare.ecc2); ++ } ++ ++ yaffs_load_tags_to_spare(&spare, &tags); ++ } ++ return yaffs_wr_nand(dev, nand_chunk, data, &spare); ++} ++ ++static int yaffs_tags_compat_rd(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, struct yaffs_ext_tags *ext_tags) ++{ ++ struct yaffs_spare spare; ++ struct yaffs_tags tags; ++ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_UNKNOWN; ++ static struct yaffs_spare spare_ff; ++ static int init; ++ int deleted; ++ ++ if (!init) { ++ memset(&spare_ff, 0xff, sizeof(spare_ff)); ++ init = 1; ++ } ++ ++ if (!yaffs_rd_chunk_nand(dev, nand_chunk, ++ data, &spare, &ecc_result, 1)) ++ return YAFFS_FAIL; ++ ++ /* ext_tags may be NULL */ ++ if (!ext_tags) ++ return YAFFS_OK; ++ ++ deleted = (hweight8(spare.page_status) < 7) ? 1 : 0; ++ ++ ext_tags->is_deleted = deleted; ++ ext_tags->ecc_result = ecc_result; ++ ext_tags->block_bad = 0; /* We're reading it */ ++ /* therefore it is not a bad block */ ++ ext_tags->chunk_used = ++ memcmp(&spare_ff, &spare, sizeof(spare_ff)) ? 1 : 0; ++ ++ if (ext_tags->chunk_used) { ++ yaffs_get_tags_from_spare(dev, &spare, &tags); ++ ext_tags->obj_id = tags.obj_id; ++ ext_tags->chunk_id = tags.chunk_id; ++ ext_tags->n_bytes = tags.n_bytes_lsb; ++ ++ if (dev->data_bytes_per_chunk >= 1024) ++ ext_tags->n_bytes |= ++ (((unsigned)tags.n_bytes_msb) << 10); ++ ++ ext_tags->serial_number = tags.serial_number; ++ } ++ ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int flash_block) ++{ ++ struct yaffs_spare spare; ++ ++ memset(&spare, 0xff, sizeof(struct yaffs_spare)); ++ ++ spare.block_status = 'Y'; ++ ++ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block, NULL, ++ &spare); ++ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block + 1, ++ NULL, &spare); ++ ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ struct yaffs_spare spare0, spare1; ++ static struct yaffs_spare spare_ff; ++ static int init; ++ enum yaffs_ecc_result dummy; ++ ++ if (!init) { ++ memset(&spare_ff, 0xff, sizeof(spare_ff)); ++ init = 1; ++ } ++ ++ *seq_number = 0; ++ ++ /* Look for bad block markers in the first two chunks */ ++ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block, ++ NULL, &spare0, &dummy, 0); ++ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block + 1, ++ NULL, &spare1, &dummy, 0); ++ ++ if (hweight8(spare0.block_status & spare1.block_status) < 7) ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ else if (memcmp(&spare_ff, &spare0, sizeof(spare_ff)) == 0) ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ else ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ ++ return YAFFS_OK; ++} ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev) ++{ ++ if(dev->param.is_yaffs2) ++ return; ++ if(!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_wr; ++ if(!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_rd; ++ if(!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_compat_query_block; ++ if(!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; ++} +diff --git a/fs/yaffs2/yaffs_tagscompat.h b/fs/yaffs2/yaffs_tagscompat.h +new file mode 100644 +index 00000000..92d298a6 +--- /dev/null ++++ b/fs/yaffs2/yaffs_tagscompat.h +@@ -0,0 +1,44 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_TAGSCOMPAT_H__ ++#define __YAFFS_TAGSCOMPAT_H__ ++ ++ ++#include "yaffs_guts.h" ++ ++#if 0 ++ ++ ++int yaffs_tags_compat_wr(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, const struct yaffs_ext_tags *tags); ++int yaffs_tags_compat_rd(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, struct yaffs_ext_tags *tags); ++int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no); ++int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number); ++ ++#endif ++ ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev); ++void yaffs_calc_tags_ecc(struct yaffs_tags *tags); ++int yaffs_check_tags_ecc(struct yaffs_tags *tags); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_tagsmarshall.c b/fs/yaffs2/yaffs_tagsmarshall.c +new file mode 100644 +index 00000000..44a83b12 +--- /dev/null ++++ b/fs/yaffs2/yaffs_tagsmarshall.c +@@ -0,0 +1,199 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_guts.h" ++#include "yaffs_trace.h" ++#include "yaffs_packedtags2.h" ++ ++static int yaffs_tags_marshall_write(struct yaffs_dev *dev, ++ int nand_chunk, const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags2 pt; ++ int retval; ++ ++ int packed_tags_size = ++ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); ++ void *packed_tags_ptr = ++ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "yaffs_tags_marshall_write chunk %d data %p tags %p", ++ nand_chunk, data, tags); ++ ++ /* For yaffs2 writing there must be both data and tags. ++ * If we're using inband tags, then the tags are stuffed into ++ * the end of the data buffer. ++ */ ++ if (!data || !tags) ++ BUG(); ++ else if (dev->param.inband_tags) { ++ struct yaffs_packed_tags2_tags_only *pt2tp; ++ pt2tp = ++ (struct yaffs_packed_tags2_tags_only *)(data + ++ dev-> ++ data_bytes_per_chunk); ++ yaffs_pack_tags2_tags_only(pt2tp, tags); ++ } else { ++ yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc); ++ } ++ ++ retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ (dev->param.inband_tags) ? NULL : packed_tags_ptr, ++ (dev->param.inband_tags) ? 0 : packed_tags_size); ++ ++ return retval; ++} ++ ++static int yaffs_tags_marshall_read(struct yaffs_dev *dev, ++ int nand_chunk, u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ int retval = 0; ++ int local_data = 0; ++ u8 spare_buffer[100]; ++ enum yaffs_ecc_result ecc_result; ++ ++ struct yaffs_packed_tags2 pt; ++ ++ int packed_tags_size = ++ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); ++ void *packed_tags_ptr = ++ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "yaffs_tags_marshall_read chunk %d data %p tags %p", ++ nand_chunk, data, tags); ++ ++ if (dev->param.inband_tags) { ++ if (!data) { ++ local_data = 1; ++ data = yaffs_get_temp_buffer(dev); ++ } ++ } ++ ++ if (dev->param.inband_tags || (data && !tags)) ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ NULL, 0, ++ &ecc_result); ++ else if (tags) ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ spare_buffer, packed_tags_size, ++ &ecc_result); ++ else ++ BUG(); ++ ++ ++ if (dev->param.inband_tags) { ++ if (tags) { ++ struct yaffs_packed_tags2_tags_only *pt2tp; ++ pt2tp = ++ (struct yaffs_packed_tags2_tags_only *) ++ &data[dev->data_bytes_per_chunk]; ++ yaffs_unpack_tags2_tags_only(tags, pt2tp); ++ } ++ } else if (tags) { ++ memcpy(packed_tags_ptr, spare_buffer, packed_tags_size); ++ yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc); ++ } ++ ++ if (local_data) ++ yaffs_release_temp_buffer(dev, data); ++ ++ if (tags && ecc_result == YAFFS_ECC_RESULT_UNFIXED) { ++ tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED; ++ dev->n_ecc_unfixed++; ++ } ++ ++ if (tags && ecc_result == -YAFFS_ECC_RESULT_FIXED) { ++ if (tags->ecc_result <= YAFFS_ECC_RESULT_NO_ERROR) ++ tags->ecc_result = YAFFS_ECC_RESULT_FIXED; ++ dev->n_ecc_fixed++; ++ } ++ ++ if (ecc_result < YAFFS_ECC_RESULT_UNFIXED) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++static int yaffs_tags_marshall_query_block(struct yaffs_dev *dev, int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "yaffs_tags_marshall_query_block %d", ++ block_no); ++ ++ retval = dev->drv.drv_check_bad_fn(dev, block_no); ++ ++ if (retval== YAFFS_FAIL) { ++ yaffs_trace(YAFFS_TRACE_MTD, "block is bad"); ++ ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ *seq_number = 0; ++ } else { ++ struct yaffs_ext_tags t; ++ ++ yaffs_tags_marshall_read(dev, ++ block_no * dev->param.chunks_per_block, ++ NULL, &t); ++ ++ if (t.chunk_used) { ++ *seq_number = t.seq_number; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else { ++ *seq_number = 0; ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ } ++ ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "block query returns seq %d state %d", ++ *seq_number, *state); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++static int yaffs_tags_marshall_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ return dev->drv.drv_mark_bad_fn(dev, block_no); ++ ++} ++ ++ ++void yaffs_tags_marshall_install(struct yaffs_dev *dev) ++{ ++ if (!dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_marshall_write; ++ ++ if (!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_marshall_read; ++ ++ if (!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_marshall_query_block; ++ ++ if (!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_marshall_mark_bad; ++ ++} +diff --git a/fs/yaffs2/yaffs_tagsmarshall.h b/fs/yaffs2/yaffs_tagsmarshall.h +new file mode 100644 +index 00000000..bf3e68a1 +--- /dev/null ++++ b/fs/yaffs2/yaffs_tagsmarshall.h +@@ -0,0 +1,22 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_TAGSMARSHALL_H__ ++#define __YAFFS_TAGSMARSHALL_H__ ++ ++#include "yaffs_guts.h" ++void yaffs_tags_marshall_install(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_trace.h b/fs/yaffs2/yaffs_trace.h +new file mode 100644 +index 00000000..fd26054d +--- /dev/null ++++ b/fs/yaffs2/yaffs_trace.h +@@ -0,0 +1,57 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YTRACE_H__ ++#define __YTRACE_H__ ++ ++extern unsigned int yaffs_trace_mask; ++extern unsigned int yaffs_wr_attempts; ++ ++/* ++ * Tracing flags. ++ * The flags masked in YAFFS_TRACE_ALWAYS are always traced. ++ */ ++ ++#define YAFFS_TRACE_OS 0x00000002 ++#define YAFFS_TRACE_ALLOCATE 0x00000004 ++#define YAFFS_TRACE_SCAN 0x00000008 ++#define YAFFS_TRACE_BAD_BLOCKS 0x00000010 ++#define YAFFS_TRACE_ERASE 0x00000020 ++#define YAFFS_TRACE_GC 0x00000040 ++#define YAFFS_TRACE_WRITE 0x00000080 ++#define YAFFS_TRACE_TRACING 0x00000100 ++#define YAFFS_TRACE_DELETION 0x00000200 ++#define YAFFS_TRACE_BUFFERS 0x00000400 ++#define YAFFS_TRACE_NANDACCESS 0x00000800 ++#define YAFFS_TRACE_GC_DETAIL 0x00001000 ++#define YAFFS_TRACE_SCAN_DEBUG 0x00002000 ++#define YAFFS_TRACE_MTD 0x00004000 ++#define YAFFS_TRACE_CHECKPOINT 0x00008000 ++ ++#define YAFFS_TRACE_VERIFY 0x00010000 ++#define YAFFS_TRACE_VERIFY_NAND 0x00020000 ++#define YAFFS_TRACE_VERIFY_FULL 0x00040000 ++#define YAFFS_TRACE_VERIFY_ALL 0x000f0000 ++ ++#define YAFFS_TRACE_SYNC 0x00100000 ++#define YAFFS_TRACE_BACKGROUND 0x00200000 ++#define YAFFS_TRACE_LOCK 0x00400000 ++#define YAFFS_TRACE_MOUNT 0x00800000 ++ ++#define YAFFS_TRACE_ERROR 0x40000000 ++#define YAFFS_TRACE_BUG 0x80000000 ++#define YAFFS_TRACE_ALWAYS 0xf0000000 ++ ++#endif +diff --git a/fs/yaffs2/yaffs_verify.c b/fs/yaffs2/yaffs_verify.c +new file mode 100644 +index 00000000..e8f2f0a6 +--- /dev/null ++++ b/fs/yaffs2/yaffs_verify.c +@@ -0,0 +1,529 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_verify.h" ++#include "yaffs_trace.h" ++#include "yaffs_bitmap.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_nand.h" ++ ++int yaffs_skip_verification(struct yaffs_dev *dev) ++{ ++ (void) dev; ++ return !(yaffs_trace_mask & ++ (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); ++} ++ ++static int yaffs_skip_full_verification(struct yaffs_dev *dev) ++{ ++ (void) dev; ++ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL)); ++} ++ ++static int yaffs_skip_nand_verification(struct yaffs_dev *dev) ++{ ++ (void) dev; ++ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND)); ++} ++ ++static const char * const block_state_name[] = { ++ "Unknown", ++ "Needs scan", ++ "Scanning", ++ "Empty", ++ "Allocating", ++ "Full", ++ "Dirty", ++ "Checkpoint", ++ "Collecting", ++ "Dead" ++}; ++ ++void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, int n) ++{ ++ int actually_used; ++ int in_use; ++ ++ if (yaffs_skip_verification(dev)) ++ return; ++ ++ /* Report illegal runtime states */ ++ if (bi->block_state >= YAFFS_NUMBER_OF_BLOCK_STATES) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Block %d has undefined state %d", ++ n, bi->block_state); ++ ++ switch (bi->block_state) { ++ case YAFFS_BLOCK_STATE_UNKNOWN: ++ case YAFFS_BLOCK_STATE_SCANNING: ++ case YAFFS_BLOCK_STATE_NEEDS_SCAN: ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Block %d has bad run-state %s", ++ n, block_state_name[bi->block_state]); ++ } ++ ++ /* Check pages in use and soft deletions are legal */ ++ ++ actually_used = bi->pages_in_use - bi->soft_del_pages; ++ ++ if (bi->pages_in_use < 0 || ++ bi->pages_in_use > dev->param.chunks_per_block || ++ bi->soft_del_pages < 0 || ++ bi->soft_del_pages > dev->param.chunks_per_block || ++ actually_used < 0 || actually_used > dev->param.chunks_per_block) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Block %d has illegal values pages_in_used %d soft_del_pages %d", ++ n, bi->pages_in_use, bi->soft_del_pages); ++ ++ /* Check chunk bitmap legal */ ++ in_use = yaffs_count_chunk_bits(dev, n); ++ if (in_use != bi->pages_in_use) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Block %d has inconsistent values pages_in_use %d counted chunk bits %d", ++ n, bi->pages_in_use, in_use); ++} ++ ++void yaffs_verify_collected_blk(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi, int n) ++{ ++ yaffs_verify_blk(dev, bi, n); ++ ++ /* After collection the block should be in the erased state */ ++ ++ if (bi->block_state != YAFFS_BLOCK_STATE_COLLECTING && ++ bi->block_state != YAFFS_BLOCK_STATE_EMPTY) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "Block %d is in state %d after gc, should be erased", ++ n, bi->block_state); ++ } ++} ++ ++void yaffs_verify_blocks(struct yaffs_dev *dev) ++{ ++ int i; ++ int state_count[YAFFS_NUMBER_OF_BLOCK_STATES]; ++ int illegal_states = 0; ++ ++ if (yaffs_skip_verification(dev)) ++ return; ++ ++ memset(state_count, 0, sizeof(state_count)); ++ ++ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); ++ yaffs_verify_blk(dev, bi, i); ++ ++ if (bi->block_state < YAFFS_NUMBER_OF_BLOCK_STATES) ++ state_count[bi->block_state]++; ++ else ++ illegal_states++; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_VERIFY, "Block summary"); ++ ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "%d blocks have illegal states", ++ illegal_states); ++ if (state_count[YAFFS_BLOCK_STATE_ALLOCATING] > 1) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Too many allocating blocks"); ++ ++ for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "%s %d blocks", ++ block_state_name[i], state_count[i]); ++ ++ if (dev->blocks_in_checkpt != state_count[YAFFS_BLOCK_STATE_CHECKPOINT]) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Checkpoint block count wrong dev %d count %d", ++ dev->blocks_in_checkpt, ++ state_count[YAFFS_BLOCK_STATE_CHECKPOINT]); ++ ++ if (dev->n_erased_blocks != state_count[YAFFS_BLOCK_STATE_EMPTY]) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Erased block count wrong dev %d count %d", ++ dev->n_erased_blocks, ++ state_count[YAFFS_BLOCK_STATE_EMPTY]); ++ ++ if (state_count[YAFFS_BLOCK_STATE_COLLECTING] > 1) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Too many collecting blocks %d (max is 1)", ++ state_count[YAFFS_BLOCK_STATE_COLLECTING]); ++} ++ ++/* ++ * Verify the object header. oh must be valid, but obj and tags may be NULL in ++ * which case those tests will not be performed. ++ */ ++void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, ++ struct yaffs_ext_tags *tags, int parent_check) ++{ ++ if (obj && yaffs_skip_verification(obj->my_dev)) ++ return; ++ ++ if (!(tags && obj && oh)) { ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Verifying object header tags %p obj %p oh %p", ++ tags, obj, oh); ++ return; ++ } ++ ++ if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN || ++ oh->type > YAFFS_OBJECT_TYPE_MAX) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header type is illegal value 0x%x", ++ tags->obj_id, oh->type); ++ ++ if (tags->obj_id != obj->obj_id) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header mismatch obj_id %d", ++ tags->obj_id, obj->obj_id); ++ ++ /* ++ * Check that the object's parent ids match if parent_check requested. ++ * ++ * Tests do not apply to the root object. ++ */ ++ ++ if (parent_check && tags->obj_id > 1 && !obj->parent) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header mismatch parent_id %d obj->parent is NULL", ++ tags->obj_id, oh->parent_obj_id); ++ ++ if (parent_check && obj->parent && ++ oh->parent_obj_id != obj->parent->obj_id && ++ (oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED || ++ obj->parent->obj_id != YAFFS_OBJECTID_DELETED)) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header mismatch parent_id %d parent_obj_id %d", ++ tags->obj_id, oh->parent_obj_id, ++ obj->parent->obj_id); ++ ++ if (tags->obj_id > 1 && oh->name[0] == 0) /* Null name */ ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header name is NULL", ++ obj->obj_id); ++ ++ if (tags->obj_id > 1 && ((u8) (oh->name[0])) == 0xff) /* Junk name */ ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d header name is 0xff", ++ obj->obj_id); ++} ++ ++void yaffs_verify_file(struct yaffs_obj *obj) ++{ ++ u32 x; ++ int required_depth; ++ int actual_depth; ++ int last_chunk; ++ u32 offset_in_chunk; ++ u32 the_chunk; ++ ++ u32 i; ++ struct yaffs_dev *dev; ++ struct yaffs_ext_tags tags; ++ struct yaffs_tnode *tn; ++ u32 obj_id; ++ ++ if (!obj) ++ return; ++ ++ if (yaffs_skip_verification(obj->my_dev)) ++ return; ++ ++ dev = obj->my_dev; ++ obj_id = obj->obj_id; ++ ++ ++ /* Check file size is consistent with tnode depth */ ++ yaffs_addr_to_chunk(dev, obj->variant.file_variant.file_size, ++ &last_chunk, &offset_in_chunk); ++ last_chunk++; ++ x = last_chunk >> YAFFS_TNODES_LEVEL0_BITS; ++ required_depth = 0; ++ while (x > 0) { ++ x >>= YAFFS_TNODES_INTERNAL_BITS; ++ required_depth++; ++ } ++ ++ actual_depth = obj->variant.file_variant.top_level; ++ ++ /* Check that the chunks in the tnode tree are all correct. ++ * We do this by scanning through the tnode tree and ++ * checking the tags for every chunk match. ++ */ ++ ++ if (yaffs_skip_nand_verification(dev)) ++ return; ++ ++ for (i = 1; i <= last_chunk; i++) { ++ tn = yaffs_find_tnode_0(dev, &obj->variant.file_variant, i); ++ ++ if (!tn) ++ continue; ++ ++ the_chunk = yaffs_get_group_base(dev, tn, i); ++ if (the_chunk > 0) { ++ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, ++ &tags); ++ if (tags.obj_id != obj_id || tags.chunk_id != i) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Object %d chunk_id %d NAND mismatch chunk %d tags (%d:%d)", ++ obj_id, i, the_chunk, ++ tags.obj_id, tags.chunk_id); ++ } ++ } ++} ++ ++void yaffs_verify_link(struct yaffs_obj *obj) ++{ ++ if (obj && yaffs_skip_verification(obj->my_dev)) ++ return; ++ ++ /* Verify sane equivalent object */ ++} ++ ++void yaffs_verify_symlink(struct yaffs_obj *obj) ++{ ++ if (obj && yaffs_skip_verification(obj->my_dev)) ++ return; ++ ++ /* Verify symlink string */ ++} ++ ++void yaffs_verify_special(struct yaffs_obj *obj) ++{ ++ if (obj && yaffs_skip_verification(obj->my_dev)) ++ return; ++} ++ ++void yaffs_verify_obj(struct yaffs_obj *obj) ++{ ++ struct yaffs_dev *dev; ++ u32 chunk_min; ++ u32 chunk_max; ++ u32 chunk_id_ok; ++ u32 chunk_in_range; ++ u32 chunk_wrongly_deleted; ++ u32 chunk_valid; ++ ++ if (!obj) ++ return; ++ ++ if (obj->being_created) ++ return; ++ ++ dev = obj->my_dev; ++ ++ if (yaffs_skip_verification(dev)) ++ return; ++ ++ /* Check sane object header chunk */ ++ ++ chunk_min = dev->internal_start_block * dev->param.chunks_per_block; ++ chunk_max = ++ (dev->internal_end_block + 1) * dev->param.chunks_per_block - 1; ++ ++ chunk_in_range = (((unsigned)(obj->hdr_chunk)) >= chunk_min && ++ ((unsigned)(obj->hdr_chunk)) <= chunk_max); ++ chunk_id_ok = chunk_in_range || (obj->hdr_chunk == 0); ++ chunk_valid = chunk_in_range && ++ yaffs_check_chunk_bit(dev, ++ obj->hdr_chunk / dev->param.chunks_per_block, ++ obj->hdr_chunk % dev->param.chunks_per_block); ++ chunk_wrongly_deleted = chunk_in_range && !chunk_valid; ++ ++ if (!obj->fake && (!chunk_id_ok || chunk_wrongly_deleted)) ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d has chunk_id %d %s %s", ++ obj->obj_id, obj->hdr_chunk, ++ chunk_id_ok ? "" : ",out of range", ++ chunk_wrongly_deleted ? ",marked as deleted" : ""); ++ ++ if (chunk_valid && !yaffs_skip_nand_verification(dev)) { ++ struct yaffs_ext_tags tags; ++ struct yaffs_obj_hdr *oh; ++ u8 *buffer = yaffs_get_temp_buffer(dev); ++ ++ oh = (struct yaffs_obj_hdr *)buffer; ++ ++ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, buffer, &tags); ++ ++ yaffs_verify_oh(obj, oh, &tags, 1); ++ ++ yaffs_release_temp_buffer(dev, buffer); ++ } ++ ++ /* Verify it has a parent */ ++ if (obj && !obj->fake && (!obj->parent || obj->parent->my_dev != dev)) { ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d has parent pointer %p which does not look like an object", ++ obj->obj_id, obj->parent); ++ } ++ ++ /* Verify parent is a directory */ ++ if (obj->parent && ++ obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d's parent is not a directory (type %d)", ++ obj->obj_id, obj->parent->variant_type); ++ } ++ ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ yaffs_verify_file(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ yaffs_verify_symlink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ yaffs_verify_dir(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ yaffs_verify_link(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ yaffs_verify_special(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ default: ++ yaffs_trace(YAFFS_TRACE_VERIFY, ++ "Obj %d has illegaltype %d", ++ obj->obj_id, obj->variant_type); ++ break; ++ } ++} ++ ++void yaffs_verify_objects(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj; ++ int i; ++ struct list_head *lh; ++ ++ if (yaffs_skip_verification(dev)) ++ return; ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { ++ list_for_each(lh, &dev->obj_bucket[i].list) { ++ obj = list_entry(lh, struct yaffs_obj, hash_link); ++ yaffs_verify_obj(obj); ++ } ++ } ++} ++ ++void yaffs_verify_obj_in_dir(struct yaffs_obj *obj) ++{ ++ struct list_head *lh; ++ struct yaffs_obj *list_obj; ++ int count = 0; ++ ++ if (!obj) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "No object to verify"); ++ BUG(); ++ return; ++ } ++ ++ if (yaffs_skip_verification(obj->my_dev)) ++ return; ++ ++ if (!obj->parent) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "Object does not have parent"); ++ BUG(); ++ return; ++ } ++ ++ if (obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "Parent is not directory"); ++ BUG(); ++ } ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ list_for_each(lh, &obj->parent->variant.dir_variant.children) { ++ list_obj = list_entry(lh, struct yaffs_obj, siblings); ++ yaffs_verify_obj(list_obj); ++ if (obj == list_obj) ++ count++; ++ } ++ ++ if (count != 1) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Object in directory %d times", ++ count); ++ BUG(); ++ } ++} ++ ++void yaffs_verify_dir(struct yaffs_obj *directory) ++{ ++ struct list_head *lh; ++ struct yaffs_obj *list_obj; ++ ++ if (!directory) { ++ BUG(); ++ return; ++ } ++ ++ if (yaffs_skip_full_verification(directory->my_dev)) ++ return; ++ ++ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Directory has wrong type: %d", ++ directory->variant_type); ++ BUG(); ++ } ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ list_for_each(lh, &directory->variant.dir_variant.children) { ++ list_obj = list_entry(lh, struct yaffs_obj, siblings); ++ if (list_obj->parent != directory) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Object in directory list has wrong parent %p", ++ list_obj->parent); ++ BUG(); ++ } ++ yaffs_verify_obj_in_dir(list_obj); ++ } ++} ++ ++static int yaffs_free_verification_failures; ++ ++void yaffs_verify_free_chunks(struct yaffs_dev *dev) ++{ ++ int counted; ++ int difference; ++ ++ if (yaffs_skip_verification(dev)) ++ return; ++ ++ counted = yaffs_count_free_chunks(dev); ++ ++ difference = dev->n_free_chunks - counted; ++ ++ if (difference) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Freechunks verification failure %d %d %d", ++ dev->n_free_chunks, counted, difference); ++ yaffs_free_verification_failures++; ++ } ++} ++ ++int yaffs_verify_file_sane(struct yaffs_obj *in) ++{ ++ (void) in; ++ return YAFFS_OK; ++} +diff --git a/fs/yaffs2/yaffs_verify.h b/fs/yaffs2/yaffs_verify.h +new file mode 100644 +index 00000000..4f4af8d2 +--- /dev/null ++++ b/fs/yaffs2/yaffs_verify.h +@@ -0,0 +1,43 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_VERIFY_H__ ++#define __YAFFS_VERIFY_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, ++ int n); ++void yaffs_verify_collected_blk(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi, int n); ++void yaffs_verify_blocks(struct yaffs_dev *dev); ++ ++void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, ++ struct yaffs_ext_tags *tags, int parent_check); ++void yaffs_verify_file(struct yaffs_obj *obj); ++void yaffs_verify_link(struct yaffs_obj *obj); ++void yaffs_verify_symlink(struct yaffs_obj *obj); ++void yaffs_verify_special(struct yaffs_obj *obj); ++void yaffs_verify_obj(struct yaffs_obj *obj); ++void yaffs_verify_objects(struct yaffs_dev *dev); ++void yaffs_verify_obj_in_dir(struct yaffs_obj *obj); ++void yaffs_verify_dir(struct yaffs_obj *directory); ++void yaffs_verify_free_chunks(struct yaffs_dev *dev); ++ ++int yaffs_verify_file_sane(struct yaffs_obj *obj); ++ ++int yaffs_skip_verification(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_vfs.c b/fs/yaffs2/yaffs_vfs.c +new file mode 100644 +index 00000000..4621043e +--- /dev/null ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -0,0 +1,3458 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * Acknowledgements: ++ * Luc van OostenRyck for numerous patches. ++ * Nick Bane for numerous patches. ++ * Nick Bane for 2.5/2.6 integration. ++ * Andras Toth for mknod rdev issue. ++ * Michael Fischer for finding the problem with inode inconsistency. ++ * Some code bodily lifted from JFFS ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * ++ * This is the file system front-end to YAFFS that hooks it up to ++ * the VFS. ++ * ++ * Special notes: ++ * >> 2.4: sb->u.generic_sbp points to the struct yaffs_dev associated with ++ * this superblock ++ * >> 2.6: sb->s_fs_info points to the struct yaffs_dev associated with this ++ * superblock ++ * >> inode->u.generic_ip points to the associated struct yaffs_obj. ++ */ ++ ++/* ++ * There are two variants of the VFS glue code. This variant should compile ++ * for any version of Linux. ++ */ ++#include ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)) ++#define YAFFS_COMPILE_BACKGROUND ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)) ++#define YAFFS_COMPILE_FREEZER ++#endif ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) ++#define YAFFS_COMPILE_EXPORTFS ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++#define YAFFS_USE_SETATTR_COPY ++#define YAFFS_USE_TRUNCATE_SETSIZE ++#endif ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++#define YAFFS_HAS_EVICT_INODE ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) ++#define YAFFS_NEW_FOLLOW_LINK 1 ++#else ++#define YAFFS_NEW_FOLLOW_LINK 0 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) ++#define YAFFS_HAS_WRITE_SUPER ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) ++#include ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++ ++#if (YAFFS_NEW_FOLLOW_LINK == 1) ++#include ++#endif ++ ++#ifdef YAFFS_COMPILE_EXPORTFS ++#include ++#endif ++ ++#ifdef YAFFS_COMPILE_BACKGROUND ++#include ++#include ++#endif ++#ifdef YAFFS_COMPILE_FREEZER ++#include ++#endif ++ ++#include ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ ++#include ++ ++#define UnlockPage(p) unlock_page(p) ++#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags) ++ ++/* FIXME: use sb->s_id instead ? */ ++#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf) ++ ++#else ++ ++#include ++#define BDEVNAME_SIZE 0 ++#define yaffs_devname(sb, buf) kdevname(sb->s_dev) ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) ++/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */ ++#define __user ++#endif ++ ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) ++#define YPROC_ROOT (&proc_root) ++#else ++#define YPROC_ROOT NULL ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) ++#define Y_INIT_TIMER(a) init_timer(a) ++#else ++#define Y_INIT_TIMER(a) init_timer_on_stack(a) ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27)) ++#define YAFFS_USE_WRITE_BEGIN_END 1 ++#else ++#define YAFFS_USE_WRITE_BEGIN_END 0 ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) ++#define YAFFS_SUPER_HAS_DIRTY ++#endif ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) ++#define set_nlink(inode, count) do { (inode)->i_nlink = (count); } while(0) ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)) ++static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size) ++{ ++ uint64_t result = partition_size; ++ do_div(result, block_size); ++ return (uint32_t) result; ++} ++#else ++#define YCALCBLOCKS(s, b) ((s)/(b)) ++#endif ++ ++#include ++#include ++ ++#include "yportenv.h" ++#include "yaffs_trace.h" ++#include "yaffs_guts.h" ++#include "yaffs_attribs.h" ++ ++#include "yaffs_linux.h" ++ ++#include "yaffs_mtdif.h" ++#include "yaffs_packedtags2.h" ++#include "yaffs_getblockinfo.h" ++ ++unsigned int yaffs_trace_mask = ++ YAFFS_TRACE_BAD_BLOCKS | ++ YAFFS_TRACE_ALWAYS | ++ 0; ++ ++unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS; ++unsigned int yaffs_auto_checkpoint = 1; ++unsigned int yaffs_gc_control = 1; ++unsigned int yaffs_bg_enable = 1; ++unsigned int yaffs_auto_select = 1; ++/* Module Parameters */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++module_param(yaffs_trace_mask, uint, 0644); ++module_param(yaffs_wr_attempts, uint, 0644); ++module_param(yaffs_auto_checkpoint, uint, 0644); ++module_param(yaffs_gc_control, uint, 0644); ++module_param(yaffs_bg_enable, uint, 0644); ++#else ++MODULE_PARM(yaffs_trace_mask, "i"); ++MODULE_PARM(yaffs_wr_attempts, "i"); ++MODULE_PARM(yaffs_auto_checkpoint, "i"); ++MODULE_PARM(yaffs_gc_control, "i"); ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) ++/* use iget and read_inode */ ++#define Y_IGET(sb, inum) iget((sb), (inum)) ++ ++#else ++/* Call local equivalent */ ++#define YAFFS_USE_OWN_IGET ++#define Y_IGET(sb, inum) yaffs_iget((sb), (inum)) ++ ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) ++#define yaffs_inode_to_obj_lv(iptr) ((iptr)->i_private) ++#else ++#define yaffs_inode_to_obj_lv(iptr) ((iptr)->u.generic_ip) ++#endif ++ ++#define yaffs_inode_to_obj(iptr) \ ++ ((struct yaffs_obj *)(yaffs_inode_to_obj_lv(iptr))) ++#define yaffs_dentry_to_obj(dptr) yaffs_inode_to_obj((dptr)->d_inode) ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->s_fs_info) ++#else ++#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->u.generic_sbp) ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) ++#define Y_CLEAR_INODE(i) clear_inode(i) ++#else ++#define Y_CLEAR_INODE(i) end_writeback(i) ++#endif ++ ++ ++#define update_dir_time(dir) do {\ ++ (dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \ ++ } while (0) ++ ++static void yaffs_fill_inode_from_obj(struct inode *inode, ++ struct yaffs_obj *obj); ++ ++ ++static void yaffs_gross_lock(struct yaffs_dev *dev) ++{ ++ yaffs_trace(YAFFS_TRACE_LOCK, "yaffs locking %p", current); ++ mutex_lock(&(yaffs_dev_to_lc(dev)->gross_lock)); ++ yaffs_trace(YAFFS_TRACE_LOCK, "yaffs locked %p", current); ++} ++ ++static void yaffs_gross_unlock(struct yaffs_dev *dev) ++{ ++ yaffs_trace(YAFFS_TRACE_LOCK, "yaffs unlocking %p", current); ++ mutex_unlock(&(yaffs_dev_to_lc(dev)->gross_lock)); ++} ++ ++ ++static int yaffs_readpage_nolock(struct file *f, struct page *pg) ++{ ++ /* Lifted from jffs2 */ ++ ++ struct yaffs_obj *obj; ++ unsigned char *pg_buf; ++ int ret; ++ loff_t pos = ((loff_t) pg->index) << PAGE_CACHE_SHIFT; ++ struct yaffs_dev *dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_readpage_nolock at %lld, size %08x", ++ (long long)pos, ++ (unsigned)PAGE_CACHE_SIZE); ++ ++ obj = yaffs_dentry_to_obj(f->f_dentry); ++ ++ dev = obj->my_dev; ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ BUG_ON(!PageLocked(pg)); ++#else ++ if (!PageLocked(pg)) ++ PAGE_BUG(pg); ++#endif ++ ++ pg_buf = kmap(pg); ++ /* FIXME: Can kmap fail? */ ++ ++ yaffs_gross_lock(dev); ++ ++ ret = yaffs_file_rd(obj, pg_buf, pos, PAGE_CACHE_SIZE); ++ ++ yaffs_gross_unlock(dev); ++ ++ if (ret >= 0) ++ ret = 0; ++ ++ if (ret) { ++ ClearPageUptodate(pg); ++ SetPageError(pg); ++ } else { ++ SetPageUptodate(pg); ++ ClearPageError(pg); ++ } ++ ++ flush_dcache_page(pg); ++ kunmap(pg); ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage_nolock done"); ++ return ret; ++} ++ ++static int yaffs_readpage_unlock(struct file *f, struct page *pg) ++{ ++ int ret = yaffs_readpage_nolock(f, pg); ++ UnlockPage(pg); ++ return ret; ++} ++ ++static int yaffs_readpage(struct file *f, struct page *pg) ++{ ++ int ret; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage"); ++ ret = yaffs_readpage_unlock(f, pg); ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage done"); ++ return ret; ++} ++ ++ ++static void yaffs_set_super_dirty_val(struct yaffs_dev *dev, int val) ++{ ++ struct yaffs_linux_context *lc = yaffs_dev_to_lc(dev); ++ ++ if (lc) ++ lc->dirty = val; ++ ++# ifdef YAFFS_SUPER_HAS_DIRTY ++ { ++ struct super_block *sb = lc->super; ++ ++ if (sb) ++ sb->s_dirt = val; ++ } ++#endif ++ ++} ++ ++static void yaffs_set_super_dirty(struct yaffs_dev *dev) ++{ ++ yaffs_set_super_dirty_val(dev, 1); ++} ++ ++static void yaffs_clear_super_dirty(struct yaffs_dev *dev) ++{ ++ yaffs_set_super_dirty_val(dev, 0); ++} ++ ++static int yaffs_check_super_dirty(struct yaffs_dev *dev) ++{ ++ struct yaffs_linux_context *lc = yaffs_dev_to_lc(dev); ++ ++ if (lc && lc->dirty) ++ return 1; ++ ++# ifdef YAFFS_SUPER_HAS_DIRTY ++ { ++ struct super_block *sb = lc->super; ++ ++ if (sb && sb->s_dirt) ++ return 1; ++ } ++#endif ++ return 0; ++ ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs_writepage(struct page *page, struct writeback_control *wbc) ++#else ++static int yaffs_writepage(struct page *page) ++#endif ++{ ++ struct yaffs_dev *dev; ++ struct address_space *mapping = page->mapping; ++ struct inode *inode; ++ unsigned long end_index; ++ char *buffer; ++ struct yaffs_obj *obj; ++ int n_written = 0; ++ unsigned n_bytes; ++ loff_t i_size; ++ ++ if (!mapping) ++ BUG(); ++ inode = mapping->host; ++ if (!inode) ++ BUG(); ++ i_size = i_size_read(inode); ++ ++ end_index = i_size >> PAGE_CACHE_SHIFT; ++ ++ if (page->index < end_index) ++ n_bytes = PAGE_CACHE_SIZE; ++ else { ++ n_bytes = i_size & (PAGE_CACHE_SIZE - 1); ++ ++ if (page->index > end_index || !n_bytes) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_writepage at %lld, inode size = %lld!!", ++ ((loff_t)page->index) << PAGE_CACHE_SHIFT, ++ inode->i_size); ++ yaffs_trace(YAFFS_TRACE_OS, ++ " -> don't care!!"); ++ ++ zero_user_segment(page, 0, PAGE_CACHE_SIZE); ++ set_page_writeback(page); ++ unlock_page(page); ++ end_page_writeback(page); ++ return 0; ++ } ++ } ++ ++ if (n_bytes != PAGE_CACHE_SIZE) ++ zero_user_segment(page, n_bytes, PAGE_CACHE_SIZE); ++ ++ get_page(page); ++ ++ buffer = kmap(page); ++ ++ obj = yaffs_inode_to_obj(inode); ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_writepage at %lld, size %08x", ++ ((loff_t)page->index) << PAGE_CACHE_SHIFT, n_bytes); ++ yaffs_trace(YAFFS_TRACE_OS, ++ "writepag0: obj = %lld, ino = %lld", ++ obj->variant.file_variant.file_size, inode->i_size); ++ ++ n_written = yaffs_wr_file(obj, buffer, ++ ((loff_t)page->index) << PAGE_CACHE_SHIFT, n_bytes, 0); ++ ++ yaffs_set_super_dirty(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "writepag1: obj = %lld, ino = %lld", ++ obj->variant.file_variant.file_size, inode->i_size); ++ ++ yaffs_gross_unlock(dev); ++ ++ kunmap(page); ++ set_page_writeback(page); ++ unlock_page(page); ++ end_page_writeback(page); ++ put_page(page); ++ ++ return (n_written == n_bytes) ? 0 : -ENOSPC; ++} ++ ++/* Space holding and freeing is done to ensure we have space available for write_begin/end */ ++/* For now we just assume few parallel writes and check against a small number. */ ++/* Todo: need to do this with a counter to handle parallel reads better */ ++ ++static ssize_t yaffs_hold_space(struct file *f) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ ++ int n_free_chunks; ++ ++ obj = yaffs_dentry_to_obj(f->f_dentry); ++ ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ n_free_chunks = yaffs_get_n_free_chunks(dev); ++ ++ yaffs_gross_unlock(dev); ++ ++ return (n_free_chunks > 20) ? 1 : 0; ++} ++ ++static void yaffs_release_space(struct file *f) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ ++ obj = yaffs_dentry_to_obj(f->f_dentry); ++ ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ yaffs_gross_unlock(dev); ++} ++ ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++static int yaffs_write_begin(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned flags, ++ struct page **pagep, void **fsdata) ++{ ++ struct page *pg = NULL; ++ pgoff_t index = pos >> PAGE_CACHE_SHIFT; ++ ++ int ret = 0; ++ int space_held = 0; ++ ++ /* Get a page */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28) ++ pg = grab_cache_page_write_begin(mapping, index, flags); ++#else ++ pg = __grab_cache_page(mapping, index); ++#endif ++ ++ *pagep = pg; ++ if (!pg) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ yaffs_trace(YAFFS_TRACE_OS, ++ "start yaffs_write_begin index %d(%x) uptodate %d", ++ (int)index, (int)index, Page_Uptodate(pg) ? 1 : 0); ++ ++ /* Get fs space */ ++ space_held = yaffs_hold_space(filp); ++ ++ if (!space_held) { ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ /* Update page if required */ ++ ++ if (!Page_Uptodate(pg)) ++ ret = yaffs_readpage_nolock(filp, pg); ++ ++ if (ret) ++ goto out; ++ ++ /* Happy path return */ ++ yaffs_trace(YAFFS_TRACE_OS, "end yaffs_write_begin - ok"); ++ ++ return 0; ++ ++out: ++ yaffs_trace(YAFFS_TRACE_OS, ++ "end yaffs_write_begin fail returning %d", ret); ++ if (space_held) ++ yaffs_release_space(filp); ++ if (pg) { ++ unlock_page(pg); ++ page_cache_release(pg); ++ } ++ return ret; ++} ++ ++#else ++ ++static int yaffs_prepare_write(struct file *f, struct page *pg, ++ unsigned offset, unsigned to) ++{ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_prepair_write"); ++ ++ if (!Page_Uptodate(pg)) ++ return yaffs_readpage_nolock(f, pg); ++ return 0; ++} ++#endif ++ ++ ++static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, ++ loff_t * pos) ++{ ++ struct yaffs_obj *obj; ++ int n_written; ++ loff_t ipos; ++ struct inode *inode; ++ struct yaffs_dev *dev; ++ ++ obj = yaffs_dentry_to_obj(f->f_dentry); ++ ++ if (!obj) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_file_write: hey obj is null!"); ++ return -EINVAL; ++ } ++ ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ inode = f->f_dentry->d_inode; ++ ++ if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) ++ ipos = inode->i_size; ++ else ++ ipos = *pos; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_file_write about to write writing %u(%x) bytes to object %d at %lld", ++ (unsigned)n, (unsigned)n, obj->obj_id, ipos); ++ ++ n_written = yaffs_wr_file(obj, buf, ipos, n, 0); ++ ++ yaffs_set_super_dirty(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_file_write: %d(%x) bytes written", ++ (unsigned)n, (unsigned)n); ++ ++ if (n_written > 0) { ++ ipos += n_written; ++ *pos = ipos; ++ if (ipos > inode->i_size) { ++ inode->i_size = ipos; ++ inode->i_blocks = (ipos + 511) >> 9; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_file_write size updated to %lld bytes, %d blocks", ++ ipos, (int)(inode->i_blocks)); ++ } ++ ++ } ++ yaffs_gross_unlock(dev); ++ return (n_written == 0) && (n > 0) ? -ENOSPC : n_written; ++} ++ ++ ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++static int yaffs_write_end(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned copied, ++ struct page *pg, void *fsdadata) ++{ ++ int ret = 0; ++ void *addr, *kva; ++ uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1); ++ ++ kva = kmap(pg); ++ addr = kva + offset_into_page; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_write_end addr %p pos %lld n_bytes %d", ++ addr, pos, copied); ++ ++ ret = yaffs_file_write(filp, addr, copied, &pos); ++ ++ if (ret != copied) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_write_end not same size ret %d copied %d", ++ ret, copied); ++ SetPageError(pg); ++ } ++ ++ kunmap(pg); ++ ++ yaffs_release_space(filp); ++ unlock_page(pg); ++ page_cache_release(pg); ++ return ret; ++} ++#else ++ ++static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, ++ unsigned to) ++{ ++ void *addr, *kva; ++ ++ loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset; ++ int n_bytes = to - offset; ++ int n_written; ++ ++ kva = kmap(pg); ++ addr = kva + offset; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_commit_write addr %p pos %lld n_bytes %d", ++ addr, pos, n_bytes); ++ ++ n_written = yaffs_file_write(f, addr, n_bytes, &pos); ++ ++ if (n_written != n_bytes) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_commit_write not same size n_written %d n_bytes %d", ++ n_written, n_bytes); ++ SetPageError(pg); ++ } ++ kunmap(pg); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_commit_write returning %d", ++ n_written == n_bytes ? 0 : n_written); ++ ++ return n_written == n_bytes ? 0 : n_written; ++} ++#endif ++ ++static struct address_space_operations yaffs_file_address_operations = { ++ .readpage = yaffs_readpage, ++ .writepage = yaffs_writepage, ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++ .write_begin = yaffs_write_begin, ++ .write_end = yaffs_write_end, ++#else ++ .prepare_write = yaffs_prepare_write, ++ .commit_write = yaffs_commit_write, ++#endif ++}; ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static int yaffs_file_flush(struct file *file, fl_owner_t id) ++#else ++static int yaffs_file_flush(struct file *file) ++#endif ++{ ++ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); ++ ++ struct yaffs_dev *dev = obj->my_dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_file_flush object %d (%s)", ++ obj->obj_id, ++ obj->dirty ? "dirty" : "clean"); ++ ++ yaffs_gross_lock(dev); ++ ++ yaffs_flush_file(obj, 1, 0); ++ ++ yaffs_gross_unlock(dev); ++ ++ return 0; ++} ++ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++static int yaffs_sync_object(struct file *file, loff_t start, loff_t end, int datasync) ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) ++static int yaffs_sync_object(struct file *file, int datasync) ++#else ++static int yaffs_sync_object(struct file *file, struct dentry *dentry, ++ int datasync) ++#endif ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) ++ struct dentry *dentry = file->f_path.dentry; ++#endif ++ ++ obj = yaffs_dentry_to_obj(dentry); ++ ++ dev = obj->my_dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, ++ "yaffs_sync_object"); ++ yaffs_gross_lock(dev); ++ yaffs_flush_file(obj, 1, datasync); ++ yaffs_gross_unlock(dev); ++ return 0; ++} ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++static const struct file_operations yaffs_file_operations = { ++ .read = do_sync_read, ++ .write = do_sync_write, ++ .aio_read = generic_file_aio_read, ++ .aio_write = generic_file_aio_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = generic_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) ++ ++static const struct file_operations yaffs_file_operations = { ++ .read = do_sync_read, ++ .write = do_sync_write, ++ .aio_read = generic_file_aio_read, ++ .aio_write = generic_file_aio_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .sendfile = generic_file_sendfile, ++}; ++ ++#else ++ ++static const struct file_operations yaffs_file_operations = { ++ .read = generic_file_read, ++ .write = generic_file_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ .sendfile = generic_file_sendfile, ++#endif ++}; ++#endif ++ ++ ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) ++static void zero_user_segment(struct page *page, unsigned start, unsigned end) ++{ ++ void *kaddr = kmap_atomic(page, KM_USER0); ++ memset(kaddr + start, 0, end - start); ++ kunmap_atomic(kaddr, KM_USER0); ++ flush_dcache_page(page); ++} ++#endif ++ ++ ++static int yaffs_vfs_setsize(struct inode *inode, loff_t newsize) ++{ ++#ifdef YAFFS_USE_TRUNCATE_SETSIZE ++ truncate_setsize(inode, newsize); ++ return 0; ++#else ++ truncate_inode_pages(&inode->i_data, newsize); ++ return 0; ++#endif ++ ++} ++ ++ ++static int yaffs_vfs_setattr(struct inode *inode, struct iattr *attr) ++{ ++#ifdef YAFFS_USE_SETATTR_COPY ++ setattr_copy(inode, attr); ++ return 0; ++#else ++ return inode_setattr(inode, attr); ++#endif ++ ++} ++ ++static int yaffs_setattr(struct dentry *dentry, struct iattr *attr) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error = 0; ++ struct yaffs_dev *dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_setattr of object %d", ++ yaffs_inode_to_obj(inode)->obj_id); ++#if 0 ++ /* Fail if a requested resize >= 2GB */ ++ if (attr->ia_valid & ATTR_SIZE && (attr->ia_size >> 31)) ++ error = -EINVAL; ++#endif ++ ++ if (error == 0) ++ error = inode_change_ok(inode, attr); ++ if (error == 0) { ++ int result; ++ if (!error) { ++ error = yaffs_vfs_setattr(inode, attr); ++ yaffs_trace(YAFFS_TRACE_OS, "inode_setattr called"); ++ if (attr->ia_valid & ATTR_SIZE) { ++ yaffs_vfs_setsize(inode, attr->ia_size); ++ inode->i_blocks = (inode->i_size + 511) >> 9; ++ } ++ } ++ dev = yaffs_inode_to_obj(inode)->my_dev; ++ if (attr->ia_valid & ATTR_SIZE) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "resize to %d(%x)", ++ (int)(attr->ia_size), ++ (int)(attr->ia_size)); ++ } ++ yaffs_gross_lock(dev); ++ result = yaffs_set_attribs(yaffs_inode_to_obj(inode), attr); ++ if (result == YAFFS_OK) { ++ error = 0; ++ } else { ++ error = -EPERM; ++ } ++ yaffs_gross_unlock(dev); ++ ++ } ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_setattr done returning %d", error); ++ ++ return error; ++} ++ ++static int yaffs_setxattr(struct dentry *dentry, const char *name, ++ const void *value, size_t size, int flags) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error = 0; ++ struct yaffs_dev *dev; ++ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_setxattr of object %d", obj->obj_id); ++ ++ if (error == 0) { ++ int result; ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ result = yaffs_set_xattrib(obj, name, value, size, flags); ++ if (result == YAFFS_OK) ++ error = 0; ++ else if (result < 0) ++ error = result; ++ yaffs_gross_unlock(dev); ++ ++ } ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_setxattr done returning %d", error); ++ ++ return error; ++} ++ ++static ssize_t yaffs_getxattr(struct dentry * dentry, const char *name, ++ void *buff, size_t size) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error = 0; ++ struct yaffs_dev *dev; ++ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_getxattr \"%s\" from object %d", ++ name, obj->obj_id); ++ ++ if (error == 0) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ error = yaffs_get_xattrib(obj, name, buff, size); ++ yaffs_gross_unlock(dev); ++ ++ } ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_getxattr done returning %d", error); ++ ++ return error; ++} ++ ++static int yaffs_removexattr(struct dentry *dentry, const char *name) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error = 0; ++ struct yaffs_dev *dev; ++ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_removexattr of object %d", obj->obj_id); ++ ++ if (error == 0) { ++ int result; ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ result = yaffs_remove_xattrib(obj, name); ++ if (result == YAFFS_OK) ++ error = 0; ++ else if (result < 0) ++ error = result; ++ yaffs_gross_unlock(dev); ++ ++ } ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_removexattr done returning %d", error); ++ ++ return error; ++} ++ ++static ssize_t yaffs_listxattr(struct dentry * dentry, char *buff, size_t size) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error = 0; ++ struct yaffs_dev *dev; ++ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_listxattr of object %d", obj->obj_id); ++ ++ if (error == 0) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ error = yaffs_list_xattrib(obj, buff, size); ++ yaffs_gross_unlock(dev); ++ ++ } ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_listxattr done returning %d", error); ++ ++ return error; ++} ++ ++ ++static const struct inode_operations yaffs_file_inode_operations = { ++ .setattr = yaffs_setattr, ++ .setxattr = yaffs_setxattr, ++ .getxattr = yaffs_getxattr, ++ .listxattr = yaffs_listxattr, ++ .removexattr = yaffs_removexattr, ++}; ++ ++ ++static int yaffs_readlink(struct dentry *dentry, char __user * buffer, ++ int buflen) ++{ ++ unsigned char *alias; ++ int ret; ++ ++ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); ++ ++ yaffs_gross_unlock(dev); ++ ++ if (!alias) ++ return -ENOMEM; ++ ++ ret = vfs_readlink(dentry, buffer, buflen, alias); ++ kfree(alias); ++ return ret; ++} ++ ++#if (YAFFS_NEW_FOLLOW_LINK == 1) ++static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) ++{ ++ void *ret; ++#else ++static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) ++{ ++ int ret ++#endif ++ unsigned char *alias; ++ int ret_int = 0; ++ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); ++ yaffs_gross_unlock(dev); ++ ++ if (!alias) { ++ ret_int = -ENOMEM; ++ goto out; ++ } ++#if (YAFFS_NEW_FOLLOW_LINK == 1) ++ nd_set_link(nd, alias); ++ ret = alias; ++out: ++ if (ret_int) ++ ret = ERR_PTR(ret_int); ++ return ret; ++#else ++ ret = vfs_follow_link(nd, alias); ++ kfree(alias); ++out: ++ if (ret_int) ++ ret = ret_int; ++ return ret; ++#endif ++} ++ ++ ++#ifdef YAFFS_HAS_PUT_INODE ++ ++/* For now put inode is just for debugging ++ * Put inode is called when the inode **structure** is put. ++ */ ++static void yaffs_put_inode(struct inode *inode) ++{ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_put_inode: ino %d, count %d"), ++ (int)inode->i_ino, atomic_read(&inode->i_count); ++ ++} ++#endif ++ ++#if (YAFFS_NEW_FOLLOW_LINK == 1) ++void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias) ++{ ++ kfree(alias); ++} ++#endif ++ ++static const struct inode_operations yaffs_symlink_inode_operations = { ++ .readlink = yaffs_readlink, ++ .follow_link = yaffs_follow_link, ++#if (YAFFS_NEW_FOLLOW_LINK == 1) ++ .put_link = yaffs_put_link, ++#endif ++ .setattr = yaffs_setattr, ++ .setxattr = yaffs_setxattr, ++ .getxattr = yaffs_getxattr, ++ .listxattr = yaffs_listxattr, ++ .removexattr = yaffs_removexattr, ++}; ++ ++#ifdef YAFFS_USE_OWN_IGET ++ ++static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino) ++{ ++ struct inode *inode; ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_iget for %lu", ino); ++ ++ inode = iget_locked(sb, ino); ++ if (!inode) ++ return ERR_PTR(-ENOMEM); ++ if (!(inode->i_state & I_NEW)) ++ return inode; ++ ++ /* NB This is called as a side effect of other functions, but ++ * we had to release the lock to prevent deadlocks, so ++ * need to lock again. ++ */ ++ ++ yaffs_gross_lock(dev); ++ ++ obj = yaffs_find_by_number(dev, inode->i_ino); ++ ++ yaffs_fill_inode_from_obj(inode, obj); ++ ++ yaffs_gross_unlock(dev); ++ ++ unlock_new_inode(inode); ++ return inode; ++} ++ ++#else ++ ++static void yaffs_read_inode(struct inode *inode) ++{ ++ /* NB This is called as a side effect of other functions, but ++ * we had to release the lock to prevent deadlocks, so ++ * need to lock again. ++ */ ++ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev = yaffs_super_to_dev(inode->i_sb); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_read_inode for %d", (int)inode->i_ino); ++ ++ if (current != yaffs_dev_to_lc(dev)->readdir_process) ++ yaffs_gross_lock(dev); ++ ++ obj = yaffs_find_by_number(dev, inode->i_ino); ++ ++ yaffs_fill_inode_from_obj(inode, obj); ++ ++ if (current != yaffs_dev_to_lc(dev)->readdir_process) ++ yaffs_gross_unlock(dev); ++} ++ ++#endif ++ ++ ++ ++struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, ++ struct yaffs_obj *obj) ++{ ++ struct inode *inode; ++ ++ if (!sb) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_get_inode for NULL super_block!!"); ++ return NULL; ++ ++ } ++ ++ if (!obj) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_get_inode for NULL object!!"); ++ return NULL; ++ ++ } ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_get_inode for object %d", obj->obj_id); ++ ++ inode = Y_IGET(sb, obj->obj_id); ++ if (IS_ERR(inode)) ++ return NULL; ++ ++ /* NB Side effect: iget calls back to yaffs_read_inode(). */ ++ /* iget also increments the inode's i_count */ ++ /* NB You can't be holding gross_lock or deadlock will happen! */ ++ ++ return inode; ++} ++ ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) ++#define YCRED(x) x ++#else ++#define YCRED(x) (x->cred) ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, ++ dev_t rdev) ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ dev_t rdev) ++#else ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ int rdev) ++#endif ++{ ++ struct inode *inode; ++ ++ struct yaffs_obj *obj = NULL; ++ struct yaffs_dev *dev; ++ ++ struct yaffs_obj *parent = yaffs_inode_to_obj(dir); ++ ++ int error = -ENOSPC; ++ uid_t uid = YCRED(current)->fsuid; ++ gid_t gid = ++ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; ++ ++ if ((dir->i_mode & S_ISGID) && S_ISDIR(mode)) ++ mode |= S_ISGID; ++ ++ if (parent) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_mknod: parent object %d type %d", ++ parent->obj_id, parent->variant_type); ++ } else { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_mknod: could not get parent object"); ++ return -EPERM; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_mknod: making oject for %s, mode %x dev %x", ++ dentry->d_name.name, mode, rdev); ++ ++ dev = parent->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ switch (mode & S_IFMT) { ++ default: ++ /* Special (socket, fifo, device...) */ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making special"); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ obj = ++ yaffs_create_special(parent, dentry->d_name.name, mode, uid, ++ gid, old_encode_dev(rdev)); ++#else ++ obj = ++ yaffs_create_special(parent, dentry->d_name.name, mode, uid, ++ gid, rdev); ++#endif ++ break; ++ case S_IFREG: /* file */ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making file"); ++ obj = yaffs_create_file(parent, dentry->d_name.name, mode, uid, ++ gid); ++ break; ++ case S_IFDIR: /* directory */ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making directory"); ++ obj = yaffs_create_dir(parent, dentry->d_name.name, mode, ++ uid, gid); ++ break; ++ case S_IFLNK: /* symlink */ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making symlink"); ++ obj = NULL; /* Do we ever get here? */ ++ break; ++ } ++ ++ /* Can not call yaffs_get_inode() with gross lock held */ ++ yaffs_gross_unlock(dev); ++ ++ if (obj) { ++ inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj); ++ d_instantiate(dentry, inode); ++ update_dir_time(dir); ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_mknod created object %d count = %d", ++ obj->obj_id, atomic_read(&inode->i_count)); ++ error = 0; ++ yaffs_fill_inode_from_obj(dir, parent); ++ } else { ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod failed making object"); ++ error = -ENOMEM; ++ } ++ ++ return error; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) ++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) ++#else ++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode) ++#endif ++{ ++ int ret_val; ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_mkdir"); ++ ret_val = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0); ++ return ret_val; ++} ++ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) ++static int yaffs_create(struct inode *dir, struct dentry *dentry, umode_t mode, ++ bool dummy) ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) ++static int yaffs_create(struct inode *dir, struct dentry *dentry, umode_t mode, ++ struct nameidata *n) ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, ++ struct nameidata *n) ++#else ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode) ++#endif ++{ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_create"); ++ return yaffs_mknod(dir, dentry, mode | S_IFREG, 0); ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, ++ unsigned int dummy) ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, ++ struct nameidata *n) ++#else ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry) ++#endif ++{ ++ struct yaffs_obj *obj; ++ struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */ ++ ++ struct yaffs_dev *dev = yaffs_inode_to_obj(dir)->my_dev; ++ ++ if (current != yaffs_dev_to_lc(dev)->readdir_process) ++ yaffs_gross_lock(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_lookup for %d:%s", ++ yaffs_inode_to_obj(dir)->obj_id, dentry->d_name.name); ++ ++ obj = yaffs_find_by_name(yaffs_inode_to_obj(dir), dentry->d_name.name); ++ ++ obj = yaffs_get_equivalent_obj(obj); /* in case it was a hardlink */ ++ ++ /* Can't hold gross lock when calling yaffs_get_inode() */ ++ if (current != yaffs_dev_to_lc(dev)->readdir_process) ++ yaffs_gross_unlock(dev); ++ ++ if (obj) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_lookup found %d", obj->obj_id); ++ ++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); ++ } else { ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_lookup not found"); ++ ++ } ++ ++/* added NCB for 2.5/6 compatability - forces add even if inode is ++ * NULL which creates dentry hash */ ++ d_add(dentry, inode); ++ ++ return NULL; ++} ++ ++/* ++ * Create a link... ++ */ ++static int yaffs_link(struct dentry *old_dentry, struct inode *dir, ++ struct dentry *dentry) ++{ ++ struct inode *inode = old_dentry->d_inode; ++ struct yaffs_obj *obj = NULL; ++ struct yaffs_obj *link = NULL; ++ struct yaffs_dev *dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_link"); ++ ++ obj = yaffs_inode_to_obj(inode); ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ if (!S_ISDIR(inode->i_mode)) /* Don't link directories */ ++ link = ++ yaffs_link_obj(yaffs_inode_to_obj(dir), dentry->d_name.name, ++ obj); ++ ++ if (link) { ++ set_nlink(old_dentry->d_inode, yaffs_get_obj_link_count(obj)); ++ d_instantiate(dentry, old_dentry->d_inode); ++ atomic_inc(&old_dentry->d_inode->i_count); ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_link link count %d i_count %d", ++ old_dentry->d_inode->i_nlink, ++ atomic_read(&old_dentry->d_inode->i_count)); ++ } ++ ++ yaffs_gross_unlock(dev); ++ ++ if (link) { ++ update_dir_time(dir); ++ return 0; ++ } ++ ++ return -EPERM; ++} ++ ++static int yaffs_symlink(struct inode *dir, struct dentry *dentry, ++ const char *symname) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ uid_t uid = YCRED(current)->fsuid; ++ gid_t gid = ++ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_symlink"); ++ ++ if (strnlen(dentry->d_name.name, YAFFS_MAX_NAME_LENGTH + 1) > ++ YAFFS_MAX_NAME_LENGTH) ++ return -ENAMETOOLONG; ++ ++ if (strnlen(symname, YAFFS_MAX_ALIAS_LENGTH + 1) > ++ YAFFS_MAX_ALIAS_LENGTH) ++ return -ENAMETOOLONG; ++ ++ dev = yaffs_inode_to_obj(dir)->my_dev; ++ yaffs_gross_lock(dev); ++ obj = yaffs_create_symlink(yaffs_inode_to_obj(dir), dentry->d_name.name, ++ S_IFLNK | S_IRWXUGO, uid, gid, symname); ++ yaffs_gross_unlock(dev); ++ ++ if (obj) { ++ struct inode *inode; ++ ++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); ++ d_instantiate(dentry, inode); ++ update_dir_time(dir); ++ yaffs_trace(YAFFS_TRACE_OS, "symlink created OK"); ++ return 0; ++ } else { ++ yaffs_trace(YAFFS_TRACE_OS, "symlink not created"); ++ } ++ ++ return -ENOMEM; ++} ++ ++/* ++ * The VFS layer already does all the dentry stuff for rename. ++ * ++ * NB: POSIX says you can rename an object over an old object of the same name ++ */ ++static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, ++ struct inode *new_dir, struct dentry *new_dentry) ++{ ++ struct yaffs_dev *dev; ++ int ret_val = YAFFS_FAIL; ++ struct yaffs_obj *target; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_rename"); ++ dev = yaffs_inode_to_obj(old_dir)->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ /* Check if the target is an existing directory that is not empty. */ ++ target = yaffs_find_by_name(yaffs_inode_to_obj(new_dir), ++ new_dentry->d_name.name); ++ ++ if (target && target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY && ++ !list_empty(&target->variant.dir_variant.children)) { ++ ++ yaffs_trace(YAFFS_TRACE_OS, "target is non-empty dir"); ++ ++ ret_val = YAFFS_FAIL; ++ } else { ++ /* Now does unlinking internally using shadowing mechanism */ ++ yaffs_trace(YAFFS_TRACE_OS, "calling yaffs_rename_obj"); ++ ++ ret_val = yaffs_rename_obj(yaffs_inode_to_obj(old_dir), ++ old_dentry->d_name.name, ++ yaffs_inode_to_obj(new_dir), ++ new_dentry->d_name.name); ++ } ++ yaffs_gross_unlock(dev); ++ ++ if (ret_val == YAFFS_OK) { ++ if (target) ++ inode_dec_link_count(new_dentry->d_inode); ++ ++ update_dir_time(old_dir); ++ if (old_dir != new_dir) ++ update_dir_time(new_dir); ++ return 0; ++ } else { ++ return -ENOTEMPTY; ++ } ++} ++ ++ ++ ++ ++static int yaffs_unlink(struct inode *dir, struct dentry *dentry) ++{ ++ int ret_val; ++ ++ struct yaffs_dev *dev; ++ struct yaffs_obj *obj; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_unlink %d:%s", ++ (int)(dir->i_ino), dentry->d_name.name); ++ obj = yaffs_inode_to_obj(dir); ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ ret_val = yaffs_unlinker(obj, dentry->d_name.name); ++ ++ if (ret_val == YAFFS_OK) { ++ inode_dec_link_count(dentry->d_inode); ++ dir->i_version++; ++ yaffs_gross_unlock(dev); ++ update_dir_time(dir); ++ return 0; ++ } ++ yaffs_gross_unlock(dev); ++ return -ENOTEMPTY; ++} ++ ++ ++ ++static const struct inode_operations yaffs_dir_inode_operations = { ++ .create = yaffs_create, ++ .lookup = yaffs_lookup, ++ .link = yaffs_link, ++ .unlink = yaffs_unlink, ++ .symlink = yaffs_symlink, ++ .mkdir = yaffs_mkdir, ++ .rmdir = yaffs_unlink, ++ .mknod = yaffs_mknod, ++ .rename = yaffs_rename, ++ .setattr = yaffs_setattr, ++ .setxattr = yaffs_setxattr, ++ .getxattr = yaffs_getxattr, ++ .listxattr = yaffs_listxattr, ++ .removexattr = yaffs_removexattr, ++}; ++ ++/*-----------------------------------------------------------------*/ ++/* Directory search context allows us to unlock access to yaffs during ++ * filldir without causing problems with the directory being modified. ++ * This is similar to the tried and tested mechanism used in yaffs direct. ++ * ++ * A search context iterates along a doubly linked list of siblings in the ++ * directory. If the iterating object is deleted then this would corrupt ++ * the list iteration, likely causing a crash. The search context avoids ++ * this by using the remove_obj_fn to move the search context to the ++ * next object before the object is deleted. ++ * ++ * Many readdirs (and thus seach conexts) may be alive simulateously so ++ * each struct yaffs_dev has a list of these. ++ * ++ * A seach context lives for the duration of a readdir. ++ * ++ * All these functions must be called while yaffs is locked. ++ */ ++ ++struct yaffs_search_context { ++ struct yaffs_dev *dev; ++ struct yaffs_obj *dir_obj; ++ struct yaffs_obj *next_return; ++ struct list_head others; ++}; ++ ++/* ++ * yaffs_new_search() creates a new search context, initialises it and ++ * adds it to the device's search context list. ++ * ++ * Called at start of readdir. ++ */ ++static struct yaffs_search_context *yaffs_new_search(struct yaffs_obj *dir) ++{ ++ struct yaffs_dev *dev = dir->my_dev; ++ struct yaffs_search_context *sc = ++ kmalloc(sizeof(struct yaffs_search_context), GFP_NOFS); ++ if (sc) { ++ sc->dir_obj = dir; ++ sc->dev = dev; ++ if (list_empty(&sc->dir_obj->variant.dir_variant.children)) ++ sc->next_return = NULL; ++ else ++ sc->next_return = ++ list_entry(dir->variant.dir_variant.children.next, ++ struct yaffs_obj, siblings); ++ INIT_LIST_HEAD(&sc->others); ++ list_add(&sc->others, &(yaffs_dev_to_lc(dev)->search_contexts)); ++ } ++ return sc; ++} ++ ++/* ++ * yaffs_search_end() disposes of a search context and cleans up. ++ */ ++static void yaffs_search_end(struct yaffs_search_context *sc) ++{ ++ if (sc) { ++ list_del(&sc->others); ++ kfree(sc); ++ } ++} ++ ++/* ++ * yaffs_search_advance() moves a search context to the next object. ++ * Called when the search iterates or when an object removal causes ++ * the search context to be moved to the next object. ++ */ ++static void yaffs_search_advance(struct yaffs_search_context *sc) ++{ ++ if (!sc) ++ return; ++ ++ if (sc->next_return == NULL || ++ list_empty(&sc->dir_obj->variant.dir_variant.children)) ++ sc->next_return = NULL; ++ else { ++ struct list_head *next = sc->next_return->siblings.next; ++ ++ if (next == &sc->dir_obj->variant.dir_variant.children) ++ sc->next_return = NULL; /* end of list */ ++ else ++ sc->next_return = ++ list_entry(next, struct yaffs_obj, siblings); ++ } ++} ++ ++/* ++ * yaffs_remove_obj_callback() is called when an object is unlinked. ++ * We check open search contexts and advance any which are currently ++ * on the object being iterated. ++ */ ++static void yaffs_remove_obj_callback(struct yaffs_obj *obj) ++{ ++ ++ struct list_head *i; ++ struct yaffs_search_context *sc; ++ struct list_head *search_contexts = ++ &(yaffs_dev_to_lc(obj->my_dev)->search_contexts); ++ ++ /* Iterate through the directory search contexts. ++ * If any are currently on the object being removed, then advance ++ * the search context to the next object to prevent a hanging pointer. ++ */ ++ list_for_each(i, search_contexts) { ++ sc = list_entry(i, struct yaffs_search_context, others); ++ if (sc->next_return == obj) ++ yaffs_search_advance(sc); ++ } ++ ++} ++ ++ ++/*-----------------------------------------------------------------*/ ++ ++static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ struct yaffs_search_context *sc; ++ struct inode *inode = f->f_dentry->d_inode; ++ unsigned long offset, curoffs; ++ struct yaffs_obj *l; ++ int ret_val = 0; ++ ++ char name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ obj = yaffs_dentry_to_obj(f->f_dentry); ++ dev = obj->my_dev; ++ ++ yaffs_gross_lock(dev); ++ ++ yaffs_dev_to_lc(dev)->readdir_process = current; ++ ++ offset = f->f_pos; ++ ++ sc = yaffs_new_search(obj); ++ if (!sc) { ++ ret_val = -ENOMEM; ++ goto out; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_readdir: starting at %d", (int)offset); ++ ++ if (offset == 0) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_readdir: entry . ino %d", ++ (int)inode->i_ino); ++ yaffs_gross_unlock(dev); ++ if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0) { ++ yaffs_gross_lock(dev); ++ goto out; ++ } ++ yaffs_gross_lock(dev); ++ offset++; ++ f->f_pos++; ++ } ++ if (offset == 1) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_readdir: entry .. ino %d", ++ (int)f->f_dentry->d_parent->d_inode->i_ino); ++ yaffs_gross_unlock(dev); ++ if (filldir(dirent, "..", 2, offset, ++ f->f_dentry->d_parent->d_inode->i_ino, ++ DT_DIR) < 0) { ++ yaffs_gross_lock(dev); ++ goto out; ++ } ++ yaffs_gross_lock(dev); ++ offset++; ++ f->f_pos++; ++ } ++ ++ curoffs = 1; ++ ++ /* If the directory has changed since the open or last call to ++ readdir, rewind to after the 2 canned entries. */ ++ if (f->f_version != inode->i_version) { ++ offset = 2; ++ f->f_pos = offset; ++ f->f_version = inode->i_version; ++ } ++ ++ while (sc->next_return) { ++ curoffs++; ++ l = sc->next_return; ++ if (curoffs >= offset) { ++ int this_inode = yaffs_get_obj_inode(l); ++ int this_type = yaffs_get_obj_type(l); ++ ++ yaffs_get_obj_name(l, name, YAFFS_MAX_NAME_LENGTH + 1); ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_readdir: %s inode %d", ++ name, yaffs_get_obj_inode(l)); ++ ++ yaffs_gross_unlock(dev); ++ ++ if (filldir(dirent, ++ name, ++ strlen(name), ++ offset, this_inode, this_type) < 0) { ++ yaffs_gross_lock(dev); ++ goto out; ++ } ++ ++ yaffs_gross_lock(dev); ++ ++ offset++; ++ f->f_pos++; ++ } ++ yaffs_search_advance(sc); ++ } ++ ++out: ++ yaffs_search_end(sc); ++ yaffs_dev_to_lc(dev)->readdir_process = NULL; ++ yaffs_gross_unlock(dev); ++ ++ return ret_val; ++} ++ ++static const struct file_operations yaffs_dir_operations = { ++ .read = generic_read_dir, ++ .readdir = yaffs_readdir, ++ .fsync = yaffs_sync_object, ++ .llseek = generic_file_llseek, ++}; ++ ++static void yaffs_fill_inode_from_obj(struct inode *inode, ++ struct yaffs_obj *obj) ++{ ++ if (inode && obj) { ++ ++ /* Check mode against the variant type and attempt to repair if broken. */ ++ u32 mode = obj->yst_mode; ++ switch (obj->variant_type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ if (!S_ISREG(mode)) { ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFREG; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ if (!S_ISLNK(mode)) { ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFLNK; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ if (!S_ISDIR(mode)) { ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFDIR; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ default: ++ /* TODO? */ ++ break; ++ } ++ ++ inode->i_flags |= S_NOATIME; ++ ++ inode->i_ino = obj->obj_id; ++ inode->i_mode = obj->yst_mode; ++ inode->i_uid = obj->yst_uid; ++ inode->i_gid = obj->yst_gid; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) ++ inode->i_blksize = inode->i_sb->s_blocksize; ++#endif ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ ++ inode->i_rdev = old_decode_dev(obj->yst_rdev); ++ inode->i_atime.tv_sec = (time_t) (obj->yst_atime); ++ inode->i_atime.tv_nsec = 0; ++ inode->i_mtime.tv_sec = (time_t) obj->yst_mtime; ++ inode->i_mtime.tv_nsec = 0; ++ inode->i_ctime.tv_sec = (time_t) obj->yst_ctime; ++ inode->i_ctime.tv_nsec = 0; ++#else ++ inode->i_rdev = obj->yst_rdev; ++ inode->i_atime = obj->yst_atime; ++ inode->i_mtime = obj->yst_mtime; ++ inode->i_ctime = obj->yst_ctime; ++#endif ++ inode->i_size = yaffs_get_obj_length(obj); ++ inode->i_blocks = (inode->i_size + 511) >> 9; ++ ++ set_nlink(inode, yaffs_get_obj_link_count(obj)); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_fill_inode mode %x uid %d gid %d size %lld count %d", ++ inode->i_mode, inode->i_uid, inode->i_gid, ++ inode->i_size, atomic_read(&inode->i_count)); ++ ++ switch (obj->yst_mode & S_IFMT) { ++ default: /* fifo, device or socket */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ init_special_inode(inode, obj->yst_mode, ++ old_decode_dev(obj->yst_rdev)); ++#else ++ init_special_inode(inode, obj->yst_mode, ++ (dev_t) (obj->yst_rdev)); ++#endif ++ break; ++ case S_IFREG: /* file */ ++ inode->i_op = &yaffs_file_inode_operations; ++ inode->i_fop = &yaffs_file_operations; ++ inode->i_mapping->a_ops = ++ &yaffs_file_address_operations; ++ break; ++ case S_IFDIR: /* directory */ ++ inode->i_op = &yaffs_dir_inode_operations; ++ inode->i_fop = &yaffs_dir_operations; ++ break; ++ case S_IFLNK: /* symlink */ ++ inode->i_op = &yaffs_symlink_inode_operations; ++ break; ++ } ++ ++ yaffs_inode_to_obj_lv(inode) = obj; ++ ++ obj->my_inode = inode; ++ ++ } else { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_fill_inode invalid parameters"); ++ } ++ ++} ++ ++ ++ ++/* ++ * yaffs background thread functions . ++ * yaffs_bg_thread_fn() the thread function ++ * yaffs_bg_start() launches the background thread. ++ * yaffs_bg_stop() cleans up the background thread. ++ * ++ * NB: ++ * The thread should only run after the yaffs is initialised ++ * The thread should be stopped before yaffs is unmounted. ++ * The thread should not do any writing while the fs is in read only. ++ */ ++ ++static unsigned yaffs_bg_gc_urgency(struct yaffs_dev *dev) ++{ ++ unsigned erased_chunks = ++ dev->n_erased_blocks * dev->param.chunks_per_block; ++ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); ++ unsigned scattered = 0; /* Free chunks not in an erased block */ ++ ++ if (erased_chunks < dev->n_free_chunks) ++ scattered = (dev->n_free_chunks - erased_chunks); ++ ++ if (!context->bg_running) ++ return 0; ++ else if (scattered < (dev->param.chunks_per_block * 2)) ++ return 0; ++ else if (erased_chunks > dev->n_free_chunks / 2) ++ return 0; ++ else if (erased_chunks > dev->n_free_chunks / 4) ++ return 1; ++ else ++ return 2; ++} ++ ++#ifdef YAFFS_COMPILE_BACKGROUND ++ ++void yaffs_background_waker(unsigned long data) ++{ ++ wake_up_process((struct task_struct *)data); ++} ++ ++static int yaffs_bg_thread_fn(void *data) ++{ ++ struct yaffs_dev *dev = (struct yaffs_dev *)data; ++ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); ++ unsigned long now = jiffies; ++ unsigned long next_dir_update = now; ++ unsigned long next_gc = now; ++ unsigned long expires; ++ unsigned int urgency; ++ ++ int gc_result; ++ struct timer_list timer; ++ ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, ++ "yaffs_background starting for dev %p", (void *)dev); ++ ++#ifdef YAFFS_COMPILE_FREEZER ++ set_freezable(); ++#endif ++ while (context->bg_running) { ++ yaffs_trace(YAFFS_TRACE_BACKGROUND, "yaffs_background"); ++ ++ if (kthread_should_stop()) ++ break; ++ ++#ifdef YAFFS_COMPILE_FREEZER ++ if (try_to_freeze()) ++ continue; ++#endif ++ yaffs_gross_lock(dev); ++ ++ now = jiffies; ++ ++ if (time_after(now, next_dir_update) && yaffs_bg_enable) { ++ yaffs_update_dirty_dirs(dev); ++ next_dir_update = now + HZ; ++ } ++ ++ if (time_after(now, next_gc) && yaffs_bg_enable) { ++ if (!dev->is_checkpointed) { ++ urgency = yaffs_bg_gc_urgency(dev); ++ gc_result = yaffs_bg_gc(dev, urgency); ++ if (urgency > 1) ++ next_gc = now + HZ / 20 + 1; ++ else if (urgency > 0) ++ next_gc = now + HZ / 10 + 1; ++ else ++ next_gc = now + HZ * 2; ++ } else { ++ /* ++ * gc not running so set to next_dir_update ++ * to cut down on wake ups ++ */ ++ next_gc = next_dir_update; ++ } ++ } ++ yaffs_gross_unlock(dev); ++#if 1 ++ expires = next_dir_update; ++ if (time_before(next_gc, expires)) ++ expires = next_gc; ++ if (time_before(expires, now)) ++ expires = now + HZ; ++ ++ Y_INIT_TIMER(&timer); ++ timer.expires = expires + 1; ++ timer.data = (unsigned long)current; ++ timer.function = yaffs_background_waker; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ add_timer(&timer); ++ schedule(); ++ del_timer_sync(&timer); ++#else ++ msleep(10); ++#endif ++ } ++ ++ return 0; ++} ++ ++static int yaffs_bg_start(struct yaffs_dev *dev) ++{ ++ int retval = 0; ++ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); ++ ++ if (dev->read_only) ++ return -1; ++ ++ context->bg_running = 1; ++ ++ context->bg_thread = kthread_run(yaffs_bg_thread_fn, ++ (void *)dev, "yaffs-bg-%d", ++ context->mount_id); ++ ++ if (IS_ERR(context->bg_thread)) { ++ retval = PTR_ERR(context->bg_thread); ++ context->bg_thread = NULL; ++ context->bg_running = 0; ++ } ++ return retval; ++} ++ ++static void yaffs_bg_stop(struct yaffs_dev *dev) ++{ ++ struct yaffs_linux_context *ctxt = yaffs_dev_to_lc(dev); ++ ++ ctxt->bg_running = 0; ++ ++ if (ctxt->bg_thread) { ++ kthread_stop(ctxt->bg_thread); ++ ctxt->bg_thread = NULL; ++ } ++} ++#else ++static int yaffs_bg_thread_fn(void *data) ++{ ++ return 0; ++} ++ ++static int yaffs_bg_start(struct yaffs_dev *dev) ++{ ++ return 0; ++} ++ ++static void yaffs_bg_stop(struct yaffs_dev *dev) ++{ ++} ++#endif ++ ++ ++static void yaffs_flush_inodes(struct super_block *sb) ++{ ++ struct inode *iptr; ++ struct yaffs_obj *obj; ++ ++ list_for_each_entry(iptr, &sb->s_inodes, i_sb_list) { ++ obj = yaffs_inode_to_obj(iptr); ++ if (obj) { ++ yaffs_trace(YAFFS_TRACE_OS, ++ "flushing obj %d", ++ obj->obj_id); ++ yaffs_flush_file(obj, 1, 0); ++ } ++ } ++} ++ ++static void yaffs_flush_super(struct super_block *sb, int do_checkpoint) ++{ ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++ if (!dev) ++ return; ++ ++ yaffs_flush_inodes(sb); ++ yaffs_update_dirty_dirs(dev); ++ yaffs_flush_whole_cache(dev); ++ if (do_checkpoint) ++ yaffs_checkpoint_save(dev); ++} ++ ++static LIST_HEAD(yaffs_context_list); ++struct mutex yaffs_context_lock; ++ ++static void yaffs_put_super(struct super_block *sb) ++{ ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_ALWAYS, ++ "yaffs_put_super"); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, ++ "Shutting down yaffs background thread"); ++ yaffs_bg_stop(dev); ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, ++ "yaffs background thread shut down"); ++ ++ yaffs_gross_lock(dev); ++ ++ yaffs_flush_super(sb, 1); ++ ++ yaffs_deinitialise(dev); ++ ++ yaffs_gross_unlock(dev); ++ ++ mutex_lock(&yaffs_context_lock); ++ list_del_init(&(yaffs_dev_to_lc(dev)->context_list)); ++ mutex_unlock(&yaffs_context_lock); ++ ++ if (yaffs_dev_to_lc(dev)->spare_buffer) { ++ kfree(yaffs_dev_to_lc(dev)->spare_buffer); ++ yaffs_dev_to_lc(dev)->spare_buffer = NULL; ++ } ++ ++ kfree(dev); ++ ++ yaffs_put_mtd_device(mtd); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_ALWAYS, ++ "yaffs_put_super done"); ++} ++ ++ ++static unsigned yaffs_gc_control_callback(struct yaffs_dev *dev) ++{ ++ return yaffs_gc_control; ++} ++ ++ ++#ifdef YAFFS_COMPILE_EXPORTFS ++ ++static struct inode *yaffs2_nfs_get_inode(struct super_block *sb, uint64_t ino, ++ uint32_t generation) ++{ ++ return Y_IGET(sb, ino); ++} ++ ++static struct dentry *yaffs2_fh_to_dentry(struct super_block *sb, ++ struct fid *fid, int fh_len, ++ int fh_type) ++{ ++ return generic_fh_to_dentry(sb, fid, fh_len, fh_type, ++ yaffs2_nfs_get_inode); ++} ++ ++static struct dentry *yaffs2_fh_to_parent(struct super_block *sb, ++ struct fid *fid, int fh_len, ++ int fh_type) ++{ ++ return generic_fh_to_parent(sb, fid, fh_len, fh_type, ++ yaffs2_nfs_get_inode); ++} ++ ++struct dentry *yaffs2_get_parent(struct dentry *dentry) ++{ ++ ++ struct super_block *sb = dentry->d_inode->i_sb; ++ struct dentry *parent = ERR_PTR(-ENOENT); ++ struct inode *inode; ++ unsigned long parent_ino; ++ struct yaffs_obj *d_obj; ++ struct yaffs_obj *parent_obj; ++ ++ d_obj = yaffs_inode_to_obj(dentry->d_inode); ++ ++ if (d_obj) { ++ parent_obj = d_obj->parent; ++ if (parent_obj) { ++ parent_ino = yaffs_get_obj_inode(parent_obj); ++ inode = Y_IGET(sb, parent_ino); ++ ++ if (IS_ERR(inode)) { ++ parent = ERR_CAST(inode); ++ } else { ++ parent = d_obtain_alias(inode); ++ if (!IS_ERR(parent)) { ++ parent = ERR_PTR(-ENOMEM); ++ iput(inode); ++ } ++ } ++ } ++ } ++ ++ return parent; ++} ++ ++/* Just declare a zero structure as a NULL value implies ++ * using the default functions of exportfs. ++ */ ++ ++static struct export_operations yaffs_export_ops = { ++ .fh_to_dentry = yaffs2_fh_to_dentry, ++ .fh_to_parent = yaffs2_fh_to_parent, ++ .get_parent = yaffs2_get_parent, ++}; ++ ++#endif ++ ++static void yaffs_unstitch_obj(struct inode *inode, struct yaffs_obj *obj) ++{ ++ /* Clear the association between the inode and ++ * the struct yaffs_obj. ++ */ ++ obj->my_inode = NULL; ++ yaffs_inode_to_obj_lv(inode) = NULL; ++ ++ /* If the object freeing was deferred, then the real ++ * free happens now. ++ * This should fix the inode inconsistency problem. ++ */ ++ yaffs_handle_defered_free(obj); ++} ++ ++#ifdef YAFFS_HAS_EVICT_INODE ++/* yaffs_evict_inode combines into one operation what was previously done in ++ * yaffs_clear_inode() and yaffs_delete_inode() ++ * ++ */ ++static void yaffs_evict_inode(struct inode *inode) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ int deleteme = 0; ++ ++ obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_evict_inode: ino %d, count %d %s", ++ (int)inode->i_ino, atomic_read(&inode->i_count), ++ obj ? "object exists" : "null object"); ++ ++ if (!inode->i_nlink && !is_bad_inode(inode)) ++ deleteme = 1; ++ truncate_inode_pages(&inode->i_data, 0); ++ Y_CLEAR_INODE(inode); ++ ++ if (deleteme && obj) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ yaffs_del_obj(obj); ++ yaffs_gross_unlock(dev); ++ } ++ if (obj) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ yaffs_unstitch_obj(inode, obj); ++ yaffs_gross_unlock(dev); ++ } ++} ++#else ++ ++/* clear is called to tell the fs to release any per-inode data it holds. ++ * The object might still exist on disk and is just being thrown out of the cache ++ * or else the object has actually been deleted and we're being called via ++ * the chain ++ * yaffs_delete_inode() -> clear_inode()->yaffs_clear_inode() ++ */ ++ ++static void yaffs_clear_inode(struct inode *inode) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_dev *dev; ++ ++ obj = yaffs_inode_to_obj(inode); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_clear_inode: ino %d, count %d %s", ++ (int)inode->i_ino, atomic_read(&inode->i_count), ++ obj ? "object exists" : "null object"); ++ ++ if (obj) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ yaffs_unstitch_obj(inode, obj); ++ yaffs_gross_unlock(dev); ++ } ++ ++} ++ ++/* delete is called when the link count is zero and the inode ++ * is put (ie. nobody wants to know about it anymore, time to ++ * delete the file). ++ * NB Must call clear_inode() ++ */ ++static void yaffs_delete_inode(struct inode *inode) ++{ ++ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); ++ struct yaffs_dev *dev; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_delete_inode: ino %d, count %d %s", ++ (int)inode->i_ino, atomic_read(&inode->i_count), ++ obj ? "object exists" : "null object"); ++ ++ if (obj) { ++ dev = obj->my_dev; ++ yaffs_gross_lock(dev); ++ yaffs_del_obj(obj); ++ yaffs_gross_unlock(dev); ++ } ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) ++ truncate_inode_pages(&inode->i_data, 0); ++#endif ++ clear_inode(inode); ++} ++#endif ++ ++ ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf) ++{ ++ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; ++ struct super_block *sb = dentry->d_sb; ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf) ++{ ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++#else ++static int yaffs_statfs(struct super_block *sb, struct statfs *buf) ++{ ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++#endif ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_statfs"); ++ ++ yaffs_gross_lock(dev); ++ ++ buf->f_type = YAFFS_MAGIC; ++ buf->f_bsize = sb->s_blocksize; ++ buf->f_namelen = 255; ++ ++ if (dev->data_bytes_per_chunk & (dev->data_bytes_per_chunk - 1)) { ++ /* Do this if chunk size is not a power of 2 */ ++ ++ uint64_t bytes_in_dev; ++ uint64_t bytes_free; ++ ++ bytes_in_dev = ++ ((uint64_t) ++ ((dev->param.end_block - dev->param.start_block + ++ 1))) * ((uint64_t) (dev->param.chunks_per_block * ++ dev->data_bytes_per_chunk)); ++ ++ do_div(bytes_in_dev, sb->s_blocksize); /* bytes_in_dev becomes the number of blocks */ ++ buf->f_blocks = bytes_in_dev; ++ ++ bytes_free = ((uint64_t) (yaffs_get_n_free_chunks(dev))) * ++ ((uint64_t) (dev->data_bytes_per_chunk)); ++ ++ do_div(bytes_free, sb->s_blocksize); ++ ++ buf->f_bfree = bytes_free; ++ ++ } else if (sb->s_blocksize > dev->data_bytes_per_chunk) { ++ ++ buf->f_blocks = ++ (dev->param.end_block - dev->param.start_block + 1) * ++ dev->param.chunks_per_block / ++ (sb->s_blocksize / dev->data_bytes_per_chunk); ++ buf->f_bfree = ++ yaffs_get_n_free_chunks(dev) / ++ (sb->s_blocksize / dev->data_bytes_per_chunk); ++ } else { ++ buf->f_blocks = ++ (dev->param.end_block - dev->param.start_block + 1) * ++ dev->param.chunks_per_block * ++ (dev->data_bytes_per_chunk / sb->s_blocksize); ++ ++ buf->f_bfree = ++ yaffs_get_n_free_chunks(dev) * ++ (dev->data_bytes_per_chunk / sb->s_blocksize); ++ } ++ ++ buf->f_files = 0; ++ buf->f_ffree = 0; ++ buf->f_bavail = buf->f_bfree; ++ ++ yaffs_gross_unlock(dev); ++ return 0; ++} ++ ++ ++ ++static int yaffs_do_sync_fs(struct super_block *sb, int request_checkpoint) ++{ ++ ++ struct yaffs_dev *dev = yaffs_super_to_dev(sb); ++ unsigned int oneshot_checkpoint = (yaffs_auto_checkpoint & 4); ++ unsigned gc_urgent = yaffs_bg_gc_urgency(dev); ++ int do_checkpoint; ++ int dirty = yaffs_check_super_dirty(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, ++ "yaffs_do_sync_fs: gc-urgency %d %s %s%s", ++ gc_urgent, ++ dirty ? "dirty" : "clean", ++ request_checkpoint ? "checkpoint requested" : "no checkpoint", ++ oneshot_checkpoint ? " one-shot" : ""); ++ ++ yaffs_gross_lock(dev); ++ do_checkpoint = ((request_checkpoint && !gc_urgent) || ++ oneshot_checkpoint) && !dev->is_checkpointed; ++ ++ if (dirty || do_checkpoint) { ++ yaffs_flush_super(sb, !dev->is_checkpointed && do_checkpoint); ++ yaffs_clear_super_dirty(dev); ++ if (oneshot_checkpoint) ++ yaffs_auto_checkpoint &= ~4; ++ } ++ yaffs_gross_unlock(dev); ++ ++ return 0; ++} ++ ++ ++#ifdef YAFFS_HAS_WRITE_SUPER ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static void yaffs_write_super(struct super_block *sb) ++#else ++static int yaffs_write_super(struct super_block *sb) ++#endif ++{ ++ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 2); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, ++ "yaffs_write_super %s", ++ request_checkpoint ? " checkpt" : ""); ++ ++ yaffs_do_sync_fs(sb, request_checkpoint); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ return 0; ++#endif ++} ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static int yaffs_sync_fs(struct super_block *sb, int wait) ++#else ++static int yaffs_sync_fs(struct super_block *sb) ++#endif ++{ ++ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 1); ++ ++ yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, ++ "yaffs_sync_fs%s", request_checkpoint ? " checkpt" : ""); ++ ++ yaffs_do_sync_fs(sb, request_checkpoint); ++ ++ return 0; ++} ++ ++ ++ ++static const struct super_operations yaffs_super_ops = { ++ .statfs = yaffs_statfs, ++ ++#ifndef YAFFS_USE_OWN_IGET ++ .read_inode = yaffs_read_inode, ++#endif ++#ifdef YAFFS_HAS_PUT_INODE ++ .put_inode = yaffs_put_inode, ++#endif ++ .put_super = yaffs_put_super, ++#ifdef YAFFS_HAS_EVICT_INODE ++ .evict_inode = yaffs_evict_inode, ++#else ++ .delete_inode = yaffs_delete_inode, ++ .clear_inode = yaffs_clear_inode, ++#endif ++ .sync_fs = yaffs_sync_fs, ++#ifdef YAFFS_HAS_WRITE_SUPER ++ .write_super = yaffs_write_super, ++#endif ++}; ++ ++struct yaffs_options { ++ int inband_tags; ++ int skip_checkpoint_read; ++ int skip_checkpoint_write; ++ int no_cache; ++ int tags_ecc_on; ++ int tags_ecc_overridden; ++ int lazy_loading_enabled; ++ int lazy_loading_overridden; ++ int empty_lost_and_found; ++ int empty_lost_and_found_overridden; ++ int disable_summary; ++}; ++ ++#define MAX_OPT_LEN 30 ++static int yaffs_parse_options(struct yaffs_options *options, ++ const char *options_str) ++{ ++ char cur_opt[MAX_OPT_LEN + 1]; ++ int p; ++ int error = 0; ++ ++ /* Parse through the options which is a comma seperated list */ ++ ++ while (options_str && *options_str && !error) { ++ memset(cur_opt, 0, MAX_OPT_LEN + 1); ++ p = 0; ++ ++ while (*options_str == ',') ++ options_str++; ++ ++ while (*options_str && *options_str != ',') { ++ if (p < MAX_OPT_LEN) { ++ cur_opt[p] = *options_str; ++ p++; ++ } ++ options_str++; ++ } ++ ++ if (!strcmp(cur_opt, "inband-tags")) { ++ options->inband_tags = 1; ++ } else if (!strcmp(cur_opt, "tags-ecc-off")) { ++ options->tags_ecc_on = 0; ++ options->tags_ecc_overridden = 1; ++ } else if (!strcmp(cur_opt, "tags-ecc-on")) { ++ options->tags_ecc_on = 1; ++ options->tags_ecc_overridden = 1; ++ } else if (!strcmp(cur_opt, "lazy-loading-off")) { ++ options->lazy_loading_enabled = 0; ++ options->lazy_loading_overridden = 1; ++ } else if (!strcmp(cur_opt, "lazy-loading-on")) { ++ options->lazy_loading_enabled = 1; ++ options->lazy_loading_overridden = 1; ++ } else if (!strcmp(cur_opt, "disable-summary")) { ++ options->disable_summary = 1; ++ } else if (!strcmp(cur_opt, "empty-lost-and-found-off")) { ++ options->empty_lost_and_found = 0; ++ options->empty_lost_and_found_overridden = 1; ++ } else if (!strcmp(cur_opt, "empty-lost-and-found-on")) { ++ options->empty_lost_and_found = 1; ++ options->empty_lost_and_found_overridden = 1; ++ } else if (!strcmp(cur_opt, "no-cache")) { ++ options->no_cache = 1; ++ } else if (!strcmp(cur_opt, "no-checkpoint-read")) { ++ options->skip_checkpoint_read = 1; ++ } else if (!strcmp(cur_opt, "no-checkpoint-write")) { ++ options->skip_checkpoint_write = 1; ++ } else if (!strcmp(cur_opt, "no-checkpoint")) { ++ options->skip_checkpoint_read = 1; ++ options->skip_checkpoint_write = 1; ++ } else { ++ printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n", ++ cur_opt); ++ error = 1; ++ } ++ } ++ ++ return error; ++} ++ ++ ++static struct dentry *yaffs_make_root(struct inode *inode) ++{ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) ++ struct dentry *root = d_alloc_root(inode); ++ ++ if (!root) ++ iput(inode); ++ ++ return root; ++#else ++ return d_make_root(inode); ++#endif ++} ++ ++ ++ ++ ++static struct super_block *yaffs_internal_read_super(int yaffs_version, ++ struct super_block *sb, ++ void *data, int silent) ++{ ++ int n_blocks; ++ struct inode *inode = NULL; ++ struct dentry *root; ++ struct yaffs_dev *dev = 0; ++ char devname_buf[BDEVNAME_SIZE + 1]; ++ struct mtd_info *mtd; ++ int err; ++ char *data_str = (char *)data; ++ struct yaffs_linux_context *context = NULL; ++ struct yaffs_param *param; ++ ++ int read_only = 0; ++ int inband_tags = 0; ++ ++ struct yaffs_options options; ++ ++ unsigned mount_id; ++ int found; ++ struct yaffs_linux_context *context_iterator; ++ struct list_head *l; ++ ++ if (!sb) { ++ printk(KERN_INFO "yaffs: sb is NULL\n"); ++ return NULL; ++ } ++ ++ sb->s_magic = YAFFS_MAGIC; ++ sb->s_op = &yaffs_super_ops; ++ sb->s_flags |= MS_NOATIME; ++ ++ read_only = ((sb->s_flags & MS_RDONLY) != 0); ++ ++#ifdef YAFFS_COMPILE_EXPORTFS ++ sb->s_export_op = &yaffs_export_ops; ++#endif ++ ++ if (!sb->s_dev) ++ printk(KERN_INFO "yaffs: sb->s_dev is NULL\n"); ++ else if (!yaffs_devname(sb, devname_buf)) ++ printk(KERN_INFO "yaffs: devname is NULL\n"); ++ else ++ printk(KERN_INFO "yaffs: dev is %d name is \"%s\" %s\n", ++ sb->s_dev, ++ yaffs_devname(sb, devname_buf), read_only ? "ro" : "rw"); ++ ++ if (!data_str) ++ data_str = ""; ++ ++ printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str); ++ ++ memset(&options, 0, sizeof(options)); ++ ++ if (yaffs_parse_options(&options, data_str)) { ++ /* Option parsing failed */ ++ return NULL; ++ } ++ ++ sb->s_blocksize = PAGE_CACHE_SIZE; ++ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_read_super: Using yaffs%d", yaffs_version); ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_read_super: block size %d", (int)(sb->s_blocksize)); ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: Attempting MTD mount of %u.%u,\"%s\"", ++ MAJOR(sb->s_dev), MINOR(sb->s_dev), ++ yaffs_devname(sb, devname_buf)); ++ ++ /* Get the device */ ++ mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); ++ if (IS_ERR(mtd)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs: MTD device %u either not valid or unavailable", ++ MINOR(sb->s_dev)); ++ return NULL; ++ } ++ ++ if (yaffs_auto_select && yaffs_version == 1 && WRITE_SIZE(mtd) >= 2048) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs2"); ++ yaffs_version = 2; ++ } ++ ++ /* Added NCB 26/5/2006 for completeness */ ++ if (yaffs_version == 2 && !options.inband_tags ++ && WRITE_SIZE(mtd) == 512) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); ++ yaffs_version = 1; ++ } ++ ++ if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || ++ options.inband_tags) ++ inband_tags = 1; ++ ++ if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) ++ return NULL; ++ ++ /* OK, so if we got here, we have an MTD that's NAND and looks ++ * like it has the right capabilities ++ * Set the struct yaffs_dev up for mtd ++ */ ++ ++ if (!read_only && !(mtd->flags & MTD_WRITEABLE)) { ++ read_only = 1; ++ printk(KERN_INFO ++ "yaffs: mtd is read only, setting superblock read only\n" ++ ); ++ sb->s_flags |= MS_RDONLY; ++ } ++ ++ dev = kmalloc(sizeof(struct yaffs_dev), GFP_KERNEL); ++ context = kmalloc(sizeof(struct yaffs_linux_context), GFP_KERNEL); ++ ++ if (!dev || !context) { ++ kfree(dev); ++ kfree(context); ++ dev = NULL; ++ context = NULL; ++ ++ /* Deep shit could not allocate device structure */ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs_read_super: Failed trying to allocate struct yaffs_dev." ++ ); ++ return NULL; ++ } ++ memset(dev, 0, sizeof(struct yaffs_dev)); ++ param = &(dev->param); ++ ++ memset(context, 0, sizeof(struct yaffs_linux_context)); ++ dev->os_context = context; ++ INIT_LIST_HEAD(&(context->context_list)); ++ context->dev = dev; ++ context->super = sb; ++ ++ dev->read_only = read_only; ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++ sb->s_fs_info = dev; ++#else ++ sb->u.generic_sbp = dev; ++#endif ++ ++ ++ dev->driver_context = mtd; ++ param->name = mtd->name; ++ ++ /* Set up the memory size parameters.... */ ++ ++ ++ param->n_reserved_blocks = 5; ++ param->n_caches = (options.no_cache) ? 0 : 10; ++ param->inband_tags = inband_tags; ++ ++ param->enable_xattr = 1; ++ if (options.lazy_loading_overridden) ++ param->disable_lazy_load = !options.lazy_loading_enabled; ++ ++ param->defered_dir_update = 1; ++ ++ if (options.tags_ecc_overridden) ++ param->no_tags_ecc = !options.tags_ecc_on; ++ ++ param->empty_lost_n_found = 1; ++ param->refresh_period = 500; ++ param->disable_summary = options.disable_summary; ++ ++ ++#ifdef CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING ++ param->disable_bad_block_marking = 1; ++#endif ++ if (options.empty_lost_and_found_overridden) ++ param->empty_lost_n_found = options.empty_lost_and_found; ++ ++ /* ... and the functions. */ ++ if (yaffs_version == 2) { ++ param->is_yaffs2 = 1; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++ param->total_bytes_per_chunk = mtd->writesize; ++ param->chunks_per_block = mtd->erasesize / mtd->writesize; ++#else ++ param->total_bytes_per_chunk = mtd->oobblock; ++ param->chunks_per_block = mtd->erasesize / mtd->oobblock; ++#endif ++ n_blocks = YCALCBLOCKS(mtd->size, mtd->erasesize); ++ ++ param->start_block = 0; ++ param->end_block = n_blocks - 1; ++ } else { ++ param->is_yaffs2 = 0; ++ n_blocks = YCALCBLOCKS(mtd->size, ++ YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK); ++ ++ param->chunks_per_block = YAFFS_CHUNKS_PER_BLOCK; ++ param->total_bytes_per_chunk = YAFFS_BYTES_PER_CHUNK; ++ } ++ ++ param->start_block = 0; ++ param->end_block = n_blocks - 1; ++ ++ yaffs_mtd_drv_install(dev); ++ ++ param->sb_dirty_fn = yaffs_set_super_dirty; ++ param->gc_control_fn = yaffs_gc_control_callback; ++ ++ yaffs_dev_to_lc(dev)->super = sb; ++ ++ param->use_nand_ecc = 1; ++ ++ param->skip_checkpt_rd = options.skip_checkpoint_read; ++ param->skip_checkpt_wr = options.skip_checkpoint_write; ++ ++ mutex_lock(&yaffs_context_lock); ++ /* Get a mount id */ ++ found = 0; ++ for (mount_id = 0; !found; mount_id++) { ++ found = 1; ++ list_for_each(l, &yaffs_context_list) { ++ context_iterator = ++ list_entry(l, struct yaffs_linux_context, ++ context_list); ++ if (context_iterator->mount_id == mount_id) ++ found = 0; ++ } ++ } ++ context->mount_id = mount_id; ++ ++ list_add_tail(&(yaffs_dev_to_lc(dev)->context_list), ++ &yaffs_context_list); ++ mutex_unlock(&yaffs_context_lock); ++ ++ /* Directory search handling... */ ++ INIT_LIST_HEAD(&(yaffs_dev_to_lc(dev)->search_contexts)); ++ param->remove_obj_fn = yaffs_remove_obj_callback; ++ ++ mutex_init(&(yaffs_dev_to_lc(dev)->gross_lock)); ++ ++ yaffs_gross_lock(dev); ++ ++ err = yaffs_guts_initialise(dev); ++ ++ yaffs_trace(YAFFS_TRACE_OS, ++ "yaffs_read_super: guts initialised %s", ++ (err == YAFFS_OK) ? "OK" : "FAILED"); ++ ++ if (err == YAFFS_OK) ++ yaffs_bg_start(dev); ++ ++ if (!context->bg_thread) ++ param->defered_dir_update = 0; ++ ++ sb->s_maxbytes = yaffs_max_file_size(dev); ++ ++ /* Release lock before yaffs_get_inode() */ ++ yaffs_gross_unlock(dev); ++ ++ /* Create root inode */ ++ if (err == YAFFS_OK) ++ inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0, yaffs_root(dev)); ++ ++ if (!inode) ++ return NULL; ++ ++ inode->i_op = &yaffs_dir_inode_operations; ++ inode->i_fop = &yaffs_dir_operations; ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_read_super: got root inode"); ++ ++ root = yaffs_make_root(inode); ++ ++ if (!root) ++ return NULL; ++ ++ sb->s_root = root; ++ if(!dev->is_checkpointed) ++ yaffs_set_super_dirty(dev); ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs_read_super: is_checkpointed %d", ++ dev->is_checkpointed); ++ ++ yaffs_trace(YAFFS_TRACE_OS, "yaffs_read_super: done"); ++ return sb; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++static struct dentry *yaffs_mount(struct file_system_type *fs_type, int flags, ++ const char *dev_name, void *data) ++{ ++ return mount_bdev(fs_type, flags, dev_name, data, yaffs_internal_read_super_mtd); ++} ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static int yaffs_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data, struct vfsmount *mnt) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs_internal_read_super_mtd, mnt); ++} ++#else ++static struct super_block *yaffs_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs_internal_read_super_mtd); ++} ++#endif ++ ++static struct file_system_type yaffs_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "yaffs", ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++ .mount = yaffs_mount, ++#else ++ .get_sb = yaffs_read_super, ++#endif ++ .kill_sb = kill_block_super, ++ .fs_flags = FS_REQUIRES_DEV, ++}; ++#else ++static struct super_block *yaffs_read_super(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(1, sb, data, silent); ++} ++ ++static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super, ++ FS_REQUIRES_DEV); ++#endif ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++static struct dentry *yaffs2_mount(struct file_system_type *fs_type, int flags, ++ const char *dev_name, void *data) ++{ ++ return mount_bdev(fs_type, flags, dev_name, data, yaffs2_internal_read_super_mtd); ++} ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) ++static int yaffs2_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, void *data, ++ struct vfsmount *mnt) ++{ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs2_internal_read_super_mtd, mnt); ++} ++#else ++static struct super_block *yaffs2_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs2_internal_read_super_mtd); ++} ++#endif ++ ++static struct file_system_type yaffs2_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "yaffs2", ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++ .mount = yaffs2_mount, ++#else ++ .get_sb = yaffs2_read_super, ++#endif ++ .kill_sb = kill_block_super, ++ .fs_flags = FS_REQUIRES_DEV, ++}; ++#else ++static struct super_block *yaffs2_read_super(struct super_block *sb, ++ void *data, int silent) ++{ ++ return yaffs_internal_read_super(2, sb, data, silent); ++} ++ ++static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super, ++ FS_REQUIRES_DEV); ++#endif ++ ++ ++static struct proc_dir_entry *my_proc_entry; ++ ++static char *yaffs_dump_dev_part0(char *buf, struct yaffs_dev *dev) ++{ ++ struct yaffs_param *param = &dev->param; ++ int bs[10]; ++ ++ yaffs_count_blocks_by_state(dev,bs); ++ ++ buf += sprintf(buf, "start_block.......... %d\n", param->start_block); ++ buf += sprintf(buf, "end_block............ %d\n", param->end_block); ++ buf += sprintf(buf, "total_bytes_per_chunk %d\n", ++ param->total_bytes_per_chunk); ++ buf += sprintf(buf, "use_nand_ecc......... %d\n", param->use_nand_ecc); ++ buf += sprintf(buf, "no_tags_ecc.......... %d\n", param->no_tags_ecc); ++ buf += sprintf(buf, "is_yaffs2............ %d\n", param->is_yaffs2); ++ buf += sprintf(buf, "inband_tags.......... %d\n", param->inband_tags); ++ buf += sprintf(buf, "empty_lost_n_found... %d\n", ++ param->empty_lost_n_found); ++ buf += sprintf(buf, "disable_lazy_load.... %d\n", ++ param->disable_lazy_load); ++ buf += sprintf(buf, "disable_bad_block_mrk %d\n", ++ param->disable_bad_block_marking); ++ buf += sprintf(buf, "refresh_period....... %d\n", ++ param->refresh_period); ++ buf += sprintf(buf, "n_caches............. %d\n", param->n_caches); ++ buf += sprintf(buf, "n_reserved_blocks.... %d\n", ++ param->n_reserved_blocks); ++ buf += sprintf(buf, "always_check_erased.. %d\n", ++ param->always_check_erased); ++ buf += sprintf(buf, "\n"); ++ buf += sprintf(buf, "block count by state\n"); ++ buf += sprintf(buf, "0:%d 1:%d 2:%d 3:%d 4:%d\n", ++ bs[0], bs[1], bs[2], bs[3], bs[4]); ++ buf += sprintf(buf, "5:%d 6:%d 7:%d 8:%d 9:%d\n", ++ bs[5], bs[6], bs[7], bs[8], bs[9]); ++ ++ return buf; ++} ++ ++static char *yaffs_dump_dev_part1(char *buf, struct yaffs_dev *dev) ++{ ++ buf += sprintf(buf, "max file size....... %lld\n", ++ (long long) yaffs_max_file_size(dev)); ++ buf += sprintf(buf, "data_bytes_per_chunk. %d\n", ++ dev->data_bytes_per_chunk); ++ buf += sprintf(buf, "chunk_grp_bits....... %d\n", dev->chunk_grp_bits); ++ buf += sprintf(buf, "chunk_grp_size....... %d\n", dev->chunk_grp_size); ++ buf += sprintf(buf, "n_erased_blocks...... %d\n", dev->n_erased_blocks); ++ buf += sprintf(buf, "blocks_in_checkpt.... %d\n", ++ dev->blocks_in_checkpt); ++ buf += sprintf(buf, "\n"); ++ buf += sprintf(buf, "n_tnodes............. %d\n", dev->n_tnodes); ++ buf += sprintf(buf, "n_obj................ %d\n", dev->n_obj); ++ buf += sprintf(buf, "n_free_chunks........ %d\n", dev->n_free_chunks); ++ buf += sprintf(buf, "\n"); ++ buf += sprintf(buf, "n_page_writes........ %u\n", dev->n_page_writes); ++ buf += sprintf(buf, "n_page_reads......... %u\n", dev->n_page_reads); ++ buf += sprintf(buf, "n_erasures........... %u\n", dev->n_erasures); ++ buf += sprintf(buf, "n_gc_copies.......... %u\n", dev->n_gc_copies); ++ buf += sprintf(buf, "all_gcs.............. %u\n", dev->all_gcs); ++ buf += sprintf(buf, "passive_gc_count..... %u\n", ++ dev->passive_gc_count); ++ buf += sprintf(buf, "oldest_dirty_gc_count %u\n", ++ dev->oldest_dirty_gc_count); ++ buf += sprintf(buf, "n_gc_blocks.......... %u\n", dev->n_gc_blocks); ++ buf += sprintf(buf, "bg_gcs............... %u\n", dev->bg_gcs); ++ buf += sprintf(buf, "n_retried_writes..... %u\n", ++ dev->n_retried_writes); ++ buf += sprintf(buf, "n_retired_blocks..... %u\n", ++ dev->n_retired_blocks); ++ buf += sprintf(buf, "n_ecc_fixed.......... %u\n", dev->n_ecc_fixed); ++ buf += sprintf(buf, "n_ecc_unfixed........ %u\n", dev->n_ecc_unfixed); ++ buf += sprintf(buf, "n_tags_ecc_fixed..... %u\n", ++ dev->n_tags_ecc_fixed); ++ buf += sprintf(buf, "n_tags_ecc_unfixed... %u\n", ++ dev->n_tags_ecc_unfixed); ++ buf += sprintf(buf, "cache_hits........... %u\n", dev->cache_hits); ++ buf += sprintf(buf, "n_deleted_files...... %u\n", dev->n_deleted_files); ++ buf += sprintf(buf, "n_unlinked_files..... %u\n", ++ dev->n_unlinked_files); ++ buf += sprintf(buf, "refresh_count........ %u\n", dev->refresh_count); ++ buf += sprintf(buf, "n_bg_deletions....... %u\n", dev->n_bg_deletions); ++ buf += sprintf(buf, "tags_used............ %u\n", dev->tags_used); ++ buf += sprintf(buf, "summary_used......... %u\n", dev->summary_used); ++ ++ return buf; ++} ++ ++static int yaffs_proc_read(char *page, ++ char **start, ++ off_t offset, int count, int *eof, void *data) ++{ ++ struct list_head *item; ++ char *buf = page; ++ int step = offset; ++ int n = 0; ++ ++ /* Get proc_file_read() to step 'offset' by one on each sucessive call. ++ * We use 'offset' (*ppos) to indicate where we are in dev_list. ++ * This also assumes the user has posted a read buffer large ++ * enough to hold the complete output; but that's life in /proc. ++ */ ++ ++ *(int *)start = 1; ++ ++ /* Print header first */ ++ if (step == 0) ++ buf += ++ sprintf(buf, ++ "Multi-version YAFFS built:" __DATE__ " " __TIME__ ++ "\n"); ++ else if (step == 1) ++ buf += sprintf(buf, "\n"); ++ else { ++ step -= 2; ++ ++ mutex_lock(&yaffs_context_lock); ++ ++ /* Locate and print the Nth entry. Order N-squared but N is small. */ ++ list_for_each(item, &yaffs_context_list) { ++ struct yaffs_linux_context *dc = ++ list_entry(item, struct yaffs_linux_context, ++ context_list); ++ struct yaffs_dev *dev = dc->dev; ++ ++ if (n < (step & ~1)) { ++ n += 2; ++ continue; ++ } ++ if ((step & 1) == 0) { ++ buf += ++ sprintf(buf, "\nDevice %d \"%s\"\n", n, ++ dev->param.name); ++ buf = yaffs_dump_dev_part0(buf, dev); ++ } else { ++ buf = yaffs_dump_dev_part1(buf, dev); ++ } ++ ++ break; ++ } ++ mutex_unlock(&yaffs_context_lock); ++ } ++ ++ return buf - page < count ? buf - page : count; ++} ++ ++/** ++ * Set the verbosity of the warnings and error messages. ++ * ++ * Note that the names can only be a..z or _ with the current code. ++ */ ++ ++static struct { ++ char *mask_name; ++ unsigned mask_bitfield; ++} mask_flags[] = { ++ {"allocate", YAFFS_TRACE_ALLOCATE}, ++ {"always", YAFFS_TRACE_ALWAYS}, ++ {"background", YAFFS_TRACE_BACKGROUND}, ++ {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS}, ++ {"buffers", YAFFS_TRACE_BUFFERS}, ++ {"bug", YAFFS_TRACE_BUG}, ++ {"checkpt", YAFFS_TRACE_CHECKPOINT}, ++ {"deletion", YAFFS_TRACE_DELETION}, ++ {"erase", YAFFS_TRACE_ERASE}, ++ {"error", YAFFS_TRACE_ERROR}, ++ {"gc_detail", YAFFS_TRACE_GC_DETAIL}, ++ {"gc", YAFFS_TRACE_GC}, ++ {"lock", YAFFS_TRACE_LOCK}, ++ {"mtd", YAFFS_TRACE_MTD}, ++ {"nandaccess", YAFFS_TRACE_NANDACCESS}, ++ {"os", YAFFS_TRACE_OS}, ++ {"scan_debug", YAFFS_TRACE_SCAN_DEBUG}, ++ {"scan", YAFFS_TRACE_SCAN}, ++ {"mount", YAFFS_TRACE_MOUNT}, ++ {"tracing", YAFFS_TRACE_TRACING}, ++ {"sync", YAFFS_TRACE_SYNC}, ++ {"write", YAFFS_TRACE_WRITE}, ++ {"verify", YAFFS_TRACE_VERIFY}, ++ {"verify_nand", YAFFS_TRACE_VERIFY_NAND}, ++ {"verify_full", YAFFS_TRACE_VERIFY_FULL}, ++ {"verify_all", YAFFS_TRACE_VERIFY_ALL}, ++ {"all", 0xffffffff}, ++ {"none", 0}, ++ {NULL, 0}, ++}; ++ ++#define MAX_MASK_NAME_LENGTH 40 ++static int yaffs_proc_write_trace_options(struct file *file, const char *buf, ++ unsigned long count, void *data) ++{ ++ unsigned rg = 0, mask_bitfield; ++ char *end; ++ char *mask_name; ++ const char *x; ++ char substring[MAX_MASK_NAME_LENGTH + 1]; ++ int i; ++ int done = 0; ++ int add, len = 0; ++ int pos = 0; ++ ++ rg = yaffs_trace_mask; ++ ++ while (!done && (pos < count)) { ++ done = 1; ++ while ((pos < count) && isspace(buf[pos])) ++ pos++; ++ ++ switch (buf[pos]) { ++ case '+': ++ case '-': ++ case '=': ++ add = buf[pos]; ++ pos++; ++ break; ++ ++ default: ++ add = ' '; ++ break; ++ } ++ mask_name = NULL; ++ ++ mask_bitfield = simple_strtoul(buf + pos, &end, 0); ++ ++ if (end > buf + pos) { ++ mask_name = "numeral"; ++ len = end - (buf + pos); ++ pos += len; ++ done = 0; ++ } else { ++ for (x = buf + pos, i = 0; ++ (*x == '_' || (*x >= 'a' && *x <= 'z')) && ++ i < MAX_MASK_NAME_LENGTH; x++, i++, pos++) ++ substring[i] = *x; ++ substring[i] = '\0'; ++ ++ for (i = 0; mask_flags[i].mask_name != NULL; i++) { ++ if (strcmp(substring, mask_flags[i].mask_name) ++ == 0) { ++ mask_name = mask_flags[i].mask_name; ++ mask_bitfield = ++ mask_flags[i].mask_bitfield; ++ done = 0; ++ break; ++ } ++ } ++ } ++ ++ if (mask_name != NULL) { ++ done = 0; ++ switch (add) { ++ case '-': ++ rg &= ~mask_bitfield; ++ break; ++ case '+': ++ rg |= mask_bitfield; ++ break; ++ case '=': ++ rg = mask_bitfield; ++ break; ++ default: ++ rg |= mask_bitfield; ++ break; ++ } ++ } ++ } ++ ++ yaffs_trace_mask = rg | YAFFS_TRACE_ALWAYS; ++ ++ printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_trace_mask); ++ ++ if (rg & YAFFS_TRACE_ALWAYS) { ++ for (i = 0; mask_flags[i].mask_name != NULL; i++) { ++ char flag; ++ flag = ((rg & mask_flags[i].mask_bitfield) == ++ mask_flags[i].mask_bitfield) ? '+' : '-'; ++ printk(KERN_DEBUG "%c%s\n", flag, ++ mask_flags[i].mask_name); ++ } ++ } ++ ++ return count; ++} ++ ++/* Debug strings are of the form: ++ * .bnnn print info on block n ++ * .cobjn,chunkn print nand chunk id for objn:chunkn ++ */ ++ ++static int yaffs_proc_debug_write(struct file *file, const char *buf, ++ unsigned long count, void *data) ++{ ++ ++ char str[100]; ++ char *p0; ++ char *p1; ++ long p1_val; ++ long p0_val; ++ char cmd; ++ struct list_head *item; ++ ++ memset(str, 0, sizeof(str)); ++ memcpy(str, buf, min((size_t)count, sizeof(str) -1)); ++ ++ cmd = str[1]; ++ ++ p0 = str + 2; ++ ++ p1 = p0; ++ ++ while (*p1 && *p1 != ',') { ++ p1++; ++ } ++ *p1 = '\0'; ++ p1++; ++ ++ p0_val = simple_strtol(p0, NULL, 0); ++ p1_val = simple_strtol(p1, NULL, 0); ++ ++ ++ mutex_lock(&yaffs_context_lock); ++ ++ /* Locate and print the Nth entry. Order N-squared but N is small. */ ++ list_for_each(item, &yaffs_context_list) { ++ struct yaffs_linux_context *dc = ++ list_entry(item, struct yaffs_linux_context, ++ context_list); ++ struct yaffs_dev *dev = dc->dev; ++ ++ if (cmd == 'b') { ++ struct yaffs_block_info *bi; ++ ++ bi = yaffs_get_block_info(dev,p0_val); ++ ++ if(bi) { ++ printk("Block %d: state %d, retire %d, use %d, seq %d\n", ++ (int)p0_val, bi->block_state, ++ bi->needs_retiring, bi->pages_in_use, ++ bi->seq_number); ++ } ++ } else if (cmd == 'c') { ++ struct yaffs_obj *obj; ++ int nand_chunk; ++ ++ obj = yaffs_find_by_number(dev, p0_val); ++ if (!obj) ++ printk("No obj %d\n", (int)p0_val); ++ else { ++ if(p1_val == 0) ++ nand_chunk = obj->hdr_chunk; ++ else ++ nand_chunk = ++ yaffs_find_chunk_in_file(obj, ++ p1_val, NULL); ++ printk("Nand chunk for %d:%d is %d\n", ++ (int)p0_val, (int)p1_val, nand_chunk); ++ } ++ } ++ } ++ ++ mutex_unlock(&yaffs_context_lock); ++ ++ return count; ++} ++ ++static int yaffs_proc_write(struct file *file, const char *buf, ++ unsigned long count, void *data) ++{ ++ if (buf[0] == '.') ++ return yaffs_proc_debug_write(file, buf, count, data); ++ return yaffs_proc_write_trace_options(file, buf, count, data); ++} ++ ++/* Stuff to handle installation of file systems */ ++struct file_system_to_install { ++ struct file_system_type *fst; ++ int installed; ++}; ++ ++static struct file_system_to_install fs_to_install[] = { ++ {&yaffs_fs_type, 0}, ++ {&yaffs2_fs_type, 0}, ++ {NULL, 0} ++}; ++ ++static int __init init_yaffs_fs(void) ++{ ++ int error = 0; ++ struct file_system_to_install *fsinst; ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs built " __DATE__ " " __TIME__ " Installing."); ++ ++ mutex_init(&yaffs_context_lock); ++ ++ /* Install the proc_fs entries */ ++ my_proc_entry = create_proc_entry("yaffs", ++ S_IRUGO | S_IFREG, YPROC_ROOT); ++ ++ if (my_proc_entry) { ++ my_proc_entry->write_proc = yaffs_proc_write; ++ my_proc_entry->read_proc = yaffs_proc_read; ++ my_proc_entry->data = NULL; ++ } else { ++ return -ENOMEM; ++ } ++ ++ /* Now add the file system entries */ ++ ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst && !error) { ++ error = register_filesystem(fsinst->fst); ++ if (!error) ++ fsinst->installed = 1; ++ fsinst++; ++ } ++ ++ /* Any errors? uninstall */ ++ if (error) { ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst) { ++ if (fsinst->installed) { ++ unregister_filesystem(fsinst->fst); ++ fsinst->installed = 0; ++ } ++ fsinst++; ++ } ++ } ++ ++ return error; ++} ++ ++static void __exit exit_yaffs_fs(void) ++{ ++ ++ struct file_system_to_install *fsinst; ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "yaffs built " __DATE__ " " __TIME__ " removing."); ++ ++ remove_proc_entry("yaffs", YPROC_ROOT); ++ ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst) { ++ if (fsinst->installed) { ++ unregister_filesystem(fsinst->fst); ++ fsinst->installed = 0; ++ } ++ fsinst++; ++ } ++} ++ ++module_init(init_yaffs_fs) ++ module_exit(exit_yaffs_fs) ++ ++ MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system"); ++MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2011"); ++MODULE_LICENSE("GPL"); +diff --git a/fs/yaffs2/yaffs_yaffs1.c b/fs/yaffs2/yaffs_yaffs1.c +new file mode 100644 +index 00000000..d277e20e +--- /dev/null ++++ b/fs/yaffs2/yaffs_yaffs1.c +@@ -0,0 +1,422 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_yaffs1.h" ++#include "yportenv.h" ++#include "yaffs_trace.h" ++#include "yaffs_bitmap.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_nand.h" ++#include "yaffs_attribs.h" ++ ++int yaffs1_scan(struct yaffs_dev *dev) ++{ ++ struct yaffs_ext_tags tags; ++ int blk; ++ int result; ++ int chunk; ++ int c; ++ int deleted; ++ enum yaffs_block_state state; ++ LIST_HEAD(hard_list); ++ struct yaffs_block_info *bi; ++ u32 seq_number; ++ struct yaffs_obj_hdr *oh; ++ struct yaffs_obj *in; ++ struct yaffs_obj *parent; ++ int alloc_failed = 0; ++ struct yaffs_shadow_fixer *shadow_fixers = NULL; ++ u8 *chunk_data; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "yaffs1_scan starts intstartblk %d intendblk %d...", ++ dev->internal_start_block, dev->internal_end_block); ++ ++ chunk_data = yaffs_get_temp_buffer(dev); ++ ++ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; ++ ++ /* Scan all the blocks to determine their state */ ++ bi = dev->block_info; ++ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; ++ blk++) { ++ yaffs_clear_chunk_bits(dev, blk); ++ bi->pages_in_use = 0; ++ bi->soft_del_pages = 0; ++ ++ yaffs_query_init_block_state(dev, blk, &state, &seq_number); ++ ++ bi->block_state = state; ++ bi->seq_number = seq_number; ++ ++ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) ++ bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, ++ "Block scanning block %d state %d seq %d", ++ blk, state, seq_number); ++ ++ if (state == YAFFS_BLOCK_STATE_DEAD) { ++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, ++ "block %d is bad", blk); ++ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { ++ yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty "); ++ dev->n_erased_blocks++; ++ dev->n_free_chunks += dev->param.chunks_per_block; ++ } ++ bi++; ++ } ++ ++ /* For each block.... */ ++ for (blk = dev->internal_start_block; ++ !alloc_failed && blk <= dev->internal_end_block; blk++) { ++ ++ cond_resched(); ++ ++ bi = yaffs_get_block_info(dev, blk); ++ state = bi->block_state; ++ ++ deleted = 0; ++ ++ /* For each chunk in each block that needs scanning.... */ ++ for (c = 0; ++ !alloc_failed && c < dev->param.chunks_per_block && ++ state == YAFFS_BLOCK_STATE_NEEDS_SCAN; c++) { ++ /* Read the tags and decide what to do */ ++ chunk = blk * dev->param.chunks_per_block + c; ++ ++ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, ++ &tags); ++ ++ /* Let's have a good look at this chunk... */ ++ ++ if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED || ++ tags.is_deleted) { ++ /* YAFFS1 only... ++ * A deleted chunk ++ */ ++ deleted++; ++ dev->n_free_chunks++; ++ } else if (!tags.chunk_used) { ++ /* An unassigned chunk in the block ++ * This means that either the block is empty or ++ * this is the one being allocated from ++ */ ++ ++ if (c == 0) { ++ /* We're looking at the first chunk in ++ *the block so the block is unused */ ++ state = YAFFS_BLOCK_STATE_EMPTY; ++ dev->n_erased_blocks++; ++ } else { ++ /* this is the block being allocated */ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ " Allocating from %d %d", ++ blk, c); ++ state = YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->alloc_block = blk; ++ dev->alloc_page = c; ++ dev->alloc_block_finder = blk; ++ ++ } ++ ++ dev->n_free_chunks += ++ (dev->param.chunks_per_block - c); ++ } else if (tags.chunk_id > 0) { ++ /* chunk_id > 0 so it is a data chunk... */ ++ unsigned int endpos; ++ ++ yaffs_set_chunk_bit(dev, blk, c); ++ bi->pages_in_use++; ++ ++ in = yaffs_find_or_create_by_number(dev, ++ tags.obj_id, ++ YAFFS_OBJECT_TYPE_FILE); ++ /* PutChunkIntoFile checks for a clash ++ * (two data chunks with the same chunk_id). ++ */ ++ ++ if (!in) ++ alloc_failed = 1; ++ ++ if (in) { ++ if (!yaffs_put_chunk_in_file ++ (in, tags.chunk_id, chunk, 1)) ++ alloc_failed = 1; ++ } ++ ++ endpos = ++ (tags.chunk_id - 1) * ++ dev->data_bytes_per_chunk + ++ tags.n_bytes; ++ if (in && ++ in->variant_type == ++ YAFFS_OBJECT_TYPE_FILE && ++ in->variant.file_variant.scanned_size < ++ endpos) { ++ in->variant.file_variant.scanned_size = ++ endpos; ++ if (!dev->param.use_header_file_size) { ++ in->variant. ++ file_variant.file_size = ++ in->variant. ++ file_variant.scanned_size; ++ } ++ ++ } ++ } else { ++ /* chunk_id == 0, so it is an ObjectHeader. ++ * Make the object ++ */ ++ yaffs_set_chunk_bit(dev, blk, c); ++ bi->pages_in_use++; ++ ++ result = yaffs_rd_chunk_tags_nand(dev, chunk, ++ chunk_data, ++ NULL); ++ ++ oh = (struct yaffs_obj_hdr *)chunk_data; ++ ++ in = yaffs_find_by_number(dev, tags.obj_id); ++ if (in && in->variant_type != oh->type) { ++ /* This should not happen, but somehow ++ * Wev'e ended up with an obj_id that ++ * has been reused but not yet deleted, ++ * and worse still it has changed type. ++ * Delete the old object. ++ */ ++ ++ yaffs_del_obj(in); ++ in = NULL; ++ } ++ ++ in = yaffs_find_or_create_by_number(dev, ++ tags.obj_id, ++ oh->type); ++ ++ if (!in) ++ alloc_failed = 1; ++ ++ if (in && oh->shadows_obj > 0) { ++ ++ struct yaffs_shadow_fixer *fixer; ++ fixer = ++ kmalloc(sizeof ++ (struct yaffs_shadow_fixer), ++ GFP_NOFS); ++ if (fixer) { ++ fixer->next = shadow_fixers; ++ shadow_fixers = fixer; ++ fixer->obj_id = tags.obj_id; ++ fixer->shadowed_id = ++ oh->shadows_obj; ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ " Shadow fixer: %d shadows %d", ++ fixer->obj_id, ++ fixer->shadowed_id); ++ ++ } ++ ++ } ++ ++ if (in && in->valid) { ++ /* We have already filled this one. ++ * We have a duplicate and need to ++ * resolve it. */ ++ ++ unsigned existing_serial = in->serial; ++ unsigned new_serial = ++ tags.serial_number; ++ ++ if (((existing_serial + 1) & 3) == ++ new_serial) { ++ /* Use new one - destroy the ++ * exisiting one */ ++ yaffs_chunk_del(dev, ++ in->hdr_chunk, ++ 1, __LINE__); ++ in->valid = 0; ++ } else { ++ /* Use existing - destroy ++ * this one. */ ++ yaffs_chunk_del(dev, chunk, 1, ++ __LINE__); ++ } ++ } ++ ++ if (in && !in->valid && ++ (tags.obj_id == YAFFS_OBJECTID_ROOT || ++ tags.obj_id == ++ YAFFS_OBJECTID_LOSTNFOUND)) { ++ /* We only load some info, don't fiddle ++ * with directory structure */ ++ in->valid = 1; ++ in->variant_type = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++ yaffs_load_attribs(in, oh); ++ in->hdr_chunk = chunk; ++ in->serial = tags.serial_number; ++ ++ } else if (in && !in->valid) { ++ /* we need to load this info */ ++ ++ in->valid = 1; ++ in->variant_type = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++ yaffs_load_attribs(in, oh); ++ in->hdr_chunk = chunk; ++ in->serial = tags.serial_number; ++ ++ yaffs_set_obj_name_from_oh(in, oh); ++ in->dirty = 0; ++ ++ /* directory stuff... ++ * hook up to parent ++ */ ++ ++ parent = ++ yaffs_find_or_create_by_number ++ (dev, oh->parent_obj_id, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ if (!parent) ++ alloc_failed = 1; ++ if (parent && parent->variant_type == ++ YAFFS_OBJECT_TYPE_UNKNOWN) { ++ /* Set up as a directory */ ++ parent->variant_type = ++ YAFFS_OBJECT_TYPE_DIRECTORY; ++ INIT_LIST_HEAD(&parent-> ++ variant.dir_variant. ++ children); ++ } else if (!parent || ++ parent->variant_type != ++ YAFFS_OBJECT_TYPE_DIRECTORY) { ++ /* Hoosterman, a problem.... ++ * We're trying to use a ++ * non-directory as a directory ++ */ ++ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." ++ ); ++ parent = dev->lost_n_found; ++ } ++ ++ yaffs_add_obj_to_dir(parent, in); ++ ++ switch (in->variant_type) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Todo got a problem */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ if (dev->param. ++ use_header_file_size) ++ in->variant. ++ file_variant.file_size ++ = yaffs_oh_to_size(oh); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ in->variant. ++ hardlink_variant.equiv_id = ++ oh->equiv_id; ++ list_add(&in->hard_links, ++ &hard_list); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ in->variant.symlink_variant. ++ alias = ++ yaffs_clone_str(oh->alias); ++ if (!in->variant. ++ symlink_variant.alias) ++ alloc_failed = 1; ++ break; ++ } ++ } ++ } ++ } ++ ++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCAN) { ++ /* If we got this far while scanning, ++ * then the block is fully allocated. */ ++ state = YAFFS_BLOCK_STATE_FULL; ++ } ++ ++ if (state == YAFFS_BLOCK_STATE_ALLOCATING) { ++ /* If the block was partially allocated then ++ * treat it as fully allocated. */ ++ state = YAFFS_BLOCK_STATE_FULL; ++ dev->alloc_block = -1; ++ } ++ ++ bi->block_state = state; ++ ++ /* Now let's see if it was dirty */ ++ if (bi->pages_in_use == 0 && ++ !bi->has_shrink_hdr && ++ bi->block_state == YAFFS_BLOCK_STATE_FULL) ++ yaffs_block_became_dirty(dev, blk); ++ } ++ ++ /* Ok, we've done all the scanning. ++ * Fix up the hard link chains. ++ * We should now have scanned all the objects, now it's time to add ++ * these hardlinks. ++ */ ++ ++ yaffs_link_fixup(dev, &hard_list); ++ ++ /* ++ * Fix up any shadowed objects. ++ * There should not be more than one of these. ++ */ ++ { ++ struct yaffs_shadow_fixer *fixer; ++ struct yaffs_obj *obj; ++ ++ while (shadow_fixers) { ++ fixer = shadow_fixers; ++ shadow_fixers = fixer->next; ++ /* Complete the rename transaction by deleting the ++ * shadowed object then setting the object header ++ to unshadowed. ++ */ ++ obj = yaffs_find_by_number(dev, fixer->shadowed_id); ++ if (obj) ++ yaffs_del_obj(obj); ++ ++ obj = yaffs_find_by_number(dev, fixer->obj_id); ++ ++ if (obj) ++ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); ++ ++ kfree(fixer); ++ } ++ } ++ ++ yaffs_release_temp_buffer(dev, chunk_data); ++ ++ if (alloc_failed) ++ return YAFFS_FAIL; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN, "yaffs1_scan ends"); ++ ++ return YAFFS_OK; ++} +diff --git a/fs/yaffs2/yaffs_yaffs1.h b/fs/yaffs2/yaffs_yaffs1.h +new file mode 100644 +index 00000000..97e2fdd0 +--- /dev/null ++++ b/fs/yaffs2/yaffs_yaffs1.h +@@ -0,0 +1,22 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_YAFFS1_H__ ++#define __YAFFS_YAFFS1_H__ ++ ++#include "yaffs_guts.h" ++int yaffs1_scan(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yaffs_yaffs2.c b/fs/yaffs2/yaffs_yaffs2.c +new file mode 100644 +index 00000000..8c31a661 +--- /dev/null ++++ b/fs/yaffs2/yaffs_yaffs2.c +@@ -0,0 +1,1534 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_guts.h" ++#include "yaffs_trace.h" ++#include "yaffs_yaffs2.h" ++#include "yaffs_checkptrw.h" ++#include "yaffs_bitmap.h" ++#include "yaffs_nand.h" ++#include "yaffs_getblockinfo.h" ++#include "yaffs_verify.h" ++#include "yaffs_attribs.h" ++#include "yaffs_summary.h" ++ ++/* ++ * Checkpoints are really no benefit on very small partitions. ++ * ++ * To save space on small partitions don't bother with checkpoints unless ++ * the partition is at least this big. ++ */ ++#define YAFFS_CHECKPOINT_MIN_BLOCKS 60 ++#define YAFFS_SMALL_HOLE_THRESHOLD 4 ++ ++/* ++ * Oldest Dirty Sequence Number handling. ++ */ ++ ++/* yaffs_calc_oldest_dirty_seq() ++ * yaffs2_find_oldest_dirty_seq() ++ * Calculate the oldest dirty sequence number if we don't know it. ++ */ ++void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev) ++{ ++ int i; ++ unsigned seq; ++ unsigned block_no = 0; ++ struct yaffs_block_info *b; ++ ++ if (!dev->param.is_yaffs2) ++ return; ++ ++ /* Find the oldest dirty sequence number. */ ++ seq = dev->seq_number + 1; ++ b = dev->block_info; ++ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { ++ if (b->block_state == YAFFS_BLOCK_STATE_FULL && ++ (b->pages_in_use - b->soft_del_pages) < ++ dev->param.chunks_per_block && ++ b->seq_number < seq) { ++ seq = b->seq_number; ++ block_no = i; ++ } ++ b++; ++ } ++ ++ if (block_no) { ++ dev->oldest_dirty_seq = seq; ++ dev->oldest_dirty_block = block_no; ++ } ++} ++ ++void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev) ++{ ++ if (!dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->oldest_dirty_seq) ++ yaffs_calc_oldest_dirty_seq(dev); ++} ++ ++/* ++ * yaffs_clear_oldest_dirty_seq() ++ * Called when a block is erased or marked bad. (ie. when its seq_number ++ * becomes invalid). If the value matches the oldest then we clear ++ * dev->oldest_dirty_seq to force its recomputation. ++ */ ++void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi) ++{ ++ ++ if (!dev->param.is_yaffs2) ++ return; ++ ++ if (!bi || bi->seq_number == dev->oldest_dirty_seq) { ++ dev->oldest_dirty_seq = 0; ++ dev->oldest_dirty_block = 0; ++ } ++} ++ ++/* ++ * yaffs2_update_oldest_dirty_seq() ++ * Update the oldest dirty sequence number whenever we dirty a block. ++ * Only do this if the oldest_dirty_seq is actually being tracked. ++ */ ++void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, ++ struct yaffs_block_info *bi) ++{ ++ if (!dev->param.is_yaffs2) ++ return; ++ ++ if (dev->oldest_dirty_seq) { ++ if (dev->oldest_dirty_seq > bi->seq_number) { ++ dev->oldest_dirty_seq = bi->seq_number; ++ dev->oldest_dirty_block = block_no; ++ } ++ } ++} ++ ++int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi) ++{ ++ ++ if (!dev->param.is_yaffs2) ++ return 1; /* disqualification only applies to yaffs2. */ ++ ++ if (!bi->has_shrink_hdr) ++ return 1; /* can gc */ ++ ++ yaffs2_find_oldest_dirty_seq(dev); ++ ++ /* Can't do gc of this block if there are any blocks older than this ++ * one that have discarded pages. ++ */ ++ return (bi->seq_number <= dev->oldest_dirty_seq); ++} ++ ++/* ++ * yaffs2_find_refresh_block() ++ * periodically finds the oldest full block by sequence number for refreshing. ++ * Only for yaffs2. ++ */ ++u32 yaffs2_find_refresh_block(struct yaffs_dev *dev) ++{ ++ u32 b; ++ u32 oldest = 0; ++ u32 oldest_seq = 0; ++ struct yaffs_block_info *bi; ++ ++ if (!dev->param.is_yaffs2) ++ return oldest; ++ ++ /* ++ * If refresh period < 10 then refreshing is disabled. ++ */ ++ if (dev->param.refresh_period < 10) ++ return oldest; ++ ++ /* ++ * Fix broken values. ++ */ ++ if (dev->refresh_skip > dev->param.refresh_period) ++ dev->refresh_skip = dev->param.refresh_period; ++ ++ if (dev->refresh_skip > 0) ++ return oldest; ++ ++ /* ++ * Refresh skip is now zero. ++ * We'll do a refresh this time around.... ++ * Update the refresh skip and find the oldest block. ++ */ ++ dev->refresh_skip = dev->param.refresh_period; ++ dev->refresh_count++; ++ bi = dev->block_info; ++ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) { ++ ++ if (oldest < 1 || bi->seq_number < oldest_seq) { ++ oldest = b; ++ oldest_seq = bi->seq_number; ++ } ++ } ++ bi++; ++ } ++ ++ if (oldest > 0) { ++ yaffs_trace(YAFFS_TRACE_GC, ++ "GC refresh count %d selected block %d with seq_number %d", ++ dev->refresh_count, oldest, oldest_seq); ++ } ++ ++ return oldest; ++} ++ ++int yaffs2_checkpt_required(struct yaffs_dev *dev) ++{ ++ int nblocks; ++ ++ if (!dev->param.is_yaffs2) ++ return 0; ++ ++ nblocks = dev->internal_end_block - dev->internal_start_block + 1; ++ ++ return !dev->param.skip_checkpt_wr && ++ !dev->read_only && (nblocks >= YAFFS_CHECKPOINT_MIN_BLOCKS); ++} ++ ++int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev) ++{ ++ int retval; ++ int n_bytes = 0; ++ int n_blocks; ++ int dev_blocks; ++ ++ if (!dev->param.is_yaffs2) ++ return 0; ++ ++ if (!dev->checkpoint_blocks_required && yaffs2_checkpt_required(dev)) { ++ /* Not a valid value so recalculate */ ++ dev_blocks = dev->param.end_block - dev->param.start_block + 1; ++ n_bytes += sizeof(struct yaffs_checkpt_validity); ++ n_bytes += sizeof(struct yaffs_checkpt_dev); ++ n_bytes += dev_blocks * sizeof(struct yaffs_block_info); ++ n_bytes += dev_blocks * dev->chunk_bit_stride; ++ n_bytes += ++ (sizeof(struct yaffs_checkpt_obj) + sizeof(u32)) * ++ dev->n_obj; ++ n_bytes += (dev->tnode_size + sizeof(u32)) * dev->n_tnodes; ++ n_bytes += sizeof(struct yaffs_checkpt_validity); ++ n_bytes += sizeof(u32); /* checksum */ ++ ++ /* Round up and add 2 blocks to allow for some bad blocks, ++ * so add 3 */ ++ ++ n_blocks = ++ (n_bytes / ++ (dev->data_bytes_per_chunk * ++ dev->param.chunks_per_block)) + 3; ++ ++ dev->checkpoint_blocks_required = n_blocks; ++ } ++ ++ retval = dev->checkpoint_blocks_required - dev->blocks_in_checkpt; ++ if (retval < 0) ++ retval = 0; ++ return retval; ++} ++ ++/*--------------------- Checkpointing --------------------*/ ++ ++static int yaffs2_wr_checkpt_validity_marker(struct yaffs_dev *dev, int head) ++{ ++ struct yaffs_checkpt_validity cp; ++ ++ memset(&cp, 0, sizeof(cp)); ++ ++ cp.struct_type = sizeof(cp); ++ cp.magic = YAFFS_MAGIC; ++ cp.version = YAFFS_CHECKPOINT_VERSION; ++ cp.head = (head) ? 1 : 0; ++ ++ return (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)) ? 1 : 0; ++} ++ ++static int yaffs2_rd_checkpt_validity_marker(struct yaffs_dev *dev, int head) ++{ ++ struct yaffs_checkpt_validity cp; ++ int ok; ++ ++ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); ++ ++ if (ok) ++ ok = (cp.struct_type == sizeof(cp)) && ++ (cp.magic == YAFFS_MAGIC) && ++ (cp.version == YAFFS_CHECKPOINT_VERSION) && ++ (cp.head == ((head) ? 1 : 0)); ++ return ok ? 1 : 0; ++} ++ ++static void yaffs2_dev_to_checkpt_dev(struct yaffs_checkpt_dev *cp, ++ struct yaffs_dev *dev) ++{ ++ cp->n_erased_blocks = dev->n_erased_blocks; ++ cp->alloc_block = dev->alloc_block; ++ cp->alloc_page = dev->alloc_page; ++ cp->n_free_chunks = dev->n_free_chunks; ++ ++ cp->n_deleted_files = dev->n_deleted_files; ++ cp->n_unlinked_files = dev->n_unlinked_files; ++ cp->n_bg_deletions = dev->n_bg_deletions; ++ cp->seq_number = dev->seq_number; ++ ++} ++ ++static void yaffs_checkpt_dev_to_dev(struct yaffs_dev *dev, ++ struct yaffs_checkpt_dev *cp) ++{ ++ dev->n_erased_blocks = cp->n_erased_blocks; ++ dev->alloc_block = cp->alloc_block; ++ dev->alloc_page = cp->alloc_page; ++ dev->n_free_chunks = cp->n_free_chunks; ++ ++ dev->n_deleted_files = cp->n_deleted_files; ++ dev->n_unlinked_files = cp->n_unlinked_files; ++ dev->n_bg_deletions = cp->n_bg_deletions; ++ dev->seq_number = cp->seq_number; ++} ++ ++static int yaffs2_wr_checkpt_dev(struct yaffs_dev *dev) ++{ ++ struct yaffs_checkpt_dev cp; ++ u32 n_bytes; ++ u32 n_blocks = dev->internal_end_block - dev->internal_start_block + 1; ++ int ok; ++ ++ /* Write device runtime values */ ++ yaffs2_dev_to_checkpt_dev(&cp, dev); ++ cp.struct_type = sizeof(cp); ++ ++ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); ++ if (!ok) ++ return 0; ++ ++ /* Write block info */ ++ n_bytes = n_blocks * sizeof(struct yaffs_block_info); ++ ok = (yaffs2_checkpt_wr(dev, dev->block_info, n_bytes) == n_bytes); ++ if (!ok) ++ return 0; ++ ++ /* Write chunk bits */ ++ n_bytes = n_blocks * dev->chunk_bit_stride; ++ ok = (yaffs2_checkpt_wr(dev, dev->chunk_bits, n_bytes) == n_bytes); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs2_rd_checkpt_dev(struct yaffs_dev *dev) ++{ ++ struct yaffs_checkpt_dev cp; ++ u32 n_bytes; ++ u32 n_blocks = ++ (dev->internal_end_block - dev->internal_start_block + 1); ++ int ok; ++ ++ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); ++ if (!ok) ++ return 0; ++ ++ if (cp.struct_type != sizeof(cp)) ++ return 0; ++ ++ yaffs_checkpt_dev_to_dev(dev, &cp); ++ ++ n_bytes = n_blocks * sizeof(struct yaffs_block_info); ++ ++ ok = (yaffs2_checkpt_rd(dev, dev->block_info, n_bytes) == n_bytes); ++ ++ if (!ok) ++ return 0; ++ ++ n_bytes = n_blocks * dev->chunk_bit_stride; ++ ++ ok = (yaffs2_checkpt_rd(dev, dev->chunk_bits, n_bytes) == n_bytes); ++ ++ return ok ? 1 : 0; ++} ++ ++static void yaffs2_obj_checkpt_obj(struct yaffs_checkpt_obj *cp, ++ struct yaffs_obj *obj) ++{ ++ cp->obj_id = obj->obj_id; ++ cp->parent_id = (obj->parent) ? obj->parent->obj_id : 0; ++ cp->hdr_chunk = obj->hdr_chunk; ++ cp->variant_type = obj->variant_type; ++ cp->deleted = obj->deleted; ++ cp->soft_del = obj->soft_del; ++ cp->unlinked = obj->unlinked; ++ cp->fake = obj->fake; ++ cp->rename_allowed = obj->rename_allowed; ++ cp->unlink_allowed = obj->unlink_allowed; ++ cp->serial = obj->serial; ++ cp->n_data_chunks = obj->n_data_chunks; ++ ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) ++ cp->size_or_equiv_obj = obj->variant.file_variant.file_size; ++ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) ++ cp->size_or_equiv_obj = obj->variant.hardlink_variant.equiv_id; ++} ++ ++static int yaffs2_checkpt_obj_to_obj(struct yaffs_obj *obj, ++ struct yaffs_checkpt_obj *cp) ++{ ++ struct yaffs_obj *parent; ++ ++ if (obj->variant_type != cp->variant_type) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "Checkpoint read object %d type %d chunk %d does not match existing object type %d", ++ cp->obj_id, cp->variant_type, cp->hdr_chunk, ++ obj->variant_type); ++ return 0; ++ } ++ ++ obj->obj_id = cp->obj_id; ++ ++ if (cp->parent_id) ++ parent = yaffs_find_or_create_by_number(obj->my_dev, ++ cp->parent_id, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ else ++ parent = NULL; ++ ++ if (parent) { ++ if (parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "Checkpoint read object %d parent %d type %d chunk %d Parent type, %d, not directory", ++ cp->obj_id, cp->parent_id, ++ cp->variant_type, cp->hdr_chunk, ++ parent->variant_type); ++ return 0; ++ } ++ yaffs_add_obj_to_dir(parent, obj); ++ } ++ ++ obj->hdr_chunk = cp->hdr_chunk; ++ obj->variant_type = cp->variant_type; ++ obj->deleted = cp->deleted; ++ obj->soft_del = cp->soft_del; ++ obj->unlinked = cp->unlinked; ++ obj->fake = cp->fake; ++ obj->rename_allowed = cp->rename_allowed; ++ obj->unlink_allowed = cp->unlink_allowed; ++ obj->serial = cp->serial; ++ obj->n_data_chunks = cp->n_data_chunks; ++ ++ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) ++ obj->variant.file_variant.file_size = cp->size_or_equiv_obj; ++ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) ++ obj->variant.hardlink_variant.equiv_id = cp->size_or_equiv_obj; ++ ++ if (obj->hdr_chunk > 0) ++ obj->lazy_loaded = 1; ++ return 1; ++} ++ ++static int yaffs2_checkpt_tnode_worker(struct yaffs_obj *in, ++ struct yaffs_tnode *tn, u32 level, ++ int chunk_offset) ++{ ++ int i; ++ struct yaffs_dev *dev = in->my_dev; ++ int ok = 1; ++ u32 base_offset; ++ ++ if (!tn) ++ return 1; ++ ++ if (level > 0) { ++ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) { ++ if (!tn->internal[i]) ++ continue; ++ ok = yaffs2_checkpt_tnode_worker(in, ++ tn->internal[i], ++ level - 1, ++ (chunk_offset << ++ YAFFS_TNODES_INTERNAL_BITS) + i); ++ } ++ return ok; ++ } ++ ++ /* Level 0 tnode */ ++ base_offset = chunk_offset << YAFFS_TNODES_LEVEL0_BITS; ++ ok = (yaffs2_checkpt_wr(dev, &base_offset, sizeof(base_offset)) == ++ sizeof(base_offset)); ++ if (ok) ++ ok = (yaffs2_checkpt_wr(dev, tn, dev->tnode_size) == ++ dev->tnode_size); ++ ++ return ok; ++} ++ ++static int yaffs2_wr_checkpt_tnodes(struct yaffs_obj *obj) ++{ ++ u32 end_marker = ~0; ++ int ok = 1; ++ ++ if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) ++ return ok; ++ ++ ok = yaffs2_checkpt_tnode_worker(obj, ++ obj->variant.file_variant.top, ++ obj->variant.file_variant. ++ top_level, 0); ++ if (ok) ++ ok = (yaffs2_checkpt_wr(obj->my_dev, &end_marker, ++ sizeof(end_marker)) == sizeof(end_marker)); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs2_rd_checkpt_tnodes(struct yaffs_obj *obj) ++{ ++ u32 base_chunk; ++ int ok = 1; ++ struct yaffs_dev *dev = obj->my_dev; ++ struct yaffs_file_var *file_stuct_ptr = &obj->variant.file_variant; ++ struct yaffs_tnode *tn; ++ int nread = 0; ++ ++ ok = (yaffs2_checkpt_rd(dev, &base_chunk, sizeof(base_chunk)) == ++ sizeof(base_chunk)); ++ ++ while (ok && (~base_chunk)) { ++ nread++; ++ /* Read level 0 tnode */ ++ ++ tn = yaffs_get_tnode(dev); ++ if (tn) ++ ok = (yaffs2_checkpt_rd(dev, tn, dev->tnode_size) == ++ dev->tnode_size); ++ else ++ ok = 0; ++ ++ if (tn && ok) ++ ok = yaffs_add_find_tnode_0(dev, ++ file_stuct_ptr, ++ base_chunk, tn) ? 1 : 0; ++ ++ if (ok) ++ ok = (yaffs2_checkpt_rd ++ (dev, &base_chunk, ++ sizeof(base_chunk)) == sizeof(base_chunk)); ++ } ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "Checkpoint read tnodes %d records, last %d. ok %d", ++ nread, base_chunk, ok); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs2_wr_checkpt_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_checkpt_obj cp; ++ int i; ++ int ok = 1; ++ struct list_head *lh; ++ ++ /* Iterate through the objects in each hash entry, ++ * dumping them to the checkpointing stream. ++ */ ++ ++ for (i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++) { ++ list_for_each(lh, &dev->obj_bucket[i].list) { ++ obj = list_entry(lh, struct yaffs_obj, hash_link); ++ if (!obj->defered_free) { ++ yaffs2_obj_checkpt_obj(&cp, obj); ++ cp.struct_type = sizeof(cp); ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "Checkpoint write object %d parent %d type %d chunk %d obj addr %p", ++ cp.obj_id, cp.parent_id, ++ cp.variant_type, cp.hdr_chunk, obj); ++ ++ ok = (yaffs2_checkpt_wr(dev, &cp, ++ sizeof(cp)) == sizeof(cp)); ++ ++ if (ok && ++ obj->variant_type == ++ YAFFS_OBJECT_TYPE_FILE) ++ ok = yaffs2_wr_checkpt_tnodes(obj); ++ } ++ } ++ } ++ ++ /* Dump end of list */ ++ memset(&cp, 0xff, sizeof(struct yaffs_checkpt_obj)); ++ cp.struct_type = sizeof(cp); ++ ++ if (ok) ++ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs2_rd_checkpt_objs(struct yaffs_dev *dev) ++{ ++ struct yaffs_obj *obj; ++ struct yaffs_checkpt_obj cp; ++ int ok = 1; ++ int done = 0; ++ LIST_HEAD(hard_list); ++ ++ ++ while (ok && !done) { ++ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); ++ if (cp.struct_type != sizeof(cp)) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "struct size %d instead of %d ok %d", ++ cp.struct_type, (int)sizeof(cp), ok); ++ ok = 0; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "Checkpoint read object %d parent %d type %d chunk %d ", ++ cp.obj_id, cp.parent_id, cp.variant_type, ++ cp.hdr_chunk); ++ ++ if (ok && cp.obj_id == ~0) { ++ done = 1; ++ } else if (ok) { ++ obj = ++ yaffs_find_or_create_by_number(dev, cp.obj_id, ++ cp.variant_type); ++ if (obj) { ++ ok = yaffs2_checkpt_obj_to_obj(obj, &cp); ++ if (!ok) ++ break; ++ if (obj->variant_type == ++ YAFFS_OBJECT_TYPE_FILE) { ++ ok = yaffs2_rd_checkpt_tnodes(obj); ++ } else if (obj->variant_type == ++ YAFFS_OBJECT_TYPE_HARDLINK) { ++ list_add(&obj->hard_links, &hard_list); ++ } ++ } else { ++ ok = 0; ++ } ++ } ++ } ++ ++ if (ok) ++ yaffs_link_fixup(dev, &hard_list); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs2_wr_checkpt_sum(struct yaffs_dev *dev) ++{ ++ u32 checkpt_sum; ++ int ok; ++ ++ yaffs2_get_checkpt_sum(dev, &checkpt_sum); ++ ++ ok = (yaffs2_checkpt_wr(dev, &checkpt_sum, sizeof(checkpt_sum)) == ++ sizeof(checkpt_sum)); ++ ++ if (!ok) ++ return 0; ++ ++ return 1; ++} ++ ++static int yaffs2_rd_checkpt_sum(struct yaffs_dev *dev) ++{ ++ u32 checkpt_sum0; ++ u32 checkpt_sum1; ++ int ok; ++ ++ yaffs2_get_checkpt_sum(dev, &checkpt_sum0); ++ ++ ok = (yaffs2_checkpt_rd(dev, &checkpt_sum1, sizeof(checkpt_sum1)) == ++ sizeof(checkpt_sum1)); ++ ++ if (!ok) ++ return 0; ++ ++ if (checkpt_sum0 != checkpt_sum1) ++ return 0; ++ ++ return 1; ++} ++ ++static int yaffs2_wr_checkpt_data(struct yaffs_dev *dev) ++{ ++ int ok = 1; ++ ++ if (!yaffs2_checkpt_required(dev)) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "skipping checkpoint write"); ++ ok = 0; ++ } ++ ++ if (ok) ++ ok = yaffs2_checkpt_open(dev, 1); ++ ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "write checkpoint validity"); ++ ok = yaffs2_wr_checkpt_validity_marker(dev, 1); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "write checkpoint device"); ++ ok = yaffs2_wr_checkpt_dev(dev); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "write checkpoint objects"); ++ ok = yaffs2_wr_checkpt_objs(dev); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "write checkpoint validity"); ++ ok = yaffs2_wr_checkpt_validity_marker(dev, 0); ++ } ++ ++ if (ok) ++ ok = yaffs2_wr_checkpt_sum(dev); ++ ++ if (!yaffs_checkpt_close(dev)) ++ ok = 0; ++ ++ if (ok) ++ dev->is_checkpointed = 1; ++ else ++ dev->is_checkpointed = 0; ++ ++ return dev->is_checkpointed; ++} ++ ++static int yaffs2_rd_checkpt_data(struct yaffs_dev *dev) ++{ ++ int ok = 1; ++ ++ if (!dev->param.is_yaffs2) ++ ok = 0; ++ ++ if (ok && dev->param.skip_checkpt_rd) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "skipping checkpoint read"); ++ ok = 0; ++ } ++ ++ if (ok) ++ ok = yaffs2_checkpt_open(dev, 0); /* open for read */ ++ ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "read checkpoint validity"); ++ ok = yaffs2_rd_checkpt_validity_marker(dev, 1); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "read checkpoint device"); ++ ok = yaffs2_rd_checkpt_dev(dev); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "read checkpoint objects"); ++ ok = yaffs2_rd_checkpt_objs(dev); ++ } ++ if (ok) { ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "read checkpoint validity"); ++ ok = yaffs2_rd_checkpt_validity_marker(dev, 0); ++ } ++ ++ if (ok) { ++ ok = yaffs2_rd_checkpt_sum(dev); ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "read checkpoint checksum %d", ok); ++ } ++ ++ if (!yaffs_checkpt_close(dev)) ++ ok = 0; ++ ++ if (ok) ++ dev->is_checkpointed = 1; ++ else ++ dev->is_checkpointed = 0; ++ ++ return ok ? 1 : 0; ++} ++ ++void yaffs2_checkpt_invalidate(struct yaffs_dev *dev) ++{ ++ if (dev->is_checkpointed || dev->blocks_in_checkpt > 0) { ++ dev->is_checkpointed = 0; ++ yaffs2_checkpt_invalidate_stream(dev); ++ } ++ if (dev->param.sb_dirty_fn) ++ dev->param.sb_dirty_fn(dev); ++} ++ ++int yaffs_checkpoint_save(struct yaffs_dev *dev) ++{ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "save entry: is_checkpointed %d", ++ dev->is_checkpointed); ++ ++ yaffs_verify_objects(dev); ++ yaffs_verify_blocks(dev); ++ yaffs_verify_free_chunks(dev); ++ ++ if (!dev->is_checkpointed) { ++ yaffs2_checkpt_invalidate(dev); ++ yaffs2_wr_checkpt_data(dev); ++ } ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, ++ "save exit: is_checkpointed %d", ++ dev->is_checkpointed); ++ ++ return dev->is_checkpointed; ++} ++ ++int yaffs2_checkpt_restore(struct yaffs_dev *dev) ++{ ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "restore entry: is_checkpointed %d", ++ dev->is_checkpointed); ++ ++ retval = yaffs2_rd_checkpt_data(dev); ++ ++ if (dev->is_checkpointed) { ++ yaffs_verify_objects(dev); ++ yaffs_verify_blocks(dev); ++ yaffs_verify_free_chunks(dev); ++ } ++ ++ yaffs_trace(YAFFS_TRACE_CHECKPOINT, ++ "restore exit: is_checkpointed %d", ++ dev->is_checkpointed); ++ ++ return retval; ++} ++ ++int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size) ++{ ++ /* if new_size > old_file_size. ++ * We're going to be writing a hole. ++ * If the hole is small then write zeros otherwise write a start ++ * of hole marker. ++ */ ++ loff_t old_file_size; ++ loff_t increase; ++ int small_hole; ++ int result = YAFFS_OK; ++ struct yaffs_dev *dev = NULL; ++ u8 *local_buffer = NULL; ++ int small_increase_ok = 0; ++ ++ if (!obj) ++ return YAFFS_FAIL; ++ ++ if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) ++ return YAFFS_FAIL; ++ ++ dev = obj->my_dev; ++ ++ /* Bail out if not yaffs2 mode */ ++ if (!dev->param.is_yaffs2) ++ return YAFFS_OK; ++ ++ old_file_size = obj->variant.file_variant.file_size; ++ ++ if (new_size <= old_file_size) ++ return YAFFS_OK; ++ ++ increase = new_size - old_file_size; ++ ++ if (increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->data_bytes_per_chunk && ++ yaffs_check_alloc_available(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1)) ++ small_hole = 1; ++ else ++ small_hole = 0; ++ ++ if (small_hole) ++ local_buffer = yaffs_get_temp_buffer(dev); ++ ++ if (local_buffer) { ++ /* fill hole with zero bytes */ ++ loff_t pos = old_file_size; ++ int this_write; ++ int written; ++ memset(local_buffer, 0, dev->data_bytes_per_chunk); ++ small_increase_ok = 1; ++ ++ while (increase > 0 && small_increase_ok) { ++ this_write = increase; ++ if (this_write > dev->data_bytes_per_chunk) ++ this_write = dev->data_bytes_per_chunk; ++ written = ++ yaffs_do_file_wr(obj, local_buffer, pos, this_write, ++ 0); ++ if (written == this_write) { ++ pos += this_write; ++ increase -= this_write; ++ } else { ++ small_increase_ok = 0; ++ } ++ } ++ ++ yaffs_release_temp_buffer(dev, local_buffer); ++ ++ /* If out of space then reverse any chunks we've added */ ++ if (!small_increase_ok) ++ yaffs_resize_file_down(obj, old_file_size); ++ } ++ ++ if (!small_increase_ok && ++ obj->parent && ++ obj->parent->obj_id != YAFFS_OBJECTID_UNLINKED && ++ obj->parent->obj_id != YAFFS_OBJECTID_DELETED) { ++ /* Write a hole start header with the old file size */ ++ yaffs_update_oh(obj, NULL, 0, 1, 0, NULL); ++ } ++ ++ return result; ++} ++ ++struct yaffs_block_index { ++ int seq; ++ int block; ++}; ++ ++static int yaffs2_ybicmp(const void *a, const void *b) ++{ ++ int aseq = ((struct yaffs_block_index *)a)->seq; ++ int bseq = ((struct yaffs_block_index *)b)->seq; ++ int ablock = ((struct yaffs_block_index *)a)->block; ++ int bblock = ((struct yaffs_block_index *)b)->block; ++ ++ if (aseq == bseq) ++ return ablock - bblock; ++ ++ return aseq - bseq; ++} ++ ++static inline int yaffs2_scan_chunk(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi, ++ int blk, int chunk_in_block, ++ int *found_chunks, ++ u8 *chunk_data, ++ struct list_head *hard_list, ++ int summary_available) ++{ ++ struct yaffs_obj_hdr *oh; ++ struct yaffs_obj *in; ++ struct yaffs_obj *parent; ++ int equiv_id; ++ loff_t file_size; ++ int is_shrink; ++ int is_unlinked; ++ struct yaffs_ext_tags tags; ++ int result; ++ int alloc_failed = 0; ++ int chunk = blk * dev->param.chunks_per_block + chunk_in_block; ++ struct yaffs_file_var *file_var; ++ struct yaffs_hardlink_var *hl_var; ++ struct yaffs_symlink_var *sl_var; ++ ++ if (summary_available) { ++ result = yaffs_summary_fetch(dev, &tags, chunk_in_block); ++ tags.seq_number = bi->seq_number; ++ } ++ ++ if (!summary_available || tags.obj_id == 0) { ++ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags); ++ dev->tags_used++; ++ } else { ++ dev->summary_used++; ++ } ++ ++ /* Let's have a good look at this chunk... */ ++ ++ if (!tags.chunk_used) { ++ /* An unassigned chunk in the block. ++ * If there are used chunks after this one, then ++ * it is a chunk that was skipped due to failing ++ * the erased check. Just skip it so that it can ++ * be deleted. ++ * But, more typically, We get here when this is ++ * an unallocated chunk and his means that ++ * either the block is empty or this is the one ++ * being allocated from ++ */ ++ ++ if (*found_chunks) { ++ /* This is a chunk that was skipped due ++ * to failing the erased check */ ++ } else if (chunk_in_block == 0) { ++ /* We're looking at the first chunk in ++ * the block so the block is unused */ ++ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; ++ dev->n_erased_blocks++; ++ } else { ++ if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || ++ bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { ++ if (dev->seq_number == bi->seq_number) { ++ /* Allocating from this block*/ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ " Allocating from %d %d", ++ blk, chunk_in_block); ++ ++ bi->block_state = ++ YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->alloc_block = blk; ++ dev->alloc_page = chunk_in_block; ++ dev->alloc_block_finder = blk; ++ } else { ++ /* This is a partially written block ++ * that is not the current ++ * allocation block. ++ */ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "Partially written block %d detected. gc will fix this.", ++ blk); ++ } ++ } ++ } ++ ++ dev->n_free_chunks++; ++ ++ } else if (tags.ecc_result == ++ YAFFS_ECC_RESULT_UNFIXED) { ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ " Unfixed ECC in chunk(%d:%d), chunk ignored", ++ blk, chunk_in_block); ++ dev->n_free_chunks++; ++ } else if (tags.obj_id > YAFFS_MAX_OBJECT_ID || ++ tags.chunk_id > YAFFS_MAX_CHUNK_ID || ++ tags.obj_id == YAFFS_OBJECTID_SUMMARY || ++ (tags.chunk_id > 0 && ++ tags.n_bytes > dev->data_bytes_per_chunk) || ++ tags.seq_number != bi->seq_number) { ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "Chunk (%d:%d) with bad tags:obj = %d, chunk_id = %d, n_bytes = %d, ignored", ++ blk, chunk_in_block, tags.obj_id, ++ tags.chunk_id, tags.n_bytes); ++ dev->n_free_chunks++; ++ } else if (tags.chunk_id > 0) { ++ /* chunk_id > 0 so it is a data chunk... */ ++ loff_t endpos; ++ loff_t chunk_base = (tags.chunk_id - 1) * ++ dev->data_bytes_per_chunk; ++ ++ *found_chunks = 1; ++ ++ yaffs_set_chunk_bit(dev, blk, chunk_in_block); ++ bi->pages_in_use++; ++ ++ in = yaffs_find_or_create_by_number(dev, ++ tags.obj_id, ++ YAFFS_OBJECT_TYPE_FILE); ++ if (!in) ++ /* Out of memory */ ++ alloc_failed = 1; ++ ++ if (in && ++ in->variant_type == YAFFS_OBJECT_TYPE_FILE && ++ chunk_base < in->variant.file_variant.shrink_size) { ++ /* This has not been invalidated by ++ * a resize */ ++ if (!yaffs_put_chunk_in_file(in, tags.chunk_id, ++ chunk, -1)) ++ alloc_failed = 1; ++ ++ /* File size is calculated by looking at ++ * the data chunks if we have not ++ * seen an object header yet. ++ * Stop this practice once we find an ++ * object header. ++ */ ++ endpos = chunk_base + tags.n_bytes; ++ ++ if (!in->valid && ++ in->variant.file_variant.scanned_size < endpos) { ++ in->variant.file_variant. ++ scanned_size = endpos; ++ in->variant.file_variant. ++ file_size = endpos; ++ } ++ } else if (in) { ++ /* This chunk has been invalidated by a ++ * resize, or a past file deletion ++ * so delete the chunk*/ ++ yaffs_chunk_del(dev, chunk, 1, __LINE__); ++ } ++ } else { ++ /* chunk_id == 0, so it is an ObjectHeader. ++ * Thus, we read in the object header and make ++ * the object ++ */ ++ *found_chunks = 1; ++ ++ yaffs_set_chunk_bit(dev, blk, chunk_in_block); ++ bi->pages_in_use++; ++ ++ oh = NULL; ++ in = NULL; ++ ++ if (tags.extra_available) { ++ in = yaffs_find_or_create_by_number(dev, ++ tags.obj_id, ++ tags.extra_obj_type); ++ if (!in) ++ alloc_failed = 1; ++ } ++ ++ if (!in || ++ (!in->valid && dev->param.disable_lazy_load) || ++ tags.extra_shadows || ++ (!in->valid && (tags.obj_id == YAFFS_OBJECTID_ROOT || ++ tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND))) { ++ ++ /* If we don't have valid info then we ++ * need to read the chunk ++ * TODO In future we can probably defer ++ * reading the chunk and living with ++ * invalid data until needed. ++ */ ++ ++ result = yaffs_rd_chunk_tags_nand(dev, ++ chunk, ++ chunk_data, ++ NULL); ++ ++ oh = (struct yaffs_obj_hdr *)chunk_data; ++ ++ if (dev->param.inband_tags) { ++ /* Fix up the header if they got ++ * corrupted by inband tags */ ++ oh->shadows_obj = ++ oh->inband_shadowed_obj_id; ++ oh->is_shrink = ++ oh->inband_is_shrink; ++ } ++ ++ if (!in) { ++ in = yaffs_find_or_create_by_number(dev, ++ tags.obj_id, oh->type); ++ if (!in) ++ alloc_failed = 1; ++ } ++ } ++ ++ if (!in) { ++ /* TODO Hoosterman we have a problem! */ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: Could not make object for object %d at chunk %d during scan", ++ tags.obj_id, chunk); ++ return YAFFS_FAIL; ++ } ++ ++ if (in->valid) { ++ /* We have already filled this one. ++ * We have a duplicate that will be ++ * discarded, but we first have to suck ++ * out resize info if it is a file. ++ */ ++ if ((in->variant_type == YAFFS_OBJECT_TYPE_FILE) && ++ ((oh && oh->type == YAFFS_OBJECT_TYPE_FILE) || ++ (tags.extra_available && ++ tags.extra_obj_type == YAFFS_OBJECT_TYPE_FILE) ++ )) { ++ loff_t this_size = (oh) ? ++ yaffs_oh_to_size(oh) : ++ tags.extra_file_size; ++ u32 parent_obj_id = (oh) ? ++ oh->parent_obj_id : ++ tags.extra_parent_id; ++ ++ is_shrink = (oh) ? ++ oh->is_shrink : ++ tags.extra_is_shrink; ++ ++ /* If it is deleted (unlinked ++ * at start also means deleted) ++ * we treat the file size as ++ * being zeroed at this point. ++ */ ++ if (parent_obj_id == YAFFS_OBJECTID_DELETED || ++ parent_obj_id == YAFFS_OBJECTID_UNLINKED) { ++ this_size = 0; ++ is_shrink = 1; ++ } ++ ++ if (is_shrink && ++ in->variant.file_variant.shrink_size > ++ this_size) ++ in->variant.file_variant.shrink_size = ++ this_size; ++ ++ if (is_shrink) ++ bi->has_shrink_hdr = 1; ++ } ++ /* Use existing - destroy this one. */ ++ yaffs_chunk_del(dev, chunk, 1, __LINE__); ++ } ++ ++ if (!in->valid && in->variant_type != ++ (oh ? oh->type : tags.extra_obj_type)) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: Bad type, %d != %d, for object %d at chunk %d during scan", ++ oh ? oh->type : tags.extra_obj_type, ++ in->variant_type, tags.obj_id, ++ chunk); ++ in = yaffs_retype_obj(in, oh ? oh->type : tags.extra_obj_type); ++ } ++ ++ if (!in->valid && ++ (tags.obj_id == YAFFS_OBJECTID_ROOT || ++ tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND)) { ++ /* We only load some info, don't fiddle ++ * with directory structure */ ++ in->valid = 1; ++ ++ if (oh) { ++ in->yst_mode = oh->yst_mode; ++ yaffs_load_attribs(in, oh); ++ in->lazy_loaded = 0; ++ } else { ++ in->lazy_loaded = 1; ++ } ++ in->hdr_chunk = chunk; ++ ++ } else if (!in->valid) { ++ /* we need to load this info */ ++ in->valid = 1; ++ in->hdr_chunk = chunk; ++ if (oh) { ++ in->variant_type = oh->type; ++ in->yst_mode = oh->yst_mode; ++ yaffs_load_attribs(in, oh); ++ ++ if (oh->shadows_obj > 0) ++ yaffs_handle_shadowed_obj(dev, ++ oh->shadows_obj, 1); ++ ++ yaffs_set_obj_name_from_oh(in, oh); ++ parent = yaffs_find_or_create_by_number(dev, ++ oh->parent_obj_id, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ file_size = yaffs_oh_to_size(oh); ++ is_shrink = oh->is_shrink; ++ equiv_id = oh->equiv_id; ++ } else { ++ in->variant_type = tags.extra_obj_type; ++ parent = yaffs_find_or_create_by_number(dev, ++ tags.extra_parent_id, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ file_size = tags.extra_file_size; ++ is_shrink = tags.extra_is_shrink; ++ equiv_id = tags.extra_equiv_id; ++ in->lazy_loaded = 1; ++ } ++ in->dirty = 0; ++ ++ if (!parent) ++ alloc_failed = 1; ++ ++ /* directory stuff... ++ * hook up to parent ++ */ ++ ++ if (parent && ++ parent->variant_type == YAFFS_OBJECT_TYPE_UNKNOWN) { ++ /* Set up as a directory */ ++ parent->variant_type = ++ YAFFS_OBJECT_TYPE_DIRECTORY; ++ INIT_LIST_HEAD(&parent-> ++ variant.dir_variant.children); ++ } else if (!parent || ++ parent->variant_type != ++ YAFFS_OBJECT_TYPE_DIRECTORY) { ++ /* Hoosterman, another problem.... ++ * Trying to use a non-directory as a directory ++ */ ++ ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." ++ ); ++ parent = dev->lost_n_found; ++ } ++ yaffs_add_obj_to_dir(parent, in); ++ ++ is_unlinked = (parent == dev->del_dir) || ++ (parent == dev->unlinked_dir); ++ ++ if (is_shrink) ++ /* Mark the block */ ++ bi->has_shrink_hdr = 1; ++ ++ /* Note re hardlinks. ++ * Since we might scan a hardlink before its equivalent ++ * object is scanned we put them all in a list. ++ * After scanning is complete, we should have all the ++ * objects, so we run through this list and fix up all ++ * the chains. ++ */ ++ ++ switch (in->variant_type) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Todo got a problem */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ file_var = &in->variant.file_variant; ++ if (file_var->scanned_size < file_size) { ++ /* This covers the case where the file ++ * size is greater than the data held. ++ * This will happen if the file is ++ * resized to be larger than its ++ * current data extents. ++ */ ++ file_var->file_size = file_size; ++ file_var->scanned_size = file_size; ++ } ++ ++ if (file_var->shrink_size > file_size) ++ file_var->shrink_size = file_size; ++ ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ hl_var = &in->variant.hardlink_variant; ++ if (!is_unlinked) { ++ hl_var->equiv_id = equiv_id; ++ list_add(&in->hard_links, hard_list); ++ } ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ sl_var = &in->variant.symlink_variant; ++ if (oh) { ++ sl_var->alias = ++ yaffs_clone_str(oh->alias); ++ if (!sl_var->alias) ++ alloc_failed = 1; ++ } ++ break; ++ } ++ } ++ } ++ return alloc_failed ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++int yaffs2_scan_backwards(struct yaffs_dev *dev) ++{ ++ int blk; ++ int block_iter; ++ int start_iter; ++ int end_iter; ++ int n_to_scan = 0; ++ enum yaffs_block_state state; ++ int c; ++ int deleted; ++ LIST_HEAD(hard_list); ++ struct yaffs_block_info *bi; ++ u32 seq_number; ++ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; ++ u8 *chunk_data; ++ int found_chunks; ++ int alloc_failed = 0; ++ struct yaffs_block_index *block_index = NULL; ++ int alt_block_index = 0; ++ int summary_available; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "yaffs2_scan_backwards starts intstartblk %d intendblk %d...", ++ dev->internal_start_block, dev->internal_end_block); ++ ++ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; ++ ++ block_index = ++ kmalloc(n_blocks * sizeof(struct yaffs_block_index), GFP_NOFS); ++ ++ if (!block_index) { ++ block_index = ++ vmalloc(n_blocks * sizeof(struct yaffs_block_index)); ++ alt_block_index = 1; ++ } ++ ++ if (!block_index) { ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "yaffs2_scan_backwards() could not allocate block index!" ++ ); ++ return YAFFS_FAIL; ++ } ++ ++ dev->blocks_in_checkpt = 0; ++ ++ chunk_data = yaffs_get_temp_buffer(dev); ++ ++ /* Scan all the blocks to determine their state */ ++ bi = dev->block_info; ++ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; ++ blk++) { ++ yaffs_clear_chunk_bits(dev, blk); ++ bi->pages_in_use = 0; ++ bi->soft_del_pages = 0; ++ ++ yaffs_query_init_block_state(dev, blk, &state, &seq_number); ++ ++ bi->block_state = state; ++ bi->seq_number = seq_number; ++ ++ if (bi->seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) ++ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; ++ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) ++ bi->block_state = YAFFS_BLOCK_STATE_DEAD; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, ++ "Block scanning block %d state %d seq %d", ++ blk, bi->block_state, seq_number); ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { ++ dev->blocks_in_checkpt++; ++ ++ } else if (bi->block_state == YAFFS_BLOCK_STATE_DEAD) { ++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, ++ "block %d is bad", blk); ++ } else if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { ++ yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty "); ++ dev->n_erased_blocks++; ++ dev->n_free_chunks += dev->param.chunks_per_block; ++ } else if (bi->block_state == ++ YAFFS_BLOCK_STATE_NEEDS_SCAN) { ++ /* Determine the highest sequence number */ ++ if (seq_number >= YAFFS_LOWEST_SEQUENCE_NUMBER && ++ seq_number < YAFFS_HIGHEST_SEQUENCE_NUMBER) { ++ block_index[n_to_scan].seq = seq_number; ++ block_index[n_to_scan].block = blk; ++ n_to_scan++; ++ if (seq_number >= dev->seq_number) ++ dev->seq_number = seq_number; ++ } else { ++ /* TODO: Nasty sequence number! */ ++ yaffs_trace(YAFFS_TRACE_SCAN, ++ "Block scanning block %d has bad sequence number %d", ++ blk, seq_number); ++ } ++ } ++ bi++; ++ } ++ ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "%d blocks to be sorted...", n_to_scan); ++ ++ cond_resched(); ++ ++ /* Sort the blocks by sequence number */ ++ sort(block_index, n_to_scan, sizeof(struct yaffs_block_index), ++ yaffs2_ybicmp, NULL); ++ ++ cond_resched(); ++ ++ yaffs_trace(YAFFS_TRACE_SCAN, "...done"); ++ ++ /* Now scan the blocks looking at the data. */ ++ start_iter = 0; ++ end_iter = n_to_scan - 1; ++ yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "%d blocks to scan", n_to_scan); ++ ++ /* For each block.... backwards */ ++ for (block_iter = end_iter; ++ !alloc_failed && block_iter >= start_iter; ++ block_iter--) { ++ /* Cooperative multitasking! This loop can run for so ++ long that watchdog timers expire. */ ++ cond_resched(); ++ ++ /* get the block to scan in the correct order */ ++ blk = block_index[block_iter].block; ++ bi = yaffs_get_block_info(dev, blk); ++ deleted = 0; ++ ++ summary_available = yaffs_summary_read(dev, dev->sum_tags, blk); ++ ++ /* For each chunk in each block that needs scanning.... */ ++ found_chunks = 0; ++ if (summary_available) ++ c = dev->chunks_per_summary - 1; ++ else ++ c = dev->param.chunks_per_block - 1; ++ ++ for (/* c is already initialised */; ++ !alloc_failed && c >= 0 && ++ (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || ++ bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING); ++ c--) { ++ /* Scan backwards... ++ * Read the tags and decide what to do ++ */ ++ if (yaffs2_scan_chunk(dev, bi, blk, c, ++ &found_chunks, chunk_data, ++ &hard_list, summary_available) == ++ YAFFS_FAIL) ++ alloc_failed = 1; ++ } ++ ++ if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN) { ++ /* If we got this far while scanning, then the block ++ * is fully allocated. */ ++ bi->block_state = YAFFS_BLOCK_STATE_FULL; ++ } ++ ++ /* Now let's see if it was dirty */ ++ if (bi->pages_in_use == 0 && ++ !bi->has_shrink_hdr && ++ bi->block_state == YAFFS_BLOCK_STATE_FULL) { ++ yaffs_block_became_dirty(dev, blk); ++ } ++ } ++ ++ yaffs_skip_rest_of_block(dev); ++ ++ if (alt_block_index) ++ vfree(block_index); ++ else ++ kfree(block_index); ++ ++ /* Ok, we've done all the scanning. ++ * Fix up the hard link chains. ++ * We have scanned all the objects, now it's time to add these ++ * hardlinks. ++ */ ++ yaffs_link_fixup(dev, &hard_list); ++ ++ yaffs_release_temp_buffer(dev, chunk_data); ++ ++ if (alloc_failed) ++ return YAFFS_FAIL; ++ ++ yaffs_trace(YAFFS_TRACE_SCAN, "yaffs2_scan_backwards ends"); ++ ++ return YAFFS_OK; ++} +diff --git a/fs/yaffs2/yaffs_yaffs2.h b/fs/yaffs2/yaffs_yaffs2.h +new file mode 100644 +index 00000000..2363bfd8 +--- /dev/null ++++ b/fs/yaffs2/yaffs_yaffs2.h +@@ -0,0 +1,39 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_YAFFS2_H__ ++#define __YAFFS_YAFFS2_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev); ++void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev); ++void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, ++ struct yaffs_block_info *bi); ++void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, ++ struct yaffs_block_info *bi); ++int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi); ++u32 yaffs2_find_refresh_block(struct yaffs_dev *dev); ++int yaffs2_checkpt_required(struct yaffs_dev *dev); ++int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev); ++ ++void yaffs2_checkpt_invalidate(struct yaffs_dev *dev); ++int yaffs2_checkpt_save(struct yaffs_dev *dev); ++int yaffs2_checkpt_restore(struct yaffs_dev *dev); ++ ++int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size); ++int yaffs2_scan_backwards(struct yaffs_dev *dev); ++ ++#endif +diff --git a/fs/yaffs2/yportenv.h b/fs/yaffs2/yportenv.h +new file mode 100644 +index 00000000..8975af33 +--- /dev/null ++++ b/fs/yaffs2/yportenv.h +@@ -0,0 +1,85 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2011 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YPORTENV_H__ ++#define __YPORTENV_H__ ++ ++/* ++ * Define the MTD version in terms of Linux Kernel versions ++ * This allows yaffs to be used independantly of the kernel ++ * as well as with it. ++ */ ++ ++#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) ++ ++#ifdef YAFFS_OUT_OF_TREE ++#include "moduleconfig.h" ++#endif ++ ++#include ++#define MTD_VERSION_CODE LINUX_VERSION_CODE ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* These type wrappings are used to support Unicode names in WinCE. */ ++#define YCHAR char ++#define YUCHAR unsigned char ++#define _Y(x) x ++ ++#define YAFFS_LOSTNFOUND_NAME "lost+found" ++#define YAFFS_LOSTNFOUND_PREFIX "obj" ++ ++ ++#define YAFFS_ROOT_MODE 0755 ++#define YAFFS_LOSTNFOUND_MODE 0700 ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) ++#define Y_CURRENT_TIME CURRENT_TIME.tv_sec ++#define Y_TIME_CONVERT(x) (x).tv_sec ++#else ++#define Y_CURRENT_TIME CURRENT_TIME ++#define Y_TIME_CONVERT(x) (x) ++#endif ++ ++#define compile_time_assertion(assertion) \ ++ ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; }) ++ ++ ++#define yaffs_printf(msk, fmt, ...) \ ++ printk(KERN_DEBUG "yaffs: " fmt "\n", ##__VA_ARGS__) ++ ++#define yaffs_trace(msk, fmt, ...) do { \ ++ if (yaffs_trace_mask & (msk)) \ ++ printk(KERN_DEBUG "yaffs: " fmt "\n", ##__VA_ARGS__); \ ++} while (0) ++ ++ ++#endif +diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h +index 5f52690c..832f533d 100644 +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -100,7 +100,7 @@ struct gpio_chip { + unsigned offset); + + int (*direction_input)(struct gpio_chip *chip, +- unsigned offset); ++ unsigned offset, int value); + int (*get)(struct gpio_chip *chip, + unsigned offset); + int (*direction_output)(struct gpio_chip *chip, +@@ -153,7 +153,7 @@ extern struct gpio_chip *gpiochip_find(const void *data, + extern int gpio_request(unsigned gpio, const char *label); + extern void gpio_free(unsigned gpio); + +-extern int gpio_direction_input(unsigned gpio); ++extern int gpio_direction_input(unsigned gpio, int value); + extern int gpio_direction_output(unsigned gpio, int value); + + extern int gpio_set_debounce(unsigned gpio, unsigned debounce); +diff --git a/include/linux/gk-i2cmux.h b/include/linux/gk-i2cmux.h +new file mode 100644 +index 00000000..b9757f98 +--- /dev/null ++++ b/include/linux/gk-i2cmux.h +@@ -0,0 +1,18 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _LINUX_GK_I2CMUX_H ++#define _LINUX_GK_I2CMUX_H ++ ++struct gk_i2cmux_platform_data { ++ int parent; ++ unsigned number; ++ unsigned gpio; ++ unsigned select_function; ++ unsigned deselect_function; ++}; ++ ++#endif /* _LINUX_GK_I2CMUX_H */ +diff --git a/include/linux/i2c.h b/include/linux/i2c.h +index 195d8b3d..ea2ade1f 100644 +--- a/include/linux/i2c.h ++++ b/include/linux/i2c.h +@@ -68,6 +68,8 @@ extern int i2c_master_recv(const struct i2c_client *client, char *buf, + */ + extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num); ++extern int i2c_transfer_noevent(struct i2c_adapter *adap, struct i2c_msg *msgs, ++ int num); + + /* This is the very generalized SMBus access routine. You probably do not + want to use this, though; one of the functions below may be much easier, +@@ -361,6 +363,8 @@ struct i2c_algorithm { + int (*smbus_xfer) (struct i2c_adapter *adap, u16 addr, + unsigned short flags, char read_write, + u8 command, int size, union i2c_smbus_data *data); ++ int (*master_xfer_noevent)(struct i2c_adapter *adap, struct i2c_msg *msgs, ++ int num); + + /* To determine what the adapter supports */ + u32 (*functionality) (struct i2c_adapter *); +diff --git a/include/linux/ipcbus.h b/include/linux/ipcbus.h +new file mode 100644 +index 00000000..848b4778 +--- /dev/null ++++ b/include/linux/ipcbus.h +@@ -0,0 +1,29 @@ ++/* ++ * IPC bus. ++ */ ++ ++#ifndef __LINUX_IPCBUS_H ++#define __LINUX_IPCBUS_H ++ ++#include ++#include ++ ++struct ipc_driver { ++ int (*match)(struct device *); ++ int (*probe)(struct device *); ++ int (*remove)(struct device *); ++ void (*shutdown)(struct device *); ++ int (*suspend)(struct device *, pm_message_t); ++ int (*resume)(struct device *); ++ ++ struct device_driver driver; ++ struct device *devices; ++}; ++ ++#define to_ipc_driver(x) container_of((x), struct ipc_driver, driver) ++ ++ ++int ipc_register_driver(struct ipc_driver *); ++void ipc_unregister_driver(struct ipc_driver *); ++ ++#endif /* __LINUX_IPCBUS_H */ +diff --git a/include/linux/phy.h b/include/linux/phy.h +index 6fe0a37d..e53bb8ce 100644 +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -119,6 +119,7 @@ struct mii_bus { + + /* list of all PHYs on bus */ + struct phy_device *phy_map[PHY_MAX_ADDR]; ++ struct phy_device *phy_used; + + /* PHY addresses to be ignored when probing */ + u32 phy_mask; +diff --git a/include/linux/spinlock_types.h b/include/linux/spinlock_types.h +index 73548eb1..eb2231ed 100644 +--- a/include/linux/spinlock_types.h ++++ b/include/linux/spinlock_types.h +@@ -80,6 +80,14 @@ typedef struct spinlock { + + #define __SPIN_LOCK_UNLOCKED(lockname) \ + (spinlock_t ) __SPIN_LOCK_INITIALIZER(lockname) ++ ++/* ++ * SPIN_LOCK_UNLOCKED defeats lockdep state tracking and is hence ++ * deprecated. ++ * Please use DEFINE_SPINLOCK() or __SPIN_LOCK_UNLOCKED() as ++ * appropriate. ++ */ ++#define SPIN_LOCK_UNLOCKED __SPIN_LOCK_UNLOCKED(old_style_spin_init) + + #define DEFINE_SPINLOCK(x) spinlock_t x = __SPIN_LOCK_UNLOCKED(x) + +diff --git a/include/linux/usb.h b/include/linux/usb.h +index 4e8e6685..a66954f6 100644 +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -714,6 +714,22 @@ static inline int usb_make_path(struct usb_device *dev, char *buf, size_t size) + .bcdDevice_lo = (lo), \ + .bcdDevice_hi = (hi) + ++/** ++ * USB_DEVICE_INTERFACE_CLASS - describe a usb device with a specific interface class ++ * @vend: the 16 bit USB Vendor ID ++ * @prod: the 16 bit USB Product ID ++ * @cl: bInterfaceClass value ++ * ++ * This macro is used to create a struct usb_device_id that matches a ++ * specific interface class of devices. ++ */ ++#define USB_DEVICE_INTERFACE_CLASS(vend, prod, cl) \ ++ .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ ++ USB_DEVICE_ID_MATCH_INT_CLASS, \ ++ .idVendor = (vend), \ ++ .idProduct = (prod), \ ++ .bInterfaceClass = (cl) ++ + /** + * USB_DEVICE_INTERFACE_PROTOCOL - describe a usb device with a specific interface protocol + * @vend: the 16 bit USB Vendor ID +@@ -1273,6 +1289,7 @@ struct urb { + int number_of_packets; /* (in) number of ISO packets */ + int interval; /* (modify) transfer interval + * (INT/ISO) */ ++ int align; + int error_count; /* (return) number of ISO errors */ + void *context; /* (in) context for completion */ + usb_complete_t complete; /* (in) completion routine */ +diff --git a/include/linux/usb/android_composite.h b/include/linux/usb/android_composite.h +new file mode 100644 +index 00000000..62e72e3b +--- /dev/null ++++ b/include/linux/usb/android_composite.h +@@ -0,0 +1,101 @@ ++/* ++ * Platform data for Android USB ++ * ++ * Copyright (C) 2008 Google, Inc. ++ * Author: Mike Lockwood ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++#ifndef __LINUX_USB_ANDROID_H ++#define __LINUX_USB_ANDROID_H ++ ++#include ++#include ++ ++struct android_usb_function { ++ struct list_head list; ++ char *name; ++ int (*bind_config)(struct usb_configuration *c); ++}; ++ ++struct android_usb_product { ++ /* Default product ID. */ ++ __u16 product_id; ++ ++ /* List of function names associated with this product. ++ * This is used to compute the USB product ID dynamically ++ * based on which functions are enabled. ++ */ ++ int num_functions; ++ char **functions; ++}; ++ ++struct android_usb_platform_data { ++ /* USB device descriptor fields */ ++ __u16 vendor_id; ++ ++ /* Default product ID. */ ++ __u16 product_id; ++ ++ __u16 version; ++ ++ char *product_name; ++ char *manufacturer_name; ++ char *serial_number; ++ ++ /* List of available USB products. ++ * This is used to compute the USB product ID dynamically ++ * based on which functions are enabled. ++ * if num_products is zero or no match can be found, ++ * we use the default product ID ++ */ ++ int num_products; ++ struct android_usb_product *products; ++ ++ /* List of all supported USB functions. ++ * This list is used to define the order in which ++ * the functions appear in the configuration's list of USB interfaces. ++ * This is necessary to avoid depending upon the order in which ++ * the individual function drivers are initialized. ++ */ ++ int num_functions; ++ char **functions; ++}; ++ ++/* Platform data for "usb_mass_storage" driver. */ ++struct usb_mass_storage_platform_data { ++ /* Contains values for the SC_INQUIRY SCSI command. */ ++ char *vendor; ++ char *product; ++ int release; ++ ++ /* number of LUNS */ ++ int nluns; ++}; ++ ++/* Platform data for USB ethernet driver. */ ++struct usb_ether_platform_data { ++ u8 ethaddr[ETH_ALEN]; ++ u32 vendorID; ++ const char *vendorDescr; ++}; ++ ++/* Platform data for ACM driver. */ ++struct acm_platform_data { ++ u8 num_inst; ++}; ++ ++extern void android_register_function(struct android_usb_function *f); ++ ++extern void android_enable_function(struct usb_function *f, int enable); ++ ++ ++#endif /* __LINUX_USB_ANDROID_H */ +diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h +index 5de41570..feb77716 100644 +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -126,6 +126,7 @@ struct usb_hcd { + unsigned wireless:1; /* Wireless USB HCD */ + unsigned authorized_default:1; + unsigned has_tt:1; /* Integrated TT in root hub */ ++ unsigned cant_recv_wakeups:1; + + unsigned int irq; /* irq allocated */ + void __iomem *regs; /* device memory/io */ +@@ -393,12 +394,13 @@ extern int usb_hcd_pci_probe(struct pci_dev *dev, + extern void usb_hcd_pci_remove(struct pci_dev *dev); + extern void usb_hcd_pci_shutdown(struct pci_dev *dev); + +-#ifdef CONFIG_PM_SLEEP ++#ifdef CONFIG_PM + extern const struct dev_pm_ops usb_hcd_pci_pm_ops; + #endif + #endif /* CONFIG_PCI */ + + /* pci-ish (pdev null is ok) buffer alloc/mapping support */ ++void usb_init_pool_max(void); + int hcd_buffer_create(struct usb_hcd *hcd); + void hcd_buffer_destroy(struct usb_hcd *hcd); + +diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h +index 3e93de7e..0972470b 100644 +--- a/include/linux/usb/quirks.h ++++ b/include/linux/usb/quirks.h +@@ -30,4 +30,21 @@ + descriptor */ + #define USB_QUIRK_DELAY_INIT 0x00000040 + ++/* device generates spurious wakeup, ignore remote wakeup capability */ ++#define USB_QUIRK_IGNORE_REMOTE_WAKEUP 0x00000200 ++ ++/* device can't handle device_qualifier descriptor requests */ ++#define USB_QUIRK_DEVICE_QUALIFIER 0x00000100 ++ ++/* ++ * For high speed and super speed interupt endpoints, the USB 2.0 and ++ * USB 3.0 spec require the interval in microframes ++ * (1 microframe = 125 microseconds) to be calculated as ++ * interval = 2 ^ (bInterval-1). ++ * ++ * Devices with this quirk report their bInterval as the result of this ++ * calculation instead of the exponent variable used in the calculation. ++ */ ++#define USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL 0x00000080 ++ + #endif /* __LINUX_USB_QUIRKS_H */ +diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h +index 47428388..56dc033f 100644 +--- a/include/linux/usb/serial.h ++++ b/include/linux/usb/serial.h +@@ -66,6 +66,7 @@ + * port. + * @flags: usb serial port flags + * @write_wait: a wait_queue_head_t used by the port. ++ * @delta_msr_wait: modem-status-change wait queue + * @work: work queue entry for the line discipline waking up. + * @throttled: nonzero if the read urb is inactive to throttle the device + * @throttle_req: nonzero if the tty wants to throttle us +@@ -112,6 +113,7 @@ struct usb_serial_port { + + unsigned long flags; + wait_queue_head_t write_wait; ++ wait_queue_head_t delta_msr_wait; + struct work_struct work; + char throttled; + char throttle_req; +diff --git a/include/linux/vermagic.h b/include/linux/vermagic.h +index 6f8fbcf1..7d89860d 100644 +--- a/include/linux/vermagic.h ++++ b/include/linux/vermagic.h +@@ -25,9 +25,12 @@ + #define MODULE_ARCH_VERMAGIC "" + #endif + ++#if 0 + #define VERMAGIC_STRING \ + UTS_RELEASE " " \ + MODULE_VERMAGIC_SMP MODULE_VERMAGIC_PREEMPT \ + MODULE_VERMAGIC_MODULE_UNLOAD MODULE_VERMAGIC_MODVERSIONS \ + MODULE_ARCH_VERMAGIC +- ++#else ++#define VERMAGIC_STRING "3.4.43-Goke" ++#endif +diff --git a/net/ipv4/ipconfig.c b/net/ipv4/ipconfig.c +index 92ac7e73..924f357f 100644 +--- a/net/ipv4/ipconfig.c ++++ b/net/ipv4/ipconfig.c +@@ -89,7 +89,7 @@ + + /* Define the friendly delay before and after opening net devices */ + #define CONF_POST_OPEN 10 /* After opening: 10 msecs */ +-#define CONF_CARRIER_TIMEOUT 120000 /* Wait for carrier timeout */ ++#define CONF_CARRIER_TIMEOUT 2000 /* Wait for carrier timeout */ + + /* Define the timeout for waiting for a DHCP/BOOTP/RARP reply */ + #define CONF_OPEN_RETRIES 2 /* (Re)open devices twice */ +diff --git a/net/ipv4/tcp_cubic.c b/net/ipv4/tcp_cubic.c +index a9077f44..f5f310c0 100644 +--- a/net/ipv4/tcp_cubic.c ++++ b/net/ipv4/tcp_cubic.c +@@ -153,6 +153,21 @@ static void bictcp_init(struct sock *sk) + tcp_sk(sk)->snd_ssthresh = initial_ssthresh; + } + ++static void bictcp_cwnd_event(struct sock *sk, enum tcp_ca_event event) ++{ ++ if (event == CA_EVENT_TX_START) { ++ s32 delta = tcp_time_stamp - tcp_sk(sk)->lsndtime; ++ struct bictcp *ca = inet_csk_ca(sk); ++ ++ /* We were application limited (idle) for a while. ++ * Shift epoch_start to keep cwnd growth to cubic curve. ++ */ ++ if (ca->epoch_start && delta > 0) ++ ca->epoch_start += delta; ++ return; ++ } ++} ++ + /* calculate the cubic root of x using a table lookup followed by one + * Newton-Raphson iteration. + * Avg err ~= 0.195% +@@ -437,7 +452,8 @@ static struct tcp_congestion_ops cubictcp __read_mostly = { + .cong_avoid = bictcp_cong_avoid, + .set_state = bictcp_state, + .undo_cwnd = bictcp_undo_cwnd, +- .pkts_acked = bictcp_acked, ++ .cwnd_event = bictcp_cwnd_event, ++ .pkts_acked = bictcp_acked, + .owner = THIS_MODULE, + .name = "cubic", + }; +diff --git a/net/wireless/Kconfig b/net/wireless/Kconfig +index 2e4444fe..48788d58 100644 +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -1,5 +1,5 @@ + config WIRELESS_EXT +- bool ++ def_bool y + + config WEXT_CORE + def_bool y +@@ -11,10 +11,10 @@ config WEXT_PROC + depends on WEXT_CORE + + config WEXT_SPY +- bool ++ def_bool y + + config WEXT_PRIV +- bool ++ def_bool y + + config CFG80211 + tristate "cfg80211 - wireless configuration API" diff --git a/br-ext-chip-goke/board/gk710x/kernel/patches/0003-overlayfs-v13-3.4-rc7.patch b/br-ext-chip-goke/board/gk710x/kernel/patches/0003-overlayfs-v13-3.4-rc7.patch new file mode 100644 index 00000000..9787cc64 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/patches/0003-overlayfs-v13-3.4-rc7.patch @@ -0,0 +1,3363 @@ +diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking +index 4fca82e..42b0539 100644 +--- a/Documentation/filesystems/Locking ++++ b/Documentation/filesystems/Locking +@@ -62,6 +62,7 @@ ata *); + int (*removexattr) (struct dentry *, const char *); + void (*truncate_range)(struct inode *, loff_t, loff_t); + int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start, u64 len); ++ struct file *(*open)(struct dentry *,struct file *,const struct cred *); + + locking rules: + all may block +@@ -89,6 +90,7 @@ listxattr: no + removexattr: yes + truncate_range: yes + fiemap: no ++open: no + Additionally, ->rmdir(), ->unlink() and ->rename() have ->i_mutex on + victim. + cross-directory ->rename() has (per-superblock) ->s_vfs_rename_sem. +diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt +new file mode 100644 +index 0000000..7161dc3 +--- /dev/null ++++ b/Documentation/filesystems/overlayfs.txt +@@ -0,0 +1,199 @@ ++Written by: Neil Brown ++ ++Overlay Filesystem ++================== ++ ++This document describes a prototype for a new approach to providing ++overlay-filesystem functionality in Linux (sometimes referred to as ++union-filesystems). An overlay-filesystem tries to present a ++filesystem which is the result over overlaying one filesystem on top ++of the other. ++ ++The result will inevitably fail to look exactly like a normal ++filesystem for various technical reasons. The expectation is that ++many use cases will be able to ignore these differences. ++ ++This approach is 'hybrid' because the objects that appear in the ++filesystem do not all appear to belong to that filesystem. In many ++cases an object accessed in the union will be indistinguishable ++from accessing the corresponding object from the original filesystem. ++This is most obvious from the 'st_dev' field returned by stat(2). ++ ++While directories will report an st_dev from the overlay-filesystem, ++all non-directory objects will report an st_dev from the lower or ++upper filesystem that is providing the object. Similarly st_ino will ++only be unique when combined with st_dev, and both of these can change ++over the lifetime of a non-directory object. Many applications and ++tools ignore these values and will not be affected. ++ ++Upper and Lower ++--------------- ++ ++An overlay filesystem combines two filesystems - an 'upper' filesystem ++and a 'lower' filesystem. When a name exists in both filesystems, the ++object in the 'upper' filesystem is visible while the object in the ++'lower' filesystem is either hidden or, in the case of directories, ++merged with the 'upper' object. ++ ++It would be more correct to refer to an upper and lower 'directory ++tree' rather than 'filesystem' as it is quite possible for both ++directory trees to be in the same filesystem and there is no ++requirement that the root of a filesystem be given for either upper or ++lower. ++ ++The lower filesystem can be any filesystem supported by Linux and does ++not need to be writable. The lower filesystem can even be another ++overlayfs. The upper filesystem will normally be writable and if it ++is it must support the creation of trusted.* extended attributes, and ++must provide valid d_type in readdir responses, at least for symbolic ++links - so NFS is not suitable. ++ ++A read-only overlay of two read-only filesystems may use any ++filesystem type. ++ ++Directories ++----------- ++ ++Overlaying mainly involved directories. If a given name appears in both ++upper and lower filesystems and refers to a non-directory in either, ++then the lower object is hidden - the name refers only to the upper ++object. ++ ++Where both upper and lower objects are directories, a merged directory ++is formed. ++ ++At mount time, the two directories given as mount options are combined ++into a merged directory: ++ ++ mount -t overlayfs overlayfs -olowerdir=/lower,upperdir=/upper /overlay ++ ++Then whenever a lookup is requested in such a merged directory, the ++lookup is performed in each actual directory and the combined result ++is cached in the dentry belonging to the overlay filesystem. If both ++actual lookups find directories, both are stored and a merged ++directory is created, otherwise only one is stored: the upper if it ++exists, else the lower. ++ ++Only the lists of names from directories are merged. Other content ++such as metadata and extended attributes are reported for the upper ++directory only. These attributes of the lower directory are hidden. ++ ++whiteouts and opaque directories ++-------------------------------- ++ ++In order to support rm and rmdir without changing the lower ++filesystem, an overlay filesystem needs to record in the upper filesystem ++that files have been removed. This is done using whiteouts and opaque ++directories (non-directories are always opaque). ++ ++The overlay filesystem uses extended attributes with a ++"trusted.overlay." prefix to record these details. ++ ++A whiteout is created as a symbolic link with target ++"(overlay-whiteout)" and with xattr "trusted.overlay.whiteout" set to "y". ++When a whiteout is found in the upper level of a merged directory, any ++matching name in the lower level is ignored, and the whiteout itself ++is also hidden. ++ ++A directory is made opaque by setting the xattr "trusted.overlay.opaque" ++to "y". Where the upper filesystem contains an opaque directory, any ++directory in the lower filesystem with the same name is ignored. ++ ++readdir ++------- ++ ++When a 'readdir' request is made on a merged directory, the upper and ++lower directories are each read and the name lists merged in the ++obvious way (upper is read first, then lower - entries that already ++exist are not re-added). This merged name list is cached in the ++'struct file' and so remains as long as the file is kept open. If the ++directory is opened and read by two processes at the same time, they ++will each have separate caches. A seekdir to the start of the ++directory (offset 0) followed by a readdir will cause the cache to be ++discarded and rebuilt. ++ ++This means that changes to the merged directory do not appear while a ++directory is being read. This is unlikely to be noticed by many ++programs. ++ ++seek offsets are assigned sequentially when the directories are read. ++Thus if ++ - read part of a directory ++ - remember an offset, and close the directory ++ - re-open the directory some time later ++ - seek to the remembered offset ++ ++there may be little correlation between the old and new locations in ++the list of filenames, particularly if anything has changed in the ++directory. ++ ++Readdir on directories that are not merged is simply handled by the ++underlying directory (upper or lower). ++ ++ ++Non-directories ++--------------- ++ ++Objects that are not directories (files, symlinks, device-special ++files etc.) are presented either from the upper or lower filesystem as ++appropriate. When a file in the lower filesystem is accessed in a way ++the requires write-access, such as opening for write access, changing ++some metadata etc., the file is first copied from the lower filesystem ++to the upper filesystem (copy_up). Note that creating a hard-link ++also requires copy_up, though of course creation of a symlink does ++not. ++ ++The copy_up may turn out to be unnecessary, for example if the file is ++opened for read-write but the data is not modified. ++ ++The copy_up process first makes sure that the containing directory ++exists in the upper filesystem - creating it and any parents as ++necessary. It then creates the object with the same metadata (owner, ++mode, mtime, symlink-target etc.) and then if the object is a file, the ++data is copied from the lower to the upper filesystem. Finally any ++extended attributes are copied up. ++ ++Once the copy_up is complete, the overlay filesystem simply ++provides direct access to the newly created file in the upper ++filesystem - future operations on the file are barely noticed by the ++overlay filesystem (though an operation on the name of the file such as ++rename or unlink will of course be noticed and handled). ++ ++ ++Non-standard behavior ++--------------------- ++ ++The copy_up operation essentially creates a new, identical file and ++moves it over to the old name. The new file may be on a different ++filesystem, so both st_dev and st_ino of the file may change. ++ ++Any open files referring to this inode will access the old data and ++metadata. Similarly any file locks obtained before copy_up will not ++apply to the copied up file. ++ ++On a file is opened with O_RDONLY fchmod(2), fchown(2), futimesat(2) ++and fsetxattr(2) will fail with EROFS. ++ ++If a file with multiple hard links is copied up, then this will ++"break" the link. Changes will not be propagated to other names ++referring to the same inode. ++ ++Symlinks in /proc/PID/ and /proc/PID/fd which point to a non-directory ++object in overlayfs will not contain vaid absolute paths, only ++relative paths leading up to the filesystem's root. This will be ++fixed in the future. ++ ++Some operations are not atomic, for example a crash during copy_up or ++rename will leave the filesystem in an inconsitent state. This will ++be addressed in the future. ++ ++Changes to underlying filesystems ++--------------------------------- ++ ++Offline changes, when the overlay is not mounted, are allowed to either ++the upper or the lower trees. ++ ++Changes to the underlying filesystems while part of a mounted overlay ++filesystem are not allowed. If the underlying filesystem is changed, ++the behavior of the overlay is undefined, though it will not result in ++a crash or deadlock. +diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt +index 0d04920..f06c91f 100644 +--- a/Documentation/filesystems/vfs.txt ++++ b/Documentation/filesystems/vfs.txt +@@ -364,6 +364,8 @@ struct inode_operations { + ssize_t (*listxattr) (struct dentry *, char *, size_t); + int (*removexattr) (struct dentry *, const char *); + void (*truncate_range)(struct inode *, loff_t, loff_t); ++ struct file *(*open) (struct dentry *, struct file *, ++ const struct cred *); + }; + + Again, all methods are called without any locks being held, unless +@@ -475,6 +477,12 @@ otherwise noted. + truncate_range: a method provided by the underlying filesystem to truncate a + range of blocks , i.e. punch a hole somewhere in a file. + ++ open: this is an alternative to f_op->open(), the difference is that this ++ method may return any open file, not necessarily originating from the ++ same filesystem as the one i_op->open() was called on. It may be useful ++ for stacking filesystems which want to allow native I/O directly on ++ underlying files. ++ + + The Address Space Object + ======================== +diff --git a/MAINTAINERS b/MAINTAINERS +index b362709..7ba226c 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4998,6 +4998,13 @@ F: drivers/scsi/osd/ + F: include/scsi/osd_* + F: fs/exofs/ + ++OVERLAYFS FILESYSTEM ++M: Miklos Szeredi ++L: linux-fsdevel@vger.kernel.org ++S: Supported ++F: fs/overlayfs/* ++F: Documentation/filesystems/overlayfs.txt ++ + P54 WIRELESS DRIVER + M: Christian Lamparter + L: linux-wireless@vger.kernel.org +diff --git a/fs/Kconfig b/fs/Kconfig +index f95ae3a..e0c5d43 100644 +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -67,6 +67,7 @@ source "fs/quota/Kconfig" + + source "fs/autofs4/Kconfig" + source "fs/fuse/Kconfig" ++source "fs/overlayfs/Kconfig" + + config CUSE + tristate "Character device in Userspace support" +diff --git a/fs/Makefile b/fs/Makefile +index 2fb9779..fcd9788 100644 +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -106,6 +106,7 @@ obj-$(CONFIG_QNX6FS_FS) += qnx6/ + obj-$(CONFIG_AUTOFS4_FS) += autofs4/ + obj-$(CONFIG_ADFS_FS) += adfs/ + obj-$(CONFIG_FUSE_FS) += fuse/ ++obj-$(CONFIG_OVERLAYFS_FS) += overlayfs/ + obj-$(CONFIG_UDF_FS) += udf/ + obj-$(CONFIG_SUN_OPENPROMFS) += openpromfs/ + obj-$(CONFIG_OMFS_FS) += omfs/ +diff --git a/fs/ecryptfs/main.c b/fs/ecryptfs/main.c +index 6895493..c54ea90 100644 +--- a/fs/ecryptfs/main.c ++++ b/fs/ecryptfs/main.c +@@ -544,6 +544,13 @@ static struct dentry *ecryptfs_mount(struct file_system_type *fs_type, int flags + s->s_maxbytes = path.dentry->d_sb->s_maxbytes; + s->s_blocksize = path.dentry->d_sb->s_blocksize; + s->s_magic = ECRYPTFS_SUPER_MAGIC; ++ s->s_stack_depth = path.dentry->d_sb->s_stack_depth + 1; ++ ++ rc = -EINVAL; ++ if (s->s_stack_depth > FILESYSTEM_MAX_STACK_DEPTH) { ++ printk(KERN_ERR "eCryptfs: maximum fs stacking depth exceeded\n"); ++ goto out_free; ++ } + + inode = ecryptfs_get_inode(path.dentry->d_inode, s); + rc = PTR_ERR(inode); +diff --git a/fs/namei.c b/fs/namei.c +index c427919..e172a5b 100644 +--- a/fs/namei.c ++++ b/fs/namei.c +@@ -328,6 +328,36 @@ static inline int do_inode_permission(struct inode *inode, int mask) + } + + /** ++ * inode_only_permission - check access rights to a given inode only ++ * @inode: inode to check permissions on ++ * @mask: right to check for (%MAY_READ, %MAY_WRITE, %MAY_EXEC, ...) ++ * ++ * Uses to check read/write/execute permissions on an inode directly, we do ++ * not check filesystem permissions. ++ */ ++int inode_only_permission(struct inode *inode, int mask) ++{ ++ int retval; ++ ++ /* ++ * Nobody gets write access to an immutable file. ++ */ ++ if (unlikely(mask & MAY_WRITE) && IS_IMMUTABLE(inode)) ++ return -EACCES; ++ ++ retval = do_inode_permission(inode, mask); ++ if (retval) ++ return retval; ++ ++ retval = devcgroup_inode_permission(inode, mask); ++ if (retval) ++ return retval; ++ ++ return security_inode_permission(inode, mask); ++} ++EXPORT_SYMBOL(inode_only_permission); ++ ++/** + * inode_permission - check for access rights to a given inode + * @inode: inode to check permission on + * @mask: right to check for (%MAY_READ, %MAY_WRITE, %MAY_EXEC, ...) +@@ -341,8 +371,6 @@ static inline int do_inode_permission(struct inode *inode, int mask) + */ + int inode_permission(struct inode *inode, int mask) + { +- int retval; +- + if (unlikely(mask & MAY_WRITE)) { + umode_t mode = inode->i_mode; + +@@ -352,23 +380,9 @@ int inode_permission(struct inode *inode, int mask) + if (IS_RDONLY(inode) && + (S_ISREG(mode) || S_ISDIR(mode) || S_ISLNK(mode))) + return -EROFS; +- +- /* +- * Nobody gets write access to an immutable file. +- */ +- if (IS_IMMUTABLE(inode)) +- return -EACCES; + } + +- retval = do_inode_permission(inode, mask); +- if (retval) +- return retval; +- +- retval = devcgroup_inode_permission(inode, mask); +- if (retval) +- return retval; +- +- return security_inode_permission(inode, mask); ++ return inode_only_permission(inode, mask); + } + + /** +diff --git a/fs/namespace.c b/fs/namespace.c +index e608199..2551ec0 100644 +--- a/fs/namespace.c ++++ b/fs/namespace.c +@@ -1325,6 +1325,24 @@ void drop_collected_mounts(struct vfsmount *mnt) + release_mounts(&umount_list); + } + ++struct vfsmount *clone_private_mount(struct path *path) ++{ ++ struct mount *old_mnt = real_mount(path->mnt); ++ struct mount *new_mnt; ++ ++ if (IS_MNT_UNBINDABLE(old_mnt)) ++ return ERR_PTR(-EINVAL); ++ ++ down_read(&namespace_sem); ++ new_mnt = clone_mnt(old_mnt, path->dentry, CL_PRIVATE); ++ up_read(&namespace_sem); ++ if (!new_mnt) ++ return ERR_PTR(-ENOMEM); ++ ++ return &new_mnt->mnt; ++} ++EXPORT_SYMBOL_GPL(clone_private_mount); ++ + int iterate_mounts(int (*f)(struct vfsmount *, void *), void *arg, + struct vfsmount *root) + { +diff --git a/fs/open.c b/fs/open.c +index 5720854..3e132ba 100644 +--- a/fs/open.c ++++ b/fs/open.c +@@ -644,24 +644,24 @@ static inline int __get_file_write_access(struct inode *inode, + return error; + } + +-static struct file *__dentry_open(struct dentry *dentry, struct vfsmount *mnt, +- struct file *f, +- int (*open)(struct inode *, struct file *), +- const struct cred *cred) ++static struct file *__dentry_open(struct path *path, struct file *f, ++ int (*open)(struct inode *, struct file *), ++ const struct cred *cred) + { + static const struct file_operations empty_fops = {}; + struct inode *inode; + int error; + ++ path_get(path); + f->f_mode = OPEN_FMODE(f->f_flags) | FMODE_LSEEK | + FMODE_PREAD | FMODE_PWRITE; + + if (unlikely(f->f_flags & O_PATH)) + f->f_mode = FMODE_PATH; + +- inode = dentry->d_inode; ++ inode = path->dentry->d_inode; + if (f->f_mode & FMODE_WRITE) { +- error = __get_file_write_access(inode, mnt); ++ error = __get_file_write_access(inode, path->mnt); + if (error) + goto cleanup_file; + if (!special_file(inode->i_mode)) +@@ -669,8 +669,7 @@ static struct file *__dentry_open(struct dentry *dentry, struct vfsmount *mnt, + } + + f->f_mapping = inode->i_mapping; +- f->f_path.dentry = dentry; +- f->f_path.mnt = mnt; ++ f->f_path = *path; + f->f_pos = 0; + file_sb_list_add(f, inode->i_sb); + +@@ -727,7 +726,7 @@ cleanup_all: + * here, so just reset the state. + */ + file_reset_write(f); +- mnt_drop_write(mnt); ++ mnt_drop_write(path->mnt); + } + } + file_sb_list_del(f); +@@ -735,8 +734,7 @@ cleanup_all: + f->f_path.mnt = NULL; + cleanup_file: + put_filp(f); +- dput(dentry); +- mntput(mnt); ++ path_put(path); + return ERR_PTR(error); + } + +@@ -762,14 +760,14 @@ cleanup_file: + struct file *lookup_instantiate_filp(struct nameidata *nd, struct dentry *dentry, + int (*open)(struct inode *, struct file *)) + { ++ struct path path = { .dentry = dentry, .mnt = nd->path.mnt }; + const struct cred *cred = current_cred(); + + if (IS_ERR(nd->intent.open.file)) + goto out; + if (IS_ERR(dentry)) + goto out_err; +- nd->intent.open.file = __dentry_open(dget(dentry), mntget(nd->path.mnt), +- nd->intent.open.file, ++ nd->intent.open.file = __dentry_open(&path, nd->intent.open.file, + open, cred); + out: + return nd->intent.open.file; +@@ -797,11 +795,9 @@ struct file *nameidata_to_filp(struct nameidata *nd) + nd->intent.open.file = NULL; + + /* Has the filesystem initialised the file for us? */ +- if (filp->f_path.dentry == NULL) { +- path_get(&nd->path); +- filp = __dentry_open(nd->path.dentry, nd->path.mnt, filp, +- NULL, cred); +- } ++ if (filp->f_path.dentry == NULL) ++ filp = vfs_open(&nd->path, filp, cred); ++ + return filp; + } + +@@ -812,27 +808,48 @@ struct file *nameidata_to_filp(struct nameidata *nd) + struct file *dentry_open(struct dentry *dentry, struct vfsmount *mnt, int flags, + const struct cred *cred) + { +- int error; + struct file *f; ++ struct file *ret; ++ struct path path = { .dentry = dentry, .mnt = mnt }; + + validate_creds(cred); + + /* We must always pass in a valid mount pointer. */ + BUG_ON(!mnt); + +- error = -ENFILE; ++ ret = ERR_PTR(-ENFILE); + f = get_empty_filp(); +- if (f == NULL) { +- dput(dentry); +- mntput(mnt); +- return ERR_PTR(error); ++ if (f != NULL) { ++ f->f_flags = flags; ++ ret = vfs_open(&path, f, cred); + } ++ path_put(&path); + +- f->f_flags = flags; +- return __dentry_open(dentry, mnt, f, NULL, cred); ++ return ret; + } + EXPORT_SYMBOL(dentry_open); + ++/** ++ * vfs_open - open the file at the given path ++ * @path: path to open ++ * @filp: newly allocated file with f_flag initialized ++ * @cred: credentials to use ++ * ++ * Open the file. If successful, the returned file will have acquired ++ * an additional reference for path. ++ */ ++struct file *vfs_open(struct path *path, struct file *filp, ++ const struct cred *cred) ++{ ++ struct inode *inode = path->dentry->d_inode; ++ ++ if (inode->i_op->open) ++ return inode->i_op->open(path->dentry, filp, cred); ++ else ++ return __dentry_open(path, filp, NULL, cred); ++} ++EXPORT_SYMBOL(vfs_open); ++ + static void __put_unused_fd(struct files_struct *files, unsigned int fd) + { + struct fdtable *fdt = files_fdtable(files); +diff --git a/fs/overlayfs/Kconfig b/fs/overlayfs/Kconfig +new file mode 100644 +index 0000000..c4517da +--- /dev/null ++++ b/fs/overlayfs/Kconfig +@@ -0,0 +1,4 @@ ++config OVERLAYFS_FS ++ tristate "Overlay filesystem support" ++ help ++ Add support for overlay filesystem. +diff --git a/fs/overlayfs/Makefile b/fs/overlayfs/Makefile +new file mode 100644 +index 0000000..8f91889 +--- /dev/null ++++ b/fs/overlayfs/Makefile +@@ -0,0 +1,7 @@ ++# ++# Makefile for the overlay filesystem. ++# ++ ++obj-$(CONFIG_OVERLAYFS_FS) += overlayfs.o ++ ++overlayfs-objs := super.o inode.o dir.o readdir.o copy_up.o +diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c +new file mode 100644 +index 0000000..87dbeee +--- /dev/null ++++ b/fs/overlayfs/copy_up.c +@@ -0,0 +1,385 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "overlayfs.h" ++ ++#define OVL_COPY_UP_CHUNK_SIZE (1 << 20) ++ ++static int ovl_copy_up_xattr(struct dentry *old, struct dentry *new) ++{ ++ ssize_t list_size, size; ++ char *buf, *name, *value; ++ int error; ++ ++ if (!old->d_inode->i_op->getxattr || ++ !new->d_inode->i_op->getxattr) ++ return 0; ++ ++ list_size = vfs_listxattr(old, NULL, 0); ++ if (list_size <= 0) { ++ if (list_size == -EOPNOTSUPP) ++ return 0; ++ return list_size; ++ } ++ ++ buf = kzalloc(list_size, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ error = -ENOMEM; ++ value = kmalloc(XATTR_SIZE_MAX, GFP_KERNEL); ++ if (!value) ++ goto out; ++ ++ list_size = vfs_listxattr(old, buf, list_size); ++ if (list_size <= 0) { ++ error = list_size; ++ goto out_free_value; ++ } ++ ++ for (name = buf; name < (buf + list_size); name += strlen(name) + 1) { ++ size = vfs_getxattr(old, name, value, XATTR_SIZE_MAX); ++ if (size <= 0) { ++ error = size; ++ goto out_free_value; ++ } ++ error = vfs_setxattr(new, name, value, size, 0); ++ if (error) ++ goto out_free_value; ++ } ++ ++out_free_value: ++ kfree(value); ++out: ++ kfree(buf); ++ return error; ++} ++ ++static int ovl_copy_up_data(struct path *old, struct path *new, loff_t len) ++{ ++ struct file *old_file; ++ struct file *new_file; ++ int error = 0; ++ ++ if (len == 0) ++ return 0; ++ ++ old_file = ovl_path_open(old, O_RDONLY); ++ if (IS_ERR(old_file)) ++ return PTR_ERR(old_file); ++ ++ new_file = ovl_path_open(new, O_WRONLY); ++ if (IS_ERR(new_file)) { ++ error = PTR_ERR(new_file); ++ goto out_fput; ++ } ++ ++ /* FIXME: copy up sparse files efficiently */ ++ while (len) { ++ loff_t offset = new_file->f_pos; ++ size_t this_len = OVL_COPY_UP_CHUNK_SIZE; ++ long bytes; ++ ++ if (len < this_len) ++ this_len = len; ++ ++ if (signal_pending_state(TASK_KILLABLE, current)) { ++ error = -EINTR; ++ break; ++ } ++ ++ bytes = do_splice_direct(old_file, &offset, new_file, this_len, ++ SPLICE_F_MOVE); ++ if (bytes <= 0) { ++ error = bytes; ++ break; ++ } ++ ++ len -= bytes; ++ } ++ ++ fput(new_file); ++out_fput: ++ fput(old_file); ++ return error; ++} ++ ++static char *ovl_read_symlink(struct dentry *realdentry) ++{ ++ int res; ++ char *buf; ++ struct inode *inode = realdentry->d_inode; ++ mm_segment_t old_fs; ++ ++ res = -EINVAL; ++ if (!inode->i_op->readlink) ++ goto err; ++ ++ res = -ENOMEM; ++ buf = (char *) __get_free_page(GFP_KERNEL); ++ if (!buf) ++ goto err; ++ ++ old_fs = get_fs(); ++ set_fs(get_ds()); ++ /* The cast to a user pointer is valid due to the set_fs() */ ++ res = inode->i_op->readlink(realdentry, ++ (char __user *)buf, PAGE_SIZE - 1); ++ set_fs(old_fs); ++ if (res < 0) { ++ free_page((unsigned long) buf); ++ goto err; ++ } ++ buf[res] = '\0'; ++ ++ return buf; ++ ++err: ++ return ERR_PTR(res); ++} ++ ++static int ovl_set_timestamps(struct dentry *upperdentry, struct kstat *stat) ++{ ++ struct iattr attr = { ++ .ia_valid = ++ ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET, ++ .ia_atime = stat->atime, ++ .ia_mtime = stat->mtime, ++ }; ++ ++ return notify_change(upperdentry, &attr); ++} ++ ++static int ovl_set_mode(struct dentry *upperdentry, umode_t mode) ++{ ++ struct iattr attr = { ++ .ia_valid = ATTR_MODE, ++ .ia_mode = mode, ++ }; ++ ++ return notify_change(upperdentry, &attr); ++} ++ ++static int ovl_copy_up_locked(struct dentry *upperdir, struct dentry *dentry, ++ struct path *lowerpath, struct kstat *stat, ++ const char *link) ++{ ++ int err; ++ struct path newpath; ++ umode_t mode = stat->mode; ++ ++ /* Can't properly set mode on creation because of the umask */ ++ stat->mode &= S_IFMT; ++ ++ ovl_path_upper(dentry, &newpath); ++ WARN_ON(newpath.dentry); ++ newpath.dentry = ovl_upper_create(upperdir, dentry, stat, link); ++ if (IS_ERR(newpath.dentry)) ++ return PTR_ERR(newpath.dentry); ++ ++ if (S_ISREG(stat->mode)) { ++ err = ovl_copy_up_data(lowerpath, &newpath, stat->size); ++ if (err) ++ goto err_remove; ++ } ++ ++ err = ovl_copy_up_xattr(lowerpath->dentry, newpath.dentry); ++ if (err) ++ goto err_remove; ++ ++ mutex_lock(&newpath.dentry->d_inode->i_mutex); ++ if (!S_ISLNK(stat->mode)) ++ err = ovl_set_mode(newpath.dentry, mode); ++ if (!err) ++ err = ovl_set_timestamps(newpath.dentry, stat); ++ mutex_unlock(&newpath.dentry->d_inode->i_mutex); ++ if (err) ++ goto err_remove; ++ ++ ovl_dentry_update(dentry, newpath.dentry); ++ ++ /* ++ * Easiest way to get rid of the lower dentry reference is to ++ * drop this dentry. This is neither needed nor possible for ++ * directories. ++ */ ++ if (!S_ISDIR(stat->mode)) ++ d_drop(dentry); ++ ++ return 0; ++ ++err_remove: ++ if (S_ISDIR(stat->mode)) ++ vfs_rmdir(upperdir->d_inode, newpath.dentry); ++ else ++ vfs_unlink(upperdir->d_inode, newpath.dentry); ++ ++ dput(newpath.dentry); ++ ++ return err; ++} ++ ++/* ++ * Copy up a single dentry ++ * ++ * Directory renames only allowed on "pure upper" (already created on ++ * upper filesystem, never copied up). Directories which are on lower or ++ * are merged may not be renamed. For these -EXDEV is returned and ++ * userspace has to deal with it. This means, when copying up a ++ * directory we can rely on it and ancestors being stable. ++ * ++ * Non-directory renames start with copy up of source if necessary. The ++ * actual rename will only proceed once the copy up was successful. Copy ++ * up uses upper parent i_mutex for exclusion. Since rename can change ++ * d_parent it is possible that the copy up will lock the old parent. At ++ * that point the file will have already been copied up anyway. ++ */ ++static int ovl_copy_up_one(struct dentry *parent, struct dentry *dentry, ++ struct path *lowerpath, struct kstat *stat) ++{ ++ int err; ++ struct kstat pstat; ++ struct path parentpath; ++ struct dentry *upperdir; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ char *link = NULL; ++ ++ ovl_path_upper(parent, &parentpath); ++ upperdir = parentpath.dentry; ++ ++ err = vfs_getattr(parentpath.mnt, parentpath.dentry, &pstat); ++ if (err) ++ return err; ++ ++ if (S_ISLNK(stat->mode)) { ++ link = ovl_read_symlink(lowerpath->dentry); ++ if (IS_ERR(link)) ++ return PTR_ERR(link); ++ } ++ ++ err = -ENOMEM; ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ goto out_free_link; ++ ++ override_cred->fsuid = stat->uid; ++ override_cred->fsgid = stat->gid; ++ /* ++ * CAP_SYS_ADMIN for copying up extended attributes ++ * CAP_DAC_OVERRIDE for create ++ * CAP_FOWNER for chmod, timestamp update ++ * CAP_FSETID for chmod ++ * CAP_MKNOD for mknod ++ */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); ++ cap_raise(override_cred->cap_effective, CAP_FOWNER); ++ cap_raise(override_cred->cap_effective, CAP_FSETID); ++ cap_raise(override_cred->cap_effective, CAP_MKNOD); ++ old_cred = override_creds(override_cred); ++ ++ mutex_lock_nested(&upperdir->d_inode->i_mutex, I_MUTEX_PARENT); ++ if (ovl_path_type(dentry) != OVL_PATH_LOWER) { ++ err = 0; ++ } else { ++ err = ovl_copy_up_locked(upperdir, dentry, lowerpath, ++ stat, link); ++ if (!err) { ++ /* Restore timestamps on parent (best effort) */ ++ ovl_set_timestamps(upperdir, &pstat); ++ } ++ } ++ ++ mutex_unlock(&upperdir->d_inode->i_mutex); ++ ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ ++out_free_link: ++ if (link) ++ free_page((unsigned long) link); ++ ++ return err; ++} ++ ++int ovl_copy_up(struct dentry *dentry) ++{ ++ int err; ++ ++ err = 0; ++ while (!err) { ++ struct dentry *next; ++ struct dentry *parent; ++ struct path lowerpath; ++ struct kstat stat; ++ enum ovl_path_type type = ovl_path_type(dentry); ++ ++ if (type != OVL_PATH_LOWER) ++ break; ++ ++ next = dget(dentry); ++ /* find the topmost dentry not yet copied up */ ++ for (;;) { ++ parent = dget_parent(next); ++ ++ type = ovl_path_type(parent); ++ if (type != OVL_PATH_LOWER) ++ break; ++ ++ dput(next); ++ next = parent; ++ } ++ ++ ovl_path_lower(next, &lowerpath); ++ err = vfs_getattr(lowerpath.mnt, lowerpath.dentry, &stat); ++ if (!err) ++ err = ovl_copy_up_one(parent, next, &lowerpath, &stat); ++ ++ dput(parent); ++ dput(next); ++ } ++ ++ return err; ++} ++ ++/* Optimize by not copying up the file first and truncating later */ ++int ovl_copy_up_truncate(struct dentry *dentry, loff_t size) ++{ ++ int err; ++ struct kstat stat; ++ struct path lowerpath; ++ struct dentry *parent = dget_parent(dentry); ++ ++ err = ovl_copy_up(parent); ++ if (err) ++ goto out_dput_parent; ++ ++ ovl_path_lower(dentry, &lowerpath); ++ err = vfs_getattr(lowerpath.mnt, lowerpath.dentry, &stat); ++ if (err) ++ goto out_dput_parent; ++ ++ if (size < stat.size) ++ stat.size = size; ++ ++ err = ovl_copy_up_one(parent, dentry, &lowerpath, &stat); ++ ++out_dput_parent: ++ dput(parent); ++ return err; ++} +diff --git a/fs/overlayfs/dir.c b/fs/overlayfs/dir.c +new file mode 100644 +index 0000000..c914c97 +--- /dev/null ++++ b/fs/overlayfs/dir.c +@@ -0,0 +1,602 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "overlayfs.h" ++ ++static const char *ovl_whiteout_symlink = "(overlay-whiteout)"; ++ ++static int ovl_whiteout(struct dentry *upperdir, struct dentry *dentry) ++{ ++ int err; ++ struct dentry *newdentry; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ /* FIXME: recheck lower dentry to see if whiteout is really needed */ ++ ++ err = -ENOMEM; ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ goto out; ++ ++ /* ++ * CAP_SYS_ADMIN for setxattr ++ * CAP_DAC_OVERRIDE for symlink creation ++ * CAP_FOWNER for unlink in sticky directory ++ */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); ++ cap_raise(override_cred->cap_effective, CAP_FOWNER); ++ override_cred->fsuid = 0; ++ override_cred->fsgid = 0; ++ old_cred = override_creds(override_cred); ++ ++ newdentry = lookup_one_len(dentry->d_name.name, upperdir, ++ dentry->d_name.len); ++ err = PTR_ERR(newdentry); ++ if (IS_ERR(newdentry)) ++ goto out_put_cred; ++ ++ /* Just been removed within the same locked region */ ++ WARN_ON(newdentry->d_inode); ++ ++ err = vfs_symlink(upperdir->d_inode, newdentry, ovl_whiteout_symlink); ++ if (err) ++ goto out_dput; ++ ++ ovl_dentry_version_inc(dentry->d_parent); ++ ++ err = vfs_setxattr(newdentry, ovl_whiteout_xattr, "y", 1, 0); ++ if (err) ++ vfs_unlink(upperdir->d_inode, newdentry); ++ ++out_dput: ++ dput(newdentry); ++out_put_cred: ++ revert_creds(old_cred); ++ put_cred(override_cred); ++out: ++ if (err) { ++ /* ++ * There's no way to recover from failure to whiteout. ++ * What should we do? Log a big fat error and... ? ++ */ ++ printk(KERN_ERR "overlayfs: ERROR - failed to whiteout '%s'\n", ++ dentry->d_name.name); ++ } ++ ++ return err; ++} ++ ++static struct dentry *ovl_lookup_create(struct dentry *upperdir, ++ struct dentry *template) ++{ ++ int err; ++ struct dentry *newdentry; ++ struct qstr *name = &template->d_name; ++ ++ newdentry = lookup_one_len(name->name, upperdir, name->len); ++ if (IS_ERR(newdentry)) ++ return newdentry; ++ ++ if (newdentry->d_inode) { ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ /* No need to check whiteout if lower parent is non-existent */ ++ err = -EEXIST; ++ if (!ovl_dentry_lower(template->d_parent)) ++ goto out_dput; ++ ++ if (!S_ISLNK(newdentry->d_inode->i_mode)) ++ goto out_dput; ++ ++ err = -ENOMEM; ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ goto out_dput; ++ ++ /* ++ * CAP_SYS_ADMIN for getxattr ++ * CAP_FOWNER for unlink in sticky directory ++ */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ cap_raise(override_cred->cap_effective, CAP_FOWNER); ++ old_cred = override_creds(override_cred); ++ ++ err = -EEXIST; ++ if (ovl_is_whiteout(newdentry)) ++ err = vfs_unlink(upperdir->d_inode, newdentry); ++ ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ if (err) ++ goto out_dput; ++ ++ dput(newdentry); ++ newdentry = lookup_one_len(name->name, upperdir, name->len); ++ if (IS_ERR(newdentry)) { ++ ovl_whiteout(upperdir, template); ++ return newdentry; ++ } ++ ++ /* ++ * Whiteout just been successfully removed, parent ++ * i_mutex is still held, there's no way the lookup ++ * could return positive. ++ */ ++ WARN_ON(newdentry->d_inode); ++ } ++ ++ return newdentry; ++ ++out_dput: ++ dput(newdentry); ++ return ERR_PTR(err); ++} ++ ++struct dentry *ovl_upper_create(struct dentry *upperdir, struct dentry *dentry, ++ struct kstat *stat, const char *link) ++{ ++ int err; ++ struct dentry *newdentry; ++ struct inode *dir = upperdir->d_inode; ++ ++ newdentry = ovl_lookup_create(upperdir, dentry); ++ if (IS_ERR(newdentry)) ++ goto out; ++ ++ switch (stat->mode & S_IFMT) { ++ case S_IFREG: ++ err = vfs_create(dir, newdentry, stat->mode, NULL); ++ break; ++ ++ case S_IFDIR: ++ err = vfs_mkdir(dir, newdentry, stat->mode); ++ break; ++ ++ case S_IFCHR: ++ case S_IFBLK: ++ case S_IFIFO: ++ case S_IFSOCK: ++ err = vfs_mknod(dir, newdentry, stat->mode, stat->rdev); ++ break; ++ ++ case S_IFLNK: ++ err = vfs_symlink(dir, newdentry, link); ++ break; ++ ++ default: ++ err = -EPERM; ++ } ++ if (err) { ++ if (ovl_dentry_is_opaque(dentry)) ++ ovl_whiteout(upperdir, dentry); ++ dput(newdentry); ++ newdentry = ERR_PTR(err); ++ } else if (WARN_ON(!newdentry->d_inode)) { ++ /* ++ * Not quite sure if non-instantiated dentry is legal or not. ++ * VFS doesn't seem to care so check and warn here. ++ */ ++ dput(newdentry); ++ newdentry = ERR_PTR(-ENOENT); ++ } ++ ++out: ++ return newdentry; ++ ++} ++ ++static int ovl_set_opaque(struct dentry *upperdentry) ++{ ++ int err; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ return -ENOMEM; ++ ++ /* CAP_SYS_ADMIN for setxattr of "trusted" namespace */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ old_cred = override_creds(override_cred); ++ err = vfs_setxattr(upperdentry, ovl_opaque_xattr, "y", 1, 0); ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ ++ return err; ++} ++ ++static int ovl_remove_opaque(struct dentry *upperdentry) ++{ ++ int err; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ return -ENOMEM; ++ ++ /* CAP_SYS_ADMIN for removexattr of "trusted" namespace */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ old_cred = override_creds(override_cred); ++ err = vfs_removexattr(upperdentry, ovl_opaque_xattr); ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ ++ return err; ++} ++ ++static int ovl_dir_getattr(struct vfsmount *mnt, struct dentry *dentry, ++ struct kstat *stat) ++{ ++ int err; ++ enum ovl_path_type type; ++ struct path realpath; ++ ++ type = ovl_path_real(dentry, &realpath); ++ err = vfs_getattr(realpath.mnt, realpath.dentry, stat); ++ if (err) ++ return err; ++ ++ stat->dev = dentry->d_sb->s_dev; ++ stat->ino = dentry->d_inode->i_ino; ++ ++ /* ++ * It's probably not worth it to count subdirs to get the ++ * correct link count. nlink=1 seems to pacify 'find' and ++ * other utilities. ++ */ ++ if (type == OVL_PATH_MERGE) ++ stat->nlink = 1; ++ ++ return 0; ++} ++ ++static int ovl_create_object(struct dentry *dentry, int mode, dev_t rdev, ++ const char *link) ++{ ++ int err; ++ struct dentry *newdentry; ++ struct dentry *upperdir; ++ struct inode *inode; ++ struct kstat stat = { ++ .mode = mode, ++ .rdev = rdev, ++ }; ++ ++ err = -ENOMEM; ++ inode = ovl_new_inode(dentry->d_sb, mode, dentry->d_fsdata); ++ if (!inode) ++ goto out; ++ ++ err = ovl_copy_up(dentry->d_parent); ++ if (err) ++ goto out_iput; ++ ++ upperdir = ovl_dentry_upper(dentry->d_parent); ++ mutex_lock_nested(&upperdir->d_inode->i_mutex, I_MUTEX_PARENT); ++ ++ newdentry = ovl_upper_create(upperdir, dentry, &stat, link); ++ err = PTR_ERR(newdentry); ++ if (IS_ERR(newdentry)) ++ goto out_unlock; ++ ++ ovl_dentry_version_inc(dentry->d_parent); ++ if (ovl_dentry_is_opaque(dentry) && S_ISDIR(mode)) { ++ err = ovl_set_opaque(newdentry); ++ if (err) { ++ vfs_rmdir(upperdir->d_inode, newdentry); ++ ovl_whiteout(upperdir, dentry); ++ goto out_dput; ++ } ++ } ++ ovl_dentry_update(dentry, newdentry); ++ d_instantiate(dentry, inode); ++ inode = NULL; ++ newdentry = NULL; ++ err = 0; ++ ++out_dput: ++ dput(newdentry); ++out_unlock: ++ mutex_unlock(&upperdir->d_inode->i_mutex); ++out_iput: ++ iput(inode); ++out: ++ return err; ++} ++ ++static int ovl_create(struct inode *dir, struct dentry *dentry, umode_t mode, ++ struct nameidata *nd) ++{ ++ return ovl_create_object(dentry, (mode & 07777) | S_IFREG, 0, NULL); ++} ++ ++static int ovl_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) ++{ ++ return ovl_create_object(dentry, (mode & 07777) | S_IFDIR, 0, NULL); ++} ++ ++static int ovl_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, ++ dev_t rdev) ++{ ++ return ovl_create_object(dentry, mode, rdev, NULL); ++} ++ ++static int ovl_symlink(struct inode *dir, struct dentry *dentry, ++ const char *link) ++{ ++ return ovl_create_object(dentry, S_IFLNK, 0, link); ++} ++ ++static int ovl_do_remove(struct dentry *dentry, bool is_dir) ++{ ++ int err; ++ enum ovl_path_type type; ++ struct path realpath; ++ struct dentry *upperdir; ++ ++ err = ovl_copy_up(dentry->d_parent); ++ if (err) ++ return err; ++ ++ upperdir = ovl_dentry_upper(dentry->d_parent); ++ mutex_lock_nested(&upperdir->d_inode->i_mutex, I_MUTEX_PARENT); ++ type = ovl_path_real(dentry, &realpath); ++ if (type != OVL_PATH_LOWER) { ++ err = -ESTALE; ++ if (realpath.dentry->d_parent != upperdir) ++ goto out_d_drop; ++ ++ /* FIXME: create whiteout up front and rename to target */ ++ ++ if (is_dir) ++ err = vfs_rmdir(upperdir->d_inode, realpath.dentry); ++ else ++ err = vfs_unlink(upperdir->d_inode, realpath.dentry); ++ if (err) ++ goto out_d_drop; ++ ++ ovl_dentry_version_inc(dentry->d_parent); ++ } ++ ++ if (type != OVL_PATH_UPPER || ovl_dentry_is_opaque(dentry)) ++ err = ovl_whiteout(upperdir, dentry); ++ ++ /* ++ * Keeping this dentry hashed would mean having to release ++ * upperpath/lowerpath, which could only be done if we are the ++ * sole user of this dentry. Too tricky... Just unhash for ++ * now. ++ */ ++out_d_drop: ++ d_drop(dentry); ++ mutex_unlock(&upperdir->d_inode->i_mutex); ++ ++ return err; ++} ++ ++static int ovl_unlink(struct inode *dir, struct dentry *dentry) ++{ ++ return ovl_do_remove(dentry, false); ++} ++ ++ ++static int ovl_rmdir(struct inode *dir, struct dentry *dentry) ++{ ++ int err; ++ enum ovl_path_type type; ++ ++ type = ovl_path_type(dentry); ++ if (type != OVL_PATH_UPPER) { ++ err = ovl_check_empty_and_clear(dentry, type); ++ if (err) ++ return err; ++ } ++ ++ return ovl_do_remove(dentry, true); ++} ++ ++static int ovl_link(struct dentry *old, struct inode *newdir, ++ struct dentry *new) ++{ ++ int err; ++ struct dentry *olddentry; ++ struct dentry *newdentry; ++ struct dentry *upperdir; ++ struct inode *newinode; ++ ++ err = ovl_copy_up(old); ++ if (err) ++ goto out; ++ ++ err = ovl_copy_up(new->d_parent); ++ if (err) ++ goto out; ++ ++ upperdir = ovl_dentry_upper(new->d_parent); ++ mutex_lock_nested(&upperdir->d_inode->i_mutex, I_MUTEX_PARENT); ++ newdentry = ovl_lookup_create(upperdir, new); ++ err = PTR_ERR(newdentry); ++ if (IS_ERR(newdentry)) ++ goto out_unlock; ++ ++ olddentry = ovl_dentry_upper(old); ++ err = vfs_link(olddentry, upperdir->d_inode, newdentry); ++ if (!err) { ++ if (WARN_ON(!newdentry->d_inode)) { ++ dput(newdentry); ++ err = -ENOENT; ++ goto out_unlock; ++ } ++ newinode = ovl_new_inode(old->d_sb, newdentry->d_inode->i_mode, ++ new->d_fsdata); ++ if (!newinode) ++ goto link_fail; ++ ++ ovl_dentry_version_inc(new->d_parent); ++ ovl_dentry_update(new, newdentry); ++ ++ d_instantiate(new, newinode); ++ } else { ++link_fail: ++ if (ovl_dentry_is_opaque(new)) ++ ovl_whiteout(upperdir, new); ++ dput(newdentry); ++ } ++out_unlock: ++ mutex_unlock(&upperdir->d_inode->i_mutex); ++out: ++ return err; ++ ++} ++ ++static int ovl_rename(struct inode *olddir, struct dentry *old, ++ struct inode *newdir, struct dentry *new) ++{ ++ int err; ++ enum ovl_path_type old_type; ++ enum ovl_path_type new_type; ++ struct dentry *old_upperdir; ++ struct dentry *new_upperdir; ++ struct dentry *olddentry; ++ struct dentry *newdentry; ++ struct dentry *trap; ++ bool old_opaque; ++ bool new_opaque; ++ bool new_create = false; ++ bool is_dir = S_ISDIR(old->d_inode->i_mode); ++ ++ /* Don't copy up directory trees */ ++ old_type = ovl_path_type(old); ++ if (old_type != OVL_PATH_UPPER && is_dir) ++ return -EXDEV; ++ ++ if (new->d_inode) { ++ new_type = ovl_path_type(new); ++ ++ if (new_type == OVL_PATH_LOWER && old_type == OVL_PATH_LOWER) { ++ if (ovl_dentry_lower(old)->d_inode == ++ ovl_dentry_lower(new)->d_inode) ++ return 0; ++ } ++ if (new_type != OVL_PATH_LOWER && old_type != OVL_PATH_LOWER) { ++ if (ovl_dentry_upper(old)->d_inode == ++ ovl_dentry_upper(new)->d_inode) ++ return 0; ++ } ++ ++ if (new_type != OVL_PATH_UPPER && ++ S_ISDIR(new->d_inode->i_mode)) { ++ err = ovl_check_empty_and_clear(new, new_type); ++ if (err) ++ return err; ++ } ++ } else { ++ new_type = OVL_PATH_UPPER; ++ } ++ ++ err = ovl_copy_up(old); ++ if (err) ++ return err; ++ ++ err = ovl_copy_up(new->d_parent); ++ if (err) ++ return err; ++ ++ old_upperdir = ovl_dentry_upper(old->d_parent); ++ new_upperdir = ovl_dentry_upper(new->d_parent); ++ ++ trap = lock_rename(new_upperdir, old_upperdir); ++ ++ olddentry = ovl_dentry_upper(old); ++ newdentry = ovl_dentry_upper(new); ++ if (newdentry) { ++ dget(newdentry); ++ } else { ++ new_create = true; ++ newdentry = ovl_lookup_create(new_upperdir, new); ++ err = PTR_ERR(newdentry); ++ if (IS_ERR(newdentry)) ++ goto out_unlock; ++ } ++ ++ err = -ESTALE; ++ if (olddentry->d_parent != old_upperdir) ++ goto out_dput; ++ if (newdentry->d_parent != new_upperdir) ++ goto out_dput; ++ if (olddentry == trap) ++ goto out_dput; ++ if (newdentry == trap) ++ goto out_dput; ++ ++ old_opaque = ovl_dentry_is_opaque(old); ++ new_opaque = ovl_dentry_is_opaque(new) || new_type != OVL_PATH_UPPER; ++ ++ if (is_dir && !old_opaque && new_opaque) { ++ err = ovl_set_opaque(olddentry); ++ if (err) ++ goto out_dput; ++ } ++ ++ err = vfs_rename(old_upperdir->d_inode, olddentry, ++ new_upperdir->d_inode, newdentry); ++ ++ if (err) { ++ if (new_create && ovl_dentry_is_opaque(new)) ++ ovl_whiteout(new_upperdir, new); ++ if (is_dir && !old_opaque && new_opaque) ++ ovl_remove_opaque(olddentry); ++ goto out_dput; ++ } ++ ++ if (old_type != OVL_PATH_UPPER || old_opaque) ++ err = ovl_whiteout(old_upperdir, old); ++ if (is_dir && old_opaque && !new_opaque) ++ ovl_remove_opaque(olddentry); ++ ++ if (old_opaque != new_opaque) ++ ovl_dentry_set_opaque(old, new_opaque); ++ ++ ovl_dentry_version_inc(old->d_parent); ++ ovl_dentry_version_inc(new->d_parent); ++ ++out_dput: ++ dput(newdentry); ++out_unlock: ++ unlock_rename(new_upperdir, old_upperdir); ++ return err; ++} ++ ++const struct inode_operations ovl_dir_inode_operations = { ++ .lookup = ovl_lookup, ++ .mkdir = ovl_mkdir, ++ .symlink = ovl_symlink, ++ .unlink = ovl_unlink, ++ .rmdir = ovl_rmdir, ++ .rename = ovl_rename, ++ .link = ovl_link, ++ .setattr = ovl_setattr, ++ .create = ovl_create, ++ .mknod = ovl_mknod, ++ .permission = ovl_permission, ++ .getattr = ovl_dir_getattr, ++ .setxattr = ovl_setxattr, ++ .getxattr = ovl_getxattr, ++ .listxattr = ovl_listxattr, ++ .removexattr = ovl_removexattr, ++}; +diff --git a/fs/overlayfs/inode.c b/fs/overlayfs/inode.c +new file mode 100644 +index 0000000..1a8e232 +--- /dev/null ++++ b/fs/overlayfs/inode.c +@@ -0,0 +1,375 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include "overlayfs.h" ++ ++int ovl_setattr(struct dentry *dentry, struct iattr *attr) ++{ ++ struct dentry *upperdentry; ++ int err; ++ ++ if ((attr->ia_valid & ATTR_SIZE) && !ovl_dentry_upper(dentry)) ++ err = ovl_copy_up_truncate(dentry, attr->ia_size); ++ else ++ err = ovl_copy_up(dentry); ++ if (err) ++ return err; ++ ++ upperdentry = ovl_dentry_upper(dentry); ++ ++ if (attr->ia_valid & (ATTR_KILL_SUID|ATTR_KILL_SGID)) ++ attr->ia_valid &= ~ATTR_MODE; ++ ++ mutex_lock(&upperdentry->d_inode->i_mutex); ++ err = notify_change(upperdentry, attr); ++ mutex_unlock(&upperdentry->d_inode->i_mutex); ++ ++ return err; ++} ++ ++static int ovl_getattr(struct vfsmount *mnt, struct dentry *dentry, ++ struct kstat *stat) ++{ ++ struct path realpath; ++ ++ ovl_path_real(dentry, &realpath); ++ return vfs_getattr(realpath.mnt, realpath.dentry, stat); ++} ++ ++int ovl_permission(struct inode *inode, int mask) ++{ ++ struct ovl_entry *oe; ++ struct dentry *alias = NULL; ++ struct inode *realinode; ++ struct dentry *realdentry; ++ bool is_upper; ++ int err; ++ ++ if (S_ISDIR(inode->i_mode)) { ++ oe = inode->i_private; ++ } else if (mask & MAY_NOT_BLOCK) { ++ return -ECHILD; ++ } else { ++ /* ++ * For non-directories find an alias and get the info ++ * from there. ++ */ ++ spin_lock(&inode->i_lock); ++ if (WARN_ON(list_empty(&inode->i_dentry))) { ++ spin_unlock(&inode->i_lock); ++ return -ENOENT; ++ } ++ alias = list_entry(inode->i_dentry.next, ++ struct dentry, d_alias); ++ dget(alias); ++ spin_unlock(&inode->i_lock); ++ oe = alias->d_fsdata; ++ } ++ ++ realdentry = ovl_entry_real(oe, &is_upper); ++ ++ /* Careful in RCU walk mode */ ++ realinode = ACCESS_ONCE(realdentry->d_inode); ++ if (!realinode) { ++ WARN_ON(!(mask & MAY_NOT_BLOCK)); ++ err = -ENOENT; ++ goto out_dput; ++ } ++ ++ if (mask & MAY_WRITE) { ++ umode_t mode = realinode->i_mode; ++ ++ /* ++ * Writes will always be redirected to upper layer, so ++ * ignore lower layer being read-only. ++ * ++ * If the overlay itself is read-only then proceed ++ * with the permission check, don't return EROFS. ++ * This will only happen if this is the lower layer of ++ * another overlayfs. ++ * ++ * If upper fs becomes read-only after the overlay was ++ * constructed return EROFS to prevent modification of ++ * upper layer. ++ */ ++ err = -EROFS; ++ if (is_upper && !IS_RDONLY(inode) && IS_RDONLY(realinode) && ++ (S_ISREG(mode) || S_ISDIR(mode) || S_ISLNK(mode))) ++ goto out_dput; ++ } ++ ++ err = inode_only_permission(realinode, mask); ++out_dput: ++ dput(alias); ++ return err; ++} ++ ++ ++struct ovl_link_data { ++ struct dentry *realdentry; ++ void *cookie; ++}; ++ ++static void *ovl_follow_link(struct dentry *dentry, struct nameidata *nd) ++{ ++ void *ret; ++ struct dentry *realdentry; ++ struct inode *realinode; ++ ++ realdentry = ovl_dentry_real(dentry); ++ realinode = realdentry->d_inode; ++ ++ if (WARN_ON(!realinode->i_op->follow_link)) ++ return ERR_PTR(-EPERM); ++ ++ ret = realinode->i_op->follow_link(realdentry, nd); ++ if (IS_ERR(ret)) ++ return ret; ++ ++ if (realinode->i_op->put_link) { ++ struct ovl_link_data *data; ++ ++ data = kmalloc(sizeof(struct ovl_link_data), GFP_KERNEL); ++ if (!data) { ++ realinode->i_op->put_link(realdentry, nd, ret); ++ return ERR_PTR(-ENOMEM); ++ } ++ data->realdentry = realdentry; ++ data->cookie = ret; ++ ++ return data; ++ } else { ++ return NULL; ++ } ++} ++ ++static void ovl_put_link(struct dentry *dentry, struct nameidata *nd, void *c) ++{ ++ struct inode *realinode; ++ struct ovl_link_data *data = c; ++ ++ if (!data) ++ return; ++ ++ realinode = data->realdentry->d_inode; ++ realinode->i_op->put_link(data->realdentry, nd, data->cookie); ++ kfree(data); ++} ++ ++static int ovl_readlink(struct dentry *dentry, char __user *buf, int bufsiz) ++{ ++ struct path realpath; ++ struct inode *realinode; ++ ++ ovl_path_real(dentry, &realpath); ++ realinode = realpath.dentry->d_inode; ++ ++ if (!realinode->i_op->readlink) ++ return -EINVAL; ++ ++ touch_atime(&realpath); ++ ++ return realinode->i_op->readlink(realpath.dentry, buf, bufsiz); ++} ++ ++ ++static bool ovl_is_private_xattr(const char *name) ++{ ++ return strncmp(name, "trusted.overlay.", 14) == 0; ++} ++ ++int ovl_setxattr(struct dentry *dentry, const char *name, ++ const void *value, size_t size, int flags) ++{ ++ int err; ++ struct dentry *upperdentry; ++ ++ if (ovl_is_private_xattr(name)) ++ return -EPERM; ++ ++ err = ovl_copy_up(dentry); ++ if (err) ++ return err; ++ ++ upperdentry = ovl_dentry_upper(dentry); ++ return vfs_setxattr(upperdentry, name, value, size, flags); ++} ++ ++ssize_t ovl_getxattr(struct dentry *dentry, const char *name, ++ void *value, size_t size) ++{ ++ if (ovl_path_type(dentry->d_parent) == OVL_PATH_MERGE && ++ ovl_is_private_xattr(name)) ++ return -ENODATA; ++ ++ return vfs_getxattr(ovl_dentry_real(dentry), name, value, size); ++} ++ ++ssize_t ovl_listxattr(struct dentry *dentry, char *list, size_t size) ++{ ++ ssize_t res; ++ int off; ++ ++ res = vfs_listxattr(ovl_dentry_real(dentry), list, size); ++ if (res <= 0 || size == 0) ++ return res; ++ ++ if (ovl_path_type(dentry->d_parent) != OVL_PATH_MERGE) ++ return res; ++ ++ /* filter out private xattrs */ ++ for (off = 0; off < res;) { ++ char *s = list + off; ++ size_t slen = strlen(s) + 1; ++ ++ BUG_ON(off + slen > res); ++ ++ if (ovl_is_private_xattr(s)) { ++ res -= slen; ++ memmove(s, s + slen, res - off); ++ } else { ++ off += slen; ++ } ++ } ++ ++ return res; ++} ++ ++int ovl_removexattr(struct dentry *dentry, const char *name) ++{ ++ int err; ++ struct path realpath; ++ enum ovl_path_type type; ++ ++ if (ovl_path_type(dentry->d_parent) == OVL_PATH_MERGE && ++ ovl_is_private_xattr(name)) ++ return -ENODATA; ++ ++ type = ovl_path_real(dentry, &realpath); ++ if (type == OVL_PATH_LOWER) { ++ err = vfs_getxattr(realpath.dentry, name, NULL, 0); ++ if (err < 0) ++ return err; ++ ++ err = ovl_copy_up(dentry); ++ if (err) ++ return err; ++ ++ ovl_path_upper(dentry, &realpath); ++ } ++ ++ return vfs_removexattr(realpath.dentry, name); ++} ++ ++static bool ovl_open_need_copy_up(int flags, enum ovl_path_type type, ++ struct dentry *realdentry) ++{ ++ if (type != OVL_PATH_LOWER) ++ return false; ++ ++ if (special_file(realdentry->d_inode->i_mode)) ++ return false; ++ ++ if (!(OPEN_FMODE(flags) & FMODE_WRITE) && !(flags & O_TRUNC)) ++ return false; ++ ++ return true; ++} ++ ++static struct file *ovl_open(struct dentry *dentry, struct file *file, ++ const struct cred *cred) ++{ ++ int err; ++ struct path realpath; ++ enum ovl_path_type type; ++ ++ type = ovl_path_real(dentry, &realpath); ++ if (ovl_open_need_copy_up(file->f_flags, type, realpath.dentry)) { ++ if (file->f_flags & O_TRUNC) ++ err = ovl_copy_up_truncate(dentry, 0); ++ else ++ err = ovl_copy_up(dentry); ++ if (err) ++ return ERR_PTR(err); ++ ++ ovl_path_upper(dentry, &realpath); ++ } ++ ++ return vfs_open(&realpath, file, cred); ++} ++ ++static const struct inode_operations ovl_file_inode_operations = { ++ .setattr = ovl_setattr, ++ .permission = ovl_permission, ++ .getattr = ovl_getattr, ++ .setxattr = ovl_setxattr, ++ .getxattr = ovl_getxattr, ++ .listxattr = ovl_listxattr, ++ .removexattr = ovl_removexattr, ++ .open = ovl_open, ++}; ++ ++static const struct inode_operations ovl_symlink_inode_operations = { ++ .setattr = ovl_setattr, ++ .follow_link = ovl_follow_link, ++ .put_link = ovl_put_link, ++ .readlink = ovl_readlink, ++ .getattr = ovl_getattr, ++ .setxattr = ovl_setxattr, ++ .getxattr = ovl_getxattr, ++ .listxattr = ovl_listxattr, ++ .removexattr = ovl_removexattr, ++}; ++ ++struct inode *ovl_new_inode(struct super_block *sb, umode_t mode, ++ struct ovl_entry *oe) ++{ ++ struct inode *inode; ++ ++ inode = new_inode(sb); ++ if (!inode) ++ return NULL; ++ ++ mode &= S_IFMT; ++ ++ inode->i_ino = get_next_ino(); ++ inode->i_mode = mode; ++ inode->i_flags |= S_NOATIME | S_NOCMTIME; ++ ++ switch (mode) { ++ case S_IFDIR: ++ inode->i_private = oe; ++ inode->i_op = &ovl_dir_inode_operations; ++ inode->i_fop = &ovl_dir_operations; ++ break; ++ ++ case S_IFLNK: ++ inode->i_op = &ovl_symlink_inode_operations; ++ break; ++ ++ case S_IFREG: ++ case S_IFSOCK: ++ case S_IFBLK: ++ case S_IFCHR: ++ case S_IFIFO: ++ inode->i_op = &ovl_file_inode_operations; ++ break; ++ ++ default: ++ WARN(1, "illegal file type: %i\n", mode); ++ iput(inode); ++ inode = NULL; ++ } ++ ++ return inode; ++ ++} +diff --git a/fs/overlayfs/overlayfs.h b/fs/overlayfs/overlayfs.h +new file mode 100644 +index 0000000..1dd05f7 +--- /dev/null ++++ b/fs/overlayfs/overlayfs.h +@@ -0,0 +1,64 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++struct ovl_entry; ++ ++enum ovl_path_type { ++ OVL_PATH_UPPER, ++ OVL_PATH_MERGE, ++ OVL_PATH_LOWER, ++}; ++ ++extern const char *ovl_opaque_xattr; ++extern const char *ovl_whiteout_xattr; ++extern const struct dentry_operations ovl_dentry_operations; ++ ++enum ovl_path_type ovl_path_type(struct dentry *dentry); ++u64 ovl_dentry_version_get(struct dentry *dentry); ++void ovl_dentry_version_inc(struct dentry *dentry); ++void ovl_path_upper(struct dentry *dentry, struct path *path); ++void ovl_path_lower(struct dentry *dentry, struct path *path); ++enum ovl_path_type ovl_path_real(struct dentry *dentry, struct path *path); ++struct dentry *ovl_dentry_upper(struct dentry *dentry); ++struct dentry *ovl_dentry_lower(struct dentry *dentry); ++struct dentry *ovl_dentry_real(struct dentry *dentry); ++struct dentry *ovl_entry_real(struct ovl_entry *oe, bool *is_upper); ++bool ovl_dentry_is_opaque(struct dentry *dentry); ++void ovl_dentry_set_opaque(struct dentry *dentry, bool opaque); ++bool ovl_is_whiteout(struct dentry *dentry); ++void ovl_dentry_update(struct dentry *dentry, struct dentry *upperdentry); ++struct dentry *ovl_lookup(struct inode *dir, struct dentry *dentry, ++ struct nameidata *nd); ++struct file *ovl_path_open(struct path *path, int flags); ++ ++struct dentry *ovl_upper_create(struct dentry *upperdir, struct dentry *dentry, ++ struct kstat *stat, const char *link); ++ ++/* readdir.c */ ++extern const struct file_operations ovl_dir_operations; ++int ovl_check_empty_and_clear(struct dentry *dentry, enum ovl_path_type type); ++ ++/* inode.c */ ++int ovl_setattr(struct dentry *dentry, struct iattr *attr); ++int ovl_permission(struct inode *inode, int mask); ++int ovl_setxattr(struct dentry *dentry, const char *name, ++ const void *value, size_t size, int flags); ++ssize_t ovl_getxattr(struct dentry *dentry, const char *name, ++ void *value, size_t size); ++ssize_t ovl_listxattr(struct dentry *dentry, char *list, size_t size); ++int ovl_removexattr(struct dentry *dentry, const char *name); ++ ++struct inode *ovl_new_inode(struct super_block *sb, umode_t mode, ++ struct ovl_entry *oe); ++/* dir.c */ ++extern const struct inode_operations ovl_dir_inode_operations; ++ ++/* copy_up.c */ ++int ovl_copy_up(struct dentry *dentry); ++int ovl_copy_up_truncate(struct dentry *dentry, loff_t size); +diff --git a/fs/overlayfs/readdir.c b/fs/overlayfs/readdir.c +new file mode 100644 +index 0000000..0797efb +--- /dev/null ++++ b/fs/overlayfs/readdir.c +@@ -0,0 +1,566 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "overlayfs.h" ++ ++struct ovl_cache_entry { ++ const char *name; ++ unsigned int len; ++ unsigned int type; ++ u64 ino; ++ bool is_whiteout; ++ struct list_head l_node; ++ struct rb_node node; ++}; ++ ++struct ovl_readdir_data { ++ struct rb_root *root; ++ struct list_head *list; ++ struct list_head *middle; ++ struct dentry *dir; ++ int count; ++ int err; ++}; ++ ++struct ovl_dir_file { ++ bool is_real; ++ bool is_cached; ++ struct list_head cursor; ++ u64 cache_version; ++ struct list_head cache; ++ struct file *realfile; ++}; ++ ++static struct ovl_cache_entry *ovl_cache_entry_from_node(struct rb_node *n) ++{ ++ return container_of(n, struct ovl_cache_entry, node); ++} ++ ++static struct ovl_cache_entry *ovl_cache_entry_find(struct rb_root *root, ++ const char *name, int len) ++{ ++ struct rb_node *node = root->rb_node; ++ int cmp; ++ ++ while (node) { ++ struct ovl_cache_entry *p = ovl_cache_entry_from_node(node); ++ ++ cmp = strncmp(name, p->name, len); ++ if (cmp > 0) ++ node = p->node.rb_right; ++ else if (cmp < 0 || len < p->len) ++ node = p->node.rb_left; ++ else ++ return p; ++ } ++ ++ return NULL; ++} ++ ++static struct ovl_cache_entry *ovl_cache_entry_new(const char *name, int len, ++ u64 ino, unsigned int d_type) ++{ ++ struct ovl_cache_entry *p; ++ ++ p = kmalloc(sizeof(*p) + len + 1, GFP_KERNEL); ++ if (p) { ++ char *name_copy = (char *) (p + 1); ++ memcpy(name_copy, name, len); ++ name_copy[len] = '\0'; ++ p->name = name_copy; ++ p->len = len; ++ p->type = d_type; ++ p->ino = ino; ++ p->is_whiteout = false; ++ } ++ ++ return p; ++} ++ ++static int ovl_cache_entry_add_rb(struct ovl_readdir_data *rdd, ++ const char *name, int len, u64 ino, ++ unsigned int d_type) ++{ ++ struct rb_node **newp = &rdd->root->rb_node; ++ struct rb_node *parent = NULL; ++ struct ovl_cache_entry *p; ++ ++ while (*newp) { ++ int cmp; ++ struct ovl_cache_entry *tmp; ++ ++ parent = *newp; ++ tmp = ovl_cache_entry_from_node(*newp); ++ cmp = strncmp(name, tmp->name, len); ++ if (cmp > 0) ++ newp = &tmp->node.rb_right; ++ else if (cmp < 0 || len < tmp->len) ++ newp = &tmp->node.rb_left; ++ else ++ return 0; ++ } ++ ++ p = ovl_cache_entry_new(name, len, ino, d_type); ++ if (p == NULL) ++ return -ENOMEM; ++ ++ list_add_tail(&p->l_node, rdd->list); ++ rb_link_node(&p->node, parent, newp); ++ rb_insert_color(&p->node, rdd->root); ++ ++ return 0; ++} ++ ++static int ovl_fill_lower(void *buf, const char *name, int namelen, ++ loff_t offset, u64 ino, unsigned int d_type) ++{ ++ struct ovl_readdir_data *rdd = buf; ++ struct ovl_cache_entry *p; ++ ++ rdd->count++; ++ p = ovl_cache_entry_find(rdd->root, name, namelen); ++ if (p) { ++ list_move_tail(&p->l_node, rdd->middle); ++ } else { ++ p = ovl_cache_entry_new(name, namelen, ino, d_type); ++ if (p == NULL) ++ rdd->err = -ENOMEM; ++ else ++ list_add_tail(&p->l_node, rdd->middle); ++ } ++ ++ return rdd->err; ++} ++ ++static void ovl_cache_free(struct list_head *list) ++{ ++ struct ovl_cache_entry *p; ++ struct ovl_cache_entry *n; ++ ++ list_for_each_entry_safe(p, n, list, l_node) ++ kfree(p); ++ ++ INIT_LIST_HEAD(list); ++} ++ ++static int ovl_fill_upper(void *buf, const char *name, int namelen, ++ loff_t offset, u64 ino, unsigned int d_type) ++{ ++ struct ovl_readdir_data *rdd = buf; ++ ++ rdd->count++; ++ return ovl_cache_entry_add_rb(rdd, name, namelen, ino, d_type); ++} ++ ++static inline int ovl_dir_read(struct path *realpath, ++ struct ovl_readdir_data *rdd, filldir_t filler) ++{ ++ struct file *realfile; ++ int err; ++ ++ realfile = ovl_path_open(realpath, O_RDONLY | O_DIRECTORY); ++ if (IS_ERR(realfile)) ++ return PTR_ERR(realfile); ++ ++ do { ++ rdd->count = 0; ++ rdd->err = 0; ++ err = vfs_readdir(realfile, filler, rdd); ++ if (err >= 0) ++ err = rdd->err; ++ } while (!err && rdd->count); ++ fput(realfile); ++ ++ return 0; ++} ++ ++static void ovl_dir_reset(struct file *file) ++{ ++ struct ovl_dir_file *od = file->private_data; ++ enum ovl_path_type type = ovl_path_type(file->f_path.dentry); ++ ++ if (ovl_dentry_version_get(file->f_path.dentry) != od->cache_version) { ++ list_del_init(&od->cursor); ++ ovl_cache_free(&od->cache); ++ od->is_cached = false; ++ } ++ WARN_ON(!od->is_real && type != OVL_PATH_MERGE); ++ if (od->is_real && type == OVL_PATH_MERGE) { ++ fput(od->realfile); ++ od->realfile = NULL; ++ od->is_real = false; ++ } ++} ++ ++static int ovl_dir_mark_whiteouts(struct ovl_readdir_data *rdd) ++{ ++ struct ovl_cache_entry *p; ++ struct dentry *dentry; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ override_cred = prepare_creds(); ++ if (!override_cred) { ++ ovl_cache_free(rdd->list); ++ return -ENOMEM; ++ } ++ ++ /* ++ * CAP_SYS_ADMIN for getxattr ++ * CAP_DAC_OVERRIDE for lookup ++ */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); ++ old_cred = override_creds(override_cred); ++ ++ mutex_lock(&rdd->dir->d_inode->i_mutex); ++ list_for_each_entry(p, rdd->list, l_node) { ++ if (p->type != DT_LNK) ++ continue; ++ ++ dentry = lookup_one_len(p->name, rdd->dir, p->len); ++ if (IS_ERR(dentry)) ++ continue; ++ ++ p->is_whiteout = ovl_is_whiteout(dentry); ++ dput(dentry); ++ } ++ mutex_unlock(&rdd->dir->d_inode->i_mutex); ++ ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ ++ return 0; ++} ++ ++static inline int ovl_dir_read_merged(struct path *upperpath, ++ struct path *lowerpath, ++ struct ovl_readdir_data *rdd) ++{ ++ int err; ++ struct rb_root root = RB_ROOT; ++ struct list_head middle; ++ ++ rdd->root = &root; ++ if (upperpath->dentry) { ++ rdd->dir = upperpath->dentry; ++ err = ovl_dir_read(upperpath, rdd, ovl_fill_upper); ++ if (err) ++ goto out; ++ ++ err = ovl_dir_mark_whiteouts(rdd); ++ if (err) ++ goto out; ++ } ++ /* ++ * Insert lowerpath entries before upperpath ones, this allows ++ * offsets to be reasonably constant ++ */ ++ list_add(&middle, rdd->list); ++ rdd->middle = &middle; ++ err = ovl_dir_read(lowerpath, rdd, ovl_fill_lower); ++ list_del(&middle); ++out: ++ rdd->root = NULL; ++ ++ return err; ++} ++ ++static void ovl_seek_cursor(struct ovl_dir_file *od, loff_t pos) ++{ ++ struct list_head *l; ++ loff_t off; ++ ++ l = od->cache.next; ++ for (off = 0; off < pos; off++) { ++ if (l == &od->cache) ++ break; ++ l = l->next; ++ } ++ list_move_tail(&od->cursor, l); ++} ++ ++static int ovl_readdir(struct file *file, void *buf, filldir_t filler) ++{ ++ struct ovl_dir_file *od = file->private_data; ++ int res; ++ ++ if (!file->f_pos) ++ ovl_dir_reset(file); ++ ++ if (od->is_real) { ++ res = vfs_readdir(od->realfile, filler, buf); ++ file->f_pos = od->realfile->f_pos; ++ ++ return res; ++ } ++ ++ if (!od->is_cached) { ++ struct path lowerpath; ++ struct path upperpath; ++ struct ovl_readdir_data rdd = { .list = &od->cache }; ++ ++ ovl_path_lower(file->f_path.dentry, &lowerpath); ++ ovl_path_upper(file->f_path.dentry, &upperpath); ++ ++ res = ovl_dir_read_merged(&upperpath, &lowerpath, &rdd); ++ if (res) { ++ ovl_cache_free(rdd.list); ++ return res; ++ } ++ ++ od->cache_version = ovl_dentry_version_get(file->f_path.dentry); ++ od->is_cached = true; ++ ++ ovl_seek_cursor(od, file->f_pos); ++ } ++ ++ while (od->cursor.next != &od->cache) { ++ int over; ++ loff_t off; ++ struct ovl_cache_entry *p; ++ ++ p = list_entry(od->cursor.next, struct ovl_cache_entry, l_node); ++ off = file->f_pos; ++ if (!p->is_whiteout) { ++ over = filler(buf, p->name, p->len, off, p->ino, ++ p->type); ++ if (over) ++ break; ++ } ++ file->f_pos++; ++ list_move(&od->cursor, &p->l_node); ++ } ++ ++ return 0; ++} ++ ++static loff_t ovl_dir_llseek(struct file *file, loff_t offset, int origin) ++{ ++ loff_t res; ++ struct ovl_dir_file *od = file->private_data; ++ ++ mutex_lock(&file->f_dentry->d_inode->i_mutex); ++ if (!file->f_pos) ++ ovl_dir_reset(file); ++ ++ if (od->is_real) { ++ res = vfs_llseek(od->realfile, offset, origin); ++ file->f_pos = od->realfile->f_pos; ++ } else { ++ res = -EINVAL; ++ ++ switch (origin) { ++ case SEEK_CUR: ++ offset += file->f_pos; ++ break; ++ case SEEK_SET: ++ break; ++ default: ++ goto out_unlock; ++ } ++ if (offset < 0) ++ goto out_unlock; ++ ++ if (offset != file->f_pos) { ++ file->f_pos = offset; ++ if (od->is_cached) ++ ovl_seek_cursor(od, offset); ++ } ++ res = offset; ++ } ++out_unlock: ++ mutex_unlock(&file->f_dentry->d_inode->i_mutex); ++ ++ return res; ++} ++ ++static int ovl_dir_fsync(struct file *file, loff_t start, loff_t end, ++ int datasync) ++{ ++ struct ovl_dir_file *od = file->private_data; ++ ++ /* May need to reopen directory if it got copied up */ ++ if (!od->realfile) { ++ struct path upperpath; ++ ++ ovl_path_upper(file->f_path.dentry, &upperpath); ++ od->realfile = ovl_path_open(&upperpath, O_RDONLY); ++ if (IS_ERR(od->realfile)) ++ return PTR_ERR(od->realfile); ++ } ++ ++ return vfs_fsync_range(od->realfile, start, end, datasync); ++} ++ ++static int ovl_dir_release(struct inode *inode, struct file *file) ++{ ++ struct ovl_dir_file *od = file->private_data; ++ ++ list_del(&od->cursor); ++ ovl_cache_free(&od->cache); ++ if (od->realfile) ++ fput(od->realfile); ++ kfree(od); ++ ++ return 0; ++} ++ ++static int ovl_dir_open(struct inode *inode, struct file *file) ++{ ++ struct path realpath; ++ struct file *realfile; ++ struct ovl_dir_file *od; ++ enum ovl_path_type type; ++ ++ od = kzalloc(sizeof(struct ovl_dir_file), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ type = ovl_path_real(file->f_path.dentry, &realpath); ++ realfile = ovl_path_open(&realpath, file->f_flags); ++ if (IS_ERR(realfile)) { ++ kfree(od); ++ return PTR_ERR(realfile); ++ } ++ INIT_LIST_HEAD(&od->cache); ++ INIT_LIST_HEAD(&od->cursor); ++ od->is_cached = false; ++ od->realfile = realfile; ++ od->is_real = (type != OVL_PATH_MERGE); ++ file->private_data = od; ++ ++ return 0; ++} ++ ++const struct file_operations ovl_dir_operations = { ++ .read = generic_read_dir, ++ .open = ovl_dir_open, ++ .readdir = ovl_readdir, ++ .llseek = ovl_dir_llseek, ++ .fsync = ovl_dir_fsync, ++ .release = ovl_dir_release, ++}; ++ ++static int ovl_check_empty_dir(struct dentry *dentry, struct list_head *list) ++{ ++ int err; ++ struct path lowerpath; ++ struct path upperpath; ++ struct ovl_cache_entry *p; ++ struct ovl_readdir_data rdd = { .list = list }; ++ ++ ovl_path_upper(dentry, &upperpath); ++ ovl_path_lower(dentry, &lowerpath); ++ ++ err = ovl_dir_read_merged(&upperpath, &lowerpath, &rdd); ++ if (err) ++ return err; ++ ++ err = 0; ++ ++ list_for_each_entry(p, list, l_node) { ++ if (p->is_whiteout) ++ continue; ++ ++ if (p->name[0] == '.') { ++ if (p->len == 1) ++ continue; ++ if (p->len == 2 && p->name[1] == '.') ++ continue; ++ } ++ err = -ENOTEMPTY; ++ break; ++ } ++ ++ return err; ++} ++ ++static int ovl_remove_whiteouts(struct dentry *dir, struct list_head *list) ++{ ++ struct path upperpath; ++ struct dentry *upperdir; ++ struct ovl_cache_entry *p; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ int err; ++ ++ ovl_path_upper(dir, &upperpath); ++ upperdir = upperpath.dentry; ++ ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ return -ENOMEM; ++ ++ /* ++ * CAP_DAC_OVERRIDE for lookup and unlink ++ * CAP_SYS_ADMIN for setxattr of "trusted" namespace ++ * CAP_FOWNER for unlink in sticky directory ++ */ ++ cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ cap_raise(override_cred->cap_effective, CAP_FOWNER); ++ old_cred = override_creds(override_cred); ++ ++ err = vfs_setxattr(upperdir, ovl_opaque_xattr, "y", 1, 0); ++ if (err) ++ goto out_revert_creds; ++ ++ mutex_lock_nested(&upperdir->d_inode->i_mutex, I_MUTEX_PARENT); ++ list_for_each_entry(p, list, l_node) { ++ struct dentry *dentry; ++ int ret; ++ ++ if (!p->is_whiteout) ++ continue; ++ ++ dentry = lookup_one_len(p->name, upperdir, p->len); ++ if (IS_ERR(dentry)) { ++ printk(KERN_WARNING ++ "overlayfs: failed to lookup whiteout %.*s: %li\n", ++ p->len, p->name, PTR_ERR(dentry)); ++ continue; ++ } ++ ret = vfs_unlink(upperdir->d_inode, dentry); ++ dput(dentry); ++ if (ret) ++ printk(KERN_WARNING ++ "overlayfs: failed to unlink whiteout %.*s: %i\n", ++ p->len, p->name, ret); ++ } ++ mutex_unlock(&upperdir->d_inode->i_mutex); ++ ++out_revert_creds: ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ ++ return err; ++} ++ ++int ovl_check_empty_and_clear(struct dentry *dentry, enum ovl_path_type type) ++{ ++ int err; ++ LIST_HEAD(list); ++ ++ err = ovl_check_empty_dir(dentry, &list); ++ if (!err && type == OVL_PATH_MERGE) ++ err = ovl_remove_whiteouts(dentry, &list); ++ ++ ovl_cache_free(&list); ++ ++ return err; ++} +diff --git a/fs/overlayfs/super.c b/fs/overlayfs/super.c +new file mode 100644 +index 0000000..1d2d1e2 +--- /dev/null ++++ b/fs/overlayfs/super.c +@@ -0,0 +1,664 @@ ++/* ++ * ++ * Copyright (C) 2011 Novell Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "overlayfs.h" ++ ++MODULE_AUTHOR("Miklos Szeredi "); ++MODULE_DESCRIPTION("Overlay filesystem"); ++MODULE_LICENSE("GPL"); ++ ++struct ovl_config { ++ char *lowerdir; ++ char *upperdir; ++}; ++ ++/* private information held for overlayfs's superblock */ ++struct ovl_fs { ++ struct vfsmount *upper_mnt; ++ struct vfsmount *lower_mnt; ++ /* pathnames of lower and upper dirs, for show_options */ ++ struct ovl_config config; ++}; ++ ++/* private information held for every overlayfs dentry */ ++struct ovl_entry { ++ /* ++ * Keep "double reference" on upper dentries, so that ++ * d_delete() doesn't think it's OK to reset d_inode to NULL. ++ */ ++ struct dentry *__upperdentry; ++ struct dentry *lowerdentry; ++ union { ++ struct { ++ u64 version; ++ bool opaque; ++ }; ++ struct rcu_head rcu; ++ }; ++}; ++ ++const char *ovl_whiteout_xattr = "trusted.overlay.whiteout"; ++const char *ovl_opaque_xattr = "trusted.overlay.opaque"; ++ ++ ++enum ovl_path_type ovl_path_type(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ if (oe->__upperdentry) { ++ if (oe->lowerdentry && S_ISDIR(dentry->d_inode->i_mode)) ++ return OVL_PATH_MERGE; ++ else ++ return OVL_PATH_UPPER; ++ } else { ++ return OVL_PATH_LOWER; ++ } ++} ++ ++static struct dentry *ovl_upperdentry_dereference(struct ovl_entry *oe) ++{ ++ struct dentry *upperdentry = ACCESS_ONCE(oe->__upperdentry); ++ smp_read_barrier_depends(); ++ return upperdentry; ++} ++ ++void ovl_path_upper(struct dentry *dentry, struct path *path) ++{ ++ struct ovl_fs *ofs = dentry->d_sb->s_fs_info; ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ path->mnt = ofs->upper_mnt; ++ path->dentry = ovl_upperdentry_dereference(oe); ++} ++ ++void ovl_path_lower(struct dentry *dentry, struct path *path) ++{ ++ struct ovl_fs *ofs = dentry->d_sb->s_fs_info; ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ path->mnt = ofs->lower_mnt; ++ path->dentry = oe->lowerdentry; ++} ++ ++enum ovl_path_type ovl_path_real(struct dentry *dentry, struct path *path) ++{ ++ ++ enum ovl_path_type type = ovl_path_type(dentry); ++ ++ if (type == OVL_PATH_LOWER) ++ ovl_path_lower(dentry, path); ++ else ++ ovl_path_upper(dentry, path); ++ ++ return type; ++} ++ ++struct dentry *ovl_dentry_upper(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ return ovl_upperdentry_dereference(oe); ++} ++ ++struct dentry *ovl_dentry_lower(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ return oe->lowerdentry; ++} ++ ++struct dentry *ovl_dentry_real(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ struct dentry *realdentry; ++ ++ realdentry = ovl_upperdentry_dereference(oe); ++ if (!realdentry) ++ realdentry = oe->lowerdentry; ++ ++ return realdentry; ++} ++ ++struct dentry *ovl_entry_real(struct ovl_entry *oe, bool *is_upper) ++{ ++ struct dentry *realdentry; ++ ++ realdentry = ovl_upperdentry_dereference(oe); ++ if (realdentry) { ++ *is_upper = true; ++ } else { ++ realdentry = oe->lowerdentry; ++ *is_upper = false; ++ } ++ return realdentry; ++} ++ ++bool ovl_dentry_is_opaque(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ return oe->opaque; ++} ++ ++void ovl_dentry_set_opaque(struct dentry *dentry, bool opaque) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ oe->opaque = opaque; ++} ++ ++void ovl_dentry_update(struct dentry *dentry, struct dentry *upperdentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ WARN_ON(!mutex_is_locked(&upperdentry->d_parent->d_inode->i_mutex)); ++ WARN_ON(oe->__upperdentry); ++ BUG_ON(!upperdentry->d_inode); ++ smp_wmb(); ++ oe->__upperdentry = dget(upperdentry); ++} ++ ++void ovl_dentry_version_inc(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ WARN_ON(!mutex_is_locked(&dentry->d_inode->i_mutex)); ++ oe->version++; ++} ++ ++u64 ovl_dentry_version_get(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ WARN_ON(!mutex_is_locked(&dentry->d_inode->i_mutex)); ++ return oe->version; ++} ++ ++bool ovl_is_whiteout(struct dentry *dentry) ++{ ++ int res; ++ char val; ++ ++ if (!dentry) ++ return false; ++ if (!dentry->d_inode) ++ return false; ++ if (!S_ISLNK(dentry->d_inode->i_mode)) ++ return false; ++ ++ res = vfs_getxattr(dentry, ovl_whiteout_xattr, &val, 1); ++ if (res == 1 && val == 'y') ++ return true; ++ ++ return false; ++} ++ ++static bool ovl_is_opaquedir(struct dentry *dentry) ++{ ++ int res; ++ char val; ++ ++ if (!S_ISDIR(dentry->d_inode->i_mode)) ++ return false; ++ ++ res = vfs_getxattr(dentry, ovl_opaque_xattr, &val, 1); ++ if (res == 1 && val == 'y') ++ return true; ++ ++ return false; ++} ++ ++static void ovl_entry_free(struct rcu_head *head) ++{ ++ struct ovl_entry *oe = container_of(head, struct ovl_entry, rcu); ++ kfree(oe); ++} ++ ++static void ovl_dentry_release(struct dentry *dentry) ++{ ++ struct ovl_entry *oe = dentry->d_fsdata; ++ ++ if (oe) { ++ dput(oe->__upperdentry); ++ dput(oe->__upperdentry); ++ dput(oe->lowerdentry); ++ call_rcu(&oe->rcu, ovl_entry_free); ++ } ++} ++ ++const struct dentry_operations ovl_dentry_operations = { ++ .d_release = ovl_dentry_release, ++}; ++ ++static struct ovl_entry *ovl_alloc_entry(void) ++{ ++ return kzalloc(sizeof(struct ovl_entry), GFP_KERNEL); ++} ++ ++static inline struct dentry *ovl_lookup_real(struct dentry *dir, ++ struct qstr *name) ++{ ++ struct dentry *dentry; ++ ++ mutex_lock(&dir->d_inode->i_mutex); ++ dentry = lookup_one_len(name->name, dir, name->len); ++ mutex_unlock(&dir->d_inode->i_mutex); ++ ++ if (IS_ERR(dentry)) { ++ if (PTR_ERR(dentry) == -ENOENT) ++ dentry = NULL; ++ } else if (!dentry->d_inode) { ++ dput(dentry); ++ dentry = NULL; ++ } ++ return dentry; ++} ++ ++static int ovl_do_lookup(struct dentry *dentry) ++{ ++ struct ovl_entry *oe; ++ struct dentry *upperdir; ++ struct dentry *lowerdir; ++ struct dentry *upperdentry = NULL; ++ struct dentry *lowerdentry = NULL; ++ struct inode *inode = NULL; ++ int err; ++ ++ err = -ENOMEM; ++ oe = ovl_alloc_entry(); ++ if (!oe) ++ goto out; ++ ++ upperdir = ovl_dentry_upper(dentry->d_parent); ++ lowerdir = ovl_dentry_lower(dentry->d_parent); ++ ++ if (upperdir) { ++ upperdentry = ovl_lookup_real(upperdir, &dentry->d_name); ++ err = PTR_ERR(upperdentry); ++ if (IS_ERR(upperdentry)) ++ goto out_put_dir; ++ ++ if (lowerdir && upperdentry && ++ (S_ISLNK(upperdentry->d_inode->i_mode) || ++ S_ISDIR(upperdentry->d_inode->i_mode))) { ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ ++ err = -ENOMEM; ++ override_cred = prepare_creds(); ++ if (!override_cred) ++ goto out_dput_upper; ++ ++ /* CAP_SYS_ADMIN needed for getxattr */ ++ cap_raise(override_cred->cap_effective, CAP_SYS_ADMIN); ++ old_cred = override_creds(override_cred); ++ ++ if (ovl_is_opaquedir(upperdentry)) { ++ oe->opaque = true; ++ } else if (ovl_is_whiteout(upperdentry)) { ++ dput(upperdentry); ++ upperdentry = NULL; ++ oe->opaque = true; ++ } ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ } ++ } ++ if (lowerdir && !oe->opaque) { ++ lowerdentry = ovl_lookup_real(lowerdir, &dentry->d_name); ++ err = PTR_ERR(lowerdentry); ++ if (IS_ERR(lowerdentry)) ++ goto out_dput_upper; ++ } ++ ++ if (lowerdentry && upperdentry && ++ (!S_ISDIR(upperdentry->d_inode->i_mode) || ++ !S_ISDIR(lowerdentry->d_inode->i_mode))) { ++ dput(lowerdentry); ++ lowerdentry = NULL; ++ oe->opaque = true; ++ } ++ ++ if (lowerdentry || upperdentry) { ++ struct dentry *realdentry; ++ ++ realdentry = upperdentry ? upperdentry : lowerdentry; ++ err = -ENOMEM; ++ inode = ovl_new_inode(dentry->d_sb, realdentry->d_inode->i_mode, ++ oe); ++ if (!inode) ++ goto out_dput; ++ } ++ ++ if (upperdentry) ++ oe->__upperdentry = dget(upperdentry); ++ ++ if (lowerdentry) ++ oe->lowerdentry = lowerdentry; ++ ++ dentry->d_fsdata = oe; ++ dentry->d_op = &ovl_dentry_operations; ++ d_add(dentry, inode); ++ ++ return 0; ++ ++out_dput: ++ dput(lowerdentry); ++out_dput_upper: ++ dput(upperdentry); ++out_put_dir: ++ kfree(oe); ++out: ++ return err; ++} ++ ++struct dentry *ovl_lookup(struct inode *dir, struct dentry *dentry, ++ struct nameidata *nd) ++{ ++ int err = ovl_do_lookup(dentry); ++ ++ if (err) ++ return ERR_PTR(err); ++ ++ return NULL; ++} ++ ++struct file *ovl_path_open(struct path *path, int flags) ++{ ++ path_get(path); ++ return dentry_open(path->dentry, path->mnt, flags, current_cred()); ++} ++ ++static void ovl_put_super(struct super_block *sb) ++{ ++ struct ovl_fs *ufs = sb->s_fs_info; ++ ++ if (!(sb->s_flags & MS_RDONLY)) ++ mnt_drop_write(ufs->upper_mnt); ++ ++ mntput(ufs->upper_mnt); ++ mntput(ufs->lower_mnt); ++ ++ kfree(ufs->config.lowerdir); ++ kfree(ufs->config.upperdir); ++ kfree(ufs); ++} ++ ++static int ovl_remount_fs(struct super_block *sb, int *flagsp, char *data) ++{ ++ int flags = *flagsp; ++ struct ovl_fs *ufs = sb->s_fs_info; ++ ++ /* When remounting rw or ro, we need to adjust the write access to the ++ * upper fs. ++ */ ++ if (((flags ^ sb->s_flags) & MS_RDONLY) == 0) ++ /* No change to readonly status */ ++ return 0; ++ ++ if (flags & MS_RDONLY) { ++ mnt_drop_write(ufs->upper_mnt); ++ return 0; ++ } else ++ return mnt_want_write(ufs->upper_mnt); ++} ++ ++/** ++ * ovl_statfs ++ * @sb: The overlayfs super block ++ * @buf: The struct kstatfs to fill in with stats ++ * ++ * Get the filesystem statistics. As writes always target the upper layer ++ * filesystem pass the statfs to the same filesystem. ++ */ ++static int ovl_statfs(struct dentry *dentry, struct kstatfs *buf) ++{ ++ struct dentry *root_dentry = dentry->d_sb->s_root; ++ struct path path; ++ ovl_path_upper(root_dentry, &path); ++ ++ if (!path.dentry->d_sb->s_op->statfs) ++ return -ENOSYS; ++ return path.dentry->d_sb->s_op->statfs(path.dentry, buf); ++} ++ ++/** ++ * ovl_show_options ++ * ++ * Prints the mount options for a given superblock. ++ * Returns zero; does not fail. ++ */ ++static int ovl_show_options(struct seq_file *m, struct dentry *dentry) ++{ ++ struct super_block *sb = dentry->d_sb; ++ struct ovl_fs *ufs = sb->s_fs_info; ++ ++ seq_printf(m, ",lowerdir=%s", ufs->config.lowerdir); ++ seq_printf(m, ",upperdir=%s", ufs->config.upperdir); ++ return 0; ++} ++ ++static const struct super_operations ovl_super_operations = { ++ .put_super = ovl_put_super, ++ .remount_fs = ovl_remount_fs, ++ .statfs = ovl_statfs, ++ .show_options = ovl_show_options, ++}; ++ ++enum { ++ Opt_lowerdir, ++ Opt_upperdir, ++ Opt_err, ++}; ++ ++static const match_table_t ovl_tokens = { ++ {Opt_lowerdir, "lowerdir=%s"}, ++ {Opt_upperdir, "upperdir=%s"}, ++ {Opt_err, NULL} ++}; ++ ++static int ovl_parse_opt(char *opt, struct ovl_config *config) ++{ ++ char *p; ++ ++ config->upperdir = NULL; ++ config->lowerdir = NULL; ++ ++ while ((p = strsep(&opt, ",")) != NULL) { ++ int token; ++ substring_t args[MAX_OPT_ARGS]; ++ ++ if (!*p) ++ continue; ++ ++ token = match_token(p, ovl_tokens, args); ++ switch (token) { ++ case Opt_upperdir: ++ kfree(config->upperdir); ++ config->upperdir = match_strdup(&args[0]); ++ if (!config->upperdir) ++ return -ENOMEM; ++ break; ++ ++ case Opt_lowerdir: ++ kfree(config->lowerdir); ++ config->lowerdir = match_strdup(&args[0]); ++ if (!config->lowerdir) ++ return -ENOMEM; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ } ++ return 0; ++} ++ ++static int ovl_fill_super(struct super_block *sb, void *data, int silent) ++{ ++ struct path lowerpath; ++ struct path upperpath; ++ struct inode *root_inode; ++ struct dentry *root_dentry; ++ struct ovl_entry *oe; ++ struct ovl_fs *ufs; ++ int err; ++ ++ err = -ENOMEM; ++ ufs = kmalloc(sizeof(struct ovl_fs), GFP_KERNEL); ++ if (!ufs) ++ goto out; ++ ++ err = ovl_parse_opt((char *) data, &ufs->config); ++ if (err) ++ goto out_free_ufs; ++ ++ err = -EINVAL; ++ if (!ufs->config.upperdir || !ufs->config.lowerdir) { ++ printk(KERN_ERR "overlayfs: missing upperdir or lowerdir\n"); ++ goto out_free_config; ++ } ++ ++ oe = ovl_alloc_entry(); ++ if (oe == NULL) ++ goto out_free_config; ++ ++ err = kern_path(ufs->config.upperdir, LOOKUP_FOLLOW, &upperpath); ++ if (err) ++ goto out_free_oe; ++ ++ err = kern_path(ufs->config.lowerdir, LOOKUP_FOLLOW, &lowerpath); ++ if (err) ++ goto out_put_upperpath; ++ ++ err = -ENOTDIR; ++ if (!S_ISDIR(upperpath.dentry->d_inode->i_mode) || ++ !S_ISDIR(lowerpath.dentry->d_inode->i_mode)) ++ goto out_put_lowerpath; ++ ++ sb->s_stack_depth = max(upperpath.mnt->mnt_sb->s_stack_depth, ++ lowerpath.mnt->mnt_sb->s_stack_depth) + 1; ++ ++ err = -EINVAL; ++ if (sb->s_stack_depth > FILESYSTEM_MAX_STACK_DEPTH) { ++ printk(KERN_ERR "overlayfs: maximum fs stacking depth exceeded\n"); ++ goto out_put_lowerpath; ++ } ++ ++ ++ ufs->upper_mnt = clone_private_mount(&upperpath); ++ err = PTR_ERR(ufs->upper_mnt); ++ if (IS_ERR(ufs->upper_mnt)) { ++ printk(KERN_ERR "overlayfs: failed to clone upperpath\n"); ++ goto out_put_lowerpath; ++ } ++ ++ ufs->lower_mnt = clone_private_mount(&lowerpath); ++ err = PTR_ERR(ufs->lower_mnt); ++ if (IS_ERR(ufs->lower_mnt)) { ++ printk(KERN_ERR "overlayfs: failed to clone lowerpath\n"); ++ goto out_put_upper_mnt; ++ } ++ ++ /* ++ * Make lower_mnt R/O. That way fchmod/fchown on lower file ++ * will fail instead of modifying lower fs. ++ */ ++ ufs->lower_mnt->mnt_flags |= MNT_READONLY; ++ ++ /* If the upper fs is r/o, we mark overlayfs r/o too */ ++ if (ufs->upper_mnt->mnt_sb->s_flags & MS_RDONLY) ++ sb->s_flags |= MS_RDONLY; ++ ++ if (!(sb->s_flags & MS_RDONLY)) { ++ err = mnt_want_write(ufs->upper_mnt); ++ if (err) ++ goto out_put_lower_mnt; ++ } ++ ++ err = -ENOMEM; ++ root_inode = ovl_new_inode(sb, S_IFDIR, oe); ++ if (!root_inode) ++ goto out_drop_write; ++ ++ root_dentry = d_make_root(root_inode); ++ if (!root_dentry) ++ goto out_drop_write; ++ ++ mntput(upperpath.mnt); ++ mntput(lowerpath.mnt); ++ ++ oe->__upperdentry = dget(upperpath.dentry); ++ oe->lowerdentry = lowerpath.dentry; ++ ++ root_dentry->d_fsdata = oe; ++ root_dentry->d_op = &ovl_dentry_operations; ++ ++ sb->s_op = &ovl_super_operations; ++ sb->s_root = root_dentry; ++ sb->s_fs_info = ufs; ++ ++ return 0; ++ ++out_drop_write: ++ if (!(sb->s_flags & MS_RDONLY)) ++ mnt_drop_write(ufs->upper_mnt); ++out_put_lower_mnt: ++ mntput(ufs->lower_mnt); ++out_put_upper_mnt: ++ mntput(ufs->upper_mnt); ++out_put_lowerpath: ++ path_put(&lowerpath); ++out_put_upperpath: ++ path_put(&upperpath); ++out_free_oe: ++ kfree(oe); ++out_free_config: ++ kfree(ufs->config.lowerdir); ++ kfree(ufs->config.upperdir); ++out_free_ufs: ++ kfree(ufs); ++out: ++ return err; ++} ++ ++static struct dentry *ovl_mount(struct file_system_type *fs_type, int flags, ++ const char *dev_name, void *raw_data) ++{ ++ return mount_nodev(fs_type, flags, raw_data, ovl_fill_super); ++} ++ ++static struct file_system_type ovl_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "overlayfs", ++ .mount = ovl_mount, ++ .kill_sb = kill_anon_super, ++}; ++ ++static int __init ovl_init(void) ++{ ++ return register_filesystem(&ovl_fs_type); ++} ++ ++static void __exit ovl_exit(void) ++{ ++ unregister_filesystem(&ovl_fs_type); ++} ++ ++module_init(ovl_init); ++module_exit(ovl_exit); +diff --git a/fs/splice.c b/fs/splice.c +index f847684..c124964 100644 +--- a/fs/splice.c ++++ b/fs/splice.c +@@ -1299,6 +1299,7 @@ long do_splice_direct(struct file *in, loff_t *ppos, struct file *out, + + return ret; + } ++EXPORT_SYMBOL(do_splice_direct); + + static int splice_pipe_to_pipe(struct pipe_inode_info *ipipe, + struct pipe_inode_info *opipe, +diff --git a/include/linux/fs.h b/include/linux/fs.h +index 8de6755..0b531ab 100644 +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -489,6 +489,12 @@ struct iattr { + */ + #include + ++/* ++ * Maximum number of layers of fs stack. Needs to be limited to ++ * prevent kernel stack overflow ++ */ ++#define FILESYSTEM_MAX_STACK_DEPTH 2 ++ + /** + * enum positive_aop_returns - aop return codes with specific semantics + * +@@ -1507,6 +1513,11 @@ struct super_block { + + /* Being remounted read-only */ + int s_readonly_remount; ++ ++ /* ++ * Indicates how deep in a filesystem stack this SB is ++ */ ++ int s_stack_depth; + }; + + /* superblock cache pruning functions */ +@@ -1664,6 +1675,8 @@ struct inode_operations { + void (*truncate_range)(struct inode *, loff_t, loff_t); + int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start, + u64 len); ++ struct file *(*open) (struct dentry *, struct file *, ++ const struct cred *); + } ____cacheline_aligned; + + struct seq_file; +@@ -2021,6 +2034,7 @@ extern long do_sys_open(int dfd, const char __user *filename, int flags, + extern struct file *filp_open(const char *, int, umode_t); + extern struct file *file_open_root(struct dentry *, struct vfsmount *, + const char *, int); ++extern struct file *vfs_open(struct path *, struct file *, const struct cred *); + extern struct file * dentry_open(struct dentry *, struct vfsmount *, int, + const struct cred *); + extern int filp_close(struct file *, fl_owner_t id); +@@ -2212,6 +2226,7 @@ extern sector_t bmap(struct inode *, sector_t); + #endif + extern int notify_change(struct dentry *, struct iattr *); + extern int inode_permission(struct inode *, int); ++extern int inode_only_permission(struct inode *, int); + extern int generic_permission(struct inode *, int); + + static inline bool execute_ok(struct inode *inode) +diff --git a/include/linux/mount.h b/include/linux/mount.h +index d7029f4..344a262 100644 +--- a/include/linux/mount.h ++++ b/include/linux/mount.h +@@ -66,6 +66,9 @@ extern void mnt_pin(struct vfsmount *mnt); + extern void mnt_unpin(struct vfsmount *mnt); + extern int __mnt_is_readonly(struct vfsmount *mnt); + ++struct path; ++extern struct vfsmount *clone_private_mount(struct path *path); ++ + struct file_system_type; + extern struct vfsmount *vfs_kern_mount(struct file_system_type *type, + int flags, const char *name, diff --git a/br-ext-chip-goke/board/gk710x/kernel/patches/0011-fix-yylloc-for-modern-computers.patch b/br-ext-chip-goke/board/gk710x/kernel/patches/0011-fix-yylloc-for-modern-computers.patch new file mode 100644 index 00000000..d7088f90 --- /dev/null +++ b/br-ext-chip-goke/board/gk710x/kernel/patches/0011-fix-yylloc-for-modern-computers.patch @@ -0,0 +1,11 @@ +--- a/scripts/dtc/dtc-lexer.lex.c_shipped 2015-08-07 22:08:04.000000000 +0300 ++++ b/scripts/dtc/dtc-lexer.lex.c_shipped 2021-11-01 22:15:12.347053553 +0300 +@@ -637,7 +637,7 @@ + #include "srcpos.h" + #include "dtc-parser.tab.h" + +-YYLTYPE yylloc; ++extern YYLTYPE yylloc; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ + #define YY_USER_ACTION \ diff --git a/br-ext-chip-goke/configs/unknown_unknown_gk7102_openipc_defconfig b/br-ext-chip-goke/configs/unknown_unknown_gk7102_openipc_defconfig new file mode 100644 index 00000000..b5c1416e --- /dev/null +++ b/br-ext-chip-goke/configs/unknown_unknown_gk7102_openipc_defconfig @@ -0,0 +1,96 @@ +# Architecture +BR2_arm=y +BR2_arm1176jzf_s=y +BR2_ARM_EABI=y +BR2_KERNEL_HEADERS_VERSION=y +BR2_DEFAULT_KERNEL_VERSION="3.4.43" +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_4=y + +# Toolchain +BR2_PER_PACKAGE_DIRECTORIES=y +BR2_GCC_VERSION_7_X=y +# BR2_TOOLCHAIN_USES_UCLIBC is not set +# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set +# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" +BR2_TOOLCHAIN_USES_MUSL=y +BR2_TOOLCHAIN_BUILDROOT_MUSL=y +BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_TOOLCHAIN_BUILDROOT_LOCALE=y +BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y + +# Kernel +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.4.43" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/gk710x.generic.config" +BR2_LINUX_KERNEL_UIMAGE=y +BR2_LINUX_KERNEL_XZ=y +BR2_LINUX_KERNEL_EXT_GOKE_PATCHER=y +BR2_LINUX_KERNEL_EXT_GOKE_PATCHER_LIST="$(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/patches/ $(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/overlay" + +# Filesystem +# BR2_TARGET_TZ_INFO is not set +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_SQUASHFS=y +BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y +BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" + +# OpenIPC configuration +BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" +BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" +BR2_TARGET_GENERIC_HOSTNAME="openipc-gk7102" +BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" + +# OpenIPC packages +BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" +BR2_PACKAGE_DROPBEAR_OPENIPC=y +# BR2_PACKAGE_FDK_AAC_OPENIPC is not set +BR2_PACKAGE_FWPRINTENV_OPENIPC=y +BR2_PACKAGE_HASERL=y +BR2_PACKAGE_GOKE_OSDRV_GK710X=y +BR2_PACKAGE_IPCTOOL=y +BR2_PACKAGE_JSON_C=y +BR2_PACKAGE_LAME_OPENIPC=y +BR2_PACKAGE_LIBCURL_OPENIPC=y +BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y +# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set +BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y +BR2_PACKAGE_LIBEVENT_OPENIPC=y +BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y +BR2_PACKAGE_LIBOGG_OPENIPC=y +BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y +BR2_PACKAGE_LIBYAML=y +BR2_PACKAGE_MAJESTIC_FONTS=y +# BR2_PACKAGE_MAJESTIC_GK710X=y +BR2_PACKAGE_MBEDTLS_OPENIPC=y +# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set +# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set +BR2_PACKAGE_MICROBE_WEB=y +# BR2_PACKAGE_MINI_SNMPD is not set +BR2_PACKAGE_MOTORS=y +BR2_PACKAGE_OPUS_OPENIPC=y +BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y +# BR2_PACKAGE_SSHPASS is not set +BR2_PACKAGE_UACME_OPENIPC=y +BR2_PACKAGE_VTUND_OPENIPC=y +BR2_PACKAGE_YAML_CLI=y + +# WiFi +BR2_PACKAGE_WIRELESS_TOOLS=y +BR2_PACKAGE_WPA_SUPPLICANT=y +BR2_PACKAGE_WPA_SUPPLICANT_CLI=y +BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y +BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y +BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y +BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y +# BR2_PACKAGE_RTL8188EU is not set + +# WIREGUARD +BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y +BR2_PACKAGE_WIREGUARD_TOOLS=y diff --git a/br-ext-chip-goke/configs/unknown_unknown_gk7102s_openipc_defconfig b/br-ext-chip-goke/configs/unknown_unknown_gk7102s_openipc_defconfig new file mode 100644 index 00000000..ad34a072 --- /dev/null +++ b/br-ext-chip-goke/configs/unknown_unknown_gk7102s_openipc_defconfig @@ -0,0 +1,96 @@ +# Architecture +BR2_arm=y +BR2_arm1176jzf_s=y +BR2_ARM_EABI=y +BR2_KERNEL_HEADERS_VERSION=y +BR2_DEFAULT_KERNEL_VERSION="3.4.43" +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_4=y + +# Toolchain +BR2_PER_PACKAGE_DIRECTORIES=y +BR2_GCC_VERSION_7_X=y +# BR2_TOOLCHAIN_USES_UCLIBC is not set +# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set +# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" +BR2_TOOLCHAIN_USES_MUSL=y +BR2_TOOLCHAIN_BUILDROOT_MUSL=y +BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_TOOLCHAIN_BUILDROOT_LOCALE=y +BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y + +# Kernel +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.4.43" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/gk710xs.generic.config" +BR2_LINUX_KERNEL_UIMAGE=y +BR2_LINUX_KERNEL_XZ=y +BR2_LINUX_KERNEL_EXT_GOKE_PATCHER=y +BR2_LINUX_KERNEL_EXT_GOKE_PATCHER_LIST="$(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/patches/ $(BR2_EXTERNAL_GOKE_PATH)/board/gk710x/kernel/overlay" + +# Filesystem +# BR2_TARGET_TZ_INFO is not set +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_SQUASHFS=y +BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y +BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" + +# OpenIPC configuration +BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" +BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" +BR2_TARGET_GENERIC_HOSTNAME="openipc-gk7102s" +BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" + +# OpenIPC packages +BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" +BR2_PACKAGE_DROPBEAR_OPENIPC=y +# BR2_PACKAGE_FDK_AAC_OPENIPC is not set +BR2_PACKAGE_FWPRINTENV_OPENIPC=y +BR2_PACKAGE_HASERL=y +BR2_PACKAGE_GOKE_OSDRV_GK710X=y +BR2_PACKAGE_IPCTOOL=y +BR2_PACKAGE_JSON_C=y +BR2_PACKAGE_LAME_OPENIPC=y +BR2_PACKAGE_LIBCURL_OPENIPC=y +BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y +# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set +# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set +BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y +BR2_PACKAGE_LIBEVENT_OPENIPC=y +BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y +BR2_PACKAGE_LIBOGG_OPENIPC=y +BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y +BR2_PACKAGE_LIBYAML=y +BR2_PACKAGE_MAJESTIC_FONTS=y +# BR2_PACKAGE_MAJESTIC_GK710X=y +BR2_PACKAGE_MBEDTLS_OPENIPC=y +# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set +# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set +BR2_PACKAGE_MICROBE_WEB=y +# BR2_PACKAGE_MINI_SNMPD is not set +BR2_PACKAGE_MOTORS=y +BR2_PACKAGE_OPUS_OPENIPC=y +BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y +# BR2_PACKAGE_SSHPASS is not set +BR2_PACKAGE_UACME_OPENIPC=y +BR2_PACKAGE_VTUND_OPENIPC=y +BR2_PACKAGE_YAML_CLI=y + +# WiFi +BR2_PACKAGE_WIRELESS_TOOLS=y +BR2_PACKAGE_WPA_SUPPLICANT=y +BR2_PACKAGE_WPA_SUPPLICANT_CLI=y +BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y +BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y +BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y +BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y +# BR2_PACKAGE_RTL8188EU is not set + +# WIREGUARD +BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y +BR2_PACKAGE_WIREGUARD_TOOLS=y diff --git a/br-ext-chip-goke/external.mk b/br-ext-chip-goke/external.mk index 49aef1fe..336d955b 100644 --- a/br-ext-chip-goke/external.mk +++ b/br-ext-chip-goke/external.mk @@ -4,6 +4,7 @@ include $(BR2_EXTERNAL_GOKE_PATH)/package/aura-httpd/aura-httpd.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/dropbear-openipc/dropbear-openipc.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/fdk-aac-openipc/fdk-aac-openipc.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/fwprintenv-openipc/fwprintenv-openipc.mk +include $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/goke-osdrv-gk710x.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk7205v200/goke-osdrv-gk7205v200.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/ipctool/ipctool.mk include $(BR2_EXTERNAL_GOKE_PATH)/package/json-c-openipc/json-c-openipc.mk diff --git a/br-ext-chip-goke/package/goke-osdrv-gk710x b/br-ext-chip-goke/package/goke-osdrv-gk710x new file mode 120000 index 00000000..e360e37b --- /dev/null +++ b/br-ext-chip-goke/package/goke-osdrv-gk710x @@ -0,0 +1 @@ +../../general/package/goke-osdrv-gk710x \ No newline at end of file diff --git a/building.sh b/building.sh index 8fec600d..2b95f3d9 100755 --- a/building.sh +++ b/building.sh @@ -135,6 +135,26 @@ fh8858v210() { ################################################################################# +gk7101() { + soc="gk7101" + fresh && make PLATFORM=goke BOARD=unknown_unknown_${soc}_openipc all && rename +} + +gk7101s() { + soc="gk7101s" + fresh && make PLATFORM=goke BOARD=unknown_unknown_${soc}_openipc all && rename +} + +gk7102() { + soc="gk7102" + fresh && make PLATFORM=goke BOARD=unknown_unknown_${soc}_openipc all && rename +} + +gk7102s() { + soc="gk7102s" + fresh && make PLATFORM=goke BOARD=unknown_unknown_${soc}_openipc all && rename +} + gk7205v200() { soc="gk7205v200" fresh && make PLATFORM=goke BOARD=unknown_unknown_${soc}_openipc all && rename @@ -482,6 +502,10 @@ xm550() { # ####### # +# gk7101 # testing.. +# gk7101s # testing.. +# gk7102 # testing.. +gk7102s # testing.. # gk7202v300 # testing.. # gk7205v200 # OpenIPC # gk7205v200_fpv # FPV @@ -560,7 +584,7 @@ xm550() { # t10 # testing.. # t20 # testing.. # t30 # testing.. -t31 # testing.. +# t31 # testing.. # ####### # diff --git a/general/package/goke-osdrv-gk710x/Config.in b/general/package/goke-osdrv-gk710x/Config.in new file mode 100644 index 00000000..20811a16 --- /dev/null +++ b/general/package/goke-osdrv-gk710x/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_GOKE_OSDRV_GK710X + bool "goke-osdrv-gk710x" + help + goke-osdrv-gk710x - Goke kernel modules and libs + + https://openipc.org diff --git a/general/package/goke-osdrv-gk710x/files/kmod/audio.ko b/general/package/goke-osdrv-gk710x/files/kmod/audio.ko new file mode 100755 index 00000000..d7fd53da Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/audio.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/kmod/hal.ko b/general/package/goke-osdrv-gk710x/files/kmod/hal.ko new file mode 100755 index 00000000..d8233486 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/hal.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/kmod/hw_crypto.ko b/general/package/goke-osdrv-gk710x/files/kmod/hw_crypto.ko new file mode 100755 index 00000000..eb4c04f4 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/hw_crypto.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/kmod/i2s.ko b/general/package/goke-osdrv-gk710x/files/kmod/i2s.ko new file mode 100755 index 00000000..c2f1f8b3 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/i2s.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/kmod/media.ko b/general/package/goke-osdrv-gk710x/files/kmod/media.ko new file mode 100755 index 00000000..3cec20d3 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/media.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/kmod/sensor.ko b/general/package/goke-osdrv-gk710x/files/kmod/sensor.ko new file mode 100755 index 00000000..77076209 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/kmod/sensor.ko differ diff --git a/general/package/goke-osdrv-gk710x/files/lib/libadi.so b/general/package/goke-osdrv-gk710x/files/lib/libadi.so new file mode 100755 index 00000000..1455b648 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/lib/libadi.so differ diff --git a/general/package/goke-osdrv-gk710x/files/lib/libimage.so b/general/package/goke-osdrv-gk710x/files/lib/libimage.so new file mode 100755 index 00000000..2d359115 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/lib/libimage.so differ diff --git a/general/package/goke-osdrv-gk710x/files/script/S95goke b/general/package/goke-osdrv-gk710x/files/script/S95goke new file mode 100755 index 00000000..ca1acc81 --- /dev/null +++ b/general/package/goke-osdrv-gk710x/files/script/S95goke @@ -0,0 +1,72 @@ +#!/bin/sh + +DAEMON="majestic" +PIDFILE="/var/run/$DAEMON.pid" + +DAEMON_ARGS="-s" + +# shellcheck source=/dev/null +[ -r "/etc/default/$DAEMON" ] && . "/etc/default/$DAEMON" + +load_majestic() { + printf 'Starting %s: ' "$DAEMON" + [ -f /usr/bin/$DAEMON ] || echo -en "DISABLED, " + # shellcheck disable=SC2086 # we need the word splitting + start-stop-daemon -b -m -S -q -p "$PIDFILE" -x "/usr/bin/$DAEMON" \ + -- $DAEMON_ARGS + status=$? + if [ "$status" -eq 0 ]; then + echo "OK" + else + echo "FAIL" + fi + return "$status" +} + +# The daemon does not create a pidfile, and use "-m" to instruct start-stop-daemon to create one. +start() { + logger -s -p daemon.info -t goke "Checking MAC address" + if [ "$(fw_printenv -n ethaddr)" = "00:00:23:34:45:66" ]; then + logger -s -p daemon.info -t goke "The eth0 interface has a lousy MAC, you have to change it.." + else + logger -s -p daemon.info -t goke "The eth0 interface has a correct MAC - $(fw_printenv -n ethaddr)" + fi + # + logger -s -p daemon.info -t goke "Loading of kernel modules and initialization of the video system has started" + export TZ=$(cat /etc/TZ) + # load_goke + # + # load_majestic +} + +stop() { + printf 'Stopping %s: ' "$DAEMON" + [ -f /usr/bin/$DAEMON ] || echo -en "DISABLED, " + start-stop-daemon -K -q -p "$PIDFILE" + status=$? + if [ "$status" -eq 0 ]; then + rm -f "$PIDFILE" + echo "OK" + else + echo "FAIL" + fi + return "$status" +} + +restart() { + stop + sleep 1 + reload +} + +reload() { + load_majestic +} + +case "$1" in + start|stop|restart|reload) + "$1";; + *) + echo "Usage: $0 {start|stop|restart|reload}" + exit 1 +esac diff --git a/general/package/goke-osdrv-gk710x/files/script/ircut_demo b/general/package/goke-osdrv-gk710x/files/script/ircut_demo new file mode 100755 index 00000000..c51470a1 --- /dev/null +++ b/general/package/goke-osdrv-gk710x/files/script/ircut_demo @@ -0,0 +1,87 @@ +#!/bin/sh + +# on GK7205V200: +# GPIO1_0 -> GPIO8 (1*8+0 = 8) +# GPIO1_1 -> GPIO9 (1*8+1 = 9) + +# on GK7205V300: +# GPIO1_3 -> GPIO11 +# GPIO1_2 -> GPIO10 + +#(normal mode) +ir_cut_enable() { + # pin_mux + echo "$gpio_0" >/sys/class/gpio/unexport + echo "$gpio_1" >/sys/class/gpio/unexport + echo "$gpio_0" >/sys/class/gpio/export + echo "$gpio_1" >/sys/class/gpio/export + + # dir + echo "out" >/sys/class/gpio/gpio$gpio_0/direction + echo "out" >/sys/class/gpio/gpio$gpio_1/direction + + # data, gpio_1: 0, gpio_0: 1 (normal mode) + echo "1" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value + + #sleep 1s + sleep 1 + + # back to original + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value +} + +# (ir mode) +ir_cut_disable() { + # pin_mux + echo "$gpio_0" >/sys/class/gpio/unexport + echo "$gpio_1" >/sys/class/gpio/unexport + echo "$gpio_0" >/sys/class/gpio/export + echo "$gpio_1" >/sys/class/gpio/export + + # dir + echo "out" >/sys/class/gpio/gpio$gpio_0/direction + echo "out" >/sys/class/gpio/gpio$gpio_1/direction + + # data, gpio_1: 1, gpio_0: 0 (ir mode) + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "1" >/sys/class/gpio/gpio$gpio_1/value + + #sleep 1s + sleep 1 + + # back to original + echo "0" >/sys/class/gpio/gpio$gpio_0/value + echo "0" >/sys/class/gpio/gpio$gpio_1/value +} + +gpio_0=0 +gpio_1=0 + +if [ $# -lt 2 ]; then + echo "usage : ./ircut_demo " + echo "for example:" + echo "ir mode : ./ircut_demo gk7205v200 1" +else + if [ $1 = "gk7205v200" ]; then + gpio_0=8 + gpio_1=9 + elif [ $1 = "gk7205v300" ]; then + gpio_0=11 + gpio_1=10 + else + echo "wrong chipid: $1, please select: gk7205v200 or gk7205v300." + exit + fi + + if [ $2 -eq 0 ]; then + echo "normal mode, ir_cut on" + ir_cut_enable >/dev/null + elif [ $2 -eq 1 ]; then + echo "ir mode, ir_cut off" + ir_cut_disable >/dev/null + else + echo "invalid mode, please slect 0 or 1." + fi +fi diff --git a/general/package/goke-osdrv-gk710x/files/script/load_goke b/general/package/goke-osdrv-gk710x/files/script/load_goke new file mode 100755 index 00000000..b4ae2a74 --- /dev/null +++ b/general/package/goke-osdrv-gk710x/files/script/load_goke @@ -0,0 +1,54 @@ +#!/bin/sh + + + +kernel_ver=$(uname -r) +cd /lib/modules/$kernel_ver/goke + +USE_OLD_SENSOR_DRIVER=NO #YES or NO, default no use. +USE_LOAD_HAL_DRIVER=YES #YES or NO, default no use. + +if [ $USE_LOAD_HAL_DRIVER = "YES" ];then + insmod hal.ko +fi +insmod hw_crypto.ko +insmod media.ko +insmod audio.ko + +if [ $USE_OLD_SENSOR_DRIVER = "YES" ]; then + if [ -e ${1}.ko ];then + insmod ${1}.ko + else + echo "${1}.ko is no exist." + exit 0 + fi +else + insmod sensor.ko + # Use sensor.ko + rm /tmp/sensor_hw.bin -f + rm /tmp/sensor_ex.ko -f + if [ $# -ne 1 ] ;then + sensordetect + else + if [ -e /etc/sensors/$1"_hw.bin" ];then + if [ -e /tmp/sensor_hw.bin ]; then + rm /tmp/sensor_hw.bin -f + fi + ln -s /etc/sensors/$1"_hw.bin" /tmp/sensor_hw.bin + else + echo "\"/etc/sensors/${1}_hw.bin\" is no exist." + exit 0 + fi + if [ -e $1"_ex.ko" ];then + if [ -e /tmp/sensor_ex.ko ]; then + rm /tmp/sensor_ex.ko -f + fi + ln -s $1"_ex.ko" /tmp/sensor_ex.ko + else + echo "\"${1}_ex.ko\" is no exist." + fi + fi + if [ -e /tmp/sensor_ex.ko ];then + insmod /tmp/sensor_ex.ko + fi +fi diff --git a/general/package/goke-osdrv-gk710x/files/sensor/config/ar0130.bin b/general/package/goke-osdrv-gk710x/files/sensor/config/ar0130.bin new file mode 100755 index 00000000..dffaf141 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/ar0130.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/config/ar0237.bin b/general/package/goke-osdrv-gk710x/files/sensor/config/ar0237.bin new file mode 100755 index 00000000..7b5180c7 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/ar0237.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/config/bg0701.bin b/general/package/goke-osdrv-gk710x/files/sensor/config/bg0701.bin new file mode 100755 index 00000000..8f0cae33 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/bg0701.bin differ diff --git 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files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/sc2035.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/config/sc2045.bin b/general/package/goke-osdrv-gk710x/files/sensor/config/sc2045.bin new file mode 100755 index 00000000..cf755128 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/sc2045.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/config/sc2135.bin b/general/package/goke-osdrv-gk710x/files/sensor/config/sc2135.bin new file mode 100755 index 00000000..b6054f12 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/config/sc2135.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710x.bin b/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710x.bin new file mode 100755 index 00000000..1f3d6476 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710x.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710xs.bin b/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710xs.bin new file mode 100755 index 00000000..002e71c6 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/fw/gk_fw_710xs.bin differ diff --git a/general/package/goke-osdrv-gk710x/files/sensor/sc1135_ex.ko b/general/package/goke-osdrv-gk710x/files/sensor/sc1135_ex.ko new file mode 100755 index 00000000..343a43a3 Binary files /dev/null and b/general/package/goke-osdrv-gk710x/files/sensor/sc1135_ex.ko differ diff --git a/general/package/goke-osdrv-gk710x/goke-osdrv-gk710x.mk b/general/package/goke-osdrv-gk710x/goke-osdrv-gk710x.mk new file mode 100644 index 00000000..1af70416 --- /dev/null +++ b/general/package/goke-osdrv-gk710x/goke-osdrv-gk710x.mk @@ -0,0 +1,36 @@ +################################################################################ +# +# goke-osdrv-gk710x +# +################################################################################ + +GOKE_OSDRV_GK710X_VERSION = +GOKE_OSDRV_GK710X_SITE = +GOKE_OSDRV_GK710X_LICENSE = MIT +GOKE_OSDRV_GK710X_LICENSE_FILES = LICENSE + +define GOKE_OSDRV_GK710X_INSTALL_TARGET_CMDS + $(INSTALL) -m 755 -d $(TARGET_DIR)/etc/init.d + $(INSTALL) -m 755 -t $(TARGET_DIR)/etc/init.d $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/script/S95goke + + $(INSTALL) -m 755 -d $(TARGET_DIR)/etc/sensors + $(INSTALL) -m 644 -t $(TARGET_DIR)/etc/sensors $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/sensor/config/*.bin + + $(INSTALL) -m 755 -d $(TARGET_DIR)/lib/firmware + $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/firmware $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/sensor/fw/*.bin + + $(INSTALL) -m 755 -d $(TARGET_DIR)/lib/modules/3.4.43/goke + $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.4.43/goke $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/kmod/*.ko + $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.4.43/goke $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/sensor/*.ko + + $(INSTALL) -m 755 -d $(TARGET_DIR)/usr/bin + $(INSTALL) -m 755 -t $(TARGET_DIR)/usr/bin $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/script/load_* + $(INSTALL) -m 755 -t $(TARGET_DIR)/usr/bin $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/script/ircut_demo + + # $(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib/sensors + + $(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib + $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/ $(BR2_EXTERNAL_GOKE_PATH)/package/goke-osdrv-gk710x/files/lib/*.so +endef + +$(eval $(generic-package))