From 58fb9d3ef752d9c125dacf3be1a83e5623047811 Mon Sep 17 00:00:00 2001 From: Andrew 'Necromant' Andrianov Date: Sat, 19 Jun 2021 14:10:42 +0000 Subject: [PATCH] hi3516ev300: Add fm25q128a spi chip id Signed-off-by: Andrew 'Necromant' Andrianov --- .../kernel/patches/spi_id_fm25q128a.patch | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/spi_id_fm25q128a.patch diff --git a/br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/spi_id_fm25q128a.patch b/br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/spi_id_fm25q128a.patch new file mode 100644 index 00000000..ba240cb5 --- /dev/null +++ b/br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/spi_id_fm25q128a.patch @@ -0,0 +1,13 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c 2021-06-19 13:56:54.523168941 +0000 ++++ b/drivers/mtd/spi-nor/spi-nor.c 2021-06-19 14:02:43.947271771 +0000 +@@ -1217,6 +1217,10 @@ + SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) }, + { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(80) }, ++ ++ { "fm25q128a", INFO(0xa14018, 0, 64 * 1024, 256, ++ SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(80) }, ++ + { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(gd), CLK_MHZ_2X(80) }, + /* GigaDevice 1.8V */