diff --git a/general/package/hisilicon-osdrv-hi3516av100/files/script/load_hisilicon b/general/package/hisilicon-osdrv-hi3516av100/files/script/load_hisilicon
index 01e7a3da..e4934ca4 100755
--- a/general/package/hisilicon-osdrv-hi3516av100/files/script/load_hisilicon
+++ b/general/package/hisilicon-osdrv-hi3516av100/files/script/load_hisilicon
@@ -216,12 +216,6 @@ insert_sns() {
 
                 devmem 0x2003002c 32 0x90007 # sensor unreset, clk 37.125MHz, VI 250MHz
                 ;;
-        ar0330)
-                devmem 0x200f0050 32 0x2 # i2c0_scl
-                devmem 0x200f0054 32 0x2 # i2c0_sda
-
-                devmem 0x2003002c 32 0xB0007 # sensor unreset, clk 27MHz, VI 250MHz
-                ;;
         ov5658)
                 devmem 0x200f0050 32 0x2     # i2c0_scl
                 devmem 0x200f0054 32 0x2     # i2c0_sda
@@ -240,6 +234,12 @@ insert_sns() {
 
                 devmem 0x2003002c 32 0xB0007 # sensor unreset, clk 27MHz, VI 250MHz
                 ;;
+        ar0330 | ar0330_i2c_dc)
+                devmem 0x200f0050 32 0x2 # i2c0_scl
+                devmem 0x200f0054 32 0x2 # i2c0_sda
+
+                devmem 0x2003002c 32 0xE0007 # sensor unreset, clk 24MHz, VI 250MHz
+                ;;
         os05a)
                 devmem 0x200f0050 32 0x2     # i2c0_scl
                 devmem 0x200f0054 32 0x2     # i2c0_sda
diff --git a/general/package/hisilicon-osdrv-hi3516av100/files/sensor/config/ar0330_i2c_dc_3M.ini b/general/package/hisilicon-osdrv-hi3516av100/files/sensor/config/ar0330_i2c_dc_3M.ini
new file mode 100644
index 00000000..cacc354d
--- /dev/null
+++ b/general/package/hisilicon-osdrv-hi3516av100/files/sensor/config/ar0330_i2c_dc_3M.ini
@@ -0,0 +1,76 @@
+[sensor]
+Sensor_type=ar0330
+Mode=WDR_MODE_NONE
+DllFile=libsns_ar0330_dc.so
+
+[mode]
+input_mode=INPUT_MODE_CMOS_33V
+dev_attr=0
+
+[isp_image]
+Isp_FrameRate=25
+Isp_Bayer=BAYER_GRBG
+
+[vi_dev]
+Input_mod=VI_MODE_DIGITAL_CAMERA
+Work_mod =0     ;VI_WORK_MODE_1Multiplex = 0
+                ;VI_WORK_MODE_2Multiplex,
+                ;VI_WORK_MODE_4Multiplex
+Combine_mode =0 ;Y/C composite or separation mode
+                ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
+                ;VI_COMBINE_SEPARATE,     /*Separate mode */
+Comp_mode    =0 ;Component mode (single-component or dual-component)
+                ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
+                ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
+Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
+                ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
+                ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
+Mask_num     =2 ;Component mask
+Mask_0       =0xFFC0000
+Mask_1       =0x0
+Scan_mode    = 1;VI_SCAN_INTERLACED = 0
+                ;VI_SCAN_PROGRESSIVE,
+Data_seq     =2 ;data sequence (ONLY for YUV format)
+                ;----2th component U/V sequence in bt1120
+                ;    VI_INPUT_DATA_VUVU = 0,
+                ;    VI_INPUT_DATA_UVUV,
+                ;----input sequence for yuv
+                ;    VI_INPUT_DATA_UYVY = 0,
+                ;    VI_INPUT_DATA_VYUY,
+                ;    VI_INPUT_DATA_YUYV,
+                ;    VI_INPUT_DATA_YVYU
+
+Vsync   =1      ; vertical synchronization signal
+                ;VI_VSYNC_FIELD = 0,
+                ;VI_VSYNC_PULSE,
+VsyncNeg=0      ;Polarity of the vertical synchronization signal
+                ;VI_VSYNC_NEG_HIGH = 0,
+                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
+Hsync  =0       ;Attribute of the horizontal synchronization signal
+                ;VI_HSYNC_VALID_SINGNAL = 0,
+                ;VI_HSYNC_PULSE,
+HsyncNeg =0     ;Polarity of the horizontal synchronization signal
+                ;VI_HSYNC_NEG_HIGH = 0,
+                ;VI_HSYNC_NEG_LOW
+VsyncValid =1   ;Attribute of the valid vertical synchronization signal
+                ;VI_VSYNC_NORM_PULSE = 0,
+                ;VI_VSYNC_VALID_SINGAL,
+VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
+                ;VI_VSYNC_VALID_NEG_HIGH = 0,
+                ;VI_VSYNC_VALID_NEG_LOW
+Timingblank_HsyncHfb =0     ;Horizontal front blanking width
+Timingblank_HsyncAct =2048  ;Horizontal effetive width
+Timingblank_HsyncHbb =0     ;Horizontal back blanking width
+Timingblank_VsyncVfb =0     ;Vertical front blanking height
+Timingblank_VsyncVact =1536  ;Vertical effetive width
+Timingblank_VsyncVbb=0      ;Vertical back blanking height
+Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
+Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
+Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
+DataPath=1
+InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
+DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
+DevRect_x=0
+DevRect_y=0
+DevRect_w=2048
+DevRect_h=1536
diff --git a/general/package/hisilicon-osdrv-hi3516av100/files/sensor/libsns_ar0330_dc.so b/general/package/hisilicon-osdrv-hi3516av100/files/sensor/libsns_ar0330_dc.so
new file mode 100644
index 00000000..589c47d6
Binary files /dev/null and b/general/package/hisilicon-osdrv-hi3516av100/files/sensor/libsns_ar0330_dc.so differ